Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 32
1 12:41:10.521862 lava-dispatcher, installed at version: 2024.01
2 12:41:10.522084 start: 0 validate
3 12:41:10.522220 Start time: 2024-02-05 12:41:10.522211+00:00 (UTC)
4 12:41:10.522346 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:41:10.522471 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:41:10.788841 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:41:10.789019 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:41:11.054727 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:41:11.054902 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:41:11.318557 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:41:11.318750 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:41:11.586283 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:41:11.586487 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:41:11.854047 validate duration: 1.33
16 12:41:11.854419 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:41:11.854530 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:41:11.854629 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:41:11.854797 Not decompressing ramdisk as can be used compressed.
20 12:41:11.854919 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:41:11.855018 saving as /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/ramdisk/initrd.cpio.gz
22 12:41:11.855124 total size: 4665395 (4 MB)
23 12:41:11.856324 progress 0 % (0 MB)
24 12:41:11.857799 progress 5 % (0 MB)
25 12:41:11.859181 progress 10 % (0 MB)
26 12:41:11.860514 progress 15 % (0 MB)
27 12:41:11.861767 progress 20 % (0 MB)
28 12:41:11.863009 progress 25 % (1 MB)
29 12:41:11.864317 progress 30 % (1 MB)
30 12:41:11.865549 progress 35 % (1 MB)
31 12:41:11.866791 progress 40 % (1 MB)
32 12:41:11.868235 progress 45 % (2 MB)
33 12:41:11.869471 progress 50 % (2 MB)
34 12:41:11.870721 progress 55 % (2 MB)
35 12:41:11.872006 progress 60 % (2 MB)
36 12:41:11.873235 progress 65 % (2 MB)
37 12:41:11.874479 progress 70 % (3 MB)
38 12:41:11.875762 progress 75 % (3 MB)
39 12:41:11.876994 progress 80 % (3 MB)
40 12:41:11.878427 progress 85 % (3 MB)
41 12:41:11.879794 progress 90 % (4 MB)
42 12:41:11.881024 progress 95 % (4 MB)
43 12:41:11.882284 progress 100 % (4 MB)
44 12:41:11.882456 4 MB downloaded in 0.03 s (162.78 MB/s)
45 12:41:11.882625 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:41:11.882895 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:41:11.883022 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:41:11.883148 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:41:11.883329 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:41:11.883468 saving as /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/kernel/Image
52 12:41:11.883568 total size: 51534336 (49 MB)
53 12:41:11.883669 No compression specified
54 12:41:11.885287 progress 0 % (0 MB)
55 12:41:11.898777 progress 5 % (2 MB)
56 12:41:11.912325 progress 10 % (4 MB)
57 12:41:11.925639 progress 15 % (7 MB)
58 12:41:11.939349 progress 20 % (9 MB)
59 12:41:11.953074 progress 25 % (12 MB)
60 12:41:11.966877 progress 30 % (14 MB)
61 12:41:11.980605 progress 35 % (17 MB)
62 12:41:11.994420 progress 40 % (19 MB)
63 12:41:12.007820 progress 45 % (22 MB)
64 12:41:12.021298 progress 50 % (24 MB)
65 12:41:12.034605 progress 55 % (27 MB)
66 12:41:12.048576 progress 60 % (29 MB)
67 12:41:12.062636 progress 65 % (31 MB)
68 12:41:12.076843 progress 70 % (34 MB)
69 12:41:12.091251 progress 75 % (36 MB)
70 12:41:12.104897 progress 80 % (39 MB)
71 12:41:12.118236 progress 85 % (41 MB)
72 12:41:12.131780 progress 90 % (44 MB)
73 12:41:12.145203 progress 95 % (46 MB)
74 12:41:12.158440 progress 100 % (49 MB)
75 12:41:12.158701 49 MB downloaded in 0.28 s (178.63 MB/s)
76 12:41:12.158872 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:41:12.159247 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:41:12.159392 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:41:12.159496 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:41:12.159647 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:41:12.159732 saving as /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/dtb/mt8192-asurada-spherion-r0.dtb
83 12:41:12.159826 total size: 47278 (0 MB)
84 12:41:12.159930 No compression specified
85 12:41:12.161622 progress 69 % (0 MB)
86 12:41:12.161937 progress 100 % (0 MB)
87 12:41:12.162142 0 MB downloaded in 0.00 s (19.49 MB/s)
88 12:41:12.162318 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:41:12.162600 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:41:12.162703 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:41:12.162803 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:41:12.162963 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:41:12.163065 saving as /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/nfsrootfs/full.rootfs.tar
95 12:41:12.163167 total size: 200813988 (191 MB)
96 12:41:12.163275 Using unxz to decompress xz
97 12:41:12.167709 progress 0 % (0 MB)
98 12:41:12.703561 progress 5 % (9 MB)
99 12:41:13.228287 progress 10 % (19 MB)
100 12:41:13.819809 progress 15 % (28 MB)
101 12:41:14.203597 progress 20 % (38 MB)
102 12:41:14.537470 progress 25 % (47 MB)
103 12:41:15.157917 progress 30 % (57 MB)
104 12:41:15.721711 progress 35 % (67 MB)
105 12:41:16.314683 progress 40 % (76 MB)
106 12:41:16.872677 progress 45 % (86 MB)
107 12:41:17.456260 progress 50 % (95 MB)
108 12:41:18.080327 progress 55 % (105 MB)
109 12:41:18.740834 progress 60 % (114 MB)
110 12:41:18.859344 progress 65 % (124 MB)
111 12:41:18.998707 progress 70 % (134 MB)
112 12:41:19.094627 progress 75 % (143 MB)
113 12:41:19.165922 progress 80 % (153 MB)
114 12:41:19.234085 progress 85 % (162 MB)
115 12:41:19.335902 progress 90 % (172 MB)
116 12:41:19.615550 progress 95 % (181 MB)
117 12:41:20.186185 progress 100 % (191 MB)
118 12:41:20.191357 191 MB downloaded in 8.03 s (23.85 MB/s)
119 12:41:20.191615 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:41:20.191902 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:41:20.191999 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:41:20.192094 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:41:20.192252 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:41:20.192328 saving as /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/modules/modules.tar
126 12:41:20.192390 total size: 8639964 (8 MB)
127 12:41:20.192454 Using unxz to decompress xz
128 12:41:20.196723 progress 0 % (0 MB)
129 12:41:20.217770 progress 5 % (0 MB)
130 12:41:20.241064 progress 10 % (0 MB)
131 12:41:20.264401 progress 15 % (1 MB)
132 12:41:20.287490 progress 20 % (1 MB)
133 12:41:20.311102 progress 25 % (2 MB)
134 12:41:20.338749 progress 30 % (2 MB)
135 12:41:20.362905 progress 35 % (2 MB)
136 12:41:20.386369 progress 40 % (3 MB)
137 12:41:20.411116 progress 45 % (3 MB)
138 12:41:20.437009 progress 50 % (4 MB)
139 12:41:20.463831 progress 55 % (4 MB)
140 12:41:20.489189 progress 60 % (4 MB)
141 12:41:20.516191 progress 65 % (5 MB)
142 12:41:20.541933 progress 70 % (5 MB)
143 12:41:20.565486 progress 75 % (6 MB)
144 12:41:20.592627 progress 80 % (6 MB)
145 12:41:20.620257 progress 85 % (7 MB)
146 12:41:20.645705 progress 90 % (7 MB)
147 12:41:20.676899 progress 95 % (7 MB)
148 12:41:20.705679 progress 100 % (8 MB)
149 12:41:20.711578 8 MB downloaded in 0.52 s (15.87 MB/s)
150 12:41:20.711874 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:41:20.712295 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:41:20.712430 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:41:20.712562 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:41:24.864914 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj
156 12:41:24.865117 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:41:24.865217 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:41:24.865390 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i
159 12:41:24.865522 makedir: /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin
160 12:41:24.865630 makedir: /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/tests
161 12:41:24.865729 makedir: /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/results
162 12:41:24.865832 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-add-keys
163 12:41:24.865983 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-add-sources
164 12:41:24.866120 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-background-process-start
165 12:41:24.866248 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-background-process-stop
166 12:41:24.866409 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-common-functions
167 12:41:24.866553 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-echo-ipv4
168 12:41:24.866690 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-install-packages
169 12:41:24.866818 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-installed-packages
170 12:41:24.866950 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-os-build
171 12:41:24.867074 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-probe-channel
172 12:41:24.867207 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-probe-ip
173 12:41:24.867353 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-target-ip
174 12:41:24.867578 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-target-mac
175 12:41:24.867710 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-target-storage
176 12:41:24.867843 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-case
177 12:41:24.867970 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-event
178 12:41:24.868105 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-feedback
179 12:41:24.868229 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-raise
180 12:41:24.868359 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-reference
181 12:41:24.868503 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-runner
182 12:41:24.868636 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-set
183 12:41:24.868762 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-test-shell
184 12:41:24.868940 Updating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-add-keys (debian)
185 12:41:24.871607 Updating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-add-sources (debian)
186 12:41:24.871825 Updating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-install-packages (debian)
187 12:41:24.876729 Updating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-installed-packages (debian)
188 12:41:24.876880 Updating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/bin/lava-os-build (debian)
189 12:41:24.881617 Creating /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/environment
190 12:41:24.881755 LAVA metadata
191 12:41:24.881833 - LAVA_JOB_ID=12703544
192 12:41:24.881899 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:41:24.882018 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:41:24.882086 skipped lava-vland-overlay
195 12:41:24.882162 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:41:24.882248 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:41:24.882311 skipped lava-multinode-overlay
198 12:41:24.882383 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:41:24.882466 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:41:24.882542 Loading test definitions
201 12:41:24.882630 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:41:24.882701 Using /lava-12703544 at stage 0
203 12:41:24.883005 uuid=12703544_1.6.2.3.1 testdef=None
204 12:41:24.883094 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:41:24.883180 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:41:24.883692 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:41:24.883923 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:41:24.892582 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:41:24.892849 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:41:24.895171 runner path: /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/0/tests/0_timesync-off test_uuid 12703544_1.6.2.3.1
213 12:41:24.895342 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:41:24.895668 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:41:24.895745 Using /lava-12703544 at stage 0
217 12:41:24.895857 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:41:24.895949 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/0/tests/1_kselftest-tpm2'
219 12:41:29.365994 Running '/usr/bin/git checkout kernelci.org
220 12:41:29.515268 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 12:41:29.516055 uuid=12703544_1.6.2.3.5 testdef=None
222 12:41:29.516217 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 12:41:29.516504 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 12:41:29.517408 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:41:29.517646 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 12:41:29.518675 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:41:29.518983 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 12:41:29.520351 runner path: /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/0/tests/1_kselftest-tpm2 test_uuid 12703544_1.6.2.3.5
232 12:41:29.520447 BOARD='mt8192-asurada-spherion-r0'
233 12:41:29.520516 BRANCH='cip-gitlab'
234 12:41:29.520585 SKIPFILE='/dev/null'
235 12:41:29.520647 SKIP_INSTALL='True'
236 12:41:29.520708 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:41:29.520768 TST_CASENAME=''
238 12:41:29.520823 TST_CMDFILES='tpm2'
239 12:41:29.520967 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:41:29.521175 Creating lava-test-runner.conf files
242 12:41:29.521239 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703544/lava-overlay-20ar0j_i/lava-12703544/0 for stage 0
243 12:41:29.521336 - 0_timesync-off
244 12:41:29.521406 - 1_kselftest-tpm2
245 12:41:29.521501 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 12:41:29.521590 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 12:41:37.187728 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:41:37.187900 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 12:41:37.187997 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:41:37.188099 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 12:41:37.188189 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 12:41:37.309439 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:41:37.309870 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 12:41:37.309988 extracting modules file /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj
255 12:41:37.545346 extracting modules file /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703544/extract-overlay-ramdisk-tscb6hvd/ramdisk
256 12:41:37.778212 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:41:37.778385 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 12:41:37.778482 [common] Applying overlay to NFS
259 12:41:37.778556 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703544/compress-overlay-lj_zhbra/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj
260 12:41:38.730297 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:41:38.730464 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 12:41:38.730565 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:41:38.730656 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 12:41:38.730738 Building ramdisk /var/lib/lava/dispatcher/tmp/12703544/extract-overlay-ramdisk-tscb6hvd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703544/extract-overlay-ramdisk-tscb6hvd/ramdisk
265 12:41:39.084136 >> 119430 blocks
266 12:41:41.008595 rename /var/lib/lava/dispatcher/tmp/12703544/extract-overlay-ramdisk-tscb6hvd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/ramdisk/ramdisk.cpio.gz
267 12:41:41.009091 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:41:41.009218 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 12:41:41.009322 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 12:41:41.009434 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/kernel/Image'
271 12:41:53.414057 Returned 0 in 12 seconds
272 12:41:53.515148 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/kernel/image.itb
273 12:41:53.873614 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:41:53.873996 output: Created: Mon Feb 5 12:41:53 2024
275 12:41:53.874070 output: Image 0 (kernel-1)
276 12:41:53.874138 output: Description:
277 12:41:53.874205 output: Created: Mon Feb 5 12:41:53 2024
278 12:41:53.874268 output: Type: Kernel Image
279 12:41:53.874333 output: Compression: lzma compressed
280 12:41:53.874392 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
281 12:41:53.874451 output: Architecture: AArch64
282 12:41:53.874507 output: OS: Linux
283 12:41:53.874561 output: Load Address: 0x00000000
284 12:41:53.874614 output: Entry Point: 0x00000000
285 12:41:53.874668 output: Hash algo: crc32
286 12:41:53.874720 output: Hash value: 8a14336a
287 12:41:53.874772 output: Image 1 (fdt-1)
288 12:41:53.874825 output: Description: mt8192-asurada-spherion-r0
289 12:41:53.874877 output: Created: Mon Feb 5 12:41:53 2024
290 12:41:53.874930 output: Type: Flat Device Tree
291 12:41:53.874982 output: Compression: uncompressed
292 12:41:53.875033 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:41:53.875085 output: Architecture: AArch64
294 12:41:53.875136 output: Hash algo: crc32
295 12:41:53.875188 output: Hash value: cc4352de
296 12:41:53.875240 output: Image 2 (ramdisk-1)
297 12:41:53.875291 output: Description: unavailable
298 12:41:53.875343 output: Created: Mon Feb 5 12:41:53 2024
299 12:41:53.875433 output: Type: RAMDisk Image
300 12:41:53.875486 output: Compression: Unknown Compression
301 12:41:53.875538 output: Data Size: 17798337 Bytes = 17381.19 KiB = 16.97 MiB
302 12:41:53.875590 output: Architecture: AArch64
303 12:41:53.875642 output: OS: Linux
304 12:41:53.875693 output: Load Address: unavailable
305 12:41:53.875745 output: Entry Point: unavailable
306 12:41:53.875795 output: Hash algo: crc32
307 12:41:53.875846 output: Hash value: cf751b22
308 12:41:53.875898 output: Default Configuration: 'conf-1'
309 12:41:53.875949 output: Configuration 0 (conf-1)
310 12:41:53.876000 output: Description: mt8192-asurada-spherion-r0
311 12:41:53.876051 output: Kernel: kernel-1
312 12:41:53.876102 output: Init Ramdisk: ramdisk-1
313 12:41:53.876153 output: FDT: fdt-1
314 12:41:53.876204 output: Loadables: kernel-1
315 12:41:53.876255 output:
316 12:41:53.876449 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:41:53.876544 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:41:53.876649 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 12:41:53.876749 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 12:41:53.876830 No LXC device requested
321 12:41:53.876910 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:41:53.876994 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 12:41:53.877073 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:41:53.877140 Checking files for TFTP limit of 4294967296 bytes.
325 12:41:53.877626 end: 1 tftp-deploy (duration 00:00:42) [common]
326 12:41:53.877730 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:41:53.877822 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:41:53.877949 substitutions:
329 12:41:53.878017 - {DTB}: 12703544/tftp-deploy-ezbae8ku/dtb/mt8192-asurada-spherion-r0.dtb
330 12:41:53.878082 - {INITRD}: 12703544/tftp-deploy-ezbae8ku/ramdisk/ramdisk.cpio.gz
331 12:41:53.878141 - {KERNEL}: 12703544/tftp-deploy-ezbae8ku/kernel/Image
332 12:41:53.878199 - {LAVA_MAC}: None
333 12:41:53.878254 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj
334 12:41:53.878310 - {NFS_SERVER_IP}: 192.168.201.1
335 12:41:53.878364 - {PRESEED_CONFIG}: None
336 12:41:53.878417 - {PRESEED_LOCAL}: None
337 12:41:53.878470 - {RAMDISK}: 12703544/tftp-deploy-ezbae8ku/ramdisk/ramdisk.cpio.gz
338 12:41:53.878524 - {ROOT_PART}: None
339 12:41:53.878577 - {ROOT}: None
340 12:41:53.878630 - {SERVER_IP}: 192.168.201.1
341 12:41:53.878682 - {TEE}: None
342 12:41:53.878734 Parsed boot commands:
343 12:41:53.878786 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:41:53.878964 Parsed boot commands: tftpboot 192.168.201.1 12703544/tftp-deploy-ezbae8ku/kernel/image.itb 12703544/tftp-deploy-ezbae8ku/kernel/cmdline
345 12:41:53.879051 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:41:53.879134 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:41:53.879226 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:41:53.879311 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:41:53.879408 Not connected, no need to disconnect.
350 12:41:53.879498 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:41:53.879576 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:41:53.879643 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 12:41:53.883585 Setting prompt string to ['lava-test: # ']
354 12:41:53.883946 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:41:53.884053 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:41:53.884151 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:41:53.884301 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:41:53.884612 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 12:41:59.025137 >> Command sent successfully.
360 12:41:59.035900 Returned 0 in 5 seconds
361 12:41:59.137263 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:41:59.138735 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:41:59.139222 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:41:59.139733 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:41:59.140082 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:41:59.140421 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:41:59.141644 [Enter `^Ec?' for help]
369 12:41:59.304016
370 12:41:59.304564
371 12:41:59.304922 F0: 102B 0000
372 12:41:59.305498
373 12:41:59.305885 F3: 1001 0000 [0200]
374 12:41:59.306251
375 12:41:59.307475 F3: 1001 0000
376 12:41:59.307908
377 12:41:59.308246 F7: 102D 0000
378 12:41:59.308566
379 12:41:59.308870 F1: 0000 0000
380 12:41:59.311472
381 12:41:59.311902 V0: 0000 0000 [0001]
382 12:41:59.312261
383 12:41:59.312577 00: 0007 8000
384 12:41:59.312899
385 12:41:59.314578 01: 0000 0000
386 12:41:59.315018
387 12:41:59.315358 BP: 0C00 0209 [0000]
388 12:41:59.315716
389 12:41:59.318716 G0: 1182 0000
390 12:41:59.319147
391 12:41:59.319538 EC: 0000 0021 [4000]
392 12:41:59.319871
393 12:41:59.322104 S7: 0000 0000 [0000]
394 12:41:59.322534
395 12:41:59.322916 CC: 0000 0000 [0001]
396 12:41:59.323243
397 12:41:59.325050 T0: 0000 0040 [010F]
398 12:41:59.325513
399 12:41:59.325852 Jump to BL
400 12:41:59.326170
401 12:41:59.351121
402 12:41:59.351775
403 12:41:59.352230
404 12:41:59.358641 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:41:59.362027 ARM64: Exception handlers installed.
406 12:41:59.366117 ARM64: Testing exception
407 12:41:59.369292 ARM64: Done test exception
408 12:41:59.377016 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:41:59.383570 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:41:59.391080 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:41:59.401495 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:41:59.408246 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:41:59.418624 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:41:59.429207 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:41:59.435882 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:41:59.453855 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:41:59.456666 WDT: Last reset was cold boot
418 12:41:59.459987 SPI1(PAD0) initialized at 2873684 Hz
419 12:41:59.464054 SPI5(PAD0) initialized at 992727 Hz
420 12:41:59.467319 VBOOT: Loading verstage.
421 12:41:59.473382 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:41:59.477257 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:41:59.480006 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:41:59.483650 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:41:59.491237 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:41:59.499023 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:41:59.508406 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
428 12:41:59.508996
429 12:41:59.509490
430 12:41:59.518841 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:41:59.522299 ARM64: Exception handlers installed.
432 12:41:59.526146 ARM64: Testing exception
433 12:41:59.526640 ARM64: Done test exception
434 12:41:59.532899 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:41:59.536253 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:41:59.550325 Probing TPM: . done!
437 12:41:59.550903 TPM ready after 0 ms
438 12:41:59.557470 Connected to device vid:did:rid of 1ae0:0028:00
439 12:41:59.564336 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 12:41:59.620884 Initialized TPM device CR50 revision 0
441 12:41:59.631981 tlcl_send_startup: Startup return code is 0
442 12:41:59.632439 TPM: setup succeeded
443 12:41:59.644150 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:41:59.652618 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:41:59.664762 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:41:59.674646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:41:59.677978 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:41:59.684596 in-header: 03 07 00 00 08 00 00 00
449 12:41:59.687531 in-data: aa e4 47 04 13 02 00 00
450 12:41:59.690989 Chrome EC: UHEPI supported
451 12:41:59.699176 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:41:59.702508 in-header: 03 95 00 00 08 00 00 00
453 12:41:59.705670 in-data: 18 20 20 08 00 00 00 00
454 12:41:59.706225 Phase 1
455 12:41:59.709763 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:41:59.712982 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:41:59.720165 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:41:59.725096 Recovery requested (1009000e)
459 12:41:59.732048 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:41:59.738041 tlcl_extend: response is 0
461 12:41:59.746735 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:41:59.752310 tlcl_extend: response is 0
463 12:41:59.759184 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:41:59.779143 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 12:41:59.786143 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:41:59.786580
467 12:41:59.786917
468 12:41:59.795948 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:41:59.799828 ARM64: Exception handlers installed.
470 12:41:59.802196 ARM64: Testing exception
471 12:41:59.802632 ARM64: Done test exception
472 12:41:59.825003 pmic_efuse_setting: Set efuses in 11 msecs
473 12:41:59.828020 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:41:59.834860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:41:59.838824 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:41:59.845495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:41:59.848514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:41:59.852163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:41:59.859333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:41:59.862902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:41:59.866804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:41:59.874051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:41:59.877628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:41:59.881320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:41:59.885903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:41:59.892046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:41:59.895546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:41:59.903284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:41:59.910024 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:41:59.914365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:41:59.921118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:41:59.924730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:41:59.932689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:41:59.936089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:41:59.944362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:41:59.946735 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:41:59.954695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:41:59.958365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:41:59.965396 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:41:59.968735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:41:59.972596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:41:59.979701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:41:59.983022 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:41:59.989848 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:41:59.993749 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:41:59.997724 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:42:00.004334 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:42:00.007796 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:42:00.015818 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:42:00.019258 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:42:00.022597 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:42:00.026631 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:42:00.033486 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:42:00.037017 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:42:00.041303 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:42:00.044389 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:42:00.051683 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:42:00.055050 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:42:00.058726 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:42:00.062754 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:42:00.066034 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:42:00.073604 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:42:00.076879 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:42:00.080405 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:42:00.087988 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:42:00.095554 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:42:00.099057 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:42:00.110199 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:42:00.118354 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:42:00.121425 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:42:00.125504 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:42:00.132621 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:42:00.139416 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 12:42:00.143589 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:42:00.147127 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 12:42:00.153865 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:42:00.162604 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 12:42:00.172300 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 12:42:00.181255 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 12:42:00.191214 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 12:42:00.199994 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 12:42:00.210403 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 12:42:00.220108 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 12:42:00.223184 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 12:42:00.227317 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 12:42:00.234344 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:42:00.237864 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:42:00.241849 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:42:00.245123 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:42:00.249811 ADC[4]: Raw value=905172 ID=7
551 12:42:00.252961 ADC[3]: Raw value=213916 ID=1
552 12:42:00.253448 RAM Code: 0x71
553 12:42:00.256936 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:42:00.263694 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:42:00.271185 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:42:00.278840 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:42:00.282362 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:42:00.286294 in-header: 03 07 00 00 08 00 00 00
559 12:42:00.287043 in-data: aa e4 47 04 13 02 00 00
560 12:42:00.289368 Chrome EC: UHEPI supported
561 12:42:00.296519 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:42:00.300949 in-header: 03 95 00 00 08 00 00 00
563 12:42:00.304244 in-data: 18 20 20 08 00 00 00 00
564 12:42:00.307624 MRC: failed to locate region type 0.
565 12:42:00.314853 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:42:00.318727 DRAM-K: Running full calibration
567 12:42:00.322457 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:42:00.325876 header.status = 0x0
569 12:42:00.329669 header.version = 0x6 (expected: 0x6)
570 12:42:00.333428 header.size = 0xd00 (expected: 0xd00)
571 12:42:00.334058 header.flags = 0x0
572 12:42:00.339987 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:42:00.357659 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:42:00.365285 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:42:00.368466 dram_init: ddr_geometry: 2
576 12:42:00.368921 [EMI] MDL number = 2
577 12:42:00.372269 [EMI] Get MDL freq = 0
578 12:42:00.372716 dram_init: ddr_type: 0
579 12:42:00.376349 is_discrete_lpddr4: 1
580 12:42:00.379889 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:42:00.380348
582 12:42:00.380699
583 12:42:00.381023 [Bian_co] ETT version 0.0.0.1
584 12:42:00.386508 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:42:00.386949
586 12:42:00.390022 dramc_set_vcore_voltage set vcore to 650000
587 12:42:00.393265 Read voltage for 800, 4
588 12:42:00.393709 Vio18 = 0
589 12:42:00.394077 Vcore = 650000
590 12:42:00.396739 Vdram = 0
591 12:42:00.397192 Vddq = 0
592 12:42:00.397593 Vmddr = 0
593 12:42:00.401086 dram_init: config_dvfs: 1
594 12:42:00.404082 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:42:00.411655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:42:00.415555 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 12:42:00.418907 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 12:42:00.421916 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 12:42:00.425986 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 12:42:00.429009 MEM_TYPE=3, freq_sel=18
601 12:42:00.431897 sv_algorithm_assistance_LP4_1600
602 12:42:00.435829 ============ PULL DRAM RESETB DOWN ============
603 12:42:00.438755 ========== PULL DRAM RESETB DOWN end =========
604 12:42:00.441637 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:42:00.445397 ===================================
606 12:42:00.449185 LPDDR4 DRAM CONFIGURATION
607 12:42:00.452121 ===================================
608 12:42:00.455247 EX_ROW_EN[0] = 0x0
609 12:42:00.455820 EX_ROW_EN[1] = 0x0
610 12:42:00.458316 LP4Y_EN = 0x0
611 12:42:00.458755 WORK_FSP = 0x0
612 12:42:00.461753 WL = 0x2
613 12:42:00.462195 RL = 0x2
614 12:42:00.465339 BL = 0x2
615 12:42:00.465826 RPST = 0x0
616 12:42:00.468567 RD_PRE = 0x0
617 12:42:00.471584 WR_PRE = 0x1
618 12:42:00.472027 WR_PST = 0x0
619 12:42:00.475296 DBI_WR = 0x0
620 12:42:00.475785 DBI_RD = 0x0
621 12:42:00.478467 OTF = 0x1
622 12:42:00.481555 ===================================
623 12:42:00.484711 ===================================
624 12:42:00.485160 ANA top config
625 12:42:00.488351 ===================================
626 12:42:00.491700 DLL_ASYNC_EN = 0
627 12:42:00.494698 ALL_SLAVE_EN = 1
628 12:42:00.495143 NEW_RANK_MODE = 1
629 12:42:00.497676 DLL_IDLE_MODE = 1
630 12:42:00.501119 LP45_APHY_COMB_EN = 1
631 12:42:00.504593 TX_ODT_DIS = 1
632 12:42:00.505036 NEW_8X_MODE = 1
633 12:42:00.508506 ===================================
634 12:42:00.511888 ===================================
635 12:42:00.514863 data_rate = 1600
636 12:42:00.518307 CKR = 1
637 12:42:00.522046 DQ_P2S_RATIO = 8
638 12:42:00.524824 ===================================
639 12:42:00.528954 CA_P2S_RATIO = 8
640 12:42:00.529394 DQ_CA_OPEN = 0
641 12:42:00.532097 DQ_SEMI_OPEN = 0
642 12:42:00.535132 CA_SEMI_OPEN = 0
643 12:42:00.538596 CA_FULL_RATE = 0
644 12:42:00.542248 DQ_CKDIV4_EN = 1
645 12:42:00.545482 CA_CKDIV4_EN = 1
646 12:42:00.545920 CA_PREDIV_EN = 0
647 12:42:00.548383 PH8_DLY = 0
648 12:42:00.551984 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:42:00.554991 DQ_AAMCK_DIV = 4
650 12:42:00.558679 CA_AAMCK_DIV = 4
651 12:42:00.562425 CA_ADMCK_DIV = 4
652 12:42:00.562870 DQ_TRACK_CA_EN = 0
653 12:42:00.565399 CA_PICK = 800
654 12:42:00.568512 CA_MCKIO = 800
655 12:42:00.572539 MCKIO_SEMI = 0
656 12:42:00.575471 PLL_FREQ = 3068
657 12:42:00.579151 DQ_UI_PI_RATIO = 32
658 12:42:00.579645 CA_UI_PI_RATIO = 0
659 12:42:00.582934 ===================================
660 12:42:00.586692 ===================================
661 12:42:00.591011 memory_type:LPDDR4
662 12:42:00.591482 GP_NUM : 10
663 12:42:00.594200 SRAM_EN : 1
664 12:42:00.594643 MD32_EN : 0
665 12:42:00.598040 ===================================
666 12:42:00.601581 [ANA_INIT] >>>>>>>>>>>>>>
667 12:42:00.605368 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:42:00.608019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:42:00.611748 ===================================
670 12:42:00.614590 data_rate = 1600,PCW = 0X7600
671 12:42:00.618368 ===================================
672 12:42:00.621709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:42:00.624420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:42:00.631084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:42:00.635026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:42:00.638404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:42:00.641411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:42:00.644588 [ANA_INIT] flow start
679 12:42:00.647877 [ANA_INIT] PLL >>>>>>>>
680 12:42:00.648337 [ANA_INIT] PLL <<<<<<<<
681 12:42:00.651564 [ANA_INIT] MIDPI >>>>>>>>
682 12:42:00.655145 [ANA_INIT] MIDPI <<<<<<<<
683 12:42:00.655715 [ANA_INIT] DLL >>>>>>>>
684 12:42:00.658076 [ANA_INIT] flow end
685 12:42:00.661086 ============ LP4 DIFF to SE enter ============
686 12:42:00.668337 ============ LP4 DIFF to SE exit ============
687 12:42:00.668886 [ANA_INIT] <<<<<<<<<<<<<
688 12:42:00.672126 [Flow] Enable top DCM control >>>>>
689 12:42:00.674895 [Flow] Enable top DCM control <<<<<
690 12:42:00.678218 Enable DLL master slave shuffle
691 12:42:00.684544 ==============================================================
692 12:42:00.685099 Gating Mode config
693 12:42:00.691751 ==============================================================
694 12:42:00.694530 Config description:
695 12:42:00.701219 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:42:00.707979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:42:00.714580 SELPH_MODE 0: By rank 1: By Phase
698 12:42:00.721552 ==============================================================
699 12:42:00.722157 GAT_TRACK_EN = 1
700 12:42:00.724438 RX_GATING_MODE = 2
701 12:42:00.727758 RX_GATING_TRACK_MODE = 2
702 12:42:00.731484 SELPH_MODE = 1
703 12:42:00.734675 PICG_EARLY_EN = 1
704 12:42:00.737981 VALID_LAT_VALUE = 1
705 12:42:00.745019 ==============================================================
706 12:42:00.747906 Enter into Gating configuration >>>>
707 12:42:00.751244 Exit from Gating configuration <<<<
708 12:42:00.754628 Enter into DVFS_PRE_config >>>>>
709 12:42:00.764145 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:42:00.767513 Exit from DVFS_PRE_config <<<<<
711 12:42:00.770853 Enter into PICG configuration >>>>
712 12:42:00.774808 Exit from PICG configuration <<<<
713 12:42:00.777789 [RX_INPUT] configuration >>>>>
714 12:42:00.778229 [RX_INPUT] configuration <<<<<
715 12:42:00.784525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:42:00.791271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:42:00.794499 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:42:00.801229 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:42:00.807494 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:42:00.814466 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:42:00.817890 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:42:00.820755 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:42:00.827512 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:42:00.830688 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:42:00.834361 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:42:00.841012 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:42:00.844473 ===================================
728 12:42:00.845060 LPDDR4 DRAM CONFIGURATION
729 12:42:00.847781 ===================================
730 12:42:00.850914 EX_ROW_EN[0] = 0x0
731 12:42:00.854020 EX_ROW_EN[1] = 0x0
732 12:42:00.854604 LP4Y_EN = 0x0
733 12:42:00.857495 WORK_FSP = 0x0
734 12:42:00.858080 WL = 0x2
735 12:42:00.860265 RL = 0x2
736 12:42:00.860752 BL = 0x2
737 12:42:00.863730 RPST = 0x0
738 12:42:00.864216 RD_PRE = 0x0
739 12:42:00.866980 WR_PRE = 0x1
740 12:42:00.867572 WR_PST = 0x0
741 12:42:00.870203 DBI_WR = 0x0
742 12:42:00.870663 DBI_RD = 0x0
743 12:42:00.873673 OTF = 0x1
744 12:42:00.877337 ===================================
745 12:42:00.880276 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:42:00.883481 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:42:00.890212 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:42:00.893533 ===================================
749 12:42:00.894072 LPDDR4 DRAM CONFIGURATION
750 12:42:00.896887 ===================================
751 12:42:00.900616 EX_ROW_EN[0] = 0x10
752 12:42:00.901059 EX_ROW_EN[1] = 0x0
753 12:42:00.903198 LP4Y_EN = 0x0
754 12:42:00.906988 WORK_FSP = 0x0
755 12:42:00.907484 WL = 0x2
756 12:42:00.909943 RL = 0x2
757 12:42:00.910382 BL = 0x2
758 12:42:00.913183 RPST = 0x0
759 12:42:00.913623 RD_PRE = 0x0
760 12:42:00.917491 WR_PRE = 0x1
761 12:42:00.918029 WR_PST = 0x0
762 12:42:00.920071 DBI_WR = 0x0
763 12:42:00.920510 DBI_RD = 0x0
764 12:42:00.923141 OTF = 0x1
765 12:42:00.927054 ===================================
766 12:42:00.934478 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:42:00.936892 nWR fixed to 40
768 12:42:00.937542 [ModeRegInit_LP4] CH0 RK0
769 12:42:00.939921 [ModeRegInit_LP4] CH0 RK1
770 12:42:00.943522 [ModeRegInit_LP4] CH1 RK0
771 12:42:00.944059 [ModeRegInit_LP4] CH1 RK1
772 12:42:00.947509 match AC timing 13
773 12:42:00.949883 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:42:00.953287 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:42:00.959813 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:42:00.963072 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:42:00.969697 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:42:00.970224 [EMI DOE] emi_dcm 0
779 12:42:00.973185 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:42:00.976792 ==
781 12:42:00.979934 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:42:00.983431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:42:00.984180 ==
784 12:42:00.990187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:42:00.993317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:42:01.003719 [CA 0] Center 37 (7~68) winsize 62
787 12:42:01.007159 [CA 1] Center 37 (6~68) winsize 63
788 12:42:01.009991 [CA 2] Center 34 (4~65) winsize 62
789 12:42:01.013043 [CA 3] Center 35 (4~66) winsize 63
790 12:42:01.017355 [CA 4] Center 33 (3~64) winsize 62
791 12:42:01.019488 [CA 5] Center 33 (3~64) winsize 62
792 12:42:01.019933
793 12:42:01.022843 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:42:01.023282
795 12:42:01.027227 [CATrainingPosCal] consider 1 rank data
796 12:42:01.029811 u2DelayCellTimex100 = 270/100 ps
797 12:42:01.033301 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:42:01.039599 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 12:42:01.042954 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 12:42:01.046399 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 12:42:01.049859 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 12:42:01.053511 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:42:01.054091
804 12:42:01.056096 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:42:01.056579
806 12:42:01.059710 [CBTSetCACLKResult] CA Dly = 33
807 12:42:01.060245 CS Dly: 5 (0~36)
808 12:42:01.063273 ==
809 12:42:01.066277 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:42:01.069574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:42:01.070067 ==
812 12:42:01.073112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:42:01.079709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:42:01.089959 [CA 0] Center 38 (7~69) winsize 63
815 12:42:01.092629 [CA 1] Center 37 (7~68) winsize 62
816 12:42:01.096291 [CA 2] Center 34 (4~65) winsize 62
817 12:42:01.099191 [CA 3] Center 35 (4~66) winsize 63
818 12:42:01.102788 [CA 4] Center 34 (3~65) winsize 63
819 12:42:01.106365 [CA 5] Center 33 (3~64) winsize 62
820 12:42:01.106947
821 12:42:01.109093 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:42:01.109606
823 12:42:01.112843 [CATrainingPosCal] consider 2 rank data
824 12:42:01.116130 u2DelayCellTimex100 = 270/100 ps
825 12:42:01.119410 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:42:01.125917 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:42:01.129186 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 12:42:01.132723 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 12:42:01.136352 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:42:01.139195 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:42:01.139896
832 12:42:01.142381 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:42:01.143051
834 12:42:01.145376 [CBTSetCACLKResult] CA Dly = 33
835 12:42:01.149488 CS Dly: 6 (0~38)
836 12:42:01.150090
837 12:42:01.153359 ----->DramcWriteLeveling(PI) begin...
838 12:42:01.153970 ==
839 12:42:01.157003 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:42:01.160118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:42:01.160654 ==
842 12:42:01.163833 Write leveling (Byte 0): 32 => 32
843 12:42:01.164274 Write leveling (Byte 1): 26 => 26
844 12:42:01.167748 DramcWriteLeveling(PI) end<-----
845 12:42:01.168191
846 12:42:01.168541 ==
847 12:42:01.170906 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:42:01.174193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:42:01.177933 ==
850 12:42:01.178471 [Gating] SW mode calibration
851 12:42:01.185250 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:42:01.192271 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:42:01.194949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:42:01.202105 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 12:42:01.204953 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 12:42:01.208073 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 12:42:01.215231 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:42:01.218127 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:42:01.221317 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:42:01.224619 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:42:01.231437 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:42:01.235026 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:42:01.238280 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:42:01.244309 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:42:01.248043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:42:01.251424 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:42:01.258268 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:42:01.261910 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:42:01.264327 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:42:01.270996 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 12:42:01.274653 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 12:42:01.278244 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 12:42:01.284596 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:42:01.288149 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:42:01.290813 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:42:01.298219 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:42:01.301340 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:42:01.304659 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:42:01.312009 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
880 12:42:01.314310 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
881 12:42:01.317523 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:42:01.323750 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:42:01.327582 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:42:01.331047 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:42:01.337410 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:42:01.341399 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
887 12:42:01.344041 0 10 8 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
888 12:42:01.350458 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 12:42:01.354215 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:42:01.357980 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:42:01.364445 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:42:01.367523 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:42:01.370214 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:42:01.377262 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
895 12:42:01.380357 0 11 8 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
896 12:42:01.383530 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
897 12:42:01.388284 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:42:01.394330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:42:01.397223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:42:01.400047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:42:01.406993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:42:01.410220 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:42:01.414310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 12:42:01.420634 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 12:42:01.423562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:42:01.427166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:42:01.433583 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:42:01.436593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:42:01.440363 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:42:01.446899 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:42:01.449942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:42:01.453509 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:42:01.460168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:42:01.463548 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:42:01.467178 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:42:01.473710 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:42:01.476558 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:42:01.480509 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 12:42:01.486609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 12:42:01.487143 Total UI for P1: 0, mck2ui 16
921 12:42:01.493258 best dqsien dly found for B0: ( 0, 14, 4)
922 12:42:01.496470 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 12:42:01.499774 Total UI for P1: 0, mck2ui 16
924 12:42:01.503701 best dqsien dly found for B1: ( 0, 14, 8)
925 12:42:01.506912 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 12:42:01.509721 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 12:42:01.510155
928 12:42:01.513285 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 12:42:01.516629 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:42:01.520319 [Gating] SW calibration Done
931 12:42:01.520895 ==
932 12:42:01.523124 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:42:01.526964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:42:01.527605 ==
935 12:42:01.530445 RX Vref Scan: 0
936 12:42:01.531031
937 12:42:01.531481 RX Vref 0 -> 0, step: 1
938 12:42:01.531864
939 12:42:01.533928 RX Delay -130 -> 252, step: 16
940 12:42:01.540772 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:42:01.543535 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:42:01.547103 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:42:01.550618 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:42:01.553808 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 12:42:01.556740 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 12:42:01.563784 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 12:42:01.566669 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 12:42:01.570046 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 12:42:01.573747 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 12:42:01.581028 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 12:42:01.583267 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:42:01.587171 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 12:42:01.590789 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 12:42:01.593545 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 12:42:01.600148 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 12:42:01.600691 ==
957 12:42:01.603056 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:42:01.606688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:42:01.607258 ==
960 12:42:01.607700 DQS Delay:
961 12:42:01.610482 DQS0 = 0, DQS1 = 0
962 12:42:01.611032 DQM Delay:
963 12:42:01.613113 DQM0 = 88, DQM1 = 76
964 12:42:01.613549 DQ Delay:
965 12:42:01.616287 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:42:01.619812 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 12:42:01.622871 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
968 12:42:01.626331 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 12:42:01.626767
970 12:42:01.627111
971 12:42:01.627463 ==
972 12:42:01.629795 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:42:01.633455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:42:01.636347 ==
975 12:42:01.636784
976 12:42:01.637130
977 12:42:01.637451 TX Vref Scan disable
978 12:42:01.639653 == TX Byte 0 ==
979 12:42:01.642975 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 12:42:01.646455 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 12:42:01.649233 == TX Byte 1 ==
982 12:42:01.653150 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
983 12:42:01.656664 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
984 12:42:01.660279 ==
985 12:42:01.660880 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:42:01.665958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:42:01.666491 ==
988 12:42:01.678813 TX Vref=22, minBit 3, minWin=26, winSum=435
989 12:42:01.682506 TX Vref=24, minBit 1, minWin=27, winSum=441
990 12:42:01.686074 TX Vref=26, minBit 1, minWin=27, winSum=449
991 12:42:01.689281 TX Vref=28, minBit 1, minWin=27, winSum=450
992 12:42:01.692845 TX Vref=30, minBit 8, minWin=27, winSum=451
993 12:42:01.699165 TX Vref=32, minBit 0, minWin=28, winSum=451
994 12:42:01.702412 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
995 12:42:01.702991
996 12:42:01.705514 Final TX Range 1 Vref 32
997 12:42:01.706099
998 12:42:01.706487 ==
999 12:42:01.708757 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:42:01.712115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:42:01.715349 ==
1002 12:42:01.715938
1003 12:42:01.716286
1004 12:42:01.716628 TX Vref Scan disable
1005 12:42:01.719533 == TX Byte 0 ==
1006 12:42:01.723131 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 12:42:01.729527 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 12:42:01.730127 == TX Byte 1 ==
1009 12:42:01.732200 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1010 12:42:01.739468 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1011 12:42:01.740050
1012 12:42:01.740439 [DATLAT]
1013 12:42:01.740796 Freq=800, CH0 RK0
1014 12:42:01.741143
1015 12:42:01.742417 DATLAT Default: 0xa
1016 12:42:01.742891 0, 0xFFFF, sum = 0
1017 12:42:01.745779 1, 0xFFFF, sum = 0
1018 12:42:01.746339 2, 0xFFFF, sum = 0
1019 12:42:01.749257 3, 0xFFFF, sum = 0
1020 12:42:01.749820 4, 0xFFFF, sum = 0
1021 12:42:01.752309 5, 0xFFFF, sum = 0
1022 12:42:01.755574 6, 0xFFFF, sum = 0
1023 12:42:01.756106 7, 0xFFFF, sum = 0
1024 12:42:01.759121 8, 0xFFFF, sum = 0
1025 12:42:01.759719 9, 0x0, sum = 1
1026 12:42:01.760094 10, 0x0, sum = 2
1027 12:42:01.762389 11, 0x0, sum = 3
1028 12:42:01.762920 12, 0x0, sum = 4
1029 12:42:01.765653 best_step = 10
1030 12:42:01.766091
1031 12:42:01.766513 ==
1032 12:42:01.768865 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:42:01.772029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:42:01.772486 ==
1035 12:42:01.775239 RX Vref Scan: 1
1036 12:42:01.775717
1037 12:42:01.779268 Set Vref Range= 32 -> 127
1038 12:42:01.779853
1039 12:42:01.780207 RX Vref 32 -> 127, step: 1
1040 12:42:01.780531
1041 12:42:01.782289 RX Delay -111 -> 252, step: 8
1042 12:42:01.782999
1043 12:42:01.785291 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:42:01.788724 [Byte1]: 32
1045 12:42:01.792010
1046 12:42:01.792433 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:42:01.794893 [Byte1]: 33
1048 12:42:01.799358
1049 12:42:01.799839 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:42:01.803335 [Byte1]: 34
1051 12:42:01.807615
1052 12:42:01.808160 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:42:01.810516 [Byte1]: 35
1054 12:42:01.815107
1055 12:42:01.815693 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:42:01.818751 [Byte1]: 36
1057 12:42:01.822425
1058 12:42:01.822925 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:42:01.826775 [Byte1]: 37
1060 12:42:01.830962
1061 12:42:01.831473 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:42:01.834238 [Byte1]: 38
1063 12:42:01.838576
1064 12:42:01.839133 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:42:01.841266 [Byte1]: 39
1066 12:42:01.846497
1067 12:42:01.847034 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:42:01.849930 [Byte1]: 40
1069 12:42:01.853953
1070 12:42:01.854522 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:42:01.859211 [Byte1]: 41
1072 12:42:01.861230
1073 12:42:01.861654 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:42:01.867577 [Byte1]: 42
1075 12:42:01.868078
1076 12:42:01.870541 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:42:01.873473 [Byte1]: 43
1078 12:42:01.873904
1079 12:42:01.877281 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:42:01.880172 [Byte1]: 44
1081 12:42:01.883720
1082 12:42:01.884148 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:42:01.886989 [Byte1]: 45
1084 12:42:01.891226
1085 12:42:01.891732 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:42:01.894311 [Byte1]: 46
1087 12:42:01.898898
1088 12:42:01.899330 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:42:01.902162 [Byte1]: 47
1090 12:42:01.906468
1091 12:42:01.906895 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:42:01.909602 [Byte1]: 48
1093 12:42:01.914186
1094 12:42:01.914613 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:42:01.917356 [Byte1]: 49
1096 12:42:01.921578
1097 12:42:01.921883 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:42:01.924830 [Byte1]: 50
1099 12:42:01.929523
1100 12:42:01.929818 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:42:01.932777 [Byte1]: 51
1102 12:42:01.936606
1103 12:42:01.936845 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:42:01.939750 [Byte1]: 52
1105 12:42:01.944781
1106 12:42:01.944967 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:42:01.947546 [Byte1]: 53
1108 12:42:01.952331
1109 12:42:01.952499 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:42:01.955099 [Byte1]: 54
1111 12:42:01.959590
1112 12:42:01.959706 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:42:01.963591 [Byte1]: 55
1114 12:42:01.967119
1115 12:42:01.967227 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:42:01.971093 [Byte1]: 56
1117 12:42:01.974632
1118 12:42:01.974740 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:42:01.978877 [Byte1]: 57
1120 12:42:01.983044
1121 12:42:01.983152 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:42:01.985697 [Byte1]: 58
1123 12:42:01.990161
1124 12:42:01.990269 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:42:01.993343 [Byte1]: 59
1126 12:42:01.998162
1127 12:42:01.998243 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:42:02.000924 [Byte1]: 60
1129 12:42:02.005327
1130 12:42:02.005404 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:42:02.008501 [Byte1]: 61
1132 12:42:02.013710
1133 12:42:02.013794 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:42:02.016418 [Byte1]: 62
1135 12:42:02.020917
1136 12:42:02.021079 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:42:02.024342 [Byte1]: 63
1138 12:42:02.028965
1139 12:42:02.029132 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:42:02.032154 [Byte1]: 64
1141 12:42:02.036282
1142 12:42:02.036457 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:42:02.039958 [Byte1]: 65
1144 12:42:02.043933
1145 12:42:02.044023 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:42:02.047047 [Byte1]: 66
1147 12:42:02.051660
1148 12:42:02.051835 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:42:02.054631 [Byte1]: 67
1150 12:42:02.059245
1151 12:42:02.059484 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:42:02.062578 [Byte1]: 68
1153 12:42:02.066865
1154 12:42:02.067058 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:42:02.069746 [Byte1]: 69
1156 12:42:02.074519
1157 12:42:02.074760 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:42:02.078132 [Byte1]: 70
1159 12:42:02.082299
1160 12:42:02.082561 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:42:02.085913 [Byte1]: 71
1162 12:42:02.090154
1163 12:42:02.090496 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:42:02.093569 [Byte1]: 72
1165 12:42:02.097804
1166 12:42:02.098214 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:42:02.100898 [Byte1]: 73
1168 12:42:02.105395
1169 12:42:02.105977 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:42:02.108414 [Byte1]: 74
1171 12:42:02.112906
1172 12:42:02.113335 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:42:02.116216 [Byte1]: 75
1174 12:42:02.120608
1175 12:42:02.121145 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:42:02.123748 [Byte1]: 76
1177 12:42:02.128323
1178 12:42:02.128856 Set Vref, RX VrefLevel [Byte0]: 77
1179 12:42:02.131646 [Byte1]: 77
1180 12:42:02.135519
1181 12:42:02.135955 Final RX Vref Byte 0 = 57 to rank0
1182 12:42:02.139340 Final RX Vref Byte 1 = 59 to rank0
1183 12:42:02.142563 Final RX Vref Byte 0 = 57 to rank1
1184 12:42:02.145578 Final RX Vref Byte 1 = 59 to rank1==
1185 12:42:02.149058 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 12:42:02.155823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 12:42:02.156344 ==
1188 12:42:02.156690 DQS Delay:
1189 12:42:02.157003 DQS0 = 0, DQS1 = 0
1190 12:42:02.158731 DQM Delay:
1191 12:42:02.159164 DQM0 = 88, DQM1 = 76
1192 12:42:02.162154 DQ Delay:
1193 12:42:02.166448 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1194 12:42:02.169644 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1195 12:42:02.172427 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
1196 12:42:02.176268 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1197 12:42:02.176699
1198 12:42:02.177052
1199 12:42:02.181916 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1200 12:42:02.185675 CH0 RK0: MR19=606, MR18=2C26
1201 12:42:02.192498 CH0_RK0: MR19=0x606, MR18=0x2C26, DQSOSC=398, MR23=63, INC=93, DEC=62
1202 12:42:02.192935
1203 12:42:02.195743 ----->DramcWriteLeveling(PI) begin...
1204 12:42:02.196180 ==
1205 12:42:02.199087 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 12:42:02.202268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 12:42:02.202741 ==
1208 12:42:02.205677 Write leveling (Byte 0): 31 => 31
1209 12:42:02.208620 Write leveling (Byte 1): 26 => 26
1210 12:42:02.211988 DramcWriteLeveling(PI) end<-----
1211 12:42:02.212429
1212 12:42:02.212770 ==
1213 12:42:02.215957 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 12:42:02.259493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 12:42:02.259954 ==
1216 12:42:02.260301 [Gating] SW mode calibration
1217 12:42:02.260994 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 12:42:02.261571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 12:42:02.261924 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 12:42:02.262243 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 12:42:02.262608 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1222 12:42:02.263002 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:42:02.263315 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:42:02.263673 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:42:02.268188 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:42:02.271260 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:42:02.274738 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:42:02.278062 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:42:02.285088 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:42:02.288076 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:42:02.291651 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:42:02.298130 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:42:02.301139 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:42:02.304567 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:42:02.310757 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:42:02.314160 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 12:42:02.318635 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1238 12:42:02.320982 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:42:02.327464 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:42:02.330794 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:42:02.334366 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:42:02.340651 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:42:02.344323 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:42:02.347412 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:42:02.353765 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1246 12:42:02.358103 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1247 12:42:02.360821 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:42:02.367490 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 12:42:02.370252 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 12:42:02.373678 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:42:02.380438 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1252 12:42:02.383941 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 0) (0 0)
1253 12:42:02.387122 0 10 8 | B1->B0 | 3232 2525 | 1 0 | (0 1) (1 1)
1254 12:42:02.394025 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1255 12:42:02.397009 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:42:02.400734 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:42:02.407847 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:42:02.411601 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:42:02.414618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:42:02.418367 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1261 12:42:02.425214 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1262 12:42:02.428830 0 11 12 | B1->B0 | 4342 4646 | 1 0 | (1 1) (0 0)
1263 12:42:02.432063 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:42:02.435698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 12:42:02.442504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 12:42:02.445602 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:42:02.448634 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:42:02.455724 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 12:42:02.458895 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 12:42:02.461944 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:42:02.468983 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:42:02.471979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:42:02.475454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:42:02.482097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:42:02.485780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:42:02.488650 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:42:02.495913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:42:02.498665 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:42:02.502470 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:42:02.508806 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:42:02.511860 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:42:02.515255 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:42:02.522295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:42:02.525416 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:42:02.528602 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 12:42:02.532200 Total UI for P1: 0, mck2ui 16
1287 12:42:02.535435 best dqsien dly found for B0: ( 0, 14, 6)
1288 12:42:02.539215 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 12:42:02.542120 Total UI for P1: 0, mck2ui 16
1290 12:42:02.545364 best dqsien dly found for B1: ( 0, 14, 8)
1291 12:42:02.548892 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1292 12:42:02.551864 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 12:42:02.554939
1294 12:42:02.558732 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 12:42:02.562317 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 12:42:02.565384 [Gating] SW calibration Done
1297 12:42:02.565814 ==
1298 12:42:02.568862 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 12:42:02.571953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 12:42:02.572497 ==
1301 12:42:02.572850 RX Vref Scan: 0
1302 12:42:02.573179
1303 12:42:02.575272 RX Vref 0 -> 0, step: 1
1304 12:42:02.575830
1305 12:42:02.578599 RX Delay -130 -> 252, step: 16
1306 12:42:02.582659 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1307 12:42:02.585512 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1308 12:42:02.591872 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1309 12:42:02.595147 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1310 12:42:02.598522 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1311 12:42:02.601505 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1312 12:42:02.604994 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1313 12:42:02.612158 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1314 12:42:02.615089 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1315 12:42:02.618192 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1316 12:42:02.621664 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1317 12:42:02.624773 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1318 12:42:02.631166 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1319 12:42:02.634617 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1320 12:42:02.637822 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1321 12:42:02.641351 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1322 12:42:02.641803 ==
1323 12:42:02.644520 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 12:42:02.651114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 12:42:02.651598 ==
1326 12:42:02.651941 DQS Delay:
1327 12:42:02.654650 DQS0 = 0, DQS1 = 0
1328 12:42:02.655076 DQM Delay:
1329 12:42:02.655452 DQM0 = 90, DQM1 = 78
1330 12:42:02.657896 DQ Delay:
1331 12:42:02.661491 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1332 12:42:02.664545 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1333 12:42:02.668384 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1334 12:42:02.671427 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1335 12:42:02.671866
1336 12:42:02.672210
1337 12:42:02.672526 ==
1338 12:42:02.674463 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 12:42:02.677846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 12:42:02.678280 ==
1341 12:42:02.678625
1342 12:42:02.678945
1343 12:42:02.681368 TX Vref Scan disable
1344 12:42:02.681797 == TX Byte 0 ==
1345 12:42:02.688025 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1346 12:42:02.691248 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1347 12:42:02.691831 == TX Byte 1 ==
1348 12:42:02.697804 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1349 12:42:02.701412 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1350 12:42:02.701846 ==
1351 12:42:02.704332 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 12:42:02.708446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 12:42:02.708885 ==
1354 12:42:02.722574 TX Vref=22, minBit 1, minWin=27, winSum=440
1355 12:42:02.726130 TX Vref=24, minBit 1, minWin=27, winSum=448
1356 12:42:02.729223 TX Vref=26, minBit 1, minWin=27, winSum=448
1357 12:42:02.732369 TX Vref=28, minBit 1, minWin=27, winSum=451
1358 12:42:02.735829 TX Vref=30, minBit 0, minWin=28, winSum=452
1359 12:42:02.742286 TX Vref=32, minBit 1, minWin=27, winSum=450
1360 12:42:02.745584 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1361 12:42:02.746013
1362 12:42:02.748992 Final TX Range 1 Vref 30
1363 12:42:02.749422
1364 12:42:02.749760 ==
1365 12:42:02.752456 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 12:42:02.755729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 12:42:02.756162 ==
1368 12:42:02.756503
1369 12:42:02.758838
1370 12:42:02.759266 TX Vref Scan disable
1371 12:42:02.762330 == TX Byte 0 ==
1372 12:42:02.765731 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1373 12:42:02.768755 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1374 12:42:02.772047 == TX Byte 1 ==
1375 12:42:02.775279 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1376 12:42:02.782168 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1377 12:42:02.782323
1378 12:42:02.782446 [DATLAT]
1379 12:42:02.782559 Freq=800, CH0 RK1
1380 12:42:02.782670
1381 12:42:02.785544 DATLAT Default: 0xa
1382 12:42:02.785676 0, 0xFFFF, sum = 0
1383 12:42:02.788833 1, 0xFFFF, sum = 0
1384 12:42:02.788968 2, 0xFFFF, sum = 0
1385 12:42:02.792124 3, 0xFFFF, sum = 0
1386 12:42:02.795121 4, 0xFFFF, sum = 0
1387 12:42:02.795256 5, 0xFFFF, sum = 0
1388 12:42:02.798730 6, 0xFFFF, sum = 0
1389 12:42:02.798865 7, 0xFFFF, sum = 0
1390 12:42:02.802270 8, 0xFFFF, sum = 0
1391 12:42:02.802405 9, 0x0, sum = 1
1392 12:42:02.802512 10, 0x0, sum = 2
1393 12:42:02.805216 11, 0x0, sum = 3
1394 12:42:02.805350 12, 0x0, sum = 4
1395 12:42:02.808648 best_step = 10
1396 12:42:02.808779
1397 12:42:02.808885 ==
1398 12:42:02.811778 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 12:42:02.814997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 12:42:02.815146 ==
1401 12:42:02.818307 RX Vref Scan: 0
1402 12:42:02.818455
1403 12:42:02.818572 RX Vref 0 -> 0, step: 1
1404 12:42:02.821553
1405 12:42:02.821719 RX Delay -95 -> 252, step: 8
1406 12:42:02.828837 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1407 12:42:02.832061 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1408 12:42:02.835935 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1409 12:42:02.839012 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1410 12:42:02.842321 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1411 12:42:02.849390 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1412 12:42:02.852323 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1413 12:42:02.855500 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1414 12:42:02.858791 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1415 12:42:02.862292 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1416 12:42:02.868537 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1417 12:42:02.872147 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1418 12:42:02.875218 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1419 12:42:02.878753 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1420 12:42:02.885361 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1421 12:42:02.889147 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1422 12:42:02.889575 ==
1423 12:42:02.891793 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 12:42:02.895055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 12:42:02.895523 ==
1426 12:42:02.899303 DQS Delay:
1427 12:42:02.899774 DQS0 = 0, DQS1 = 0
1428 12:42:02.900117 DQM Delay:
1429 12:42:02.902305 DQM0 = 86, DQM1 = 76
1430 12:42:02.902729 DQ Delay:
1431 12:42:02.905854 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1432 12:42:02.908770 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1433 12:42:02.912075 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1434 12:42:02.915421 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1435 12:42:02.915850
1436 12:42:02.916186
1437 12:42:02.925514 [DQSOSCAuto] RK1, (LSB)MR18= 0x2924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1438 12:42:02.925946 CH0 RK1: MR19=606, MR18=2924
1439 12:42:02.932256 CH0_RK1: MR19=0x606, MR18=0x2924, DQSOSC=399, MR23=63, INC=92, DEC=61
1440 12:42:02.934908 [RxdqsGatingPostProcess] freq 800
1441 12:42:02.941473 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 12:42:02.944971 Pre-setting of DQS Precalculation
1443 12:42:02.948638 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 12:42:02.949067 ==
1445 12:42:02.951862 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 12:42:02.958995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 12:42:02.959468 ==
1448 12:42:02.961445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 12:42:02.968350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 12:42:02.977595 [CA 0] Center 36 (6~67) winsize 62
1451 12:42:02.980589 [CA 1] Center 36 (6~67) winsize 62
1452 12:42:02.984352 [CA 2] Center 35 (5~65) winsize 61
1453 12:42:02.987296 [CA 3] Center 34 (4~65) winsize 62
1454 12:42:02.991225 [CA 4] Center 34 (4~65) winsize 62
1455 12:42:02.994066 [CA 5] Center 34 (3~65) winsize 63
1456 12:42:02.994494
1457 12:42:02.997625 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1458 12:42:02.998054
1459 12:42:03.000833 [CATrainingPosCal] consider 1 rank data
1460 12:42:03.003883 u2DelayCellTimex100 = 270/100 ps
1461 12:42:03.007134 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 12:42:03.014070 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 12:42:03.017071 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 12:42:03.020489 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 12:42:03.023717 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 12:42:03.027022 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1467 12:42:03.027479
1468 12:42:03.030378 CA PerBit enable=1, Macro0, CA PI delay=34
1469 12:42:03.030802
1470 12:42:03.033952 [CBTSetCACLKResult] CA Dly = 34
1471 12:42:03.034379 CS Dly: 4 (0~35)
1472 12:42:03.036721 ==
1473 12:42:03.040542 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 12:42:03.044018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 12:42:03.044449 ==
1476 12:42:03.047351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 12:42:03.053856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 12:42:03.063663 [CA 0] Center 36 (6~67) winsize 62
1479 12:42:03.067351 [CA 1] Center 36 (6~67) winsize 62
1480 12:42:03.070942 [CA 2] Center 34 (4~65) winsize 62
1481 12:42:03.074233 [CA 3] Center 34 (3~65) winsize 63
1482 12:42:03.078131 [CA 4] Center 34 (3~65) winsize 63
1483 12:42:03.082422 [CA 5] Center 34 (3~65) winsize 63
1484 12:42:03.082846
1485 12:42:03.085429 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 12:42:03.085851
1487 12:42:03.089252 [CATrainingPosCal] consider 2 rank data
1488 12:42:03.092150 u2DelayCellTimex100 = 270/100 ps
1489 12:42:03.095663 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 12:42:03.098973 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 12:42:03.102303 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 12:42:03.106105 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 12:42:03.109521 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 12:42:03.112931 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1495 12:42:03.113362
1496 12:42:03.115986 CA PerBit enable=1, Macro0, CA PI delay=34
1497 12:42:03.116416
1498 12:42:03.119831 [CBTSetCACLKResult] CA Dly = 34
1499 12:42:03.122477 CS Dly: 5 (0~37)
1500 12:42:03.122906
1501 12:42:03.125984 ----->DramcWriteLeveling(PI) begin...
1502 12:42:03.126421 ==
1503 12:42:03.128987 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 12:42:03.132482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 12:42:03.132915 ==
1506 12:42:03.135654 Write leveling (Byte 0): 29 => 29
1507 12:42:03.139195 Write leveling (Byte 1): 29 => 29
1508 12:42:03.142575 DramcWriteLeveling(PI) end<-----
1509 12:42:03.143031
1510 12:42:03.143400 ==
1511 12:42:03.146470 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 12:42:03.149660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 12:42:03.150091 ==
1514 12:42:03.152491 [Gating] SW mode calibration
1515 12:42:03.159305 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 12:42:03.165911 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 12:42:03.169113 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 12:42:03.172556 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1519 12:42:03.178705 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:42:03.182383 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:42:03.185623 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:42:03.192414 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:42:03.195648 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:42:03.198778 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:42:03.205784 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:42:03.209245 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:42:03.212485 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:42:03.218414 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:42:03.222262 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:42:03.225450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:42:03.231957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:42:03.235490 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:42:03.238486 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:42:03.245602 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 12:42:03.248547 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:42:03.252622 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:42:03.258384 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:42:03.261637 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:42:03.265229 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:42:03.271454 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:42:03.275036 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:42:03.278191 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1543 12:42:03.285143 0 9 8 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
1544 12:42:03.288208 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 12:42:03.291468 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 12:42:03.298700 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 12:42:03.301611 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:42:03.305313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:42:03.309024 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:42:03.314890 0 10 4 | B1->B0 | 3333 3131 | 0 0 | (0 1) (0 1)
1551 12:42:03.318741 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1552 12:42:03.325816 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:42:03.328598 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:42:03.331419 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:42:03.334886 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:42:03.341314 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:42:03.344842 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:42:03.348174 0 11 4 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
1559 12:42:03.354668 0 11 8 | B1->B0 | 3939 4545 | 1 1 | (0 0) (0 0)
1560 12:42:03.357740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:42:03.361074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 12:42:03.367815 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 12:42:03.371042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:42:03.374477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:42:03.381096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:42:03.384345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1567 12:42:03.390915 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:42:03.394434 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:42:03.398009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:42:03.400757 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:42:03.407155 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:42:03.410210 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:42:03.413813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:42:03.419980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:42:03.424075 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:42:03.430371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:42:03.433643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:42:03.437295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:42:03.443257 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:42:03.446791 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:42:03.450550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:42:03.454010 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:42:03.460495 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1584 12:42:03.463690 Total UI for P1: 0, mck2ui 16
1585 12:42:03.466579 best dqsien dly found for B0: ( 0, 14, 6)
1586 12:42:03.469983 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 12:42:03.473453 Total UI for P1: 0, mck2ui 16
1588 12:42:03.476990 best dqsien dly found for B1: ( 0, 14, 8)
1589 12:42:03.479929 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1590 12:42:03.483425 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1591 12:42:03.483861
1592 12:42:03.486565 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 12:42:03.489992 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1594 12:42:03.493451 [Gating] SW calibration Done
1595 12:42:03.493988 ==
1596 12:42:03.496634 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 12:42:03.500590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 12:42:03.503415 ==
1599 12:42:03.503848 RX Vref Scan: 0
1600 12:42:03.504191
1601 12:42:03.506737 RX Vref 0 -> 0, step: 1
1602 12:42:03.507298
1603 12:42:03.510143 RX Delay -130 -> 252, step: 16
1604 12:42:03.513347 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1605 12:42:03.517138 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1606 12:42:03.520080 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 12:42:03.523563 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1608 12:42:03.529897 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1609 12:42:03.533152 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1610 12:42:03.536447 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1611 12:42:03.540042 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1612 12:42:03.543443 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1613 12:42:03.549871 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1614 12:42:03.553650 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1615 12:42:03.556991 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1616 12:42:03.560071 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1617 12:42:03.563061 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1618 12:42:03.569914 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1619 12:42:03.572727 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1620 12:42:03.573190 ==
1621 12:42:03.576213 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 12:42:03.579933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 12:42:03.580565 ==
1624 12:42:03.582725 DQS Delay:
1625 12:42:03.583305 DQS0 = 0, DQS1 = 0
1626 12:42:03.583867 DQM Delay:
1627 12:42:03.586382 DQM0 = 87, DQM1 = 78
1628 12:42:03.586876 DQ Delay:
1629 12:42:03.589612 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1630 12:42:03.592892 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1631 12:42:03.596202 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1632 12:42:03.599628 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1633 12:42:03.600074
1634 12:42:03.600566
1635 12:42:03.601041 ==
1636 12:42:03.602780 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 12:42:03.610053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 12:42:03.610478 ==
1639 12:42:03.610814
1640 12:42:03.611125
1641 12:42:03.611467 TX Vref Scan disable
1642 12:42:03.613315 == TX Byte 0 ==
1643 12:42:03.616465 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1644 12:42:03.623457 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1645 12:42:03.623884 == TX Byte 1 ==
1646 12:42:03.626500 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1647 12:42:03.633480 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1648 12:42:03.634059 ==
1649 12:42:03.636350 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 12:42:03.639475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 12:42:03.639923 ==
1652 12:42:03.649555 TX Vref=22, minBit 0, minWin=27, winSum=440
1653 12:42:03.656834 TX Vref=24, minBit 3, minWin=27, winSum=445
1654 12:42:03.660001 TX Vref=26, minBit 1, minWin=27, winSum=450
1655 12:42:03.662972 TX Vref=28, minBit 1, minWin=27, winSum=454
1656 12:42:03.666424 TX Vref=30, minBit 1, minWin=27, winSum=453
1657 12:42:03.669438 TX Vref=32, minBit 1, minWin=27, winSum=450
1658 12:42:03.676398 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
1659 12:42:03.676954
1660 12:42:03.679556 Final TX Range 1 Vref 28
1661 12:42:03.680001
1662 12:42:03.680342 ==
1663 12:42:03.683352 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 12:42:03.686501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 12:42:03.687073 ==
1666 12:42:03.687604
1667 12:42:03.688059
1668 12:42:03.689504 TX Vref Scan disable
1669 12:42:03.693381 == TX Byte 0 ==
1670 12:42:03.696082 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1671 12:42:03.699418 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1672 12:42:03.702960 == TX Byte 1 ==
1673 12:42:03.706644 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1674 12:42:03.709482 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1675 12:42:03.709936
1676 12:42:03.712609 [DATLAT]
1677 12:42:03.713167 Freq=800, CH1 RK0
1678 12:42:03.713657
1679 12:42:03.716610 DATLAT Default: 0xa
1680 12:42:03.717036 0, 0xFFFF, sum = 0
1681 12:42:03.720036 1, 0xFFFF, sum = 0
1682 12:42:03.720633 2, 0xFFFF, sum = 0
1683 12:42:03.722817 3, 0xFFFF, sum = 0
1684 12:42:03.723441 4, 0xFFFF, sum = 0
1685 12:42:03.726157 5, 0xFFFF, sum = 0
1686 12:42:03.726728 6, 0xFFFF, sum = 0
1687 12:42:03.729338 7, 0xFFFF, sum = 0
1688 12:42:03.729764 8, 0xFFFF, sum = 0
1689 12:42:03.732666 9, 0x0, sum = 1
1690 12:42:03.733218 10, 0x0, sum = 2
1691 12:42:03.735931 11, 0x0, sum = 3
1692 12:42:03.736370 12, 0x0, sum = 4
1693 12:42:03.739570 best_step = 10
1694 12:42:03.740005
1695 12:42:03.740344 ==
1696 12:42:03.742736 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 12:42:03.746006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 12:42:03.746735 ==
1699 12:42:03.747143 RX Vref Scan: 1
1700 12:42:03.749550
1701 12:42:03.749988 Set Vref Range= 32 -> 127
1702 12:42:03.750326
1703 12:42:03.752674 RX Vref 32 -> 127, step: 1
1704 12:42:03.753127
1705 12:42:03.755985 RX Delay -95 -> 252, step: 8
1706 12:42:03.756513
1707 12:42:03.759254 Set Vref, RX VrefLevel [Byte0]: 32
1708 12:42:03.762927 [Byte1]: 32
1709 12:42:03.763352
1710 12:42:03.765780 Set Vref, RX VrefLevel [Byte0]: 33
1711 12:42:03.769093 [Byte1]: 33
1712 12:42:03.769535
1713 12:42:03.772340 Set Vref, RX VrefLevel [Byte0]: 34
1714 12:42:03.776380 [Byte1]: 34
1715 12:42:03.780312
1716 12:42:03.780733 Set Vref, RX VrefLevel [Byte0]: 35
1717 12:42:03.783564 [Byte1]: 35
1718 12:42:03.787558
1719 12:42:03.787986 Set Vref, RX VrefLevel [Byte0]: 36
1720 12:42:03.790872 [Byte1]: 36
1721 12:42:03.795060
1722 12:42:03.795521 Set Vref, RX VrefLevel [Byte0]: 37
1723 12:42:03.798338 [Byte1]: 37
1724 12:42:03.802999
1725 12:42:03.803461 Set Vref, RX VrefLevel [Byte0]: 38
1726 12:42:03.806311 [Byte1]: 38
1727 12:42:03.810594
1728 12:42:03.811122 Set Vref, RX VrefLevel [Byte0]: 39
1729 12:42:03.813664 [Byte1]: 39
1730 12:42:03.818098
1731 12:42:03.818525 Set Vref, RX VrefLevel [Byte0]: 40
1732 12:42:03.821188 [Byte1]: 40
1733 12:42:03.826089
1734 12:42:03.826510 Set Vref, RX VrefLevel [Byte0]: 41
1735 12:42:03.829217 [Byte1]: 41
1736 12:42:03.833040
1737 12:42:03.833465 Set Vref, RX VrefLevel [Byte0]: 42
1738 12:42:03.836347 [Byte1]: 42
1739 12:42:03.841008
1740 12:42:03.841433 Set Vref, RX VrefLevel [Byte0]: 43
1741 12:42:03.843874 [Byte1]: 43
1742 12:42:03.848253
1743 12:42:03.848674 Set Vref, RX VrefLevel [Byte0]: 44
1744 12:42:03.851722 [Byte1]: 44
1745 12:42:03.855961
1746 12:42:03.856379 Set Vref, RX VrefLevel [Byte0]: 45
1747 12:42:03.859014 [Byte1]: 45
1748 12:42:03.863938
1749 12:42:03.864364 Set Vref, RX VrefLevel [Byte0]: 46
1750 12:42:03.866955 [Byte1]: 46
1751 12:42:03.871063
1752 12:42:03.871530 Set Vref, RX VrefLevel [Byte0]: 47
1753 12:42:03.874508 [Byte1]: 47
1754 12:42:03.879222
1755 12:42:03.879691 Set Vref, RX VrefLevel [Byte0]: 48
1756 12:42:03.881850 [Byte1]: 48
1757 12:42:03.886328
1758 12:42:03.886752 Set Vref, RX VrefLevel [Byte0]: 49
1759 12:42:03.889980 [Byte1]: 49
1760 12:42:03.893928
1761 12:42:03.894351 Set Vref, RX VrefLevel [Byte0]: 50
1762 12:42:03.897243 [Byte1]: 50
1763 12:42:03.901358
1764 12:42:03.901780 Set Vref, RX VrefLevel [Byte0]: 51
1765 12:42:03.905235 [Byte1]: 51
1766 12:42:03.909538
1767 12:42:03.910066 Set Vref, RX VrefLevel [Byte0]: 52
1768 12:42:03.912243 [Byte1]: 52
1769 12:42:03.916373
1770 12:42:03.916797 Set Vref, RX VrefLevel [Byte0]: 53
1771 12:42:03.920209 [Byte1]: 53
1772 12:42:03.924286
1773 12:42:03.924806 Set Vref, RX VrefLevel [Byte0]: 54
1774 12:42:03.928176 [Byte1]: 54
1775 12:42:03.931881
1776 12:42:03.932303 Set Vref, RX VrefLevel [Byte0]: 55
1777 12:42:03.935060 [Byte1]: 55
1778 12:42:03.940303
1779 12:42:03.940724 Set Vref, RX VrefLevel [Byte0]: 56
1780 12:42:03.942776 [Byte1]: 56
1781 12:42:03.947131
1782 12:42:03.951150 Set Vref, RX VrefLevel [Byte0]: 57
1783 12:42:03.954411 [Byte1]: 57
1784 12:42:03.954855
1785 12:42:03.957445 Set Vref, RX VrefLevel [Byte0]: 58
1786 12:42:03.960563 [Byte1]: 58
1787 12:42:03.961099
1788 12:42:03.963654 Set Vref, RX VrefLevel [Byte0]: 59
1789 12:42:03.966670 [Byte1]: 59
1790 12:42:03.967098
1791 12:42:03.970511 Set Vref, RX VrefLevel [Byte0]: 60
1792 12:42:03.973290 [Byte1]: 60
1793 12:42:03.977521
1794 12:42:03.978206 Set Vref, RX VrefLevel [Byte0]: 61
1795 12:42:03.980569 [Byte1]: 61
1796 12:42:03.985311
1797 12:42:03.985738 Set Vref, RX VrefLevel [Byte0]: 62
1798 12:42:03.988376 [Byte1]: 62
1799 12:42:03.992882
1800 12:42:03.993419 Set Vref, RX VrefLevel [Byte0]: 63
1801 12:42:03.995872 [Byte1]: 63
1802 12:42:04.000084
1803 12:42:04.000509 Set Vref, RX VrefLevel [Byte0]: 64
1804 12:42:04.003703 [Byte1]: 64
1805 12:42:04.008101
1806 12:42:04.008525 Set Vref, RX VrefLevel [Byte0]: 65
1807 12:42:04.011243 [Byte1]: 65
1808 12:42:04.016120
1809 12:42:04.016690 Set Vref, RX VrefLevel [Byte0]: 66
1810 12:42:04.018971 [Byte1]: 66
1811 12:42:04.023608
1812 12:42:04.024136 Set Vref, RX VrefLevel [Byte0]: 67
1813 12:42:04.026537 [Byte1]: 67
1814 12:42:04.030550
1815 12:42:04.030980 Set Vref, RX VrefLevel [Byte0]: 68
1816 12:42:04.034196 [Byte1]: 68
1817 12:42:04.038199
1818 12:42:04.038634 Set Vref, RX VrefLevel [Byte0]: 69
1819 12:42:04.041839 [Byte1]: 69
1820 12:42:04.045935
1821 12:42:04.046472 Set Vref, RX VrefLevel [Byte0]: 70
1822 12:42:04.049740 [Byte1]: 70
1823 12:42:04.053725
1824 12:42:04.054121 Set Vref, RX VrefLevel [Byte0]: 71
1825 12:42:04.057231 [Byte1]: 71
1826 12:42:04.061125
1827 12:42:04.061554 Set Vref, RX VrefLevel [Byte0]: 72
1828 12:42:04.064340 [Byte1]: 72
1829 12:42:04.068828
1830 12:42:04.069255 Set Vref, RX VrefLevel [Byte0]: 73
1831 12:42:04.071843 [Byte1]: 73
1832 12:42:04.077069
1833 12:42:04.077493 Set Vref, RX VrefLevel [Byte0]: 74
1834 12:42:04.079523 [Byte1]: 74
1835 12:42:04.084385
1836 12:42:04.084810 Set Vref, RX VrefLevel [Byte0]: 75
1837 12:42:04.087013 [Byte1]: 75
1838 12:42:04.091317
1839 12:42:04.091793 Final RX Vref Byte 0 = 61 to rank0
1840 12:42:04.095060 Final RX Vref Byte 1 = 52 to rank0
1841 12:42:04.098402 Final RX Vref Byte 0 = 61 to rank1
1842 12:42:04.102110 Final RX Vref Byte 1 = 52 to rank1==
1843 12:42:04.104928 Dram Type= 6, Freq= 0, CH_1, rank 0
1844 12:42:04.111401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 12:42:04.111845 ==
1846 12:42:04.112190 DQS Delay:
1847 12:42:04.112513 DQS0 = 0, DQS1 = 0
1848 12:42:04.114664 DQM Delay:
1849 12:42:04.115092 DQM0 = 86, DQM1 = 80
1850 12:42:04.118089 DQ Delay:
1851 12:42:04.121192 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1852 12:42:04.125327 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1853 12:42:04.128094 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1854 12:42:04.131806 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1855 12:42:04.132235
1856 12:42:04.132574
1857 12:42:04.137609 [DQSOSCAuto] RK0, (LSB)MR18= 0x172a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1858 12:42:04.140892 CH1 RK0: MR19=606, MR18=172A
1859 12:42:04.147689 CH1_RK0: MR19=0x606, MR18=0x172A, DQSOSC=399, MR23=63, INC=92, DEC=61
1860 12:42:04.148210
1861 12:42:04.151086 ----->DramcWriteLeveling(PI) begin...
1862 12:42:04.151555 ==
1863 12:42:04.154117 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 12:42:04.157492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 12:42:04.157927 ==
1866 12:42:04.161130 Write leveling (Byte 0): 27 => 27
1867 12:42:04.164110 Write leveling (Byte 1): 28 => 28
1868 12:42:04.167605 DramcWriteLeveling(PI) end<-----
1869 12:42:04.168037
1870 12:42:04.168380 ==
1871 12:42:04.170954 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 12:42:04.174316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 12:42:04.174747 ==
1874 12:42:04.177732 [Gating] SW mode calibration
1875 12:42:04.184345 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1876 12:42:04.191211 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1877 12:42:04.194030 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1878 12:42:04.200778 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1879 12:42:04.204056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1880 12:42:04.207327 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:42:04.211230 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:42:04.217494 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:42:04.220723 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:42:04.224395 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:42:04.231555 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:42:04.234540 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:42:04.237605 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:42:04.243762 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:42:04.247467 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:42:04.250871 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:42:04.257107 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:42:04.260551 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:42:04.263941 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1894 12:42:04.271086 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1895 12:42:04.273838 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:42:04.277062 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:42:04.283927 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:42:04.286973 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:42:04.290714 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:42:04.296781 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:42:04.300528 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:42:04.303874 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1903 12:42:04.310799 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
1904 12:42:04.313906 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:42:04.316909 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:42:04.323481 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:42:04.327333 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 12:42:04.330122 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 12:42:04.336967 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1910 12:42:04.340518 0 10 4 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
1911 12:42:04.343621 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1912 12:42:04.350070 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:42:04.354053 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:42:04.356702 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:42:04.360042 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:42:04.366419 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 12:42:04.370308 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 12:42:04.373877 0 11 4 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
1919 12:42:04.380546 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1920 12:42:04.383449 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:42:04.386713 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:42:04.393722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:42:04.396465 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:42:04.400101 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 12:42:04.406733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 12:42:04.410537 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1927 12:42:04.413718 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1928 12:42:04.419664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:42:04.423210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:42:04.426481 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:42:04.432970 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:42:04.436859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:42:04.439978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:42:04.446887 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:42:04.450029 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:42:04.453899 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:42:04.459801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:42:04.463650 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:42:04.466527 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:42:04.473043 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:42:04.476116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1942 12:42:04.479633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1943 12:42:04.486561 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 12:42:04.486996 Total UI for P1: 0, mck2ui 16
1945 12:42:04.489920 best dqsien dly found for B0: ( 0, 14, 2)
1946 12:42:04.493295 Total UI for P1: 0, mck2ui 16
1947 12:42:04.496776 best dqsien dly found for B1: ( 0, 14, 4)
1948 12:42:04.499756 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1949 12:42:04.506496 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1950 12:42:04.507022
1951 12:42:04.509523 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1952 12:42:04.513334 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1953 12:42:04.516546 [Gating] SW calibration Done
1954 12:42:04.516999 ==
1955 12:42:04.519671 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 12:42:04.523041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 12:42:04.523625 ==
1958 12:42:04.523976 RX Vref Scan: 0
1959 12:42:04.526360
1960 12:42:04.526886 RX Vref 0 -> 0, step: 1
1961 12:42:04.527227
1962 12:42:04.529931 RX Delay -130 -> 252, step: 16
1963 12:42:04.533094 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1964 12:42:04.536034 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1965 12:42:04.542692 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1966 12:42:04.546319 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1967 12:42:04.549941 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1968 12:42:04.552668 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1969 12:42:04.556435 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1970 12:42:04.563072 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1971 12:42:04.566282 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1972 12:42:04.569376 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1973 12:42:04.573358 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1974 12:42:04.576269 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1975 12:42:04.582866 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1976 12:42:04.586375 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1977 12:42:04.589847 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1978 12:42:04.592806 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1979 12:42:04.593340 ==
1980 12:42:04.596500 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:42:04.603022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:42:04.603594 ==
1983 12:42:04.603946 DQS Delay:
1984 12:42:04.606302 DQS0 = 0, DQS1 = 0
1985 12:42:04.606837 DQM Delay:
1986 12:42:04.607182 DQM0 = 83, DQM1 = 80
1987 12:42:04.609642 DQ Delay:
1988 12:42:04.612728 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1989 12:42:04.615654 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1990 12:42:04.619338 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1991 12:42:04.622540 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1992 12:42:04.623034
1993 12:42:04.623415
1994 12:42:04.623743 ==
1995 12:42:04.625638 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 12:42:04.629040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 12:42:04.629580 ==
1998 12:42:04.629931
1999 12:42:04.630251
2000 12:42:04.632679 TX Vref Scan disable
2001 12:42:04.636188 == TX Byte 0 ==
2002 12:42:04.639033 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2003 12:42:04.642407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2004 12:42:04.646039 == TX Byte 1 ==
2005 12:42:04.649231 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 12:42:04.652097 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 12:42:04.652536 ==
2008 12:42:04.655588 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 12:42:04.658811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 12:42:04.661977 ==
2011 12:42:04.673100 TX Vref=22, minBit 1, minWin=27, winSum=447
2012 12:42:04.676614 TX Vref=24, minBit 0, minWin=27, winSum=450
2013 12:42:04.680883 TX Vref=26, minBit 1, minWin=27, winSum=453
2014 12:42:04.682791 TX Vref=28, minBit 4, minWin=27, winSum=453
2015 12:42:04.686206 TX Vref=30, minBit 0, minWin=28, winSum=455
2016 12:42:04.693628 TX Vref=32, minBit 1, minWin=27, winSum=454
2017 12:42:04.697246 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
2018 12:42:04.697831
2019 12:42:04.699477 Final TX Range 1 Vref 30
2020 12:42:04.699905
2021 12:42:04.700243 ==
2022 12:42:04.703344 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 12:42:04.706691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 12:42:04.707260 ==
2025 12:42:04.707699
2026 12:42:04.709957
2027 12:42:04.710423 TX Vref Scan disable
2028 12:42:04.713487 == TX Byte 0 ==
2029 12:42:04.716659 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2030 12:42:04.723047 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2031 12:42:04.723653 == TX Byte 1 ==
2032 12:42:04.726327 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2033 12:42:04.729923 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2034 12:42:04.733267
2035 12:42:04.733790 [DATLAT]
2036 12:42:04.734128 Freq=800, CH1 RK1
2037 12:42:04.734444
2038 12:42:04.736572 DATLAT Default: 0xa
2039 12:42:04.737101 0, 0xFFFF, sum = 0
2040 12:42:04.740331 1, 0xFFFF, sum = 0
2041 12:42:04.740861 2, 0xFFFF, sum = 0
2042 12:42:04.743059 3, 0xFFFF, sum = 0
2043 12:42:04.743536 4, 0xFFFF, sum = 0
2044 12:42:04.746183 5, 0xFFFF, sum = 0
2045 12:42:04.750085 6, 0xFFFF, sum = 0
2046 12:42:04.750608 7, 0xFFFF, sum = 0
2047 12:42:04.753417 8, 0xFFFF, sum = 0
2048 12:42:04.753847 9, 0x0, sum = 1
2049 12:42:04.754189 10, 0x0, sum = 2
2050 12:42:04.756400 11, 0x0, sum = 3
2051 12:42:04.756855 12, 0x0, sum = 4
2052 12:42:04.759629 best_step = 10
2053 12:42:04.760047
2054 12:42:04.760381 ==
2055 12:42:04.763680 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 12:42:04.766607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 12:42:04.767342 ==
2058 12:42:04.769541 RX Vref Scan: 0
2059 12:42:04.769962
2060 12:42:04.770297 RX Vref 0 -> 0, step: 1
2061 12:42:04.770610
2062 12:42:04.773087 RX Delay -95 -> 252, step: 8
2063 12:42:04.779636 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2064 12:42:04.782745 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2065 12:42:04.786019 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2066 12:42:04.789837 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2067 12:42:04.792626 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2068 12:42:04.799450 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2069 12:42:04.803472 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2070 12:42:04.806123 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2071 12:42:04.809326 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2072 12:42:04.812804 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2073 12:42:04.819397 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2074 12:42:04.822418 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2075 12:42:04.826465 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2076 12:42:04.829544 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2077 12:42:04.835649 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2078 12:42:04.839044 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2079 12:42:04.839522 ==
2080 12:42:04.842267 Dram Type= 6, Freq= 0, CH_1, rank 1
2081 12:42:04.845581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2082 12:42:04.846012 ==
2083 12:42:04.849406 DQS Delay:
2084 12:42:04.849838 DQS0 = 0, DQS1 = 0
2085 12:42:04.850178 DQM Delay:
2086 12:42:04.852327 DQM0 = 86, DQM1 = 81
2087 12:42:04.852757 DQ Delay:
2088 12:42:04.855504 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2089 12:42:04.859241 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2090 12:42:04.862256 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2091 12:42:04.865840 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2092 12:42:04.866352
2093 12:42:04.866693
2094 12:42:04.875324 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2095 12:42:04.875952 CH1 RK1: MR19=606, MR18=203C
2096 12:42:04.882280 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2097 12:42:04.885497 [RxdqsGatingPostProcess] freq 800
2098 12:42:04.892487 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2099 12:42:04.895537 Pre-setting of DQS Precalculation
2100 12:42:04.898693 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2101 12:42:04.909275 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2102 12:42:04.915498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2103 12:42:04.916070
2104 12:42:04.916451
2105 12:42:04.919237 [Calibration Summary] 1600 Mbps
2106 12:42:04.919867 CH 0, Rank 0
2107 12:42:04.922156 SW Impedance : PASS
2108 12:42:04.922834 DUTY Scan : NO K
2109 12:42:04.925500 ZQ Calibration : PASS
2110 12:42:04.928729 Jitter Meter : NO K
2111 12:42:04.929202 CBT Training : PASS
2112 12:42:04.933140 Write leveling : PASS
2113 12:42:04.935554 RX DQS gating : PASS
2114 12:42:04.935989 RX DQ/DQS(RDDQC) : PASS
2115 12:42:04.939490 TX DQ/DQS : PASS
2116 12:42:04.939920 RX DATLAT : PASS
2117 12:42:04.942410 RX DQ/DQS(Engine): PASS
2118 12:42:04.945310 TX OE : NO K
2119 12:42:04.945844 All Pass.
2120 12:42:04.946194
2121 12:42:04.946511 CH 0, Rank 1
2122 12:42:04.948522 SW Impedance : PASS
2123 12:42:04.952192 DUTY Scan : NO K
2124 12:42:04.952626 ZQ Calibration : PASS
2125 12:42:04.955341 Jitter Meter : NO K
2126 12:42:04.958377 CBT Training : PASS
2127 12:42:04.958811 Write leveling : PASS
2128 12:42:04.961697 RX DQS gating : PASS
2129 12:42:04.965198 RX DQ/DQS(RDDQC) : PASS
2130 12:42:04.965626 TX DQ/DQS : PASS
2131 12:42:04.968115 RX DATLAT : PASS
2132 12:42:04.971446 RX DQ/DQS(Engine): PASS
2133 12:42:04.971883 TX OE : NO K
2134 12:42:04.974661 All Pass.
2135 12:42:04.975119
2136 12:42:04.975548 CH 1, Rank 0
2137 12:42:04.978989 SW Impedance : PASS
2138 12:42:04.979461 DUTY Scan : NO K
2139 12:42:04.981518 ZQ Calibration : PASS
2140 12:42:04.984572 Jitter Meter : NO K
2141 12:42:04.985134 CBT Training : PASS
2142 12:42:04.987795 Write leveling : PASS
2143 12:42:04.992255 RX DQS gating : PASS
2144 12:42:04.992683 RX DQ/DQS(RDDQC) : PASS
2145 12:42:04.995002 TX DQ/DQS : PASS
2146 12:42:04.998315 RX DATLAT : PASS
2147 12:42:04.998743 RX DQ/DQS(Engine): PASS
2148 12:42:05.002090 TX OE : NO K
2149 12:42:05.002527 All Pass.
2150 12:42:05.002868
2151 12:42:05.003186 CH 1, Rank 1
2152 12:42:05.004753 SW Impedance : PASS
2153 12:42:05.008210 DUTY Scan : NO K
2154 12:42:05.008641 ZQ Calibration : PASS
2155 12:42:05.011612 Jitter Meter : NO K
2156 12:42:05.015483 CBT Training : PASS
2157 12:42:05.015917 Write leveling : PASS
2158 12:42:05.017986 RX DQS gating : PASS
2159 12:42:05.021526 RX DQ/DQS(RDDQC) : PASS
2160 12:42:05.021957 TX DQ/DQS : PASS
2161 12:42:05.024809 RX DATLAT : PASS
2162 12:42:05.028076 RX DQ/DQS(Engine): PASS
2163 12:42:05.028532 TX OE : NO K
2164 12:42:05.031422 All Pass.
2165 12:42:05.031853
2166 12:42:05.032193 DramC Write-DBI off
2167 12:42:05.034826 PER_BANK_REFRESH: Hybrid Mode
2168 12:42:05.035258 TX_TRACKING: ON
2169 12:42:05.037886 [GetDramInforAfterCalByMRR] Vendor 6.
2170 12:42:05.045447 [GetDramInforAfterCalByMRR] Revision 606.
2171 12:42:05.048494 [GetDramInforAfterCalByMRR] Revision 2 0.
2172 12:42:05.048925 MR0 0x3b3b
2173 12:42:05.049265 MR8 0x5151
2174 12:42:05.051222 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 12:42:05.051688
2176 12:42:05.054799 MR0 0x3b3b
2177 12:42:05.055226 MR8 0x5151
2178 12:42:05.057763 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 12:42:05.058195
2180 12:42:05.068136 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2181 12:42:05.071195 [FAST_K] Save calibration result to emmc
2182 12:42:05.074959 [FAST_K] Save calibration result to emmc
2183 12:42:05.077779 dram_init: config_dvfs: 1
2184 12:42:05.081376 dramc_set_vcore_voltage set vcore to 662500
2185 12:42:05.084879 Read voltage for 1200, 2
2186 12:42:05.085321 Vio18 = 0
2187 12:42:05.085662 Vcore = 662500
2188 12:42:05.088167 Vdram = 0
2189 12:42:05.088651 Vddq = 0
2190 12:42:05.089000 Vmddr = 0
2191 12:42:05.095126 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2192 12:42:05.098040 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2193 12:42:05.101137 MEM_TYPE=3, freq_sel=15
2194 12:42:05.104919 sv_algorithm_assistance_LP4_1600
2195 12:42:05.107677 ============ PULL DRAM RESETB DOWN ============
2196 12:42:05.111400 ========== PULL DRAM RESETB DOWN end =========
2197 12:42:05.117540 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2198 12:42:05.121639 ===================================
2199 12:42:05.122175 LPDDR4 DRAM CONFIGURATION
2200 12:42:05.124149 ===================================
2201 12:42:05.127330 EX_ROW_EN[0] = 0x0
2202 12:42:05.130658 EX_ROW_EN[1] = 0x0
2203 12:42:05.131086 LP4Y_EN = 0x0
2204 12:42:05.134487 WORK_FSP = 0x0
2205 12:42:05.134915 WL = 0x4
2206 12:42:05.137559 RL = 0x4
2207 12:42:05.138006 BL = 0x2
2208 12:42:05.140795 RPST = 0x0
2209 12:42:05.141226 RD_PRE = 0x0
2210 12:42:05.144405 WR_PRE = 0x1
2211 12:42:05.144837 WR_PST = 0x0
2212 12:42:05.147235 DBI_WR = 0x0
2213 12:42:05.147849 DBI_RD = 0x0
2214 12:42:05.150857 OTF = 0x1
2215 12:42:05.154080 ===================================
2216 12:42:05.157221 ===================================
2217 12:42:05.157651 ANA top config
2218 12:42:05.160765 ===================================
2219 12:42:05.163961 DLL_ASYNC_EN = 0
2220 12:42:05.167524 ALL_SLAVE_EN = 0
2221 12:42:05.171208 NEW_RANK_MODE = 1
2222 12:42:05.171705 DLL_IDLE_MODE = 1
2223 12:42:05.174242 LP45_APHY_COMB_EN = 1
2224 12:42:05.177613 TX_ODT_DIS = 1
2225 12:42:05.181152 NEW_8X_MODE = 1
2226 12:42:05.183547 ===================================
2227 12:42:05.187105 ===================================
2228 12:42:05.190701 data_rate = 2400
2229 12:42:05.191227 CKR = 1
2230 12:42:05.193870 DQ_P2S_RATIO = 8
2231 12:42:05.197304 ===================================
2232 12:42:05.200531 CA_P2S_RATIO = 8
2233 12:42:05.203702 DQ_CA_OPEN = 0
2234 12:42:05.207720 DQ_SEMI_OPEN = 0
2235 12:42:05.210127 CA_SEMI_OPEN = 0
2236 12:42:05.213665 CA_FULL_RATE = 0
2237 12:42:05.214203 DQ_CKDIV4_EN = 0
2238 12:42:05.217058 CA_CKDIV4_EN = 0
2239 12:42:05.220274 CA_PREDIV_EN = 0
2240 12:42:05.223431 PH8_DLY = 17
2241 12:42:05.226899 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2242 12:42:05.230263 DQ_AAMCK_DIV = 4
2243 12:42:05.230693 CA_AAMCK_DIV = 4
2244 12:42:05.233242 CA_ADMCK_DIV = 4
2245 12:42:05.236515 DQ_TRACK_CA_EN = 0
2246 12:42:05.239847 CA_PICK = 1200
2247 12:42:05.243453 CA_MCKIO = 1200
2248 12:42:05.246708 MCKIO_SEMI = 0
2249 12:42:05.249850 PLL_FREQ = 2366
2250 12:42:05.252811 DQ_UI_PI_RATIO = 32
2251 12:42:05.253239 CA_UI_PI_RATIO = 0
2252 12:42:05.256437 ===================================
2253 12:42:05.259833 ===================================
2254 12:42:05.263032 memory_type:LPDDR4
2255 12:42:05.265904 GP_NUM : 10
2256 12:42:05.266333 SRAM_EN : 1
2257 12:42:05.269586 MD32_EN : 0
2258 12:42:05.272912 ===================================
2259 12:42:05.276081 [ANA_INIT] >>>>>>>>>>>>>>
2260 12:42:05.276512 <<<<<< [CONFIGURE PHASE]: ANA_TX
2261 12:42:05.282869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2262 12:42:05.286349 ===================================
2263 12:42:05.286780 data_rate = 2400,PCW = 0X5b00
2264 12:42:05.290063 ===================================
2265 12:42:05.292712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2266 12:42:05.299543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 12:42:05.306406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 12:42:05.309329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2269 12:42:05.312983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2270 12:42:05.316175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2271 12:42:05.319473 [ANA_INIT] flow start
2272 12:42:05.319906 [ANA_INIT] PLL >>>>>>>>
2273 12:42:05.322685 [ANA_INIT] PLL <<<<<<<<
2274 12:42:05.326074 [ANA_INIT] MIDPI >>>>>>>>
2275 12:42:05.329402 [ANA_INIT] MIDPI <<<<<<<<
2276 12:42:05.329832 [ANA_INIT] DLL >>>>>>>>
2277 12:42:05.332576 [ANA_INIT] DLL <<<<<<<<
2278 12:42:05.336207 [ANA_INIT] flow end
2279 12:42:05.339815 ============ LP4 DIFF to SE enter ============
2280 12:42:05.342830 ============ LP4 DIFF to SE exit ============
2281 12:42:05.346498 [ANA_INIT] <<<<<<<<<<<<<
2282 12:42:05.349948 [Flow] Enable top DCM control >>>>>
2283 12:42:05.352328 [Flow] Enable top DCM control <<<<<
2284 12:42:05.355932 Enable DLL master slave shuffle
2285 12:42:05.358767 ==============================================================
2286 12:42:05.362751 Gating Mode config
2287 12:42:05.366532 ==============================================================
2288 12:42:05.369258 Config description:
2289 12:42:05.378939 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2290 12:42:05.385570 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2291 12:42:05.388892 SELPH_MODE 0: By rank 1: By Phase
2292 12:42:05.395982 ==============================================================
2293 12:42:05.398760 GAT_TRACK_EN = 1
2294 12:42:05.402602 RX_GATING_MODE = 2
2295 12:42:05.405289 RX_GATING_TRACK_MODE = 2
2296 12:42:05.408811 SELPH_MODE = 1
2297 12:42:05.412368 PICG_EARLY_EN = 1
2298 12:42:05.412798 VALID_LAT_VALUE = 1
2299 12:42:05.418903 ==============================================================
2300 12:42:05.423150 Enter into Gating configuration >>>>
2301 12:42:05.426375 Exit from Gating configuration <<<<
2302 12:42:05.429045 Enter into DVFS_PRE_config >>>>>
2303 12:42:05.439224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2304 12:42:05.442457 Exit from DVFS_PRE_config <<<<<
2305 12:42:05.445593 Enter into PICG configuration >>>>
2306 12:42:05.449067 Exit from PICG configuration <<<<
2307 12:42:05.452137 [RX_INPUT] configuration >>>>>
2308 12:42:05.455794 [RX_INPUT] configuration <<<<<
2309 12:42:05.462041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2310 12:42:05.465195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2311 12:42:05.471702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 12:42:05.478591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 12:42:05.485216 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 12:42:05.492039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 12:42:05.495477 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2316 12:42:05.498162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2317 12:42:05.501486 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2318 12:42:05.508157 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2319 12:42:05.511584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2320 12:42:05.515264 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 12:42:05.518684 ===================================
2322 12:42:05.521729 LPDDR4 DRAM CONFIGURATION
2323 12:42:05.524776 ===================================
2324 12:42:05.525259 EX_ROW_EN[0] = 0x0
2325 12:42:05.528458 EX_ROW_EN[1] = 0x0
2326 12:42:05.531472 LP4Y_EN = 0x0
2327 12:42:05.531907 WORK_FSP = 0x0
2328 12:42:05.534730 WL = 0x4
2329 12:42:05.535161 RL = 0x4
2330 12:42:05.538921 BL = 0x2
2331 12:42:05.539394 RPST = 0x0
2332 12:42:05.541251 RD_PRE = 0x0
2333 12:42:05.541709 WR_PRE = 0x1
2334 12:42:05.544859 WR_PST = 0x0
2335 12:42:05.545391 DBI_WR = 0x0
2336 12:42:05.548172 DBI_RD = 0x0
2337 12:42:05.548607 OTF = 0x1
2338 12:42:05.551518 ===================================
2339 12:42:05.555119 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2340 12:42:05.561965 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2341 12:42:05.565511 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2342 12:42:05.567711 ===================================
2343 12:42:05.570968 LPDDR4 DRAM CONFIGURATION
2344 12:42:05.575006 ===================================
2345 12:42:05.575514 EX_ROW_EN[0] = 0x10
2346 12:42:05.577988 EX_ROW_EN[1] = 0x0
2347 12:42:05.578421 LP4Y_EN = 0x0
2348 12:42:05.581296 WORK_FSP = 0x0
2349 12:42:05.581804 WL = 0x4
2350 12:42:05.584752 RL = 0x4
2351 12:42:05.588062 BL = 0x2
2352 12:42:05.588494 RPST = 0x0
2353 12:42:05.591251 RD_PRE = 0x0
2354 12:42:05.591717 WR_PRE = 0x1
2355 12:42:05.595127 WR_PST = 0x0
2356 12:42:05.595722 DBI_WR = 0x0
2357 12:42:05.598188 DBI_RD = 0x0
2358 12:42:05.598714 OTF = 0x1
2359 12:42:05.601116 ===================================
2360 12:42:05.608016 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2361 12:42:05.608449 ==
2362 12:42:05.610782 Dram Type= 6, Freq= 0, CH_0, rank 0
2363 12:42:05.614221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 12:42:05.614651 ==
2365 12:42:05.617636 [Duty_Offset_Calibration]
2366 12:42:05.620830 B0:2 B1:0 CA:4
2367 12:42:05.621258
2368 12:42:05.624657 [DutyScan_Calibration_Flow] k_type=0
2369 12:42:05.631967
2370 12:42:05.632455 ==CLK 0==
2371 12:42:05.635408 Final CLK duty delay cell = -4
2372 12:42:05.638875 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2373 12:42:05.641974 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2374 12:42:05.645160 [-4] AVG Duty = 4937%(X100)
2375 12:42:05.645681
2376 12:42:05.648811 CH0 CLK Duty spec in!! Max-Min= 187%
2377 12:42:05.651324 [DutyScan_Calibration_Flow] ====Done====
2378 12:42:05.651804
2379 12:42:05.654922 [DutyScan_Calibration_Flow] k_type=1
2380 12:42:05.671478
2381 12:42:05.672040 ==DQS 0 ==
2382 12:42:05.674401 Final DQS duty delay cell = 0
2383 12:42:05.677773 [0] MAX Duty = 5156%(X100), DQS PI = 14
2384 12:42:05.681366 [0] MIN Duty = 5093%(X100), DQS PI = 2
2385 12:42:05.681913 [0] AVG Duty = 5124%(X100)
2386 12:42:05.684759
2387 12:42:05.685182 ==DQS 1 ==
2388 12:42:05.687402 Final DQS duty delay cell = 0
2389 12:42:05.690620 [0] MAX Duty = 5125%(X100), DQS PI = 50
2390 12:42:05.694169 [0] MIN Duty = 5000%(X100), DQS PI = 0
2391 12:42:05.694251 [0] AVG Duty = 5062%(X100)
2392 12:42:05.697173
2393 12:42:05.700721 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2394 12:42:05.700807
2395 12:42:05.704124 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2396 12:42:05.707245 [DutyScan_Calibration_Flow] ====Done====
2397 12:42:05.707328
2398 12:42:05.710432 [DutyScan_Calibration_Flow] k_type=3
2399 12:42:05.728255
2400 12:42:05.728679 ==DQM 0 ==
2401 12:42:05.730572 Final DQM duty delay cell = 0
2402 12:42:05.734056 [0] MAX Duty = 5094%(X100), DQS PI = 20
2403 12:42:05.737388 [0] MIN Duty = 4844%(X100), DQS PI = 52
2404 12:42:05.740668 [0] AVG Duty = 4969%(X100)
2405 12:42:05.741092
2406 12:42:05.741424 ==DQM 1 ==
2407 12:42:05.744292 Final DQM duty delay cell = 0
2408 12:42:05.747353 [0] MAX Duty = 5000%(X100), DQS PI = 6
2409 12:42:05.750669 [0] MIN Duty = 4875%(X100), DQS PI = 20
2410 12:42:05.754066 [0] AVG Duty = 4937%(X100)
2411 12:42:05.754491
2412 12:42:05.757410 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2413 12:42:05.757836
2414 12:42:05.760687 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2415 12:42:05.764585 [DutyScan_Calibration_Flow] ====Done====
2416 12:42:05.765010
2417 12:42:05.767316 [DutyScan_Calibration_Flow] k_type=2
2418 12:42:05.784079
2419 12:42:05.784507 ==DQ 0 ==
2420 12:42:05.787602 Final DQ duty delay cell = 0
2421 12:42:05.790694 [0] MAX Duty = 5125%(X100), DQS PI = 18
2422 12:42:05.793855 [0] MIN Duty = 4969%(X100), DQS PI = 52
2423 12:42:05.794346 [0] AVG Duty = 5047%(X100)
2424 12:42:05.797138
2425 12:42:05.797606 ==DQ 1 ==
2426 12:42:05.800893 Final DQ duty delay cell = 0
2427 12:42:05.803912 [0] MAX Duty = 5156%(X100), DQS PI = 6
2428 12:42:05.807204 [0] MIN Duty = 4938%(X100), DQS PI = 14
2429 12:42:05.807840 [0] AVG Duty = 5047%(X100)
2430 12:42:05.808208
2431 12:42:05.810153 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2432 12:42:05.813644
2433 12:42:05.817037 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2434 12:42:05.820830 [DutyScan_Calibration_Flow] ====Done====
2435 12:42:05.821251 ==
2436 12:42:05.823557 Dram Type= 6, Freq= 0, CH_1, rank 0
2437 12:42:05.827088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2438 12:42:05.827561 ==
2439 12:42:05.830144 [Duty_Offset_Calibration]
2440 12:42:05.830573 B0:0 B1:-1 CA:3
2441 12:42:05.830916
2442 12:42:05.833568 [DutyScan_Calibration_Flow] k_type=0
2443 12:42:05.843521
2444 12:42:05.843953 ==CLK 0==
2445 12:42:05.846513 Final CLK duty delay cell = -4
2446 12:42:05.849522 [-4] MAX Duty = 5031%(X100), DQS PI = 12
2447 12:42:05.852716 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2448 12:42:05.856004 [-4] AVG Duty = 4953%(X100)
2449 12:42:05.856237
2450 12:42:05.859306 CH1 CLK Duty spec in!! Max-Min= 155%
2451 12:42:05.862607 [DutyScan_Calibration_Flow] ====Done====
2452 12:42:05.862839
2453 12:42:05.865903 [DutyScan_Calibration_Flow] k_type=1
2454 12:42:05.882234
2455 12:42:05.882467 ==DQS 0 ==
2456 12:42:05.885487 Final DQS duty delay cell = 0
2457 12:42:05.889101 [0] MAX Duty = 5124%(X100), DQS PI = 0
2458 12:42:05.892158 [0] MIN Duty = 4907%(X100), DQS PI = 6
2459 12:42:05.892392 [0] AVG Duty = 5015%(X100)
2460 12:42:05.895705
2461 12:42:05.895957 ==DQS 1 ==
2462 12:42:05.898738 Final DQS duty delay cell = 0
2463 12:42:05.902135 [0] MAX Duty = 5156%(X100), DQS PI = 0
2464 12:42:05.905694 [0] MIN Duty = 5000%(X100), DQS PI = 56
2465 12:42:05.905925 [0] AVG Duty = 5078%(X100)
2466 12:42:05.908822
2467 12:42:05.912237 CH1 DQS 0 Duty spec in!! Max-Min= 217%
2468 12:42:05.912491
2469 12:42:05.916316 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2470 12:42:05.919272 [DutyScan_Calibration_Flow] ====Done====
2471 12:42:05.919606
2472 12:42:05.922166 [DutyScan_Calibration_Flow] k_type=3
2473 12:42:05.938786
2474 12:42:05.939020 ==DQM 0 ==
2475 12:42:05.942212 Final DQM duty delay cell = 0
2476 12:42:05.945498 [0] MAX Duty = 5031%(X100), DQS PI = 60
2477 12:42:05.949548 [0] MIN Duty = 4813%(X100), DQS PI = 6
2478 12:42:05.951940 [0] AVG Duty = 4922%(X100)
2479 12:42:05.952173
2480 12:42:05.952355 ==DQM 1 ==
2481 12:42:05.955386 Final DQM duty delay cell = 0
2482 12:42:05.958896 [0] MAX Duty = 4969%(X100), DQS PI = 0
2483 12:42:05.961740 [0] MIN Duty = 4844%(X100), DQS PI = 30
2484 12:42:05.965237 [0] AVG Duty = 4906%(X100)
2485 12:42:05.965469
2486 12:42:05.968330 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2487 12:42:05.968563
2488 12:42:05.971643 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2489 12:42:05.975263 [DutyScan_Calibration_Flow] ====Done====
2490 12:42:05.975550
2491 12:42:05.978134 [DutyScan_Calibration_Flow] k_type=2
2492 12:42:05.993886
2493 12:42:05.993971 ==DQ 0 ==
2494 12:42:05.997297 Final DQ duty delay cell = -4
2495 12:42:06.000711 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2496 12:42:06.004305 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2497 12:42:06.007542 [-4] AVG Duty = 4953%(X100)
2498 12:42:06.007626
2499 12:42:06.007692 ==DQ 1 ==
2500 12:42:06.011673 Final DQ duty delay cell = 0
2501 12:42:06.014177 [0] MAX Duty = 5031%(X100), DQS PI = 2
2502 12:42:06.018197 [0] MIN Duty = 4876%(X100), DQS PI = 30
2503 12:42:06.018280 [0] AVG Duty = 4953%(X100)
2504 12:42:06.020670
2505 12:42:06.024225 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2506 12:42:06.024309
2507 12:42:06.027251 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2508 12:42:06.030606 [DutyScan_Calibration_Flow] ====Done====
2509 12:42:06.034186 nWR fixed to 30
2510 12:42:06.034270 [ModeRegInit_LP4] CH0 RK0
2511 12:42:06.037711 [ModeRegInit_LP4] CH0 RK1
2512 12:42:06.040591 [ModeRegInit_LP4] CH1 RK0
2513 12:42:06.044644 [ModeRegInit_LP4] CH1 RK1
2514 12:42:06.044728 match AC timing 7
2515 12:42:06.050576 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2516 12:42:06.054186 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2517 12:42:06.057478 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2518 12:42:06.064224 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2519 12:42:06.067771 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2520 12:42:06.067856 ==
2521 12:42:06.071189 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 12:42:06.074043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 12:42:06.074131 ==
2524 12:42:06.080604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2525 12:42:06.087686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2526 12:42:06.094192 [CA 0] Center 39 (9~70) winsize 62
2527 12:42:06.097429 [CA 1] Center 38 (8~69) winsize 62
2528 12:42:06.101183 [CA 2] Center 35 (5~66) winsize 62
2529 12:42:06.104421 [CA 3] Center 35 (5~66) winsize 62
2530 12:42:06.107805 [CA 4] Center 34 (4~65) winsize 62
2531 12:42:06.110721 [CA 5] Center 33 (3~63) winsize 61
2532 12:42:06.110805
2533 12:42:06.114939 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2534 12:42:06.115023
2535 12:42:06.117633 [CATrainingPosCal] consider 1 rank data
2536 12:42:06.120805 u2DelayCellTimex100 = 270/100 ps
2537 12:42:06.124587 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 12:42:06.131096 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2539 12:42:06.134460 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 12:42:06.137719 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 12:42:06.140632 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2542 12:42:06.143963 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2543 12:42:06.144046
2544 12:42:06.147138 CA PerBit enable=1, Macro0, CA PI delay=33
2545 12:42:06.147221
2546 12:42:06.150419 [CBTSetCACLKResult] CA Dly = 33
2547 12:42:06.150503 CS Dly: 7 (0~38)
2548 12:42:06.154004 ==
2549 12:42:06.157142 Dram Type= 6, Freq= 0, CH_0, rank 1
2550 12:42:06.160938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 12:42:06.161022 ==
2552 12:42:06.163817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2553 12:42:06.170777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2554 12:42:06.180168 [CA 0] Center 39 (9~70) winsize 62
2555 12:42:06.183666 [CA 1] Center 39 (9~70) winsize 62
2556 12:42:06.187122 [CA 2] Center 35 (5~66) winsize 62
2557 12:42:06.189780 [CA 3] Center 35 (5~66) winsize 62
2558 12:42:06.193771 [CA 4] Center 34 (4~65) winsize 62
2559 12:42:06.196590 [CA 5] Center 33 (3~64) winsize 62
2560 12:42:06.196674
2561 12:42:06.199905 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2562 12:42:06.199989
2563 12:42:06.203038 [CATrainingPosCal] consider 2 rank data
2564 12:42:06.206372 u2DelayCellTimex100 = 270/100 ps
2565 12:42:06.209729 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2566 12:42:06.216697 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2567 12:42:06.219990 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2568 12:42:06.223593 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 12:42:06.226841 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2570 12:42:06.230260 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2571 12:42:06.230347
2572 12:42:06.233757 CA PerBit enable=1, Macro0, CA PI delay=33
2573 12:42:06.233840
2574 12:42:06.236650 [CBTSetCACLKResult] CA Dly = 33
2575 12:42:06.236733 CS Dly: 8 (0~41)
2576 12:42:06.236799
2577 12:42:06.243307 ----->DramcWriteLeveling(PI) begin...
2578 12:42:06.243431 ==
2579 12:42:06.246482 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 12:42:06.249908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 12:42:06.249992 ==
2582 12:42:06.253072 Write leveling (Byte 0): 29 => 29
2583 12:42:06.256502 Write leveling (Byte 1): 27 => 27
2584 12:42:06.259386 DramcWriteLeveling(PI) end<-----
2585 12:42:06.259485
2586 12:42:06.259550 ==
2587 12:42:06.262687 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 12:42:06.266403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 12:42:06.266487 ==
2590 12:42:06.269348 [Gating] SW mode calibration
2591 12:42:06.276237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2592 12:42:06.283026 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2593 12:42:06.286434 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2594 12:42:06.289354 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2595 12:42:06.297054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 12:42:06.299727 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 12:42:06.303127 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 12:42:06.309221 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 12:42:06.312886 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2600 12:42:06.316294 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2601 12:42:06.322610 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2602 12:42:06.326007 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2603 12:42:06.329085 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 12:42:06.335820 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 12:42:06.338797 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 12:42:06.342492 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 12:42:06.349169 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2608 12:42:06.352302 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2609 12:42:06.355896 1 1 0 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
2610 12:42:06.362125 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2611 12:42:06.366039 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 12:42:06.369140 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 12:42:06.372346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 12:42:06.378862 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:42:06.382038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 12:42:06.385841 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2617 12:42:06.392051 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 12:42:06.395855 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:42:06.398628 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:42:06.405425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:42:06.408827 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:42:06.411990 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:42:06.418344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:42:06.422181 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:42:06.425771 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:42:06.431716 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:42:06.435282 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:42:06.439076 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:42:06.445057 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:42:06.449056 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:42:06.451628 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 12:42:06.458644 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2633 12:42:06.461863 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2634 12:42:06.464882 Total UI for P1: 0, mck2ui 16
2635 12:42:06.468521 best dqsien dly found for B0: ( 1, 3, 26)
2636 12:42:06.472211 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2637 12:42:06.478975 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 12:42:06.479059 Total UI for P1: 0, mck2ui 16
2639 12:42:06.482194 best dqsien dly found for B1: ( 1, 4, 2)
2640 12:42:06.488679 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2641 12:42:06.492053 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2642 12:42:06.492157
2643 12:42:06.494985 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2644 12:42:06.498667 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2645 12:42:06.501927 [Gating] SW calibration Done
2646 12:42:06.502037 ==
2647 12:42:06.504834 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 12:42:06.509232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 12:42:06.509324 ==
2650 12:42:06.511345 RX Vref Scan: 0
2651 12:42:06.511448
2652 12:42:06.511512 RX Vref 0 -> 0, step: 1
2653 12:42:06.511573
2654 12:42:06.514631 RX Delay -40 -> 252, step: 8
2655 12:42:06.518392 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2656 12:42:06.525104 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2657 12:42:06.528305 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2658 12:42:06.531832 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2659 12:42:06.534878 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2660 12:42:06.538325 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2661 12:42:06.544889 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2662 12:42:06.548103 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2663 12:42:06.551227 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2664 12:42:06.554431 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2665 12:42:06.557897 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2666 12:42:06.564514 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2667 12:42:06.567952 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2668 12:42:06.571500 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2669 12:42:06.574575 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2670 12:42:06.577572 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2671 12:42:06.581096 ==
2672 12:42:06.581172 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:42:06.588173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:42:06.588278 ==
2675 12:42:06.588370 DQS Delay:
2676 12:42:06.590948 DQS0 = 0, DQS1 = 0
2677 12:42:06.591048 DQM Delay:
2678 12:42:06.594484 DQM0 = 118, DQM1 = 107
2679 12:42:06.594559 DQ Delay:
2680 12:42:06.597926 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2681 12:42:06.601180 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2682 12:42:06.604521 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2683 12:42:06.607665 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2684 12:42:06.607742
2685 12:42:06.607808
2686 12:42:06.607867 ==
2687 12:42:06.611243 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 12:42:06.617229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 12:42:06.617308 ==
2690 12:42:06.617389
2691 12:42:06.617487
2692 12:42:06.617582 TX Vref Scan disable
2693 12:42:06.621007 == TX Byte 0 ==
2694 12:42:06.624197 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2695 12:42:06.631791 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2696 12:42:06.631871 == TX Byte 1 ==
2697 12:42:06.634413 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2698 12:42:06.641191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2699 12:42:06.641269 ==
2700 12:42:06.644125 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 12:42:06.647230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 12:42:06.647307 ==
2703 12:42:06.658777 TX Vref=22, minBit 2, minWin=25, winSum=409
2704 12:42:06.662177 TX Vref=24, minBit 5, minWin=25, winSum=415
2705 12:42:06.666027 TX Vref=26, minBit 5, minWin=25, winSum=418
2706 12:42:06.669122 TX Vref=28, minBit 1, minWin=26, winSum=427
2707 12:42:06.672178 TX Vref=30, minBit 10, minWin=26, winSum=430
2708 12:42:06.678462 TX Vref=32, minBit 2, minWin=26, winSum=428
2709 12:42:06.681840 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 30
2710 12:42:06.681918
2711 12:42:06.685621 Final TX Range 1 Vref 30
2712 12:42:06.685701
2713 12:42:06.685782 ==
2714 12:42:06.688668 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 12:42:06.691949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 12:42:06.695316 ==
2717 12:42:06.695444
2718 12:42:06.695525
2719 12:42:06.695606 TX Vref Scan disable
2720 12:42:06.698736 == TX Byte 0 ==
2721 12:42:06.701910 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2722 12:42:06.708683 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2723 12:42:06.708763 == TX Byte 1 ==
2724 12:42:06.712241 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2725 12:42:06.718972 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2726 12:42:06.719078
2727 12:42:06.719179 [DATLAT]
2728 12:42:06.719277 Freq=1200, CH0 RK0
2729 12:42:06.719399
2730 12:42:06.722050 DATLAT Default: 0xd
2731 12:42:06.725140 0, 0xFFFF, sum = 0
2732 12:42:06.725242 1, 0xFFFF, sum = 0
2733 12:42:06.728318 2, 0xFFFF, sum = 0
2734 12:42:06.728397 3, 0xFFFF, sum = 0
2735 12:42:06.732100 4, 0xFFFF, sum = 0
2736 12:42:06.732175 5, 0xFFFF, sum = 0
2737 12:42:06.736174 6, 0xFFFF, sum = 0
2738 12:42:06.736252 7, 0xFFFF, sum = 0
2739 12:42:06.738731 8, 0xFFFF, sum = 0
2740 12:42:06.738832 9, 0xFFFF, sum = 0
2741 12:42:06.742074 10, 0xFFFF, sum = 0
2742 12:42:06.742173 11, 0xFFFF, sum = 0
2743 12:42:06.745152 12, 0x0, sum = 1
2744 12:42:06.745226 13, 0x0, sum = 2
2745 12:42:06.748749 14, 0x0, sum = 3
2746 12:42:06.748822 15, 0x0, sum = 4
2747 12:42:06.751888 best_step = 13
2748 12:42:06.751986
2749 12:42:06.752066 ==
2750 12:42:06.755429 Dram Type= 6, Freq= 0, CH_0, rank 0
2751 12:42:06.758264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2752 12:42:06.758366 ==
2753 12:42:06.758464 RX Vref Scan: 1
2754 12:42:06.758560
2755 12:42:06.761936 Set Vref Range= 32 -> 127
2756 12:42:06.762036
2757 12:42:06.764794 RX Vref 32 -> 127, step: 1
2758 12:42:06.764871
2759 12:42:06.768004 RX Delay -21 -> 252, step: 4
2760 12:42:06.768078
2761 12:42:06.771873 Set Vref, RX VrefLevel [Byte0]: 32
2762 12:42:06.774907 [Byte1]: 32
2763 12:42:06.775006
2764 12:42:06.778244 Set Vref, RX VrefLevel [Byte0]: 33
2765 12:42:06.781137 [Byte1]: 33
2766 12:42:06.785355
2767 12:42:06.785476 Set Vref, RX VrefLevel [Byte0]: 34
2768 12:42:06.788159 [Byte1]: 34
2769 12:42:06.793522
2770 12:42:06.793635 Set Vref, RX VrefLevel [Byte0]: 35
2771 12:42:06.796162 [Byte1]: 35
2772 12:42:06.800895
2773 12:42:06.801033 Set Vref, RX VrefLevel [Byte0]: 36
2774 12:42:06.804145 [Byte1]: 36
2775 12:42:06.809410
2776 12:42:06.809507 Set Vref, RX VrefLevel [Byte0]: 37
2777 12:42:06.812395 [Byte1]: 37
2778 12:42:06.817107
2779 12:42:06.817205 Set Vref, RX VrefLevel [Byte0]: 38
2780 12:42:06.820038 [Byte1]: 38
2781 12:42:06.824840
2782 12:42:06.824939 Set Vref, RX VrefLevel [Byte0]: 39
2783 12:42:06.828005 [Byte1]: 39
2784 12:42:06.832722
2785 12:42:06.832793 Set Vref, RX VrefLevel [Byte0]: 40
2786 12:42:06.836439 [Byte1]: 40
2787 12:42:06.840768
2788 12:42:06.840865 Set Vref, RX VrefLevel [Byte0]: 41
2789 12:42:06.844455 [Byte1]: 41
2790 12:42:06.848329
2791 12:42:06.848407 Set Vref, RX VrefLevel [Byte0]: 42
2792 12:42:06.851703 [Byte1]: 42
2793 12:42:06.856441
2794 12:42:06.856523 Set Vref, RX VrefLevel [Byte0]: 43
2795 12:42:06.861015 [Byte1]: 43
2796 12:42:06.864490
2797 12:42:06.864577 Set Vref, RX VrefLevel [Byte0]: 44
2798 12:42:06.867991 [Byte1]: 44
2799 12:42:06.872682
2800 12:42:06.872805 Set Vref, RX VrefLevel [Byte0]: 45
2801 12:42:06.875998 [Byte1]: 45
2802 12:42:06.880285
2803 12:42:06.880409 Set Vref, RX VrefLevel [Byte0]: 46
2804 12:42:06.884201 [Byte1]: 46
2805 12:42:06.888468
2806 12:42:06.888608 Set Vref, RX VrefLevel [Byte0]: 47
2807 12:42:06.891548 [Byte1]: 47
2808 12:42:06.896443
2809 12:42:06.896621 Set Vref, RX VrefLevel [Byte0]: 48
2810 12:42:06.899309 [Byte1]: 48
2811 12:42:06.904042
2812 12:42:06.904262 Set Vref, RX VrefLevel [Byte0]: 49
2813 12:42:06.907416 [Byte1]: 49
2814 12:42:06.912708
2815 12:42:06.912997 Set Vref, RX VrefLevel [Byte0]: 50
2816 12:42:06.915634 [Byte1]: 50
2817 12:42:06.920246
2818 12:42:06.920706 Set Vref, RX VrefLevel [Byte0]: 51
2819 12:42:06.923664 [Byte1]: 51
2820 12:42:06.928062
2821 12:42:06.928490 Set Vref, RX VrefLevel [Byte0]: 52
2822 12:42:06.931428 [Byte1]: 52
2823 12:42:06.936254
2824 12:42:06.936682 Set Vref, RX VrefLevel [Byte0]: 53
2825 12:42:06.939185 [Byte1]: 53
2826 12:42:06.943485
2827 12:42:06.943569 Set Vref, RX VrefLevel [Byte0]: 54
2828 12:42:06.946956 [Byte1]: 54
2829 12:42:06.951295
2830 12:42:06.951420 Set Vref, RX VrefLevel [Byte0]: 55
2831 12:42:06.954763 [Byte1]: 55
2832 12:42:06.959587
2833 12:42:06.959669 Set Vref, RX VrefLevel [Byte0]: 56
2834 12:42:06.963126 [Byte1]: 56
2835 12:42:06.967231
2836 12:42:06.967314 Set Vref, RX VrefLevel [Byte0]: 57
2837 12:42:06.970815 [Byte1]: 57
2838 12:42:06.975260
2839 12:42:06.975368 Set Vref, RX VrefLevel [Byte0]: 58
2840 12:42:06.978829 [Byte1]: 58
2841 12:42:06.983440
2842 12:42:06.983538 Set Vref, RX VrefLevel [Byte0]: 59
2843 12:42:06.986442 [Byte1]: 59
2844 12:42:06.991330
2845 12:42:06.991460 Set Vref, RX VrefLevel [Byte0]: 60
2846 12:42:06.994727 [Byte1]: 60
2847 12:42:06.998966
2848 12:42:06.999048 Set Vref, RX VrefLevel [Byte0]: 61
2849 12:42:07.002234 [Byte1]: 61
2850 12:42:07.006868
2851 12:42:07.006951 Set Vref, RX VrefLevel [Byte0]: 62
2852 12:42:07.010442 [Byte1]: 62
2853 12:42:07.015000
2854 12:42:07.015084 Set Vref, RX VrefLevel [Byte0]: 63
2855 12:42:07.018548 [Byte1]: 63
2856 12:42:07.023024
2857 12:42:07.023108 Set Vref, RX VrefLevel [Byte0]: 64
2858 12:42:07.026029 [Byte1]: 64
2859 12:42:07.030859
2860 12:42:07.030942 Set Vref, RX VrefLevel [Byte0]: 65
2861 12:42:07.033856 [Byte1]: 65
2862 12:42:07.038780
2863 12:42:07.038878 Set Vref, RX VrefLevel [Byte0]: 66
2864 12:42:07.042093 [Byte1]: 66
2865 12:42:07.046419
2866 12:42:07.046528 Set Vref, RX VrefLevel [Byte0]: 67
2867 12:42:07.049837 [Byte1]: 67
2868 12:42:07.054459
2869 12:42:07.054542 Set Vref, RX VrefLevel [Byte0]: 68
2870 12:42:07.058002 [Byte1]: 68
2871 12:42:07.062670
2872 12:42:07.062753 Final RX Vref Byte 0 = 51 to rank0
2873 12:42:07.065996 Final RX Vref Byte 1 = 58 to rank0
2874 12:42:07.068964 Final RX Vref Byte 0 = 51 to rank1
2875 12:42:07.072872 Final RX Vref Byte 1 = 58 to rank1==
2876 12:42:07.076277 Dram Type= 6, Freq= 0, CH_0, rank 0
2877 12:42:07.082484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 12:42:07.082568 ==
2879 12:42:07.082635 DQS Delay:
2880 12:42:07.082697 DQS0 = 0, DQS1 = 0
2881 12:42:07.085562 DQM Delay:
2882 12:42:07.085645 DQM0 = 117, DQM1 = 105
2883 12:42:07.089194 DQ Delay:
2884 12:42:07.092720 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2885 12:42:07.095765 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2886 12:42:07.098897 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2887 12:42:07.102459 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2888 12:42:07.102543
2889 12:42:07.102609
2890 12:42:07.109060 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2891 12:42:07.112319 CH0 RK0: MR19=403, MR18=1FD
2892 12:42:07.118865 CH0_RK0: MR19=0x403, MR18=0x1FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2893 12:42:07.118949
2894 12:42:07.121982 ----->DramcWriteLeveling(PI) begin...
2895 12:42:07.122067 ==
2896 12:42:07.125794 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 12:42:07.128645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 12:42:07.131809 ==
2899 12:42:07.131892 Write leveling (Byte 0): 31 => 31
2900 12:42:07.135243 Write leveling (Byte 1): 27 => 27
2901 12:42:07.138784 DramcWriteLeveling(PI) end<-----
2902 12:42:07.138867
2903 12:42:07.138932 ==
2904 12:42:07.142361 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 12:42:07.148643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 12:42:07.148727 ==
2907 12:42:07.148833 [Gating] SW mode calibration
2908 12:42:07.159092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2909 12:42:07.161800 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2910 12:42:07.168673 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2911 12:42:07.172146 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2912 12:42:07.175579 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 12:42:07.181790 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 12:42:07.185325 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 12:42:07.189410 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 12:42:07.191948 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2917 12:42:07.198399 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2918 12:42:07.201930 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2919 12:42:07.205299 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2920 12:42:07.211837 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 12:42:07.215643 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 12:42:07.218440 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 12:42:07.225195 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 12:42:07.228680 1 0 24 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
2925 12:42:07.231944 1 0 28 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
2926 12:42:07.238711 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
2927 12:42:07.242514 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 12:42:07.245786 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 12:42:07.251885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 12:42:07.255337 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 12:42:07.259073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 12:42:07.265555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2933 12:42:07.268362 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2934 12:42:07.272309 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2935 12:42:07.278780 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:42:07.282146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:42:07.285888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:42:07.291881 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:42:07.295962 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:42:07.299009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:42:07.305289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:42:07.308633 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:42:07.311613 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:42:07.318578 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:42:07.322169 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:42:07.324947 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:42:07.332170 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:42:07.334934 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2949 12:42:07.338491 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2950 12:42:07.341617 Total UI for P1: 0, mck2ui 16
2951 12:42:07.345227 best dqsien dly found for B0: ( 1, 3, 24)
2952 12:42:07.348160 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2953 12:42:07.354908 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 12:42:07.358304 Total UI for P1: 0, mck2ui 16
2955 12:42:07.361665 best dqsien dly found for B1: ( 1, 4, 0)
2956 12:42:07.364744 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2957 12:42:07.368777 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2958 12:42:07.369206
2959 12:42:07.371484 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2960 12:42:07.374800 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2961 12:42:07.378082 [Gating] SW calibration Done
2962 12:42:07.378513 ==
2963 12:42:07.381313 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 12:42:07.384684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 12:42:07.385114 ==
2966 12:42:07.388277 RX Vref Scan: 0
2967 12:42:07.388737
2968 12:42:07.389088 RX Vref 0 -> 0, step: 1
2969 12:42:07.391465
2970 12:42:07.391899 RX Delay -40 -> 252, step: 8
2971 12:42:07.397859 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2972 12:42:07.401317 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2973 12:42:07.404618 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2974 12:42:07.407831 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2975 12:42:07.411059 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2976 12:42:07.418243 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2977 12:42:07.421518 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2978 12:42:07.424951 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2979 12:42:07.427888 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2980 12:42:07.430888 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2981 12:42:07.437576 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2982 12:42:07.441041 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2983 12:42:07.444236 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2984 12:42:07.447467 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2985 12:42:07.450719 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2986 12:42:07.457749 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2987 12:42:07.458276 ==
2988 12:42:07.460918 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 12:42:07.464298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 12:42:07.464730 ==
2991 12:42:07.465069 DQS Delay:
2992 12:42:07.468377 DQS0 = 0, DQS1 = 0
2993 12:42:07.468908 DQM Delay:
2994 12:42:07.471502 DQM0 = 115, DQM1 = 110
2995 12:42:07.472033 DQ Delay:
2996 12:42:07.474690 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2997 12:42:07.477956 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2998 12:42:07.480636 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2999 12:42:07.484250 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
3000 12:42:07.484803
3001 12:42:07.485147
3002 12:42:07.487703 ==
3003 12:42:07.490394 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 12:42:07.493684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 12:42:07.494121 ==
3006 12:42:07.494457
3007 12:42:07.494773
3008 12:42:07.497352 TX Vref Scan disable
3009 12:42:07.497781 == TX Byte 0 ==
3010 12:42:07.504131 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3011 12:42:07.507192 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3012 12:42:07.507672 == TX Byte 1 ==
3013 12:42:07.513824 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3014 12:42:07.516876 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3015 12:42:07.517306 ==
3016 12:42:07.520590 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 12:42:07.523486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 12:42:07.523921 ==
3019 12:42:07.536025 TX Vref=22, minBit 5, minWin=25, winSum=414
3020 12:42:07.539671 TX Vref=24, minBit 1, minWin=25, winSum=417
3021 12:42:07.542944 TX Vref=26, minBit 0, minWin=26, winSum=420
3022 12:42:07.545885 TX Vref=28, minBit 10, minWin=25, winSum=423
3023 12:42:07.549251 TX Vref=30, minBit 14, minWin=25, winSum=424
3024 12:42:07.556018 TX Vref=32, minBit 5, minWin=25, winSum=422
3025 12:42:07.559121 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 26
3026 12:42:07.559588
3027 12:42:07.563066 Final TX Range 1 Vref 26
3028 12:42:07.563547
3029 12:42:07.563896 ==
3030 12:42:07.566076 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 12:42:07.569089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 12:42:07.572680 ==
3033 12:42:07.573109
3034 12:42:07.573447
3035 12:42:07.573761 TX Vref Scan disable
3036 12:42:07.576015 == TX Byte 0 ==
3037 12:42:07.579471 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3038 12:42:07.586178 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3039 12:42:07.586614 == TX Byte 1 ==
3040 12:42:07.589195 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3041 12:42:07.596348 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3042 12:42:07.596779
3043 12:42:07.597117 [DATLAT]
3044 12:42:07.597431 Freq=1200, CH0 RK1
3045 12:42:07.597737
3046 12:42:07.599497 DATLAT Default: 0xd
3047 12:42:07.599928 0, 0xFFFF, sum = 0
3048 12:42:07.602531 1, 0xFFFF, sum = 0
3049 12:42:07.602966 2, 0xFFFF, sum = 0
3050 12:42:07.606113 3, 0xFFFF, sum = 0
3051 12:42:07.609594 4, 0xFFFF, sum = 0
3052 12:42:07.610029 5, 0xFFFF, sum = 0
3053 12:42:07.612810 6, 0xFFFF, sum = 0
3054 12:42:07.613245 7, 0xFFFF, sum = 0
3055 12:42:07.615769 8, 0xFFFF, sum = 0
3056 12:42:07.616203 9, 0xFFFF, sum = 0
3057 12:42:07.619077 10, 0xFFFF, sum = 0
3058 12:42:07.619557 11, 0xFFFF, sum = 0
3059 12:42:07.622171 12, 0x0, sum = 1
3060 12:42:07.622675 13, 0x0, sum = 2
3061 12:42:07.626467 14, 0x0, sum = 3
3062 12:42:07.626904 15, 0x0, sum = 4
3063 12:42:07.629226 best_step = 13
3064 12:42:07.629654
3065 12:42:07.629992 ==
3066 12:42:07.632174 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 12:42:07.635816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 12:42:07.636250 ==
3069 12:42:07.636588 RX Vref Scan: 0
3070 12:42:07.636907
3071 12:42:07.639487 RX Vref 0 -> 0, step: 1
3072 12:42:07.639916
3073 12:42:07.642751 RX Delay -21 -> 252, step: 4
3074 12:42:07.648380 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3075 12:42:07.652147 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3076 12:42:07.655201 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3077 12:42:07.658544 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3078 12:42:07.661945 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3079 12:42:07.665018 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3080 12:42:07.671704 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3081 12:42:07.674998 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3082 12:42:07.678506 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3083 12:42:07.681928 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3084 12:42:07.684954 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3085 12:42:07.692053 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3086 12:42:07.695003 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3087 12:42:07.698569 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3088 12:42:07.701710 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3089 12:42:07.704952 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3090 12:42:07.708478 ==
3091 12:42:07.711758 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 12:42:07.715480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 12:42:07.715563 ==
3094 12:42:07.715628 DQS Delay:
3095 12:42:07.718335 DQS0 = 0, DQS1 = 0
3096 12:42:07.718402 DQM Delay:
3097 12:42:07.721522 DQM0 = 115, DQM1 = 106
3098 12:42:07.721600 DQ Delay:
3099 12:42:07.725224 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3100 12:42:07.728607 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3101 12:42:07.731701 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3102 12:42:07.735372 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3103 12:42:07.735468
3104 12:42:07.735543
3105 12:42:07.745352 [DQSOSCAuto] RK1, (LSB)MR18= 0x2ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3106 12:42:07.745482 CH0 RK1: MR19=403, MR18=2FF
3107 12:42:07.751746 CH0_RK1: MR19=0x403, MR18=0x2FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3108 12:42:07.755189 [RxdqsGatingPostProcess] freq 1200
3109 12:42:07.761340 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 12:42:07.764699 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 12:42:07.768564 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 12:42:07.771293 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 12:42:07.774593 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 12:42:07.778815 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 12:42:07.781583 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 12:42:07.784804 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 12:42:07.785212 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 12:42:07.788036 Pre-setting of DQS Precalculation
3119 12:42:07.794745 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 12:42:07.795273 ==
3121 12:42:07.797976 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 12:42:07.801388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 12:42:07.801844 ==
3124 12:42:07.808164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 12:42:07.814923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3126 12:42:07.822137 [CA 0] Center 38 (8~68) winsize 61
3127 12:42:07.826389 [CA 1] Center 37 (7~68) winsize 62
3128 12:42:07.828835 [CA 2] Center 35 (5~65) winsize 61
3129 12:42:07.832461 [CA 3] Center 34 (4~64) winsize 61
3130 12:42:07.835102 [CA 4] Center 34 (4~65) winsize 62
3131 12:42:07.839096 [CA 5] Center 33 (3~63) winsize 61
3132 12:42:07.839629
3133 12:42:07.842540 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3134 12:42:07.843220
3135 12:42:07.845565 [CATrainingPosCal] consider 1 rank data
3136 12:42:07.848390 u2DelayCellTimex100 = 270/100 ps
3137 12:42:07.852689 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3138 12:42:07.859261 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 12:42:07.862051 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3140 12:42:07.865554 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 12:42:07.869175 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3142 12:42:07.871552 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3143 12:42:07.872149
3144 12:42:07.875628 CA PerBit enable=1, Macro0, CA PI delay=33
3145 12:42:07.876174
3146 12:42:07.878676 [CBTSetCACLKResult] CA Dly = 33
3147 12:42:07.879178 CS Dly: 5 (0~36)
3148 12:42:07.882064 ==
3149 12:42:07.885183 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 12:42:07.888518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 12:42:07.888914 ==
3152 12:42:07.891497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 12:42:07.898979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 12:42:07.907978 [CA 0] Center 37 (7~68) winsize 62
3155 12:42:07.910908 [CA 1] Center 38 (8~68) winsize 61
3156 12:42:07.914521 [CA 2] Center 35 (5~65) winsize 61
3157 12:42:07.918157 [CA 3] Center 33 (3~64) winsize 62
3158 12:42:07.921105 [CA 4] Center 33 (3~64) winsize 62
3159 12:42:07.924189 [CA 5] Center 34 (4~64) winsize 61
3160 12:42:07.924827
3161 12:42:07.927534 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3162 12:42:07.927970
3163 12:42:07.931461 [CATrainingPosCal] consider 2 rank data
3164 12:42:07.934634 u2DelayCellTimex100 = 270/100 ps
3165 12:42:07.938108 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3166 12:42:07.944419 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3167 12:42:07.947519 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3168 12:42:07.950877 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 12:42:07.954394 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 12:42:07.957567 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3171 12:42:07.957989
3172 12:42:07.962197 CA PerBit enable=1, Macro0, CA PI delay=33
3173 12:42:07.962617
3174 12:42:07.964332 [CBTSetCACLKResult] CA Dly = 33
3175 12:42:07.964754 CS Dly: 6 (0~39)
3176 12:42:07.965086
3177 12:42:07.971093 ----->DramcWriteLeveling(PI) begin...
3178 12:42:07.971669 ==
3179 12:42:07.974137 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 12:42:07.977412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 12:42:07.977838 ==
3182 12:42:07.980915 Write leveling (Byte 0): 25 => 25
3183 12:42:07.984619 Write leveling (Byte 1): 28 => 28
3184 12:42:07.987053 DramcWriteLeveling(PI) end<-----
3185 12:42:07.987541
3186 12:42:07.988045 ==
3187 12:42:07.991173 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 12:42:07.994163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 12:42:07.994589 ==
3190 12:42:07.996985 [Gating] SW mode calibration
3191 12:42:08.003661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 12:42:08.010410 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 12:42:08.013888 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 12:42:08.017119 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 12:42:08.023984 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 12:42:08.027104 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 12:42:08.030140 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 12:42:08.036819 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 12:42:08.040495 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3200 12:42:08.043211 0 15 28 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (1 0)
3201 12:42:08.050527 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 12:42:08.053376 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 12:42:08.056817 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 12:42:08.063842 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 12:42:08.066790 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 12:42:08.070226 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 12:42:08.076525 1 0 24 | B1->B0 | 2424 2f2f | 0 0 | (1 1) (0 0)
3208 12:42:08.080226 1 0 28 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
3209 12:42:08.083277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 12:42:08.090165 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 12:42:08.093205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 12:42:08.097035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 12:42:08.100099 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 12:42:08.106790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 12:42:08.109718 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:42:08.113260 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 12:42:08.119616 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:42:08.123085 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:42:08.126322 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:42:08.133021 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:42:08.136679 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:42:08.139544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:42:08.146269 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:42:08.149861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:42:08.153323 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:42:08.159980 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:42:08.163194 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:42:08.166567 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:42:08.173230 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:42:08.176595 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:42:08.179501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3232 12:42:08.186436 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3233 12:42:08.189186 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 12:42:08.193083 Total UI for P1: 0, mck2ui 16
3235 12:42:08.196190 best dqsien dly found for B0: ( 1, 3, 26)
3236 12:42:08.199353 Total UI for P1: 0, mck2ui 16
3237 12:42:08.202627 best dqsien dly found for B1: ( 1, 3, 28)
3238 12:42:08.206682 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3239 12:42:08.209160 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3240 12:42:08.209589
3241 12:42:08.212904 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3242 12:42:08.216062 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3243 12:42:08.219489 [Gating] SW calibration Done
3244 12:42:08.219923 ==
3245 12:42:08.222510 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 12:42:08.225970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 12:42:08.229444 ==
3248 12:42:08.229874 RX Vref Scan: 0
3249 12:42:08.230213
3250 12:42:08.232731 RX Vref 0 -> 0, step: 1
3251 12:42:08.233160
3252 12:42:08.233499 RX Delay -40 -> 252, step: 8
3253 12:42:08.240045 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3254 12:42:08.242833 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3255 12:42:08.245760 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3256 12:42:08.249130 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3257 12:42:08.252483 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3258 12:42:08.259201 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3259 12:42:08.262492 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3260 12:42:08.265712 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3261 12:42:08.269657 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3262 12:42:08.272369 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3263 12:42:08.279349 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3264 12:42:08.282489 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3265 12:42:08.285758 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3266 12:42:08.289186 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3267 12:42:08.295685 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3268 12:42:08.299326 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3269 12:42:08.299807 ==
3270 12:42:08.302802 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:42:08.306001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:42:08.306434 ==
3273 12:42:08.306774 DQS Delay:
3274 12:42:08.309175 DQS0 = 0, DQS1 = 0
3275 12:42:08.309601 DQM Delay:
3276 12:42:08.312560 DQM0 = 114, DQM1 = 112
3277 12:42:08.312991 DQ Delay:
3278 12:42:08.315541 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =115
3279 12:42:08.319099 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3280 12:42:08.322767 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3281 12:42:08.329195 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3282 12:42:08.329625
3283 12:42:08.329961
3284 12:42:08.330273 ==
3285 12:42:08.332901 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 12:42:08.335778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 12:42:08.336210 ==
3288 12:42:08.336551
3289 12:42:08.336865
3290 12:42:08.339314 TX Vref Scan disable
3291 12:42:08.339768 == TX Byte 0 ==
3292 12:42:08.345352 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3293 12:42:08.348988 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3294 12:42:08.349418 == TX Byte 1 ==
3295 12:42:08.356228 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3296 12:42:08.358685 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3297 12:42:08.359117 ==
3298 12:42:08.361793 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:42:08.365181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:42:08.365613 ==
3301 12:42:08.377998 TX Vref=22, minBit 2, minWin=25, winSum=410
3302 12:42:08.381324 TX Vref=24, minBit 3, minWin=25, winSum=419
3303 12:42:08.384774 TX Vref=26, minBit 6, minWin=25, winSum=424
3304 12:42:08.388046 TX Vref=28, minBit 9, minWin=25, winSum=429
3305 12:42:08.391091 TX Vref=30, minBit 0, minWin=26, winSum=432
3306 12:42:08.398208 TX Vref=32, minBit 0, minWin=26, winSum=430
3307 12:42:08.401187 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
3308 12:42:08.401774
3309 12:42:08.405217 Final TX Range 1 Vref 30
3310 12:42:08.405688
3311 12:42:08.406029 ==
3312 12:42:08.407920 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 12:42:08.411340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 12:42:08.411898 ==
3315 12:42:08.414452
3316 12:42:08.414893
3317 12:42:08.415235 TX Vref Scan disable
3318 12:42:08.417503 == TX Byte 0 ==
3319 12:42:08.421810 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3320 12:42:08.427702 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3321 12:42:08.428150 == TX Byte 1 ==
3322 12:42:08.430663 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3323 12:42:08.437354 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3324 12:42:08.437828
3325 12:42:08.438194 [DATLAT]
3326 12:42:08.438556 Freq=1200, CH1 RK0
3327 12:42:08.438942
3328 12:42:08.440705 DATLAT Default: 0xd
3329 12:42:08.441151 0, 0xFFFF, sum = 0
3330 12:42:08.444524 1, 0xFFFF, sum = 0
3331 12:42:08.445115 2, 0xFFFF, sum = 0
3332 12:42:08.448295 3, 0xFFFF, sum = 0
3333 12:42:08.451008 4, 0xFFFF, sum = 0
3334 12:42:08.451594 5, 0xFFFF, sum = 0
3335 12:42:08.454633 6, 0xFFFF, sum = 0
3336 12:42:08.455226 7, 0xFFFF, sum = 0
3337 12:42:08.457601 8, 0xFFFF, sum = 0
3338 12:42:08.458101 9, 0xFFFF, sum = 0
3339 12:42:08.461051 10, 0xFFFF, sum = 0
3340 12:42:08.461561 11, 0xFFFF, sum = 0
3341 12:42:08.464439 12, 0x0, sum = 1
3342 12:42:08.464920 13, 0x0, sum = 2
3343 12:42:08.467609 14, 0x0, sum = 3
3344 12:42:08.468068 15, 0x0, sum = 4
3345 12:42:08.468519 best_step = 13
3346 12:42:08.470838
3347 12:42:08.471277 ==
3348 12:42:08.474367 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 12:42:08.477567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 12:42:08.478064 ==
3351 12:42:08.478588 RX Vref Scan: 1
3352 12:42:08.479065
3353 12:42:08.480693 Set Vref Range= 32 -> 127
3354 12:42:08.481198
3355 12:42:08.484168 RX Vref 32 -> 127, step: 1
3356 12:42:08.484705
3357 12:42:08.488001 RX Delay -13 -> 252, step: 4
3358 12:42:08.488492
3359 12:42:08.490659 Set Vref, RX VrefLevel [Byte0]: 32
3360 12:42:08.493909 [Byte1]: 32
3361 12:42:08.494490
3362 12:42:08.498376 Set Vref, RX VrefLevel [Byte0]: 33
3363 12:42:08.500531 [Byte1]: 33
3364 12:42:08.504023
3365 12:42:08.504306 Set Vref, RX VrefLevel [Byte0]: 34
3366 12:42:08.507909 [Byte1]: 34
3367 12:42:08.511614
3368 12:42:08.511782 Set Vref, RX VrefLevel [Byte0]: 35
3369 12:42:08.514833 [Byte1]: 35
3370 12:42:08.519517
3371 12:42:08.519647 Set Vref, RX VrefLevel [Byte0]: 36
3372 12:42:08.522571 [Byte1]: 36
3373 12:42:08.527727
3374 12:42:08.527859 Set Vref, RX VrefLevel [Byte0]: 37
3375 12:42:08.530795 [Byte1]: 37
3376 12:42:08.535086
3377 12:42:08.535244 Set Vref, RX VrefLevel [Byte0]: 38
3378 12:42:08.538634 [Byte1]: 38
3379 12:42:08.543133
3380 12:42:08.543293 Set Vref, RX VrefLevel [Byte0]: 39
3381 12:42:08.546312 [Byte1]: 39
3382 12:42:08.551088
3383 12:42:08.551261 Set Vref, RX VrefLevel [Byte0]: 40
3384 12:42:08.554273 [Byte1]: 40
3385 12:42:08.558993
3386 12:42:08.559136 Set Vref, RX VrefLevel [Byte0]: 41
3387 12:42:08.562675 [Byte1]: 41
3388 12:42:08.567477
3389 12:42:08.567702 Set Vref, RX VrefLevel [Byte0]: 42
3390 12:42:08.570120 [Byte1]: 42
3391 12:42:08.575566
3392 12:42:08.576019 Set Vref, RX VrefLevel [Byte0]: 43
3393 12:42:08.578277 [Byte1]: 43
3394 12:42:08.583327
3395 12:42:08.583892 Set Vref, RX VrefLevel [Byte0]: 44
3396 12:42:08.586204 [Byte1]: 44
3397 12:42:08.591137
3398 12:42:08.591619 Set Vref, RX VrefLevel [Byte0]: 45
3399 12:42:08.594132 [Byte1]: 45
3400 12:42:08.598612
3401 12:42:08.599130 Set Vref, RX VrefLevel [Byte0]: 46
3402 12:42:08.601953 [Byte1]: 46
3403 12:42:08.606967
3404 12:42:08.607490 Set Vref, RX VrefLevel [Byte0]: 47
3405 12:42:08.609971 [Byte1]: 47
3406 12:42:08.614634
3407 12:42:08.615197 Set Vref, RX VrefLevel [Byte0]: 48
3408 12:42:08.618050 [Byte1]: 48
3409 12:42:08.622703
3410 12:42:08.623276 Set Vref, RX VrefLevel [Byte0]: 49
3411 12:42:08.625650 [Byte1]: 49
3412 12:42:08.630856
3413 12:42:08.631465 Set Vref, RX VrefLevel [Byte0]: 50
3414 12:42:08.633685 [Byte1]: 50
3415 12:42:08.638744
3416 12:42:08.639161 Set Vref, RX VrefLevel [Byte0]: 51
3417 12:42:08.641447 [Byte1]: 51
3418 12:42:08.646275
3419 12:42:08.646803 Set Vref, RX VrefLevel [Byte0]: 52
3420 12:42:08.649408 [Byte1]: 52
3421 12:42:08.653630
3422 12:42:08.654104 Set Vref, RX VrefLevel [Byte0]: 53
3423 12:42:08.657030 [Byte1]: 53
3424 12:42:08.662132
3425 12:42:08.662714 Set Vref, RX VrefLevel [Byte0]: 54
3426 12:42:08.665246 [Byte1]: 54
3427 12:42:08.669676
3428 12:42:08.670213 Set Vref, RX VrefLevel [Byte0]: 55
3429 12:42:08.673304 [Byte1]: 55
3430 12:42:08.677421
3431 12:42:08.677907 Set Vref, RX VrefLevel [Byte0]: 56
3432 12:42:08.680914 [Byte1]: 56
3433 12:42:08.685563
3434 12:42:08.686116 Set Vref, RX VrefLevel [Byte0]: 57
3435 12:42:08.688587 [Byte1]: 57
3436 12:42:08.693247
3437 12:42:08.693675 Set Vref, RX VrefLevel [Byte0]: 58
3438 12:42:08.696304 [Byte1]: 58
3439 12:42:08.701297
3440 12:42:08.701726 Set Vref, RX VrefLevel [Byte0]: 59
3441 12:42:08.705120 [Byte1]: 59
3442 12:42:08.709061
3443 12:42:08.709487 Set Vref, RX VrefLevel [Byte0]: 60
3444 12:42:08.712594 [Byte1]: 60
3445 12:42:08.717250
3446 12:42:08.717678 Set Vref, RX VrefLevel [Byte0]: 61
3447 12:42:08.720149 [Byte1]: 61
3448 12:42:08.725084
3449 12:42:08.725508 Set Vref, RX VrefLevel [Byte0]: 62
3450 12:42:08.729090 [Byte1]: 62
3451 12:42:08.732646
3452 12:42:08.733194 Set Vref, RX VrefLevel [Byte0]: 63
3453 12:42:08.736060 [Byte1]: 63
3454 12:42:08.740500
3455 12:42:08.741032 Set Vref, RX VrefLevel [Byte0]: 64
3456 12:42:08.744423 [Byte1]: 64
3457 12:42:08.749125
3458 12:42:08.749672 Set Vref, RX VrefLevel [Byte0]: 65
3459 12:42:08.751745 [Byte1]: 65
3460 12:42:08.757352
3461 12:42:08.757778 Final RX Vref Byte 0 = 47 to rank0
3462 12:42:08.760889 Final RX Vref Byte 1 = 51 to rank0
3463 12:42:08.762934 Final RX Vref Byte 0 = 47 to rank1
3464 12:42:08.766053 Final RX Vref Byte 1 = 51 to rank1==
3465 12:42:08.769620 Dram Type= 6, Freq= 0, CH_1, rank 0
3466 12:42:08.776203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 12:42:08.776643 ==
3468 12:42:08.777016 DQS Delay:
3469 12:42:08.777335 DQS0 = 0, DQS1 = 0
3470 12:42:08.779458 DQM Delay:
3471 12:42:08.779920 DQM0 = 115, DQM1 = 112
3472 12:42:08.782474 DQ Delay:
3473 12:42:08.785851 DQ0 =122, DQ1 =110, DQ2 =106, DQ3 =116
3474 12:42:08.789322 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3475 12:42:08.792951 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3476 12:42:08.796301 DQ12 =118, DQ13 =120, DQ14 =118, DQ15 =120
3477 12:42:08.796897
3478 12:42:08.797524
3479 12:42:08.806268 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3480 12:42:08.806704 CH1 RK0: MR19=304, MR18=F501
3481 12:42:08.812932 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3482 12:42:08.813361
3483 12:42:08.816369 ----->DramcWriteLeveling(PI) begin...
3484 12:42:08.816805 ==
3485 12:42:08.820152 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 12:42:08.823439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 12:42:08.826740 ==
3488 12:42:08.827273 Write leveling (Byte 0): 26 => 26
3489 12:42:08.829218 Write leveling (Byte 1): 30 => 30
3490 12:42:08.833227 DramcWriteLeveling(PI) end<-----
3491 12:42:08.833756
3492 12:42:08.834099 ==
3493 12:42:08.835967 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 12:42:08.843015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 12:42:08.843607 ==
3496 12:42:08.846281 [Gating] SW mode calibration
3497 12:42:08.852612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3498 12:42:08.856036 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3499 12:42:08.862672 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 12:42:08.865761 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 12:42:08.869257 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 12:42:08.875709 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 12:42:08.879595 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 12:42:08.882705 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3505 12:42:08.889456 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
3506 12:42:08.892698 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3507 12:42:08.895897 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 12:42:08.902122 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 12:42:08.905435 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 12:42:08.908833 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 12:42:08.915307 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 12:42:08.919066 1 0 20 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3513 12:42:08.922208 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3514 12:42:08.928612 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3515 12:42:08.931929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 12:42:08.935406 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 12:42:08.942062 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 12:42:08.945289 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 12:42:08.948135 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 12:42:08.955069 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:42:08.958429 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3522 12:42:08.961329 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3523 12:42:08.968431 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:42:08.972059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:42:08.975316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:42:08.981933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:42:08.984431 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:42:08.987989 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:42:08.994369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:42:08.997841 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:42:09.000984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:42:09.007924 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:42:09.011080 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:42:09.014140 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:42:09.020513 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:42:09.023965 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:42:09.027031 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3538 12:42:09.033511 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3539 12:42:09.034016 Total UI for P1: 0, mck2ui 16
3540 12:42:09.040437 best dqsien dly found for B0: ( 1, 3, 24)
3541 12:42:09.043686 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 12:42:09.047335 Total UI for P1: 0, mck2ui 16
3543 12:42:09.050113 best dqsien dly found for B1: ( 1, 3, 26)
3544 12:42:09.053488 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3545 12:42:09.056760 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3546 12:42:09.057189
3547 12:42:09.060169 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3548 12:42:09.063488 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3549 12:42:09.066923 [Gating] SW calibration Done
3550 12:42:09.067404 ==
3551 12:42:09.069920 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 12:42:09.073515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 12:42:09.076774 ==
3554 12:42:09.077217 RX Vref Scan: 0
3555 12:42:09.077667
3556 12:42:09.079990 RX Vref 0 -> 0, step: 1
3557 12:42:09.080434
3558 12:42:09.083221 RX Delay -40 -> 252, step: 8
3559 12:42:09.086425 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3560 12:42:09.090428 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3561 12:42:09.092976 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3562 12:42:09.096798 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3563 12:42:09.103203 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3564 12:42:09.106335 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3565 12:42:09.109918 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3566 12:42:09.112586 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3567 12:42:09.115826 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3568 12:42:09.122848 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3569 12:42:09.126186 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3570 12:42:09.129134 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3571 12:42:09.132967 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3572 12:42:09.139050 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3573 12:42:09.142466 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3574 12:42:09.145626 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3575 12:42:09.146070 ==
3576 12:42:09.149309 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 12:42:09.152316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 12:42:09.152763 ==
3579 12:42:09.155484 DQS Delay:
3580 12:42:09.155929 DQS0 = 0, DQS1 = 0
3581 12:42:09.159033 DQM Delay:
3582 12:42:09.159516 DQM0 = 113, DQM1 = 111
3583 12:42:09.159967 DQ Delay:
3584 12:42:09.165273 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115
3585 12:42:09.168516 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3586 12:42:09.172368 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3587 12:42:09.175355 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3588 12:42:09.175898
3589 12:42:09.176395
3590 12:42:09.176841 ==
3591 12:42:09.178719 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 12:42:09.181824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 12:42:09.182290 ==
3594 12:42:09.182671
3595 12:42:09.182993
3596 12:42:09.185280 TX Vref Scan disable
3597 12:42:09.188606 == TX Byte 0 ==
3598 12:42:09.192288 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3599 12:42:09.195875 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3600 12:42:09.198837 == TX Byte 1 ==
3601 12:42:09.202342 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3602 12:42:09.205151 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3603 12:42:09.205579 ==
3604 12:42:09.208936 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 12:42:09.215085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 12:42:09.215564 ==
3607 12:42:09.225370 TX Vref=22, minBit 1, minWin=25, winSum=422
3608 12:42:09.228771 TX Vref=24, minBit 1, minWin=25, winSum=421
3609 12:42:09.232204 TX Vref=26, minBit 4, minWin=25, winSum=427
3610 12:42:09.235489 TX Vref=28, minBit 1, minWin=26, winSum=430
3611 12:42:09.238368 TX Vref=30, minBit 1, minWin=26, winSum=431
3612 12:42:09.245530 TX Vref=32, minBit 2, minWin=26, winSum=431
3613 12:42:09.248758 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3614 12:42:09.249186
3615 12:42:09.251743 Final TX Range 1 Vref 30
3616 12:42:09.252175
3617 12:42:09.252516 ==
3618 12:42:09.255056 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 12:42:09.258905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 12:42:09.261644 ==
3621 12:42:09.262072
3622 12:42:09.262404
3623 12:42:09.262715 TX Vref Scan disable
3624 12:42:09.265037 == TX Byte 0 ==
3625 12:42:09.268441 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3626 12:42:09.274928 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3627 12:42:09.275506 == TX Byte 1 ==
3628 12:42:09.278359 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3629 12:42:09.285196 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3630 12:42:09.285665
3631 12:42:09.286152 [DATLAT]
3632 12:42:09.286607 Freq=1200, CH1 RK1
3633 12:42:09.287143
3634 12:42:09.288284 DATLAT Default: 0xd
3635 12:42:09.291167 0, 0xFFFF, sum = 0
3636 12:42:09.291778 1, 0xFFFF, sum = 0
3637 12:42:09.294618 2, 0xFFFF, sum = 0
3638 12:42:09.295069 3, 0xFFFF, sum = 0
3639 12:42:09.298031 4, 0xFFFF, sum = 0
3640 12:42:09.298483 5, 0xFFFF, sum = 0
3641 12:42:09.301143 6, 0xFFFF, sum = 0
3642 12:42:09.301594 7, 0xFFFF, sum = 0
3643 12:42:09.304714 8, 0xFFFF, sum = 0
3644 12:42:09.305165 9, 0xFFFF, sum = 0
3645 12:42:09.307743 10, 0xFFFF, sum = 0
3646 12:42:09.308194 11, 0xFFFF, sum = 0
3647 12:42:09.311265 12, 0x0, sum = 1
3648 12:42:09.311766 13, 0x0, sum = 2
3649 12:42:09.314869 14, 0x0, sum = 3
3650 12:42:09.315309 15, 0x0, sum = 4
3651 12:42:09.318001 best_step = 13
3652 12:42:09.318421
3653 12:42:09.318750 ==
3654 12:42:09.321499 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 12:42:09.324158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 12:42:09.324581 ==
3657 12:42:09.328413 RX Vref Scan: 0
3658 12:42:09.328833
3659 12:42:09.329168 RX Vref 0 -> 0, step: 1
3660 12:42:09.329479
3661 12:42:09.330838 RX Delay -13 -> 252, step: 4
3662 12:42:09.337482 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3663 12:42:09.341148 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3664 12:42:09.344111 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3665 12:42:09.347496 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3666 12:42:09.350589 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3667 12:42:09.357483 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3668 12:42:09.361056 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3669 12:42:09.363692 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3670 12:42:09.367266 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3671 12:42:09.374025 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3672 12:42:09.377019 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3673 12:42:09.380456 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3674 12:42:09.384055 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3675 12:42:09.386955 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3676 12:42:09.393551 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3677 12:42:09.397206 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3678 12:42:09.397629 ==
3679 12:42:09.399835 Dram Type= 6, Freq= 0, CH_1, rank 1
3680 12:42:09.403331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3681 12:42:09.403868 ==
3682 12:42:09.406492 DQS Delay:
3683 12:42:09.406906 DQS0 = 0, DQS1 = 0
3684 12:42:09.410265 DQM Delay:
3685 12:42:09.410686 DQM0 = 114, DQM1 = 111
3686 12:42:09.411018 DQ Delay:
3687 12:42:09.412980 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3688 12:42:09.419793 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =110
3689 12:42:09.423347 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3690 12:42:09.426400 DQ12 =118, DQ13 =116, DQ14 =114, DQ15 =120
3691 12:42:09.426950
3692 12:42:09.427297
3693 12:42:09.433058 [DQSOSCAuto] RK1, (LSB)MR18= 0xf508, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3694 12:42:09.436008 CH1 RK1: MR19=304, MR18=F508
3695 12:42:09.442967 CH1_RK1: MR19=0x304, MR18=0xF508, DQSOSC=406, MR23=63, INC=39, DEC=26
3696 12:42:09.445982 [RxdqsGatingPostProcess] freq 1200
3697 12:42:09.452870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3698 12:42:09.456119 best DQS0 dly(2T, 0.5T) = (0, 11)
3699 12:42:09.456553 best DQS1 dly(2T, 0.5T) = (0, 11)
3700 12:42:09.459235 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3701 12:42:09.462312 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3702 12:42:09.465963 best DQS0 dly(2T, 0.5T) = (0, 11)
3703 12:42:09.469071 best DQS1 dly(2T, 0.5T) = (0, 11)
3704 12:42:09.472475 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3705 12:42:09.475524 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3706 12:42:09.479300 Pre-setting of DQS Precalculation
3707 12:42:09.485406 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3708 12:42:09.492072 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3709 12:42:09.498618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3710 12:42:09.499041
3711 12:42:09.499412
3712 12:42:09.502015 [Calibration Summary] 2400 Mbps
3713 12:42:09.502588 CH 0, Rank 0
3714 12:42:09.505919 SW Impedance : PASS
3715 12:42:09.508680 DUTY Scan : NO K
3716 12:42:09.509100 ZQ Calibration : PASS
3717 12:42:09.512304 Jitter Meter : NO K
3718 12:42:09.515470 CBT Training : PASS
3719 12:42:09.515891 Write leveling : PASS
3720 12:42:09.518718 RX DQS gating : PASS
3721 12:42:09.521821 RX DQ/DQS(RDDQC) : PASS
3722 12:42:09.522240 TX DQ/DQS : PASS
3723 12:42:09.525310 RX DATLAT : PASS
3724 12:42:09.528728 RX DQ/DQS(Engine): PASS
3725 12:42:09.529171 TX OE : NO K
3726 12:42:09.531737 All Pass.
3727 12:42:09.532179
3728 12:42:09.532628 CH 0, Rank 1
3729 12:42:09.534978 SW Impedance : PASS
3730 12:42:09.535459 DUTY Scan : NO K
3731 12:42:09.538064 ZQ Calibration : PASS
3732 12:42:09.541675 Jitter Meter : NO K
3733 12:42:09.542129 CBT Training : PASS
3734 12:42:09.544963 Write leveling : PASS
3735 12:42:09.548982 RX DQS gating : PASS
3736 12:42:09.549402 RX DQ/DQS(RDDQC) : PASS
3737 12:42:09.552199 TX DQ/DQS : PASS
3738 12:42:09.554510 RX DATLAT : PASS
3739 12:42:09.554929 RX DQ/DQS(Engine): PASS
3740 12:42:09.558054 TX OE : NO K
3741 12:42:09.558476 All Pass.
3742 12:42:09.558808
3743 12:42:09.561289 CH 1, Rank 0
3744 12:42:09.561709 SW Impedance : PASS
3745 12:42:09.564731 DUTY Scan : NO K
3746 12:42:09.568347 ZQ Calibration : PASS
3747 12:42:09.568794 Jitter Meter : NO K
3748 12:42:09.571316 CBT Training : PASS
3749 12:42:09.571793 Write leveling : PASS
3750 12:42:09.574238 RX DQS gating : PASS
3751 12:42:09.577476 RX DQ/DQS(RDDQC) : PASS
3752 12:42:09.577905 TX DQ/DQS : PASS
3753 12:42:09.580922 RX DATLAT : PASS
3754 12:42:09.584035 RX DQ/DQS(Engine): PASS
3755 12:42:09.584456 TX OE : NO K
3756 12:42:09.587918 All Pass.
3757 12:42:09.588464
3758 12:42:09.588938 CH 1, Rank 1
3759 12:42:09.590755 SW Impedance : PASS
3760 12:42:09.591276 DUTY Scan : NO K
3761 12:42:09.593732 ZQ Calibration : PASS
3762 12:42:09.597475 Jitter Meter : NO K
3763 12:42:09.597927 CBT Training : PASS
3764 12:42:09.600415 Write leveling : PASS
3765 12:42:09.604249 RX DQS gating : PASS
3766 12:42:09.604676 RX DQ/DQS(RDDQC) : PASS
3767 12:42:09.607173 TX DQ/DQS : PASS
3768 12:42:09.610328 RX DATLAT : PASS
3769 12:42:09.610776 RX DQ/DQS(Engine): PASS
3770 12:42:09.613969 TX OE : NO K
3771 12:42:09.614416 All Pass.
3772 12:42:09.614865
3773 12:42:09.617044 DramC Write-DBI off
3774 12:42:09.620547 PER_BANK_REFRESH: Hybrid Mode
3775 12:42:09.620990 TX_TRACKING: ON
3776 12:42:09.630701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3777 12:42:09.633271 [FAST_K] Save calibration result to emmc
3778 12:42:09.636660 dramc_set_vcore_voltage set vcore to 650000
3779 12:42:09.639966 Read voltage for 600, 5
3780 12:42:09.640387 Vio18 = 0
3781 12:42:09.640720 Vcore = 650000
3782 12:42:09.643312 Vdram = 0
3783 12:42:09.643827 Vddq = 0
3784 12:42:09.644175 Vmddr = 0
3785 12:42:09.650211 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3786 12:42:09.653540 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3787 12:42:09.657195 MEM_TYPE=3, freq_sel=19
3788 12:42:09.660189 sv_algorithm_assistance_LP4_1600
3789 12:42:09.663069 ============ PULL DRAM RESETB DOWN ============
3790 12:42:09.670717 ========== PULL DRAM RESETB DOWN end =========
3791 12:42:09.673512 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3792 12:42:09.676136 ===================================
3793 12:42:09.679757 LPDDR4 DRAM CONFIGURATION
3794 12:42:09.683239 ===================================
3795 12:42:09.683908 EX_ROW_EN[0] = 0x0
3796 12:42:09.686410 EX_ROW_EN[1] = 0x0
3797 12:42:09.686823 LP4Y_EN = 0x0
3798 12:42:09.689521 WORK_FSP = 0x0
3799 12:42:09.689899 WL = 0x2
3800 12:42:09.692798 RL = 0x2
3801 12:42:09.693232 BL = 0x2
3802 12:42:09.696410 RPST = 0x0
3803 12:42:09.699588 RD_PRE = 0x0
3804 12:42:09.700007 WR_PRE = 0x1
3805 12:42:09.703752 WR_PST = 0x0
3806 12:42:09.704185 DBI_WR = 0x0
3807 12:42:09.706269 DBI_RD = 0x0
3808 12:42:09.706698 OTF = 0x1
3809 12:42:09.709599 ===================================
3810 12:42:09.713410 ===================================
3811 12:42:09.716691 ANA top config
3812 12:42:09.719135 ===================================
3813 12:42:09.719679 DLL_ASYNC_EN = 0
3814 12:42:09.722511 ALL_SLAVE_EN = 1
3815 12:42:09.725880 NEW_RANK_MODE = 1
3816 12:42:09.729531 DLL_IDLE_MODE = 1
3817 12:42:09.729961 LP45_APHY_COMB_EN = 1
3818 12:42:09.732630 TX_ODT_DIS = 1
3819 12:42:09.736082 NEW_8X_MODE = 1
3820 12:42:09.739105 ===================================
3821 12:42:09.742472 ===================================
3822 12:42:09.745386 data_rate = 1200
3823 12:42:09.748835 CKR = 1
3824 12:42:09.752008 DQ_P2S_RATIO = 8
3825 12:42:09.755216 ===================================
3826 12:42:09.755772 CA_P2S_RATIO = 8
3827 12:42:09.759747 DQ_CA_OPEN = 0
3828 12:42:09.761822 DQ_SEMI_OPEN = 0
3829 12:42:09.765390 CA_SEMI_OPEN = 0
3830 12:42:09.768231 CA_FULL_RATE = 0
3831 12:42:09.772485 DQ_CKDIV4_EN = 1
3832 12:42:09.776443 CA_CKDIV4_EN = 1
3833 12:42:09.776871 CA_PREDIV_EN = 0
3834 12:42:09.778639 PH8_DLY = 0
3835 12:42:09.781706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3836 12:42:09.785209 DQ_AAMCK_DIV = 4
3837 12:42:09.788275 CA_AAMCK_DIV = 4
3838 12:42:09.791695 CA_ADMCK_DIV = 4
3839 12:42:09.792126 DQ_TRACK_CA_EN = 0
3840 12:42:09.795321 CA_PICK = 600
3841 12:42:09.797846 CA_MCKIO = 600
3842 12:42:09.801765 MCKIO_SEMI = 0
3843 12:42:09.805237 PLL_FREQ = 2288
3844 12:42:09.808064 DQ_UI_PI_RATIO = 32
3845 12:42:09.811644 CA_UI_PI_RATIO = 0
3846 12:42:09.814726 ===================================
3847 12:42:09.817720 ===================================
3848 12:42:09.818151 memory_type:LPDDR4
3849 12:42:09.821314 GP_NUM : 10
3850 12:42:09.824690 SRAM_EN : 1
3851 12:42:09.825118 MD32_EN : 0
3852 12:42:09.827950 ===================================
3853 12:42:09.831194 [ANA_INIT] >>>>>>>>>>>>>>
3854 12:42:09.834459 <<<<<< [CONFIGURE PHASE]: ANA_TX
3855 12:42:09.837775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3856 12:42:09.840953 ===================================
3857 12:42:09.844259 data_rate = 1200,PCW = 0X5800
3858 12:42:09.847739 ===================================
3859 12:42:09.850628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3860 12:42:09.854481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 12:42:09.861077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 12:42:09.864064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3863 12:42:09.867674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3864 12:42:09.874774 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3865 12:42:09.875317 [ANA_INIT] flow start
3866 12:42:09.877014 [ANA_INIT] PLL >>>>>>>>
3867 12:42:09.880546 [ANA_INIT] PLL <<<<<<<<
3868 12:42:09.880969 [ANA_INIT] MIDPI >>>>>>>>
3869 12:42:09.883673 [ANA_INIT] MIDPI <<<<<<<<
3870 12:42:09.886991 [ANA_INIT] DLL >>>>>>>>
3871 12:42:09.887455 [ANA_INIT] flow end
3872 12:42:09.893752 ============ LP4 DIFF to SE enter ============
3873 12:42:09.896983 ============ LP4 DIFF to SE exit ============
3874 12:42:09.897503 [ANA_INIT] <<<<<<<<<<<<<
3875 12:42:09.900909 [Flow] Enable top DCM control >>>>>
3876 12:42:09.903310 [Flow] Enable top DCM control <<<<<
3877 12:42:09.906759 Enable DLL master slave shuffle
3878 12:42:09.913978 ==============================================================
3879 12:42:09.917085 Gating Mode config
3880 12:42:09.919673 ==============================================================
3881 12:42:09.922975 Config description:
3882 12:42:09.932999 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3883 12:42:09.939900 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3884 12:42:09.943074 SELPH_MODE 0: By rank 1: By Phase
3885 12:42:09.949333 ==============================================================
3886 12:42:09.952592 GAT_TRACK_EN = 1
3887 12:42:09.956095 RX_GATING_MODE = 2
3888 12:42:09.959597 RX_GATING_TRACK_MODE = 2
3889 12:42:09.963338 SELPH_MODE = 1
3890 12:42:09.965772 PICG_EARLY_EN = 1
3891 12:42:09.966191 VALID_LAT_VALUE = 1
3892 12:42:09.972442 ==============================================================
3893 12:42:09.975786 Enter into Gating configuration >>>>
3894 12:42:09.979937 Exit from Gating configuration <<<<
3895 12:42:09.982210 Enter into DVFS_PRE_config >>>>>
3896 12:42:09.992142 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3897 12:42:09.995543 Exit from DVFS_PRE_config <<<<<
3898 12:42:09.998500 Enter into PICG configuration >>>>
3899 12:42:10.002434 Exit from PICG configuration <<<<
3900 12:42:10.005444 [RX_INPUT] configuration >>>>>
3901 12:42:10.008668 [RX_INPUT] configuration <<<<<
3902 12:42:10.015336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3903 12:42:10.018861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3904 12:42:10.025244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 12:42:10.031775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 12:42:10.038188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 12:42:10.044713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 12:42:10.047706 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3909 12:42:10.051648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3910 12:42:10.054563 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3911 12:42:10.061849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3912 12:42:10.064293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3913 12:42:10.068456 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3914 12:42:10.071479 ===================================
3915 12:42:10.074298 LPDDR4 DRAM CONFIGURATION
3916 12:42:10.077893 ===================================
3917 12:42:10.081206 EX_ROW_EN[0] = 0x0
3918 12:42:10.081770 EX_ROW_EN[1] = 0x0
3919 12:42:10.085117 LP4Y_EN = 0x0
3920 12:42:10.085547 WORK_FSP = 0x0
3921 12:42:10.087539 WL = 0x2
3922 12:42:10.088061 RL = 0x2
3923 12:42:10.091254 BL = 0x2
3924 12:42:10.091757 RPST = 0x0
3925 12:42:10.094309 RD_PRE = 0x0
3926 12:42:10.094832 WR_PRE = 0x1
3927 12:42:10.098520 WR_PST = 0x0
3928 12:42:10.100769 DBI_WR = 0x0
3929 12:42:10.101191 DBI_RD = 0x0
3930 12:42:10.104091 OTF = 0x1
3931 12:42:10.106963 ===================================
3932 12:42:10.110171 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3933 12:42:10.113806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3934 12:42:10.117412 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3935 12:42:10.120569 ===================================
3936 12:42:10.123972 LPDDR4 DRAM CONFIGURATION
3937 12:42:10.127339 ===================================
3938 12:42:10.130427 EX_ROW_EN[0] = 0x10
3939 12:42:10.130993 EX_ROW_EN[1] = 0x0
3940 12:42:10.133820 LP4Y_EN = 0x0
3941 12:42:10.134351 WORK_FSP = 0x0
3942 12:42:10.137542 WL = 0x2
3943 12:42:10.138123 RL = 0x2
3944 12:42:10.139847 BL = 0x2
3945 12:42:10.144074 RPST = 0x0
3946 12:42:10.144644 RD_PRE = 0x0
3947 12:42:10.146630 WR_PRE = 0x1
3948 12:42:10.147195 WR_PST = 0x0
3949 12:42:10.150564 DBI_WR = 0x0
3950 12:42:10.151142 DBI_RD = 0x0
3951 12:42:10.153773 OTF = 0x1
3952 12:42:10.156690 ===================================
3953 12:42:10.160024 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3954 12:42:10.165669 nWR fixed to 30
3955 12:42:10.169163 [ModeRegInit_LP4] CH0 RK0
3956 12:42:10.169726 [ModeRegInit_LP4] CH0 RK1
3957 12:42:10.172293 [ModeRegInit_LP4] CH1 RK0
3958 12:42:10.175182 [ModeRegInit_LP4] CH1 RK1
3959 12:42:10.175787 match AC timing 17
3960 12:42:10.181940 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3961 12:42:10.184944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3962 12:42:10.188520 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3963 12:42:10.194870 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3964 12:42:10.198482 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3965 12:42:10.199007 ==
3966 12:42:10.201299 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 12:42:10.204716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 12:42:10.207911 ==
3969 12:42:10.211465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3970 12:42:10.218216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3971 12:42:10.221432 [CA 0] Center 36 (6~67) winsize 62
3972 12:42:10.224428 [CA 1] Center 35 (5~66) winsize 62
3973 12:42:10.227605 [CA 2] Center 34 (4~65) winsize 62
3974 12:42:10.230863 [CA 3] Center 34 (4~65) winsize 62
3975 12:42:10.234225 [CA 4] Center 33 (3~64) winsize 62
3976 12:42:10.237941 [CA 5] Center 33 (3~64) winsize 62
3977 12:42:10.238372
3978 12:42:10.241135 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3979 12:42:10.241564
3980 12:42:10.244699 [CATrainingPosCal] consider 1 rank data
3981 12:42:10.247552 u2DelayCellTimex100 = 270/100 ps
3982 12:42:10.251231 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3983 12:42:10.254293 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3984 12:42:10.258410 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3985 12:42:10.263927 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 12:42:10.267523 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3987 12:42:10.270567 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 12:42:10.271086
3989 12:42:10.274221 CA PerBit enable=1, Macro0, CA PI delay=33
3990 12:42:10.274747
3991 12:42:10.277049 [CBTSetCACLKResult] CA Dly = 33
3992 12:42:10.277475 CS Dly: 4 (0~35)
3993 12:42:10.280824 ==
3994 12:42:10.281401 Dram Type= 6, Freq= 0, CH_0, rank 1
3995 12:42:10.287163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 12:42:10.287820 ==
3997 12:42:10.290015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3998 12:42:10.296552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3999 12:42:10.300424 [CA 0] Center 36 (6~67) winsize 62
4000 12:42:10.303886 [CA 1] Center 36 (6~67) winsize 62
4001 12:42:10.307303 [CA 2] Center 34 (4~65) winsize 62
4002 12:42:10.310548 [CA 3] Center 34 (4~65) winsize 62
4003 12:42:10.313717 [CA 4] Center 33 (3~64) winsize 62
4004 12:42:10.317449 [CA 5] Center 33 (3~64) winsize 62
4005 12:42:10.317877
4006 12:42:10.320168 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4007 12:42:10.320596
4008 12:42:10.323895 [CATrainingPosCal] consider 2 rank data
4009 12:42:10.326819 u2DelayCellTimex100 = 270/100 ps
4010 12:42:10.333454 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4011 12:42:10.336663 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 12:42:10.339888 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4013 12:42:10.343341 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4014 12:42:10.346247 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4015 12:42:10.349957 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 12:42:10.350383
4017 12:42:10.352974 CA PerBit enable=1, Macro0, CA PI delay=33
4018 12:42:10.353402
4019 12:42:10.356508 [CBTSetCACLKResult] CA Dly = 33
4020 12:42:10.359518 CS Dly: 4 (0~36)
4021 12:42:10.359945
4022 12:42:10.363089 ----->DramcWriteLeveling(PI) begin...
4023 12:42:10.363686 ==
4024 12:42:10.366384 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 12:42:10.370134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 12:42:10.370557 ==
4027 12:42:10.373023 Write leveling (Byte 0): 33 => 33
4028 12:42:10.376474 Write leveling (Byte 1): 29 => 29
4029 12:42:10.379164 DramcWriteLeveling(PI) end<-----
4030 12:42:10.379653
4031 12:42:10.379990 ==
4032 12:42:10.382753 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 12:42:10.386226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 12:42:10.386653 ==
4035 12:42:10.389455 [Gating] SW mode calibration
4036 12:42:10.396183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4037 12:42:10.402528 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4038 12:42:10.405601 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 12:42:10.412575 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 12:42:10.416171 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 12:42:10.419050 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
4042 12:42:10.425489 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
4043 12:42:10.428503 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:42:10.432082 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 12:42:10.439145 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 12:42:10.441806 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:42:10.445127 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 12:42:10.451581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 12:42:10.455064 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4050 12:42:10.458530 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4051 12:42:10.465002 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:42:10.468233 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 12:42:10.471973 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 12:42:10.478303 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:42:10.481766 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 12:42:10.484924 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 12:42:10.491298 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4058 12:42:10.494596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4059 12:42:10.498095 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:42:10.504744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:42:10.507579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:42:10.511463 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:42:10.518093 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:42:10.521187 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:42:10.524202 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:42:10.531343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:42:10.534151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:42:10.537676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:42:10.544265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:42:10.547337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:42:10.550592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:42:10.557463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:42:10.560352 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:42:10.563781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4075 12:42:10.567668 Total UI for P1: 0, mck2ui 16
4076 12:42:10.570421 best dqsien dly found for B0: ( 0, 13, 14)
4077 12:42:10.574008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 12:42:10.577502 Total UI for P1: 0, mck2ui 16
4079 12:42:10.580222 best dqsien dly found for B1: ( 0, 13, 16)
4080 12:42:10.587140 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4081 12:42:10.590704 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4082 12:42:10.591126
4083 12:42:10.593321 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4084 12:42:10.596652 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4085 12:42:10.599871 [Gating] SW calibration Done
4086 12:42:10.600294 ==
4087 12:42:10.604279 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 12:42:10.606882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 12:42:10.607310 ==
4090 12:42:10.610026 RX Vref Scan: 0
4091 12:42:10.610451
4092 12:42:10.610786 RX Vref 0 -> 0, step: 1
4093 12:42:10.611096
4094 12:42:10.613428 RX Delay -230 -> 252, step: 16
4095 12:42:10.619989 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4096 12:42:10.622977 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4097 12:42:10.626386 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4098 12:42:10.629748 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4099 12:42:10.633382 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4100 12:42:10.639711 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4101 12:42:10.643210 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4102 12:42:10.645887 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4103 12:42:10.649472 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4104 12:42:10.656258 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4105 12:42:10.659235 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4106 12:42:10.662510 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4107 12:42:10.665833 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4108 12:42:10.672784 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4109 12:42:10.675705 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4110 12:42:10.679286 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4111 12:42:10.679750 ==
4112 12:42:10.682544 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 12:42:10.688896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 12:42:10.689328 ==
4115 12:42:10.689740 DQS Delay:
4116 12:42:10.690064 DQS0 = 0, DQS1 = 0
4117 12:42:10.692374 DQM Delay:
4118 12:42:10.692817 DQM0 = 42, DQM1 = 34
4119 12:42:10.695357 DQ Delay:
4120 12:42:10.698653 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4121 12:42:10.702565 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4122 12:42:10.705984 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4123 12:42:10.708983 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4124 12:42:10.709450
4125 12:42:10.709826
4126 12:42:10.710242 ==
4127 12:42:10.712764 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 12:42:10.715501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 12:42:10.715954 ==
4130 12:42:10.716301
4131 12:42:10.716622
4132 12:42:10.718612 TX Vref Scan disable
4133 12:42:10.719039 == TX Byte 0 ==
4134 12:42:10.724958 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4135 12:42:10.728574 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4136 12:42:10.731677 == TX Byte 1 ==
4137 12:42:10.735312 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4138 12:42:10.738975 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4139 12:42:10.739444 ==
4140 12:42:10.741702 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:42:10.744903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:42:10.748751 ==
4143 12:42:10.749182
4144 12:42:10.749520
4145 12:42:10.749837 TX Vref Scan disable
4146 12:42:10.751933 == TX Byte 0 ==
4147 12:42:10.755937 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4148 12:42:10.761996 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4149 12:42:10.762465 == TX Byte 1 ==
4150 12:42:10.765395 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4151 12:42:10.772528 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4152 12:42:10.772959
4153 12:42:10.773296 [DATLAT]
4154 12:42:10.773613 Freq=600, CH0 RK0
4155 12:42:10.773925
4156 12:42:10.775131 DATLAT Default: 0x9
4157 12:42:10.775598 0, 0xFFFF, sum = 0
4158 12:42:10.778914 1, 0xFFFF, sum = 0
4159 12:42:10.781669 2, 0xFFFF, sum = 0
4160 12:42:10.782116 3, 0xFFFF, sum = 0
4161 12:42:10.784981 4, 0xFFFF, sum = 0
4162 12:42:10.785417 5, 0xFFFF, sum = 0
4163 12:42:10.788212 6, 0xFFFF, sum = 0
4164 12:42:10.788648 7, 0xFFFF, sum = 0
4165 12:42:10.791387 8, 0x0, sum = 1
4166 12:42:10.791837 9, 0x0, sum = 2
4167 12:42:10.795096 10, 0x0, sum = 3
4168 12:42:10.795638 11, 0x0, sum = 4
4169 12:42:10.796091 best_step = 9
4170 12:42:10.796509
4171 12:42:10.798400 ==
4172 12:42:10.801829 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 12:42:10.805034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 12:42:10.805483 ==
4175 12:42:10.805959 RX Vref Scan: 1
4176 12:42:10.806489
4177 12:42:10.808049 RX Vref 0 -> 0, step: 1
4178 12:42:10.808528
4179 12:42:10.811646 RX Delay -179 -> 252, step: 8
4180 12:42:10.812083
4181 12:42:10.814745 Set Vref, RX VrefLevel [Byte0]: 51
4182 12:42:10.818291 [Byte1]: 58
4183 12:42:10.818827
4184 12:42:10.821536 Final RX Vref Byte 0 = 51 to rank0
4185 12:42:10.825000 Final RX Vref Byte 1 = 58 to rank0
4186 12:42:10.827865 Final RX Vref Byte 0 = 51 to rank1
4187 12:42:10.831278 Final RX Vref Byte 1 = 58 to rank1==
4188 12:42:10.834630 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 12:42:10.838198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 12:42:10.841945 ==
4191 12:42:10.842483 DQS Delay:
4192 12:42:10.842942 DQS0 = 0, DQS1 = 0
4193 12:42:10.844287 DQM Delay:
4194 12:42:10.844755 DQM0 = 42, DQM1 = 33
4195 12:42:10.847590 DQ Delay:
4196 12:42:10.850984 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4197 12:42:10.851473 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4198 12:42:10.854546 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =32
4199 12:42:10.860801 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4200 12:42:10.861344
4201 12:42:10.861816
4202 12:42:10.867491 [DQSOSCAuto] RK0, (LSB)MR18= 0x453d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4203 12:42:10.870993 CH0 RK0: MR19=808, MR18=453D
4204 12:42:10.877405 CH0_RK0: MR19=0x808, MR18=0x453D, DQSOSC=396, MR23=63, INC=167, DEC=111
4205 12:42:10.877943
4206 12:42:10.880417 ----->DramcWriteLeveling(PI) begin...
4207 12:42:10.880862 ==
4208 12:42:10.884185 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 12:42:10.887016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 12:42:10.887488 ==
4211 12:42:10.890613 Write leveling (Byte 0): 32 => 32
4212 12:42:10.894082 Write leveling (Byte 1): 29 => 29
4213 12:42:10.897274 DramcWriteLeveling(PI) end<-----
4214 12:42:10.897808
4215 12:42:10.898256 ==
4216 12:42:10.900244 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 12:42:10.903428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 12:42:10.907159 ==
4219 12:42:10.907672 [Gating] SW mode calibration
4220 12:42:10.913223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4221 12:42:10.920256 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4222 12:42:10.923552 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 12:42:10.930107 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 12:42:10.933512 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 12:42:10.937242 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
4226 12:42:10.942913 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4227 12:42:10.946378 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 12:42:10.949528 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 12:42:10.956394 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:42:10.959471 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:42:10.962907 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 12:42:10.969407 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 12:42:10.972321 0 10 12 | B1->B0 | 2a2a 3535 | 1 0 | (0 0) (0 0)
4234 12:42:10.975834 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4235 12:42:10.982248 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:42:10.985678 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 12:42:10.988913 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:42:10.995583 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:42:10.999096 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:42:11.002931 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:42:11.008607 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4242 12:42:11.012653 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:42:11.015326 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:42:11.022008 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:42:11.025314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:42:11.028589 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:42:11.035399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:42:11.038603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:42:11.041769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:42:11.048570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:42:11.052002 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:42:11.055430 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:42:11.061605 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:42:11.065550 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:42:11.067934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:42:11.075036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:42:11.078014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4258 12:42:11.081410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4259 12:42:11.084601 Total UI for P1: 0, mck2ui 16
4260 12:42:11.087555 best dqsien dly found for B0: ( 0, 13, 12)
4261 12:42:11.094759 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 12:42:11.097580 Total UI for P1: 0, mck2ui 16
4263 12:42:11.101144 best dqsien dly found for B1: ( 0, 13, 14)
4264 12:42:11.104093 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4265 12:42:11.107563 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4266 12:42:11.108247
4267 12:42:11.110464 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4268 12:42:11.113938 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4269 12:42:11.117198 [Gating] SW calibration Done
4270 12:42:11.117672 ==
4271 12:42:11.120456 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 12:42:11.124051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 12:42:11.127009 ==
4274 12:42:11.127480 RX Vref Scan: 0
4275 12:42:11.127861
4276 12:42:11.130651 RX Vref 0 -> 0, step: 1
4277 12:42:11.131081
4278 12:42:11.133810 RX Delay -230 -> 252, step: 16
4279 12:42:11.137092 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4280 12:42:11.140483 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4281 12:42:11.143767 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4282 12:42:11.147486 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4283 12:42:11.153964 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4284 12:42:11.156919 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4285 12:42:11.161315 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4286 12:42:11.163330 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4287 12:42:11.170550 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4288 12:42:11.173658 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4289 12:42:11.177060 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4290 12:42:11.180398 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4291 12:42:11.186576 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4292 12:42:11.189801 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4293 12:42:11.193405 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4294 12:42:11.196342 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4295 12:42:11.199536 ==
4296 12:42:11.203116 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 12:42:11.206671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 12:42:11.207201 ==
4299 12:42:11.207618 DQS Delay:
4300 12:42:11.209252 DQS0 = 0, DQS1 = 0
4301 12:42:11.209855 DQM Delay:
4302 12:42:11.213444 DQM0 = 41, DQM1 = 32
4303 12:42:11.213870 DQ Delay:
4304 12:42:11.216045 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4305 12:42:11.219494 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4306 12:42:11.222355 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4307 12:42:11.226073 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4308 12:42:11.226674
4309 12:42:11.227021
4310 12:42:11.227494 ==
4311 12:42:11.229384 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 12:42:11.233160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 12:42:11.233686 ==
4314 12:42:11.234026
4315 12:42:11.234339
4316 12:42:11.236259 TX Vref Scan disable
4317 12:42:11.239427 == TX Byte 0 ==
4318 12:42:11.242776 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4319 12:42:11.245944 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4320 12:42:11.249389 == TX Byte 1 ==
4321 12:42:11.252047 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4322 12:42:11.255525 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4323 12:42:11.256051 ==
4324 12:42:11.259743 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 12:42:11.265747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 12:42:11.266427 ==
4327 12:42:11.266952
4328 12:42:11.267599
4329 12:42:11.268112 TX Vref Scan disable
4330 12:42:11.269934 == TX Byte 0 ==
4331 12:42:11.272912 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4332 12:42:11.279645 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4333 12:42:11.280266 == TX Byte 1 ==
4334 12:42:11.283226 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4335 12:42:11.289417 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4336 12:42:11.290017
4337 12:42:11.290517 [DATLAT]
4338 12:42:11.291119 Freq=600, CH0 RK1
4339 12:42:11.291733
4340 12:42:11.292900 DATLAT Default: 0x9
4341 12:42:11.296340 0, 0xFFFF, sum = 0
4342 12:42:11.296773 1, 0xFFFF, sum = 0
4343 12:42:11.300321 2, 0xFFFF, sum = 0
4344 12:42:11.300752 3, 0xFFFF, sum = 0
4345 12:42:11.302986 4, 0xFFFF, sum = 0
4346 12:42:11.303562 5, 0xFFFF, sum = 0
4347 12:42:11.306676 6, 0xFFFF, sum = 0
4348 12:42:11.307207 7, 0xFFFF, sum = 0
4349 12:42:11.309467 8, 0x0, sum = 1
4350 12:42:11.310113 9, 0x0, sum = 2
4351 12:42:11.312825 10, 0x0, sum = 3
4352 12:42:11.313258 11, 0x0, sum = 4
4353 12:42:11.313600 best_step = 9
4354 12:42:11.313913
4355 12:42:11.316483 ==
4356 12:42:11.316908 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 12:42:11.322873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 12:42:11.323443 ==
4359 12:42:11.323801 RX Vref Scan: 0
4360 12:42:11.324118
4361 12:42:11.326026 RX Vref 0 -> 0, step: 1
4362 12:42:11.326449
4363 12:42:11.329233 RX Delay -195 -> 252, step: 8
4364 12:42:11.335982 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4365 12:42:11.339444 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4366 12:42:11.342727 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4367 12:42:11.345735 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4368 12:42:11.349408 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4369 12:42:11.355929 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4370 12:42:11.359441 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4371 12:42:11.362505 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4372 12:42:11.366176 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4373 12:42:11.373117 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4374 12:42:11.375829 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4375 12:42:11.379433 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4376 12:42:11.382294 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4377 12:42:11.388597 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4378 12:42:11.391992 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4379 12:42:11.395306 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4380 12:42:11.395772 ==
4381 12:42:11.398159 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 12:42:11.401970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 12:42:11.406186 ==
4384 12:42:11.406718 DQS Delay:
4385 12:42:11.407056 DQS0 = 0, DQS1 = 0
4386 12:42:11.408253 DQM Delay:
4387 12:42:11.408720 DQM0 = 40, DQM1 = 33
4388 12:42:11.411931 DQ Delay:
4389 12:42:11.415269 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4390 12:42:11.415752 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4391 12:42:11.418265 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4392 12:42:11.421966 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4393 12:42:11.425487
4394 12:42:11.425906
4395 12:42:11.431698 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4396 12:42:11.434588 CH0 RK1: MR19=808, MR18=3E38
4397 12:42:11.441300 CH0_RK1: MR19=0x808, MR18=0x3E38, DQSOSC=398, MR23=63, INC=165, DEC=110
4398 12:42:11.444920 [RxdqsGatingPostProcess] freq 600
4399 12:42:11.447746 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4400 12:42:11.451110 Pre-setting of DQS Precalculation
4401 12:42:11.458243 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4402 12:42:11.458927 ==
4403 12:42:11.461194 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 12:42:11.464206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 12:42:11.464919 ==
4406 12:42:11.471405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 12:42:11.477392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4408 12:42:11.481025 [CA 0] Center 36 (6~66) winsize 61
4409 12:42:11.484417 [CA 1] Center 36 (6~66) winsize 61
4410 12:42:11.487596 [CA 2] Center 34 (4~65) winsize 62
4411 12:42:11.490635 [CA 3] Center 33 (3~64) winsize 62
4412 12:42:11.494245 [CA 4] Center 34 (4~65) winsize 62
4413 12:42:11.497170 [CA 5] Center 33 (3~64) winsize 62
4414 12:42:11.497585
4415 12:42:11.501011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4416 12:42:11.501529
4417 12:42:11.503974 [CATrainingPosCal] consider 1 rank data
4418 12:42:11.507181 u2DelayCellTimex100 = 270/100 ps
4419 12:42:11.510372 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4420 12:42:11.513925 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4421 12:42:11.516663 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 12:42:11.520568 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 12:42:11.523214 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 12:42:11.526654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 12:42:11.527115
4426 12:42:11.534398 CA PerBit enable=1, Macro0, CA PI delay=33
4427 12:42:11.534956
4428 12:42:11.536607 [CBTSetCACLKResult] CA Dly = 33
4429 12:42:11.537076 CS Dly: 4 (0~35)
4430 12:42:11.537469 ==
4431 12:42:11.540678 Dram Type= 6, Freq= 0, CH_1, rank 1
4432 12:42:11.543944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 12:42:11.544474 ==
4434 12:42:11.550138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 12:42:11.557189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4436 12:42:11.560459 [CA 0] Center 35 (5~66) winsize 62
4437 12:42:11.563169 [CA 1] Center 36 (6~66) winsize 61
4438 12:42:11.566696 [CA 2] Center 34 (4~65) winsize 62
4439 12:42:11.569755 [CA 3] Center 33 (3~64) winsize 62
4440 12:42:11.573366 [CA 4] Center 34 (4~65) winsize 62
4441 12:42:11.576537 [CA 5] Center 33 (3~64) winsize 62
4442 12:42:11.577080
4443 12:42:11.579889 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4444 12:42:11.580454
4445 12:42:11.583312 [CATrainingPosCal] consider 2 rank data
4446 12:42:11.586129 u2DelayCellTimex100 = 270/100 ps
4447 12:42:11.589308 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4448 12:42:11.592661 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4449 12:42:11.596559 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 12:42:11.599735 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 12:42:11.606342 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 12:42:11.610900 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 12:42:11.611577
4454 12:42:11.612498 CA PerBit enable=1, Macro0, CA PI delay=33
4455 12:42:11.613117
4456 12:42:11.615821 [CBTSetCACLKResult] CA Dly = 33
4457 12:42:11.616247 CS Dly: 5 (0~37)
4458 12:42:11.616585
4459 12:42:11.619224 ----->DramcWriteLeveling(PI) begin...
4460 12:42:11.619701 ==
4461 12:42:11.623015 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 12:42:11.629004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 12:42:11.629595 ==
4464 12:42:11.632319 Write leveling (Byte 0): 28 => 28
4465 12:42:11.635500 Write leveling (Byte 1): 29 => 29
4466 12:42:11.638830 DramcWriteLeveling(PI) end<-----
4467 12:42:11.639484
4468 12:42:11.639904 ==
4469 12:42:11.641905 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 12:42:11.645399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:42:11.645827 ==
4472 12:42:11.648774 [Gating] SW mode calibration
4473 12:42:11.656062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4474 12:42:11.662400 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4475 12:42:11.665584 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 12:42:11.668496 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 12:42:11.675422 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 12:42:11.678316 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (1 1) (1 1)
4479 12:42:11.681431 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 12:42:11.688397 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 12:42:11.691664 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 12:42:11.694864 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:42:11.701728 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 12:42:11.704942 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 12:42:11.707956 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 12:42:11.714631 0 10 12 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (0 0)
4487 12:42:11.718124 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 12:42:11.720878 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 12:42:11.728207 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:42:11.731475 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:42:11.734316 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:42:11.740614 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 12:42:11.744161 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:42:11.747455 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4495 12:42:11.754778 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:42:11.757378 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:42:11.761227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:42:11.767051 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:42:11.771120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:42:11.774239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:42:11.780674 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:42:11.783715 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:42:11.787275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:42:11.793557 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:42:11.797101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:42:11.800364 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:42:11.806735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:42:11.810634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:42:11.814003 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:42:11.820185 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 12:42:11.820637 Total UI for P1: 0, mck2ui 16
4512 12:42:11.823506 best dqsien dly found for B0: ( 0, 13, 10)
4513 12:42:11.826442 Total UI for P1: 0, mck2ui 16
4514 12:42:11.830371 best dqsien dly found for B1: ( 0, 13, 10)
4515 12:42:11.836973 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4516 12:42:11.839891 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4517 12:42:11.840335
4518 12:42:11.843072 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4519 12:42:11.846751 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4520 12:42:11.849707 [Gating] SW calibration Done
4521 12:42:11.850200 ==
4522 12:42:11.853814 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 12:42:11.856504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 12:42:11.857100 ==
4525 12:42:11.859818 RX Vref Scan: 0
4526 12:42:11.860305
4527 12:42:11.860802 RX Vref 0 -> 0, step: 1
4528 12:42:11.861273
4529 12:42:11.863311 RX Delay -230 -> 252, step: 16
4530 12:42:11.869808 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4531 12:42:11.873056 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4532 12:42:11.876367 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4533 12:42:11.880284 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4534 12:42:11.882649 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4535 12:42:11.889905 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4536 12:42:11.892880 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4537 12:42:11.895889 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4538 12:42:11.900053 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4539 12:42:11.906538 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4540 12:42:11.909254 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4541 12:42:11.912526 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4542 12:42:11.916040 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4543 12:42:11.922581 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4544 12:42:11.925566 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4545 12:42:11.929245 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4546 12:42:11.929801 ==
4547 12:42:11.932587 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 12:42:11.935275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 12:42:11.938989 ==
4550 12:42:11.939640 DQS Delay:
4551 12:42:11.940150 DQS0 = 0, DQS1 = 0
4552 12:42:11.941793 DQM Delay:
4553 12:42:11.942276 DQM0 = 46, DQM1 = 40
4554 12:42:11.945446 DQ Delay:
4555 12:42:11.949163 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4556 12:42:11.949749 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4557 12:42:11.952400 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4558 12:42:11.959037 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =41
4559 12:42:11.959682
4560 12:42:11.960187
4561 12:42:11.960663 ==
4562 12:42:11.961581 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 12:42:11.965134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 12:42:11.965687 ==
4565 12:42:11.965796
4566 12:42:11.965862
4567 12:42:11.968255 TX Vref Scan disable
4568 12:42:11.968338 == TX Byte 0 ==
4569 12:42:11.974354 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 12:42:11.977816 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 12:42:11.977922 == TX Byte 1 ==
4572 12:42:11.984054 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4573 12:42:11.987812 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4574 12:42:11.987912 ==
4575 12:42:11.991294 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 12:42:11.994035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 12:42:11.994118 ==
4578 12:42:11.997813
4579 12:42:11.997901
4580 12:42:11.997971 TX Vref Scan disable
4581 12:42:12.001213 == TX Byte 0 ==
4582 12:42:12.004129 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 12:42:12.010935 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 12:42:12.011126 == TX Byte 1 ==
4585 12:42:12.015232 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4586 12:42:12.021158 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4587 12:42:12.021376
4588 12:42:12.021499 [DATLAT]
4589 12:42:12.021608 Freq=600, CH1 RK0
4590 12:42:12.021712
4591 12:42:12.024362 DATLAT Default: 0x9
4592 12:42:12.027643 0, 0xFFFF, sum = 0
4593 12:42:12.027876 1, 0xFFFF, sum = 0
4594 12:42:12.030806 2, 0xFFFF, sum = 0
4595 12:42:12.031077 3, 0xFFFF, sum = 0
4596 12:42:12.034282 4, 0xFFFF, sum = 0
4597 12:42:12.034544 5, 0xFFFF, sum = 0
4598 12:42:12.037564 6, 0xFFFF, sum = 0
4599 12:42:12.037860 7, 0xFFFF, sum = 0
4600 12:42:12.040624 8, 0x0, sum = 1
4601 12:42:12.040874 9, 0x0, sum = 2
4602 12:42:12.044285 10, 0x0, sum = 3
4603 12:42:12.044654 11, 0x0, sum = 4
4604 12:42:12.044918 best_step = 9
4605 12:42:12.045150
4606 12:42:12.047051 ==
4607 12:42:12.050972 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 12:42:12.053920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 12:42:12.054368 ==
4610 12:42:12.054814 RX Vref Scan: 1
4611 12:42:12.055246
4612 12:42:12.057606 RX Vref 0 -> 0, step: 1
4613 12:42:12.058153
4614 12:42:12.060737 RX Delay -179 -> 252, step: 8
4615 12:42:12.061289
4616 12:42:12.063967 Set Vref, RX VrefLevel [Byte0]: 47
4617 12:42:12.067138 [Byte1]: 51
4618 12:42:12.067688
4619 12:42:12.070471 Final RX Vref Byte 0 = 47 to rank0
4620 12:42:12.073770 Final RX Vref Byte 1 = 51 to rank0
4621 12:42:12.077231 Final RX Vref Byte 0 = 47 to rank1
4622 12:42:12.080005 Final RX Vref Byte 1 = 51 to rank1==
4623 12:42:12.083606 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 12:42:12.090550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 12:42:12.091121 ==
4626 12:42:12.091532 DQS Delay:
4627 12:42:12.093325 DQS0 = 0, DQS1 = 0
4628 12:42:12.093798 DQM Delay:
4629 12:42:12.094174 DQM0 = 42, DQM1 = 34
4630 12:42:12.096555 DQ Delay:
4631 12:42:12.100090 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =44
4632 12:42:12.103292 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4633 12:42:12.106791 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4634 12:42:12.110006 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4635 12:42:12.110575
4636 12:42:12.110946
4637 12:42:12.116092 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4638 12:42:12.119778 CH1 RK0: MR19=808, MR18=2B44
4639 12:42:12.126642 CH1_RK0: MR19=0x808, MR18=0x2B44, DQSOSC=396, MR23=63, INC=167, DEC=111
4640 12:42:12.127210
4641 12:42:12.129503 ----->DramcWriteLeveling(PI) begin...
4642 12:42:12.130087 ==
4643 12:42:12.132395 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 12:42:12.136286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:42:12.136859 ==
4646 12:42:12.139526 Write leveling (Byte 0): 30 => 30
4647 12:42:12.143754 Write leveling (Byte 1): 30 => 30
4648 12:42:12.145801 DramcWriteLeveling(PI) end<-----
4649 12:42:12.146374
4650 12:42:12.146750 ==
4651 12:42:12.149498 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 12:42:12.155708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 12:42:12.156190 ==
4654 12:42:12.156566 [Gating] SW mode calibration
4655 12:42:12.166429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4656 12:42:12.168777 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4657 12:42:12.175701 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 12:42:12.178558 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 12:42:12.182050 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4660 12:42:12.188403 0 9 12 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (1 0)
4661 12:42:12.191578 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4662 12:42:12.194996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 12:42:12.202132 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 12:42:12.204667 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:42:12.208049 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 12:42:12.214222 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 12:42:12.217636 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4668 12:42:12.220831 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4669 12:42:12.228130 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 12:42:12.230991 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 12:42:12.234217 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 12:42:12.240736 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 12:42:12.244469 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:42:12.247666 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 12:42:12.253928 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 12:42:12.257874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4677 12:42:12.260478 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:42:12.267223 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:42:12.270443 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:42:12.274097 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:42:12.280248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:42:12.283837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:42:12.286846 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:42:12.293439 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:42:12.297210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:42:12.300945 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:42:12.307020 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:42:12.310451 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:42:12.313336 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:42:12.319725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:42:12.324813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:42:12.326656 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4693 12:42:12.333443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 12:42:12.333911 Total UI for P1: 0, mck2ui 16
4695 12:42:12.339825 best dqsien dly found for B0: ( 0, 13, 12)
4696 12:42:12.340361 Total UI for P1: 0, mck2ui 16
4697 12:42:12.346703 best dqsien dly found for B1: ( 0, 13, 12)
4698 12:42:12.349947 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4699 12:42:12.353005 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4700 12:42:12.353487
4701 12:42:12.356893 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4702 12:42:12.360033 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4703 12:42:12.363449 [Gating] SW calibration Done
4704 12:42:12.363923 ==
4705 12:42:12.366405 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 12:42:12.369593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 12:42:12.370237 ==
4708 12:42:12.372803 RX Vref Scan: 0
4709 12:42:12.373276
4710 12:42:12.373647 RX Vref 0 -> 0, step: 1
4711 12:42:12.373995
4712 12:42:12.375983 RX Delay -230 -> 252, step: 16
4713 12:42:12.382917 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4714 12:42:12.385665 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4715 12:42:12.389286 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4716 12:42:12.392373 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4717 12:42:12.399656 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4718 12:42:12.402528 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4719 12:42:12.406110 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4720 12:42:12.409361 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4721 12:42:12.412116 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4722 12:42:12.418631 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4723 12:42:12.422330 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4724 12:42:12.425597 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4725 12:42:12.428490 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4726 12:42:12.435507 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4727 12:42:12.438107 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4728 12:42:12.442124 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4729 12:42:12.442695 ==
4730 12:42:12.445849 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 12:42:12.452006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 12:42:12.452641 ==
4733 12:42:12.453018 DQS Delay:
4734 12:42:12.455475 DQS0 = 0, DQS1 = 0
4735 12:42:12.455944 DQM Delay:
4736 12:42:12.456314 DQM0 = 43, DQM1 = 39
4737 12:42:12.458957 DQ Delay:
4738 12:42:12.462056 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4739 12:42:12.464830 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4740 12:42:12.468630 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4741 12:42:12.471413 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4742 12:42:12.471886
4743 12:42:12.472254
4744 12:42:12.472594 ==
4745 12:42:12.474697 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 12:42:12.478396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 12:42:12.478965 ==
4748 12:42:12.479350
4749 12:42:12.479762
4750 12:42:12.481495 TX Vref Scan disable
4751 12:42:12.484322 == TX Byte 0 ==
4752 12:42:12.487767 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 12:42:12.490949 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 12:42:12.494063 == TX Byte 1 ==
4755 12:42:12.497478 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4756 12:42:12.500729 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4757 12:42:12.501336 ==
4758 12:42:12.504424 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 12:42:12.510996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 12:42:12.511474 ==
4761 12:42:12.511828
4762 12:42:12.512151
4763 12:42:12.512458 TX Vref Scan disable
4764 12:42:12.514640 == TX Byte 0 ==
4765 12:42:12.518078 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4766 12:42:12.524832 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4767 12:42:12.525267 == TX Byte 1 ==
4768 12:42:12.528210 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4769 12:42:12.534405 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4770 12:42:12.534840
4771 12:42:12.535181 [DATLAT]
4772 12:42:12.535533 Freq=600, CH1 RK1
4773 12:42:12.535853
4774 12:42:12.537602 DATLAT Default: 0x9
4775 12:42:12.538029 0, 0xFFFF, sum = 0
4776 12:42:12.541246 1, 0xFFFF, sum = 0
4777 12:42:12.544557 2, 0xFFFF, sum = 0
4778 12:42:12.544990 3, 0xFFFF, sum = 0
4779 12:42:12.547663 4, 0xFFFF, sum = 0
4780 12:42:12.548161 5, 0xFFFF, sum = 0
4781 12:42:12.551075 6, 0xFFFF, sum = 0
4782 12:42:12.551561 7, 0xFFFF, sum = 0
4783 12:42:12.554262 8, 0x0, sum = 1
4784 12:42:12.554750 9, 0x0, sum = 2
4785 12:42:12.557801 10, 0x0, sum = 3
4786 12:42:12.558290 11, 0x0, sum = 4
4787 12:42:12.558673 best_step = 9
4788 12:42:12.559055
4789 12:42:12.560852 ==
4790 12:42:12.563872 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 12:42:12.567821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 12:42:12.568245 ==
4793 12:42:12.568577 RX Vref Scan: 0
4794 12:42:12.568910
4795 12:42:12.570566 RX Vref 0 -> 0, step: 1
4796 12:42:12.570986
4797 12:42:12.573908 RX Delay -179 -> 252, step: 8
4798 12:42:12.580724 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4799 12:42:12.583798 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4800 12:42:12.587210 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4801 12:42:12.590240 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4802 12:42:12.597256 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4803 12:42:12.600420 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4804 12:42:12.603521 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4805 12:42:12.606681 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4806 12:42:12.610153 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4807 12:42:12.616633 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4808 12:42:12.619815 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4809 12:42:12.623736 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4810 12:42:12.626584 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4811 12:42:12.633523 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4812 12:42:12.636871 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4813 12:42:12.639466 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4814 12:42:12.639920 ==
4815 12:42:12.642805 Dram Type= 6, Freq= 0, CH_1, rank 1
4816 12:42:12.650163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4817 12:42:12.650605 ==
4818 12:42:12.651052 DQS Delay:
4819 12:42:12.652648 DQS0 = 0, DQS1 = 0
4820 12:42:12.653086 DQM Delay:
4821 12:42:12.653528 DQM0 = 37, DQM1 = 35
4822 12:42:12.656118 DQ Delay:
4823 12:42:12.659283 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4824 12:42:12.662733 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4825 12:42:12.665848 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4826 12:42:12.669618 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4827 12:42:12.670059
4828 12:42:12.670501
4829 12:42:12.675590 [DQSOSCAuto] RK1, (LSB)MR18= 0x395e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4830 12:42:12.678997 CH1 RK1: MR19=808, MR18=395E
4831 12:42:12.685467 CH1_RK1: MR19=0x808, MR18=0x395E, DQSOSC=392, MR23=63, INC=170, DEC=113
4832 12:42:12.689247 [RxdqsGatingPostProcess] freq 600
4833 12:42:12.693092 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4834 12:42:12.695307 Pre-setting of DQS Precalculation
4835 12:42:12.702119 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4836 12:42:12.708850 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4837 12:42:12.716017 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4838 12:42:12.716679
4839 12:42:12.717036
4840 12:42:12.718465 [Calibration Summary] 1200 Mbps
4841 12:42:12.722653 CH 0, Rank 0
4842 12:42:12.723076 SW Impedance : PASS
4843 12:42:12.725847 DUTY Scan : NO K
4844 12:42:12.726266 ZQ Calibration : PASS
4845 12:42:12.728702 Jitter Meter : NO K
4846 12:42:12.731905 CBT Training : PASS
4847 12:42:12.732401 Write leveling : PASS
4848 12:42:12.735250 RX DQS gating : PASS
4849 12:42:12.738476 RX DQ/DQS(RDDQC) : PASS
4850 12:42:12.738988 TX DQ/DQS : PASS
4851 12:42:12.741957 RX DATLAT : PASS
4852 12:42:12.745747 RX DQ/DQS(Engine): PASS
4853 12:42:12.746169 TX OE : NO K
4854 12:42:12.748168 All Pass.
4855 12:42:12.748591
4856 12:42:12.748925 CH 0, Rank 1
4857 12:42:12.751739 SW Impedance : PASS
4858 12:42:12.752162 DUTY Scan : NO K
4859 12:42:12.754494 ZQ Calibration : PASS
4860 12:42:12.758045 Jitter Meter : NO K
4861 12:42:12.758466 CBT Training : PASS
4862 12:42:12.761392 Write leveling : PASS
4863 12:42:12.765486 RX DQS gating : PASS
4864 12:42:12.765911 RX DQ/DQS(RDDQC) : PASS
4865 12:42:12.768354 TX DQ/DQS : PASS
4866 12:42:12.771173 RX DATLAT : PASS
4867 12:42:12.771675 RX DQ/DQS(Engine): PASS
4868 12:42:12.774992 TX OE : NO K
4869 12:42:12.775556 All Pass.
4870 12:42:12.775901
4871 12:42:12.777778 CH 1, Rank 0
4872 12:42:12.778215 SW Impedance : PASS
4873 12:42:12.781232 DUTY Scan : NO K
4874 12:42:12.785016 ZQ Calibration : PASS
4875 12:42:12.785454 Jitter Meter : NO K
4876 12:42:12.787879 CBT Training : PASS
4877 12:42:12.791274 Write leveling : PASS
4878 12:42:12.791773 RX DQS gating : PASS
4879 12:42:12.794151 RX DQ/DQS(RDDQC) : PASS
4880 12:42:12.797685 TX DQ/DQS : PASS
4881 12:42:12.798114 RX DATLAT : PASS
4882 12:42:12.800876 RX DQ/DQS(Engine): PASS
4883 12:42:12.804340 TX OE : NO K
4884 12:42:12.804821 All Pass.
4885 12:42:12.805183
4886 12:42:12.805520 CH 1, Rank 1
4887 12:42:12.807530 SW Impedance : PASS
4888 12:42:12.810464 DUTY Scan : NO K
4889 12:42:12.810908 ZQ Calibration : PASS
4890 12:42:12.813859 Jitter Meter : NO K
4891 12:42:12.817465 CBT Training : PASS
4892 12:42:12.817925 Write leveling : PASS
4893 12:42:12.820266 RX DQS gating : PASS
4894 12:42:12.823648 RX DQ/DQS(RDDQC) : PASS
4895 12:42:12.824045 TX DQ/DQS : PASS
4896 12:42:12.827157 RX DATLAT : PASS
4897 12:42:12.830419 RX DQ/DQS(Engine): PASS
4898 12:42:12.830869 TX OE : NO K
4899 12:42:12.831229 All Pass.
4900 12:42:12.833379
4901 12:42:12.833813 DramC Write-DBI off
4902 12:42:12.836811 PER_BANK_REFRESH: Hybrid Mode
4903 12:42:12.837230 TX_TRACKING: ON
4904 12:42:12.846470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4905 12:42:12.849927 [FAST_K] Save calibration result to emmc
4906 12:42:12.853629 dramc_set_vcore_voltage set vcore to 662500
4907 12:42:12.856667 Read voltage for 933, 3
4908 12:42:12.857146 Vio18 = 0
4909 12:42:12.859541 Vcore = 662500
4910 12:42:12.859960 Vdram = 0
4911 12:42:12.860357 Vddq = 0
4912 12:42:12.862969 Vmddr = 0
4913 12:42:12.866304 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4914 12:42:12.872777 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4915 12:42:12.873229 MEM_TYPE=3, freq_sel=17
4916 12:42:12.876683 sv_algorithm_assistance_LP4_1600
4917 12:42:12.883410 ============ PULL DRAM RESETB DOWN ============
4918 12:42:12.886251 ========== PULL DRAM RESETB DOWN end =========
4919 12:42:12.889885 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4920 12:42:12.892801 ===================================
4921 12:42:12.896204 LPDDR4 DRAM CONFIGURATION
4922 12:42:12.899462 ===================================
4923 12:42:12.899911 EX_ROW_EN[0] = 0x0
4924 12:42:12.902208 EX_ROW_EN[1] = 0x0
4925 12:42:12.905845 LP4Y_EN = 0x0
4926 12:42:12.906287 WORK_FSP = 0x0
4927 12:42:12.909275 WL = 0x3
4928 12:42:12.909696 RL = 0x3
4929 12:42:12.912207 BL = 0x2
4930 12:42:12.912656 RPST = 0x0
4931 12:42:12.915643 RD_PRE = 0x0
4932 12:42:12.916079 WR_PRE = 0x1
4933 12:42:12.918994 WR_PST = 0x0
4934 12:42:12.919515 DBI_WR = 0x0
4935 12:42:12.922118 DBI_RD = 0x0
4936 12:42:12.922563 OTF = 0x1
4937 12:42:12.925549 ===================================
4938 12:42:12.929163 ===================================
4939 12:42:12.932299 ANA top config
4940 12:42:12.935718 ===================================
4941 12:42:12.938809 DLL_ASYNC_EN = 0
4942 12:42:12.939229 ALL_SLAVE_EN = 1
4943 12:42:12.942088 NEW_RANK_MODE = 1
4944 12:42:12.946937 DLL_IDLE_MODE = 1
4945 12:42:12.948560 LP45_APHY_COMB_EN = 1
4946 12:42:12.948971 TX_ODT_DIS = 1
4947 12:42:12.952358 NEW_8X_MODE = 1
4948 12:42:12.955147 ===================================
4949 12:42:12.958570 ===================================
4950 12:42:12.961950 data_rate = 1866
4951 12:42:12.965342 CKR = 1
4952 12:42:12.968429 DQ_P2S_RATIO = 8
4953 12:42:12.971913 ===================================
4954 12:42:12.975143 CA_P2S_RATIO = 8
4955 12:42:12.975660 DQ_CA_OPEN = 0
4956 12:42:12.978183 DQ_SEMI_OPEN = 0
4957 12:42:12.982036 CA_SEMI_OPEN = 0
4958 12:42:12.985050 CA_FULL_RATE = 0
4959 12:42:12.988113 DQ_CKDIV4_EN = 1
4960 12:42:12.991592 CA_CKDIV4_EN = 1
4961 12:42:12.992016 CA_PREDIV_EN = 0
4962 12:42:12.994609 PH8_DLY = 0
4963 12:42:12.998302 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4964 12:42:13.001549 DQ_AAMCK_DIV = 4
4965 12:42:13.004827 CA_AAMCK_DIV = 4
4966 12:42:13.007865 CA_ADMCK_DIV = 4
4967 12:42:13.011013 DQ_TRACK_CA_EN = 0
4968 12:42:13.011528 CA_PICK = 933
4969 12:42:13.014515 CA_MCKIO = 933
4970 12:42:13.017709 MCKIO_SEMI = 0
4971 12:42:13.021189 PLL_FREQ = 3732
4972 12:42:13.024480 DQ_UI_PI_RATIO = 32
4973 12:42:13.027635 CA_UI_PI_RATIO = 0
4974 12:42:13.031499 ===================================
4975 12:42:13.034515 ===================================
4976 12:42:13.034964 memory_type:LPDDR4
4977 12:42:13.037721 GP_NUM : 10
4978 12:42:13.041180 SRAM_EN : 1
4979 12:42:13.041635 MD32_EN : 0
4980 12:42:13.044386 ===================================
4981 12:42:13.047348 [ANA_INIT] >>>>>>>>>>>>>>
4982 12:42:13.051252 <<<<<< [CONFIGURE PHASE]: ANA_TX
4983 12:42:13.054529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4984 12:42:13.057341 ===================================
4985 12:42:13.060854 data_rate = 1866,PCW = 0X8f00
4986 12:42:13.064078 ===================================
4987 12:42:13.068233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4988 12:42:13.074055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 12:42:13.077269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 12:42:13.084704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4991 12:42:13.087293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4992 12:42:13.090128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4993 12:42:13.090583 [ANA_INIT] flow start
4994 12:42:13.093328 [ANA_INIT] PLL >>>>>>>>
4995 12:42:13.096792 [ANA_INIT] PLL <<<<<<<<
4996 12:42:13.097266 [ANA_INIT] MIDPI >>>>>>>>
4997 12:42:13.100258 [ANA_INIT] MIDPI <<<<<<<<
4998 12:42:13.103303 [ANA_INIT] DLL >>>>>>>>
4999 12:42:13.103786 [ANA_INIT] flow end
5000 12:42:13.109933 ============ LP4 DIFF to SE enter ============
5001 12:42:13.113829 ============ LP4 DIFF to SE exit ============
5002 12:42:13.116643 [ANA_INIT] <<<<<<<<<<<<<
5003 12:42:13.119654 [Flow] Enable top DCM control >>>>>
5004 12:42:13.123143 [Flow] Enable top DCM control <<<<<
5005 12:42:13.123620 Enable DLL master slave shuffle
5006 12:42:13.130001 ==============================================================
5007 12:42:13.133289 Gating Mode config
5008 12:42:13.136846 ==============================================================
5009 12:42:13.140006 Config description:
5010 12:42:13.149743 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5011 12:42:13.156803 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5012 12:42:13.159321 SELPH_MODE 0: By rank 1: By Phase
5013 12:42:13.165845 ==============================================================
5014 12:42:13.169505 GAT_TRACK_EN = 1
5015 12:42:13.172676 RX_GATING_MODE = 2
5016 12:42:13.176013 RX_GATING_TRACK_MODE = 2
5017 12:42:13.179598 SELPH_MODE = 1
5018 12:42:13.182909 PICG_EARLY_EN = 1
5019 12:42:13.186493 VALID_LAT_VALUE = 1
5020 12:42:13.188865 ==============================================================
5021 12:42:13.192655 Enter into Gating configuration >>>>
5022 12:42:13.195997 Exit from Gating configuration <<<<
5023 12:42:13.199334 Enter into DVFS_PRE_config >>>>>
5024 12:42:13.212198 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5025 12:42:13.212764 Exit from DVFS_PRE_config <<<<<
5026 12:42:13.215593 Enter into PICG configuration >>>>
5027 12:42:13.218793 Exit from PICG configuration <<<<
5028 12:42:13.222323 [RX_INPUT] configuration >>>>>
5029 12:42:13.225658 [RX_INPUT] configuration <<<<<
5030 12:42:13.232478 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5031 12:42:13.235274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5032 12:42:13.242354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 12:42:13.248887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 12:42:13.255615 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 12:42:13.262142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 12:42:13.265392 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5037 12:42:13.268610 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5038 12:42:13.271795 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5039 12:42:13.278217 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5040 12:42:13.281521 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5041 12:42:13.285721 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5042 12:42:13.287660 ===================================
5043 12:42:13.291073 LPDDR4 DRAM CONFIGURATION
5044 12:42:13.294591 ===================================
5045 12:42:13.297996 EX_ROW_EN[0] = 0x0
5046 12:42:13.298562 EX_ROW_EN[1] = 0x0
5047 12:42:13.301275 LP4Y_EN = 0x0
5048 12:42:13.301866 WORK_FSP = 0x0
5049 12:42:13.304857 WL = 0x3
5050 12:42:13.305425 RL = 0x3
5051 12:42:13.307654 BL = 0x2
5052 12:42:13.308125 RPST = 0x0
5053 12:42:13.310834 RD_PRE = 0x0
5054 12:42:13.311337 WR_PRE = 0x1
5055 12:42:13.314450 WR_PST = 0x0
5056 12:42:13.317663 DBI_WR = 0x0
5057 12:42:13.318139 DBI_RD = 0x0
5058 12:42:13.320664 OTF = 0x1
5059 12:42:13.324166 ===================================
5060 12:42:13.327483 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5061 12:42:13.331123 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5062 12:42:13.333989 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5063 12:42:13.337489 ===================================
5064 12:42:13.340741 LPDDR4 DRAM CONFIGURATION
5065 12:42:13.343828 ===================================
5066 12:42:13.347283 EX_ROW_EN[0] = 0x10
5067 12:42:13.347999 EX_ROW_EN[1] = 0x0
5068 12:42:13.350543 LP4Y_EN = 0x0
5069 12:42:13.351180 WORK_FSP = 0x0
5070 12:42:13.353824 WL = 0x3
5071 12:42:13.353907 RL = 0x3
5072 12:42:13.356534 BL = 0x2
5073 12:42:13.356617 RPST = 0x0
5074 12:42:13.360640 RD_PRE = 0x0
5075 12:42:13.360722 WR_PRE = 0x1
5076 12:42:13.363286 WR_PST = 0x0
5077 12:42:13.367504 DBI_WR = 0x0
5078 12:42:13.367667 DBI_RD = 0x0
5079 12:42:13.370123 OTF = 0x1
5080 12:42:13.374189 ===================================
5081 12:42:13.377088 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5082 12:42:13.382333 nWR fixed to 30
5083 12:42:13.385219 [ModeRegInit_LP4] CH0 RK0
5084 12:42:13.385368 [ModeRegInit_LP4] CH0 RK1
5085 12:42:13.388894 [ModeRegInit_LP4] CH1 RK0
5086 12:42:13.392163 [ModeRegInit_LP4] CH1 RK1
5087 12:42:13.392291 match AC timing 9
5088 12:42:13.399233 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5089 12:42:13.402653 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5090 12:42:13.404962 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5091 12:42:13.411538 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5092 12:42:13.415491 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5093 12:42:13.415783 ==
5094 12:42:13.418144 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 12:42:13.421583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 12:42:13.421947 ==
5097 12:42:13.428191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5098 12:42:13.435069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5099 12:42:13.438605 [CA 0] Center 37 (7~68) winsize 62
5100 12:42:13.441565 [CA 1] Center 37 (7~68) winsize 62
5101 12:42:13.444822 [CA 2] Center 34 (4~65) winsize 62
5102 12:42:13.448093 [CA 3] Center 34 (4~64) winsize 61
5103 12:42:13.451576 [CA 4] Center 33 (3~64) winsize 62
5104 12:42:13.454913 [CA 5] Center 33 (3~63) winsize 61
5105 12:42:13.455340
5106 12:42:13.458139 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5107 12:42:13.458669
5108 12:42:13.461662 [CATrainingPosCal] consider 1 rank data
5109 12:42:13.464705 u2DelayCellTimex100 = 270/100 ps
5110 12:42:13.467859 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5111 12:42:13.471628 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5112 12:42:13.474555 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5113 12:42:13.481602 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5114 12:42:13.485085 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5115 12:42:13.487662 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5116 12:42:13.488095
5117 12:42:13.490841 CA PerBit enable=1, Macro0, CA PI delay=33
5118 12:42:13.491282
5119 12:42:13.494048 [CBTSetCACLKResult] CA Dly = 33
5120 12:42:13.494473 CS Dly: 6 (0~37)
5121 12:42:13.494812 ==
5122 12:42:13.497994 Dram Type= 6, Freq= 0, CH_0, rank 1
5123 12:42:13.504838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 12:42:13.505365 ==
5125 12:42:13.507870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5126 12:42:13.514153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5127 12:42:13.517585 [CA 0] Center 37 (7~68) winsize 62
5128 12:42:13.520719 [CA 1] Center 37 (7~68) winsize 62
5129 12:42:13.524048 [CA 2] Center 34 (4~65) winsize 62
5130 12:42:13.526847 [CA 3] Center 34 (4~65) winsize 62
5131 12:42:13.530840 [CA 4] Center 33 (3~64) winsize 62
5132 12:42:13.534011 [CA 5] Center 32 (2~63) winsize 62
5133 12:42:13.534545
5134 12:42:13.537006 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5135 12:42:13.537532
5136 12:42:13.540910 [CATrainingPosCal] consider 2 rank data
5137 12:42:13.543939 u2DelayCellTimex100 = 270/100 ps
5138 12:42:13.547110 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5139 12:42:13.553824 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5140 12:42:13.556532 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5141 12:42:13.560728 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5142 12:42:13.563524 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5143 12:42:13.566949 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5144 12:42:13.567605
5145 12:42:13.569729 CA PerBit enable=1, Macro0, CA PI delay=33
5146 12:42:13.570156
5147 12:42:13.573382 [CBTSetCACLKResult] CA Dly = 33
5148 12:42:13.576249 CS Dly: 7 (0~39)
5149 12:42:13.576672
5150 12:42:13.579472 ----->DramcWriteLeveling(PI) begin...
5151 12:42:13.579908 ==
5152 12:42:13.582912 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 12:42:13.586105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 12:42:13.586721 ==
5155 12:42:13.589518 Write leveling (Byte 0): 31 => 31
5156 12:42:13.593084 Write leveling (Byte 1): 29 => 29
5157 12:42:13.596213 DramcWriteLeveling(PI) end<-----
5158 12:42:13.596643
5159 12:42:13.596983 ==
5160 12:42:13.599643 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 12:42:13.603178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 12:42:13.603675 ==
5163 12:42:13.606526 [Gating] SW mode calibration
5164 12:42:13.612864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5165 12:42:13.619722 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5166 12:42:13.622748 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5167 12:42:13.625833 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 12:42:13.632515 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 12:42:13.636625 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 12:42:13.639437 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 12:42:13.645735 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 12:42:13.649423 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5173 12:42:13.652376 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5174 12:42:13.659519 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5175 12:42:13.662465 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5176 12:42:13.668581 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 12:42:13.672092 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 12:42:13.675096 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 12:42:13.682061 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 12:42:13.685133 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 12:42:13.688677 0 15 28 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
5182 12:42:13.695490 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5183 12:42:13.698410 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 12:42:13.702078 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 12:42:13.708034 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 12:42:13.711576 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:42:13.715120 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:42:13.721452 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 12:42:13.724866 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5190 12:42:13.728057 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5191 12:42:13.734873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5192 12:42:13.738300 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:42:13.741578 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:42:13.747643 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:42:13.751609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:42:13.754556 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:42:13.761543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:42:13.764108 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:42:13.767890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:42:13.775196 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:42:13.777706 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:42:13.780968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:42:13.786887 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:42:13.790653 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:42:13.793790 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:42:13.800650 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5207 12:42:13.801246 Total UI for P1: 0, mck2ui 16
5208 12:42:13.807714 best dqsien dly found for B0: ( 1, 2, 30)
5209 12:42:13.810494 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 12:42:13.813437 Total UI for P1: 0, mck2ui 16
5211 12:42:13.817119 best dqsien dly found for B1: ( 1, 3, 0)
5212 12:42:13.820166 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5213 12:42:13.823550 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5214 12:42:13.824025
5215 12:42:13.826437 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5216 12:42:13.830137 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5217 12:42:13.833708 [Gating] SW calibration Done
5218 12:42:13.834311 ==
5219 12:42:13.836041 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 12:42:13.839392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 12:42:13.842536 ==
5222 12:42:13.842959 RX Vref Scan: 0
5223 12:42:13.843299
5224 12:42:13.846603 RX Vref 0 -> 0, step: 1
5225 12:42:13.847027
5226 12:42:13.847427 RX Delay -80 -> 252, step: 8
5227 12:42:13.853485 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5228 12:42:13.856594 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5229 12:42:13.859686 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5230 12:42:13.862977 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5231 12:42:13.866061 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5232 12:42:13.869797 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5233 12:42:13.876211 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5234 12:42:13.879849 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5235 12:42:13.883060 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5236 12:42:13.886588 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5237 12:42:13.889170 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5238 12:42:13.895812 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5239 12:42:13.899438 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5240 12:42:13.902668 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5241 12:42:13.906311 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5242 12:42:13.909596 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5243 12:42:13.910156 ==
5244 12:42:13.912207 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 12:42:13.919270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 12:42:13.919882 ==
5247 12:42:13.920260 DQS Delay:
5248 12:42:13.922298 DQS0 = 0, DQS1 = 0
5249 12:42:13.922772 DQM Delay:
5250 12:42:13.925985 DQM0 = 99, DQM1 = 89
5251 12:42:13.926555 DQ Delay:
5252 12:42:13.930080 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5253 12:42:13.932093 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5254 12:42:13.935991 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5255 12:42:13.939060 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5256 12:42:13.939681
5257 12:42:13.940064
5258 12:42:13.940416 ==
5259 12:42:13.942241 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 12:42:13.945379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 12:42:13.945846 ==
5262 12:42:13.946190
5263 12:42:13.946508
5264 12:42:13.949786 TX Vref Scan disable
5265 12:42:13.952202 == TX Byte 0 ==
5266 12:42:13.955503 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5267 12:42:13.959108 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5268 12:42:13.962391 == TX Byte 1 ==
5269 12:42:13.965408 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5270 12:42:13.968269 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5271 12:42:13.968727 ==
5272 12:42:13.972665 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 12:42:13.978610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 12:42:13.978695 ==
5275 12:42:13.978762
5276 12:42:13.978822
5277 12:42:13.978881 TX Vref Scan disable
5278 12:42:13.981747 == TX Byte 0 ==
5279 12:42:13.985192 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5280 12:42:13.991603 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5281 12:42:13.991708 == TX Byte 1 ==
5282 12:42:13.995267 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5283 12:42:14.001778 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5284 12:42:14.001978
5285 12:42:14.002090 [DATLAT]
5286 12:42:14.002189 Freq=933, CH0 RK0
5287 12:42:14.002285
5288 12:42:14.004886 DATLAT Default: 0xd
5289 12:42:14.008073 0, 0xFFFF, sum = 0
5290 12:42:14.008214 1, 0xFFFF, sum = 0
5291 12:42:14.011521 2, 0xFFFF, sum = 0
5292 12:42:14.011679 3, 0xFFFF, sum = 0
5293 12:42:14.015225 4, 0xFFFF, sum = 0
5294 12:42:14.015505 5, 0xFFFF, sum = 0
5295 12:42:14.018418 6, 0xFFFF, sum = 0
5296 12:42:14.018683 7, 0xFFFF, sum = 0
5297 12:42:14.021771 8, 0xFFFF, sum = 0
5298 12:42:14.021993 9, 0xFFFF, sum = 0
5299 12:42:14.024862 10, 0x0, sum = 1
5300 12:42:14.025197 11, 0x0, sum = 2
5301 12:42:14.028368 12, 0x0, sum = 3
5302 12:42:14.028704 13, 0x0, sum = 4
5303 12:42:14.031827 best_step = 11
5304 12:42:14.032232
5305 12:42:14.032492 ==
5306 12:42:14.035244 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 12:42:14.038598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 12:42:14.039096 ==
5309 12:42:14.039461 RX Vref Scan: 1
5310 12:42:14.039795
5311 12:42:14.041692 RX Vref 0 -> 0, step: 1
5312 12:42:14.042114
5313 12:42:14.044827 RX Delay -61 -> 252, step: 4
5314 12:42:14.045249
5315 12:42:14.048600 Set Vref, RX VrefLevel [Byte0]: 51
5316 12:42:14.051736 [Byte1]: 58
5317 12:42:14.054827
5318 12:42:14.055355 Final RX Vref Byte 0 = 51 to rank0
5319 12:42:14.058460 Final RX Vref Byte 1 = 58 to rank0
5320 12:42:14.061753 Final RX Vref Byte 0 = 51 to rank1
5321 12:42:14.065080 Final RX Vref Byte 1 = 58 to rank1==
5322 12:42:14.067812 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 12:42:14.074985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 12:42:14.075594 ==
5325 12:42:14.075950 DQS Delay:
5326 12:42:14.077938 DQS0 = 0, DQS1 = 0
5327 12:42:14.078364 DQM Delay:
5328 12:42:14.078701 DQM0 = 98, DQM1 = 87
5329 12:42:14.081979 DQ Delay:
5330 12:42:14.084496 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5331 12:42:14.088026 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5332 12:42:14.091325 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5333 12:42:14.095156 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5334 12:42:14.095790
5335 12:42:14.096135
5336 12:42:14.101350 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5337 12:42:14.104144 CH0 RK0: MR19=505, MR18=1A15
5338 12:42:14.110204 CH0_RK0: MR19=0x505, MR18=0x1A15, DQSOSC=413, MR23=63, INC=63, DEC=42
5339 12:42:14.110633
5340 12:42:14.113638 ----->DramcWriteLeveling(PI) begin...
5341 12:42:14.114069 ==
5342 12:42:14.117229 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 12:42:14.120536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 12:42:14.120964 ==
5345 12:42:14.123649 Write leveling (Byte 0): 30 => 30
5346 12:42:14.127032 Write leveling (Byte 1): 29 => 29
5347 12:42:14.130352 DramcWriteLeveling(PI) end<-----
5348 12:42:14.130776
5349 12:42:14.131111 ==
5350 12:42:14.133859 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 12:42:14.140765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 12:42:14.141302 ==
5353 12:42:14.141642 [Gating] SW mode calibration
5354 12:42:14.150712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 12:42:14.154000 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 12:42:14.160948 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5357 12:42:14.163882 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 12:42:14.167743 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 12:42:14.173883 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 12:42:14.176448 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:42:14.179707 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 12:42:14.186386 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5363 12:42:14.189673 0 14 28 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
5364 12:42:14.193302 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5365 12:42:14.200026 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5366 12:42:14.202951 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 12:42:14.205973 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:42:14.213744 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 12:42:14.217058 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 12:42:14.219313 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5371 12:42:14.226334 0 15 28 | B1->B0 | 2d2d 4343 | 1 0 | (0 0) (0 0)
5372 12:42:14.229879 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5373 12:42:14.232989 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 12:42:14.239153 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 12:42:14.242509 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:42:14.245755 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:42:14.248947 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:42:14.255348 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:42:14.258693 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5380 12:42:14.261957 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5381 12:42:14.268634 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:42:14.272049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:42:14.275806 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:42:14.281848 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:42:14.285847 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:42:14.292065 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:42:14.294958 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:42:14.298421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:42:14.304906 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:42:14.308347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:42:14.311467 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:42:14.318620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:42:14.321991 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:42:14.325432 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:42:14.328695 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5396 12:42:14.335062 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5397 12:42:14.338302 Total UI for P1: 0, mck2ui 16
5398 12:42:14.341772 best dqsien dly found for B0: ( 1, 2, 28)
5399 12:42:14.345041 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 12:42:14.348248 Total UI for P1: 0, mck2ui 16
5401 12:42:14.351519 best dqsien dly found for B1: ( 1, 3, 0)
5402 12:42:14.354679 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5403 12:42:14.358728 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5404 12:42:14.359278
5405 12:42:14.361398 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5406 12:42:14.367889 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5407 12:42:14.368421 [Gating] SW calibration Done
5408 12:42:14.368765 ==
5409 12:42:14.371015 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 12:42:14.377446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 12:42:14.377876 ==
5412 12:42:14.378213 RX Vref Scan: 0
5413 12:42:14.378525
5414 12:42:14.381245 RX Vref 0 -> 0, step: 1
5415 12:42:14.381671
5416 12:42:14.384244 RX Delay -80 -> 252, step: 8
5417 12:42:14.387842 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5418 12:42:14.390891 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5419 12:42:14.394028 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5420 12:42:14.397225 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5421 12:42:14.404454 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5422 12:42:14.408119 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5423 12:42:14.410534 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5424 12:42:14.414502 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5425 12:42:14.417452 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5426 12:42:14.423844 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5427 12:42:14.427319 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5428 12:42:14.430165 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5429 12:42:14.433543 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5430 12:42:14.438119 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5431 12:42:14.440517 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5432 12:42:14.447814 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5433 12:42:14.448241 ==
5434 12:42:14.450914 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 12:42:14.453761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 12:42:14.454291 ==
5437 12:42:14.454630 DQS Delay:
5438 12:42:14.457404 DQS0 = 0, DQS1 = 0
5439 12:42:14.457935 DQM Delay:
5440 12:42:14.460448 DQM0 = 97, DQM1 = 91
5441 12:42:14.460976 DQ Delay:
5442 12:42:14.463357 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5443 12:42:14.466475 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5444 12:42:14.469911 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5445 12:42:14.473344 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5446 12:42:14.473873
5447 12:42:14.474210
5448 12:42:14.474520 ==
5449 12:42:14.476584 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 12:42:14.480221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 12:42:14.483530 ==
5452 12:42:14.484059
5453 12:42:14.484400
5454 12:42:14.484713 TX Vref Scan disable
5455 12:42:14.486675 == TX Byte 0 ==
5456 12:42:14.490337 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5457 12:42:14.493535 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5458 12:42:14.496317 == TX Byte 1 ==
5459 12:42:14.499467 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5460 12:42:14.502981 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5461 12:42:14.506246 ==
5462 12:42:14.509390 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 12:42:14.512606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 12:42:14.513035 ==
5465 12:42:14.513372
5466 12:42:14.513682
5467 12:42:14.516252 TX Vref Scan disable
5468 12:42:14.516679 == TX Byte 0 ==
5469 12:42:14.522826 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5470 12:42:14.525844 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5471 12:42:14.526290 == TX Byte 1 ==
5472 12:42:14.532895 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5473 12:42:14.535719 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5474 12:42:14.536142
5475 12:42:14.536476 [DATLAT]
5476 12:42:14.539023 Freq=933, CH0 RK1
5477 12:42:14.539491
5478 12:42:14.539835 DATLAT Default: 0xb
5479 12:42:14.542192 0, 0xFFFF, sum = 0
5480 12:42:14.542624 1, 0xFFFF, sum = 0
5481 12:42:14.545655 2, 0xFFFF, sum = 0
5482 12:42:14.548572 3, 0xFFFF, sum = 0
5483 12:42:14.549001 4, 0xFFFF, sum = 0
5484 12:42:14.551901 5, 0xFFFF, sum = 0
5485 12:42:14.551985 6, 0xFFFF, sum = 0
5486 12:42:14.555532 7, 0xFFFF, sum = 0
5487 12:42:14.555622 8, 0xFFFF, sum = 0
5488 12:42:14.558787 9, 0xFFFF, sum = 0
5489 12:42:14.558876 10, 0x0, sum = 1
5490 12:42:14.561584 11, 0x0, sum = 2
5491 12:42:14.561681 12, 0x0, sum = 3
5492 12:42:14.565911 13, 0x0, sum = 4
5493 12:42:14.566342 best_step = 11
5494 12:42:14.566678
5495 12:42:14.566989 ==
5496 12:42:14.568986 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 12:42:14.572538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 12:42:14.572966 ==
5499 12:42:14.575167 RX Vref Scan: 0
5500 12:42:14.575623
5501 12:42:14.578656 RX Vref 0 -> 0, step: 1
5502 12:42:14.579185
5503 12:42:14.579586 RX Delay -53 -> 252, step: 4
5504 12:42:14.586617 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5505 12:42:14.590040 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5506 12:42:14.593511 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5507 12:42:14.596647 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5508 12:42:14.599272 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5509 12:42:14.603083 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5510 12:42:14.609369 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5511 12:42:14.612820 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5512 12:42:14.616251 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5513 12:42:14.619973 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5514 12:42:14.623231 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5515 12:42:14.629356 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5516 12:42:14.632859 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5517 12:42:14.635812 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5518 12:42:14.639293 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5519 12:42:14.642172 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5520 12:42:14.642619 ==
5521 12:42:14.645578 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 12:42:14.651710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 12:42:14.651797 ==
5524 12:42:14.651885 DQS Delay:
5525 12:42:14.656379 DQS0 = 0, DQS1 = 0
5526 12:42:14.656465 DQM Delay:
5527 12:42:14.658610 DQM0 = 96, DQM1 = 88
5528 12:42:14.658695 DQ Delay:
5529 12:42:14.661883 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5530 12:42:14.664741 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =106
5531 12:42:14.668316 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5532 12:42:14.671249 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5533 12:42:14.671359
5534 12:42:14.671487
5535 12:42:14.678122 [DQSOSCAuto] RK1, (LSB)MR18= 0x1713, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5536 12:42:14.681504 CH0 RK1: MR19=505, MR18=1713
5537 12:42:14.687786 CH0_RK1: MR19=0x505, MR18=0x1713, DQSOSC=414, MR23=63, INC=63, DEC=42
5538 12:42:14.691715 [RxdqsGatingPostProcess] freq 933
5539 12:42:14.698168 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 12:42:14.701070 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 12:42:14.701211 best DQS1 dly(2T, 0.5T) = (0, 11)
5542 12:42:14.704922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 12:42:14.707725 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5544 12:42:14.711068 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 12:42:14.714206 best DQS1 dly(2T, 0.5T) = (0, 11)
5546 12:42:14.717772 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 12:42:14.721122 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5548 12:42:14.724203 Pre-setting of DQS Precalculation
5549 12:42:14.730572 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 12:42:14.731000 ==
5551 12:42:14.733996 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 12:42:14.737244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 12:42:14.737720 ==
5554 12:42:14.744645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 12:42:14.751224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5556 12:42:14.754137 [CA 0] Center 36 (6~67) winsize 62
5557 12:42:14.757715 [CA 1] Center 36 (6~67) winsize 62
5558 12:42:14.760589 [CA 2] Center 34 (4~65) winsize 62
5559 12:42:14.763645 [CA 3] Center 34 (4~65) winsize 62
5560 12:42:14.768027 [CA 4] Center 34 (4~65) winsize 62
5561 12:42:14.770293 [CA 5] Center 33 (3~64) winsize 62
5562 12:42:14.770916
5563 12:42:14.773784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5564 12:42:14.774396
5565 12:42:14.777514 [CATrainingPosCal] consider 1 rank data
5566 12:42:14.780711 u2DelayCellTimex100 = 270/100 ps
5567 12:42:14.783630 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 12:42:14.786700 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 12:42:14.790220 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 12:42:14.793990 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 12:42:14.797558 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 12:42:14.800439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 12:42:14.800616
5574 12:42:14.806583 CA PerBit enable=1, Macro0, CA PI delay=33
5575 12:42:14.806759
5576 12:42:14.806897 [CBTSetCACLKResult] CA Dly = 33
5577 12:42:14.810120 CS Dly: 5 (0~36)
5578 12:42:14.810203 ==
5579 12:42:14.813017 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 12:42:14.816810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 12:42:14.816895 ==
5582 12:42:14.822969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 12:42:14.830267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5584 12:42:14.833007 [CA 0] Center 36 (6~67) winsize 62
5585 12:42:14.836375 [CA 1] Center 36 (6~67) winsize 62
5586 12:42:14.839484 [CA 2] Center 34 (4~65) winsize 62
5587 12:42:14.842972 [CA 3] Center 33 (3~64) winsize 62
5588 12:42:14.846155 [CA 4] Center 33 (3~64) winsize 62
5589 12:42:14.849782 [CA 5] Center 33 (3~64) winsize 62
5590 12:42:14.849865
5591 12:42:14.852539 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5592 12:42:14.852622
5593 12:42:14.855776 [CATrainingPosCal] consider 2 rank data
5594 12:42:14.858990 u2DelayCellTimex100 = 270/100 ps
5595 12:42:14.862488 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5596 12:42:14.865536 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5597 12:42:14.869516 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5598 12:42:14.872821 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5599 12:42:14.878851 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5600 12:42:14.882525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5601 12:42:14.882609
5602 12:42:14.885669 CA PerBit enable=1, Macro0, CA PI delay=33
5603 12:42:14.885752
5604 12:42:14.888552 [CBTSetCACLKResult] CA Dly = 33
5605 12:42:14.888636 CS Dly: 6 (0~38)
5606 12:42:14.888702
5607 12:42:14.891961 ----->DramcWriteLeveling(PI) begin...
5608 12:42:14.892045 ==
5609 12:42:14.895574 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 12:42:14.902120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 12:42:14.902204 ==
5612 12:42:14.905214 Write leveling (Byte 0): 29 => 29
5613 12:42:14.908408 Write leveling (Byte 1): 29 => 29
5614 12:42:14.911911 DramcWriteLeveling(PI) end<-----
5615 12:42:14.911994
5616 12:42:14.912059 ==
5617 12:42:14.914839 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 12:42:14.918287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 12:42:14.918374 ==
5620 12:42:14.921651 [Gating] SW mode calibration
5621 12:42:14.928062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 12:42:14.934712 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 12:42:14.938457 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 12:42:14.941533 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 12:42:14.947857 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 12:42:14.951342 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 12:42:14.954726 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 12:42:14.961454 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 12:42:14.964442 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5630 12:42:14.967870 0 14 28 | B1->B0 | 2e2e 2424 | 1 1 | (1 0) (1 0)
5631 12:42:14.974483 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 12:42:14.977621 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 12:42:14.981227 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 12:42:14.987929 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 12:42:14.990703 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 12:42:14.995187 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 12:42:15.000946 0 15 24 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5638 12:42:15.004435 0 15 28 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (0 0)
5639 12:42:15.007616 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 12:42:15.014126 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 12:42:15.017822 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 12:42:15.021087 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 12:42:15.027807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 12:42:15.030596 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:42:15.034259 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5646 12:42:15.042502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5647 12:42:15.043885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:42:15.046637 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:42:15.053418 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:42:15.057080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:42:15.060316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:42:15.066839 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:42:15.069875 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:42:15.073093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:42:15.079969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:42:15.083287 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:42:15.086516 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:42:15.093289 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:42:15.096269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:42:15.100004 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:42:15.106055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 12:42:15.109481 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5663 12:42:15.112646 Total UI for P1: 0, mck2ui 16
5664 12:42:15.116224 best dqsien dly found for B1: ( 1, 2, 24)
5665 12:42:15.119157 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 12:42:15.122895 Total UI for P1: 0, mck2ui 16
5667 12:42:15.125856 best dqsien dly found for B0: ( 1, 2, 26)
5668 12:42:15.129237 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5669 12:42:15.132585 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5670 12:42:15.133017
5671 12:42:15.139188 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5672 12:42:15.142226 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5673 12:42:15.145898 [Gating] SW calibration Done
5674 12:42:15.146327 ==
5675 12:42:15.148969 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 12:42:15.152590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 12:42:15.153027 ==
5678 12:42:15.153523 RX Vref Scan: 0
5679 12:42:15.153982
5680 12:42:15.155247 RX Vref 0 -> 0, step: 1
5681 12:42:15.155761
5682 12:42:15.159649 RX Delay -80 -> 252, step: 8
5683 12:42:15.162386 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5684 12:42:15.165257 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5685 12:42:15.171969 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5686 12:42:15.175200 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5687 12:42:15.178767 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5688 12:42:15.181588 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5689 12:42:15.184915 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5690 12:42:15.188304 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5691 12:42:15.194751 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5692 12:42:15.198456 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5693 12:42:15.201303 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5694 12:42:15.205076 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5695 12:42:15.208292 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5696 12:42:15.214534 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5697 12:42:15.217963 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5698 12:42:15.221141 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5699 12:42:15.221570 ==
5700 12:42:15.224541 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:42:15.227858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:42:15.228306 ==
5703 12:42:15.230952 DQS Delay:
5704 12:42:15.231400 DQS0 = 0, DQS1 = 0
5705 12:42:15.234904 DQM Delay:
5706 12:42:15.235331 DQM0 = 99, DQM1 = 95
5707 12:42:15.235735 DQ Delay:
5708 12:42:15.238061 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5709 12:42:15.240759 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5710 12:42:15.244443 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5711 12:42:15.250811 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5712 12:42:15.251240
5713 12:42:15.251615
5714 12:42:15.251930 ==
5715 12:42:15.254239 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 12:42:15.257732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 12:42:15.258165 ==
5718 12:42:15.258512
5719 12:42:15.258827
5720 12:42:15.260497 TX Vref Scan disable
5721 12:42:15.260928 == TX Byte 0 ==
5722 12:42:15.267412 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5723 12:42:15.270427 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5724 12:42:15.270854 == TX Byte 1 ==
5725 12:42:15.277741 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5726 12:42:15.280597 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5727 12:42:15.281121 ==
5728 12:42:15.284267 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 12:42:15.287676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 12:42:15.288155 ==
5731 12:42:15.291140
5732 12:42:15.291620
5733 12:42:15.291964 TX Vref Scan disable
5734 12:42:15.293887 == TX Byte 0 ==
5735 12:42:15.297200 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5736 12:42:15.303707 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5737 12:42:15.303792 == TX Byte 1 ==
5738 12:42:15.306391 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5739 12:42:15.312727 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5740 12:42:15.312812
5741 12:42:15.312877 [DATLAT]
5742 12:42:15.312937 Freq=933, CH1 RK0
5743 12:42:15.312996
5744 12:42:15.316533 DATLAT Default: 0xd
5745 12:42:15.316616 0, 0xFFFF, sum = 0
5746 12:42:15.319314 1, 0xFFFF, sum = 0
5747 12:42:15.322899 2, 0xFFFF, sum = 0
5748 12:42:15.322984 3, 0xFFFF, sum = 0
5749 12:42:15.326447 4, 0xFFFF, sum = 0
5750 12:42:15.326532 5, 0xFFFF, sum = 0
5751 12:42:15.329473 6, 0xFFFF, sum = 0
5752 12:42:15.329558 7, 0xFFFF, sum = 0
5753 12:42:15.332702 8, 0xFFFF, sum = 0
5754 12:42:15.332787 9, 0xFFFF, sum = 0
5755 12:42:15.336449 10, 0x0, sum = 1
5756 12:42:15.336533 11, 0x0, sum = 2
5757 12:42:15.339249 12, 0x0, sum = 3
5758 12:42:15.339334 13, 0x0, sum = 4
5759 12:42:15.339441 best_step = 11
5760 12:42:15.342741
5761 12:42:15.342833 ==
5762 12:42:15.346168 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 12:42:15.349545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 12:42:15.349738 ==
5765 12:42:15.349831 RX Vref Scan: 1
5766 12:42:15.349912
5767 12:42:15.352380 RX Vref 0 -> 0, step: 1
5768 12:42:15.352515
5769 12:42:15.356616 RX Delay -53 -> 252, step: 4
5770 12:42:15.356770
5771 12:42:15.359278 Set Vref, RX VrefLevel [Byte0]: 47
5772 12:42:15.362741 [Byte1]: 51
5773 12:42:15.366047
5774 12:42:15.366266 Final RX Vref Byte 0 = 47 to rank0
5775 12:42:15.369280 Final RX Vref Byte 1 = 51 to rank0
5776 12:42:15.372500 Final RX Vref Byte 0 = 47 to rank1
5777 12:42:15.375758 Final RX Vref Byte 1 = 51 to rank1==
5778 12:42:15.379303 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 12:42:15.385742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 12:42:15.386089 ==
5781 12:42:15.386300 DQS Delay:
5782 12:42:15.389090 DQS0 = 0, DQS1 = 0
5783 12:42:15.389333 DQM Delay:
5784 12:42:15.389527 DQM0 = 97, DQM1 = 94
5785 12:42:15.392264 DQ Delay:
5786 12:42:15.395585 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =98
5787 12:42:15.399151 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5788 12:42:15.402297 DQ8 =80, DQ9 =86, DQ10 =92, DQ11 =88
5789 12:42:15.405528 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5790 12:42:15.405611
5791 12:42:15.405676
5792 12:42:15.411801 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5793 12:42:15.415233 CH1 RK0: MR19=505, MR18=D1C
5794 12:42:15.421418 CH1_RK0: MR19=0x505, MR18=0xD1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5795 12:42:15.421501
5796 12:42:15.425340 ----->DramcWriteLeveling(PI) begin...
5797 12:42:15.425425 ==
5798 12:42:15.427975 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 12:42:15.431493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 12:42:15.431577 ==
5801 12:42:15.434666 Write leveling (Byte 0): 24 => 24
5802 12:42:15.438198 Write leveling (Byte 1): 26 => 26
5803 12:42:15.441238 DramcWriteLeveling(PI) end<-----
5804 12:42:15.441322
5805 12:42:15.441387 ==
5806 12:42:15.444858 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 12:42:15.451335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 12:42:15.451431 ==
5809 12:42:15.451498 [Gating] SW mode calibration
5810 12:42:15.461477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 12:42:15.464753 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 12:42:15.471078 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 12:42:15.474549 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 12:42:15.477384 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 12:42:15.484184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 12:42:15.487570 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 12:42:15.490971 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5818 12:42:15.497527 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5819 12:42:15.500850 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5820 12:42:15.504235 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 12:42:15.510525 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 12:42:15.514320 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 12:42:15.517055 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 12:42:15.523764 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 12:42:15.526949 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 12:42:15.530364 0 15 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
5827 12:42:15.537019 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5828 12:42:15.540318 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 12:42:15.543776 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 12:42:15.550115 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:42:15.553101 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 12:42:15.556413 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 12:42:15.563538 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:42:15.566314 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5835 12:42:15.569888 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5836 12:42:15.576098 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:42:15.579931 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:42:15.582833 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:42:15.589487 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:42:15.593236 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:42:15.596124 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:42:15.602522 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:42:15.606023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:42:15.609568 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:42:15.616832 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:42:15.618988 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:42:15.622398 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:42:15.629230 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:42:15.632489 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:42:15.636050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5851 12:42:15.642381 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5852 12:42:15.645301 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:42:15.648776 Total UI for P1: 0, mck2ui 16
5854 12:42:15.652257 best dqsien dly found for B0: ( 1, 2, 26)
5855 12:42:15.655960 Total UI for P1: 0, mck2ui 16
5856 12:42:15.658991 best dqsien dly found for B1: ( 1, 2, 28)
5857 12:42:15.662334 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5858 12:42:15.665171 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5859 12:42:15.665254
5860 12:42:15.668909 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 12:42:15.671884 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5862 12:42:15.675218 [Gating] SW calibration Done
5863 12:42:15.675300 ==
5864 12:42:15.678610 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 12:42:15.682001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 12:42:15.684979 ==
5867 12:42:15.685063 RX Vref Scan: 0
5868 12:42:15.685129
5869 12:42:15.688221 RX Vref 0 -> 0, step: 1
5870 12:42:15.688304
5871 12:42:15.691331 RX Delay -80 -> 252, step: 8
5872 12:42:15.694795 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5873 12:42:15.698792 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5874 12:42:15.701806 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5875 12:42:15.704988 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5876 12:42:15.707895 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5877 12:42:15.714721 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5878 12:42:15.718647 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5879 12:42:15.720974 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5880 12:42:15.724206 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5881 12:42:15.727737 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5882 12:42:15.731145 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5883 12:42:15.737796 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5884 12:42:15.741302 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5885 12:42:15.744726 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5886 12:42:15.747898 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5887 12:42:15.751093 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5888 12:42:15.754010 ==
5889 12:42:15.758177 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 12:42:15.761080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 12:42:15.761164 ==
5892 12:42:15.761230 DQS Delay:
5893 12:42:15.764900 DQS0 = 0, DQS1 = 0
5894 12:42:15.764984 DQM Delay:
5895 12:42:15.767557 DQM0 = 97, DQM1 = 94
5896 12:42:15.767640 DQ Delay:
5897 12:42:15.770408 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5898 12:42:15.773795 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5899 12:42:15.776736 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5900 12:42:15.779977 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5901 12:42:15.780080
5902 12:42:15.780171
5903 12:42:15.780259 ==
5904 12:42:15.783898 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 12:42:15.787223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 12:42:15.790313 ==
5907 12:42:15.790434
5908 12:42:15.790501
5909 12:42:15.790564 TX Vref Scan disable
5910 12:42:15.793192 == TX Byte 0 ==
5911 12:42:15.796724 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5912 12:42:15.799770 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5913 12:42:15.803357 == TX Byte 1 ==
5914 12:42:15.806643 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5915 12:42:15.810168 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5916 12:42:15.813288 ==
5917 12:42:15.816433 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 12:42:15.819619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 12:42:15.819729 ==
5920 12:42:15.819824
5921 12:42:15.819913
5922 12:42:15.823013 TX Vref Scan disable
5923 12:42:15.823109 == TX Byte 0 ==
5924 12:42:15.829517 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5925 12:42:15.832758 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5926 12:42:15.832842 == TX Byte 1 ==
5927 12:42:15.839428 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5928 12:42:15.842818 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5929 12:42:15.842935
5930 12:42:15.843030 [DATLAT]
5931 12:42:15.846071 Freq=933, CH1 RK1
5932 12:42:15.846155
5933 12:42:15.846220 DATLAT Default: 0xb
5934 12:42:15.849526 0, 0xFFFF, sum = 0
5935 12:42:15.849611 1, 0xFFFF, sum = 0
5936 12:42:15.852711 2, 0xFFFF, sum = 0
5937 12:42:15.855796 3, 0xFFFF, sum = 0
5938 12:42:15.855881 4, 0xFFFF, sum = 0
5939 12:42:15.859559 5, 0xFFFF, sum = 0
5940 12:42:15.859644 6, 0xFFFF, sum = 0
5941 12:42:15.862519 7, 0xFFFF, sum = 0
5942 12:42:15.862603 8, 0xFFFF, sum = 0
5943 12:42:15.865745 9, 0xFFFF, sum = 0
5944 12:42:15.865830 10, 0x0, sum = 1
5945 12:42:15.869670 11, 0x0, sum = 2
5946 12:42:15.869754 12, 0x0, sum = 3
5947 12:42:15.872565 13, 0x0, sum = 4
5948 12:42:15.872650 best_step = 11
5949 12:42:15.872715
5950 12:42:15.872776 ==
5951 12:42:15.876362 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 12:42:15.879537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 12:42:15.879621 ==
5954 12:42:15.882196 RX Vref Scan: 0
5955 12:42:15.882278
5956 12:42:15.886115 RX Vref 0 -> 0, step: 1
5957 12:42:15.886198
5958 12:42:15.886264 RX Delay -53 -> 252, step: 4
5959 12:42:15.893355 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5960 12:42:15.896609 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5961 12:42:15.900243 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5962 12:42:15.903400 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5963 12:42:15.906390 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5964 12:42:15.913146 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5965 12:42:15.916717 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5966 12:42:15.919968 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5967 12:42:15.923113 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5968 12:42:15.926227 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5969 12:42:15.930475 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5970 12:42:15.936619 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5971 12:42:15.939844 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5972 12:42:15.942955 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5973 12:42:15.946229 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5974 12:42:15.952906 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5975 12:42:15.953335 ==
5976 12:42:15.956384 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 12:42:15.959210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 12:42:15.959685 ==
5979 12:42:15.960030 DQS Delay:
5980 12:42:15.963008 DQS0 = 0, DQS1 = 0
5981 12:42:15.963476 DQM Delay:
5982 12:42:15.966187 DQM0 = 96, DQM1 = 91
5983 12:42:15.966616 DQ Delay:
5984 12:42:15.969511 DQ0 =100, DQ1 =94, DQ2 =86, DQ3 =94
5985 12:42:15.973151 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =94
5986 12:42:15.976049 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5987 12:42:15.979346 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =102
5988 12:42:15.979819
5989 12:42:15.980160
5990 12:42:15.986087 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5991 12:42:15.989815 CH1 RK1: MR19=505, MR18=B22
5992 12:42:15.996198 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5993 12:42:15.999353 [RxdqsGatingPostProcess] freq 933
5994 12:42:16.006455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 12:42:16.009007 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 12:42:16.011916 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 12:42:16.015599 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 12:42:16.018610 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 12:42:16.018729 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 12:42:16.021864 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 12:42:16.025441 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 12:42:16.028869 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 12:42:16.031850 Pre-setting of DQS Precalculation
6004 12:42:16.038217 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 12:42:16.045365 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 12:42:16.051394 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 12:42:16.051602
6008 12:42:16.051763
6009 12:42:16.054938 [Calibration Summary] 1866 Mbps
6010 12:42:16.055153 CH 0, Rank 0
6011 12:42:16.058261 SW Impedance : PASS
6012 12:42:16.061765 DUTY Scan : NO K
6013 12:42:16.062051 ZQ Calibration : PASS
6014 12:42:16.065165 Jitter Meter : NO K
6015 12:42:16.068620 CBT Training : PASS
6016 12:42:16.069001 Write leveling : PASS
6017 12:42:16.071298 RX DQS gating : PASS
6018 12:42:16.074517 RX DQ/DQS(RDDQC) : PASS
6019 12:42:16.074604 TX DQ/DQS : PASS
6020 12:42:16.078214 RX DATLAT : PASS
6021 12:42:16.081390 RX DQ/DQS(Engine): PASS
6022 12:42:16.081465 TX OE : NO K
6023 12:42:16.084299 All Pass.
6024 12:42:16.084376
6025 12:42:16.084447 CH 0, Rank 1
6026 12:42:16.088039 SW Impedance : PASS
6027 12:42:16.088137 DUTY Scan : NO K
6028 12:42:16.091300 ZQ Calibration : PASS
6029 12:42:16.094314 Jitter Meter : NO K
6030 12:42:16.094413 CBT Training : PASS
6031 12:42:16.097912 Write leveling : PASS
6032 12:42:16.101091 RX DQS gating : PASS
6033 12:42:16.101164 RX DQ/DQS(RDDQC) : PASS
6034 12:42:16.104482 TX DQ/DQS : PASS
6035 12:42:16.107156 RX DATLAT : PASS
6036 12:42:16.107258 RX DQ/DQS(Engine): PASS
6037 12:42:16.111204 TX OE : NO K
6038 12:42:16.111305 All Pass.
6039 12:42:16.111404
6040 12:42:16.114297 CH 1, Rank 0
6041 12:42:16.114368 SW Impedance : PASS
6042 12:42:16.117252 DUTY Scan : NO K
6043 12:42:16.120837 ZQ Calibration : PASS
6044 12:42:16.120909 Jitter Meter : NO K
6045 12:42:16.123946 CBT Training : PASS
6046 12:42:16.127145 Write leveling : PASS
6047 12:42:16.127219 RX DQS gating : PASS
6048 12:42:16.130583 RX DQ/DQS(RDDQC) : PASS
6049 12:42:16.134199 TX DQ/DQS : PASS
6050 12:42:16.134303 RX DATLAT : PASS
6051 12:42:16.136820 RX DQ/DQS(Engine): PASS
6052 12:42:16.136894 TX OE : NO K
6053 12:42:16.140190 All Pass.
6054 12:42:16.140265
6055 12:42:16.140327 CH 1, Rank 1
6056 12:42:16.143851 SW Impedance : PASS
6057 12:42:16.143923 DUTY Scan : NO K
6058 12:42:16.147217 ZQ Calibration : PASS
6059 12:42:16.150579 Jitter Meter : NO K
6060 12:42:16.150678 CBT Training : PASS
6061 12:42:16.153525 Write leveling : PASS
6062 12:42:16.156562 RX DQS gating : PASS
6063 12:42:16.156639 RX DQ/DQS(RDDQC) : PASS
6064 12:42:16.159715 TX DQ/DQS : PASS
6065 12:42:16.163499 RX DATLAT : PASS
6066 12:42:16.163577 RX DQ/DQS(Engine): PASS
6067 12:42:16.166910 TX OE : NO K
6068 12:42:16.167011 All Pass.
6069 12:42:16.167103
6070 12:42:16.170256 DramC Write-DBI off
6071 12:42:16.173655 PER_BANK_REFRESH: Hybrid Mode
6072 12:42:16.173757 TX_TRACKING: ON
6073 12:42:16.183106 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 12:42:16.186752 [FAST_K] Save calibration result to emmc
6075 12:42:16.190121 dramc_set_vcore_voltage set vcore to 650000
6076 12:42:16.193342 Read voltage for 400, 6
6077 12:42:16.193423 Vio18 = 0
6078 12:42:16.193487 Vcore = 650000
6079 12:42:16.196198 Vdram = 0
6080 12:42:16.196288 Vddq = 0
6081 12:42:16.196354 Vmddr = 0
6082 12:42:16.203197 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 12:42:16.206410 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 12:42:16.209697 MEM_TYPE=3, freq_sel=20
6085 12:42:16.212847 sv_algorithm_assistance_LP4_800
6086 12:42:16.216596 ============ PULL DRAM RESETB DOWN ============
6087 12:42:16.224002 ========== PULL DRAM RESETB DOWN end =========
6088 12:42:16.226651 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 12:42:16.229758 ===================================
6090 12:42:16.232698 LPDDR4 DRAM CONFIGURATION
6091 12:42:16.235939 ===================================
6092 12:42:16.236040 EX_ROW_EN[0] = 0x0
6093 12:42:16.239565 EX_ROW_EN[1] = 0x0
6094 12:42:16.239715 LP4Y_EN = 0x0
6095 12:42:16.242793 WORK_FSP = 0x0
6096 12:42:16.242867 WL = 0x2
6097 12:42:16.246078 RL = 0x2
6098 12:42:16.246184 BL = 0x2
6099 12:42:16.249466 RPST = 0x0
6100 12:42:16.249569 RD_PRE = 0x0
6101 12:42:16.252517 WR_PRE = 0x1
6102 12:42:16.256548 WR_PST = 0x0
6103 12:42:16.256621 DBI_WR = 0x0
6104 12:42:16.258973 DBI_RD = 0x0
6105 12:42:16.259070 OTF = 0x1
6106 12:42:16.262576 ===================================
6107 12:42:16.265784 ===================================
6108 12:42:16.265888 ANA top config
6109 12:42:16.269314 ===================================
6110 12:42:16.272660 DLL_ASYNC_EN = 0
6111 12:42:16.275927 ALL_SLAVE_EN = 1
6112 12:42:16.278959 NEW_RANK_MODE = 1
6113 12:42:16.282065 DLL_IDLE_MODE = 1
6114 12:42:16.282189 LP45_APHY_COMB_EN = 1
6115 12:42:16.285664 TX_ODT_DIS = 1
6116 12:42:16.288625 NEW_8X_MODE = 1
6117 12:42:16.291803 ===================================
6118 12:42:16.295382 ===================================
6119 12:42:16.298584 data_rate = 800
6120 12:42:16.301929 CKR = 1
6121 12:42:16.305485 DQ_P2S_RATIO = 4
6122 12:42:16.308579 ===================================
6123 12:42:16.308762 CA_P2S_RATIO = 4
6124 12:42:16.312457 DQ_CA_OPEN = 0
6125 12:42:16.315549 DQ_SEMI_OPEN = 1
6126 12:42:16.319088 CA_SEMI_OPEN = 1
6127 12:42:16.321901 CA_FULL_RATE = 0
6128 12:42:16.325101 DQ_CKDIV4_EN = 0
6129 12:42:16.325613 CA_CKDIV4_EN = 1
6130 12:42:16.329241 CA_PREDIV_EN = 0
6131 12:42:16.331518 PH8_DLY = 0
6132 12:42:16.334841 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 12:42:16.338518 DQ_AAMCK_DIV = 0
6134 12:42:16.341827 CA_AAMCK_DIV = 0
6135 12:42:16.345207 CA_ADMCK_DIV = 4
6136 12:42:16.345814 DQ_TRACK_CA_EN = 0
6137 12:42:16.348271 CA_PICK = 800
6138 12:42:16.351259 CA_MCKIO = 400
6139 12:42:16.354713 MCKIO_SEMI = 400
6140 12:42:16.358695 PLL_FREQ = 3016
6141 12:42:16.361572 DQ_UI_PI_RATIO = 32
6142 12:42:16.364640 CA_UI_PI_RATIO = 32
6143 12:42:16.368249 ===================================
6144 12:42:16.371226 ===================================
6145 12:42:16.371692 memory_type:LPDDR4
6146 12:42:16.374473 GP_NUM : 10
6147 12:42:16.377688 SRAM_EN : 1
6148 12:42:16.378117 MD32_EN : 0
6149 12:42:16.381233 ===================================
6150 12:42:16.384448 [ANA_INIT] >>>>>>>>>>>>>>
6151 12:42:16.387872 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 12:42:16.391011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 12:42:16.394709 ===================================
6154 12:42:16.397583 data_rate = 800,PCW = 0X7400
6155 12:42:16.401011 ===================================
6156 12:42:16.404009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 12:42:16.407354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 12:42:16.420619 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 12:42:16.423845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 12:42:16.427847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 12:42:16.431021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 12:42:16.434148 [ANA_INIT] flow start
6163 12:42:16.437355 [ANA_INIT] PLL >>>>>>>>
6164 12:42:16.437783 [ANA_INIT] PLL <<<<<<<<
6165 12:42:16.440664 [ANA_INIT] MIDPI >>>>>>>>
6166 12:42:16.444195 [ANA_INIT] MIDPI <<<<<<<<
6167 12:42:16.444623 [ANA_INIT] DLL >>>>>>>>
6168 12:42:16.447471 [ANA_INIT] flow end
6169 12:42:16.450508 ============ LP4 DIFF to SE enter ============
6170 12:42:16.457278 ============ LP4 DIFF to SE exit ============
6171 12:42:16.457722 [ANA_INIT] <<<<<<<<<<<<<
6172 12:42:16.459982 [Flow] Enable top DCM control >>>>>
6173 12:42:16.463145 [Flow] Enable top DCM control <<<<<
6174 12:42:16.466616 Enable DLL master slave shuffle
6175 12:42:16.473467 ==============================================================
6176 12:42:16.473899 Gating Mode config
6177 12:42:16.479736 ==============================================================
6178 12:42:16.483184 Config description:
6179 12:42:16.493250 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 12:42:16.499522 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 12:42:16.503173 SELPH_MODE 0: By rank 1: By Phase
6182 12:42:16.510266 ==============================================================
6183 12:42:16.512859 GAT_TRACK_EN = 0
6184 12:42:16.516465 RX_GATING_MODE = 2
6185 12:42:16.516892 RX_GATING_TRACK_MODE = 2
6186 12:42:16.519627 SELPH_MODE = 1
6187 12:42:16.523320 PICG_EARLY_EN = 1
6188 12:42:16.525994 VALID_LAT_VALUE = 1
6189 12:42:16.532371 ==============================================================
6190 12:42:16.535702 Enter into Gating configuration >>>>
6191 12:42:16.538775 Exit from Gating configuration <<<<
6192 12:42:16.543354 Enter into DVFS_PRE_config >>>>>
6193 12:42:16.553860 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 12:42:16.555333 Exit from DVFS_PRE_config <<<<<
6195 12:42:16.558613 Enter into PICG configuration >>>>
6196 12:42:16.562278 Exit from PICG configuration <<<<
6197 12:42:16.565380 [RX_INPUT] configuration >>>>>
6198 12:42:16.569259 [RX_INPUT] configuration <<<<<
6199 12:42:16.572334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 12:42:16.578449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 12:42:16.584960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 12:42:16.591751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 12:42:16.598491 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 12:42:16.604742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 12:42:16.608246 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 12:42:16.611649 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 12:42:16.617464 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 12:42:16.622085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 12:42:16.624380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 12:42:16.627775 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 12:42:16.631198 ===================================
6212 12:42:16.634446 LPDDR4 DRAM CONFIGURATION
6213 12:42:16.638470 ===================================
6214 12:42:16.638981 EX_ROW_EN[0] = 0x0
6215 12:42:16.641377 EX_ROW_EN[1] = 0x0
6216 12:42:16.644191 LP4Y_EN = 0x0
6217 12:42:16.644758 WORK_FSP = 0x0
6218 12:42:16.647688 WL = 0x2
6219 12:42:16.648113 RL = 0x2
6220 12:42:16.651216 BL = 0x2
6221 12:42:16.651751 RPST = 0x0
6222 12:42:16.654023 RD_PRE = 0x0
6223 12:42:16.654636 WR_PRE = 0x1
6224 12:42:16.657767 WR_PST = 0x0
6225 12:42:16.658417 DBI_WR = 0x0
6226 12:42:16.660957 DBI_RD = 0x0
6227 12:42:16.661608 OTF = 0x1
6228 12:42:16.665287 ===================================
6229 12:42:16.671091 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 12:42:16.673510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 12:42:16.677174 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 12:42:16.680583 ===================================
6233 12:42:16.684057 LPDDR4 DRAM CONFIGURATION
6234 12:42:16.687216 ===================================
6235 12:42:16.690192 EX_ROW_EN[0] = 0x10
6236 12:42:16.690741 EX_ROW_EN[1] = 0x0
6237 12:42:16.693594 LP4Y_EN = 0x0
6238 12:42:16.694208 WORK_FSP = 0x0
6239 12:42:16.696701 WL = 0x2
6240 12:42:16.697319 RL = 0x2
6241 12:42:16.700008 BL = 0x2
6242 12:42:16.700540 RPST = 0x0
6243 12:42:16.703625 RD_PRE = 0x0
6244 12:42:16.704154 WR_PRE = 0x1
6245 12:42:16.706617 WR_PST = 0x0
6246 12:42:16.707071 DBI_WR = 0x0
6247 12:42:16.710127 DBI_RD = 0x0
6248 12:42:16.710683 OTF = 0x1
6249 12:42:16.713483 ===================================
6250 12:42:16.720005 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 12:42:16.724782 nWR fixed to 30
6252 12:42:16.727966 [ModeRegInit_LP4] CH0 RK0
6253 12:42:16.728427 [ModeRegInit_LP4] CH0 RK1
6254 12:42:16.731395 [ModeRegInit_LP4] CH1 RK0
6255 12:42:16.734702 [ModeRegInit_LP4] CH1 RK1
6256 12:42:16.735284 match AC timing 19
6257 12:42:16.741587 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 12:42:16.744137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 12:42:16.747864 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 12:42:16.755052 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 12:42:16.757436 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 12:42:16.757864 ==
6263 12:42:16.760886 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 12:42:16.764100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 12:42:16.764611 ==
6266 12:42:16.770385 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 12:42:16.778428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6268 12:42:16.780702 [CA 0] Center 36 (8~64) winsize 57
6269 12:42:16.783452 [CA 1] Center 36 (8~64) winsize 57
6270 12:42:16.787262 [CA 2] Center 36 (8~64) winsize 57
6271 12:42:16.790841 [CA 3] Center 36 (8~64) winsize 57
6272 12:42:16.793681 [CA 4] Center 36 (8~64) winsize 57
6273 12:42:16.796938 [CA 5] Center 36 (8~64) winsize 57
6274 12:42:16.797529
6275 12:42:16.800655 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6276 12:42:16.801215
6277 12:42:16.803447 [CATrainingPosCal] consider 1 rank data
6278 12:42:16.806475 u2DelayCellTimex100 = 270/100 ps
6279 12:42:16.810258 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:42:16.813624 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:42:16.816521 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:42:16.819648 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:42:16.823025 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:42:16.826405 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:42:16.827003
6286 12:42:16.833227 CA PerBit enable=1, Macro0, CA PI delay=36
6287 12:42:16.833744
6288 12:42:16.836122 [CBTSetCACLKResult] CA Dly = 36
6289 12:42:16.836644 CS Dly: 1 (0~32)
6290 12:42:16.836996 ==
6291 12:42:16.839632 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 12:42:16.844126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 12:42:16.844555 ==
6294 12:42:16.849512 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 12:42:16.855924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6296 12:42:16.859529 [CA 0] Center 36 (8~64) winsize 57
6297 12:42:16.862394 [CA 1] Center 36 (8~64) winsize 57
6298 12:42:16.866629 [CA 2] Center 36 (8~64) winsize 57
6299 12:42:16.869500 [CA 3] Center 36 (8~64) winsize 57
6300 12:42:16.872320 [CA 4] Center 36 (8~64) winsize 57
6301 12:42:16.875968 [CA 5] Center 36 (8~64) winsize 57
6302 12:42:16.876617
6303 12:42:16.878830 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6304 12:42:16.879585
6305 12:42:16.883094 [CATrainingPosCal] consider 2 rank data
6306 12:42:16.885992 u2DelayCellTimex100 = 270/100 ps
6307 12:42:16.889589 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 12:42:16.892448 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 12:42:16.895321 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 12:42:16.898723 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 12:42:16.902212 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 12:42:16.905424 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:42:16.906034
6314 12:42:16.911994 CA PerBit enable=1, Macro0, CA PI delay=36
6315 12:42:16.912553
6316 12:42:16.913139 [CBTSetCACLKResult] CA Dly = 36
6317 12:42:16.915477 CS Dly: 1 (0~32)
6318 12:42:16.916051
6319 12:42:16.918923 ----->DramcWriteLeveling(PI) begin...
6320 12:42:16.919606 ==
6321 12:42:16.921931 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 12:42:16.925244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 12:42:16.925857 ==
6324 12:42:16.929344 Write leveling (Byte 0): 40 => 8
6325 12:42:16.932436 Write leveling (Byte 1): 40 => 8
6326 12:42:16.935614 DramcWriteLeveling(PI) end<-----
6327 12:42:16.936125
6328 12:42:16.936678 ==
6329 12:42:16.938214 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 12:42:16.941694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:42:16.944935 ==
6332 12:42:16.945578 [Gating] SW mode calibration
6333 12:42:16.954486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 12:42:16.958267 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 12:42:16.961354 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 12:42:16.968003 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 12:42:16.970984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 12:42:16.974194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 12:42:16.980609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 12:42:16.984016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 12:42:16.987709 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 12:42:16.994769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 12:42:16.997373 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 12:42:17.000883 Total UI for P1: 0, mck2ui 16
6345 12:42:17.003975 best dqsien dly found for B0: ( 0, 14, 24)
6346 12:42:17.007022 Total UI for P1: 0, mck2ui 16
6347 12:42:17.011264 best dqsien dly found for B1: ( 0, 14, 24)
6348 12:42:17.014100 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 12:42:17.016976 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 12:42:17.017054
6351 12:42:17.020621 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 12:42:17.026692 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 12:42:17.026769 [Gating] SW calibration Done
6354 12:42:17.030006 ==
6355 12:42:17.030110 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 12:42:17.036624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 12:42:17.036706 ==
6358 12:42:17.036772 RX Vref Scan: 0
6359 12:42:17.036848
6360 12:42:17.040041 RX Vref 0 -> 0, step: 1
6361 12:42:17.040125
6362 12:42:17.043490 RX Delay -410 -> 252, step: 16
6363 12:42:17.046433 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6364 12:42:17.052942 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6365 12:42:17.056668 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6366 12:42:17.060072 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6367 12:42:17.062782 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6368 12:42:17.069313 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6369 12:42:17.072892 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6370 12:42:17.076317 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6371 12:42:17.079299 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6372 12:42:17.085942 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6373 12:42:17.089299 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6374 12:42:17.092604 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6375 12:42:17.095928 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6376 12:42:17.102787 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6377 12:42:17.106145 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6378 12:42:17.110055 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6379 12:42:17.110246 ==
6380 12:42:17.112500 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:42:17.119274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:42:17.119508 ==
6383 12:42:17.119667 DQS Delay:
6384 12:42:17.122401 DQS0 = 35, DQS1 = 59
6385 12:42:17.122593 DQM Delay:
6386 12:42:17.122752 DQM0 = 4, DQM1 = 17
6387 12:42:17.125726 DQ Delay:
6388 12:42:17.129044 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6389 12:42:17.129121 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6390 12:42:17.131854 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6391 12:42:17.135126 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6392 12:42:17.138554
6393 12:42:17.138655
6394 12:42:17.138756 ==
6395 12:42:17.141743 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 12:42:17.145243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 12:42:17.145325 ==
6398 12:42:17.145388
6399 12:42:17.145472
6400 12:42:17.148170 TX Vref Scan disable
6401 12:42:17.148270 == TX Byte 0 ==
6402 12:42:17.151857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 12:42:17.158490 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 12:42:17.158594 == TX Byte 1 ==
6405 12:42:17.161466 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 12:42:17.168783 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 12:42:17.168890 ==
6408 12:42:17.171807 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 12:42:17.175136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 12:42:17.175256 ==
6411 12:42:17.175357
6412 12:42:17.175441
6413 12:42:17.178190 TX Vref Scan disable
6414 12:42:17.178299 == TX Byte 0 ==
6415 12:42:17.184921 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 12:42:17.188260 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 12:42:17.188338 == TX Byte 1 ==
6418 12:42:17.194221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 12:42:17.197727 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 12:42:17.197829
6421 12:42:17.197931 [DATLAT]
6422 12:42:17.200796 Freq=400, CH0 RK0
6423 12:42:17.200873
6424 12:42:17.200937 DATLAT Default: 0xf
6425 12:42:17.204073 0, 0xFFFF, sum = 0
6426 12:42:17.204176 1, 0xFFFF, sum = 0
6427 12:42:17.207966 2, 0xFFFF, sum = 0
6428 12:42:17.208045 3, 0xFFFF, sum = 0
6429 12:42:17.212024 4, 0xFFFF, sum = 0
6430 12:42:17.212102 5, 0xFFFF, sum = 0
6431 12:42:17.214062 6, 0xFFFF, sum = 0
6432 12:42:17.214170 7, 0xFFFF, sum = 0
6433 12:42:17.218402 8, 0xFFFF, sum = 0
6434 12:42:17.220646 9, 0xFFFF, sum = 0
6435 12:42:17.220721 10, 0xFFFF, sum = 0
6436 12:42:17.224215 11, 0xFFFF, sum = 0
6437 12:42:17.224291 12, 0xFFFF, sum = 0
6438 12:42:17.227260 13, 0x0, sum = 1
6439 12:42:17.227359 14, 0x0, sum = 2
6440 12:42:17.230857 15, 0x0, sum = 3
6441 12:42:17.230956 16, 0x0, sum = 4
6442 12:42:17.233799 best_step = 14
6443 12:42:17.233899
6444 12:42:17.233988 ==
6445 12:42:17.237585 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 12:42:17.240752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 12:42:17.240832 ==
6448 12:42:17.240915 RX Vref Scan: 1
6449 12:42:17.240998
6450 12:42:17.243814 RX Vref 0 -> 0, step: 1
6451 12:42:17.243903
6452 12:42:17.247230 RX Delay -359 -> 252, step: 8
6453 12:42:17.247331
6454 12:42:17.250373 Set Vref, RX VrefLevel [Byte0]: 51
6455 12:42:17.253735 [Byte1]: 58
6456 12:42:17.257942
6457 12:42:17.258052 Final RX Vref Byte 0 = 51 to rank0
6458 12:42:17.260976 Final RX Vref Byte 1 = 58 to rank0
6459 12:42:17.264367 Final RX Vref Byte 0 = 51 to rank1
6460 12:42:17.268283 Final RX Vref Byte 1 = 58 to rank1==
6461 12:42:17.271470 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 12:42:17.277643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 12:42:17.277727 ==
6464 12:42:17.277822 DQS Delay:
6465 12:42:17.281187 DQS0 = 44, DQS1 = 60
6466 12:42:17.281302 DQM Delay:
6467 12:42:17.281395 DQM0 = 10, DQM1 = 16
6468 12:42:17.284211 DQ Delay:
6469 12:42:17.287147 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6470 12:42:17.290864 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6471 12:42:17.290946 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6472 12:42:17.297410 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6473 12:42:17.297518
6474 12:42:17.297609
6475 12:42:17.304117 [DQSOSCAuto] RK0, (LSB)MR18= 0x9589, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6476 12:42:17.307271 CH0 RK0: MR19=C0C, MR18=9589
6477 12:42:17.314025 CH0_RK0: MR19=0xC0C, MR18=0x9589, DQSOSC=391, MR23=63, INC=386, DEC=257
6478 12:42:17.314451 ==
6479 12:42:17.317763 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 12:42:17.320949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 12:42:17.321378 ==
6482 12:42:17.324315 [Gating] SW mode calibration
6483 12:42:17.330882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 12:42:17.337375 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 12:42:17.340904 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 12:42:17.343941 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 12:42:17.350643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 12:42:17.353914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 12:42:17.357313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 12:42:17.363620 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 12:42:17.366916 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 12:42:17.370750 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 12:42:17.376938 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 12:42:17.377586 Total UI for P1: 0, mck2ui 16
6495 12:42:17.383659 best dqsien dly found for B0: ( 0, 14, 24)
6496 12:42:17.384317 Total UI for P1: 0, mck2ui 16
6497 12:42:17.390470 best dqsien dly found for B1: ( 0, 14, 24)
6498 12:42:17.393248 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 12:42:17.397027 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 12:42:17.397626
6501 12:42:17.400216 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 12:42:17.403398 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 12:42:17.406337 [Gating] SW calibration Done
6504 12:42:17.406831 ==
6505 12:42:17.409702 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 12:42:17.413376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 12:42:17.413805 ==
6508 12:42:17.416762 RX Vref Scan: 0
6509 12:42:17.417184
6510 12:42:17.419740 RX Vref 0 -> 0, step: 1
6511 12:42:17.420164
6512 12:42:17.420497 RX Delay -410 -> 252, step: 16
6513 12:42:17.426492 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6514 12:42:17.430142 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6515 12:42:17.433599 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6516 12:42:17.439457 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6517 12:42:17.442895 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6518 12:42:17.445895 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6519 12:42:17.449075 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6520 12:42:17.455845 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6521 12:42:17.459182 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6522 12:42:17.462690 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 12:42:17.465833 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 12:42:17.472271 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 12:42:17.475500 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 12:42:17.478775 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 12:42:17.482328 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6528 12:42:17.488564 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6529 12:42:17.489145 ==
6530 12:42:17.492461 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:42:17.495581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:42:17.496045 ==
6533 12:42:17.498466 DQS Delay:
6534 12:42:17.498886 DQS0 = 35, DQS1 = 59
6535 12:42:17.499387 DQM Delay:
6536 12:42:17.502274 DQM0 = 7, DQM1 = 16
6537 12:42:17.502800 DQ Delay:
6538 12:42:17.505630 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6539 12:42:17.508627 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6540 12:42:17.512579 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6541 12:42:17.515291 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6542 12:42:17.515842
6543 12:42:17.516181
6544 12:42:17.516497 ==
6545 12:42:17.519232 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 12:42:17.521940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 12:42:17.522375 ==
6548 12:42:17.522711
6549 12:42:17.525227
6550 12:42:17.525717 TX Vref Scan disable
6551 12:42:17.528208 == TX Byte 0 ==
6552 12:42:17.532018 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6553 12:42:17.535138 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6554 12:42:17.538248 == TX Byte 1 ==
6555 12:42:17.541668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6556 12:42:17.545103 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6557 12:42:17.545715 ==
6558 12:42:17.548689 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 12:42:17.551505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 12:42:17.554768 ==
6561 12:42:17.555463
6562 12:42:17.556088
6563 12:42:17.556700 TX Vref Scan disable
6564 12:42:17.558261 == TX Byte 0 ==
6565 12:42:17.561100 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6566 12:42:17.564330 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6567 12:42:17.567850 == TX Byte 1 ==
6568 12:42:17.571244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6569 12:42:17.574256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6570 12:42:17.574484
6571 12:42:17.577580 [DATLAT]
6572 12:42:17.577876 Freq=400, CH0 RK1
6573 12:42:17.578131
6574 12:42:17.581924 DATLAT Default: 0xe
6575 12:42:17.582243 0, 0xFFFF, sum = 0
6576 12:42:17.584311 1, 0xFFFF, sum = 0
6577 12:42:17.584652 2, 0xFFFF, sum = 0
6578 12:42:17.587433 3, 0xFFFF, sum = 0
6579 12:42:17.587670 4, 0xFFFF, sum = 0
6580 12:42:17.591044 5, 0xFFFF, sum = 0
6581 12:42:17.591395 6, 0xFFFF, sum = 0
6582 12:42:17.594772 7, 0xFFFF, sum = 0
6583 12:42:17.595090 8, 0xFFFF, sum = 0
6584 12:42:17.597180 9, 0xFFFF, sum = 0
6585 12:42:17.597521 10, 0xFFFF, sum = 0
6586 12:42:17.601133 11, 0xFFFF, sum = 0
6587 12:42:17.604221 12, 0xFFFF, sum = 0
6588 12:42:17.604473 13, 0x0, sum = 1
6589 12:42:17.604680 14, 0x0, sum = 2
6590 12:42:17.607338 15, 0x0, sum = 3
6591 12:42:17.607608 16, 0x0, sum = 4
6592 12:42:17.610938 best_step = 14
6593 12:42:17.611224
6594 12:42:17.611513 ==
6595 12:42:17.613751 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 12:42:17.617057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 12:42:17.617139 ==
6598 12:42:17.620550 RX Vref Scan: 0
6599 12:42:17.620650
6600 12:42:17.620749 RX Vref 0 -> 0, step: 1
6601 12:42:17.623353
6602 12:42:17.623477 RX Delay -359 -> 252, step: 8
6603 12:42:17.631967 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6604 12:42:17.635392 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6605 12:42:17.638690 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6606 12:42:17.642309 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6607 12:42:17.648421 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6608 12:42:17.652112 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6609 12:42:17.655509 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6610 12:42:17.661731 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6611 12:42:17.665222 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6612 12:42:17.668323 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6613 12:42:17.671574 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6614 12:42:17.678330 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6615 12:42:17.681133 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6616 12:42:17.684863 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6617 12:42:17.687755 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6618 12:42:17.694357 iDelay=209, Bit 15, Center -40 (-287 ~ 208) 496
6619 12:42:17.694464 ==
6620 12:42:17.697880 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 12:42:17.701494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 12:42:17.701570 ==
6623 12:42:17.701633 DQS Delay:
6624 12:42:17.704720 DQS0 = 44, DQS1 = 60
6625 12:42:17.704800 DQM Delay:
6626 12:42:17.707909 DQM0 = 10, DQM1 = 15
6627 12:42:17.707987 DQ Delay:
6628 12:42:17.711173 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6629 12:42:17.714184 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6630 12:42:17.717421 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6631 12:42:17.721041 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6632 12:42:17.721150
6633 12:42:17.721216
6634 12:42:17.731240 [DQSOSCAuto] RK1, (LSB)MR18= 0x9087, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6635 12:42:17.731321 CH0 RK1: MR19=C0C, MR18=9087
6636 12:42:17.737807 CH0_RK1: MR19=0xC0C, MR18=0x9087, DQSOSC=391, MR23=63, INC=386, DEC=257
6637 12:42:17.741226 [RxdqsGatingPostProcess] freq 400
6638 12:42:17.747088 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 12:42:17.750923 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 12:42:17.754006 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 12:42:17.757225 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 12:42:17.760772 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 12:42:17.763955 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 12:42:17.764129 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 12:42:17.767274 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 12:42:17.770035 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 12:42:17.774058 Pre-setting of DQS Precalculation
6648 12:42:17.779993 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 12:42:17.780076 ==
6650 12:42:17.783835 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 12:42:17.786959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 12:42:17.787056 ==
6653 12:42:17.793136 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 12:42:17.800488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 12:42:17.803691 [CA 0] Center 36 (8~64) winsize 57
6656 12:42:17.807286 [CA 1] Center 36 (8~64) winsize 57
6657 12:42:17.810500 [CA 2] Center 36 (8~64) winsize 57
6658 12:42:17.810926 [CA 3] Center 36 (8~64) winsize 57
6659 12:42:17.813944 [CA 4] Center 36 (8~64) winsize 57
6660 12:42:17.817068 [CA 5] Center 36 (8~64) winsize 57
6661 12:42:17.817509
6662 12:42:17.823743 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 12:42:17.824266
6664 12:42:17.826699 [CATrainingPosCal] consider 1 rank data
6665 12:42:17.830030 u2DelayCellTimex100 = 270/100 ps
6666 12:42:17.832939 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:42:17.836150 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:42:17.839325 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:42:17.842505 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:42:17.845796 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:42:17.849547 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:42:17.849705
6673 12:42:17.852894 CA PerBit enable=1, Macro0, CA PI delay=36
6674 12:42:17.853041
6675 12:42:17.855929 [CBTSetCACLKResult] CA Dly = 36
6676 12:42:17.858999 CS Dly: 1 (0~32)
6677 12:42:17.859151 ==
6678 12:42:17.862483 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 12:42:17.866684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 12:42:17.866890 ==
6681 12:42:17.872165 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 12:42:17.879322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6683 12:42:17.883012 [CA 0] Center 36 (8~64) winsize 57
6684 12:42:17.886360 [CA 1] Center 36 (8~64) winsize 57
6685 12:42:17.889149 [CA 2] Center 36 (8~64) winsize 57
6686 12:42:17.889574 [CA 3] Center 36 (8~64) winsize 57
6687 12:42:17.892202 [CA 4] Center 36 (8~64) winsize 57
6688 12:42:17.895672 [CA 5] Center 36 (8~64) winsize 57
6689 12:42:17.896128
6690 12:42:17.902550 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6691 12:42:17.903021
6692 12:42:17.905490 [CATrainingPosCal] consider 2 rank data
6693 12:42:17.909454 u2DelayCellTimex100 = 270/100 ps
6694 12:42:17.913055 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 12:42:17.916108 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 12:42:17.918614 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 12:42:17.922143 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 12:42:17.925649 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 12:42:17.928917 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:42:17.929592
6701 12:42:17.931708 CA PerBit enable=1, Macro0, CA PI delay=36
6702 12:42:17.931791
6703 12:42:17.934749 [CBTSetCACLKResult] CA Dly = 36
6704 12:42:17.937877 CS Dly: 1 (0~32)
6705 12:42:17.937961
6706 12:42:17.941270 ----->DramcWriteLeveling(PI) begin...
6707 12:42:17.941374 ==
6708 12:42:17.945363 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 12:42:17.947891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 12:42:17.947980 ==
6711 12:42:17.951582 Write leveling (Byte 0): 40 => 8
6712 12:42:17.954294 Write leveling (Byte 1): 40 => 8
6713 12:42:17.958280 DramcWriteLeveling(PI) end<-----
6714 12:42:17.958358
6715 12:42:17.958421 ==
6716 12:42:17.961421 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 12:42:17.964200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:42:17.964309 ==
6719 12:42:17.967833 [Gating] SW mode calibration
6720 12:42:17.974630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 12:42:17.981273 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 12:42:17.984057 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 12:42:17.990853 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 12:42:17.994115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 12:42:17.997841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 12:42:18.003956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 12:42:18.007108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 12:42:18.010281 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 12:42:18.017217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 12:42:18.020226 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 12:42:18.023311 Total UI for P1: 0, mck2ui 16
6732 12:42:18.026933 best dqsien dly found for B0: ( 0, 14, 24)
6733 12:42:18.030749 Total UI for P1: 0, mck2ui 16
6734 12:42:18.033637 best dqsien dly found for B1: ( 0, 14, 24)
6735 12:42:18.037217 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 12:42:18.040521 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 12:42:18.040699
6738 12:42:18.043376 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 12:42:18.050269 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 12:42:18.050433 [Gating] SW calibration Done
6741 12:42:18.050550 ==
6742 12:42:18.053347 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 12:42:18.059706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 12:42:18.059815 ==
6745 12:42:18.059913 RX Vref Scan: 0
6746 12:42:18.060006
6747 12:42:18.062835 RX Vref 0 -> 0, step: 1
6748 12:42:18.062925
6749 12:42:18.066188 RX Delay -410 -> 252, step: 16
6750 12:42:18.070046 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6751 12:42:18.073103 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6752 12:42:18.079621 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6753 12:42:18.083279 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6754 12:42:18.086729 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6755 12:42:18.089630 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6756 12:42:18.095950 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6757 12:42:18.099259 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6758 12:42:18.102607 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6759 12:42:18.106446 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6760 12:42:18.113373 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6761 12:42:18.115621 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6762 12:42:18.119053 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6763 12:42:18.125996 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6764 12:42:18.129327 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6765 12:42:18.132327 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6766 12:42:18.132429 ==
6767 12:42:18.135294 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:42:18.139097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:42:18.139203 ==
6770 12:42:18.142280 DQS Delay:
6771 12:42:18.142379 DQS0 = 43, DQS1 = 51
6772 12:42:18.145877 DQM Delay:
6773 12:42:18.145987 DQM0 = 13, DQM1 = 14
6774 12:42:18.149003 DQ Delay:
6775 12:42:18.149103 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6776 12:42:18.151764 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6777 12:42:18.155216 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6778 12:42:18.158467 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6779 12:42:18.158542
6780 12:42:18.158645
6781 12:42:18.158734 ==
6782 12:42:18.162203 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 12:42:18.168682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 12:42:18.168765 ==
6785 12:42:18.168831
6786 12:42:18.168890
6787 12:42:18.172492 TX Vref Scan disable
6788 12:42:18.172659 == TX Byte 0 ==
6789 12:42:18.175150 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 12:42:18.181694 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 12:42:18.181876 == TX Byte 1 ==
6792 12:42:18.184858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 12:42:18.191281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 12:42:18.191524 ==
6795 12:42:18.194933 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 12:42:18.197834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 12:42:18.198049 ==
6798 12:42:18.198205
6799 12:42:18.198367
6800 12:42:18.201439 TX Vref Scan disable
6801 12:42:18.201642 == TX Byte 0 ==
6802 12:42:18.204395 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 12:42:18.210812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 12:42:18.211088 == TX Byte 1 ==
6805 12:42:18.214353 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 12:42:18.221470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 12:42:18.221805
6808 12:42:18.222049 [DATLAT]
6809 12:42:18.224203 Freq=400, CH1 RK0
6810 12:42:18.224512
6811 12:42:18.224754 DATLAT Default: 0xf
6812 12:42:18.227574 0, 0xFFFF, sum = 0
6813 12:42:18.227884 1, 0xFFFF, sum = 0
6814 12:42:18.231023 2, 0xFFFF, sum = 0
6815 12:42:18.231335 3, 0xFFFF, sum = 0
6816 12:42:18.234307 4, 0xFFFF, sum = 0
6817 12:42:18.234617 5, 0xFFFF, sum = 0
6818 12:42:18.237549 6, 0xFFFF, sum = 0
6819 12:42:18.237859 7, 0xFFFF, sum = 0
6820 12:42:18.240737 8, 0xFFFF, sum = 0
6821 12:42:18.241047 9, 0xFFFF, sum = 0
6822 12:42:18.243771 10, 0xFFFF, sum = 0
6823 12:42:18.244080 11, 0xFFFF, sum = 0
6824 12:42:18.247358 12, 0xFFFF, sum = 0
6825 12:42:18.247714 13, 0x0, sum = 1
6826 12:42:18.250936 14, 0x0, sum = 2
6827 12:42:18.251334 15, 0x0, sum = 3
6828 12:42:18.254362 16, 0x0, sum = 4
6829 12:42:18.254942 best_step = 14
6830 12:42:18.255301
6831 12:42:18.255686 ==
6832 12:42:18.257415 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 12:42:18.264031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 12:42:18.264479 ==
6835 12:42:18.264822 RX Vref Scan: 1
6836 12:42:18.265222
6837 12:42:18.267786 RX Vref 0 -> 0, step: 1
6838 12:42:18.268214
6839 12:42:18.270642 RX Delay -343 -> 252, step: 8
6840 12:42:18.271070
6841 12:42:18.273817 Set Vref, RX VrefLevel [Byte0]: 47
6842 12:42:18.277045 [Byte1]: 51
6843 12:42:18.280992
6844 12:42:18.281416 Final RX Vref Byte 0 = 47 to rank0
6845 12:42:18.284008 Final RX Vref Byte 1 = 51 to rank0
6846 12:42:18.287260 Final RX Vref Byte 0 = 47 to rank1
6847 12:42:18.290403 Final RX Vref Byte 1 = 51 to rank1==
6848 12:42:18.293793 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 12:42:18.300856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 12:42:18.301289 ==
6851 12:42:18.301636 DQS Delay:
6852 12:42:18.303892 DQS0 = 44, DQS1 = 52
6853 12:42:18.304351 DQM Delay:
6854 12:42:18.304704 DQM0 = 11, DQM1 = 10
6855 12:42:18.306792 DQ Delay:
6856 12:42:18.310574 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6857 12:42:18.313556 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6858 12:42:18.314028 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6859 12:42:18.316984 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6860 12:42:18.320791
6861 12:42:18.321384
6862 12:42:18.326830 [DQSOSCAuto] RK0, (LSB)MR18= 0x678e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6863 12:42:18.330398 CH1 RK0: MR19=C0C, MR18=678E
6864 12:42:18.337116 CH1_RK0: MR19=0xC0C, MR18=0x678E, DQSOSC=392, MR23=63, INC=384, DEC=256
6865 12:42:18.337701 ==
6866 12:42:18.340310 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 12:42:18.343161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 12:42:18.343813 ==
6869 12:42:18.346740 [Gating] SW mode calibration
6870 12:42:18.353260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 12:42:18.359769 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 12:42:18.362943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 12:42:18.366157 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 12:42:18.373072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 12:42:18.376219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 12:42:18.379499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 12:42:18.386225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 12:42:18.389331 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 12:42:18.393339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 12:42:18.399994 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 12:42:18.400323 Total UI for P1: 0, mck2ui 16
6882 12:42:18.406829 best dqsien dly found for B0: ( 0, 14, 24)
6883 12:42:18.407218 Total UI for P1: 0, mck2ui 16
6884 12:42:18.412701 best dqsien dly found for B1: ( 0, 14, 24)
6885 12:42:18.416100 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 12:42:18.419409 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 12:42:18.419843
6888 12:42:18.422923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 12:42:18.425723 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 12:42:18.429184 [Gating] SW calibration Done
6891 12:42:18.429611 ==
6892 12:42:18.433391 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 12:42:18.435570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 12:42:18.436008 ==
6895 12:42:18.438883 RX Vref Scan: 0
6896 12:42:18.439311
6897 12:42:18.439721 RX Vref 0 -> 0, step: 1
6898 12:42:18.442189
6899 12:42:18.442616 RX Delay -410 -> 252, step: 16
6900 12:42:18.448796 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6901 12:42:18.452827 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6902 12:42:18.455936 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6903 12:42:18.459107 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6904 12:42:18.465546 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6905 12:42:18.468390 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6906 12:42:18.471888 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6907 12:42:18.478492 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6908 12:42:18.481976 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6909 12:42:18.484978 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6910 12:42:18.488373 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6911 12:42:18.494935 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6912 12:42:18.498286 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6913 12:42:18.501539 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6914 12:42:18.505244 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6915 12:42:18.511700 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6916 12:42:18.512179 ==
6917 12:42:18.514788 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:42:18.518091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:42:18.518585 ==
6920 12:42:18.518987 DQS Delay:
6921 12:42:18.521193 DQS0 = 51, DQS1 = 51
6922 12:42:18.521728 DQM Delay:
6923 12:42:18.525073 DQM0 = 16, DQM1 = 15
6924 12:42:18.525589 DQ Delay:
6925 12:42:18.528138 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6926 12:42:18.531553 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6927 12:42:18.534568 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6928 12:42:18.538092 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6929 12:42:18.538533
6930 12:42:18.538871
6931 12:42:18.539182 ==
6932 12:42:18.541612 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 12:42:18.544472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 12:42:18.547644 ==
6935 12:42:18.548068
6936 12:42:18.548400
6937 12:42:18.548712 TX Vref Scan disable
6938 12:42:18.551397 == TX Byte 0 ==
6939 12:42:18.554957 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6940 12:42:18.557707 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6941 12:42:18.560935 == TX Byte 1 ==
6942 12:42:18.564669 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6943 12:42:18.567581 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6944 12:42:18.568241 ==
6945 12:42:18.570977 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 12:42:18.574422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 12:42:18.577971 ==
6948 12:42:18.578646
6949 12:42:18.579239
6950 12:42:18.579874 TX Vref Scan disable
6951 12:42:18.581139 == TX Byte 0 ==
6952 12:42:18.584345 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6953 12:42:18.587428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6954 12:42:18.590445 == TX Byte 1 ==
6955 12:42:18.594050 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6956 12:42:18.597368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6957 12:42:18.597717
6958 12:42:18.600964 [DATLAT]
6959 12:42:18.601229 Freq=400, CH1 RK1
6960 12:42:18.601480
6961 12:42:18.603705 DATLAT Default: 0xe
6962 12:42:18.603959 0, 0xFFFF, sum = 0
6963 12:42:18.607101 1, 0xFFFF, sum = 0
6964 12:42:18.607316 2, 0xFFFF, sum = 0
6965 12:42:18.610464 3, 0xFFFF, sum = 0
6966 12:42:18.610618 4, 0xFFFF, sum = 0
6967 12:42:18.613712 5, 0xFFFF, sum = 0
6968 12:42:18.613868 6, 0xFFFF, sum = 0
6969 12:42:18.617261 7, 0xFFFF, sum = 0
6970 12:42:18.617500 8, 0xFFFF, sum = 0
6971 12:42:18.620628 9, 0xFFFF, sum = 0
6972 12:42:18.620825 10, 0xFFFF, sum = 0
6973 12:42:18.623930 11, 0xFFFF, sum = 0
6974 12:42:18.624174 12, 0xFFFF, sum = 0
6975 12:42:18.627325 13, 0x0, sum = 1
6976 12:42:18.627582 14, 0x0, sum = 2
6977 12:42:18.631533 15, 0x0, sum = 3
6978 12:42:18.631777 16, 0x0, sum = 4
6979 12:42:18.634447 best_step = 14
6980 12:42:18.634684
6981 12:42:18.634821 ==
6982 12:42:18.636849 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 12:42:18.640430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 12:42:18.640609 ==
6985 12:42:18.643768 RX Vref Scan: 0
6986 12:42:18.643964
6987 12:42:18.644125 RX Vref 0 -> 0, step: 1
6988 12:42:18.644257
6989 12:42:18.646641 RX Delay -343 -> 252, step: 8
6990 12:42:18.654846 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6991 12:42:18.658466 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6992 12:42:18.662244 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6993 12:42:18.668379 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6994 12:42:18.671806 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6995 12:42:18.674806 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6996 12:42:18.678002 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6997 12:42:18.684547 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6998 12:42:18.688038 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6999 12:42:18.691489 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
7000 12:42:18.694762 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
7001 12:42:18.701551 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7002 12:42:18.704910 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
7003 12:42:18.707973 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
7004 12:42:18.711529 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7005 12:42:18.717659 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
7006 12:42:18.717743 ==
7007 12:42:18.720591 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 12:42:18.723832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 12:42:18.723916 ==
7010 12:42:18.727548 DQS Delay:
7011 12:42:18.727631 DQS0 = 48, DQS1 = 52
7012 12:42:18.727697 DQM Delay:
7013 12:42:18.730449 DQM0 = 11, DQM1 = 10
7014 12:42:18.730532 DQ Delay:
7015 12:42:18.734527 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
7016 12:42:18.736999 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7017 12:42:18.740140 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7018 12:42:18.743958 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7019 12:42:18.744057
7020 12:42:18.744141
7021 12:42:18.753551 [DQSOSCAuto] RK1, (LSB)MR18= 0x75ad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7022 12:42:18.753635 CH1 RK1: MR19=C0C, MR18=75AD
7023 12:42:18.760642 CH1_RK1: MR19=0xC0C, MR18=0x75AD, DQSOSC=388, MR23=63, INC=392, DEC=261
7024 12:42:18.763659 [RxdqsGatingPostProcess] freq 400
7025 12:42:18.770202 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 12:42:18.773518 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 12:42:18.776707 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 12:42:18.780687 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 12:42:18.784311 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 12:42:18.787011 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 12:42:18.789957 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 12:42:18.793196 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 12:42:18.796401 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 12:42:18.796485 Pre-setting of DQS Precalculation
7035 12:42:18.802860 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 12:42:18.809439 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 12:42:18.816029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 12:42:18.816114
7039 12:42:18.816179
7040 12:42:18.819948 [Calibration Summary] 800 Mbps
7041 12:42:18.822873 CH 0, Rank 0
7042 12:42:18.822957 SW Impedance : PASS
7043 12:42:18.826131 DUTY Scan : NO K
7044 12:42:18.829400 ZQ Calibration : PASS
7045 12:42:18.829484 Jitter Meter : NO K
7046 12:42:18.832758 CBT Training : PASS
7047 12:42:18.836405 Write leveling : PASS
7048 12:42:18.836489 RX DQS gating : PASS
7049 12:42:18.839826 RX DQ/DQS(RDDQC) : PASS
7050 12:42:18.842686 TX DQ/DQS : PASS
7051 12:42:18.842770 RX DATLAT : PASS
7052 12:42:18.845649 RX DQ/DQS(Engine): PASS
7053 12:42:18.849443 TX OE : NO K
7054 12:42:18.849526 All Pass.
7055 12:42:18.849592
7056 12:42:18.849652 CH 0, Rank 1
7057 12:42:18.852345 SW Impedance : PASS
7058 12:42:18.855590 DUTY Scan : NO K
7059 12:42:18.855674 ZQ Calibration : PASS
7060 12:42:18.859375 Jitter Meter : NO K
7061 12:42:18.859460 CBT Training : PASS
7062 12:42:18.862057 Write leveling : NO K
7063 12:42:18.866152 RX DQS gating : PASS
7064 12:42:18.866318 RX DQ/DQS(RDDQC) : PASS
7065 12:42:18.868909 TX DQ/DQS : PASS
7066 12:42:18.872147 RX DATLAT : PASS
7067 12:42:18.872295 RX DQ/DQS(Engine): PASS
7068 12:42:18.875650 TX OE : NO K
7069 12:42:18.875791 All Pass.
7070 12:42:18.875899
7071 12:42:18.878598 CH 1, Rank 0
7072 12:42:18.878732 SW Impedance : PASS
7073 12:42:18.882358 DUTY Scan : NO K
7074 12:42:18.885086 ZQ Calibration : PASS
7075 12:42:18.885199 Jitter Meter : NO K
7076 12:42:18.888886 CBT Training : PASS
7077 12:42:18.892046 Write leveling : PASS
7078 12:42:18.892210 RX DQS gating : PASS
7079 12:42:18.895118 RX DQ/DQS(RDDQC) : PASS
7080 12:42:18.898305 TX DQ/DQS : PASS
7081 12:42:18.898379 RX DATLAT : PASS
7082 12:42:18.901725 RX DQ/DQS(Engine): PASS
7083 12:42:18.905144 TX OE : NO K
7084 12:42:18.905221 All Pass.
7085 12:42:18.905287
7086 12:42:18.905345 CH 1, Rank 1
7087 12:42:18.908080 SW Impedance : PASS
7088 12:42:18.911741 DUTY Scan : NO K
7089 12:42:18.911811 ZQ Calibration : PASS
7090 12:42:18.914759 Jitter Meter : NO K
7091 12:42:18.918067 CBT Training : PASS
7092 12:42:18.918155 Write leveling : NO K
7093 12:42:18.921253 RX DQS gating : PASS
7094 12:42:18.925215 RX DQ/DQS(RDDQC) : PASS
7095 12:42:18.925399 TX DQ/DQS : PASS
7096 12:42:18.927832 RX DATLAT : PASS
7097 12:42:18.931199 RX DQ/DQS(Engine): PASS
7098 12:42:18.931434 TX OE : NO K
7099 12:42:18.934552 All Pass.
7100 12:42:18.934726
7101 12:42:18.934815 DramC Write-DBI off
7102 12:42:18.937748 PER_BANK_REFRESH: Hybrid Mode
7103 12:42:18.937860 TX_TRACKING: ON
7104 12:42:18.947912 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 12:42:18.951279 [FAST_K] Save calibration result to emmc
7106 12:42:18.953990 dramc_set_vcore_voltage set vcore to 725000
7107 12:42:18.957758 Read voltage for 1600, 0
7108 12:42:18.957832 Vio18 = 0
7109 12:42:18.960941 Vcore = 725000
7110 12:42:18.961016 Vdram = 0
7111 12:42:18.961078 Vddq = 0
7112 12:42:18.963858 Vmddr = 0
7113 12:42:18.967276 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 12:42:18.973851 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 12:42:18.973940 MEM_TYPE=3, freq_sel=13
7116 12:42:18.977883 sv_algorithm_assistance_LP4_3733
7117 12:42:18.983807 ============ PULL DRAM RESETB DOWN ============
7118 12:42:18.987118 ========== PULL DRAM RESETB DOWN end =========
7119 12:42:18.990784 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 12:42:18.993653 ===================================
7121 12:42:18.997255 LPDDR4 DRAM CONFIGURATION
7122 12:42:19.000543 ===================================
7123 12:42:19.003692 EX_ROW_EN[0] = 0x0
7124 12:42:19.003791 EX_ROW_EN[1] = 0x0
7125 12:42:19.007008 LP4Y_EN = 0x0
7126 12:42:19.007078 WORK_FSP = 0x1
7127 12:42:19.010077 WL = 0x5
7128 12:42:19.010148 RL = 0x5
7129 12:42:19.013698 BL = 0x2
7130 12:42:19.013766 RPST = 0x0
7131 12:42:19.017311 RD_PRE = 0x0
7132 12:42:19.017393 WR_PRE = 0x1
7133 12:42:19.020483 WR_PST = 0x1
7134 12:42:19.020566 DBI_WR = 0x0
7135 12:42:19.023626 DBI_RD = 0x0
7136 12:42:19.023708 OTF = 0x1
7137 12:42:19.027142 ===================================
7138 12:42:19.029915 ===================================
7139 12:42:19.032972 ANA top config
7140 12:42:19.037292 ===================================
7141 12:42:19.040172 DLL_ASYNC_EN = 0
7142 12:42:19.040272 ALL_SLAVE_EN = 0
7143 12:42:19.043355 NEW_RANK_MODE = 1
7144 12:42:19.046280 DLL_IDLE_MODE = 1
7145 12:42:19.049875 LP45_APHY_COMB_EN = 1
7146 12:42:19.052882 TX_ODT_DIS = 0
7147 12:42:19.052980 NEW_8X_MODE = 1
7148 12:42:19.056772 ===================================
7149 12:42:19.059619 ===================================
7150 12:42:19.062905 data_rate = 3200
7151 12:42:19.066371 CKR = 1
7152 12:42:19.069627 DQ_P2S_RATIO = 8
7153 12:42:19.073080 ===================================
7154 12:42:19.075907 CA_P2S_RATIO = 8
7155 12:42:19.079150 DQ_CA_OPEN = 0
7156 12:42:19.079256 DQ_SEMI_OPEN = 0
7157 12:42:19.082520 CA_SEMI_OPEN = 0
7158 12:42:19.086214 CA_FULL_RATE = 0
7159 12:42:19.089239 DQ_CKDIV4_EN = 0
7160 12:42:19.092536 CA_CKDIV4_EN = 0
7161 12:42:19.096427 CA_PREDIV_EN = 0
7162 12:42:19.096506 PH8_DLY = 12
7163 12:42:19.099308 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 12:42:19.102281 DQ_AAMCK_DIV = 4
7165 12:42:19.105882 CA_AAMCK_DIV = 4
7166 12:42:19.108847 CA_ADMCK_DIV = 4
7167 12:42:19.112539 DQ_TRACK_CA_EN = 0
7168 12:42:19.115738 CA_PICK = 1600
7169 12:42:19.115837 CA_MCKIO = 1600
7170 12:42:19.119096 MCKIO_SEMI = 0
7171 12:42:19.122246 PLL_FREQ = 3068
7172 12:42:19.125956 DQ_UI_PI_RATIO = 32
7173 12:42:19.128641 CA_UI_PI_RATIO = 0
7174 12:42:19.132131 ===================================
7175 12:42:19.135340 ===================================
7176 12:42:19.138796 memory_type:LPDDR4
7177 12:42:19.138898 GP_NUM : 10
7178 12:42:19.141933 SRAM_EN : 1
7179 12:42:19.142041 MD32_EN : 0
7180 12:42:19.145163 ===================================
7181 12:42:19.148695 [ANA_INIT] >>>>>>>>>>>>>>
7182 12:42:19.152201 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 12:42:19.155614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 12:42:19.158470 ===================================
7185 12:42:19.162089 data_rate = 3200,PCW = 0X7600
7186 12:42:19.165200 ===================================
7187 12:42:19.168668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 12:42:19.175543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 12:42:19.178454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 12:42:19.184811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 12:42:19.188316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 12:42:19.191340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 12:42:19.191482 [ANA_INIT] flow start
7194 12:42:19.194595 [ANA_INIT] PLL >>>>>>>>
7195 12:42:19.197891 [ANA_INIT] PLL <<<<<<<<
7196 12:42:19.201759 [ANA_INIT] MIDPI >>>>>>>>
7197 12:42:19.201880 [ANA_INIT] MIDPI <<<<<<<<
7198 12:42:19.205023 [ANA_INIT] DLL >>>>>>>>
7199 12:42:19.208109 [ANA_INIT] DLL <<<<<<<<
7200 12:42:19.208197 [ANA_INIT] flow end
7201 12:42:19.215284 ============ LP4 DIFF to SE enter ============
7202 12:42:19.217703 ============ LP4 DIFF to SE exit ============
7203 12:42:19.217840 [ANA_INIT] <<<<<<<<<<<<<
7204 12:42:19.221080 [Flow] Enable top DCM control >>>>>
7205 12:42:19.224229 [Flow] Enable top DCM control <<<<<
7206 12:42:19.228033 Enable DLL master slave shuffle
7207 12:42:19.234252 ==============================================================
7208 12:42:19.237375 Gating Mode config
7209 12:42:19.241619 ==============================================================
7210 12:42:19.244146 Config description:
7211 12:42:19.253949 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 12:42:19.260876 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 12:42:19.264183 SELPH_MODE 0: By rank 1: By Phase
7214 12:42:19.270543 ==============================================================
7215 12:42:19.274623 GAT_TRACK_EN = 1
7216 12:42:19.277858 RX_GATING_MODE = 2
7217 12:42:19.280994 RX_GATING_TRACK_MODE = 2
7218 12:42:19.284117 SELPH_MODE = 1
7219 12:42:19.284545 PICG_EARLY_EN = 1
7220 12:42:19.287266 VALID_LAT_VALUE = 1
7221 12:42:19.294019 ==============================================================
7222 12:42:19.297261 Enter into Gating configuration >>>>
7223 12:42:19.301040 Exit from Gating configuration <<<<
7224 12:42:19.303575 Enter into DVFS_PRE_config >>>>>
7225 12:42:19.313587 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 12:42:19.317826 Exit from DVFS_PRE_config <<<<<
7227 12:42:19.321057 Enter into PICG configuration >>>>
7228 12:42:19.324334 Exit from PICG configuration <<<<
7229 12:42:19.327111 [RX_INPUT] configuration >>>>>
7230 12:42:19.330231 [RX_INPUT] configuration <<<<<
7231 12:42:19.334127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 12:42:19.340105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 12:42:19.346339 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 12:42:19.353289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 12:42:19.359669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 12:42:19.366319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 12:42:19.369456 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 12:42:19.373486 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 12:42:19.376362 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 12:42:19.382449 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 12:42:19.386348 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 12:42:19.389469 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 12:42:19.392546 ===================================
7244 12:42:19.395965 LPDDR4 DRAM CONFIGURATION
7245 12:42:19.399031 ===================================
7246 12:42:19.399657 EX_ROW_EN[0] = 0x0
7247 12:42:19.402778 EX_ROW_EN[1] = 0x0
7248 12:42:19.406152 LP4Y_EN = 0x0
7249 12:42:19.406577 WORK_FSP = 0x1
7250 12:42:19.409129 WL = 0x5
7251 12:42:19.409554 RL = 0x5
7252 12:42:19.412891 BL = 0x2
7253 12:42:19.413312 RPST = 0x0
7254 12:42:19.416109 RD_PRE = 0x0
7255 12:42:19.416552 WR_PRE = 0x1
7256 12:42:19.419019 WR_PST = 0x1
7257 12:42:19.419502 DBI_WR = 0x0
7258 12:42:19.422214 DBI_RD = 0x0
7259 12:42:19.422642 OTF = 0x1
7260 12:42:19.426254 ===================================
7261 12:42:19.429131 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 12:42:19.435153 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 12:42:19.438578 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 12:42:19.441670 ===================================
7265 12:42:19.445019 LPDDR4 DRAM CONFIGURATION
7266 12:42:19.448475 ===================================
7267 12:42:19.448559 EX_ROW_EN[0] = 0x10
7268 12:42:19.451855 EX_ROW_EN[1] = 0x0
7269 12:42:19.454849 LP4Y_EN = 0x0
7270 12:42:19.454932 WORK_FSP = 0x1
7271 12:42:19.458640 WL = 0x5
7272 12:42:19.458723 RL = 0x5
7273 12:42:19.461497 BL = 0x2
7274 12:42:19.461581 RPST = 0x0
7275 12:42:19.465237 RD_PRE = 0x0
7276 12:42:19.465320 WR_PRE = 0x1
7277 12:42:19.468703 WR_PST = 0x1
7278 12:42:19.468787 DBI_WR = 0x0
7279 12:42:19.471876 DBI_RD = 0x0
7280 12:42:19.471959 OTF = 0x1
7281 12:42:19.474937 ===================================
7282 12:42:19.481817 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 12:42:19.481992 ==
7284 12:42:19.485212 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 12:42:19.488718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 12:42:19.491888 ==
7287 12:42:19.492076 [Duty_Offset_Calibration]
7288 12:42:19.495169 B0:2 B1:0 CA:4
7289 12:42:19.495325
7290 12:42:19.498056 [DutyScan_Calibration_Flow] k_type=0
7291 12:42:19.506804
7292 12:42:19.507041 ==CLK 0==
7293 12:42:19.509967 Final CLK duty delay cell = -4
7294 12:42:19.513345 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7295 12:42:19.516880 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7296 12:42:19.520056 [-4] AVG Duty = 4937%(X100)
7297 12:42:19.520390
7298 12:42:19.523514 CH0 CLK Duty spec in!! Max-Min= 187%
7299 12:42:19.526736 [DutyScan_Calibration_Flow] ====Done====
7300 12:42:19.527140
7301 12:42:19.529205 [DutyScan_Calibration_Flow] k_type=1
7302 12:42:19.547569
7303 12:42:19.548184 ==DQS 0 ==
7304 12:42:19.550295 Final DQS duty delay cell = 0
7305 12:42:19.553653 [0] MAX Duty = 5218%(X100), DQS PI = 22
7306 12:42:19.557332 [0] MIN Duty = 5093%(X100), DQS PI = 2
7307 12:42:19.560988 [0] AVG Duty = 5155%(X100)
7308 12:42:19.561556
7309 12:42:19.562060 ==DQS 1 ==
7310 12:42:19.563906 Final DQS duty delay cell = 0
7311 12:42:19.566618 [0] MAX Duty = 5187%(X100), DQS PI = 2
7312 12:42:19.570123 [0] MIN Duty = 4969%(X100), DQS PI = 10
7313 12:42:19.573394 [0] AVG Duty = 5078%(X100)
7314 12:42:19.573954
7315 12:42:19.576690 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7316 12:42:19.577126
7317 12:42:19.580146 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7318 12:42:19.583081 [DutyScan_Calibration_Flow] ====Done====
7319 12:42:19.583684
7320 12:42:19.586422 [DutyScan_Calibration_Flow] k_type=3
7321 12:42:19.603461
7322 12:42:19.603568 ==DQM 0 ==
7323 12:42:19.607151 Final DQM duty delay cell = 0
7324 12:42:19.610311 [0] MAX Duty = 5124%(X100), DQS PI = 22
7325 12:42:19.613433 [0] MIN Duty = 4875%(X100), DQS PI = 56
7326 12:42:19.616319 [0] AVG Duty = 4999%(X100)
7327 12:42:19.616393
7328 12:42:19.616454 ==DQM 1 ==
7329 12:42:19.619713 Final DQM duty delay cell = 0
7330 12:42:19.623192 [0] MAX Duty = 5000%(X100), DQS PI = 2
7331 12:42:19.627098 [0] MIN Duty = 4844%(X100), DQS PI = 16
7332 12:42:19.629798 [0] AVG Duty = 4922%(X100)
7333 12:42:19.629872
7334 12:42:19.633130 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7335 12:42:19.633204
7336 12:42:19.636656 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7337 12:42:19.639992 [DutyScan_Calibration_Flow] ====Done====
7338 12:42:19.640065
7339 12:42:19.642838 [DutyScan_Calibration_Flow] k_type=2
7340 12:42:19.660417
7341 12:42:19.660499 ==DQ 0 ==
7342 12:42:19.664213 Final DQ duty delay cell = 0
7343 12:42:19.667039 [0] MAX Duty = 5156%(X100), DQS PI = 22
7344 12:42:19.670705 [0] MIN Duty = 4938%(X100), DQS PI = 12
7345 12:42:19.670779 [0] AVG Duty = 5047%(X100)
7346 12:42:19.673724
7347 12:42:19.673799 ==DQ 1 ==
7348 12:42:19.677331 Final DQ duty delay cell = 0
7349 12:42:19.680550 [0] MAX Duty = 5187%(X100), DQS PI = 2
7350 12:42:19.683732 [0] MIN Duty = 4907%(X100), DQS PI = 34
7351 12:42:19.683808 [0] AVG Duty = 5047%(X100)
7352 12:42:19.683871
7353 12:42:19.690365 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7354 12:42:19.690440
7355 12:42:19.693451 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7356 12:42:19.697404 [DutyScan_Calibration_Flow] ====Done====
7357 12:42:19.697477 ==
7358 12:42:19.700479 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 12:42:19.703928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 12:42:19.704001 ==
7361 12:42:19.706882 [Duty_Offset_Calibration]
7362 12:42:19.706953 B0:0 B1:-1 CA:3
7363 12:42:19.707012
7364 12:42:19.710166 [DutyScan_Calibration_Flow] k_type=0
7365 12:42:19.720211
7366 12:42:19.720283 ==CLK 0==
7367 12:42:19.723504 Final CLK duty delay cell = -4
7368 12:42:19.726932 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7369 12:42:19.730178 [-4] MIN Duty = 4844%(X100), DQS PI = 60
7370 12:42:19.733570 [-4] AVG Duty = 4922%(X100)
7371 12:42:19.733641
7372 12:42:19.736680 CH1 CLK Duty spec in!! Max-Min= 156%
7373 12:42:19.739666 [DutyScan_Calibration_Flow] ====Done====
7374 12:42:19.739737
7375 12:42:19.743238 [DutyScan_Calibration_Flow] k_type=1
7376 12:42:19.759212
7377 12:42:19.759317 ==DQS 0 ==
7378 12:42:19.762596 Final DQS duty delay cell = 0
7379 12:42:19.765894 [0] MAX Duty = 5250%(X100), DQS PI = 28
7380 12:42:19.769694 [0] MIN Duty = 4907%(X100), DQS PI = 60
7381 12:42:19.772555 [0] AVG Duty = 5078%(X100)
7382 12:42:19.772627
7383 12:42:19.772717 ==DQS 1 ==
7384 12:42:19.775868 Final DQS duty delay cell = -4
7385 12:42:19.778810 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7386 12:42:19.782269 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7387 12:42:19.785444 [-4] AVG Duty = 4906%(X100)
7388 12:42:19.785519
7389 12:42:19.788702 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7390 12:42:19.788831
7391 12:42:19.792001 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7392 12:42:19.795285 [DutyScan_Calibration_Flow] ====Done====
7393 12:42:19.795416
7394 12:42:19.798518 [DutyScan_Calibration_Flow] k_type=3
7395 12:42:19.816716
7396 12:42:19.816798 ==DQM 0 ==
7397 12:42:19.820192 Final DQM duty delay cell = 0
7398 12:42:19.822928 [0] MAX Duty = 5062%(X100), DQS PI = 30
7399 12:42:19.826054 [0] MIN Duty = 4782%(X100), DQS PI = 40
7400 12:42:19.830074 [0] AVG Duty = 4922%(X100)
7401 12:42:19.830146
7402 12:42:19.830207 ==DQM 1 ==
7403 12:42:19.832879 Final DQM duty delay cell = 0
7404 12:42:19.836202 [0] MAX Duty = 5000%(X100), DQS PI = 32
7405 12:42:19.839460 [0] MIN Duty = 4813%(X100), DQS PI = 0
7406 12:42:19.843194 [0] AVG Duty = 4906%(X100)
7407 12:42:19.843295
7408 12:42:19.846359 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7409 12:42:19.846436
7410 12:42:19.849161 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7411 12:42:19.853096 [DutyScan_Calibration_Flow] ====Done====
7412 12:42:19.853172
7413 12:42:19.855893 [DutyScan_Calibration_Flow] k_type=2
7414 12:42:19.872750
7415 12:42:19.872828 ==DQ 0 ==
7416 12:42:19.875786 Final DQ duty delay cell = -4
7417 12:42:19.879025 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7418 12:42:19.882312 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7419 12:42:19.885653 [-4] AVG Duty = 4875%(X100)
7420 12:42:19.885728
7421 12:42:19.885793 ==DQ 1 ==
7422 12:42:19.888939 Final DQ duty delay cell = 0
7423 12:42:19.892121 [0] MAX Duty = 5062%(X100), DQS PI = 30
7424 12:42:19.896059 [0] MIN Duty = 4875%(X100), DQS PI = 0
7425 12:42:19.898768 [0] AVG Duty = 4968%(X100)
7426 12:42:19.898840
7427 12:42:19.902727 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7428 12:42:19.902804
7429 12:42:19.905376 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7430 12:42:19.908925 [DutyScan_Calibration_Flow] ====Done====
7431 12:42:19.911965 nWR fixed to 30
7432 12:42:19.915662 [ModeRegInit_LP4] CH0 RK0
7433 12:42:19.915735 [ModeRegInit_LP4] CH0 RK1
7434 12:42:19.918843 [ModeRegInit_LP4] CH1 RK0
7435 12:42:19.922018 [ModeRegInit_LP4] CH1 RK1
7436 12:42:19.922090 match AC timing 5
7437 12:42:19.928262 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 12:42:19.931946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 12:42:19.935432 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 12:42:19.941215 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 12:42:19.944784 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 12:42:19.947859 [MiockJmeterHQA]
7443 12:42:19.947935
7444 12:42:19.951490 [DramcMiockJmeter] u1RxGatingPI = 0
7445 12:42:19.951566 0 : 4252, 4027
7446 12:42:19.951628 4 : 4363, 4137
7447 12:42:19.954669 8 : 4253, 4026
7448 12:42:19.954743 12 : 4252, 4027
7449 12:42:19.957675 16 : 4366, 4139
7450 12:42:19.957746 20 : 4253, 4027
7451 12:42:19.961338 24 : 4257, 4032
7452 12:42:19.961412 28 : 4363, 4138
7453 12:42:19.961479 32 : 4253, 4026
7454 12:42:19.964601 36 : 4252, 4027
7455 12:42:19.964672 40 : 4250, 4027
7456 12:42:19.968309 44 : 4252, 4027
7457 12:42:19.968378 48 : 4253, 4027
7458 12:42:19.971535 52 : 4363, 4137
7459 12:42:19.971607 56 : 4363, 4138
7460 12:42:19.974655 60 : 4363, 4140
7461 12:42:19.974723 64 : 4250, 4027
7462 12:42:19.974783 68 : 4252, 4029
7463 12:42:19.978055 72 : 4250, 4027
7464 12:42:19.978128 76 : 4250, 4027
7465 12:42:19.981314 80 : 4361, 4137
7466 12:42:19.981385 84 : 4250, 4026
7467 12:42:19.984467 88 : 4250, 4027
7468 12:42:19.984539 92 : 4250, 4027
7469 12:42:19.987829 96 : 4250, 3021
7470 12:42:19.987900 100 : 4252, 0
7471 12:42:19.987961 104 : 4253, 0
7472 12:42:19.991106 108 : 4250, 0
7473 12:42:19.991181 112 : 4250, 0
7474 12:42:19.994020 116 : 4250, 0
7475 12:42:19.994093 120 : 4361, 0
7476 12:42:19.994158 124 : 4365, 0
7477 12:42:19.997438 128 : 4363, 0
7478 12:42:19.997513 132 : 4250, 0
7479 12:42:19.997576 136 : 4249, 0
7480 12:42:20.001575 140 : 4249, 0
7481 12:42:20.001649 144 : 4250, 0
7482 12:42:20.004378 148 : 4250, 0
7483 12:42:20.004449 152 : 4360, 0
7484 12:42:20.004514 156 : 4250, 0
7485 12:42:20.008333 160 : 4250, 0
7486 12:42:20.008403 164 : 4249, 0
7487 12:42:20.010818 168 : 4255, 0
7488 12:42:20.010888 172 : 4361, 0
7489 12:42:20.010992 176 : 4250, 0
7490 12:42:20.014158 180 : 4360, 0
7491 12:42:20.014235 184 : 4250, 0
7492 12:42:20.017701 188 : 4250, 0
7493 12:42:20.017771 192 : 4360, 0
7494 12:42:20.017832 196 : 4252, 0
7495 12:42:20.020726 200 : 4250, 0
7496 12:42:20.020795 204 : 4360, 0
7497 12:42:20.023818 208 : 4250, 0
7498 12:42:20.023887 212 : 4250, 0
7499 12:42:20.023948 216 : 4249, 0
7500 12:42:20.027162 220 : 4253, 329
7501 12:42:20.027233 224 : 4250, 4007
7502 12:42:20.030664 228 : 4252, 4029
7503 12:42:20.030736 232 : 4255, 4032
7504 12:42:20.033695 236 : 4363, 4140
7505 12:42:20.033763 240 : 4360, 4138
7506 12:42:20.037199 244 : 4252, 4027
7507 12:42:20.037274 248 : 4250, 4027
7508 12:42:20.040648 252 : 4363, 4140
7509 12:42:20.040718 256 : 4250, 4027
7510 12:42:20.040780 260 : 4250, 4027
7511 12:42:20.043704 264 : 4250, 4027
7512 12:42:20.043783 268 : 4253, 4029
7513 12:42:20.046886 272 : 4250, 4027
7514 12:42:20.046963 276 : 4361, 4137
7515 12:42:20.050221 280 : 4360, 4137
7516 12:42:20.050294 284 : 4250, 4026
7517 12:42:20.053405 288 : 4250, 4027
7518 12:42:20.053479 292 : 4250, 4027
7519 12:42:20.057320 296 : 4249, 4027
7520 12:42:20.057389 300 : 4249, 4027
7521 12:42:20.060194 304 : 4361, 4137
7522 12:42:20.060263 308 : 4250, 4027
7523 12:42:20.064300 312 : 4249, 4027
7524 12:42:20.064373 316 : 4362, 4140
7525 12:42:20.066743 320 : 4250, 4026
7526 12:42:20.066810 324 : 4250, 4027
7527 12:42:20.066870 328 : 4361, 4137
7528 12:42:20.070021 332 : 4360, 4101
7529 12:42:20.070091 336 : 4250, 1921
7530 12:42:20.070150
7531 12:42:20.073251 MIOCK jitter meter ch=0
7532 12:42:20.073318
7533 12:42:20.076944 1T = (336-100) = 236 dly cells
7534 12:42:20.083338 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7535 12:42:20.083465 ==
7536 12:42:20.086858 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 12:42:20.089625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 12:42:20.089697 ==
7539 12:42:20.096587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 12:42:20.100041 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 12:42:20.103227 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 12:42:20.109485 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 12:42:20.119122 [CA 0] Center 44 (14~74) winsize 61
7544 12:42:20.123635 [CA 1] Center 43 (13~74) winsize 62
7545 12:42:20.125817 [CA 2] Center 39 (10~68) winsize 59
7546 12:42:20.128604 [CA 3] Center 38 (9~68) winsize 60
7547 12:42:20.132132 [CA 4] Center 36 (7~66) winsize 60
7548 12:42:20.135476 [CA 5] Center 36 (6~66) winsize 61
7549 12:42:20.135546
7550 12:42:20.139526 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7551 12:42:20.139597
7552 12:42:20.145062 [CATrainingPosCal] consider 1 rank data
7553 12:42:20.145144 u2DelayCellTimex100 = 275/100 ps
7554 12:42:20.151943 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7555 12:42:20.155344 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7556 12:42:20.159057 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7557 12:42:20.161929 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7558 12:42:20.164857 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7559 12:42:20.168318 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7560 12:42:20.168410
7561 12:42:20.172099 CA PerBit enable=1, Macro0, CA PI delay=36
7562 12:42:20.172175
7563 12:42:20.174775 [CBTSetCACLKResult] CA Dly = 36
7564 12:42:20.178314 CS Dly: 10 (0~41)
7565 12:42:20.181455 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 12:42:20.184926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 12:42:20.185005 ==
7568 12:42:20.188348 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 12:42:20.195164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 12:42:20.195285 ==
7571 12:42:20.198284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 12:42:20.204414 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 12:42:20.208306 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 12:42:20.214657 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 12:42:20.222965 [CA 0] Center 43 (13~74) winsize 62
7576 12:42:20.225848 [CA 1] Center 43 (13~73) winsize 61
7577 12:42:20.229956 [CA 2] Center 38 (9~68) winsize 60
7578 12:42:20.232558 [CA 3] Center 38 (9~68) winsize 60
7579 12:42:20.235667 [CA 4] Center 36 (6~66) winsize 61
7580 12:42:20.239597 [CA 5] Center 36 (6~66) winsize 61
7581 12:42:20.239678
7582 12:42:20.242433 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 12:42:20.242534
7584 12:42:20.245609 [CATrainingPosCal] consider 2 rank data
7585 12:42:20.249041 u2DelayCellTimex100 = 275/100 ps
7586 12:42:20.256516 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7587 12:42:20.259045 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7588 12:42:20.261944 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7589 12:42:20.265342 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7590 12:42:20.268908 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7591 12:42:20.272233 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7592 12:42:20.272313
7593 12:42:20.275110 CA PerBit enable=1, Macro0, CA PI delay=36
7594 12:42:20.275229
7595 12:42:20.278248 [CBTSetCACLKResult] CA Dly = 36
7596 12:42:20.282044 CS Dly: 11 (0~43)
7597 12:42:20.284984 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 12:42:20.288459 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 12:42:20.288539
7600 12:42:20.291679 ----->DramcWriteLeveling(PI) begin...
7601 12:42:20.295115 ==
7602 12:42:20.297900 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 12:42:20.301764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 12:42:20.301845 ==
7605 12:42:20.304923 Write leveling (Byte 0): 34 => 34
7606 12:42:20.308458 Write leveling (Byte 1): 25 => 25
7607 12:42:20.311822 DramcWriteLeveling(PI) end<-----
7608 12:42:20.311901
7609 12:42:20.311966 ==
7610 12:42:20.314575 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 12:42:20.317785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 12:42:20.317888 ==
7613 12:42:20.321405 [Gating] SW mode calibration
7614 12:42:20.328139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 12:42:20.334283 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 12:42:20.337515 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:42:20.340973 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 12:42:20.347587 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7619 12:42:20.350746 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7620 12:42:20.353930 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7621 12:42:20.360730 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7622 12:42:20.363710 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 12:42:20.367224 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 12:42:20.374045 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 12:42:20.377188 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 12:42:20.380500 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7627 12:42:20.387477 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7628 12:42:20.390413 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7629 12:42:20.393541 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7630 12:42:20.400531 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7631 12:42:20.404281 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:42:20.406599 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:42:20.413134 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 12:42:20.416739 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7635 12:42:20.419734 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7636 12:42:20.426113 1 6 16 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
7637 12:42:20.429901 1 6 20 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
7638 12:42:20.432930 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 12:42:20.439854 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 12:42:20.442584 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 12:42:20.446037 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 12:42:20.452595 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 12:42:20.455852 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 12:42:20.459280 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7645 12:42:20.465844 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7646 12:42:20.469138 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 12:42:20.472513 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:42:20.479307 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:42:20.482512 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:42:20.485568 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:42:20.492423 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:42:20.495509 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:42:20.498677 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:42:20.506060 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:42:20.508779 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:42:20.512357 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:42:20.518660 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 12:42:20.522186 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 12:42:20.525208 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7660 12:42:20.529179 Total UI for P1: 0, mck2ui 16
7661 12:42:20.531965 best dqsien dly found for B0: ( 1, 9, 8)
7662 12:42:20.538151 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7663 12:42:20.541876 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7664 12:42:20.544738 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 12:42:20.548904 Total UI for P1: 0, mck2ui 16
7666 12:42:20.551730 best dqsien dly found for B1: ( 1, 9, 20)
7667 12:42:20.554528 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7668 12:42:20.558102 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7669 12:42:20.561251
7670 12:42:20.564647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7671 12:42:20.568050 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7672 12:42:20.570994 [Gating] SW calibration Done
7673 12:42:20.571067 ==
7674 12:42:20.574620 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 12:42:20.577715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 12:42:20.577790 ==
7677 12:42:20.581077 RX Vref Scan: 0
7678 12:42:20.581150
7679 12:42:20.581212 RX Vref 0 -> 0, step: 1
7680 12:42:20.581272
7681 12:42:20.584869 RX Delay 0 -> 252, step: 8
7682 12:42:20.587601 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7683 12:42:20.591252 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7684 12:42:20.597384 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7685 12:42:20.600860 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7686 12:42:20.604193 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7687 12:42:20.607667 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7688 12:42:20.610569 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7689 12:42:20.617307 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7690 12:42:20.620990 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7691 12:42:20.623961 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7692 12:42:20.627183 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7693 12:42:20.633733 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7694 12:42:20.636830 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7695 12:42:20.641092 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7696 12:42:20.643863 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7697 12:42:20.646612 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7698 12:42:20.650014 ==
7699 12:42:20.653300 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:42:20.656794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:42:20.656872 ==
7702 12:42:20.656965 DQS Delay:
7703 12:42:20.659765 DQS0 = 0, DQS1 = 0
7704 12:42:20.659910 DQM Delay:
7705 12:42:20.663203 DQM0 = 131, DQM1 = 127
7706 12:42:20.663304 DQ Delay:
7707 12:42:20.666995 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7708 12:42:20.670051 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7709 12:42:20.673285 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7710 12:42:20.676232 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7711 12:42:20.676313
7712 12:42:20.676376
7713 12:42:20.680099 ==
7714 12:42:20.683240 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 12:42:20.686891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 12:42:20.686971 ==
7717 12:42:20.687036
7718 12:42:20.687097
7719 12:42:20.689622 TX Vref Scan disable
7720 12:42:20.689722 == TX Byte 0 ==
7721 12:42:20.693027 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7722 12:42:20.699761 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7723 12:42:20.699847 == TX Byte 1 ==
7724 12:42:20.705745 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7725 12:42:20.709422 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7726 12:42:20.709515 ==
7727 12:42:20.712678 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 12:42:20.715745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 12:42:20.715822 ==
7730 12:42:20.730071
7731 12:42:20.733160 TX Vref early break, caculate TX vref
7732 12:42:20.736649 TX Vref=16, minBit 1, minWin=22, winSum=370
7733 12:42:20.740546 TX Vref=18, minBit 6, minWin=22, winSum=378
7734 12:42:20.743033 TX Vref=20, minBit 1, minWin=23, winSum=386
7735 12:42:20.746673 TX Vref=22, minBit 4, minWin=24, winSum=399
7736 12:42:20.750107 TX Vref=24, minBit 8, minWin=24, winSum=407
7737 12:42:20.756235 TX Vref=26, minBit 4, minWin=25, winSum=416
7738 12:42:20.760232 TX Vref=28, minBit 4, minWin=25, winSum=417
7739 12:42:20.762696 TX Vref=30, minBit 1, minWin=25, winSum=412
7740 12:42:20.766262 TX Vref=32, minBit 0, minWin=25, winSum=409
7741 12:42:20.769284 TX Vref=34, minBit 0, minWin=24, winSum=395
7742 12:42:20.776365 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
7743 12:42:20.776447
7744 12:42:20.779285 Final TX Range 0 Vref 28
7745 12:42:20.779408
7746 12:42:20.779479 ==
7747 12:42:20.782943 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 12:42:20.786284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 12:42:20.786391 ==
7750 12:42:20.786482
7751 12:42:20.786553
7752 12:42:20.789396 TX Vref Scan disable
7753 12:42:20.796051 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7754 12:42:20.796156 == TX Byte 0 ==
7755 12:42:20.799587 u2DelayCellOfst[0]=14 cells (4 PI)
7756 12:42:20.803112 u2DelayCellOfst[1]=17 cells (5 PI)
7757 12:42:20.805751 u2DelayCellOfst[2]=10 cells (3 PI)
7758 12:42:20.809502 u2DelayCellOfst[3]=14 cells (4 PI)
7759 12:42:20.812247 u2DelayCellOfst[4]=10 cells (3 PI)
7760 12:42:20.816133 u2DelayCellOfst[5]=0 cells (0 PI)
7761 12:42:20.819725 u2DelayCellOfst[6]=17 cells (5 PI)
7762 12:42:20.822869 u2DelayCellOfst[7]=17 cells (5 PI)
7763 12:42:20.825871 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7764 12:42:20.829056 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7765 12:42:20.832324 == TX Byte 1 ==
7766 12:42:20.836765 u2DelayCellOfst[8]=0 cells (0 PI)
7767 12:42:20.838879 u2DelayCellOfst[9]=0 cells (0 PI)
7768 12:42:20.838954 u2DelayCellOfst[10]=3 cells (1 PI)
7769 12:42:20.842163 u2DelayCellOfst[11]=0 cells (0 PI)
7770 12:42:20.846250 u2DelayCellOfst[12]=7 cells (2 PI)
7771 12:42:20.849098 u2DelayCellOfst[13]=10 cells (3 PI)
7772 12:42:20.853023 u2DelayCellOfst[14]=14 cells (4 PI)
7773 12:42:20.855684 u2DelayCellOfst[15]=7 cells (2 PI)
7774 12:42:20.862463 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7775 12:42:20.865408 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7776 12:42:20.865494 DramC Write-DBI on
7777 12:42:20.865567 ==
7778 12:42:20.868642 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 12:42:20.875516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 12:42:20.875623 ==
7781 12:42:20.875709
7782 12:42:20.875790
7783 12:42:20.875868 TX Vref Scan disable
7784 12:42:20.879759 == TX Byte 0 ==
7785 12:42:20.883044 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7786 12:42:20.886085 == TX Byte 1 ==
7787 12:42:20.889483 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7788 12:42:20.893173 DramC Write-DBI off
7789 12:42:20.893313
7790 12:42:20.893467 [DATLAT]
7791 12:42:20.893582 Freq=1600, CH0 RK0
7792 12:42:20.893693
7793 12:42:20.896013 DATLAT Default: 0xf
7794 12:42:20.899719 0, 0xFFFF, sum = 0
7795 12:42:20.899938 1, 0xFFFF, sum = 0
7796 12:42:20.903012 2, 0xFFFF, sum = 0
7797 12:42:20.903205 3, 0xFFFF, sum = 0
7798 12:42:20.906376 4, 0xFFFF, sum = 0
7799 12:42:20.906605 5, 0xFFFF, sum = 0
7800 12:42:20.909860 6, 0xFFFF, sum = 0
7801 12:42:20.910139 7, 0xFFFF, sum = 0
7802 12:42:20.912760 8, 0xFFFF, sum = 0
7803 12:42:20.913040 9, 0xFFFF, sum = 0
7804 12:42:20.915859 10, 0xFFFF, sum = 0
7805 12:42:20.916223 11, 0xFFFF, sum = 0
7806 12:42:20.919434 12, 0xFFFF, sum = 0
7807 12:42:20.919897 13, 0xFFFF, sum = 0
7808 12:42:20.922626 14, 0x0, sum = 1
7809 12:42:20.923063 15, 0x0, sum = 2
7810 12:42:20.925773 16, 0x0, sum = 3
7811 12:42:20.926245 17, 0x0, sum = 4
7812 12:42:20.929590 best_step = 15
7813 12:42:20.930058
7814 12:42:20.930518 ==
7815 12:42:20.932825 Dram Type= 6, Freq= 0, CH_0, rank 0
7816 12:42:20.935703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7817 12:42:20.936144 ==
7818 12:42:20.938877 RX Vref Scan: 1
7819 12:42:20.939312
7820 12:42:20.939803 Set Vref Range= 24 -> 127
7821 12:42:20.940219
7822 12:42:20.942325 RX Vref 24 -> 127, step: 1
7823 12:42:20.942761
7824 12:42:20.946128 RX Delay 11 -> 252, step: 4
7825 12:42:20.946564
7826 12:42:20.948751 Set Vref, RX VrefLevel [Byte0]: 24
7827 12:42:20.952574 [Byte1]: 24
7828 12:42:20.953161
7829 12:42:20.955804 Set Vref, RX VrefLevel [Byte0]: 25
7830 12:42:20.958977 [Byte1]: 25
7831 12:42:20.962746
7832 12:42:20.963219 Set Vref, RX VrefLevel [Byte0]: 26
7833 12:42:20.965939 [Byte1]: 26
7834 12:42:20.970224
7835 12:42:20.970859 Set Vref, RX VrefLevel [Byte0]: 27
7836 12:42:20.973802 [Byte1]: 27
7837 12:42:20.977812
7838 12:42:20.978376 Set Vref, RX VrefLevel [Byte0]: 28
7839 12:42:20.981582 [Byte1]: 28
7840 12:42:20.985404
7841 12:42:20.986034 Set Vref, RX VrefLevel [Byte0]: 29
7842 12:42:20.988589 [Byte1]: 29
7843 12:42:20.992994
7844 12:42:20.993416 Set Vref, RX VrefLevel [Byte0]: 30
7845 12:42:20.996314 [Byte1]: 30
7846 12:42:21.001284
7847 12:42:21.001709 Set Vref, RX VrefLevel [Byte0]: 31
7848 12:42:21.004168 [Byte1]: 31
7849 12:42:21.008486
7850 12:42:21.008909 Set Vref, RX VrefLevel [Byte0]: 32
7851 12:42:21.011536 [Byte1]: 32
7852 12:42:21.016047
7853 12:42:21.016468 Set Vref, RX VrefLevel [Byte0]: 33
7854 12:42:21.019444 [Byte1]: 33
7855 12:42:21.024284
7856 12:42:21.024708 Set Vref, RX VrefLevel [Byte0]: 34
7857 12:42:21.026966 [Byte1]: 34
7858 12:42:21.031222
7859 12:42:21.031892 Set Vref, RX VrefLevel [Byte0]: 35
7860 12:42:21.034388 [Byte1]: 35
7861 12:42:21.039120
7862 12:42:21.039585 Set Vref, RX VrefLevel [Byte0]: 36
7863 12:42:21.042224 [Byte1]: 36
7864 12:42:21.046463
7865 12:42:21.047072 Set Vref, RX VrefLevel [Byte0]: 37
7866 12:42:21.049788 [Byte1]: 37
7867 12:42:21.053976
7868 12:42:21.054538 Set Vref, RX VrefLevel [Byte0]: 38
7869 12:42:21.057405 [Byte1]: 38
7870 12:42:21.061363
7871 12:42:21.061951 Set Vref, RX VrefLevel [Byte0]: 39
7872 12:42:21.065310 [Byte1]: 39
7873 12:42:21.069975
7874 12:42:21.070516 Set Vref, RX VrefLevel [Byte0]: 40
7875 12:42:21.072866 [Byte1]: 40
7876 12:42:21.077760
7877 12:42:21.078293 Set Vref, RX VrefLevel [Byte0]: 41
7878 12:42:21.080172 [Byte1]: 41
7879 12:42:21.084435
7880 12:42:21.084857 Set Vref, RX VrefLevel [Byte0]: 42
7881 12:42:21.087706 [Byte1]: 42
7882 12:42:21.092111
7883 12:42:21.092629 Set Vref, RX VrefLevel [Byte0]: 43
7884 12:42:21.096226 [Byte1]: 43
7885 12:42:21.099685
7886 12:42:21.100128 Set Vref, RX VrefLevel [Byte0]: 44
7887 12:42:21.103476 [Byte1]: 44
7888 12:42:21.107484
7889 12:42:21.107947 Set Vref, RX VrefLevel [Byte0]: 45
7890 12:42:21.110523 [Byte1]: 45
7891 12:42:21.115287
7892 12:42:21.115787 Set Vref, RX VrefLevel [Byte0]: 46
7893 12:42:21.118932 [Byte1]: 46
7894 12:42:21.122845
7895 12:42:21.123312 Set Vref, RX VrefLevel [Byte0]: 47
7896 12:42:21.125906 [Byte1]: 47
7897 12:42:21.130359
7898 12:42:21.130793 Set Vref, RX VrefLevel [Byte0]: 48
7899 12:42:21.133816 [Byte1]: 48
7900 12:42:21.137977
7901 12:42:21.138476 Set Vref, RX VrefLevel [Byte0]: 49
7902 12:42:21.141105 [Byte1]: 49
7903 12:42:21.145710
7904 12:42:21.146174 Set Vref, RX VrefLevel [Byte0]: 50
7905 12:42:21.149101 [Byte1]: 50
7906 12:42:21.153133
7907 12:42:21.153572 Set Vref, RX VrefLevel [Byte0]: 51
7908 12:42:21.156088 [Byte1]: 51
7909 12:42:21.160805
7910 12:42:21.161292 Set Vref, RX VrefLevel [Byte0]: 52
7911 12:42:21.164480 [Byte1]: 52
7912 12:42:21.168408
7913 12:42:21.168826 Set Vref, RX VrefLevel [Byte0]: 53
7914 12:42:21.171522 [Byte1]: 53
7915 12:42:21.176110
7916 12:42:21.176643 Set Vref, RX VrefLevel [Byte0]: 54
7917 12:42:21.179335 [Byte1]: 54
7918 12:42:21.183312
7919 12:42:21.183777 Set Vref, RX VrefLevel [Byte0]: 55
7920 12:42:21.187185 [Byte1]: 55
7921 12:42:21.190785
7922 12:42:21.191204 Set Vref, RX VrefLevel [Byte0]: 56
7923 12:42:21.194216 [Byte1]: 56
7924 12:42:21.198848
7925 12:42:21.199282 Set Vref, RX VrefLevel [Byte0]: 57
7926 12:42:21.201924 [Byte1]: 57
7927 12:42:21.206535
7928 12:42:21.207101 Set Vref, RX VrefLevel [Byte0]: 58
7929 12:42:21.209742 [Byte1]: 58
7930 12:42:21.213933
7931 12:42:21.214469 Set Vref, RX VrefLevel [Byte0]: 59
7932 12:42:21.217056 [Byte1]: 59
7933 12:42:21.221314
7934 12:42:21.221742 Set Vref, RX VrefLevel [Byte0]: 60
7935 12:42:21.224957 [Byte1]: 60
7936 12:42:21.229328
7937 12:42:21.229702 Set Vref, RX VrefLevel [Byte0]: 61
7938 12:42:21.232371 [Byte1]: 61
7939 12:42:21.236871
7940 12:42:21.237255 Set Vref, RX VrefLevel [Byte0]: 62
7941 12:42:21.240038 [Byte1]: 62
7942 12:42:21.244726
7943 12:42:21.245253 Set Vref, RX VrefLevel [Byte0]: 63
7944 12:42:21.247697 [Byte1]: 63
7945 12:42:21.251871
7946 12:42:21.252378 Set Vref, RX VrefLevel [Byte0]: 64
7947 12:42:21.256309 [Byte1]: 64
7948 12:42:21.259627
7949 12:42:21.260025 Set Vref, RX VrefLevel [Byte0]: 65
7950 12:42:21.262961 [Byte1]: 65
7951 12:42:21.267540
7952 12:42:21.267929 Set Vref, RX VrefLevel [Byte0]: 66
7953 12:42:21.270411 [Byte1]: 66
7954 12:42:21.274930
7955 12:42:21.275347 Set Vref, RX VrefLevel [Byte0]: 67
7956 12:42:21.278203 [Byte1]: 67
7957 12:42:21.282618
7958 12:42:21.283154 Set Vref, RX VrefLevel [Byte0]: 68
7959 12:42:21.285983 [Byte1]: 68
7960 12:42:21.289905
7961 12:42:21.290316 Set Vref, RX VrefLevel [Byte0]: 69
7962 12:42:21.293538 [Byte1]: 69
7963 12:42:21.297680
7964 12:42:21.298081 Set Vref, RX VrefLevel [Byte0]: 70
7965 12:42:21.301220 [Byte1]: 70
7966 12:42:21.305294
7967 12:42:21.305683 Set Vref, RX VrefLevel [Byte0]: 71
7968 12:42:21.308753 [Byte1]: 71
7969 12:42:21.312812
7970 12:42:21.313351 Set Vref, RX VrefLevel [Byte0]: 72
7971 12:42:21.316168 [Byte1]: 72
7972 12:42:21.320111
7973 12:42:21.320615 Set Vref, RX VrefLevel [Byte0]: 73
7974 12:42:21.323918 [Byte1]: 73
7975 12:42:21.328196
7976 12:42:21.328887 Final RX Vref Byte 0 = 56 to rank0
7977 12:42:21.331232 Final RX Vref Byte 1 = 59 to rank0
7978 12:42:21.334639 Final RX Vref Byte 0 = 56 to rank1
7979 12:42:21.337899 Final RX Vref Byte 1 = 59 to rank1==
7980 12:42:21.341908 Dram Type= 6, Freq= 0, CH_0, rank 0
7981 12:42:21.347769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 12:42:21.348492 ==
7983 12:42:21.348999 DQS Delay:
7984 12:42:21.351516 DQS0 = 0, DQS1 = 0
7985 12:42:21.352232 DQM Delay:
7986 12:42:21.352824 DQM0 = 128, DQM1 = 123
7987 12:42:21.354339 DQ Delay:
7988 12:42:21.357646 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7989 12:42:21.361326 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7990 12:42:21.364442 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =120
7991 12:42:21.367406 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7992 12:42:21.367870
7993 12:42:21.368255
7994 12:42:21.368630
7995 12:42:21.371064 [DramC_TX_OE_Calibration] TA2
7996 12:42:21.374322 Original DQ_B0 (3 6) =30, OEN = 27
7997 12:42:21.377255 Original DQ_B1 (3 6) =30, OEN = 27
7998 12:42:21.380700 24, 0x0, End_B0=24 End_B1=24
7999 12:42:21.384007 25, 0x0, End_B0=25 End_B1=25
8000 12:42:21.384646 26, 0x0, End_B0=26 End_B1=26
8001 12:42:21.388356 27, 0x0, End_B0=27 End_B1=27
8002 12:42:21.390856 28, 0x0, End_B0=28 End_B1=28
8003 12:42:21.394081 29, 0x0, End_B0=29 End_B1=29
8004 12:42:21.394659 30, 0x0, End_B0=30 End_B1=30
8005 12:42:21.397190 31, 0x4141, End_B0=30 End_B1=30
8006 12:42:21.400902 Byte0 end_step=30 best_step=27
8007 12:42:21.404426 Byte1 end_step=30 best_step=27
8008 12:42:21.407263 Byte0 TX OE(2T, 0.5T) = (3, 3)
8009 12:42:21.410408 Byte1 TX OE(2T, 0.5T) = (3, 3)
8010 12:42:21.410870
8011 12:42:21.411417
8012 12:42:21.417582 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
8013 12:42:21.420615 CH0 RK0: MR19=303, MR18=1916
8014 12:42:21.427254 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
8015 12:42:21.427768
8016 12:42:21.431206 ----->DramcWriteLeveling(PI) begin...
8017 12:42:21.431747 ==
8018 12:42:21.433672 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 12:42:21.436870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 12:42:21.437299 ==
8021 12:42:21.440432 Write leveling (Byte 0): 35 => 35
8022 12:42:21.443412 Write leveling (Byte 1): 27 => 27
8023 12:42:21.446855 DramcWriteLeveling(PI) end<-----
8024 12:42:21.447300
8025 12:42:21.447749 ==
8026 12:42:21.450115 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 12:42:21.453451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 12:42:21.456516 ==
8029 12:42:21.456987 [Gating] SW mode calibration
8030 12:42:21.466415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8031 12:42:21.469971 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8032 12:42:21.474040 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 12:42:21.479807 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:42:21.483113 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8035 12:42:21.486703 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8036 12:42:21.493069 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8037 12:42:21.497356 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8038 12:42:21.499413 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 12:42:21.506462 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 12:42:21.510081 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 12:42:21.513165 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8042 12:42:21.519695 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8043 12:42:21.522763 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8044 12:42:21.526343 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8045 12:42:21.533436 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8046 12:42:21.536018 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 12:42:21.538835 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 12:42:21.545409 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 12:42:21.548898 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8050 12:42:21.552083 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
8051 12:42:21.558755 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8052 12:42:21.562312 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8053 12:42:21.568640 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8054 12:42:21.571587 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 12:42:21.574766 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 12:42:21.578588 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 12:42:21.585234 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 12:42:21.588380 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8059 12:42:21.591882 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8060 12:42:21.598255 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8061 12:42:21.602307 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8062 12:42:21.605244 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:42:21.612029 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:42:21.617334 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:42:21.618443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:42:21.625041 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:42:21.629367 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:42:21.632168 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:42:21.638635 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:42:21.641466 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 12:42:21.644779 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 12:42:21.651467 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 12:42:21.654908 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8074 12:42:21.657803 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8075 12:42:21.665033 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 12:42:21.667537 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8077 12:42:21.670962 Total UI for P1: 0, mck2ui 16
8078 12:42:21.674255 best dqsien dly found for B0: ( 1, 9, 8)
8079 12:42:21.677807 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8080 12:42:21.684103 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 12:42:21.688159 Total UI for P1: 0, mck2ui 16
8082 12:42:21.690708 best dqsien dly found for B1: ( 1, 9, 20)
8083 12:42:21.694795 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8084 12:42:21.697510 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8085 12:42:21.698084
8086 12:42:21.700838 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8087 12:42:21.704021 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8088 12:42:21.707357 [Gating] SW calibration Done
8089 12:42:21.707863 ==
8090 12:42:21.710671 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 12:42:21.713638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 12:42:21.714115 ==
8093 12:42:21.717238 RX Vref Scan: 0
8094 12:42:21.717760
8095 12:42:21.720141 RX Vref 0 -> 0, step: 1
8096 12:42:21.720568
8097 12:42:21.720909 RX Delay 0 -> 252, step: 8
8098 12:42:21.727441 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8099 12:42:21.730516 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8100 12:42:21.733707 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8101 12:42:21.738087 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8102 12:42:21.739926 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8103 12:42:21.746671 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8104 12:42:21.749974 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8105 12:42:21.753744 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8106 12:42:21.757162 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8107 12:42:21.759758 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8108 12:42:21.767595 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8109 12:42:21.770503 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8110 12:42:21.773114 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8111 12:42:21.776560 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8112 12:42:21.783026 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8113 12:42:21.786257 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8114 12:42:21.786788 ==
8115 12:42:21.789479 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:42:21.792922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:42:21.793451 ==
8118 12:42:21.796072 DQS Delay:
8119 12:42:21.796602 DQS0 = 0, DQS1 = 0
8120 12:42:21.796950 DQM Delay:
8121 12:42:21.799118 DQM0 = 132, DQM1 = 124
8122 12:42:21.799581 DQ Delay:
8123 12:42:21.803412 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8124 12:42:21.805877 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8125 12:42:21.812326 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8126 12:42:21.816294 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8127 12:42:21.816821
8128 12:42:21.817161
8129 12:42:21.817476 ==
8130 12:42:21.819355 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:42:21.822126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:42:21.822569 ==
8133 12:42:21.822906
8134 12:42:21.823220
8135 12:42:21.825937 TX Vref Scan disable
8136 12:42:21.828774 == TX Byte 0 ==
8137 12:42:21.831991 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8138 12:42:21.835338 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8139 12:42:21.839887 == TX Byte 1 ==
8140 12:42:21.842781 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8141 12:42:21.845540 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8142 12:42:21.846112 ==
8143 12:42:21.849109 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 12:42:21.852092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 12:42:21.855739 ==
8146 12:42:21.867899
8147 12:42:21.870543 TX Vref early break, caculate TX vref
8148 12:42:21.874336 TX Vref=16, minBit 2, minWin=23, winSum=385
8149 12:42:21.877590 TX Vref=18, minBit 6, minWin=23, winSum=390
8150 12:42:21.880750 TX Vref=20, minBit 4, minWin=24, winSum=398
8151 12:42:21.884127 TX Vref=22, minBit 1, minWin=25, winSum=408
8152 12:42:21.887905 TX Vref=24, minBit 1, minWin=25, winSum=415
8153 12:42:21.894117 TX Vref=26, minBit 1, minWin=25, winSum=421
8154 12:42:21.897018 TX Vref=28, minBit 4, minWin=25, winSum=422
8155 12:42:21.900668 TX Vref=30, minBit 2, minWin=25, winSum=416
8156 12:42:21.903618 TX Vref=32, minBit 1, minWin=25, winSum=407
8157 12:42:21.907193 TX Vref=34, minBit 0, minWin=24, winSum=399
8158 12:42:21.913336 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8159 12:42:21.913913
8160 12:42:21.917474 Final TX Range 0 Vref 28
8161 12:42:21.918062
8162 12:42:21.918560 ==
8163 12:42:21.920097 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 12:42:21.923039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 12:42:21.923574 ==
8166 12:42:21.924062
8167 12:42:21.924558
8168 12:42:21.926361 TX Vref Scan disable
8169 12:42:21.933106 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8170 12:42:21.933652 == TX Byte 0 ==
8171 12:42:21.936413 u2DelayCellOfst[0]=10 cells (3 PI)
8172 12:42:21.939788 u2DelayCellOfst[1]=14 cells (4 PI)
8173 12:42:21.943091 u2DelayCellOfst[2]=7 cells (2 PI)
8174 12:42:21.946254 u2DelayCellOfst[3]=7 cells (2 PI)
8175 12:42:21.949579 u2DelayCellOfst[4]=7 cells (2 PI)
8176 12:42:21.953114 u2DelayCellOfst[5]=0 cells (0 PI)
8177 12:42:21.955792 u2DelayCellOfst[6]=14 cells (4 PI)
8178 12:42:21.959791 u2DelayCellOfst[7]=14 cells (4 PI)
8179 12:42:21.962923 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8180 12:42:21.966746 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8181 12:42:21.969508 == TX Byte 1 ==
8182 12:42:21.972701 u2DelayCellOfst[8]=0 cells (0 PI)
8183 12:42:21.976027 u2DelayCellOfst[9]=0 cells (0 PI)
8184 12:42:21.979410 u2DelayCellOfst[10]=7 cells (2 PI)
8185 12:42:21.980030 u2DelayCellOfst[11]=0 cells (0 PI)
8186 12:42:21.982398 u2DelayCellOfst[12]=10 cells (3 PI)
8187 12:42:21.986247 u2DelayCellOfst[13]=10 cells (3 PI)
8188 12:42:21.989536 u2DelayCellOfst[14]=17 cells (5 PI)
8189 12:42:21.992518 u2DelayCellOfst[15]=10 cells (3 PI)
8190 12:42:21.999079 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8191 12:42:22.002268 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8192 12:42:22.002758 DramC Write-DBI on
8193 12:42:22.003240 ==
8194 12:42:22.006127 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:42:22.012001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:42:22.012490 ==
8197 12:42:22.012982
8198 12:42:22.013442
8199 12:42:22.015726 TX Vref Scan disable
8200 12:42:22.016308 == TX Byte 0 ==
8201 12:42:22.021864 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8202 12:42:22.022437 == TX Byte 1 ==
8203 12:42:22.025444 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8204 12:42:22.029130 DramC Write-DBI off
8205 12:42:22.029707
8206 12:42:22.030201 [DATLAT]
8207 12:42:22.032457 Freq=1600, CH0 RK1
8208 12:42:22.032945
8209 12:42:22.033438 DATLAT Default: 0xf
8210 12:42:22.035451 0, 0xFFFF, sum = 0
8211 12:42:22.036045 1, 0xFFFF, sum = 0
8212 12:42:22.038804 2, 0xFFFF, sum = 0
8213 12:42:22.039430 3, 0xFFFF, sum = 0
8214 12:42:22.041772 4, 0xFFFF, sum = 0
8215 12:42:22.042263 5, 0xFFFF, sum = 0
8216 12:42:22.045621 6, 0xFFFF, sum = 0
8217 12:42:22.048336 7, 0xFFFF, sum = 0
8218 12:42:22.048829 8, 0xFFFF, sum = 0
8219 12:42:22.051781 9, 0xFFFF, sum = 0
8220 12:42:22.052262 10, 0xFFFF, sum = 0
8221 12:42:22.055798 11, 0xFFFF, sum = 0
8222 12:42:22.056330 12, 0xFFFF, sum = 0
8223 12:42:22.058266 13, 0xFFFF, sum = 0
8224 12:42:22.058798 14, 0x0, sum = 1
8225 12:42:22.061847 15, 0x0, sum = 2
8226 12:42:22.062375 16, 0x0, sum = 3
8227 12:42:22.064989 17, 0x0, sum = 4
8228 12:42:22.065564 best_step = 15
8229 12:42:22.065916
8230 12:42:22.066239 ==
8231 12:42:22.067976 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 12:42:22.071253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 12:42:22.074827 ==
8234 12:42:22.075350 RX Vref Scan: 0
8235 12:42:22.075771
8236 12:42:22.078459 RX Vref 0 -> 0, step: 1
8237 12:42:22.078982
8238 12:42:22.081899 RX Delay 11 -> 252, step: 4
8239 12:42:22.084376 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8240 12:42:22.087902 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8241 12:42:22.091254 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8242 12:42:22.097613 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8243 12:42:22.100899 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8244 12:42:22.103939 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8245 12:42:22.108056 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8246 12:42:22.111306 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8247 12:42:22.117961 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8248 12:42:22.120541 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8249 12:42:22.124147 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8250 12:42:22.127792 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8251 12:42:22.133725 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8252 12:42:22.137154 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8253 12:42:22.141271 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8254 12:42:22.143663 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8255 12:42:22.144187 ==
8256 12:42:22.146738 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 12:42:22.153321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 12:42:22.153852 ==
8259 12:42:22.154197 DQS Delay:
8260 12:42:22.156581 DQS0 = 0, DQS1 = 0
8261 12:42:22.157105 DQM Delay:
8262 12:42:22.157448 DQM0 = 129, DQM1 = 124
8263 12:42:22.160180 DQ Delay:
8264 12:42:22.163502 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
8265 12:42:22.166442 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8266 12:42:22.169990 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8267 12:42:22.173037 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =130
8268 12:42:22.173471
8269 12:42:22.173811
8270 12:42:22.174124
8271 12:42:22.178460 [DramC_TX_OE_Calibration] TA2
8272 12:42:22.180186 Original DQ_B0 (3 6) =30, OEN = 27
8273 12:42:22.183148 Original DQ_B1 (3 6) =30, OEN = 27
8274 12:42:22.186615 24, 0x0, End_B0=24 End_B1=24
8275 12:42:22.187162 25, 0x0, End_B0=25 End_B1=25
8276 12:42:22.189879 26, 0x0, End_B0=26 End_B1=26
8277 12:42:22.192959 27, 0x0, End_B0=27 End_B1=27
8278 12:42:22.196785 28, 0x0, End_B0=28 End_B1=28
8279 12:42:22.199779 29, 0x0, End_B0=29 End_B1=29
8280 12:42:22.200220 30, 0x0, End_B0=30 End_B1=30
8281 12:42:22.202805 31, 0x4141, End_B0=30 End_B1=30
8282 12:42:22.206152 Byte0 end_step=30 best_step=27
8283 12:42:22.209457 Byte1 end_step=30 best_step=27
8284 12:42:22.212889 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 12:42:22.215889 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 12:42:22.216420
8287 12:42:22.216759
8288 12:42:22.222987 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
8289 12:42:22.226223 CH0 RK1: MR19=303, MR18=1411
8290 12:42:22.232567 CH0_RK1: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
8291 12:42:22.235738 [RxdqsGatingPostProcess] freq 1600
8292 12:42:22.243021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 12:42:22.243615 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 12:42:22.246169 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 12:42:22.248951 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 12:42:22.252838 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 12:42:22.255588 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 12:42:22.258744 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 12:42:22.262478 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 12:42:22.265663 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 12:42:22.268587 Pre-setting of DQS Precalculation
8302 12:42:22.272291 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 12:42:22.272827 ==
8304 12:42:22.275282 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 12:42:22.281965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 12:42:22.282500 ==
8307 12:42:22.285865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 12:42:22.292068 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 12:42:22.295263 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 12:42:22.301534 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 12:42:22.309370 [CA 0] Center 42 (13~72) winsize 60
8312 12:42:22.313440 [CA 1] Center 42 (13~72) winsize 60
8313 12:42:22.317032 [CA 2] Center 38 (9~68) winsize 60
8314 12:42:22.319555 [CA 3] Center 37 (8~67) winsize 60
8315 12:42:22.322784 [CA 4] Center 38 (8~69) winsize 62
8316 12:42:22.326357 [CA 5] Center 37 (7~67) winsize 61
8317 12:42:22.326925
8318 12:42:22.329583 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 12:42:22.330150
8320 12:42:22.336427 [CATrainingPosCal] consider 1 rank data
8321 12:42:22.336994 u2DelayCellTimex100 = 275/100 ps
8322 12:42:22.342295 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8323 12:42:22.346426 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8324 12:42:22.348933 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8325 12:42:22.352464 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8326 12:42:22.355260 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8327 12:42:22.358506 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8328 12:42:22.358933
8329 12:42:22.362853 CA PerBit enable=1, Macro0, CA PI delay=37
8330 12:42:22.363422
8331 12:42:22.365503 [CBTSetCACLKResult] CA Dly = 37
8332 12:42:22.368961 CS Dly: 8 (0~39)
8333 12:42:22.372094 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 12:42:22.375270 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 12:42:22.375898 ==
8336 12:42:22.378980 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 12:42:22.385079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 12:42:22.385653 ==
8339 12:42:22.388670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 12:42:22.395323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 12:42:22.398454 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 12:42:22.404885 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 12:42:22.413388 [CA 0] Center 42 (12~72) winsize 61
8344 12:42:22.415993 [CA 1] Center 43 (14~72) winsize 59
8345 12:42:22.419973 [CA 2] Center 38 (9~68) winsize 60
8346 12:42:22.422295 [CA 3] Center 37 (8~66) winsize 59
8347 12:42:22.425894 [CA 4] Center 38 (8~68) winsize 61
8348 12:42:22.429506 [CA 5] Center 37 (7~67) winsize 61
8349 12:42:22.430110
8350 12:42:22.432619 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8351 12:42:22.433090
8352 12:42:22.439504 [CATrainingPosCal] consider 2 rank data
8353 12:42:22.440053 u2DelayCellTimex100 = 275/100 ps
8354 12:42:22.445869 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8355 12:42:22.449111 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8356 12:42:22.452007 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8357 12:42:22.455824 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8358 12:42:22.458721 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8359 12:42:22.462554 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8360 12:42:22.462978
8361 12:42:22.465187 CA PerBit enable=1, Macro0, CA PI delay=37
8362 12:42:22.465614
8363 12:42:22.468548 [CBTSetCACLKResult] CA Dly = 37
8364 12:42:22.471783 CS Dly: 9 (0~42)
8365 12:42:22.475357 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 12:42:22.478389 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 12:42:22.478810
8368 12:42:22.482153 ----->DramcWriteLeveling(PI) begin...
8369 12:42:22.482582 ==
8370 12:42:22.485402 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 12:42:22.491806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 12:42:22.492272 ==
8373 12:42:22.495729 Write leveling (Byte 0): 23 => 23
8374 12:42:22.496150 Write leveling (Byte 1): 28 => 28
8375 12:42:22.499089 DramcWriteLeveling(PI) end<-----
8376 12:42:22.499560
8377 12:42:22.501765 ==
8378 12:42:22.505901 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 12:42:22.508442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 12:42:22.508868 ==
8381 12:42:22.512138 [Gating] SW mode calibration
8382 12:42:22.518384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 12:42:22.521867 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 12:42:22.528392 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:42:22.531899 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:42:22.534814 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:42:22.542170 1 4 12 | B1->B0 | 2423 3232 | 1 1 | (0 0) (1 1)
8388 12:42:22.544658 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8389 12:42:22.548400 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 12:42:22.554245 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 12:42:22.558494 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 12:42:22.561096 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 12:42:22.568348 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 12:42:22.571719 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8395 12:42:22.574753 1 5 12 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (1 0)
8396 12:42:22.581351 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8397 12:42:22.584057 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 12:42:22.587676 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 12:42:22.594678 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 12:42:22.597353 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 12:42:22.600839 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 12:42:22.607891 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8403 12:42:22.610263 1 6 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8404 12:42:22.613782 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 12:42:22.620625 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 12:42:22.623516 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 12:42:22.627164 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 12:42:22.633664 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 12:42:22.636746 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 12:42:22.640679 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 12:42:22.647011 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 12:42:22.650347 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 12:42:22.653263 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:42:22.660154 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:42:22.663029 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:42:22.666746 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:42:22.673142 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:42:22.676749 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:42:22.679481 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:42:22.685999 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 12:42:22.689980 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 12:42:22.692740 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 12:42:22.699333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 12:42:22.702732 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 12:42:22.706109 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 12:42:22.712896 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8427 12:42:22.715985 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 12:42:22.719482 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8429 12:42:22.723090 Total UI for P1: 0, mck2ui 16
8430 12:42:22.725521 best dqsien dly found for B0: ( 1, 9, 10)
8431 12:42:22.732883 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 12:42:22.736364 Total UI for P1: 0, mck2ui 16
8433 12:42:22.739159 best dqsien dly found for B1: ( 1, 9, 14)
8434 12:42:22.742581 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8435 12:42:22.745697 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8436 12:42:22.746265
8437 12:42:22.748811 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 12:42:22.751841 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8439 12:42:22.755569 [Gating] SW calibration Done
8440 12:42:22.756041 ==
8441 12:42:22.758674 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 12:42:22.762111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 12:42:22.765661 ==
8444 12:42:22.766235 RX Vref Scan: 0
8445 12:42:22.766610
8446 12:42:22.768305 RX Vref 0 -> 0, step: 1
8447 12:42:22.768775
8448 12:42:22.769146 RX Delay 0 -> 252, step: 8
8449 12:42:22.775420 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8450 12:42:22.778920 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8451 12:42:22.782014 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8452 12:42:22.785635 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8453 12:42:22.788906 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8454 12:42:22.795090 iDelay=208, Bit 5, Center 143 (88 ~ 199) 112
8455 12:42:22.798556 iDelay=208, Bit 6, Center 151 (96 ~ 207) 112
8456 12:42:22.801441 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8457 12:42:22.804625 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8458 12:42:22.811273 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8459 12:42:22.814565 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8460 12:42:22.818484 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8461 12:42:22.821100 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8462 12:42:22.824310 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8463 12:42:22.830710 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8464 12:42:22.834198 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8465 12:42:22.834769 ==
8466 12:42:22.837384 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 12:42:22.840970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 12:42:22.841541 ==
8469 12:42:22.844481 DQS Delay:
8470 12:42:22.845103 DQS0 = 0, DQS1 = 0
8471 12:42:22.847389 DQM Delay:
8472 12:42:22.847862 DQM0 = 136, DQM1 = 131
8473 12:42:22.848229 DQ Delay:
8474 12:42:22.853850 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8475 12:42:22.857868 DQ4 =131, DQ5 =143, DQ6 =151, DQ7 =131
8476 12:42:22.861228 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8477 12:42:22.864087 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =135
8478 12:42:22.864558
8479 12:42:22.865018
8480 12:42:22.865546 ==
8481 12:42:22.867113 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 12:42:22.870408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 12:42:22.870881 ==
8484 12:42:22.871253
8485 12:42:22.871666
8486 12:42:22.874230 TX Vref Scan disable
8487 12:42:22.877175 == TX Byte 0 ==
8488 12:42:22.880951 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8489 12:42:22.884267 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8490 12:42:22.887335 == TX Byte 1 ==
8491 12:42:22.890295 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8492 12:42:22.893344 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8493 12:42:22.893831 ==
8494 12:42:22.897026 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 12:42:22.903997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 12:42:22.904578 ==
8497 12:42:22.915537
8498 12:42:22.919168 TX Vref early break, caculate TX vref
8499 12:42:22.922083 TX Vref=16, minBit 8, minWin=21, winSum=368
8500 12:42:22.925413 TX Vref=18, minBit 3, minWin=23, winSum=381
8501 12:42:22.928103 TX Vref=20, minBit 8, minWin=23, winSum=386
8502 12:42:22.931561 TX Vref=22, minBit 8, minWin=23, winSum=400
8503 12:42:22.935009 TX Vref=24, minBit 8, minWin=24, winSum=404
8504 12:42:22.941668 TX Vref=26, minBit 8, minWin=25, winSum=419
8505 12:42:22.944955 TX Vref=28, minBit 0, minWin=25, winSum=419
8506 12:42:22.948203 TX Vref=30, minBit 9, minWin=24, winSum=414
8507 12:42:22.951298 TX Vref=32, minBit 9, minWin=24, winSum=408
8508 12:42:22.955004 TX Vref=34, minBit 9, minWin=23, winSum=393
8509 12:42:22.961002 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 26
8510 12:42:22.961575
8511 12:42:22.964418 Final TX Range 0 Vref 26
8512 12:42:22.964886
8513 12:42:22.965251 ==
8514 12:42:22.967484 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 12:42:22.971034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 12:42:22.971495 ==
8517 12:42:22.971836
8518 12:42:22.972148
8519 12:42:22.974165 TX Vref Scan disable
8520 12:42:22.981254 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8521 12:42:22.981780 == TX Byte 0 ==
8522 12:42:22.984185 u2DelayCellOfst[0]=17 cells (5 PI)
8523 12:42:22.987779 u2DelayCellOfst[1]=10 cells (3 PI)
8524 12:42:22.990962 u2DelayCellOfst[2]=0 cells (0 PI)
8525 12:42:22.994495 u2DelayCellOfst[3]=7 cells (2 PI)
8526 12:42:22.997585 u2DelayCellOfst[4]=7 cells (2 PI)
8527 12:42:23.001137 u2DelayCellOfst[5]=17 cells (5 PI)
8528 12:42:23.004372 u2DelayCellOfst[6]=17 cells (5 PI)
8529 12:42:23.007461 u2DelayCellOfst[7]=7 cells (2 PI)
8530 12:42:23.010852 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8531 12:42:23.014638 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8532 12:42:23.017685 == TX Byte 1 ==
8533 12:42:23.020939 u2DelayCellOfst[8]=0 cells (0 PI)
8534 12:42:23.024285 u2DelayCellOfst[9]=7 cells (2 PI)
8535 12:42:23.024845 u2DelayCellOfst[10]=14 cells (4 PI)
8536 12:42:23.027528 u2DelayCellOfst[11]=7 cells (2 PI)
8537 12:42:23.031012 u2DelayCellOfst[12]=14 cells (4 PI)
8538 12:42:23.033996 u2DelayCellOfst[13]=17 cells (5 PI)
8539 12:42:23.037603 u2DelayCellOfst[14]=17 cells (5 PI)
8540 12:42:23.040663 u2DelayCellOfst[15]=17 cells (5 PI)
8541 12:42:23.047198 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8542 12:42:23.050308 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8543 12:42:23.050774 DramC Write-DBI on
8544 12:42:23.051142 ==
8545 12:42:23.053869 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 12:42:23.060860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 12:42:23.061432 ==
8548 12:42:23.061804
8549 12:42:23.062145
8550 12:42:23.062470 TX Vref Scan disable
8551 12:42:23.064703 == TX Byte 0 ==
8552 12:42:23.067678 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8553 12:42:23.071054 == TX Byte 1 ==
8554 12:42:23.074498 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8555 12:42:23.077762 DramC Write-DBI off
8556 12:42:23.078293
8557 12:42:23.078633 [DATLAT]
8558 12:42:23.078944 Freq=1600, CH1 RK0
8559 12:42:23.079244
8560 12:42:23.080830 DATLAT Default: 0xf
8561 12:42:23.084035 0, 0xFFFF, sum = 0
8562 12:42:23.084496 1, 0xFFFF, sum = 0
8563 12:42:23.088009 2, 0xFFFF, sum = 0
8564 12:42:23.088435 3, 0xFFFF, sum = 0
8565 12:42:23.090909 4, 0xFFFF, sum = 0
8566 12:42:23.091337 5, 0xFFFF, sum = 0
8567 12:42:23.094641 6, 0xFFFF, sum = 0
8568 12:42:23.095067 7, 0xFFFF, sum = 0
8569 12:42:23.097430 8, 0xFFFF, sum = 0
8570 12:42:23.097856 9, 0xFFFF, sum = 0
8571 12:42:23.100764 10, 0xFFFF, sum = 0
8572 12:42:23.101192 11, 0xFFFF, sum = 0
8573 12:42:23.104024 12, 0xFFFF, sum = 0
8574 12:42:23.104466 13, 0xFFFF, sum = 0
8575 12:42:23.107331 14, 0x0, sum = 1
8576 12:42:23.107802 15, 0x0, sum = 2
8577 12:42:23.110724 16, 0x0, sum = 3
8578 12:42:23.111154 17, 0x0, sum = 4
8579 12:42:23.114393 best_step = 15
8580 12:42:23.114914
8581 12:42:23.115250 ==
8582 12:42:23.116991 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 12:42:23.120897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 12:42:23.121422 ==
8585 12:42:23.123749 RX Vref Scan: 1
8586 12:42:23.124269
8587 12:42:23.124606 Set Vref Range= 24 -> 127
8588 12:42:23.124919
8589 12:42:23.126791 RX Vref 24 -> 127, step: 1
8590 12:42:23.127213
8591 12:42:23.130264 RX Delay 19 -> 252, step: 4
8592 12:42:23.130683
8593 12:42:23.133778 Set Vref, RX VrefLevel [Byte0]: 24
8594 12:42:23.137370 [Byte1]: 24
8595 12:42:23.137894
8596 12:42:23.140061 Set Vref, RX VrefLevel [Byte0]: 25
8597 12:42:23.144000 [Byte1]: 25
8598 12:42:23.147663
8599 12:42:23.148182 Set Vref, RX VrefLevel [Byte0]: 26
8600 12:42:23.150634 [Byte1]: 26
8601 12:42:23.155110
8602 12:42:23.155753 Set Vref, RX VrefLevel [Byte0]: 27
8603 12:42:23.158982 [Byte1]: 27
8604 12:42:23.162292
8605 12:42:23.162818 Set Vref, RX VrefLevel [Byte0]: 28
8606 12:42:23.165512 [Byte1]: 28
8607 12:42:23.169964
8608 12:42:23.170487 Set Vref, RX VrefLevel [Byte0]: 29
8609 12:42:23.173207 [Byte1]: 29
8610 12:42:23.177097
8611 12:42:23.177521 Set Vref, RX VrefLevel [Byte0]: 30
8612 12:42:23.180775 [Byte1]: 30
8613 12:42:23.184781
8614 12:42:23.185200 Set Vref, RX VrefLevel [Byte0]: 31
8615 12:42:23.188652 [Byte1]: 31
8616 12:42:23.192744
8617 12:42:23.193229 Set Vref, RX VrefLevel [Byte0]: 32
8618 12:42:23.195927 [Byte1]: 32
8619 12:42:23.200180
8620 12:42:23.200722 Set Vref, RX VrefLevel [Byte0]: 33
8621 12:42:23.203396 [Byte1]: 33
8622 12:42:23.207771
8623 12:42:23.208191 Set Vref, RX VrefLevel [Byte0]: 34
8624 12:42:23.210735 [Byte1]: 34
8625 12:42:23.215242
8626 12:42:23.215806 Set Vref, RX VrefLevel [Byte0]: 35
8627 12:42:23.218418 [Byte1]: 35
8628 12:42:23.223219
8629 12:42:23.223827 Set Vref, RX VrefLevel [Byte0]: 36
8630 12:42:23.226608 [Byte1]: 36
8631 12:42:23.230496
8632 12:42:23.231058 Set Vref, RX VrefLevel [Byte0]: 37
8633 12:42:23.234405 [Byte1]: 37
8634 12:42:23.238279
8635 12:42:23.238845 Set Vref, RX VrefLevel [Byte0]: 38
8636 12:42:23.241397 [Byte1]: 38
8637 12:42:23.245924
8638 12:42:23.246486 Set Vref, RX VrefLevel [Byte0]: 39
8639 12:42:23.249776 [Byte1]: 39
8640 12:42:23.253358
8641 12:42:23.253823 Set Vref, RX VrefLevel [Byte0]: 40
8642 12:42:23.256418 [Byte1]: 40
8643 12:42:23.261690
8644 12:42:23.262109 Set Vref, RX VrefLevel [Byte0]: 41
8645 12:42:23.264700 [Byte1]: 41
8646 12:42:23.268432
8647 12:42:23.268852 Set Vref, RX VrefLevel [Byte0]: 42
8648 12:42:23.271702 [Byte1]: 42
8649 12:42:23.275731
8650 12:42:23.276151 Set Vref, RX VrefLevel [Byte0]: 43
8651 12:42:23.279347 [Byte1]: 43
8652 12:42:23.283588
8653 12:42:23.284106 Set Vref, RX VrefLevel [Byte0]: 44
8654 12:42:23.286665 [Byte1]: 44
8655 12:42:23.291229
8656 12:42:23.291806 Set Vref, RX VrefLevel [Byte0]: 45
8657 12:42:23.294326 [Byte1]: 45
8658 12:42:23.298790
8659 12:42:23.299313 Set Vref, RX VrefLevel [Byte0]: 46
8660 12:42:23.302071 [Byte1]: 46
8661 12:42:23.306409
8662 12:42:23.306924 Set Vref, RX VrefLevel [Byte0]: 47
8663 12:42:23.309345 [Byte1]: 47
8664 12:42:23.314164
8665 12:42:23.314683 Set Vref, RX VrefLevel [Byte0]: 48
8666 12:42:23.317215 [Byte1]: 48
8667 12:42:23.321649
8668 12:42:23.322175 Set Vref, RX VrefLevel [Byte0]: 49
8669 12:42:23.324689 [Byte1]: 49
8670 12:42:23.328744
8671 12:42:23.329261 Set Vref, RX VrefLevel [Byte0]: 50
8672 12:42:23.332102 [Byte1]: 50
8673 12:42:23.336725
8674 12:42:23.337289 Set Vref, RX VrefLevel [Byte0]: 51
8675 12:42:23.339828 [Byte1]: 51
8676 12:42:23.344469
8677 12:42:23.345034 Set Vref, RX VrefLevel [Byte0]: 52
8678 12:42:23.347675 [Byte1]: 52
8679 12:42:23.351911
8680 12:42:23.352479 Set Vref, RX VrefLevel [Byte0]: 53
8681 12:42:23.354602 [Byte1]: 53
8682 12:42:23.359601
8683 12:42:23.360160 Set Vref, RX VrefLevel [Byte0]: 54
8684 12:42:23.362709 [Byte1]: 54
8685 12:42:23.366831
8686 12:42:23.367441 Set Vref, RX VrefLevel [Byte0]: 55
8687 12:42:23.369989 [Byte1]: 55
8688 12:42:23.374558
8689 12:42:23.375126 Set Vref, RX VrefLevel [Byte0]: 56
8690 12:42:23.377714 [Byte1]: 56
8691 12:42:23.382372
8692 12:42:23.382835 Set Vref, RX VrefLevel [Byte0]: 57
8693 12:42:23.385036 [Byte1]: 57
8694 12:42:23.389683
8695 12:42:23.390249 Set Vref, RX VrefLevel [Byte0]: 58
8696 12:42:23.393089 [Byte1]: 58
8697 12:42:23.397117
8698 12:42:23.397679 Set Vref, RX VrefLevel [Byte0]: 59
8699 12:42:23.400679 [Byte1]: 59
8700 12:42:23.404814
8701 12:42:23.405379 Set Vref, RX VrefLevel [Byte0]: 60
8702 12:42:23.408233 [Byte1]: 60
8703 12:42:23.412312
8704 12:42:23.412779 Set Vref, RX VrefLevel [Byte0]: 61
8705 12:42:23.415745 [Byte1]: 61
8706 12:42:23.420688
8707 12:42:23.421304 Set Vref, RX VrefLevel [Byte0]: 62
8708 12:42:23.422672 [Byte1]: 62
8709 12:42:23.427705
8710 12:42:23.428170 Set Vref, RX VrefLevel [Byte0]: 63
8711 12:42:23.430753 [Byte1]: 63
8712 12:42:23.435217
8713 12:42:23.435868 Set Vref, RX VrefLevel [Byte0]: 64
8714 12:42:23.438388 [Byte1]: 64
8715 12:42:23.442467
8716 12:42:23.443026 Set Vref, RX VrefLevel [Byte0]: 65
8717 12:42:23.445825 [Byte1]: 65
8718 12:42:23.450235
8719 12:42:23.450800 Set Vref, RX VrefLevel [Byte0]: 66
8720 12:42:23.453442 [Byte1]: 66
8721 12:42:23.457631
8722 12:42:23.458098 Set Vref, RX VrefLevel [Byte0]: 67
8723 12:42:23.461252 [Byte1]: 67
8724 12:42:23.465406
8725 12:42:23.465970 Set Vref, RX VrefLevel [Byte0]: 68
8726 12:42:23.468625 [Byte1]: 68
8727 12:42:23.473067
8728 12:42:23.473637 Set Vref, RX VrefLevel [Byte0]: 69
8729 12:42:23.475745 [Byte1]: 69
8730 12:42:23.481139
8731 12:42:23.481702 Final RX Vref Byte 0 = 54 to rank0
8732 12:42:23.483395 Final RX Vref Byte 1 = 60 to rank0
8733 12:42:23.486973 Final RX Vref Byte 0 = 54 to rank1
8734 12:42:23.490347 Final RX Vref Byte 1 = 60 to rank1==
8735 12:42:23.493731 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 12:42:23.499939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 12:42:23.500515 ==
8738 12:42:23.500891 DQS Delay:
8739 12:42:23.502986 DQS0 = 0, DQS1 = 0
8740 12:42:23.503521 DQM Delay:
8741 12:42:23.506668 DQM0 = 133, DQM1 = 130
8742 12:42:23.507235 DQ Delay:
8743 12:42:23.509581 DQ0 =142, DQ1 =130, DQ2 =120, DQ3 =132
8744 12:42:23.513793 DQ4 =126, DQ5 =142, DQ6 =146, DQ7 =126
8745 12:42:23.516457 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8746 12:42:23.519721 DQ12 =138, DQ13 =140, DQ14 =136, DQ15 =140
8747 12:42:23.520292
8748 12:42:23.520668
8749 12:42:23.521007
8750 12:42:23.522802 [DramC_TX_OE_Calibration] TA2
8751 12:42:23.526553 Original DQ_B0 (3 6) =30, OEN = 27
8752 12:42:23.529884 Original DQ_B1 (3 6) =30, OEN = 27
8753 12:42:23.533262 24, 0x0, End_B0=24 End_B1=24
8754 12:42:23.535966 25, 0x0, End_B0=25 End_B1=25
8755 12:42:23.536399 26, 0x0, End_B0=26 End_B1=26
8756 12:42:23.539327 27, 0x0, End_B0=27 End_B1=27
8757 12:42:23.542572 28, 0x0, End_B0=28 End_B1=28
8758 12:42:23.546210 29, 0x0, End_B0=29 End_B1=29
8759 12:42:23.546757 30, 0x0, End_B0=30 End_B1=30
8760 12:42:23.549455 31, 0x5151, End_B0=30 End_B1=30
8761 12:42:23.552595 Byte0 end_step=30 best_step=27
8762 12:42:23.555732 Byte1 end_step=30 best_step=27
8763 12:42:23.559324 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 12:42:23.562511 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 12:42:23.562939
8766 12:42:23.563275
8767 12:42:23.569164 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8768 12:42:23.572183 CH1 RK0: MR19=303, MR18=D17
8769 12:42:23.578965 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8770 12:42:23.579502
8771 12:42:23.582213 ----->DramcWriteLeveling(PI) begin...
8772 12:42:23.582647 ==
8773 12:42:23.585957 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 12:42:23.589282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 12:42:23.589826 ==
8776 12:42:23.592078 Write leveling (Byte 0): 25 => 25
8777 12:42:23.595279 Write leveling (Byte 1): 27 => 27
8778 12:42:23.599032 DramcWriteLeveling(PI) end<-----
8779 12:42:23.599491
8780 12:42:23.599835 ==
8781 12:42:23.601922 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 12:42:23.608315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 12:42:23.608748 ==
8784 12:42:23.609090 [Gating] SW mode calibration
8785 12:42:23.618622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 12:42:23.621958 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 12:42:23.628661 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 12:42:23.631617 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 12:42:23.634684 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8790 12:42:23.641669 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8791 12:42:23.645614 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:42:23.648373 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 12:42:23.651660 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 12:42:23.658267 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 12:42:23.661474 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 12:42:23.664235 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8797 12:42:23.671100 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
8798 12:42:23.675481 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8799 12:42:23.677624 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:42:23.684372 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:42:23.688038 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:42:23.694697 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 12:42:23.698108 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 12:42:23.700971 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 12:42:23.707507 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8806 12:42:23.710951 1 6 12 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
8807 12:42:23.714358 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:42:23.720676 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:42:23.724117 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 12:42:23.726985 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 12:42:23.733562 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 12:42:23.737257 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8813 12:42:23.740242 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8814 12:42:23.746827 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8815 12:42:23.750807 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:42:23.753482 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:42:23.759828 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:42:23.763077 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:42:23.766673 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:42:23.772975 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:42:23.776487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:42:23.779670 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:42:23.785904 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:42:23.789707 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:42:23.793273 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:42:23.799567 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:42:23.802994 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:42:23.806089 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8829 12:42:23.812826 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8830 12:42:23.816278 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8831 12:42:23.819435 Total UI for P1: 0, mck2ui 16
8832 12:42:23.822884 best dqsien dly found for B0: ( 1, 9, 6)
8833 12:42:23.826194 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 12:42:23.829761 Total UI for P1: 0, mck2ui 16
8835 12:42:23.833080 best dqsien dly found for B1: ( 1, 9, 12)
8836 12:42:23.836005 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8837 12:42:23.839030 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8838 12:42:23.839639
8839 12:42:23.842509 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8840 12:42:23.849421 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8841 12:42:23.849992 [Gating] SW calibration Done
8842 12:42:23.850371 ==
8843 12:42:23.852854 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 12:42:23.858629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 12:42:23.859186 ==
8846 12:42:23.859727 RX Vref Scan: 0
8847 12:42:23.860281
8848 12:42:23.862456 RX Vref 0 -> 0, step: 1
8849 12:42:23.863023
8850 12:42:23.865473 RX Delay 0 -> 252, step: 8
8851 12:42:23.868470 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8852 12:42:23.872310 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8853 12:42:23.875556 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8854 12:42:23.882022 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8855 12:42:23.885794 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8856 12:42:23.888372 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8857 12:42:23.892140 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8858 12:42:23.895511 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8859 12:42:23.901766 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8860 12:42:23.905325 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8861 12:42:23.909001 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8862 12:42:23.912220 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8863 12:42:23.914995 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8864 12:42:23.922070 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8865 12:42:23.925718 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8866 12:42:23.928066 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8867 12:42:23.928543 ==
8868 12:42:23.931924 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 12:42:23.938201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 12:42:23.938780 ==
8871 12:42:23.939161 DQS Delay:
8872 12:42:23.939553 DQS0 = 0, DQS1 = 0
8873 12:42:23.941338 DQM Delay:
8874 12:42:23.941810 DQM0 = 135, DQM1 = 130
8875 12:42:23.944146 DQ Delay:
8876 12:42:23.947951 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8877 12:42:23.951345 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8878 12:42:23.954970 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8879 12:42:23.957810 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8880 12:42:23.958285
8881 12:42:23.958679
8882 12:42:23.959302 ==
8883 12:42:23.961332 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 12:42:23.963984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 12:42:23.967316 ==
8886 12:42:23.967776
8887 12:42:23.968117
8888 12:42:23.968437 TX Vref Scan disable
8889 12:42:23.970758 == TX Byte 0 ==
8890 12:42:23.973920 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8891 12:42:23.977547 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8892 12:42:23.981368 == TX Byte 1 ==
8893 12:42:23.984095 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8894 12:42:23.990419 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8895 12:42:23.990956 ==
8896 12:42:23.993701 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 12:42:23.997872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 12:42:23.998412 ==
8899 12:42:24.012110
8900 12:42:24.014823 TX Vref early break, caculate TX vref
8901 12:42:24.018843 TX Vref=16, minBit 9, minWin=22, winSum=377
8902 12:42:24.021846 TX Vref=18, minBit 9, minWin=22, winSum=384
8903 12:42:24.024987 TX Vref=20, minBit 9, minWin=22, winSum=394
8904 12:42:24.028219 TX Vref=22, minBit 9, minWin=23, winSum=400
8905 12:42:24.031867 TX Vref=24, minBit 9, minWin=23, winSum=409
8906 12:42:24.038148 TX Vref=26, minBit 9, minWin=24, winSum=411
8907 12:42:24.041460 TX Vref=28, minBit 8, minWin=24, winSum=414
8908 12:42:24.044581 TX Vref=30, minBit 8, minWin=24, winSum=415
8909 12:42:24.047872 TX Vref=32, minBit 9, minWin=24, winSum=411
8910 12:42:24.051186 TX Vref=34, minBit 0, minWin=24, winSum=401
8911 12:42:24.057809 TX Vref=36, minBit 9, minWin=23, winSum=394
8912 12:42:24.060771 TX Vref=38, minBit 8, minWin=22, winSum=384
8913 12:42:24.068169 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 30
8914 12:42:24.068735
8915 12:42:24.069108 Final TX Range 0 Vref 30
8916 12:42:24.069456
8917 12:42:24.069784 ==
8918 12:42:24.071256 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 12:42:24.077389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 12:42:24.077956 ==
8921 12:42:24.078330
8922 12:42:24.078678
8923 12:42:24.079005 TX Vref Scan disable
8924 12:42:24.084423 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8925 12:42:24.084977 == TX Byte 0 ==
8926 12:42:24.088420 u2DelayCellOfst[0]=14 cells (4 PI)
8927 12:42:24.091428 u2DelayCellOfst[1]=10 cells (3 PI)
8928 12:42:24.095284 u2DelayCellOfst[2]=0 cells (0 PI)
8929 12:42:24.098267 u2DelayCellOfst[3]=7 cells (2 PI)
8930 12:42:24.100966 u2DelayCellOfst[4]=7 cells (2 PI)
8931 12:42:24.104466 u2DelayCellOfst[5]=17 cells (5 PI)
8932 12:42:24.107706 u2DelayCellOfst[6]=14 cells (4 PI)
8933 12:42:24.110945 u2DelayCellOfst[7]=7 cells (2 PI)
8934 12:42:24.114787 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8935 12:42:24.117449 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8936 12:42:24.121725 == TX Byte 1 ==
8937 12:42:24.125193 u2DelayCellOfst[8]=0 cells (0 PI)
8938 12:42:24.127287 u2DelayCellOfst[9]=3 cells (1 PI)
8939 12:42:24.130604 u2DelayCellOfst[10]=14 cells (4 PI)
8940 12:42:24.134528 u2DelayCellOfst[11]=7 cells (2 PI)
8941 12:42:24.137086 u2DelayCellOfst[12]=14 cells (4 PI)
8942 12:42:24.141135 u2DelayCellOfst[13]=14 cells (4 PI)
8943 12:42:24.143560 u2DelayCellOfst[14]=17 cells (5 PI)
8944 12:42:24.143992 u2DelayCellOfst[15]=17 cells (5 PI)
8945 12:42:24.150769 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8946 12:42:24.154173 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8947 12:42:24.157172 DramC Write-DBI on
8948 12:42:24.157628 ==
8949 12:42:24.160192 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 12:42:24.163823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 12:42:24.164413 ==
8952 12:42:24.164794
8953 12:42:24.165159
8954 12:42:24.167175 TX Vref Scan disable
8955 12:42:24.167654 == TX Byte 0 ==
8956 12:42:24.173582 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8957 12:42:24.174110 == TX Byte 1 ==
8958 12:42:24.176950 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8959 12:42:24.180119 DramC Write-DBI off
8960 12:42:24.180545
8961 12:42:24.180887 [DATLAT]
8962 12:42:24.183441 Freq=1600, CH1 RK1
8963 12:42:24.183874
8964 12:42:24.184215 DATLAT Default: 0xf
8965 12:42:24.186466 0, 0xFFFF, sum = 0
8966 12:42:24.190564 1, 0xFFFF, sum = 0
8967 12:42:24.191098 2, 0xFFFF, sum = 0
8968 12:42:24.193819 3, 0xFFFF, sum = 0
8969 12:42:24.194355 4, 0xFFFF, sum = 0
8970 12:42:24.196261 5, 0xFFFF, sum = 0
8971 12:42:24.196692 6, 0xFFFF, sum = 0
8972 12:42:24.199826 7, 0xFFFF, sum = 0
8973 12:42:24.200257 8, 0xFFFF, sum = 0
8974 12:42:24.203063 9, 0xFFFF, sum = 0
8975 12:42:24.203715 10, 0xFFFF, sum = 0
8976 12:42:24.206172 11, 0xFFFF, sum = 0
8977 12:42:24.206621 12, 0xFFFF, sum = 0
8978 12:42:24.210323 13, 0xFFFF, sum = 0
8979 12:42:24.210930 14, 0x0, sum = 1
8980 12:42:24.212743 15, 0x0, sum = 2
8981 12:42:24.213179 16, 0x0, sum = 3
8982 12:42:24.216399 17, 0x0, sum = 4
8983 12:42:24.216926 best_step = 15
8984 12:42:24.217265
8985 12:42:24.217579 ==
8986 12:42:24.219434 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 12:42:24.225967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 12:42:24.226681 ==
8989 12:42:24.227071 RX Vref Scan: 0
8990 12:42:24.227471
8991 12:42:24.229593 RX Vref 0 -> 0, step: 1
8992 12:42:24.230018
8993 12:42:24.232458 RX Delay 11 -> 252, step: 4
8994 12:42:24.235750 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8995 12:42:24.238826 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8996 12:42:24.245888 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8997 12:42:24.248864 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8998 12:42:24.252024 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8999 12:42:24.255872 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9000 12:42:24.259143 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
9001 12:42:24.265574 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9002 12:42:24.268937 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9003 12:42:24.272458 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9004 12:42:24.275401 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9005 12:42:24.279037 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9006 12:42:24.285569 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9007 12:42:24.288293 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9008 12:42:24.291586 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9009 12:42:24.295188 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9010 12:42:24.299101 ==
9011 12:42:24.301848 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 12:42:24.305076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 12:42:24.305552 ==
9014 12:42:24.305926 DQS Delay:
9015 12:42:24.308195 DQS0 = 0, DQS1 = 0
9016 12:42:24.308667 DQM Delay:
9017 12:42:24.311994 DQM0 = 132, DQM1 = 128
9018 12:42:24.312424 DQ Delay:
9019 12:42:24.315191 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
9020 12:42:24.317962 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =130
9021 12:42:24.321169 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9022 12:42:24.324636 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9023 12:42:24.325169
9024 12:42:24.325512
9025 12:42:24.325826
9026 12:42:24.327895 [DramC_TX_OE_Calibration] TA2
9027 12:42:24.331175 Original DQ_B0 (3 6) =30, OEN = 27
9028 12:42:24.334585 Original DQ_B1 (3 6) =30, OEN = 27
9029 12:42:24.338224 24, 0x0, End_B0=24 End_B1=24
9030 12:42:24.341062 25, 0x0, End_B0=25 End_B1=25
9031 12:42:24.341605 26, 0x0, End_B0=26 End_B1=26
9032 12:42:24.344596 27, 0x0, End_B0=27 End_B1=27
9033 12:42:24.347886 28, 0x0, End_B0=28 End_B1=28
9034 12:42:24.351357 29, 0x0, End_B0=29 End_B1=29
9035 12:42:24.354251 30, 0x0, End_B0=30 End_B1=30
9036 12:42:24.358213 31, 0x4141, End_B0=30 End_B1=30
9037 12:42:24.358752 Byte0 end_step=30 best_step=27
9038 12:42:24.361020 Byte1 end_step=30 best_step=27
9039 12:42:24.363869 Byte0 TX OE(2T, 0.5T) = (3, 3)
9040 12:42:24.367737 Byte1 TX OE(2T, 0.5T) = (3, 3)
9041 12:42:24.368287
9042 12:42:24.368742
9043 12:42:24.373560 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9044 12:42:24.377308 CH1 RK1: MR19=303, MR18=111F
9045 12:42:24.383522 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
9046 12:42:24.386804 [RxdqsGatingPostProcess] freq 1600
9047 12:42:24.393796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9048 12:42:24.396601 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 12:42:24.401168 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 12:42:24.403601 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 12:42:24.406854 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 12:42:24.407342 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 12:42:24.410158 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 12:42:24.413390 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 12:42:24.416730 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 12:42:24.420045 Pre-setting of DQS Precalculation
9057 12:42:24.426754 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9058 12:42:24.432823 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9059 12:42:24.440000 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9060 12:42:24.440595
9061 12:42:24.441094
9062 12:42:24.443158 [Calibration Summary] 3200 Mbps
9063 12:42:24.443804 CH 0, Rank 0
9064 12:42:24.446360 SW Impedance : PASS
9065 12:42:24.449597 DUTY Scan : NO K
9066 12:42:24.450193 ZQ Calibration : PASS
9067 12:42:24.452594 Jitter Meter : NO K
9068 12:42:24.455675 CBT Training : PASS
9069 12:42:24.456301 Write leveling : PASS
9070 12:42:24.459714 RX DQS gating : PASS
9071 12:42:24.462063 RX DQ/DQS(RDDQC) : PASS
9072 12:42:24.462541 TX DQ/DQS : PASS
9073 12:42:24.465370 RX DATLAT : PASS
9074 12:42:24.469235 RX DQ/DQS(Engine): PASS
9075 12:42:24.469807 TX OE : PASS
9076 12:42:24.472047 All Pass.
9077 12:42:24.472521
9078 12:42:24.472897 CH 0, Rank 1
9079 12:42:24.475397 SW Impedance : PASS
9080 12:42:24.475843 DUTY Scan : NO K
9081 12:42:24.479197 ZQ Calibration : PASS
9082 12:42:24.482121 Jitter Meter : NO K
9083 12:42:24.482665 CBT Training : PASS
9084 12:42:24.485385 Write leveling : PASS
9085 12:42:24.488663 RX DQS gating : PASS
9086 12:42:24.489187 RX DQ/DQS(RDDQC) : PASS
9087 12:42:24.491592 TX DQ/DQS : PASS
9088 12:42:24.495656 RX DATLAT : PASS
9089 12:42:24.496227 RX DQ/DQS(Engine): PASS
9090 12:42:24.498592 TX OE : PASS
9091 12:42:24.499160 All Pass.
9092 12:42:24.499591
9093 12:42:24.501838 CH 1, Rank 0
9094 12:42:24.502605 SW Impedance : PASS
9095 12:42:24.505478 DUTY Scan : NO K
9096 12:42:24.508474 ZQ Calibration : PASS
9097 12:42:24.508938 Jitter Meter : NO K
9098 12:42:24.511576 CBT Training : PASS
9099 12:42:24.515029 Write leveling : PASS
9100 12:42:24.515488 RX DQS gating : PASS
9101 12:42:24.518804 RX DQ/DQS(RDDQC) : PASS
9102 12:42:24.521671 TX DQ/DQS : PASS
9103 12:42:24.522194 RX DATLAT : PASS
9104 12:42:24.525139 RX DQ/DQS(Engine): PASS
9105 12:42:24.525665 TX OE : PASS
9106 12:42:24.528058 All Pass.
9107 12:42:24.528479
9108 12:42:24.528813 CH 1, Rank 1
9109 12:42:24.531475 SW Impedance : PASS
9110 12:42:24.535025 DUTY Scan : NO K
9111 12:42:24.535574 ZQ Calibration : PASS
9112 12:42:24.537939 Jitter Meter : NO K
9113 12:42:24.538459 CBT Training : PASS
9114 12:42:24.542033 Write leveling : PASS
9115 12:42:24.545613 RX DQS gating : PASS
9116 12:42:24.546136 RX DQ/DQS(RDDQC) : PASS
9117 12:42:24.548593 TX DQ/DQS : PASS
9118 12:42:24.551353 RX DATLAT : PASS
9119 12:42:24.551818 RX DQ/DQS(Engine): PASS
9120 12:42:24.554570 TX OE : PASS
9121 12:42:24.555108 All Pass.
9122 12:42:24.555497
9123 12:42:24.558106 DramC Write-DBI on
9124 12:42:24.561142 PER_BANK_REFRESH: Hybrid Mode
9125 12:42:24.561584 TX_TRACKING: ON
9126 12:42:24.571321 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9127 12:42:24.577468 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9128 12:42:24.587730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9129 12:42:24.590358 [FAST_K] Save calibration result to emmc
9130 12:42:24.594258 sync common calibartion params.
9131 12:42:24.594679 sync cbt_mode0:1, 1:1
9132 12:42:24.597092 dram_init: ddr_geometry: 2
9133 12:42:24.600195 dram_init: ddr_geometry: 2
9134 12:42:24.600617 dram_init: ddr_geometry: 2
9135 12:42:24.603824 0:dram_rank_size:100000000
9136 12:42:24.607318 1:dram_rank_size:100000000
9137 12:42:24.610857 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9138 12:42:24.613425 DFS_SHUFFLE_HW_MODE: ON
9139 12:42:24.617019 dramc_set_vcore_voltage set vcore to 725000
9140 12:42:24.620297 Read voltage for 1600, 0
9141 12:42:24.620791 Vio18 = 0
9142 12:42:24.623194 Vcore = 725000
9143 12:42:24.623710 Vdram = 0
9144 12:42:24.624050 Vddq = 0
9145 12:42:24.626876 Vmddr = 0
9146 12:42:24.627297 switch to 3200 Mbps bootup
9147 12:42:24.630229 [DramcRunTimeConfig]
9148 12:42:24.630750 PHYPLL
9149 12:42:24.633281 DPM_CONTROL_AFTERK: ON
9150 12:42:24.633705 PER_BANK_REFRESH: ON
9151 12:42:24.636771 REFRESH_OVERHEAD_REDUCTION: ON
9152 12:42:24.639745 CMD_PICG_NEW_MODE: OFF
9153 12:42:24.640355 XRTWTW_NEW_MODE: ON
9154 12:42:24.642763 XRTRTR_NEW_MODE: ON
9155 12:42:24.643180 TX_TRACKING: ON
9156 12:42:24.646728 RDSEL_TRACKING: OFF
9157 12:42:24.649623 DQS Precalculation for DVFS: ON
9158 12:42:24.650044 RX_TRACKING: OFF
9159 12:42:24.652992 HW_GATING DBG: ON
9160 12:42:24.653510 ZQCS_ENABLE_LP4: ON
9161 12:42:24.656269 RX_PICG_NEW_MODE: ON
9162 12:42:24.656769 TX_PICG_NEW_MODE: ON
9163 12:42:24.659340 ENABLE_RX_DCM_DPHY: ON
9164 12:42:24.662574 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9165 12:42:24.666457 DUMMY_READ_FOR_TRACKING: OFF
9166 12:42:24.669071 !!! SPM_CONTROL_AFTERK: OFF
9167 12:42:24.669533 !!! SPM could not control APHY
9168 12:42:24.672709 IMPEDANCE_TRACKING: ON
9169 12:42:24.673133 TEMP_SENSOR: ON
9170 12:42:24.675918 HW_SAVE_FOR_SR: OFF
9171 12:42:24.679213 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9172 12:42:24.682585 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9173 12:42:24.685674 Read ODT Tracking: ON
9174 12:42:24.686098 Refresh Rate DeBounce: ON
9175 12:42:24.689085 DFS_NO_QUEUE_FLUSH: ON
9176 12:42:24.692181 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9177 12:42:24.695559 ENABLE_DFS_RUNTIME_MRW: OFF
9178 12:42:24.695985 DDR_RESERVE_NEW_MODE: ON
9179 12:42:24.698795 MR_CBT_SWITCH_FREQ: ON
9180 12:42:24.702048 =========================
9181 12:42:24.720934 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9182 12:42:24.724002 dram_init: ddr_geometry: 2
9183 12:42:24.742388 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9184 12:42:24.744944 dram_init: dram init end (result: 0)
9185 12:42:24.751687 DRAM-K: Full calibration passed in 24422 msecs
9186 12:42:24.755463 MRC: failed to locate region type 0.
9187 12:42:24.756033 DRAM rank0 size:0x100000000,
9188 12:42:24.758670 DRAM rank1 size=0x100000000
9189 12:42:24.768227 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9190 12:42:24.774901 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9191 12:42:24.781295 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9192 12:42:24.791527 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9193 12:42:24.792078 DRAM rank0 size:0x100000000,
9194 12:42:24.794637 DRAM rank1 size=0x100000000
9195 12:42:24.795238 CBMEM:
9196 12:42:24.797762 IMD: root @ 0xfffff000 254 entries.
9197 12:42:24.801449 IMD: root @ 0xffffec00 62 entries.
9198 12:42:24.804146 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9199 12:42:24.810905 WARNING: RO_VPD is uninitialized or empty.
9200 12:42:24.814073 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9201 12:42:24.821849 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9202 12:42:24.835473 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9203 12:42:24.846042 BS: romstage times (exec / console): total (unknown) / 23952 ms
9204 12:42:24.846602
9205 12:42:24.846970
9206 12:42:24.856053 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9207 12:42:24.859714 ARM64: Exception handlers installed.
9208 12:42:24.862312 ARM64: Testing exception
9209 12:42:24.866642 ARM64: Done test exception
9210 12:42:24.867208 Enumerating buses...
9211 12:42:24.869575 Show all devs... Before device enumeration.
9212 12:42:24.872223 Root Device: enabled 1
9213 12:42:24.875462 CPU_CLUSTER: 0: enabled 1
9214 12:42:24.876033 CPU: 00: enabled 1
9215 12:42:24.879583 Compare with tree...
9216 12:42:24.880140 Root Device: enabled 1
9217 12:42:24.882092 CPU_CLUSTER: 0: enabled 1
9218 12:42:24.886085 CPU: 00: enabled 1
9219 12:42:24.886652 Root Device scanning...
9220 12:42:24.888967 scan_static_bus for Root Device
9221 12:42:24.891998 CPU_CLUSTER: 0 enabled
9222 12:42:24.895984 scan_static_bus for Root Device done
9223 12:42:24.898986 scan_bus: bus Root Device finished in 8 msecs
9224 12:42:24.899606 done
9225 12:42:24.905395 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9226 12:42:24.908398 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9227 12:42:24.915105 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9228 12:42:24.918380 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9229 12:42:24.921942 Allocating resources...
9230 12:42:24.925658 Reading resources...
9231 12:42:24.928520 Root Device read_resources bus 0 link: 0
9232 12:42:24.931794 DRAM rank0 size:0x100000000,
9233 12:42:24.932276 DRAM rank1 size=0x100000000
9234 12:42:24.938756 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9235 12:42:24.939330 CPU: 00 missing read_resources
9236 12:42:24.945268 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9237 12:42:24.947848 Root Device read_resources bus 0 link: 0 done
9238 12:42:24.951539 Done reading resources.
9239 12:42:24.954763 Show resources in subtree (Root Device)...After reading.
9240 12:42:24.958059 Root Device child on link 0 CPU_CLUSTER: 0
9241 12:42:24.960938 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 12:42:24.971446 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 12:42:24.971973 CPU: 00
9244 12:42:24.977508 Root Device assign_resources, bus 0 link: 0
9245 12:42:24.982048 CPU_CLUSTER: 0 missing set_resources
9246 12:42:24.983856 Root Device assign_resources, bus 0 link: 0 done
9247 12:42:24.987916 Done setting resources.
9248 12:42:24.990554 Show resources in subtree (Root Device)...After assigning values.
9249 12:42:24.994346 Root Device child on link 0 CPU_CLUSTER: 0
9250 12:42:25.000942 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 12:42:25.006957 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 12:42:25.010469 CPU: 00
9253 12:42:25.010998 Done allocating resources.
9254 12:42:25.017064 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9255 12:42:25.017606 Enabling resources...
9256 12:42:25.020440 done.
9257 12:42:25.023751 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9258 12:42:25.027224 Initializing devices...
9259 12:42:25.027701 Root Device init
9260 12:42:25.030220 init hardware done!
9261 12:42:25.030640 0x00000018: ctrlr->caps
9262 12:42:25.033128 52.000 MHz: ctrlr->f_max
9263 12:42:25.036696 0.400 MHz: ctrlr->f_min
9264 12:42:25.039722 0x40ff8080: ctrlr->voltages
9265 12:42:25.040153 sclk: 390625
9266 12:42:25.040486 Bus Width = 1
9267 12:42:25.043198 sclk: 390625
9268 12:42:25.043785 Bus Width = 1
9269 12:42:25.046182 Early init status = 3
9270 12:42:25.049977 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9271 12:42:25.053416 in-header: 03 fc 00 00 01 00 00 00
9272 12:42:25.056739 in-data: 00
9273 12:42:25.059873 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9274 12:42:25.065545 in-header: 03 fd 00 00 00 00 00 00
9275 12:42:25.068923 in-data:
9276 12:42:25.071889 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9277 12:42:25.076240 in-header: 03 fc 00 00 01 00 00 00
9278 12:42:25.079551 in-data: 00
9279 12:42:25.083522 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9280 12:42:25.088975 in-header: 03 fd 00 00 00 00 00 00
9281 12:42:25.091554 in-data:
9282 12:42:25.094965 [SSUSB] Setting up USB HOST controller...
9283 12:42:25.098931 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9284 12:42:25.102268 [SSUSB] phy power-on done.
9285 12:42:25.105576 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9286 12:42:25.111280 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9287 12:42:25.115323 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9288 12:42:25.121716 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9289 12:42:25.127956 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9290 12:42:25.134779 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9291 12:42:25.142034 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9292 12:42:25.148489 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9293 12:42:25.151320 SPM: binary array size = 0x9dc
9294 12:42:25.155234 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9295 12:42:25.161313 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9296 12:42:25.167836 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9297 12:42:25.174277 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9298 12:42:25.177281 configure_display: Starting display init
9299 12:42:25.211493 anx7625_power_on_init: Init interface.
9300 12:42:25.215402 anx7625_disable_pd_protocol: Disabled PD feature.
9301 12:42:25.218785 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9302 12:42:25.247689 anx7625_start_dp_work: Secure OCM version=00
9303 12:42:25.249906 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9304 12:42:25.264312 sp_tx_get_edid_block: EDID Block = 1
9305 12:42:25.367223 Extracted contents:
9306 12:42:25.370082 header: 00 ff ff ff ff ff ff 00
9307 12:42:25.374210 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9308 12:42:25.376693 version: 01 04
9309 12:42:25.380356 basic params: 95 1f 11 78 0a
9310 12:42:25.383576 chroma info: 76 90 94 55 54 90 27 21 50 54
9311 12:42:25.387260 established: 00 00 00
9312 12:42:25.393466 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9313 12:42:25.396878 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9314 12:42:25.403144 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9315 12:42:25.410296 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9316 12:42:25.416343 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9317 12:42:25.419922 extensions: 00
9318 12:42:25.420493 checksum: fb
9319 12:42:25.420864
9320 12:42:25.426346 Manufacturer: IVO Model 57d Serial Number 0
9321 12:42:25.426929 Made week 0 of 2020
9322 12:42:25.429932 EDID version: 1.4
9323 12:42:25.430484 Digital display
9324 12:42:25.432698 6 bits per primary color channel
9325 12:42:25.433176 DisplayPort interface
9326 12:42:25.435981 Maximum image size: 31 cm x 17 cm
9327 12:42:25.439516 Gamma: 220%
9328 12:42:25.440159 Check DPMS levels
9329 12:42:25.446032 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9330 12:42:25.449128 First detailed timing is preferred timing
9331 12:42:25.453108 Established timings supported:
9332 12:42:25.453634 Standard timings supported:
9333 12:42:25.455780 Detailed timings
9334 12:42:25.458965 Hex of detail: 383680a07038204018303c0035ae10000019
9335 12:42:25.465296 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9336 12:42:25.468744 0780 0798 07c8 0820 hborder 0
9337 12:42:25.472004 0438 043b 0447 0458 vborder 0
9338 12:42:25.475205 -hsync -vsync
9339 12:42:25.475847 Did detailed timing
9340 12:42:25.482343 Hex of detail: 000000000000000000000000000000000000
9341 12:42:25.485269 Manufacturer-specified data, tag 0
9342 12:42:25.488732 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9343 12:42:25.492346 ASCII string: InfoVision
9344 12:42:25.495332 Hex of detail: 000000fe00523134304e574635205248200a
9345 12:42:25.499241 ASCII string: R140NWF5 RH
9346 12:42:25.499828 Checksum
9347 12:42:25.501988 Checksum: 0xfb (valid)
9348 12:42:25.504987 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9349 12:42:25.508461 DSI data_rate: 832800000 bps
9350 12:42:25.515010 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9351 12:42:25.517963 anx7625_parse_edid: pixelclock(138800).
9352 12:42:25.521742 hactive(1920), hsync(48), hfp(24), hbp(88)
9353 12:42:25.525247 vactive(1080), vsync(12), vfp(3), vbp(17)
9354 12:42:25.528612 anx7625_dsi_config: config dsi.
9355 12:42:25.535063 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9356 12:42:25.548893 anx7625_dsi_config: success to config DSI
9357 12:42:25.552358 anx7625_dp_start: MIPI phy setup OK.
9358 12:42:25.555497 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9359 12:42:25.558332 mtk_ddp_mode_set invalid vrefresh 60
9360 12:42:25.561692 main_disp_path_setup
9361 12:42:25.562112 ovl_layer_smi_id_en
9362 12:42:25.564923 ovl_layer_smi_id_en
9363 12:42:25.565343 ccorr_config
9364 12:42:25.565679 aal_config
9365 12:42:25.568899 gamma_config
9366 12:42:25.569319 postmask_config
9367 12:42:25.572243 dither_config
9368 12:42:25.575245 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9369 12:42:25.581840 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9370 12:42:25.585299 Root Device init finished in 554 msecs
9371 12:42:25.588036 CPU_CLUSTER: 0 init
9372 12:42:25.595316 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9373 12:42:25.602034 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9374 12:42:25.602560 APU_MBOX 0x190000b0 = 0x10001
9375 12:42:25.604547 APU_MBOX 0x190001b0 = 0x10001
9376 12:42:25.608206 APU_MBOX 0x190005b0 = 0x10001
9377 12:42:25.611542 APU_MBOX 0x190006b0 = 0x10001
9378 12:42:25.617715 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9379 12:42:25.628066 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9380 12:42:25.640321 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9381 12:42:25.646994 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9382 12:42:25.658700 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9383 12:42:25.667654 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9384 12:42:25.671325 CPU_CLUSTER: 0 init finished in 81 msecs
9385 12:42:25.674414 Devices initialized
9386 12:42:25.677458 Show all devs... After init.
9387 12:42:25.678034 Root Device: enabled 1
9388 12:42:25.680876 CPU_CLUSTER: 0: enabled 1
9389 12:42:25.684353 CPU: 00: enabled 1
9390 12:42:25.687422 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9391 12:42:25.690163 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9392 12:42:25.693815 ELOG: NV offset 0x57f000 size 0x1000
9393 12:42:25.700639 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9394 12:42:25.708175 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9395 12:42:25.710530 ELOG: Event(17) added with size 13 at 2024-02-05 12:42:29 UTC
9396 12:42:25.714494 out: cmd=0x121: 03 db 21 01 00 00 00 00
9397 12:42:25.717594 in-header: 03 30 00 00 2c 00 00 00
9398 12:42:25.730986 in-data: 2f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 12:42:25.738069 ELOG: Event(A1) added with size 10 at 2024-02-05 12:42:29 UTC
9400 12:42:25.744492 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9401 12:42:25.750934 ELOG: Event(A0) added with size 9 at 2024-02-05 12:42:29 UTC
9402 12:42:25.754306 elog_add_boot_reason: Logged dev mode boot
9403 12:42:25.757574 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9404 12:42:25.760863 Finalize devices...
9405 12:42:25.761398 Devices finalized
9406 12:42:25.767892 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9407 12:42:25.770479 Writing coreboot table at 0xffe64000
9408 12:42:25.774322 0. 000000000010a000-0000000000113fff: RAMSTAGE
9409 12:42:25.777304 1. 0000000040000000-00000000400fffff: RAM
9410 12:42:25.784086 2. 0000000040100000-000000004032afff: RAMSTAGE
9411 12:42:25.787550 3. 000000004032b000-00000000545fffff: RAM
9412 12:42:25.790811 4. 0000000054600000-000000005465ffff: BL31
9413 12:42:25.794213 5. 0000000054660000-00000000ffe63fff: RAM
9414 12:42:25.800658 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9415 12:42:25.804586 7. 0000000100000000-000000023fffffff: RAM
9416 12:42:25.805126 Passing 5 GPIOs to payload:
9417 12:42:25.810497 NAME | PORT | POLARITY | VALUE
9418 12:42:25.814878 EC in RW | 0x000000aa | low | undefined
9419 12:42:25.820549 EC interrupt | 0x00000005 | low | undefined
9420 12:42:25.823864 TPM interrupt | 0x000000ab | high | undefined
9421 12:42:25.830585 SD card detect | 0x00000011 | high | undefined
9422 12:42:25.833382 speaker enable | 0x00000093 | high | undefined
9423 12:42:25.837721 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9424 12:42:25.840304 in-header: 03 f9 00 00 02 00 00 00
9425 12:42:25.843402 in-data: 02 00
9426 12:42:25.846904 ADC[4]: Raw value=902955 ID=7
9427 12:42:25.847641 ADC[3]: Raw value=213916 ID=1
9428 12:42:25.850741 RAM Code: 0x71
9429 12:42:25.853635 ADC[6]: Raw value=75000 ID=0
9430 12:42:25.854161 ADC[5]: Raw value=213546 ID=1
9431 12:42:25.856751 SKU Code: 0x1
9432 12:42:25.863459 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8928
9433 12:42:25.863981 coreboot table: 964 bytes.
9434 12:42:25.866708 IMD ROOT 0. 0xfffff000 0x00001000
9435 12:42:25.869777 IMD SMALL 1. 0xffffe000 0x00001000
9436 12:42:25.872926 RO MCACHE 2. 0xffffc000 0x00001104
9437 12:42:25.876166 CONSOLE 3. 0xfff7c000 0x00080000
9438 12:42:25.880235 FMAP 4. 0xfff7b000 0x00000452
9439 12:42:25.882752 TIME STAMP 5. 0xfff7a000 0x00000910
9440 12:42:25.886899 VBOOT WORK 6. 0xfff66000 0x00014000
9441 12:42:25.890318 RAMOOPS 7. 0xffe66000 0x00100000
9442 12:42:25.892943 COREBOOT 8. 0xffe64000 0x00002000
9443 12:42:25.896240 IMD small region:
9444 12:42:25.899744 IMD ROOT 0. 0xffffec00 0x00000400
9445 12:42:25.902665 VPD 1. 0xffffeb80 0x0000006c
9446 12:42:25.906141 MMC STATUS 2. 0xffffeb60 0x00000004
9447 12:42:25.909854 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9448 12:42:25.913983 Probing TPM: done!
9449 12:42:25.916010 Connected to device vid:did:rid of 1ae0:0028:00
9450 12:42:25.927307 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9451 12:42:25.930958 Initialized TPM device CR50 revision 0
9452 12:42:25.933936 Checking cr50 for pending updates
9453 12:42:25.938625 Reading cr50 TPM mode
9454 12:42:25.947521 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9455 12:42:25.953849 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9456 12:42:25.993966 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9457 12:42:25.996978 Checking segment from ROM address 0x40100000
9458 12:42:26.000722 Checking segment from ROM address 0x4010001c
9459 12:42:26.007172 Loading segment from ROM address 0x40100000
9460 12:42:26.007812 code (compression=0)
9461 12:42:26.016982 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9462 12:42:26.024052 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9463 12:42:26.024619 it's not compressed!
9464 12:42:26.030093 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9465 12:42:26.036798 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9466 12:42:26.053914 Loading segment from ROM address 0x4010001c
9467 12:42:26.054426 Entry Point 0x80000000
9468 12:42:26.057597 Loaded segments
9469 12:42:26.060346 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9470 12:42:26.067521 Jumping to boot code at 0x80000000(0xffe64000)
9471 12:42:26.074394 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9472 12:42:26.080993 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9473 12:42:26.088603 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9474 12:42:26.091887 Checking segment from ROM address 0x40100000
9475 12:42:26.095475 Checking segment from ROM address 0x4010001c
9476 12:42:26.101706 Loading segment from ROM address 0x40100000
9477 12:42:26.102245 code (compression=1)
9478 12:42:26.108445 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9479 12:42:26.118494 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9480 12:42:26.119054 using LZMA
9481 12:42:26.127264 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9482 12:42:26.134138 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9483 12:42:26.137045 Loading segment from ROM address 0x4010001c
9484 12:42:26.137618 Entry Point 0x54601000
9485 12:42:26.140628 Loaded segments
9486 12:42:26.143737 NOTICE: MT8192 bl31_setup
9487 12:42:26.150482 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9488 12:42:26.154195 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9489 12:42:26.156777 WARNING: region 0:
9490 12:42:26.160744 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 12:42:26.161182 WARNING: region 1:
9492 12:42:26.167179 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9493 12:42:26.170029 WARNING: region 2:
9494 12:42:26.173263 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9495 12:42:26.177270 WARNING: region 3:
9496 12:42:26.180106 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 12:42:26.183669 WARNING: region 4:
9498 12:42:26.189881 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 12:42:26.190447 WARNING: region 5:
9500 12:42:26.194227 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 12:42:26.196956 WARNING: region 6:
9502 12:42:26.200020 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 12:42:26.203468 WARNING: region 7:
9504 12:42:26.206970 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 12:42:26.213512 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9506 12:42:26.216831 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9507 12:42:26.220292 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9508 12:42:26.227089 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9509 12:42:26.230535 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9510 12:42:26.233938 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9511 12:42:26.240712 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9512 12:42:26.243971 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9513 12:42:26.250528 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9514 12:42:26.254282 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9515 12:42:26.257257 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9516 12:42:26.263627 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9517 12:42:26.266452 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9518 12:42:26.269860 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9519 12:42:26.276404 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9520 12:42:26.279707 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9521 12:42:26.286614 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9522 12:42:26.289604 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9523 12:42:26.293593 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9524 12:42:26.299760 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9525 12:42:26.302937 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9526 12:42:26.309737 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9527 12:42:26.312913 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9528 12:42:26.316550 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9529 12:42:26.322707 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9530 12:42:26.326569 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9531 12:42:26.333019 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9532 12:42:26.336503 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9533 12:42:26.340131 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9534 12:42:26.346043 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9535 12:42:26.349487 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9536 12:42:26.356333 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9537 12:42:26.359625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9538 12:42:26.362732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9539 12:42:26.366005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9540 12:42:26.372865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9541 12:42:26.376425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9542 12:42:26.379597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9543 12:42:26.382943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9544 12:42:26.389707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9545 12:42:26.392335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9546 12:42:26.396276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9547 12:42:26.399233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9548 12:42:26.406367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9549 12:42:26.409360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9550 12:42:26.412533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9551 12:42:26.415609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9552 12:42:26.422483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9553 12:42:26.426382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9554 12:42:26.432701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9555 12:42:26.435907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9556 12:42:26.439128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9557 12:42:26.446336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9558 12:42:26.449159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9559 12:42:26.456445 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9560 12:42:26.459657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9561 12:42:26.462450 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9562 12:42:26.469663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9563 12:42:26.472179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9564 12:42:26.479408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9565 12:42:26.482065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9566 12:42:26.489428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9567 12:42:26.492227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9568 12:42:26.499158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9569 12:42:26.502131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9570 12:42:26.505811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9571 12:42:26.512211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9572 12:42:26.516013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9573 12:42:26.522460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9574 12:42:26.525614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9575 12:42:26.532634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9576 12:42:26.535686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9577 12:42:26.542174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9578 12:42:26.545804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9579 12:42:26.549436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9580 12:42:26.555109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9581 12:42:26.558492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9582 12:42:26.565497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9583 12:42:26.568958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9584 12:42:26.575007 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9585 12:42:26.578806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9586 12:42:26.585266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9587 12:42:26.588260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9588 12:42:26.592046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9589 12:42:26.598351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9590 12:42:26.602166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9591 12:42:26.608213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9592 12:42:26.611421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9593 12:42:26.618292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9594 12:42:26.621476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9595 12:42:26.625680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9596 12:42:26.631583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9597 12:42:26.635275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9598 12:42:26.641551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9599 12:42:26.644941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9600 12:42:26.651592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9601 12:42:26.654664 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9602 12:42:26.657954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9603 12:42:26.661970 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9604 12:42:26.667919 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9605 12:42:26.671574 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9606 12:42:26.674657 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9607 12:42:26.681198 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9608 12:42:26.684387 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9609 12:42:26.692042 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9610 12:42:26.695153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9611 12:42:26.698419 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9612 12:42:26.704644 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9613 12:42:26.708529 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9614 12:42:26.715067 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9615 12:42:26.718317 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9616 12:42:26.721472 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9617 12:42:26.728558 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9618 12:42:26.731154 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9619 12:42:26.738205 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9620 12:42:26.741308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9621 12:42:26.744672 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9622 12:42:26.748043 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9623 12:42:26.754761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9624 12:42:26.758392 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9625 12:42:26.762212 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9626 12:42:26.767477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9627 12:42:26.772642 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9628 12:42:26.775193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9629 12:42:26.777882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9630 12:42:26.784912 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9631 12:42:26.788136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9632 12:42:26.794759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9633 12:42:26.797705 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9634 12:42:26.801195 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9635 12:42:26.807456 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9636 12:42:26.810696 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9637 12:42:26.817183 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9638 12:42:26.820991 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9639 12:42:26.823760 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9640 12:42:26.830492 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9641 12:42:26.834199 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9642 12:42:26.840856 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9643 12:42:26.843810 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9644 12:42:26.847759 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9645 12:42:26.854126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9646 12:42:26.857274 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9647 12:42:26.864098 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9648 12:42:26.867230 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9649 12:42:26.870656 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9650 12:42:26.877842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9651 12:42:26.880553 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9652 12:42:26.883553 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9653 12:42:26.890146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9654 12:42:26.894038 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9655 12:42:26.900389 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9656 12:42:26.903864 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9657 12:42:26.906750 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9658 12:42:26.913466 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9659 12:42:26.916663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9660 12:42:26.923558 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9661 12:42:26.927283 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9662 12:42:26.930331 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9663 12:42:26.936940 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9664 12:42:26.940639 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9665 12:42:26.947264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9666 12:42:26.950531 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9667 12:42:26.953311 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9668 12:42:26.960100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9669 12:42:26.963074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9670 12:42:26.970224 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9671 12:42:26.973344 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9672 12:42:26.976003 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9673 12:42:26.983040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9674 12:42:26.986236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9675 12:42:26.993049 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9676 12:42:26.995893 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9677 12:42:26.999791 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9678 12:42:27.006115 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9679 12:42:27.009344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9680 12:42:27.015452 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9681 12:42:27.018868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9682 12:42:27.026078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9683 12:42:27.028773 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9684 12:42:27.032516 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9685 12:42:27.038708 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9686 12:42:27.042184 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9687 12:42:27.048995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9688 12:42:27.053005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9689 12:42:27.055171 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9690 12:42:27.061867 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9691 12:42:27.065242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9692 12:42:27.071742 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9693 12:42:27.075281 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9694 12:42:27.078322 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9695 12:42:27.085142 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9696 12:42:27.088501 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9697 12:42:27.095187 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9698 12:42:27.098170 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9699 12:42:27.104347 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9700 12:42:27.107553 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9701 12:42:27.110908 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9702 12:42:27.118410 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9703 12:42:27.120946 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9704 12:42:27.128048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9705 12:42:27.131463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9706 12:42:27.137722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9707 12:42:27.140975 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9708 12:42:27.143913 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9709 12:42:27.151182 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9710 12:42:27.154044 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9711 12:42:27.160733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9712 12:42:27.163822 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9713 12:42:27.170455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9714 12:42:27.173311 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9715 12:42:27.176790 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9716 12:42:27.183635 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9717 12:42:27.187476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9718 12:42:27.193834 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9719 12:42:27.196851 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9720 12:42:27.203602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9721 12:42:27.207075 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9722 12:42:27.210394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9723 12:42:27.216640 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9724 12:42:27.219605 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9725 12:42:27.226390 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9726 12:42:27.230481 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9727 12:42:27.236307 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9728 12:42:27.239758 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9729 12:42:27.242714 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9730 12:42:27.249634 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9731 12:42:27.252941 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9732 12:42:27.259281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9733 12:42:27.262568 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9734 12:42:27.265896 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9735 12:42:27.272930 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9736 12:42:27.276085 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9737 12:42:27.279437 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9738 12:42:27.282712 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9739 12:42:27.289150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9740 12:42:27.292452 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9741 12:42:27.295891 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9742 12:42:27.302696 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9743 12:42:27.305554 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9744 12:42:27.308712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9745 12:42:27.315253 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9746 12:42:27.319067 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9747 12:42:27.325417 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9748 12:42:27.328425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9749 12:42:27.331935 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9750 12:42:27.338353 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9751 12:42:27.341739 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9752 12:42:27.348495 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9753 12:42:27.351653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9754 12:42:27.355301 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9755 12:42:27.361158 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9756 12:42:27.364765 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9757 12:42:27.368026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9758 12:42:27.374942 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9759 12:42:27.377795 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9760 12:42:27.384604 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9761 12:42:27.387769 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9762 12:42:27.391084 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9763 12:42:27.397880 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9764 12:42:27.401734 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9765 12:42:27.404764 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9766 12:42:27.410889 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9767 12:42:27.414449 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9768 12:42:27.418189 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9769 12:42:27.424293 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9770 12:42:27.428090 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9771 12:42:27.434591 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9772 12:42:27.437979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9773 12:42:27.440769 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9774 12:42:27.444228 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9775 12:42:27.450734 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9776 12:42:27.454013 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9777 12:42:27.457535 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9778 12:42:27.461265 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9779 12:42:27.467116 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9780 12:42:27.471039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9781 12:42:27.473380 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9782 12:42:27.477260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9783 12:42:27.483917 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9784 12:42:27.487259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9785 12:42:27.490156 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9786 12:42:27.496905 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9787 12:42:27.500194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9788 12:42:27.503985 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9789 12:42:27.510021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9790 12:42:27.513492 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9791 12:42:27.520210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9792 12:42:27.523604 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9793 12:42:27.530056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9794 12:42:27.533140 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9795 12:42:27.536259 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9796 12:42:27.543232 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9797 12:42:27.546502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9798 12:42:27.553451 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9799 12:42:27.556321 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9800 12:42:27.562703 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9801 12:42:27.566157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9802 12:42:27.569861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9803 12:42:27.576317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9804 12:42:27.579297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9805 12:42:27.586012 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9806 12:42:27.589377 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9807 12:42:27.592486 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9808 12:42:27.599462 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9809 12:42:27.602854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9810 12:42:27.609340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9811 12:42:27.612089 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9812 12:42:27.619012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9813 12:42:27.622215 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9814 12:42:27.625911 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9815 12:42:27.632454 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9816 12:42:27.636026 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9817 12:42:27.642471 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9818 12:42:27.646259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9819 12:42:27.648982 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9820 12:42:27.655478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9821 12:42:27.659589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9822 12:42:27.665170 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9823 12:42:27.668399 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9824 12:42:27.675182 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9825 12:42:27.678148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9826 12:42:27.682420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9827 12:42:27.688537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9828 12:42:27.691474 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9829 12:42:27.698287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9830 12:42:27.701860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9831 12:42:27.704588 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9832 12:42:27.711605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9833 12:42:27.715226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9834 12:42:27.721369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9835 12:42:27.725137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9836 12:42:27.727985 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9837 12:42:27.734502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9838 12:42:27.737848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9839 12:42:27.744205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9840 12:42:27.747590 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9841 12:42:27.754213 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9842 12:42:27.757341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9843 12:42:27.760810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9844 12:42:27.767748 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9845 12:42:27.770644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9846 12:42:27.777401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9847 12:42:27.780708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9848 12:42:27.786821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9849 12:42:27.790227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9850 12:42:27.793259 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9851 12:42:27.799943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9852 12:42:27.803289 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9853 12:42:27.810450 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9854 12:42:27.813114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9855 12:42:27.819835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9856 12:42:27.822937 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9857 12:42:27.826608 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9858 12:42:27.833280 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9859 12:42:27.836563 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9860 12:42:27.843092 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9861 12:42:27.846097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9862 12:42:27.852659 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9863 12:42:27.856531 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9864 12:42:27.859482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9865 12:42:27.866555 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9866 12:42:27.869419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9867 12:42:27.876328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9868 12:42:27.879683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9869 12:42:27.886196 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9870 12:42:27.889252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9871 12:42:27.895753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9872 12:42:27.898623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9873 12:42:27.905416 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9874 12:42:27.909229 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9875 12:42:27.912165 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9876 12:42:27.918958 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9877 12:42:27.922835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9878 12:42:27.928496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9879 12:42:27.931858 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9880 12:42:27.938663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9881 12:42:27.942343 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9882 12:42:27.945458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9883 12:42:27.952076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9884 12:42:27.954914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9885 12:42:27.962201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9886 12:42:27.965123 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9887 12:42:27.971869 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9888 12:42:27.975086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9889 12:42:27.981588 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9890 12:42:27.984823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9891 12:42:27.989205 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9892 12:42:27.994942 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9893 12:42:27.998326 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9894 12:42:28.004707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9895 12:42:28.008176 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9896 12:42:28.014914 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9897 12:42:28.018937 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9898 12:42:28.021128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9899 12:42:28.027536 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9900 12:42:28.031393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9901 12:42:28.037668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9902 12:42:28.041498 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9903 12:42:28.048557 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9904 12:42:28.051007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9905 12:42:28.057723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9906 12:42:28.061230 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9907 12:42:28.064207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9908 12:42:28.070936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9909 12:42:28.074387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9910 12:42:28.080902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9911 12:42:28.083790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9912 12:42:28.090969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9913 12:42:28.094193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9914 12:42:28.101116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9915 12:42:28.104059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9916 12:42:28.110581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9917 12:42:28.113697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9918 12:42:28.120476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9919 12:42:28.123382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9920 12:42:28.130101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9921 12:42:28.133913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9922 12:42:28.140306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9923 12:42:28.143728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9924 12:42:28.149951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9925 12:42:28.153639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9926 12:42:28.159660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9927 12:42:28.162916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9928 12:42:28.169991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9929 12:42:28.173089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9930 12:42:28.180026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9931 12:42:28.182892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9932 12:42:28.189763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9933 12:42:28.192745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9934 12:42:28.199328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9935 12:42:28.202811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9936 12:42:28.209553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9937 12:42:28.212512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9938 12:42:28.218912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9939 12:42:28.222525 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9940 12:42:28.225737 INFO: [APUAPC] vio 0
9941 12:42:28.229712 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9942 12:42:28.236083 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9943 12:42:28.236610 INFO: [APUAPC] D0_APC_0: 0x400510
9944 12:42:28.238823 INFO: [APUAPC] D0_APC_1: 0x0
9945 12:42:28.242566 INFO: [APUAPC] D0_APC_2: 0x1540
9946 12:42:28.245867 INFO: [APUAPC] D0_APC_3: 0x0
9947 12:42:28.249232 INFO: [APUAPC] D1_APC_0: 0xffffffff
9948 12:42:28.252600 INFO: [APUAPC] D1_APC_1: 0xffffffff
9949 12:42:28.256332 INFO: [APUAPC] D1_APC_2: 0x3fffff
9950 12:42:28.258901 INFO: [APUAPC] D1_APC_3: 0x0
9951 12:42:28.263009 INFO: [APUAPC] D2_APC_0: 0xffffffff
9952 12:42:28.265107 INFO: [APUAPC] D2_APC_1: 0xffffffff
9953 12:42:28.268731 INFO: [APUAPC] D2_APC_2: 0x3fffff
9954 12:42:28.271819 INFO: [APUAPC] D2_APC_3: 0x0
9955 12:42:28.275520 INFO: [APUAPC] D3_APC_0: 0xffffffff
9956 12:42:28.278887 INFO: [APUAPC] D3_APC_1: 0xffffffff
9957 12:42:28.282047 INFO: [APUAPC] D3_APC_2: 0x3fffff
9958 12:42:28.285541 INFO: [APUAPC] D3_APC_3: 0x0
9959 12:42:28.288359 INFO: [APUAPC] D4_APC_0: 0xffffffff
9960 12:42:28.291842 INFO: [APUAPC] D4_APC_1: 0xffffffff
9961 12:42:28.294848 INFO: [APUAPC] D4_APC_2: 0x3fffff
9962 12:42:28.298890 INFO: [APUAPC] D4_APC_3: 0x0
9963 12:42:28.302339 INFO: [APUAPC] D5_APC_0: 0xffffffff
9964 12:42:28.305611 INFO: [APUAPC] D5_APC_1: 0xffffffff
9965 12:42:28.308551 INFO: [APUAPC] D5_APC_2: 0x3fffff
9966 12:42:28.312260 INFO: [APUAPC] D5_APC_3: 0x0
9967 12:42:28.314836 INFO: [APUAPC] D6_APC_0: 0xffffffff
9968 12:42:28.318202 INFO: [APUAPC] D6_APC_1: 0xffffffff
9969 12:42:28.321374 INFO: [APUAPC] D6_APC_2: 0x3fffff
9970 12:42:28.324846 INFO: [APUAPC] D6_APC_3: 0x0
9971 12:42:28.327847 INFO: [APUAPC] D7_APC_0: 0xffffffff
9972 12:42:28.331811 INFO: [APUAPC] D7_APC_1: 0xffffffff
9973 12:42:28.335473 INFO: [APUAPC] D7_APC_2: 0x3fffff
9974 12:42:28.338027 INFO: [APUAPC] D7_APC_3: 0x0
9975 12:42:28.341041 INFO: [APUAPC] D8_APC_0: 0xffffffff
9976 12:42:28.344368 INFO: [APUAPC] D8_APC_1: 0xffffffff
9977 12:42:28.347612 INFO: [APUAPC] D8_APC_2: 0x3fffff
9978 12:42:28.351917 INFO: [APUAPC] D8_APC_3: 0x0
9979 12:42:28.354260 INFO: [APUAPC] D9_APC_0: 0xffffffff
9980 12:42:28.357642 INFO: [APUAPC] D9_APC_1: 0xffffffff
9981 12:42:28.361358 INFO: [APUAPC] D9_APC_2: 0x3fffff
9982 12:42:28.364854 INFO: [APUAPC] D9_APC_3: 0x0
9983 12:42:28.367432 INFO: [APUAPC] D10_APC_0: 0xffffffff
9984 12:42:28.370838 INFO: [APUAPC] D10_APC_1: 0xffffffff
9985 12:42:28.374411 INFO: [APUAPC] D10_APC_2: 0x3fffff
9986 12:42:28.377691 INFO: [APUAPC] D10_APC_3: 0x0
9987 12:42:28.380515 INFO: [APUAPC] D11_APC_0: 0xffffffff
9988 12:42:28.383868 INFO: [APUAPC] D11_APC_1: 0xffffffff
9989 12:42:28.387656 INFO: [APUAPC] D11_APC_2: 0x3fffff
9990 12:42:28.391477 INFO: [APUAPC] D11_APC_3: 0x0
9991 12:42:28.394464 INFO: [APUAPC] D12_APC_0: 0xffffffff
9992 12:42:28.397770 INFO: [APUAPC] D12_APC_1: 0xffffffff
9993 12:42:28.400787 INFO: [APUAPC] D12_APC_2: 0x3fffff
9994 12:42:28.403923 INFO: [APUAPC] D12_APC_3: 0x0
9995 12:42:28.407461 INFO: [APUAPC] D13_APC_0: 0xffffffff
9996 12:42:28.411026 INFO: [APUAPC] D13_APC_1: 0xffffffff
9997 12:42:28.413594 INFO: [APUAPC] D13_APC_2: 0x3fffff
9998 12:42:28.416928 INFO: [APUAPC] D13_APC_3: 0x0
9999 12:42:28.420138 INFO: [APUAPC] D14_APC_0: 0xffffffff
10000 12:42:28.423755 INFO: [APUAPC] D14_APC_1: 0xffffffff
10001 12:42:28.426870 INFO: [APUAPC] D14_APC_2: 0x3fffff
10002 12:42:28.430728 INFO: [APUAPC] D14_APC_3: 0x0
10003 12:42:28.434156 INFO: [APUAPC] D15_APC_0: 0xffffffff
10004 12:42:28.437274 INFO: [APUAPC] D15_APC_1: 0xffffffff
10005 12:42:28.440700 INFO: [APUAPC] D15_APC_2: 0x3fffff
10006 12:42:28.443934 INFO: [APUAPC] D15_APC_3: 0x0
10007 12:42:28.447663 INFO: [APUAPC] APC_CON: 0x4
10008 12:42:28.450458 INFO: [NOCDAPC] D0_APC_0: 0x0
10009 12:42:28.453272 INFO: [NOCDAPC] D0_APC_1: 0x0
10010 12:42:28.453837 INFO: [NOCDAPC] D1_APC_0: 0x0
10011 12:42:28.457063 INFO: [NOCDAPC] D1_APC_1: 0xfff
10012 12:42:28.460431 INFO: [NOCDAPC] D2_APC_0: 0x0
10013 12:42:28.463280 INFO: [NOCDAPC] D2_APC_1: 0xfff
10014 12:42:28.467071 INFO: [NOCDAPC] D3_APC_0: 0x0
10015 12:42:28.470379 INFO: [NOCDAPC] D3_APC_1: 0xfff
10016 12:42:28.473317 INFO: [NOCDAPC] D4_APC_0: 0x0
10017 12:42:28.477334 INFO: [NOCDAPC] D4_APC_1: 0xfff
10018 12:42:28.479754 INFO: [NOCDAPC] D5_APC_0: 0x0
10019 12:42:28.482976 INFO: [NOCDAPC] D5_APC_1: 0xfff
10020 12:42:28.486672 INFO: [NOCDAPC] D6_APC_0: 0x0
10021 12:42:28.487193 INFO: [NOCDAPC] D6_APC_1: 0xfff
10022 12:42:28.489856 INFO: [NOCDAPC] D7_APC_0: 0x0
10023 12:42:28.493671 INFO: [NOCDAPC] D7_APC_1: 0xfff
10024 12:42:28.497106 INFO: [NOCDAPC] D8_APC_0: 0x0
10025 12:42:28.499585 INFO: [NOCDAPC] D8_APC_1: 0xfff
10026 12:42:28.503395 INFO: [NOCDAPC] D9_APC_0: 0x0
10027 12:42:28.506800 INFO: [NOCDAPC] D9_APC_1: 0xfff
10028 12:42:28.509806 INFO: [NOCDAPC] D10_APC_0: 0x0
10029 12:42:28.513038 INFO: [NOCDAPC] D10_APC_1: 0xfff
10030 12:42:28.516129 INFO: [NOCDAPC] D11_APC_0: 0x0
10031 12:42:28.519492 INFO: [NOCDAPC] D11_APC_1: 0xfff
10032 12:42:28.522673 INFO: [NOCDAPC] D12_APC_0: 0x0
10033 12:42:28.526532 INFO: [NOCDAPC] D12_APC_1: 0xfff
10034 12:42:28.529221 INFO: [NOCDAPC] D13_APC_0: 0x0
10035 12:42:28.529642 INFO: [NOCDAPC] D13_APC_1: 0xfff
10036 12:42:28.533730 INFO: [NOCDAPC] D14_APC_0: 0x0
10037 12:42:28.536250 INFO: [NOCDAPC] D14_APC_1: 0xfff
10038 12:42:28.539398 INFO: [NOCDAPC] D15_APC_0: 0x0
10039 12:42:28.542752 INFO: [NOCDAPC] D15_APC_1: 0xfff
10040 12:42:28.545472 INFO: [NOCDAPC] APC_CON: 0x4
10041 12:42:28.549445 INFO: [APUAPC] set_apusys_apc done
10042 12:42:28.552282 INFO: [DEVAPC] devapc_init done
10043 12:42:28.555887 INFO: GICv3 without legacy support detected.
10044 12:42:28.562966 INFO: ARM GICv3 driver initialized in EL3
10045 12:42:28.565630 INFO: Maximum SPI INTID supported: 639
10046 12:42:28.568657 INFO: BL31: Initializing runtime services
10047 12:42:28.575501 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10048 12:42:28.578965 INFO: SPM: enable CPC mode
10049 12:42:28.581940 INFO: mcdi ready for mcusys-off-idle and system suspend
10050 12:42:28.585268 INFO: BL31: Preparing for EL3 exit to normal world
10051 12:42:28.591765 INFO: Entry point address = 0x80000000
10052 12:42:28.592260 INFO: SPSR = 0x8
10053 12:42:28.598630
10054 12:42:28.599150
10055 12:42:28.599527
10056 12:42:28.601782 Starting depthcharge on Spherion...
10057 12:42:28.602311
10058 12:42:28.602673 Wipe memory regions:
10059 12:42:28.603046
10060 12:42:28.605715 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10061 12:42:28.606199 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10062 12:42:28.606616 Setting prompt string to ['asurada:']
10063 12:42:28.607026 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10064 12:42:28.607722 [0x00000040000000, 0x00000054600000)
10065 12:42:28.727780
10066 12:42:28.728348 [0x00000054660000, 0x00000080000000)
10067 12:42:28.988210
10068 12:42:28.988787 [0x000000821a7280, 0x000000ffe64000)
10069 12:42:29.733249
10070 12:42:29.733827 [0x00000100000000, 0x00000240000000)
10071 12:42:31.623547
10072 12:42:31.626220 Initializing XHCI USB controller at 0x11200000.
10073 12:42:32.664316
10074 12:42:32.667461 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10075 12:42:32.667944
10076 12:42:32.668327
10077 12:42:32.668685
10078 12:42:32.669534 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 12:42:32.770962 asurada: tftpboot 192.168.201.1 12703544/tftp-deploy-ezbae8ku/kernel/image.itb 12703544/tftp-deploy-ezbae8ku/kernel/cmdline
10081 12:42:32.771693 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 12:42:32.772155 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10083 12:42:32.776394 tftpboot 192.168.201.1 12703544/tftp-deploy-ezbae8ku/kernel/image.ittp-deploy-ezbae8ku/kernel/cmdline
10084 12:42:32.776875
10085 12:42:32.777247 Waiting for link
10086 12:42:32.937462
10087 12:42:32.938037 R8152: Initializing
10088 12:42:32.938416
10089 12:42:32.940396 Version 6 (ocp_data = 5c30)
10090 12:42:32.940877
10091 12:42:32.944389 R8152: Done initializing
10092 12:42:32.944971
10093 12:42:32.945346 Adding net device
10094 12:42:34.921996
10095 12:42:34.922589 done.
10096 12:42:34.923019
10097 12:42:34.923462 MAC: 00:24:32:30:7c:7b
10098 12:42:34.923908
10099 12:42:34.924874 Sending DHCP discover... done.
10100 12:42:34.925465
10101 12:42:34.927522 Waiting for reply... done.
10102 12:42:34.928060
10103 12:42:34.930778 Sending DHCP request... done.
10104 12:42:34.931281
10105 12:42:34.937442 Waiting for reply... done.
10106 12:42:34.937922
10107 12:42:34.938294 My ip is 192.168.201.14
10108 12:42:34.938647
10109 12:42:34.940469 The DHCP server ip is 192.168.201.1
10110 12:42:34.941044
10111 12:42:34.946729 TFTP server IP predefined by user: 192.168.201.1
10112 12:42:34.947166
10113 12:42:34.954400 Bootfile predefined by user: 12703544/tftp-deploy-ezbae8ku/kernel/image.itb
10114 12:42:34.954953
10115 12:42:34.956830 Sending tftp read request... done.
10116 12:42:34.957261
10117 12:42:34.963324 Waiting for the transfer...
10118 12:42:34.963941
10119 12:42:35.674285 00000000 ################################################################
10120 12:42:35.674818
10121 12:42:36.391868 00080000 ################################################################
10122 12:42:36.392386
10123 12:42:37.112094 00100000 ################################################################
10124 12:42:37.112623
10125 12:42:37.831085 00180000 ################################################################
10126 12:42:37.831661
10127 12:42:38.530186 00200000 ################################################################
10128 12:42:38.530710
10129 12:42:39.228144 00280000 ################################################################
10130 12:42:39.228723
10131 12:42:39.949066 00300000 ################################################################
10132 12:42:39.949586
10133 12:42:40.657372 00380000 ################################################################
10134 12:42:40.658090
10135 12:42:41.369427 00400000 ################################################################
10136 12:42:41.369944
10137 12:42:42.106119 00480000 ################################################################
10138 12:42:42.106819
10139 12:42:42.829834 00500000 ################################################################
10140 12:42:42.830385
10141 12:42:43.552054 00580000 ################################################################
10142 12:42:43.552581
10143 12:42:44.286154 00600000 ################################################################
10144 12:42:44.286672
10145 12:42:45.012828 00680000 ################################################################
10146 12:42:45.013363
10147 12:42:45.739889 00700000 ################################################################
10148 12:42:45.740410
10149 12:42:46.461966 00780000 ################################################################
10150 12:42:46.462522
10151 12:42:47.166664 00800000 ################################################################
10152 12:42:47.167240
10153 12:42:47.878101 00880000 ################################################################
10154 12:42:47.878631
10155 12:42:48.589626 00900000 ################################################################
10156 12:42:48.590160
10157 12:42:49.312339 00980000 ################################################################
10158 12:42:49.312879
10159 12:42:50.040807 00a00000 ################################################################
10160 12:42:50.041403
10161 12:42:50.778179 00a80000 ################################################################
10162 12:42:50.778715
10163 12:42:51.507638 00b00000 ################################################################
10164 12:42:51.508173
10165 12:42:52.234745 00b80000 ################################################################
10166 12:42:52.235279
10167 12:42:52.962708 00c00000 ################################################################
10168 12:42:52.963251
10169 12:42:53.681524 00c80000 ################################################################
10170 12:42:53.682113
10171 12:42:54.406308 00d00000 ################################################################
10172 12:42:54.406844
10173 12:42:55.147838 00d80000 ################################################################
10174 12:42:55.148371
10175 12:42:55.871527 00e00000 ################################################################
10176 12:42:55.872117
10177 12:42:56.591185 00e80000 ################################################################
10178 12:42:56.591835
10179 12:42:57.285925 00f00000 ################################################################
10180 12:42:57.286459
10181 12:42:57.995068 00f80000 ################################################################
10182 12:42:57.995615
10183 12:42:58.716201 01000000 ################################################################
10184 12:42:58.716726
10185 12:42:59.444748 01080000 ################################################################
10186 12:42:59.445270
10187 12:43:00.153874 01100000 ################################################################
10188 12:43:00.154490
10189 12:43:00.866357 01180000 ################################################################
10190 12:43:00.866856
10191 12:43:01.585252 01200000 ################################################################
10192 12:43:01.585770
10193 12:43:02.315501 01280000 ################################################################
10194 12:43:02.316198
10195 12:43:03.053161 01300000 ################################################################
10196 12:43:03.053723
10197 12:43:03.766436 01380000 ################################################################
10198 12:43:03.767013
10199 12:43:04.475767 01400000 ################################################################
10200 12:43:04.476331
10201 12:43:05.203065 01480000 ################################################################
10202 12:43:05.203659
10203 12:43:05.919973 01500000 ################################################################
10204 12:43:05.920551
10205 12:43:06.639292 01580000 ################################################################
10206 12:43:06.639896
10207 12:43:07.357441 01600000 ################################################################
10208 12:43:07.357973
10209 12:43:08.089943 01680000 ################################################################
10210 12:43:08.090501
10211 12:43:08.807767 01700000 ################################################################
10212 12:43:08.808307
10213 12:43:09.535149 01780000 ################################################################
10214 12:43:09.535804
10215 12:43:10.260344 01800000 ################################################################
10216 12:43:10.260858
10217 12:43:10.982453 01880000 ################################################################
10218 12:43:10.983018
10219 12:43:11.706560 01900000 ################################################################
10220 12:43:11.707089
10221 12:43:12.409913 01980000 ################################################################
10222 12:43:12.410526
10223 12:43:13.126586 01a00000 ################################################################
10224 12:43:13.127108
10225 12:43:13.827013 01a80000 ################################################################
10226 12:43:13.827574
10227 12:43:14.541045 01b00000 ################################################################
10228 12:43:14.541628
10229 12:43:15.253550 01b80000 ################################################################
10230 12:43:15.254127
10231 12:43:15.966062 01c00000 ################################################################
10232 12:43:15.966615
10233 12:43:15.990120 01c80000 ## done.
10234 12:43:15.990659
10235 12:43:15.992258 The bootfile was 29900510 bytes long.
10236 12:43:15.992692
10237 12:43:15.995349 Sending tftp read request... done.
10238 12:43:15.995824
10239 12:43:15.999292 Waiting for the transfer...
10240 12:43:15.999773
10241 12:43:16.000118 00000000 # done.
10242 12:43:16.000453
10243 12:43:16.005380 Command line loaded dynamically from TFTP file: 12703544/tftp-deploy-ezbae8ku/kernel/cmdline
10244 12:43:16.009325
10245 12:43:16.028799 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10246 12:43:16.029431
10247 12:43:16.029881 Loading FIT.
10248 12:43:16.030218
10249 12:43:16.032073 Image ramdisk-1 has 17798337 bytes.
10250 12:43:16.032506
10251 12:43:16.035442 Image fdt-1 has 47278 bytes.
10252 12:43:16.035876
10253 12:43:16.038624 Image kernel-1 has 12052857 bytes.
10254 12:43:16.039093
10255 12:43:16.048733 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10256 12:43:16.049252
10257 12:43:16.065336 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10258 12:43:16.065889
10259 12:43:16.071819 Choosing best match conf-1 for compat google,spherion-rev2.
10260 12:43:16.072248
10261 12:43:16.079864 Connected to device vid:did:rid of 1ae0:0028:00
10262 12:43:16.086644
10263 12:43:16.089997 tpm_get_response: command 0x17b, return code 0x0
10264 12:43:16.090439
10265 12:43:16.093875 ec_init: CrosEC protocol v3 supported (256, 248)
10266 12:43:16.097368
10267 12:43:16.100366 tpm_cleanup: add release locality here.
10268 12:43:16.100789
10269 12:43:16.101124 Shutting down all USB controllers.
10270 12:43:16.103730
10271 12:43:16.104149 Removing current net device
10272 12:43:16.104499
10273 12:43:16.110643 Exiting depthcharge with code 4 at timestamp: 76756073
10274 12:43:16.111171
10275 12:43:16.114208 LZMA decompressing kernel-1 to 0x821a6718
10276 12:43:16.114648
10277 12:43:16.117463 LZMA decompressing kernel-1 to 0x40000000
10278 12:43:17.616652
10279 12:43:17.617457 jumping to kernel
10280 12:43:17.619316 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10281 12:43:17.619929 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10282 12:43:17.620376 Setting prompt string to ['Linux version [0-9]']
10283 12:43:17.620758 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10284 12:43:17.621132 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10285 12:43:17.699202
10286 12:43:17.701984 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10287 12:43:17.706399 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10288 12:43:17.707003 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10289 12:43:17.707443 Setting prompt string to []
10290 12:43:17.707881 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10291 12:43:17.708356 Using line separator: #'\n'#
10292 12:43:17.708700 No login prompt set.
10293 12:43:17.709026 Parsing kernel messages
10294 12:43:17.709336 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10295 12:43:17.709913 [login-action] Waiting for messages, (timeout 00:03:36)
10296 12:43:17.710273 Waiting using forced prompt support (timeout 00:01:48)
10297 12:43:17.725180 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10298 12:43:17.728854 [ 0.000000] random: crng init done
10299 12:43:17.735171 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10300 12:43:17.738222 [ 0.000000] efi: UEFI not found.
10301 12:43:17.745095 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10302 12:43:17.751230 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10303 12:43:17.761860 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10304 12:43:17.771349 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10305 12:43:17.777563 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10306 12:43:17.784010 [ 0.000000] printk: bootconsole [mtk8250] enabled
10307 12:43:17.791305 [ 0.000000] NUMA: No NUMA configuration found
10308 12:43:17.797882 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10309 12:43:17.801178 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10310 12:43:17.804611 [ 0.000000] Zone ranges:
10311 12:43:17.811300 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10312 12:43:17.814088 [ 0.000000] DMA32 empty
10313 12:43:17.821070 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10314 12:43:17.824001 [ 0.000000] Movable zone start for each node
10315 12:43:17.827784 [ 0.000000] Early memory node ranges
10316 12:43:17.833961 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10317 12:43:17.840615 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10318 12:43:17.847488 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10319 12:43:17.854083 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10320 12:43:17.860386 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10321 12:43:17.866993 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10322 12:43:17.923686 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10323 12:43:17.930011 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10324 12:43:17.936537 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10325 12:43:17.939633 [ 0.000000] psci: probing for conduit method from DT.
10326 12:43:17.946412 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10327 12:43:17.950072 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10328 12:43:17.957044 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10329 12:43:17.959842 [ 0.000000] psci: SMC Calling Convention v1.2
10330 12:43:17.966498 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10331 12:43:17.969407 [ 0.000000] Detected VIPT I-cache on CPU0
10332 12:43:17.976086 [ 0.000000] CPU features: detected: GIC system register CPU interface
10333 12:43:17.982499 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10334 12:43:17.989698 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10335 12:43:17.996066 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10336 12:43:18.005623 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10337 12:43:18.012648 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10338 12:43:18.016033 [ 0.000000] alternatives: applying boot alternatives
10339 12:43:18.022501 [ 0.000000] Fallback order for Node 0: 0
10340 12:43:18.028406 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10341 12:43:18.032555 [ 0.000000] Policy zone: Normal
10342 12:43:18.055583 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10343 12:43:18.064975 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10344 12:43:18.076001 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10345 12:43:18.087028 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10346 12:43:18.092498 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10347 12:43:18.095473 <6>[ 0.000000] software IO TLB: area num 8.
10348 12:43:18.152288 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10349 12:43:18.301715 <6>[ 0.000000] Memory: 7949876K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 402892K reserved, 32768K cma-reserved)
10350 12:43:18.308460 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10351 12:43:18.315402 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10352 12:43:18.318361 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10353 12:43:18.324566 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10354 12:43:18.331575 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10355 12:43:18.335128 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10356 12:43:18.344948 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10357 12:43:18.351027 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10358 12:43:18.358326 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10359 12:43:18.364405 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10360 12:43:18.367523 <6>[ 0.000000] GICv3: 608 SPIs implemented
10361 12:43:18.370987 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10362 12:43:18.377147 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10363 12:43:18.381101 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10364 12:43:18.387140 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10365 12:43:18.400456 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10366 12:43:18.413324 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10367 12:43:18.420235 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10368 12:43:18.427748 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10369 12:43:18.441270 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10370 12:43:18.447689 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10371 12:43:18.454148 <6>[ 0.009187] Console: colour dummy device 80x25
10372 12:43:18.464250 <6>[ 0.013944] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10373 12:43:18.470675 <6>[ 0.024387] pid_max: default: 32768 minimum: 301
10374 12:43:18.474174 <6>[ 0.029288] LSM: Security Framework initializing
10375 12:43:18.481067 <6>[ 0.034257] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10376 12:43:18.490836 <6>[ 0.042072] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 12:43:18.501045 <6>[ 0.051478] cblist_init_generic: Setting adjustable number of callback queues.
10378 12:43:18.504292 <6>[ 0.058922] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 12:43:18.513639 <6>[ 0.065299] cblist_init_generic: Setting adjustable number of callback queues.
10380 12:43:18.520678 <6>[ 0.072754] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 12:43:18.523879 <6>[ 0.079157] rcu: Hierarchical SRCU implementation.
10382 12:43:18.530160 <6>[ 0.084204] rcu: Max phase no-delay instances is 1000.
10383 12:43:18.536973 <6>[ 0.091270] EFI services will not be available.
10384 12:43:18.540413 <6>[ 0.096230] smp: Bringing up secondary CPUs ...
10385 12:43:18.549058 <6>[ 0.101283] Detected VIPT I-cache on CPU1
10386 12:43:18.556122 <6>[ 0.101351] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10387 12:43:18.562311 <6>[ 0.101381] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10388 12:43:18.565326 <6>[ 0.101727] Detected VIPT I-cache on CPU2
10389 12:43:18.572038 <6>[ 0.101779] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10390 12:43:18.581593 <6>[ 0.101798] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10391 12:43:18.585284 <6>[ 0.102061] Detected VIPT I-cache on CPU3
10392 12:43:18.592013 <6>[ 0.102107] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10393 12:43:18.597960 <6>[ 0.102121] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10394 12:43:18.601905 <6>[ 0.102426] CPU features: detected: Spectre-v4
10395 12:43:18.608568 <6>[ 0.102432] CPU features: detected: Spectre-BHB
10396 12:43:18.611612 <6>[ 0.102437] Detected PIPT I-cache on CPU4
10397 12:43:18.618447 <6>[ 0.102492] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10398 12:43:18.624920 <6>[ 0.102509] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10399 12:43:18.631084 <6>[ 0.102797] Detected PIPT I-cache on CPU5
10400 12:43:18.638301 <6>[ 0.102859] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10401 12:43:18.644226 <6>[ 0.102875] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10402 12:43:18.647605 <6>[ 0.103158] Detected PIPT I-cache on CPU6
10403 12:43:18.655135 <6>[ 0.103221] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10404 12:43:18.664062 <6>[ 0.103238] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10405 12:43:18.667430 <6>[ 0.103537] Detected PIPT I-cache on CPU7
10406 12:43:18.674876 <6>[ 0.103599] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10407 12:43:18.680739 <6>[ 0.103616] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10408 12:43:18.684140 <6>[ 0.103664] smp: Brought up 1 node, 8 CPUs
10409 12:43:18.690856 <6>[ 0.244947] SMP: Total of 8 processors activated.
10410 12:43:18.694270 <6>[ 0.249899] CPU features: detected: 32-bit EL0 Support
10411 12:43:18.703889 <6>[ 0.255293] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10412 12:43:18.710696 <6>[ 0.264093] CPU features: detected: Common not Private translations
10413 12:43:18.717240 <6>[ 0.270568] CPU features: detected: CRC32 instructions
10414 12:43:18.724117 <6>[ 0.275919] CPU features: detected: RCpc load-acquire (LDAPR)
10415 12:43:18.727315 <6>[ 0.281879] CPU features: detected: LSE atomic instructions
10416 12:43:18.733601 <6>[ 0.287660] CPU features: detected: Privileged Access Never
10417 12:43:18.739756 <6>[ 0.293476] CPU features: detected: RAS Extension Support
10418 12:43:18.746339 <6>[ 0.299085] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10419 12:43:18.750559 <6>[ 0.306347] CPU: All CPU(s) started at EL2
10420 12:43:18.756309 <6>[ 0.310691] alternatives: applying system-wide alternatives
10421 12:43:18.766650 <6>[ 0.321401] devtmpfs: initialized
10422 12:43:18.782647 <6>[ 0.330339] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10423 12:43:18.789107 <6>[ 0.340299] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10424 12:43:18.795601 <6>[ 0.348482] pinctrl core: initialized pinctrl subsystem
10425 12:43:18.799154 <6>[ 0.355119] DMI not present or invalid.
10426 12:43:18.805552 <6>[ 0.359532] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10427 12:43:18.815171 <6>[ 0.366410] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10428 12:43:18.821896 <6>[ 0.373992] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10429 12:43:18.832333 <6>[ 0.382217] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10430 12:43:18.835700 <6>[ 0.390461] audit: initializing netlink subsys (disabled)
10431 12:43:18.844796 <5>[ 0.396155] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10432 12:43:18.851580 <6>[ 0.396855] thermal_sys: Registered thermal governor 'step_wise'
10433 12:43:18.858170 <6>[ 0.404124] thermal_sys: Registered thermal governor 'power_allocator'
10434 12:43:18.861475 <6>[ 0.410379] cpuidle: using governor menu
10435 12:43:18.868256 <6>[ 0.421338] NET: Registered PF_QIPCRTR protocol family
10436 12:43:18.874576 <6>[ 0.426820] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10437 12:43:18.880967 <6>[ 0.433924] ASID allocator initialised with 32768 entries
10438 12:43:18.884708 <6>[ 0.440465] Serial: AMBA PL011 UART driver
10439 12:43:18.894562 <4>[ 0.449219] Trying to register duplicate clock ID: 134
10440 12:43:18.948369 <6>[ 0.506604] KASLR enabled
10441 12:43:18.962737 <6>[ 0.514353] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10442 12:43:18.969928 <6>[ 0.521366] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10443 12:43:18.976041 <6>[ 0.527856] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10444 12:43:18.983091 <6>[ 0.534860] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10445 12:43:18.989394 <6>[ 0.541346] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10446 12:43:18.996113 <6>[ 0.548351] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10447 12:43:19.002332 <6>[ 0.554836] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10448 12:43:19.009026 <6>[ 0.561843] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10449 12:43:19.012299 <6>[ 0.569372] ACPI: Interpreter disabled.
10450 12:43:19.020651 <6>[ 0.575791] iommu: Default domain type: Translated
10451 12:43:19.027628 <6>[ 0.580903] iommu: DMA domain TLB invalidation policy: strict mode
10452 12:43:19.031173 <5>[ 0.587565] SCSI subsystem initialized
10453 12:43:19.037548 <6>[ 0.591733] usbcore: registered new interface driver usbfs
10454 12:43:19.044099 <6>[ 0.597464] usbcore: registered new interface driver hub
10455 12:43:19.046988 <6>[ 0.603013] usbcore: registered new device driver usb
10456 12:43:19.054120 <6>[ 0.609119] pps_core: LinuxPPS API ver. 1 registered
10457 12:43:19.064267 <6>[ 0.614313] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10458 12:43:19.067720 <6>[ 0.623662] PTP clock support registered
10459 12:43:19.070932 <6>[ 0.627907] EDAC MC: Ver: 3.0.0
10460 12:43:19.079274 <6>[ 0.633060] FPGA manager framework
10461 12:43:19.085426 <6>[ 0.636741] Advanced Linux Sound Architecture Driver Initialized.
10462 12:43:19.088052 <6>[ 0.643525] vgaarb: loaded
10463 12:43:19.094614 <6>[ 0.646676] clocksource: Switched to clocksource arch_sys_counter
10464 12:43:19.097963 <5>[ 0.653113] VFS: Disk quotas dquot_6.6.0
10465 12:43:19.105174 <6>[ 0.657293] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10466 12:43:19.108381 <6>[ 0.664483] pnp: PnP ACPI: disabled
10467 12:43:19.116942 <6>[ 0.671141] NET: Registered PF_INET protocol family
10468 12:43:19.126167 <6>[ 0.676737] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10469 12:43:19.137690 <6>[ 0.689061] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10470 12:43:19.147463 <6>[ 0.697876] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10471 12:43:19.154066 <6>[ 0.705851] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10472 12:43:19.163689 <6>[ 0.714551] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10473 12:43:19.171139 <6>[ 0.724311] TCP: Hash tables configured (established 65536 bind 65536)
10474 12:43:19.177476 <6>[ 0.731181] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10475 12:43:19.187220 <6>[ 0.738383] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 12:43:19.193398 <6>[ 0.746087] NET: Registered PF_UNIX/PF_LOCAL protocol family
10477 12:43:19.200216 <6>[ 0.752240] RPC: Registered named UNIX socket transport module.
10478 12:43:19.203536 <6>[ 0.758393] RPC: Registered udp transport module.
10479 12:43:19.210116 <6>[ 0.763324] RPC: Registered tcp transport module.
10480 12:43:19.217118 <6>[ 0.768255] RPC: Registered tcp NFSv4.1 backchannel transport module.
10481 12:43:19.219845 <6>[ 0.774920] PCI: CLS 0 bytes, default 64
10482 12:43:19.223305 <6>[ 0.779245] Unpacking initramfs...
10483 12:43:19.247627 <6>[ 0.798803] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10484 12:43:19.257489 <6>[ 0.807449] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10485 12:43:19.260646 <6>[ 0.816296] kvm [1]: IPA Size Limit: 40 bits
10486 12:43:19.266949 <6>[ 0.820822] kvm [1]: GICv3: no GICV resource entry
10487 12:43:19.270141 <6>[ 0.825844] kvm [1]: disabling GICv2 emulation
10488 12:43:19.277320 <6>[ 0.830547] kvm [1]: GIC system register CPU interface enabled
10489 12:43:19.280583 <6>[ 0.836725] kvm [1]: vgic interrupt IRQ18
10490 12:43:19.286916 <6>[ 0.841082] kvm [1]: VHE mode initialized successfully
10491 12:43:19.294073 <5>[ 0.847565] Initialise system trusted keyrings
10492 12:43:19.300027 <6>[ 0.852405] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10493 12:43:19.307842 <6>[ 0.862427] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10494 12:43:19.313975 <5>[ 0.868819] NFS: Registering the id_resolver key type
10495 12:43:19.317259 <5>[ 0.874122] Key type id_resolver registered
10496 12:43:19.324244 <5>[ 0.878537] Key type id_legacy registered
10497 12:43:19.330947 <6>[ 0.882817] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10498 12:43:19.336982 <6>[ 0.889738] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10499 12:43:19.344352 <6>[ 0.897464] 9p: Installing v9fs 9p2000 file system support
10500 12:43:19.380796 <5>[ 0.935153] Key type asymmetric registered
10501 12:43:19.384062 <5>[ 0.939485] Asymmetric key parser 'x509' registered
10502 12:43:19.393969 <6>[ 0.944630] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10503 12:43:19.396854 <6>[ 0.952250] io scheduler mq-deadline registered
10504 12:43:19.400318 <6>[ 0.957035] io scheduler kyber registered
10505 12:43:19.419667 <6>[ 0.974173] EINJ: ACPI disabled.
10506 12:43:19.452086 <4>[ 0.999962] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10507 12:43:19.462027 <4>[ 1.010602] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 12:43:19.476566 <6>[ 1.031500] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10509 12:43:19.484473 <6>[ 1.039541] printk: console [ttyS0] disabled
10510 12:43:19.512717 <6>[ 1.064182] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10511 12:43:19.519018 <6>[ 1.073662] printk: console [ttyS0] enabled
10512 12:43:19.522709 <6>[ 1.073662] printk: console [ttyS0] enabled
10513 12:43:19.529342 <6>[ 1.082558] printk: bootconsole [mtk8250] disabled
10514 12:43:19.532990 <6>[ 1.082558] printk: bootconsole [mtk8250] disabled
10515 12:43:19.539054 <6>[ 1.093686] SuperH (H)SCI(F) driver initialized
10516 12:43:19.542398 <6>[ 1.098985] msm_serial: driver initialized
10517 12:43:19.556747 <6>[ 1.107986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10518 12:43:19.566402 <6>[ 1.116534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10519 12:43:19.572900 <6>[ 1.125076] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10520 12:43:19.582866 <6>[ 1.133705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10521 12:43:19.593048 <6>[ 1.142412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10522 12:43:19.599098 <6>[ 1.151144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10523 12:43:19.609855 <6>[ 1.159686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10524 12:43:19.615594 <6>[ 1.168490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10525 12:43:19.627277 <6>[ 1.177032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10526 12:43:19.638069 <6>[ 1.192819] loop: module loaded
10527 12:43:19.644506 <6>[ 1.198853] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10528 12:43:19.667553 <4>[ 1.222377] mtk-pmic-keys: Failed to locate of_node [id: -1]
10529 12:43:19.675089 <6>[ 1.229451] megasas: 07.719.03.00-rc1
10530 12:43:19.685030 <6>[ 1.239328] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10531 12:43:19.691691 <6>[ 1.246080] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10532 12:43:19.708202 <6>[ 1.262621] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10533 12:43:19.764727 <6>[ 1.312498] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10534 12:43:19.974317 <6>[ 1.528603] Freeing initrd memory: 17376K
10535 12:43:19.984147 <6>[ 1.539038] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10536 12:43:19.995138 <6>[ 1.549987] tun: Universal TUN/TAP device driver, 1.6
10537 12:43:19.998515 <6>[ 1.556064] thunder_xcv, ver 1.0
10538 12:43:20.002488 <6>[ 1.559573] thunder_bgx, ver 1.0
10539 12:43:20.005641 <6>[ 1.563072] nicpf, ver 1.0
10540 12:43:20.015766 <6>[ 1.567098] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10541 12:43:20.019418 <6>[ 1.574574] hns3: Copyright (c) 2017 Huawei Corporation.
10542 12:43:20.025284 <6>[ 1.580164] hclge is initializing
10543 12:43:20.028978 <6>[ 1.583752] e1000: Intel(R) PRO/1000 Network Driver
10544 12:43:20.035544 <6>[ 1.588881] e1000: Copyright (c) 1999-2006 Intel Corporation.
10545 12:43:20.039445 <6>[ 1.594894] e1000e: Intel(R) PRO/1000 Network Driver
10546 12:43:20.045586 <6>[ 1.600109] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10547 12:43:20.052361 <6>[ 1.606294] igb: Intel(R) Gigabit Ethernet Network Driver
10548 12:43:20.058937 <6>[ 1.611943] igb: Copyright (c) 2007-2014 Intel Corporation.
10549 12:43:20.065761 <6>[ 1.617780] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10550 12:43:20.072185 <6>[ 1.624298] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10551 12:43:20.074881 <6>[ 1.630771] sky2: driver version 1.30
10552 12:43:20.082225 <6>[ 1.635761] VFIO - User Level meta-driver version: 0.3
10553 12:43:20.089831 <6>[ 1.643984] usbcore: registered new interface driver usb-storage
10554 12:43:20.095562 <6>[ 1.650430] usbcore: registered new device driver onboard-usb-hub
10555 12:43:20.105246 <6>[ 1.659607] mt6397-rtc mt6359-rtc: registered as rtc0
10556 12:43:20.114613 <6>[ 1.665075] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:43:24 UTC (1707137004)
10557 12:43:20.117626 <6>[ 1.674641] i2c_dev: i2c /dev entries driver
10558 12:43:20.134579 <6>[ 1.686352] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10559 12:43:20.154373 <6>[ 1.709348] cpu cpu0: EM: created perf domain
10560 12:43:20.157765 <6>[ 1.714288] cpu cpu4: EM: created perf domain
10561 12:43:20.165400 <6>[ 1.719921] sdhci: Secure Digital Host Controller Interface driver
10562 12:43:20.171573 <6>[ 1.726355] sdhci: Copyright(c) Pierre Ossman
10563 12:43:20.178695 <6>[ 1.731306] Synopsys Designware Multimedia Card Interface Driver
10564 12:43:20.184752 <6>[ 1.737933] sdhci-pltfm: SDHCI platform and OF driver helper
10565 12:43:20.188327 <6>[ 1.738063] mmc0: CQHCI version 5.10
10566 12:43:20.194985 <6>[ 1.748011] ledtrig-cpu: registered to indicate activity on CPUs
10567 12:43:20.201378 <6>[ 1.755125] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10568 12:43:20.209108 <6>[ 1.762178] usbcore: registered new interface driver usbhid
10569 12:43:20.211218 <6>[ 1.768000] usbhid: USB HID core driver
10570 12:43:20.218014 <6>[ 1.772198] spi_master spi0: will run message pump with realtime priority
10571 12:43:20.262683 <6>[ 1.810884] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10572 12:43:20.281822 <6>[ 1.826974] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10573 12:43:20.286144 <6>[ 1.840619] mmc0: Command Queue Engine enabled
10574 12:43:20.292345 <6>[ 1.845404] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10575 12:43:20.299307 <6>[ 1.852341] cros-ec-spi spi0.0: Chrome EC device registered
10576 12:43:20.302685 <6>[ 1.852730] mmcblk0: mmc0:0001 DA4128 116 GiB
10577 12:43:20.312363 <6>[ 1.866899] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10578 12:43:20.320205 <6>[ 1.874579] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10579 12:43:20.326285 <6>[ 1.880584] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10580 12:43:20.333168 <6>[ 1.886633] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10581 12:43:20.342651 <6>[ 1.891065] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10582 12:43:20.349289 <6>[ 1.903744] NET: Registered PF_PACKET protocol family
10583 12:43:20.352886 <6>[ 1.909140] 9pnet: Installing 9P2000 support
10584 12:43:20.359701 <5>[ 1.913707] Key type dns_resolver registered
10585 12:43:20.363252 <6>[ 1.918730] registered taskstats version 1
10586 12:43:20.369549 <5>[ 1.923103] Loading compiled-in X.509 certificates
10587 12:43:20.398724 <4>[ 1.946940] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 12:43:20.408482 <4>[ 1.957840] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 12:43:20.415676 <3>[ 1.968400] debugfs: File 'uA_load' in directory '/' already present!
10590 12:43:20.421936 <3>[ 1.975109] debugfs: File 'min_uV' in directory '/' already present!
10591 12:43:20.428846 <3>[ 1.981722] debugfs: File 'max_uV' in directory '/' already present!
10592 12:43:20.435778 <3>[ 1.988334] debugfs: File 'constraint_flags' in directory '/' already present!
10593 12:43:20.446826 <3>[ 1.998126] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10594 12:43:20.457959 <6>[ 2.012993] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10595 12:43:20.465444 <6>[ 2.020151] xhci-mtk 11200000.usb: xHCI Host Controller
10596 12:43:20.471622 <6>[ 2.025656] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10597 12:43:20.482523 <6>[ 2.033515] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10598 12:43:20.488589 <6>[ 2.042944] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10599 12:43:20.495731 <6>[ 2.049030] xhci-mtk 11200000.usb: xHCI Host Controller
10600 12:43:20.502769 <6>[ 2.054510] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10601 12:43:20.508414 <6>[ 2.062164] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10602 12:43:20.515501 <6>[ 2.070033] hub 1-0:1.0: USB hub found
10603 12:43:20.518572 <6>[ 2.074061] hub 1-0:1.0: 1 port detected
10604 12:43:20.526185 <6>[ 2.078354] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10605 12:43:20.532660 <6>[ 2.087159] hub 2-0:1.0: USB hub found
10606 12:43:20.536010 <6>[ 2.091188] hub 2-0:1.0: 1 port detected
10607 12:43:20.544163 <6>[ 2.098797] mtk-msdc 11f70000.mmc: Got CD GPIO
10608 12:43:20.558606 <6>[ 2.109731] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10609 12:43:20.564327 <6>[ 2.117771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10610 12:43:20.574434 <4>[ 2.125686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10611 12:43:20.584294 <6>[ 2.135253] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10612 12:43:20.591498 <6>[ 2.143329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10613 12:43:20.600492 <6>[ 2.151356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10614 12:43:20.607348 <6>[ 2.159278] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10615 12:43:20.613790 <6>[ 2.167095] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10616 12:43:20.623743 <6>[ 2.174912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10617 12:43:20.633652 <6>[ 2.185197] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10618 12:43:20.640443 <6>[ 2.193559] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10619 12:43:20.650085 <6>[ 2.201911] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10620 12:43:20.660053 <6>[ 2.210251] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10621 12:43:20.666955 <6>[ 2.218591] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10622 12:43:20.676857 <6>[ 2.226932] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10623 12:43:20.683461 <6>[ 2.235271] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10624 12:43:20.693195 <6>[ 2.243611] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10625 12:43:20.700160 <6>[ 2.251952] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10626 12:43:20.710294 <6>[ 2.260292] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10627 12:43:20.716502 <6>[ 2.268630] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10628 12:43:20.726244 <6>[ 2.276969] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10629 12:43:20.733352 <6>[ 2.285308] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10630 12:43:20.742878 <6>[ 2.293647] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10631 12:43:20.749451 <6>[ 2.301987] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10632 12:43:20.756303 <6>[ 2.310742] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10633 12:43:20.763040 <6>[ 2.317958] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10634 12:43:20.770122 <6>[ 2.324810] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10635 12:43:20.779945 <6>[ 2.331656] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10636 12:43:20.786819 <6>[ 2.338646] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10637 12:43:20.793530 <6>[ 2.345522] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10638 12:43:20.803800 <6>[ 2.354658] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10639 12:43:20.812838 <6>[ 2.363777] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10640 12:43:20.823578 <6>[ 2.373073] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10641 12:43:20.833050 <6>[ 2.382540] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10642 12:43:20.842773 <6>[ 2.392006] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10643 12:43:20.849167 <6>[ 2.401126] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10644 12:43:20.859810 <6>[ 2.410594] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10645 12:43:20.869516 <6>[ 2.419713] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10646 12:43:20.879276 <6>[ 2.429007] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10647 12:43:20.889307 <6>[ 2.439167] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10648 12:43:20.898948 <6>[ 2.450625] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10649 12:43:20.905111 <6>[ 2.460506] Trying to probe devices needed for running init ...
10650 12:43:20.947512 <6>[ 2.498981] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10651 12:43:21.102116 <6>[ 2.656995] hub 1-1:1.0: USB hub found
10652 12:43:21.104934 <6>[ 2.661519] hub 1-1:1.0: 4 ports detected
10653 12:43:21.114662 <6>[ 2.669739] hub 1-1:1.0: USB hub found
10654 12:43:21.118550 <6>[ 2.674169] hub 1-1:1.0: 4 ports detected
10655 12:43:21.227421 <6>[ 2.779331] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10656 12:43:21.253693 <6>[ 2.808756] hub 2-1:1.0: USB hub found
10657 12:43:21.257093 <6>[ 2.813261] hub 2-1:1.0: 3 ports detected
10658 12:43:21.266870 <6>[ 2.821704] hub 2-1:1.0: USB hub found
10659 12:43:21.270395 <6>[ 2.826188] hub 2-1:1.0: 3 ports detected
10660 12:43:21.443111 <6>[ 2.994982] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10661 12:43:21.575879 <6>[ 3.130919] hub 1-1.4:1.0: USB hub found
10662 12:43:21.579912 <6>[ 3.135610] hub 1-1.4:1.0: 2 ports detected
10663 12:43:21.589133 <6>[ 3.144067] hub 1-1.4:1.0: USB hub found
10664 12:43:21.592060 <6>[ 3.148665] hub 1-1.4:1.0: 2 ports detected
10665 12:43:21.655316 <6>[ 3.207166] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10666 12:43:21.891253 <6>[ 3.442999] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10667 12:43:22.083136 <6>[ 3.634985] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10668 12:43:33.208684 <6>[ 14.768042] ALSA device list:
10669 12:43:33.215247 <6>[ 14.771338] No soundcards found.
10670 12:43:33.223214 <6>[ 14.779483] Freeing unused kernel memory: 8448K
10671 12:43:33.226532 <6>[ 14.784485] Run /init as init process
10672 12:43:33.238059 Loading, please wait...
10673 12:43:33.259606 Starting version 247.3-7+deb11u2
10674 12:43:33.459969 <6>[ 15.013134] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10675 12:43:33.470969 <6>[ 15.027079] remoteproc remoteproc0: scp is available
10676 12:43:33.480792 <3>[ 15.029499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 12:43:33.487536 <6>[ 15.030772] usbcore: registered new device driver r8152-cfgselector
10678 12:43:33.490883 <6>[ 15.032390] remoteproc remoteproc0: powering up scp
10679 12:43:33.500425 <3>[ 15.041140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 12:43:33.507260 <6>[ 15.042915] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10681 12:43:33.513978 <6>[ 15.042968] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10682 12:43:33.523587 <6>[ 15.042986] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10683 12:43:33.533827 <6>[ 15.046997] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10684 12:43:33.536825 <6>[ 15.047020] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10685 12:43:33.546408 <6>[ 15.095052] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10686 12:43:33.553038 <3>[ 15.099351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:43:33.556771 <6>[ 15.108739] mc: Linux media interface: v0.10
10688 12:43:33.566616 <3>[ 15.119240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:43:33.569391 <6>[ 15.120474] Bluetooth: Core ver 2.22
10690 12:43:33.580082 <4>[ 15.125645] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10691 12:43:33.583523 <4>[ 15.125645] Fallback method does not support PEC.
10692 12:43:33.590004 <3>[ 15.127659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 12:43:33.600652 <6>[ 15.130023] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10694 12:43:33.604821 <6>[ 15.131614] NET: Registered PF_BLUETOOTH protocol family
10695 12:43:33.614348 <4>[ 15.131743] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10696 12:43:33.620535 <4>[ 15.132116] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10697 12:43:33.630883 <3>[ 15.141051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10698 12:43:33.637210 <3>[ 15.145180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 12:43:33.646864 <4>[ 15.152723] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10700 12:43:33.653844 <4>[ 15.152731] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10701 12:43:33.659912 <6>[ 15.153256] Bluetooth: HCI device and connection manager initialized
10702 12:43:33.669636 <3>[ 15.161594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 12:43:33.676756 <3>[ 15.164521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 12:43:33.683657 <6>[ 15.165493] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10705 12:43:33.690212 <6>[ 15.165502] pci_bus 0000:00: root bus resource [bus 00-ff]
10706 12:43:33.695959 <6>[ 15.165510] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10707 12:43:33.706964 <6>[ 15.165516] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10708 12:43:33.712409 <6>[ 15.165562] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10709 12:43:33.722632 <6>[ 15.165584] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10710 12:43:33.725794 <6>[ 15.165710] pci 0000:00:00.0: supports D1 D2
10711 12:43:33.732442 <6>[ 15.165716] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10712 12:43:33.738978 <6>[ 15.167208] Bluetooth: HCI socket layer initialized
10713 12:43:33.745692 <6>[ 15.168856] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10714 12:43:33.752081 <6>[ 15.169057] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10715 12:43:33.759626 <6>[ 15.169091] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10716 12:43:33.766179 <6>[ 15.169114] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10717 12:43:33.775801 <6>[ 15.169133] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10718 12:43:33.778750 <6>[ 15.169275] pci 0000:01:00.0: supports D1 D2
10719 12:43:33.785525 <6>[ 15.169279] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10720 12:43:33.792105 <6>[ 15.172410] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10721 12:43:33.801650 <3>[ 15.174453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 12:43:33.809090 <6>[ 15.178828] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10723 12:43:33.815035 <6>[ 15.178910] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10724 12:43:33.825067 <6>[ 15.178920] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10725 12:43:33.831786 <6>[ 15.178939] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10726 12:43:33.841364 <6>[ 15.178956] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10727 12:43:33.847792 <6>[ 15.178972] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10728 12:43:33.854660 <6>[ 15.178992] pci 0000:00:00.0: PCI bridge to [bus 01]
10729 12:43:33.861052 <6>[ 15.179004] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10730 12:43:33.867723 <6>[ 15.179220] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10731 12:43:33.874569 <6>[ 15.180727] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10732 12:43:33.881207 <6>[ 15.181075] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10733 12:43:33.887870 <6>[ 15.181787] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10734 12:43:33.894340 <6>[ 15.182271] Bluetooth: L2CAP socket layer initialized
10735 12:43:33.897382 <6>[ 15.182291] Bluetooth: SCO socket layer initialized
10736 12:43:33.907725 <6>[ 15.183499] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10737 12:43:33.914221 <6>[ 15.185558] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10738 12:43:33.924476 <3>[ 15.190545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 12:43:33.930974 <6>[ 15.198604] remoteproc remoteproc0: remote processor scp is now up
10740 12:43:33.933791 <6>[ 15.206954] r8152 2-1.3:1.0 eth0: v1.12.13
10741 12:43:33.940735 <6>[ 15.207002] usbcore: registered new interface driver r8152
10742 12:43:33.947063 <3>[ 15.207663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 12:43:33.956914 <6>[ 15.223603] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10744 12:43:33.967031 <3>[ 15.230380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 12:43:33.973357 <3>[ 15.230383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 12:43:33.984026 <3>[ 15.230420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 12:43:33.990497 <6>[ 15.237758] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10748 12:43:34.001135 <6>[ 15.239483] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10749 12:43:34.010363 <3>[ 15.246025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 12:43:34.016600 <3>[ 15.246027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 12:43:34.027015 <3>[ 15.246030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 12:43:34.033860 <3>[ 15.246033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 12:43:34.039685 <6>[ 15.269626] videodev: Linux video capture interface: v2.00
10754 12:43:34.046019 <3>[ 15.275160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 12:43:34.053170 <6>[ 15.275404] usbcore: registered new interface driver cdc_ether
10756 12:43:34.059939 <5>[ 15.279061] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10757 12:43:34.066164 <6>[ 15.287384] usbcore: registered new interface driver r8153_ecm
10758 12:43:34.072492 <5>[ 15.290738] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10759 12:43:34.082985 <5>[ 15.290978] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10760 12:43:34.092615 <4>[ 15.291036] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10761 12:43:34.096292 <6>[ 15.291041] cfg80211: failed to load regulatory.db
10762 12:43:34.102451 <6>[ 15.308587] usbcore: registered new interface driver btusb
10763 12:43:34.112636 <4>[ 15.309107] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10764 12:43:34.118769 <3>[ 15.309118] Bluetooth: hci0: Failed to load firmware file (-2)
10765 12:43:34.125415 <3>[ 15.309122] Bluetooth: hci0: Failed to set up firmware (-2)
10766 12:43:34.135065 <4>[ 15.309126] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10767 12:43:34.142145 <6>[ 15.329441] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10768 12:43:34.148456 <6>[ 15.337847] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10769 12:43:34.154785 <6>[ 15.355904] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10770 12:43:34.165051 <6>[ 15.365931] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10771 12:43:34.175108 <6>[ 15.375803] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10772 12:43:34.178326 <6>[ 15.378156] usbcore: registered new interface driver uvcvideo
10773 12:43:34.184555 <6>[ 15.385971] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10774 12:43:34.211529 <6>[ 15.767955] mt7921e 0000:01:00.0: ASIC revision: 79610010
10775 12:43:34.313324 <6>[ 15.866604] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10776 12:43:34.316874 <6>[ 15.866604]
10777 12:43:34.320561 Begin: Loading essential drivers ... done.
10778 12:43:34.323072 Begin: Running /scripts/init-premount ... done.
10779 12:43:34.329964 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10780 12:43:34.340325 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10781 12:43:34.343142 Device /sys/class/net/enx002432307c7b found
10782 12:43:34.343660 done.
10783 12:43:34.393943 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10784 12:43:34.586110 <6>[ 16.138860] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10785 12:43:35.252960 <6>[ 16.809238] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10786 12:43:35.429614 <6>[ 16.986323] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10787 12:43:35.608611 IP-Config: no response after 2 secs - giving up
10788 12:43:35.646043 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10789 12:43:36.377979 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10790 12:43:36.384495 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10791 12:43:36.390697 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10792 12:43:36.397800 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10793 12:43:36.404009 host : mt8192-asurada-spherion-r0-cbg-2
10794 12:43:36.410889 domain : lava-rack
10795 12:43:36.413739 rootserver: 192.168.201.1 rootpath:
10796 12:43:36.414310 filename :
10797 12:43:36.540997 done.
10798 12:43:36.549866 Begin: Running /scripts/nfs-bottom ... done.
10799 12:43:36.569002 Begin: Running /scripts/init-bottom ... done.
10800 12:43:37.817067 <6>[ 19.373993] NET: Registered PF_INET6 protocol family
10801 12:43:37.825385 <6>[ 19.381902] Segment Routing with IPv6
10802 12:43:37.827899 <6>[ 19.385853] In-situ OAM (IOAM) with IPv6
10803 12:43:37.960757 <30>[ 19.498224] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10804 12:43:37.964300 <30>[ 19.522591] systemd[1]: Detected architecture arm64.
10805 12:43:37.987550
10806 12:43:37.990543 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10807 12:43:37.991071
10808 12:43:38.009069 <30>[ 19.566102] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10809 12:43:39.064783 <30>[ 20.618332] systemd[1]: Queued start job for default target Graphical Interface.
10810 12:43:39.092561 <30>[ 20.649608] systemd[1]: Created slice system-getty.slice.
10811 12:43:39.099829 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10812 12:43:39.115941 <30>[ 20.672568] systemd[1]: Created slice system-modprobe.slice.
10813 12:43:39.122600 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10814 12:43:39.139540 <30>[ 20.696380] systemd[1]: Created slice system-serial\x2dgetty.slice.
10815 12:43:39.149303 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10816 12:43:39.163044 <30>[ 20.720193] systemd[1]: Created slice User and Session Slice.
10817 12:43:39.169904 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10818 12:43:39.190305 <30>[ 20.743883] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10819 12:43:39.200366 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10820 12:43:39.218110 <30>[ 20.771696] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10821 12:43:39.224672 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10822 12:43:39.248940 <30>[ 20.799157] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10823 12:43:39.255424 <30>[ 20.811330] systemd[1]: Reached target Local Encrypted Volumes.
10824 12:43:39.261605 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10825 12:43:39.278178 <30>[ 20.835227] systemd[1]: Reached target Paths.
10826 12:43:39.281292 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10827 12:43:39.297870 <30>[ 20.854988] systemd[1]: Reached target Remote File Systems.
10828 12:43:39.304222 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10829 12:43:39.322251 <30>[ 20.879359] systemd[1]: Reached target Slices.
10830 12:43:39.328941 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10831 12:43:39.342718 <30>[ 20.899006] systemd[1]: Reached target Swap.
10832 12:43:39.345337 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10833 12:43:39.366016 <30>[ 20.919590] systemd[1]: Listening on initctl Compatibility Named Pipe.
10834 12:43:39.372113 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10835 12:43:39.378782 <30>[ 20.936161] systemd[1]: Listening on Journal Audit Socket.
10836 12:43:39.385304 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10837 12:43:39.403750 <30>[ 20.960551] systemd[1]: Listening on Journal Socket (/dev/log).
10838 12:43:39.409902 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10839 12:43:39.426502 <30>[ 20.983612] systemd[1]: Listening on Journal Socket.
10840 12:43:39.433120 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10841 12:43:39.451081 <30>[ 21.004789] systemd[1]: Listening on Network Service Netlink Socket.
10842 12:43:39.457211 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10843 12:43:39.473802 <30>[ 21.030585] systemd[1]: Listening on udev Control Socket.
10844 12:43:39.480585 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10845 12:43:39.494671 <30>[ 21.051495] systemd[1]: Listening on udev Kernel Socket.
10846 12:43:39.501124 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10847 12:43:39.542063 <30>[ 21.099028] systemd[1]: Mounting Huge Pages File System...
10848 12:43:39.548175 Mounting [0;1;39mHuge Pages File System[0m...
10849 12:43:39.565909 <30>[ 21.123280] systemd[1]: Mounting POSIX Message Queue File System...
10850 12:43:39.573436 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10851 12:43:39.595056 <30>[ 21.152212] systemd[1]: Mounting Kernel Debug File System...
10852 12:43:39.601156 Mounting [0;1;39mKernel Debug File System[0m...
10853 12:43:39.621239 <30>[ 21.175572] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10854 12:43:39.650357 <30>[ 21.203706] systemd[1]: Starting Create list of static device nodes for the current kernel...
10855 12:43:39.656140 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10856 12:43:39.678448 <30>[ 21.235269] systemd[1]: Starting Load Kernel Module configfs...
10857 12:43:39.684487 Starting [0;1;39mLoad Kernel Module configfs[0m...
10858 12:43:39.703483 <30>[ 21.260260] systemd[1]: Starting Load Kernel Module drm...
10859 12:43:39.709591 Starting [0;1;39mLoad Kernel Module drm[0m...
10860 12:43:39.725063 <30>[ 21.282430] systemd[1]: Starting Load Kernel Module fuse...
10861 12:43:39.731943 Starting [0;1;39mLoad Kernel Module fuse[0m...
10862 12:43:39.770541 <6>[ 21.327164] fuse: init (API version 7.37)
10863 12:43:39.779849 <30>[ 21.328594] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10864 12:43:39.822747 <30>[ 21.379871] systemd[1]: Starting Journal Service...
10865 12:43:39.829499 Starting [0;1;39mJournal Service[0m...
10866 12:43:39.856106 <30>[ 21.413069] systemd[1]: Starting Load Kernel Modules...
10867 12:43:39.862389 Starting [0;1;39mLoad Kernel Modules[0m...
10868 12:43:39.885378 <30>[ 21.439892] systemd[1]: Starting Remount Root and Kernel File Systems...
10869 12:43:39.892063 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10870 12:43:39.909799 <30>[ 21.467316] systemd[1]: Starting Coldplug All udev Devices...
10871 12:43:39.916502 Starting [0;1;39mColdplug All udev Devices[0m...
10872 12:43:39.933334 <30>[ 21.491035] systemd[1]: Mounted Huge Pages File System.
10873 12:43:39.940652 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10874 12:43:39.955453 <30>[ 21.511712] systemd[1]: Mounted POSIX Message Queue File System.
10875 12:43:39.971538 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File Sy<3>[ 21.523611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:43:39.971996 stem[0m.
10877 12:43:39.985723 <30>[ 21.543255] systemd[1]: Mounted Kernel Debug File System.
10878 12:43:39.999767 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 21.554301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 12:43:40.002469 m.
10880 12:43:40.022902 <30>[ 21.576817] systemd[1]: Finished Create list of static device nodes for the current kernel.
10881 12:43:40.032484 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10882 12:43:40.044873 <3>[ 21.598633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 12:43:40.051031 <30>[ 21.608514] systemd[1]: modprobe@configfs.service: Succeeded.
10884 12:43:40.058830 <30>[ 21.616386] systemd[1]: Finished Load Kernel Module configfs.
10885 12:43:40.076208 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configf<3>[ 21.627984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 12:43:40.076730 s[0m.
10887 12:43:40.091451 <30>[ 21.647701] systemd[1]: modprobe@drm.service: Succeeded.
10888 12:43:40.098133 <30>[ 21.654019] systemd[1]: Finished Load Kernel Module drm.
10889 12:43:40.107611 <3>[ 21.657555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 12:43:40.111140 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10891 12:43:40.127738 <30>[ 21.684360] systemd[1]: modprobe@fuse.service: Succeeded.
10892 12:43:40.133933 <30>[ 21.691262] systemd[1]: Finished Load Kernel Module fuse.
10893 12:43:40.147725 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0<3>[ 21.702306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 12:43:40.151274 m.
10895 12:43:40.167452 <30>[ 21.724063] systemd[1]: Finished Load Kernel Modules.
10896 12:43:40.180313 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.732775] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:43:40.180828 l Modules[0m.
10898 12:43:40.200567 <30>[ 21.757421] systemd[1]: Finished Remount Root and Kernel File Systems.
10899 12:43:40.214153 [[0;32m OK [0m] Finished [0<3>[ 21.767189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 12:43:40.217693 ;1;39mRemount Root and Kernel File Systems[0m.
10901 12:43:40.245317 <3>[ 21.798965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:43:40.273292 <30>[ 21.830468] systemd[1]: Mounting FUSE Control File System...
10903 12:43:40.283385 <3>[ 21.831475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 12:43:40.289322 Mounting [0;1;39mFUSE Control File System[0m...
10905 12:43:40.306999 <30>[ 21.864000] systemd[1]: Mounting Kernel Configuration File System...
10906 12:43:40.313535 Mounting [0;1;39mKernel Configuration File System[0m...
10907 12:43:40.340367 <30>[ 21.894544] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10908 12:43:40.350892 <30>[ 21.903870] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10909 12:43:40.360502 <30>[ 21.917925] systemd[1]: Starting Load/Save Random Seed...
10910 12:43:40.367478 Starting [0;1;39mLoad/Save Random Seed[0m...
10911 12:43:40.387296 <30>[ 21.944619] systemd[1]: Starting Apply Kernel Variables...
10912 12:43:40.393608 Starting [0;1;39mApply Kernel Variables[0m...
10913 12:43:40.416781 <30>[ 21.974278] systemd[1]: Starting Create System Users...
10914 12:43:40.423058 Starting [0;1;39mCreate System Users[0m...
10915 12:43:40.439533 <30>[ 21.996949] systemd[1]: Started Journal Service.
10916 12:43:40.456263 <4>[ 22.000973] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10917 12:43:40.462758 <3>[ 22.017572] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10918 12:43:40.469170 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10919 12:43:40.487799 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10920 12:43:40.501954 See 'systemctl status systemd-udev-trigger.service' for details.
10921 12:43:40.518760 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10922 12:43:40.538369 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10923 12:43:40.558930 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10924 12:43:40.579805 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10925 12:43:40.599976 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10926 12:43:40.647887 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10927 12:43:40.663857 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10928 12:43:40.713391 <46>[ 22.267620] systemd-journald[297]: Received client request to flush runtime journal.
10929 12:43:41.486806 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10930 12:43:41.501931 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10931 12:43:41.517803 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10932 12:43:41.573712 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10933 12:43:42.157258 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10934 12:43:42.211018 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10935 12:43:42.291148 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10936 12:43:42.355138 Starting [0;1;39mNetwork Service[0m...
10937 12:43:42.697604 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10938 12:43:42.728300 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10939 12:43:42.773528 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10940 12:43:43.047133 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10941 12:43:43.064851 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10942 12:43:43.109963 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10943 12:43:43.135821 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10944 12:43:43.166946 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10945 12:43:43.207489 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10946 12:43:43.270282 Starting [0;1;39mNetwork Name Resolution[0m...
10947 12:43:43.296307 Starting [0;1;39mNetwork Time Synchronization[0m...
10948 12:43:43.312824 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10949 12:43:43.330219 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10950 12:43:43.371738 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10951 12:43:43.534397 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10952 12:43:43.549840 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10953 12:43:43.569511 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10954 12:43:43.581788 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10955 12:43:43.597543 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10956 12:43:43.745449 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10957 12:43:43.782202 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10958 12:43:43.813639 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10959 12:43:43.842044 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10960 12:43:43.857977 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10961 12:43:44.045947 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10962 12:43:44.057166 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10963 12:43:44.073720 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10964 12:43:44.114461 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10965 12:43:44.662260 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10966 12:43:45.017952 Starting [0;1;39mUser Login Management[0m...
10967 12:43:45.035154 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10968 12:43:45.061604 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10969 12:43:45.080431 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10970 12:43:45.098496 Starting [0;1;39mPermit User Sessions[0m...
10971 12:43:45.238654 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10972 12:43:45.289614 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10973 12:43:45.353540 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10974 12:43:45.369953 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10975 12:43:45.394170 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10976 12:43:45.418323 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10977 12:43:45.439281 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10978 12:43:45.458087 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10979 12:43:45.511040 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10980 12:43:45.564643 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10981 12:43:45.640627
10982 12:43:45.640783
10983 12:43:45.643301 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10984 12:43:45.643405
10985 12:43:45.646670 debian-bullseye-arm64 login: root (automatic login)
10986 12:43:45.646747
10987 12:43:45.646809
10988 12:43:46.071096 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
10989 12:43:46.071658
10990 12:43:46.078126 The programs included with the Debian GNU/Linux system are free software;
10991 12:43:46.084159 the exact distribution terms for each program are described in the
10992 12:43:46.087161 individual files in /usr/share/doc/*/copyright.
10993 12:43:46.087645
10994 12:43:46.094289 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10995 12:43:46.097048 permitted by applicable law.
10996 12:43:47.260162 Matched prompt #10: / #
10998 12:43:47.261552 Setting prompt string to ['/ #']
10999 12:43:47.261994 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11001 12:43:47.262980 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11002 12:43:47.263456 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
11003 12:43:47.263824 Setting prompt string to ['/ #']
11004 12:43:47.264137 Forcing a shell prompt, looking for ['/ #']
11006 12:43:47.314927 / #
11007 12:43:47.315599 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11008 12:43:47.316016 Waiting using forced prompt support (timeout 00:02:30)
11009 12:43:47.322113
11010 12:43:47.323076 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11011 12:43:47.323770 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
11013 12:43:47.425139 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj'
11014 12:43:47.432012 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703544/extract-nfsrootfs-oqzy2ekj'
11016 12:43:47.534002 / # export NFS_SERVER_IP='192.168.201.1'
11017 12:43:47.540908 export NFS_SERVER_IP='192.168.201.1'
11018 12:43:47.541864 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11019 12:43:47.542447 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
11020 12:43:47.542959 end: 2 depthcharge-action (duration 00:01:54) [common]
11021 12:43:47.543522 start: 3 lava-test-retry (timeout 00:07:24) [common]
11022 12:43:47.544025 start: 3.1 lava-test-shell (timeout 00:07:24) [common]
11023 12:43:47.544485 Using namespace: common
11025 12:43:47.645847 / # #
11026 12:43:47.646539 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11027 12:43:47.653017 #
11028 12:43:47.653909 Using /lava-12703544
11030 12:43:47.755107 / # export SHELL=/bin/bash
11031 12:43:47.762145 export SHELL=/bin/bash
11033 12:43:47.863756 / # . /lava-12703544/environment
11034 12:43:47.870189 . /lava-12703544/environment
11036 12:43:47.979504 / # /lava-12703544/bin/lava-test-runner /lava-12703544/0
11037 12:43:47.980144 Test shell timeout: 10s (minimum of the action and connection timeout)
11038 12:43:47.986228 /lava-12703544/bin/lava-test-runner /lava-12703544/0
11039 12:43:48.368099 + export TESTRUN_ID=0_timesync-off
11040 12:43:48.371058 + TESTRUN_ID=0_timesync-off
11041 12:43:48.374565 + cd /lava-12703544/0/tests/0_timesync-off
11042 12:43:48.377736 ++ cat uuid
11043 12:43:48.386722 + UUID=12703544_1.6.2.3.1
11044 12:43:48.387176 + set +x
11045 12:43:48.393003 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12703544_1.6.2.3.1>
11046 12:43:48.393706 Received signal: <STARTRUN> 0_timesync-off 12703544_1.6.2.3.1
11047 12:43:48.394080 Starting test lava.0_timesync-off (12703544_1.6.2.3.1)
11048 12:43:48.394489 Skipping test definition patterns.
11049 12:43:48.396187 + systemctl stop systemd-timesyncd
11050 12:43:48.450558 + set +x
11051 12:43:48.453590 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12703544_1.6.2.3.1>
11052 12:43:48.454275 Received signal: <ENDRUN> 0_timesync-off 12703544_1.6.2.3.1
11053 12:43:48.454689 Ending use of test pattern.
11054 12:43:48.455009 Ending test lava.0_timesync-off (12703544_1.6.2.3.1), duration 0.06
11056 12:43:48.564214 + export TESTRUN_ID=1_kselftest-tpm2
11057 12:43:48.568051 + TESTRUN_ID=1_kselftest-tpm2
11058 12:43:48.573635 + cd /lava-12703544/0/tests/1_kselftest-tpm2
11059 12:43:48.573718 ++ cat uuid
11060 12:43:48.582507 + UUID=12703544_1.6.2.3.5
11061 12:43:48.582589 + set +x
11062 12:43:48.589109 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12703544_1.6.2.3.5>
11063 12:43:48.589363 Received signal: <STARTRUN> 1_kselftest-tpm2 12703544_1.6.2.3.5
11064 12:43:48.589435 Starting test lava.1_kselftest-tpm2 (12703544_1.6.2.3.5)
11065 12:43:48.589516 Skipping test definition patterns.
11066 12:43:48.593115 + cd ./automated/linux/kselftest/
11067 12:43:48.618537 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11068 12:43:48.673557 INFO: install_deps skipped
11069 12:43:48.818703 --2024-02-05 12:43:48-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11070 12:43:48.838722 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11071 12:43:48.974124 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11072 12:43:49.107768 HTTP request sent, awaiting response... 200 OK
11073 12:43:49.110968 Length: 2966020 (2.8M) [application/octet-stream]
11074 12:43:49.114237 Saving to: 'kselftest.tar.xz'
11075 12:43:49.114316
11076 12:43:49.114380
11077 12:43:49.378064 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11078 12:43:49.646082 kselftest.tar.xz 1%[ ] 47.81K 178KB/s
11079 12:43:50.093750 kselftest.tar.xz 7%[> ] 217.50K 406KB/s
11080 12:43:50.330308 kselftest.tar.xz 28%[====> ] 815.64K 829KB/s
11081 12:43:50.464753 kselftest.tar.xz 67%[============> ] 1.91M 1.57MB/s
11082 12:43:50.470889 kselftest.tar.xz 100%[===================>] 2.83M 2.09MB/s in 1.4s
11083 12:43:50.471329
11084 12:43:50.730469 2024-02-05 12:43:50 (2.09 MB/s) - 'kselftest.tar.xz' saved [2966020/2966020]
11085 12:43:50.731059
11086 12:43:57.862874 skiplist:
11087 12:43:57.865905 ========================================
11088 12:43:57.868909 ========================================
11089 12:43:57.930982 tpm2:test_smoke.sh
11090 12:43:57.933920 tpm2:test_space.sh
11091 12:43:57.954693 ============== Tests to run ===============
11092 12:43:57.958023 tpm2:test_smoke.sh
11093 12:43:57.958424 tpm2:test_space.sh
11094 12:43:57.964926 ===========End Tests to run ===============
11095 12:43:57.968165 shardfile-tpm2 pass
11096 12:43:58.100503 <12>[ 39.659764] kselftest: Running tests in tpm2
11097 12:43:58.112664 TAP version 13
11098 12:43:58.127906 1..2
11099 12:43:58.170152 # selftests: tpm2: test_smoke.sh
11100 12:43:59.783414 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11101 12:43:59.786684 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11102 12:43:59.793252 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11103 12:43:59.796478 # Traceback (most recent call last):
11104 12:43:59.806490 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11105 12:43:59.809856 # if self.tpm:
11106 12:43:59.813113 # AttributeError: 'Client' object has no attribute 'tpm'
11107 12:43:59.817131 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11108 12:43:59.823441 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11109 12:43:59.827048 # Traceback (most recent call last):
11110 12:43:59.836510 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11111 12:43:59.839469 # if self.tpm:
11112 12:43:59.843167 # AttributeError: 'Client' object has no attribute 'tpm'
11113 12:43:59.849779 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11114 12:43:59.856333 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11115 12:43:59.859255 # Traceback (most recent call last):
11116 12:43:59.869647 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11117 12:43:59.870075 # if self.tpm:
11118 12:43:59.876458 # AttributeError: 'Client' object has no attribute 'tpm'
11119 12:43:59.879759 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11120 12:43:59.886574 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11121 12:43:59.889441 # Traceback (most recent call last):
11122 12:43:59.900216 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11123 12:43:59.902183 # if self.tpm:
11124 12:43:59.905922 # AttributeError: 'Client' object has no attribute 'tpm'
11125 12:43:59.912960 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11126 12:43:59.915988 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11127 12:43:59.919191 # Traceback (most recent call last):
11128 12:43:59.928781 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11129 12:43:59.932294 # if self.tpm:
11130 12:43:59.935301 # AttributeError: 'Client' object has no attribute 'tpm'
11131 12:43:59.942520 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11132 12:43:59.949230 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11133 12:43:59.952017 # Traceback (most recent call last):
11134 12:43:59.962192 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11135 12:43:59.962614 # if self.tpm:
11136 12:43:59.968938 # AttributeError: 'Client' object has no attribute 'tpm'
11137 12:43:59.972282 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11138 12:43:59.978402 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11139 12:43:59.981767 # Traceback (most recent call last):
11140 12:43:59.991860 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11141 12:43:59.995245 # if self.tpm:
11142 12:43:59.998503 # AttributeError: 'Client' object has no attribute 'tpm'
11143 12:44:00.005325 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11144 12:44:00.011897 # Exception ignored in: <function Client.__del__ at 0xffff904acd30>
11145 12:44:00.015294 # Traceback (most recent call last):
11146 12:44:00.024817 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11147 12:44:00.025254 # if self.tpm:
11148 12:44:00.031663 # AttributeError: 'Client' object has no attribute 'tpm'
11149 12:44:00.032107 #
11150 12:44:00.038357 # ======================================================================
11151 12:44:00.041647 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11152 12:44:00.048080 # ----------------------------------------------------------------------
11153 12:44:00.051161 # Traceback (most recent call last):
11154 12:44:00.061107 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11155 12:44:00.068054 # self.root_key = self.client.create_root_key()
11156 12:44:00.078472 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11157 12:44:00.084117 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11158 12:44:00.094257 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11159 12:44:00.097685 # raise ProtocolError(cc, rc)
11160 12:44:00.100718 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11161 12:44:00.104409 #
11162 12:44:00.107521 # ======================================================================
11163 12:44:00.114521 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11164 12:44:00.120914 # ----------------------------------------------------------------------
11165 12:44:00.123774 # Traceback (most recent call last):
11166 12:44:00.134048 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11167 12:44:00.137387 # self.client = tpm2.Client()
11168 12:44:00.145559 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11169 12:44:00.152071 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11170 12:44:00.155664 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11171 12:44:00.156084 #
11172 12:44:00.162330 # ======================================================================
11173 12:44:00.169114 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11174 12:44:00.175323 # ----------------------------------------------------------------------
11175 12:44:00.179420 # Traceback (most recent call last):
11176 12:44:00.188602 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11177 12:44:00.192101 # self.client = tpm2.Client()
11178 12:44:00.202470 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11179 12:44:00.205716 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11180 12:44:00.212038 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11181 12:44:00.212485 #
11182 12:44:00.218629 # ======================================================================
11183 12:44:00.221763 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11184 12:44:00.228327 # ----------------------------------------------------------------------
11185 12:44:00.231529 # Traceback (most recent call last):
11186 12:44:00.241534 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11187 12:44:00.244807 # self.client = tpm2.Client()
11188 12:44:00.254658 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11189 12:44:00.261421 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11190 12:44:00.264961 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11191 12:44:00.265499 #
11192 12:44:00.271665 # ======================================================================
11193 12:44:00.277710 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11194 12:44:00.285096 # ----------------------------------------------------------------------
11195 12:44:00.288093 # Traceback (most recent call last):
11196 12:44:00.297726 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11197 12:44:00.300846 # self.client = tpm2.Client()
11198 12:44:00.311007 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11199 12:44:00.314345 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11200 12:44:00.321022 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11201 12:44:00.321446 #
11202 12:44:00.327464 # ======================================================================
11203 12:44:00.330927 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11204 12:44:00.337611 # ----------------------------------------------------------------------
11205 12:44:00.341121 # Traceback (most recent call last):
11206 12:44:00.350976 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11207 12:44:00.354103 # self.client = tpm2.Client()
11208 12:44:00.364161 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11209 12:44:00.367307 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11210 12:44:00.374712 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11211 12:44:00.375174 #
11212 12:44:00.380458 # ======================================================================
11213 12:44:00.384205 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11214 12:44:00.390888 # ----------------------------------------------------------------------
11215 12:44:00.393798 # Traceback (most recent call last):
11216 12:44:00.403754 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11217 12:44:00.406938 # self.client = tpm2.Client()
11218 12:44:00.416968 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11219 12:44:00.423467 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11220 12:44:00.427148 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11221 12:44:00.430209 #
11222 12:44:00.433264 # ======================================================================
11223 12:44:00.440023 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11224 12:44:00.446722 # ----------------------------------------------------------------------
11225 12:44:00.450240 # Traceback (most recent call last):
11226 12:44:00.459546 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11227 12:44:00.463422 # self.client = tpm2.Client()
11228 12:44:00.473131 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11229 12:44:00.476190 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11230 12:44:00.482924 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11231 12:44:00.483354 #
11232 12:44:00.489494 # ======================================================================
11233 12:44:00.496553 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11234 12:44:00.502576 # ----------------------------------------------------------------------
11235 12:44:00.506182 # Traceback (most recent call last):
11236 12:44:00.515998 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11237 12:44:00.519065 # self.client = tpm2.Client()
11238 12:44:00.528969 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11239 12:44:00.532316 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11240 12:44:00.539223 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11241 12:44:00.539692 #
11242 12:44:00.545108 # ----------------------------------------------------------------------
11243 12:44:00.547971 # Ran 9 tests in 0.052s
11244 12:44:00.548400 #
11245 12:44:00.548739 # FAILED (errors=9)
11246 12:44:00.551464 # test_async (tpm2_tests.AsyncTest) ... ok
11247 12:44:00.559245 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11248 12:44:00.559717 #
11249 12:44:00.568717 # ----------------------------------------------------------------------
11250 12:44:00.569143 # Ran 2 tests in 0.043s
11251 12:44:00.569478 #
11252 12:44:00.569791 # OK
11253 12:44:00.572553 ok 1 selftests: tpm2: test_smoke.sh
11254 12:44:00.576001 # selftests: tpm2: test_space.sh
11255 12:44:00.579751 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11256 12:44:00.582879 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11257 12:44:00.595047 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11258 12:44:00.616991 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11259 12:44:00.617418 #
11260 12:44:00.623940 # ======================================================================
11261 12:44:00.630830 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11262 12:44:00.637011 # ----------------------------------------------------------------------
11263 12:44:00.640152 # Traceback (most recent call last):
11264 12:44:00.650545 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11265 12:44:00.653749 # root1 = space1.create_root_key()
11266 12:44:00.663796 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11267 12:44:00.670635 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11268 12:44:00.680108 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11269 12:44:00.683310 # raise ProtocolError(cc, rc)
11270 12:44:00.690007 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11271 12:44:00.690432 #
11272 12:44:00.696528 # ======================================================================
11273 12:44:00.700331 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11274 12:44:00.707995 # ----------------------------------------------------------------------
11275 12:44:00.710196 # Traceback (most recent call last):
11276 12:44:00.720046 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11277 12:44:00.723215 # space1.create_root_key()
11278 12:44:00.733329 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11279 12:44:00.739745 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11280 12:44:00.749603 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11281 12:44:00.753408 # raise ProtocolError(cc, rc)
11282 12:44:00.759845 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11283 12:44:00.760263 #
11284 12:44:00.766694 # ======================================================================
11285 12:44:00.769634 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11286 12:44:00.776466 # ----------------------------------------------------------------------
11287 12:44:00.780318 # Traceback (most recent call last):
11288 12:44:00.789906 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11289 12:44:00.793133 # root1 = space1.create_root_key()
11290 12:44:00.806267 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11291 12:44:00.809633 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11292 12:44:00.819038 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11293 12:44:00.822865 # raise ProtocolError(cc, rc)
11294 12:44:00.830050 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11295 12:44:00.830472 #
11296 12:44:00.835640 # ======================================================================
11297 12:44:00.838754 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11298 12:44:00.846118 # ----------------------------------------------------------------------
11299 12:44:00.849179 # Traceback (most recent call last):
11300 12:44:00.862819 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11301 12:44:00.865899 # root1 = space1.create_root_key()
11302 12:44:00.875602 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11303 12:44:00.881955 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11304 12:44:00.892131 # File "/lava-12703544/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11305 12:44:00.895917 # raise ProtocolError(cc, rc)
11306 12:44:00.899907 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11307 12:44:00.900338 #
11308 12:44:00.905555 # ----------------------------------------------------------------------
11309 12:44:00.908826 # Ran 4 tests in 0.090s
11310 12:44:00.909257 #
11311 12:44:00.912769 # FAILED (errors=4)
11312 12:44:00.915650 not ok 2 selftests: tpm2: test_space.sh # exit=1
11313 12:44:00.918916 tpm2_test_smoke_sh pass
11314 12:44:00.919000 tpm2_test_space_sh fail
11315 12:44:00.925348 + ../../utils/send-to-lava.sh ./output/result.txt
11316 12:44:00.961843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11317 12:44:00.962150 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11319 12:44:01.032761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11320 12:44:01.033501 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11322 12:44:01.098157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11323 12:44:01.099031 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11325 12:44:01.101670 + set +x
11326 12:44:01.104846 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12703544_1.6.2.3.5>
11327 12:44:01.105530 Received signal: <ENDRUN> 1_kselftest-tpm2 12703544_1.6.2.3.5
11328 12:44:01.105905 Ending use of test pattern.
11329 12:44:01.106226 Ending test lava.1_kselftest-tpm2 (12703544_1.6.2.3.5), duration 12.52
11331 12:44:01.108359 <LAVA_TEST_RUNNER EXIT>
11332 12:44:01.109036 ok: lava_test_shell seems to have completed
11333 12:44:01.109574 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11334 12:44:01.109983 end: 3.1 lava-test-shell (duration 00:00:14) [common]
11335 12:44:01.110406 end: 3 lava-test-retry (duration 00:00:14) [common]
11336 12:44:01.110839 start: 4 finalize (timeout 00:07:11) [common]
11337 12:44:01.111286 start: 4.1 power-off (timeout 00:00:30) [common]
11338 12:44:01.112126 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11339 12:44:01.229292 >> Command sent successfully.
11340 12:44:01.233271 Returned 0 in 0 seconds
11341 12:44:01.334171 end: 4.1 power-off (duration 00:00:00) [common]
11343 12:44:01.335883 start: 4.2 read-feedback (timeout 00:07:11) [common]
11344 12:44:01.337362 Listened to connection for namespace 'common' for up to 1s
11345 12:44:02.337884 Finalising connection for namespace 'common'
11346 12:44:02.338560 Disconnecting from shell: Finalise
11347 12:44:02.339007 / #
11348 12:44:02.439941 end: 4.2 read-feedback (duration 00:00:01) [common]
11349 12:44:02.440731 end: 4 finalize (duration 00:00:01) [common]
11350 12:44:02.441531 Cleaning after the job
11351 12:44:02.442045 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/ramdisk
11352 12:44:02.455055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/kernel
11353 12:44:02.484546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/dtb
11354 12:44:02.484819 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/nfsrootfs
11355 12:44:02.577013 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703544/tftp-deploy-ezbae8ku/modules
11356 12:44:02.584307 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703544
11357 12:44:03.232681 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703544
11358 12:44:03.232865 Job finished correctly