Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 17
- Kernel Errors: 34
1 12:37:18.849287 lava-dispatcher, installed at version: 2024.01
2 12:37:18.849504 start: 0 validate
3 12:37:18.849633 Start time: 2024-02-05 12:37:18.849625+00:00 (UTC)
4 12:37:18.849755 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:37:18.849892 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:37:19.124340 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:37:19.125086 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:37:36.399233 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:37:36.399472 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:37:36.666530 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:37:36.667281 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:37:42.930639 validate duration: 24.08
14 12:37:42.930962 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:37:42.931092 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:37:42.931208 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:37:42.931372 Not decompressing ramdisk as can be used compressed.
18 12:37:42.931474 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:37:42.931552 saving as /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/ramdisk/rootfs.cpio.gz
20 12:37:42.931633 total size: 26246609 (25 MB)
21 12:37:43.203437 progress 0 % (0 MB)
22 12:37:43.214781 progress 5 % (1 MB)
23 12:37:43.225828 progress 10 % (2 MB)
24 12:37:43.236769 progress 15 % (3 MB)
25 12:37:43.247692 progress 20 % (5 MB)
26 12:37:43.255472 progress 25 % (6 MB)
27 12:37:43.262187 progress 30 % (7 MB)
28 12:37:43.268974 progress 35 % (8 MB)
29 12:37:43.275774 progress 40 % (10 MB)
30 12:37:43.282496 progress 45 % (11 MB)
31 12:37:43.289137 progress 50 % (12 MB)
32 12:37:43.295920 progress 55 % (13 MB)
33 12:37:43.302719 progress 60 % (15 MB)
34 12:37:43.309488 progress 65 % (16 MB)
35 12:37:43.316207 progress 70 % (17 MB)
36 12:37:43.323166 progress 75 % (18 MB)
37 12:37:43.329874 progress 80 % (20 MB)
38 12:37:43.336507 progress 85 % (21 MB)
39 12:37:43.343010 progress 90 % (22 MB)
40 12:37:43.349546 progress 95 % (23 MB)
41 12:37:43.356126 progress 100 % (25 MB)
42 12:37:43.356409 25 MB downloaded in 0.42 s (58.93 MB/s)
43 12:37:43.356580 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:37:43.356832 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:37:43.356921 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:37:43.357007 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:37:43.357141 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:37:43.357211 saving as /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/kernel/Image
50 12:37:43.357273 total size: 51534336 (49 MB)
51 12:37:43.357335 No compression specified
52 12:37:43.358592 progress 0 % (0 MB)
53 12:37:43.371944 progress 5 % (2 MB)
54 12:37:43.385078 progress 10 % (4 MB)
55 12:37:43.398114 progress 15 % (7 MB)
56 12:37:43.411282 progress 20 % (9 MB)
57 12:37:43.424492 progress 25 % (12 MB)
58 12:37:43.437504 progress 30 % (14 MB)
59 12:37:43.450595 progress 35 % (17 MB)
60 12:37:43.463690 progress 40 % (19 MB)
61 12:37:43.476530 progress 45 % (22 MB)
62 12:37:43.489550 progress 50 % (24 MB)
63 12:37:43.502560 progress 55 % (27 MB)
64 12:37:43.515668 progress 60 % (29 MB)
65 12:37:43.528850 progress 65 % (31 MB)
66 12:37:43.541769 progress 70 % (34 MB)
67 12:37:43.554854 progress 75 % (36 MB)
68 12:37:43.567959 progress 80 % (39 MB)
69 12:37:43.580875 progress 85 % (41 MB)
70 12:37:43.593804 progress 90 % (44 MB)
71 12:37:43.606744 progress 95 % (46 MB)
72 12:37:43.619547 progress 100 % (49 MB)
73 12:37:43.619796 49 MB downloaded in 0.26 s (187.21 MB/s)
74 12:37:43.619955 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:37:43.620190 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:37:43.620284 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:37:43.620371 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:37:43.620510 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:37:43.620584 saving as /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/dtb/mt8192-asurada-spherion-r0.dtb
81 12:37:43.620647 total size: 47278 (0 MB)
82 12:37:43.620710 No compression specified
83 12:37:43.621830 progress 69 % (0 MB)
84 12:37:43.622137 progress 100 % (0 MB)
85 12:37:43.622294 0 MB downloaded in 0.00 s (27.42 MB/s)
86 12:37:43.622417 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:37:43.622644 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:37:43.622730 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:37:43.622813 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:37:43.622922 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:37:43.622991 saving as /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/modules/modules.tar
93 12:37:43.623053 total size: 8639964 (8 MB)
94 12:37:43.623115 Using unxz to decompress xz
95 12:37:43.626870 progress 0 % (0 MB)
96 12:37:43.649098 progress 5 % (0 MB)
97 12:37:43.675793 progress 10 % (0 MB)
98 12:37:43.700240 progress 15 % (1 MB)
99 12:37:43.724252 progress 20 % (1 MB)
100 12:37:43.749096 progress 25 % (2 MB)
101 12:37:43.776928 progress 30 % (2 MB)
102 12:37:43.801479 progress 35 % (2 MB)
103 12:37:43.825171 progress 40 % (3 MB)
104 12:37:43.850085 progress 45 % (3 MB)
105 12:37:43.875728 progress 50 % (4 MB)
106 12:37:43.901758 progress 55 % (4 MB)
107 12:37:43.926711 progress 60 % (4 MB)
108 12:37:43.952558 progress 65 % (5 MB)
109 12:37:43.977936 progress 70 % (5 MB)
110 12:37:44.001382 progress 75 % (6 MB)
111 12:37:44.028362 progress 80 % (6 MB)
112 12:37:44.056287 progress 85 % (7 MB)
113 12:37:44.081444 progress 90 % (7 MB)
114 12:37:44.110833 progress 95 % (7 MB)
115 12:37:44.138236 progress 100 % (8 MB)
116 12:37:44.144163 8 MB downloaded in 0.52 s (15.81 MB/s)
117 12:37:44.144414 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:37:44.144687 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:37:44.144781 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:37:44.144877 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:37:44.144960 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:37:44.145050 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:37:44.145281 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn
125 12:37:44.145409 makedir: /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin
126 12:37:44.145512 makedir: /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/tests
127 12:37:44.145633 makedir: /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/results
128 12:37:44.145786 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-add-keys
129 12:37:44.145995 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-add-sources
130 12:37:44.146141 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-background-process-start
131 12:37:44.146271 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-background-process-stop
132 12:37:44.146394 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-common-functions
133 12:37:44.146516 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-echo-ipv4
134 12:37:44.146643 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-install-packages
135 12:37:44.146767 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-installed-packages
136 12:37:44.146889 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-os-build
137 12:37:44.147012 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-probe-channel
138 12:37:44.147136 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-probe-ip
139 12:37:44.147265 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-target-ip
140 12:37:44.147386 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-target-mac
141 12:37:44.147507 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-target-storage
142 12:37:44.147631 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-case
143 12:37:44.147780 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-event
144 12:37:44.147942 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-feedback
145 12:37:44.148066 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-raise
146 12:37:44.148186 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-reference
147 12:37:44.148316 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-runner
148 12:37:44.148437 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-set
149 12:37:44.148561 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-test-shell
150 12:37:44.148687 Updating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-install-packages (oe)
151 12:37:44.148837 Updating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/bin/lava-installed-packages (oe)
152 12:37:44.148981 Creating /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/environment
153 12:37:44.149082 LAVA metadata
154 12:37:44.149160 - LAVA_JOB_ID=12703509
155 12:37:44.149241 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:37:44.149348 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:37:44.149417 skipped lava-vland-overlay
158 12:37:44.149491 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:37:44.149580 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:37:44.149645 skipped lava-multinode-overlay
161 12:37:44.149718 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:37:44.149803 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:37:44.149877 Loading test definitions
164 12:37:44.150009 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:37:44.150086 Using /lava-12703509 at stage 0
166 12:37:44.150457 uuid=12703509_1.5.2.3.1 testdef=None
167 12:37:44.150547 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:37:44.150640 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:37:44.151162 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:37:44.151388 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:37:44.152027 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:37:44.152358 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:37:44.152977 runner path: /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12703509_1.5.2.3.1
176 12:37:44.153136 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:37:44.153347 Creating lava-test-runner.conf files
179 12:37:44.153411 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703509/lava-overlay-21_nwlxn/lava-12703509/0 for stage 0
180 12:37:44.153499 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:37:44.153597 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:37:44.153684 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:37:44.161771 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:37:44.161918 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:37:44.162061 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:37:44.162150 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:37:44.162251 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:37:44.838631 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:37:44.838998 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:37:44.839113 extracting modules file /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703509/extract-overlay-ramdisk-5p_ofg2p/ramdisk
191 12:37:45.052572 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:37:45.052759 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:37:45.052858 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703509/compress-overlay-glpx7qi5/overlay-1.5.2.4.tar.gz to ramdisk
194 12:37:45.052931 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703509/compress-overlay-glpx7qi5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703509/extract-overlay-ramdisk-5p_ofg2p/ramdisk
195 12:37:45.059664 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:37:45.059837 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:37:45.059958 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:37:45.060082 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:37:45.060197 Building ramdisk /var/lib/lava/dispatcher/tmp/12703509/extract-overlay-ramdisk-5p_ofg2p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703509/extract-overlay-ramdisk-5p_ofg2p/ramdisk
200 12:37:45.629152 >> 228459 blocks
201 12:37:49.694228 rename /var/lib/lava/dispatcher/tmp/12703509/extract-overlay-ramdisk-5p_ofg2p/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/ramdisk/ramdisk.cpio.gz
202 12:37:49.694688 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:37:49.694863 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:37:49.695014 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:37:49.695172 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/kernel/Image'
206 12:38:02.893504 Returned 0 in 13 seconds
207 12:38:02.994118 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/kernel/image.itb
208 12:38:03.584263 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:38:03.584628 output: Created: Mon Feb 5 12:38:03 2024
210 12:38:03.584709 output: Image 0 (kernel-1)
211 12:38:03.584772 output: Description:
212 12:38:03.584832 output: Created: Mon Feb 5 12:38:03 2024
213 12:38:03.584895 output: Type: Kernel Image
214 12:38:03.584954 output: Compression: lzma compressed
215 12:38:03.585010 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
216 12:38:03.585066 output: Architecture: AArch64
217 12:38:03.585123 output: OS: Linux
218 12:38:03.585181 output: Load Address: 0x00000000
219 12:38:03.585238 output: Entry Point: 0x00000000
220 12:38:03.585296 output: Hash algo: crc32
221 12:38:03.585352 output: Hash value: 8a14336a
222 12:38:03.585408 output: Image 1 (fdt-1)
223 12:38:03.585464 output: Description: mt8192-asurada-spherion-r0
224 12:38:03.585519 output: Created: Mon Feb 5 12:38:03 2024
225 12:38:03.585573 output: Type: Flat Device Tree
226 12:38:03.585626 output: Compression: uncompressed
227 12:38:03.585679 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:38:03.585732 output: Architecture: AArch64
229 12:38:03.585785 output: Hash algo: crc32
230 12:38:03.585837 output: Hash value: cc4352de
231 12:38:03.585890 output: Image 2 (ramdisk-1)
232 12:38:03.585948 output: Description: unavailable
233 12:38:03.586003 output: Created: Mon Feb 5 12:38:03 2024
234 12:38:03.586056 output: Type: RAMDisk Image
235 12:38:03.586108 output: Compression: Unknown Compression
236 12:38:03.586161 output: Data Size: 39375356 Bytes = 38452.50 KiB = 37.55 MiB
237 12:38:03.586214 output: Architecture: AArch64
238 12:38:03.586266 output: OS: Linux
239 12:38:03.586318 output: Load Address: unavailable
240 12:38:03.586375 output: Entry Point: unavailable
241 12:38:03.586444 output: Hash algo: crc32
242 12:38:03.586496 output: Hash value: 7c4f4813
243 12:38:03.586549 output: Default Configuration: 'conf-1'
244 12:38:03.586601 output: Configuration 0 (conf-1)
245 12:38:03.586653 output: Description: mt8192-asurada-spherion-r0
246 12:38:03.586705 output: Kernel: kernel-1
247 12:38:03.586758 output: Init Ramdisk: ramdisk-1
248 12:38:03.586810 output: FDT: fdt-1
249 12:38:03.586862 output: Loadables: kernel-1
250 12:38:03.586915 output:
251 12:38:03.587103 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:38:03.587198 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:38:03.587301 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 12:38:03.587397 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:38:03.587473 No LXC device requested
256 12:38:03.587550 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:38:03.587635 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:38:03.587715 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:38:03.587785 Checking files for TFTP limit of 4294967296 bytes.
260 12:38:03.588263 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:38:03.588372 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:38:03.588482 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:38:03.588607 substitutions:
264 12:38:03.588674 - {DTB}: 12703509/tftp-deploy-5m3tmryu/dtb/mt8192-asurada-spherion-r0.dtb
265 12:38:03.588740 - {INITRD}: 12703509/tftp-deploy-5m3tmryu/ramdisk/ramdisk.cpio.gz
266 12:38:03.588800 - {KERNEL}: 12703509/tftp-deploy-5m3tmryu/kernel/Image
267 12:38:03.588859 - {LAVA_MAC}: None
268 12:38:03.588917 - {PRESEED_CONFIG}: None
269 12:38:03.588973 - {PRESEED_LOCAL}: None
270 12:38:03.589028 - {RAMDISK}: 12703509/tftp-deploy-5m3tmryu/ramdisk/ramdisk.cpio.gz
271 12:38:03.589084 - {ROOT_PART}: None
272 12:38:03.589139 - {ROOT}: None
273 12:38:03.589196 - {SERVER_IP}: 192.168.201.1
274 12:38:03.589250 - {TEE}: None
275 12:38:03.589306 Parsed boot commands:
276 12:38:03.589362 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:38:03.589533 Parsed boot commands: tftpboot 192.168.201.1 12703509/tftp-deploy-5m3tmryu/kernel/image.itb 12703509/tftp-deploy-5m3tmryu/kernel/cmdline
278 12:38:03.589621 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:38:03.589707 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:38:03.589799 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:38:03.589882 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:38:03.589957 Not connected, no need to disconnect.
283 12:38:03.590072 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:38:03.590153 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:38:03.590220 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 12:38:03.593645 Setting prompt string to ['lava-test: # ']
287 12:38:03.594024 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:38:03.594166 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:38:03.594314 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:38:03.594434 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:38:03.594683 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 12:38:08.724364 >> Command sent successfully.
293 12:38:08.726830 Returned 0 in 5 seconds
294 12:38:08.827225 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:38:08.827555 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:38:08.827657 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:38:08.827744 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:38:08.827810 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:38:08.827881 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:38:08.828143 [Enter `^Ec?' for help]
302 12:38:09.001588
303 12:38:09.001741
304 12:38:09.001815 F0: 102B 0000
305 12:38:09.001879
306 12:38:09.001949 F3: 1001 0000 [0200]
307 12:38:09.002046
308 12:38:09.005197 F3: 1001 0000
309 12:38:09.005283
310 12:38:09.005350 F7: 102D 0000
311 12:38:09.005411
312 12:38:09.005470 F1: 0000 0000
313 12:38:09.005529
314 12:38:09.008868 V0: 0000 0000 [0001]
315 12:38:09.008957
316 12:38:09.009032 00: 0007 8000
317 12:38:09.009097
318 12:38:09.012791 01: 0000 0000
319 12:38:09.012877
320 12:38:09.012948 BP: 0C00 0209 [0000]
321 12:38:09.013015
322 12:38:09.013076 G0: 1182 0000
323 12:38:09.016565
324 12:38:09.016649 EC: 0000 0021 [4000]
325 12:38:09.016715
326 12:38:09.020405 S7: 0000 0000 [0000]
327 12:38:09.020489
328 12:38:09.020556 CC: 0000 0000 [0001]
329 12:38:09.020620
330 12:38:09.023884 T0: 0000 0040 [010F]
331 12:38:09.023971
332 12:38:09.024039 Jump to BL
333 12:38:09.024101
334 12:38:09.048423
335 12:38:09.048510
336 12:38:09.048578
337 12:38:09.055910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:38:09.059729 ARM64: Exception handlers installed.
339 12:38:09.063478 ARM64: Testing exception
340 12:38:09.063564 ARM64: Done test exception
341 12:38:09.070798 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:38:09.082311 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:38:09.089445 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:38:09.099626 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:38:09.106212 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:38:09.112985 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:38:09.125064 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:38:09.131417 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:38:09.150938 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:38:09.154194 WDT: Last reset was cold boot
351 12:38:09.157799 SPI1(PAD0) initialized at 2873684 Hz
352 12:38:09.161212 SPI5(PAD0) initialized at 992727 Hz
353 12:38:09.164592 VBOOT: Loading verstage.
354 12:38:09.171202 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:38:09.174323 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:38:09.177969 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:38:09.181076 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:38:09.188328 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:38:09.195027 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:38:09.206085 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:38:09.206170
362 12:38:09.206237
363 12:38:09.215777 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:38:09.219366 ARM64: Exception handlers installed.
365 12:38:09.222762 ARM64: Testing exception
366 12:38:09.222848 ARM64: Done test exception
367 12:38:09.229573 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:38:09.232762 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:38:09.247174 Probing TPM: . done!
370 12:38:09.247262 TPM ready after 0 ms
371 12:38:09.254177 Connected to device vid:did:rid of 1ae0:0028:00
372 12:38:09.260711 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:38:09.317370 Initialized TPM device CR50 revision 0
374 12:38:09.329245 tlcl_send_startup: Startup return code is 0
375 12:38:09.329333 TPM: setup succeeded
376 12:38:09.340360 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:38:09.349258 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:38:09.359703 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:38:09.368565 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:38:09.372117 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:38:09.380672 in-header: 03 07 00 00 08 00 00 00
382 12:38:09.384247 in-data: aa e4 47 04 13 02 00 00
383 12:38:09.387983 Chrome EC: UHEPI supported
384 12:38:09.395530 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:38:09.399091 in-header: 03 ad 00 00 08 00 00 00
386 12:38:09.403006 in-data: 00 20 20 08 00 00 00 00
387 12:38:09.403092 Phase 1
388 12:38:09.406463 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:38:09.413838 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:38:09.418216 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:38:09.421500 Recovery requested (1009000e)
392 12:38:09.429894 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:38:09.435163 tlcl_extend: response is 0
394 12:38:09.444672 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:38:09.450300 tlcl_extend: response is 0
396 12:38:09.457036 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:38:09.477310 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:38:09.484399 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:38:09.484487
400 12:38:09.484574
401 12:38:09.494371 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:38:09.497917 ARM64: Exception handlers installed.
403 12:38:09.498011 ARM64: Testing exception
404 12:38:09.500978 ARM64: Done test exception
405 12:38:09.523093 pmic_efuse_setting: Set efuses in 11 msecs
406 12:38:09.526334 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:38:09.533072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:38:09.536939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:38:09.540577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:38:09.547042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:38:09.550189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:38:09.558302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:38:09.562092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:38:09.565312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:38:09.569043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:38:09.576244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:38:09.580279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:38:09.584138 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:38:09.587574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:38:09.593895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:38:09.600971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:38:09.608138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:38:09.611540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:38:09.618984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:38:09.623221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:38:09.629561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:38:09.633357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:38:09.640488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:38:09.647296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:38:09.650424 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:38:09.657147 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:38:09.663716 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:38:09.666994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:38:09.670409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:38:09.676995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:38:09.680284 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:38:09.686831 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:38:09.690629 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:38:09.697228 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:38:09.700297 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:38:09.707099 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:38:09.710232 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:38:09.717433 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:38:09.720073 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:38:09.727235 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:38:09.730508 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:38:09.733648 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:38:09.740509 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:38:09.743511 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:38:09.747531 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:38:09.751125 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:38:09.757996 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:38:09.761924 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:38:09.765204 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:38:09.768041 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:38:09.774677 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:38:09.778462 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:38:09.784852 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:38:09.794620 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:38:09.798290 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:38:09.808186 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:38:09.814941 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:38:09.818218 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:38:09.824763 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:38:09.828186 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:38:09.835098 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
467 12:38:09.841842 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:38:09.845065 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:38:09.848763 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:38:09.860489 [RTC]rtc_get_frequency_meter,154: input=15, output=773
471 12:38:09.869245 [RTC]rtc_get_frequency_meter,154: input=23, output=958
472 12:38:09.878953 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 12:38:09.888430 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 12:38:09.897651 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 12:38:09.901296 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 12:38:09.907956 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 12:38:09.911111 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 12:38:09.914817 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 12:38:09.917777 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 12:38:09.921094 ADC[4]: Raw value=902876 ID=7
481 12:38:09.924896 ADC[3]: Raw value=213179 ID=1
482 12:38:09.927717 RAM Code: 0x71
483 12:38:09.931497 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 12:38:09.934590 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 12:38:09.944626 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 12:38:09.951222 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 12:38:09.954709 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 12:38:09.958103 in-header: 03 07 00 00 08 00 00 00
489 12:38:09.961809 in-data: aa e4 47 04 13 02 00 00
490 12:38:09.964791 Chrome EC: UHEPI supported
491 12:38:09.971329 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 12:38:09.974841 in-header: 03 ed 00 00 08 00 00 00
493 12:38:09.977872 in-data: 80 20 60 08 00 00 00 00
494 12:38:09.981409 MRC: failed to locate region type 0.
495 12:38:09.988226 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 12:38:09.991276 DRAM-K: Running full calibration
497 12:38:09.994644 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 12:38:09.998105 header.status = 0x0
499 12:38:10.001727 header.version = 0x6 (expected: 0x6)
500 12:38:10.004986 header.size = 0xd00 (expected: 0xd00)
501 12:38:10.008103 header.flags = 0x0
502 12:38:10.011288 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 12:38:10.030550 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 12:38:10.036991 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 12:38:10.040620 dram_init: ddr_geometry: 2
506 12:38:10.043783 [EMI] MDL number = 2
507 12:38:10.043869 [EMI] Get MDL freq = 0
508 12:38:10.046992 dram_init: ddr_type: 0
509 12:38:10.047081 is_discrete_lpddr4: 1
510 12:38:10.050164 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 12:38:10.050255
512 12:38:10.050324
513 12:38:10.053796 [Bian_co] ETT version 0.0.0.1
514 12:38:10.060478 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 12:38:10.060569
516 12:38:10.064022 dramc_set_vcore_voltage set vcore to 650000
517 12:38:10.064109 Read voltage for 800, 4
518 12:38:10.067095 Vio18 = 0
519 12:38:10.067182 Vcore = 650000
520 12:38:10.067250 Vdram = 0
521 12:38:10.070261 Vddq = 0
522 12:38:10.070347 Vmddr = 0
523 12:38:10.074041 dram_init: config_dvfs: 1
524 12:38:10.077109 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 12:38:10.083618 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 12:38:10.087011 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
527 12:38:10.090657 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
528 12:38:10.093794 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 12:38:10.097148 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 12:38:10.100470 MEM_TYPE=3, freq_sel=18
531 12:38:10.104622 sv_algorithm_assistance_LP4_1600
532 12:38:10.108260 ============ PULL DRAM RESETB DOWN ============
533 12:38:10.111748 ========== PULL DRAM RESETB DOWN end =========
534 12:38:10.115214 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 12:38:10.118663 ===================================
536 12:38:10.122978 LPDDR4 DRAM CONFIGURATION
537 12:38:10.126278 ===================================
538 12:38:10.126370 EX_ROW_EN[0] = 0x0
539 12:38:10.129763 EX_ROW_EN[1] = 0x0
540 12:38:10.129877 LP4Y_EN = 0x0
541 12:38:10.133977 WORK_FSP = 0x0
542 12:38:10.134067 WL = 0x2
543 12:38:10.137537 RL = 0x2
544 12:38:10.137625 BL = 0x2
545 12:38:10.141083 RPST = 0x0
546 12:38:10.141172 RD_PRE = 0x0
547 12:38:10.144899 WR_PRE = 0x1
548 12:38:10.144988 WR_PST = 0x0
549 12:38:10.148630 DBI_WR = 0x0
550 12:38:10.148729 DBI_RD = 0x0
551 12:38:10.152131 OTF = 0x1
552 12:38:10.152221 ===================================
553 12:38:10.155617 ===================================
554 12:38:10.158770 ANA top config
555 12:38:10.162159 ===================================
556 12:38:10.165653 DLL_ASYNC_EN = 0
557 12:38:10.165743 ALL_SLAVE_EN = 1
558 12:38:10.168879 NEW_RANK_MODE = 1
559 12:38:10.172360 DLL_IDLE_MODE = 1
560 12:38:10.175763 LP45_APHY_COMB_EN = 1
561 12:38:10.175851 TX_ODT_DIS = 1
562 12:38:10.178829 NEW_8X_MODE = 1
563 12:38:10.182474 ===================================
564 12:38:10.186055 ===================================
565 12:38:10.188974 data_rate = 1600
566 12:38:10.192708 CKR = 1
567 12:38:10.195647 DQ_P2S_RATIO = 8
568 12:38:10.199286 ===================================
569 12:38:10.199373 CA_P2S_RATIO = 8
570 12:38:10.202430 DQ_CA_OPEN = 0
571 12:38:10.205930 DQ_SEMI_OPEN = 0
572 12:38:10.209068 CA_SEMI_OPEN = 0
573 12:38:10.212608 CA_FULL_RATE = 0
574 12:38:10.215953 DQ_CKDIV4_EN = 1
575 12:38:10.216044 CA_CKDIV4_EN = 1
576 12:38:10.219886 CA_PREDIV_EN = 0
577 12:38:10.223806 PH8_DLY = 0
578 12:38:10.223898 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 12:38:10.227912 DQ_AAMCK_DIV = 4
580 12:38:10.231326 CA_AAMCK_DIV = 4
581 12:38:10.234993 CA_ADMCK_DIV = 4
582 12:38:10.235083 DQ_TRACK_CA_EN = 0
583 12:38:10.238876 CA_PICK = 800
584 12:38:10.242618 CA_MCKIO = 800
585 12:38:10.246060 MCKIO_SEMI = 0
586 12:38:10.249042 PLL_FREQ = 3068
587 12:38:10.252343 DQ_UI_PI_RATIO = 32
588 12:38:10.252437 CA_UI_PI_RATIO = 0
589 12:38:10.256350 ===================================
590 12:38:10.259069 ===================================
591 12:38:10.262393 memory_type:LPDDR4
592 12:38:10.265847 GP_NUM : 10
593 12:38:10.266005 SRAM_EN : 1
594 12:38:10.269157 MD32_EN : 0
595 12:38:10.272434 ===================================
596 12:38:10.276691 [ANA_INIT] >>>>>>>>>>>>>>
597 12:38:10.276785 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 12:38:10.279669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:38:10.283747 ===================================
600 12:38:10.287384 data_rate = 1600,PCW = 0X7600
601 12:38:10.291237 ===================================
602 12:38:10.295041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 12:38:10.298554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 12:38:10.306137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 12:38:10.309780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 12:38:10.312840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 12:38:10.316555 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 12:38:10.319508 [ANA_INIT] flow start
609 12:38:10.319598 [ANA_INIT] PLL >>>>>>>>
610 12:38:10.323509 [ANA_INIT] PLL <<<<<<<<
611 12:38:10.326291 [ANA_INIT] MIDPI >>>>>>>>
612 12:38:10.326379 [ANA_INIT] MIDPI <<<<<<<<
613 12:38:10.329779 [ANA_INIT] DLL >>>>>>>>
614 12:38:10.333094 [ANA_INIT] flow end
615 12:38:10.336441 ============ LP4 DIFF to SE enter ============
616 12:38:10.339994 ============ LP4 DIFF to SE exit ============
617 12:38:10.343224 [ANA_INIT] <<<<<<<<<<<<<
618 12:38:10.346373 [Flow] Enable top DCM control >>>>>
619 12:38:10.349838 [Flow] Enable top DCM control <<<<<
620 12:38:10.352951 Enable DLL master slave shuffle
621 12:38:10.356510 ==============================================================
622 12:38:10.360387 Gating Mode config
623 12:38:10.362976 ==============================================================
624 12:38:10.366538 Config description:
625 12:38:10.376560 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 12:38:10.382973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 12:38:10.386542 SELPH_MODE 0: By rank 1: By Phase
628 12:38:10.393483 ==============================================================
629 12:38:10.396337 GAT_TRACK_EN = 1
630 12:38:10.399852 RX_GATING_MODE = 2
631 12:38:10.403116 RX_GATING_TRACK_MODE = 2
632 12:38:10.406412 SELPH_MODE = 1
633 12:38:10.406505 PICG_EARLY_EN = 1
634 12:38:10.409840 VALID_LAT_VALUE = 1
635 12:38:10.416278 ==============================================================
636 12:38:10.420097 Enter into Gating configuration >>>>
637 12:38:10.423546 Exit from Gating configuration <<<<
638 12:38:10.426344 Enter into DVFS_PRE_config >>>>>
639 12:38:10.436305 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 12:38:10.439573 Exit from DVFS_PRE_config <<<<<
641 12:38:10.443104 Enter into PICG configuration >>>>
642 12:38:10.446701 Exit from PICG configuration <<<<
643 12:38:10.449868 [RX_INPUT] configuration >>>>>
644 12:38:10.453480 [RX_INPUT] configuration <<<<<
645 12:38:10.456623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 12:38:10.463628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 12:38:10.469909 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 12:38:10.476574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 12:38:10.479971 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 12:38:10.486522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 12:38:10.490145 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 12:38:10.496867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 12:38:10.500245 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 12:38:10.504024 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 12:38:10.507226 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 12:38:10.514279 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 12:38:10.517519 ===================================
658 12:38:10.517617 LPDDR4 DRAM CONFIGURATION
659 12:38:10.520621 ===================================
660 12:38:10.524340 EX_ROW_EN[0] = 0x0
661 12:38:10.524428 EX_ROW_EN[1] = 0x0
662 12:38:10.527629 LP4Y_EN = 0x0
663 12:38:10.527714 WORK_FSP = 0x0
664 12:38:10.530761 WL = 0x2
665 12:38:10.530847 RL = 0x2
666 12:38:10.534326 BL = 0x2
667 12:38:10.534411 RPST = 0x0
668 12:38:10.537696 RD_PRE = 0x0
669 12:38:10.540969 WR_PRE = 0x1
670 12:38:10.541055 WR_PST = 0x0
671 12:38:10.544064 DBI_WR = 0x0
672 12:38:10.544151 DBI_RD = 0x0
673 12:38:10.547489 OTF = 0x1
674 12:38:10.550977 ===================================
675 12:38:10.554582 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 12:38:10.557403 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 12:38:10.561093 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 12:38:10.564449 ===================================
679 12:38:10.567552 LPDDR4 DRAM CONFIGURATION
680 12:38:10.570762 ===================================
681 12:38:10.574076 EX_ROW_EN[0] = 0x10
682 12:38:10.574175 EX_ROW_EN[1] = 0x0
683 12:38:10.577723 LP4Y_EN = 0x0
684 12:38:10.577810 WORK_FSP = 0x0
685 12:38:10.580938 WL = 0x2
686 12:38:10.581024 RL = 0x2
687 12:38:10.584461 BL = 0x2
688 12:38:10.584548 RPST = 0x0
689 12:38:10.587918 RD_PRE = 0x0
690 12:38:10.588005 WR_PRE = 0x1
691 12:38:10.590853 WR_PST = 0x0
692 12:38:10.590939 DBI_WR = 0x0
693 12:38:10.594424 DBI_RD = 0x0
694 12:38:10.594511 OTF = 0x1
695 12:38:10.597575 ===================================
696 12:38:10.604280 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 12:38:10.608840 nWR fixed to 40
698 12:38:10.612217 [ModeRegInit_LP4] CH0 RK0
699 12:38:10.612314 [ModeRegInit_LP4] CH0 RK1
700 12:38:10.615703 [ModeRegInit_LP4] CH1 RK0
701 12:38:10.618837 [ModeRegInit_LP4] CH1 RK1
702 12:38:10.618927 match AC timing 13
703 12:38:10.625796 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 12:38:10.629141 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 12:38:10.632169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 12:38:10.638798 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 12:38:10.642565 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 12:38:10.642662 [EMI DOE] emi_dcm 0
709 12:38:10.649720 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 12:38:10.649843 ==
711 12:38:10.652495 Dram Type= 6, Freq= 0, CH_0, rank 0
712 12:38:10.655710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 12:38:10.655825 ==
714 12:38:10.662586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 12:38:10.666182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 12:38:10.676579 [CA 0] Center 38 (7~69) winsize 63
717 12:38:10.680064 [CA 1] Center 38 (7~69) winsize 63
718 12:38:10.683484 [CA 2] Center 35 (5~66) winsize 62
719 12:38:10.686616 [CA 3] Center 35 (5~66) winsize 62
720 12:38:10.689889 [CA 4] Center 35 (4~66) winsize 63
721 12:38:10.693272 [CA 5] Center 33 (3~64) winsize 62
722 12:38:10.693364
723 12:38:10.696543 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 12:38:10.696632
725 12:38:10.700013 [CATrainingPosCal] consider 1 rank data
726 12:38:10.703390 u2DelayCellTimex100 = 270/100 ps
727 12:38:10.706704 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 12:38:10.709976 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 12:38:10.716779 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 12:38:10.720159 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 12:38:10.723494 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
732 12:38:10.726585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 12:38:10.726676
734 12:38:10.730250 CA PerBit enable=1, Macro0, CA PI delay=33
735 12:38:10.730337
736 12:38:10.733449 [CBTSetCACLKResult] CA Dly = 33
737 12:38:10.733537 CS Dly: 5 (0~36)
738 12:38:10.733604 ==
739 12:38:10.736653 Dram Type= 6, Freq= 0, CH_0, rank 1
740 12:38:10.743620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 12:38:10.743782 ==
742 12:38:10.746705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 12:38:10.753386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 12:38:10.763130 [CA 0] Center 38 (7~69) winsize 63
745 12:38:10.766898 [CA 1] Center 38 (8~69) winsize 62
746 12:38:10.770275 [CA 2] Center 36 (6~66) winsize 61
747 12:38:10.774293 [CA 3] Center 35 (5~66) winsize 62
748 12:38:10.777798 [CA 4] Center 35 (4~66) winsize 63
749 12:38:10.781029 [CA 5] Center 34 (4~65) winsize 62
750 12:38:10.781126
751 12:38:10.785037 [CmdBusTrainingLP45] Vref(ca) range 1: 30
752 12:38:10.785129
753 12:38:10.788547 [CATrainingPosCal] consider 2 rank data
754 12:38:10.792431 u2DelayCellTimex100 = 270/100 ps
755 12:38:10.795811 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 12:38:10.799899 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 12:38:10.803307 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 12:38:10.806724 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 12:38:10.810485 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
760 12:38:10.813715 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 12:38:10.813840
762 12:38:10.817208 CA PerBit enable=1, Macro0, CA PI delay=34
763 12:38:10.817301
764 12:38:10.820980 [CBTSetCACLKResult] CA Dly = 34
765 12:38:10.821074 CS Dly: 6 (0~38)
766 12:38:10.821142
767 12:38:10.824344 ----->DramcWriteLeveling(PI) begin...
768 12:38:10.824436 ==
769 12:38:10.828063 Dram Type= 6, Freq= 0, CH_0, rank 0
770 12:38:10.831566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 12:38:10.831667 ==
772 12:38:10.835387 Write leveling (Byte 0): 34 => 34
773 12:38:10.839290 Write leveling (Byte 1): 31 => 31
774 12:38:10.842669 DramcWriteLeveling(PI) end<-----
775 12:38:10.842765
776 12:38:10.842836 ==
777 12:38:10.846464 Dram Type= 6, Freq= 0, CH_0, rank 0
778 12:38:10.850252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 12:38:10.850360 ==
780 12:38:10.853770 [Gating] SW mode calibration
781 12:38:10.860988 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 12:38:10.864722 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 12:38:10.868308 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 12:38:10.872192 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 12:38:10.879569 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 12:38:10.882992 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:38:10.886802 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:38:10.890468 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:38:10.894516 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:38:10.901596 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:38:10.905521 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:38:10.909330 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:38:10.913024 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:38:10.916570 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:38:10.920298 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:38:10.927639 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:38:10.931647 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:38:10.935438 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:38:10.939158 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:38:10.943025 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 12:38:10.946755 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 12:38:10.953992 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:38:10.957918 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:38:10.961610 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:38:10.965516 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:38:10.968890 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:38:10.976158 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:38:10.980142 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
809 12:38:10.983707 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 12:38:10.987565 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
811 12:38:10.991209 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:38:10.994907 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:38:11.002031 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:38:11.005934 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:38:11.009741 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 12:38:11.012989 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
817 12:38:11.016985 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
818 12:38:11.024325 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 12:38:11.027948 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:38:11.032141 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:38:11.035450 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:38:11.039155 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:38:11.046437 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:38:11.050545 0 11 4 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
825 12:38:11.053957 0 11 8 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
826 12:38:11.057802 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
827 12:38:11.061298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:38:11.065374 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:38:11.072648 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:38:11.076341 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:38:11.080415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:38:11.083482 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 12:38:11.087637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 12:38:11.094953 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:38:11.097981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:38:11.101464 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:38:11.104898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:38:11.111607 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:38:11.114813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:38:11.118150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:38:11.125043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:38:11.128545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:38:11.132010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:38:11.138435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:38:11.142124 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:38:11.145400 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:38:11.148401 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:38:11.155229 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 12:38:11.158772 Total UI for P1: 0, mck2ui 16
850 12:38:11.161890 best dqsien dly found for B0: ( 0, 14, 2)
851 12:38:11.165459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 12:38:11.168811 Total UI for P1: 0, mck2ui 16
853 12:38:11.171968 best dqsien dly found for B1: ( 0, 14, 4)
854 12:38:11.175141 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 12:38:11.179025 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
856 12:38:11.179119
857 12:38:11.182269 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 12:38:11.185328 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 12:38:11.188589 [Gating] SW calibration Done
860 12:38:11.188679 ==
861 12:38:11.191829 Dram Type= 6, Freq= 0, CH_0, rank 0
862 12:38:11.195436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 12:38:11.198851 ==
864 12:38:11.198940 RX Vref Scan: 0
865 12:38:11.199008
866 12:38:11.201906 RX Vref 0 -> 0, step: 1
867 12:38:11.202048
868 12:38:11.205208 RX Delay -130 -> 252, step: 16
869 12:38:11.208477 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 12:38:11.212065 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 12:38:11.215387 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 12:38:11.218749 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 12:38:11.225565 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
874 12:38:11.228470 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 12:38:11.232069 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 12:38:11.235439 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 12:38:11.238712 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 12:38:11.245448 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
879 12:38:11.248663 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 12:38:11.251728 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 12:38:11.255402 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 12:38:11.258455 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
883 12:38:11.265412 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 12:38:11.268583 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 12:38:11.268682 ==
886 12:38:11.271926 Dram Type= 6, Freq= 0, CH_0, rank 0
887 12:38:11.275577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 12:38:11.275669 ==
889 12:38:11.278587 DQS Delay:
890 12:38:11.278680 DQS0 = 0, DQS1 = 0
891 12:38:11.278750 DQM Delay:
892 12:38:11.282327 DQM0 = 89, DQM1 = 79
893 12:38:11.282416 DQ Delay:
894 12:38:11.285461 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
895 12:38:11.288926 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
896 12:38:11.292209 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
897 12:38:11.295340 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
898 12:38:11.295429
899 12:38:11.295496
900 12:38:11.295557 ==
901 12:38:11.298749 Dram Type= 6, Freq= 0, CH_0, rank 0
902 12:38:11.305326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 12:38:11.305428 ==
904 12:38:11.305498
905 12:38:11.305561
906 12:38:11.305623 TX Vref Scan disable
907 12:38:11.308610 == TX Byte 0 ==
908 12:38:11.312066 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
909 12:38:11.315284 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
910 12:38:11.319080 == TX Byte 1 ==
911 12:38:11.322222 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 12:38:11.325540 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 12:38:11.328640 ==
914 12:38:11.332301 Dram Type= 6, Freq= 0, CH_0, rank 0
915 12:38:11.335156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 12:38:11.335249 ==
917 12:38:11.348094 TX Vref=22, minBit 6, minWin=27, winSum=440
918 12:38:11.351467 TX Vref=24, minBit 8, minWin=27, winSum=444
919 12:38:11.354967 TX Vref=26, minBit 10, minWin=27, winSum=449
920 12:38:11.358191 TX Vref=28, minBit 9, minWin=27, winSum=452
921 12:38:11.361203 TX Vref=30, minBit 4, minWin=28, winSum=458
922 12:38:11.367964 TX Vref=32, minBit 10, minWin=27, winSum=457
923 12:38:11.371593 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
924 12:38:11.371701
925 12:38:11.374753 Final TX Range 1 Vref 30
926 12:38:11.374842
927 12:38:11.374909 ==
928 12:38:11.378278 Dram Type= 6, Freq= 0, CH_0, rank 0
929 12:38:11.381390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 12:38:11.381479 ==
931 12:38:11.384765
932 12:38:11.384851
933 12:38:11.384918 TX Vref Scan disable
934 12:38:11.387991 == TX Byte 0 ==
935 12:38:11.391491 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
936 12:38:11.394766 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
937 12:38:11.398209 == TX Byte 1 ==
938 12:38:11.401340 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 12:38:11.405297 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 12:38:11.408168
941 12:38:11.408260 [DATLAT]
942 12:38:11.408329 Freq=800, CH0 RK0
943 12:38:11.408392
944 12:38:11.411735 DATLAT Default: 0xa
945 12:38:11.411820 0, 0xFFFF, sum = 0
946 12:38:11.415079 1, 0xFFFF, sum = 0
947 12:38:11.415168 2, 0xFFFF, sum = 0
948 12:38:11.418213 3, 0xFFFF, sum = 0
949 12:38:11.418300 4, 0xFFFF, sum = 0
950 12:38:11.421568 5, 0xFFFF, sum = 0
951 12:38:11.421655 6, 0xFFFF, sum = 0
952 12:38:11.424933 7, 0xFFFF, sum = 0
953 12:38:11.425021 8, 0xFFFF, sum = 0
954 12:38:11.428206 9, 0x0, sum = 1
955 12:38:11.428294 10, 0x0, sum = 2
956 12:38:11.431458 11, 0x0, sum = 3
957 12:38:11.431545 12, 0x0, sum = 4
958 12:38:11.435051 best_step = 10
959 12:38:11.435167
960 12:38:11.435263 ==
961 12:38:11.438355 Dram Type= 6, Freq= 0, CH_0, rank 0
962 12:38:11.441551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 12:38:11.441639 ==
964 12:38:11.445410 RX Vref Scan: 1
965 12:38:11.445498
966 12:38:11.445567 Set Vref Range= 32 -> 127
967 12:38:11.445631
968 12:38:11.448282 RX Vref 32 -> 127, step: 1
969 12:38:11.448369
970 12:38:11.451710 RX Delay -79 -> 252, step: 8
971 12:38:11.451798
972 12:38:11.454839 Set Vref, RX VrefLevel [Byte0]: 32
973 12:38:11.458363 [Byte1]: 32
974 12:38:11.458453
975 12:38:11.461800 Set Vref, RX VrefLevel [Byte0]: 33
976 12:38:11.465382 [Byte1]: 33
977 12:38:11.468492
978 12:38:11.468588 Set Vref, RX VrefLevel [Byte0]: 34
979 12:38:11.471785 [Byte1]: 34
980 12:38:11.476205
981 12:38:11.476298 Set Vref, RX VrefLevel [Byte0]: 35
982 12:38:11.479057 [Byte1]: 35
983 12:38:11.483474
984 12:38:11.483570 Set Vref, RX VrefLevel [Byte0]: 36
985 12:38:11.486817 [Byte1]: 36
986 12:38:11.491010
987 12:38:11.491101 Set Vref, RX VrefLevel [Byte0]: 37
988 12:38:11.494299 [Byte1]: 37
989 12:38:11.498336
990 12:38:11.498427 Set Vref, RX VrefLevel [Byte0]: 38
991 12:38:11.501902 [Byte1]: 38
992 12:38:11.506249
993 12:38:11.506343 Set Vref, RX VrefLevel [Byte0]: 39
994 12:38:11.509285 [Byte1]: 39
995 12:38:11.513718
996 12:38:11.513819 Set Vref, RX VrefLevel [Byte0]: 40
997 12:38:11.516731 [Byte1]: 40
998 12:38:11.521477
999 12:38:11.521571 Set Vref, RX VrefLevel [Byte0]: 41
1000 12:38:11.524474 [Byte1]: 41
1001 12:38:11.529079
1002 12:38:11.529174 Set Vref, RX VrefLevel [Byte0]: 42
1003 12:38:11.532487 [Byte1]: 42
1004 12:38:11.536398
1005 12:38:11.536492 Set Vref, RX VrefLevel [Byte0]: 43
1006 12:38:11.539615 [Byte1]: 43
1007 12:38:11.543985
1008 12:38:11.544079 Set Vref, RX VrefLevel [Byte0]: 44
1009 12:38:11.547466 [Byte1]: 44
1010 12:38:11.551790
1011 12:38:11.551886 Set Vref, RX VrefLevel [Byte0]: 45
1012 12:38:11.554968 [Byte1]: 45
1013 12:38:11.559208
1014 12:38:11.559317 Set Vref, RX VrefLevel [Byte0]: 46
1015 12:38:11.562507 [Byte1]: 46
1016 12:38:11.566406
1017 12:38:11.566503 Set Vref, RX VrefLevel [Byte0]: 47
1018 12:38:11.569605 [Byte1]: 47
1019 12:38:11.573956
1020 12:38:11.574046 Set Vref, RX VrefLevel [Byte0]: 48
1021 12:38:11.577130 [Byte1]: 48
1022 12:38:11.581507
1023 12:38:11.581605 Set Vref, RX VrefLevel [Byte0]: 49
1024 12:38:11.584927 [Byte1]: 49
1025 12:38:11.589021
1026 12:38:11.589113 Set Vref, RX VrefLevel [Byte0]: 50
1027 12:38:11.592622 [Byte1]: 50
1028 12:38:11.596830
1029 12:38:11.596920 Set Vref, RX VrefLevel [Byte0]: 51
1030 12:38:11.600154 [Byte1]: 51
1031 12:38:11.604093
1032 12:38:11.604214 Set Vref, RX VrefLevel [Byte0]: 52
1033 12:38:11.607346 [Byte1]: 52
1034 12:38:11.611639
1035 12:38:11.611741 Set Vref, RX VrefLevel [Byte0]: 53
1036 12:38:11.615007 [Byte1]: 53
1037 12:38:11.619155
1038 12:38:11.619256 Set Vref, RX VrefLevel [Byte0]: 54
1039 12:38:11.622373 [Byte1]: 54
1040 12:38:11.627009
1041 12:38:11.627113 Set Vref, RX VrefLevel [Byte0]: 55
1042 12:38:11.629951 [Byte1]: 55
1043 12:38:11.634595
1044 12:38:11.634722 Set Vref, RX VrefLevel [Byte0]: 56
1045 12:38:11.637643 [Byte1]: 56
1046 12:38:11.641826
1047 12:38:11.641954 Set Vref, RX VrefLevel [Byte0]: 57
1048 12:38:11.645644 [Byte1]: 57
1049 12:38:11.649390
1050 12:38:11.649506 Set Vref, RX VrefLevel [Byte0]: 58
1051 12:38:11.652711 [Byte1]: 58
1052 12:38:11.657217
1053 12:38:11.657351 Set Vref, RX VrefLevel [Byte0]: 59
1054 12:38:11.660199 [Byte1]: 59
1055 12:38:11.664646
1056 12:38:11.664737 Set Vref, RX VrefLevel [Byte0]: 60
1057 12:38:11.667792 [Byte1]: 60
1058 12:38:11.672083
1059 12:38:11.672244 Set Vref, RX VrefLevel [Byte0]: 61
1060 12:38:11.675383 [Byte1]: 61
1061 12:38:11.679358
1062 12:38:11.679459 Set Vref, RX VrefLevel [Byte0]: 62
1063 12:38:11.682966 [Byte1]: 62
1064 12:38:11.686850
1065 12:38:11.686979 Set Vref, RX VrefLevel [Byte0]: 63
1066 12:38:11.690135 [Byte1]: 63
1067 12:38:11.694646
1068 12:38:11.694732 Set Vref, RX VrefLevel [Byte0]: 64
1069 12:38:11.698173 [Byte1]: 64
1070 12:38:11.702282
1071 12:38:11.702412 Set Vref, RX VrefLevel [Byte0]: 65
1072 12:38:11.705543 [Byte1]: 65
1073 12:38:11.709924
1074 12:38:11.710049 Set Vref, RX VrefLevel [Byte0]: 66
1075 12:38:11.713152 [Byte1]: 66
1076 12:38:11.717243
1077 12:38:11.717331 Set Vref, RX VrefLevel [Byte0]: 67
1078 12:38:11.720366 [Byte1]: 67
1079 12:38:11.724793
1080 12:38:11.724913 Set Vref, RX VrefLevel [Byte0]: 68
1081 12:38:11.728028 [Byte1]: 68
1082 12:38:11.732422
1083 12:38:11.732513 Set Vref, RX VrefLevel [Byte0]: 69
1084 12:38:11.735711 [Byte1]: 69
1085 12:38:11.740030
1086 12:38:11.740119 Set Vref, RX VrefLevel [Byte0]: 70
1087 12:38:11.743136 [Byte1]: 70
1088 12:38:11.747377
1089 12:38:11.747476 Set Vref, RX VrefLevel [Byte0]: 71
1090 12:38:11.750906 [Byte1]: 71
1091 12:38:11.755384
1092 12:38:11.755501 Set Vref, RX VrefLevel [Byte0]: 72
1093 12:38:11.758701 [Byte1]: 72
1094 12:38:11.762458
1095 12:38:11.762558 Set Vref, RX VrefLevel [Byte0]: 73
1096 12:38:11.765787 [Byte1]: 73
1097 12:38:11.770356
1098 12:38:11.770467 Set Vref, RX VrefLevel [Byte0]: 74
1099 12:38:11.773369 [Byte1]: 74
1100 12:38:11.777870
1101 12:38:11.778007 Set Vref, RX VrefLevel [Byte0]: 75
1102 12:38:11.781242 [Byte1]: 75
1103 12:38:11.785380
1104 12:38:11.785499 Set Vref, RX VrefLevel [Byte0]: 76
1105 12:38:11.788809 [Byte1]: 76
1106 12:38:11.792844
1107 12:38:11.792938 Final RX Vref Byte 0 = 62 to rank0
1108 12:38:11.796136 Final RX Vref Byte 1 = 60 to rank0
1109 12:38:11.799404 Final RX Vref Byte 0 = 62 to rank1
1110 12:38:11.802669 Final RX Vref Byte 1 = 60 to rank1==
1111 12:38:11.805935 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 12:38:11.812915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 12:38:11.813026 ==
1114 12:38:11.813098 DQS Delay:
1115 12:38:11.813161 DQS0 = 0, DQS1 = 0
1116 12:38:11.816109 DQM Delay:
1117 12:38:11.816197 DQM0 = 93, DQM1 = 81
1118 12:38:11.819377 DQ Delay:
1119 12:38:11.823111 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1120 12:38:11.826217 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1121 12:38:11.829539 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1122 12:38:11.832773 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1123 12:38:11.832863
1124 12:38:11.832932
1125 12:38:11.839565 [DQSOSCAuto] RK0, (LSB)MR18= 0x403b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1126 12:38:11.843015 CH0 RK0: MR19=606, MR18=403B
1127 12:38:11.849324 CH0_RK0: MR19=0x606, MR18=0x403B, DQSOSC=393, MR23=63, INC=95, DEC=63
1128 12:38:11.849470
1129 12:38:11.853188 ----->DramcWriteLeveling(PI) begin...
1130 12:38:11.853288 ==
1131 12:38:11.856632 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 12:38:11.859572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 12:38:11.859661 ==
1134 12:38:11.863144 Write leveling (Byte 0): 32 => 32
1135 12:38:11.866420 Write leveling (Byte 1): 28 => 28
1136 12:38:11.869547 DramcWriteLeveling(PI) end<-----
1137 12:38:11.869636
1138 12:38:11.869703 ==
1139 12:38:11.872987 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 12:38:11.876393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 12:38:11.876484 ==
1142 12:38:11.879889 [Gating] SW mode calibration
1143 12:38:11.886369 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 12:38:11.893284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 12:38:11.896542 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1146 12:38:11.900148 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 12:38:11.906608 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:38:11.909852 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:38:11.913340 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:38:11.919807 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:38:11.923237 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:38:11.926646 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:38:11.970916 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:38:11.971277 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:38:11.971366 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:38:11.971434 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:38:11.971916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:38:11.972184 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:38:11.972441 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:38:11.972874 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:38:11.972960 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1162 12:38:11.973211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1163 12:38:12.014946 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1164 12:38:12.015302 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:38:12.015564 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:38:12.015633 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:38:12.015697 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:38:12.015939 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:38:12.016261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:38:12.016357 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1171 12:38:12.016426 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
1172 12:38:12.016489 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:38:12.058984 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 12:38:12.059344 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:38:12.059442 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 12:38:12.059510 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 12:38:12.059572 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:38:12.060054 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
1179 12:38:12.060323 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1180 12:38:12.060579 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:38:12.060650 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:38:12.060895 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:38:12.064552 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:38:12.067847 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:38:12.071147 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:38:12.078051 0 11 4 | B1->B0 | 2424 3030 | 1 0 | (0 0) (0 0)
1187 12:38:12.081422 0 11 8 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
1188 12:38:12.084707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:38:12.091326 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:38:12.094505 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:38:12.097706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 12:38:12.101148 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 12:38:12.108980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 12:38:12.112496 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1195 12:38:12.115795 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:38:12.119419 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:38:12.126243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:38:12.129565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:38:12.132725 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:38:12.136681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:38:12.143113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:38:12.146424 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:38:12.150290 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:38:12.156841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:38:12.159888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:38:12.163431 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:38:12.169928 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:38:12.173432 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:38:12.176802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:38:12.183374 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 12:38:12.186880 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1212 12:38:12.189989 Total UI for P1: 0, mck2ui 16
1213 12:38:12.193487 best dqsien dly found for B0: ( 0, 14, 4)
1214 12:38:12.196735 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 12:38:12.200327 Total UI for P1: 0, mck2ui 16
1216 12:38:12.203581 best dqsien dly found for B1: ( 0, 14, 6)
1217 12:38:12.206785 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1218 12:38:12.209991 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1219 12:38:12.210117
1220 12:38:12.213450 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 12:38:12.216700 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1222 12:38:12.220318 [Gating] SW calibration Done
1223 12:38:12.220405 ==
1224 12:38:12.223606 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 12:38:12.229974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 12:38:12.230087 ==
1227 12:38:12.230155 RX Vref Scan: 0
1228 12:38:12.230227
1229 12:38:12.233297 RX Vref 0 -> 0, step: 1
1230 12:38:12.233374
1231 12:38:12.236771 RX Delay -130 -> 252, step: 16
1232 12:38:12.240402 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1233 12:38:12.243528 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1234 12:38:12.246883 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1235 12:38:12.250090 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1236 12:38:12.256624 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1237 12:38:12.260094 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1238 12:38:12.263333 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1239 12:38:12.266715 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1240 12:38:12.270193 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1241 12:38:12.276925 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1242 12:38:12.280016 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1243 12:38:12.283586 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1244 12:38:12.286695 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1245 12:38:12.290521 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1246 12:38:12.296726 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1247 12:38:12.300133 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1248 12:38:12.300258 ==
1249 12:38:12.303645 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 12:38:12.307155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 12:38:12.307247 ==
1252 12:38:12.310330 DQS Delay:
1253 12:38:12.310423 DQS0 = 0, DQS1 = 0
1254 12:38:12.310491 DQM Delay:
1255 12:38:12.313960 DQM0 = 88, DQM1 = 80
1256 12:38:12.314064 DQ Delay:
1257 12:38:12.317126 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1258 12:38:12.320508 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1259 12:38:12.323694 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1260 12:38:12.327633 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =93
1261 12:38:12.327754
1262 12:38:12.327860
1263 12:38:12.327953 ==
1264 12:38:12.330468 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 12:38:12.333848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 12:38:12.336898 ==
1267 12:38:12.337013
1268 12:38:12.337109
1269 12:38:12.337236 TX Vref Scan disable
1270 12:38:12.341055 == TX Byte 0 ==
1271 12:38:12.343736 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1272 12:38:12.346930 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1273 12:38:12.350427 == TX Byte 1 ==
1274 12:38:12.353648 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1275 12:38:12.357158 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1276 12:38:12.360723 ==
1277 12:38:12.363927 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 12:38:12.367109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 12:38:12.367200 ==
1280 12:38:12.380261 TX Vref=22, minBit 8, minWin=27, winSum=446
1281 12:38:12.383214 TX Vref=24, minBit 8, minWin=27, winSum=448
1282 12:38:12.386501 TX Vref=26, minBit 8, minWin=27, winSum=449
1283 12:38:12.389952 TX Vref=28, minBit 8, minWin=27, winSum=453
1284 12:38:12.393078 TX Vref=30, minBit 8, minWin=27, winSum=456
1285 12:38:12.396341 TX Vref=32, minBit 3, minWin=28, winSum=457
1286 12:38:12.403373 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 32
1287 12:38:12.403493
1288 12:38:12.406597 Final TX Range 1 Vref 32
1289 12:38:12.406695
1290 12:38:12.406766 ==
1291 12:38:12.409957 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 12:38:12.413184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 12:38:12.413283 ==
1294 12:38:12.413352
1295 12:38:12.416387
1296 12:38:12.416476 TX Vref Scan disable
1297 12:38:12.419848 == TX Byte 0 ==
1298 12:38:12.423514 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1299 12:38:12.426716 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1300 12:38:12.430076 == TX Byte 1 ==
1301 12:38:12.433460 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1302 12:38:12.436790 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1303 12:38:12.439948
1304 12:38:12.440036 [DATLAT]
1305 12:38:12.440103 Freq=800, CH0 RK1
1306 12:38:12.440166
1307 12:38:12.443487 DATLAT Default: 0xa
1308 12:38:12.443574 0, 0xFFFF, sum = 0
1309 12:38:12.446682 1, 0xFFFF, sum = 0
1310 12:38:12.446772 2, 0xFFFF, sum = 0
1311 12:38:12.449855 3, 0xFFFF, sum = 0
1312 12:38:12.450014 4, 0xFFFF, sum = 0
1313 12:38:12.453378 5, 0xFFFF, sum = 0
1314 12:38:12.453466 6, 0xFFFF, sum = 0
1315 12:38:12.456589 7, 0xFFFF, sum = 0
1316 12:38:12.456677 8, 0xFFFF, sum = 0
1317 12:38:12.459890 9, 0x0, sum = 1
1318 12:38:12.459976 10, 0x0, sum = 2
1319 12:38:12.463475 11, 0x0, sum = 3
1320 12:38:12.463561 12, 0x0, sum = 4
1321 12:38:12.466506 best_step = 10
1322 12:38:12.466591
1323 12:38:12.466656 ==
1324 12:38:12.470063 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 12:38:12.473288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 12:38:12.473375 ==
1327 12:38:12.476714 RX Vref Scan: 0
1328 12:38:12.476799
1329 12:38:12.476866 RX Vref 0 -> 0, step: 1
1330 12:38:12.476928
1331 12:38:12.479969 RX Delay -79 -> 252, step: 8
1332 12:38:12.486753 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1333 12:38:12.490314 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1334 12:38:12.493512 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1335 12:38:12.496491 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1336 12:38:12.499925 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1337 12:38:12.507050 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1338 12:38:12.509737 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1339 12:38:12.513194 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1340 12:38:12.516455 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1341 12:38:12.519940 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1342 12:38:12.526720 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1343 12:38:12.530078 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1344 12:38:12.533057 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1345 12:38:12.536597 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1346 12:38:12.539872 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1347 12:38:12.546665 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1348 12:38:12.546771 ==
1349 12:38:12.550311 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 12:38:12.553272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 12:38:12.553370 ==
1352 12:38:12.553437 DQS Delay:
1353 12:38:12.556496 DQS0 = 0, DQS1 = 0
1354 12:38:12.556580 DQM Delay:
1355 12:38:12.559877 DQM0 = 91, DQM1 = 81
1356 12:38:12.559962 DQ Delay:
1357 12:38:12.563202 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1358 12:38:12.566488 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1359 12:38:12.569634 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1360 12:38:12.573179 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1361 12:38:12.573301
1362 12:38:12.573400
1363 12:38:12.580080 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1364 12:38:12.583181 CH0 RK1: MR19=606, MR18=3F19
1365 12:38:12.589802 CH0_RK1: MR19=0x606, MR18=0x3F19, DQSOSC=393, MR23=63, INC=95, DEC=63
1366 12:38:12.593762 [RxdqsGatingPostProcess] freq 800
1367 12:38:12.600035 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 12:38:12.603358 Pre-setting of DQS Precalculation
1369 12:38:12.606743 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 12:38:12.606838 ==
1371 12:38:12.610432 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 12:38:12.613256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 12:38:12.613346 ==
1374 12:38:12.620030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 12:38:12.626744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 12:38:12.634986 [CA 0] Center 36 (6~67) winsize 62
1377 12:38:12.638505 [CA 1] Center 37 (6~68) winsize 63
1378 12:38:12.641568 [CA 2] Center 35 (5~65) winsize 61
1379 12:38:12.645036 [CA 3] Center 34 (4~65) winsize 62
1380 12:38:12.648589 [CA 4] Center 34 (4~65) winsize 62
1381 12:38:12.651913 [CA 5] Center 34 (4~64) winsize 61
1382 12:38:12.652083
1383 12:38:12.655284 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1384 12:38:12.655370
1385 12:38:12.658721 [CATrainingPosCal] consider 1 rank data
1386 12:38:12.661869 u2DelayCellTimex100 = 270/100 ps
1387 12:38:12.665125 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1388 12:38:12.668564 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1389 12:38:12.675117 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1390 12:38:12.678675 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1391 12:38:12.681925 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1392 12:38:12.684973 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1393 12:38:12.685062
1394 12:38:12.688685 CA PerBit enable=1, Macro0, CA PI delay=34
1395 12:38:12.688772
1396 12:38:12.691701 [CBTSetCACLKResult] CA Dly = 34
1397 12:38:12.691788 CS Dly: 5 (0~36)
1398 12:38:12.691859 ==
1399 12:38:12.695031 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 12:38:12.702092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 12:38:12.702195 ==
1402 12:38:12.705036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 12:38:12.711947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 12:38:12.720995 [CA 0] Center 37 (7~68) winsize 62
1405 12:38:12.724684 [CA 1] Center 37 (6~68) winsize 63
1406 12:38:12.727753 [CA 2] Center 35 (5~66) winsize 62
1407 12:38:12.731087 [CA 3] Center 35 (5~65) winsize 61
1408 12:38:12.734450 [CA 4] Center 34 (4~65) winsize 62
1409 12:38:12.737855 [CA 5] Center 34 (4~64) winsize 61
1410 12:38:12.737951
1411 12:38:12.741068 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1412 12:38:12.741154
1413 12:38:12.744585 [CATrainingPosCal] consider 2 rank data
1414 12:38:12.747701 u2DelayCellTimex100 = 270/100 ps
1415 12:38:12.751167 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1416 12:38:12.754446 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1417 12:38:12.760998 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1418 12:38:12.764370 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1419 12:38:12.768170 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 12:38:12.772271 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1421 12:38:12.772367
1422 12:38:12.775500 CA PerBit enable=1, Macro0, CA PI delay=34
1423 12:38:12.775589
1424 12:38:12.778865 [CBTSetCACLKResult] CA Dly = 34
1425 12:38:12.778952 CS Dly: 6 (0~38)
1426 12:38:12.779019
1427 12:38:12.782781 ----->DramcWriteLeveling(PI) begin...
1428 12:38:12.782874 ==
1429 12:38:12.785762 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 12:38:12.790083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 12:38:12.790186 ==
1432 12:38:12.793588 Write leveling (Byte 0): 27 => 27
1433 12:38:12.797670 Write leveling (Byte 1): 27 => 27
1434 12:38:12.801122 DramcWriteLeveling(PI) end<-----
1435 12:38:12.801240
1436 12:38:12.801336 ==
1437 12:38:12.804856 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 12:38:12.808487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 12:38:12.808605 ==
1440 12:38:12.811562 [Gating] SW mode calibration
1441 12:38:12.818488 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 12:38:12.821603 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 12:38:12.828644 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1444 12:38:12.832286 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1445 12:38:12.834951 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:38:12.838487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:38:12.845222 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:38:12.848499 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:38:12.852041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:38:12.858603 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:38:12.861829 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:38:12.865442 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:38:12.872001 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:38:12.875285 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:38:12.879063 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:38:12.885363 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:38:12.889127 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:38:12.892452 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:38:12.898737 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1460 12:38:12.902249 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1461 12:38:12.905605 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:38:12.908979 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:38:12.915835 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:38:12.919200 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:38:12.922181 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:38:12.928804 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:38:12.932649 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:38:12.935646 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1469 12:38:12.942797 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1470 12:38:12.945736 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:38:12.948752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 12:38:12.955816 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 12:38:12.959011 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 12:38:12.961977 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 12:38:12.968828 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1476 12:38:12.972224 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
1477 12:38:12.975705 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1478 12:38:12.982090 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:38:12.985805 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:38:12.988793 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:38:12.992464 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:38:12.998862 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:38:13.002163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:38:13.005601 0 11 4 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
1485 12:38:13.012462 0 11 8 | B1->B0 | 4343 4545 | 1 0 | (0 0) (0 0)
1486 12:38:13.015716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:38:13.019001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:38:13.025498 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 12:38:13.028676 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 12:38:13.032404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 12:38:13.038973 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1492 12:38:13.042221 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1493 12:38:13.045834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:38:13.052257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:38:13.055435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:38:13.059284 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:38:13.065713 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:38:13.069125 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:38:13.072372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:38:13.079371 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:38:13.082545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:38:13.085840 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:38:13.088807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:38:13.095559 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:38:13.099205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:38:13.102346 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:38:13.108878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:38:13.112363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1509 12:38:13.115520 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:38:13.119007 Total UI for P1: 0, mck2ui 16
1511 12:38:13.122353 best dqsien dly found for B0: ( 0, 14, 4)
1512 12:38:13.125806 Total UI for P1: 0, mck2ui 16
1513 12:38:13.129320 best dqsien dly found for B1: ( 0, 14, 4)
1514 12:38:13.132397 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1515 12:38:13.135821 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1516 12:38:13.135939
1517 12:38:13.142501 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1518 12:38:13.145672 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1519 12:38:13.145760 [Gating] SW calibration Done
1520 12:38:13.145827 ==
1521 12:38:13.149006 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 12:38:13.155933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 12:38:13.156038 ==
1524 12:38:13.156107 RX Vref Scan: 0
1525 12:38:13.156184
1526 12:38:13.159479 RX Vref 0 -> 0, step: 1
1527 12:38:13.159565
1528 12:38:13.162581 RX Delay -130 -> 252, step: 16
1529 12:38:13.165897 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1530 12:38:13.169333 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1531 12:38:13.172768 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1532 12:38:13.179207 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1533 12:38:13.182796 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1534 12:38:13.186158 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1535 12:38:13.189386 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1536 12:38:13.192555 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1537 12:38:13.199681 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1538 12:38:13.202936 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1539 12:38:13.206166 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1540 12:38:13.209195 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1541 12:38:13.212956 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1542 12:38:13.219499 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1543 12:38:13.222778 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1544 12:38:13.226245 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1545 12:38:13.226338 ==
1546 12:38:13.229322 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 12:38:13.232699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 12:38:13.232788 ==
1549 12:38:13.236394 DQS Delay:
1550 12:38:13.236481 DQS0 = 0, DQS1 = 0
1551 12:38:13.236547 DQM Delay:
1552 12:38:13.239747 DQM0 = 92, DQM1 = 82
1553 12:38:13.239833 DQ Delay:
1554 12:38:13.243103 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1555 12:38:13.246325 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1556 12:38:13.249715 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1557 12:38:13.252940 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1558 12:38:13.253079
1559 12:38:13.253168
1560 12:38:13.253231 ==
1561 12:38:13.256239 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 12:38:13.263120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 12:38:13.263226 ==
1564 12:38:13.263295
1565 12:38:13.263357
1566 12:38:13.263415 TX Vref Scan disable
1567 12:38:13.266376 == TX Byte 0 ==
1568 12:38:13.270301 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1569 12:38:13.276557 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1570 12:38:13.276654 == TX Byte 1 ==
1571 12:38:13.280424 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1572 12:38:13.283314 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1573 12:38:13.286624 ==
1574 12:38:13.290125 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 12:38:13.293320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 12:38:13.293410 ==
1577 12:38:13.305829 TX Vref=22, minBit 8, minWin=27, winSum=445
1578 12:38:13.308888 TX Vref=24, minBit 10, minWin=27, winSum=450
1579 12:38:13.312389 TX Vref=26, minBit 10, minWin=27, winSum=453
1580 12:38:13.315983 TX Vref=28, minBit 15, minWin=27, winSum=457
1581 12:38:13.318954 TX Vref=30, minBit 8, minWin=27, winSum=457
1582 12:38:13.325515 TX Vref=32, minBit 8, minWin=27, winSum=455
1583 12:38:13.328875 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 28
1584 12:38:13.328974
1585 12:38:13.332075 Final TX Range 1 Vref 28
1586 12:38:13.332180
1587 12:38:13.332276 ==
1588 12:38:13.335478 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 12:38:13.338862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 12:38:13.341921 ==
1591 12:38:13.342087
1592 12:38:13.342219
1593 12:38:13.342313 TX Vref Scan disable
1594 12:38:13.345967 == TX Byte 0 ==
1595 12:38:13.349139 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1596 12:38:13.352206 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1597 12:38:13.356217 == TX Byte 1 ==
1598 12:38:13.359966 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1599 12:38:13.362898 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1600 12:38:13.363022
1601 12:38:13.366519 [DATLAT]
1602 12:38:13.366627 Freq=800, CH1 RK0
1603 12:38:13.366717
1604 12:38:13.369754 DATLAT Default: 0xa
1605 12:38:13.369876 0, 0xFFFF, sum = 0
1606 12:38:13.373220 1, 0xFFFF, sum = 0
1607 12:38:13.373341 2, 0xFFFF, sum = 0
1608 12:38:13.376389 3, 0xFFFF, sum = 0
1609 12:38:13.376487 4, 0xFFFF, sum = 0
1610 12:38:13.379889 5, 0xFFFF, sum = 0
1611 12:38:13.379994 6, 0xFFFF, sum = 0
1612 12:38:13.383394 7, 0xFFFF, sum = 0
1613 12:38:13.383489 8, 0xFFFF, sum = 0
1614 12:38:13.386374 9, 0x0, sum = 1
1615 12:38:13.386465 10, 0x0, sum = 2
1616 12:38:13.389833 11, 0x0, sum = 3
1617 12:38:13.389996 12, 0x0, sum = 4
1618 12:38:13.393303 best_step = 10
1619 12:38:13.393407
1620 12:38:13.393480 ==
1621 12:38:13.396418 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 12:38:13.400044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 12:38:13.400187 ==
1624 12:38:13.400263 RX Vref Scan: 1
1625 12:38:13.400326
1626 12:38:13.403408 Set Vref Range= 32 -> 127
1627 12:38:13.403500
1628 12:38:13.406953 RX Vref 32 -> 127, step: 1
1629 12:38:13.407042
1630 12:38:13.409844 RX Delay -95 -> 252, step: 8
1631 12:38:13.409983
1632 12:38:13.413418 Set Vref, RX VrefLevel [Byte0]: 32
1633 12:38:13.416647 [Byte1]: 32
1634 12:38:13.416736
1635 12:38:13.420038 Set Vref, RX VrefLevel [Byte0]: 33
1636 12:38:13.423370 [Byte1]: 33
1637 12:38:13.423459
1638 12:38:13.427063 Set Vref, RX VrefLevel [Byte0]: 34
1639 12:38:13.429931 [Byte1]: 34
1640 12:38:13.433482
1641 12:38:13.433572 Set Vref, RX VrefLevel [Byte0]: 35
1642 12:38:13.437099 [Byte1]: 35
1643 12:38:13.441377
1644 12:38:13.441471 Set Vref, RX VrefLevel [Byte0]: 36
1645 12:38:13.444575 [Byte1]: 36
1646 12:38:13.448892
1647 12:38:13.448984 Set Vref, RX VrefLevel [Byte0]: 37
1648 12:38:13.451996 [Byte1]: 37
1649 12:38:13.456571
1650 12:38:13.456669 Set Vref, RX VrefLevel [Byte0]: 38
1651 12:38:13.459877 [Byte1]: 38
1652 12:38:13.463857
1653 12:38:13.463950 Set Vref, RX VrefLevel [Byte0]: 39
1654 12:38:13.467396 [Byte1]: 39
1655 12:38:13.471818
1656 12:38:13.471911 Set Vref, RX VrefLevel [Byte0]: 40
1657 12:38:13.474775 [Byte1]: 40
1658 12:38:13.478944
1659 12:38:13.479073 Set Vref, RX VrefLevel [Byte0]: 41
1660 12:38:13.482440 [Byte1]: 41
1661 12:38:13.486722
1662 12:38:13.486815 Set Vref, RX VrefLevel [Byte0]: 42
1663 12:38:13.490074 [Byte1]: 42
1664 12:38:13.494290
1665 12:38:13.494413 Set Vref, RX VrefLevel [Byte0]: 43
1666 12:38:13.497517 [Byte1]: 43
1667 12:38:13.502003
1668 12:38:13.502097 Set Vref, RX VrefLevel [Byte0]: 44
1669 12:38:13.505131 [Byte1]: 44
1670 12:38:13.509701
1671 12:38:13.509823 Set Vref, RX VrefLevel [Byte0]: 45
1672 12:38:13.513155 [Byte1]: 45
1673 12:38:13.516829
1674 12:38:13.516949 Set Vref, RX VrefLevel [Byte0]: 46
1675 12:38:13.520553 [Byte1]: 46
1676 12:38:13.524781
1677 12:38:13.524877 Set Vref, RX VrefLevel [Byte0]: 47
1678 12:38:13.527826 [Byte1]: 47
1679 12:38:13.532475
1680 12:38:13.532573 Set Vref, RX VrefLevel [Byte0]: 48
1681 12:38:13.535354 [Byte1]: 48
1682 12:38:13.539818
1683 12:38:13.539940 Set Vref, RX VrefLevel [Byte0]: 49
1684 12:38:13.543306 [Byte1]: 49
1685 12:38:13.547685
1686 12:38:13.547778 Set Vref, RX VrefLevel [Byte0]: 50
1687 12:38:13.550816 [Byte1]: 50
1688 12:38:13.555134
1689 12:38:13.555236 Set Vref, RX VrefLevel [Byte0]: 51
1690 12:38:13.558387 [Byte1]: 51
1691 12:38:13.562513
1692 12:38:13.562609 Set Vref, RX VrefLevel [Byte0]: 52
1693 12:38:13.565958 [Byte1]: 52
1694 12:38:13.570126
1695 12:38:13.570223 Set Vref, RX VrefLevel [Byte0]: 53
1696 12:38:13.573583 [Byte1]: 53
1697 12:38:13.577740
1698 12:38:13.577826 Set Vref, RX VrefLevel [Byte0]: 54
1699 12:38:13.581027 [Byte1]: 54
1700 12:38:13.585553
1701 12:38:13.585680 Set Vref, RX VrefLevel [Byte0]: 55
1702 12:38:13.588609 [Byte1]: 55
1703 12:38:13.593172
1704 12:38:13.593303 Set Vref, RX VrefLevel [Byte0]: 56
1705 12:38:13.596238 [Byte1]: 56
1706 12:38:13.601112
1707 12:38:13.601210 Set Vref, RX VrefLevel [Byte0]: 57
1708 12:38:13.604168 [Byte1]: 57
1709 12:38:13.608228
1710 12:38:13.608318 Set Vref, RX VrefLevel [Byte0]: 58
1711 12:38:13.611871 [Byte1]: 58
1712 12:38:13.615875
1713 12:38:13.615970 Set Vref, RX VrefLevel [Byte0]: 59
1714 12:38:13.619420 [Byte1]: 59
1715 12:38:13.623469
1716 12:38:13.623559 Set Vref, RX VrefLevel [Byte0]: 60
1717 12:38:13.626981 [Byte1]: 60
1718 12:38:13.631233
1719 12:38:13.631326 Set Vref, RX VrefLevel [Byte0]: 61
1720 12:38:13.634170 [Byte1]: 61
1721 12:38:13.639129
1722 12:38:13.639227 Set Vref, RX VrefLevel [Byte0]: 62
1723 12:38:13.641996 [Byte1]: 62
1724 12:38:13.646333
1725 12:38:13.646426 Set Vref, RX VrefLevel [Byte0]: 63
1726 12:38:13.649345 [Byte1]: 63
1727 12:38:13.653824
1728 12:38:13.653931 Set Vref, RX VrefLevel [Byte0]: 64
1729 12:38:13.657193 [Byte1]: 64
1730 12:38:13.661162
1731 12:38:13.661258 Set Vref, RX VrefLevel [Byte0]: 65
1732 12:38:13.664766 [Byte1]: 65
1733 12:38:13.669153
1734 12:38:13.669253 Set Vref, RX VrefLevel [Byte0]: 66
1735 12:38:13.672285 [Byte1]: 66
1736 12:38:13.676652
1737 12:38:13.676748 Set Vref, RX VrefLevel [Byte0]: 67
1738 12:38:13.680051 [Byte1]: 67
1739 12:38:13.684644
1740 12:38:13.684739 Set Vref, RX VrefLevel [Byte0]: 68
1741 12:38:13.687241 [Byte1]: 68
1742 12:38:13.692227
1743 12:38:13.692333 Set Vref, RX VrefLevel [Byte0]: 69
1744 12:38:13.695194 [Byte1]: 69
1745 12:38:13.699738
1746 12:38:13.699848 Set Vref, RX VrefLevel [Byte0]: 70
1747 12:38:13.702811 [Byte1]: 70
1748 12:38:13.707211
1749 12:38:13.707308 Set Vref, RX VrefLevel [Byte0]: 71
1750 12:38:13.710406 [Byte1]: 71
1751 12:38:13.714493
1752 12:38:13.714587 Set Vref, RX VrefLevel [Byte0]: 72
1753 12:38:13.718150 [Byte1]: 72
1754 12:38:13.721919
1755 12:38:13.722052 Set Vref, RX VrefLevel [Byte0]: 73
1756 12:38:13.725707 [Byte1]: 73
1757 12:38:13.729723
1758 12:38:13.729817 Set Vref, RX VrefLevel [Byte0]: 74
1759 12:38:13.732999 [Byte1]: 74
1760 12:38:13.737430
1761 12:38:13.737591 Set Vref, RX VrefLevel [Byte0]: 75
1762 12:38:13.740637 [Byte1]: 75
1763 12:38:13.745543
1764 12:38:13.745638 Final RX Vref Byte 0 = 52 to rank0
1765 12:38:13.748360 Final RX Vref Byte 1 = 62 to rank0
1766 12:38:13.751424 Final RX Vref Byte 0 = 52 to rank1
1767 12:38:13.754738 Final RX Vref Byte 1 = 62 to rank1==
1768 12:38:13.758242 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 12:38:13.764607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 12:38:13.764718 ==
1771 12:38:13.764810 DQS Delay:
1772 12:38:13.764903 DQS0 = 0, DQS1 = 0
1773 12:38:13.768421 DQM Delay:
1774 12:38:13.768525 DQM0 = 92, DQM1 = 84
1775 12:38:13.771412 DQ Delay:
1776 12:38:13.775086 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1777 12:38:13.778103 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1778 12:38:13.781620 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1779 12:38:13.784863 DQ12 =96, DQ13 =88, DQ14 =88, DQ15 =88
1780 12:38:13.785012
1781 12:38:13.785110
1782 12:38:13.791480 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1783 12:38:13.794966 CH1 RK0: MR19=606, MR18=2D4B
1784 12:38:13.801561 CH1_RK0: MR19=0x606, MR18=0x2D4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1785 12:38:13.801674
1786 12:38:13.805069 ----->DramcWriteLeveling(PI) begin...
1787 12:38:13.805176 ==
1788 12:38:13.808479 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 12:38:13.811883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:38:13.811989 ==
1791 12:38:13.814837 Write leveling (Byte 0): 28 => 28
1792 12:38:13.818644 Write leveling (Byte 1): 29 => 29
1793 12:38:13.821694 DramcWriteLeveling(PI) end<-----
1794 12:38:13.821821
1795 12:38:13.821915 ==
1796 12:38:13.825076 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 12:38:13.828446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 12:38:13.828572 ==
1799 12:38:13.832014 [Gating] SW mode calibration
1800 12:38:13.838520 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 12:38:13.845461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 12:38:13.848680 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1803 12:38:13.851783 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 12:38:13.858814 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:38:13.861903 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:38:13.865171 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:38:13.872365 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:38:13.875118 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:38:13.878808 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:38:13.885165 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:38:13.888568 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:38:13.891984 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:38:13.895262 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:38:13.902204 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:38:13.905228 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:38:13.908700 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:38:13.915259 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:38:13.919031 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1819 12:38:13.921910 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1820 12:38:13.928814 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:38:13.931894 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:38:13.935497 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:38:13.942169 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:38:13.945484 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:38:13.948787 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:38:13.955380 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:38:13.959167 0 9 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1828 12:38:13.962088 0 9 8 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 1)
1829 12:38:13.965571 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 12:38:13.972429 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 12:38:13.975879 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 12:38:13.978875 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:38:13.985559 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:38:13.989322 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:38:13.992581 0 10 4 | B1->B0 | 2c2c 3131 | 1 0 | (1 1) (0 0)
1836 12:38:13.999097 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1837 12:38:14.002340 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:38:14.005447 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:38:14.012212 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:38:14.015855 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:38:14.018943 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:38:14.025614 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:38:14.028876 0 11 4 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
1844 12:38:14.032585 0 11 8 | B1->B0 | 4646 4140 | 0 1 | (0 0) (1 1)
1845 12:38:14.038913 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:38:14.042738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:38:14.045730 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 12:38:14.049288 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:38:14.055854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:38:14.059487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:38:14.062647 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 12:38:14.069171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1853 12:38:14.072597 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:38:14.076036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:38:14.082901 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:38:14.086554 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:38:14.089166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:38:14.095993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:38:14.099347 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:38:14.103023 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:38:14.109423 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:38:14.112939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:38:14.116465 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:38:14.119336 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:38:14.125910 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:38:14.129338 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1867 12:38:14.132754 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 12:38:14.139255 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:38:14.142837 Total UI for P1: 0, mck2ui 16
1870 12:38:14.146050 best dqsien dly found for B0: ( 0, 14, 4)
1871 12:38:14.146141 Total UI for P1: 0, mck2ui 16
1872 12:38:14.152885 best dqsien dly found for B1: ( 0, 14, 2)
1873 12:38:14.155968 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1874 12:38:14.159566 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1875 12:38:14.159660
1876 12:38:14.163096 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 12:38:14.166141 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1878 12:38:14.169679 [Gating] SW calibration Done
1879 12:38:14.169772 ==
1880 12:38:14.173123 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 12:38:14.176387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 12:38:14.176475 ==
1883 12:38:14.179367 RX Vref Scan: 0
1884 12:38:14.179453
1885 12:38:14.179520 RX Vref 0 -> 0, step: 1
1886 12:38:14.179584
1887 12:38:14.182879 RX Delay -130 -> 252, step: 16
1888 12:38:14.186507 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1889 12:38:14.193182 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1890 12:38:14.196164 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1891 12:38:14.199487 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1892 12:38:14.203003 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1893 12:38:14.206230 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1894 12:38:14.212796 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1895 12:38:14.216164 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1896 12:38:14.219648 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1897 12:38:14.222991 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1898 12:38:14.226569 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1899 12:38:14.229912 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1900 12:38:14.236393 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1901 12:38:14.239938 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1902 12:38:14.243283 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1903 12:38:14.246730 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1904 12:38:14.246819 ==
1905 12:38:14.249720 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 12:38:14.256792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 12:38:14.256896 ==
1908 12:38:14.256965 DQS Delay:
1909 12:38:14.259804 DQS0 = 0, DQS1 = 0
1910 12:38:14.259889 DQM Delay:
1911 12:38:14.259954 DQM0 = 90, DQM1 = 84
1912 12:38:14.263531 DQ Delay:
1913 12:38:14.266898 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1914 12:38:14.269929 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1915 12:38:14.273378 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1916 12:38:14.276363 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1917 12:38:14.276449
1918 12:38:14.276516
1919 12:38:14.276576 ==
1920 12:38:14.279750 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 12:38:14.283584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 12:38:14.283672 ==
1923 12:38:14.283739
1924 12:38:14.283799
1925 12:38:14.286779 TX Vref Scan disable
1926 12:38:14.286864 == TX Byte 0 ==
1927 12:38:14.293216 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1928 12:38:14.296535 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1929 12:38:14.296625 == TX Byte 1 ==
1930 12:38:14.303461 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1931 12:38:14.306748 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1932 12:38:14.306839 ==
1933 12:38:14.309998 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 12:38:14.313292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 12:38:14.313395 ==
1936 12:38:14.326943 TX Vref=22, minBit 8, minWin=27, winSum=451
1937 12:38:14.330222 TX Vref=24, minBit 13, minWin=27, winSum=452
1938 12:38:14.333790 TX Vref=26, minBit 13, minWin=27, winSum=455
1939 12:38:14.337179 TX Vref=28, minBit 8, minWin=28, winSum=459
1940 12:38:14.340340 TX Vref=30, minBit 13, minWin=27, winSum=459
1941 12:38:14.347170 TX Vref=32, minBit 8, minWin=28, winSum=459
1942 12:38:14.350295 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1943 12:38:14.350388
1944 12:38:14.353901 Final TX Range 1 Vref 28
1945 12:38:14.354052
1946 12:38:14.354119 ==
1947 12:38:14.356971 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 12:38:14.360405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 12:38:14.360496 ==
1950 12:38:14.363842
1951 12:38:14.363957
1952 12:38:14.364055 TX Vref Scan disable
1953 12:38:14.367076 == TX Byte 0 ==
1954 12:38:14.370355 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1955 12:38:14.373748 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1956 12:38:14.376983 == TX Byte 1 ==
1957 12:38:14.380476 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 12:38:14.383798 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 12:38:14.387064
1960 12:38:14.387182 [DATLAT]
1961 12:38:14.387279 Freq=800, CH1 RK1
1962 12:38:14.387342
1963 12:38:14.390485 DATLAT Default: 0xa
1964 12:38:14.390572 0, 0xFFFF, sum = 0
1965 12:38:14.393832 1, 0xFFFF, sum = 0
1966 12:38:14.393965 2, 0xFFFF, sum = 0
1967 12:38:14.397311 3, 0xFFFF, sum = 0
1968 12:38:14.397420 4, 0xFFFF, sum = 0
1969 12:38:14.400703 5, 0xFFFF, sum = 0
1970 12:38:14.400790 6, 0xFFFF, sum = 0
1971 12:38:14.404285 7, 0xFFFF, sum = 0
1972 12:38:14.404371 8, 0xFFFF, sum = 0
1973 12:38:14.407408 9, 0x0, sum = 1
1974 12:38:14.407496 10, 0x0, sum = 2
1975 12:38:14.410546 11, 0x0, sum = 3
1976 12:38:14.410632 12, 0x0, sum = 4
1977 12:38:14.413869 best_step = 10
1978 12:38:14.414033
1979 12:38:14.414101 ==
1980 12:38:14.417354 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:38:14.420728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:38:14.420816 ==
1983 12:38:14.424112 RX Vref Scan: 0
1984 12:38:14.424198
1985 12:38:14.424265 RX Vref 0 -> 0, step: 1
1986 12:38:14.424329
1987 12:38:14.427633 RX Delay -95 -> 252, step: 8
1988 12:38:14.434376 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1989 12:38:14.437474 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1990 12:38:14.440688 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1991 12:38:14.444071 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1992 12:38:14.447403 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1993 12:38:14.450949 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1994 12:38:14.457652 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1995 12:38:14.461367 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1996 12:38:14.464355 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1997 12:38:14.468130 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1998 12:38:14.470763 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1999 12:38:14.477957 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2000 12:38:14.480895 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2001 12:38:14.484420 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2002 12:38:14.487370 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2003 12:38:14.491141 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2004 12:38:14.494365 ==
2005 12:38:14.494456 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 12:38:14.500685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 12:38:14.500808 ==
2008 12:38:14.500906 DQS Delay:
2009 12:38:14.504124 DQS0 = 0, DQS1 = 0
2010 12:38:14.504211 DQM Delay:
2011 12:38:14.507291 DQM0 = 92, DQM1 = 85
2012 12:38:14.507379 DQ Delay:
2013 12:38:14.511124 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2014 12:38:14.514366 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2015 12:38:14.517538 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2016 12:38:14.521025 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2017 12:38:14.521115
2018 12:38:14.521182
2019 12:38:14.527533 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2020 12:38:14.530850 CH1 RK1: MR19=606, MR18=3C12
2021 12:38:14.537897 CH1_RK1: MR19=0x606, MR18=0x3C12, DQSOSC=394, MR23=63, INC=95, DEC=63
2022 12:38:14.541176 [RxdqsGatingPostProcess] freq 800
2023 12:38:14.544478 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 12:38:14.547544 Pre-setting of DQS Precalculation
2025 12:38:14.554244 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 12:38:14.560745 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 12:38:14.567979 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 12:38:14.568116
2029 12:38:14.568202
2030 12:38:14.570796 [Calibration Summary] 1600 Mbps
2031 12:38:14.570883 CH 0, Rank 0
2032 12:38:14.573904 SW Impedance : PASS
2033 12:38:14.577464 DUTY Scan : NO K
2034 12:38:14.577553 ZQ Calibration : PASS
2035 12:38:14.580631 Jitter Meter : NO K
2036 12:38:14.584131 CBT Training : PASS
2037 12:38:14.584219 Write leveling : PASS
2038 12:38:14.587273 RX DQS gating : PASS
2039 12:38:14.591217 RX DQ/DQS(RDDQC) : PASS
2040 12:38:14.591324 TX DQ/DQS : PASS
2041 12:38:14.594178 RX DATLAT : PASS
2042 12:38:14.597593 RX DQ/DQS(Engine): PASS
2043 12:38:14.597679 TX OE : NO K
2044 12:38:14.600822 All Pass.
2045 12:38:14.600907
2046 12:38:14.600974 CH 0, Rank 1
2047 12:38:14.604373 SW Impedance : PASS
2048 12:38:14.604458 DUTY Scan : NO K
2049 12:38:14.607388 ZQ Calibration : PASS
2050 12:38:14.611159 Jitter Meter : NO K
2051 12:38:14.611248 CBT Training : PASS
2052 12:38:14.614301 Write leveling : PASS
2053 12:38:14.614395 RX DQS gating : PASS
2054 12:38:14.617616 RX DQ/DQS(RDDQC) : PASS
2055 12:38:14.621234 TX DQ/DQS : PASS
2056 12:38:14.621327 RX DATLAT : PASS
2057 12:38:14.624408 RX DQ/DQS(Engine): PASS
2058 12:38:14.627620 TX OE : NO K
2059 12:38:14.627709 All Pass.
2060 12:38:14.627776
2061 12:38:14.627835 CH 1, Rank 0
2062 12:38:14.630931 SW Impedance : PASS
2063 12:38:14.634400 DUTY Scan : NO K
2064 12:38:14.634487 ZQ Calibration : PASS
2065 12:38:14.637905 Jitter Meter : NO K
2066 12:38:14.640905 CBT Training : PASS
2067 12:38:14.640991 Write leveling : PASS
2068 12:38:14.644540 RX DQS gating : PASS
2069 12:38:14.644625 RX DQ/DQS(RDDQC) : PASS
2070 12:38:14.647755 TX DQ/DQS : PASS
2071 12:38:14.651064 RX DATLAT : PASS
2072 12:38:14.651152 RX DQ/DQS(Engine): PASS
2073 12:38:14.654580 TX OE : NO K
2074 12:38:14.654667 All Pass.
2075 12:38:14.654735
2076 12:38:14.657720 CH 1, Rank 1
2077 12:38:14.657806 SW Impedance : PASS
2078 12:38:14.661334 DUTY Scan : NO K
2079 12:38:14.664567 ZQ Calibration : PASS
2080 12:38:14.664654 Jitter Meter : NO K
2081 12:38:14.667648 CBT Training : PASS
2082 12:38:14.671114 Write leveling : PASS
2083 12:38:14.671201 RX DQS gating : PASS
2084 12:38:14.674460 RX DQ/DQS(RDDQC) : PASS
2085 12:38:14.677877 TX DQ/DQS : PASS
2086 12:38:14.677973 RX DATLAT : PASS
2087 12:38:14.681060 RX DQ/DQS(Engine): PASS
2088 12:38:14.684580 TX OE : NO K
2089 12:38:14.684668 All Pass.
2090 12:38:14.684736
2091 12:38:14.684798 DramC Write-DBI off
2092 12:38:14.687674 PER_BANK_REFRESH: Hybrid Mode
2093 12:38:14.690962 TX_TRACKING: ON
2094 12:38:14.694431 [GetDramInforAfterCalByMRR] Vendor 6.
2095 12:38:14.697912 [GetDramInforAfterCalByMRR] Revision 606.
2096 12:38:14.701411 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 12:38:14.701502 MR0 0x3b3b
2098 12:38:14.701568 MR8 0x5151
2099 12:38:14.707905 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 12:38:14.708003
2101 12:38:14.708070 MR0 0x3b3b
2102 12:38:14.708132 MR8 0x5151
2103 12:38:14.711710 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:38:14.711796
2105 12:38:14.721258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 12:38:14.724622 [FAST_K] Save calibration result to emmc
2107 12:38:14.728151 [FAST_K] Save calibration result to emmc
2108 12:38:14.731118 dram_init: config_dvfs: 1
2109 12:38:14.734331 dramc_set_vcore_voltage set vcore to 662500
2110 12:38:14.737743 Read voltage for 1200, 2
2111 12:38:14.737834 Vio18 = 0
2112 12:38:14.737901 Vcore = 662500
2113 12:38:14.741299 Vdram = 0
2114 12:38:14.741384 Vddq = 0
2115 12:38:14.741450 Vmddr = 0
2116 12:38:14.747768 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 12:38:14.751321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 12:38:14.754619 MEM_TYPE=3, freq_sel=15
2119 12:38:14.758015 sv_algorithm_assistance_LP4_1600
2120 12:38:14.761130 ============ PULL DRAM RESETB DOWN ============
2121 12:38:14.764730 ========== PULL DRAM RESETB DOWN end =========
2122 12:38:14.771396 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 12:38:14.774705 ===================================
2124 12:38:14.777950 LPDDR4 DRAM CONFIGURATION
2125 12:38:14.781086 ===================================
2126 12:38:14.781177 EX_ROW_EN[0] = 0x0
2127 12:38:14.784598 EX_ROW_EN[1] = 0x0
2128 12:38:14.784686 LP4Y_EN = 0x0
2129 12:38:14.787672 WORK_FSP = 0x0
2130 12:38:14.787757 WL = 0x4
2131 12:38:14.790842 RL = 0x4
2132 12:38:14.790926 BL = 0x2
2133 12:38:14.794222 RPST = 0x0
2134 12:38:14.794321 RD_PRE = 0x0
2135 12:38:14.797581 WR_PRE = 0x1
2136 12:38:14.797667 WR_PST = 0x0
2137 12:38:14.801193 DBI_WR = 0x0
2138 12:38:14.801279 DBI_RD = 0x0
2139 12:38:14.804196 OTF = 0x1
2140 12:38:14.807803 ===================================
2141 12:38:14.811388 ===================================
2142 12:38:14.811478 ANA top config
2143 12:38:14.814675 ===================================
2144 12:38:14.817924 DLL_ASYNC_EN = 0
2145 12:38:14.821309 ALL_SLAVE_EN = 0
2146 12:38:14.824255 NEW_RANK_MODE = 1
2147 12:38:14.824345 DLL_IDLE_MODE = 1
2148 12:38:14.827876 LP45_APHY_COMB_EN = 1
2149 12:38:14.830994 TX_ODT_DIS = 1
2150 12:38:14.834511 NEW_8X_MODE = 1
2151 12:38:14.837880 ===================================
2152 12:38:14.840940 ===================================
2153 12:38:14.844540 data_rate = 2400
2154 12:38:14.844631 CKR = 1
2155 12:38:14.847615 DQ_P2S_RATIO = 8
2156 12:38:14.851168 ===================================
2157 12:38:14.854366 CA_P2S_RATIO = 8
2158 12:38:14.857654 DQ_CA_OPEN = 0
2159 12:38:14.861155 DQ_SEMI_OPEN = 0
2160 12:38:14.864965 CA_SEMI_OPEN = 0
2161 12:38:14.865055 CA_FULL_RATE = 0
2162 12:38:14.867836 DQ_CKDIV4_EN = 0
2163 12:38:14.870970 CA_CKDIV4_EN = 0
2164 12:38:14.874455 CA_PREDIV_EN = 0
2165 12:38:14.877953 PH8_DLY = 17
2166 12:38:14.881198 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 12:38:14.881287 DQ_AAMCK_DIV = 4
2168 12:38:14.884390 CA_AAMCK_DIV = 4
2169 12:38:14.887783 CA_ADMCK_DIV = 4
2170 12:38:14.891057 DQ_TRACK_CA_EN = 0
2171 12:38:14.894620 CA_PICK = 1200
2172 12:38:14.897929 CA_MCKIO = 1200
2173 12:38:14.898026 MCKIO_SEMI = 0
2174 12:38:14.901553 PLL_FREQ = 2366
2175 12:38:14.904692 DQ_UI_PI_RATIO = 32
2176 12:38:14.907690 CA_UI_PI_RATIO = 0
2177 12:38:14.911562 ===================================
2178 12:38:14.914551 ===================================
2179 12:38:14.917678 memory_type:LPDDR4
2180 12:38:14.917765 GP_NUM : 10
2181 12:38:14.921344 SRAM_EN : 1
2182 12:38:14.924771 MD32_EN : 0
2183 12:38:14.928025 ===================================
2184 12:38:14.928114 [ANA_INIT] >>>>>>>>>>>>>>
2185 12:38:14.931202 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 12:38:14.934607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 12:38:14.937672 ===================================
2188 12:38:14.941205 data_rate = 2400,PCW = 0X5b00
2189 12:38:14.944302 ===================================
2190 12:38:14.947874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:38:14.954404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 12:38:14.957577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 12:38:14.964545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 12:38:14.967846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 12:38:14.971119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 12:38:14.971209 [ANA_INIT] flow start
2197 12:38:14.974858 [ANA_INIT] PLL >>>>>>>>
2198 12:38:14.978141 [ANA_INIT] PLL <<<<<<<<
2199 12:38:14.978227 [ANA_INIT] MIDPI >>>>>>>>
2200 12:38:14.981305 [ANA_INIT] MIDPI <<<<<<<<
2201 12:38:14.984955 [ANA_INIT] DLL >>>>>>>>
2202 12:38:14.987825 [ANA_INIT] DLL <<<<<<<<
2203 12:38:14.987915 [ANA_INIT] flow end
2204 12:38:14.991268 ============ LP4 DIFF to SE enter ============
2205 12:38:14.998159 ============ LP4 DIFF to SE exit ============
2206 12:38:14.998263 [ANA_INIT] <<<<<<<<<<<<<
2207 12:38:15.001275 [Flow] Enable top DCM control >>>>>
2208 12:38:15.004514 [Flow] Enable top DCM control <<<<<
2209 12:38:15.008141 Enable DLL master slave shuffle
2210 12:38:15.014572 ==============================================================
2211 12:38:15.014695 Gating Mode config
2212 12:38:15.021186 ==============================================================
2213 12:38:15.024375 Config description:
2214 12:38:15.031368 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 12:38:15.037897 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 12:38:15.044527 SELPH_MODE 0: By rank 1: By Phase
2217 12:38:15.047844 ==============================================================
2218 12:38:15.051507 GAT_TRACK_EN = 1
2219 12:38:15.054827 RX_GATING_MODE = 2
2220 12:38:15.058179 RX_GATING_TRACK_MODE = 2
2221 12:38:15.061418 SELPH_MODE = 1
2222 12:38:15.064940 PICG_EARLY_EN = 1
2223 12:38:15.068132 VALID_LAT_VALUE = 1
2224 12:38:15.074973 ==============================================================
2225 12:38:15.077908 Enter into Gating configuration >>>>
2226 12:38:15.081855 Exit from Gating configuration <<<<
2227 12:38:15.081980 Enter into DVFS_PRE_config >>>>>
2228 12:38:15.095161 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 12:38:15.098351 Exit from DVFS_PRE_config <<<<<
2230 12:38:15.101404 Enter into PICG configuration >>>>
2231 12:38:15.105067 Exit from PICG configuration <<<<
2232 12:38:15.105161 [RX_INPUT] configuration >>>>>
2233 12:38:15.107969 [RX_INPUT] configuration <<<<<
2234 12:38:15.114694 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 12:38:15.117998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 12:38:15.125069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 12:38:15.131562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 12:38:15.137974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 12:38:15.145123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 12:38:15.148372 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 12:38:15.151365 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 12:38:15.155143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 12:38:15.161617 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 12:38:15.165211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 12:38:15.168564 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 12:38:15.171648 ===================================
2247 12:38:15.175028 LPDDR4 DRAM CONFIGURATION
2248 12:38:15.178450 ===================================
2249 12:38:15.181936 EX_ROW_EN[0] = 0x0
2250 12:38:15.182034 EX_ROW_EN[1] = 0x0
2251 12:38:15.185233 LP4Y_EN = 0x0
2252 12:38:15.185320 WORK_FSP = 0x0
2253 12:38:15.188206 WL = 0x4
2254 12:38:15.188293 RL = 0x4
2255 12:38:15.191969 BL = 0x2
2256 12:38:15.192055 RPST = 0x0
2257 12:38:15.195115 RD_PRE = 0x0
2258 12:38:15.195200 WR_PRE = 0x1
2259 12:38:15.198364 WR_PST = 0x0
2260 12:38:15.198454 DBI_WR = 0x0
2261 12:38:15.202170 DBI_RD = 0x0
2262 12:38:15.202256 OTF = 0x1
2263 12:38:15.205183 ===================================
2264 12:38:15.208574 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 12:38:15.215535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 12:38:15.218485 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 12:38:15.221847 ===================================
2268 12:38:15.225213 LPDDR4 DRAM CONFIGURATION
2269 12:38:15.228830 ===================================
2270 12:38:15.228923 EX_ROW_EN[0] = 0x10
2271 12:38:15.231595 EX_ROW_EN[1] = 0x0
2272 12:38:15.231681 LP4Y_EN = 0x0
2273 12:38:15.235017 WORK_FSP = 0x0
2274 12:38:15.238517 WL = 0x4
2275 12:38:15.238605 RL = 0x4
2276 12:38:15.242095 BL = 0x2
2277 12:38:15.242181 RPST = 0x0
2278 12:38:15.245297 RD_PRE = 0x0
2279 12:38:15.245382 WR_PRE = 0x1
2280 12:38:15.248642 WR_PST = 0x0
2281 12:38:15.248728 DBI_WR = 0x0
2282 12:38:15.251652 DBI_RD = 0x0
2283 12:38:15.251738 OTF = 0x1
2284 12:38:15.255196 ===================================
2285 12:38:15.261979 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 12:38:15.262095 ==
2287 12:38:15.264984 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 12:38:15.268349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 12:38:15.268439 ==
2290 12:38:15.272125 [Duty_Offset_Calibration]
2291 12:38:15.275350 B0:2 B1:0 CA:1
2292 12:38:15.275439
2293 12:38:15.278325 [DutyScan_Calibration_Flow] k_type=0
2294 12:38:15.285324
2295 12:38:15.285437 ==CLK 0==
2296 12:38:15.289003 Final CLK duty delay cell = -4
2297 12:38:15.292180 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2298 12:38:15.295680 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2299 12:38:15.298770 [-4] AVG Duty = 4953%(X100)
2300 12:38:15.298855
2301 12:38:15.302212 CH0 CLK Duty spec in!! Max-Min= 156%
2302 12:38:15.305821 [DutyScan_Calibration_Flow] ====Done====
2303 12:38:15.305936
2304 12:38:15.309377 [DutyScan_Calibration_Flow] k_type=1
2305 12:38:15.324101
2306 12:38:15.324248 ==DQS 0 ==
2307 12:38:15.327484 Final DQS duty delay cell = 0
2308 12:38:15.331169 [0] MAX Duty = 5187%(X100), DQS PI = 30
2309 12:38:15.334256 [0] MIN Duty = 4938%(X100), DQS PI = 0
2310 12:38:15.337790 [0] AVG Duty = 5062%(X100)
2311 12:38:15.337876
2312 12:38:15.337947 ==DQS 1 ==
2313 12:38:15.340571 Final DQS duty delay cell = -4
2314 12:38:15.344035 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2315 12:38:15.347481 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2316 12:38:15.350766 [-4] AVG Duty = 5031%(X100)
2317 12:38:15.350851
2318 12:38:15.354384 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2319 12:38:15.354482
2320 12:38:15.357398 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2321 12:38:15.360954 [DutyScan_Calibration_Flow] ====Done====
2322 12:38:15.361042
2323 12:38:15.364143 [DutyScan_Calibration_Flow] k_type=3
2324 12:38:15.381340
2325 12:38:15.381479 ==DQM 0 ==
2326 12:38:15.384425 Final DQM duty delay cell = 0
2327 12:38:15.387808 [0] MAX Duty = 5062%(X100), DQS PI = 24
2328 12:38:15.391292 [0] MIN Duty = 4813%(X100), DQS PI = 2
2329 12:38:15.391441 [0] AVG Duty = 4937%(X100)
2330 12:38:15.394618
2331 12:38:15.394704 ==DQM 1 ==
2332 12:38:15.397799 Final DQM duty delay cell = 0
2333 12:38:15.401366 [0] MAX Duty = 5187%(X100), DQS PI = 46
2334 12:38:15.404440 [0] MIN Duty = 5000%(X100), DQS PI = 22
2335 12:38:15.404528 [0] AVG Duty = 5093%(X100)
2336 12:38:15.407901
2337 12:38:15.410976 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2338 12:38:15.411062
2339 12:38:15.414416 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2340 12:38:15.417658 [DutyScan_Calibration_Flow] ====Done====
2341 12:38:15.417772
2342 12:38:15.421281 [DutyScan_Calibration_Flow] k_type=2
2343 12:38:15.437662
2344 12:38:15.437809 ==DQ 0 ==
2345 12:38:15.441148 Final DQ duty delay cell = -4
2346 12:38:15.444533 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2347 12:38:15.447739 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2348 12:38:15.451155 [-4] AVG Duty = 4968%(X100)
2349 12:38:15.451247
2350 12:38:15.451314 ==DQ 1 ==
2351 12:38:15.454213 Final DQ duty delay cell = 4
2352 12:38:15.457707 [4] MAX Duty = 5093%(X100), DQS PI = 4
2353 12:38:15.460792 [4] MIN Duty = 5031%(X100), DQS PI = 0
2354 12:38:15.460883 [4] AVG Duty = 5062%(X100)
2355 12:38:15.460950
2356 12:38:15.464164 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2357 12:38:15.467591
2358 12:38:15.470918 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2359 12:38:15.474177 [DutyScan_Calibration_Flow] ====Done====
2360 12:38:15.474265 ==
2361 12:38:15.477814 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 12:38:15.481002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 12:38:15.481095 ==
2364 12:38:15.484206 [Duty_Offset_Calibration]
2365 12:38:15.484291 B0:0 B1:-1 CA:2
2366 12:38:15.484356
2367 12:38:15.487390 [DutyScan_Calibration_Flow] k_type=0
2368 12:38:15.497634
2369 12:38:15.497754 ==CLK 0==
2370 12:38:15.501149 Final CLK duty delay cell = 0
2371 12:38:15.504323 [0] MAX Duty = 5156%(X100), DQS PI = 16
2372 12:38:15.507831 [0] MIN Duty = 4938%(X100), DQS PI = 44
2373 12:38:15.507920 [0] AVG Duty = 5047%(X100)
2374 12:38:15.511380
2375 12:38:15.514389 CH1 CLK Duty spec in!! Max-Min= 218%
2376 12:38:15.517822 [DutyScan_Calibration_Flow] ====Done====
2377 12:38:15.517947
2378 12:38:15.521194 [DutyScan_Calibration_Flow] k_type=1
2379 12:38:15.536965
2380 12:38:15.537114 ==DQS 0 ==
2381 12:38:15.540246 Final DQS duty delay cell = 0
2382 12:38:15.543847 [0] MAX Duty = 5093%(X100), DQS PI = 22
2383 12:38:15.546839 [0] MIN Duty = 4969%(X100), DQS PI = 0
2384 12:38:15.546937 [0] AVG Duty = 5031%(X100)
2385 12:38:15.550317
2386 12:38:15.550404 ==DQS 1 ==
2387 12:38:15.553665 Final DQS duty delay cell = 0
2388 12:38:15.557260 [0] MAX Duty = 5156%(X100), DQS PI = 0
2389 12:38:15.560407 [0] MIN Duty = 4844%(X100), DQS PI = 36
2390 12:38:15.560498 [0] AVG Duty = 5000%(X100)
2391 12:38:15.560564
2392 12:38:15.563915 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2393 12:38:15.567143
2394 12:38:15.570346 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2395 12:38:15.573927 [DutyScan_Calibration_Flow] ====Done====
2396 12:38:15.574070
2397 12:38:15.577233 [DutyScan_Calibration_Flow] k_type=3
2398 12:38:15.593628
2399 12:38:15.593779 ==DQM 0 ==
2400 12:38:15.596754 Final DQM duty delay cell = 4
2401 12:38:15.600578 [4] MAX Duty = 5093%(X100), DQS PI = 6
2402 12:38:15.603774 [4] MIN Duty = 4969%(X100), DQS PI = 28
2403 12:38:15.603864 [4] AVG Duty = 5031%(X100)
2404 12:38:15.607287
2405 12:38:15.607374 ==DQM 1 ==
2406 12:38:15.610315 Final DQM duty delay cell = -4
2407 12:38:15.613599 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2408 12:38:15.617081 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2409 12:38:15.620218 [-4] AVG Duty = 4891%(X100)
2410 12:38:15.620309
2411 12:38:15.623858 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2412 12:38:15.623945
2413 12:38:15.626862 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2414 12:38:15.630568 [DutyScan_Calibration_Flow] ====Done====
2415 12:38:15.630660
2416 12:38:15.633714 [DutyScan_Calibration_Flow] k_type=2
2417 12:38:15.650473
2418 12:38:15.650621 ==DQ 0 ==
2419 12:38:15.653872 Final DQ duty delay cell = 0
2420 12:38:15.657056 [0] MAX Duty = 5062%(X100), DQS PI = 20
2421 12:38:15.660514 [0] MIN Duty = 4938%(X100), DQS PI = 0
2422 12:38:15.660615 [0] AVG Duty = 5000%(X100)
2423 12:38:15.660681
2424 12:38:15.663733 ==DQ 1 ==
2425 12:38:15.667114 Final DQ duty delay cell = 0
2426 12:38:15.670759 [0] MAX Duty = 5031%(X100), DQS PI = 2
2427 12:38:15.673717 [0] MIN Duty = 4813%(X100), DQS PI = 36
2428 12:38:15.673805 [0] AVG Duty = 4922%(X100)
2429 12:38:15.673871
2430 12:38:15.676946 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2431 12:38:15.677031
2432 12:38:15.680609 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2433 12:38:15.687266 [DutyScan_Calibration_Flow] ====Done====
2434 12:38:15.690411 nWR fixed to 30
2435 12:38:15.690524 [ModeRegInit_LP4] CH0 RK0
2436 12:38:15.693560 [ModeRegInit_LP4] CH0 RK1
2437 12:38:15.697169 [ModeRegInit_LP4] CH1 RK0
2438 12:38:15.697275 [ModeRegInit_LP4] CH1 RK1
2439 12:38:15.700803 match AC timing 7
2440 12:38:15.703962 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 12:38:15.707221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 12:38:15.713795 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 12:38:15.716951 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 12:38:15.723862 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 12:38:15.723999 ==
2446 12:38:15.727056 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 12:38:15.730473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 12:38:15.730580 ==
2449 12:38:15.737213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 12:38:15.740306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2451 12:38:15.750469 [CA 0] Center 38 (7~69) winsize 63
2452 12:38:15.753326 [CA 1] Center 38 (8~69) winsize 62
2453 12:38:15.756697 [CA 2] Center 35 (5~66) winsize 62
2454 12:38:15.759861 [CA 3] Center 34 (4~65) winsize 62
2455 12:38:15.763907 [CA 4] Center 34 (4~65) winsize 62
2456 12:38:15.767011 [CA 5] Center 33 (3~63) winsize 61
2457 12:38:15.767107
2458 12:38:15.770083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2459 12:38:15.770172
2460 12:38:15.773624 [CATrainingPosCal] consider 1 rank data
2461 12:38:15.776734 u2DelayCellTimex100 = 270/100 ps
2462 12:38:15.780245 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2463 12:38:15.783730 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2464 12:38:15.790152 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2465 12:38:15.793770 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2466 12:38:15.796844 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2467 12:38:15.800135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2468 12:38:15.800228
2469 12:38:15.803369 CA PerBit enable=1, Macro0, CA PI delay=33
2470 12:38:15.803457
2471 12:38:15.806556 [CBTSetCACLKResult] CA Dly = 33
2472 12:38:15.806642 CS Dly: 6 (0~37)
2473 12:38:15.806709 ==
2474 12:38:15.810286 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 12:38:15.816619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 12:38:15.816735 ==
2477 12:38:15.819991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 12:38:15.826688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2479 12:38:15.836195 [CA 0] Center 39 (8~70) winsize 63
2480 12:38:15.838946 [CA 1] Center 38 (8~69) winsize 62
2481 12:38:15.842332 [CA 2] Center 35 (5~66) winsize 62
2482 12:38:15.845801 [CA 3] Center 35 (5~66) winsize 62
2483 12:38:15.848992 [CA 4] Center 34 (4~65) winsize 62
2484 12:38:15.852770 [CA 5] Center 34 (4~64) winsize 61
2485 12:38:15.852866
2486 12:38:15.855719 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2487 12:38:15.855806
2488 12:38:15.859349 [CATrainingPosCal] consider 2 rank data
2489 12:38:15.862562 u2DelayCellTimex100 = 270/100 ps
2490 12:38:15.865758 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2491 12:38:15.869606 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2492 12:38:15.872728 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2493 12:38:15.879557 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2494 12:38:15.882645 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2495 12:38:15.885843 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2496 12:38:15.885985
2497 12:38:15.889178 CA PerBit enable=1, Macro0, CA PI delay=33
2498 12:38:15.889265
2499 12:38:15.892805 [CBTSetCACLKResult] CA Dly = 33
2500 12:38:15.892893 CS Dly: 7 (0~39)
2501 12:38:15.892959
2502 12:38:15.895976 ----->DramcWriteLeveling(PI) begin...
2503 12:38:15.896064 ==
2504 12:38:15.899241 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 12:38:15.905893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 12:38:15.906054 ==
2507 12:38:15.909635 Write leveling (Byte 0): 34 => 34
2508 12:38:15.912857 Write leveling (Byte 1): 31 => 31
2509 12:38:15.912950 DramcWriteLeveling(PI) end<-----
2510 12:38:15.915945
2511 12:38:15.916025 ==
2512 12:38:15.919203 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:38:15.922680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:38:15.922828 ==
2515 12:38:15.925969 [Gating] SW mode calibration
2516 12:38:15.932737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 12:38:15.936015 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 12:38:15.943010 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2519 12:38:15.945806 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2520 12:38:15.949282 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 12:38:15.956008 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 12:38:15.959319 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 12:38:15.962781 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 12:38:15.969484 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2525 12:38:15.972957 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2526 12:38:15.976252 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
2527 12:38:15.982672 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 12:38:15.985903 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 12:38:15.989228 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 12:38:15.992865 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 12:38:15.999415 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:38:16.002933 1 0 24 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
2533 12:38:16.005994 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2534 12:38:16.012786 1 1 0 | B1->B0 | 3231 4646 | 1 0 | (1 1) (0 0)
2535 12:38:16.015957 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:38:16.019215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 12:38:16.025820 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 12:38:16.029503 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 12:38:16.032893 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:38:16.039250 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:38:16.043082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 12:38:16.046328 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 12:38:16.052900 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:38:16.056180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:38:16.059381 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:38:16.066200 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:38:16.069525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:38:16.072931 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:38:16.075989 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:38:16.082871 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:38:16.086297 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:38:16.089689 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:38:16.096522 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:38:16.099525 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:38:16.103005 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:38:16.109693 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:38:16.112729 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2558 12:38:16.116177 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:38:16.119693 Total UI for P1: 0, mck2ui 16
2560 12:38:16.122864 best dqsien dly found for B0: ( 1, 3, 28)
2561 12:38:16.126314 Total UI for P1: 0, mck2ui 16
2562 12:38:16.129951 best dqsien dly found for B1: ( 1, 3, 28)
2563 12:38:16.132788 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2564 12:38:16.136037 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2565 12:38:16.136148
2566 12:38:16.142924 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2567 12:38:16.146272 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 12:38:16.146366 [Gating] SW calibration Done
2569 12:38:16.149634 ==
2570 12:38:16.149739 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 12:38:16.156383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 12:38:16.156508 ==
2573 12:38:16.156609 RX Vref Scan: 0
2574 12:38:16.156700
2575 12:38:16.159445 RX Vref 0 -> 0, step: 1
2576 12:38:16.159556
2577 12:38:16.162867 RX Delay -40 -> 252, step: 8
2578 12:38:16.166075 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2579 12:38:16.169858 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2580 12:38:16.172671 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2581 12:38:16.179417 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2582 12:38:16.182662 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2583 12:38:16.186290 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2584 12:38:16.189398 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2585 12:38:16.193091 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2586 12:38:16.199447 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2587 12:38:16.202893 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2588 12:38:16.206486 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2589 12:38:16.209700 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2590 12:38:16.212889 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2591 12:38:16.216335 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2592 12:38:16.223070 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2593 12:38:16.226419 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2594 12:38:16.226541 ==
2595 12:38:16.229948 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 12:38:16.233245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 12:38:16.233339 ==
2598 12:38:16.236382 DQS Delay:
2599 12:38:16.236496 DQS0 = 0, DQS1 = 0
2600 12:38:16.236586 DQM Delay:
2601 12:38:16.239959 DQM0 = 123, DQM1 = 110
2602 12:38:16.240057 DQ Delay:
2603 12:38:16.243356 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2604 12:38:16.246693 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2605 12:38:16.249792 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2606 12:38:16.256458 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2607 12:38:16.256567
2608 12:38:16.256641
2609 12:38:16.256704 ==
2610 12:38:16.259769 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 12:38:16.263106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 12:38:16.263227 ==
2613 12:38:16.263296
2614 12:38:16.263358
2615 12:38:16.266454 TX Vref Scan disable
2616 12:38:16.266534 == TX Byte 0 ==
2617 12:38:16.273116 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2618 12:38:16.276419 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2619 12:38:16.276536 == TX Byte 1 ==
2620 12:38:16.283554 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2621 12:38:16.286910 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2622 12:38:16.287008 ==
2623 12:38:16.290259 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 12:38:16.293188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 12:38:16.293277 ==
2626 12:38:16.306058 TX Vref=22, minBit 7, minWin=23, winSum=403
2627 12:38:16.309352 TX Vref=24, minBit 5, minWin=24, winSum=412
2628 12:38:16.312368 TX Vref=26, minBit 3, minWin=24, winSum=414
2629 12:38:16.316208 TX Vref=28, minBit 7, minWin=24, winSum=421
2630 12:38:16.319209 TX Vref=30, minBit 7, minWin=24, winSum=417
2631 12:38:16.322759 TX Vref=32, minBit 1, minWin=25, winSum=416
2632 12:38:16.329511 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 32
2633 12:38:16.329656
2634 12:38:16.332777 Final TX Range 1 Vref 32
2635 12:38:16.332892
2636 12:38:16.332996 ==
2637 12:38:16.336063 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 12:38:16.339554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 12:38:16.339644 ==
2640 12:38:16.339731
2641 12:38:16.339810
2642 12:38:16.342763 TX Vref Scan disable
2643 12:38:16.346262 == TX Byte 0 ==
2644 12:38:16.349570 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 12:38:16.352904 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 12:38:16.356035 == TX Byte 1 ==
2647 12:38:16.359837 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2648 12:38:16.363133 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2649 12:38:16.363229
2650 12:38:16.365961 [DATLAT]
2651 12:38:16.366064 Freq=1200, CH0 RK0
2652 12:38:16.366150
2653 12:38:16.369421 DATLAT Default: 0xd
2654 12:38:16.369545 0, 0xFFFF, sum = 0
2655 12:38:16.372818 1, 0xFFFF, sum = 0
2656 12:38:16.372909 2, 0xFFFF, sum = 0
2657 12:38:16.376214 3, 0xFFFF, sum = 0
2658 12:38:16.376305 4, 0xFFFF, sum = 0
2659 12:38:16.379682 5, 0xFFFF, sum = 0
2660 12:38:16.379773 6, 0xFFFF, sum = 0
2661 12:38:16.382852 7, 0xFFFF, sum = 0
2662 12:38:16.382942 8, 0xFFFF, sum = 0
2663 12:38:16.386178 9, 0xFFFF, sum = 0
2664 12:38:16.386297 10, 0xFFFF, sum = 0
2665 12:38:16.389550 11, 0xFFFF, sum = 0
2666 12:38:16.389653 12, 0x0, sum = 1
2667 12:38:16.392700 13, 0x0, sum = 2
2668 12:38:16.392804 14, 0x0, sum = 3
2669 12:38:16.396050 15, 0x0, sum = 4
2670 12:38:16.396167 best_step = 13
2671 12:38:16.396236
2672 12:38:16.396298 ==
2673 12:38:16.399596 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 12:38:16.406201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 12:38:16.406322 ==
2676 12:38:16.406391 RX Vref Scan: 1
2677 12:38:16.406471
2678 12:38:16.409424 Set Vref Range= 32 -> 127
2679 12:38:16.409511
2680 12:38:16.412898 RX Vref 32 -> 127, step: 1
2681 12:38:16.412990
2682 12:38:16.413058 RX Delay -13 -> 252, step: 4
2683 12:38:16.416258
2684 12:38:16.416350 Set Vref, RX VrefLevel [Byte0]: 32
2685 12:38:16.419545 [Byte1]: 32
2686 12:38:16.423953
2687 12:38:16.424056 Set Vref, RX VrefLevel [Byte0]: 33
2688 12:38:16.427808 [Byte1]: 33
2689 12:38:16.432005
2690 12:38:16.432126 Set Vref, RX VrefLevel [Byte0]: 34
2691 12:38:16.435340 [Byte1]: 34
2692 12:38:16.439968
2693 12:38:16.440104 Set Vref, RX VrefLevel [Byte0]: 35
2694 12:38:16.443183 [Byte1]: 35
2695 12:38:16.447858
2696 12:38:16.447977 Set Vref, RX VrefLevel [Byte0]: 36
2697 12:38:16.451069 [Byte1]: 36
2698 12:38:16.455639
2699 12:38:16.455738 Set Vref, RX VrefLevel [Byte0]: 37
2700 12:38:16.459069 [Byte1]: 37
2701 12:38:16.463474
2702 12:38:16.463576 Set Vref, RX VrefLevel [Byte0]: 38
2703 12:38:16.466700 [Byte1]: 38
2704 12:38:16.471569
2705 12:38:16.471671 Set Vref, RX VrefLevel [Byte0]: 39
2706 12:38:16.475035 [Byte1]: 39
2707 12:38:16.479527
2708 12:38:16.479637 Set Vref, RX VrefLevel [Byte0]: 40
2709 12:38:16.482619 [Byte1]: 40
2710 12:38:16.487084
2711 12:38:16.487181 Set Vref, RX VrefLevel [Byte0]: 41
2712 12:38:16.490346 [Byte1]: 41
2713 12:38:16.495022
2714 12:38:16.495117 Set Vref, RX VrefLevel [Byte0]: 42
2715 12:38:16.498513 [Byte1]: 42
2716 12:38:16.503372
2717 12:38:16.503471 Set Vref, RX VrefLevel [Byte0]: 43
2718 12:38:16.506397 [Byte1]: 43
2719 12:38:16.510952
2720 12:38:16.511048 Set Vref, RX VrefLevel [Byte0]: 44
2721 12:38:16.514256 [Byte1]: 44
2722 12:38:16.518869
2723 12:38:16.518983 Set Vref, RX VrefLevel [Byte0]: 45
2724 12:38:16.522013 [Byte1]: 45
2725 12:38:16.526657
2726 12:38:16.526772 Set Vref, RX VrefLevel [Byte0]: 46
2727 12:38:16.529967 [Byte1]: 46
2728 12:38:16.534442
2729 12:38:16.534562 Set Vref, RX VrefLevel [Byte0]: 47
2730 12:38:16.537629 [Byte1]: 47
2731 12:38:16.542867
2732 12:38:16.543032 Set Vref, RX VrefLevel [Byte0]: 48
2733 12:38:16.545586 [Byte1]: 48
2734 12:38:16.550577
2735 12:38:16.550680 Set Vref, RX VrefLevel [Byte0]: 49
2736 12:38:16.553625 [Byte1]: 49
2737 12:38:16.558100
2738 12:38:16.558237 Set Vref, RX VrefLevel [Byte0]: 50
2739 12:38:16.561303 [Byte1]: 50
2740 12:38:16.566307
2741 12:38:16.566406 Set Vref, RX VrefLevel [Byte0]: 51
2742 12:38:16.569683 [Byte1]: 51
2743 12:38:16.574066
2744 12:38:16.574161 Set Vref, RX VrefLevel [Byte0]: 52
2745 12:38:16.577351 [Byte1]: 52
2746 12:38:16.581952
2747 12:38:16.582043 Set Vref, RX VrefLevel [Byte0]: 53
2748 12:38:16.585336 [Byte1]: 53
2749 12:38:16.589963
2750 12:38:16.590080 Set Vref, RX VrefLevel [Byte0]: 54
2751 12:38:16.593216 [Byte1]: 54
2752 12:38:16.597609
2753 12:38:16.597727 Set Vref, RX VrefLevel [Byte0]: 55
2754 12:38:16.601030 [Byte1]: 55
2755 12:38:16.605490
2756 12:38:16.605616 Set Vref, RX VrefLevel [Byte0]: 56
2757 12:38:16.608610 [Byte1]: 56
2758 12:38:16.613679
2759 12:38:16.613837 Set Vref, RX VrefLevel [Byte0]: 57
2760 12:38:16.616698 [Byte1]: 57
2761 12:38:16.621360
2762 12:38:16.621495 Set Vref, RX VrefLevel [Byte0]: 58
2763 12:38:16.624828 [Byte1]: 58
2764 12:38:16.629387
2765 12:38:16.629478 Set Vref, RX VrefLevel [Byte0]: 59
2766 12:38:16.632413 [Byte1]: 59
2767 12:38:16.637316
2768 12:38:16.637404 Set Vref, RX VrefLevel [Byte0]: 60
2769 12:38:16.640494 [Byte1]: 60
2770 12:38:16.644811
2771 12:38:16.644921 Set Vref, RX VrefLevel [Byte0]: 61
2772 12:38:16.648095 [Byte1]: 61
2773 12:38:16.652912
2774 12:38:16.653024 Set Vref, RX VrefLevel [Byte0]: 62
2775 12:38:16.656146 [Byte1]: 62
2776 12:38:16.660937
2777 12:38:16.661053 Set Vref, RX VrefLevel [Byte0]: 63
2778 12:38:16.664007 [Byte1]: 63
2779 12:38:16.668619
2780 12:38:16.668734 Set Vref, RX VrefLevel [Byte0]: 64
2781 12:38:16.671944 [Byte1]: 64
2782 12:38:16.676665
2783 12:38:16.676772 Set Vref, RX VrefLevel [Byte0]: 65
2784 12:38:16.680013 [Byte1]: 65
2785 12:38:16.684548
2786 12:38:16.684637 Set Vref, RX VrefLevel [Byte0]: 66
2787 12:38:16.687901 [Byte1]: 66
2788 12:38:16.692342
2789 12:38:16.692439 Set Vref, RX VrefLevel [Byte0]: 67
2790 12:38:16.695808 [Byte1]: 67
2791 12:38:16.700262
2792 12:38:16.700360 Set Vref, RX VrefLevel [Byte0]: 68
2793 12:38:16.703773 [Byte1]: 68
2794 12:38:16.708480
2795 12:38:16.708582 Final RX Vref Byte 0 = 57 to rank0
2796 12:38:16.711779 Final RX Vref Byte 1 = 48 to rank0
2797 12:38:16.714957 Final RX Vref Byte 0 = 57 to rank1
2798 12:38:16.718135 Final RX Vref Byte 1 = 48 to rank1==
2799 12:38:16.721660 Dram Type= 6, Freq= 0, CH_0, rank 0
2800 12:38:16.725339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2801 12:38:16.728502 ==
2802 12:38:16.728601 DQS Delay:
2803 12:38:16.728670 DQS0 = 0, DQS1 = 0
2804 12:38:16.731597 DQM Delay:
2805 12:38:16.731686 DQM0 = 122, DQM1 = 109
2806 12:38:16.734787 DQ Delay:
2807 12:38:16.738454 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2808 12:38:16.741506 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2809 12:38:16.745205 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2810 12:38:16.748213 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2811 12:38:16.748302
2812 12:38:16.748400
2813 12:38:16.755049 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2814 12:38:16.758456 CH0 RK0: MR19=404, MR18=B08
2815 12:38:16.764873 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2816 12:38:16.765002
2817 12:38:16.768213 ----->DramcWriteLeveling(PI) begin...
2818 12:38:16.768317 ==
2819 12:38:16.771714 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 12:38:16.775009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 12:38:16.775097 ==
2822 12:38:16.778257 Write leveling (Byte 0): 34 => 34
2823 12:38:16.781653 Write leveling (Byte 1): 29 => 29
2824 12:38:16.784998 DramcWriteLeveling(PI) end<-----
2825 12:38:16.785083
2826 12:38:16.785149 ==
2827 12:38:16.788715 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 12:38:16.791996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 12:38:16.795253 ==
2830 12:38:16.795324 [Gating] SW mode calibration
2831 12:38:16.801706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2832 12:38:16.808436 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2833 12:38:16.811832 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2834 12:38:16.818650 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 12:38:16.821878 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 12:38:16.825419 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 12:38:16.831950 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:38:16.835020 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:38:16.838596 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 12:38:16.845443 0 15 28 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (1 0)
2841 12:38:16.848662 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 12:38:16.851788 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 12:38:16.855271 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 12:38:16.861541 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:38:16.865325 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:38:16.868747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 12:38:16.875519 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2848 12:38:16.878560 1 0 28 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
2849 12:38:16.881782 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 12:38:16.888660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 12:38:16.891912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 12:38:16.895506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:38:16.901901 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:38:16.905351 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:38:16.908713 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2856 12:38:16.915592 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 12:38:16.918793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2858 12:38:16.921885 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 12:38:16.925400 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:38:16.932445 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:38:16.935504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:38:16.938768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:38:16.945911 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:38:16.949113 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:38:16.952150 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:38:16.959197 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:38:16.962308 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:38:16.965549 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:38:16.972308 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:38:16.975862 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:38:16.978832 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:38:16.985898 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2873 12:38:16.989250 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2874 12:38:16.992378 Total UI for P1: 0, mck2ui 16
2875 12:38:16.996239 best dqsien dly found for B1: ( 1, 3, 28)
2876 12:38:16.999084 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:38:17.002776 Total UI for P1: 0, mck2ui 16
2878 12:38:17.005956 best dqsien dly found for B0: ( 1, 3, 30)
2879 12:38:17.009506 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2880 12:38:17.012799 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2881 12:38:17.012884
2882 12:38:17.016177 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 12:38:17.019721 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 12:38:17.022556 [Gating] SW calibration Done
2885 12:38:17.022641 ==
2886 12:38:17.025989 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 12:38:17.029625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 12:38:17.032572 ==
2889 12:38:17.032673 RX Vref Scan: 0
2890 12:38:17.032754
2891 12:38:17.035912 RX Vref 0 -> 0, step: 1
2892 12:38:17.035996
2893 12:38:17.039342 RX Delay -40 -> 252, step: 8
2894 12:38:17.042471 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2895 12:38:17.046120 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 12:38:17.049245 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2897 12:38:17.052937 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2898 12:38:17.059505 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2899 12:38:17.062728 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2900 12:38:17.065879 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 12:38:17.069433 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2902 12:38:17.072747 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2903 12:38:17.075876 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2904 12:38:17.082885 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2905 12:38:17.086571 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2906 12:38:17.089252 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2907 12:38:17.092722 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2908 12:38:17.096212 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2909 12:38:17.102970 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2910 12:38:17.103050 ==
2911 12:38:17.106454 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:38:17.109562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:38:17.109666 ==
2914 12:38:17.109761 DQS Delay:
2915 12:38:17.112981 DQS0 = 0, DQS1 = 0
2916 12:38:17.113081 DQM Delay:
2917 12:38:17.116372 DQM0 = 120, DQM1 = 108
2918 12:38:17.116473 DQ Delay:
2919 12:38:17.119672 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2920 12:38:17.122971 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2921 12:38:17.126205 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2922 12:38:17.129654 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2923 12:38:17.129754
2924 12:38:17.129846
2925 12:38:17.132846 ==
2926 12:38:17.136178 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 12:38:17.139458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 12:38:17.139541 ==
2929 12:38:17.139644
2930 12:38:17.139744
2931 12:38:17.142941 TX Vref Scan disable
2932 12:38:17.143022 == TX Byte 0 ==
2933 12:38:17.146488 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2934 12:38:17.152768 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2935 12:38:17.152849 == TX Byte 1 ==
2936 12:38:17.156377 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2937 12:38:17.162681 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2938 12:38:17.162767 ==
2939 12:38:17.166421 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 12:38:17.169804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 12:38:17.169906 ==
2942 12:38:17.181877 TX Vref=22, minBit 1, minWin=24, winSum=410
2943 12:38:17.185043 TX Vref=24, minBit 0, minWin=25, winSum=420
2944 12:38:17.188491 TX Vref=26, minBit 1, minWin=24, winSum=420
2945 12:38:17.191593 TX Vref=28, minBit 1, minWin=24, winSum=420
2946 12:38:17.195424 TX Vref=30, minBit 5, minWin=25, winSum=425
2947 12:38:17.198584 TX Vref=32, minBit 1, minWin=25, winSum=420
2948 12:38:17.205332 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
2949 12:38:17.205412
2950 12:38:17.208643 Final TX Range 1 Vref 30
2951 12:38:17.208744
2952 12:38:17.208846 ==
2953 12:38:17.212067 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 12:38:17.215168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 12:38:17.215244 ==
2956 12:38:17.215323
2957 12:38:17.215399
2958 12:38:17.218783 TX Vref Scan disable
2959 12:38:17.221833 == TX Byte 0 ==
2960 12:38:17.225043 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2961 12:38:17.228723 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2962 12:38:17.231675 == TX Byte 1 ==
2963 12:38:17.235518 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2964 12:38:17.238337 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2965 12:38:17.238426
2966 12:38:17.241890 [DATLAT]
2967 12:38:17.242002 Freq=1200, CH0 RK1
2968 12:38:17.242092
2969 12:38:17.245208 DATLAT Default: 0xd
2970 12:38:17.245290 0, 0xFFFF, sum = 0
2971 12:38:17.248616 1, 0xFFFF, sum = 0
2972 12:38:17.248694 2, 0xFFFF, sum = 0
2973 12:38:17.251840 3, 0xFFFF, sum = 0
2974 12:38:17.251917 4, 0xFFFF, sum = 0
2975 12:38:17.255195 5, 0xFFFF, sum = 0
2976 12:38:17.255274 6, 0xFFFF, sum = 0
2977 12:38:17.258602 7, 0xFFFF, sum = 0
2978 12:38:17.258706 8, 0xFFFF, sum = 0
2979 12:38:17.262125 9, 0xFFFF, sum = 0
2980 12:38:17.262208 10, 0xFFFF, sum = 0
2981 12:38:17.265697 11, 0xFFFF, sum = 0
2982 12:38:17.265801 12, 0x0, sum = 1
2983 12:38:17.268843 13, 0x0, sum = 2
2984 12:38:17.268949 14, 0x0, sum = 3
2985 12:38:17.272232 15, 0x0, sum = 4
2986 12:38:17.272336 best_step = 13
2987 12:38:17.272435
2988 12:38:17.272533 ==
2989 12:38:17.275645 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 12:38:17.282514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 12:38:17.282592 ==
2992 12:38:17.282691 RX Vref Scan: 0
2993 12:38:17.282769
2994 12:38:17.285581 RX Vref 0 -> 0, step: 1
2995 12:38:17.285689
2996 12:38:17.288773 RX Delay -21 -> 252, step: 4
2997 12:38:17.292148 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2998 12:38:17.295241 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
2999 12:38:17.302210 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3000 12:38:17.305706 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3001 12:38:17.309203 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3002 12:38:17.312514 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3003 12:38:17.315759 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3004 12:38:17.322101 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3005 12:38:17.325540 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3006 12:38:17.328871 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3007 12:38:17.332079 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3008 12:38:17.335547 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3009 12:38:17.338943 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3010 12:38:17.345578 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3011 12:38:17.348828 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3012 12:38:17.352173 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3013 12:38:17.352279 ==
3014 12:38:17.355314 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 12:38:17.359037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 12:38:17.362214 ==
3017 12:38:17.362295 DQS Delay:
3018 12:38:17.362361 DQS0 = 0, DQS1 = 0
3019 12:38:17.365634 DQM Delay:
3020 12:38:17.365738 DQM0 = 119, DQM1 = 108
3021 12:38:17.369022 DQ Delay:
3022 12:38:17.372215 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3023 12:38:17.375647 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3024 12:38:17.379166 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3025 12:38:17.382221 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3026 12:38:17.382333
3027 12:38:17.382433
3028 12:38:17.389151 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3029 12:38:17.392489 CH0 RK1: MR19=403, MR18=11F8
3030 12:38:17.398974 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3031 12:38:17.402683 [RxdqsGatingPostProcess] freq 1200
3032 12:38:17.405920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 12:38:17.409092 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 12:38:17.412462 best DQS1 dly(2T, 0.5T) = (0, 11)
3035 12:38:17.415478 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 12:38:17.418886 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3037 12:38:17.422315 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 12:38:17.425730 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 12:38:17.429374 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 12:38:17.432397 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 12:38:17.435725 Pre-setting of DQS Precalculation
3042 12:38:17.439596 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 12:38:17.442524 ==
3044 12:38:17.442609 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 12:38:17.449093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 12:38:17.449224 ==
3047 12:38:17.452542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 12:38:17.459192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3049 12:38:17.468133 [CA 0] Center 37 (7~68) winsize 62
3050 12:38:17.471307 [CA 1] Center 37 (7~68) winsize 62
3051 12:38:17.474733 [CA 2] Center 35 (5~65) winsize 61
3052 12:38:17.478319 [CA 3] Center 34 (4~65) winsize 62
3053 12:38:17.481813 [CA 4] Center 33 (3~64) winsize 62
3054 12:38:17.484650 [CA 5] Center 33 (3~64) winsize 62
3055 12:38:17.484726
3056 12:38:17.488198 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3057 12:38:17.488277
3058 12:38:17.491617 [CATrainingPosCal] consider 1 rank data
3059 12:38:17.494989 u2DelayCellTimex100 = 270/100 ps
3060 12:38:17.498319 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 12:38:17.501383 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 12:38:17.505106 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3063 12:38:17.511428 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3064 12:38:17.514934 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3065 12:38:17.518380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3066 12:38:17.518454
3067 12:38:17.521491 CA PerBit enable=1, Macro0, CA PI delay=33
3068 12:38:17.521565
3069 12:38:17.524698 [CBTSetCACLKResult] CA Dly = 33
3070 12:38:17.524778 CS Dly: 5 (0~36)
3071 12:38:17.524842 ==
3072 12:38:17.528263 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 12:38:17.534853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 12:38:17.534936 ==
3075 12:38:17.538457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 12:38:17.544717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 12:38:17.553771 [CA 0] Center 38 (8~68) winsize 61
3078 12:38:17.557114 [CA 1] Center 38 (7~69) winsize 63
3079 12:38:17.560465 [CA 2] Center 35 (5~66) winsize 62
3080 12:38:17.563732 [CA 3] Center 35 (5~65) winsize 61
3081 12:38:17.566800 [CA 4] Center 34 (4~64) winsize 61
3082 12:38:17.570528 [CA 5] Center 34 (4~64) winsize 61
3083 12:38:17.570606
3084 12:38:17.573556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3085 12:38:17.573640
3086 12:38:17.577017 [CATrainingPosCal] consider 2 rank data
3087 12:38:17.580528 u2DelayCellTimex100 = 270/100 ps
3088 12:38:17.583643 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3089 12:38:17.587342 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3090 12:38:17.590372 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3091 12:38:17.597474 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3092 12:38:17.600411 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3093 12:38:17.603822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3094 12:38:17.603897
3095 12:38:17.607295 CA PerBit enable=1, Macro0, CA PI delay=34
3096 12:38:17.607368
3097 12:38:17.610464 [CBTSetCACLKResult] CA Dly = 34
3098 12:38:17.610538 CS Dly: 6 (0~39)
3099 12:38:17.610601
3100 12:38:17.613704 ----->DramcWriteLeveling(PI) begin...
3101 12:38:17.613777 ==
3102 12:38:17.616977 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 12:38:17.624141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 12:38:17.624236 ==
3105 12:38:17.627269 Write leveling (Byte 0): 26 => 26
3106 12:38:17.630462 Write leveling (Byte 1): 27 => 27
3107 12:38:17.630534 DramcWriteLeveling(PI) end<-----
3108 12:38:17.633691
3109 12:38:17.633767 ==
3110 12:38:17.637456 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 12:38:17.640364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 12:38:17.640451 ==
3113 12:38:17.643924 [Gating] SW mode calibration
3114 12:38:17.650502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 12:38:17.653601 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 12:38:17.660513 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 12:38:17.663902 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 12:38:17.667266 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:38:17.674009 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:38:17.677017 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:38:17.680651 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3122 12:38:17.687292 0 15 24 | B1->B0 | 2b2b 2828 | 0 1 | (0 0) (1 0)
3123 12:38:17.690367 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3124 12:38:17.693914 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 12:38:17.700426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 12:38:17.703883 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:38:17.707212 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:38:17.710740 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:38:17.717337 1 0 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
3130 12:38:17.720694 1 0 24 | B1->B0 | 3d3d 4545 | 0 0 | (1 1) (0 0)
3131 12:38:17.723813 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 12:38:17.730713 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 12:38:17.734003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:38:17.737037 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:38:17.743775 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:38:17.747326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:38:17.750654 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3138 12:38:17.757086 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3139 12:38:17.760248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 12:38:17.763767 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 12:38:17.770786 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:38:17.773693 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:38:17.777409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:38:17.784128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:38:17.787146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:38:17.790708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:38:17.797371 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:38:17.800508 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:38:17.803733 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:38:17.807483 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:38:17.814256 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:38:17.817436 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:38:17.820857 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3154 12:38:17.827464 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3155 12:38:17.830539 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3156 12:38:17.833772 Total UI for P1: 0, mck2ui 16
3157 12:38:17.837200 best dqsien dly found for B0: ( 1, 3, 22)
3158 12:38:17.840560 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:38:17.843949 Total UI for P1: 0, mck2ui 16
3160 12:38:17.847267 best dqsien dly found for B1: ( 1, 3, 28)
3161 12:38:17.850460 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3162 12:38:17.853802 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3163 12:38:17.853890
3164 12:38:17.860666 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3165 12:38:17.863832 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3166 12:38:17.863922 [Gating] SW calibration Done
3167 12:38:17.867342 ==
3168 12:38:17.870777 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 12:38:17.873809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 12:38:17.873896 ==
3171 12:38:17.874004 RX Vref Scan: 0
3172 12:38:17.874068
3173 12:38:17.877092 RX Vref 0 -> 0, step: 1
3174 12:38:17.877177
3175 12:38:17.880640 RX Delay -40 -> 252, step: 8
3176 12:38:17.883932 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3177 12:38:17.887327 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3178 12:38:17.890796 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3179 12:38:17.897512 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3180 12:38:17.900812 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3181 12:38:17.904242 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3182 12:38:17.907458 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3183 12:38:17.910662 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3184 12:38:17.917281 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3185 12:38:17.920708 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3186 12:38:17.923933 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3187 12:38:17.927634 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3188 12:38:17.930665 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 12:38:17.937433 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3190 12:38:17.941199 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3191 12:38:17.944295 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3192 12:38:17.944395 ==
3193 12:38:17.947728 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 12:38:17.951305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:38:17.951404 ==
3196 12:38:17.954220 DQS Delay:
3197 12:38:17.954289 DQS0 = 0, DQS1 = 0
3198 12:38:17.954350 DQM Delay:
3199 12:38:17.957452 DQM0 = 120, DQM1 = 113
3200 12:38:17.957521 DQ Delay:
3201 12:38:17.960940 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3202 12:38:17.964153 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3203 12:38:17.970703 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3204 12:38:17.973981 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3205 12:38:17.974054
3206 12:38:17.974120
3207 12:38:17.974181 ==
3208 12:38:17.977513 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 12:38:17.981152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 12:38:17.981245 ==
3211 12:38:17.981327
3212 12:38:17.981425
3213 12:38:17.984436 TX Vref Scan disable
3214 12:38:17.984542 == TX Byte 0 ==
3215 12:38:17.990979 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3216 12:38:17.994121 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3217 12:38:17.994209 == TX Byte 1 ==
3218 12:38:18.000841 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3219 12:38:18.004532 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3220 12:38:18.004624 ==
3221 12:38:18.007578 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 12:38:18.011066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 12:38:18.011145 ==
3224 12:38:18.023647 TX Vref=22, minBit 10, minWin=24, winSum=405
3225 12:38:18.026967 TX Vref=24, minBit 3, minWin=25, winSum=412
3226 12:38:18.030145 TX Vref=26, minBit 8, minWin=25, winSum=417
3227 12:38:18.033653 TX Vref=28, minBit 10, minWin=25, winSum=424
3228 12:38:18.037077 TX Vref=30, minBit 10, minWin=25, winSum=424
3229 12:38:18.043406 TX Vref=32, minBit 14, minWin=25, winSum=423
3230 12:38:18.046860 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 28
3231 12:38:18.046939
3232 12:38:18.050255 Final TX Range 1 Vref 28
3233 12:38:18.050332
3234 12:38:18.050417 ==
3235 12:38:18.053618 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:38:18.057131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:38:18.060237 ==
3238 12:38:18.060337
3239 12:38:18.060418
3240 12:38:18.060517 TX Vref Scan disable
3241 12:38:18.063633 == TX Byte 0 ==
3242 12:38:18.067135 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 12:38:18.070094 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 12:38:18.073409 == TX Byte 1 ==
3245 12:38:18.076922 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3246 12:38:18.080280 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3247 12:38:18.083705
3248 12:38:18.083823 [DATLAT]
3249 12:38:18.083925 Freq=1200, CH1 RK0
3250 12:38:18.084025
3251 12:38:18.087156 DATLAT Default: 0xd
3252 12:38:18.087233 0, 0xFFFF, sum = 0
3253 12:38:18.090210 1, 0xFFFF, sum = 0
3254 12:38:18.090288 2, 0xFFFF, sum = 0
3255 12:38:18.093822 3, 0xFFFF, sum = 0
3256 12:38:18.093924 4, 0xFFFF, sum = 0
3257 12:38:18.096947 5, 0xFFFF, sum = 0
3258 12:38:18.100472 6, 0xFFFF, sum = 0
3259 12:38:18.100553 7, 0xFFFF, sum = 0
3260 12:38:18.103427 8, 0xFFFF, sum = 0
3261 12:38:18.103503 9, 0xFFFF, sum = 0
3262 12:38:18.107158 10, 0xFFFF, sum = 0
3263 12:38:18.107264 11, 0xFFFF, sum = 0
3264 12:38:18.110386 12, 0x0, sum = 1
3265 12:38:18.110473 13, 0x0, sum = 2
3266 12:38:18.113606 14, 0x0, sum = 3
3267 12:38:18.113686 15, 0x0, sum = 4
3268 12:38:18.113766 best_step = 13
3269 12:38:18.113881
3270 12:38:18.117031 ==
3271 12:38:18.120496 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 12:38:18.123921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 12:38:18.124026 ==
3274 12:38:18.124136 RX Vref Scan: 1
3275 12:38:18.124230
3276 12:38:18.127124 Set Vref Range= 32 -> 127
3277 12:38:18.127222
3278 12:38:18.130424 RX Vref 32 -> 127, step: 1
3279 12:38:18.130495
3280 12:38:18.133726 RX Delay -13 -> 252, step: 4
3281 12:38:18.133823
3282 12:38:18.136892 Set Vref, RX VrefLevel [Byte0]: 32
3283 12:38:18.140461 [Byte1]: 32
3284 12:38:18.140568
3285 12:38:18.143629 Set Vref, RX VrefLevel [Byte0]: 33
3286 12:38:18.147205 [Byte1]: 33
3287 12:38:18.147303
3288 12:38:18.150423 Set Vref, RX VrefLevel [Byte0]: 34
3289 12:38:18.153835 [Byte1]: 34
3290 12:38:18.157752
3291 12:38:18.157857 Set Vref, RX VrefLevel [Byte0]: 35
3292 12:38:18.161052 [Byte1]: 35
3293 12:38:18.165986
3294 12:38:18.166074 Set Vref, RX VrefLevel [Byte0]: 36
3295 12:38:18.169172 [Byte1]: 36
3296 12:38:18.173874
3297 12:38:18.174018 Set Vref, RX VrefLevel [Byte0]: 37
3298 12:38:18.177175 [Byte1]: 37
3299 12:38:18.181696
3300 12:38:18.181797 Set Vref, RX VrefLevel [Byte0]: 38
3301 12:38:18.184944 [Byte1]: 38
3302 12:38:18.189273
3303 12:38:18.189384 Set Vref, RX VrefLevel [Byte0]: 39
3304 12:38:18.192640 [Byte1]: 39
3305 12:38:18.197307
3306 12:38:18.197412 Set Vref, RX VrefLevel [Byte0]: 40
3307 12:38:18.200767 [Byte1]: 40
3308 12:38:18.205079
3309 12:38:18.205155 Set Vref, RX VrefLevel [Byte0]: 41
3310 12:38:18.208577 [Byte1]: 41
3311 12:38:18.213213
3312 12:38:18.213288 Set Vref, RX VrefLevel [Byte0]: 42
3313 12:38:18.216513 [Byte1]: 42
3314 12:38:18.221319
3315 12:38:18.221399 Set Vref, RX VrefLevel [Byte0]: 43
3316 12:38:18.224137 [Byte1]: 43
3317 12:38:18.228616
3318 12:38:18.228716 Set Vref, RX VrefLevel [Byte0]: 44
3319 12:38:18.232238 [Byte1]: 44
3320 12:38:18.236760
3321 12:38:18.236860 Set Vref, RX VrefLevel [Byte0]: 45
3322 12:38:18.240035 [Byte1]: 45
3323 12:38:18.244972
3324 12:38:18.245041 Set Vref, RX VrefLevel [Byte0]: 46
3325 12:38:18.248015 [Byte1]: 46
3326 12:38:18.252660
3327 12:38:18.252734 Set Vref, RX VrefLevel [Byte0]: 47
3328 12:38:18.255826 [Byte1]: 47
3329 12:38:18.260234
3330 12:38:18.260320 Set Vref, RX VrefLevel [Byte0]: 48
3331 12:38:18.263705 [Byte1]: 48
3332 12:38:18.268541
3333 12:38:18.268644 Set Vref, RX VrefLevel [Byte0]: 49
3334 12:38:18.271511 [Byte1]: 49
3335 12:38:18.276305
3336 12:38:18.276405 Set Vref, RX VrefLevel [Byte0]: 50
3337 12:38:18.279744 [Byte1]: 50
3338 12:38:18.284382
3339 12:38:18.284481 Set Vref, RX VrefLevel [Byte0]: 51
3340 12:38:18.287307 [Byte1]: 51
3341 12:38:18.292036
3342 12:38:18.292115 Set Vref, RX VrefLevel [Byte0]: 52
3343 12:38:18.295110 [Byte1]: 52
3344 12:38:18.299750
3345 12:38:18.299821 Set Vref, RX VrefLevel [Byte0]: 53
3346 12:38:18.303025 [Byte1]: 53
3347 12:38:18.307653
3348 12:38:18.307728 Set Vref, RX VrefLevel [Byte0]: 54
3349 12:38:18.311029 [Byte1]: 54
3350 12:38:18.315450
3351 12:38:18.315526 Set Vref, RX VrefLevel [Byte0]: 55
3352 12:38:18.318947 [Byte1]: 55
3353 12:38:18.323510
3354 12:38:18.323616 Set Vref, RX VrefLevel [Byte0]: 56
3355 12:38:18.326836 [Byte1]: 56
3356 12:38:18.331701
3357 12:38:18.331801 Set Vref, RX VrefLevel [Byte0]: 57
3358 12:38:18.334885 [Byte1]: 57
3359 12:38:18.339533
3360 12:38:18.339606 Set Vref, RX VrefLevel [Byte0]: 58
3361 12:38:18.342702 [Byte1]: 58
3362 12:38:18.346942
3363 12:38:18.347020 Set Vref, RX VrefLevel [Byte0]: 59
3364 12:38:18.350344 [Byte1]: 59
3365 12:38:18.355105
3366 12:38:18.355193 Set Vref, RX VrefLevel [Byte0]: 60
3367 12:38:18.358356 [Byte1]: 60
3368 12:38:18.363028
3369 12:38:18.363108 Set Vref, RX VrefLevel [Byte0]: 61
3370 12:38:18.366321 [Byte1]: 61
3371 12:38:18.370993
3372 12:38:18.371110 Set Vref, RX VrefLevel [Byte0]: 62
3373 12:38:18.374111 [Byte1]: 62
3374 12:38:18.378898
3375 12:38:18.378986 Set Vref, RX VrefLevel [Byte0]: 63
3376 12:38:18.382034 [Byte1]: 63
3377 12:38:18.386840
3378 12:38:18.386963 Set Vref, RX VrefLevel [Byte0]: 64
3379 12:38:18.390313 [Byte1]: 64
3380 12:38:18.394568
3381 12:38:18.394684 Set Vref, RX VrefLevel [Byte0]: 65
3382 12:38:18.398100 [Byte1]: 65
3383 12:38:18.402338
3384 12:38:18.402427 Set Vref, RX VrefLevel [Byte0]: 66
3385 12:38:18.405695 [Byte1]: 66
3386 12:38:18.410172
3387 12:38:18.410256 Set Vref, RX VrefLevel [Byte0]: 67
3388 12:38:18.413626 [Byte1]: 67
3389 12:38:18.418265
3390 12:38:18.418368 Final RX Vref Byte 0 = 51 to rank0
3391 12:38:18.421772 Final RX Vref Byte 1 = 53 to rank0
3392 12:38:18.424975 Final RX Vref Byte 0 = 51 to rank1
3393 12:38:18.428146 Final RX Vref Byte 1 = 53 to rank1==
3394 12:38:18.431848 Dram Type= 6, Freq= 0, CH_1, rank 0
3395 12:38:18.438403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3396 12:38:18.438488 ==
3397 12:38:18.438554 DQS Delay:
3398 12:38:18.438616 DQS0 = 0, DQS1 = 0
3399 12:38:18.441579 DQM Delay:
3400 12:38:18.441662 DQM0 = 119, DQM1 = 112
3401 12:38:18.444939 DQ Delay:
3402 12:38:18.448159 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3403 12:38:18.451356 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3404 12:38:18.454774 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3405 12:38:18.458195 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =116
3406 12:38:18.458278
3407 12:38:18.458343
3408 12:38:18.464768 [DQSOSCAuto] RK0, (LSB)MR18= 0x619, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3409 12:38:18.468191 CH1 RK0: MR19=404, MR18=619
3410 12:38:18.475048 CH1_RK0: MR19=0x404, MR18=0x619, DQSOSC=400, MR23=63, INC=40, DEC=27
3411 12:38:18.475142
3412 12:38:18.478332 ----->DramcWriteLeveling(PI) begin...
3413 12:38:18.478419 ==
3414 12:38:18.481594 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 12:38:18.484721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 12:38:18.488098 ==
3417 12:38:18.488185 Write leveling (Byte 0): 25 => 25
3418 12:38:18.491715 Write leveling (Byte 1): 29 => 29
3419 12:38:18.494882 DramcWriteLeveling(PI) end<-----
3420 12:38:18.494965
3421 12:38:18.495047 ==
3422 12:38:18.498244 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 12:38:18.505044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 12:38:18.505136 ==
3425 12:38:18.505224 [Gating] SW mode calibration
3426 12:38:18.515132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3427 12:38:18.518546 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3428 12:38:18.521847 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 12:38:18.528501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 12:38:18.531698 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 12:38:18.534934 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 12:38:18.542200 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 12:38:18.545041 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 12:38:18.548152 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
3435 12:38:18.554797 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
3436 12:38:18.558052 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 12:38:18.561553 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 12:38:18.568368 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 12:38:18.571432 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 12:38:18.574820 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 12:38:18.581720 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3442 12:38:18.584761 1 0 24 | B1->B0 | 3a3a 2626 | 1 0 | (0 0) (0 0)
3443 12:38:18.588293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 12:38:18.591514 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 12:38:18.598200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 12:38:18.601661 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 12:38:18.605212 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 12:38:18.611659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 12:38:18.615003 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 12:38:18.618422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3451 12:38:18.625303 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3452 12:38:18.628274 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 12:38:18.632096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 12:38:18.638457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:38:18.641609 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:38:18.644918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:38:18.651775 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:38:18.655050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:38:18.658347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:38:18.665012 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:38:18.668322 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:38:18.671992 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:38:18.678448 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:38:18.681492 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:38:18.685041 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3466 12:38:18.688096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3467 12:38:18.695143 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3468 12:38:18.698214 Total UI for P1: 0, mck2ui 16
3469 12:38:18.701677 best dqsien dly found for B0: ( 1, 3, 22)
3470 12:38:18.704902 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 12:38:18.708119 Total UI for P1: 0, mck2ui 16
3472 12:38:18.711438 best dqsien dly found for B1: ( 1, 3, 24)
3473 12:38:18.714783 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3474 12:38:18.717852 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3475 12:38:18.717962
3476 12:38:18.721604 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3477 12:38:18.727827 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3478 12:38:18.727916 [Gating] SW calibration Done
3479 12:38:18.727984 ==
3480 12:38:18.731436 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 12:38:18.737814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 12:38:18.737906 ==
3483 12:38:18.738013 RX Vref Scan: 0
3484 12:38:18.738078
3485 12:38:18.741451 RX Vref 0 -> 0, step: 1
3486 12:38:18.741537
3487 12:38:18.744556 RX Delay -40 -> 252, step: 8
3488 12:38:18.747961 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3489 12:38:18.751104 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3490 12:38:18.754825 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3491 12:38:18.758209 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3492 12:38:18.764638 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3493 12:38:18.768258 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3494 12:38:18.771264 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3495 12:38:18.774389 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3496 12:38:18.777751 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3497 12:38:18.784865 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3498 12:38:18.787629 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3499 12:38:18.791498 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3500 12:38:18.794544 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3501 12:38:18.798070 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3502 12:38:18.804317 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3503 12:38:18.807876 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3504 12:38:18.807961 ==
3505 12:38:18.811041 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 12:38:18.814624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 12:38:18.814710 ==
3508 12:38:18.817904 DQS Delay:
3509 12:38:18.818037 DQS0 = 0, DQS1 = 0
3510 12:38:18.818104 DQM Delay:
3511 12:38:18.821328 DQM0 = 120, DQM1 = 112
3512 12:38:18.821440 DQ Delay:
3513 12:38:18.824315 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3514 12:38:18.827728 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3515 12:38:18.831469 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3516 12:38:18.837419 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3517 12:38:18.837508
3518 12:38:18.837575
3519 12:38:18.837637 ==
3520 12:38:18.841107 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 12:38:18.844165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 12:38:18.844252 ==
3523 12:38:18.844350
3524 12:38:18.844412
3525 12:38:18.847452 TX Vref Scan disable
3526 12:38:18.847537 == TX Byte 0 ==
3527 12:38:18.854353 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3528 12:38:18.857448 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3529 12:38:18.857534 == TX Byte 1 ==
3530 12:38:18.864395 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3531 12:38:18.867539 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3532 12:38:18.867629 ==
3533 12:38:18.870986 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 12:38:18.874227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 12:38:18.874314 ==
3536 12:38:18.886862 TX Vref=22, minBit 1, minWin=25, winSum=415
3537 12:38:18.890183 TX Vref=24, minBit 9, minWin=25, winSum=424
3538 12:38:18.893836 TX Vref=26, minBit 3, minWin=25, winSum=426
3539 12:38:18.897149 TX Vref=28, minBit 1, minWin=26, winSum=427
3540 12:38:18.900279 TX Vref=30, minBit 1, minWin=26, winSum=427
3541 12:38:18.906921 TX Vref=32, minBit 9, minWin=25, winSum=427
3542 12:38:18.910446 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3543 12:38:18.910536
3544 12:38:18.913719 Final TX Range 1 Vref 28
3545 12:38:18.913806
3546 12:38:18.913873 ==
3547 12:38:18.917038 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 12:38:18.920684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 12:38:18.920771 ==
3550 12:38:18.920837
3551 12:38:18.923979
3552 12:38:18.924064 TX Vref Scan disable
3553 12:38:18.927139 == TX Byte 0 ==
3554 12:38:18.930318 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3555 12:38:18.933834 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3556 12:38:18.936960 == TX Byte 1 ==
3557 12:38:18.940388 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 12:38:18.943873 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 12:38:18.943987
3560 12:38:18.947054 [DATLAT]
3561 12:38:18.947142 Freq=1200, CH1 RK1
3562 12:38:18.947211
3563 12:38:18.950664 DATLAT Default: 0xd
3564 12:38:18.950749 0, 0xFFFF, sum = 0
3565 12:38:18.953739 1, 0xFFFF, sum = 0
3566 12:38:18.953825 2, 0xFFFF, sum = 0
3567 12:38:18.957571 3, 0xFFFF, sum = 0
3568 12:38:18.957657 4, 0xFFFF, sum = 0
3569 12:38:18.960420 5, 0xFFFF, sum = 0
3570 12:38:18.960506 6, 0xFFFF, sum = 0
3571 12:38:18.964318 7, 0xFFFF, sum = 0
3572 12:38:18.964404 8, 0xFFFF, sum = 0
3573 12:38:18.967058 9, 0xFFFF, sum = 0
3574 12:38:18.970587 10, 0xFFFF, sum = 0
3575 12:38:18.970707 11, 0xFFFF, sum = 0
3576 12:38:18.973778 12, 0x0, sum = 1
3577 12:38:18.973866 13, 0x0, sum = 2
3578 12:38:18.976841 14, 0x0, sum = 3
3579 12:38:18.976954 15, 0x0, sum = 4
3580 12:38:18.977102 best_step = 13
3581 12:38:18.977181
3582 12:38:18.980433 ==
3583 12:38:18.983480 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 12:38:18.986953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 12:38:18.987042 ==
3586 12:38:18.987111 RX Vref Scan: 0
3587 12:38:18.987175
3588 12:38:18.990060 RX Vref 0 -> 0, step: 1
3589 12:38:18.990146
3590 12:38:18.993584 RX Delay -13 -> 252, step: 4
3591 12:38:18.997048 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3592 12:38:19.003609 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3593 12:38:19.006922 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3594 12:38:19.009987 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3595 12:38:19.013229 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3596 12:38:19.017033 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3597 12:38:19.023407 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3598 12:38:19.027049 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3599 12:38:19.029887 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3600 12:38:19.033610 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3601 12:38:19.036741 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3602 12:38:19.040405 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3603 12:38:19.046766 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3604 12:38:19.050149 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3605 12:38:19.053681 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3606 12:38:19.056898 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3607 12:38:19.056986 ==
3608 12:38:19.059870 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 12:38:19.066534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 12:38:19.066653 ==
3611 12:38:19.066754 DQS Delay:
3612 12:38:19.070483 DQS0 = 0, DQS1 = 0
3613 12:38:19.070588 DQM Delay:
3614 12:38:19.073224 DQM0 = 119, DQM1 = 113
3615 12:38:19.073328 DQ Delay:
3616 12:38:19.076845 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3617 12:38:19.080215 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3618 12:38:19.083184 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3619 12:38:19.086512 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3620 12:38:19.086617
3621 12:38:19.086709
3622 12:38:19.096747 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3623 12:38:19.096867 CH1 RK1: MR19=403, MR18=8EC
3624 12:38:19.103210 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3625 12:38:19.106518 [RxdqsGatingPostProcess] freq 1200
3626 12:38:19.113137 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3627 12:38:19.116381 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 12:38:19.120044 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 12:38:19.123057 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 12:38:19.126636 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 12:38:19.130075 best DQS0 dly(2T, 0.5T) = (0, 11)
3632 12:38:19.130179 best DQS1 dly(2T, 0.5T) = (0, 11)
3633 12:38:19.133047 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3634 12:38:19.136272 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3635 12:38:19.139652 Pre-setting of DQS Precalculation
3636 12:38:19.146638 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3637 12:38:19.153182 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3638 12:38:19.159851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3639 12:38:19.159962
3640 12:38:19.160060
3641 12:38:19.163030 [Calibration Summary] 2400 Mbps
3642 12:38:19.163134 CH 0, Rank 0
3643 12:38:19.166197 SW Impedance : PASS
3644 12:38:19.169590 DUTY Scan : NO K
3645 12:38:19.169693 ZQ Calibration : PASS
3646 12:38:19.172880 Jitter Meter : NO K
3647 12:38:19.176308 CBT Training : PASS
3648 12:38:19.176408 Write leveling : PASS
3649 12:38:19.179878 RX DQS gating : PASS
3650 12:38:19.182710 RX DQ/DQS(RDDQC) : PASS
3651 12:38:19.182785 TX DQ/DQS : PASS
3652 12:38:19.186277 RX DATLAT : PASS
3653 12:38:19.189634 RX DQ/DQS(Engine): PASS
3654 12:38:19.189740 TX OE : NO K
3655 12:38:19.192828 All Pass.
3656 12:38:19.192928
3657 12:38:19.193018 CH 0, Rank 1
3658 12:38:19.196385 SW Impedance : PASS
3659 12:38:19.196483 DUTY Scan : NO K
3660 12:38:19.199738 ZQ Calibration : PASS
3661 12:38:19.202999 Jitter Meter : NO K
3662 12:38:19.203115 CBT Training : PASS
3663 12:38:19.206060 Write leveling : PASS
3664 12:38:19.206147 RX DQS gating : PASS
3665 12:38:19.209702 RX DQ/DQS(RDDQC) : PASS
3666 12:38:19.212851 TX DQ/DQS : PASS
3667 12:38:19.212922 RX DATLAT : PASS
3668 12:38:19.216627 RX DQ/DQS(Engine): PASS
3669 12:38:19.219433 TX OE : NO K
3670 12:38:19.219530 All Pass.
3671 12:38:19.219627
3672 12:38:19.219715 CH 1, Rank 0
3673 12:38:19.223226 SW Impedance : PASS
3674 12:38:19.226365 DUTY Scan : NO K
3675 12:38:19.226455 ZQ Calibration : PASS
3676 12:38:19.229919 Jitter Meter : NO K
3677 12:38:19.233219 CBT Training : PASS
3678 12:38:19.233324 Write leveling : PASS
3679 12:38:19.236701 RX DQS gating : PASS
3680 12:38:19.239556 RX DQ/DQS(RDDQC) : PASS
3681 12:38:19.239658 TX DQ/DQS : PASS
3682 12:38:19.242936 RX DATLAT : PASS
3683 12:38:19.246318 RX DQ/DQS(Engine): PASS
3684 12:38:19.246419 TX OE : NO K
3685 12:38:19.246488 All Pass.
3686 12:38:19.249515
3687 12:38:19.249600 CH 1, Rank 1
3688 12:38:19.253028 SW Impedance : PASS
3689 12:38:19.253129 DUTY Scan : NO K
3690 12:38:19.256185 ZQ Calibration : PASS
3691 12:38:19.256286 Jitter Meter : NO K
3692 12:38:19.259777 CBT Training : PASS
3693 12:38:19.263121 Write leveling : PASS
3694 12:38:19.263224 RX DQS gating : PASS
3695 12:38:19.266312 RX DQ/DQS(RDDQC) : PASS
3696 12:38:19.269470 TX DQ/DQS : PASS
3697 12:38:19.269599 RX DATLAT : PASS
3698 12:38:19.272773 RX DQ/DQS(Engine): PASS
3699 12:38:19.276486 TX OE : NO K
3700 12:38:19.276571 All Pass.
3701 12:38:19.276637
3702 12:38:19.279936 DramC Write-DBI off
3703 12:38:19.280021 PER_BANK_REFRESH: Hybrid Mode
3704 12:38:19.282878 TX_TRACKING: ON
3705 12:38:19.289705 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3706 12:38:19.296469 [FAST_K] Save calibration result to emmc
3707 12:38:19.299842 dramc_set_vcore_voltage set vcore to 650000
3708 12:38:19.299920 Read voltage for 600, 5
3709 12:38:19.303032 Vio18 = 0
3710 12:38:19.303109 Vcore = 650000
3711 12:38:19.303204 Vdram = 0
3712 12:38:19.306377 Vddq = 0
3713 12:38:19.306450 Vmddr = 0
3714 12:38:19.309588 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3715 12:38:19.316472 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3716 12:38:19.319462 MEM_TYPE=3, freq_sel=19
3717 12:38:19.323058 sv_algorithm_assistance_LP4_1600
3718 12:38:19.326396 ============ PULL DRAM RESETB DOWN ============
3719 12:38:19.329830 ========== PULL DRAM RESETB DOWN end =========
3720 12:38:19.332930 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3721 12:38:19.336293 ===================================
3722 12:38:19.339361 LPDDR4 DRAM CONFIGURATION
3723 12:38:19.342855 ===================================
3724 12:38:19.346185 EX_ROW_EN[0] = 0x0
3725 12:38:19.346265 EX_ROW_EN[1] = 0x0
3726 12:38:19.349655 LP4Y_EN = 0x0
3727 12:38:19.349729 WORK_FSP = 0x0
3728 12:38:19.352671 WL = 0x2
3729 12:38:19.352742 RL = 0x2
3730 12:38:19.356455 BL = 0x2
3731 12:38:19.356526 RPST = 0x0
3732 12:38:19.359542 RD_PRE = 0x0
3733 12:38:19.359615 WR_PRE = 0x1
3734 12:38:19.363072 WR_PST = 0x0
3735 12:38:19.366278 DBI_WR = 0x0
3736 12:38:19.366373 DBI_RD = 0x0
3737 12:38:19.369251 OTF = 0x1
3738 12:38:19.372543 ===================================
3739 12:38:19.376305 ===================================
3740 12:38:19.376387 ANA top config
3741 12:38:19.379583 ===================================
3742 12:38:19.382584 DLL_ASYNC_EN = 0
3743 12:38:19.382660 ALL_SLAVE_EN = 1
3744 12:38:19.385752 NEW_RANK_MODE = 1
3745 12:38:19.389176 DLL_IDLE_MODE = 1
3746 12:38:19.392689 LP45_APHY_COMB_EN = 1
3747 12:38:19.396256 TX_ODT_DIS = 1
3748 12:38:19.396333 NEW_8X_MODE = 1
3749 12:38:19.399394 ===================================
3750 12:38:19.402588 ===================================
3751 12:38:19.405692 data_rate = 1200
3752 12:38:19.409151 CKR = 1
3753 12:38:19.412484 DQ_P2S_RATIO = 8
3754 12:38:19.415730 ===================================
3755 12:38:19.419303 CA_P2S_RATIO = 8
3756 12:38:19.422415 DQ_CA_OPEN = 0
3757 12:38:19.422491 DQ_SEMI_OPEN = 0
3758 12:38:19.425820 CA_SEMI_OPEN = 0
3759 12:38:19.429053 CA_FULL_RATE = 0
3760 12:38:19.432580 DQ_CKDIV4_EN = 1
3761 12:38:19.435895 CA_CKDIV4_EN = 1
3762 12:38:19.438923 CA_PREDIV_EN = 0
3763 12:38:19.438997 PH8_DLY = 0
3764 12:38:19.442528 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3765 12:38:19.445794 DQ_AAMCK_DIV = 4
3766 12:38:19.449165 CA_AAMCK_DIV = 4
3767 12:38:19.452354 CA_ADMCK_DIV = 4
3768 12:38:19.455783 DQ_TRACK_CA_EN = 0
3769 12:38:19.455855 CA_PICK = 600
3770 12:38:19.459472 CA_MCKIO = 600
3771 12:38:19.462647 MCKIO_SEMI = 0
3772 12:38:19.465810 PLL_FREQ = 2288
3773 12:38:19.469070 DQ_UI_PI_RATIO = 32
3774 12:38:19.472493 CA_UI_PI_RATIO = 0
3775 12:38:19.475743 ===================================
3776 12:38:19.479468 ===================================
3777 12:38:19.479556 memory_type:LPDDR4
3778 12:38:19.482282 GP_NUM : 10
3779 12:38:19.485857 SRAM_EN : 1
3780 12:38:19.485932 MD32_EN : 0
3781 12:38:19.489063 ===================================
3782 12:38:19.492251 [ANA_INIT] >>>>>>>>>>>>>>
3783 12:38:19.495504 <<<<<< [CONFIGURE PHASE]: ANA_TX
3784 12:38:19.498826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3785 12:38:19.502518 ===================================
3786 12:38:19.505854 data_rate = 1200,PCW = 0X5800
3787 12:38:19.508944 ===================================
3788 12:38:19.512450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3789 12:38:19.515708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3790 12:38:19.522197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3791 12:38:19.525722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3792 12:38:19.528880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3793 12:38:19.532383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3794 12:38:19.535687 [ANA_INIT] flow start
3795 12:38:19.538887 [ANA_INIT] PLL >>>>>>>>
3796 12:38:19.538965 [ANA_INIT] PLL <<<<<<<<
3797 12:38:19.542407 [ANA_INIT] MIDPI >>>>>>>>
3798 12:38:19.545443 [ANA_INIT] MIDPI <<<<<<<<
3799 12:38:19.545519 [ANA_INIT] DLL >>>>>>>>
3800 12:38:19.548823 [ANA_INIT] flow end
3801 12:38:19.552655 ============ LP4 DIFF to SE enter ============
3802 12:38:19.559049 ============ LP4 DIFF to SE exit ============
3803 12:38:19.559139 [ANA_INIT] <<<<<<<<<<<<<
3804 12:38:19.562374 [Flow] Enable top DCM control >>>>>
3805 12:38:19.565388 [Flow] Enable top DCM control <<<<<
3806 12:38:19.568862 Enable DLL master slave shuffle
3807 12:38:19.575317 ==============================================================
3808 12:38:19.575414 Gating Mode config
3809 12:38:19.581898 ==============================================================
3810 12:38:19.585617 Config description:
3811 12:38:19.592135 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3812 12:38:19.601986 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3813 12:38:19.605471 SELPH_MODE 0: By rank 1: By Phase
3814 12:38:19.612044 ==============================================================
3815 12:38:19.615370 GAT_TRACK_EN = 1
3816 12:38:19.615458 RX_GATING_MODE = 2
3817 12:38:19.618619 RX_GATING_TRACK_MODE = 2
3818 12:38:19.621996 SELPH_MODE = 1
3819 12:38:19.625214 PICG_EARLY_EN = 1
3820 12:38:19.628481 VALID_LAT_VALUE = 1
3821 12:38:19.635129 ==============================================================
3822 12:38:19.638669 Enter into Gating configuration >>>>
3823 12:38:19.641893 Exit from Gating configuration <<<<
3824 12:38:19.644997 Enter into DVFS_PRE_config >>>>>
3825 12:38:19.655134 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3826 12:38:19.658454 Exit from DVFS_PRE_config <<<<<
3827 12:38:19.661659 Enter into PICG configuration >>>>
3828 12:38:19.665328 Exit from PICG configuration <<<<
3829 12:38:19.668311 [RX_INPUT] configuration >>>>>
3830 12:38:19.671616 [RX_INPUT] configuration <<<<<
3831 12:38:19.675033 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3832 12:38:19.681606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3833 12:38:19.689107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 12:38:19.691537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 12:38:19.698427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 12:38:19.704939 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 12:38:19.708158 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3838 12:38:19.711675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3839 12:38:19.718023 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3840 12:38:19.721504 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3841 12:38:19.724776 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3842 12:38:19.731845 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3843 12:38:19.734854 ===================================
3844 12:38:19.734935 LPDDR4 DRAM CONFIGURATION
3845 12:38:19.738582 ===================================
3846 12:38:19.741441 EX_ROW_EN[0] = 0x0
3847 12:38:19.741517 EX_ROW_EN[1] = 0x0
3848 12:38:19.745026 LP4Y_EN = 0x0
3849 12:38:19.748369 WORK_FSP = 0x0
3850 12:38:19.748449 WL = 0x2
3851 12:38:19.751612 RL = 0x2
3852 12:38:19.751689 BL = 0x2
3853 12:38:19.754756 RPST = 0x0
3854 12:38:19.754830 RD_PRE = 0x0
3855 12:38:19.757973 WR_PRE = 0x1
3856 12:38:19.758059 WR_PST = 0x0
3857 12:38:19.761413 DBI_WR = 0x0
3858 12:38:19.761489 DBI_RD = 0x0
3859 12:38:19.764482 OTF = 0x1
3860 12:38:19.768192 ===================================
3861 12:38:19.771588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3862 12:38:19.774729 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3863 12:38:19.781377 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 12:38:19.781459 ===================================
3865 12:38:19.784464 LPDDR4 DRAM CONFIGURATION
3866 12:38:19.787975 ===================================
3867 12:38:19.791070 EX_ROW_EN[0] = 0x10
3868 12:38:19.791144 EX_ROW_EN[1] = 0x0
3869 12:38:19.794517 LP4Y_EN = 0x0
3870 12:38:19.794593 WORK_FSP = 0x0
3871 12:38:19.797896 WL = 0x2
3872 12:38:19.798017 RL = 0x2
3873 12:38:19.801219 BL = 0x2
3874 12:38:19.804845 RPST = 0x0
3875 12:38:19.804921 RD_PRE = 0x0
3876 12:38:19.807773 WR_PRE = 0x1
3877 12:38:19.807851 WR_PST = 0x0
3878 12:38:19.811333 DBI_WR = 0x0
3879 12:38:19.811404 DBI_RD = 0x0
3880 12:38:19.814366 OTF = 0x1
3881 12:38:19.817815 ===================================
3882 12:38:19.820958 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3883 12:38:19.826745 nWR fixed to 30
3884 12:38:19.829895 [ModeRegInit_LP4] CH0 RK0
3885 12:38:19.830012 [ModeRegInit_LP4] CH0 RK1
3886 12:38:19.833083 [ModeRegInit_LP4] CH1 RK0
3887 12:38:19.836292 [ModeRegInit_LP4] CH1 RK1
3888 12:38:19.836364 match AC timing 17
3889 12:38:19.843324 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3890 12:38:19.846325 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3891 12:38:19.849797 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3892 12:38:19.856721 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3893 12:38:19.859766 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3894 12:38:19.859848 ==
3895 12:38:19.863054 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 12:38:19.866402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3897 12:38:19.866491 ==
3898 12:38:19.872777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3899 12:38:19.879501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3900 12:38:19.882793 [CA 0] Center 36 (6~66) winsize 61
3901 12:38:19.885910 [CA 1] Center 36 (6~67) winsize 62
3902 12:38:19.889366 [CA 2] Center 34 (4~65) winsize 62
3903 12:38:19.892852 [CA 3] Center 34 (3~65) winsize 63
3904 12:38:19.895842 [CA 4] Center 33 (3~64) winsize 62
3905 12:38:19.899383 [CA 5] Center 33 (2~64) winsize 63
3906 12:38:19.899462
3907 12:38:19.902654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3908 12:38:19.902756
3909 12:38:19.905736 [CATrainingPosCal] consider 1 rank data
3910 12:38:19.909322 u2DelayCellTimex100 = 270/100 ps
3911 12:38:19.912583 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3912 12:38:19.915892 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3913 12:38:19.919531 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3914 12:38:19.922719 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3915 12:38:19.929245 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3916 12:38:19.932593 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3917 12:38:19.932700
3918 12:38:19.935542 CA PerBit enable=1, Macro0, CA PI delay=33
3919 12:38:19.935618
3920 12:38:19.938837 [CBTSetCACLKResult] CA Dly = 33
3921 12:38:19.938913 CS Dly: 4 (0~35)
3922 12:38:19.938976 ==
3923 12:38:19.942197 Dram Type= 6, Freq= 0, CH_0, rank 1
3924 12:38:19.949065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 12:38:19.949146 ==
3926 12:38:19.952365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 12:38:19.959005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3928 12:38:19.961981 [CA 0] Center 36 (6~67) winsize 62
3929 12:38:19.965159 [CA 1] Center 36 (6~67) winsize 62
3930 12:38:19.968797 [CA 2] Center 34 (4~65) winsize 62
3931 12:38:19.972166 [CA 3] Center 34 (4~65) winsize 62
3932 12:38:19.975142 [CA 4] Center 34 (3~65) winsize 63
3933 12:38:19.978672 [CA 5] Center 33 (3~64) winsize 62
3934 12:38:19.978745
3935 12:38:19.982052 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3936 12:38:19.982133
3937 12:38:19.985445 [CATrainingPosCal] consider 2 rank data
3938 12:38:19.988554 u2DelayCellTimex100 = 270/100 ps
3939 12:38:19.991873 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3940 12:38:19.995067 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3941 12:38:20.001821 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 12:38:20.005022 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 12:38:20.008870 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 12:38:20.011795 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3945 12:38:20.011870
3946 12:38:20.015266 CA PerBit enable=1, Macro0, CA PI delay=33
3947 12:38:20.015367
3948 12:38:20.018665 [CBTSetCACLKResult] CA Dly = 33
3949 12:38:20.018740 CS Dly: 5 (0~37)
3950 12:38:20.018803
3951 12:38:20.022175 ----->DramcWriteLeveling(PI) begin...
3952 12:38:20.025057 ==
3953 12:38:20.028710 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 12:38:20.032052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 12:38:20.032128 ==
3956 12:38:20.034913 Write leveling (Byte 0): 33 => 33
3957 12:38:20.038591 Write leveling (Byte 1): 33 => 33
3958 12:38:20.042030 DramcWriteLeveling(PI) end<-----
3959 12:38:20.042131
3960 12:38:20.042225 ==
3961 12:38:20.045024 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 12:38:20.048440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 12:38:20.048515 ==
3964 12:38:20.051535 [Gating] SW mode calibration
3965 12:38:20.058226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3966 12:38:20.064707 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3967 12:38:20.068038 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 12:38:20.071552 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 12:38:20.078054 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3970 12:38:20.081639 0 9 12 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 1)
3971 12:38:20.084839 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3972 12:38:20.088161 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 12:38:20.095062 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 12:38:20.098081 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 12:38:20.101286 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 12:38:20.107934 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 12:38:20.111515 0 10 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
3978 12:38:20.114672 0 10 12 | B1->B0 | 2424 3939 | 1 0 | (0 0) (0 0)
3979 12:38:20.121371 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
3980 12:38:20.124414 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 12:38:20.127982 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 12:38:20.134515 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 12:38:20.137748 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 12:38:20.141226 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 12:38:20.148147 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 12:38:20.151335 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3987 12:38:20.154669 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3988 12:38:20.160953 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 12:38:20.164736 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 12:38:20.168123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:38:20.174420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:38:20.177671 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:38:20.181003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:38:20.187935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:38:20.191183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:38:20.194599 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:38:20.201031 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:38:20.204335 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:38:20.207831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:38:20.211110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:38:20.217666 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4002 12:38:20.221405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4003 12:38:20.224767 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4004 12:38:20.227710 Total UI for P1: 0, mck2ui 16
4005 12:38:20.231021 best dqsien dly found for B0: ( 0, 13, 10)
4006 12:38:20.237626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:38:20.237738 Total UI for P1: 0, mck2ui 16
4008 12:38:20.244788 best dqsien dly found for B1: ( 0, 13, 16)
4009 12:38:20.248150 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4010 12:38:20.251067 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4011 12:38:20.251141
4012 12:38:20.254841 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4013 12:38:20.258133 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4014 12:38:20.260985 [Gating] SW calibration Done
4015 12:38:20.261085 ==
4016 12:38:20.264621 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 12:38:20.267847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 12:38:20.267936 ==
4019 12:38:20.271312 RX Vref Scan: 0
4020 12:38:20.271398
4021 12:38:20.271484 RX Vref 0 -> 0, step: 1
4022 12:38:20.274253
4023 12:38:20.274338 RX Delay -230 -> 252, step: 16
4024 12:38:20.280916 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4025 12:38:20.284517 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4026 12:38:20.287908 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4027 12:38:20.291056 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4028 12:38:20.294272 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4029 12:38:20.301117 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4030 12:38:20.304717 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4031 12:38:20.307745 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4032 12:38:20.311049 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4033 12:38:20.317420 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4034 12:38:20.321175 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4035 12:38:20.324442 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4036 12:38:20.327673 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4037 12:38:20.334285 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4038 12:38:20.337693 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4039 12:38:20.340828 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4040 12:38:20.340903 ==
4041 12:38:20.344471 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 12:38:20.347512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 12:38:20.347586 ==
4044 12:38:20.351239 DQS Delay:
4045 12:38:20.351309 DQS0 = 0, DQS1 = 0
4046 12:38:20.354246 DQM Delay:
4047 12:38:20.354318 DQM0 = 53, DQM1 = 40
4048 12:38:20.354385 DQ Delay:
4049 12:38:20.357828 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4050 12:38:20.361134 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4051 12:38:20.364344 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4052 12:38:20.367415 DQ12 =49, DQ13 =41, DQ14 =57, DQ15 =49
4053 12:38:20.367501
4054 12:38:20.367567
4055 12:38:20.371085 ==
4056 12:38:20.374221 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 12:38:20.377209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 12:38:20.377281 ==
4059 12:38:20.377349
4060 12:38:20.377407
4061 12:38:20.380892 TX Vref Scan disable
4062 12:38:20.380965 == TX Byte 0 ==
4063 12:38:20.384091 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4064 12:38:20.390489 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4065 12:38:20.390563 == TX Byte 1 ==
4066 12:38:20.397159 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4067 12:38:20.400694 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4068 12:38:20.400767 ==
4069 12:38:20.404003 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 12:38:20.407290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 12:38:20.407363 ==
4072 12:38:20.407425
4073 12:38:20.407484
4074 12:38:20.410614 TX Vref Scan disable
4075 12:38:20.413788 == TX Byte 0 ==
4076 12:38:20.417232 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 12:38:20.420362 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 12:38:20.424126 == TX Byte 1 ==
4079 12:38:20.427307 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4080 12:38:20.430423 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4081 12:38:20.430501
4082 12:38:20.433726 [DATLAT]
4083 12:38:20.433799 Freq=600, CH0 RK0
4084 12:38:20.433862
4085 12:38:20.437162 DATLAT Default: 0x9
4086 12:38:20.437234 0, 0xFFFF, sum = 0
4087 12:38:20.440564 1, 0xFFFF, sum = 0
4088 12:38:20.440638 2, 0xFFFF, sum = 0
4089 12:38:20.443783 3, 0xFFFF, sum = 0
4090 12:38:20.443858 4, 0xFFFF, sum = 0
4091 12:38:20.446884 5, 0xFFFF, sum = 0
4092 12:38:20.446964 6, 0xFFFF, sum = 0
4093 12:38:20.450314 7, 0xFFFF, sum = 0
4094 12:38:20.450395 8, 0x0, sum = 1
4095 12:38:20.453717 9, 0x0, sum = 2
4096 12:38:20.453797 10, 0x0, sum = 3
4097 12:38:20.456850 11, 0x0, sum = 4
4098 12:38:20.456923 best_step = 9
4099 12:38:20.456991
4100 12:38:20.457047 ==
4101 12:38:20.460506 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 12:38:20.463774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 12:38:20.467076 ==
4104 12:38:20.467157 RX Vref Scan: 1
4105 12:38:20.467230
4106 12:38:20.470520 RX Vref 0 -> 0, step: 1
4107 12:38:20.470597
4108 12:38:20.473449 RX Delay -179 -> 252, step: 8
4109 12:38:20.473523
4110 12:38:20.476893 Set Vref, RX VrefLevel [Byte0]: 57
4111 12:38:20.480002 [Byte1]: 48
4112 12:38:20.480077
4113 12:38:20.483385 Final RX Vref Byte 0 = 57 to rank0
4114 12:38:20.487031 Final RX Vref Byte 1 = 48 to rank0
4115 12:38:20.490207 Final RX Vref Byte 0 = 57 to rank1
4116 12:38:20.493407 Final RX Vref Byte 1 = 48 to rank1==
4117 12:38:20.496959 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 12:38:20.500325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 12:38:20.500421 ==
4120 12:38:20.500499 DQS Delay:
4121 12:38:20.503472 DQS0 = 0, DQS1 = 0
4122 12:38:20.503543 DQM Delay:
4123 12:38:20.506760 DQM0 = 50, DQM1 = 37
4124 12:38:20.506835 DQ Delay:
4125 12:38:20.510322 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =48
4126 12:38:20.513627 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4127 12:38:20.516893 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4128 12:38:20.520226 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4129 12:38:20.520307
4130 12:38:20.520371
4131 12:38:20.529868 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4132 12:38:20.530010 CH0 RK0: MR19=808, MR18=5751
4133 12:38:20.536686 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4134 12:38:20.536772
4135 12:38:20.540146 ----->DramcWriteLeveling(PI) begin...
4136 12:38:20.540229 ==
4137 12:38:20.543477 Dram Type= 6, Freq= 0, CH_0, rank 1
4138 12:38:20.550161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:38:20.550241 ==
4140 12:38:20.553587 Write leveling (Byte 0): 32 => 32
4141 12:38:20.556598 Write leveling (Byte 1): 32 => 32
4142 12:38:20.556678 DramcWriteLeveling(PI) end<-----
4143 12:38:20.556742
4144 12:38:20.559889 ==
4145 12:38:20.563170 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 12:38:20.566434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 12:38:20.566521 ==
4148 12:38:20.569861 [Gating] SW mode calibration
4149 12:38:20.576673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4150 12:38:20.580059 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4151 12:38:20.586503 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 12:38:20.589756 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 12:38:20.593336 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 12:38:20.599636 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 1)
4155 12:38:20.603267 0 9 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4156 12:38:20.606432 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 12:38:20.612861 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 12:38:20.616387 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 12:38:20.619573 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 12:38:20.626073 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 12:38:20.629817 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 12:38:20.632667 0 10 12 | B1->B0 | 2b2b 3131 | 0 0 | (1 1) (0 0)
4163 12:38:20.639316 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4164 12:38:20.642929 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 12:38:20.646172 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 12:38:20.652427 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 12:38:20.655816 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 12:38:20.659256 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 12:38:20.665668 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 12:38:20.668846 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4171 12:38:20.672541 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 12:38:20.679093 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 12:38:20.682212 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 12:38:20.685537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:38:20.692097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:38:20.695714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:38:20.698967 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:38:20.705470 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:38:20.709217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:38:20.712786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:38:20.718752 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:38:20.722249 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:38:20.725367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:38:20.728850 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:38:20.735446 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:38:20.738874 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4187 12:38:20.741974 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4188 12:38:20.745909 Total UI for P1: 0, mck2ui 16
4189 12:38:20.748795 best dqsien dly found for B0: ( 0, 13, 12)
4190 12:38:20.755317 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:38:20.758342 Total UI for P1: 0, mck2ui 16
4192 12:38:20.761728 best dqsien dly found for B1: ( 0, 13, 14)
4193 12:38:20.765262 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4194 12:38:20.768373 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4195 12:38:20.768460
4196 12:38:20.771779 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4197 12:38:20.775108 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4198 12:38:20.778760 [Gating] SW calibration Done
4199 12:38:20.778836 ==
4200 12:38:20.781705 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 12:38:20.785277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 12:38:20.785355 ==
4203 12:38:20.788924 RX Vref Scan: 0
4204 12:38:20.788997
4205 12:38:20.791792 RX Vref 0 -> 0, step: 1
4206 12:38:20.791865
4207 12:38:20.791926 RX Delay -230 -> 252, step: 16
4208 12:38:20.798577 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4209 12:38:20.801834 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4210 12:38:20.805285 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4211 12:38:20.808509 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4212 12:38:20.815468 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4213 12:38:20.818429 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4214 12:38:20.821680 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4215 12:38:20.825093 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4216 12:38:20.828367 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4217 12:38:20.835154 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4218 12:38:20.838297 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4219 12:38:20.841823 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4220 12:38:20.845247 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4221 12:38:20.851854 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4222 12:38:20.855066 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4223 12:38:20.858360 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4224 12:38:20.858476 ==
4225 12:38:20.861516 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 12:38:20.864917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 12:38:20.868297 ==
4228 12:38:20.868383 DQS Delay:
4229 12:38:20.868470 DQS0 = 0, DQS1 = 0
4230 12:38:20.872043 DQM Delay:
4231 12:38:20.872128 DQM0 = 51, DQM1 = 44
4232 12:38:20.875116 DQ Delay:
4233 12:38:20.875227 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4234 12:38:20.878170 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4235 12:38:20.881559 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4236 12:38:20.884950 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4237 12:38:20.885035
4238 12:38:20.888217
4239 12:38:20.888303 ==
4240 12:38:20.891777 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 12:38:20.895114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 12:38:20.895201 ==
4243 12:38:20.895288
4244 12:38:20.895370
4245 12:38:20.898221 TX Vref Scan disable
4246 12:38:20.898306 == TX Byte 0 ==
4247 12:38:20.905176 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4248 12:38:20.908379 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4249 12:38:20.908465 == TX Byte 1 ==
4250 12:38:20.914965 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4251 12:38:20.918290 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4252 12:38:20.918378 ==
4253 12:38:20.921606 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 12:38:20.924847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 12:38:20.924932 ==
4256 12:38:20.924999
4257 12:38:20.925086
4258 12:38:20.928002 TX Vref Scan disable
4259 12:38:20.932141 == TX Byte 0 ==
4260 12:38:20.934794 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4261 12:38:20.937933 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4262 12:38:20.941323 == TX Byte 1 ==
4263 12:38:20.944790 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4264 12:38:20.948106 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4265 12:38:20.948190
4266 12:38:20.951694 [DATLAT]
4267 12:38:20.951779 Freq=600, CH0 RK1
4268 12:38:20.951846
4269 12:38:20.954868 DATLAT Default: 0x9
4270 12:38:20.954952 0, 0xFFFF, sum = 0
4271 12:38:20.958269 1, 0xFFFF, sum = 0
4272 12:38:20.958355 2, 0xFFFF, sum = 0
4273 12:38:20.961547 3, 0xFFFF, sum = 0
4274 12:38:20.961633 4, 0xFFFF, sum = 0
4275 12:38:20.964709 5, 0xFFFF, sum = 0
4276 12:38:20.964819 6, 0xFFFF, sum = 0
4277 12:38:20.967979 7, 0xFFFF, sum = 0
4278 12:38:20.968090 8, 0x0, sum = 1
4279 12:38:20.971382 9, 0x0, sum = 2
4280 12:38:20.971460 10, 0x0, sum = 3
4281 12:38:20.974472 11, 0x0, sum = 4
4282 12:38:20.974547 best_step = 9
4283 12:38:20.974610
4284 12:38:20.974669 ==
4285 12:38:20.978154 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 12:38:20.981188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 12:38:20.984683 ==
4288 12:38:20.984761 RX Vref Scan: 0
4289 12:38:20.984833
4290 12:38:20.987795 RX Vref 0 -> 0, step: 1
4291 12:38:20.987867
4292 12:38:20.991132 RX Delay -179 -> 252, step: 8
4293 12:38:20.994969 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4294 12:38:20.997861 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4295 12:38:21.004817 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4296 12:38:21.008092 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4297 12:38:21.011497 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4298 12:38:21.014922 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4299 12:38:21.017983 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4300 12:38:21.024595 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4301 12:38:21.027872 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4302 12:38:21.031089 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4303 12:38:21.034734 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4304 12:38:21.040955 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4305 12:38:21.044295 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4306 12:38:21.048034 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4307 12:38:21.051140 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4308 12:38:21.054562 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4309 12:38:21.054641 ==
4310 12:38:21.057862 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 12:38:21.064482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 12:38:21.064563 ==
4313 12:38:21.064627 DQS Delay:
4314 12:38:21.068017 DQS0 = 0, DQS1 = 0
4315 12:38:21.068096 DQM Delay:
4316 12:38:21.070964 DQM0 = 49, DQM1 = 42
4317 12:38:21.071037 DQ Delay:
4318 12:38:21.074309 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4319 12:38:21.077374 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4320 12:38:21.081162 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4321 12:38:21.084253 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =48
4322 12:38:21.084336
4323 12:38:21.084400
4324 12:38:21.090975 [DQSOSCAuto] RK1, (LSB)MR18= 0x632f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4325 12:38:21.094255 CH0 RK1: MR19=808, MR18=632F
4326 12:38:21.100931 CH0_RK1: MR19=0x808, MR18=0x632F, DQSOSC=391, MR23=63, INC=171, DEC=114
4327 12:38:21.104126 [RxdqsGatingPostProcess] freq 600
4328 12:38:21.110568 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4329 12:38:21.110651 Pre-setting of DQS Precalculation
4330 12:38:21.117540 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4331 12:38:21.117624 ==
4332 12:38:21.120907 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 12:38:21.123848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 12:38:21.123931 ==
4335 12:38:21.131007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4336 12:38:21.137171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4337 12:38:21.140700 [CA 0] Center 35 (5~66) winsize 62
4338 12:38:21.143995 [CA 1] Center 35 (5~66) winsize 62
4339 12:38:21.147123 [CA 2] Center 34 (3~65) winsize 63
4340 12:38:21.150736 [CA 3] Center 33 (3~64) winsize 62
4341 12:38:21.153837 [CA 4] Center 34 (3~65) winsize 63
4342 12:38:21.157257 [CA 5] Center 33 (3~64) winsize 62
4343 12:38:21.157338
4344 12:38:21.160445 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4345 12:38:21.160527
4346 12:38:21.164063 [CATrainingPosCal] consider 1 rank data
4347 12:38:21.167117 u2DelayCellTimex100 = 270/100 ps
4348 12:38:21.170253 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4349 12:38:21.173643 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4350 12:38:21.177089 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4351 12:38:21.180270 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4352 12:38:21.183804 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4353 12:38:21.186940 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4354 12:38:21.187022
4355 12:38:21.193700 CA PerBit enable=1, Macro0, CA PI delay=33
4356 12:38:21.193783
4357 12:38:21.196888 [CBTSetCACLKResult] CA Dly = 33
4358 12:38:21.196998 CS Dly: 4 (0~35)
4359 12:38:21.197095 ==
4360 12:38:21.200579 Dram Type= 6, Freq= 0, CH_1, rank 1
4361 12:38:21.203780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 12:38:21.203851 ==
4363 12:38:21.210271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4364 12:38:21.217230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4365 12:38:21.220155 [CA 0] Center 35 (5~66) winsize 62
4366 12:38:21.223724 [CA 1] Center 35 (5~66) winsize 62
4367 12:38:21.227086 [CA 2] Center 34 (4~65) winsize 62
4368 12:38:21.230048 [CA 3] Center 34 (4~65) winsize 62
4369 12:38:21.233661 [CA 4] Center 34 (4~65) winsize 62
4370 12:38:21.236892 [CA 5] Center 34 (4~64) winsize 61
4371 12:38:21.236988
4372 12:38:21.240439 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4373 12:38:21.240522
4374 12:38:21.243822 [CATrainingPosCal] consider 2 rank data
4375 12:38:21.247230 u2DelayCellTimex100 = 270/100 ps
4376 12:38:21.250285 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4377 12:38:21.253872 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4378 12:38:21.257071 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 12:38:21.260094 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4380 12:38:21.263959 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 12:38:21.267032 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4382 12:38:21.267159
4383 12:38:21.273467 CA PerBit enable=1, Macro0, CA PI delay=34
4384 12:38:21.273552
4385 12:38:21.276689 [CBTSetCACLKResult] CA Dly = 34
4386 12:38:21.276773 CS Dly: 5 (0~37)
4387 12:38:21.276839
4388 12:38:21.280372 ----->DramcWriteLeveling(PI) begin...
4389 12:38:21.280458 ==
4390 12:38:21.283627 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 12:38:21.287000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 12:38:21.287084 ==
4393 12:38:21.290168 Write leveling (Byte 0): 31 => 31
4394 12:38:21.293382 Write leveling (Byte 1): 31 => 31
4395 12:38:21.296915 DramcWriteLeveling(PI) end<-----
4396 12:38:21.296999
4397 12:38:21.297064 ==
4398 12:38:21.300266 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 12:38:21.303671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 12:38:21.307230 ==
4401 12:38:21.307314 [Gating] SW mode calibration
4402 12:38:21.316965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4403 12:38:21.320215 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4404 12:38:21.323340 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 12:38:21.330218 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 12:38:21.333436 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 12:38:21.336666 0 9 12 | B1->B0 | 2c2c 2d2d | 1 1 | (1 0) (1 0)
4408 12:38:21.343868 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 12:38:21.346622 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 12:38:21.349798 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:38:21.357062 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:38:21.360195 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:38:21.363190 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:38:21.369868 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4415 12:38:21.373280 0 10 12 | B1->B0 | 3e3e 3d3d | 0 0 | (1 1) (1 1)
4416 12:38:21.376659 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 12:38:21.383252 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 12:38:21.386425 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 12:38:21.389517 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:38:21.396628 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:38:21.399966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:38:21.403173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:38:21.409806 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4424 12:38:21.413141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 12:38:21.416391 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:38:21.422786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:38:21.426580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:38:21.429873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:38:21.432782 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:38:21.439735 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:38:21.442660 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:38:21.446546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:38:21.452883 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:38:21.456181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:38:21.459872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:38:21.466283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:38:21.469876 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:38:21.472684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4439 12:38:21.479600 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4440 12:38:21.482845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:38:21.486222 Total UI for P1: 0, mck2ui 16
4442 12:38:21.489515 best dqsien dly found for B0: ( 0, 13, 10)
4443 12:38:21.493034 Total UI for P1: 0, mck2ui 16
4444 12:38:21.496092 best dqsien dly found for B1: ( 0, 13, 12)
4445 12:38:21.499760 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4446 12:38:21.503103 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4447 12:38:21.503180
4448 12:38:21.506401 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4449 12:38:21.509652 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4450 12:38:21.512663 [Gating] SW calibration Done
4451 12:38:21.512797 ==
4452 12:38:21.515972 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 12:38:21.522935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 12:38:21.523023 ==
4455 12:38:21.523090 RX Vref Scan: 0
4456 12:38:21.523150
4457 12:38:21.526153 RX Vref 0 -> 0, step: 1
4458 12:38:21.526250
4459 12:38:21.529580 RX Delay -230 -> 252, step: 16
4460 12:38:21.532875 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4461 12:38:21.536027 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4462 12:38:21.539275 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4463 12:38:21.546463 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4464 12:38:21.549181 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4465 12:38:21.552897 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4466 12:38:21.556115 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4467 12:38:21.559664 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4468 12:38:21.565718 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4469 12:38:21.569273 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4470 12:38:21.572582 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4471 12:38:21.576064 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4472 12:38:21.582421 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4473 12:38:21.585750 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4474 12:38:21.588979 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4475 12:38:21.592336 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4476 12:38:21.592438 ==
4477 12:38:21.595825 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 12:38:21.602243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 12:38:21.602341 ==
4480 12:38:21.602411 DQS Delay:
4481 12:38:21.605341 DQS0 = 0, DQS1 = 0
4482 12:38:21.605429 DQM Delay:
4483 12:38:21.608954 DQM0 = 50, DQM1 = 43
4484 12:38:21.609062 DQ Delay:
4485 12:38:21.612068 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4486 12:38:21.615264 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4487 12:38:21.619123 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =41
4488 12:38:21.621919 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4489 12:38:21.622022
4490 12:38:21.622086
4491 12:38:21.622144 ==
4492 12:38:21.625390 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 12:38:21.628657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 12:38:21.628737 ==
4495 12:38:21.628809
4496 12:38:21.628871
4497 12:38:21.632009 TX Vref Scan disable
4498 12:38:21.635675 == TX Byte 0 ==
4499 12:38:21.638669 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 12:38:21.642148 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 12:38:21.645437 == TX Byte 1 ==
4502 12:38:21.648545 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4503 12:38:21.652360 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4504 12:38:21.652434 ==
4505 12:38:21.655616 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 12:38:21.658931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 12:38:21.662331 ==
4508 12:38:21.662411
4509 12:38:21.662472
4510 12:38:21.662530 TX Vref Scan disable
4511 12:38:21.665820 == TX Byte 0 ==
4512 12:38:21.669011 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 12:38:21.675582 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 12:38:21.675655 == TX Byte 1 ==
4515 12:38:21.678845 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 12:38:21.685505 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 12:38:21.685583
4518 12:38:21.685646 [DATLAT]
4519 12:38:21.685706 Freq=600, CH1 RK0
4520 12:38:21.685774
4521 12:38:21.689146 DATLAT Default: 0x9
4522 12:38:21.689231 0, 0xFFFF, sum = 0
4523 12:38:21.692380 1, 0xFFFF, sum = 0
4524 12:38:21.692449 2, 0xFFFF, sum = 0
4525 12:38:21.695710 3, 0xFFFF, sum = 0
4526 12:38:21.698892 4, 0xFFFF, sum = 0
4527 12:38:21.698961 5, 0xFFFF, sum = 0
4528 12:38:21.702170 6, 0xFFFF, sum = 0
4529 12:38:21.702244 7, 0xFFFF, sum = 0
4530 12:38:21.702317 8, 0x0, sum = 1
4531 12:38:21.705686 9, 0x0, sum = 2
4532 12:38:21.705763 10, 0x0, sum = 3
4533 12:38:21.709173 11, 0x0, sum = 4
4534 12:38:21.709258 best_step = 9
4535 12:38:21.709322
4536 12:38:21.709381 ==
4537 12:38:21.712117 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 12:38:21.718907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 12:38:21.719028 ==
4540 12:38:21.719122 RX Vref Scan: 1
4541 12:38:21.719248
4542 12:38:21.722085 RX Vref 0 -> 0, step: 1
4543 12:38:21.722160
4544 12:38:21.725523 RX Delay -179 -> 252, step: 8
4545 12:38:21.725596
4546 12:38:21.728678 Set Vref, RX VrefLevel [Byte0]: 51
4547 12:38:21.732247 [Byte1]: 53
4548 12:38:21.732319
4549 12:38:21.735640 Final RX Vref Byte 0 = 51 to rank0
4550 12:38:21.738987 Final RX Vref Byte 1 = 53 to rank0
4551 12:38:21.741968 Final RX Vref Byte 0 = 51 to rank1
4552 12:38:21.745864 Final RX Vref Byte 1 = 53 to rank1==
4553 12:38:21.748946 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 12:38:21.751874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 12:38:21.751951 ==
4556 12:38:21.755358 DQS Delay:
4557 12:38:21.755434 DQS0 = 0, DQS1 = 0
4558 12:38:21.755493 DQM Delay:
4559 12:38:21.758672 DQM0 = 48, DQM1 = 40
4560 12:38:21.758743 DQ Delay:
4561 12:38:21.761835 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4562 12:38:21.765233 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4563 12:38:21.768980 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4564 12:38:21.772264 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4565 12:38:21.772341
4566 12:38:21.772404
4567 12:38:21.781892 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f76, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4568 12:38:21.785568 CH1 RK0: MR19=808, MR18=4F76
4569 12:38:21.789031 CH1_RK0: MR19=0x808, MR18=0x4F76, DQSOSC=387, MR23=63, INC=175, DEC=116
4570 12:38:21.789115
4571 12:38:21.792138 ----->DramcWriteLeveling(PI) begin...
4572 12:38:21.795410 ==
4573 12:38:21.798862 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 12:38:21.801859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:38:21.801951 ==
4576 12:38:21.805144 Write leveling (Byte 0): 29 => 29
4577 12:38:21.808528 Write leveling (Byte 1): 29 => 29
4578 12:38:21.811826 DramcWriteLeveling(PI) end<-----
4579 12:38:21.811909
4580 12:38:21.811973 ==
4581 12:38:21.815234 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 12:38:21.818385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 12:38:21.818471 ==
4584 12:38:21.821832 [Gating] SW mode calibration
4585 12:38:21.828911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4586 12:38:21.831975 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4587 12:38:21.838787 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 12:38:21.842101 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 12:38:21.845116 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
4590 12:38:21.851784 0 9 12 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 1)
4591 12:38:21.855553 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4592 12:38:21.858328 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 12:38:21.865000 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 12:38:21.868459 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 12:38:21.871609 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 12:38:21.878281 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 12:38:21.881820 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4598 12:38:21.884964 0 10 12 | B1->B0 | 3b3b 3131 | 1 0 | (0 0) (0 0)
4599 12:38:21.891769 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 12:38:21.895105 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 12:38:21.898334 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 12:38:21.904909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 12:38:21.908183 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 12:38:21.911770 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 12:38:21.918385 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 12:38:21.921500 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4607 12:38:21.924961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 12:38:21.931414 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 12:38:21.934857 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:38:21.937967 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:38:21.944733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:38:21.947956 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:38:21.951274 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:38:21.958028 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:38:21.961374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:38:21.964391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:38:21.971073 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:38:21.974599 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:38:21.977801 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:38:21.984347 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:38:21.987778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4622 12:38:21.991351 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4623 12:38:21.994483 Total UI for P1: 0, mck2ui 16
4624 12:38:21.998138 best dqsien dly found for B1: ( 0, 13, 8)
4625 12:38:22.001194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 12:38:22.004462 Total UI for P1: 0, mck2ui 16
4627 12:38:22.007901 best dqsien dly found for B0: ( 0, 13, 10)
4628 12:38:22.011293 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4629 12:38:22.017603 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4630 12:38:22.017721
4631 12:38:22.020916 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4632 12:38:22.024521 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4633 12:38:22.027907 [Gating] SW calibration Done
4634 12:38:22.027995 ==
4635 12:38:22.031278 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 12:38:22.034445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 12:38:22.034555 ==
4638 12:38:22.034656 RX Vref Scan: 0
4639 12:38:22.034763
4640 12:38:22.037758 RX Vref 0 -> 0, step: 1
4641 12:38:22.037858
4642 12:38:22.041462 RX Delay -230 -> 252, step: 16
4643 12:38:22.044456 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4644 12:38:22.047854 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4645 12:38:22.054602 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4646 12:38:22.057815 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4647 12:38:22.061279 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4648 12:38:22.064170 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4649 12:38:22.071138 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4650 12:38:22.074469 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4651 12:38:22.077519 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4652 12:38:22.081194 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4653 12:38:22.084373 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4654 12:38:22.090818 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4655 12:38:22.094668 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4656 12:38:22.097588 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4657 12:38:22.101409 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4658 12:38:22.107653 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4659 12:38:22.107768 ==
4660 12:38:22.110863 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 12:38:22.114318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 12:38:22.114425 ==
4663 12:38:22.114519 DQS Delay:
4664 12:38:22.117447 DQS0 = 0, DQS1 = 0
4665 12:38:22.117548 DQM Delay:
4666 12:38:22.120780 DQM0 = 52, DQM1 = 47
4667 12:38:22.120915 DQ Delay:
4668 12:38:22.124247 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4669 12:38:22.127544 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4670 12:38:22.130898 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4671 12:38:22.134369 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4672 12:38:22.134473
4673 12:38:22.134542
4674 12:38:22.134605 ==
4675 12:38:22.137387 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 12:38:22.141339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 12:38:22.141465 ==
4678 12:38:22.141584
4679 12:38:22.144188
4680 12:38:22.144292 TX Vref Scan disable
4681 12:38:22.147438 == TX Byte 0 ==
4682 12:38:22.150892 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4683 12:38:22.153959 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4684 12:38:22.157224 == TX Byte 1 ==
4685 12:38:22.160824 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4686 12:38:22.164195 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4687 12:38:22.164311 ==
4688 12:38:22.167416 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 12:38:22.174323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 12:38:22.174426 ==
4691 12:38:22.174496
4692 12:38:22.174557
4693 12:38:22.174620 TX Vref Scan disable
4694 12:38:22.178872 == TX Byte 0 ==
4695 12:38:22.181743 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 12:38:22.188393 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 12:38:22.188512 == TX Byte 1 ==
4698 12:38:22.191641 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4699 12:38:22.198586 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4700 12:38:22.198695
4701 12:38:22.198788 [DATLAT]
4702 12:38:22.198880 Freq=600, CH1 RK1
4703 12:38:22.198988
4704 12:38:22.201901 DATLAT Default: 0x9
4705 12:38:22.202007 0, 0xFFFF, sum = 0
4706 12:38:22.205348 1, 0xFFFF, sum = 0
4707 12:38:22.205458 2, 0xFFFF, sum = 0
4708 12:38:22.208596 3, 0xFFFF, sum = 0
4709 12:38:22.208682 4, 0xFFFF, sum = 0
4710 12:38:22.211796 5, 0xFFFF, sum = 0
4711 12:38:22.215442 6, 0xFFFF, sum = 0
4712 12:38:22.215547 7, 0xFFFF, sum = 0
4713 12:38:22.215630 8, 0x0, sum = 1
4714 12:38:22.218761 9, 0x0, sum = 2
4715 12:38:22.218846 10, 0x0, sum = 3
4716 12:38:22.221833 11, 0x0, sum = 4
4717 12:38:22.221919 best_step = 9
4718 12:38:22.222025
4719 12:38:22.222087 ==
4720 12:38:22.224992 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 12:38:22.232063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 12:38:22.232199 ==
4723 12:38:22.232285 RX Vref Scan: 0
4724 12:38:22.232379
4725 12:38:22.235136 RX Vref 0 -> 0, step: 1
4726 12:38:22.235240
4727 12:38:22.238976 RX Delay -163 -> 252, step: 8
4728 12:38:22.241742 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4729 12:38:22.245350 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4730 12:38:22.251866 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4731 12:38:22.255172 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4732 12:38:22.258519 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4733 12:38:22.261716 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4734 12:38:22.265234 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4735 12:38:22.271671 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4736 12:38:22.275272 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4737 12:38:22.278491 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4738 12:38:22.281509 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4739 12:38:22.288450 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4740 12:38:22.291745 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4741 12:38:22.294905 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4742 12:38:22.298337 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4743 12:38:22.301853 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4744 12:38:22.301984 ==
4745 12:38:22.305057 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 12:38:22.311901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 12:38:22.311986 ==
4748 12:38:22.312053 DQS Delay:
4749 12:38:22.315109 DQS0 = 0, DQS1 = 0
4750 12:38:22.315192 DQM Delay:
4751 12:38:22.318315 DQM0 = 49, DQM1 = 43
4752 12:38:22.318400 DQ Delay:
4753 12:38:22.321744 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4754 12:38:22.324905 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4755 12:38:22.328549 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4756 12:38:22.331618 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4757 12:38:22.331723
4758 12:38:22.331857
4759 12:38:22.338203 [DQSOSCAuto] RK1, (LSB)MR18= 0x551c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4760 12:38:22.341734 CH1 RK1: MR19=808, MR18=551C
4761 12:38:22.348392 CH1_RK1: MR19=0x808, MR18=0x551C, DQSOSC=393, MR23=63, INC=169, DEC=113
4762 12:38:22.351736 [RxdqsGatingPostProcess] freq 600
4763 12:38:22.354817 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4764 12:38:22.358237 Pre-setting of DQS Precalculation
4765 12:38:22.364936 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4766 12:38:22.371508 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4767 12:38:22.378061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4768 12:38:22.378149
4769 12:38:22.378236
4770 12:38:22.381371 [Calibration Summary] 1200 Mbps
4771 12:38:22.381483 CH 0, Rank 0
4772 12:38:22.384562 SW Impedance : PASS
4773 12:38:22.388070 DUTY Scan : NO K
4774 12:38:22.388156 ZQ Calibration : PASS
4775 12:38:22.391388 Jitter Meter : NO K
4776 12:38:22.394554 CBT Training : PASS
4777 12:38:22.394640 Write leveling : PASS
4778 12:38:22.398363 RX DQS gating : PASS
4779 12:38:22.401677 RX DQ/DQS(RDDQC) : PASS
4780 12:38:22.401763 TX DQ/DQS : PASS
4781 12:38:22.404668 RX DATLAT : PASS
4782 12:38:22.408335 RX DQ/DQS(Engine): PASS
4783 12:38:22.408420 TX OE : NO K
4784 12:38:22.411413 All Pass.
4785 12:38:22.411500
4786 12:38:22.411586 CH 0, Rank 1
4787 12:38:22.415156 SW Impedance : PASS
4788 12:38:22.415242 DUTY Scan : NO K
4789 12:38:22.418263 ZQ Calibration : PASS
4790 12:38:22.421400 Jitter Meter : NO K
4791 12:38:22.421486 CBT Training : PASS
4792 12:38:22.424964 Write leveling : PASS
4793 12:38:22.425049 RX DQS gating : PASS
4794 12:38:22.428116 RX DQ/DQS(RDDQC) : PASS
4795 12:38:22.431236 TX DQ/DQS : PASS
4796 12:38:22.431322 RX DATLAT : PASS
4797 12:38:22.435225 RX DQ/DQS(Engine): PASS
4798 12:38:22.437876 TX OE : NO K
4799 12:38:22.438020 All Pass.
4800 12:38:22.438106
4801 12:38:22.438186 CH 1, Rank 0
4802 12:38:22.441543 SW Impedance : PASS
4803 12:38:22.444877 DUTY Scan : NO K
4804 12:38:22.444963 ZQ Calibration : PASS
4805 12:38:22.448033 Jitter Meter : NO K
4806 12:38:22.451265 CBT Training : PASS
4807 12:38:22.451351 Write leveling : PASS
4808 12:38:22.454843 RX DQS gating : PASS
4809 12:38:22.457934 RX DQ/DQS(RDDQC) : PASS
4810 12:38:22.458059 TX DQ/DQS : PASS
4811 12:38:22.461169 RX DATLAT : PASS
4812 12:38:22.464738 RX DQ/DQS(Engine): PASS
4813 12:38:22.464824 TX OE : NO K
4814 12:38:22.464910 All Pass.
4815 12:38:22.467784
4816 12:38:22.467870 CH 1, Rank 1
4817 12:38:22.471149 SW Impedance : PASS
4818 12:38:22.471235 DUTY Scan : NO K
4819 12:38:22.474560 ZQ Calibration : PASS
4820 12:38:22.474646 Jitter Meter : NO K
4821 12:38:22.477854 CBT Training : PASS
4822 12:38:22.481421 Write leveling : PASS
4823 12:38:22.481523 RX DQS gating : PASS
4824 12:38:22.484620 RX DQ/DQS(RDDQC) : PASS
4825 12:38:22.487767 TX DQ/DQS : PASS
4826 12:38:22.487854 RX DATLAT : PASS
4827 12:38:22.491246 RX DQ/DQS(Engine): PASS
4828 12:38:22.494472 TX OE : NO K
4829 12:38:22.494559 All Pass.
4830 12:38:22.494644
4831 12:38:22.497718 DramC Write-DBI off
4832 12:38:22.497829 PER_BANK_REFRESH: Hybrid Mode
4833 12:38:22.501696 TX_TRACKING: ON
4834 12:38:22.508168 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4835 12:38:22.511422 [FAST_K] Save calibration result to emmc
4836 12:38:22.518167 dramc_set_vcore_voltage set vcore to 662500
4837 12:38:22.518253 Read voltage for 933, 3
4838 12:38:22.521633 Vio18 = 0
4839 12:38:22.521719 Vcore = 662500
4840 12:38:22.521823 Vdram = 0
4841 12:38:22.524584 Vddq = 0
4842 12:38:22.524669 Vmddr = 0
4843 12:38:22.528027 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4844 12:38:22.534859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4845 12:38:22.538240 MEM_TYPE=3, freq_sel=17
4846 12:38:22.538319 sv_algorithm_assistance_LP4_1600
4847 12:38:22.544665 ============ PULL DRAM RESETB DOWN ============
4848 12:38:22.547888 ========== PULL DRAM RESETB DOWN end =========
4849 12:38:22.551250 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4850 12:38:22.554561 ===================================
4851 12:38:22.557697 LPDDR4 DRAM CONFIGURATION
4852 12:38:22.561649 ===================================
4853 12:38:22.564393 EX_ROW_EN[0] = 0x0
4854 12:38:22.564472 EX_ROW_EN[1] = 0x0
4855 12:38:22.567898 LP4Y_EN = 0x0
4856 12:38:22.567978 WORK_FSP = 0x0
4857 12:38:22.571113 WL = 0x3
4858 12:38:22.571189 RL = 0x3
4859 12:38:22.574774 BL = 0x2
4860 12:38:22.574855 RPST = 0x0
4861 12:38:22.577794 RD_PRE = 0x0
4862 12:38:22.577873 WR_PRE = 0x1
4863 12:38:22.581207 WR_PST = 0x0
4864 12:38:22.581285 DBI_WR = 0x0
4865 12:38:22.584475 DBI_RD = 0x0
4866 12:38:22.584552 OTF = 0x1
4867 12:38:22.587800 ===================================
4868 12:38:22.591038 ===================================
4869 12:38:22.594513 ANA top config
4870 12:38:22.597800 ===================================
4871 12:38:22.601370 DLL_ASYNC_EN = 0
4872 12:38:22.601486 ALL_SLAVE_EN = 1
4873 12:38:22.604519 NEW_RANK_MODE = 1
4874 12:38:22.607759 DLL_IDLE_MODE = 1
4875 12:38:22.611472 LP45_APHY_COMB_EN = 1
4876 12:38:22.614420 TX_ODT_DIS = 1
4877 12:38:22.614493 NEW_8X_MODE = 1
4878 12:38:22.617721 ===================================
4879 12:38:22.621183 ===================================
4880 12:38:22.624509 data_rate = 1866
4881 12:38:22.627699 CKR = 1
4882 12:38:22.631603 DQ_P2S_RATIO = 8
4883 12:38:22.634446 ===================================
4884 12:38:22.637487 CA_P2S_RATIO = 8
4885 12:38:22.637571 DQ_CA_OPEN = 0
4886 12:38:22.640950 DQ_SEMI_OPEN = 0
4887 12:38:22.644309 CA_SEMI_OPEN = 0
4888 12:38:22.647393 CA_FULL_RATE = 0
4889 12:38:22.650838 DQ_CKDIV4_EN = 1
4890 12:38:22.654236 CA_CKDIV4_EN = 1
4891 12:38:22.654313 CA_PREDIV_EN = 0
4892 12:38:22.657436 PH8_DLY = 0
4893 12:38:22.660701 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4894 12:38:22.664401 DQ_AAMCK_DIV = 4
4895 12:38:22.667576 CA_AAMCK_DIV = 4
4896 12:38:22.671340 CA_ADMCK_DIV = 4
4897 12:38:22.671417 DQ_TRACK_CA_EN = 0
4898 12:38:22.674444 CA_PICK = 933
4899 12:38:22.677689 CA_MCKIO = 933
4900 12:38:22.680909 MCKIO_SEMI = 0
4901 12:38:22.684273 PLL_FREQ = 3732
4902 12:38:22.687584 DQ_UI_PI_RATIO = 32
4903 12:38:22.691129 CA_UI_PI_RATIO = 0
4904 12:38:22.694387 ===================================
4905 12:38:22.698145 ===================================
4906 12:38:22.698231 memory_type:LPDDR4
4907 12:38:22.701011 GP_NUM : 10
4908 12:38:22.704323 SRAM_EN : 1
4909 12:38:22.704401 MD32_EN : 0
4910 12:38:22.707701 ===================================
4911 12:38:22.710713 [ANA_INIT] >>>>>>>>>>>>>>
4912 12:38:22.714005 <<<<<< [CONFIGURE PHASE]: ANA_TX
4913 12:38:22.717737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4914 12:38:22.720993 ===================================
4915 12:38:22.723987 data_rate = 1866,PCW = 0X8f00
4916 12:38:22.727586 ===================================
4917 12:38:22.730796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4918 12:38:22.734077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4919 12:38:22.740747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4920 12:38:22.744003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4921 12:38:22.747634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4922 12:38:22.750627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4923 12:38:22.754053 [ANA_INIT] flow start
4924 12:38:22.757393 [ANA_INIT] PLL >>>>>>>>
4925 12:38:22.757466 [ANA_INIT] PLL <<<<<<<<
4926 12:38:22.760795 [ANA_INIT] MIDPI >>>>>>>>
4927 12:38:22.763804 [ANA_INIT] MIDPI <<<<<<<<
4928 12:38:22.763874 [ANA_INIT] DLL >>>>>>>>
4929 12:38:22.767183 [ANA_INIT] flow end
4930 12:38:22.770531 ============ LP4 DIFF to SE enter ============
4931 12:38:22.777240 ============ LP4 DIFF to SE exit ============
4932 12:38:22.777320 [ANA_INIT] <<<<<<<<<<<<<
4933 12:38:22.780424 [Flow] Enable top DCM control >>>>>
4934 12:38:22.783875 [Flow] Enable top DCM control <<<<<
4935 12:38:22.787189 Enable DLL master slave shuffle
4936 12:38:22.794204 ==============================================================
4937 12:38:22.794280 Gating Mode config
4938 12:38:22.800937 ==============================================================
4939 12:38:22.803944 Config description:
4940 12:38:22.810437 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4941 12:38:22.816945 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4942 12:38:22.824034 SELPH_MODE 0: By rank 1: By Phase
4943 12:38:22.830349 ==============================================================
4944 12:38:22.830506 GAT_TRACK_EN = 1
4945 12:38:22.833834 RX_GATING_MODE = 2
4946 12:38:22.837227 RX_GATING_TRACK_MODE = 2
4947 12:38:22.840593 SELPH_MODE = 1
4948 12:38:22.843571 PICG_EARLY_EN = 1
4949 12:38:22.846695 VALID_LAT_VALUE = 1
4950 12:38:22.853454 ==============================================================
4951 12:38:22.857010 Enter into Gating configuration >>>>
4952 12:38:22.860263 Exit from Gating configuration <<<<
4953 12:38:22.863509 Enter into DVFS_PRE_config >>>>>
4954 12:38:22.873679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4955 12:38:22.877281 Exit from DVFS_PRE_config <<<<<
4956 12:38:22.880153 Enter into PICG configuration >>>>
4957 12:38:22.883522 Exit from PICG configuration <<<<
4958 12:38:22.886908 [RX_INPUT] configuration >>>>>
4959 12:38:22.887000 [RX_INPUT] configuration <<<<<
4960 12:38:22.893686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4961 12:38:22.900606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4962 12:38:22.903498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4963 12:38:22.910280 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4964 12:38:22.916937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4965 12:38:22.923314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4966 12:38:22.926710 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4967 12:38:22.930383 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4968 12:38:22.936770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4969 12:38:22.940182 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4970 12:38:22.943530 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4971 12:38:22.947156 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4972 12:38:22.950376 ===================================
4973 12:38:22.953442 LPDDR4 DRAM CONFIGURATION
4974 12:38:22.957393 ===================================
4975 12:38:22.960360 EX_ROW_EN[0] = 0x0
4976 12:38:22.960443 EX_ROW_EN[1] = 0x0
4977 12:38:22.963486 LP4Y_EN = 0x0
4978 12:38:22.963569 WORK_FSP = 0x0
4979 12:38:22.966640 WL = 0x3
4980 12:38:22.966738 RL = 0x3
4981 12:38:22.970305 BL = 0x2
4982 12:38:22.970388 RPST = 0x0
4983 12:38:22.973506 RD_PRE = 0x0
4984 12:38:22.973589 WR_PRE = 0x1
4985 12:38:22.976655 WR_PST = 0x0
4986 12:38:22.980439 DBI_WR = 0x0
4987 12:38:22.980522 DBI_RD = 0x0
4988 12:38:22.983575 OTF = 0x1
4989 12:38:22.986555 ===================================
4990 12:38:22.990056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4991 12:38:22.993456 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4992 12:38:22.997044 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 12:38:23.000031 ===================================
4994 12:38:23.003392 LPDDR4 DRAM CONFIGURATION
4995 12:38:23.006555 ===================================
4996 12:38:23.009993 EX_ROW_EN[0] = 0x10
4997 12:38:23.010103 EX_ROW_EN[1] = 0x0
4998 12:38:23.013512 LP4Y_EN = 0x0
4999 12:38:23.013616 WORK_FSP = 0x0
5000 12:38:23.016544 WL = 0x3
5001 12:38:23.016622 RL = 0x3
5002 12:38:23.019838 BL = 0x2
5003 12:38:23.019917 RPST = 0x0
5004 12:38:23.023311 RD_PRE = 0x0
5005 12:38:23.023389 WR_PRE = 0x1
5006 12:38:23.026614 WR_PST = 0x0
5007 12:38:23.026688 DBI_WR = 0x0
5008 12:38:23.030053 DBI_RD = 0x0
5009 12:38:23.030134 OTF = 0x1
5010 12:38:23.033173 ===================================
5011 12:38:23.040378 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5012 12:38:23.044992 nWR fixed to 30
5013 12:38:23.048574 [ModeRegInit_LP4] CH0 RK0
5014 12:38:23.048652 [ModeRegInit_LP4] CH0 RK1
5015 12:38:23.051737 [ModeRegInit_LP4] CH1 RK0
5016 12:38:23.054879 [ModeRegInit_LP4] CH1 RK1
5017 12:38:23.054955 match AC timing 9
5018 12:38:23.061537 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5019 12:38:23.064985 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5020 12:38:23.068288 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5021 12:38:23.074744 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5022 12:38:23.078206 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5023 12:38:23.078287 ==
5024 12:38:23.081709 Dram Type= 6, Freq= 0, CH_0, rank 0
5025 12:38:23.085133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5026 12:38:23.085213 ==
5027 12:38:23.091537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5028 12:38:23.098475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5029 12:38:23.101492 [CA 0] Center 38 (7~69) winsize 63
5030 12:38:23.105158 [CA 1] Center 38 (8~69) winsize 62
5031 12:38:23.108320 [CA 2] Center 35 (5~66) winsize 62
5032 12:38:23.111779 [CA 3] Center 34 (4~65) winsize 62
5033 12:38:23.115189 [CA 4] Center 34 (4~65) winsize 62
5034 12:38:23.118012 [CA 5] Center 33 (3~64) winsize 62
5035 12:38:23.118092
5036 12:38:23.121151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5037 12:38:23.121225
5038 12:38:23.124600 [CATrainingPosCal] consider 1 rank data
5039 12:38:23.127902 u2DelayCellTimex100 = 270/100 ps
5040 12:38:23.131252 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5041 12:38:23.134691 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5042 12:38:23.137995 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5043 12:38:23.141544 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5044 12:38:23.144572 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5045 12:38:23.148089 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5046 12:38:23.148173
5047 12:38:23.154592 CA PerBit enable=1, Macro0, CA PI delay=33
5048 12:38:23.154706
5049 12:38:23.157955 [CBTSetCACLKResult] CA Dly = 33
5050 12:38:23.158081 CS Dly: 6 (0~37)
5051 12:38:23.158153 ==
5052 12:38:23.161194 Dram Type= 6, Freq= 0, CH_0, rank 1
5053 12:38:23.164512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 12:38:23.164592 ==
5055 12:38:23.171119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 12:38:23.177897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5057 12:38:23.181225 [CA 0] Center 38 (8~69) winsize 62
5058 12:38:23.184694 [CA 1] Center 38 (8~69) winsize 62
5059 12:38:23.187967 [CA 2] Center 36 (6~67) winsize 62
5060 12:38:23.191095 [CA 3] Center 35 (5~66) winsize 62
5061 12:38:23.194414 [CA 4] Center 34 (4~65) winsize 62
5062 12:38:23.197575 [CA 5] Center 34 (4~65) winsize 62
5063 12:38:23.197653
5064 12:38:23.201145 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5065 12:38:23.201219
5066 12:38:23.204435 [CATrainingPosCal] consider 2 rank data
5067 12:38:23.207747 u2DelayCellTimex100 = 270/100 ps
5068 12:38:23.211065 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5069 12:38:23.214360 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5070 12:38:23.217838 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5071 12:38:23.220917 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5072 12:38:23.224440 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5073 12:38:23.231085 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5074 12:38:23.231173
5075 12:38:23.234432 CA PerBit enable=1, Macro0, CA PI delay=34
5076 12:38:23.234516
5077 12:38:23.237821 [CBTSetCACLKResult] CA Dly = 34
5078 12:38:23.237905 CS Dly: 7 (0~39)
5079 12:38:23.238012
5080 12:38:23.240886 ----->DramcWriteLeveling(PI) begin...
5081 12:38:23.240971 ==
5082 12:38:23.244096 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 12:38:23.247639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 12:38:23.251010 ==
5085 12:38:23.251095 Write leveling (Byte 0): 31 => 31
5086 12:38:23.254051 Write leveling (Byte 1): 30 => 30
5087 12:38:23.257558 DramcWriteLeveling(PI) end<-----
5088 12:38:23.257641
5089 12:38:23.257707 ==
5090 12:38:23.260630 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 12:38:23.267417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 12:38:23.267501 ==
5093 12:38:23.270770 [Gating] SW mode calibration
5094 12:38:23.277386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5095 12:38:23.280773 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5096 12:38:23.287426 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5097 12:38:23.290911 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 12:38:23.294068 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 12:38:23.297684 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 12:38:23.304401 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 12:38:23.307771 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5102 12:38:23.310716 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5103 12:38:23.317834 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5104 12:38:23.321028 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5105 12:38:23.324467 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 12:38:23.331048 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 12:38:23.334354 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 12:38:23.337766 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 12:38:23.344143 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:38:23.347536 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5111 12:38:23.350882 0 15 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5112 12:38:23.357595 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 12:38:23.360754 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 12:38:23.364152 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 12:38:23.370615 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 12:38:23.373929 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 12:38:23.377501 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:38:23.383808 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:38:23.387178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5120 12:38:23.390925 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5121 12:38:23.394328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 12:38:23.400724 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 12:38:23.404648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:38:23.407244 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:38:23.414037 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:38:23.417480 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:38:23.420871 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:38:23.427400 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:38:23.430642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:38:23.434052 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:38:23.440794 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:38:23.443934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:38:23.447676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:38:23.454008 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5135 12:38:23.457298 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5136 12:38:23.460759 Total UI for P1: 0, mck2ui 16
5137 12:38:23.463840 best dqsien dly found for B0: ( 1, 2, 24)
5138 12:38:23.467083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:38:23.470346 Total UI for P1: 0, mck2ui 16
5140 12:38:23.473739 best dqsien dly found for B1: ( 1, 2, 28)
5141 12:38:23.476892 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5142 12:38:23.480147 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5143 12:38:23.480232
5144 12:38:23.486896 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5145 12:38:23.490289 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5146 12:38:23.493797 [Gating] SW calibration Done
5147 12:38:23.493881 ==
5148 12:38:23.496842 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 12:38:23.500184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 12:38:23.500269 ==
5151 12:38:23.500353 RX Vref Scan: 0
5152 12:38:23.500433
5153 12:38:23.503532 RX Vref 0 -> 0, step: 1
5154 12:38:23.503616
5155 12:38:23.506843 RX Delay -80 -> 252, step: 8
5156 12:38:23.510178 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5157 12:38:23.513498 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5158 12:38:23.519776 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5159 12:38:23.523273 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5160 12:38:23.526542 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5161 12:38:23.529995 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5162 12:38:23.533311 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5163 12:38:23.536604 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5164 12:38:23.543052 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5165 12:38:23.546516 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5166 12:38:23.549999 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5167 12:38:23.552955 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5168 12:38:23.556353 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5169 12:38:23.562831 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5170 12:38:23.566193 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5171 12:38:23.569799 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5172 12:38:23.569883 ==
5173 12:38:23.572876 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:38:23.576447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:38:23.576532 ==
5176 12:38:23.579507 DQS Delay:
5177 12:38:23.579591 DQS0 = 0, DQS1 = 0
5178 12:38:23.579677 DQM Delay:
5179 12:38:23.582940 DQM0 = 107, DQM1 = 90
5180 12:38:23.583025 DQ Delay:
5181 12:38:23.586325 DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =107
5182 12:38:23.589481 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5183 12:38:23.592893 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5184 12:38:23.595849 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5185 12:38:23.595933
5186 12:38:23.599526
5187 12:38:23.599610 ==
5188 12:38:23.602857 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 12:38:23.606257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 12:38:23.606352 ==
5191 12:38:23.606438
5192 12:38:23.606518
5193 12:38:23.609411 TX Vref Scan disable
5194 12:38:23.609498 == TX Byte 0 ==
5195 12:38:23.615942 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5196 12:38:23.619215 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5197 12:38:23.619300 == TX Byte 1 ==
5198 12:38:23.625862 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5199 12:38:23.629212 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5200 12:38:23.629296 ==
5201 12:38:23.632536 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 12:38:23.635847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 12:38:23.635933 ==
5204 12:38:23.636017
5205 12:38:23.636096
5206 12:38:23.639170 TX Vref Scan disable
5207 12:38:23.642558 == TX Byte 0 ==
5208 12:38:23.645733 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5209 12:38:23.649015 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5210 12:38:23.652384 == TX Byte 1 ==
5211 12:38:23.655816 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5212 12:38:23.659375 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5213 12:38:23.659457
5214 12:38:23.662317 [DATLAT]
5215 12:38:23.662399 Freq=933, CH0 RK0
5216 12:38:23.662464
5217 12:38:23.665845 DATLAT Default: 0xd
5218 12:38:23.665958 0, 0xFFFF, sum = 0
5219 12:38:23.669210 1, 0xFFFF, sum = 0
5220 12:38:23.669294 2, 0xFFFF, sum = 0
5221 12:38:23.672675 3, 0xFFFF, sum = 0
5222 12:38:23.672783 4, 0xFFFF, sum = 0
5223 12:38:23.675492 5, 0xFFFF, sum = 0
5224 12:38:23.675575 6, 0xFFFF, sum = 0
5225 12:38:23.678903 7, 0xFFFF, sum = 0
5226 12:38:23.678986 8, 0xFFFF, sum = 0
5227 12:38:23.682348 9, 0xFFFF, sum = 0
5228 12:38:23.682432 10, 0x0, sum = 1
5229 12:38:23.685538 11, 0x0, sum = 2
5230 12:38:23.685621 12, 0x0, sum = 3
5231 12:38:23.689003 13, 0x0, sum = 4
5232 12:38:23.689086 best_step = 11
5233 12:38:23.689151
5234 12:38:23.689211 ==
5235 12:38:23.692173 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 12:38:23.695446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 12:38:23.698761 ==
5238 12:38:23.698843 RX Vref Scan: 1
5239 12:38:23.698908
5240 12:38:23.702432 RX Vref 0 -> 0, step: 1
5241 12:38:23.702514
5242 12:38:23.705419 RX Delay -53 -> 252, step: 4
5243 12:38:23.705501
5244 12:38:23.708794 Set Vref, RX VrefLevel [Byte0]: 57
5245 12:38:23.712200 [Byte1]: 48
5246 12:38:23.712283
5247 12:38:23.715653 Final RX Vref Byte 0 = 57 to rank0
5248 12:38:23.718613 Final RX Vref Byte 1 = 48 to rank0
5249 12:38:23.722059 Final RX Vref Byte 0 = 57 to rank1
5250 12:38:23.725418 Final RX Vref Byte 1 = 48 to rank1==
5251 12:38:23.728709 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 12:38:23.732049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 12:38:23.732133 ==
5254 12:38:23.735481 DQS Delay:
5255 12:38:23.735563 DQS0 = 0, DQS1 = 0
5256 12:38:23.735628 DQM Delay:
5257 12:38:23.738725 DQM0 = 107, DQM1 = 91
5258 12:38:23.738807 DQ Delay:
5259 12:38:23.742078 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5260 12:38:23.745433 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5261 12:38:23.748816 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5262 12:38:23.752031 DQ12 =94, DQ13 =94, DQ14 =104, DQ15 =98
5263 12:38:23.752113
5264 12:38:23.755353
5265 12:38:23.761552 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5266 12:38:23.764838 CH0 RK0: MR19=505, MR18=2622
5267 12:38:23.771680 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5268 12:38:23.771763
5269 12:38:23.775007 ----->DramcWriteLeveling(PI) begin...
5270 12:38:23.775090 ==
5271 12:38:23.778075 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 12:38:23.781579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 12:38:23.781662 ==
5274 12:38:23.785106 Write leveling (Byte 0): 33 => 33
5275 12:38:23.788143 Write leveling (Byte 1): 31 => 31
5276 12:38:23.791754 DramcWriteLeveling(PI) end<-----
5277 12:38:23.791836
5278 12:38:23.791900 ==
5279 12:38:23.794927 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 12:38:23.798355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 12:38:23.798438 ==
5282 12:38:23.801329 [Gating] SW mode calibration
5283 12:38:23.807951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5284 12:38:23.814658 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5285 12:38:23.817875 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 12:38:23.821400 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 12:38:23.828156 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 12:38:23.831539 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 12:38:23.835012 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 12:38:23.841462 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 12:38:23.844895 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
5292 12:38:23.848439 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 1)
5293 12:38:23.854912 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 12:38:23.857843 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 12:38:23.861657 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 12:38:23.867832 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 12:38:23.871167 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 12:38:23.874747 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 12:38:23.881333 0 15 24 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 1)
5300 12:38:23.884688 0 15 28 | B1->B0 | 3c3c 4545 | 1 0 | (0 0) (0 0)
5301 12:38:23.888007 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 12:38:23.894608 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 12:38:23.897796 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 12:38:23.901145 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 12:38:23.904721 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 12:38:23.911632 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 12:38:23.914992 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5308 12:38:23.917878 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5309 12:38:23.924674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5310 12:38:23.927963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 12:38:23.931462 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 12:38:23.937857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 12:38:23.941158 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 12:38:23.944438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:38:23.951170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:38:23.954497 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:38:23.957522 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:38:23.964742 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:38:23.967647 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:38:23.970956 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:38:23.977698 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:38:23.981089 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:38:23.984366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:38:23.991077 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5325 12:38:23.991158 Total UI for P1: 0, mck2ui 16
5326 12:38:23.994611 best dqsien dly found for B0: ( 1, 2, 26)
5327 12:38:24.001403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:38:24.004592 Total UI for P1: 0, mck2ui 16
5329 12:38:24.007750 best dqsien dly found for B1: ( 1, 2, 28)
5330 12:38:24.011229 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5331 12:38:24.014404 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5332 12:38:24.014486
5333 12:38:24.017879 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5334 12:38:24.021255 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5335 12:38:24.024296 [Gating] SW calibration Done
5336 12:38:24.024378 ==
5337 12:38:24.027634 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 12:38:24.030939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 12:38:24.031023 ==
5340 12:38:24.034284 RX Vref Scan: 0
5341 12:38:24.034365
5342 12:38:24.037693 RX Vref 0 -> 0, step: 1
5343 12:38:24.037775
5344 12:38:24.037841 RX Delay -80 -> 252, step: 8
5345 12:38:24.044978 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5346 12:38:24.047815 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5347 12:38:24.051237 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5348 12:38:24.054616 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5349 12:38:24.057988 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5350 12:38:24.061129 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5351 12:38:24.067918 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5352 12:38:24.070794 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5353 12:38:24.074174 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5354 12:38:24.077503 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5355 12:38:24.081091 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5356 12:38:24.084569 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5357 12:38:24.091213 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5358 12:38:24.094290 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5359 12:38:24.097615 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5360 12:38:24.100888 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5361 12:38:24.100971 ==
5362 12:38:24.104338 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 12:38:24.107429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 12:38:24.110826 ==
5365 12:38:24.110908 DQS Delay:
5366 12:38:24.110973 DQS0 = 0, DQS1 = 0
5367 12:38:24.114234 DQM Delay:
5368 12:38:24.114316 DQM0 = 104, DQM1 = 92
5369 12:38:24.117453 DQ Delay:
5370 12:38:24.120846 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5371 12:38:24.123905 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5372 12:38:24.127367 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =95
5373 12:38:24.130722 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5374 12:38:24.130805
5375 12:38:24.130869
5376 12:38:24.130928 ==
5377 12:38:24.134163 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 12:38:24.137438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 12:38:24.137523 ==
5380 12:38:24.137588
5381 12:38:24.137647
5382 12:38:24.140746 TX Vref Scan disable
5383 12:38:24.140828 == TX Byte 0 ==
5384 12:38:24.147675 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5385 12:38:24.150522 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5386 12:38:24.150605 == TX Byte 1 ==
5387 12:38:24.157365 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5388 12:38:24.161056 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5389 12:38:24.161138 ==
5390 12:38:24.164283 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 12:38:24.167573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 12:38:24.167655 ==
5393 12:38:24.167720
5394 12:38:24.167779
5395 12:38:24.170881 TX Vref Scan disable
5396 12:38:24.174208 == TX Byte 0 ==
5397 12:38:24.177487 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5398 12:38:24.180893 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5399 12:38:24.184002 == TX Byte 1 ==
5400 12:38:24.187298 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5401 12:38:24.190709 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5402 12:38:24.190791
5403 12:38:24.194371 [DATLAT]
5404 12:38:24.194453 Freq=933, CH0 RK1
5405 12:38:24.194518
5406 12:38:24.197165 DATLAT Default: 0xb
5407 12:38:24.197246 0, 0xFFFF, sum = 0
5408 12:38:24.200801 1, 0xFFFF, sum = 0
5409 12:38:24.200885 2, 0xFFFF, sum = 0
5410 12:38:24.203851 3, 0xFFFF, sum = 0
5411 12:38:24.203934 4, 0xFFFF, sum = 0
5412 12:38:24.207446 5, 0xFFFF, sum = 0
5413 12:38:24.207536 6, 0xFFFF, sum = 0
5414 12:38:24.210452 7, 0xFFFF, sum = 0
5415 12:38:24.210536 8, 0xFFFF, sum = 0
5416 12:38:24.213907 9, 0xFFFF, sum = 0
5417 12:38:24.214038 10, 0x0, sum = 1
5418 12:38:24.217389 11, 0x0, sum = 2
5419 12:38:24.217476 12, 0x0, sum = 3
5420 12:38:24.220870 13, 0x0, sum = 4
5421 12:38:24.220953 best_step = 11
5422 12:38:24.221017
5423 12:38:24.221076 ==
5424 12:38:24.223805 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 12:38:24.230628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 12:38:24.230711 ==
5427 12:38:24.230778 RX Vref Scan: 0
5428 12:38:24.230854
5429 12:38:24.234018 RX Vref 0 -> 0, step: 1
5430 12:38:24.234100
5431 12:38:24.237425 RX Delay -53 -> 252, step: 4
5432 12:38:24.240730 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5433 12:38:24.243897 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5434 12:38:24.250496 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5435 12:38:24.253903 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5436 12:38:24.257260 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5437 12:38:24.260635 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5438 12:38:24.263959 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5439 12:38:24.270532 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5440 12:38:24.273856 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5441 12:38:24.277209 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5442 12:38:24.280691 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5443 12:38:24.283869 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5444 12:38:24.287319 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5445 12:38:24.294074 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5446 12:38:24.297296 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5447 12:38:24.300563 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5448 12:38:24.300646 ==
5449 12:38:24.303929 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 12:38:24.307074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 12:38:24.310718 ==
5452 12:38:24.310800 DQS Delay:
5453 12:38:24.310864 DQS0 = 0, DQS1 = 0
5454 12:38:24.313890 DQM Delay:
5455 12:38:24.314009 DQM0 = 104, DQM1 = 93
5456 12:38:24.316883 DQ Delay:
5457 12:38:24.320566 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5458 12:38:24.323545 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5459 12:38:24.327052 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5460 12:38:24.330126 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =100
5461 12:38:24.330208
5462 12:38:24.330272
5463 12:38:24.336958 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5464 12:38:24.340345 CH0 RK1: MR19=505, MR18=2E0E
5465 12:38:24.346886 CH0_RK1: MR19=0x505, MR18=0x2E0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5466 12:38:24.350112 [RxdqsGatingPostProcess] freq 933
5467 12:38:24.353357 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5468 12:38:24.357117 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 12:38:24.360111 best DQS1 dly(2T, 0.5T) = (0, 10)
5470 12:38:24.363413 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 12:38:24.366819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5472 12:38:24.370320 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 12:38:24.373451 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 12:38:24.376879 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 12:38:24.380137 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 12:38:24.383574 Pre-setting of DQS Precalculation
5477 12:38:24.387020 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5478 12:38:24.387103 ==
5479 12:38:24.390293 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 12:38:24.396834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 12:38:24.396917 ==
5482 12:38:24.400193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5483 12:38:24.406838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5484 12:38:24.410292 [CA 0] Center 38 (8~68) winsize 61
5485 12:38:24.413308 [CA 1] Center 38 (8~68) winsize 61
5486 12:38:24.416798 [CA 2] Center 35 (5~66) winsize 62
5487 12:38:24.420385 [CA 3] Center 34 (4~65) winsize 62
5488 12:38:24.423381 [CA 4] Center 35 (5~66) winsize 62
5489 12:38:24.427099 [CA 5] Center 34 (4~65) winsize 62
5490 12:38:24.427189
5491 12:38:24.430057 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5492 12:38:24.430139
5493 12:38:24.433440 [CATrainingPosCal] consider 1 rank data
5494 12:38:24.436911 u2DelayCellTimex100 = 270/100 ps
5495 12:38:24.440146 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5496 12:38:24.443294 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5497 12:38:24.446725 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5498 12:38:24.453503 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5499 12:38:24.456895 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5500 12:38:24.460244 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5501 12:38:24.460326
5502 12:38:24.463766 CA PerBit enable=1, Macro0, CA PI delay=34
5503 12:38:24.463849
5504 12:38:24.466653 [CBTSetCACLKResult] CA Dly = 34
5505 12:38:24.466735 CS Dly: 6 (0~37)
5506 12:38:24.466800 ==
5507 12:38:24.469973 Dram Type= 6, Freq= 0, CH_1, rank 1
5508 12:38:24.476616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:38:24.476700 ==
5510 12:38:24.479838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 12:38:24.486437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5512 12:38:24.490058 [CA 0] Center 38 (8~68) winsize 61
5513 12:38:24.493232 [CA 1] Center 38 (8~69) winsize 62
5514 12:38:24.496860 [CA 2] Center 36 (6~66) winsize 61
5515 12:38:24.499820 [CA 3] Center 35 (6~65) winsize 60
5516 12:38:24.503417 [CA 4] Center 35 (5~65) winsize 61
5517 12:38:24.506791 [CA 5] Center 35 (5~65) winsize 61
5518 12:38:24.506873
5519 12:38:24.509768 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5520 12:38:24.509850
5521 12:38:24.513069 [CATrainingPosCal] consider 2 rank data
5522 12:38:24.516447 u2DelayCellTimex100 = 270/100 ps
5523 12:38:24.519738 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5524 12:38:24.523028 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5525 12:38:24.530127 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5526 12:38:24.533150 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5527 12:38:24.536654 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5528 12:38:24.539679 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5529 12:38:24.539761
5530 12:38:24.543232 CA PerBit enable=1, Macro0, CA PI delay=35
5531 12:38:24.543314
5532 12:38:24.546715 [CBTSetCACLKResult] CA Dly = 35
5533 12:38:24.546797 CS Dly: 7 (0~40)
5534 12:38:24.546862
5535 12:38:24.549859 ----->DramcWriteLeveling(PI) begin...
5536 12:38:24.553209 ==
5537 12:38:24.553291 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 12:38:24.560066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 12:38:24.560148 ==
5540 12:38:24.563110 Write leveling (Byte 0): 26 => 26
5541 12:38:24.566476 Write leveling (Byte 1): 27 => 27
5542 12:38:24.570182 DramcWriteLeveling(PI) end<-----
5543 12:38:24.570265
5544 12:38:24.570329 ==
5545 12:38:24.573359 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 12:38:24.576247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 12:38:24.576329 ==
5548 12:38:24.579876 [Gating] SW mode calibration
5549 12:38:24.586217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 12:38:24.589588 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5551 12:38:24.596610 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 12:38:24.599453 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 12:38:24.602792 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 12:38:24.609681 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 12:38:24.612982 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 12:38:24.616360 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 12:38:24.622947 0 14 24 | B1->B0 | 3333 3030 | 1 1 | (0 1) (1 1)
5558 12:38:24.626325 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5559 12:38:24.629341 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 12:38:24.636089 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 12:38:24.639414 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 12:38:24.642664 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 12:38:24.649198 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 12:38:24.652740 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 12:38:24.655909 0 15 24 | B1->B0 | 2525 2525 | 0 1 | (0 0) (0 0)
5566 12:38:24.662651 0 15 28 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
5567 12:38:24.665915 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 12:38:24.669332 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 12:38:24.675970 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 12:38:24.679336 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 12:38:24.682592 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 12:38:24.689466 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 12:38:24.693014 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5574 12:38:24.696094 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5575 12:38:24.702842 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:38:24.705800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:38:24.709659 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:38:24.715935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:38:24.719395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:38:24.722893 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:38:24.726169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:38:24.732635 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:38:24.736048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:38:24.739374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:38:24.745728 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:38:24.749376 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:38:24.752402 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:38:24.759315 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5589 12:38:24.762290 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5590 12:38:24.765928 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5591 12:38:24.772536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:38:24.775935 Total UI for P1: 0, mck2ui 16
5593 12:38:24.779211 best dqsien dly found for B0: ( 1, 2, 24)
5594 12:38:24.779287 Total UI for P1: 0, mck2ui 16
5595 12:38:24.785393 best dqsien dly found for B1: ( 1, 2, 28)
5596 12:38:24.788684 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5597 12:38:24.792382 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5598 12:38:24.792486
5599 12:38:24.795911 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5600 12:38:24.798525 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5601 12:38:24.802367 [Gating] SW calibration Done
5602 12:38:24.802444 ==
5603 12:38:24.805257 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 12:38:24.808490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 12:38:24.808590 ==
5606 12:38:24.811981 RX Vref Scan: 0
5607 12:38:24.812054
5608 12:38:24.812121 RX Vref 0 -> 0, step: 1
5609 12:38:24.815348
5610 12:38:24.815419 RX Delay -80 -> 252, step: 8
5611 12:38:24.822010 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5612 12:38:24.825327 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5613 12:38:24.828845 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5614 12:38:24.832205 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5615 12:38:24.835488 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5616 12:38:24.838754 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5617 12:38:24.842000 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5618 12:38:24.848893 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5619 12:38:24.852082 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5620 12:38:24.855203 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5621 12:38:24.858881 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5622 12:38:24.862214 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5623 12:38:24.868645 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5624 12:38:24.871781 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5625 12:38:24.875657 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5626 12:38:24.879000 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5627 12:38:24.879110 ==
5628 12:38:24.881849 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 12:38:24.885301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:38:24.885383 ==
5631 12:38:24.888672 DQS Delay:
5632 12:38:24.888773 DQS0 = 0, DQS1 = 0
5633 12:38:24.891997 DQM Delay:
5634 12:38:24.892071 DQM0 = 101, DQM1 = 95
5635 12:38:24.892133 DQ Delay:
5636 12:38:24.895331 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5637 12:38:24.898807 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5638 12:38:24.902140 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5639 12:38:24.908823 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5640 12:38:24.908896
5641 12:38:24.908958
5642 12:38:24.909016 ==
5643 12:38:24.912174 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 12:38:24.915119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 12:38:24.915189 ==
5646 12:38:24.915250
5647 12:38:24.915316
5648 12:38:24.918473 TX Vref Scan disable
5649 12:38:24.918571 == TX Byte 0 ==
5650 12:38:24.925238 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5651 12:38:24.928594 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5652 12:38:24.928696 == TX Byte 1 ==
5653 12:38:24.935325 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5654 12:38:24.938255 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5655 12:38:24.938328 ==
5656 12:38:24.941664 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 12:38:24.945300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 12:38:24.945402 ==
5659 12:38:24.945497
5660 12:38:24.945586
5661 12:38:24.948209 TX Vref Scan disable
5662 12:38:24.951851 == TX Byte 0 ==
5663 12:38:24.954894 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 12:38:24.958262 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 12:38:24.961751 == TX Byte 1 ==
5666 12:38:24.965121 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5667 12:38:24.968213 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5668 12:38:24.968315
5669 12:38:24.971543 [DATLAT]
5670 12:38:24.971616 Freq=933, CH1 RK0
5671 12:38:24.971682
5672 12:38:24.975368 DATLAT Default: 0xd
5673 12:38:24.975443 0, 0xFFFF, sum = 0
5674 12:38:24.978179 1, 0xFFFF, sum = 0
5675 12:38:24.978255 2, 0xFFFF, sum = 0
5676 12:38:24.981697 3, 0xFFFF, sum = 0
5677 12:38:24.981802 4, 0xFFFF, sum = 0
5678 12:38:24.985123 5, 0xFFFF, sum = 0
5679 12:38:24.985208 6, 0xFFFF, sum = 0
5680 12:38:24.988488 7, 0xFFFF, sum = 0
5681 12:38:24.988592 8, 0xFFFF, sum = 0
5682 12:38:24.991651 9, 0xFFFF, sum = 0
5683 12:38:24.991726 10, 0x0, sum = 1
5684 12:38:24.994905 11, 0x0, sum = 2
5685 12:38:24.995010 12, 0x0, sum = 3
5686 12:38:24.998183 13, 0x0, sum = 4
5687 12:38:24.998265 best_step = 11
5688 12:38:24.998330
5689 12:38:24.998389 ==
5690 12:38:25.001824 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:38:25.008147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:38:25.008230 ==
5693 12:38:25.008296 RX Vref Scan: 1
5694 12:38:25.008357
5695 12:38:25.011465 RX Vref 0 -> 0, step: 1
5696 12:38:25.011548
5697 12:38:25.014856 RX Delay -53 -> 252, step: 4
5698 12:38:25.014939
5699 12:38:25.018386 Set Vref, RX VrefLevel [Byte0]: 51
5700 12:38:25.021271 [Byte1]: 53
5701 12:38:25.021353
5702 12:38:25.024614 Final RX Vref Byte 0 = 51 to rank0
5703 12:38:25.027999 Final RX Vref Byte 1 = 53 to rank0
5704 12:38:25.031324 Final RX Vref Byte 0 = 51 to rank1
5705 12:38:25.034913 Final RX Vref Byte 1 = 53 to rank1==
5706 12:38:25.037815 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 12:38:25.041161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 12:38:25.041245 ==
5709 12:38:25.044613 DQS Delay:
5710 12:38:25.044695 DQS0 = 0, DQS1 = 0
5711 12:38:25.044760 DQM Delay:
5712 12:38:25.047904 DQM0 = 104, DQM1 = 97
5713 12:38:25.047986 DQ Delay:
5714 12:38:25.051271 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5715 12:38:25.054563 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5716 12:38:25.057909 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5717 12:38:25.064285 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =104
5718 12:38:25.064371
5719 12:38:25.064455
5720 12:38:25.071209 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f37, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5721 12:38:25.074359 CH1 RK0: MR19=505, MR18=1F37
5722 12:38:25.081121 CH1_RK0: MR19=0x505, MR18=0x1F37, DQSOSC=404, MR23=63, INC=66, DEC=44
5723 12:38:25.081207
5724 12:38:25.084351 ----->DramcWriteLeveling(PI) begin...
5725 12:38:25.084438 ==
5726 12:38:25.087891 Dram Type= 6, Freq= 0, CH_1, rank 1
5727 12:38:25.091217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 12:38:25.091303 ==
5729 12:38:25.094203 Write leveling (Byte 0): 28 => 28
5730 12:38:25.098042 Write leveling (Byte 1): 29 => 29
5731 12:38:25.100831 DramcWriteLeveling(PI) end<-----
5732 12:38:25.100916
5733 12:38:25.101001 ==
5734 12:38:25.104274 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:38:25.108008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:38:25.108092 ==
5737 12:38:25.110969 [Gating] SW mode calibration
5738 12:38:25.117602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5739 12:38:25.124592 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5740 12:38:25.127806 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 12:38:25.134104 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 12:38:25.137307 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 12:38:25.140753 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 12:38:25.144050 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 12:38:25.150874 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 12:38:25.154330 0 14 24 | B1->B0 | 3030 3333 | 1 1 | (1 1) (1 0)
5747 12:38:25.157394 0 14 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 0)
5748 12:38:25.164110 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5749 12:38:25.167945 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 12:38:25.170863 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 12:38:25.177303 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 12:38:25.181527 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 12:38:25.184428 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 12:38:25.190933 0 15 24 | B1->B0 | 2c2c 2626 | 0 0 | (0 0) (0 0)
5755 12:38:25.194083 0 15 28 | B1->B0 | 3e3e 3636 | 0 1 | (0 0) (0 0)
5756 12:38:25.197663 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 12:38:25.204331 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 12:38:25.207801 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 12:38:25.210823 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 12:38:25.217371 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 12:38:25.220741 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 12:38:25.224089 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5763 12:38:25.230625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5764 12:38:25.234006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 12:38:25.237292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 12:38:25.243857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 12:38:25.247285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:38:25.250636 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:38:25.257513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:38:25.260807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:38:25.264181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:38:25.270819 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:38:25.274016 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:38:25.277148 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:38:25.280737 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:38:25.287205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:38:25.290423 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:38:25.294136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5779 12:38:25.300716 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5780 12:38:25.303986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:38:25.307420 Total UI for P1: 0, mck2ui 16
5782 12:38:25.310780 best dqsien dly found for B0: ( 1, 2, 26)
5783 12:38:25.314013 Total UI for P1: 0, mck2ui 16
5784 12:38:25.317360 best dqsien dly found for B1: ( 1, 2, 26)
5785 12:38:25.320596 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5786 12:38:25.323953 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5787 12:38:25.324346
5788 12:38:25.327323 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5789 12:38:25.330751 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5790 12:38:25.334272 [Gating] SW calibration Done
5791 12:38:25.334712 ==
5792 12:38:25.337442 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 12:38:25.343679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 12:38:25.344131 ==
5795 12:38:25.344493 RX Vref Scan: 0
5796 12:38:25.344840
5797 12:38:25.346937 RX Vref 0 -> 0, step: 1
5798 12:38:25.347387
5799 12:38:25.350176 RX Delay -80 -> 252, step: 8
5800 12:38:25.353560 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5801 12:38:25.356962 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5802 12:38:25.360197 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5803 12:38:25.363583 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5804 12:38:25.370311 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5805 12:38:25.373790 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5806 12:38:25.376817 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5807 12:38:25.380494 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5808 12:38:25.383839 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5809 12:38:25.386855 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5810 12:38:25.393552 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5811 12:38:25.396724 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5812 12:38:25.400181 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5813 12:38:25.403928 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5814 12:38:25.406832 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5815 12:38:25.413529 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5816 12:38:25.414086 ==
5817 12:38:25.417098 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 12:38:25.420262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 12:38:25.420660 ==
5820 12:38:25.421090 DQS Delay:
5821 12:38:25.423364 DQS0 = 0, DQS1 = 0
5822 12:38:25.423843 DQM Delay:
5823 12:38:25.426877 DQM0 = 103, DQM1 = 95
5824 12:38:25.427340 DQ Delay:
5825 12:38:25.430264 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5826 12:38:25.433514 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5827 12:38:25.436916 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5828 12:38:25.440264 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5829 12:38:25.440708
5830 12:38:25.441068
5831 12:38:25.441407 ==
5832 12:38:25.443229 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 12:38:25.450032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 12:38:25.450543 ==
5835 12:38:25.450986
5836 12:38:25.451419
5837 12:38:25.451829 TX Vref Scan disable
5838 12:38:25.453933 == TX Byte 0 ==
5839 12:38:25.456941 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5840 12:38:25.463526 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5841 12:38:25.464155 == TX Byte 1 ==
5842 12:38:25.466857 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5843 12:38:25.470226 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5844 12:38:25.473628 ==
5845 12:38:25.477090 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 12:38:25.480419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 12:38:25.480854 ==
5848 12:38:25.481286
5849 12:38:25.481693
5850 12:38:25.483724 TX Vref Scan disable
5851 12:38:25.484204 == TX Byte 0 ==
5852 12:38:25.490080 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5853 12:38:25.493514 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5854 12:38:25.493977 == TX Byte 1 ==
5855 12:38:25.499949 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5856 12:38:25.503429 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5857 12:38:25.503914
5858 12:38:25.504343 [DATLAT]
5859 12:38:25.506606 Freq=933, CH1 RK1
5860 12:38:25.507078
5861 12:38:25.507531 DATLAT Default: 0xb
5862 12:38:25.510244 0, 0xFFFF, sum = 0
5863 12:38:25.510688 1, 0xFFFF, sum = 0
5864 12:38:25.513260 2, 0xFFFF, sum = 0
5865 12:38:25.513747 3, 0xFFFF, sum = 0
5866 12:38:25.516533 4, 0xFFFF, sum = 0
5867 12:38:25.516969 5, 0xFFFF, sum = 0
5868 12:38:25.520023 6, 0xFFFF, sum = 0
5869 12:38:25.523323 7, 0xFFFF, sum = 0
5870 12:38:25.523823 8, 0xFFFF, sum = 0
5871 12:38:25.526795 9, 0xFFFF, sum = 0
5872 12:38:25.527236 10, 0x0, sum = 1
5873 12:38:25.527717 11, 0x0, sum = 2
5874 12:38:25.530013 12, 0x0, sum = 3
5875 12:38:25.530453 13, 0x0, sum = 4
5876 12:38:25.533638 best_step = 11
5877 12:38:25.534101
5878 12:38:25.534440 ==
5879 12:38:25.536853 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 12:38:25.540085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 12:38:25.540510 ==
5882 12:38:25.543281 RX Vref Scan: 0
5883 12:38:25.543701
5884 12:38:25.544036 RX Vref 0 -> 0, step: 1
5885 12:38:25.544352
5886 12:38:25.546577 RX Delay -53 -> 252, step: 4
5887 12:38:25.553675 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5888 12:38:25.557237 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5889 12:38:25.560725 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5890 12:38:25.564389 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5891 12:38:25.567453 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5892 12:38:25.573659 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5893 12:38:25.576986 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5894 12:38:25.580307 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5895 12:38:25.583995 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5896 12:38:25.586936 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5897 12:38:25.593617 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5898 12:38:25.596997 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5899 12:38:25.600684 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5900 12:38:25.603868 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5901 12:38:25.606966 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5902 12:38:25.613566 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5903 12:38:25.614037 ==
5904 12:38:25.616906 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 12:38:25.620395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 12:38:25.620822 ==
5907 12:38:25.621156 DQS Delay:
5908 12:38:25.623742 DQS0 = 0, DQS1 = 0
5909 12:38:25.624181 DQM Delay:
5910 12:38:25.627053 DQM0 = 105, DQM1 = 97
5911 12:38:25.627604 DQ Delay:
5912 12:38:25.630509 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5913 12:38:25.633631 DQ4 =108, DQ5 =114, DQ6 =112, DQ7 =102
5914 12:38:25.637285 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5915 12:38:25.640482 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5916 12:38:25.640907
5917 12:38:25.641238
5918 12:38:25.650410 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5919 12:38:25.651032 CH1 RK1: MR19=504, MR18=20FD
5920 12:38:25.657137 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5921 12:38:25.660592 [RxdqsGatingPostProcess] freq 933
5922 12:38:25.666792 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5923 12:38:25.669794 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 12:38:25.673107 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 12:38:25.676312 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 12:38:25.679819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 12:38:25.683232 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 12:38:25.683316 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 12:38:25.686775 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 12:38:25.689864 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 12:38:25.693260 Pre-setting of DQS Precalculation
5932 12:38:25.699748 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5933 12:38:25.706462 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5934 12:38:25.713376 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5935 12:38:25.713460
5936 12:38:25.713526
5937 12:38:25.716773 [Calibration Summary] 1866 Mbps
5938 12:38:25.719860 CH 0, Rank 0
5939 12:38:25.719943 SW Impedance : PASS
5940 12:38:25.723104 DUTY Scan : NO K
5941 12:38:25.723187 ZQ Calibration : PASS
5942 12:38:25.726333 Jitter Meter : NO K
5943 12:38:25.729573 CBT Training : PASS
5944 12:38:25.729656 Write leveling : PASS
5945 12:38:25.732923 RX DQS gating : PASS
5946 12:38:25.736439 RX DQ/DQS(RDDQC) : PASS
5947 12:38:25.736593 TX DQ/DQS : PASS
5948 12:38:25.739818 RX DATLAT : PASS
5949 12:38:25.743197 RX DQ/DQS(Engine): PASS
5950 12:38:25.743280 TX OE : NO K
5951 12:38:25.746488 All Pass.
5952 12:38:25.746594
5953 12:38:25.746661 CH 0, Rank 1
5954 12:38:25.749510 SW Impedance : PASS
5955 12:38:25.749593 DUTY Scan : NO K
5956 12:38:25.752903 ZQ Calibration : PASS
5957 12:38:25.756424 Jitter Meter : NO K
5958 12:38:25.756508 CBT Training : PASS
5959 12:38:25.759708 Write leveling : PASS
5960 12:38:25.763125 RX DQS gating : PASS
5961 12:38:25.763208 RX DQ/DQS(RDDQC) : PASS
5962 12:38:25.766503 TX DQ/DQS : PASS
5963 12:38:25.769452 RX DATLAT : PASS
5964 12:38:25.769535 RX DQ/DQS(Engine): PASS
5965 12:38:25.772656 TX OE : NO K
5966 12:38:25.772740 All Pass.
5967 12:38:25.772805
5968 12:38:25.776044 CH 1, Rank 0
5969 12:38:25.776128 SW Impedance : PASS
5970 12:38:25.779515 DUTY Scan : NO K
5971 12:38:25.779598 ZQ Calibration : PASS
5972 12:38:25.782849 Jitter Meter : NO K
5973 12:38:25.786265 CBT Training : PASS
5974 12:38:25.786348 Write leveling : PASS
5975 12:38:25.789581 RX DQS gating : PASS
5976 12:38:25.792964 RX DQ/DQS(RDDQC) : PASS
5977 12:38:25.793047 TX DQ/DQS : PASS
5978 12:38:25.796144 RX DATLAT : PASS
5979 12:38:25.799425 RX DQ/DQS(Engine): PASS
5980 12:38:25.799508 TX OE : NO K
5981 12:38:25.803111 All Pass.
5982 12:38:25.803194
5983 12:38:25.803260 CH 1, Rank 1
5984 12:38:25.805945 SW Impedance : PASS
5985 12:38:25.806030 DUTY Scan : NO K
5986 12:38:25.809379 ZQ Calibration : PASS
5987 12:38:25.812665 Jitter Meter : NO K
5988 12:38:25.812749 CBT Training : PASS
5989 12:38:25.816326 Write leveling : PASS
5990 12:38:25.819261 RX DQS gating : PASS
5991 12:38:25.819344 RX DQ/DQS(RDDQC) : PASS
5992 12:38:25.822698 TX DQ/DQS : PASS
5993 12:38:25.822781 RX DATLAT : PASS
5994 12:38:25.826247 RX DQ/DQS(Engine): PASS
5995 12:38:25.829340 TX OE : NO K
5996 12:38:25.829423 All Pass.
5997 12:38:25.829488
5998 12:38:25.832716 DramC Write-DBI off
5999 12:38:25.832799 PER_BANK_REFRESH: Hybrid Mode
6000 12:38:25.836289 TX_TRACKING: ON
6001 12:38:25.845875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6002 12:38:25.849424 [FAST_K] Save calibration result to emmc
6003 12:38:25.852376 dramc_set_vcore_voltage set vcore to 650000
6004 12:38:25.855907 Read voltage for 400, 6
6005 12:38:25.855990 Vio18 = 0
6006 12:38:25.856056 Vcore = 650000
6007 12:38:25.856117 Vdram = 0
6008 12:38:25.858921 Vddq = 0
6009 12:38:25.859004 Vmddr = 0
6010 12:38:25.865942 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6011 12:38:25.869421 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6012 12:38:25.872750 MEM_TYPE=3, freq_sel=20
6013 12:38:25.875895 sv_algorithm_assistance_LP4_800
6014 12:38:25.879312 ============ PULL DRAM RESETB DOWN ============
6015 12:38:25.882648 ========== PULL DRAM RESETB DOWN end =========
6016 12:38:25.889026 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6017 12:38:25.892369 ===================================
6018 12:38:25.892453 LPDDR4 DRAM CONFIGURATION
6019 12:38:25.895689 ===================================
6020 12:38:25.899243 EX_ROW_EN[0] = 0x0
6021 12:38:25.899326 EX_ROW_EN[1] = 0x0
6022 12:38:25.902570 LP4Y_EN = 0x0
6023 12:38:25.905842 WORK_FSP = 0x0
6024 12:38:25.905973 WL = 0x2
6025 12:38:25.909357 RL = 0x2
6026 12:38:25.909440 BL = 0x2
6027 12:38:25.912422 RPST = 0x0
6028 12:38:25.912506 RD_PRE = 0x0
6029 12:38:25.915777 WR_PRE = 0x1
6030 12:38:25.915860 WR_PST = 0x0
6031 12:38:25.919099 DBI_WR = 0x0
6032 12:38:25.919182 DBI_RD = 0x0
6033 12:38:25.922520 OTF = 0x1
6034 12:38:25.925664 ===================================
6035 12:38:25.928921 ===================================
6036 12:38:25.929005 ANA top config
6037 12:38:25.932571 ===================================
6038 12:38:25.935487 DLL_ASYNC_EN = 0
6039 12:38:25.939077 ALL_SLAVE_EN = 1
6040 12:38:25.939160 NEW_RANK_MODE = 1
6041 12:38:25.942256 DLL_IDLE_MODE = 1
6042 12:38:25.945617 LP45_APHY_COMB_EN = 1
6043 12:38:25.948886 TX_ODT_DIS = 1
6044 12:38:25.948971 NEW_8X_MODE = 1
6045 12:38:25.952366 ===================================
6046 12:38:25.955811 ===================================
6047 12:38:25.958944 data_rate = 800
6048 12:38:25.962497 CKR = 1
6049 12:38:25.965764 DQ_P2S_RATIO = 4
6050 12:38:25.968990 ===================================
6051 12:38:25.972276 CA_P2S_RATIO = 4
6052 12:38:25.975586 DQ_CA_OPEN = 0
6053 12:38:25.975670 DQ_SEMI_OPEN = 1
6054 12:38:25.978841 CA_SEMI_OPEN = 1
6055 12:38:25.982219 CA_FULL_RATE = 0
6056 12:38:25.985570 DQ_CKDIV4_EN = 0
6057 12:38:25.989076 CA_CKDIV4_EN = 1
6058 12:38:25.992011 CA_PREDIV_EN = 0
6059 12:38:25.992095 PH8_DLY = 0
6060 12:38:25.995487 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6061 12:38:25.998856 DQ_AAMCK_DIV = 0
6062 12:38:26.002121 CA_AAMCK_DIV = 0
6063 12:38:26.005344 CA_ADMCK_DIV = 4
6064 12:38:26.009120 DQ_TRACK_CA_EN = 0
6065 12:38:26.009203 CA_PICK = 800
6066 12:38:26.012087 CA_MCKIO = 400
6067 12:38:26.015235 MCKIO_SEMI = 400
6068 12:38:26.018769 PLL_FREQ = 3016
6069 12:38:26.022117 DQ_UI_PI_RATIO = 32
6070 12:38:26.025466 CA_UI_PI_RATIO = 32
6071 12:38:26.028652 ===================================
6072 12:38:26.032071 ===================================
6073 12:38:26.035244 memory_type:LPDDR4
6074 12:38:26.035328 GP_NUM : 10
6075 12:38:26.038593 SRAM_EN : 1
6076 12:38:26.038676 MD32_EN : 0
6077 12:38:26.042022 ===================================
6078 12:38:26.045439 [ANA_INIT] >>>>>>>>>>>>>>
6079 12:38:26.048578 <<<<<< [CONFIGURE PHASE]: ANA_TX
6080 12:38:26.052042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6081 12:38:26.055181 ===================================
6082 12:38:26.058874 data_rate = 800,PCW = 0X7400
6083 12:38:26.061869 ===================================
6084 12:38:26.065402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6085 12:38:26.068460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 12:38:26.081863 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 12:38:26.085465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6088 12:38:26.088863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6089 12:38:26.092310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6090 12:38:26.095662 [ANA_INIT] flow start
6091 12:38:26.098884 [ANA_INIT] PLL >>>>>>>>
6092 12:38:26.098967 [ANA_INIT] PLL <<<<<<<<
6093 12:38:26.102284 [ANA_INIT] MIDPI >>>>>>>>
6094 12:38:26.105489 [ANA_INIT] MIDPI <<<<<<<<
6095 12:38:26.105573 [ANA_INIT] DLL >>>>>>>>
6096 12:38:26.108973 [ANA_INIT] flow end
6097 12:38:26.111986 ============ LP4 DIFF to SE enter ============
6098 12:38:26.115352 ============ LP4 DIFF to SE exit ============
6099 12:38:26.119004 [ANA_INIT] <<<<<<<<<<<<<
6100 12:38:26.122277 [Flow] Enable top DCM control >>>>>
6101 12:38:26.125273 [Flow] Enable top DCM control <<<<<
6102 12:38:26.128966 Enable DLL master slave shuffle
6103 12:38:26.135301 ==============================================================
6104 12:38:26.135384 Gating Mode config
6105 12:38:26.142404 ==============================================================
6106 12:38:26.142488 Config description:
6107 12:38:26.151997 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6108 12:38:26.158464 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6109 12:38:26.165432 SELPH_MODE 0: By rank 1: By Phase
6110 12:38:26.168630 ==============================================================
6111 12:38:26.172184 GAT_TRACK_EN = 0
6112 12:38:26.175409 RX_GATING_MODE = 2
6113 12:38:26.178765 RX_GATING_TRACK_MODE = 2
6114 12:38:26.181810 SELPH_MODE = 1
6115 12:38:26.185613 PICG_EARLY_EN = 1
6116 12:38:26.188475 VALID_LAT_VALUE = 1
6117 12:38:26.195355 ==============================================================
6118 12:38:26.198832 Enter into Gating configuration >>>>
6119 12:38:26.201937 Exit from Gating configuration <<<<
6120 12:38:26.202041 Enter into DVFS_PRE_config >>>>>
6121 12:38:26.215373 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6122 12:38:26.218847 Exit from DVFS_PRE_config <<<<<
6123 12:38:26.221925 Enter into PICG configuration >>>>
6124 12:38:26.225244 Exit from PICG configuration <<<<
6125 12:38:26.225327 [RX_INPUT] configuration >>>>>
6126 12:38:26.228640 [RX_INPUT] configuration <<<<<
6127 12:38:26.235181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6128 12:38:26.238351 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6129 12:38:26.245405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 12:38:26.251958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 12:38:26.258679 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 12:38:26.264952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 12:38:26.268648 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6134 12:38:26.271678 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6135 12:38:26.278590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6136 12:38:26.281610 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6137 12:38:26.285048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6138 12:38:26.288341 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6139 12:38:26.291664 ===================================
6140 12:38:26.294799 LPDDR4 DRAM CONFIGURATION
6141 12:38:26.298141 ===================================
6142 12:38:26.301527 EX_ROW_EN[0] = 0x0
6143 12:38:26.301612 EX_ROW_EN[1] = 0x0
6144 12:38:26.305129 LP4Y_EN = 0x0
6145 12:38:26.305213 WORK_FSP = 0x0
6146 12:38:26.308385 WL = 0x2
6147 12:38:26.308469 RL = 0x2
6148 12:38:26.311800 BL = 0x2
6149 12:38:26.311884 RPST = 0x0
6150 12:38:26.314979 RD_PRE = 0x0
6151 12:38:26.315062 WR_PRE = 0x1
6152 12:38:26.317957 WR_PST = 0x0
6153 12:38:26.321791 DBI_WR = 0x0
6154 12:38:26.321875 DBI_RD = 0x0
6155 12:38:26.324934 OTF = 0x1
6156 12:38:26.328317 ===================================
6157 12:38:26.331586 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6158 12:38:26.334895 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6159 12:38:26.337790 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 12:38:26.341437 ===================================
6161 12:38:26.344825 LPDDR4 DRAM CONFIGURATION
6162 12:38:26.348044 ===================================
6163 12:38:26.351322 EX_ROW_EN[0] = 0x10
6164 12:38:26.351407 EX_ROW_EN[1] = 0x0
6165 12:38:26.354629 LP4Y_EN = 0x0
6166 12:38:26.354713 WORK_FSP = 0x0
6167 12:38:26.357994 WL = 0x2
6168 12:38:26.358077 RL = 0x2
6169 12:38:26.361294 BL = 0x2
6170 12:38:26.361377 RPST = 0x0
6171 12:38:26.364702 RD_PRE = 0x0
6172 12:38:26.364786 WR_PRE = 0x1
6173 12:38:26.368079 WR_PST = 0x0
6174 12:38:26.368163 DBI_WR = 0x0
6175 12:38:26.371211 DBI_RD = 0x0
6176 12:38:26.371298 OTF = 0x1
6177 12:38:26.374446 ===================================
6178 12:38:26.381043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6179 12:38:26.386182 nWR fixed to 30
6180 12:38:26.389553 [ModeRegInit_LP4] CH0 RK0
6181 12:38:26.389637 [ModeRegInit_LP4] CH0 RK1
6182 12:38:26.392548 [ModeRegInit_LP4] CH1 RK0
6183 12:38:26.396179 [ModeRegInit_LP4] CH1 RK1
6184 12:38:26.396264 match AC timing 19
6185 12:38:26.402893 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6186 12:38:26.406310 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6187 12:38:26.409310 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6188 12:38:26.416063 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6189 12:38:26.419426 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6190 12:38:26.419510 ==
6191 12:38:26.422887 Dram Type= 6, Freq= 0, CH_0, rank 0
6192 12:38:26.425927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6193 12:38:26.426053 ==
6194 12:38:26.432655 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6195 12:38:26.439260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6196 12:38:26.442647 [CA 0] Center 36 (8~64) winsize 57
6197 12:38:26.445994 [CA 1] Center 36 (8~64) winsize 57
6198 12:38:26.449306 [CA 2] Center 36 (8~64) winsize 57
6199 12:38:26.449390 [CA 3] Center 36 (8~64) winsize 57
6200 12:38:26.452543 [CA 4] Center 36 (8~64) winsize 57
6201 12:38:26.455675 [CA 5] Center 36 (8~64) winsize 57
6202 12:38:26.455759
6203 12:38:26.462282 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6204 12:38:26.462367
6205 12:38:26.466009 [CATrainingPosCal] consider 1 rank data
6206 12:38:26.466094 u2DelayCellTimex100 = 270/100 ps
6207 12:38:26.472895 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 12:38:26.476086 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 12:38:26.479507 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 12:38:26.482479 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 12:38:26.485834 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 12:38:26.489293 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 12:38:26.489377
6214 12:38:26.492472 CA PerBit enable=1, Macro0, CA PI delay=36
6215 12:38:26.492556
6216 12:38:26.495883 [CBTSetCACLKResult] CA Dly = 36
6217 12:38:26.499036 CS Dly: 1 (0~32)
6218 12:38:26.499144 ==
6219 12:38:26.502454 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 12:38:26.505874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 12:38:26.505985 ==
6222 12:38:26.512652 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 12:38:26.516175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6224 12:38:26.519450 [CA 0] Center 36 (8~64) winsize 57
6225 12:38:26.522714 [CA 1] Center 36 (8~64) winsize 57
6226 12:38:26.525875 [CA 2] Center 36 (8~64) winsize 57
6227 12:38:26.529428 [CA 3] Center 36 (8~64) winsize 57
6228 12:38:26.532230 [CA 4] Center 36 (8~64) winsize 57
6229 12:38:26.535691 [CA 5] Center 36 (8~64) winsize 57
6230 12:38:26.535776
6231 12:38:26.539244 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6232 12:38:26.539331
6233 12:38:26.542118 [CATrainingPosCal] consider 2 rank data
6234 12:38:26.545811 u2DelayCellTimex100 = 270/100 ps
6235 12:38:26.548726 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:38:26.552089 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 12:38:26.555594 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 12:38:26.562166 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 12:38:26.565589 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:38:26.568847 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:38:26.568932
6242 12:38:26.572285 CA PerBit enable=1, Macro0, CA PI delay=36
6243 12:38:26.572370
6244 12:38:26.575357 [CBTSetCACLKResult] CA Dly = 36
6245 12:38:26.575469 CS Dly: 1 (0~32)
6246 12:38:26.575566
6247 12:38:26.579059 ----->DramcWriteLeveling(PI) begin...
6248 12:38:26.579167 ==
6249 12:38:26.582524 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 12:38:26.588819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 12:38:26.588925 ==
6252 12:38:26.592019 Write leveling (Byte 0): 40 => 8
6253 12:38:26.595376 Write leveling (Byte 1): 32 => 0
6254 12:38:26.595456 DramcWriteLeveling(PI) end<-----
6255 12:38:26.595533
6256 12:38:26.598820 ==
6257 12:38:26.602290 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 12:38:26.605488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 12:38:26.605593 ==
6260 12:38:26.608964 [Gating] SW mode calibration
6261 12:38:26.615212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6262 12:38:26.618712 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6263 12:38:26.625240 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 12:38:26.629033 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 12:38:26.632273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 12:38:26.638784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 12:38:26.642145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 12:38:26.645467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 12:38:26.651830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 12:38:26.655296 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 12:38:26.658577 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 12:38:26.661869 Total UI for P1: 0, mck2ui 16
6273 12:38:26.665466 best dqsien dly found for B0: ( 0, 14, 24)
6274 12:38:26.668814 Total UI for P1: 0, mck2ui 16
6275 12:38:26.672127 best dqsien dly found for B1: ( 0, 14, 24)
6276 12:38:26.675441 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6277 12:38:26.678958 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6278 12:38:26.679044
6279 12:38:26.685178 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 12:38:26.688598 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 12:38:26.688708 [Gating] SW calibration Done
6282 12:38:26.691888 ==
6283 12:38:26.695102 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 12:38:26.698193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 12:38:26.698276 ==
6286 12:38:26.698341 RX Vref Scan: 0
6287 12:38:26.698402
6288 12:38:26.701548 RX Vref 0 -> 0, step: 1
6289 12:38:26.701660
6290 12:38:26.704751 RX Delay -410 -> 252, step: 16
6291 12:38:26.708315 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6292 12:38:26.714768 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6293 12:38:26.718112 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6294 12:38:26.721796 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6295 12:38:26.725076 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6296 12:38:26.728495 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6297 12:38:26.734842 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6298 12:38:26.737960 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6299 12:38:26.741803 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6300 12:38:26.744659 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6301 12:38:26.751495 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6302 12:38:26.754990 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6303 12:38:26.757826 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6304 12:38:26.764426 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6305 12:38:26.768207 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6306 12:38:26.771404 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6307 12:38:26.771475 ==
6308 12:38:26.774310 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 12:38:26.778211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 12:38:26.781536 ==
6311 12:38:26.781630 DQS Delay:
6312 12:38:26.781721 DQS0 = 27, DQS1 = 43
6313 12:38:26.784786 DQM Delay:
6314 12:38:26.784884 DQM0 = 12, DQM1 = 13
6315 12:38:26.787820 DQ Delay:
6316 12:38:26.787889 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6317 12:38:26.791715 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6318 12:38:26.794364 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6319 12:38:26.797991 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6320 12:38:26.798075
6321 12:38:26.798140
6322 12:38:26.798200 ==
6323 12:38:26.801179 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 12:38:26.808200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 12:38:26.808283 ==
6326 12:38:26.808347
6327 12:38:26.808406
6328 12:38:26.808463 TX Vref Scan disable
6329 12:38:26.811191 == TX Byte 0 ==
6330 12:38:26.814745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 12:38:26.817908 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 12:38:26.821427 == TX Byte 1 ==
6333 12:38:26.824490 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6334 12:38:26.827981 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6335 12:38:26.831186 ==
6336 12:38:26.834394 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 12:38:26.837793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 12:38:26.837889 ==
6339 12:38:26.837985
6340 12:38:26.838074
6341 12:38:26.841016 TX Vref Scan disable
6342 12:38:26.841108 == TX Byte 0 ==
6343 12:38:26.844667 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 12:38:26.851363 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 12:38:26.851433 == TX Byte 1 ==
6346 12:38:26.854271 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6347 12:38:26.860842 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6348 12:38:26.860937
6349 12:38:26.861030 [DATLAT]
6350 12:38:26.861117 Freq=400, CH0 RK0
6351 12:38:26.861204
6352 12:38:26.864354 DATLAT Default: 0xf
6353 12:38:26.864448 0, 0xFFFF, sum = 0
6354 12:38:26.867756 1, 0xFFFF, sum = 0
6355 12:38:26.870877 2, 0xFFFF, sum = 0
6356 12:38:26.870944 3, 0xFFFF, sum = 0
6357 12:38:26.874503 4, 0xFFFF, sum = 0
6358 12:38:26.874573 5, 0xFFFF, sum = 0
6359 12:38:26.877774 6, 0xFFFF, sum = 0
6360 12:38:26.877877 7, 0xFFFF, sum = 0
6361 12:38:26.880842 8, 0xFFFF, sum = 0
6362 12:38:26.880912 9, 0xFFFF, sum = 0
6363 12:38:26.884202 10, 0xFFFF, sum = 0
6364 12:38:26.884301 11, 0xFFFF, sum = 0
6365 12:38:26.887572 12, 0xFFFF, sum = 0
6366 12:38:26.887646 13, 0x0, sum = 1
6367 12:38:26.890762 14, 0x0, sum = 2
6368 12:38:26.890837 15, 0x0, sum = 3
6369 12:38:26.894172 16, 0x0, sum = 4
6370 12:38:26.894245 best_step = 14
6371 12:38:26.894306
6372 12:38:26.894364 ==
6373 12:38:26.897364 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 12:38:26.900872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 12:38:26.904094 ==
6376 12:38:26.904178 RX Vref Scan: 1
6377 12:38:26.904243
6378 12:38:26.907479 RX Vref 0 -> 0, step: 1
6379 12:38:26.907562
6380 12:38:26.910807 RX Delay -327 -> 252, step: 8
6381 12:38:26.910890
6382 12:38:26.914365 Set Vref, RX VrefLevel [Byte0]: 57
6383 12:38:26.917420 [Byte1]: 48
6384 12:38:26.917551
6385 12:38:26.920552 Final RX Vref Byte 0 = 57 to rank0
6386 12:38:26.924044 Final RX Vref Byte 1 = 48 to rank0
6387 12:38:26.927642 Final RX Vref Byte 0 = 57 to rank1
6388 12:38:26.930683 Final RX Vref Byte 1 = 48 to rank1==
6389 12:38:26.933878 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 12:38:26.937373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 12:38:26.937456 ==
6392 12:38:26.940832 DQS Delay:
6393 12:38:26.940915 DQS0 = 24, DQS1 = 48
6394 12:38:26.944156 DQM Delay:
6395 12:38:26.944242 DQM0 = 9, DQM1 = 16
6396 12:38:26.944328 DQ Delay:
6397 12:38:26.947320 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6398 12:38:26.950640 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6399 12:38:26.953888 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6400 12:38:26.957159 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6401 12:38:26.957245
6402 12:38:26.957331
6403 12:38:26.967029 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6404 12:38:26.967119 CH0 RK0: MR19=C0C, MR18=AAA2
6405 12:38:26.973967 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6406 12:38:26.974059 ==
6407 12:38:26.977121 Dram Type= 6, Freq= 0, CH_0, rank 1
6408 12:38:26.983863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 12:38:26.983944 ==
6410 12:38:26.987142 [Gating] SW mode calibration
6411 12:38:26.993689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6412 12:38:26.996954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6413 12:38:27.003855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 12:38:27.007207 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 12:38:27.010641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 12:38:27.017227 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 12:38:27.020277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 12:38:27.023709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 12:38:27.030194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 12:38:27.033626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 12:38:27.037127 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 12:38:27.040259 Total UI for P1: 0, mck2ui 16
6423 12:38:27.043900 best dqsien dly found for B0: ( 0, 14, 24)
6424 12:38:27.046989 Total UI for P1: 0, mck2ui 16
6425 12:38:27.050112 best dqsien dly found for B1: ( 0, 14, 24)
6426 12:38:27.053580 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6427 12:38:27.056860 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6428 12:38:27.056943
6429 12:38:27.060262 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 12:38:27.066981 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 12:38:27.067063 [Gating] SW calibration Done
6432 12:38:27.067129 ==
6433 12:38:27.070586 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 12:38:27.077197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 12:38:27.077280 ==
6436 12:38:27.077346 RX Vref Scan: 0
6437 12:38:27.077407
6438 12:38:27.080338 RX Vref 0 -> 0, step: 1
6439 12:38:27.080421
6440 12:38:27.083730 RX Delay -410 -> 252, step: 16
6441 12:38:27.086879 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6442 12:38:27.090211 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6443 12:38:27.096899 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6444 12:38:27.100153 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6445 12:38:27.103469 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6446 12:38:27.106686 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6447 12:38:27.113701 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6448 12:38:27.116627 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6449 12:38:27.120030 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6450 12:38:27.123510 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6451 12:38:27.129926 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6452 12:38:27.133411 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6453 12:38:27.136369 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6454 12:38:27.139930 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6455 12:38:27.146699 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6456 12:38:27.150077 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6457 12:38:27.150160 ==
6458 12:38:27.153393 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 12:38:27.156526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 12:38:27.156614 ==
6461 12:38:27.159487 DQS Delay:
6462 12:38:27.159569 DQS0 = 27, DQS1 = 43
6463 12:38:27.163140 DQM Delay:
6464 12:38:27.163222 DQM0 = 9, DQM1 = 16
6465 12:38:27.163288 DQ Delay:
6466 12:38:27.166330 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6467 12:38:27.169707 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6468 12:38:27.172984 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6469 12:38:27.176482 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6470 12:38:27.176565
6471 12:38:27.176630
6472 12:38:27.176688 ==
6473 12:38:27.179650 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 12:38:27.186188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 12:38:27.186275 ==
6476 12:38:27.186341
6477 12:38:27.186403
6478 12:38:27.186460 TX Vref Scan disable
6479 12:38:27.189526 == TX Byte 0 ==
6480 12:38:27.192989 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6481 12:38:27.196104 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6482 12:38:27.199678 == TX Byte 1 ==
6483 12:38:27.202919 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6484 12:38:27.206006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6485 12:38:27.206090 ==
6486 12:38:27.209332 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 12:38:27.216033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 12:38:27.216117 ==
6489 12:38:27.216182
6490 12:38:27.216243
6491 12:38:27.216300 TX Vref Scan disable
6492 12:38:27.219262 == TX Byte 0 ==
6493 12:38:27.222527 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6494 12:38:27.225881 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6495 12:38:27.229057 == TX Byte 1 ==
6496 12:38:27.232890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6497 12:38:27.235602 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6498 12:38:27.235686
6499 12:38:27.238978 [DATLAT]
6500 12:38:27.239067 Freq=400, CH0 RK1
6501 12:38:27.239134
6502 12:38:27.242324 DATLAT Default: 0xe
6503 12:38:27.242406 0, 0xFFFF, sum = 0
6504 12:38:27.245874 1, 0xFFFF, sum = 0
6505 12:38:27.246000 2, 0xFFFF, sum = 0
6506 12:38:27.248815 3, 0xFFFF, sum = 0
6507 12:38:27.248898 4, 0xFFFF, sum = 0
6508 12:38:27.252198 5, 0xFFFF, sum = 0
6509 12:38:27.252282 6, 0xFFFF, sum = 0
6510 12:38:27.255645 7, 0xFFFF, sum = 0
6511 12:38:27.255729 8, 0xFFFF, sum = 0
6512 12:38:27.259134 9, 0xFFFF, sum = 0
6513 12:38:27.262321 10, 0xFFFF, sum = 0
6514 12:38:27.262405 11, 0xFFFF, sum = 0
6515 12:38:27.265607 12, 0xFFFF, sum = 0
6516 12:38:27.265691 13, 0x0, sum = 1
6517 12:38:27.268852 14, 0x0, sum = 2
6518 12:38:27.268936 15, 0x0, sum = 3
6519 12:38:27.269002 16, 0x0, sum = 4
6520 12:38:27.272164 best_step = 14
6521 12:38:27.272281
6522 12:38:27.272376 ==
6523 12:38:27.275620 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 12:38:27.278956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 12:38:27.279039 ==
6526 12:38:27.282251 RX Vref Scan: 0
6527 12:38:27.282333
6528 12:38:27.285297 RX Vref 0 -> 0, step: 1
6529 12:38:27.285380
6530 12:38:27.285445 RX Delay -327 -> 252, step: 8
6531 12:38:27.293808 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6532 12:38:27.297205 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6533 12:38:27.300578 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6534 12:38:27.303860 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6535 12:38:27.310407 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6536 12:38:27.313880 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6537 12:38:27.317119 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6538 12:38:27.320559 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6539 12:38:27.327146 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6540 12:38:27.330537 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6541 12:38:27.333957 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6542 12:38:27.337639 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6543 12:38:27.343699 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6544 12:38:27.346961 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6545 12:38:27.350396 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6546 12:38:27.357181 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6547 12:38:27.357264 ==
6548 12:38:27.360454 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 12:38:27.363608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 12:38:27.363693 ==
6551 12:38:27.363758 DQS Delay:
6552 12:38:27.367321 DQS0 = 28, DQS1 = 40
6553 12:38:27.367404 DQM Delay:
6554 12:38:27.370374 DQM0 = 11, DQM1 = 13
6555 12:38:27.370457 DQ Delay:
6556 12:38:27.373552 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6557 12:38:27.377301 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6558 12:38:27.380160 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6559 12:38:27.383676 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6560 12:38:27.383760
6561 12:38:27.383825
6562 12:38:27.390470 [DQSOSCAuto] RK1, (LSB)MR18= 0xc072, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6563 12:38:27.393604 CH0 RK1: MR19=C0C, MR18=C072
6564 12:38:27.400181 CH0_RK1: MR19=0xC0C, MR18=0xC072, DQSOSC=386, MR23=63, INC=396, DEC=264
6565 12:38:27.403574 [RxdqsGatingPostProcess] freq 400
6566 12:38:27.410187 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6567 12:38:27.410271 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 12:38:27.413225 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 12:38:27.417171 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 12:38:27.420367 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 12:38:27.423709 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 12:38:27.427090 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 12:38:27.430406 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 12:38:27.433886 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 12:38:27.436771 Pre-setting of DQS Precalculation
6576 12:38:27.440153 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6577 12:38:27.444017 ==
6578 12:38:27.446820 Dram Type= 6, Freq= 0, CH_1, rank 0
6579 12:38:27.450111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 12:38:27.450201 ==
6581 12:38:27.453427 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6582 12:38:27.460241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6583 12:38:27.463212 [CA 0] Center 36 (8~64) winsize 57
6584 12:38:27.466701 [CA 1] Center 36 (8~64) winsize 57
6585 12:38:27.469923 [CA 2] Center 36 (8~64) winsize 57
6586 12:38:27.473189 [CA 3] Center 36 (8~64) winsize 57
6587 12:38:27.476908 [CA 4] Center 36 (8~64) winsize 57
6588 12:38:27.480186 [CA 5] Center 36 (8~64) winsize 57
6589 12:38:27.480281
6590 12:38:27.483500 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6591 12:38:27.483592
6592 12:38:27.486793 [CATrainingPosCal] consider 1 rank data
6593 12:38:27.489667 u2DelayCellTimex100 = 270/100 ps
6594 12:38:27.493129 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 12:38:27.496305 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 12:38:27.500114 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 12:38:27.503396 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 12:38:27.509685 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 12:38:27.513019 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 12:38:27.513116
6601 12:38:27.516646 CA PerBit enable=1, Macro0, CA PI delay=36
6602 12:38:27.516746
6603 12:38:27.519836 [CBTSetCACLKResult] CA Dly = 36
6604 12:38:27.519929 CS Dly: 1 (0~32)
6605 12:38:27.519997 ==
6606 12:38:27.523226 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 12:38:27.529735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 12:38:27.529833 ==
6609 12:38:27.532995 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 12:38:27.539910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6611 12:38:27.543148 [CA 0] Center 36 (8~64) winsize 57
6612 12:38:27.546140 [CA 1] Center 36 (8~64) winsize 57
6613 12:38:27.549530 [CA 2] Center 36 (8~64) winsize 57
6614 12:38:27.552987 [CA 3] Center 36 (8~64) winsize 57
6615 12:38:27.556489 [CA 4] Center 36 (8~64) winsize 57
6616 12:38:27.559482 [CA 5] Center 36 (8~64) winsize 57
6617 12:38:27.559568
6618 12:38:27.562993 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6619 12:38:27.563076
6620 12:38:27.565948 [CATrainingPosCal] consider 2 rank data
6621 12:38:27.569823 u2DelayCellTimex100 = 270/100 ps
6622 12:38:27.572687 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:38:27.576018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 12:38:27.579310 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 12:38:27.582862 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 12:38:27.586084 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:38:27.589273 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:38:27.589405
6629 12:38:27.596057 CA PerBit enable=1, Macro0, CA PI delay=36
6630 12:38:27.596143
6631 12:38:27.596208 [CBTSetCACLKResult] CA Dly = 36
6632 12:38:27.599411 CS Dly: 1 (0~32)
6633 12:38:27.599520
6634 12:38:27.602580 ----->DramcWriteLeveling(PI) begin...
6635 12:38:27.602700 ==
6636 12:38:27.605892 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 12:38:27.609355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 12:38:27.609461 ==
6639 12:38:27.612728 Write leveling (Byte 0): 40 => 8
6640 12:38:27.616246 Write leveling (Byte 1): 32 => 0
6641 12:38:27.619394 DramcWriteLeveling(PI) end<-----
6642 12:38:27.619505
6643 12:38:27.619606 ==
6644 12:38:27.622510 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 12:38:27.625833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 12:38:27.629169 ==
6647 12:38:27.629314 [Gating] SW mode calibration
6648 12:38:27.636101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6649 12:38:27.642542 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6650 12:38:27.645850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 12:38:27.652503 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 12:38:27.655814 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 12:38:27.658909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 12:38:27.665616 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 12:38:27.669514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 12:38:27.672217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 12:38:27.679141 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 12:38:27.682498 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 12:38:27.685874 Total UI for P1: 0, mck2ui 16
6660 12:38:27.689171 best dqsien dly found for B0: ( 0, 14, 24)
6661 12:38:27.692474 Total UI for P1: 0, mck2ui 16
6662 12:38:27.695811 best dqsien dly found for B1: ( 0, 14, 24)
6663 12:38:27.699074 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6664 12:38:27.702513 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6665 12:38:27.702597
6666 12:38:27.705751 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 12:38:27.709049 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 12:38:27.712572 [Gating] SW calibration Done
6669 12:38:27.712656 ==
6670 12:38:27.715892 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 12:38:27.719253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 12:38:27.722423 ==
6673 12:38:27.722507 RX Vref Scan: 0
6674 12:38:27.722574
6675 12:38:27.725556 RX Vref 0 -> 0, step: 1
6676 12:38:27.725640
6677 12:38:27.728882 RX Delay -410 -> 252, step: 16
6678 12:38:27.732376 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6679 12:38:27.735789 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6680 12:38:27.738810 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6681 12:38:27.745430 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6682 12:38:27.748975 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6683 12:38:27.752298 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6684 12:38:27.755604 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6685 12:38:27.762380 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6686 12:38:27.765662 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6687 12:38:27.768851 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6688 12:38:27.771908 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6689 12:38:27.778657 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6690 12:38:27.782196 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6691 12:38:27.785604 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6692 12:38:27.789000 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6693 12:38:27.795532 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6694 12:38:27.795643 ==
6695 12:38:27.798620 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 12:38:27.802124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 12:38:27.802209 ==
6698 12:38:27.802277 DQS Delay:
6699 12:38:27.805365 DQS0 = 19, DQS1 = 43
6700 12:38:27.805436 DQM Delay:
6701 12:38:27.808779 DQM0 = 2, DQM1 = 20
6702 12:38:27.808882 DQ Delay:
6703 12:38:27.811864 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6704 12:38:27.815232 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6705 12:38:27.818798 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6706 12:38:27.821751 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6707 12:38:27.821827
6708 12:38:27.821892
6709 12:38:27.821968 ==
6710 12:38:27.825380 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 12:38:27.828680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 12:38:27.828759 ==
6713 12:38:27.828827
6714 12:38:27.828888
6715 12:38:27.831910 TX Vref Scan disable
6716 12:38:27.831992 == TX Byte 0 ==
6717 12:38:27.838747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 12:38:27.842170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 12:38:27.842250 == TX Byte 1 ==
6720 12:38:27.848405 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6721 12:38:27.851807 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6722 12:38:27.851884 ==
6723 12:38:27.855086 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 12:38:27.858526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 12:38:27.858600 ==
6726 12:38:27.858662
6727 12:38:27.858725
6728 12:38:27.861811 TX Vref Scan disable
6729 12:38:27.865248 == TX Byte 0 ==
6730 12:38:27.868595 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 12:38:27.872074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 12:38:27.872148 == TX Byte 1 ==
6733 12:38:27.878560 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6734 12:38:27.881922 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6735 12:38:27.882027
6736 12:38:27.882092 [DATLAT]
6737 12:38:27.885006 Freq=400, CH1 RK0
6738 12:38:27.885086
6739 12:38:27.885149 DATLAT Default: 0xf
6740 12:38:27.888467 0, 0xFFFF, sum = 0
6741 12:38:27.888553 1, 0xFFFF, sum = 0
6742 12:38:27.892061 2, 0xFFFF, sum = 0
6743 12:38:27.892150 3, 0xFFFF, sum = 0
6744 12:38:27.895260 4, 0xFFFF, sum = 0
6745 12:38:27.898700 5, 0xFFFF, sum = 0
6746 12:38:27.898781 6, 0xFFFF, sum = 0
6747 12:38:27.901871 7, 0xFFFF, sum = 0
6748 12:38:27.902009 8, 0xFFFF, sum = 0
6749 12:38:27.905024 9, 0xFFFF, sum = 0
6750 12:38:27.905097 10, 0xFFFF, sum = 0
6751 12:38:27.908333 11, 0xFFFF, sum = 0
6752 12:38:27.908425 12, 0xFFFF, sum = 0
6753 12:38:27.911899 13, 0x0, sum = 1
6754 12:38:27.911985 14, 0x0, sum = 2
6755 12:38:27.915041 15, 0x0, sum = 3
6756 12:38:27.915124 16, 0x0, sum = 4
6757 12:38:27.918517 best_step = 14
6758 12:38:27.918591
6759 12:38:27.918671 ==
6760 12:38:27.921875 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 12:38:27.925199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 12:38:27.925281 ==
6763 12:38:27.925362 RX Vref Scan: 1
6764 12:38:27.925438
6765 12:38:27.928480 RX Vref 0 -> 0, step: 1
6766 12:38:27.928554
6767 12:38:27.931925 RX Delay -327 -> 252, step: 8
6768 12:38:27.931998
6769 12:38:27.935492 Set Vref, RX VrefLevel [Byte0]: 51
6770 12:38:27.938426 [Byte1]: 53
6771 12:38:27.942211
6772 12:38:27.942291 Final RX Vref Byte 0 = 51 to rank0
6773 12:38:27.945670 Final RX Vref Byte 1 = 53 to rank0
6774 12:38:27.948926 Final RX Vref Byte 0 = 51 to rank1
6775 12:38:27.952341 Final RX Vref Byte 1 = 53 to rank1==
6776 12:38:27.955744 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 12:38:27.962161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 12:38:27.962237 ==
6779 12:38:27.962318 DQS Delay:
6780 12:38:27.965647 DQS0 = 32, DQS1 = 40
6781 12:38:27.965732 DQM Delay:
6782 12:38:27.965838 DQM0 = 11, DQM1 = 13
6783 12:38:27.968579 DQ Delay:
6784 12:38:27.972345 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6785 12:38:27.972427 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6786 12:38:27.975609 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6787 12:38:27.978675 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6788 12:38:27.978759
6789 12:38:27.982097
6790 12:38:27.988739 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6791 12:38:27.991991 CH1 RK0: MR19=C0C, MR18=93CD
6792 12:38:27.998791 CH1_RK0: MR19=0xC0C, MR18=0x93CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6793 12:38:27.998870 ==
6794 12:38:28.002278 Dram Type= 6, Freq= 0, CH_1, rank 1
6795 12:38:28.005658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 12:38:28.005734 ==
6797 12:38:28.008648 [Gating] SW mode calibration
6798 12:38:28.015538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6799 12:38:28.021921 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6800 12:38:28.025355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 12:38:28.028669 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 12:38:28.035264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 12:38:28.038495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 12:38:28.041778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 12:38:28.045041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 12:38:28.051806 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 12:38:28.055232 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 12:38:28.058237 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 12:38:28.061780 Total UI for P1: 0, mck2ui 16
6810 12:38:28.065166 best dqsien dly found for B0: ( 0, 14, 24)
6811 12:38:28.068440 Total UI for P1: 0, mck2ui 16
6812 12:38:28.071886 best dqsien dly found for B1: ( 0, 14, 24)
6813 12:38:28.074880 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6814 12:38:28.081723 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6815 12:38:28.081805
6816 12:38:28.084912 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 12:38:28.088332 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 12:38:28.092042 [Gating] SW calibration Done
6819 12:38:28.092117 ==
6820 12:38:28.094825 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 12:38:28.098184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 12:38:28.098260 ==
6823 12:38:28.098346 RX Vref Scan: 0
6824 12:38:28.101454
6825 12:38:28.101528 RX Vref 0 -> 0, step: 1
6826 12:38:28.101606
6827 12:38:28.105294 RX Delay -410 -> 252, step: 16
6828 12:38:28.108481 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6829 12:38:28.115119 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6830 12:38:28.118253 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6831 12:38:28.121455 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6832 12:38:28.125043 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6833 12:38:28.131753 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6834 12:38:28.135016 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6835 12:38:28.138422 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6836 12:38:28.141719 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6837 12:38:28.148218 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6838 12:38:28.151689 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6839 12:38:28.155034 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6840 12:38:28.158467 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6841 12:38:28.164681 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6842 12:38:28.168048 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6843 12:38:28.171348 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6844 12:38:28.171425 ==
6845 12:38:28.174786 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 12:38:28.178295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 12:38:28.181675 ==
6848 12:38:28.181754 DQS Delay:
6849 12:38:28.181834 DQS0 = 35, DQS1 = 43
6850 12:38:28.184431 DQM Delay:
6851 12:38:28.184503 DQM0 = 18, DQM1 = 18
6852 12:38:28.187838 DQ Delay:
6853 12:38:28.191238 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6854 12:38:28.191312 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6855 12:38:28.194776 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6856 12:38:28.197756 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6857 12:38:28.201174
6858 12:38:28.201249
6859 12:38:28.201328 ==
6860 12:38:28.204560 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 12:38:28.207815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 12:38:28.207893 ==
6863 12:38:28.207974
6864 12:38:28.208058
6865 12:38:28.211237 TX Vref Scan disable
6866 12:38:28.211317 == TX Byte 0 ==
6867 12:38:28.214817 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6868 12:38:28.221495 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6869 12:38:28.221575 == TX Byte 1 ==
6870 12:38:28.224431 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6871 12:38:28.231301 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6872 12:38:28.231380 ==
6873 12:38:28.234323 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 12:38:28.237819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 12:38:28.237931 ==
6876 12:38:28.238063
6877 12:38:28.238142
6878 12:38:28.241252 TX Vref Scan disable
6879 12:38:28.241362 == TX Byte 0 ==
6880 12:38:28.244505 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6881 12:38:28.251028 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6882 12:38:28.251111 == TX Byte 1 ==
6883 12:38:28.254422 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6884 12:38:28.261349 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6885 12:38:28.261429
6886 12:38:28.261518 [DATLAT]
6887 12:38:28.261597 Freq=400, CH1 RK1
6888 12:38:28.261673
6889 12:38:28.264279 DATLAT Default: 0xe
6890 12:38:28.267642 0, 0xFFFF, sum = 0
6891 12:38:28.267721 1, 0xFFFF, sum = 0
6892 12:38:28.270942 2, 0xFFFF, sum = 0
6893 12:38:28.271026 3, 0xFFFF, sum = 0
6894 12:38:28.274304 4, 0xFFFF, sum = 0
6895 12:38:28.274409 5, 0xFFFF, sum = 0
6896 12:38:28.277751 6, 0xFFFF, sum = 0
6897 12:38:28.277856 7, 0xFFFF, sum = 0
6898 12:38:28.281066 8, 0xFFFF, sum = 0
6899 12:38:28.281142 9, 0xFFFF, sum = 0
6900 12:38:28.284308 10, 0xFFFF, sum = 0
6901 12:38:28.284390 11, 0xFFFF, sum = 0
6902 12:38:28.287700 12, 0xFFFF, sum = 0
6903 12:38:28.287817 13, 0x0, sum = 1
6904 12:38:28.291036 14, 0x0, sum = 2
6905 12:38:28.291131 15, 0x0, sum = 3
6906 12:38:28.294345 16, 0x0, sum = 4
6907 12:38:28.294449 best_step = 14
6908 12:38:28.294536
6909 12:38:28.294614 ==
6910 12:38:28.297849 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 12:38:28.301093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 12:38:28.304360 ==
6913 12:38:28.304437 RX Vref Scan: 0
6914 12:38:28.304538
6915 12:38:28.307750 RX Vref 0 -> 0, step: 1
6916 12:38:28.307829
6917 12:38:28.310947 RX Delay -327 -> 252, step: 8
6918 12:38:28.317625 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6919 12:38:28.320847 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6920 12:38:28.324029 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6921 12:38:28.327526 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6922 12:38:28.333889 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6923 12:38:28.337441 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6924 12:38:28.340646 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6925 12:38:28.344147 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6926 12:38:28.347461 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6927 12:38:28.353920 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6928 12:38:28.357545 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6929 12:38:28.360873 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6930 12:38:28.367604 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6931 12:38:28.371032 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6932 12:38:28.373991 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6933 12:38:28.377343 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6934 12:38:28.377426 ==
6935 12:38:28.380641 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 12:38:28.387283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 12:38:28.387366 ==
6938 12:38:28.387431 DQS Delay:
6939 12:38:28.390734 DQS0 = 28, DQS1 = 36
6940 12:38:28.390809 DQM Delay:
6941 12:38:28.390872 DQM0 = 9, DQM1 = 11
6942 12:38:28.394273 DQ Delay:
6943 12:38:28.397661 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6944 12:38:28.397743 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6945 12:38:28.400470 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6946 12:38:28.404263 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6947 12:38:28.404345
6948 12:38:28.407531
6949 12:38:28.414062 [DQSOSCAuto] RK1, (LSB)MR18= 0xae57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6950 12:38:28.417221 CH1 RK1: MR19=C0C, MR18=AE57
6951 12:38:28.424153 CH1_RK1: MR19=0xC0C, MR18=0xAE57, DQSOSC=388, MR23=63, INC=392, DEC=261
6952 12:38:28.427733 [RxdqsGatingPostProcess] freq 400
6953 12:38:28.430594 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6954 12:38:28.433877 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 12:38:28.437429 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 12:38:28.440368 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 12:38:28.443858 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 12:38:28.447185 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 12:38:28.450621 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 12:38:28.453741 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 12:38:28.457097 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 12:38:28.460568 Pre-setting of DQS Precalculation
6963 12:38:28.463845 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6964 12:38:28.470749 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6965 12:38:28.480308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6966 12:38:28.480392
6967 12:38:28.480457
6968 12:38:28.480518 [Calibration Summary] 800 Mbps
6969 12:38:28.483661 CH 0, Rank 0
6970 12:38:28.487149 SW Impedance : PASS
6971 12:38:28.487232 DUTY Scan : NO K
6972 12:38:28.490431 ZQ Calibration : PASS
6973 12:38:28.490518 Jitter Meter : NO K
6974 12:38:28.493924 CBT Training : PASS
6975 12:38:28.497206 Write leveling : PASS
6976 12:38:28.497289 RX DQS gating : PASS
6977 12:38:28.500579 RX DQ/DQS(RDDQC) : PASS
6978 12:38:28.503791 TX DQ/DQS : PASS
6979 12:38:28.503902 RX DATLAT : PASS
6980 12:38:28.506796 RX DQ/DQS(Engine): PASS
6981 12:38:28.510545 TX OE : NO K
6982 12:38:28.510628 All Pass.
6983 12:38:28.510693
6984 12:38:28.510755 CH 0, Rank 1
6985 12:38:28.513685 SW Impedance : PASS
6986 12:38:28.516838 DUTY Scan : NO K
6987 12:38:28.516951 ZQ Calibration : PASS
6988 12:38:28.520069 Jitter Meter : NO K
6989 12:38:28.523528 CBT Training : PASS
6990 12:38:28.523611 Write leveling : NO K
6991 12:38:28.526783 RX DQS gating : PASS
6992 12:38:28.529897 RX DQ/DQS(RDDQC) : PASS
6993 12:38:28.530018 TX DQ/DQS : PASS
6994 12:38:28.533689 RX DATLAT : PASS
6995 12:38:28.536792 RX DQ/DQS(Engine): PASS
6996 12:38:28.536905 TX OE : NO K
6997 12:38:28.536974 All Pass.
6998 12:38:28.537067
6999 12:38:28.539963 CH 1, Rank 0
7000 12:38:28.543362 SW Impedance : PASS
7001 12:38:28.543453 DUTY Scan : NO K
7002 12:38:28.546549 ZQ Calibration : PASS
7003 12:38:28.546633 Jitter Meter : NO K
7004 12:38:28.549791 CBT Training : PASS
7005 12:38:28.553242 Write leveling : PASS
7006 12:38:28.553371 RX DQS gating : PASS
7007 12:38:28.556676 RX DQ/DQS(RDDQC) : PASS
7008 12:38:28.559917 TX DQ/DQS : PASS
7009 12:38:28.560019 RX DATLAT : PASS
7010 12:38:28.563401 RX DQ/DQS(Engine): PASS
7011 12:38:28.566733 TX OE : NO K
7012 12:38:28.566824 All Pass.
7013 12:38:28.566909
7014 12:38:28.566983 CH 1, Rank 1
7015 12:38:28.569542 SW Impedance : PASS
7016 12:38:28.572807 DUTY Scan : NO K
7017 12:38:28.572890 ZQ Calibration : PASS
7018 12:38:28.576141 Jitter Meter : NO K
7019 12:38:28.579647 CBT Training : PASS
7020 12:38:28.579730 Write leveling : NO K
7021 12:38:28.582974 RX DQS gating : PASS
7022 12:38:28.585908 RX DQ/DQS(RDDQC) : PASS
7023 12:38:28.586036 TX DQ/DQS : PASS
7024 12:38:28.589619 RX DATLAT : PASS
7025 12:38:28.592716 RX DQ/DQS(Engine): PASS
7026 12:38:28.592803 TX OE : NO K
7027 12:38:28.596108 All Pass.
7028 12:38:28.596194
7029 12:38:28.596282 DramC Write-DBI off
7030 12:38:28.599372 PER_BANK_REFRESH: Hybrid Mode
7031 12:38:28.599458 TX_TRACKING: ON
7032 12:38:28.609487 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7033 12:38:28.612889 [FAST_K] Save calibration result to emmc
7034 12:38:28.616285 dramc_set_vcore_voltage set vcore to 725000
7035 12:38:28.619419 Read voltage for 1600, 0
7036 12:38:28.619506 Vio18 = 0
7037 12:38:28.622716 Vcore = 725000
7038 12:38:28.622803 Vdram = 0
7039 12:38:28.622889 Vddq = 0
7040 12:38:28.626169 Vmddr = 0
7041 12:38:28.629487 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7042 12:38:28.635977 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7043 12:38:28.636064 MEM_TYPE=3, freq_sel=13
7044 12:38:28.639099 sv_algorithm_assistance_LP4_3733
7045 12:38:28.642606 ============ PULL DRAM RESETB DOWN ============
7046 12:38:28.649461 ========== PULL DRAM RESETB DOWN end =========
7047 12:38:28.652562 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7048 12:38:28.655660 ===================================
7049 12:38:28.659393 LPDDR4 DRAM CONFIGURATION
7050 12:38:28.662521 ===================================
7051 12:38:28.662608 EX_ROW_EN[0] = 0x0
7052 12:38:28.665917 EX_ROW_EN[1] = 0x0
7053 12:38:28.668981 LP4Y_EN = 0x0
7054 12:38:28.669066 WORK_FSP = 0x1
7055 12:38:28.672316 WL = 0x5
7056 12:38:28.672402 RL = 0x5
7057 12:38:28.675711 BL = 0x2
7058 12:38:28.675797 RPST = 0x0
7059 12:38:28.679131 RD_PRE = 0x0
7060 12:38:28.679218 WR_PRE = 0x1
7061 12:38:28.682465 WR_PST = 0x1
7062 12:38:28.682552 DBI_WR = 0x0
7063 12:38:28.685620 DBI_RD = 0x0
7064 12:38:28.685706 OTF = 0x1
7065 12:38:28.689046 ===================================
7066 12:38:28.692527 ===================================
7067 12:38:28.695832 ANA top config
7068 12:38:28.699242 ===================================
7069 12:38:28.699329 DLL_ASYNC_EN = 0
7070 12:38:28.702325 ALL_SLAVE_EN = 0
7071 12:38:28.705684 NEW_RANK_MODE = 1
7072 12:38:28.708946 DLL_IDLE_MODE = 1
7073 12:38:28.709033 LP45_APHY_COMB_EN = 1
7074 12:38:28.712341 TX_ODT_DIS = 0
7075 12:38:28.715594 NEW_8X_MODE = 1
7076 12:38:28.718956 ===================================
7077 12:38:28.722414 ===================================
7078 12:38:28.725795 data_rate = 3200
7079 12:38:28.729116 CKR = 1
7080 12:38:28.732106 DQ_P2S_RATIO = 8
7081 12:38:28.735619 ===================================
7082 12:38:28.735721 CA_P2S_RATIO = 8
7083 12:38:28.738849 DQ_CA_OPEN = 0
7084 12:38:28.742230 DQ_SEMI_OPEN = 0
7085 12:38:28.745788 CA_SEMI_OPEN = 0
7086 12:38:28.749229 CA_FULL_RATE = 0
7087 12:38:28.752314 DQ_CKDIV4_EN = 0
7088 12:38:28.752395 CA_CKDIV4_EN = 0
7089 12:38:28.755862 CA_PREDIV_EN = 0
7090 12:38:28.759326 PH8_DLY = 12
7091 12:38:28.762082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7092 12:38:28.765483 DQ_AAMCK_DIV = 4
7093 12:38:28.769073 CA_AAMCK_DIV = 4
7094 12:38:28.769150 CA_ADMCK_DIV = 4
7095 12:38:28.771907 DQ_TRACK_CA_EN = 0
7096 12:38:28.775452 CA_PICK = 1600
7097 12:38:28.778761 CA_MCKIO = 1600
7098 12:38:28.782188 MCKIO_SEMI = 0
7099 12:38:28.785172 PLL_FREQ = 3068
7100 12:38:28.788588 DQ_UI_PI_RATIO = 32
7101 12:38:28.788662 CA_UI_PI_RATIO = 0
7102 12:38:28.792315 ===================================
7103 12:38:28.795318 ===================================
7104 12:38:28.798727 memory_type:LPDDR4
7105 12:38:28.802169 GP_NUM : 10
7106 12:38:28.802246 SRAM_EN : 1
7107 12:38:28.805146 MD32_EN : 0
7108 12:38:28.808749 ===================================
7109 12:38:28.812095 [ANA_INIT] >>>>>>>>>>>>>>
7110 12:38:28.815230 <<<<<< [CONFIGURE PHASE]: ANA_TX
7111 12:38:28.818398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7112 12:38:28.822112 ===================================
7113 12:38:28.822190 data_rate = 3200,PCW = 0X7600
7114 12:38:28.825393 ===================================
7115 12:38:28.828587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7116 12:38:28.835182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 12:38:28.841825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 12:38:28.845219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7119 12:38:28.848626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7120 12:38:28.851916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7121 12:38:28.855340 [ANA_INIT] flow start
7122 12:38:28.855417 [ANA_INIT] PLL >>>>>>>>
7123 12:38:28.858291 [ANA_INIT] PLL <<<<<<<<
7124 12:38:28.861926 [ANA_INIT] MIDPI >>>>>>>>
7125 12:38:28.865179 [ANA_INIT] MIDPI <<<<<<<<
7126 12:38:28.865254 [ANA_INIT] DLL >>>>>>>>
7127 12:38:28.868415 [ANA_INIT] DLL <<<<<<<<
7128 12:38:28.871810 [ANA_INIT] flow end
7129 12:38:28.875383 ============ LP4 DIFF to SE enter ============
7130 12:38:28.878229 ============ LP4 DIFF to SE exit ============
7131 12:38:28.881524 [ANA_INIT] <<<<<<<<<<<<<
7132 12:38:28.884980 [Flow] Enable top DCM control >>>>>
7133 12:38:28.888598 [Flow] Enable top DCM control <<<<<
7134 12:38:28.891535 Enable DLL master slave shuffle
7135 12:38:28.895288 ==============================================================
7136 12:38:28.898200 Gating Mode config
7137 12:38:28.901584 ==============================================================
7138 12:38:28.904961 Config description:
7139 12:38:28.915092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7140 12:38:28.921576 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7141 12:38:28.924894 SELPH_MODE 0: By rank 1: By Phase
7142 12:38:28.931427 ==============================================================
7143 12:38:28.934686 GAT_TRACK_EN = 1
7144 12:38:28.938095 RX_GATING_MODE = 2
7145 12:38:28.941508 RX_GATING_TRACK_MODE = 2
7146 12:38:28.944788 SELPH_MODE = 1
7147 12:38:28.948172 PICG_EARLY_EN = 1
7148 12:38:28.951203 VALID_LAT_VALUE = 1
7149 12:38:28.954849 ==============================================================
7150 12:38:28.958165 Enter into Gating configuration >>>>
7151 12:38:28.961171 Exit from Gating configuration <<<<
7152 12:38:28.964896 Enter into DVFS_PRE_config >>>>>
7153 12:38:28.974369 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7154 12:38:28.977868 Exit from DVFS_PRE_config <<<<<
7155 12:38:28.981072 Enter into PICG configuration >>>>
7156 12:38:28.984443 Exit from PICG configuration <<<<
7157 12:38:28.987855 [RX_INPUT] configuration >>>>>
7158 12:38:28.991232 [RX_INPUT] configuration <<<<<
7159 12:38:28.998057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7160 12:38:29.001389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7161 12:38:29.007664 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 12:38:29.014523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 12:38:29.021047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 12:38:29.027718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 12:38:29.030960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7166 12:38:29.034389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7167 12:38:29.037591 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7168 12:38:29.044363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7169 12:38:29.047707 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7170 12:38:29.050951 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 12:38:29.054335 ===================================
7172 12:38:29.057466 LPDDR4 DRAM CONFIGURATION
7173 12:38:29.060942 ===================================
7174 12:38:29.061036 EX_ROW_EN[0] = 0x0
7175 12:38:29.064139 EX_ROW_EN[1] = 0x0
7176 12:38:29.064214 LP4Y_EN = 0x0
7177 12:38:29.067621 WORK_FSP = 0x1
7178 12:38:29.070788 WL = 0x5
7179 12:38:29.070887 RL = 0x5
7180 12:38:29.074266 BL = 0x2
7181 12:38:29.074343 RPST = 0x0
7182 12:38:29.077776 RD_PRE = 0x0
7183 12:38:29.077878 WR_PRE = 0x1
7184 12:38:29.080895 WR_PST = 0x1
7185 12:38:29.081003 DBI_WR = 0x0
7186 12:38:29.083983 DBI_RD = 0x0
7187 12:38:29.084060 OTF = 0x1
7188 12:38:29.087358 ===================================
7189 12:38:29.090724 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7190 12:38:29.097352 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7191 12:38:29.100851 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 12:38:29.104199 ===================================
7193 12:38:29.107580 LPDDR4 DRAM CONFIGURATION
7194 12:38:29.110889 ===================================
7195 12:38:29.110960 EX_ROW_EN[0] = 0x10
7196 12:38:29.114314 EX_ROW_EN[1] = 0x0
7197 12:38:29.114385 LP4Y_EN = 0x0
7198 12:38:29.117485 WORK_FSP = 0x1
7199 12:38:29.117562 WL = 0x5
7200 12:38:29.120597 RL = 0x5
7201 12:38:29.120672 BL = 0x2
7202 12:38:29.123921 RPST = 0x0
7203 12:38:29.127475 RD_PRE = 0x0
7204 12:38:29.127575 WR_PRE = 0x1
7205 12:38:29.130793 WR_PST = 0x1
7206 12:38:29.130862 DBI_WR = 0x0
7207 12:38:29.134151 DBI_RD = 0x0
7208 12:38:29.134218 OTF = 0x1
7209 12:38:29.137515 ===================================
7210 12:38:29.144084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7211 12:38:29.144190 ==
7212 12:38:29.147423 Dram Type= 6, Freq= 0, CH_0, rank 0
7213 12:38:29.150777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7214 12:38:29.150851 ==
7215 12:38:29.154262 [Duty_Offset_Calibration]
7216 12:38:29.154337 B0:2 B1:0 CA:1
7217 12:38:29.154401
7218 12:38:29.157428 [DutyScan_Calibration_Flow] k_type=0
7219 12:38:29.167844
7220 12:38:29.167925 ==CLK 0==
7221 12:38:29.171545 Final CLK duty delay cell = -4
7222 12:38:29.174492 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7223 12:38:29.177839 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7224 12:38:29.181420 [-4] AVG Duty = 4922%(X100)
7225 12:38:29.181528
7226 12:38:29.184435 CH0 CLK Duty spec in!! Max-Min= 218%
7227 12:38:29.187432 [DutyScan_Calibration_Flow] ====Done====
7228 12:38:29.187507
7229 12:38:29.191052 [DutyScan_Calibration_Flow] k_type=1
7230 12:38:29.207256
7231 12:38:29.207332 ==DQS 0 ==
7232 12:38:29.210545 Final DQS duty delay cell = 0
7233 12:38:29.214050 [0] MAX Duty = 5249%(X100), DQS PI = 32
7234 12:38:29.217368 [0] MIN Duty = 4969%(X100), DQS PI = 2
7235 12:38:29.220622 [0] AVG Duty = 5109%(X100)
7236 12:38:29.220725
7237 12:38:29.220817 ==DQS 1 ==
7238 12:38:29.223838 Final DQS duty delay cell = -4
7239 12:38:29.227383 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7240 12:38:29.230669 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7241 12:38:29.234096 [-4] AVG Duty = 5000%(X100)
7242 12:38:29.234170
7243 12:38:29.237204 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7244 12:38:29.237303
7245 12:38:29.240727 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7246 12:38:29.243977 [DutyScan_Calibration_Flow] ====Done====
7247 12:38:29.244081
7248 12:38:29.247290 [DutyScan_Calibration_Flow] k_type=3
7249 12:38:29.265044
7250 12:38:29.265149 ==DQM 0 ==
7251 12:38:29.268518 Final DQM duty delay cell = 0
7252 12:38:29.271722 [0] MAX Duty = 5093%(X100), DQS PI = 26
7253 12:38:29.275026 [0] MIN Duty = 4844%(X100), DQS PI = 0
7254 12:38:29.275107 [0] AVG Duty = 4968%(X100)
7255 12:38:29.278337
7256 12:38:29.278413 ==DQM 1 ==
7257 12:38:29.281537 Final DQM duty delay cell = 0
7258 12:38:29.284580 [0] MAX Duty = 5249%(X100), DQS PI = 30
7259 12:38:29.288222 [0] MIN Duty = 5000%(X100), DQS PI = 20
7260 12:38:29.291449 [0] AVG Duty = 5124%(X100)
7261 12:38:29.291524
7262 12:38:29.294497 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7263 12:38:29.294575
7264 12:38:29.297885 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7265 12:38:29.301237 [DutyScan_Calibration_Flow] ====Done====
7266 12:38:29.301334
7267 12:38:29.304698 [DutyScan_Calibration_Flow] k_type=2
7268 12:38:29.322090
7269 12:38:29.322168 ==DQ 0 ==
7270 12:38:29.325161 Final DQ duty delay cell = 0
7271 12:38:29.328624 [0] MAX Duty = 5156%(X100), DQS PI = 36
7272 12:38:29.331928 [0] MIN Duty = 5000%(X100), DQS PI = 0
7273 12:38:29.332031 [0] AVG Duty = 5078%(X100)
7274 12:38:29.332124
7275 12:38:29.335114 ==DQ 1 ==
7276 12:38:29.338836 Final DQ duty delay cell = 0
7277 12:38:29.342136 [0] MAX Duty = 4969%(X100), DQS PI = 44
7278 12:38:29.345423 [0] MIN Duty = 4875%(X100), DQS PI = 12
7279 12:38:29.345524 [0] AVG Duty = 4922%(X100)
7280 12:38:29.345618
7281 12:38:29.348623 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7282 12:38:29.351936
7283 12:38:29.355007 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7284 12:38:29.358352 [DutyScan_Calibration_Flow] ====Done====
7285 12:38:29.358429 ==
7286 12:38:29.361762 Dram Type= 6, Freq= 0, CH_1, rank 0
7287 12:38:29.364845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 12:38:29.364918 ==
7289 12:38:29.368141 [Duty_Offset_Calibration]
7290 12:38:29.368241 B0:0 B1:-1 CA:2
7291 12:38:29.368332
7292 12:38:29.371607 [DutyScan_Calibration_Flow] k_type=0
7293 12:38:29.382035
7294 12:38:29.382148 ==CLK 0==
7295 12:38:29.385571 Final CLK duty delay cell = 0
7296 12:38:29.388669 [0] MAX Duty = 5156%(X100), DQS PI = 10
7297 12:38:29.392151 [0] MIN Duty = 4906%(X100), DQS PI = 46
7298 12:38:29.392254 [0] AVG Duty = 5031%(X100)
7299 12:38:29.395552
7300 12:38:29.398618 CH1 CLK Duty spec in!! Max-Min= 250%
7301 12:38:29.402176 [DutyScan_Calibration_Flow] ====Done====
7302 12:38:29.402252
7303 12:38:29.405213 [DutyScan_Calibration_Flow] k_type=1
7304 12:38:29.421845
7305 12:38:29.421931 ==DQS 0 ==
7306 12:38:29.425463 Final DQS duty delay cell = 0
7307 12:38:29.428390 [0] MAX Duty = 5093%(X100), DQS PI = 24
7308 12:38:29.431673 [0] MIN Duty = 4969%(X100), DQS PI = 2
7309 12:38:29.431755 [0] AVG Duty = 5031%(X100)
7310 12:38:29.434919
7311 12:38:29.435003 ==DQS 1 ==
7312 12:38:29.438273 Final DQS duty delay cell = 0
7313 12:38:29.441869 [0] MAX Duty = 5187%(X100), DQS PI = 62
7314 12:38:29.445213 [0] MIN Duty = 4844%(X100), DQS PI = 32
7315 12:38:29.448271 [0] AVG Duty = 5015%(X100)
7316 12:38:29.448338
7317 12:38:29.451784 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7318 12:38:29.451880
7319 12:38:29.455105 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7320 12:38:29.458314 [DutyScan_Calibration_Flow] ====Done====
7321 12:38:29.458413
7322 12:38:29.461728 [DutyScan_Calibration_Flow] k_type=3
7323 12:38:29.479545
7324 12:38:29.479655 ==DQM 0 ==
7325 12:38:29.482953 Final DQM duty delay cell = 4
7326 12:38:29.486138 [4] MAX Duty = 5125%(X100), DQS PI = 8
7327 12:38:29.489462 [4] MIN Duty = 4969%(X100), DQS PI = 44
7328 12:38:29.492831 [4] AVG Duty = 5047%(X100)
7329 12:38:29.492905
7330 12:38:29.492968 ==DQM 1 ==
7331 12:38:29.496164 Final DQM duty delay cell = 0
7332 12:38:29.499349 [0] MAX Duty = 5281%(X100), DQS PI = 58
7333 12:38:29.502567 [0] MIN Duty = 4876%(X100), DQS PI = 34
7334 12:38:29.506126 [0] AVG Duty = 5078%(X100)
7335 12:38:29.506201
7336 12:38:29.509453 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7337 12:38:29.509525
7338 12:38:29.512716 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7339 12:38:29.515751 [DutyScan_Calibration_Flow] ====Done====
7340 12:38:29.515841
7341 12:38:29.519110 [DutyScan_Calibration_Flow] k_type=2
7342 12:38:29.536199
7343 12:38:29.536284 ==DQ 0 ==
7344 12:38:29.539956 Final DQ duty delay cell = 0
7345 12:38:29.543233 [0] MAX Duty = 5062%(X100), DQS PI = 20
7346 12:38:29.546512 [0] MIN Duty = 4969%(X100), DQS PI = 0
7347 12:38:29.546584 [0] AVG Duty = 5015%(X100)
7348 12:38:29.546644
7349 12:38:29.549428 ==DQ 1 ==
7350 12:38:29.553200 Final DQ duty delay cell = 0
7351 12:38:29.556545 [0] MAX Duty = 5062%(X100), DQS PI = 2
7352 12:38:29.559889 [0] MIN Duty = 4844%(X100), DQS PI = 32
7353 12:38:29.559962 [0] AVG Duty = 4953%(X100)
7354 12:38:29.560033
7355 12:38:29.563134 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7356 12:38:29.563201
7357 12:38:29.566558 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7358 12:38:29.573101 [DutyScan_Calibration_Flow] ====Done====
7359 12:38:29.576473 nWR fixed to 30
7360 12:38:29.576554 [ModeRegInit_LP4] CH0 RK0
7361 12:38:29.579865 [ModeRegInit_LP4] CH0 RK1
7362 12:38:29.583392 [ModeRegInit_LP4] CH1 RK0
7363 12:38:29.583464 [ModeRegInit_LP4] CH1 RK1
7364 12:38:29.586337 match AC timing 5
7365 12:38:29.589699 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7366 12:38:29.593163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7367 12:38:29.599786 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7368 12:38:29.602736 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7369 12:38:29.609320 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7370 12:38:29.609397 [MiockJmeterHQA]
7371 12:38:29.609484
7372 12:38:29.612814 [DramcMiockJmeter] u1RxGatingPI = 0
7373 12:38:29.616237 0 : 4252, 4027
7374 12:38:29.616315 4 : 4252, 4027
7375 12:38:29.616379 8 : 4253, 4026
7376 12:38:29.619255 12 : 4252, 4027
7377 12:38:29.619354 16 : 4252, 4027
7378 12:38:29.622767 20 : 4253, 4026
7379 12:38:29.622847 24 : 4252, 4027
7380 12:38:29.626248 28 : 4252, 4027
7381 12:38:29.626330 32 : 4253, 4027
7382 12:38:29.626394 36 : 4363, 4138
7383 12:38:29.629424 40 : 4253, 4026
7384 12:38:29.629506 44 : 4252, 4027
7385 12:38:29.632845 48 : 4252, 4027
7386 12:38:29.632926 52 : 4253, 4027
7387 12:38:29.636411 56 : 4252, 4027
7388 12:38:29.636495 60 : 4363, 4137
7389 12:38:29.639682 64 : 4365, 4140
7390 12:38:29.639795 68 : 4249, 4027
7391 12:38:29.639893 72 : 4250, 4026
7392 12:38:29.642585 76 : 4250, 4027
7393 12:38:29.642662 80 : 4250, 4027
7394 12:38:29.645890 84 : 4250, 4027
7395 12:38:29.646015 88 : 4361, 3822
7396 12:38:29.649290 92 : 4250, 0
7397 12:38:29.649375 96 : 4251, 0
7398 12:38:29.649443 100 : 4360, 0
7399 12:38:29.652803 104 : 4361, 0
7400 12:38:29.652889 108 : 4250, 0
7401 12:38:29.655757 112 : 4249, 0
7402 12:38:29.655842 116 : 4250, 0
7403 12:38:29.655909 120 : 4252, 0
7404 12:38:29.659088 124 : 4250, 0
7405 12:38:29.659172 128 : 4250, 0
7406 12:38:29.659240 132 : 4252, 0
7407 12:38:29.662265 136 : 4361, 0
7408 12:38:29.662350 140 : 4250, 0
7409 12:38:29.665734 144 : 4250, 0
7410 12:38:29.665818 148 : 4250, 0
7411 12:38:29.665885 152 : 4360, 0
7412 12:38:29.669351 156 : 4361, 0
7413 12:38:29.669435 160 : 4250, 0
7414 12:38:29.672340 164 : 4250, 0
7415 12:38:29.672426 168 : 4250, 0
7416 12:38:29.672494 172 : 4253, 0
7417 12:38:29.675861 176 : 4250, 0
7418 12:38:29.675945 180 : 4250, 0
7419 12:38:29.679286 184 : 4252, 0
7420 12:38:29.679372 188 : 4361, 0
7421 12:38:29.679465 192 : 4250, 0
7422 12:38:29.682531 196 : 4361, 0
7423 12:38:29.682615 200 : 4250, 4
7424 12:38:29.685908 204 : 4360, 2424
7425 12:38:29.686031 208 : 4361, 4138
7426 12:38:29.688820 212 : 4250, 4027
7427 12:38:29.688943 216 : 4363, 4140
7428 12:38:29.689035 220 : 4361, 4138
7429 12:38:29.692190 224 : 4250, 4027
7430 12:38:29.692315 228 : 4250, 4026
7431 12:38:29.695627 232 : 4361, 4137
7432 12:38:29.695713 236 : 4250, 4027
7433 12:38:29.698994 240 : 4250, 4027
7434 12:38:29.699113 244 : 4250, 4026
7435 12:38:29.702536 248 : 4250, 4027
7436 12:38:29.702622 252 : 4250, 4027
7437 12:38:29.705371 256 : 4249, 4027
7438 12:38:29.705458 260 : 4360, 4137
7439 12:38:29.709085 264 : 4250, 4027
7440 12:38:29.709193 268 : 4250, 4027
7441 12:38:29.712097 272 : 4361, 4138
7442 12:38:29.712203 276 : 4250, 4027
7443 12:38:29.712308 280 : 4250, 4026
7444 12:38:29.715335 284 : 4361, 4137
7445 12:38:29.715442 288 : 4250, 4027
7446 12:38:29.718961 292 : 4249, 4027
7447 12:38:29.719041 296 : 4250, 4026
7448 12:38:29.722103 300 : 4250, 4027
7449 12:38:29.722188 304 : 4250, 4027
7450 12:38:29.725354 308 : 4249, 4027
7451 12:38:29.725433 312 : 4360, 4116
7452 12:38:29.728785 316 : 4250, 2238
7453 12:38:29.728866 320 : 4250, 11
7454 12:38:29.728950
7455 12:38:29.732286 MIOCK jitter meter ch=0
7456 12:38:29.732361
7457 12:38:29.735171 1T = (320-92) = 228 dly cells
7458 12:38:29.738887 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7459 12:38:29.738967 ==
7460 12:38:29.742098 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 12:38:29.748792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 12:38:29.748873 ==
7463 12:38:29.752212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 12:38:29.758389 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 12:38:29.761926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 12:38:29.768251 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 12:38:29.776490 [CA 0] Center 42 (12~73) winsize 62
7468 12:38:29.779850 [CA 1] Center 42 (12~72) winsize 61
7469 12:38:29.783162 [CA 2] Center 37 (7~67) winsize 61
7470 12:38:29.786471 [CA 3] Center 37 (7~67) winsize 61
7471 12:38:29.790093 [CA 4] Center 36 (6~66) winsize 61
7472 12:38:29.793347 [CA 5] Center 35 (5~65) winsize 61
7473 12:38:29.793430
7474 12:38:29.796370 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 12:38:29.796454
7476 12:38:29.799674 [CATrainingPosCal] consider 1 rank data
7477 12:38:29.803165 u2DelayCellTimex100 = 285/100 ps
7478 12:38:29.806465 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7479 12:38:29.813157 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7480 12:38:29.816097 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7481 12:38:29.819782 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7482 12:38:29.822920 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7483 12:38:29.826408 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7484 12:38:29.826491
7485 12:38:29.829927 CA PerBit enable=1, Macro0, CA PI delay=35
7486 12:38:29.830031
7487 12:38:29.832893 [CBTSetCACLKResult] CA Dly = 35
7488 12:38:29.832977 CS Dly: 9 (0~40)
7489 12:38:29.839948 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 12:38:29.843242 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 12:38:29.843326 ==
7492 12:38:29.846419 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 12:38:29.849802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 12:38:29.849915 ==
7495 12:38:29.856236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 12:38:29.859758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 12:38:29.866353 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 12:38:29.869478 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 12:38:29.879539 [CA 0] Center 43 (13~73) winsize 61
7500 12:38:29.882947 [CA 1] Center 43 (13~73) winsize 61
7501 12:38:29.886505 [CA 2] Center 38 (8~68) winsize 61
7502 12:38:29.889723 [CA 3] Center 38 (8~68) winsize 61
7503 12:38:29.893012 [CA 4] Center 36 (6~66) winsize 61
7504 12:38:29.896492 [CA 5] Center 36 (6~66) winsize 61
7505 12:38:29.896579
7506 12:38:29.899873 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 12:38:29.899956
7508 12:38:29.903259 [CATrainingPosCal] consider 2 rank data
7509 12:38:29.906424 u2DelayCellTimex100 = 285/100 ps
7510 12:38:29.909836 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7511 12:38:29.916359 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7512 12:38:29.919794 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7513 12:38:29.923219 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7514 12:38:29.926579 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7515 12:38:29.929693 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7516 12:38:29.929776
7517 12:38:29.933355 CA PerBit enable=1, Macro0, CA PI delay=35
7518 12:38:29.933437
7519 12:38:29.936553 [CBTSetCACLKResult] CA Dly = 35
7520 12:38:29.936636 CS Dly: 10 (0~43)
7521 12:38:29.943052 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 12:38:29.946304 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 12:38:29.946387
7524 12:38:29.949959 ----->DramcWriteLeveling(PI) begin...
7525 12:38:29.950058 ==
7526 12:38:29.953356 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 12:38:29.956574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 12:38:29.956676 ==
7529 12:38:29.959875 Write leveling (Byte 0): 35 => 35
7530 12:38:29.962774 Write leveling (Byte 1): 30 => 30
7531 12:38:29.966489 DramcWriteLeveling(PI) end<-----
7532 12:38:29.966572
7533 12:38:29.966638 ==
7534 12:38:29.969779 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 12:38:29.976359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 12:38:29.976459 ==
7537 12:38:29.976526 [Gating] SW mode calibration
7538 12:38:29.986294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 12:38:29.989693 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 12:38:29.992711 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 12:38:29.999380 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 12:38:30.002901 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7543 12:38:30.005798 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7544 12:38:30.012493 1 4 16 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
7545 12:38:30.015782 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7546 12:38:30.018972 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 12:38:30.025729 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 12:38:30.029170 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 12:38:30.032385 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 12:38:30.038930 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7551 12:38:30.042305 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7552 12:38:30.045558 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7553 12:38:30.052451 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7554 12:38:30.055532 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7555 12:38:30.058718 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 12:38:30.065426 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 12:38:30.068746 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7558 12:38:30.072085 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7559 12:38:30.078772 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 12:38:30.081819 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7561 12:38:30.085274 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7562 12:38:30.091881 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 12:38:30.095360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 12:38:30.098596 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 12:38:30.105217 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 12:38:30.108170 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 12:38:30.111500 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 12:38:30.118199 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 12:38:30.121467 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 12:38:30.125055 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 12:38:30.131737 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 12:38:30.134753 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 12:38:30.138396 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:38:30.144850 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:38:30.148560 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:38:30.151629 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:38:30.158526 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:38:30.161552 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:38:30.165292 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:38:30.171377 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:38:30.174814 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:38:30.178500 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 12:38:30.184770 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 12:38:30.188358 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 12:38:30.191688 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 12:38:30.195114 Total UI for P1: 0, mck2ui 16
7587 12:38:30.198046 best dqsien dly found for B0: ( 1, 9, 12)
7588 12:38:30.201420 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 12:38:30.204863 Total UI for P1: 0, mck2ui 16
7590 12:38:30.207926 best dqsien dly found for B1: ( 1, 9, 20)
7591 12:38:30.214494 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7592 12:38:30.217791 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 12:38:30.217867
7594 12:38:30.221330 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7595 12:38:30.224728 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 12:38:30.227821 [Gating] SW calibration Done
7597 12:38:30.227897 ==
7598 12:38:30.231266 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 12:38:30.234585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 12:38:30.234663 ==
7601 12:38:30.237885 RX Vref Scan: 0
7602 12:38:30.238001
7603 12:38:30.238070 RX Vref 0 -> 0, step: 1
7604 12:38:30.238131
7605 12:38:30.241047 RX Delay 0 -> 252, step: 8
7606 12:38:30.244398 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7607 12:38:30.250987 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7608 12:38:30.254574 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7609 12:38:30.257583 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7610 12:38:30.260951 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7611 12:38:30.264225 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7612 12:38:30.267605 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7613 12:38:30.274184 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7614 12:38:30.277459 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7615 12:38:30.280822 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7616 12:38:30.284139 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7617 12:38:30.290626 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7618 12:38:30.293935 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7619 12:38:30.297374 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7620 12:38:30.300755 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7621 12:38:30.304048 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7622 12:38:30.304131 ==
7623 12:38:30.307466 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 12:38:30.314057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 12:38:30.314144 ==
7626 12:38:30.314210 DQS Delay:
7627 12:38:30.317339 DQS0 = 0, DQS1 = 0
7628 12:38:30.317423 DQM Delay:
7629 12:38:30.317489 DQM0 = 138, DQM1 = 126
7630 12:38:30.320841 DQ Delay:
7631 12:38:30.323912 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7632 12:38:30.327914 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7633 12:38:30.330573 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7634 12:38:30.334211 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =131
7635 12:38:30.334295
7636 12:38:30.334376
7637 12:38:30.334454 ==
7638 12:38:30.337398 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 12:38:30.340792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 12:38:30.344051 ==
7641 12:38:30.344134
7642 12:38:30.344199
7643 12:38:30.344260 TX Vref Scan disable
7644 12:38:30.347432 == TX Byte 0 ==
7645 12:38:30.350866 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7646 12:38:30.354322 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7647 12:38:30.357457 == TX Byte 1 ==
7648 12:38:30.360727 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7649 12:38:30.364037 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7650 12:38:30.367508 ==
7651 12:38:30.367592 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 12:38:30.373899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 12:38:30.374007 ==
7654 12:38:30.386631
7655 12:38:30.389847 TX Vref early break, caculate TX vref
7656 12:38:30.392954 TX Vref=16, minBit 12, minWin=22, winSum=380
7657 12:38:30.396060 TX Vref=18, minBit 6, minWin=23, winSum=387
7658 12:38:30.399277 TX Vref=20, minBit 12, minWin=23, winSum=395
7659 12:38:30.402546 TX Vref=22, minBit 4, minWin=24, winSum=406
7660 12:38:30.409447 TX Vref=24, minBit 5, minWin=25, winSum=416
7661 12:38:30.412872 TX Vref=26, minBit 7, minWin=25, winSum=422
7662 12:38:30.416031 TX Vref=28, minBit 1, minWin=25, winSum=426
7663 12:38:30.419301 TX Vref=30, minBit 7, minWin=25, winSum=423
7664 12:38:30.422688 TX Vref=32, minBit 0, minWin=25, winSum=413
7665 12:38:30.425839 TX Vref=34, minBit 9, minWin=24, winSum=403
7666 12:38:30.432561 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
7667 12:38:30.432645
7668 12:38:30.435747 Final TX Range 0 Vref 28
7669 12:38:30.435830
7670 12:38:30.435896 ==
7671 12:38:30.439157 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:38:30.442559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:38:30.442644 ==
7674 12:38:30.442710
7675 12:38:30.442771
7676 12:38:30.445772 TX Vref Scan disable
7677 12:38:30.452481 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7678 12:38:30.452564 == TX Byte 0 ==
7679 12:38:30.456086 u2DelayCellOfst[0]=13 cells (4 PI)
7680 12:38:30.459415 u2DelayCellOfst[1]=17 cells (5 PI)
7681 12:38:30.462205 u2DelayCellOfst[2]=10 cells (3 PI)
7682 12:38:30.465801 u2DelayCellOfst[3]=13 cells (4 PI)
7683 12:38:30.469090 u2DelayCellOfst[4]=6 cells (2 PI)
7684 12:38:30.472487 u2DelayCellOfst[5]=0 cells (0 PI)
7685 12:38:30.475674 u2DelayCellOfst[6]=17 cells (5 PI)
7686 12:38:30.479148 u2DelayCellOfst[7]=17 cells (5 PI)
7687 12:38:30.482310 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7688 12:38:30.485838 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7689 12:38:30.489121 == TX Byte 1 ==
7690 12:38:30.492275 u2DelayCellOfst[8]=0 cells (0 PI)
7691 12:38:30.492358 u2DelayCellOfst[9]=0 cells (0 PI)
7692 12:38:30.495878 u2DelayCellOfst[10]=10 cells (3 PI)
7693 12:38:30.498749 u2DelayCellOfst[11]=0 cells (0 PI)
7694 12:38:30.502110 u2DelayCellOfst[12]=13 cells (4 PI)
7695 12:38:30.505502 u2DelayCellOfst[13]=10 cells (3 PI)
7696 12:38:30.508954 u2DelayCellOfst[14]=13 cells (4 PI)
7697 12:38:30.512242 u2DelayCellOfst[15]=10 cells (3 PI)
7698 12:38:30.515718 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7699 12:38:30.522244 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7700 12:38:30.522328 DramC Write-DBI on
7701 12:38:30.522392 ==
7702 12:38:30.525758 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:38:30.531941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:38:30.532025 ==
7705 12:38:30.532091
7706 12:38:30.532152
7707 12:38:30.532210 TX Vref Scan disable
7708 12:38:30.536194 == TX Byte 0 ==
7709 12:38:30.539403 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7710 12:38:30.542663 == TX Byte 1 ==
7711 12:38:30.545968 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7712 12:38:30.549425 DramC Write-DBI off
7713 12:38:30.549507
7714 12:38:30.549572 [DATLAT]
7715 12:38:30.549632 Freq=1600, CH0 RK0
7716 12:38:30.549691
7717 12:38:30.552633 DATLAT Default: 0xf
7718 12:38:30.552716 0, 0xFFFF, sum = 0
7719 12:38:30.555820 1, 0xFFFF, sum = 0
7720 12:38:30.559337 2, 0xFFFF, sum = 0
7721 12:38:30.559421 3, 0xFFFF, sum = 0
7722 12:38:30.562723 4, 0xFFFF, sum = 0
7723 12:38:30.562809 5, 0xFFFF, sum = 0
7724 12:38:30.565883 6, 0xFFFF, sum = 0
7725 12:38:30.566024 7, 0xFFFF, sum = 0
7726 12:38:30.569177 8, 0xFFFF, sum = 0
7727 12:38:30.569253 9, 0xFFFF, sum = 0
7728 12:38:30.572502 10, 0xFFFF, sum = 0
7729 12:38:30.572606 11, 0xFFFF, sum = 0
7730 12:38:30.575843 12, 0xFFFF, sum = 0
7731 12:38:30.575918 13, 0xFFFF, sum = 0
7732 12:38:30.579223 14, 0x0, sum = 1
7733 12:38:30.579299 15, 0x0, sum = 2
7734 12:38:30.582704 16, 0x0, sum = 3
7735 12:38:30.582786 17, 0x0, sum = 4
7736 12:38:30.585787 best_step = 15
7737 12:38:30.585861
7738 12:38:30.585925 ==
7739 12:38:30.589215 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 12:38:30.592586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 12:38:30.592690 ==
7742 12:38:30.592783 RX Vref Scan: 1
7743 12:38:30.595983
7744 12:38:30.596081 Set Vref Range= 24 -> 127
7745 12:38:30.596174
7746 12:38:30.599258 RX Vref 24 -> 127, step: 1
7747 12:38:30.599330
7748 12:38:30.602607 RX Delay 19 -> 252, step: 4
7749 12:38:30.602684
7750 12:38:30.605809 Set Vref, RX VrefLevel [Byte0]: 24
7751 12:38:30.609182 [Byte1]: 24
7752 12:38:30.609286
7753 12:38:30.612254 Set Vref, RX VrefLevel [Byte0]: 25
7754 12:38:30.615529 [Byte1]: 25
7755 12:38:30.615603
7756 12:38:30.618876 Set Vref, RX VrefLevel [Byte0]: 26
7757 12:38:30.622489 [Byte1]: 26
7758 12:38:30.626076
7759 12:38:30.626177 Set Vref, RX VrefLevel [Byte0]: 27
7760 12:38:30.629449 [Byte1]: 27
7761 12:38:30.633611
7762 12:38:30.633710 Set Vref, RX VrefLevel [Byte0]: 28
7763 12:38:30.637356 [Byte1]: 28
7764 12:38:30.641196
7765 12:38:30.641346 Set Vref, RX VrefLevel [Byte0]: 29
7766 12:38:30.644770 [Byte1]: 29
7767 12:38:30.648929
7768 12:38:30.649034 Set Vref, RX VrefLevel [Byte0]: 30
7769 12:38:30.652486 [Byte1]: 30
7770 12:38:30.656548
7771 12:38:30.656622 Set Vref, RX VrefLevel [Byte0]: 31
7772 12:38:30.659808 [Byte1]: 31
7773 12:38:30.664116
7774 12:38:30.664192 Set Vref, RX VrefLevel [Byte0]: 32
7775 12:38:30.667513 [Byte1]: 32
7776 12:38:30.671786
7777 12:38:30.671857 Set Vref, RX VrefLevel [Byte0]: 33
7778 12:38:30.674775 [Byte1]: 33
7779 12:38:30.679244
7780 12:38:30.679345 Set Vref, RX VrefLevel [Byte0]: 34
7781 12:38:30.682432 [Byte1]: 34
7782 12:38:30.686696
7783 12:38:30.686771 Set Vref, RX VrefLevel [Byte0]: 35
7784 12:38:30.689868 [Byte1]: 35
7785 12:38:30.694396
7786 12:38:30.694472 Set Vref, RX VrefLevel [Byte0]: 36
7787 12:38:30.697762 [Byte1]: 36
7788 12:38:30.702082
7789 12:38:30.702159 Set Vref, RX VrefLevel [Byte0]: 37
7790 12:38:30.705514 [Byte1]: 37
7791 12:38:30.709736
7792 12:38:30.709815 Set Vref, RX VrefLevel [Byte0]: 38
7793 12:38:30.712737 [Byte1]: 38
7794 12:38:30.717240
7795 12:38:30.717344 Set Vref, RX VrefLevel [Byte0]: 39
7796 12:38:30.720427 [Byte1]: 39
7797 12:38:30.724628
7798 12:38:30.724730 Set Vref, RX VrefLevel [Byte0]: 40
7799 12:38:30.728026 [Byte1]: 40
7800 12:38:30.732072
7801 12:38:30.732171 Set Vref, RX VrefLevel [Byte0]: 41
7802 12:38:30.735762 [Byte1]: 41
7803 12:38:30.739955
7804 12:38:30.740072 Set Vref, RX VrefLevel [Byte0]: 42
7805 12:38:30.743277 [Byte1]: 42
7806 12:38:30.747441
7807 12:38:30.747542 Set Vref, RX VrefLevel [Byte0]: 43
7808 12:38:30.750654 [Byte1]: 43
7809 12:38:30.755065
7810 12:38:30.755139 Set Vref, RX VrefLevel [Byte0]: 44
7811 12:38:30.758296 [Byte1]: 44
7812 12:38:30.762555
7813 12:38:30.762629 Set Vref, RX VrefLevel [Byte0]: 45
7814 12:38:30.765816 [Byte1]: 45
7815 12:38:30.770051
7816 12:38:30.770134 Set Vref, RX VrefLevel [Byte0]: 46
7817 12:38:30.773337 [Byte1]: 46
7818 12:38:30.777553
7819 12:38:30.777667 Set Vref, RX VrefLevel [Byte0]: 47
7820 12:38:30.781055 [Byte1]: 47
7821 12:38:30.785289
7822 12:38:30.785371 Set Vref, RX VrefLevel [Byte0]: 48
7823 12:38:30.788672 [Byte1]: 48
7824 12:38:30.792802
7825 12:38:30.792885 Set Vref, RX VrefLevel [Byte0]: 49
7826 12:38:30.796060 [Byte1]: 49
7827 12:38:30.800296
7828 12:38:30.800380 Set Vref, RX VrefLevel [Byte0]: 50
7829 12:38:30.803887 [Byte1]: 50
7830 12:38:30.808033
7831 12:38:30.808116 Set Vref, RX VrefLevel [Byte0]: 51
7832 12:38:30.811414 [Byte1]: 51
7833 12:38:30.815592
7834 12:38:30.815674 Set Vref, RX VrefLevel [Byte0]: 52
7835 12:38:30.819080 [Byte1]: 52
7836 12:38:30.823334
7837 12:38:30.823417 Set Vref, RX VrefLevel [Byte0]: 53
7838 12:38:30.826824 [Byte1]: 53
7839 12:38:30.830792
7840 12:38:30.830874 Set Vref, RX VrefLevel [Byte0]: 54
7841 12:38:30.834147 [Byte1]: 54
7842 12:38:30.838422
7843 12:38:30.838505 Set Vref, RX VrefLevel [Byte0]: 55
7844 12:38:30.841641 [Byte1]: 55
7845 12:38:30.845872
7846 12:38:30.845961 Set Vref, RX VrefLevel [Byte0]: 56
7847 12:38:30.849285 [Byte1]: 56
7848 12:38:30.853410
7849 12:38:30.853492 Set Vref, RX VrefLevel [Byte0]: 57
7850 12:38:30.856956 [Byte1]: 57
7851 12:38:30.860987
7852 12:38:30.861070 Set Vref, RX VrefLevel [Byte0]: 58
7853 12:38:30.864255 [Byte1]: 58
7854 12:38:30.868475
7855 12:38:30.868585 Set Vref, RX VrefLevel [Byte0]: 59
7856 12:38:30.871850 [Byte1]: 59
7857 12:38:30.876163
7858 12:38:30.876246 Set Vref, RX VrefLevel [Byte0]: 60
7859 12:38:30.879336 [Byte1]: 60
7860 12:38:30.883718
7861 12:38:30.883800 Set Vref, RX VrefLevel [Byte0]: 61
7862 12:38:30.887002 [Byte1]: 61
7863 12:38:30.891435
7864 12:38:30.894737 Set Vref, RX VrefLevel [Byte0]: 62
7865 12:38:30.894825 [Byte1]: 62
7866 12:38:30.898838
7867 12:38:30.898921 Set Vref, RX VrefLevel [Byte0]: 63
7868 12:38:30.902401 [Byte1]: 63
7869 12:38:30.906362
7870 12:38:30.906445 Set Vref, RX VrefLevel [Byte0]: 64
7871 12:38:30.909915 [Byte1]: 64
7872 12:38:30.916402
7873 12:38:30.916486 Set Vref, RX VrefLevel [Byte0]: 65
7874 12:38:30.917336 [Byte1]: 65
7875 12:38:30.921349
7876 12:38:30.921432 Set Vref, RX VrefLevel [Byte0]: 66
7877 12:38:30.924711 [Byte1]: 66
7878 12:38:30.929310
7879 12:38:30.929393 Set Vref, RX VrefLevel [Byte0]: 67
7880 12:38:30.932660 [Byte1]: 67
7881 12:38:30.937031
7882 12:38:30.937113 Set Vref, RX VrefLevel [Byte0]: 68
7883 12:38:30.939874 [Byte1]: 68
7884 12:38:30.944122
7885 12:38:30.944205 Set Vref, RX VrefLevel [Byte0]: 69
7886 12:38:30.947862 [Byte1]: 69
7887 12:38:30.952052
7888 12:38:30.952135 Set Vref, RX VrefLevel [Byte0]: 70
7889 12:38:30.955357 [Byte1]: 70
7890 12:38:30.959763
7891 12:38:30.959846 Set Vref, RX VrefLevel [Byte0]: 71
7892 12:38:30.962588 [Byte1]: 71
7893 12:38:30.966986
7894 12:38:30.967072 Set Vref, RX VrefLevel [Byte0]: 72
7895 12:38:30.970568 [Byte1]: 72
7896 12:38:30.974893
7897 12:38:30.974972 Set Vref, RX VrefLevel [Byte0]: 73
7898 12:38:30.977752 [Byte1]: 73
7899 12:38:30.982050
7900 12:38:30.982135 Set Vref, RX VrefLevel [Byte0]: 74
7901 12:38:30.985243 [Byte1]: 74
7902 12:38:30.990035
7903 12:38:30.990109 Set Vref, RX VrefLevel [Byte0]: 75
7904 12:38:30.993255 [Byte1]: 75
7905 12:38:30.997535
7906 12:38:30.997605 Set Vref, RX VrefLevel [Byte0]: 76
7907 12:38:31.000800 [Byte1]: 76
7908 12:38:31.004698
7909 12:38:31.004769 Set Vref, RX VrefLevel [Byte0]: 77
7910 12:38:31.008175 [Byte1]: 77
7911 12:38:31.012324
7912 12:38:31.012395 Set Vref, RX VrefLevel [Byte0]: 78
7913 12:38:31.015594 [Byte1]: 78
7914 12:38:31.020160
7915 12:38:31.020235 Final RX Vref Byte 0 = 59 to rank0
7916 12:38:31.023602 Final RX Vref Byte 1 = 60 to rank0
7917 12:38:31.026817 Final RX Vref Byte 0 = 59 to rank1
7918 12:38:31.030071 Final RX Vref Byte 1 = 60 to rank1==
7919 12:38:31.033109 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 12:38:31.039870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 12:38:31.039944 ==
7922 12:38:31.040007 DQS Delay:
7923 12:38:31.040075 DQS0 = 0, DQS1 = 0
7924 12:38:31.043278 DQM Delay:
7925 12:38:31.043347 DQM0 = 136, DQM1 = 124
7926 12:38:31.046698 DQ Delay:
7927 12:38:31.049875 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7928 12:38:31.053243 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7929 12:38:31.056473 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7930 12:38:31.059715 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7931 12:38:31.059786
7932 12:38:31.059854
7933 12:38:31.059913
7934 12:38:31.062981 [DramC_TX_OE_Calibration] TA2
7935 12:38:31.066351 Original DQ_B0 (3 6) =30, OEN = 27
7936 12:38:31.069637 Original DQ_B1 (3 6) =30, OEN = 27
7937 12:38:31.072896 24, 0x0, End_B0=24 End_B1=24
7938 12:38:31.072969 25, 0x0, End_B0=25 End_B1=25
7939 12:38:31.076437 26, 0x0, End_B0=26 End_B1=26
7940 12:38:31.079767 27, 0x0, End_B0=27 End_B1=27
7941 12:38:31.083147 28, 0x0, End_B0=28 End_B1=28
7942 12:38:31.086315 29, 0x0, End_B0=29 End_B1=29
7943 12:38:31.086391 30, 0x0, End_B0=30 End_B1=30
7944 12:38:31.089703 31, 0x4545, End_B0=30 End_B1=30
7945 12:38:31.092616 Byte0 end_step=30 best_step=27
7946 12:38:31.096017 Byte1 end_step=30 best_step=27
7947 12:38:31.099352 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 12:38:31.102648 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 12:38:31.102721
7950 12:38:31.102782
7951 12:38:31.109347 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7952 12:38:31.112815 CH0 RK0: MR19=303, MR18=1C1A
7953 12:38:31.119540 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7954 12:38:31.119616
7955 12:38:31.122757 ----->DramcWriteLeveling(PI) begin...
7956 12:38:31.122829 ==
7957 12:38:31.126341 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 12:38:31.129212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 12:38:31.129284 ==
7960 12:38:31.132607 Write leveling (Byte 0): 38 => 38
7961 12:38:31.136090 Write leveling (Byte 1): 27 => 27
7962 12:38:31.139151 DramcWriteLeveling(PI) end<-----
7963 12:38:31.139243
7964 12:38:31.139305 ==
7965 12:38:31.142369 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 12:38:31.145691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 12:38:31.145764 ==
7968 12:38:31.149169 [Gating] SW mode calibration
7969 12:38:31.155722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 12:38:31.162517 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 12:38:31.165734 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 12:38:31.172850 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 12:38:31.175634 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 12:38:31.178948 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7975 12:38:31.185935 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 12:38:31.188788 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 12:38:31.192370 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 12:38:31.195884 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 12:38:31.202781 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 12:38:31.205668 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7981 12:38:31.209158 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 12:38:31.215784 1 5 12 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
7983 12:38:31.219476 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
7984 12:38:31.222143 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 12:38:31.228923 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 12:38:31.232621 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 12:38:31.235627 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 12:38:31.242394 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 12:38:31.245606 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7990 12:38:31.249116 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
7991 12:38:31.255539 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 12:38:31.258877 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 12:38:31.262114 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:38:31.269212 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 12:38:31.272993 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 12:38:31.275848 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 12:38:31.282529 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 12:38:31.286020 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 12:38:31.289461 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8000 12:38:31.295829 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:38:31.299389 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:38:31.302570 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:38:31.309385 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 12:38:31.312868 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:38:31.316504 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:38:31.319355 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:38:31.325556 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:38:31.329031 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:38:31.332611 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:38:31.339490 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:38:31.342445 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:38:31.345836 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:38:31.352323 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8014 12:38:31.356011 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 12:38:31.359192 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8016 12:38:31.362550 Total UI for P1: 0, mck2ui 16
8017 12:38:31.365629 best dqsien dly found for B0: ( 1, 9, 10)
8018 12:38:31.372596 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 12:38:31.373165 Total UI for P1: 0, mck2ui 16
8020 12:38:31.378855 best dqsien dly found for B1: ( 1, 9, 14)
8021 12:38:31.382164 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8022 12:38:31.385498 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8023 12:38:31.386007
8024 12:38:31.388665 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8025 12:38:31.391913 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8026 12:38:31.395317 [Gating] SW calibration Done
8027 12:38:31.395786 ==
8028 12:38:31.398715 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 12:38:31.401975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 12:38:31.402531 ==
8031 12:38:31.405267 RX Vref Scan: 0
8032 12:38:31.405735
8033 12:38:31.406175 RX Vref 0 -> 0, step: 1
8034 12:38:31.408847
8035 12:38:31.409470 RX Delay 0 -> 252, step: 8
8036 12:38:31.411911 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8037 12:38:31.418736 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8038 12:38:31.422348 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8039 12:38:31.425545 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8040 12:38:31.428888 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8041 12:38:31.432180 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8042 12:38:31.439178 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8043 12:38:31.442238 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8044 12:38:31.445398 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8045 12:38:31.448478 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8046 12:38:31.451864 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8047 12:38:31.458555 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8048 12:38:31.461891 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8049 12:38:31.465174 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8050 12:38:31.468936 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8051 12:38:31.472194 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8052 12:38:31.475172 ==
8053 12:38:31.478591 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 12:38:31.481972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 12:38:31.482526 ==
8056 12:38:31.482959 DQS Delay:
8057 12:38:31.485257 DQS0 = 0, DQS1 = 0
8058 12:38:31.485727 DQM Delay:
8059 12:38:31.488549 DQM0 = 136, DQM1 = 125
8060 12:38:31.489021 DQ Delay:
8061 12:38:31.491773 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8062 12:38:31.494884 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8063 12:38:31.498320 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8064 12:38:31.502070 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8065 12:38:31.502651
8066 12:38:31.503030
8067 12:38:31.503375 ==
8068 12:38:31.505172 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 12:38:31.511656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 12:38:31.512135 ==
8071 12:38:31.512510
8072 12:38:31.512858
8073 12:38:31.513196 TX Vref Scan disable
8074 12:38:31.515776 == TX Byte 0 ==
8075 12:38:31.518970 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8076 12:38:31.522362 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8077 12:38:31.525656 == TX Byte 1 ==
8078 12:38:31.528704 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8079 12:38:31.531958 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8080 12:38:31.536053 ==
8081 12:38:31.538902 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 12:38:31.542150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 12:38:31.542648 ==
8084 12:38:31.555894
8085 12:38:31.558977 TX Vref early break, caculate TX vref
8086 12:38:31.562492 TX Vref=16, minBit 3, minWin=23, winSum=390
8087 12:38:31.565980 TX Vref=18, minBit 0, minWin=23, winSum=397
8088 12:38:31.569025 TX Vref=20, minBit 8, minWin=23, winSum=404
8089 12:38:31.572496 TX Vref=22, minBit 0, minWin=25, winSum=414
8090 12:38:31.575671 TX Vref=24, minBit 2, minWin=25, winSum=422
8091 12:38:31.582126 TX Vref=26, minBit 2, minWin=26, winSum=429
8092 12:38:31.585302 TX Vref=28, minBit 0, minWin=26, winSum=427
8093 12:38:31.588793 TX Vref=30, minBit 2, minWin=26, winSum=425
8094 12:38:31.592162 TX Vref=32, minBit 0, minWin=25, winSum=415
8095 12:38:31.595287 TX Vref=34, minBit 0, minWin=25, winSum=406
8096 12:38:31.602520 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 26
8097 12:38:31.603090
8098 12:38:31.605775 Final TX Range 0 Vref 26
8099 12:38:31.606381
8100 12:38:31.606756 ==
8101 12:38:31.608722 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:38:31.612060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:38:31.612540 ==
8104 12:38:31.612909
8105 12:38:31.613254
8106 12:38:31.615211 TX Vref Scan disable
8107 12:38:31.621908 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8108 12:38:31.622469 == TX Byte 0 ==
8109 12:38:31.625267 u2DelayCellOfst[0]=13 cells (4 PI)
8110 12:38:31.628346 u2DelayCellOfst[1]=20 cells (6 PI)
8111 12:38:31.632055 u2DelayCellOfst[2]=13 cells (4 PI)
8112 12:38:31.635607 u2DelayCellOfst[3]=13 cells (4 PI)
8113 12:38:31.638912 u2DelayCellOfst[4]=10 cells (3 PI)
8114 12:38:31.642243 u2DelayCellOfst[5]=0 cells (0 PI)
8115 12:38:31.645342 u2DelayCellOfst[6]=17 cells (5 PI)
8116 12:38:31.648794 u2DelayCellOfst[7]=20 cells (6 PI)
8117 12:38:31.652120 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8118 12:38:31.655176 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8119 12:38:31.658667 == TX Byte 1 ==
8120 12:38:31.659145 u2DelayCellOfst[8]=0 cells (0 PI)
8121 12:38:31.661907 u2DelayCellOfst[9]=3 cells (1 PI)
8122 12:38:31.665324 u2DelayCellOfst[10]=6 cells (2 PI)
8123 12:38:31.668681 u2DelayCellOfst[11]=3 cells (1 PI)
8124 12:38:31.671757 u2DelayCellOfst[12]=13 cells (4 PI)
8125 12:38:31.675061 u2DelayCellOfst[13]=10 cells (3 PI)
8126 12:38:31.678619 u2DelayCellOfst[14]=13 cells (4 PI)
8127 12:38:31.681933 u2DelayCellOfst[15]=10 cells (3 PI)
8128 12:38:31.685168 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8129 12:38:31.692046 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8130 12:38:31.692525 DramC Write-DBI on
8131 12:38:31.692903 ==
8132 12:38:31.695416 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 12:38:31.698489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 12:38:31.701659 ==
8135 12:38:31.702238
8136 12:38:31.702640
8137 12:38:31.703046 TX Vref Scan disable
8138 12:38:31.705478 == TX Byte 0 ==
8139 12:38:31.709229 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8140 12:38:31.711968 == TX Byte 1 ==
8141 12:38:31.715728 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8142 12:38:31.718849 DramC Write-DBI off
8143 12:38:31.719322
8144 12:38:31.719699 [DATLAT]
8145 12:38:31.720147 Freq=1600, CH0 RK1
8146 12:38:31.720499
8147 12:38:31.722315 DATLAT Default: 0xf
8148 12:38:31.722789 0, 0xFFFF, sum = 0
8149 12:38:31.725139 1, 0xFFFF, sum = 0
8150 12:38:31.728467 2, 0xFFFF, sum = 0
8151 12:38:31.728943 3, 0xFFFF, sum = 0
8152 12:38:31.732222 4, 0xFFFF, sum = 0
8153 12:38:31.732701 5, 0xFFFF, sum = 0
8154 12:38:31.735385 6, 0xFFFF, sum = 0
8155 12:38:31.735961 7, 0xFFFF, sum = 0
8156 12:38:31.738700 8, 0xFFFF, sum = 0
8157 12:38:31.739174 9, 0xFFFF, sum = 0
8158 12:38:31.742024 10, 0xFFFF, sum = 0
8159 12:38:31.742465 11, 0xFFFF, sum = 0
8160 12:38:31.745248 12, 0xFFFF, sum = 0
8161 12:38:31.745747 13, 0xFFFF, sum = 0
8162 12:38:31.748618 14, 0x0, sum = 1
8163 12:38:31.749095 15, 0x0, sum = 2
8164 12:38:31.752239 16, 0x0, sum = 3
8165 12:38:31.752824 17, 0x0, sum = 4
8166 12:38:31.755266 best_step = 15
8167 12:38:31.755733
8168 12:38:31.756103 ==
8169 12:38:31.758615 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 12:38:31.762038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 12:38:31.762510 ==
8172 12:38:31.765218 RX Vref Scan: 0
8173 12:38:31.765685
8174 12:38:31.766086 RX Vref 0 -> 0, step: 1
8175 12:38:31.766624
8176 12:38:31.768552 RX Delay 11 -> 252, step: 4
8177 12:38:31.772214 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8178 12:38:31.778548 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8179 12:38:31.781913 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8180 12:38:31.785321 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8181 12:38:31.788952 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8182 12:38:31.792354 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8183 12:38:31.798344 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8184 12:38:31.801861 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8185 12:38:31.805255 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8186 12:38:31.808238 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8187 12:38:31.811672 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8188 12:38:31.818183 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8189 12:38:31.821892 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8190 12:38:31.825346 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8191 12:38:31.828220 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8192 12:38:31.831544 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8193 12:38:31.835457 ==
8194 12:38:31.838239 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:38:31.841499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:38:31.841935 ==
8197 12:38:31.842422 DQS Delay:
8198 12:38:31.845051 DQS0 = 0, DQS1 = 0
8199 12:38:31.845528 DQM Delay:
8200 12:38:31.848272 DQM0 = 133, DQM1 = 123
8201 12:38:31.848699 DQ Delay:
8202 12:38:31.852087 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8203 12:38:31.855238 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8204 12:38:31.858601 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8205 12:38:31.861688 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8206 12:38:31.862158
8207 12:38:31.862587
8208 12:38:31.862996
8209 12:38:31.864910 [DramC_TX_OE_Calibration] TA2
8210 12:38:31.868833 Original DQ_B0 (3 6) =30, OEN = 27
8211 12:38:31.871625 Original DQ_B1 (3 6) =30, OEN = 27
8212 12:38:31.875164 24, 0x0, End_B0=24 End_B1=24
8213 12:38:31.878331 25, 0x0, End_B0=25 End_B1=25
8214 12:38:31.878769 26, 0x0, End_B0=26 End_B1=26
8215 12:38:31.881762 27, 0x0, End_B0=27 End_B1=27
8216 12:38:31.885158 28, 0x0, End_B0=28 End_B1=28
8217 12:38:31.888375 29, 0x0, End_B0=29 End_B1=29
8218 12:38:31.888920 30, 0x0, End_B0=30 End_B1=30
8219 12:38:31.891803 31, 0x4141, End_B0=30 End_B1=30
8220 12:38:31.894972 Byte0 end_step=30 best_step=27
8221 12:38:31.898345 Byte1 end_step=30 best_step=27
8222 12:38:31.901532 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 12:38:31.905075 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 12:38:31.905654
8225 12:38:31.906077
8226 12:38:31.911668 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8227 12:38:31.914821 CH0 RK1: MR19=303, MR18=210D
8228 12:38:31.921772 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8229 12:38:31.924736 [RxdqsGatingPostProcess] freq 1600
8230 12:38:31.931507 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 12:38:31.932085 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 12:38:31.934873 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 12:38:31.938359 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 12:38:31.941722 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 12:38:31.944680 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 12:38:31.947745 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 12:38:31.951269 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 12:38:31.954788 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 12:38:31.958209 Pre-setting of DQS Precalculation
8240 12:38:31.961544 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 12:38:31.962169 ==
8242 12:38:31.964504 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 12:38:31.971266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 12:38:31.971746 ==
8245 12:38:31.974614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 12:38:31.981664 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 12:38:31.984587 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 12:38:31.991092 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 12:38:31.998636 [CA 0] Center 40 (11~70) winsize 60
8250 12:38:32.002253 [CA 1] Center 41 (11~71) winsize 61
8251 12:38:32.005248 [CA 2] Center 37 (8~67) winsize 60
8252 12:38:32.008815 [CA 3] Center 36 (6~66) winsize 61
8253 12:38:32.012177 [CA 4] Center 36 (7~66) winsize 60
8254 12:38:32.015458 [CA 5] Center 36 (6~66) winsize 61
8255 12:38:32.016024
8256 12:38:32.018785 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8257 12:38:32.019348
8258 12:38:32.022239 [CATrainingPosCal] consider 1 rank data
8259 12:38:32.025489 u2DelayCellTimex100 = 285/100 ps
8260 12:38:32.028378 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8261 12:38:32.035261 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8262 12:38:32.038617 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8263 12:38:32.041770 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8264 12:38:32.045353 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8265 12:38:32.048613 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8266 12:38:32.049180
8267 12:38:32.051586 CA PerBit enable=1, Macro0, CA PI delay=36
8268 12:38:32.052060
8269 12:38:32.055296 [CBTSetCACLKResult] CA Dly = 36
8270 12:38:32.055768 CS Dly: 9 (0~40)
8271 12:38:32.062039 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 12:38:32.065809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 12:38:32.066422 ==
8274 12:38:32.068928 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 12:38:32.072272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 12:38:32.072841 ==
8277 12:38:32.078440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 12:38:32.082064 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 12:38:32.088491 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 12:38:32.091535 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 12:38:32.101732 [CA 0] Center 43 (14~72) winsize 59
8282 12:38:32.105274 [CA 1] Center 42 (12~72) winsize 61
8283 12:38:32.108819 [CA 2] Center 38 (9~68) winsize 60
8284 12:38:32.111920 [CA 3] Center 37 (8~67) winsize 60
8285 12:38:32.115272 [CA 4] Center 39 (10~68) winsize 59
8286 12:38:32.118583 [CA 5] Center 37 (8~67) winsize 60
8287 12:38:32.119183
8288 12:38:32.121499 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8289 12:38:32.122095
8290 12:38:32.125683 [CATrainingPosCal] consider 2 rank data
8291 12:38:32.128305 u2DelayCellTimex100 = 285/100 ps
8292 12:38:32.131379 CA0 delay=42 (14~70),Diff = 5 PI (17 cell)
8293 12:38:32.138420 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8294 12:38:32.141580 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8295 12:38:32.144925 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 12:38:32.148278 CA4 delay=38 (10~66),Diff = 1 PI (3 cell)
8297 12:38:32.151660 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 12:38:32.152120
8299 12:38:32.154959 CA PerBit enable=1, Macro0, CA PI delay=37
8300 12:38:32.155449
8301 12:38:32.158183 [CBTSetCACLKResult] CA Dly = 37
8302 12:38:32.161776 CS Dly: 9 (0~41)
8303 12:38:32.165001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 12:38:32.168052 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 12:38:32.168526
8306 12:38:32.171528 ----->DramcWriteLeveling(PI) begin...
8307 12:38:32.171995 ==
8308 12:38:32.174835 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 12:38:32.178278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 12:38:32.181532 ==
8311 12:38:32.182040 Write leveling (Byte 0): 25 => 25
8312 12:38:32.185126 Write leveling (Byte 1): 27 => 27
8313 12:38:32.188232 DramcWriteLeveling(PI) end<-----
8314 12:38:32.188716
8315 12:38:32.189085 ==
8316 12:38:32.191229 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 12:38:32.198133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 12:38:32.198688 ==
8319 12:38:32.199058 [Gating] SW mode calibration
8320 12:38:32.208230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 12:38:32.211374 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 12:38:32.218346 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:38:32.221413 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 12:38:32.224890 1 4 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (1 1)
8325 12:38:32.228323 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 12:38:32.235057 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 12:38:32.238127 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 12:38:32.241870 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 12:38:32.248274 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 12:38:32.251647 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:38:32.254524 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8332 12:38:32.261444 1 5 8 | B1->B0 | 2d2d 2929 | 1 1 | (1 0) (1 0)
8333 12:38:32.264749 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8334 12:38:32.268212 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 12:38:32.274818 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 12:38:32.278086 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 12:38:32.281488 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 12:38:32.288142 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 12:38:32.291478 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:38:32.294825 1 6 8 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
8341 12:38:32.301339 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 12:38:32.304856 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 12:38:32.308327 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 12:38:32.314875 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 12:38:32.318107 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 12:38:32.320988 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:38:32.327737 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8348 12:38:32.331058 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8349 12:38:32.334581 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 12:38:32.341198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 12:38:32.344176 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:38:32.347438 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:38:32.354198 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:38:32.358054 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:38:32.360999 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:38:32.364423 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:38:32.370848 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:38:32.374282 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:38:32.377785 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:38:32.384349 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:38:32.388076 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:38:32.391255 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:38:32.397770 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8364 12:38:32.401303 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8365 12:38:32.404704 Total UI for P1: 0, mck2ui 16
8366 12:38:32.407637 best dqsien dly found for B0: ( 1, 9, 4)
8367 12:38:32.410638 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8368 12:38:32.417583 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:38:32.418193 Total UI for P1: 0, mck2ui 16
8370 12:38:32.423905 best dqsien dly found for B1: ( 1, 9, 10)
8371 12:38:32.427580 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8372 12:38:32.430803 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8373 12:38:32.431275
8374 12:38:32.433865 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8375 12:38:32.437388 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 12:38:32.440951 [Gating] SW calibration Done
8377 12:38:32.441538 ==
8378 12:38:32.443925 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 12:38:32.447293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 12:38:32.447773 ==
8381 12:38:32.450582 RX Vref Scan: 0
8382 12:38:32.451049
8383 12:38:32.451420 RX Vref 0 -> 0, step: 1
8384 12:38:32.451769
8385 12:38:32.453853 RX Delay 0 -> 252, step: 8
8386 12:38:32.457379 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8387 12:38:32.463924 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8388 12:38:32.467308 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8389 12:38:32.470337 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8390 12:38:32.474209 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8391 12:38:32.477345 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8392 12:38:32.483553 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 12:38:32.486998 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8394 12:38:32.490551 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8395 12:38:32.494029 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8396 12:38:32.497360 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 12:38:32.500844 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8398 12:38:32.507028 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 12:38:32.510148 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8400 12:38:32.513870 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 12:38:32.517302 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8402 12:38:32.517878 ==
8403 12:38:32.520504 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:38:32.527109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:38:32.527738 ==
8406 12:38:32.528124 DQS Delay:
8407 12:38:32.530310 DQS0 = 0, DQS1 = 0
8408 12:38:32.530784 DQM Delay:
8409 12:38:32.533410 DQM0 = 137, DQM1 = 130
8410 12:38:32.533883 DQ Delay:
8411 12:38:32.537042 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8412 12:38:32.540035 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8413 12:38:32.543387 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8414 12:38:32.546879 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8415 12:38:32.547470
8416 12:38:32.547849
8417 12:38:32.548199 ==
8418 12:38:32.549983 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 12:38:32.556776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 12:38:32.557350 ==
8421 12:38:32.557728
8422 12:38:32.558157
8423 12:38:32.558586 TX Vref Scan disable
8424 12:38:32.560176 == TX Byte 0 ==
8425 12:38:32.563231 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 12:38:32.570215 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 12:38:32.570788 == TX Byte 1 ==
8428 12:38:32.573606 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 12:38:32.580101 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 12:38:32.580675 ==
8431 12:38:32.583361 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 12:38:32.586902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 12:38:32.587491 ==
8434 12:38:32.598900
8435 12:38:32.602140 TX Vref early break, caculate TX vref
8436 12:38:32.605504 TX Vref=16, minBit 10, minWin=22, winSum=372
8437 12:38:32.608889 TX Vref=18, minBit 10, minWin=22, winSum=381
8438 12:38:32.612179 TX Vref=20, minBit 10, minWin=23, winSum=398
8439 12:38:32.615447 TX Vref=22, minBit 10, minWin=24, winSum=404
8440 12:38:32.622183 TX Vref=24, minBit 10, minWin=24, winSum=410
8441 12:38:32.625598 TX Vref=26, minBit 15, minWin=25, winSum=426
8442 12:38:32.628913 TX Vref=28, minBit 14, minWin=25, winSum=426
8443 12:38:32.632170 TX Vref=30, minBit 12, minWin=25, winSum=420
8444 12:38:32.635175 TX Vref=32, minBit 9, minWin=24, winSum=408
8445 12:38:32.638815 TX Vref=34, minBit 5, minWin=24, winSum=402
8446 12:38:32.645269 [TxChooseVref] Worse bit 15, Min win 25, Win sum 426, Final Vref 26
8447 12:38:32.645819
8448 12:38:32.648882 Final TX Range 0 Vref 26
8449 12:38:32.649448
8450 12:38:32.649819 ==
8451 12:38:32.652200 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 12:38:32.655690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 12:38:32.656160 ==
8454 12:38:32.656529
8455 12:38:32.656872
8456 12:38:32.658441 TX Vref Scan disable
8457 12:38:32.665019 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8458 12:38:32.665491 == TX Byte 0 ==
8459 12:38:32.668783 u2DelayCellOfst[0]=17 cells (5 PI)
8460 12:38:32.672261 u2DelayCellOfst[1]=13 cells (4 PI)
8461 12:38:32.675388 u2DelayCellOfst[2]=0 cells (0 PI)
8462 12:38:32.678813 u2DelayCellOfst[3]=6 cells (2 PI)
8463 12:38:32.681857 u2DelayCellOfst[4]=10 cells (3 PI)
8464 12:38:32.685467 u2DelayCellOfst[5]=20 cells (6 PI)
8465 12:38:32.688942 u2DelayCellOfst[6]=20 cells (6 PI)
8466 12:38:32.691853 u2DelayCellOfst[7]=6 cells (2 PI)
8467 12:38:32.695234 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8468 12:38:32.698824 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 12:38:32.702228 == TX Byte 1 ==
8470 12:38:32.704819 u2DelayCellOfst[8]=0 cells (0 PI)
8471 12:38:32.708406 u2DelayCellOfst[9]=3 cells (1 PI)
8472 12:38:32.708968 u2DelayCellOfst[10]=6 cells (2 PI)
8473 12:38:32.711649 u2DelayCellOfst[11]=3 cells (1 PI)
8474 12:38:32.714940 u2DelayCellOfst[12]=13 cells (4 PI)
8475 12:38:32.718509 u2DelayCellOfst[13]=17 cells (5 PI)
8476 12:38:32.721742 u2DelayCellOfst[14]=17 cells (5 PI)
8477 12:38:32.725438 u2DelayCellOfst[15]=17 cells (5 PI)
8478 12:38:32.731371 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8479 12:38:32.734971 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8480 12:38:32.735539 DramC Write-DBI on
8481 12:38:32.735915 ==
8482 12:38:32.738609 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 12:38:32.745015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 12:38:32.745587 ==
8485 12:38:32.745993
8486 12:38:32.746352
8487 12:38:32.746686 TX Vref Scan disable
8488 12:38:32.749278 == TX Byte 0 ==
8489 12:38:32.752043 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8490 12:38:32.755124 == TX Byte 1 ==
8491 12:38:32.758707 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8492 12:38:32.762051 DramC Write-DBI off
8493 12:38:32.762522
8494 12:38:32.762892 [DATLAT]
8495 12:38:32.763243 Freq=1600, CH1 RK0
8496 12:38:32.763576
8497 12:38:32.765502 DATLAT Default: 0xf
8498 12:38:32.766004 0, 0xFFFF, sum = 0
8499 12:38:32.768488 1, 0xFFFF, sum = 0
8500 12:38:32.772207 2, 0xFFFF, sum = 0
8501 12:38:32.772785 3, 0xFFFF, sum = 0
8502 12:38:32.775468 4, 0xFFFF, sum = 0
8503 12:38:32.776049 5, 0xFFFF, sum = 0
8504 12:38:32.778963 6, 0xFFFF, sum = 0
8505 12:38:32.779441 7, 0xFFFF, sum = 0
8506 12:38:32.781715 8, 0xFFFF, sum = 0
8507 12:38:32.782226 9, 0xFFFF, sum = 0
8508 12:38:32.785254 10, 0xFFFF, sum = 0
8509 12:38:32.785727 11, 0xFFFF, sum = 0
8510 12:38:32.788374 12, 0xFFFF, sum = 0
8511 12:38:32.788847 13, 0xFFFF, sum = 0
8512 12:38:32.792161 14, 0x0, sum = 1
8513 12:38:32.792638 15, 0x0, sum = 2
8514 12:38:32.795311 16, 0x0, sum = 3
8515 12:38:32.795788 17, 0x0, sum = 4
8516 12:38:32.798280 best_step = 15
8517 12:38:32.798747
8518 12:38:32.799120 ==
8519 12:38:32.801744 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 12:38:32.805264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 12:38:32.805827 ==
8522 12:38:32.808572 RX Vref Scan: 1
8523 12:38:32.809136
8524 12:38:32.809509 Set Vref Range= 24 -> 127
8525 12:38:32.809857
8526 12:38:32.812098 RX Vref 24 -> 127, step: 1
8527 12:38:32.812663
8528 12:38:32.815414 RX Delay 19 -> 252, step: 4
8529 12:38:32.815977
8530 12:38:32.818795 Set Vref, RX VrefLevel [Byte0]: 24
8531 12:38:32.822124 [Byte1]: 24
8532 12:38:32.822713
8533 12:38:32.825460 Set Vref, RX VrefLevel [Byte0]: 25
8534 12:38:32.828845 [Byte1]: 25
8535 12:38:32.829442
8536 12:38:32.831771 Set Vref, RX VrefLevel [Byte0]: 26
8537 12:38:32.835124 [Byte1]: 26
8538 12:38:32.839348
8539 12:38:32.839909 Set Vref, RX VrefLevel [Byte0]: 27
8540 12:38:32.842392 [Byte1]: 27
8541 12:38:32.846476
8542 12:38:32.846967 Set Vref, RX VrefLevel [Byte0]: 28
8543 12:38:32.849741 [Byte1]: 28
8544 12:38:32.854000
8545 12:38:32.854469 Set Vref, RX VrefLevel [Byte0]: 29
8546 12:38:32.857285 [Byte1]: 29
8547 12:38:32.861611
8548 12:38:32.862144 Set Vref, RX VrefLevel [Byte0]: 30
8549 12:38:32.864855 [Byte1]: 30
8550 12:38:32.869249
8551 12:38:32.869801 Set Vref, RX VrefLevel [Byte0]: 31
8552 12:38:32.872416 [Byte1]: 31
8553 12:38:32.876654
8554 12:38:32.877173 Set Vref, RX VrefLevel [Byte0]: 32
8555 12:38:32.880147 [Byte1]: 32
8556 12:38:32.884389
8557 12:38:32.884851 Set Vref, RX VrefLevel [Byte0]: 33
8558 12:38:32.887457 [Byte1]: 33
8559 12:38:32.892130
8560 12:38:32.892611 Set Vref, RX VrefLevel [Byte0]: 34
8561 12:38:32.895457 [Byte1]: 34
8562 12:38:32.899734
8563 12:38:32.900293 Set Vref, RX VrefLevel [Byte0]: 35
8564 12:38:32.902674 [Byte1]: 35
8565 12:38:32.907250
8566 12:38:32.907805 Set Vref, RX VrefLevel [Byte0]: 36
8567 12:38:32.910217 [Byte1]: 36
8568 12:38:32.915102
8569 12:38:32.915653 Set Vref, RX VrefLevel [Byte0]: 37
8570 12:38:32.918212 [Byte1]: 37
8571 12:38:32.922458
8572 12:38:32.923024 Set Vref, RX VrefLevel [Byte0]: 38
8573 12:38:32.926030 [Byte1]: 38
8574 12:38:32.929932
8575 12:38:32.930442 Set Vref, RX VrefLevel [Byte0]: 39
8576 12:38:32.933254 [Byte1]: 39
8577 12:38:32.937881
8578 12:38:32.938481 Set Vref, RX VrefLevel [Byte0]: 40
8579 12:38:32.941136 [Byte1]: 40
8580 12:38:32.944948
8581 12:38:32.945411 Set Vref, RX VrefLevel [Byte0]: 41
8582 12:38:32.948202 [Byte1]: 41
8583 12:38:32.952433
8584 12:38:32.952897 Set Vref, RX VrefLevel [Byte0]: 42
8585 12:38:32.955797 [Byte1]: 42
8586 12:38:32.960086
8587 12:38:32.960548 Set Vref, RX VrefLevel [Byte0]: 43
8588 12:38:32.963590 [Byte1]: 43
8589 12:38:32.967977
8590 12:38:32.968437 Set Vref, RX VrefLevel [Byte0]: 44
8591 12:38:32.971092 [Byte1]: 44
8592 12:38:32.975351
8593 12:38:32.975930 Set Vref, RX VrefLevel [Byte0]: 45
8594 12:38:32.978655 [Byte1]: 45
8595 12:38:32.982794
8596 12:38:32.983257 Set Vref, RX VrefLevel [Byte0]: 46
8597 12:38:32.986092 [Byte1]: 46
8598 12:38:32.990773
8599 12:38:32.991415 Set Vref, RX VrefLevel [Byte0]: 47
8600 12:38:32.993806 [Byte1]: 47
8601 12:38:32.997719
8602 12:38:32.998307 Set Vref, RX VrefLevel [Byte0]: 48
8603 12:38:33.001556 [Byte1]: 48
8604 12:38:33.005628
8605 12:38:33.006251 Set Vref, RX VrefLevel [Byte0]: 49
8606 12:38:33.008689 [Byte1]: 49
8607 12:38:33.013544
8608 12:38:33.014150 Set Vref, RX VrefLevel [Byte0]: 50
8609 12:38:33.016813 [Byte1]: 50
8610 12:38:33.020791
8611 12:38:33.021350 Set Vref, RX VrefLevel [Byte0]: 51
8612 12:38:33.024562 [Byte1]: 51
8613 12:38:33.028538
8614 12:38:33.029097 Set Vref, RX VrefLevel [Byte0]: 52
8615 12:38:33.031890 [Byte1]: 52
8616 12:38:33.035768
8617 12:38:33.036334 Set Vref, RX VrefLevel [Byte0]: 53
8618 12:38:33.039602 [Byte1]: 53
8619 12:38:33.043909
8620 12:38:33.044473 Set Vref, RX VrefLevel [Byte0]: 54
8621 12:38:33.046533 [Byte1]: 54
8622 12:38:33.050887
8623 12:38:33.051460 Set Vref, RX VrefLevel [Byte0]: 55
8624 12:38:33.054852 [Byte1]: 55
8625 12:38:33.058387
8626 12:38:33.058860 Set Vref, RX VrefLevel [Byte0]: 56
8627 12:38:33.062128 [Byte1]: 56
8628 12:38:33.066564
8629 12:38:33.067126 Set Vref, RX VrefLevel [Byte0]: 57
8630 12:38:33.069831 [Byte1]: 57
8631 12:38:33.074160
8632 12:38:33.074716 Set Vref, RX VrefLevel [Byte0]: 58
8633 12:38:33.077111 [Byte1]: 58
8634 12:38:33.081621
8635 12:38:33.082231 Set Vref, RX VrefLevel [Byte0]: 59
8636 12:38:33.085073 [Byte1]: 59
8637 12:38:33.089080
8638 12:38:33.089546 Set Vref, RX VrefLevel [Byte0]: 60
8639 12:38:33.092202 [Byte1]: 60
8640 12:38:33.096416
8641 12:38:33.096971 Set Vref, RX VrefLevel [Byte0]: 61
8642 12:38:33.099496 [Byte1]: 61
8643 12:38:33.104160
8644 12:38:33.104948 Set Vref, RX VrefLevel [Byte0]: 62
8645 12:38:33.107491 [Byte1]: 62
8646 12:38:33.111243
8647 12:38:33.112064 Set Vref, RX VrefLevel [Byte0]: 63
8648 12:38:33.114610 [Byte1]: 63
8649 12:38:33.119287
8650 12:38:33.119931 Set Vref, RX VrefLevel [Byte0]: 64
8651 12:38:33.122081 [Byte1]: 64
8652 12:38:33.126355
8653 12:38:33.126659 Set Vref, RX VrefLevel [Byte0]: 65
8654 12:38:33.129656 [Byte1]: 65
8655 12:38:33.134186
8656 12:38:33.134383 Set Vref, RX VrefLevel [Byte0]: 66
8657 12:38:33.137681 [Byte1]: 66
8658 12:38:33.141799
8659 12:38:33.142415 Set Vref, RX VrefLevel [Byte0]: 67
8660 12:38:33.145141 [Byte1]: 67
8661 12:38:33.149438
8662 12:38:33.149902 Set Vref, RX VrefLevel [Byte0]: 68
8663 12:38:33.152833 [Byte1]: 68
8664 12:38:33.156854
8665 12:38:33.157389 Set Vref, RX VrefLevel [Byte0]: 69
8666 12:38:33.160267 [Byte1]: 69
8667 12:38:33.164621
8668 12:38:33.165085 Set Vref, RX VrefLevel [Byte0]: 70
8669 12:38:33.167905 [Byte1]: 70
8670 12:38:33.172081
8671 12:38:33.172498 Set Vref, RX VrefLevel [Byte0]: 71
8672 12:38:33.175312 [Byte1]: 71
8673 12:38:33.179640
8674 12:38:33.180057 Final RX Vref Byte 0 = 50 to rank0
8675 12:38:33.182945 Final RX Vref Byte 1 = 60 to rank0
8676 12:38:33.186516 Final RX Vref Byte 0 = 50 to rank1
8677 12:38:33.189535 Final RX Vref Byte 1 = 60 to rank1==
8678 12:38:33.192877 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 12:38:33.199298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 12:38:33.199729 ==
8681 12:38:33.200062 DQS Delay:
8682 12:38:33.200373 DQS0 = 0, DQS1 = 0
8683 12:38:33.202617 DQM Delay:
8684 12:38:33.203036 DQM0 = 133, DQM1 = 129
8685 12:38:33.206040 DQ Delay:
8686 12:38:33.209505 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8687 12:38:33.212612 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8688 12:38:33.216121 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8689 12:38:33.219249 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8690 12:38:33.219843
8691 12:38:33.220194
8692 12:38:33.220505
8693 12:38:33.222574 [DramC_TX_OE_Calibration] TA2
8694 12:38:33.225922 Original DQ_B0 (3 6) =30, OEN = 27
8695 12:38:33.229488 Original DQ_B1 (3 6) =30, OEN = 27
8696 12:38:33.232707 24, 0x0, End_B0=24 End_B1=24
8697 12:38:33.233132 25, 0x0, End_B0=25 End_B1=25
8698 12:38:33.236334 26, 0x0, End_B0=26 End_B1=26
8699 12:38:33.239813 27, 0x0, End_B0=27 End_B1=27
8700 12:38:33.242754 28, 0x0, End_B0=28 End_B1=28
8701 12:38:33.243181 29, 0x0, End_B0=29 End_B1=29
8702 12:38:33.246287 30, 0x0, End_B0=30 End_B1=30
8703 12:38:33.250015 31, 0x4141, End_B0=30 End_B1=30
8704 12:38:33.253401 Byte0 end_step=30 best_step=27
8705 12:38:33.256105 Byte1 end_step=30 best_step=27
8706 12:38:33.259486 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 12:38:33.259913 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 12:38:33.260251
8709 12:38:33.263010
8710 12:38:33.269974 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8711 12:38:33.273331 CH1 RK0: MR19=303, MR18=1826
8712 12:38:33.279309 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8713 12:38:33.279876
8714 12:38:33.283020 ----->DramcWriteLeveling(PI) begin...
8715 12:38:33.283563 ==
8716 12:38:33.286582 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 12:38:33.289132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 12:38:33.289563 ==
8719 12:38:33.292820 Write leveling (Byte 0): 24 => 24
8720 12:38:33.295792 Write leveling (Byte 1): 29 => 29
8721 12:38:33.299267 DramcWriteLeveling(PI) end<-----
8722 12:38:33.299408
8723 12:38:33.299490 ==
8724 12:38:33.303187 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 12:38:33.305911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 12:38:33.306106 ==
8727 12:38:33.309213 [Gating] SW mode calibration
8728 12:38:33.316007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 12:38:33.322437 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 12:38:33.325746 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 12:38:33.329323 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 12:38:33.336332 1 4 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8733 12:38:33.339200 1 4 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 1)
8734 12:38:33.342777 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 12:38:33.349612 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 12:38:33.352698 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 12:38:33.356129 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 12:38:33.362892 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 12:38:33.366353 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8740 12:38:33.369295 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8741 12:38:33.376050 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (1 0) (1 0)
8742 12:38:33.379459 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 12:38:33.382598 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 12:38:33.389584 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 12:38:33.392940 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 12:38:33.395725 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 12:38:33.399326 1 6 4 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
8748 12:38:33.405753 1 6 8 | B1->B0 | 4242 2323 | 0 0 | (0 0) (0 0)
8749 12:38:33.409299 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8750 12:38:33.412642 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 12:38:33.418976 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 12:38:33.422782 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 12:38:33.426026 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 12:38:33.432339 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 12:38:33.435456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 12:38:33.438947 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8757 12:38:33.445750 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8758 12:38:33.449104 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 12:38:33.452470 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 12:38:33.458911 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 12:38:33.462350 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 12:38:33.465437 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 12:38:33.472344 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 12:38:33.475816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 12:38:33.479173 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 12:38:33.485530 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 12:38:33.488852 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:38:33.492069 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:38:33.499052 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:38:33.502306 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:38:33.505385 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8772 12:38:33.512283 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8773 12:38:33.515646 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8774 12:38:33.518716 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:38:33.521979 Total UI for P1: 0, mck2ui 16
8776 12:38:33.525662 best dqsien dly found for B0: ( 1, 9, 10)
8777 12:38:33.528533 Total UI for P1: 0, mck2ui 16
8778 12:38:33.532131 best dqsien dly found for B1: ( 1, 9, 8)
8779 12:38:33.535250 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8780 12:38:33.538612 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8781 12:38:33.538694
8782 12:38:33.542211 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8783 12:38:33.545409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8784 12:38:33.548793 [Gating] SW calibration Done
8785 12:38:33.548877 ==
8786 12:38:33.552123 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 12:38:33.558908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 12:38:33.558993 ==
8789 12:38:33.559059 RX Vref Scan: 0
8790 12:38:33.559121
8791 12:38:33.562094 RX Vref 0 -> 0, step: 1
8792 12:38:33.562178
8793 12:38:33.565063 RX Delay 0 -> 252, step: 8
8794 12:38:33.568465 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8795 12:38:33.571924 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8796 12:38:33.575117 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8797 12:38:33.578899 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8798 12:38:33.582153 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8799 12:38:33.588764 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8800 12:38:33.591926 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8801 12:38:33.595497 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8802 12:38:33.598771 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8803 12:38:33.602052 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8804 12:38:33.608835 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8805 12:38:33.611740 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8806 12:38:33.615130 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8807 12:38:33.618550 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8808 12:38:33.625233 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8809 12:38:33.628556 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8810 12:38:33.628801 ==
8811 12:38:33.632191 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 12:38:33.635140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 12:38:33.635385 ==
8814 12:38:33.635577 DQS Delay:
8815 12:38:33.638393 DQS0 = 0, DQS1 = 0
8816 12:38:33.638636 DQM Delay:
8817 12:38:33.641640 DQM0 = 137, DQM1 = 131
8818 12:38:33.641926 DQ Delay:
8819 12:38:33.645441 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8820 12:38:33.648720 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8821 12:38:33.651823 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8822 12:38:33.658686 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8823 12:38:33.659005
8824 12:38:33.659227
8825 12:38:33.659407 ==
8826 12:38:33.662121 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 12:38:33.665492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 12:38:33.665758 ==
8829 12:38:33.665972
8830 12:38:33.666180
8831 12:38:33.668413 TX Vref Scan disable
8832 12:38:33.668692 == TX Byte 0 ==
8833 12:38:33.675295 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8834 12:38:33.678724 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8835 12:38:33.678983 == TX Byte 1 ==
8836 12:38:33.685335 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8837 12:38:33.688929 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8838 12:38:33.689209 ==
8839 12:38:33.691969 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 12:38:33.695455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 12:38:33.695677 ==
8842 12:38:33.708904
8843 12:38:33.712262 TX Vref early break, caculate TX vref
8844 12:38:33.715535 TX Vref=16, minBit 9, minWin=21, winSum=381
8845 12:38:33.718866 TX Vref=18, minBit 12, minWin=22, winSum=390
8846 12:38:33.722337 TX Vref=20, minBit 9, minWin=23, winSum=400
8847 12:38:33.725406 TX Vref=22, minBit 9, minWin=23, winSum=405
8848 12:38:33.729215 TX Vref=24, minBit 10, minWin=24, winSum=412
8849 12:38:33.735981 TX Vref=26, minBit 8, minWin=25, winSum=419
8850 12:38:33.738851 TX Vref=28, minBit 9, minWin=24, winSum=418
8851 12:38:33.742509 TX Vref=30, minBit 10, minWin=24, winSum=415
8852 12:38:33.745354 TX Vref=32, minBit 8, minWin=24, winSum=404
8853 12:38:33.748808 TX Vref=34, minBit 8, minWin=23, winSum=397
8854 12:38:33.755146 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 26
8855 12:38:33.755573
8856 12:38:33.758860 Final TX Range 0 Vref 26
8857 12:38:33.759337
8858 12:38:33.759670 ==
8859 12:38:33.762125 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 12:38:33.765097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 12:38:33.765671 ==
8862 12:38:33.766235
8863 12:38:33.766628
8864 12:38:33.769085 TX Vref Scan disable
8865 12:38:33.775266 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8866 12:38:33.775775 == TX Byte 0 ==
8867 12:38:33.778745 u2DelayCellOfst[0]=13 cells (4 PI)
8868 12:38:33.781933 u2DelayCellOfst[1]=10 cells (3 PI)
8869 12:38:33.785156 u2DelayCellOfst[2]=0 cells (0 PI)
8870 12:38:33.788597 u2DelayCellOfst[3]=3 cells (1 PI)
8871 12:38:33.791787 u2DelayCellOfst[4]=6 cells (2 PI)
8872 12:38:33.794753 u2DelayCellOfst[5]=17 cells (5 PI)
8873 12:38:33.798159 u2DelayCellOfst[6]=17 cells (5 PI)
8874 12:38:33.801515 u2DelayCellOfst[7]=3 cells (1 PI)
8875 12:38:33.804616 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8876 12:38:33.807869 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8877 12:38:33.811490 == TX Byte 1 ==
8878 12:38:33.811562 u2DelayCellOfst[8]=0 cells (0 PI)
8879 12:38:33.814866 u2DelayCellOfst[9]=3 cells (1 PI)
8880 12:38:33.817933 u2DelayCellOfst[10]=6 cells (2 PI)
8881 12:38:33.821204 u2DelayCellOfst[11]=3 cells (1 PI)
8882 12:38:33.824726 u2DelayCellOfst[12]=13 cells (4 PI)
8883 12:38:33.828220 u2DelayCellOfst[13]=13 cells (4 PI)
8884 12:38:33.831060 u2DelayCellOfst[14]=17 cells (5 PI)
8885 12:38:33.834772 u2DelayCellOfst[15]=17 cells (5 PI)
8886 12:38:33.838098 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8887 12:38:33.844512 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8888 12:38:33.844587 DramC Write-DBI on
8889 12:38:33.844650 ==
8890 12:38:33.847969 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 12:38:33.851375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 12:38:33.855125 ==
8893 12:38:33.855208
8894 12:38:33.855273
8895 12:38:33.855333 TX Vref Scan disable
8896 12:38:33.858470 == TX Byte 0 ==
8897 12:38:33.861445 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8898 12:38:33.864625 == TX Byte 1 ==
8899 12:38:33.868150 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8900 12:38:33.868233 DramC Write-DBI off
8901 12:38:33.871368
8902 12:38:33.871474 [DATLAT]
8903 12:38:33.871550 Freq=1600, CH1 RK1
8904 12:38:33.871620
8905 12:38:33.874868 DATLAT Default: 0xf
8906 12:38:33.874956 0, 0xFFFF, sum = 0
8907 12:38:33.878296 1, 0xFFFF, sum = 0
8908 12:38:33.878393 2, 0xFFFF, sum = 0
8909 12:38:33.881622 3, 0xFFFF, sum = 0
8910 12:38:33.881726 4, 0xFFFF, sum = 0
8911 12:38:33.884594 5, 0xFFFF, sum = 0
8912 12:38:33.888253 6, 0xFFFF, sum = 0
8913 12:38:33.888411 7, 0xFFFF, sum = 0
8914 12:38:33.891192 8, 0xFFFF, sum = 0
8915 12:38:33.891357 9, 0xFFFF, sum = 0
8916 12:38:33.894549 10, 0xFFFF, sum = 0
8917 12:38:33.894698 11, 0xFFFF, sum = 0
8918 12:38:33.898438 12, 0xFFFF, sum = 0
8919 12:38:33.898565 13, 0xFFFF, sum = 0
8920 12:38:33.901777 14, 0x0, sum = 1
8921 12:38:33.901984 15, 0x0, sum = 2
8922 12:38:33.904579 16, 0x0, sum = 3
8923 12:38:33.904736 17, 0x0, sum = 4
8924 12:38:33.907881 best_step = 15
8925 12:38:33.908072
8926 12:38:33.908203 ==
8927 12:38:33.911236 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 12:38:33.914708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 12:38:33.914949 ==
8930 12:38:33.915103 RX Vref Scan: 0
8931 12:38:33.915290
8932 12:38:33.918238 RX Vref 0 -> 0, step: 1
8933 12:38:33.918503
8934 12:38:33.921155 RX Delay 19 -> 252, step: 4
8935 12:38:33.924825 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8936 12:38:33.931405 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
8937 12:38:33.934803 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
8938 12:38:33.938216 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8939 12:38:33.941332 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8940 12:38:33.944671 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8941 12:38:33.947937 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8942 12:38:33.951384 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8943 12:38:33.958141 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8944 12:38:33.961647 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8945 12:38:33.964693 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8946 12:38:33.967895 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8947 12:38:33.971136 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8948 12:38:33.978114 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8949 12:38:33.981679 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8950 12:38:33.984715 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8951 12:38:33.984816 ==
8952 12:38:33.988004 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 12:38:33.991473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 12:38:33.994734 ==
8955 12:38:33.994810 DQS Delay:
8956 12:38:33.994873 DQS0 = 0, DQS1 = 0
8957 12:38:33.998128 DQM Delay:
8958 12:38:33.998216 DQM0 = 133, DQM1 = 130
8959 12:38:34.001639 DQ Delay:
8960 12:38:34.004658 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =130
8961 12:38:34.007850 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
8962 12:38:34.011241 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8963 12:38:34.014593 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8964 12:38:34.014668
8965 12:38:34.014731
8966 12:38:34.014789
8967 12:38:34.017903 [DramC_TX_OE_Calibration] TA2
8968 12:38:34.021196 Original DQ_B0 (3 6) =30, OEN = 27
8969 12:38:34.024466 Original DQ_B1 (3 6) =30, OEN = 27
8970 12:38:34.024540 24, 0x0, End_B0=24 End_B1=24
8971 12:38:34.028091 25, 0x0, End_B0=25 End_B1=25
8972 12:38:34.031140 26, 0x0, End_B0=26 End_B1=26
8973 12:38:34.034508 27, 0x0, End_B0=27 End_B1=27
8974 12:38:34.037681 28, 0x0, End_B0=28 End_B1=28
8975 12:38:34.037765 29, 0x0, End_B0=29 End_B1=29
8976 12:38:34.040983 30, 0x0, End_B0=30 End_B1=30
8977 12:38:34.044196 31, 0x4141, End_B0=30 End_B1=30
8978 12:38:34.047895 Byte0 end_step=30 best_step=27
8979 12:38:34.051191 Byte1 end_step=30 best_step=27
8980 12:38:34.054321 Byte0 TX OE(2T, 0.5T) = (3, 3)
8981 12:38:34.054394 Byte1 TX OE(2T, 0.5T) = (3, 3)
8982 12:38:34.054457
8983 12:38:34.054530
8984 12:38:34.064306 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
8985 12:38:34.067632 CH1 RK1: MR19=303, MR18=1B06
8986 12:38:34.074200 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
8987 12:38:34.074277 [RxdqsGatingPostProcess] freq 1600
8988 12:38:34.080803 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8989 12:38:34.084202 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 12:38:34.087325 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 12:38:34.090791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 12:38:34.094531 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 12:38:34.097400 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 12:38:34.100867 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 12:38:34.104362 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 12:38:34.107900 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 12:38:34.108016 Pre-setting of DQS Precalculation
8998 12:38:34.114131 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8999 12:38:34.120684 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9000 12:38:34.127713 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9001 12:38:34.127797
9002 12:38:34.127862
9003 12:38:34.130894 [Calibration Summary] 3200 Mbps
9004 12:38:34.134219 CH 0, Rank 0
9005 12:38:34.134329 SW Impedance : PASS
9006 12:38:34.137662 DUTY Scan : NO K
9007 12:38:34.140635 ZQ Calibration : PASS
9008 12:38:34.140738 Jitter Meter : NO K
9009 12:38:34.143987 CBT Training : PASS
9010 12:38:34.144056 Write leveling : PASS
9011 12:38:34.147431 RX DQS gating : PASS
9012 12:38:34.150736 RX DQ/DQS(RDDQC) : PASS
9013 12:38:34.150808 TX DQ/DQS : PASS
9014 12:38:34.154127 RX DATLAT : PASS
9015 12:38:34.157589 RX DQ/DQS(Engine): PASS
9016 12:38:34.157658 TX OE : PASS
9017 12:38:34.161015 All Pass.
9018 12:38:34.161103
9019 12:38:34.161173 CH 0, Rank 1
9020 12:38:34.163997 SW Impedance : PASS
9021 12:38:34.164112 DUTY Scan : NO K
9022 12:38:34.167689 ZQ Calibration : PASS
9023 12:38:34.170871 Jitter Meter : NO K
9024 12:38:34.171021 CBT Training : PASS
9025 12:38:34.174022 Write leveling : PASS
9026 12:38:34.177493 RX DQS gating : PASS
9027 12:38:34.177640 RX DQ/DQS(RDDQC) : PASS
9028 12:38:34.180970 TX DQ/DQS : PASS
9029 12:38:34.184072 RX DATLAT : PASS
9030 12:38:34.184238 RX DQ/DQS(Engine): PASS
9031 12:38:34.187233 TX OE : PASS
9032 12:38:34.187423 All Pass.
9033 12:38:34.187588
9034 12:38:34.190782 CH 1, Rank 0
9035 12:38:34.190988 SW Impedance : PASS
9036 12:38:34.194007 DUTY Scan : NO K
9037 12:38:34.197413 ZQ Calibration : PASS
9038 12:38:34.197602 Jitter Meter : NO K
9039 12:38:34.200451 CBT Training : PASS
9040 12:38:34.203917 Write leveling : PASS
9041 12:38:34.204160 RX DQS gating : PASS
9042 12:38:34.207341 RX DQ/DQS(RDDQC) : PASS
9043 12:38:34.207556 TX DQ/DQS : PASS
9044 12:38:34.210786 RX DATLAT : PASS
9045 12:38:34.213882 RX DQ/DQS(Engine): PASS
9046 12:38:34.214124 TX OE : PASS
9047 12:38:34.217316 All Pass.
9048 12:38:34.217605
9049 12:38:34.217866 CH 1, Rank 1
9050 12:38:34.220498 SW Impedance : PASS
9051 12:38:34.220791 DUTY Scan : NO K
9052 12:38:34.223682 ZQ Calibration : PASS
9053 12:38:34.227161 Jitter Meter : NO K
9054 12:38:34.227389 CBT Training : PASS
9055 12:38:34.230475 Write leveling : PASS
9056 12:38:34.233499 RX DQS gating : PASS
9057 12:38:34.233824 RX DQ/DQS(RDDQC) : PASS
9058 12:38:34.236833 TX DQ/DQS : PASS
9059 12:38:34.240616 RX DATLAT : PASS
9060 12:38:34.240861 RX DQ/DQS(Engine): PASS
9061 12:38:34.243419 TX OE : PASS
9062 12:38:34.243663 All Pass.
9063 12:38:34.243852
9064 12:38:34.247081 DramC Write-DBI on
9065 12:38:34.250423 PER_BANK_REFRESH: Hybrid Mode
9066 12:38:34.250672 TX_TRACKING: ON
9067 12:38:34.260247 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9068 12:38:34.266558 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9069 12:38:34.273352 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 12:38:34.276851 [FAST_K] Save calibration result to emmc
9071 12:38:34.280476 sync common calibartion params.
9072 12:38:34.283735 sync cbt_mode0:1, 1:1
9073 12:38:34.287386 dram_init: ddr_geometry: 2
9074 12:38:34.287792 dram_init: ddr_geometry: 2
9075 12:38:34.290254 dram_init: ddr_geometry: 2
9076 12:38:34.293787 0:dram_rank_size:100000000
9077 12:38:34.294231 1:dram_rank_size:100000000
9078 12:38:34.300368 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9079 12:38:34.303811 DFS_SHUFFLE_HW_MODE: ON
9080 12:38:34.307032 dramc_set_vcore_voltage set vcore to 725000
9081 12:38:34.310188 Read voltage for 1600, 0
9082 12:38:34.310584 Vio18 = 0
9083 12:38:34.310897 Vcore = 725000
9084 12:38:34.313609 Vdram = 0
9085 12:38:34.314029 Vddq = 0
9086 12:38:34.314345 Vmddr = 0
9087 12:38:34.316850 switch to 3200 Mbps bootup
9088 12:38:34.317245 [DramcRunTimeConfig]
9089 12:38:34.320326 PHYPLL
9090 12:38:34.320719 DPM_CONTROL_AFTERK: ON
9091 12:38:34.323641 PER_BANK_REFRESH: ON
9092 12:38:34.326687 REFRESH_OVERHEAD_REDUCTION: ON
9093 12:38:34.327081 CMD_PICG_NEW_MODE: OFF
9094 12:38:34.330259 XRTWTW_NEW_MODE: ON
9095 12:38:34.330655 XRTRTR_NEW_MODE: ON
9096 12:38:34.333305 TX_TRACKING: ON
9097 12:38:34.333698 RDSEL_TRACKING: OFF
9098 12:38:34.336655 DQS Precalculation for DVFS: ON
9099 12:38:34.340230 RX_TRACKING: OFF
9100 12:38:34.340624 HW_GATING DBG: ON
9101 12:38:34.343403 ZQCS_ENABLE_LP4: ON
9102 12:38:34.343794 RX_PICG_NEW_MODE: ON
9103 12:38:34.346834 TX_PICG_NEW_MODE: ON
9104 12:38:34.350075 ENABLE_RX_DCM_DPHY: ON
9105 12:38:34.350471 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9106 12:38:34.353288 DUMMY_READ_FOR_TRACKING: OFF
9107 12:38:34.356670 !!! SPM_CONTROL_AFTERK: OFF
9108 12:38:34.360155 !!! SPM could not control APHY
9109 12:38:34.360730 IMPEDANCE_TRACKING: ON
9110 12:38:34.363240 TEMP_SENSOR: ON
9111 12:38:34.363634 HW_SAVE_FOR_SR: OFF
9112 12:38:34.366593 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9113 12:38:34.369582 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9114 12:38:34.372986 Read ODT Tracking: ON
9115 12:38:34.376459 Refresh Rate DeBounce: ON
9116 12:38:34.376677 DFS_NO_QUEUE_FLUSH: ON
9117 12:38:34.380061 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9118 12:38:34.383273 ENABLE_DFS_RUNTIME_MRW: OFF
9119 12:38:34.386821 DDR_RESERVE_NEW_MODE: ON
9120 12:38:34.387036 MR_CBT_SWITCH_FREQ: ON
9121 12:38:34.389987 =========================
9122 12:38:34.408917 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9123 12:38:34.411928 dram_init: ddr_geometry: 2
9124 12:38:34.430511 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9125 12:38:34.433509 dram_init: dram init end (result: 0)
9126 12:38:34.440332 DRAM-K: Full calibration passed in 24438 msecs
9127 12:38:34.443694 MRC: failed to locate region type 0.
9128 12:38:34.443910 DRAM rank0 size:0x100000000,
9129 12:38:34.446740 DRAM rank1 size=0x100000000
9130 12:38:34.457057 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9131 12:38:34.463744 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9132 12:38:34.469993 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9133 12:38:34.476543 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9134 12:38:34.479961 DRAM rank0 size:0x100000000,
9135 12:38:34.483602 DRAM rank1 size=0x100000000
9136 12:38:34.483817 CBMEM:
9137 12:38:34.486646 IMD: root @ 0xfffff000 254 entries.
9138 12:38:34.489951 IMD: root @ 0xffffec00 62 entries.
9139 12:38:34.493479 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9140 12:38:34.496806 WARNING: RO_VPD is uninitialized or empty.
9141 12:38:34.503792 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9142 12:38:34.510454 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9143 12:38:34.523552 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9144 12:38:34.534660 BS: romstage times (exec / console): total (unknown) / 23951 ms
9145 12:38:34.535103
9146 12:38:34.535549
9147 12:38:34.544808 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9148 12:38:34.547965 ARM64: Exception handlers installed.
9149 12:38:34.551362 ARM64: Testing exception
9150 12:38:34.554567 ARM64: Done test exception
9151 12:38:34.554799 Enumerating buses...
9152 12:38:34.558004 Show all devs... Before device enumeration.
9153 12:38:34.561273 Root Device: enabled 1
9154 12:38:34.564414 CPU_CLUSTER: 0: enabled 1
9155 12:38:34.564601 CPU: 00: enabled 1
9156 12:38:34.567837 Compare with tree...
9157 12:38:34.568022 Root Device: enabled 1
9158 12:38:34.571369 CPU_CLUSTER: 0: enabled 1
9159 12:38:34.574834 CPU: 00: enabled 1
9160 12:38:34.575020 Root Device scanning...
9161 12:38:34.577549 scan_static_bus for Root Device
9162 12:38:34.581103 CPU_CLUSTER: 0 enabled
9163 12:38:34.584322 scan_static_bus for Root Device done
9164 12:38:34.587627 scan_bus: bus Root Device finished in 8 msecs
9165 12:38:34.587856 done
9166 12:38:34.594903 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9167 12:38:34.597766 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9168 12:38:34.604271 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9169 12:38:34.607512 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9170 12:38:34.611023 Allocating resources...
9171 12:38:34.614598 Reading resources...
9172 12:38:34.617332 Root Device read_resources bus 0 link: 0
9173 12:38:34.617517 DRAM rank0 size:0x100000000,
9174 12:38:34.620888 DRAM rank1 size=0x100000000
9175 12:38:34.624410 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9176 12:38:34.627560 CPU: 00 missing read_resources
9177 12:38:34.631140 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9178 12:38:34.637132 Root Device read_resources bus 0 link: 0 done
9179 12:38:34.637334 Done reading resources.
9180 12:38:34.643826 Show resources in subtree (Root Device)...After reading.
9181 12:38:34.647297 Root Device child on link 0 CPU_CLUSTER: 0
9182 12:38:34.650696 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 12:38:34.660892 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 12:38:34.661079 CPU: 00
9185 12:38:34.663966 Root Device assign_resources, bus 0 link: 0
9186 12:38:34.667640 CPU_CLUSTER: 0 missing set_resources
9187 12:38:34.674098 Root Device assign_resources, bus 0 link: 0 done
9188 12:38:34.674282 Done setting resources.
9189 12:38:34.680770 Show resources in subtree (Root Device)...After assigning values.
9190 12:38:34.683997 Root Device child on link 0 CPU_CLUSTER: 0
9191 12:38:34.687486 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 12:38:34.697385 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 12:38:34.697520 CPU: 00
9194 12:38:34.700318 Done allocating resources.
9195 12:38:34.703812 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9196 12:38:34.707572 Enabling resources...
9197 12:38:34.707737 done.
9198 12:38:34.714230 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9199 12:38:34.714427 Initializing devices...
9200 12:38:34.717565 Root Device init
9201 12:38:34.717759 init hardware done!
9202 12:38:34.720527 0x00000018: ctrlr->caps
9203 12:38:34.723937 52.000 MHz: ctrlr->f_max
9204 12:38:34.724097 0.400 MHz: ctrlr->f_min
9205 12:38:34.727194 0x40ff8080: ctrlr->voltages
9206 12:38:34.727351 sclk: 390625
9207 12:38:34.730389 Bus Width = 1
9208 12:38:34.730504 sclk: 390625
9209 12:38:34.733753 Bus Width = 1
9210 12:38:34.733868 Early init status = 3
9211 12:38:34.740196 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9212 12:38:34.743749 in-header: 03 fc 00 00 01 00 00 00
9213 12:38:34.747136 in-data: 00
9214 12:38:34.750220 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9215 12:38:34.755464 in-header: 03 fd 00 00 00 00 00 00
9216 12:38:34.758673 in-data:
9217 12:38:34.761890 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9218 12:38:34.766599 in-header: 03 fc 00 00 01 00 00 00
9219 12:38:34.769399 in-data: 00
9220 12:38:34.773336 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9221 12:38:34.779079 in-header: 03 fd 00 00 00 00 00 00
9222 12:38:34.781946 in-data:
9223 12:38:34.785539 [SSUSB] Setting up USB HOST controller...
9224 12:38:34.788375 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9225 12:38:34.791697 [SSUSB] phy power-on done.
9226 12:38:34.795045 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9227 12:38:34.802079 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9228 12:38:34.805302 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9229 12:38:34.812148 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9230 12:38:34.818816 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9231 12:38:34.825266 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9232 12:38:34.832102 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9233 12:38:34.838606 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9234 12:38:34.841848 SPM: binary array size = 0x9dc
9235 12:38:34.845313 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9236 12:38:34.852152 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9237 12:38:34.858460 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9238 12:38:34.861883 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9239 12:38:34.868392 configure_display: Starting display init
9240 12:38:34.901873 anx7625_power_on_init: Init interface.
9241 12:38:34.905361 anx7625_disable_pd_protocol: Disabled PD feature.
9242 12:38:34.908266 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9243 12:38:34.936689 anx7625_start_dp_work: Secure OCM version=00
9244 12:38:34.939733 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9245 12:38:34.954541 sp_tx_get_edid_block: EDID Block = 1
9246 12:38:35.057794 Extracted contents:
9247 12:38:35.061070 header: 00 ff ff ff ff ff ff 00
9248 12:38:35.064169 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9249 12:38:35.067570 version: 01 04
9250 12:38:35.070613 basic params: 95 1f 11 78 0a
9251 12:38:35.074080 chroma info: 76 90 94 55 54 90 27 21 50 54
9252 12:38:35.077356 established: 00 00 00
9253 12:38:35.083967 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9254 12:38:35.087321 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9255 12:38:35.093990 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9256 12:38:35.100473 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9257 12:38:35.106814 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9258 12:38:35.110375 extensions: 00
9259 12:38:35.110945 checksum: fb
9260 12:38:35.111318
9261 12:38:35.113673 Manufacturer: IVO Model 57d Serial Number 0
9262 12:38:35.117041 Made week 0 of 2020
9263 12:38:35.117614 EDID version: 1.4
9264 12:38:35.120305 Digital display
9265 12:38:35.124067 6 bits per primary color channel
9266 12:38:35.124679 DisplayPort interface
9267 12:38:35.127094 Maximum image size: 31 cm x 17 cm
9268 12:38:35.130513 Gamma: 220%
9269 12:38:35.131085 Check DPMS levels
9270 12:38:35.133544 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9271 12:38:35.137260 First detailed timing is preferred timing
9272 12:38:35.140224 Established timings supported:
9273 12:38:35.143940 Standard timings supported:
9274 12:38:35.146821 Detailed timings
9275 12:38:35.150645 Hex of detail: 383680a07038204018303c0035ae10000019
9276 12:38:35.153507 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9277 12:38:35.160341 0780 0798 07c8 0820 hborder 0
9278 12:38:35.163720 0438 043b 0447 0458 vborder 0
9279 12:38:35.167115 -hsync -vsync
9280 12:38:35.167696 Did detailed timing
9281 12:38:35.173682 Hex of detail: 000000000000000000000000000000000000
9282 12:38:35.174314 Manufacturer-specified data, tag 0
9283 12:38:35.180446 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9284 12:38:35.181083 ASCII string: InfoVision
9285 12:38:35.186929 Hex of detail: 000000fe00523134304e574635205248200a
9286 12:38:35.190116 ASCII string: R140NWF5 RH
9287 12:38:35.190695 Checksum
9288 12:38:35.191072 Checksum: 0xfb (valid)
9289 12:38:35.197004 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9290 12:38:35.200008 DSI data_rate: 832800000 bps
9291 12:38:35.203156 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9292 12:38:35.210218 anx7625_parse_edid: pixelclock(138800).
9293 12:38:35.213134 hactive(1920), hsync(48), hfp(24), hbp(88)
9294 12:38:35.216846 vactive(1080), vsync(12), vfp(3), vbp(17)
9295 12:38:35.219725 anx7625_dsi_config: config dsi.
9296 12:38:35.226581 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9297 12:38:35.239248 anx7625_dsi_config: success to config DSI
9298 12:38:35.242266 anx7625_dp_start: MIPI phy setup OK.
9299 12:38:35.245823 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9300 12:38:35.249117 mtk_ddp_mode_set invalid vrefresh 60
9301 12:38:35.252463 main_disp_path_setup
9302 12:38:35.252743 ovl_layer_smi_id_en
9303 12:38:35.255692 ovl_layer_smi_id_en
9304 12:38:35.255921 ccorr_config
9305 12:38:35.256063 aal_config
9306 12:38:35.258733 gamma_config
9307 12:38:35.258925 postmask_config
9308 12:38:35.262522 dither_config
9309 12:38:35.265889 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9310 12:38:35.272525 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9311 12:38:35.275256 Root Device init finished in 555 msecs
9312 12:38:35.275338 CPU_CLUSTER: 0 init
9313 12:38:35.285767 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9314 12:38:35.289114 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9315 12:38:35.292377 APU_MBOX 0x190000b0 = 0x10001
9316 12:38:35.295425 APU_MBOX 0x190001b0 = 0x10001
9317 12:38:35.298862 APU_MBOX 0x190005b0 = 0x10001
9318 12:38:35.302261 APU_MBOX 0x190006b0 = 0x10001
9319 12:38:35.305286 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9320 12:38:35.317891 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9321 12:38:35.330004 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9322 12:38:35.336877 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9323 12:38:35.348431 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9324 12:38:35.357956 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9325 12:38:35.361010 CPU_CLUSTER: 0 init finished in 81 msecs
9326 12:38:35.364263 Devices initialized
9327 12:38:35.367836 Show all devs... After init.
9328 12:38:35.367992 Root Device: enabled 1
9329 12:38:35.370912 CPU_CLUSTER: 0: enabled 1
9330 12:38:35.374451 CPU: 00: enabled 1
9331 12:38:35.377597 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9332 12:38:35.380759 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9333 12:38:35.384083 ELOG: NV offset 0x57f000 size 0x1000
9334 12:38:35.391054 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9335 12:38:35.397535 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9336 12:38:35.401091 ELOG: Event(17) added with size 13 at 2024-02-05 12:37:59 UTC
9337 12:38:35.404766 out: cmd=0x121: 03 db 21 01 00 00 00 00
9338 12:38:35.408446 in-header: 03 74 00 00 2c 00 00 00
9339 12:38:35.421673 in-data: ec 67 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 12:38:35.428241 ELOG: Event(A1) added with size 10 at 2024-02-05 12:37:59 UTC
9341 12:38:35.434939 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9342 12:38:35.442129 ELOG: Event(A0) added with size 9 at 2024-02-05 12:37:59 UTC
9343 12:38:35.445504 elog_add_boot_reason: Logged dev mode boot
9344 12:38:35.448651 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9345 12:38:35.451787 Finalize devices...
9346 12:38:35.452251 Devices finalized
9347 12:38:35.458191 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9348 12:38:35.461625 Writing coreboot table at 0xffe64000
9349 12:38:35.465082 0. 000000000010a000-0000000000113fff: RAMSTAGE
9350 12:38:35.468007 1. 0000000040000000-00000000400fffff: RAM
9351 12:38:35.471603 2. 0000000040100000-000000004032afff: RAMSTAGE
9352 12:38:35.478302 3. 000000004032b000-00000000545fffff: RAM
9353 12:38:35.481509 4. 0000000054600000-000000005465ffff: BL31
9354 12:38:35.484911 5. 0000000054660000-00000000ffe63fff: RAM
9355 12:38:35.487920 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9356 12:38:35.494926 7. 0000000100000000-000000023fffffff: RAM
9357 12:38:35.495351 Passing 5 GPIOs to payload:
9358 12:38:35.501532 NAME | PORT | POLARITY | VALUE
9359 12:38:35.504483 EC in RW | 0x000000aa | low | undefined
9360 12:38:35.510923 EC interrupt | 0x00000005 | low | undefined
9361 12:38:35.514238 TPM interrupt | 0x000000ab | high | undefined
9362 12:38:35.517794 SD card detect | 0x00000011 | high | undefined
9363 12:38:35.524270 speaker enable | 0x00000093 | high | undefined
9364 12:38:35.527617 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9365 12:38:35.531098 in-header: 03 f9 00 00 02 00 00 00
9366 12:38:35.531253 in-data: 02 00
9367 12:38:35.534448 ADC[4]: Raw value=901032 ID=7
9368 12:38:35.537793 ADC[3]: Raw value=212810 ID=1
9369 12:38:35.537957 RAM Code: 0x71
9370 12:38:35.541028 ADC[6]: Raw value=74502 ID=0
9371 12:38:35.544375 ADC[5]: Raw value=211703 ID=1
9372 12:38:35.544529 SKU Code: 0x1
9373 12:38:35.551041 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d248
9374 12:38:35.553967 coreboot table: 964 bytes.
9375 12:38:35.557603 IMD ROOT 0. 0xfffff000 0x00001000
9376 12:38:35.560892 IMD SMALL 1. 0xffffe000 0x00001000
9377 12:38:35.563885 RO MCACHE 2. 0xffffc000 0x00001104
9378 12:38:35.567439 CONSOLE 3. 0xfff7c000 0x00080000
9379 12:38:35.570617 FMAP 4. 0xfff7b000 0x00000452
9380 12:38:35.574086 TIME STAMP 5. 0xfff7a000 0x00000910
9381 12:38:35.577433 VBOOT WORK 6. 0xfff66000 0x00014000
9382 12:38:35.580837 RAMOOPS 7. 0xffe66000 0x00100000
9383 12:38:35.583713 COREBOOT 8. 0xffe64000 0x00002000
9384 12:38:35.583796 IMD small region:
9385 12:38:35.587151 IMD ROOT 0. 0xffffec00 0x00000400
9386 12:38:35.590589 VPD 1. 0xffffeb80 0x0000006c
9387 12:38:35.593928 MMC STATUS 2. 0xffffeb60 0x00000004
9388 12:38:35.600428 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9389 12:38:35.600574 Probing TPM: done!
9390 12:38:35.607491 Connected to device vid:did:rid of 1ae0:0028:00
9391 12:38:35.614507 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9392 12:38:35.618160 Initialized TPM device CR50 revision 0
9393 12:38:35.621323 Checking cr50 for pending updates
9394 12:38:35.627302 Reading cr50 TPM mode
9395 12:38:35.636120 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9396 12:38:35.643093 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9397 12:38:35.683121 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9398 12:38:35.686548 Checking segment from ROM address 0x40100000
9399 12:38:35.690057 Checking segment from ROM address 0x4010001c
9400 12:38:35.697067 Loading segment from ROM address 0x40100000
9401 12:38:35.697613 code (compression=0)
9402 12:38:35.703160 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9403 12:38:35.713783 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9404 12:38:35.714380 it's not compressed!
9405 12:38:35.720274 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9406 12:38:35.723440 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9407 12:38:35.743820 Loading segment from ROM address 0x4010001c
9408 12:38:35.744379 Entry Point 0x80000000
9409 12:38:35.747194 Loaded segments
9410 12:38:35.750545 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9411 12:38:35.757254 Jumping to boot code at 0x80000000(0xffe64000)
9412 12:38:35.763636 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9413 12:38:35.770216 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9414 12:38:35.777761 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9415 12:38:35.781583 Checking segment from ROM address 0x40100000
9416 12:38:35.784708 Checking segment from ROM address 0x4010001c
9417 12:38:35.791519 Loading segment from ROM address 0x40100000
9418 12:38:35.792090 code (compression=1)
9419 12:38:35.798516 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9420 12:38:35.808237 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9421 12:38:35.808804 using LZMA
9422 12:38:35.816801 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9423 12:38:35.823164 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9424 12:38:35.826436 Loading segment from ROM address 0x4010001c
9425 12:38:35.827007 Entry Point 0x54601000
9426 12:38:35.829764 Loaded segments
9427 12:38:35.833241 NOTICE: MT8192 bl31_setup
9428 12:38:35.840222 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9429 12:38:35.843573 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9430 12:38:35.846718 WARNING: region 0:
9431 12:38:35.850149 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 12:38:35.850625 WARNING: region 1:
9433 12:38:35.856934 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9434 12:38:35.860112 WARNING: region 2:
9435 12:38:35.863496 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9436 12:38:35.866929 WARNING: region 3:
9437 12:38:35.870379 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 12:38:35.873593 WARNING: region 4:
9439 12:38:35.877269 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 12:38:35.880520 WARNING: region 5:
9441 12:38:35.883684 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 12:38:35.886861 WARNING: region 6:
9443 12:38:35.890621 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 12:38:35.891185 WARNING: region 7:
9445 12:38:35.896659 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 12:38:35.903751 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9447 12:38:35.906924 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9448 12:38:35.910106 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9449 12:38:35.916627 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9450 12:38:35.920432 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9451 12:38:35.923480 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9452 12:38:35.930009 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9453 12:38:35.933729 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9454 12:38:35.937024 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9455 12:38:35.943624 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9456 12:38:35.947129 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9457 12:38:35.950080 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9458 12:38:35.957124 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9459 12:38:35.960431 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9460 12:38:35.966915 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9461 12:38:35.970251 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9462 12:38:35.973834 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9463 12:38:35.980152 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9464 12:38:35.983721 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9465 12:38:35.986911 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9466 12:38:35.994020 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9467 12:38:35.997329 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9468 12:38:36.004182 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9469 12:38:36.006992 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9470 12:38:36.010944 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9471 12:38:36.017687 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9472 12:38:36.020768 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9473 12:38:36.027160 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9474 12:38:36.030423 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9475 12:38:36.033718 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9476 12:38:36.040923 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9477 12:38:36.043856 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9478 12:38:36.047393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9479 12:38:36.054212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9480 12:38:36.057304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9481 12:38:36.060579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9482 12:38:36.063764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9483 12:38:36.070559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9484 12:38:36.074316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9485 12:38:36.077385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9486 12:38:36.080814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9487 12:38:36.086873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9488 12:38:36.090474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9489 12:38:36.093920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9490 12:38:36.097031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9491 12:38:36.103726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9492 12:38:36.107559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9493 12:38:36.110710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9494 12:38:36.116794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9495 12:38:36.120461 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9496 12:38:36.123628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9497 12:38:36.130118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9498 12:38:36.133829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9499 12:38:36.140409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9500 12:38:36.143935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9501 12:38:36.150544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9502 12:38:36.154035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9503 12:38:36.157215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9504 12:38:36.163506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9505 12:38:36.166991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9506 12:38:36.173600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9507 12:38:36.177315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9508 12:38:36.183770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9509 12:38:36.187223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9510 12:38:36.190216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9511 12:38:36.197059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9512 12:38:36.200501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9513 12:38:36.206832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9514 12:38:36.210473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9515 12:38:36.216746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9516 12:38:36.220544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9517 12:38:36.223561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9518 12:38:36.230438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9519 12:38:36.233411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9520 12:38:36.240041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9521 12:38:36.243458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9522 12:38:36.250116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9523 12:38:36.253555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9524 12:38:36.259802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9525 12:38:36.263106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9526 12:38:36.266410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9527 12:38:36.273102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9528 12:38:36.276607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9529 12:38:36.283564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9530 12:38:36.286611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9531 12:38:36.293413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9532 12:38:36.296812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9533 12:38:36.300240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9534 12:38:36.306418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9535 12:38:36.309911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9536 12:38:36.316723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9537 12:38:36.319962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9538 12:38:36.326778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9539 12:38:36.330098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9540 12:38:36.333610 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9541 12:38:36.340457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9542 12:38:36.343338 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9543 12:38:36.346585 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9544 12:38:36.353445 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9545 12:38:36.356787 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9546 12:38:36.360259 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9547 12:38:36.363723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9548 12:38:36.369843 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9549 12:38:36.373282 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9550 12:38:36.380455 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9551 12:38:36.383904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9552 12:38:36.386975 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9553 12:38:36.393828 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9554 12:38:36.397109 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9555 12:38:36.403440 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9556 12:38:36.407070 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9557 12:38:36.410328 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9558 12:38:36.417417 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9559 12:38:36.421078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9560 12:38:36.427508 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9561 12:38:36.430893 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9562 12:38:36.434283 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9563 12:38:36.437685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9564 12:38:36.444211 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9565 12:38:36.447588 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9566 12:38:36.450571 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9567 12:38:36.454413 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9568 12:38:36.461065 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9569 12:38:36.464432 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9570 12:38:36.467846 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9571 12:38:36.474020 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9572 12:38:36.477719 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9573 12:38:36.484248 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9574 12:38:36.487360 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9575 12:38:36.490871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9576 12:38:36.497028 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9577 12:38:36.500656 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9578 12:38:36.504159 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9579 12:38:36.510458 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9580 12:38:36.514220 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9581 12:38:36.520485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9582 12:38:36.524237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9583 12:38:36.527290 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9584 12:38:36.533860 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9585 12:38:36.537278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9586 12:38:36.543996 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9587 12:38:36.547340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9588 12:38:36.550723 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9589 12:38:36.557126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9590 12:38:36.560547 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9591 12:38:36.564035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9592 12:38:36.570441 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9593 12:38:36.573836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9594 12:38:36.580641 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9595 12:38:36.583410 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9596 12:38:36.586829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9597 12:38:36.593632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9598 12:38:36.597305 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9599 12:38:36.603967 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9600 12:38:36.607102 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9601 12:38:36.610657 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9602 12:38:36.617114 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9603 12:38:36.620509 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9604 12:38:36.623884 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9605 12:38:36.630400 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9606 12:38:36.633661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9607 12:38:36.640212 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9608 12:38:36.643690 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9609 12:38:36.647275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9610 12:38:36.653838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9611 12:38:36.657122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9612 12:38:36.663747 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9613 12:38:36.667022 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9614 12:38:36.670612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9615 12:38:36.676721 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9616 12:38:36.680042 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9617 12:38:36.687007 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9618 12:38:36.690323 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9619 12:38:36.693571 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9620 12:38:36.700360 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9621 12:38:36.703475 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9622 12:38:36.706793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9623 12:38:36.713801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9624 12:38:36.717232 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9625 12:38:36.723793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9626 12:38:36.727162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9627 12:38:36.730233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9628 12:38:36.736876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9629 12:38:36.740427 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9630 12:38:36.747343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9631 12:38:36.750180 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9632 12:38:36.753560 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9633 12:38:36.760292 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9634 12:38:36.763722 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9635 12:38:36.770083 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9636 12:38:36.773687 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9637 12:38:36.780399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9638 12:38:36.783372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9639 12:38:36.787432 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9640 12:38:36.794302 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9641 12:38:36.796618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9642 12:38:36.803323 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9643 12:38:36.806718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9644 12:38:36.810092 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9645 12:38:36.816864 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9646 12:38:36.820228 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9647 12:38:36.827151 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9648 12:38:36.830226 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9649 12:38:36.836793 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9650 12:38:36.839755 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9651 12:38:36.843576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9652 12:38:36.850199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9653 12:38:36.853212 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9654 12:38:36.860401 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9655 12:38:36.863809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9656 12:38:36.866886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9657 12:38:36.873497 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9658 12:38:36.876699 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9659 12:38:36.883419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9660 12:38:36.886533 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9661 12:38:36.890055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9662 12:38:36.896688 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9663 12:38:36.899862 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9664 12:38:36.906559 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9665 12:38:36.910091 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9666 12:38:36.916682 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9667 12:38:36.920083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9668 12:38:36.923468 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9669 12:38:36.930030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9670 12:38:36.933105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9671 12:38:36.940043 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9672 12:38:36.943121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9673 12:38:36.946415 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9674 12:38:36.953057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9675 12:38:36.956370 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9676 12:38:36.959564 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9677 12:38:36.963030 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9678 12:38:36.969821 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9679 12:38:36.973129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9680 12:38:36.976406 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9681 12:38:36.982782 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9682 12:38:36.986254 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9683 12:38:36.993159 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9684 12:38:36.996363 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9685 12:38:36.999682 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9686 12:38:37.005877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9687 12:38:37.009649 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9688 12:38:37.012748 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9689 12:38:37.019490 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9690 12:38:37.022609 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9691 12:38:37.026191 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9692 12:38:37.032578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9693 12:38:37.035812 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9694 12:38:37.038857 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9695 12:38:37.045857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9696 12:38:37.049495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9697 12:38:37.055551 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9698 12:38:37.058954 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9699 12:38:37.062293 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9700 12:38:37.068830 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9701 12:38:37.072210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9702 12:38:37.079320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9703 12:38:37.082691 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9704 12:38:37.085611 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9705 12:38:37.092407 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9706 12:38:37.095452 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9707 12:38:37.098616 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9708 12:38:37.105141 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9709 12:38:37.108888 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9710 12:38:37.112072 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9711 12:38:37.118576 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9712 12:38:37.121715 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9713 12:38:37.128462 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9714 12:38:37.131889 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9715 12:38:37.135158 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9716 12:38:37.138481 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9717 12:38:37.145003 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9718 12:38:37.148630 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9719 12:38:37.151818 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9720 12:38:37.155344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9721 12:38:37.158345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9722 12:38:37.165052 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9723 12:38:37.168297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9724 12:38:37.171368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9725 12:38:37.174864 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9726 12:38:37.181867 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9727 12:38:37.185291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9728 12:38:37.191429 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9729 12:38:37.194903 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9730 12:38:37.198040 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9731 12:38:37.204348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9732 12:38:37.207585 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9733 12:38:37.214643 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9734 12:38:37.217996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9735 12:38:37.221600 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9736 12:38:37.228291 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9737 12:38:37.231248 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9738 12:38:37.237705 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9739 12:38:37.241353 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9740 12:38:37.248106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9741 12:38:37.251479 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9742 12:38:37.254886 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9743 12:38:37.261012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9744 12:38:37.264611 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9745 12:38:37.270756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9746 12:38:37.274191 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9747 12:38:37.277705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9748 12:38:37.284398 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9749 12:38:37.287489 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9750 12:38:37.294484 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9751 12:38:37.297396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9752 12:38:37.300710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9753 12:38:37.307328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9754 12:38:37.310592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9755 12:38:37.317242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9756 12:38:37.320908 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9757 12:38:37.327206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9758 12:38:37.330290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9759 12:38:37.333936 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9760 12:38:37.340056 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9761 12:38:37.343936 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9762 12:38:37.350386 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9763 12:38:37.353986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9764 12:38:37.357222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9765 12:38:37.364138 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9766 12:38:37.367493 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9767 12:38:37.370583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9768 12:38:37.377299 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9769 12:38:37.380679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9770 12:38:37.387223 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9771 12:38:37.390630 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9772 12:38:37.397474 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9773 12:38:37.400420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9774 12:38:37.407283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9775 12:38:37.410041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9776 12:38:37.413469 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9777 12:38:37.420671 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9778 12:38:37.423652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9779 12:38:37.427052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9780 12:38:37.433772 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9781 12:38:37.436786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9782 12:38:37.443610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9783 12:38:37.446643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9784 12:38:37.450213 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9785 12:38:37.456872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9786 12:38:37.460371 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9787 12:38:37.467184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9788 12:38:37.470540 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9789 12:38:37.476814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9790 12:38:37.480508 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9791 12:38:37.483551 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9792 12:38:37.490372 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9793 12:38:37.493671 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9794 12:38:37.500026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9795 12:38:37.503893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9796 12:38:37.507196 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9797 12:38:37.513705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9798 12:38:37.516515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9799 12:38:37.523878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9800 12:38:37.526935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9801 12:38:37.529966 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9802 12:38:37.536651 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9803 12:38:37.540004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9804 12:38:37.546693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9805 12:38:37.550006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9806 12:38:37.556533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9807 12:38:37.559977 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9808 12:38:37.563423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9809 12:38:37.570004 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9810 12:38:37.573319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9811 12:38:37.579791 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9812 12:38:37.583480 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9813 12:38:37.589652 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9814 12:38:37.593138 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9815 12:38:37.596495 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9816 12:38:37.603091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9817 12:38:37.606413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9818 12:38:37.612925 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9819 12:38:37.616538 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9820 12:38:37.623169 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9821 12:38:37.626562 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9822 12:38:37.632975 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9823 12:38:37.636457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9824 12:38:37.639599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9825 12:38:37.646482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9826 12:38:37.649696 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9827 12:38:37.656325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9828 12:38:37.659322 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9829 12:38:37.666405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9830 12:38:37.669284 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9831 12:38:37.672991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9832 12:38:37.679658 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9833 12:38:37.682800 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9834 12:38:37.689293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9835 12:38:37.692816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9836 12:38:37.699444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9837 12:38:37.702574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9838 12:38:37.709459 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9839 12:38:37.712813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9840 12:38:37.716074 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9841 12:38:37.722594 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9842 12:38:37.726205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9843 12:38:37.732709 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9844 12:38:37.736178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9845 12:38:37.742535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9846 12:38:37.746157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9847 12:38:37.749333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9848 12:38:37.755734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9849 12:38:37.758927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9850 12:38:37.762504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9851 12:38:37.769132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9852 12:38:37.772841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9853 12:38:37.779796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9854 12:38:37.782941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9855 12:38:37.789291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9856 12:38:37.792649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9857 12:38:37.799327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9858 12:38:37.802685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9859 12:38:37.809401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9860 12:38:37.812229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9861 12:38:37.819421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9862 12:38:37.822153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9863 12:38:37.829045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9864 12:38:37.831840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9865 12:38:37.838856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9866 12:38:37.842465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9867 12:38:37.848915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9868 12:38:37.852124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9869 12:38:37.859043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9870 12:38:37.862579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9871 12:38:37.868877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9872 12:38:37.872260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9873 12:38:37.878809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9874 12:38:37.882380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9875 12:38:37.888563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9876 12:38:37.891951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9877 12:38:37.898788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9878 12:38:37.902401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9879 12:38:37.908803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9880 12:38:37.911896 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9881 12:38:37.915759 INFO: [APUAPC] vio 0
9882 12:38:37.918569 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9883 12:38:37.921913 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9884 12:38:37.925501 INFO: [APUAPC] D0_APC_0: 0x400510
9885 12:38:37.928674 INFO: [APUAPC] D0_APC_1: 0x0
9886 12:38:37.931944 INFO: [APUAPC] D0_APC_2: 0x1540
9887 12:38:37.935343 INFO: [APUAPC] D0_APC_3: 0x0
9888 12:38:37.938616 INFO: [APUAPC] D1_APC_0: 0xffffffff
9889 12:38:37.942167 INFO: [APUAPC] D1_APC_1: 0xffffffff
9890 12:38:37.945635 INFO: [APUAPC] D1_APC_2: 0x3fffff
9891 12:38:37.948260 INFO: [APUAPC] D1_APC_3: 0x0
9892 12:38:37.952156 INFO: [APUAPC] D2_APC_0: 0xffffffff
9893 12:38:37.955173 INFO: [APUAPC] D2_APC_1: 0xffffffff
9894 12:38:37.958475 INFO: [APUAPC] D2_APC_2: 0x3fffff
9895 12:38:37.961665 INFO: [APUAPC] D2_APC_3: 0x0
9896 12:38:37.965034 INFO: [APUAPC] D3_APC_0: 0xffffffff
9897 12:38:37.968066 INFO: [APUAPC] D3_APC_1: 0xffffffff
9898 12:38:37.971698 INFO: [APUAPC] D3_APC_2: 0x3fffff
9899 12:38:37.974981 INFO: [APUAPC] D3_APC_3: 0x0
9900 12:38:37.978217 INFO: [APUAPC] D4_APC_0: 0xffffffff
9901 12:38:37.981489 INFO: [APUAPC] D4_APC_1: 0xffffffff
9902 12:38:37.984704 INFO: [APUAPC] D4_APC_2: 0x3fffff
9903 12:38:37.987842 INFO: [APUAPC] D4_APC_3: 0x0
9904 12:38:37.991245 INFO: [APUAPC] D5_APC_0: 0xffffffff
9905 12:38:37.994606 INFO: [APUAPC] D5_APC_1: 0xffffffff
9906 12:38:37.998276 INFO: [APUAPC] D5_APC_2: 0x3fffff
9907 12:38:38.001525 INFO: [APUAPC] D5_APC_3: 0x0
9908 12:38:38.004975 INFO: [APUAPC] D6_APC_0: 0xffffffff
9909 12:38:38.008261 INFO: [APUAPC] D6_APC_1: 0xffffffff
9910 12:38:38.011513 INFO: [APUAPC] D6_APC_2: 0x3fffff
9911 12:38:38.014781 INFO: [APUAPC] D6_APC_3: 0x0
9912 12:38:38.018131 INFO: [APUAPC] D7_APC_0: 0xffffffff
9913 12:38:38.021817 INFO: [APUAPC] D7_APC_1: 0xffffffff
9914 12:38:38.025120 INFO: [APUAPC] D7_APC_2: 0x3fffff
9915 12:38:38.028472 INFO: [APUAPC] D7_APC_3: 0x0
9916 12:38:38.031686 INFO: [APUAPC] D8_APC_0: 0xffffffff
9917 12:38:38.034626 INFO: [APUAPC] D8_APC_1: 0xffffffff
9918 12:38:38.038332 INFO: [APUAPC] D8_APC_2: 0x3fffff
9919 12:38:38.038946 INFO: [APUAPC] D8_APC_3: 0x0
9920 12:38:38.044831 INFO: [APUAPC] D9_APC_0: 0xffffffff
9921 12:38:38.048388 INFO: [APUAPC] D9_APC_1: 0xffffffff
9922 12:38:38.051526 INFO: [APUAPC] D9_APC_2: 0x3fffff
9923 12:38:38.052094 INFO: [APUAPC] D9_APC_3: 0x0
9924 12:38:38.054908 INFO: [APUAPC] D10_APC_0: 0xffffffff
9925 12:38:38.061656 INFO: [APUAPC] D10_APC_1: 0xffffffff
9926 12:38:38.065032 INFO: [APUAPC] D10_APC_2: 0x3fffff
9927 12:38:38.065617 INFO: [APUAPC] D10_APC_3: 0x0
9928 12:38:38.071332 INFO: [APUAPC] D11_APC_0: 0xffffffff
9929 12:38:38.074967 INFO: [APUAPC] D11_APC_1: 0xffffffff
9930 12:38:38.078044 INFO: [APUAPC] D11_APC_2: 0x3fffff
9931 12:38:38.078529 INFO: [APUAPC] D11_APC_3: 0x0
9932 12:38:38.084645 INFO: [APUAPC] D12_APC_0: 0xffffffff
9933 12:38:38.088147 INFO: [APUAPC] D12_APC_1: 0xffffffff
9934 12:38:38.091309 INFO: [APUAPC] D12_APC_2: 0x3fffff
9935 12:38:38.091780 INFO: [APUAPC] D12_APC_3: 0x0
9936 12:38:38.098017 INFO: [APUAPC] D13_APC_0: 0xffffffff
9937 12:38:38.101321 INFO: [APUAPC] D13_APC_1: 0xffffffff
9938 12:38:38.104606 INFO: [APUAPC] D13_APC_2: 0x3fffff
9939 12:38:38.105181 INFO: [APUAPC] D13_APC_3: 0x0
9940 12:38:38.111239 INFO: [APUAPC] D14_APC_0: 0xffffffff
9941 12:38:38.114474 INFO: [APUAPC] D14_APC_1: 0xffffffff
9942 12:38:38.118080 INFO: [APUAPC] D14_APC_2: 0x3fffff
9943 12:38:38.118659 INFO: [APUAPC] D14_APC_3: 0x0
9944 12:38:38.125092 INFO: [APUAPC] D15_APC_0: 0xffffffff
9945 12:38:38.128240 INFO: [APUAPC] D15_APC_1: 0xffffffff
9946 12:38:38.131130 INFO: [APUAPC] D15_APC_2: 0x3fffff
9947 12:38:38.131623 INFO: [APUAPC] D15_APC_3: 0x0
9948 12:38:38.134599 INFO: [APUAPC] APC_CON: 0x4
9949 12:38:38.137855 INFO: [NOCDAPC] D0_APC_0: 0x0
9950 12:38:38.141163 INFO: [NOCDAPC] D0_APC_1: 0x0
9951 12:38:38.144654 INFO: [NOCDAPC] D1_APC_0: 0x0
9952 12:38:38.147706 INFO: [NOCDAPC] D1_APC_1: 0xfff
9953 12:38:38.151262 INFO: [NOCDAPC] D2_APC_0: 0x0
9954 12:38:38.154228 INFO: [NOCDAPC] D2_APC_1: 0xfff
9955 12:38:38.157605 INFO: [NOCDAPC] D3_APC_0: 0x0
9956 12:38:38.161518 INFO: [NOCDAPC] D3_APC_1: 0xfff
9957 12:38:38.162136 INFO: [NOCDAPC] D4_APC_0: 0x0
9958 12:38:38.164818 INFO: [NOCDAPC] D4_APC_1: 0xfff
9959 12:38:38.167936 INFO: [NOCDAPC] D5_APC_0: 0x0
9960 12:38:38.171253 INFO: [NOCDAPC] D5_APC_1: 0xfff
9961 12:38:38.174664 INFO: [NOCDAPC] D6_APC_0: 0x0
9962 12:38:38.178063 INFO: [NOCDAPC] D6_APC_1: 0xfff
9963 12:38:38.181249 INFO: [NOCDAPC] D7_APC_0: 0x0
9964 12:38:38.184630 INFO: [NOCDAPC] D7_APC_1: 0xfff
9965 12:38:38.187749 INFO: [NOCDAPC] D8_APC_0: 0x0
9966 12:38:38.191057 INFO: [NOCDAPC] D8_APC_1: 0xfff
9967 12:38:38.191568 INFO: [NOCDAPC] D9_APC_0: 0x0
9968 12:38:38.194508 INFO: [NOCDAPC] D9_APC_1: 0xfff
9969 12:38:38.197611 INFO: [NOCDAPC] D10_APC_0: 0x0
9970 12:38:38.201233 INFO: [NOCDAPC] D10_APC_1: 0xfff
9971 12:38:38.204719 INFO: [NOCDAPC] D11_APC_0: 0x0
9972 12:38:38.207426 INFO: [NOCDAPC] D11_APC_1: 0xfff
9973 12:38:38.211195 INFO: [NOCDAPC] D12_APC_0: 0x0
9974 12:38:38.214403 INFO: [NOCDAPC] D12_APC_1: 0xfff
9975 12:38:38.218044 INFO: [NOCDAPC] D13_APC_0: 0x0
9976 12:38:38.220627 INFO: [NOCDAPC] D13_APC_1: 0xfff
9977 12:38:38.224045 INFO: [NOCDAPC] D14_APC_0: 0x0
9978 12:38:38.227967 INFO: [NOCDAPC] D14_APC_1: 0xfff
9979 12:38:38.231197 INFO: [NOCDAPC] D15_APC_0: 0x0
9980 12:38:38.234004 INFO: [NOCDAPC] D15_APC_1: 0xfff
9981 12:38:38.234475 INFO: [NOCDAPC] APC_CON: 0x4
9982 12:38:38.237415 INFO: [APUAPC] set_apusys_apc done
9983 12:38:38.240822 INFO: [DEVAPC] devapc_init done
9984 12:38:38.247826 INFO: GICv3 without legacy support detected.
9985 12:38:38.250792 INFO: ARM GICv3 driver initialized in EL3
9986 12:38:38.254126 INFO: Maximum SPI INTID supported: 639
9987 12:38:38.257466 INFO: BL31: Initializing runtime services
9988 12:38:38.264616 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9989 12:38:38.267503 INFO: SPM: enable CPC mode
9990 12:38:38.271045 INFO: mcdi ready for mcusys-off-idle and system suspend
9991 12:38:38.277341 INFO: BL31: Preparing for EL3 exit to normal world
9992 12:38:38.280856 INFO: Entry point address = 0x80000000
9993 12:38:38.281430 INFO: SPSR = 0x8
9994 12:38:38.288502
9995 12:38:38.289106
9996 12:38:38.289494
9997 12:38:38.291105 Starting depthcharge on Spherion...
9998 12:38:38.291623
9999 12:38:38.291999 Wipe memory regions:
10000 12:38:38.292372
10001 12:38:38.294882 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10002 12:38:38.295439 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10003 12:38:38.295884 Setting prompt string to ['asurada:']
10004 12:38:38.296310 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10005 12:38:38.297288 [0x00000040000000, 0x00000054600000)
10006 12:38:38.416956
10007 12:38:38.417529 [0x00000054660000, 0x00000080000000)
10008 12:38:38.677144
10009 12:38:38.677379 [0x000000821a7280, 0x000000ffe64000)
10010 12:38:39.421911
10011 12:38:39.422525 [0x00000100000000, 0x00000240000000)
10012 12:38:41.311800
10013 12:38:41.314933 Initializing XHCI USB controller at 0x11200000.
10014 12:38:42.353210
10015 12:38:42.356001 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10016 12:38:42.356445
10017 12:38:42.356780
10018 12:38:42.357090
10019 12:38:42.357822 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 12:38:42.458966 asurada: tftpboot 192.168.201.1 12703509/tftp-deploy-5m3tmryu/kernel/image.itb 12703509/tftp-deploy-5m3tmryu/kernel/cmdline
10022 12:38:42.459484 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 12:38:42.459896 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10024 12:38:42.464400 tftpboot 192.168.201.1 12703509/tftp-deploy-5m3tmryu/kernel/image.itp-deploy-5m3tmryu/kernel/cmdline
10025 12:38:42.464831
10026 12:38:42.465163 Waiting for link
10027 12:38:42.621921
10028 12:38:42.622068 R8152: Initializing
10029 12:38:42.622140
10030 12:38:42.625302 Version 9 (ocp_data = 6010)
10031 12:38:42.625386
10032 12:38:42.628943 R8152: Done initializing
10033 12:38:42.629027
10034 12:38:42.629094 Adding net device
10035 12:38:44.573679
10036 12:38:44.573826 done.
10037 12:38:44.573894
10038 12:38:44.573962 MAC: 00:e0:4c:72:2d:d6
10039 12:38:44.574024
10040 12:38:44.576946 Sending DHCP discover... done.
10041 12:38:44.577030
10042 12:38:44.580322 Waiting for reply... done.
10043 12:38:44.580406
10044 12:38:44.583810 Sending DHCP request... done.
10045 12:38:44.583893
10046 12:38:44.583959 Waiting for reply... done.
10047 12:38:44.584020
10048 12:38:44.586887 My ip is 192.168.201.21
10049 12:38:44.586971
10050 12:38:44.590198 The DHCP server ip is 192.168.201.1
10051 12:38:44.590282
10052 12:38:44.593740 TFTP server IP predefined by user: 192.168.201.1
10053 12:38:44.593825
10054 12:38:44.600365 Bootfile predefined by user: 12703509/tftp-deploy-5m3tmryu/kernel/image.itb
10055 12:38:44.600449
10056 12:38:44.603620 Sending tftp read request... done.
10057 12:38:44.603703
10058 12:38:44.606639 Waiting for the transfer...
10059 12:38:44.606723
10060 12:38:44.868835 00000000 ################################################################
10061 12:38:44.868972
10062 12:38:45.127331 00080000 ################################################################
10063 12:38:45.127506
10064 12:38:45.390178 00100000 ################################################################
10065 12:38:45.390329
10066 12:38:45.656751 00180000 ################################################################
10067 12:38:45.656878
10068 12:38:45.928154 00200000 ################################################################
10069 12:38:45.928309
10070 12:38:46.195047 00280000 ################################################################
10071 12:38:46.195174
10072 12:38:46.450367 00300000 ################################################################
10073 12:38:46.450493
10074 12:38:46.720509 00380000 ################################################################
10075 12:38:46.720668
10076 12:38:46.990929 00400000 ################################################################
10077 12:38:46.991062
10078 12:38:47.261122 00480000 ################################################################
10079 12:38:47.261290
10080 12:38:47.532047 00500000 ################################################################
10081 12:38:47.532182
10082 12:38:47.803349 00580000 ################################################################
10083 12:38:47.803487
10084 12:38:48.075404 00600000 ################################################################
10085 12:38:48.075537
10086 12:38:48.339384 00680000 ################################################################
10087 12:38:48.339524
10088 12:38:48.600890 00700000 ################################################################
10089 12:38:48.601023
10090 12:38:48.862278 00780000 ################################################################
10091 12:38:48.862417
10092 12:38:49.118266 00800000 ################################################################
10093 12:38:49.118398
10094 12:38:49.386458 00880000 ################################################################
10095 12:38:49.386634
10096 12:38:49.643275 00900000 ################################################################
10097 12:38:49.643431
10098 12:38:49.899621 00980000 ################################################################
10099 12:38:49.899781
10100 12:38:50.157422 00a00000 ################################################################
10101 12:38:50.157577
10102 12:38:50.416282 00a80000 ################################################################
10103 12:38:50.416452
10104 12:38:50.675599 00b00000 ################################################################
10105 12:38:50.675759
10106 12:38:50.937773 00b80000 ################################################################
10107 12:38:50.937931
10108 12:38:51.201703 00c00000 ################################################################
10109 12:38:51.201843
10110 12:38:51.461177 00c80000 ################################################################
10111 12:38:51.461371
10112 12:38:51.718018 00d00000 ################################################################
10113 12:38:51.718190
10114 12:38:51.974473 00d80000 ################################################################
10115 12:38:51.974607
10116 12:38:52.230122 00e00000 ################################################################
10117 12:38:52.230256
10118 12:38:52.491447 00e80000 ################################################################
10119 12:38:52.491585
10120 12:38:52.763220 00f00000 ################################################################
10121 12:38:52.763367
10122 12:38:53.028450 00f80000 ################################################################
10123 12:38:53.028588
10124 12:38:53.314808 01000000 ################################################################
10125 12:38:53.314945
10126 12:38:53.591041 01080000 ################################################################
10127 12:38:53.591182
10128 12:38:53.884293 01100000 ################################################################
10129 12:38:53.884436
10130 12:38:54.165833 01180000 ################################################################
10131 12:38:54.166020
10132 12:38:54.435057 01200000 ################################################################
10133 12:38:54.435242
10134 12:38:54.699596 01280000 ################################################################
10135 12:38:54.699743
10136 12:38:54.961896 01300000 ################################################################
10137 12:38:54.962076
10138 12:38:55.234040 01380000 ################################################################
10139 12:38:55.234189
10140 12:38:55.498372 01400000 ################################################################
10141 12:38:55.498532
10142 12:38:55.757009 01480000 ################################################################
10143 12:38:55.757151
10144 12:38:56.013522 01500000 ################################################################
10145 12:38:56.013684
10146 12:38:56.276147 01580000 ################################################################
10147 12:38:56.276277
10148 12:38:56.539406 01600000 ################################################################
10149 12:38:56.539546
10150 12:38:56.804626 01680000 ################################################################
10151 12:38:56.804764
10152 12:38:57.056564 01700000 ################################################################
10153 12:38:57.056728
10154 12:38:57.306288 01780000 ################################################################
10155 12:38:57.306442
10156 12:38:57.561789 01800000 ################################################################
10157 12:38:57.562007
10158 12:38:57.838491 01880000 ################################################################
10159 12:38:57.838633
10160 12:38:58.107186 01900000 ################################################################
10161 12:38:58.107325
10162 12:38:58.384557 01980000 ################################################################
10163 12:38:58.384738
10164 12:38:58.644798 01a00000 ################################################################
10165 12:38:58.644942
10166 12:38:58.909912 01a80000 ################################################################
10167 12:38:58.910087
10168 12:38:59.183453 01b00000 ################################################################
10169 12:38:59.183589
10170 12:38:59.438813 01b80000 ################################################################
10171 12:38:59.438952
10172 12:38:59.699518 01c00000 ################################################################
10173 12:38:59.699654
10174 12:38:59.958052 01c80000 ################################################################
10175 12:38:59.958184
10176 12:39:00.248674 01d00000 ################################################################
10177 12:39:00.248814
10178 12:39:00.530097 01d80000 ################################################################
10179 12:39:00.530329
10180 12:39:00.804606 01e00000 ################################################################
10181 12:39:00.804746
10182 12:39:01.058200 01e80000 ################################################################
10183 12:39:01.058337
10184 12:39:01.350708 01f00000 ################################################################
10185 12:39:01.350847
10186 12:39:01.604966 01f80000 ################################################################
10187 12:39:01.605103
10188 12:39:01.897249 02000000 ################################################################
10189 12:39:01.897386
10190 12:39:02.194335 02080000 ################################################################
10191 12:39:02.194475
10192 12:39:02.489234 02100000 ################################################################
10193 12:39:02.489377
10194 12:39:02.754098 02180000 ################################################################
10195 12:39:02.754243
10196 12:39:03.041061 02200000 ################################################################
10197 12:39:03.041207
10198 12:39:03.328142 02280000 ################################################################
10199 12:39:03.328280
10200 12:39:03.625070 02300000 ################################################################
10201 12:39:03.625208
10202 12:39:03.883206 02380000 ################################################################
10203 12:39:03.883339
10204 12:39:04.134782 02400000 ################################################################
10205 12:39:04.134940
10206 12:39:04.396864 02480000 ################################################################
10207 12:39:04.396991
10208 12:39:04.646956 02500000 ################################################################
10209 12:39:04.647115
10210 12:39:04.904323 02580000 ################################################################
10211 12:39:04.904489
10212 12:39:05.159778 02600000 ################################################################
10213 12:39:05.159934
10214 12:39:05.413217 02680000 ################################################################
10215 12:39:05.413354
10216 12:39:05.676870 02700000 ################################################################
10217 12:39:05.677010
10218 12:39:05.954187 02780000 ################################################################
10219 12:39:05.954324
10220 12:39:06.254071 02800000 ################################################################
10221 12:39:06.254202
10222 12:39:06.514833 02880000 ################################################################
10223 12:39:06.514988
10224 12:39:06.774101 02900000 ################################################################
10225 12:39:06.774234
10226 12:39:07.041080 02980000 ################################################################
10227 12:39:07.041213
10228 12:39:07.296362 02a00000 ################################################################
10229 12:39:07.296517
10230 12:39:07.545374 02a80000 ################################################################
10231 12:39:07.545498
10232 12:39:07.798723 02b00000 ################################################################
10233 12:39:07.798852
10234 12:39:08.086863 02b80000 ################################################################
10235 12:39:08.087018
10236 12:39:08.382986 02c00000 ################################################################
10237 12:39:08.383118
10238 12:39:08.683617 02c80000 ################################################################
10239 12:39:08.683748
10240 12:39:08.982095 02d00000 ################################################################
10241 12:39:08.982237
10242 12:39:09.281346 02d80000 ################################################################
10243 12:39:09.281480
10244 12:39:09.582034 02e00000 ################################################################
10245 12:39:09.582169
10246 12:39:09.834242 02e80000 ################################################################
10247 12:39:09.834380
10248 12:39:10.130754 02f00000 ################################################################
10249 12:39:10.130886
10250 12:39:10.427176 02f80000 ################################################################
10251 12:39:10.427310
10252 12:39:10.723382 03000000 ################################################################
10253 12:39:10.723513
10254 12:39:11.009966 03080000 ################################################################
10255 12:39:11.010100
10256 12:39:11.066126 03100000 ############ done.
10257 12:39:11.066221
10258 12:39:11.069243 The bootfile was 51477526 bytes long.
10259 12:39:11.069335
10260 12:39:11.072902 Sending tftp read request... done.
10261 12:39:11.073078
10262 12:39:11.073178 Waiting for the transfer...
10263 12:39:11.073281
10264 12:39:11.076048 00000000 # done.
10265 12:39:11.076160
10266 12:39:11.083044 Command line loaded dynamically from TFTP file: 12703509/tftp-deploy-5m3tmryu/kernel/cmdline
10267 12:39:11.083150
10268 12:39:11.096467 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10269 12:39:11.096693
10270 12:39:11.099810 Loading FIT.
10271 12:39:11.100051
10272 12:39:11.103017 Image ramdisk-1 has 39375356 bytes.
10273 12:39:11.103271
10274 12:39:11.103424 Image fdt-1 has 47278 bytes.
10275 12:39:11.103562
10276 12:39:11.106114 Image kernel-1 has 12052857 bytes.
10277 12:39:11.106293
10278 12:39:11.116299 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10279 12:39:11.116547
10280 12:39:11.133184 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10281 12:39:11.133776
10282 12:39:11.139909 Choosing best match conf-1 for compat google,spherion-rev2.
10283 12:39:11.143641
10284 12:39:11.148711 Connected to device vid:did:rid of 1ae0:0028:00
10285 12:39:11.155647
10286 12:39:11.158405 tpm_get_response: command 0x17b, return code 0x0
10287 12:39:11.158883
10288 12:39:11.161598 ec_init: CrosEC protocol v3 supported (256, 248)
10289 12:39:11.166078
10290 12:39:11.169362 tpm_cleanup: add release locality here.
10291 12:39:11.169937
10292 12:39:11.170377 Shutting down all USB controllers.
10293 12:39:11.172358
10294 12:39:11.172831 Removing current net device
10295 12:39:11.173210
10296 12:39:11.179124 Exiting depthcharge with code 4 at timestamp: 62127020
10297 12:39:11.179596
10298 12:39:11.182698 LZMA decompressing kernel-1 to 0x821a6718
10299 12:39:11.183172
10300 12:39:11.185468 LZMA decompressing kernel-1 to 0x40000000
10301 12:39:12.685689
10302 12:39:12.686308 jumping to kernel
10303 12:39:12.688369 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10304 12:39:12.688903 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10305 12:39:12.689310 Setting prompt string to ['Linux version [0-9]']
10306 12:39:12.689688 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10307 12:39:12.690118 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10308 12:39:12.768793
10309 12:39:12.772321 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10310 12:39:12.775995 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10311 12:39:12.776505 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10312 12:39:12.776909 Setting prompt string to []
10313 12:39:12.777330 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10314 12:39:12.777734 Using line separator: #'\n'#
10315 12:39:12.778131 No login prompt set.
10316 12:39:12.778562 Parsing kernel messages
10317 12:39:12.778912 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10318 12:39:12.779501 [login-action] Waiting for messages, (timeout 00:03:51)
10319 12:39:12.779881 Waiting using forced prompt support (timeout 00:01:55)
10320 12:39:12.795730 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10321 12:39:12.798836 [ 0.000000] random: crng init done
10322 12:39:12.805451 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10323 12:39:12.806074 [ 0.000000] efi: UEFI not found.
10324 12:39:12.815477 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10325 12:39:12.822210 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10326 12:39:12.832145 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10327 12:39:12.841729 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10328 12:39:12.848855 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10329 12:39:12.851584 [ 0.000000] printk: bootconsole [mtk8250] enabled
10330 12:39:12.860603 [ 0.000000] NUMA: No NUMA configuration found
10331 12:39:12.867152 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10332 12:39:12.873976 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10333 12:39:12.874454 [ 0.000000] Zone ranges:
10334 12:39:12.880697 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10335 12:39:12.884038 [ 0.000000] DMA32 empty
10336 12:39:12.890544 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10337 12:39:12.894018 [ 0.000000] Movable zone start for each node
10338 12:39:12.897307 [ 0.000000] Early memory node ranges
10339 12:39:12.903917 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10340 12:39:12.910415 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10341 12:39:12.917279 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10342 12:39:12.924054 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10343 12:39:12.930441 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10344 12:39:12.937308 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10345 12:39:12.992592 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10346 12:39:12.999141 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10347 12:39:13.005714 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10348 12:39:13.009110 [ 0.000000] psci: probing for conduit method from DT.
10349 12:39:13.015819 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10350 12:39:13.019216 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10351 12:39:13.025867 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10352 12:39:13.029110 [ 0.000000] psci: SMC Calling Convention v1.2
10353 12:39:13.035645 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10354 12:39:13.039200 [ 0.000000] Detected VIPT I-cache on CPU0
10355 12:39:13.045591 [ 0.000000] CPU features: detected: GIC system register CPU interface
10356 12:39:13.052562 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10357 12:39:13.058547 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10358 12:39:13.065112 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10359 12:39:13.075146 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10360 12:39:13.081522 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10361 12:39:13.085061 [ 0.000000] alternatives: applying boot alternatives
10362 12:39:13.091428 [ 0.000000] Fallback order for Node 0: 0
10363 12:39:13.098386 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10364 12:39:13.101616 [ 0.000000] Policy zone: Normal
10365 12:39:13.114809 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10366 12:39:13.124694 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10367 12:39:13.137025 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10368 12:39:13.146913 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10369 12:39:13.154051 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10370 12:39:13.156959 <6>[ 0.000000] software IO TLB: area num 8.
10371 12:39:13.213338 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10372 12:39:13.362151 <6>[ 0.000000] Memory: 7928800K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 423968K reserved, 32768K cma-reserved)
10373 12:39:13.368935 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10374 12:39:13.375490 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10375 12:39:13.378660 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10376 12:39:13.385590 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10377 12:39:13.391864 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10378 12:39:13.395147 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10379 12:39:13.405223 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10380 12:39:13.411755 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10381 12:39:13.414944 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10382 12:39:13.423181 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10383 12:39:13.426613 <6>[ 0.000000] GICv3: 608 SPIs implemented
10384 12:39:13.433375 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10385 12:39:13.436495 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10386 12:39:13.439821 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10387 12:39:13.449675 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10388 12:39:13.459511 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10389 12:39:13.473315 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10390 12:39:13.479319 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10391 12:39:13.488261 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10392 12:39:13.502100 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10393 12:39:13.508325 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10394 12:39:13.515043 <6>[ 0.009235] Console: colour dummy device 80x25
10395 12:39:13.524714 <6>[ 0.013989] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10396 12:39:13.531744 <6>[ 0.024496] pid_max: default: 32768 minimum: 301
10397 12:39:13.534899 <6>[ 0.029397] LSM: Security Framework initializing
10398 12:39:13.541889 <6>[ 0.034336] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 12:39:13.551775 <6>[ 0.042149] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 12:39:13.561669 <6>[ 0.051573] cblist_init_generic: Setting adjustable number of callback queues.
10401 12:39:13.565126 <6>[ 0.059063] cblist_init_generic: Setting shift to 3 and lim to 1.
10402 12:39:13.575178 <6>[ 0.065403] cblist_init_generic: Setting adjustable number of callback queues.
10403 12:39:13.581284 <6>[ 0.072830] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 12:39:13.584761 <6>[ 0.079230] rcu: Hierarchical SRCU implementation.
10405 12:39:13.591084 <6>[ 0.084245] rcu: Max phase no-delay instances is 1000.
10406 12:39:13.598044 <6>[ 0.091271] EFI services will not be available.
10407 12:39:13.601478 <6>[ 0.096226] smp: Bringing up secondary CPUs ...
10408 12:39:13.609781 <6>[ 0.101304] Detected VIPT I-cache on CPU1
10409 12:39:13.616191 <6>[ 0.101374] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10410 12:39:13.623093 <6>[ 0.101407] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10411 12:39:13.625865 <6>[ 0.101749] Detected VIPT I-cache on CPU2
10412 12:39:13.636135 <6>[ 0.101802] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10413 12:39:13.642552 <6>[ 0.101820] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10414 12:39:13.645978 <6>[ 0.102083] Detected VIPT I-cache on CPU3
10415 12:39:13.652419 <6>[ 0.102132] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10416 12:39:13.658917 <6>[ 0.102147] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10417 12:39:13.662563 <6>[ 0.102455] CPU features: detected: Spectre-v4
10418 12:39:13.669501 <6>[ 0.102461] CPU features: detected: Spectre-BHB
10419 12:39:13.672720 <6>[ 0.102467] Detected PIPT I-cache on CPU4
10420 12:39:13.679256 <6>[ 0.102526] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10421 12:39:13.685865 <6>[ 0.102544] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10422 12:39:13.692151 <6>[ 0.102837] Detected PIPT I-cache on CPU5
10423 12:39:13.699147 <6>[ 0.102899] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10424 12:39:13.705652 <6>[ 0.102916] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10425 12:39:13.709017 <6>[ 0.103199] Detected PIPT I-cache on CPU6
10426 12:39:13.715684 <6>[ 0.103262] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10427 12:39:13.721982 <6>[ 0.103279] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10428 12:39:13.728890 <6>[ 0.103580] Detected PIPT I-cache on CPU7
10429 12:39:13.735308 <6>[ 0.103645] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10430 12:39:13.742177 <6>[ 0.103661] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10431 12:39:13.745584 <6>[ 0.103709] smp: Brought up 1 node, 8 CPUs
10432 12:39:13.752130 <6>[ 0.245004] SMP: Total of 8 processors activated.
10433 12:39:13.755592 <6>[ 0.249925] CPU features: detected: 32-bit EL0 Support
10434 12:39:13.764956 <6>[ 0.255287] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10435 12:39:13.772236 <6>[ 0.264142] CPU features: detected: Common not Private translations
10436 12:39:13.775243 <6>[ 0.270617] CPU features: detected: CRC32 instructions
10437 12:39:13.781986 <6>[ 0.275968] CPU features: detected: RCpc load-acquire (LDAPR)
10438 12:39:13.788427 <6>[ 0.281928] CPU features: detected: LSE atomic instructions
10439 12:39:13.795260 <6>[ 0.287709] CPU features: detected: Privileged Access Never
10440 12:39:13.798526 <6>[ 0.293489] CPU features: detected: RAS Extension Support
10441 12:39:13.808498 <6>[ 0.299097] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10442 12:39:13.812197 <6>[ 0.306317] CPU: All CPU(s) started at EL2
10443 12:39:13.818370 <6>[ 0.310634] alternatives: applying system-wide alternatives
10444 12:39:13.827331 <6>[ 0.321361] devtmpfs: initialized
10445 12:39:13.839671 <6>[ 0.330309] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10446 12:39:13.849665 <6>[ 0.340264] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10447 12:39:13.855928 <6>[ 0.348460] pinctrl core: initialized pinctrl subsystem
10448 12:39:13.859275 <6>[ 0.355099] DMI not present or invalid.
10449 12:39:13.865926 <6>[ 0.359513] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10450 12:39:13.875899 <6>[ 0.366357] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10451 12:39:13.882437 <6>[ 0.373929] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10452 12:39:13.892333 <6>[ 0.382149] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10453 12:39:13.895639 <6>[ 0.390392] audit: initializing netlink subsys (disabled)
10454 12:39:13.905918 <5>[ 0.396087] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10455 12:39:13.912524 <6>[ 0.396786] thermal_sys: Registered thermal governor 'step_wise'
10456 12:39:13.919281 <6>[ 0.404056] thermal_sys: Registered thermal governor 'power_allocator'
10457 12:39:13.922375 <6>[ 0.410312] cpuidle: using governor menu
10458 12:39:13.928776 <6>[ 0.421273] NET: Registered PF_QIPCRTR protocol family
10459 12:39:13.935749 <6>[ 0.426744] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10460 12:39:13.938762 <6>[ 0.433845] ASID allocator initialised with 32768 entries
10461 12:39:13.946447 <6>[ 0.440413] Serial: AMBA PL011 UART driver
10462 12:39:13.954749 <4>[ 0.449210] Trying to register duplicate clock ID: 134
10463 12:39:14.011324 <6>[ 0.508955] KASLR enabled
10464 12:39:14.026326 <6>[ 0.516830] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10465 12:39:14.032983 <6>[ 0.523842] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10466 12:39:14.039261 <6>[ 0.530333] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10467 12:39:14.045705 <6>[ 0.537338] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10468 12:39:14.052514 <6>[ 0.543824] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10469 12:39:14.058979 <6>[ 0.550829] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10470 12:39:14.065903 <6>[ 0.557316] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10471 12:39:14.072546 <6>[ 0.564320] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10472 12:39:14.075586 <6>[ 0.571842] ACPI: Interpreter disabled.
10473 12:39:14.084143 <6>[ 0.578270] iommu: Default domain type: Translated
10474 12:39:14.090785 <6>[ 0.583384] iommu: DMA domain TLB invalidation policy: strict mode
10475 12:39:14.094014 <5>[ 0.590049] SCSI subsystem initialized
10476 12:39:14.100924 <6>[ 0.594210] usbcore: registered new interface driver usbfs
10477 12:39:14.107471 <6>[ 0.599944] usbcore: registered new interface driver hub
10478 12:39:14.110420 <6>[ 0.605495] usbcore: registered new device driver usb
10479 12:39:14.117669 <6>[ 0.611604] pps_core: LinuxPPS API ver. 1 registered
10480 12:39:14.127273 <6>[ 0.616798] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10481 12:39:14.130806 <6>[ 0.626147] PTP clock support registered
10482 12:39:14.134201 <6>[ 0.630391] EDAC MC: Ver: 3.0.0
10483 12:39:14.141364 <6>[ 0.635549] FPGA manager framework
10484 12:39:14.148081 <6>[ 0.639230] Advanced Linux Sound Architecture Driver Initialized.
10485 12:39:14.151509 <6>[ 0.646011] vgaarb: loaded
10486 12:39:14.157875 <6>[ 0.649158] clocksource: Switched to clocksource arch_sys_counter
10487 12:39:14.161336 <5>[ 0.655595] VFS: Disk quotas dquot_6.6.0
10488 12:39:14.167790 <6>[ 0.659778] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10489 12:39:14.171130 <6>[ 0.666973] pnp: PnP ACPI: disabled
10490 12:39:14.179323 <6>[ 0.673631] NET: Registered PF_INET protocol family
10491 12:39:14.189116 <6>[ 0.679223] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10492 12:39:14.200873 <6>[ 0.691545] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10493 12:39:14.210456 <6>[ 0.700360] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10494 12:39:14.217417 <6>[ 0.708329] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10495 12:39:14.224028 <6>[ 0.717026] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10496 12:39:14.236074 <6>[ 0.726743] TCP: Hash tables configured (established 65536 bind 65536)
10497 12:39:14.242716 <6>[ 0.733603] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 12:39:14.249474 <6>[ 0.740804] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10499 12:39:14.255486 <6>[ 0.748506] NET: Registered PF_UNIX/PF_LOCAL protocol family
10500 12:39:14.261904 <6>[ 0.754680] RPC: Registered named UNIX socket transport module.
10501 12:39:14.265191 <6>[ 0.760833] RPC: Registered udp transport module.
10502 12:39:14.272080 <6>[ 0.765767] RPC: Registered tcp transport module.
10503 12:39:14.278463 <6>[ 0.770698] RPC: Registered tcp NFSv4.1 backchannel transport module.
10504 12:39:14.281763 <6>[ 0.777367] PCI: CLS 0 bytes, default 64
10505 12:39:14.285279 <6>[ 0.781767] Unpacking initramfs...
10506 12:39:14.302629 <6>[ 0.793769] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10507 12:39:14.312963 <6>[ 0.802446] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10508 12:39:14.316013 <6>[ 0.811307] kvm [1]: IPA Size Limit: 40 bits
10509 12:39:14.323073 <6>[ 0.815837] kvm [1]: GICv3: no GICV resource entry
10510 12:39:14.326113 <6>[ 0.820859] kvm [1]: disabling GICv2 emulation
10511 12:39:14.332565 <6>[ 0.825546] kvm [1]: GIC system register CPU interface enabled
10512 12:39:14.336005 <6>[ 0.831719] kvm [1]: vgic interrupt IRQ18
10513 12:39:14.342737 <6>[ 0.836073] kvm [1]: VHE mode initialized successfully
10514 12:39:14.349183 <5>[ 0.842586] Initialise system trusted keyrings
10515 12:39:14.355614 <6>[ 0.847389] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10516 12:39:14.363371 <6>[ 0.857467] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10517 12:39:14.370068 <5>[ 0.863870] NFS: Registering the id_resolver key type
10518 12:39:14.372905 <5>[ 0.869175] Key type id_resolver registered
10519 12:39:14.379506 <5>[ 0.873591] Key type id_legacy registered
10520 12:39:14.386626 <6>[ 0.877875] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10521 12:39:14.392986 <6>[ 0.884793] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10522 12:39:14.399552 <6>[ 0.892516] 9p: Installing v9fs 9p2000 file system support
10523 12:39:14.435776 <5>[ 0.929668] Key type asymmetric registered
10524 12:39:14.439012 <5>[ 0.933998] Asymmetric key parser 'x509' registered
10525 12:39:14.448975 <6>[ 0.939137] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10526 12:39:14.451960 <6>[ 0.946749] io scheduler mq-deadline registered
10527 12:39:14.455575 <6>[ 0.951528] io scheduler kyber registered
10528 12:39:14.474502 <6>[ 0.968582] EINJ: ACPI disabled.
10529 12:39:14.506619 <4>[ 0.994264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 12:39:14.516867 <4>[ 1.004894] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 12:39:14.531453 <6>[ 1.025725] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10532 12:39:14.539593 <6>[ 1.033733] printk: console [ttyS0] disabled
10533 12:39:14.567230 <6>[ 1.058358] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10534 12:39:14.574160 <6>[ 1.067832] printk: console [ttyS0] enabled
10535 12:39:14.577483 <6>[ 1.067832] printk: console [ttyS0] enabled
10536 12:39:14.583883 <6>[ 1.076725] printk: bootconsole [mtk8250] disabled
10537 12:39:14.587292 <6>[ 1.076725] printk: bootconsole [mtk8250] disabled
10538 12:39:14.593925 <6>[ 1.087961] SuperH (H)SCI(F) driver initialized
10539 12:39:14.597068 <6>[ 1.093248] msm_serial: driver initialized
10540 12:39:14.611105 <6>[ 1.102297] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10541 12:39:14.621089 <6>[ 1.110844] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10542 12:39:14.627578 <6>[ 1.119387] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10543 12:39:14.637737 <6>[ 1.128015] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10544 12:39:14.647862 <6>[ 1.136726] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10545 12:39:14.654253 <6>[ 1.145448] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10546 12:39:14.664026 <6>[ 1.153991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10547 12:39:14.670999 <6>[ 1.162798] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10548 12:39:14.680572 <6>[ 1.171342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10549 12:39:14.693136 <6>[ 1.187155] loop: module loaded
10550 12:39:14.699296 <6>[ 1.193134] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10551 12:39:14.722116 <4>[ 1.216469] mtk-pmic-keys: Failed to locate of_node [id: -1]
10552 12:39:14.729309 <6>[ 1.223495] megasas: 07.719.03.00-rc1
10553 12:39:14.738717 <6>[ 1.233029] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10554 12:39:14.750563 <6>[ 1.244515] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10555 12:39:14.767067 <6>[ 1.261066] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10556 12:39:14.822990 <6>[ 1.310771] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10557 12:39:15.895475 <6>[ 2.390035] Freeing initrd memory: 38448K
10558 12:39:15.906457 <6>[ 2.400609] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10559 12:39:15.917060 <6>[ 2.411463] tun: Universal TUN/TAP device driver, 1.6
10560 12:39:15.920200 <6>[ 2.417529] thunder_xcv, ver 1.0
10561 12:39:15.923770 <6>[ 2.421024] thunder_bgx, ver 1.0
10562 12:39:15.926801 <6>[ 2.424519] nicpf, ver 1.0
10563 12:39:15.937232 <6>[ 2.428532] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10564 12:39:15.940705 <6>[ 2.436008] hns3: Copyright (c) 2017 Huawei Corporation.
10565 12:39:15.947026 <6>[ 2.441594] hclge is initializing
10566 12:39:15.950376 <6>[ 2.445169] e1000: Intel(R) PRO/1000 Network Driver
10567 12:39:15.957349 <6>[ 2.450297] e1000: Copyright (c) 1999-2006 Intel Corporation.
10568 12:39:15.960905 <6>[ 2.456310] e1000e: Intel(R) PRO/1000 Network Driver
10569 12:39:15.967250 <6>[ 2.461526] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10570 12:39:15.973675 <6>[ 2.467714] igb: Intel(R) Gigabit Ethernet Network Driver
10571 12:39:15.980465 <6>[ 2.473364] igb: Copyright (c) 2007-2014 Intel Corporation.
10572 12:39:15.987262 <6>[ 2.479200] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10573 12:39:15.993421 <6>[ 2.485717] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10574 12:39:15.996857 <6>[ 2.492176] sky2: driver version 1.30
10575 12:39:16.003637 <6>[ 2.497163] VFIO - User Level meta-driver version: 0.3
10576 12:39:16.010868 <6>[ 2.505381] usbcore: registered new interface driver usb-storage
10577 12:39:16.017309 <6>[ 2.511823] usbcore: registered new device driver onboard-usb-hub
10578 12:39:16.026716 <6>[ 2.520965] mt6397-rtc mt6359-rtc: registered as rtc0
10579 12:39:16.036378 <6>[ 2.526464] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:38:40 UTC (1707136720)
10580 12:39:16.039697 <6>[ 2.536081] i2c_dev: i2c /dev entries driver
10581 12:39:16.057054 <6>[ 2.547872] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10582 12:39:16.076607 <6>[ 2.570868] cpu cpu0: EM: created perf domain
10583 12:39:16.079767 <6>[ 2.575798] cpu cpu4: EM: created perf domain
10584 12:39:16.086855 <6>[ 2.581365] sdhci: Secure Digital Host Controller Interface driver
10585 12:39:16.093803 <6>[ 2.587797] sdhci: Copyright(c) Pierre Ossman
10586 12:39:16.100211 <6>[ 2.592769] Synopsys Designware Multimedia Card Interface Driver
10587 12:39:16.106483 <6>[ 2.599409] sdhci-pltfm: SDHCI platform and OF driver helper
10588 12:39:16.110061 <6>[ 2.599532] mmc0: CQHCI version 5.10
10589 12:39:16.116578 <6>[ 2.609414] ledtrig-cpu: registered to indicate activity on CPUs
10590 12:39:16.123318 <6>[ 2.616356] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10591 12:39:16.129811 <6>[ 2.623403] usbcore: registered new interface driver usbhid
10592 12:39:16.133290 <6>[ 2.629225] usbhid: USB HID core driver
10593 12:39:16.139546 <6>[ 2.633417] spi_master spi0: will run message pump with realtime priority
10594 12:39:16.181700 <6>[ 2.669275] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10595 12:39:16.200071 <6>[ 2.684360] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10596 12:39:16.206830 <6>[ 2.699878] cros-ec-spi spi0.0: Chrome EC device registered
10597 12:39:16.210502 <6>[ 2.705927] mmc0: Command Queue Engine enabled
10598 12:39:16.216870 <6>[ 2.710675] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10599 12:39:16.223980 <6>[ 2.718367] mmcblk0: mmc0:0001 DA4128 116 GiB
10600 12:39:16.232408 <6>[ 2.726856] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10601 12:39:16.239610 <6>[ 2.734159] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10602 12:39:16.246339 <6>[ 2.740266] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10603 12:39:16.256489 <6>[ 2.745243] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 12:39:16.262832 <6>[ 2.746173] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10605 12:39:16.266069 <6>[ 2.756072] NET: Registered PF_PACKET protocol family
10606 12:39:16.272836 <6>[ 2.766715] 9pnet: Installing 9P2000 support
10607 12:39:16.276412 <5>[ 2.771283] Key type dns_resolver registered
10608 12:39:16.282631 <6>[ 2.776286] registered taskstats version 1
10609 12:39:16.286151 <5>[ 2.780666] Loading compiled-in X.509 certificates
10610 12:39:16.316341 <4>[ 2.804198] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 12:39:16.326330 <4>[ 2.814988] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 12:39:16.333053 <3>[ 2.825596] debugfs: File 'uA_load' in directory '/' already present!
10613 12:39:16.339513 <3>[ 2.832323] debugfs: File 'min_uV' in directory '/' already present!
10614 12:39:16.346205 <3>[ 2.838936] debugfs: File 'max_uV' in directory '/' already present!
10615 12:39:16.352752 <3>[ 2.845546] debugfs: File 'constraint_flags' in directory '/' already present!
10616 12:39:16.364386 <3>[ 2.855354] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10617 12:39:16.378322 <6>[ 2.872970] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 12:39:16.385229 <6>[ 2.879841] xhci-mtk 11200000.usb: xHCI Host Controller
10619 12:39:16.392105 <6>[ 2.885366] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 12:39:16.401853 <6>[ 2.893293] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 12:39:16.408558 <6>[ 2.902737] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 12:39:16.415309 <6>[ 2.908839] xhci-mtk 11200000.usb: xHCI Host Controller
10623 12:39:16.421915 <6>[ 2.914327] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 12:39:16.428881 <6>[ 2.921983] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 12:39:16.435445 <6>[ 2.929922] hub 1-0:1.0: USB hub found
10626 12:39:16.438371 <6>[ 2.933959] hub 1-0:1.0: 1 port detected
10627 12:39:16.448609 <6>[ 2.938257] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10628 12:39:16.451841 <6>[ 2.947110] hub 2-0:1.0: USB hub found
10629 12:39:16.455182 <6>[ 2.951136] hub 2-0:1.0: 1 port detected
10630 12:39:16.464359 <6>[ 2.958876] mtk-msdc 11f70000.mmc: Got CD GPIO
10631 12:39:16.478229 <6>[ 2.969563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10632 12:39:16.484814 <6>[ 2.977593] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10633 12:39:16.494833 <4>[ 2.985517] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10634 12:39:16.505090 <6>[ 2.995095] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10635 12:39:16.511909 <6>[ 3.003173] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10636 12:39:16.518429 <6>[ 3.011187] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10637 12:39:16.527826 <6>[ 3.019109] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10638 12:39:16.534565 <6>[ 3.026927] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10639 12:39:16.544816 <6>[ 3.034745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10640 12:39:16.554348 <6>[ 3.045165] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10641 12:39:16.560988 <6>[ 3.053535] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10642 12:39:16.570881 <6>[ 3.061887] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10643 12:39:16.577705 <6>[ 3.070226] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10644 12:39:16.587780 <6>[ 3.078564] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10645 12:39:16.594084 <6>[ 3.086903] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10646 12:39:16.603865 <6>[ 3.095241] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10647 12:39:16.614319 <6>[ 3.103580] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10648 12:39:16.620440 <6>[ 3.111918] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10649 12:39:16.630298 <6>[ 3.120258] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10650 12:39:16.637123 <6>[ 3.128596] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10651 12:39:16.647200 <6>[ 3.136935] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10652 12:39:16.654081 <6>[ 3.145275] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10653 12:39:16.663472 <6>[ 3.153612] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10654 12:39:16.669994 <6>[ 3.161951] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10655 12:39:16.676600 <6>[ 3.170700] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10656 12:39:16.683272 <6>[ 3.177855] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10657 12:39:16.689971 <6>[ 3.184613] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10658 12:39:16.700150 <6>[ 3.191366] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10659 12:39:16.706760 <6>[ 3.198293] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10660 12:39:16.713902 <6>[ 3.205145] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10661 12:39:16.723139 <6>[ 3.214274] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10662 12:39:16.733476 <6>[ 3.223393] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10663 12:39:16.743088 <6>[ 3.232689] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10664 12:39:16.753009 <6>[ 3.242157] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10665 12:39:16.759671 <6>[ 3.251623] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10666 12:39:16.769729 <6>[ 3.260743] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10667 12:39:16.779672 <6>[ 3.270208] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10668 12:39:16.789775 <6>[ 3.279327] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10669 12:39:16.799589 <6>[ 3.288621] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10670 12:39:16.809229 <6>[ 3.298787] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10671 12:39:16.819029 <6>[ 3.310324] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10672 12:39:16.870094 <6>[ 3.361432] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 12:39:17.025236 <6>[ 3.519290] hub 1-1:1.0: USB hub found
10674 12:39:17.028091 <6>[ 3.523823] hub 1-1:1.0: 4 ports detected
10675 12:39:17.037565 <6>[ 3.532162] hub 1-1:1.0: USB hub found
10676 12:39:17.041086 <6>[ 3.536638] hub 1-1:1.0: 4 ports detected
10677 12:39:17.150670 <6>[ 3.641775] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10678 12:39:17.176921 <6>[ 3.671270] hub 2-1:1.0: USB hub found
10679 12:39:17.179901 <6>[ 3.675762] hub 2-1:1.0: 3 ports detected
10680 12:39:17.189627 <6>[ 3.683866] hub 2-1:1.0: USB hub found
10681 12:39:17.192944 <6>[ 3.688353] hub 2-1:1.0: 3 ports detected
10682 12:39:17.366194 <6>[ 3.857457] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10683 12:39:17.498339 <6>[ 3.992727] hub 1-1.4:1.0: USB hub found
10684 12:39:17.501318 <6>[ 3.997367] hub 1-1.4:1.0: 2 ports detected
10685 12:39:17.511058 <6>[ 4.005565] hub 1-1.4:1.0: USB hub found
10686 12:39:17.514282 <6>[ 4.010231] hub 1-1.4:1.0: 2 ports detected
10687 12:39:17.578159 <6>[ 4.069689] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10688 12:39:17.810565 <6>[ 4.301476] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 12:39:18.001894 <6>[ 4.493482] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 12:39:29.099208 <6>[ 15.598438] ALSA device list:
10691 12:39:29.105564 <6>[ 15.601730] No soundcards found.
10692 12:39:29.113865 <6>[ 15.609788] Freeing unused kernel memory: 8448K
10693 12:39:29.117267 <6>[ 15.614775] Run /init as init process
10694 12:39:29.162823 <6>[ 15.658790] NET: Registered PF_INET6 protocol family
10695 12:39:29.169648 <6>[ 15.664883] Segment Routing with IPv6
10696 12:39:29.172989 <6>[ 15.668844] In-situ OAM (IOAM) with IPv6
10697 12:39:29.207055 <30>[ 15.683177] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10698 12:39:29.210533 <30>[ 15.706963] systemd[1]: Detected architecture arm64.
10699 12:39:29.211007
10700 12:39:29.217085 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10701 12:39:29.217689
10702 12:39:29.229213 <30>[ 15.725521] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10703 12:39:29.365586 <30>[ 15.858217] systemd[1]: Queued start job for default target Graphical Interface.
10704 12:39:29.410479 <30>[ 15.906248] systemd[1]: Created slice system-getty.slice.
10705 12:39:29.416471 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10706 12:39:29.434250 <30>[ 15.930024] systemd[1]: Created slice system-modprobe.slice.
10707 12:39:29.440656 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10708 12:39:29.458349 <30>[ 15.954014] systemd[1]: Created slice system-serial\x2dgetty.slice.
10709 12:39:29.468320 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10710 12:39:29.482952 <30>[ 15.978699] systemd[1]: Created slice User and Session Slice.
10711 12:39:29.489345 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10712 12:39:29.508810 <30>[ 16.001683] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10713 12:39:29.515487 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10714 12:39:29.537756 <30>[ 16.030118] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10715 12:39:29.543810 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10716 12:39:29.568829 <30>[ 16.057986] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10717 12:39:29.575521 <30>[ 16.070302] systemd[1]: Reached target Local Encrypted Volumes.
10718 12:39:29.581813 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10719 12:39:29.598085 <30>[ 16.093979] systemd[1]: Reached target Paths.
10720 12:39:29.604531 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10721 12:39:29.617602 <30>[ 16.113525] systemd[1]: Reached target Remote File Systems.
10722 12:39:29.624170 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10723 12:39:29.641995 <30>[ 16.137814] systemd[1]: Reached target Slices.
10724 12:39:29.648631 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10725 12:39:29.661614 <30>[ 16.157460] systemd[1]: Reached target Swap.
10726 12:39:29.664897 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10727 12:39:29.685181 <30>[ 16.177960] systemd[1]: Listening on initctl Compatibility Named Pipe.
10728 12:39:29.692147 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10729 12:39:29.698633 <30>[ 16.193097] systemd[1]: Listening on Journal Audit Socket.
10730 12:39:29.705455 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10731 12:39:29.717823 <30>[ 16.213924] systemd[1]: Listening on Journal Socket (/dev/log).
10732 12:39:29.724560 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10733 12:39:29.742753 <30>[ 16.238681] systemd[1]: Listening on Journal Socket.
10734 12:39:29.749304 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10735 12:39:29.762048 <30>[ 16.258139] systemd[1]: Listening on Network Service Netlink Socket.
10736 12:39:29.772458 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10737 12:39:29.786808 <30>[ 16.282663] systemd[1]: Listening on udev Control Socket.
10738 12:39:29.793279 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10739 12:39:29.810751 <30>[ 16.306527] systemd[1]: Listening on udev Kernel Socket.
10740 12:39:29.817432 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10741 12:39:29.857645 <30>[ 16.353597] systemd[1]: Mounting Huge Pages File System...
10742 12:39:29.863902 Mounting [0;1;39mHuge Pages File System[0m...
10743 12:39:29.880225 <30>[ 16.375906] systemd[1]: Mounting POSIX Message Queue File System...
10744 12:39:29.886938 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10745 12:39:29.933564 <30>[ 16.429621] systemd[1]: Mounting Kernel Debug File System...
10746 12:39:29.940272 Mounting [0;1;39mKernel Debug File System[0m...
10747 12:39:29.956963 <30>[ 16.449669] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10748 12:39:29.968023 <30>[ 16.460640] systemd[1]: Starting Create list of static device nodes for the current kernel...
10749 12:39:29.974782 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10750 12:39:29.992196 <30>[ 16.488308] systemd[1]: Starting Load Kernel Module configfs...
10751 12:39:29.998827 Starting [0;1;39mLoad Kernel Module configfs[0m...
10752 12:39:30.017735 <30>[ 16.513861] systemd[1]: Starting Load Kernel Module drm...
10753 12:39:30.024336 Starting [0;1;39mLoad Kernel Module drm[0m...
10754 12:39:30.041119 <30>[ 16.533826] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10755 12:39:30.074269 <30>[ 16.570305] systemd[1]: Starting Journal Service...
10756 12:39:30.077574 Starting [0;1;39mJournal Service[0m...
10757 12:39:30.098155 <30>[ 16.594100] systemd[1]: Starting Load Kernel Modules...
10758 12:39:30.104882 Starting [0;1;39mLoad Kernel Modules[0m...
10759 12:39:30.126172 <30>[ 16.618541] systemd[1]: Starting Remount Root and Kernel File Systems...
10760 12:39:30.132272 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10761 12:39:30.150867 <30>[ 16.646838] systemd[1]: Starting Coldplug All udev Devices...
10762 12:39:30.157372 Starting [0;1;39mColdplug All udev Devices[0m...
10763 12:39:30.176147 <30>[ 16.672245] systemd[1]: Started Journal Service.
10764 12:39:30.182357 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10765 12:39:30.199657 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10766 12:39:30.218222 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10767 12:39:30.233651 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10768 12:39:30.254307 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10769 12:39:30.271662 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10770 12:39:30.291925 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10771 12:39:30.310731 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10772 12:39:30.331949 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10773 12:39:30.349728 See 'systemctl status systemd-remount-fs.service' for details.
10774 12:39:30.409974 Mounting [0;1;39mKernel Configuration File System[0m...
10775 12:39:30.430650 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10776 12:39:30.443844 <46>[ 16.936727] systemd-journald[177]: Received client request to flush runtime journal.
10777 12:39:30.454645 Starting [0;1;39mLoad/Save Random Seed[0m...
10778 12:39:30.474995 Starting [0;1;39mApply Kernel Variables[0m...
10779 12:39:30.495355 Starting [0;1;39mCreate System Users[0m...
10780 12:39:30.514545 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10781 12:39:30.530531 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10782 12:39:30.550420 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10783 12:39:30.563195 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10784 12:39:30.579200 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10785 12:39:30.595050 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10786 12:39:30.650283 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10787 12:39:30.670116 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10788 12:39:30.681746 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10789 12:39:30.701162 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10790 12:39:30.737764 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10791 12:39:30.761356 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10792 12:39:30.778431 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10793 12:39:30.788728 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10794 12:39:30.815368 Starting [0;1;39mNetwork Service[0m...
10795 12:39:30.839862 Starting [0;1;39mNetwork Time Synchronization[0m...
10796 12:39:30.858050 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10797 12:39:30.892426 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10798 12:39:30.911795 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10799 12:39:30.926449 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10800 12:39:30.944387 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10801 12:39:30.965628 [[0;32m OK [<6>[ 17.458855] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10802 12:39:30.972712 0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10803 12:39:30.993742 [[0;32m OK [0m] Reached targ<6>[ 17.488231] remoteproc remoteproc0: scp is available
10804 12:39:31.000774 et [0;1;39mSyst<6>[ 17.494975] remoteproc remoteproc0: powering up scp
10805 12:39:31.010302 em Time Set[0m.<6>[ 17.500885] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10806 12:39:31.010879
10807 12:39:31.016912 <6>[ 17.510697] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10808 12:39:31.023630 <3>[ 17.516725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 12:39:31.029860 <6>[ 17.524674] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10810 12:39:31.039777 <3>[ 17.524980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 12:39:31.046609 <6>[ 17.532504] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10812 12:39:31.056621 <3>[ 17.540502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 12:39:31.066223 <6>[ 17.549207] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10814 12:39:31.079673 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchron<3>[ 17.571404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 12:39:31.080228 ized[0m.
10816 12:39:31.089408 <3>[ 17.580169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 12:39:31.096003 <4>[ 17.586374] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10818 12:39:31.102715 <3>[ 17.589129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 12:39:31.109553 <6>[ 17.600588] mc: Linux media interface: v0.10
10820 12:39:31.115830 <4>[ 17.603822] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10821 12:39:31.122777 <3>[ 17.605302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 12:39:31.128669 <6>[ 17.618744] usbcore: registered new device driver r8152-cfgselector
10823 12:39:31.138848 <3>[ 17.624765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 12:39:31.145390 <3>[ 17.625776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 12:39:31.151720 <6>[ 17.626525] videodev: Linux video capture interface: v2.00
10826 12:39:31.158431 <6>[ 17.627298] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10827 12:39:31.168780 <6>[ 17.642105] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10828 12:39:31.175883 <6>[ 17.642121] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10829 12:39:31.182123 <3>[ 17.647599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 12:39:31.188671 <6>[ 17.653261] remoteproc remoteproc0: remote processor scp is now up
10831 12:39:31.199157 <4>[ 17.655642] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10832 12:39:31.202543 <4>[ 17.655642] Fallback method does not support PEC.
10833 12:39:31.212373 <3>[ 17.660912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 12:39:31.219212 <3>[ 17.660917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 12:39:31.229403 <3>[ 17.661030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 12:39:31.236221 <3>[ 17.670977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 12:39:31.246426 <3>[ 17.676606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 12:39:31.252914 <3>[ 17.676621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 12:39:31.259395 <3>[ 17.676692] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 12:39:31.269513 <3>[ 17.676702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 12:39:31.276064 <3>[ 17.676778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 12:39:31.286046 <6>[ 17.681783] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10843 12:39:31.296029 <6>[ 17.682213] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10844 12:39:31.302545 <6>[ 17.690144] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10845 12:39:31.312538 <6>[ 17.711723] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10846 12:39:31.322124 <6>[ 17.717785] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10847 12:39:31.325433 <6>[ 17.721636] pci_bus 0000:00: root bus resource [bus 00-ff]
10848 12:39:31.335592 <6>[ 17.730749] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10849 12:39:31.341805 <6>[ 17.738369] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10850 12:39:31.352343 <6>[ 17.754279] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10851 12:39:31.358948 <6>[ 17.762381] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10852 12:39:31.366114 <6>[ 17.762449] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10853 12:39:31.373988 <6>[ 17.762466] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10854 12:39:31.377691 <6>[ 17.762562] pci 0000:00:00.0: supports D1 D2
10855 12:39:31.380676 <6>[ 17.763108] Bluetooth: Core ver 2.22
10856 12:39:31.388393 <6>[ 17.763169] NET: Registered PF_BLUETOOTH protocol family
10857 12:39:31.395380 <6>[ 17.763171] Bluetooth: HCI device and connection manager initialized
10858 12:39:31.398798 <6>[ 17.763200] Bluetooth: HCI socket layer initialized
10859 12:39:31.405464 <6>[ 17.763212] Bluetooth: L2CAP socket layer initialized
10860 12:39:31.409057 <6>[ 17.763223] Bluetooth: SCO socket layer initialized
10861 12:39:31.419632 <3>[ 17.770965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 12:39:31.426335 <6>[ 17.778662] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10863 12:39:31.432657 <6>[ 17.779820] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10864 12:39:31.443003 <6>[ 17.789938] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10865 12:39:31.450051 <4>[ 17.793254] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10866 12:39:31.456723 <4>[ 17.793263] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10867 12:39:31.463489 <6>[ 17.798027] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10868 12:39:31.477431 <6>[ 17.806484] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10869 12:39:31.484499 <6>[ 17.814088] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10870 12:39:31.491288 <6>[ 17.814984] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10871 12:39:31.497920 <6>[ 17.822759] usbcore: registered new interface driver uvcvideo
10872 12:39:31.504543 <6>[ 17.828167] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10873 12:39:31.511451 <6>[ 17.828687] usbcore: registered new interface driver btusb
10874 12:39:31.521762 <4>[ 17.829852] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10875 12:39:31.525182 <3>[ 17.829864] Bluetooth: hci0: Failed to load firmware file (-2)
10876 12:39:31.531905 <3>[ 17.829868] Bluetooth: hci0: Failed to set up firmware (-2)
10877 12:39:31.542015 <4>[ 17.829875] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10878 12:39:31.548783 <6>[ 17.845384] r8152 2-1.3:1.0 eth0: v1.12.13
10879 12:39:31.555430 <6>[ 17.851802] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10880 12:39:31.558908 <6>[ 17.861747] usbcore: registered new interface driver r8152
10881 12:39:31.566239 <6>[ 17.868057] pci 0000:01:00.0: supports D1 D2
10882 12:39:31.572930 <3>[ 17.880893] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10883 12:39:31.579881 <6>[ 17.883801] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10884 12:39:31.586105 <6>[ 17.883972] usbcore: registered new interface driver cdc_ether
10885 12:39:31.597163 <3>[ 17.886143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 12:39:31.603948 <3>[ 17.892903] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 12:39:31.614436 <3>[ 17.893812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10888 12:39:31.617908 <6>[ 17.896197] usbcore: registered new interface driver r8153_ecm
10889 12:39:31.624532 <6>[ 17.905422] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10890 12:39:31.634277 <3>[ 17.915461] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 12:39:31.644173 <6>[ 17.920365] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10892 12:39:31.647457 <6>[ 17.934869] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10893 12:39:31.657238 <6>[ 17.935469] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10894 12:39:31.667077 <3>[ 17.951104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 12:39:31.673720 <6>[ 17.951537] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10896 12:39:31.683622 <3>[ 17.981938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:39:31.690387 <6>[ 17.985752] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10898 12:39:31.700314 <3>[ 18.012494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 12:39:31.707088 <6>[ 18.021971] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10900 12:39:31.713337 <6>[ 18.208506] pci 0000:00:00.0: PCI bridge to [bus 01]
10901 12:39:31.719753 <6>[ 18.208511] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10902 12:39:31.726520 <6>[ 18.208667] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10903 12:39:31.733028 [[0;32m OK [<6>[ 18.228685] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10904 12:39:31.743230 0m] Started [0;<6>[ 18.236133] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10905 12:39:31.746724 1;39mDiscard unused blocks once a week[0m.
10906 12:39:31.769366 [[0;32m OK [<5>[ 18.262398] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10907 12:39:31.772561 0m] Reached target [0;1;39mTimers[0m.
10908 12:39:31.789787 <5>[ 18.282755] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10909 12:39:31.796447 <5>[ 18.290360] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10910 12:39:31.809563 [[0;32m OK [<4>[ 18.299511] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10911 12:39:31.812824 0m] Listening on<6>[ 18.309616] cfg80211: failed to load regulatory.db
10912 12:39:31.819503 [0;1;39mD-Bus System Message Bus Socket[0m.
10913 12:39:31.833443 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10914 12:39:31.849633 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10915 12:39:31.856211 <6>[ 18.351138] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10916 12:39:31.863085 <6>[ 18.358964] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10917 12:39:31.889269 <6>[ 18.385760] mt7921e 0000:01:00.0: ASIC revision: 79610010
10918 12:39:31.901639 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10919 12:39:31.938623 Starting [0;1;39mUser Login Management[0m...
10920 12:39:31.957286 Starting [0;1;39mNetwork Name Resolution[0m...
10921 12:39:31.993421 <6>[ 18.486469] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10922 12:39:31.996760 <6>[ 18.486469]
10923 12:39:32.000152 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10924 12:39:32.030273 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10925 12:39:32.149054 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10926 12:39:32.159220 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10927 12:39:32.173422 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10928 12:39:32.193366 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10929 12:39:32.212681 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10930 12:39:32.229129 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10931 12:39:32.261456 <6>[ 18.754652] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10932 12:39:32.275074 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10933 12:39:32.294788 Starting [0;1;39mPermit User Sessions[0m...
10934 12:39:32.318589 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10935 12:39:32.336742 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10936 12:39:32.374239 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10937 12:39:32.395478 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10938 12:39:32.414274 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10939 12:39:32.429990 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10940 12:39:32.445800 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10941 12:39:32.494695 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10942 12:39:32.518375 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10943 12:39:32.537227 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10944 12:39:32.575328 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10945 12:39:32.614092
10946 12:39:32.614662
10947 12:39:32.617445 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10948 12:39:32.617977
10949 12:39:32.620571 debian-bullseye-arm64 login: root (automatic login)
10950 12:39:32.621044
10951 12:39:32.621412
10952 12:39:32.636815 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
10953 12:39:32.637287
10954 12:39:32.643432 The programs included with the Debian GNU/Linux system are free software;
10955 12:39:32.650137 the exact distribution terms for each program are described in the
10956 12:39:32.653510 individual files in /usr/share/doc/*/copyright.
10957 12:39:32.653968
10958 12:39:32.660220 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10959 12:39:32.663272 permitted by applicable law.
10960 12:39:32.664544 Matched prompt #10: / #
10962 12:39:32.665556 Setting prompt string to ['/ #']
10963 12:39:32.666025 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10965 12:39:32.667022 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10966 12:39:32.667469 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
10967 12:39:32.667825 Setting prompt string to ['/ #']
10968 12:39:32.668133 Forcing a shell prompt, looking for ['/ #']
10970 12:39:32.718918 / #
10971 12:39:32.719557 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10972 12:39:32.719973 Waiting using forced prompt support (timeout 00:02:30)
10973 12:39:32.725169
10974 12:39:32.726152 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10975 12:39:32.726962 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
10976 12:39:32.727730 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10977 12:39:32.728433 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
10978 12:39:32.729116 end: 2 depthcharge-action (duration 00:01:29) [common]
10979 12:39:32.729849 start: 3 lava-test-retry (timeout 00:08:10) [common]
10980 12:39:32.730452 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
10981 12:39:32.730871 Using namespace: common
10983 12:39:32.831885 / # #
10984 12:39:32.832384 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10985 12:39:32.838036 #
10986 12:39:32.838745 Using /lava-12703509
10988 12:39:32.939790 / # export SHELL=/bin/sh
10989 12:39:32.940027 export SHELL=/bin/sh<6>[ 19.415513] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
10990 12:39:32.940121 <6>[ 19.423563] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10991 12:39:32.944864
10993 12:39:33.045652 / # . /lava-12703509/environment
10994 12:39:33.051997 . /lava-12703509/environment
10996 12:39:33.153404 / # /lava-12703509/bin/lava-test-runner /lava-12703509/0
10997 12:39:33.153914 Test shell timeout: 10s (minimum of the action and connection timeout)
10998 12:39:33.155442 <6>[ 19.597683] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10999 12:39:33.159414 /lava-12703509/bin/lava-test-runner /lava-12703509/0
11000 12:39:33.185040 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11001 12:39:33.191596 + cd /lava-12703509/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11002 12:39:33.192033 + cat uuid
11003 12:39:33.194917 + UUID=12703509_1.5.2.3.1
11004 12:39:33.195523 + set +x
11005 12:39:33.201764 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12703509_1.5.2.3.1>
11006 12:39:33.202529 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12703509_1.5.2.3.1
11007 12:39:33.202923 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12703509_1.5.2.3.1)
11008 12:39:33.203333 Skipping test definition patterns.
11009 12:39:33.204663 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11010 12:39:33.211284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11011 12:39:33.211713 device: /dev/video2
11012 12:39:33.212301 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11014 12:39:33.221432 <4>[ 19.714062] use of bytesused == 0 is deprecated and will be removed in the future,
11015 12:39:33.224652 <4>[ 19.721952] use the actual size instead.
11016 12:39:33.238993 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11017 12:39:33.251134 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11018 12:39:33.258562
11019 12:39:33.273156 Compliance test for mtk-vcodec-enc device /dev/video2:
11020 12:39:33.279275
11021 12:39:33.289867 Driver Info:
11022 12:39:33.298733 Driver name : mtk-vcodec-enc
11023 12:39:33.313179 Card type : MT8192 video encoder
11024 12:39:33.323192 Bus info : platform:17020000.vcodec
11025 12:39:33.329769 Driver version : 6.1.75
11026 12:39:33.340808 Capabilities : 0x84204000
11027 12:39:33.350052 Video Memory-to-Memory Multiplanar
11028 12:39:33.360291 Streaming
11029 12:39:33.370393 Extended Pix Format
11030 12:39:33.381641 Device Capabilities
11031 12:39:33.392770 Device Caps : 0x04204000
11032 12:39:33.404218 Video Memory-to-Memory Multiplanar
11033 12:39:33.416991 Streaming
11034 12:39:33.428244 Extended Pix Format
11035 12:39:33.438667 Detected Stateful Encoder
11036 12:39:33.453258
11037 12:39:33.466976 Required ioctls:
11038 12:39:33.484598 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11039 12:39:33.485018 test VIDIOC_QUERYCAP: OK
11040 12:39:33.485798 Received signal: <TESTSET> START Required-ioctls
11041 12:39:33.486338 Starting test_set Required-ioctls
11042 12:39:33.508576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11043 12:39:33.509331 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11045 12:39:33.511732 test invalid ioctls: OK
11046 12:39:33.534365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11047 12:39:33.534799
11048 12:39:33.535376 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11050 12:39:33.546977 Allow for multiple opens:
11051 12:39:33.554686 <LAVA_SIGNAL_TESTSET STOP>
11052 12:39:33.555379 Received signal: <TESTSET> STOP
11053 12:39:33.555757 Closing test_set Required-ioctls
11054 12:39:33.565511 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11055 12:39:33.566338 Received signal: <TESTSET> START Allow-for-multiple-opens
11056 12:39:33.566708 Starting test_set Allow-for-multiple-opens
11057 12:39:33.568296 test second /dev/video2 open: OK
11058 12:39:33.590996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11059 12:39:33.591779 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11061 12:39:33.594182 test VIDIOC_QUERYCAP: OK
11062 12:39:33.615155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11063 12:39:33.615972 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11065 12:39:33.618355 test VIDIOC_G/S_PRIORITY: OK
11066 12:39:33.641352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11067 12:39:33.642236 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11069 12:39:33.644613 test for unlimited opens: OK
11070 12:39:33.665348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11071 12:39:33.665975
11072 12:39:33.666655 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11074 12:39:33.675146 Debug ioctls:
11075 12:39:33.681606 <LAVA_SIGNAL_TESTSET STOP>
11076 12:39:33.682105 Received signal: <TESTSET> STOP
11077 12:39:33.682313 Closing test_set Allow-for-multiple-opens
11078 12:39:33.691467 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11079 12:39:33.691986 Received signal: <TESTSET> START Debug-ioctls
11080 12:39:33.692268 Starting test_set Debug-ioctls
11081 12:39:33.694761 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11082 12:39:33.715619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11083 12:39:33.716130 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11085 12:39:33.722000 test VIDIOC_LOG_STATUS: OK (Not Supported)
11086 12:39:33.739814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11087 12:39:33.740053
11088 12:39:33.740531 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11090 12:39:33.750561 Input ioctls:
11091 12:39:33.760138 <LAVA_SIGNAL_TESTSET STOP>
11092 12:39:33.760641 Received signal: <TESTSET> STOP
11093 12:39:33.760919 Closing test_set Debug-ioctls
11094 12:39:33.771281 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11095 12:39:33.771723 Received signal: <TESTSET> START Input-ioctls
11096 12:39:33.771995 Starting test_set Input-ioctls
11097 12:39:33.774457 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11098 12:39:33.800936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11099 12:39:33.801231 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11101 12:39:33.804203 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11102 12:39:33.822040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11103 12:39:33.822292 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11105 12:39:33.828955 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11106 12:39:33.846855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11107 12:39:33.847103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11109 12:39:33.853450 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11110 12:39:33.872333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11111 12:39:33.873174 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11113 12:39:33.875301 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11114 12:39:33.898061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11115 12:39:33.898944 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11117 12:39:33.901288 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11118 12:39:33.922614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11119 12:39:33.923569 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11121 12:39:33.925753 Inputs: 0 Audio Inputs: 0 Tuners: 0
11122 12:39:33.936222
11123 12:39:33.957532 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11124 12:39:33.978759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11125 12:39:33.979465 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11127 12:39:33.984763 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11128 12:39:34.009016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11129 12:39:34.010068 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11131 12:39:34.015432 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11132 12:39:34.038853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11133 12:39:34.039616 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11135 12:39:34.045717 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11136 12:39:34.070747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11137 12:39:34.071488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11139 12:39:34.077381 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11140 12:39:34.105348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11141 12:39:34.106173 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11143 12:39:34.112630
11144 12:39:34.132856 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11145 12:39:34.151242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11146 12:39:34.151912 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11148 12:39:34.157653 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11149 12:39:34.179294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11150 12:39:34.179956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11152 12:39:34.182780 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11153 12:39:34.198654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11154 12:39:34.199301 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11156 12:39:34.201901 test VIDIOC_G/S_EDID: OK (Not Supported)
11157 12:39:34.225186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11158 12:39:34.225687
11159 12:39:34.226420 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11161 12:39:34.236053 Control ioctls:
11162 12:39:34.242791 <LAVA_SIGNAL_TESTSET STOP>
11163 12:39:34.243556 Received signal: <TESTSET> STOP
11164 12:39:34.244051 Closing test_set Input-ioctls
11165 12:39:34.251899 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11166 12:39:34.252602 Received signal: <TESTSET> START Control-ioctls
11167 12:39:34.253034 Starting test_set Control-ioctls
11168 12:39:34.255196 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11169 12:39:34.282177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11170 12:39:34.282597 test VIDIOC_QUERYCTRL: OK
11171 12:39:34.283181 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11173 12:39:34.305692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11174 12:39:34.306787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11176 12:39:34.308811 test VIDIOC_G/S_CTRL: OK
11177 12:39:34.334439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11178 12:39:34.335270 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11180 12:39:34.337560 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11181 12:39:34.359020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11182 12:39:34.359811 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11184 12:39:34.369005 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11185 12:39:34.372281 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11186 12:39:34.403636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11187 12:39:34.404769 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11189 12:39:34.406968 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11190 12:39:34.427172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11191 12:39:34.428258 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11193 12:39:34.430741 Standard Controls: 16 Private Controls: 0
11194 12:39:34.439925
11195 12:39:34.451604 Format ioctls:
11196 12:39:34.458612 <LAVA_SIGNAL_TESTSET STOP>
11197 12:39:34.459298 Received signal: <TESTSET> STOP
11198 12:39:34.459716 Closing test_set Control-ioctls
11199 12:39:34.468054 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11200 12:39:34.468772 Received signal: <TESTSET> START Format-ioctls
11201 12:39:34.469138 Starting test_set Format-ioctls
11202 12:39:34.471027 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11203 12:39:34.496511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11204 12:39:34.496772 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11206 12:39:34.499718 test VIDIOC_G/S_PARM: OK
11207 12:39:34.519201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11208 12:39:34.519463 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11210 12:39:34.522296 test VIDIOC_G_FBUF: OK (Not Supported)
11211 12:39:34.544901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11212 12:39:34.545155 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11214 12:39:34.548580 test VIDIOC_G_FMT: OK
11215 12:39:34.569797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11216 12:39:34.570065 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11218 12:39:34.573299 test VIDIOC_TRY_FMT: OK
11219 12:39:34.594948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11220 12:39:34.595225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11222 12:39:34.604672 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11223 12:39:34.604757 test VIDIOC_S_FMT: FAIL
11224 12:39:34.630836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11225 12:39:34.631090 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11227 12:39:34.634204 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11228 12:39:34.656573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11229 12:39:34.656827 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11231 12:39:34.660058 test Cropping: OK
11232 12:39:34.683253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11233 12:39:34.683509 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11235 12:39:34.686494 test Composing: OK (Not Supported)
11236 12:39:34.707367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11237 12:39:34.707621 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11239 12:39:34.710400 test Scaling: OK (Not Supported)
11240 12:39:34.731600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11241 12:39:34.731772
11242 12:39:34.732039 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11244 12:39:34.741778 Codec ioctls:
11245 12:39:34.749677 <LAVA_SIGNAL_TESTSET STOP>
11246 12:39:34.750390 Received signal: <TESTSET> STOP
11247 12:39:34.750752 Closing test_set Format-ioctls
11248 12:39:34.759600 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11249 12:39:34.760277 Received signal: <TESTSET> START Codec-ioctls
11250 12:39:34.760635 Starting test_set Codec-ioctls
11251 12:39:34.762221 test VIDIOC_(TRY_)ENCODER_CMD: OK
11252 12:39:34.783381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11253 12:39:34.784058 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11255 12:39:34.789715 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11256 12:39:34.811636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11257 12:39:34.812319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11259 12:39:34.818551 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11260 12:39:34.836315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11261 12:39:34.836749
11262 12:39:34.837350 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11264 12:39:34.847042 Buffer ioctls:
11265 12:39:34.855256 <LAVA_SIGNAL_TESTSET STOP>
11266 12:39:34.855927 Received signal: <TESTSET> STOP
11267 12:39:34.856279 Closing test_set Codec-ioctls
11268 12:39:34.867132 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11269 12:39:34.867808 Received signal: <TESTSET> START Buffer-ioctls
11270 12:39:34.868171 Starting test_set Buffer-ioctls
11271 12:39:34.870477 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11272 12:39:34.896388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11273 12:39:34.896837 test VIDIOC_EXPBUF: OK
11274 12:39:34.897611 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11276 12:39:34.917463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11277 12:39:34.918145 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11279 12:39:34.920809 test Requests: OK (Not Supported)
11280 12:39:34.942701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11281 12:39:34.943344
11282 12:39:34.943956 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11284 12:39:34.953541 Test input 0:
11285 12:39:34.962539
11286 12:39:34.973807 Streaming ioctls:
11287 12:39:34.980997 <LAVA_SIGNAL_TESTSET STOP>
11288 12:39:34.981768 Received signal: <TESTSET> STOP
11289 12:39:34.982247 Closing test_set Buffer-ioctls
11290 12:39:34.990498 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11291 12:39:34.991181 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11292 12:39:34.991544 Starting test_set Streaming-ioctls_Test-input-0
11293 12:39:34.993959 test read/write: OK (Not Supported)
11294 12:39:35.015586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11295 12:39:35.016266 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11297 12:39:35.022316 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11298 12:39:35.033192 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11299 12:39:35.039362 test blocking wait: FAIL
11300 12:39:35.065023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11301 12:39:35.065702 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11303 12:39:35.075026 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11304 12:39:35.075456 test MMAP (select): FAIL
11305 12:39:35.106272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11306 12:39:35.106952 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11308 12:39:35.112705 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11309 12:39:35.115540 test MMAP (epoll): FAIL
11310 12:39:35.140165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11311 12:39:35.140852 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11313 12:39:35.149736 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11314 12:39:35.156496 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11315 12:39:35.165842 test USERPTR (select): FAIL
11316 12:39:35.191172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11317 12:39:35.191857 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11319 12:39:35.198046 test DMABUF: Cannot test, specify --expbuf-device
11320 12:39:35.207072
11321 12:39:35.224932 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11322 12:39:35.230568 <LAVA_TEST_RUNNER EXIT>
11323 12:39:35.231459 ok: lava_test_shell seems to have completed
11324 12:39:35.231874 Marking unfinished test run as failed
11326 12:39:35.236562 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11327 12:39:35.237219 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11328 12:39:35.237706 end: 3 lava-test-retry (duration 00:00:03) [common]
11329 12:39:35.238240 start: 4 finalize (timeout 00:08:08) [common]
11330 12:39:35.238759 start: 4.1 power-off (timeout 00:00:30) [common]
11331 12:39:35.239623 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11332 12:39:35.356155 >> Command sent successfully.
11333 12:39:35.367039 Returned 0 in 0 seconds
11334 12:39:35.468361 end: 4.1 power-off (duration 00:00:00) [common]
11336 12:39:35.469807 start: 4.2 read-feedback (timeout 00:08:07) [common]
11337 12:39:35.471090 Listened to connection for namespace 'common' for up to 1s
11338 12:39:36.471767 Finalising connection for namespace 'common'
11339 12:39:36.472415 Disconnecting from shell: Finalise
11340 12:39:36.472813 / #
11341 12:39:36.573720 end: 4.2 read-feedback (duration 00:00:01) [common]
11342 12:39:36.574392 end: 4 finalize (duration 00:00:01) [common]
11343 12:39:36.575004 Cleaning after the job
11344 12:39:36.575513 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/ramdisk
11345 12:39:36.594547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/kernel
11346 12:39:36.615639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/dtb
11347 12:39:36.615997 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703509/tftp-deploy-5m3tmryu/modules
11348 12:39:36.625403 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703509
11349 12:39:36.683458 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703509
11350 12:39:36.683641 Job finished correctly