Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 13
1 20:10:18.706579 lava-dispatcher, installed at version: 2024.01
2 20:10:18.706843 start: 0 validate
3 20:10:18.706978 Start time: 2024-03-03 20:10:18.706970+00:00 (UTC)
4 20:10:18.707111 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:10:18.707246 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 20:10:18.997702 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:10:18.997871 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:10:19.267224 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:10:19.267469 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:11:04.613223 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:11:04.613396 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:11:05.142285 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:11:05.142493 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:11:05.410562 validate duration: 46.70
16 20:11:05.410818 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:11:05.410916 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:11:05.411001 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:11:05.411122 Not decompressing ramdisk as can be used compressed.
20 20:11:05.411260 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20240129.0/arm64/initrd.cpio.gz
21 20:11:05.411368 saving as /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/ramdisk/initrd.cpio.gz
22 20:11:05.411431 total size: 4663052 (4 MB)
23 20:11:08.080897 progress 0 % (0 MB)
24 20:11:08.082505 progress 5 % (0 MB)
25 20:11:08.083789 progress 10 % (0 MB)
26 20:11:08.085044 progress 15 % (0 MB)
27 20:11:08.086300 progress 20 % (0 MB)
28 20:11:08.087568 progress 25 % (1 MB)
29 20:11:08.088814 progress 30 % (1 MB)
30 20:11:08.090049 progress 35 % (1 MB)
31 20:11:08.091317 progress 40 % (1 MB)
32 20:11:08.092714 progress 45 % (2 MB)
33 20:11:08.093962 progress 50 % (2 MB)
34 20:11:08.095247 progress 55 % (2 MB)
35 20:11:08.096486 progress 60 % (2 MB)
36 20:11:08.097714 progress 65 % (2 MB)
37 20:11:08.098979 progress 70 % (3 MB)
38 20:11:08.100206 progress 75 % (3 MB)
39 20:11:08.101441 progress 80 % (3 MB)
40 20:11:08.102774 progress 85 % (3 MB)
41 20:11:08.104177 progress 90 % (4 MB)
42 20:11:08.105411 progress 95 % (4 MB)
43 20:11:08.106704 progress 100 % (4 MB)
44 20:11:08.106848 4 MB downloaded in 2.70 s (1.65 MB/s)
45 20:11:08.106997 end: 1.1.1 http-download (duration 00:00:03) [common]
47 20:11:08.107241 end: 1.1 download-retry (duration 00:00:03) [common]
48 20:11:08.107328 start: 1.2 download-retry (timeout 00:09:57) [common]
49 20:11:08.107413 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 20:11:08.107548 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:11:08.107616 saving as /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/kernel/Image
52 20:11:08.107675 total size: 51601920 (49 MB)
53 20:11:08.107735 No compression specified
54 20:11:08.108800 progress 0 % (0 MB)
55 20:11:08.122088 progress 5 % (2 MB)
56 20:11:08.135689 progress 10 % (4 MB)
57 20:11:08.149289 progress 15 % (7 MB)
58 20:11:08.162454 progress 20 % (9 MB)
59 20:11:08.179627 progress 25 % (12 MB)
60 20:11:08.197987 progress 30 % (14 MB)
61 20:11:08.211923 progress 35 % (17 MB)
62 20:11:08.228669 progress 40 % (19 MB)
63 20:11:08.242391 progress 45 % (22 MB)
64 20:11:08.257731 progress 50 % (24 MB)
65 20:11:08.278461 progress 55 % (27 MB)
66 20:11:08.296978 progress 60 % (29 MB)
67 20:11:08.310904 progress 65 % (32 MB)
68 20:11:08.325002 progress 70 % (34 MB)
69 20:11:08.338915 progress 75 % (36 MB)
70 20:11:08.352653 progress 80 % (39 MB)
71 20:11:08.366374 progress 85 % (41 MB)
72 20:11:08.380279 progress 90 % (44 MB)
73 20:11:08.397487 progress 95 % (46 MB)
74 20:11:08.415230 progress 100 % (49 MB)
75 20:11:08.415634 49 MB downloaded in 0.31 s (159.80 MB/s)
76 20:11:08.415894 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:11:08.416318 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:11:08.416469 start: 1.3 download-retry (timeout 00:09:57) [common]
80 20:11:08.416619 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 20:11:08.416866 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:11:08.416994 saving as /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/dtb/mt8192-asurada-spherion-r0.dtb
83 20:11:08.417110 total size: 47278 (0 MB)
84 20:11:08.417225 No compression specified
85 20:11:08.419106 progress 69 % (0 MB)
86 20:11:08.419515 progress 100 % (0 MB)
87 20:11:08.419789 0 MB downloaded in 0.00 s (16.85 MB/s)
88 20:11:08.420022 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:11:08.420481 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:11:08.420660 start: 1.4 download-retry (timeout 00:09:57) [common]
92 20:11:08.420834 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 20:11:08.421062 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20240129.0/arm64/full.rootfs.tar.xz
94 20:11:08.421195 saving as /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/nfsrootfs/full.rootfs.tar
95 20:11:08.421339 total size: 125310928 (119 MB)
96 20:11:08.421484 Using unxz to decompress xz
97 20:11:08.427278 progress 0 % (0 MB)
98 20:11:08.804794 progress 5 % (6 MB)
99 20:11:09.172312 progress 10 % (11 MB)
100 20:11:09.518480 progress 15 % (17 MB)
101 20:11:09.723535 progress 20 % (23 MB)
102 20:11:09.907796 progress 25 % (29 MB)
103 20:11:10.271897 progress 30 % (35 MB)
104 20:11:10.645228 progress 35 % (41 MB)
105 20:11:11.054387 progress 40 % (47 MB)
106 20:11:11.454732 progress 45 % (53 MB)
107 20:11:11.844940 progress 50 % (59 MB)
108 20:11:12.201461 progress 55 % (65 MB)
109 20:11:12.575955 progress 60 % (71 MB)
110 20:11:12.939793 progress 65 % (77 MB)
111 20:11:13.319786 progress 70 % (83 MB)
112 20:11:13.721698 progress 75 % (89 MB)
113 20:11:14.180873 progress 80 % (95 MB)
114 20:11:14.701800 progress 85 % (101 MB)
115 20:11:14.965511 progress 90 % (107 MB)
116 20:11:15.326216 progress 95 % (113 MB)
117 20:11:15.719917 progress 100 % (119 MB)
118 20:11:15.725168 119 MB downloaded in 7.30 s (16.36 MB/s)
119 20:11:15.725456 end: 1.4.1 http-download (duration 00:00:07) [common]
121 20:11:15.725744 end: 1.4 download-retry (duration 00:00:07) [common]
122 20:11:15.725903 start: 1.5 download-retry (timeout 00:09:50) [common]
123 20:11:15.726064 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 20:11:15.726245 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:11:15.726321 saving as /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/modules/modules.tar
126 20:11:15.726384 total size: 8632284 (8 MB)
127 20:11:15.726462 Using unxz to decompress xz
128 20:11:15.730744 progress 0 % (0 MB)
129 20:11:15.755020 progress 5 % (0 MB)
130 20:11:15.785256 progress 10 % (0 MB)
131 20:11:15.818669 progress 15 % (1 MB)
132 20:11:15.851617 progress 20 % (1 MB)
133 20:11:15.884430 progress 25 % (2 MB)
134 20:11:15.916764 progress 30 % (2 MB)
135 20:11:15.950847 progress 35 % (2 MB)
136 20:11:15.980446 progress 40 % (3 MB)
137 20:11:16.013091 progress 45 % (3 MB)
138 20:11:16.045760 progress 50 % (4 MB)
139 20:11:16.077186 progress 55 % (4 MB)
140 20:11:16.113336 progress 60 % (4 MB)
141 20:11:16.146693 progress 65 % (5 MB)
142 20:11:16.179160 progress 70 % (5 MB)
143 20:11:16.208311 progress 75 % (6 MB)
144 20:11:16.237239 progress 80 % (6 MB)
145 20:11:16.271999 progress 85 % (7 MB)
146 20:11:16.307422 progress 90 % (7 MB)
147 20:11:16.339726 progress 95 % (7 MB)
148 20:11:16.379798 progress 100 % (8 MB)
149 20:11:16.387102 8 MB downloaded in 0.66 s (12.46 MB/s)
150 20:11:16.387405 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:11:16.387714 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:11:16.387839 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 20:11:16.387942 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 20:11:18.799311 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti
156 20:11:18.799520 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 20:11:18.799621 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 20:11:18.799793 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x
159 20:11:18.799925 makedir: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin
160 20:11:18.800029 makedir: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/tests
161 20:11:18.800130 makedir: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/results
162 20:11:18.800255 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-add-keys
163 20:11:18.800408 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-add-sources
164 20:11:18.800554 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-background-process-start
165 20:11:18.800684 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-background-process-stop
166 20:11:18.800813 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-common-functions
167 20:11:18.800940 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-echo-ipv4
168 20:11:18.801067 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-install-packages
169 20:11:18.801194 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-installed-packages
170 20:11:18.801320 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-os-build
171 20:11:18.801445 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-probe-channel
172 20:11:18.801571 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-probe-ip
173 20:11:18.801696 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-target-ip
174 20:11:18.801821 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-target-mac
175 20:11:18.801944 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-target-storage
176 20:11:18.802071 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-case
177 20:11:18.802199 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-event
178 20:11:18.802325 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-feedback
179 20:11:18.802514 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-raise
180 20:11:18.802661 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-reference
181 20:11:18.802787 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-runner
182 20:11:18.802915 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-set
183 20:11:18.803041 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-test-shell
184 20:11:18.803169 Updating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-install-packages (oe)
185 20:11:18.803324 Updating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/bin/lava-installed-packages (oe)
186 20:11:18.803449 Creating /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/environment
187 20:11:18.803546 LAVA metadata
188 20:11:18.803618 - LAVA_JOB_ID=12928089
189 20:11:18.803681 - LAVA_DISPATCHER_IP=192.168.201.1
190 20:11:18.803790 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
191 20:11:18.803858 skipped lava-vland-overlay
192 20:11:18.803932 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 20:11:18.804011 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
194 20:11:18.804072 skipped lava-multinode-overlay
195 20:11:18.804144 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 20:11:18.804220 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
197 20:11:18.804295 Loading test definitions
198 20:11:18.804383 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
199 20:11:18.804453 Using /lava-12928089 at stage 0
200 20:11:18.804770 uuid=12928089_1.6.2.3.1 testdef=None
201 20:11:18.804860 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 20:11:18.804944 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
203 20:11:18.805458 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 20:11:18.805679 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
206 20:11:18.806322 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 20:11:18.806713 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
209 20:11:18.807343 runner path: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/0/tests/0_dmesg test_uuid 12928089_1.6.2.3.1
210 20:11:18.807507 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 20:11:18.807729 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:47) [common]
213 20:11:18.807801 Using /lava-12928089 at stage 1
214 20:11:18.808104 uuid=12928089_1.6.2.3.5 testdef=None
215 20:11:18.808192 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 20:11:18.808276 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
217 20:11:18.808784 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 20:11:18.808998 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
220 20:11:18.809645 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 20:11:18.809872 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
223 20:11:18.810560 runner path: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/1/tests/1_bootrr test_uuid 12928089_1.6.2.3.5
224 20:11:18.810716 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 20:11:18.810919 Creating lava-test-runner.conf files
227 20:11:18.810982 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/0 for stage 0
228 20:11:18.811073 - 0_dmesg
229 20:11:18.811153 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928089/lava-overlay-3_ra6r7x/lava-12928089/1 for stage 1
230 20:11:18.811244 - 1_bootrr
231 20:11:18.811338 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 20:11:18.811421 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
233 20:11:18.819493 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 20:11:18.819636 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:47) [common]
235 20:11:18.819727 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 20:11:18.819815 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 20:11:18.819900 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:47) [common]
238 20:11:18.945831 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 20:11:18.946336 start: 1.6.4 extract-modules (timeout 00:09:46) [common]
240 20:11:18.946548 extracting modules file /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti
241 20:11:19.199976 extracting modules file /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928089/extract-overlay-ramdisk-621xob7l/ramdisk
242 20:11:19.435209 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 20:11:19.435380 start: 1.6.5 apply-overlay-tftp (timeout 00:09:46) [common]
244 20:11:19.435473 [common] Applying overlay to NFS
245 20:11:19.435547 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928089/compress-overlay-drhl4hp3/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti
246 20:11:19.443884 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 20:11:19.444043 start: 1.6.6 configure-preseed-file (timeout 00:09:46) [common]
248 20:11:19.444170 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 20:11:19.444292 start: 1.6.7 compress-ramdisk (timeout 00:09:46) [common]
250 20:11:19.444403 Building ramdisk /var/lib/lava/dispatcher/tmp/12928089/extract-overlay-ramdisk-621xob7l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928089/extract-overlay-ramdisk-621xob7l/ramdisk
251 20:11:19.789818 >> 119447 blocks
252 20:11:21.732957 rename /var/lib/lava/dispatcher/tmp/12928089/extract-overlay-ramdisk-621xob7l/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/ramdisk/ramdisk.cpio.gz
253 20:11:21.733425 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 20:11:21.733554 start: 1.6.8 prepare-kernel (timeout 00:09:44) [common]
255 20:11:21.733660 start: 1.6.8.1 prepare-fit (timeout 00:09:44) [common]
256 20:11:21.733769 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/kernel/Image'
257 20:11:35.806770 Returned 0 in 14 seconds
258 20:11:35.907533 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/kernel/image.itb
259 20:11:36.291933 output: FIT description: Kernel Image image with one or more FDT blobs
260 20:11:36.292331 output: Created: Sun Mar 3 20:11:36 2024
261 20:11:36.292413 output: Image 0 (kernel-1)
262 20:11:36.292523 output: Description:
263 20:11:36.292604 output: Created: Sun Mar 3 20:11:36 2024
264 20:11:36.292705 output: Type: Kernel Image
265 20:11:36.292832 output: Compression: lzma compressed
266 20:11:36.292893 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
267 20:11:36.292955 output: Architecture: AArch64
268 20:11:36.293017 output: OS: Linux
269 20:11:36.293078 output: Load Address: 0x00000000
270 20:11:36.293147 output: Entry Point: 0x00000000
271 20:11:36.293218 output: Hash algo: crc32
272 20:11:36.293274 output: Hash value: 91cb1a17
273 20:11:36.293329 output: Image 1 (fdt-1)
274 20:11:36.293383 output: Description: mt8192-asurada-spherion-r0
275 20:11:36.293439 output: Created: Sun Mar 3 20:11:36 2024
276 20:11:36.293492 output: Type: Flat Device Tree
277 20:11:36.293545 output: Compression: uncompressed
278 20:11:36.293597 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 20:11:36.293649 output: Architecture: AArch64
280 20:11:36.293701 output: Hash algo: crc32
281 20:11:36.293753 output: Hash value: cc4352de
282 20:11:36.293805 output: Image 2 (ramdisk-1)
283 20:11:36.293857 output: Description: unavailable
284 20:11:36.293909 output: Created: Sun Mar 3 20:11:36 2024
285 20:11:36.293961 output: Type: RAMDisk Image
286 20:11:36.294013 output: Compression: Unknown Compression
287 20:11:36.294064 output: Data Size: 17806052 Bytes = 17388.72 KiB = 16.98 MiB
288 20:11:36.294117 output: Architecture: AArch64
289 20:11:36.294169 output: OS: Linux
290 20:11:36.294220 output: Load Address: unavailable
291 20:11:36.294272 output: Entry Point: unavailable
292 20:11:36.294323 output: Hash algo: crc32
293 20:11:36.294375 output: Hash value: c3725b48
294 20:11:36.294467 output: Default Configuration: 'conf-1'
295 20:11:36.294521 output: Configuration 0 (conf-1)
296 20:11:36.294572 output: Description: mt8192-asurada-spherion-r0
297 20:11:36.294624 output: Kernel: kernel-1
298 20:11:36.294676 output: Init Ramdisk: ramdisk-1
299 20:11:36.294728 output: FDT: fdt-1
300 20:11:36.294779 output: Loadables: kernel-1
301 20:11:36.294831 output:
302 20:11:36.295043 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
303 20:11:36.295146 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
304 20:11:36.295251 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 20:11:36.295348 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:29) [common]
306 20:11:36.295436 No LXC device requested
307 20:11:36.295516 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 20:11:36.295602 start: 1.8 deploy-device-env (timeout 00:09:29) [common]
309 20:11:36.295682 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 20:11:36.295749 Checking files for TFTP limit of 4294967296 bytes.
311 20:11:36.296316 end: 1 tftp-deploy (duration 00:00:31) [common]
312 20:11:36.296422 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 20:11:36.296516 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 20:11:36.296649 substitutions:
315 20:11:36.296715 - {DTB}: 12928089/tftp-deploy-u_hjodma/dtb/mt8192-asurada-spherion-r0.dtb
316 20:11:36.296783 - {INITRD}: 12928089/tftp-deploy-u_hjodma/ramdisk/ramdisk.cpio.gz
317 20:11:36.296843 - {KERNEL}: 12928089/tftp-deploy-u_hjodma/kernel/Image
318 20:11:36.296899 - {LAVA_MAC}: None
319 20:11:36.296955 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti
320 20:11:36.297010 - {NFS_SERVER_IP}: 192.168.201.1
321 20:11:36.297063 - {PRESEED_CONFIG}: None
322 20:11:36.297117 - {PRESEED_LOCAL}: None
323 20:11:36.297171 - {RAMDISK}: 12928089/tftp-deploy-u_hjodma/ramdisk/ramdisk.cpio.gz
324 20:11:36.297224 - {ROOT_PART}: None
325 20:11:36.297277 - {ROOT}: None
326 20:11:36.297330 - {SERVER_IP}: 192.168.201.1
327 20:11:36.297383 - {TEE}: None
328 20:11:36.297435 Parsed boot commands:
329 20:11:36.297487 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 20:11:36.297677 Parsed boot commands: tftpboot 192.168.201.1 12928089/tftp-deploy-u_hjodma/kernel/image.itb 12928089/tftp-deploy-u_hjodma/kernel/cmdline
331 20:11:36.297763 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 20:11:36.297843 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 20:11:36.297961 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 20:11:36.298045 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 20:11:36.298117 Not connected, no need to disconnect.
336 20:11:36.298189 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 20:11:36.298269 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 20:11:36.298337 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
339 20:11:36.302486 Setting prompt string to ['lava-test: # ']
340 20:11:36.302876 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 20:11:36.302999 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 20:11:36.303096 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 20:11:36.303214 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 20:11:36.303440 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
345 20:11:41.435053 >> Command sent successfully.
346 20:11:41.437637 Returned 0 in 5 seconds
347 20:11:41.538051 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 20:11:41.538493 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 20:11:41.538599 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 20:11:41.538689 Setting prompt string to 'Starting depthcharge on Spherion...'
352 20:11:41.538760 Changing prompt to 'Starting depthcharge on Spherion...'
353 20:11:41.538827 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 20:11:41.539109 [Enter `^Ec?' for help]
355 20:11:41.716985
356 20:11:41.717134
357 20:11:41.717204 F0: 102B 0000
358 20:11:41.717270
359 20:11:41.717329 F3: 1001 0000 [0200]
360 20:11:41.719774
361 20:11:41.719859 F3: 1001 0000
362 20:11:41.719926
363 20:11:41.719987 F7: 102D 0000
364 20:11:41.720045
365 20:11:41.722919 F1: 0000 0000
366 20:11:41.723006
367 20:11:41.723072 V0: 0000 0000 [0001]
368 20:11:41.723138
369 20:11:41.726879 00: 0007 8000
370 20:11:41.726975
371 20:11:41.727042 01: 0000 0000
372 20:11:41.727105
373 20:11:41.729903 BP: 0C00 0209 [0000]
374 20:11:41.729991
375 20:11:41.730057 G0: 1182 0000
376 20:11:41.730118
377 20:11:41.733223 EC: 0000 0021 [4000]
378 20:11:41.733309
379 20:11:41.733375 S7: 0000 0000 [0000]
380 20:11:41.733436
381 20:11:41.737051 CC: 0000 0000 [0001]
382 20:11:41.737148
383 20:11:41.737217 T0: 0000 0040 [010F]
384 20:11:41.737280
385 20:11:41.737363 Jump to BL
386 20:11:41.737436
387 20:11:41.763697
388 20:11:41.763838
389 20:11:41.763911
390 20:11:41.771273 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 20:11:41.775686 ARM64: Exception handlers installed.
392 20:11:41.778768 ARM64: Testing exception
393 20:11:41.782669 ARM64: Done test exception
394 20:11:41.788690 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 20:11:41.799035 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 20:11:41.805648 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 20:11:41.816026 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 20:11:41.822445 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 20:11:41.829262 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 20:11:41.840365 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 20:11:41.846935 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 20:11:41.866044 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 20:11:41.869846 WDT: Last reset was cold boot
404 20:11:41.873845 SPI1(PAD0) initialized at 2873684 Hz
405 20:11:41.876221 SPI5(PAD0) initialized at 992727 Hz
406 20:11:41.879998 VBOOT: Loading verstage.
407 20:11:41.885964 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 20:11:41.889630 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 20:11:41.892793 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 20:11:41.896138 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 20:11:41.904064 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 20:11:41.910305 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 20:11:41.921103 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 20:11:41.921243
415 20:11:41.921343
416 20:11:41.931126 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 20:11:41.935075 ARM64: Exception handlers installed.
418 20:11:41.937747 ARM64: Testing exception
419 20:11:41.937844 ARM64: Done test exception
420 20:11:41.944424 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 20:11:41.947799 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:11:41.963027 Probing TPM: . done!
423 20:11:41.963172 TPM ready after 0 ms
424 20:11:41.970563 Connected to device vid:did:rid of 1ae0:0028:00
425 20:11:41.976796 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 20:11:42.034280 Initialized TPM device CR50 revision 0
427 20:11:42.044467 tlcl_send_startup: Startup return code is 0
428 20:11:42.044612 TPM: setup succeeded
429 20:11:42.056017 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 20:11:42.065019 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 20:11:42.076365 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 20:11:42.086703 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 20:11:42.089749 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 20:11:42.097432 in-header: 03 07 00 00 08 00 00 00
435 20:11:42.100377 in-data: aa e4 47 04 13 02 00 00
436 20:11:42.104215 Chrome EC: UHEPI supported
437 20:11:42.111381 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 20:11:42.115186 in-header: 03 ad 00 00 08 00 00 00
439 20:11:42.115316 in-data: 00 20 20 08 00 00 00 00
440 20:11:42.118853 Phase 1
441 20:11:42.122897 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 20:11:42.127003 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 20:11:42.133766 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 20:11:42.137825 Recovery requested (1009000e)
445 20:11:42.144969 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 20:11:42.150319 tlcl_extend: response is 0
447 20:11:42.159966 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 20:11:42.165791 tlcl_extend: response is 0
449 20:11:42.172623 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 20:11:42.192886 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 20:11:42.199496 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 20:11:42.199630
453 20:11:42.199727
454 20:11:42.210221 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 20:11:42.213713 ARM64: Exception handlers installed.
456 20:11:42.213821 ARM64: Testing exception
457 20:11:42.217541 ARM64: Done test exception
458 20:11:42.237906 pmic_efuse_setting: Set efuses in 11 msecs
459 20:11:42.241752 pmwrap_interface_init: Select PMIF_VLD_RDY
460 20:11:42.248305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 20:11:42.251299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 20:11:42.258610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 20:11:42.262599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 20:11:42.266375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 20:11:42.270151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 20:11:42.277825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 20:11:42.280991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 20:11:42.285461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 20:11:42.288459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 20:11:42.296442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 20:11:42.300239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 20:11:42.304243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 20:11:42.311097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 20:11:42.315096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 20:11:42.322698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 20:11:42.326174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 20:11:42.334038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 20:11:42.337569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 20:11:42.345574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 20:11:42.348767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 20:11:42.355630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 20:11:42.359225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 20:11:42.367365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 20:11:42.370647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 20:11:42.378381 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 20:11:42.382039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 20:11:42.386620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 20:11:42.393305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 20:11:42.397262 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 20:11:42.400835 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 20:11:42.407672 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 20:11:42.411416 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 20:11:42.415153 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 20:11:42.422357 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 20:11:42.426519 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 20:11:42.434079 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 20:11:42.438025 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 20:11:42.441677 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 20:11:42.445215 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 20:11:42.448722 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 20:11:42.455986 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 20:11:42.459775 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 20:11:42.463371 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 20:11:42.467153 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 20:11:42.471211 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 20:11:42.474516 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 20:11:42.482752 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 20:11:42.485633 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 20:11:42.489711 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 20:11:42.493261 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 20:11:42.500945 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 20:11:42.508799 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 20:11:42.515562 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 20:11:42.522771 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 20:11:42.530550 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 20:11:42.534017 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 20:11:42.537939 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 20:11:42.545457 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 20:11:42.552413 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
520 20:11:42.555930 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 20:11:42.563784 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 20:11:42.566785 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 20:11:42.575418 [RTC]rtc_get_frequency_meter,154: input=15, output=790
524 20:11:42.584820 [RTC]rtc_get_frequency_meter,154: input=23, output=980
525 20:11:42.595103 [RTC]rtc_get_frequency_meter,154: input=19, output=884
526 20:11:42.604449 [RTC]rtc_get_frequency_meter,154: input=17, output=836
527 20:11:42.613573 [RTC]rtc_get_frequency_meter,154: input=16, output=813
528 20:11:42.622923 [RTC]rtc_get_frequency_meter,154: input=15, output=790
529 20:11:42.633271 [RTC]rtc_get_frequency_meter,154: input=16, output=814
530 20:11:42.637789 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
531 20:11:42.640634 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
532 20:11:42.644198 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 20:11:42.651749 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 20:11:42.656031 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 20:11:42.659197 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 20:11:42.663136 ADC[4]: Raw value=901328 ID=7
537 20:11:42.663243 ADC[3]: Raw value=213336 ID=1
538 20:11:42.666992 RAM Code: 0x71
539 20:11:42.671056 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 20:11:42.674742 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 20:11:42.685586 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 20:11:42.689921 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 20:11:42.692957 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 20:11:42.698110 in-header: 03 07 00 00 08 00 00 00
545 20:11:42.701818 in-data: aa e4 47 04 13 02 00 00
546 20:11:42.704899 Chrome EC: UHEPI supported
547 20:11:42.712193 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 20:11:42.715866 in-header: 03 ed 00 00 08 00 00 00
549 20:11:42.715974 in-data: 80 20 60 08 00 00 00 00
550 20:11:42.720153 MRC: failed to locate region type 0.
551 20:11:42.726889 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 20:11:42.730633 DRAM-K: Running full calibration
553 20:11:42.738261 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 20:11:42.738447 header.status = 0x0
555 20:11:42.741672 header.version = 0x6 (expected: 0x6)
556 20:11:42.745415 header.size = 0xd00 (expected: 0xd00)
557 20:11:42.745521 header.flags = 0x0
558 20:11:42.752607 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 20:11:42.771382 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
560 20:11:42.779091 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 20:11:42.779226 dram_init: ddr_geometry: 2
562 20:11:42.782252 [EMI] MDL number = 2
563 20:11:42.786482 [EMI] Get MDL freq = 0
564 20:11:42.786591 dram_init: ddr_type: 0
565 20:11:42.790341 is_discrete_lpddr4: 1
566 20:11:42.790475 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 20:11:42.790544
568 20:11:42.794411
569 20:11:42.794514 [Bian_co] ETT version 0.0.0.1
570 20:11:42.798631 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 20:11:42.798726
572 20:11:42.805026 dramc_set_vcore_voltage set vcore to 650000
573 20:11:42.805140 Read voltage for 800, 4
574 20:11:42.805236 Vio18 = 0
575 20:11:42.809335 Vcore = 650000
576 20:11:42.809433 Vdram = 0
577 20:11:42.809521 Vddq = 0
578 20:11:42.812094 Vmddr = 0
579 20:11:42.812184 dram_init: config_dvfs: 1
580 20:11:42.818773 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 20:11:42.822119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 20:11:42.825640 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
583 20:11:42.832056 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
584 20:11:42.835554 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
585 20:11:42.839125 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
586 20:11:42.842356 MEM_TYPE=3, freq_sel=18
587 20:11:42.842501 sv_algorithm_assistance_LP4_1600
588 20:11:42.849445 ============ PULL DRAM RESETB DOWN ============
589 20:11:42.852669 ========== PULL DRAM RESETB DOWN end =========
590 20:11:42.856166 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 20:11:42.858987 ===================================
592 20:11:42.862770 LPDDR4 DRAM CONFIGURATION
593 20:11:42.865755 ===================================
594 20:11:42.869057 EX_ROW_EN[0] = 0x0
595 20:11:42.869169 EX_ROW_EN[1] = 0x0
596 20:11:42.872821 LP4Y_EN = 0x0
597 20:11:42.872944 WORK_FSP = 0x0
598 20:11:42.875975 WL = 0x2
599 20:11:42.876078 RL = 0x2
600 20:11:42.878879 BL = 0x2
601 20:11:42.878967 RPST = 0x0
602 20:11:42.882344 RD_PRE = 0x0
603 20:11:42.882467 WR_PRE = 0x1
604 20:11:42.885560 WR_PST = 0x0
605 20:11:42.885677 DBI_WR = 0x0
606 20:11:42.889697 DBI_RD = 0x0
607 20:11:42.889788 OTF = 0x1
608 20:11:42.892349 ===================================
609 20:11:42.896031 ===================================
610 20:11:42.899722 ANA top config
611 20:11:42.903383 ===================================
612 20:11:42.903488 DLL_ASYNC_EN = 0
613 20:11:42.905905 ALL_SLAVE_EN = 1
614 20:11:42.910039 NEW_RANK_MODE = 1
615 20:11:42.912858 DLL_IDLE_MODE = 1
616 20:11:42.913022 LP45_APHY_COMB_EN = 1
617 20:11:42.916077 TX_ODT_DIS = 1
618 20:11:42.919460 NEW_8X_MODE = 1
619 20:11:42.922785 ===================================
620 20:11:42.926905 ===================================
621 20:11:42.929638 data_rate = 1600
622 20:11:42.933012 CKR = 1
623 20:11:42.935987 DQ_P2S_RATIO = 8
624 20:11:42.936150 ===================================
625 20:11:42.939519 CA_P2S_RATIO = 8
626 20:11:42.943582 DQ_CA_OPEN = 0
627 20:11:42.946198 DQ_SEMI_OPEN = 0
628 20:11:42.949771 CA_SEMI_OPEN = 0
629 20:11:42.953417 CA_FULL_RATE = 0
630 20:11:42.953515 DQ_CKDIV4_EN = 1
631 20:11:42.956834 CA_CKDIV4_EN = 1
632 20:11:42.960188 CA_PREDIV_EN = 0
633 20:11:42.963350 PH8_DLY = 0
634 20:11:42.966575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 20:11:42.969514 DQ_AAMCK_DIV = 4
636 20:11:42.969609 CA_AAMCK_DIV = 4
637 20:11:42.973338 CA_ADMCK_DIV = 4
638 20:11:42.976580 DQ_TRACK_CA_EN = 0
639 20:11:42.979899 CA_PICK = 800
640 20:11:42.983416 CA_MCKIO = 800
641 20:11:42.986770 MCKIO_SEMI = 0
642 20:11:42.986919 PLL_FREQ = 3068
643 20:11:42.990774 DQ_UI_PI_RATIO = 32
644 20:11:42.994282 CA_UI_PI_RATIO = 0
645 20:11:42.998569 ===================================
646 20:11:43.001610 ===================================
647 20:11:43.001716 memory_type:LPDDR4
648 20:11:43.005394 GP_NUM : 10
649 20:11:43.005492 SRAM_EN : 1
650 20:11:43.009181 MD32_EN : 0
651 20:11:43.013163 ===================================
652 20:11:43.013271 [ANA_INIT] >>>>>>>>>>>>>>
653 20:11:43.016489 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 20:11:43.020302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 20:11:43.024043 ===================================
656 20:11:43.027322 data_rate = 1600,PCW = 0X7600
657 20:11:43.030629 ===================================
658 20:11:43.034256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 20:11:43.037228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 20:11:43.043779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 20:11:43.050568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 20:11:43.054425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 20:11:43.057940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 20:11:43.058037 [ANA_INIT] flow start
665 20:11:43.061061 [ANA_INIT] PLL >>>>>>>>
666 20:11:43.064330 [ANA_INIT] PLL <<<<<<<<
667 20:11:43.064421 [ANA_INIT] MIDPI >>>>>>>>
668 20:11:43.067342 [ANA_INIT] MIDPI <<<<<<<<
669 20:11:43.071333 [ANA_INIT] DLL >>>>>>>>
670 20:11:43.071432 [ANA_INIT] flow end
671 20:11:43.074311 ============ LP4 DIFF to SE enter ============
672 20:11:43.081379 ============ LP4 DIFF to SE exit ============
673 20:11:43.081492 [ANA_INIT] <<<<<<<<<<<<<
674 20:11:43.084387 [Flow] Enable top DCM control >>>>>
675 20:11:43.087457 [Flow] Enable top DCM control <<<<<
676 20:11:43.090906 Enable DLL master slave shuffle
677 20:11:43.098313 ==============================================================
678 20:11:43.098469 Gating Mode config
679 20:11:43.104479 ==============================================================
680 20:11:43.107872 Config description:
681 20:11:43.114932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 20:11:43.120908 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 20:11:43.128582 SELPH_MODE 0: By rank 1: By Phase
684 20:11:43.134822 ==============================================================
685 20:11:43.134997 GAT_TRACK_EN = 1
686 20:11:43.137701 RX_GATING_MODE = 2
687 20:11:43.141419 RX_GATING_TRACK_MODE = 2
688 20:11:43.144812 SELPH_MODE = 1
689 20:11:43.148460 PICG_EARLY_EN = 1
690 20:11:43.151345 VALID_LAT_VALUE = 1
691 20:11:43.158186 ==============================================================
692 20:11:43.161438 Enter into Gating configuration >>>>
693 20:11:43.165266 Exit from Gating configuration <<<<
694 20:11:43.165400 Enter into DVFS_PRE_config >>>>>
695 20:11:43.178665 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 20:11:43.181718 Exit from DVFS_PRE_config <<<<<
697 20:11:43.185588 Enter into PICG configuration >>>>
698 20:11:43.188330 Exit from PICG configuration <<<<
699 20:11:43.188466 [RX_INPUT] configuration >>>>>
700 20:11:43.192244 [RX_INPUT] configuration <<<<<
701 20:11:43.198214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 20:11:43.202080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 20:11:43.208456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 20:11:43.216420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 20:11:43.223157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 20:11:43.225998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 20:11:43.233031 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 20:11:43.236253 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 20:11:43.239453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 20:11:43.242898 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 20:11:43.247023 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 20:11:43.253407 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 20:11:43.256674 ===================================
714 20:11:43.256776 LPDDR4 DRAM CONFIGURATION
715 20:11:43.260107 ===================================
716 20:11:43.263234 EX_ROW_EN[0] = 0x0
717 20:11:43.266674 EX_ROW_EN[1] = 0x0
718 20:11:43.266765 LP4Y_EN = 0x0
719 20:11:43.269634 WORK_FSP = 0x0
720 20:11:43.269722 WL = 0x2
721 20:11:43.273187 RL = 0x2
722 20:11:43.273277 BL = 0x2
723 20:11:43.276806 RPST = 0x0
724 20:11:43.276896 RD_PRE = 0x0
725 20:11:43.279892 WR_PRE = 0x1
726 20:11:43.279978 WR_PST = 0x0
727 20:11:43.283419 DBI_WR = 0x0
728 20:11:43.283506 DBI_RD = 0x0
729 20:11:43.286569 OTF = 0x1
730 20:11:43.290282 ===================================
731 20:11:43.293384 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 20:11:43.296661 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 20:11:43.303737 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 20:11:43.306573 ===================================
735 20:11:43.306698 LPDDR4 DRAM CONFIGURATION
736 20:11:43.310349 ===================================
737 20:11:43.314099 EX_ROW_EN[0] = 0x10
738 20:11:43.314227 EX_ROW_EN[1] = 0x0
739 20:11:43.316665 LP4Y_EN = 0x0
740 20:11:43.316752 WORK_FSP = 0x0
741 20:11:43.320210 WL = 0x2
742 20:11:43.323459 RL = 0x2
743 20:11:43.323572 BL = 0x2
744 20:11:43.326975 RPST = 0x0
745 20:11:43.327066 RD_PRE = 0x0
746 20:11:43.331359 WR_PRE = 0x1
747 20:11:43.331458 WR_PST = 0x0
748 20:11:43.333451 DBI_WR = 0x0
749 20:11:43.333538 DBI_RD = 0x0
750 20:11:43.337022 OTF = 0x1
751 20:11:43.340161 ===================================
752 20:11:43.343338 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 20:11:43.348952 nWR fixed to 40
754 20:11:43.352327 [ModeRegInit_LP4] CH0 RK0
755 20:11:43.352426 [ModeRegInit_LP4] CH0 RK1
756 20:11:43.355863 [ModeRegInit_LP4] CH1 RK0
757 20:11:43.358857 [ModeRegInit_LP4] CH1 RK1
758 20:11:43.358949 match AC timing 13
759 20:11:43.365481 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 20:11:43.368773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 20:11:43.372858 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 20:11:43.379405 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 20:11:43.382677 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 20:11:43.382777 [EMI DOE] emi_dcm 0
765 20:11:43.389162 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 20:11:43.389318 ==
767 20:11:43.392805 Dram Type= 6, Freq= 0, CH_0, rank 0
768 20:11:43.395879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 20:11:43.396015 ==
770 20:11:43.402645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 20:11:43.406100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 20:11:43.416348 [CA 0] Center 37 (7~68) winsize 62
773 20:11:43.419524 [CA 1] Center 37 (6~68) winsize 63
774 20:11:43.423777 [CA 2] Center 35 (5~66) winsize 62
775 20:11:43.426448 [CA 3] Center 34 (4~65) winsize 62
776 20:11:43.429727 [CA 4] Center 34 (3~65) winsize 63
777 20:11:43.433031 [CA 5] Center 33 (3~64) winsize 62
778 20:11:43.433172
779 20:11:43.436578 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 20:11:43.436714
781 20:11:43.439654 [CATrainingPosCal] consider 1 rank data
782 20:11:43.443372 u2DelayCellTimex100 = 270/100 ps
783 20:11:43.446715 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 20:11:43.449796 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 20:11:43.453140 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 20:11:43.460162 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 20:11:43.463417 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
788 20:11:43.467165 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 20:11:43.467273
790 20:11:43.470572 CA PerBit enable=1, Macro0, CA PI delay=33
791 20:11:43.470708
792 20:11:43.473250 [CBTSetCACLKResult] CA Dly = 33
793 20:11:43.473338 CS Dly: 5 (0~36)
794 20:11:43.473406 ==
795 20:11:43.477119 Dram Type= 6, Freq= 0, CH_0, rank 1
796 20:11:43.483380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 20:11:43.483488 ==
798 20:11:43.487157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 20:11:43.493599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 20:11:43.502596 [CA 0] Center 37 (6~68) winsize 63
801 20:11:43.505832 [CA 1] Center 37 (7~68) winsize 62
802 20:11:43.509397 [CA 2] Center 35 (5~66) winsize 62
803 20:11:43.513069 [CA 3] Center 35 (4~66) winsize 63
804 20:11:43.516007 [CA 4] Center 34 (3~65) winsize 63
805 20:11:43.519488 [CA 5] Center 33 (3~64) winsize 62
806 20:11:43.519584
807 20:11:43.522679 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 20:11:43.522769
809 20:11:43.526673 [CATrainingPosCal] consider 2 rank data
810 20:11:43.529940 u2DelayCellTimex100 = 270/100 ps
811 20:11:43.533679 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 20:11:43.536360 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 20:11:43.542943 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 20:11:43.546657 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 20:11:43.549344 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
816 20:11:43.552951 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 20:11:43.553049
818 20:11:43.556193 CA PerBit enable=1, Macro0, CA PI delay=33
819 20:11:43.556298
820 20:11:43.559854 [CBTSetCACLKResult] CA Dly = 33
821 20:11:43.559979 CS Dly: 6 (0~38)
822 20:11:43.560065
823 20:11:43.562998 ----->DramcWriteLeveling(PI) begin...
824 20:11:43.563091 ==
825 20:11:43.566231 Dram Type= 6, Freq= 0, CH_0, rank 0
826 20:11:43.573127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 20:11:43.573243 ==
828 20:11:43.577104 Write leveling (Byte 0): 29 => 29
829 20:11:43.577206 Write leveling (Byte 1): 29 => 29
830 20:11:43.581187 DramcWriteLeveling(PI) end<-----
831 20:11:43.581283
832 20:11:43.581351 ==
833 20:11:43.584763 Dram Type= 6, Freq= 0, CH_0, rank 0
834 20:11:43.587804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 20:11:43.587904 ==
836 20:11:43.590983 [Gating] SW mode calibration
837 20:11:43.597768 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 20:11:43.605364 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 20:11:43.608651 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 20:11:43.612078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 20:11:43.618262 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 20:11:43.621952 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 20:11:43.625475 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 20:11:43.632206 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 20:11:43.635314 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 20:11:43.639117 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 20:11:43.646149 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 20:11:43.648858 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 20:11:43.651995 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 20:11:43.655327 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 20:11:43.661780 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 20:11:43.665453 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 20:11:43.668616 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 20:11:43.675774 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 20:11:43.679081 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 20:11:43.682082 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 20:11:43.688817 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
858 20:11:43.692162 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:11:43.695574 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:11:43.701996 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:11:43.706108 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:11:43.709237 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:11:43.715443 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 20:11:43.719025 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 20:11:43.722164 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
866 20:11:43.725859 0 9 12 | B1->B0 | 2727 3131 | 0 1 | (0 0) (1 1)
867 20:11:43.732291 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 20:11:43.735637 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 20:11:43.738961 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 20:11:43.746258 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 20:11:43.749016 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 20:11:43.753297 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
873 20:11:43.759666 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
874 20:11:43.762429 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
875 20:11:43.766237 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 20:11:43.772460 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 20:11:43.776436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 20:11:43.779010 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 20:11:43.782622 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 20:11:43.789269 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 20:11:43.793207 0 11 8 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
882 20:11:43.796564 0 11 12 | B1->B0 | 3737 4141 | 1 0 | (0 0) (0 0)
883 20:11:43.803169 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 20:11:43.806796 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 20:11:43.809523 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 20:11:43.816095 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 20:11:43.819281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 20:11:43.823346 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 20:11:43.829705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 20:11:43.833044 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 20:11:43.836413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 20:11:43.839652 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 20:11:43.846870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 20:11:43.850294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 20:11:43.853635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 20:11:43.860150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 20:11:43.863109 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 20:11:43.866319 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 20:11:43.874380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 20:11:43.876744 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 20:11:43.880755 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 20:11:43.886492 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 20:11:43.890053 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 20:11:43.893280 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 20:11:43.900409 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 20:11:43.900551 Total UI for P1: 0, mck2ui 16
907 20:11:43.903438 best dqsien dly found for B0: ( 0, 14, 6)
908 20:11:43.910115 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 20:11:43.913358 Total UI for P1: 0, mck2ui 16
910 20:11:43.917017 best dqsien dly found for B1: ( 0, 14, 8)
911 20:11:43.920285 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
912 20:11:43.923992 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 20:11:43.924079
914 20:11:43.927993 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 20:11:43.931022 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 20:11:43.934313 [Gating] SW calibration Done
917 20:11:43.934408 ==
918 20:11:43.937252 Dram Type= 6, Freq= 0, CH_0, rank 0
919 20:11:43.940607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 20:11:43.940694 ==
921 20:11:43.943655 RX Vref Scan: 0
922 20:11:43.943759
923 20:11:43.943859 RX Vref 0 -> 0, step: 1
924 20:11:43.943937
925 20:11:43.946995 RX Delay -130 -> 252, step: 16
926 20:11:43.950170 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 20:11:43.956997 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 20:11:43.960702 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 20:11:43.965036 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 20:11:43.967465 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
931 20:11:43.970597 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 20:11:43.977224 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
933 20:11:43.980317 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
934 20:11:43.984208 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
935 20:11:43.987554 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
936 20:11:43.990338 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 20:11:43.994066 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
938 20:11:44.001035 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 20:11:44.003733 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
940 20:11:44.007499 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 20:11:44.011336 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 20:11:44.011471 ==
943 20:11:44.014367 Dram Type= 6, Freq= 0, CH_0, rank 0
944 20:11:44.021030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 20:11:44.021173 ==
946 20:11:44.021295 DQS Delay:
947 20:11:44.024474 DQS0 = 0, DQS1 = 0
948 20:11:44.024603 DQM Delay:
949 20:11:44.024718 DQM0 = 85, DQM1 = 79
950 20:11:44.027618 DQ Delay:
951 20:11:44.031161 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 20:11:44.034106 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
953 20:11:44.037696 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
954 20:11:44.041000 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
955 20:11:44.041127
956 20:11:44.041242
957 20:11:44.041353 ==
958 20:11:44.044287 Dram Type= 6, Freq= 0, CH_0, rank 0
959 20:11:44.047366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 20:11:44.047492 ==
961 20:11:44.047606
962 20:11:44.047717
963 20:11:44.051173 TX Vref Scan disable
964 20:11:44.051297 == TX Byte 0 ==
965 20:11:44.057511 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
966 20:11:44.061095 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
967 20:11:44.061224 == TX Byte 1 ==
968 20:11:44.067947 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
969 20:11:44.070883 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
970 20:11:44.071009 ==
971 20:11:44.074684 Dram Type= 6, Freq= 0, CH_0, rank 0
972 20:11:44.077663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 20:11:44.077786 ==
974 20:11:44.091727 TX Vref=22, minBit 0, minWin=27, winSum=437
975 20:11:44.094513 TX Vref=24, minBit 1, minWin=27, winSum=441
976 20:11:44.097821 TX Vref=26, minBit 8, minWin=27, winSum=446
977 20:11:44.101055 TX Vref=28, minBit 13, minWin=27, winSum=450
978 20:11:44.104670 TX Vref=30, minBit 12, minWin=27, winSum=449
979 20:11:44.111437 TX Vref=32, minBit 1, minWin=28, winSum=453
980 20:11:44.114916 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 32
981 20:11:44.115044
982 20:11:44.118761 Final TX Range 1 Vref 32
983 20:11:44.118887
984 20:11:44.119001 ==
985 20:11:44.121914 Dram Type= 6, Freq= 0, CH_0, rank 0
986 20:11:44.124800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 20:11:44.124925 ==
988 20:11:44.128176
989 20:11:44.128301
990 20:11:44.128414 TX Vref Scan disable
991 20:11:44.131604 == TX Byte 0 ==
992 20:11:44.134542 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
993 20:11:44.138097 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
994 20:11:44.141693 == TX Byte 1 ==
995 20:11:44.144638 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
996 20:11:44.148289 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
997 20:11:44.148411
998 20:11:44.151794 [DATLAT]
999 20:11:44.151916 Freq=800, CH0 RK0
1000 20:11:44.152029
1001 20:11:44.155379 DATLAT Default: 0xa
1002 20:11:44.155500 0, 0xFFFF, sum = 0
1003 20:11:44.158377 1, 0xFFFF, sum = 0
1004 20:11:44.158513 2, 0xFFFF, sum = 0
1005 20:11:44.161913 3, 0xFFFF, sum = 0
1006 20:11:44.162036 4, 0xFFFF, sum = 0
1007 20:11:44.164927 5, 0xFFFF, sum = 0
1008 20:11:44.165056 6, 0xFFFF, sum = 0
1009 20:11:44.168146 7, 0xFFFF, sum = 0
1010 20:11:44.168271 8, 0xFFFF, sum = 0
1011 20:11:44.172284 9, 0x0, sum = 1
1012 20:11:44.172407 10, 0x0, sum = 2
1013 20:11:44.175130 11, 0x0, sum = 3
1014 20:11:44.175256 12, 0x0, sum = 4
1015 20:11:44.178741 best_step = 10
1016 20:11:44.178863
1017 20:11:44.178975 ==
1018 20:11:44.181813 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 20:11:44.184821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 20:11:44.184943 ==
1021 20:11:44.188665 RX Vref Scan: 1
1022 20:11:44.188788
1023 20:11:44.188901 Set Vref Range= 32 -> 127
1024 20:11:44.189012
1025 20:11:44.192011 RX Vref 32 -> 127, step: 1
1026 20:11:44.192132
1027 20:11:44.195744 RX Delay -111 -> 252, step: 8
1028 20:11:44.195861
1029 20:11:44.198366 Set Vref, RX VrefLevel [Byte0]: 32
1030 20:11:44.202329 [Byte1]: 32
1031 20:11:44.202482
1032 20:11:44.205068 Set Vref, RX VrefLevel [Byte0]: 33
1033 20:11:44.208779 [Byte1]: 33
1034 20:11:44.212265
1035 20:11:44.212386 Set Vref, RX VrefLevel [Byte0]: 34
1036 20:11:44.215713 [Byte1]: 34
1037 20:11:44.219595
1038 20:11:44.219717 Set Vref, RX VrefLevel [Byte0]: 35
1039 20:11:44.222698 [Byte1]: 35
1040 20:11:44.226887
1041 20:11:44.227008 Set Vref, RX VrefLevel [Byte0]: 36
1042 20:11:44.230909 [Byte1]: 36
1043 20:11:44.235202
1044 20:11:44.235323 Set Vref, RX VrefLevel [Byte0]: 37
1045 20:11:44.238459 [Byte1]: 37
1046 20:11:44.243062
1047 20:11:44.243185 Set Vref, RX VrefLevel [Byte0]: 38
1048 20:11:44.246168 [Byte1]: 38
1049 20:11:44.250707
1050 20:11:44.250829 Set Vref, RX VrefLevel [Byte0]: 39
1051 20:11:44.253999 [Byte1]: 39
1052 20:11:44.258104
1053 20:11:44.258225 Set Vref, RX VrefLevel [Byte0]: 40
1054 20:11:44.261099 [Byte1]: 40
1055 20:11:44.265618
1056 20:11:44.265740 Set Vref, RX VrefLevel [Byte0]: 41
1057 20:11:44.269004 [Byte1]: 41
1058 20:11:44.273346
1059 20:11:44.273466 Set Vref, RX VrefLevel [Byte0]: 42
1060 20:11:44.276906 [Byte1]: 42
1061 20:11:44.280942
1062 20:11:44.281063 Set Vref, RX VrefLevel [Byte0]: 43
1063 20:11:44.283758 [Byte1]: 43
1064 20:11:44.288273
1065 20:11:44.288395 Set Vref, RX VrefLevel [Byte0]: 44
1066 20:11:44.291443 [Byte1]: 44
1067 20:11:44.295733
1068 20:11:44.295852 Set Vref, RX VrefLevel [Byte0]: 45
1069 20:11:44.299153 [Byte1]: 45
1070 20:11:44.304086
1071 20:11:44.304185 Set Vref, RX VrefLevel [Byte0]: 46
1072 20:11:44.307029 [Byte1]: 46
1073 20:11:44.311445
1074 20:11:44.311530 Set Vref, RX VrefLevel [Byte0]: 47
1075 20:11:44.314601 [Byte1]: 47
1076 20:11:44.318854
1077 20:11:44.318931 Set Vref, RX VrefLevel [Byte0]: 48
1078 20:11:44.322136 [Byte1]: 48
1079 20:11:44.327209
1080 20:11:44.327333 Set Vref, RX VrefLevel [Byte0]: 49
1081 20:11:44.329751 [Byte1]: 49
1082 20:11:44.334001
1083 20:11:44.334083 Set Vref, RX VrefLevel [Byte0]: 50
1084 20:11:44.337380 [Byte1]: 50
1085 20:11:44.341934
1086 20:11:44.342016 Set Vref, RX VrefLevel [Byte0]: 51
1087 20:11:44.345466 [Byte1]: 51
1088 20:11:44.349787
1089 20:11:44.349868 Set Vref, RX VrefLevel [Byte0]: 52
1090 20:11:44.353022 [Byte1]: 52
1091 20:11:44.357055
1092 20:11:44.357136 Set Vref, RX VrefLevel [Byte0]: 53
1093 20:11:44.360331 [Byte1]: 53
1094 20:11:44.365434
1095 20:11:44.365515 Set Vref, RX VrefLevel [Byte0]: 54
1096 20:11:44.368592 [Byte1]: 54
1097 20:11:44.372822
1098 20:11:44.372922 Set Vref, RX VrefLevel [Byte0]: 55
1099 20:11:44.376035 [Byte1]: 55
1100 20:11:44.380022
1101 20:11:44.380102 Set Vref, RX VrefLevel [Byte0]: 56
1102 20:11:44.383305 [Byte1]: 56
1103 20:11:44.388571
1104 20:11:44.388653 Set Vref, RX VrefLevel [Byte0]: 57
1105 20:11:44.390868 [Byte1]: 57
1106 20:11:44.395735
1107 20:11:44.395822 Set Vref, RX VrefLevel [Byte0]: 58
1108 20:11:44.398739 [Byte1]: 58
1109 20:11:44.402749
1110 20:11:44.402830 Set Vref, RX VrefLevel [Byte0]: 59
1111 20:11:44.406320 [Byte1]: 59
1112 20:11:44.411207
1113 20:11:44.411289 Set Vref, RX VrefLevel [Byte0]: 60
1114 20:11:44.413943 [Byte1]: 60
1115 20:11:44.418543
1116 20:11:44.418651 Set Vref, RX VrefLevel [Byte0]: 61
1117 20:11:44.421492 [Byte1]: 61
1118 20:11:44.425668
1119 20:11:44.425797 Set Vref, RX VrefLevel [Byte0]: 62
1120 20:11:44.429062 [Byte1]: 62
1121 20:11:44.433907
1122 20:11:44.433989 Set Vref, RX VrefLevel [Byte0]: 63
1123 20:11:44.436895 [Byte1]: 63
1124 20:11:44.441364
1125 20:11:44.441485 Set Vref, RX VrefLevel [Byte0]: 64
1126 20:11:44.444982 [Byte1]: 64
1127 20:11:44.448857
1128 20:11:44.448939 Set Vref, RX VrefLevel [Byte0]: 65
1129 20:11:44.452265 [Byte1]: 65
1130 20:11:44.456163
1131 20:11:44.459637 Set Vref, RX VrefLevel [Byte0]: 66
1132 20:11:44.459736 [Byte1]: 66
1133 20:11:44.464140
1134 20:11:44.464222 Set Vref, RX VrefLevel [Byte0]: 67
1135 20:11:44.467253 [Byte1]: 67
1136 20:11:44.472067
1137 20:11:44.472150 Set Vref, RX VrefLevel [Byte0]: 68
1138 20:11:44.475304 [Byte1]: 68
1139 20:11:44.480668
1140 20:11:44.480811 Set Vref, RX VrefLevel [Byte0]: 69
1141 20:11:44.483195 [Byte1]: 69
1142 20:11:44.487598
1143 20:11:44.487697 Set Vref, RX VrefLevel [Byte0]: 70
1144 20:11:44.490914 [Byte1]: 70
1145 20:11:44.494690
1146 20:11:44.494789 Set Vref, RX VrefLevel [Byte0]: 71
1147 20:11:44.498498 [Byte1]: 71
1148 20:11:44.502154
1149 20:11:44.502257 Set Vref, RX VrefLevel [Byte0]: 72
1150 20:11:44.505467 [Byte1]: 72
1151 20:11:44.510358
1152 20:11:44.510478 Set Vref, RX VrefLevel [Byte0]: 73
1153 20:11:44.514265 [Byte1]: 73
1154 20:11:44.517431
1155 20:11:44.517529 Set Vref, RX VrefLevel [Byte0]: 74
1156 20:11:44.521095 [Byte1]: 74
1157 20:11:44.525392
1158 20:11:44.525476 Set Vref, RX VrefLevel [Byte0]: 75
1159 20:11:44.528359 [Byte1]: 75
1160 20:11:44.532682
1161 20:11:44.532769 Set Vref, RX VrefLevel [Byte0]: 76
1162 20:11:44.536736 [Byte1]: 76
1163 20:11:44.540585
1164 20:11:44.540668 Set Vref, RX VrefLevel [Byte0]: 77
1165 20:11:44.543869 [Byte1]: 77
1166 20:11:44.548003
1167 20:11:44.548089 Final RX Vref Byte 0 = 62 to rank0
1168 20:11:44.551909 Final RX Vref Byte 1 = 56 to rank0
1169 20:11:44.555077 Final RX Vref Byte 0 = 62 to rank1
1170 20:11:44.558571 Final RX Vref Byte 1 = 56 to rank1==
1171 20:11:44.562295 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 20:11:44.565215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 20:11:44.568292 ==
1174 20:11:44.568376 DQS Delay:
1175 20:11:44.568442 DQS0 = 0, DQS1 = 0
1176 20:11:44.571498 DQM Delay:
1177 20:11:44.571582 DQM0 = 87, DQM1 = 80
1178 20:11:44.575542 DQ Delay:
1179 20:11:44.575628 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1180 20:11:44.578393 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1181 20:11:44.581948 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1182 20:11:44.585386 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1183 20:11:44.585472
1184 20:11:44.588732
1185 20:11:44.594861 [DQSOSCAuto] RK0, (LSB)MR18= 0x240b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 400 ps
1186 20:11:44.598567 CH0 RK0: MR19=606, MR18=240B
1187 20:11:44.605490 CH0_RK0: MR19=0x606, MR18=0x240B, DQSOSC=400, MR23=63, INC=92, DEC=61
1188 20:11:44.605588
1189 20:11:44.608242 ----->DramcWriteLeveling(PI) begin...
1190 20:11:44.608328 ==
1191 20:11:44.611786 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 20:11:44.614873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 20:11:44.614999 ==
1194 20:11:44.618294 Write leveling (Byte 0): 30 => 30
1195 20:11:44.622265 Write leveling (Byte 1): 29 => 29
1196 20:11:44.625406 DramcWriteLeveling(PI) end<-----
1197 20:11:44.625492
1198 20:11:44.625557 ==
1199 20:11:44.628910 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 20:11:44.631940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 20:11:44.632029 ==
1202 20:11:44.635340 [Gating] SW mode calibration
1203 20:11:44.642327 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 20:11:44.649150 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 20:11:44.693159 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 20:11:44.693318 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1207 20:11:44.693719 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1208 20:11:44.694300 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1209 20:11:44.694635 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 20:11:44.695011 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 20:11:44.695093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 20:11:44.695369 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 20:11:44.697181 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 20:11:44.697710 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 20:11:44.737191 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 20:11:44.737350 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 20:11:44.737706 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 20:11:44.738248 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 20:11:44.739008 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 20:11:44.739316 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 20:11:44.739398 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1222 20:11:44.739565 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1223 20:11:44.739745 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1224 20:11:44.740030 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 20:11:44.754030 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 20:11:44.754272 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 20:11:44.754579 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 20:11:44.754665 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 20:11:44.757079 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 20:11:44.760636 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1231 20:11:44.767977 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
1232 20:11:44.771250 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1233 20:11:44.774271 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 20:11:44.777259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 20:11:44.784556 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 20:11:44.787482 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 20:11:44.791148 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 20:11:44.797661 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1239 20:11:44.801009 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
1240 20:11:44.804675 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1241 20:11:44.811085 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 20:11:44.814435 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 20:11:44.817910 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 20:11:44.821001 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 20:11:44.828772 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 20:11:44.832164 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1247 20:11:44.835956 0 11 8 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
1248 20:11:44.839288 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1249 20:11:44.846097 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 20:11:44.849609 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 20:11:44.853752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 20:11:44.857400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 20:11:44.863904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 20:11:44.867008 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1255 20:11:44.870266 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1256 20:11:44.877124 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 20:11:44.880748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 20:11:44.883784 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 20:11:44.887262 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 20:11:44.894205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 20:11:44.897356 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 20:11:44.901214 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 20:11:44.907297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 20:11:44.910850 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 20:11:44.914228 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 20:11:44.920826 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 20:11:44.924492 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 20:11:44.927707 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 20:11:44.934180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 20:11:44.937923 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1271 20:11:44.941504 Total UI for P1: 0, mck2ui 16
1272 20:11:44.944220 best dqsien dly found for B0: ( 0, 14, 2)
1273 20:11:44.947533 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1274 20:11:44.950726 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 20:11:44.954718 Total UI for P1: 0, mck2ui 16
1276 20:11:44.957756 best dqsien dly found for B1: ( 0, 14, 8)
1277 20:11:44.961184 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1278 20:11:44.964757 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1279 20:11:44.964841
1280 20:11:44.971102 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1281 20:11:44.974660 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 20:11:44.974771 [Gating] SW calibration Done
1283 20:11:44.977867 ==
1284 20:11:44.981584 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 20:11:44.984349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 20:11:44.984433 ==
1287 20:11:44.984515 RX Vref Scan: 0
1288 20:11:44.984607
1289 20:11:44.988013 RX Vref 0 -> 0, step: 1
1290 20:11:44.988095
1291 20:11:44.991224 RX Delay -130 -> 252, step: 16
1292 20:11:44.995069 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1293 20:11:44.998029 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 20:11:45.004196 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1295 20:11:45.008486 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1296 20:11:45.011204 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1297 20:11:45.014634 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1298 20:11:45.018232 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1299 20:11:45.021418 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1300 20:11:45.027745 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1301 20:11:45.031564 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1302 20:11:45.035272 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1303 20:11:45.037730 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1304 20:11:45.041357 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1305 20:11:45.047883 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1306 20:11:45.051663 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1307 20:11:45.055230 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1308 20:11:45.055317 ==
1309 20:11:45.058144 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 20:11:45.061322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 20:11:45.061407 ==
1312 20:11:45.065146 DQS Delay:
1313 20:11:45.065231 DQS0 = 0, DQS1 = 0
1314 20:11:45.068001 DQM Delay:
1315 20:11:45.068084 DQM0 = 87, DQM1 = 79
1316 20:11:45.068149 DQ Delay:
1317 20:11:45.072118 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1318 20:11:45.074848 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1319 20:11:45.078452 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1320 20:11:45.081726 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1321 20:11:45.081812
1322 20:11:45.081878
1323 20:11:45.081938 ==
1324 20:11:45.085201 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 20:11:45.091616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 20:11:45.091774 ==
1327 20:11:45.091846
1328 20:11:45.091907
1329 20:11:45.091964 TX Vref Scan disable
1330 20:11:45.095712 == TX Byte 0 ==
1331 20:11:45.098850 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1332 20:11:45.102569 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1333 20:11:45.105652 == TX Byte 1 ==
1334 20:11:45.108792 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1335 20:11:45.112357 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1336 20:11:45.115477 ==
1337 20:11:45.115564 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 20:11:45.123340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 20:11:45.123483 ==
1340 20:11:45.134669 TX Vref=22, minBit 2, minWin=27, winSum=441
1341 20:11:45.138266 TX Vref=24, minBit 3, minWin=27, winSum=446
1342 20:11:45.141850 TX Vref=26, minBit 2, minWin=27, winSum=445
1343 20:11:45.144567 TX Vref=28, minBit 6, minWin=27, winSum=452
1344 20:11:45.148057 TX Vref=30, minBit 0, minWin=28, winSum=453
1345 20:11:45.151236 TX Vref=32, minBit 0, minWin=28, winSum=451
1346 20:11:45.158159 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1347 20:11:45.158258
1348 20:11:45.161151 Final TX Range 1 Vref 30
1349 20:11:45.161235
1350 20:11:45.161303 ==
1351 20:11:45.164981 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 20:11:45.168132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 20:11:45.168220 ==
1354 20:11:45.168286
1355 20:11:45.171636
1356 20:11:45.171716 TX Vref Scan disable
1357 20:11:45.175076 == TX Byte 0 ==
1358 20:11:45.177933 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 20:11:45.181540 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 20:11:45.184831 == TX Byte 1 ==
1361 20:11:45.188190 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1362 20:11:45.191752 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1363 20:11:45.195081
1364 20:11:45.195166 [DATLAT]
1365 20:11:45.195230 Freq=800, CH0 RK1
1366 20:11:45.195291
1367 20:11:45.198145 DATLAT Default: 0xa
1368 20:11:45.198254 0, 0xFFFF, sum = 0
1369 20:11:45.201629 1, 0xFFFF, sum = 0
1370 20:11:45.201738 2, 0xFFFF, sum = 0
1371 20:11:45.204556 3, 0xFFFF, sum = 0
1372 20:11:45.204641 4, 0xFFFF, sum = 0
1373 20:11:45.208363 5, 0xFFFF, sum = 0
1374 20:11:45.208446 6, 0xFFFF, sum = 0
1375 20:11:45.211201 7, 0xFFFF, sum = 0
1376 20:11:45.211284 8, 0xFFFF, sum = 0
1377 20:11:45.214879 9, 0x0, sum = 1
1378 20:11:45.214964 10, 0x0, sum = 2
1379 20:11:45.218448 11, 0x0, sum = 3
1380 20:11:45.218533 12, 0x0, sum = 4
1381 20:11:45.221886 best_step = 10
1382 20:11:45.221968
1383 20:11:45.222032 ==
1384 20:11:45.225139 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 20:11:45.229019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 20:11:45.229102 ==
1387 20:11:45.231597 RX Vref Scan: 0
1388 20:11:45.231678
1389 20:11:45.231743 RX Vref 0 -> 0, step: 1
1390 20:11:45.231805
1391 20:11:45.234940 RX Delay -111 -> 252, step: 8
1392 20:11:45.241440 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1393 20:11:45.245519 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1394 20:11:45.248534 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1395 20:11:45.251808 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1396 20:11:45.255099 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1397 20:11:45.262114 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1398 20:11:45.265410 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1399 20:11:45.268722 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1400 20:11:45.271679 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1401 20:11:45.275043 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1402 20:11:45.278402 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1403 20:11:45.284936 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1404 20:11:45.289063 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1405 20:11:45.292021 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1406 20:11:45.295026 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1407 20:11:45.301916 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1408 20:11:45.302014 ==
1409 20:11:45.305304 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 20:11:45.308440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 20:11:45.308523 ==
1412 20:11:45.308589 DQS Delay:
1413 20:11:45.311992 DQS0 = 0, DQS1 = 0
1414 20:11:45.312075 DQM Delay:
1415 20:11:45.315606 DQM0 = 87, DQM1 = 78
1416 20:11:45.315688 DQ Delay:
1417 20:11:45.318962 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1418 20:11:45.322160 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1419 20:11:45.325405 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1420 20:11:45.328660 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1421 20:11:45.328742
1422 20:11:45.328806
1423 20:11:45.336102 [DQSOSCAuto] RK1, (LSB)MR18= 0x331c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1424 20:11:45.339138 CH0 RK1: MR19=606, MR18=331C
1425 20:11:45.345854 CH0_RK1: MR19=0x606, MR18=0x331C, DQSOSC=396, MR23=63, INC=94, DEC=62
1426 20:11:45.348480 [RxdqsGatingPostProcess] freq 800
1427 20:11:45.351861 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 20:11:45.355220 Pre-setting of DQS Precalculation
1429 20:11:45.362328 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 20:11:45.362469 ==
1431 20:11:45.366171 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 20:11:45.369166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 20:11:45.369250 ==
1434 20:11:45.375900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 20:11:45.382259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 20:11:45.390149 [CA 0] Center 36 (6~67) winsize 62
1437 20:11:45.392926 [CA 1] Center 36 (5~67) winsize 63
1438 20:11:45.396398 [CA 2] Center 34 (4~64) winsize 61
1439 20:11:45.399662 [CA 3] Center 33 (3~64) winsize 62
1440 20:11:45.403134 [CA 4] Center 34 (3~65) winsize 63
1441 20:11:45.406078 [CA 5] Center 33 (3~64) winsize 62
1442 20:11:45.406203
1443 20:11:45.409470 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1444 20:11:45.409554
1445 20:11:45.413190 [CATrainingPosCal] consider 1 rank data
1446 20:11:45.417159 u2DelayCellTimex100 = 270/100 ps
1447 20:11:45.419855 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1448 20:11:45.423309 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1449 20:11:45.427361 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1450 20:11:45.432954 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1451 20:11:45.436903 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1452 20:11:45.440052 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1453 20:11:45.440135
1454 20:11:45.443176 CA PerBit enable=1, Macro0, CA PI delay=33
1455 20:11:45.443259
1456 20:11:45.446876 [CBTSetCACLKResult] CA Dly = 33
1457 20:11:45.446958 CS Dly: 4 (0~35)
1458 20:11:45.447024 ==
1459 20:11:45.449736 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 20:11:45.456652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 20:11:45.456736 ==
1462 20:11:45.460651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 20:11:45.467204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 20:11:45.476236 [CA 0] Center 36 (5~67) winsize 63
1465 20:11:45.479009 [CA 1] Center 36 (5~67) winsize 63
1466 20:11:45.482710 [CA 2] Center 34 (4~64) winsize 61
1467 20:11:45.485900 [CA 3] Center 33 (3~64) winsize 62
1468 20:11:45.489745 [CA 4] Center 34 (3~65) winsize 63
1469 20:11:45.493422 [CA 5] Center 33 (3~64) winsize 62
1470 20:11:45.493505
1471 20:11:45.496897 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1472 20:11:45.496980
1473 20:11:45.500804 [CATrainingPosCal] consider 2 rank data
1474 20:11:45.504630 u2DelayCellTimex100 = 270/100 ps
1475 20:11:45.508350 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1476 20:11:45.511970 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1477 20:11:45.516307 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1478 20:11:45.519433 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1479 20:11:45.523188 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1480 20:11:45.523279 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1481 20:11:45.523346
1482 20:11:45.530488 CA PerBit enable=1, Macro0, CA PI delay=33
1483 20:11:45.530580
1484 20:11:45.530646 [CBTSetCACLKResult] CA Dly = 33
1485 20:11:45.533726 CS Dly: 4 (0~36)
1486 20:11:45.533815
1487 20:11:45.537003 ----->DramcWriteLeveling(PI) begin...
1488 20:11:45.537094 ==
1489 20:11:45.540600 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 20:11:45.543628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 20:11:45.543716 ==
1492 20:11:45.547061 Write leveling (Byte 0): 27 => 27
1493 20:11:45.550176 Write leveling (Byte 1): 28 => 28
1494 20:11:45.553591 DramcWriteLeveling(PI) end<-----
1495 20:11:45.553676
1496 20:11:45.553743 ==
1497 20:11:45.557018 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 20:11:45.560281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 20:11:45.563749 ==
1500 20:11:45.563833 [Gating] SW mode calibration
1501 20:11:45.570469 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 20:11:45.577239 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 20:11:45.580541 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 20:11:45.587195 0 6 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (1 1)
1505 20:11:45.590781 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1506 20:11:45.594024 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 20:11:45.600461 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 20:11:45.604017 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 20:11:45.607204 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 20:11:45.610549 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 20:11:45.617654 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 20:11:45.621396 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 20:11:45.623915 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 20:11:45.630695 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 20:11:45.634220 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 20:11:45.638069 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 20:11:45.643901 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 20:11:45.647506 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 20:11:45.650730 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 20:11:45.657253 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1521 20:11:45.661460 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1522 20:11:45.664219 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 20:11:45.668176 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 20:11:45.674599 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 20:11:45.677885 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 20:11:45.681496 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 20:11:45.688057 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 20:11:45.691241 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 20:11:45.694999 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1530 20:11:45.700784 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 20:11:45.704250 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1532 20:11:45.707862 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 20:11:45.714298 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 20:11:45.717826 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 20:11:45.721226 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 20:11:45.728114 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1537 20:11:45.731482 0 10 8 | B1->B0 | 2c2c 2f2f | 0 0 | (1 0) (1 0)
1538 20:11:45.735074 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 20:11:45.738533 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 20:11:45.745690 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 20:11:45.748069 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 20:11:45.751388 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 20:11:45.757943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 20:11:45.761491 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 20:11:45.765285 0 11 8 | B1->B0 | 3535 3030 | 0 0 | (0 0) (0 0)
1546 20:11:45.771366 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 20:11:45.775317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 20:11:45.778669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 20:11:45.784906 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 20:11:45.788455 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 20:11:45.791539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 20:11:45.798125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 20:11:45.801510 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1554 20:11:45.804863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 20:11:45.808535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 20:11:45.815440 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 20:11:45.818414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 20:11:45.821665 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 20:11:45.828165 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 20:11:45.831718 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 20:11:45.834885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 20:11:45.842390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 20:11:45.845141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 20:11:45.848372 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 20:11:45.855124 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 20:11:45.858692 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 20:11:45.861984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 20:11:45.865246 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 20:11:45.872075 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1570 20:11:45.876200 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 20:11:45.878737 Total UI for P1: 0, mck2ui 16
1572 20:11:45.881971 best dqsien dly found for B0: ( 0, 14, 8)
1573 20:11:45.886285 Total UI for P1: 0, mck2ui 16
1574 20:11:45.889072 best dqsien dly found for B1: ( 0, 14, 8)
1575 20:11:45.892000 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1576 20:11:45.895811 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1577 20:11:45.895903
1578 20:11:45.898740 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1579 20:11:45.902559 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1580 20:11:45.905653 [Gating] SW calibration Done
1581 20:11:45.905741 ==
1582 20:11:45.909996 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 20:11:45.912474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 20:11:45.912560 ==
1585 20:11:45.915552 RX Vref Scan: 0
1586 20:11:45.915637
1587 20:11:45.919374 RX Vref 0 -> 0, step: 1
1588 20:11:45.919458
1589 20:11:45.919524 RX Delay -130 -> 252, step: 16
1590 20:11:45.926154 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1591 20:11:45.929440 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1592 20:11:45.932918 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1593 20:11:45.936225 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1594 20:11:45.939520 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1595 20:11:45.946228 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1596 20:11:45.949657 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1597 20:11:45.953214 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1598 20:11:45.956415 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1599 20:11:45.959953 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1600 20:11:45.962970 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1601 20:11:45.969979 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1602 20:11:45.973138 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1603 20:11:45.976338 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1604 20:11:45.979776 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1605 20:11:45.986411 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1606 20:11:45.986520 ==
1607 20:11:45.989745 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 20:11:45.993245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 20:11:45.993350 ==
1610 20:11:45.993449 DQS Delay:
1611 20:11:45.996705 DQS0 = 0, DQS1 = 0
1612 20:11:45.996789 DQM Delay:
1613 20:11:46.000037 DQM0 = 83, DQM1 = 76
1614 20:11:46.000121 DQ Delay:
1615 20:11:46.003454 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1616 20:11:46.006470 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1617 20:11:46.010510 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1618 20:11:46.013484 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1619 20:11:46.013570
1620 20:11:46.013636
1621 20:11:46.013697 ==
1622 20:11:46.016696 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 20:11:46.020269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 20:11:46.020353 ==
1625 20:11:46.020419
1626 20:11:46.020480
1627 20:11:46.022998 TX Vref Scan disable
1628 20:11:46.027042 == TX Byte 0 ==
1629 20:11:46.030133 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1630 20:11:46.033514 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1631 20:11:46.033595 == TX Byte 1 ==
1632 20:11:46.041597 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1633 20:11:46.044337 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1634 20:11:46.044441 ==
1635 20:11:46.046996 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 20:11:46.050218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 20:11:46.050330 ==
1638 20:11:46.064308 TX Vref=22, minBit 9, minWin=26, winSum=434
1639 20:11:46.068164 TX Vref=24, minBit 8, minWin=26, winSum=438
1640 20:11:46.071613 TX Vref=26, minBit 0, minWin=27, winSum=444
1641 20:11:46.075577 TX Vref=28, minBit 10, minWin=27, winSum=452
1642 20:11:46.078437 TX Vref=30, minBit 13, minWin=27, winSum=451
1643 20:11:46.081441 TX Vref=32, minBit 10, minWin=27, winSum=451
1644 20:11:46.088652 [TxChooseVref] Worse bit 10, Min win 27, Win sum 452, Final Vref 28
1645 20:11:46.088776
1646 20:11:46.091691 Final TX Range 1 Vref 28
1647 20:11:46.091769
1648 20:11:46.091831 ==
1649 20:11:46.095217 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 20:11:46.098355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 20:11:46.098456 ==
1652 20:11:46.098519
1653 20:11:46.098577
1654 20:11:46.101660 TX Vref Scan disable
1655 20:11:46.105081 == TX Byte 0 ==
1656 20:11:46.108447 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1657 20:11:46.112940 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1658 20:11:46.116234 == TX Byte 1 ==
1659 20:11:46.118968 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1660 20:11:46.121935 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1661 20:11:46.122022
1662 20:11:46.125430 [DATLAT]
1663 20:11:46.125574 Freq=800, CH1 RK0
1664 20:11:46.125735
1665 20:11:46.128605 DATLAT Default: 0xa
1666 20:11:46.128691 0, 0xFFFF, sum = 0
1667 20:11:46.132085 1, 0xFFFF, sum = 0
1668 20:11:46.132172 2, 0xFFFF, sum = 0
1669 20:11:46.135277 3, 0xFFFF, sum = 0
1670 20:11:46.135379 4, 0xFFFF, sum = 0
1671 20:11:46.138497 5, 0xFFFF, sum = 0
1672 20:11:46.138581 6, 0xFFFF, sum = 0
1673 20:11:46.142063 7, 0xFFFF, sum = 0
1674 20:11:46.142196 8, 0xFFFF, sum = 0
1675 20:11:46.145291 9, 0x0, sum = 1
1676 20:11:46.145393 10, 0x0, sum = 2
1677 20:11:46.148769 11, 0x0, sum = 3
1678 20:11:46.148872 12, 0x0, sum = 4
1679 20:11:46.148971 best_step = 10
1680 20:11:46.151955
1681 20:11:46.152054 ==
1682 20:11:46.155607 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 20:11:46.158557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 20:11:46.158665 ==
1685 20:11:46.158754 RX Vref Scan: 1
1686 20:11:46.158856
1687 20:11:46.162215 Set Vref Range= 32 -> 127
1688 20:11:46.162334
1689 20:11:46.165546 RX Vref 32 -> 127, step: 1
1690 20:11:46.165659
1691 20:11:46.168670 RX Delay -111 -> 252, step: 8
1692 20:11:46.168769
1693 20:11:46.172261 Set Vref, RX VrefLevel [Byte0]: 32
1694 20:11:46.175726 [Byte1]: 32
1695 20:11:46.175828
1696 20:11:46.180382 Set Vref, RX VrefLevel [Byte0]: 33
1697 20:11:46.182232 [Byte1]: 33
1698 20:11:46.182346
1699 20:11:46.185642 Set Vref, RX VrefLevel [Byte0]: 34
1700 20:11:46.189041 [Byte1]: 34
1701 20:11:46.192731
1702 20:11:46.192873 Set Vref, RX VrefLevel [Byte0]: 35
1703 20:11:46.196177 [Byte1]: 35
1704 20:11:46.200050
1705 20:11:46.200161 Set Vref, RX VrefLevel [Byte0]: 36
1706 20:11:46.204507 [Byte1]: 36
1707 20:11:46.207765
1708 20:11:46.207881 Set Vref, RX VrefLevel [Byte0]: 37
1709 20:11:46.211261 [Byte1]: 37
1710 20:11:46.215670
1711 20:11:46.215780 Set Vref, RX VrefLevel [Byte0]: 38
1712 20:11:46.219238 [Byte1]: 38
1713 20:11:46.223463
1714 20:11:46.223573 Set Vref, RX VrefLevel [Byte0]: 39
1715 20:11:46.226974 [Byte1]: 39
1716 20:11:46.231184
1717 20:11:46.231293 Set Vref, RX VrefLevel [Byte0]: 40
1718 20:11:46.234369 [Byte1]: 40
1719 20:11:46.238271
1720 20:11:46.238373 Set Vref, RX VrefLevel [Byte0]: 41
1721 20:11:46.241550 [Byte1]: 41
1722 20:11:46.245890
1723 20:11:46.245992 Set Vref, RX VrefLevel [Byte0]: 42
1724 20:11:46.250242 [Byte1]: 42
1725 20:11:46.253458
1726 20:11:46.253561 Set Vref, RX VrefLevel [Byte0]: 43
1727 20:11:46.257182 [Byte1]: 43
1728 20:11:46.262050
1729 20:11:46.262162 Set Vref, RX VrefLevel [Byte0]: 44
1730 20:11:46.264771 [Byte1]: 44
1731 20:11:46.268862
1732 20:11:46.268970 Set Vref, RX VrefLevel [Byte0]: 45
1733 20:11:46.272444 [Byte1]: 45
1734 20:11:46.277067
1735 20:11:46.277157 Set Vref, RX VrefLevel [Byte0]: 46
1736 20:11:46.280123 [Byte1]: 46
1737 20:11:46.284754
1738 20:11:46.284837 Set Vref, RX VrefLevel [Byte0]: 47
1739 20:11:46.287745 [Byte1]: 47
1740 20:11:46.292353
1741 20:11:46.292440 Set Vref, RX VrefLevel [Byte0]: 48
1742 20:11:46.295736 [Byte1]: 48
1743 20:11:46.299916
1744 20:11:46.300002 Set Vref, RX VrefLevel [Byte0]: 49
1745 20:11:46.302997 [Byte1]: 49
1746 20:11:46.307311
1747 20:11:46.307396 Set Vref, RX VrefLevel [Byte0]: 50
1748 20:11:46.310275 [Byte1]: 50
1749 20:11:46.314661
1750 20:11:46.314776 Set Vref, RX VrefLevel [Byte0]: 51
1751 20:11:46.318460 [Byte1]: 51
1752 20:11:46.322514
1753 20:11:46.322616 Set Vref, RX VrefLevel [Byte0]: 52
1754 20:11:46.325519 [Byte1]: 52
1755 20:11:46.330154
1756 20:11:46.330276 Set Vref, RX VrefLevel [Byte0]: 53
1757 20:11:46.333756 [Byte1]: 53
1758 20:11:46.337646
1759 20:11:46.337768 Set Vref, RX VrefLevel [Byte0]: 54
1760 20:11:46.341273 [Byte1]: 54
1761 20:11:46.345304
1762 20:11:46.345429 Set Vref, RX VrefLevel [Byte0]: 55
1763 20:11:46.348547 [Byte1]: 55
1764 20:11:46.353656
1765 20:11:46.353764 Set Vref, RX VrefLevel [Byte0]: 56
1766 20:11:46.356318 [Byte1]: 56
1767 20:11:46.360724
1768 20:11:46.360838 Set Vref, RX VrefLevel [Byte0]: 57
1769 20:11:46.364136 [Byte1]: 57
1770 20:11:46.368151
1771 20:11:46.368250 Set Vref, RX VrefLevel [Byte0]: 58
1772 20:11:46.371932 [Byte1]: 58
1773 20:11:46.376315
1774 20:11:46.376411 Set Vref, RX VrefLevel [Byte0]: 59
1775 20:11:46.379414 [Byte1]: 59
1776 20:11:46.383664
1777 20:11:46.383774 Set Vref, RX VrefLevel [Byte0]: 60
1778 20:11:46.386729 [Byte1]: 60
1779 20:11:46.391283
1780 20:11:46.391394 Set Vref, RX VrefLevel [Byte0]: 61
1781 20:11:46.394376 [Byte1]: 61
1782 20:11:46.398970
1783 20:11:46.399082 Set Vref, RX VrefLevel [Byte0]: 62
1784 20:11:46.402924 [Byte1]: 62
1785 20:11:46.406473
1786 20:11:46.406593 Set Vref, RX VrefLevel [Byte0]: 63
1787 20:11:46.409832 [Byte1]: 63
1788 20:11:46.414098
1789 20:11:46.414219 Set Vref, RX VrefLevel [Byte0]: 64
1790 20:11:46.417728 [Byte1]: 64
1791 20:11:46.422292
1792 20:11:46.422413 Set Vref, RX VrefLevel [Byte0]: 65
1793 20:11:46.425617 [Byte1]: 65
1794 20:11:46.429739
1795 20:11:46.429853 Set Vref, RX VrefLevel [Byte0]: 66
1796 20:11:46.432913 [Byte1]: 66
1797 20:11:46.437699
1798 20:11:46.437819 Set Vref, RX VrefLevel [Byte0]: 67
1799 20:11:46.440440 [Byte1]: 67
1800 20:11:46.444921
1801 20:11:46.445035 Set Vref, RX VrefLevel [Byte0]: 68
1802 20:11:46.448908 [Byte1]: 68
1803 20:11:46.452493
1804 20:11:46.452609 Set Vref, RX VrefLevel [Byte0]: 69
1805 20:11:46.456269 [Byte1]: 69
1806 20:11:46.460199
1807 20:11:46.460312 Set Vref, RX VrefLevel [Byte0]: 70
1808 20:11:46.463742 [Byte1]: 70
1809 20:11:46.468413
1810 20:11:46.468498 Set Vref, RX VrefLevel [Byte0]: 71
1811 20:11:46.471516 [Byte1]: 71
1812 20:11:46.475991
1813 20:11:46.476080 Set Vref, RX VrefLevel [Byte0]: 72
1814 20:11:46.479089 [Byte1]: 72
1815 20:11:46.483003
1816 20:11:46.483091 Set Vref, RX VrefLevel [Byte0]: 73
1817 20:11:46.486522 [Byte1]: 73
1818 20:11:46.491350
1819 20:11:46.491444 Set Vref, RX VrefLevel [Byte0]: 74
1820 20:11:46.494185 [Byte1]: 74
1821 20:11:46.498484
1822 20:11:46.498600 Set Vref, RX VrefLevel [Byte0]: 75
1823 20:11:46.502121 [Byte1]: 75
1824 20:11:46.505935
1825 20:11:46.506053 Set Vref, RX VrefLevel [Byte0]: 76
1826 20:11:46.509666 [Byte1]: 76
1827 20:11:46.513712
1828 20:11:46.513829 Final RX Vref Byte 0 = 62 to rank0
1829 20:11:46.516845 Final RX Vref Byte 1 = 56 to rank0
1830 20:11:46.520834 Final RX Vref Byte 0 = 62 to rank1
1831 20:11:46.523690 Final RX Vref Byte 1 = 56 to rank1==
1832 20:11:46.527505 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 20:11:46.530319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 20:11:46.533715 ==
1835 20:11:46.533848 DQS Delay:
1836 20:11:46.533958 DQS0 = 0, DQS1 = 0
1837 20:11:46.536909 DQM Delay:
1838 20:11:46.537033 DQM0 = 82, DQM1 = 73
1839 20:11:46.540612 DQ Delay:
1840 20:11:46.540735 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1841 20:11:46.544067 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1842 20:11:46.547565 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1843 20:11:46.550621 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1844 20:11:46.550709
1845 20:11:46.554249
1846 20:11:46.560685 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1847 20:11:46.564362 CH1 RK0: MR19=605, MR18=26FB
1848 20:11:46.570448 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1849 20:11:46.570576
1850 20:11:46.574377 ----->DramcWriteLeveling(PI) begin...
1851 20:11:46.574480 ==
1852 20:11:46.577240 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 20:11:46.581134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 20:11:46.581270 ==
1855 20:11:46.584470 Write leveling (Byte 0): 27 => 27
1856 20:11:46.587423 Write leveling (Byte 1): 27 => 27
1857 20:11:46.591216 DramcWriteLeveling(PI) end<-----
1858 20:11:46.591348
1859 20:11:46.591464 ==
1860 20:11:46.594229 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 20:11:46.597684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 20:11:46.597813 ==
1863 20:11:46.600765 [Gating] SW mode calibration
1864 20:11:46.607596 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 20:11:46.614075 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 20:11:46.617400 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 20:11:46.621096 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1868 20:11:46.624303 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 20:11:46.631652 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 20:11:46.634408 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 20:11:46.637485 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 20:11:46.644200 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 20:11:46.647749 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 20:11:46.651320 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 20:11:46.657641 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 20:11:46.661227 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 20:11:46.664572 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 20:11:46.670884 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 20:11:46.674690 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 20:11:46.678518 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 20:11:46.681261 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 20:11:46.688120 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 20:11:46.692263 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1884 20:11:46.694672 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 20:11:46.701660 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 20:11:46.704653 0 8 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1887 20:11:46.709420 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 20:11:46.715679 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 20:11:46.718791 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 20:11:46.721826 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 20:11:46.728559 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1892 20:11:46.731816 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1893 20:11:46.735778 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 20:11:46.738524 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 20:11:46.745312 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 20:11:46.748258 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 20:11:46.751897 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 20:11:46.758443 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 20:11:46.762025 0 10 4 | B1->B0 | 3232 2e2e | 1 0 | (0 1) (0 1)
1900 20:11:46.765555 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 20:11:46.772192 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 20:11:46.775586 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 20:11:46.778826 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 20:11:46.785693 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 20:11:46.788684 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1906 20:11:46.792357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 20:11:46.798743 0 11 4 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
1908 20:11:46.802381 0 11 8 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1909 20:11:46.806114 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 20:11:46.808919 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 20:11:46.815559 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 20:11:46.819107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 20:11:46.822515 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 20:11:46.829403 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1915 20:11:46.833144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 20:11:46.835753 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1917 20:11:46.842285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 20:11:46.846286 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 20:11:46.849107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 20:11:46.856007 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 20:11:46.859007 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 20:11:46.862314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 20:11:46.865690 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 20:11:46.872494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 20:11:46.876438 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 20:11:46.879514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 20:11:46.886055 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 20:11:46.889390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 20:11:46.892650 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 20:11:46.899657 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 20:11:46.903168 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1932 20:11:46.906045 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 20:11:46.909176 Total UI for P1: 0, mck2ui 16
1934 20:11:46.913289 best dqsien dly found for B0: ( 0, 14, 4)
1935 20:11:46.916686 Total UI for P1: 0, mck2ui 16
1936 20:11:46.919899 best dqsien dly found for B1: ( 0, 14, 4)
1937 20:11:46.923488 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1938 20:11:46.926076 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1939 20:11:46.926164
1940 20:11:46.929754 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 20:11:46.937270 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1942 20:11:46.937373 [Gating] SW calibration Done
1943 20:11:46.937465 ==
1944 20:11:46.939450 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 20:11:46.946661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 20:11:46.946759 ==
1947 20:11:46.946849 RX Vref Scan: 0
1948 20:11:46.946932
1949 20:11:46.950238 RX Vref 0 -> 0, step: 1
1950 20:11:46.950327
1951 20:11:46.952782 RX Delay -130 -> 252, step: 16
1952 20:11:46.956261 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1953 20:11:46.959684 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1954 20:11:46.963227 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1955 20:11:46.966266 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1956 20:11:46.972846 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1957 20:11:46.976514 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1958 20:11:46.979950 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1959 20:11:46.983485 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1960 20:11:46.986432 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1961 20:11:46.993001 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1962 20:11:46.996611 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1963 20:11:47.000126 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1964 20:11:47.003144 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1965 20:11:47.006674 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1966 20:11:47.013395 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1967 20:11:47.017342 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1968 20:11:47.017445 ==
1969 20:11:47.019955 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 20:11:47.023467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 20:11:47.023568 ==
1972 20:11:47.023653 DQS Delay:
1973 20:11:47.026720 DQS0 = 0, DQS1 = 0
1974 20:11:47.026832 DQM Delay:
1975 20:11:47.030247 DQM0 = 80, DQM1 = 76
1976 20:11:47.030347 DQ Delay:
1977 20:11:47.033491 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1978 20:11:47.036836 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1979 20:11:47.040806 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1980 20:11:47.044385 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1981 20:11:47.044472
1982 20:11:47.044557
1983 20:11:47.044638 ==
1984 20:11:47.047212 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 20:11:47.051340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 20:11:47.051427 ==
1987 20:11:47.054212
1988 20:11:47.054295
1989 20:11:47.054417 TX Vref Scan disable
1990 20:11:47.057019 == TX Byte 0 ==
1991 20:11:47.060278 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 20:11:47.063579 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 20:11:47.067672 == TX Byte 1 ==
1994 20:11:47.070065 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1995 20:11:47.073599 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1996 20:11:47.073699 ==
1997 20:11:47.077361 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 20:11:47.085359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 20:11:47.085449 ==
2000 20:11:47.095567 TX Vref=22, minBit 11, minWin=26, winSum=439
2001 20:11:47.098461 TX Vref=24, minBit 9, minWin=27, winSum=443
2002 20:11:47.102268 TX Vref=26, minBit 0, minWin=27, winSum=444
2003 20:11:47.105214 TX Vref=28, minBit 10, minWin=27, winSum=448
2004 20:11:47.108675 TX Vref=30, minBit 9, minWin=27, winSum=449
2005 20:11:47.115521 TX Vref=32, minBit 10, minWin=27, winSum=448
2006 20:11:47.119007 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
2007 20:11:47.119095
2008 20:11:47.122404 Final TX Range 1 Vref 30
2009 20:11:47.122489
2010 20:11:47.122556 ==
2011 20:11:47.125597 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 20:11:47.128737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 20:11:47.128822 ==
2014 20:11:47.128889
2015 20:11:47.132015
2016 20:11:47.132100 TX Vref Scan disable
2017 20:11:47.135235 == TX Byte 0 ==
2018 20:11:47.139087 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 20:11:47.142976 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 20:11:47.146098 == TX Byte 1 ==
2021 20:11:47.149175 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2022 20:11:47.152536 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2023 20:11:47.156051
2024 20:11:47.156133 [DATLAT]
2025 20:11:47.156199 Freq=800, CH1 RK1
2026 20:11:47.156263
2027 20:11:47.158681 DATLAT Default: 0xa
2028 20:11:47.158765 0, 0xFFFF, sum = 0
2029 20:11:47.162408 1, 0xFFFF, sum = 0
2030 20:11:47.162494 2, 0xFFFF, sum = 0
2031 20:11:47.166519 3, 0xFFFF, sum = 0
2032 20:11:47.166604 4, 0xFFFF, sum = 0
2033 20:11:47.168689 5, 0xFFFF, sum = 0
2034 20:11:47.168774 6, 0xFFFF, sum = 0
2035 20:11:47.172402 7, 0xFFFF, sum = 0
2036 20:11:47.175674 8, 0xFFFF, sum = 0
2037 20:11:47.175758 9, 0x0, sum = 1
2038 20:11:47.175826 10, 0x0, sum = 2
2039 20:11:47.179261 11, 0x0, sum = 3
2040 20:11:47.179346 12, 0x0, sum = 4
2041 20:11:47.182327 best_step = 10
2042 20:11:47.182425
2043 20:11:47.182513 ==
2044 20:11:47.185505 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 20:11:47.189034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 20:11:47.189120 ==
2047 20:11:47.193091 RX Vref Scan: 0
2048 20:11:47.193176
2049 20:11:47.193260 RX Vref 0 -> 0, step: 1
2050 20:11:47.193342
2051 20:11:47.195830 RX Delay -111 -> 252, step: 8
2052 20:11:47.202254 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2053 20:11:47.205360 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2054 20:11:47.208782 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2055 20:11:47.212347 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2056 20:11:47.216410 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2057 20:11:47.222176 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2058 20:11:47.226023 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2059 20:11:47.229339 iDelay=209, Bit 7, Center 80 (-31 ~ 192) 224
2060 20:11:47.232557 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2061 20:11:47.236043 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
2062 20:11:47.239332 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2063 20:11:47.245762 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2064 20:11:47.249682 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2065 20:11:47.252724 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2066 20:11:47.255929 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2067 20:11:47.262992 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2068 20:11:47.263095 ==
2069 20:11:47.266546 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 20:11:47.269514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 20:11:47.269592 ==
2072 20:11:47.269656 DQS Delay:
2073 20:11:47.272672 DQS0 = 0, DQS1 = 0
2074 20:11:47.272771 DQM Delay:
2075 20:11:47.276656 DQM0 = 80, DQM1 = 75
2076 20:11:47.276732 DQ Delay:
2077 20:11:47.279248 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2078 20:11:47.283013 DQ4 =84, DQ5 =88, DQ6 =92, DQ7 =80
2079 20:11:47.285992 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
2080 20:11:47.289445 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2081 20:11:47.289550
2082 20:11:47.289645
2083 20:11:47.296324 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2084 20:11:47.300064 CH1 RK1: MR19=606, MR18=1C27
2085 20:11:47.306188 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2086 20:11:47.310063 [RxdqsGatingPostProcess] freq 800
2087 20:11:47.313489 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 20:11:47.316250 Pre-setting of DQS Precalculation
2089 20:11:47.323084 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 20:11:47.329880 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 20:11:47.336328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 20:11:47.336471
2093 20:11:47.336589
2094 20:11:47.339734 [Calibration Summary] 1600 Mbps
2095 20:11:47.339860 CH 0, Rank 0
2096 20:11:47.343072 SW Impedance : PASS
2097 20:11:47.346531 DUTY Scan : NO K
2098 20:11:47.346656 ZQ Calibration : PASS
2099 20:11:47.350202 Jitter Meter : NO K
2100 20:11:47.353427 CBT Training : PASS
2101 20:11:47.353545 Write leveling : PASS
2102 20:11:47.356513 RX DQS gating : PASS
2103 20:11:47.360645 RX DQ/DQS(RDDQC) : PASS
2104 20:11:47.360771 TX DQ/DQS : PASS
2105 20:11:47.363582 RX DATLAT : PASS
2106 20:11:47.363682 RX DQ/DQS(Engine): PASS
2107 20:11:47.366893 TX OE : NO K
2108 20:11:47.366969 All Pass.
2109 20:11:47.367032
2110 20:11:47.370295 CH 0, Rank 1
2111 20:11:47.370409 SW Impedance : PASS
2112 20:11:47.373239 DUTY Scan : NO K
2113 20:11:47.376862 ZQ Calibration : PASS
2114 20:11:47.376965 Jitter Meter : NO K
2115 20:11:47.380376 CBT Training : PASS
2116 20:11:47.383511 Write leveling : PASS
2117 20:11:47.383595 RX DQS gating : PASS
2118 20:11:47.386998 RX DQ/DQS(RDDQC) : PASS
2119 20:11:47.390240 TX DQ/DQS : PASS
2120 20:11:47.390347 RX DATLAT : PASS
2121 20:11:47.393641 RX DQ/DQS(Engine): PASS
2122 20:11:47.393716 TX OE : NO K
2123 20:11:47.396948 All Pass.
2124 20:11:47.397052
2125 20:11:47.397142 CH 1, Rank 0
2126 20:11:47.400683 SW Impedance : PASS
2127 20:11:47.400782 DUTY Scan : NO K
2128 20:11:47.403612 ZQ Calibration : PASS
2129 20:11:47.406867 Jitter Meter : NO K
2130 20:11:47.406942 CBT Training : PASS
2131 20:11:47.410939 Write leveling : PASS
2132 20:11:47.413409 RX DQS gating : PASS
2133 20:11:47.413509 RX DQ/DQS(RDDQC) : PASS
2134 20:11:47.416892 TX DQ/DQS : PASS
2135 20:11:47.420658 RX DATLAT : PASS
2136 20:11:47.420760 RX DQ/DQS(Engine): PASS
2137 20:11:47.424235 TX OE : NO K
2138 20:11:47.424321 All Pass.
2139 20:11:47.424385
2140 20:11:47.427729 CH 1, Rank 1
2141 20:11:47.427833 SW Impedance : PASS
2142 20:11:47.430367 DUTY Scan : NO K
2143 20:11:47.430465 ZQ Calibration : PASS
2144 20:11:47.434258 Jitter Meter : NO K
2145 20:11:47.437730 CBT Training : PASS
2146 20:11:47.437814 Write leveling : PASS
2147 20:11:47.440768 RX DQS gating : PASS
2148 20:11:47.443874 RX DQ/DQS(RDDQC) : PASS
2149 20:11:47.443957 TX DQ/DQS : PASS
2150 20:11:47.447730 RX DATLAT : PASS
2151 20:11:47.450607 RX DQ/DQS(Engine): PASS
2152 20:11:47.450701 TX OE : NO K
2153 20:11:47.453983 All Pass.
2154 20:11:47.454067
2155 20:11:47.454133 DramC Write-DBI off
2156 20:11:47.457317 PER_BANK_REFRESH: Hybrid Mode
2157 20:11:47.457400 TX_TRACKING: ON
2158 20:11:47.460616 [GetDramInforAfterCalByMRR] Vendor 6.
2159 20:11:47.464132 [GetDramInforAfterCalByMRR] Revision 606.
2160 20:11:47.470692 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 20:11:47.470778 MR0 0x3b3b
2162 20:11:47.470844 MR8 0x5151
2163 20:11:47.474246 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 20:11:47.474329
2165 20:11:47.477369 MR0 0x3b3b
2166 20:11:47.477478 MR8 0x5151
2167 20:11:47.480654 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 20:11:47.480737
2169 20:11:47.490522 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 20:11:47.494389 [FAST_K] Save calibration result to emmc
2171 20:11:47.497570 [FAST_K] Save calibration result to emmc
2172 20:11:47.501021 dram_init: config_dvfs: 1
2173 20:11:47.504181 dramc_set_vcore_voltage set vcore to 662500
2174 20:11:47.504306 Read voltage for 1200, 2
2175 20:11:47.507540 Vio18 = 0
2176 20:11:47.507664 Vcore = 662500
2177 20:11:47.507779 Vdram = 0
2178 20:11:47.510705 Vddq = 0
2179 20:11:47.510830 Vmddr = 0
2180 20:11:47.514067 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 20:11:47.521201 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 20:11:47.524393 MEM_TYPE=3, freq_sel=15
2183 20:11:47.528123 sv_algorithm_assistance_LP4_1600
2184 20:11:47.531205 ============ PULL DRAM RESETB DOWN ============
2185 20:11:47.534507 ========== PULL DRAM RESETB DOWN end =========
2186 20:11:47.540863 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 20:11:47.544815 ===================================
2188 20:11:47.544929 LPDDR4 DRAM CONFIGURATION
2189 20:11:47.547682 ===================================
2190 20:11:47.551349 EX_ROW_EN[0] = 0x0
2191 20:11:47.551431 EX_ROW_EN[1] = 0x0
2192 20:11:47.554448 LP4Y_EN = 0x0
2193 20:11:47.554532 WORK_FSP = 0x0
2194 20:11:47.557872 WL = 0x4
2195 20:11:47.557956 RL = 0x4
2196 20:11:47.561934 BL = 0x2
2197 20:11:47.562019 RPST = 0x0
2198 20:11:47.564679 RD_PRE = 0x0
2199 20:11:47.564766 WR_PRE = 0x1
2200 20:11:47.567971 WR_PST = 0x0
2201 20:11:47.571292 DBI_WR = 0x0
2202 20:11:47.571376 DBI_RD = 0x0
2203 20:11:47.574603 OTF = 0x1
2204 20:11:47.577818 ===================================
2205 20:11:47.577901 ===================================
2206 20:11:47.581833 ANA top config
2207 20:11:47.584944 ===================================
2208 20:11:47.588279 DLL_ASYNC_EN = 0
2209 20:11:47.588363 ALL_SLAVE_EN = 0
2210 20:11:47.591109 NEW_RANK_MODE = 1
2211 20:11:47.594864 DLL_IDLE_MODE = 1
2212 20:11:47.597975 LP45_APHY_COMB_EN = 1
2213 20:11:47.601249 TX_ODT_DIS = 1
2214 20:11:47.601333 NEW_8X_MODE = 1
2215 20:11:47.604775 ===================================
2216 20:11:47.607977 ===================================
2217 20:11:47.611604 data_rate = 2400
2218 20:11:47.614976 CKR = 1
2219 20:11:47.617933 DQ_P2S_RATIO = 8
2220 20:11:47.622411 ===================================
2221 20:11:47.624951 CA_P2S_RATIO = 8
2222 20:11:47.625035 DQ_CA_OPEN = 0
2223 20:11:47.628141 DQ_SEMI_OPEN = 0
2224 20:11:47.631282 CA_SEMI_OPEN = 0
2225 20:11:47.635579 CA_FULL_RATE = 0
2226 20:11:47.638294 DQ_CKDIV4_EN = 0
2227 20:11:47.641942 CA_CKDIV4_EN = 0
2228 20:11:47.642029 CA_PREDIV_EN = 0
2229 20:11:47.645485 PH8_DLY = 17
2230 20:11:47.649055 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 20:11:47.651836 DQ_AAMCK_DIV = 4
2232 20:11:47.655304 CA_AAMCK_DIV = 4
2233 20:11:47.655417 CA_ADMCK_DIV = 4
2234 20:11:47.658685 DQ_TRACK_CA_EN = 0
2235 20:11:47.661953 CA_PICK = 1200
2236 20:11:47.665520 CA_MCKIO = 1200
2237 20:11:47.668934 MCKIO_SEMI = 0
2238 20:11:47.671609 PLL_FREQ = 2366
2239 20:11:47.675069 DQ_UI_PI_RATIO = 32
2240 20:11:47.678702 CA_UI_PI_RATIO = 0
2241 20:11:47.678790 ===================================
2242 20:11:47.681613 ===================================
2243 20:11:47.685488 memory_type:LPDDR4
2244 20:11:47.688754 GP_NUM : 10
2245 20:11:47.688846 SRAM_EN : 1
2246 20:11:47.691988 MD32_EN : 0
2247 20:11:47.695538 ===================================
2248 20:11:47.698810 [ANA_INIT] >>>>>>>>>>>>>>
2249 20:11:47.701957 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 20:11:47.705506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 20:11:47.708471 ===================================
2252 20:11:47.708560 data_rate = 2400,PCW = 0X5b00
2253 20:11:47.711981 ===================================
2254 20:11:47.715598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 20:11:47.721988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 20:11:47.728732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 20:11:47.732411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 20:11:47.735381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 20:11:47.739190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 20:11:47.742106 [ANA_INIT] flow start
2261 20:11:47.742205 [ANA_INIT] PLL >>>>>>>>
2262 20:11:47.746081 [ANA_INIT] PLL <<<<<<<<
2263 20:11:47.749301 [ANA_INIT] MIDPI >>>>>>>>
2264 20:11:47.749399 [ANA_INIT] MIDPI <<<<<<<<
2265 20:11:47.752317 [ANA_INIT] DLL >>>>>>>>
2266 20:11:47.755807 [ANA_INIT] DLL <<<<<<<<
2267 20:11:47.755906 [ANA_INIT] flow end
2268 20:11:47.762635 ============ LP4 DIFF to SE enter ============
2269 20:11:47.765308 ============ LP4 DIFF to SE exit ============
2270 20:11:47.769521 [ANA_INIT] <<<<<<<<<<<<<
2271 20:11:47.772192 [Flow] Enable top DCM control >>>>>
2272 20:11:47.772305 [Flow] Enable top DCM control <<<<<
2273 20:11:47.775754 Enable DLL master slave shuffle
2274 20:11:47.782184 ==============================================================
2275 20:11:47.785969 Gating Mode config
2276 20:11:47.788873 ==============================================================
2277 20:11:47.792657 Config description:
2278 20:11:47.802542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 20:11:47.808919 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 20:11:47.812389 SELPH_MODE 0: By rank 1: By Phase
2281 20:11:47.819224 ==============================================================
2282 20:11:47.822509 GAT_TRACK_EN = 1
2283 20:11:47.822589 RX_GATING_MODE = 2
2284 20:11:47.825999 RX_GATING_TRACK_MODE = 2
2285 20:11:47.829761 SELPH_MODE = 1
2286 20:11:47.832803 PICG_EARLY_EN = 1
2287 20:11:47.836324 VALID_LAT_VALUE = 1
2288 20:11:47.842667 ==============================================================
2289 20:11:47.846233 Enter into Gating configuration >>>>
2290 20:11:47.850126 Exit from Gating configuration <<<<
2291 20:11:47.852925 Enter into DVFS_PRE_config >>>>>
2292 20:11:47.862787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 20:11:47.866335 Exit from DVFS_PRE_config <<<<<
2294 20:11:47.869500 Enter into PICG configuration >>>>
2295 20:11:47.873076 Exit from PICG configuration <<<<
2296 20:11:47.876437 [RX_INPUT] configuration >>>>>
2297 20:11:47.876522 [RX_INPUT] configuration <<<<<
2298 20:11:47.883587 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 20:11:47.889779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 20:11:47.893087 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 20:11:47.899556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 20:11:47.906837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 20:11:47.913050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 20:11:47.916417 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 20:11:47.919609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 20:11:47.926622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 20:11:47.929698 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 20:11:47.933067 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 20:11:47.936748 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 20:11:47.939980 ===================================
2311 20:11:47.943211 LPDDR4 DRAM CONFIGURATION
2312 20:11:47.946802 ===================================
2313 20:11:47.949890 EX_ROW_EN[0] = 0x0
2314 20:11:47.949976 EX_ROW_EN[1] = 0x0
2315 20:11:47.953363 LP4Y_EN = 0x0
2316 20:11:47.953447 WORK_FSP = 0x0
2317 20:11:47.956284 WL = 0x4
2318 20:11:47.956363 RL = 0x4
2319 20:11:47.960088 BL = 0x2
2320 20:11:47.960172 RPST = 0x0
2321 20:11:47.963116 RD_PRE = 0x0
2322 20:11:47.963199 WR_PRE = 0x1
2323 20:11:47.966784 WR_PST = 0x0
2324 20:11:47.966869 DBI_WR = 0x0
2325 20:11:47.969663 DBI_RD = 0x0
2326 20:11:47.969747 OTF = 0x1
2327 20:11:47.973364 ===================================
2328 20:11:47.980741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 20:11:47.983362 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 20:11:47.986961 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 20:11:47.990238 ===================================
2332 20:11:47.993763 LPDDR4 DRAM CONFIGURATION
2333 20:11:47.997465 ===================================
2334 20:11:47.997548 EX_ROW_EN[0] = 0x10
2335 20:11:48.000337 EX_ROW_EN[1] = 0x0
2336 20:11:48.000419 LP4Y_EN = 0x0
2337 20:11:48.003543 WORK_FSP = 0x0
2338 20:11:48.006821 WL = 0x4
2339 20:11:48.006904 RL = 0x4
2340 20:11:48.010886 BL = 0x2
2341 20:11:48.010970 RPST = 0x0
2342 20:11:48.013762 RD_PRE = 0x0
2343 20:11:48.013858 WR_PRE = 0x1
2344 20:11:48.017373 WR_PST = 0x0
2345 20:11:48.017498 DBI_WR = 0x0
2346 20:11:48.020431 DBI_RD = 0x0
2347 20:11:48.020514 OTF = 0x1
2348 20:11:48.024513 ===================================
2349 20:11:48.030779 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 20:11:48.030868 ==
2351 20:11:48.034157 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 20:11:48.037703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 20:11:48.037787 ==
2354 20:11:48.041277 [Duty_Offset_Calibration]
2355 20:11:48.041359 B0:2 B1:-1 CA:1
2356 20:11:48.044324
2357 20:11:48.047135 [DutyScan_Calibration_Flow] k_type=0
2358 20:11:48.054298
2359 20:11:48.054384 ==CLK 0==
2360 20:11:48.057761 Final CLK duty delay cell = -4
2361 20:11:48.060634 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2362 20:11:48.064463 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2363 20:11:48.067714 [-4] AVG Duty = 4953%(X100)
2364 20:11:48.067796
2365 20:11:48.071549 CH0 CLK Duty spec in!! Max-Min= 156%
2366 20:11:48.074919 [DutyScan_Calibration_Flow] ====Done====
2367 20:11:48.075001
2368 20:11:48.078067 [DutyScan_Calibration_Flow] k_type=1
2369 20:11:48.092550
2370 20:11:48.092680 ==DQS 0 ==
2371 20:11:48.095688 Final DQS duty delay cell = -4
2372 20:11:48.099229 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2373 20:11:48.103702 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2374 20:11:48.105652 [-4] AVG Duty = 4938%(X100)
2375 20:11:48.105734
2376 20:11:48.105798 ==DQS 1 ==
2377 20:11:48.108977 Final DQS duty delay cell = -4
2378 20:11:48.112237 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2379 20:11:48.115594 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2380 20:11:48.118881 [-4] AVG Duty = 5062%(X100)
2381 20:11:48.118969
2382 20:11:48.122658 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2383 20:11:48.122741
2384 20:11:48.125916 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2385 20:11:48.129023 [DutyScan_Calibration_Flow] ====Done====
2386 20:11:48.129128
2387 20:11:48.133080 [DutyScan_Calibration_Flow] k_type=3
2388 20:11:48.149904
2389 20:11:48.150003 ==DQM 0 ==
2390 20:11:48.153223 Final DQM duty delay cell = 0
2391 20:11:48.156576 [0] MAX Duty = 5000%(X100), DQS PI = 54
2392 20:11:48.159944 [0] MIN Duty = 4907%(X100), DQS PI = 2
2393 20:11:48.160028 [0] AVG Duty = 4953%(X100)
2394 20:11:48.160092
2395 20:11:48.163090 ==DQM 1 ==
2396 20:11:48.166008 Final DQM duty delay cell = 0
2397 20:11:48.169571 [0] MAX Duty = 5124%(X100), DQS PI = 32
2398 20:11:48.173412 [0] MIN Duty = 4969%(X100), DQS PI = 8
2399 20:11:48.173494 [0] AVG Duty = 5046%(X100)
2400 20:11:48.173560
2401 20:11:48.176408 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2402 20:11:48.179539
2403 20:11:48.183106 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2404 20:11:48.186717 [DutyScan_Calibration_Flow] ====Done====
2405 20:11:48.186807
2406 20:11:48.189882 [DutyScan_Calibration_Flow] k_type=2
2407 20:11:48.204731
2408 20:11:48.204841 ==DQ 0 ==
2409 20:11:48.208220 Final DQ duty delay cell = -4
2410 20:11:48.211799 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2411 20:11:48.214782 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2412 20:11:48.218386 [-4] AVG Duty = 4969%(X100)
2413 20:11:48.218504
2414 20:11:48.218570 ==DQ 1 ==
2415 20:11:48.221736 Final DQ duty delay cell = 0
2416 20:11:48.225623 [0] MAX Duty = 5031%(X100), DQS PI = 18
2417 20:11:48.229173 [0] MIN Duty = 4907%(X100), DQS PI = 46
2418 20:11:48.229256 [0] AVG Duty = 4969%(X100)
2419 20:11:48.229322
2420 20:11:48.231849 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2421 20:11:48.235635
2422 20:11:48.238616 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2423 20:11:48.241980 [DutyScan_Calibration_Flow] ====Done====
2424 20:11:48.242064 ==
2425 20:11:48.245075 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 20:11:48.248678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 20:11:48.248763 ==
2428 20:11:48.252367 [Duty_Offset_Calibration]
2429 20:11:48.252449 B0:1 B1:1 CA:2
2430 20:11:48.252514
2431 20:11:48.255710 [DutyScan_Calibration_Flow] k_type=0
2432 20:11:48.265638
2433 20:11:48.265722 ==CLK 0==
2434 20:11:48.268741 Final CLK duty delay cell = 0
2435 20:11:48.272359 [0] MAX Duty = 5156%(X100), DQS PI = 24
2436 20:11:48.275463 [0] MIN Duty = 4938%(X100), DQS PI = 46
2437 20:11:48.275547 [0] AVG Duty = 5047%(X100)
2438 20:11:48.275612
2439 20:11:48.278893 CH1 CLK Duty spec in!! Max-Min= 218%
2440 20:11:48.285261 [DutyScan_Calibration_Flow] ====Done====
2441 20:11:48.285353
2442 20:11:48.288508 [DutyScan_Calibration_Flow] k_type=1
2443 20:11:48.304838
2444 20:11:48.304957 ==DQS 0 ==
2445 20:11:48.308337 Final DQS duty delay cell = 0
2446 20:11:48.311380 [0] MAX Duty = 5031%(X100), DQS PI = 18
2447 20:11:48.314634 [0] MIN Duty = 4844%(X100), DQS PI = 50
2448 20:11:48.314749 [0] AVG Duty = 4937%(X100)
2449 20:11:48.318062
2450 20:11:48.318187 ==DQS 1 ==
2451 20:11:48.321133 Final DQS duty delay cell = 0
2452 20:11:48.324455 [0] MAX Duty = 5062%(X100), DQS PI = 36
2453 20:11:48.327652 [0] MIN Duty = 4907%(X100), DQS PI = 0
2454 20:11:48.331477 [0] AVG Duty = 4984%(X100)
2455 20:11:48.331560
2456 20:11:48.334722 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2457 20:11:48.334798
2458 20:11:48.337924 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2459 20:11:48.341534 [DutyScan_Calibration_Flow] ====Done====
2460 20:11:48.341610
2461 20:11:48.344633 [DutyScan_Calibration_Flow] k_type=3
2462 20:11:48.361698
2463 20:11:48.361815 ==DQM 0 ==
2464 20:11:48.365095 Final DQM duty delay cell = 0
2465 20:11:48.367581 [0] MAX Duty = 5093%(X100), DQS PI = 18
2466 20:11:48.371128 [0] MIN Duty = 4844%(X100), DQS PI = 50
2467 20:11:48.371213 [0] AVG Duty = 4968%(X100)
2468 20:11:48.374274
2469 20:11:48.374406 ==DQM 1 ==
2470 20:11:48.377720 Final DQM duty delay cell = 0
2471 20:11:48.380915 [0] MAX Duty = 5125%(X100), DQS PI = 62
2472 20:11:48.384817 [0] MIN Duty = 4938%(X100), DQS PI = 22
2473 20:11:48.384902 [0] AVG Duty = 5031%(X100)
2474 20:11:48.387592
2475 20:11:48.391364 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2476 20:11:48.391448
2477 20:11:48.394297 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2478 20:11:48.397899 [DutyScan_Calibration_Flow] ====Done====
2479 20:11:48.397992
2480 20:11:48.401026 [DutyScan_Calibration_Flow] k_type=2
2481 20:11:48.417407
2482 20:11:48.417559 ==DQ 0 ==
2483 20:11:48.420842 Final DQ duty delay cell = 0
2484 20:11:48.424528 [0] MAX Duty = 5156%(X100), DQS PI = 18
2485 20:11:48.427872 [0] MIN Duty = 4938%(X100), DQS PI = 50
2486 20:11:48.427964 [0] AVG Duty = 5047%(X100)
2487 20:11:48.428035
2488 20:11:48.430801 ==DQ 1 ==
2489 20:11:48.434250 Final DQ duty delay cell = 0
2490 20:11:48.437549 [0] MAX Duty = 5093%(X100), DQS PI = 8
2491 20:11:48.441353 [0] MIN Duty = 5031%(X100), DQS PI = 2
2492 20:11:48.441439 [0] AVG Duty = 5062%(X100)
2493 20:11:48.441505
2494 20:11:48.444520 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2495 20:11:48.444598
2496 20:11:48.448186 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2497 20:11:48.450892 [DutyScan_Calibration_Flow] ====Done====
2498 20:11:48.456460 nWR fixed to 30
2499 20:11:48.459835 [ModeRegInit_LP4] CH0 RK0
2500 20:11:48.459919 [ModeRegInit_LP4] CH0 RK1
2501 20:11:48.463419 [ModeRegInit_LP4] CH1 RK0
2502 20:11:48.467058 [ModeRegInit_LP4] CH1 RK1
2503 20:11:48.467132 match AC timing 7
2504 20:11:48.473331 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 20:11:48.476608 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 20:11:48.480722 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 20:11:48.486533 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 20:11:48.490053 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 20:11:48.490131 ==
2510 20:11:48.493368 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 20:11:48.496775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 20:11:48.496860 ==
2513 20:11:48.503577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 20:11:48.510681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 20:11:48.517264 [CA 0] Center 40 (10~71) winsize 62
2516 20:11:48.521103 [CA 1] Center 39 (9~70) winsize 62
2517 20:11:48.524032 [CA 2] Center 36 (6~67) winsize 62
2518 20:11:48.527147 [CA 3] Center 36 (5~67) winsize 63
2519 20:11:48.531298 [CA 4] Center 35 (5~65) winsize 61
2520 20:11:48.533828 [CA 5] Center 34 (4~65) winsize 62
2521 20:11:48.533937
2522 20:11:48.537250 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2523 20:11:48.537351
2524 20:11:48.540717 [CATrainingPosCal] consider 1 rank data
2525 20:11:48.544682 u2DelayCellTimex100 = 270/100 ps
2526 20:11:48.547721 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2527 20:11:48.551104 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2528 20:11:48.558216 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2529 20:11:48.561305 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2530 20:11:48.564709 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2531 20:11:48.568972 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2532 20:11:48.569149
2533 20:11:48.571629 CA PerBit enable=1, Macro0, CA PI delay=34
2534 20:11:48.571713
2535 20:11:48.574694 [CBTSetCACLKResult] CA Dly = 34
2536 20:11:48.574770 CS Dly: 7 (0~38)
2537 20:11:48.574833 ==
2538 20:11:48.578336 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 20:11:48.584372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 20:11:48.584460 ==
2541 20:11:48.588155 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 20:11:48.595266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2543 20:11:48.603933 [CA 0] Center 39 (9~70) winsize 62
2544 20:11:48.607092 [CA 1] Center 39 (9~70) winsize 62
2545 20:11:48.610268 [CA 2] Center 36 (6~67) winsize 62
2546 20:11:48.613554 [CA 3] Center 36 (5~67) winsize 63
2547 20:11:48.617155 [CA 4] Center 34 (4~65) winsize 62
2548 20:11:48.620094 [CA 5] Center 34 (4~64) winsize 61
2549 20:11:48.620181
2550 20:11:48.623254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 20:11:48.623351
2552 20:11:48.626604 [CATrainingPosCal] consider 2 rank data
2553 20:11:48.630027 u2DelayCellTimex100 = 270/100 ps
2554 20:11:48.634274 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2555 20:11:48.637178 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2556 20:11:48.640330 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2557 20:11:48.647177 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2558 20:11:48.650271 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2559 20:11:48.653806 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2560 20:11:48.653891
2561 20:11:48.657259 CA PerBit enable=1, Macro0, CA PI delay=34
2562 20:11:48.657344
2563 20:11:48.660314 [CBTSetCACLKResult] CA Dly = 34
2564 20:11:48.660398 CS Dly: 8 (0~41)
2565 20:11:48.660464
2566 20:11:48.663799 ----->DramcWriteLeveling(PI) begin...
2567 20:11:48.663884 ==
2568 20:11:48.667047 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 20:11:48.673516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 20:11:48.673601 ==
2571 20:11:48.677272 Write leveling (Byte 0): 31 => 31
2572 20:11:48.680348 Write leveling (Byte 1): 30 => 30
2573 20:11:48.680433 DramcWriteLeveling(PI) end<-----
2574 20:11:48.680499
2575 20:11:48.683690 ==
2576 20:11:48.687320 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 20:11:48.690580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 20:11:48.690665 ==
2579 20:11:48.693917 [Gating] SW mode calibration
2580 20:11:48.700857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 20:11:48.704343 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 20:11:48.710901 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 20:11:48.714046 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2584 20:11:48.717404 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2585 20:11:48.723854 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 20:11:48.727407 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 20:11:48.730562 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 20:11:48.733878 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 20:11:48.740731 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 20:11:48.744201 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
2591 20:11:48.748005 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2592 20:11:48.754182 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 20:11:48.758249 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 20:11:48.761239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 20:11:48.767897 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 20:11:48.771412 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 20:11:48.774747 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 20:11:48.781199 1 1 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2599 20:11:48.784598 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2600 20:11:48.787647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 20:11:48.791128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 20:11:48.797924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 20:11:48.801241 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 20:11:48.804947 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 20:11:48.811655 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 20:11:48.814732 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2607 20:11:48.818014 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 20:11:48.825002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 20:11:48.828664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 20:11:48.831196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 20:11:48.838312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 20:11:48.842251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 20:11:48.844950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 20:11:48.851412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 20:11:48.854982 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 20:11:48.857797 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 20:11:48.864501 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 20:11:48.868101 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 20:11:48.871279 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 20:11:48.874671 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 20:11:48.881643 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 20:11:48.885020 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2623 20:11:48.888399 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 20:11:48.891451 Total UI for P1: 0, mck2ui 16
2625 20:11:48.895138 best dqsien dly found for B0: ( 1, 4, 0)
2626 20:11:48.901836 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 20:11:48.901929 Total UI for P1: 0, mck2ui 16
2628 20:11:48.908231 best dqsien dly found for B1: ( 1, 4, 2)
2629 20:11:48.911980 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2630 20:11:48.915414 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2631 20:11:48.915538
2632 20:11:48.918196 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2633 20:11:48.921829 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2634 20:11:48.924947 [Gating] SW calibration Done
2635 20:11:48.925047 ==
2636 20:11:48.928639 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 20:11:48.932100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 20:11:48.932180 ==
2639 20:11:48.932246 RX Vref Scan: 0
2640 20:11:48.932306
2641 20:11:48.935798 RX Vref 0 -> 0, step: 1
2642 20:11:48.935898
2643 20:11:48.938633 RX Delay -40 -> 252, step: 8
2644 20:11:48.942072 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2645 20:11:48.945550 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2646 20:11:48.952195 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2647 20:11:48.955220 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2648 20:11:48.958615 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2649 20:11:48.961849 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2650 20:11:48.965678 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2651 20:11:48.969298 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2652 20:11:48.975587 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 20:11:48.978818 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2654 20:11:48.982448 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2655 20:11:48.985355 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2656 20:11:48.989053 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2657 20:11:48.995872 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2658 20:11:48.999005 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2659 20:11:49.002318 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2660 20:11:49.002462 ==
2661 20:11:49.005452 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 20:11:49.008890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 20:11:49.008975 ==
2664 20:11:49.012314 DQS Delay:
2665 20:11:49.012422 DQS0 = 0, DQS1 = 0
2666 20:11:49.015854 DQM Delay:
2667 20:11:49.015951 DQM0 = 116, DQM1 = 107
2668 20:11:49.016016 DQ Delay:
2669 20:11:49.020061 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2670 20:11:49.022388 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2671 20:11:49.025554 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2672 20:11:49.032596 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2673 20:11:49.032678
2674 20:11:49.032742
2675 20:11:49.032801 ==
2676 20:11:49.036506 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 20:11:49.039263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 20:11:49.039340 ==
2679 20:11:49.039402
2680 20:11:49.039460
2681 20:11:49.043180 TX Vref Scan disable
2682 20:11:49.043310 == TX Byte 0 ==
2683 20:11:49.049216 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2684 20:11:49.052683 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2685 20:11:49.052783 == TX Byte 1 ==
2686 20:11:49.059216 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2687 20:11:49.063131 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2688 20:11:49.063246 ==
2689 20:11:49.065963 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 20:11:49.069377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 20:11:49.069452 ==
2692 20:11:49.082273 TX Vref=22, minBit 1, minWin=24, winSum=414
2693 20:11:49.085139 TX Vref=24, minBit 7, minWin=25, winSum=421
2694 20:11:49.088474 TX Vref=26, minBit 1, minWin=25, winSum=423
2695 20:11:49.092291 TX Vref=28, minBit 1, minWin=25, winSum=427
2696 20:11:49.095370 TX Vref=30, minBit 0, minWin=26, winSum=428
2697 20:11:49.098874 TX Vref=32, minBit 1, minWin=26, winSum=432
2698 20:11:49.105068 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 32
2699 20:11:49.105191
2700 20:11:49.108625 Final TX Range 1 Vref 32
2701 20:11:49.108735
2702 20:11:49.108827 ==
2703 20:11:49.112354 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 20:11:49.115263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 20:11:49.115361 ==
2706 20:11:49.115473
2707 20:11:49.115583
2708 20:11:49.118661 TX Vref Scan disable
2709 20:11:49.122379 == TX Byte 0 ==
2710 20:11:49.125588 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2711 20:11:49.128888 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2712 20:11:49.132233 == TX Byte 1 ==
2713 20:11:49.135492 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2714 20:11:49.139289 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2715 20:11:49.139373
2716 20:11:49.142652 [DATLAT]
2717 20:11:49.142734 Freq=1200, CH0 RK0
2718 20:11:49.142800
2719 20:11:49.145759 DATLAT Default: 0xd
2720 20:11:49.145840 0, 0xFFFF, sum = 0
2721 20:11:49.148999 1, 0xFFFF, sum = 0
2722 20:11:49.149083 2, 0xFFFF, sum = 0
2723 20:11:49.152126 3, 0xFFFF, sum = 0
2724 20:11:49.152210 4, 0xFFFF, sum = 0
2725 20:11:49.155606 5, 0xFFFF, sum = 0
2726 20:11:49.155690 6, 0xFFFF, sum = 0
2727 20:11:49.159041 7, 0xFFFF, sum = 0
2728 20:11:49.159124 8, 0xFFFF, sum = 0
2729 20:11:49.162354 9, 0xFFFF, sum = 0
2730 20:11:49.162474 10, 0xFFFF, sum = 0
2731 20:11:49.166565 11, 0xFFFF, sum = 0
2732 20:11:49.166666 12, 0x0, sum = 1
2733 20:11:49.169352 13, 0x0, sum = 2
2734 20:11:49.169436 14, 0x0, sum = 3
2735 20:11:49.173078 15, 0x0, sum = 4
2736 20:11:49.173162 best_step = 13
2737 20:11:49.173227
2738 20:11:49.173287 ==
2739 20:11:49.176032 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 20:11:49.179691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 20:11:49.182672 ==
2742 20:11:49.182773 RX Vref Scan: 1
2743 20:11:49.182839
2744 20:11:49.185944 Set Vref Range= 32 -> 127
2745 20:11:49.186026
2746 20:11:49.189325 RX Vref 32 -> 127, step: 1
2747 20:11:49.189408
2748 20:11:49.189474 RX Delay -21 -> 252, step: 4
2749 20:11:49.189535
2750 20:11:49.192583 Set Vref, RX VrefLevel [Byte0]: 32
2751 20:11:49.196079 [Byte1]: 32
2752 20:11:49.199913
2753 20:11:49.200000 Set Vref, RX VrefLevel [Byte0]: 33
2754 20:11:49.203507 [Byte1]: 33
2755 20:11:49.207976
2756 20:11:49.208063 Set Vref, RX VrefLevel [Byte0]: 34
2757 20:11:49.211274 [Byte1]: 34
2758 20:11:49.215701
2759 20:11:49.215791 Set Vref, RX VrefLevel [Byte0]: 35
2760 20:11:49.219249 [Byte1]: 35
2761 20:11:49.224030
2762 20:11:49.224169 Set Vref, RX VrefLevel [Byte0]: 36
2763 20:11:49.227267 [Byte1]: 36
2764 20:11:49.231573
2765 20:11:49.231756 Set Vref, RX VrefLevel [Byte0]: 37
2766 20:11:49.235184 [Byte1]: 37
2767 20:11:49.239593
2768 20:11:49.239692 Set Vref, RX VrefLevel [Byte0]: 38
2769 20:11:49.242890 [Byte1]: 38
2770 20:11:49.247678
2771 20:11:49.247778 Set Vref, RX VrefLevel [Byte0]: 39
2772 20:11:49.251002 [Byte1]: 39
2773 20:11:49.255866
2774 20:11:49.255952 Set Vref, RX VrefLevel [Byte0]: 40
2775 20:11:49.258614 [Byte1]: 40
2776 20:11:49.263356
2777 20:11:49.263441 Set Vref, RX VrefLevel [Byte0]: 41
2778 20:11:49.266896 [Byte1]: 41
2779 20:11:49.271251
2780 20:11:49.271335 Set Vref, RX VrefLevel [Byte0]: 42
2781 20:11:49.275235 [Byte1]: 42
2782 20:11:49.279531
2783 20:11:49.279615 Set Vref, RX VrefLevel [Byte0]: 43
2784 20:11:49.282741 [Byte1]: 43
2785 20:11:49.287194
2786 20:11:49.287278 Set Vref, RX VrefLevel [Byte0]: 44
2787 20:11:49.290517 [Byte1]: 44
2788 20:11:49.295122
2789 20:11:49.295234 Set Vref, RX VrefLevel [Byte0]: 45
2790 20:11:49.298507 [Byte1]: 45
2791 20:11:49.303084
2792 20:11:49.303170 Set Vref, RX VrefLevel [Byte0]: 46
2793 20:11:49.306994 [Byte1]: 46
2794 20:11:49.311082
2795 20:11:49.311166 Set Vref, RX VrefLevel [Byte0]: 47
2796 20:11:49.314592 [Byte1]: 47
2797 20:11:49.318978
2798 20:11:49.319063 Set Vref, RX VrefLevel [Byte0]: 48
2799 20:11:49.322145 [Byte1]: 48
2800 20:11:49.326998
2801 20:11:49.327114 Set Vref, RX VrefLevel [Byte0]: 49
2802 20:11:49.329991 [Byte1]: 49
2803 20:11:49.334668
2804 20:11:49.334752 Set Vref, RX VrefLevel [Byte0]: 50
2805 20:11:49.337944 [Byte1]: 50
2806 20:11:49.343014
2807 20:11:49.343100 Set Vref, RX VrefLevel [Byte0]: 51
2808 20:11:49.346003 [Byte1]: 51
2809 20:11:49.350677
2810 20:11:49.350760 Set Vref, RX VrefLevel [Byte0]: 52
2811 20:11:49.354060 [Byte1]: 52
2812 20:11:49.358530
2813 20:11:49.358713 Set Vref, RX VrefLevel [Byte0]: 53
2814 20:11:49.361647 [Byte1]: 53
2815 20:11:49.366288
2816 20:11:49.366371 Set Vref, RX VrefLevel [Byte0]: 54
2817 20:11:49.370250 [Byte1]: 54
2818 20:11:49.374764
2819 20:11:49.374890 Set Vref, RX VrefLevel [Byte0]: 55
2820 20:11:49.377559 [Byte1]: 55
2821 20:11:49.382206
2822 20:11:49.382326 Set Vref, RX VrefLevel [Byte0]: 56
2823 20:11:49.385639 [Byte1]: 56
2824 20:11:49.390382
2825 20:11:49.390540 Set Vref, RX VrefLevel [Byte0]: 57
2826 20:11:49.394239 [Byte1]: 57
2827 20:11:49.398286
2828 20:11:49.398414 Set Vref, RX VrefLevel [Byte0]: 58
2829 20:11:49.401516 [Byte1]: 58
2830 20:11:49.406321
2831 20:11:49.406442 Set Vref, RX VrefLevel [Byte0]: 59
2832 20:11:49.409588 [Byte1]: 59
2833 20:11:49.414002
2834 20:11:49.414163 Set Vref, RX VrefLevel [Byte0]: 60
2835 20:11:49.417472 [Byte1]: 60
2836 20:11:49.422141
2837 20:11:49.422253 Set Vref, RX VrefLevel [Byte0]: 61
2838 20:11:49.425352 [Byte1]: 61
2839 20:11:49.430718
2840 20:11:49.430845 Set Vref, RX VrefLevel [Byte0]: 62
2841 20:11:49.433094 [Byte1]: 62
2842 20:11:49.437762
2843 20:11:49.437844 Set Vref, RX VrefLevel [Byte0]: 63
2844 20:11:49.440900 [Byte1]: 63
2845 20:11:49.445779
2846 20:11:49.445877 Set Vref, RX VrefLevel [Byte0]: 64
2847 20:11:49.448850 [Byte1]: 64
2848 20:11:49.454067
2849 20:11:49.454187 Set Vref, RX VrefLevel [Byte0]: 65
2850 20:11:49.456875 [Byte1]: 65
2851 20:11:49.461990
2852 20:11:49.462073 Set Vref, RX VrefLevel [Byte0]: 66
2853 20:11:49.464628 [Byte1]: 66
2854 20:11:49.469482
2855 20:11:49.469563 Set Vref, RX VrefLevel [Byte0]: 67
2856 20:11:49.472656 [Byte1]: 67
2857 20:11:49.477364
2858 20:11:49.477445 Set Vref, RX VrefLevel [Byte0]: 68
2859 20:11:49.480815 [Byte1]: 68
2860 20:11:49.485624
2861 20:11:49.485706 Set Vref, RX VrefLevel [Byte0]: 69
2862 20:11:49.488499 [Byte1]: 69
2863 20:11:49.493176
2864 20:11:49.493260 Set Vref, RX VrefLevel [Byte0]: 70
2865 20:11:49.496689 [Byte1]: 70
2866 20:11:49.501385
2867 20:11:49.501468 Final RX Vref Byte 0 = 54 to rank0
2868 20:11:49.504537 Final RX Vref Byte 1 = 52 to rank0
2869 20:11:49.508424 Final RX Vref Byte 0 = 54 to rank1
2870 20:11:49.511323 Final RX Vref Byte 1 = 52 to rank1==
2871 20:11:49.515253 Dram Type= 6, Freq= 0, CH_0, rank 0
2872 20:11:49.517934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 20:11:49.521468 ==
2874 20:11:49.521552 DQS Delay:
2875 20:11:49.521618 DQS0 = 0, DQS1 = 0
2876 20:11:49.524944 DQM Delay:
2877 20:11:49.525027 DQM0 = 115, DQM1 = 105
2878 20:11:49.528016 DQ Delay:
2879 20:11:49.531703 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =112
2880 20:11:49.534683 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2881 20:11:49.538282 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2882 20:11:49.541286 DQ12 =116, DQ13 =110, DQ14 =118, DQ15 =114
2883 20:11:49.541373
2884 20:11:49.541439
2885 20:11:49.548207 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
2886 20:11:49.551278 CH0 RK0: MR19=403, MR18=F0
2887 20:11:49.558186 CH0_RK0: MR19=0x403, MR18=0xF0, DQSOSC=410, MR23=63, INC=39, DEC=26
2888 20:11:49.558271
2889 20:11:49.561821 ----->DramcWriteLeveling(PI) begin...
2890 20:11:49.561906 ==
2891 20:11:49.564796 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 20:11:49.568080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 20:11:49.568166 ==
2894 20:11:49.571603 Write leveling (Byte 0): 33 => 33
2895 20:11:49.574880 Write leveling (Byte 1): 28 => 28
2896 20:11:49.578436 DramcWriteLeveling(PI) end<-----
2897 20:11:49.578520
2898 20:11:49.578586 ==
2899 20:11:49.581688 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 20:11:49.584880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 20:11:49.584964 ==
2902 20:11:49.588810 [Gating] SW mode calibration
2903 20:11:49.595253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2904 20:11:49.601529 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2905 20:11:49.605087 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2906 20:11:49.608264 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2907 20:11:49.615071 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 20:11:49.618249 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 20:11:49.621667 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 20:11:49.628369 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 20:11:49.632533 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2912 20:11:49.635637 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2913 20:11:49.642092 1 0 0 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (0 0)
2914 20:11:49.645191 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2915 20:11:49.648741 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 20:11:49.656164 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 20:11:49.659015 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 20:11:49.661993 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 20:11:49.665321 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2920 20:11:49.671928 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2921 20:11:49.675485 1 1 0 | B1->B0 | 3535 4242 | 1 0 | (0 0) (0 0)
2922 20:11:49.679109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 20:11:49.686111 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 20:11:49.688896 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 20:11:49.692333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 20:11:49.698687 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 20:11:49.702925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 20:11:49.705595 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2929 20:11:49.712395 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2930 20:11:49.715777 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 20:11:49.718697 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 20:11:49.725961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 20:11:49.728844 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 20:11:49.732221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 20:11:49.735635 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 20:11:49.742253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 20:11:49.745471 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 20:11:49.749405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 20:11:49.755787 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 20:11:49.759313 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 20:11:49.762262 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 20:11:49.769238 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 20:11:49.773045 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2944 20:11:49.776480 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2945 20:11:49.782340 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2946 20:11:49.782461 Total UI for P1: 0, mck2ui 16
2947 20:11:49.789364 best dqsien dly found for B0: ( 1, 3, 26)
2948 20:11:49.792334 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 20:11:49.795885 Total UI for P1: 0, mck2ui 16
2950 20:11:49.798951 best dqsien dly found for B1: ( 1, 4, 0)
2951 20:11:49.803041 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2952 20:11:49.806094 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2953 20:11:49.806179
2954 20:11:49.809028 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2955 20:11:49.813816 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2956 20:11:49.816134 [Gating] SW calibration Done
2957 20:11:49.816248 ==
2958 20:11:49.819526 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 20:11:49.823027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 20:11:49.823119 ==
2961 20:11:49.826174 RX Vref Scan: 0
2962 20:11:49.826292
2963 20:11:49.826388 RX Vref 0 -> 0, step: 1
2964 20:11:49.826484
2965 20:11:49.829537 RX Delay -40 -> 252, step: 8
2966 20:11:49.836120 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2967 20:11:49.839307 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2968 20:11:49.843045 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2969 20:11:49.846526 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2970 20:11:49.849742 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2971 20:11:49.852876 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2972 20:11:49.859553 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2973 20:11:49.862583 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2974 20:11:49.865938 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2975 20:11:49.869306 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2976 20:11:49.872978 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2977 20:11:49.879535 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2978 20:11:49.883022 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2979 20:11:49.886326 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2980 20:11:49.890142 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2981 20:11:49.892768 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2982 20:11:49.892853 ==
2983 20:11:49.896663 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 20:11:49.903421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 20:11:49.903509 ==
2986 20:11:49.903576 DQS Delay:
2987 20:11:49.906943 DQS0 = 0, DQS1 = 0
2988 20:11:49.907026 DQM Delay:
2989 20:11:49.907093 DQM0 = 115, DQM1 = 106
2990 20:11:49.909782 DQ Delay:
2991 20:11:49.913163 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2992 20:11:49.916366 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2993 20:11:49.920412 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2994 20:11:49.923819 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2995 20:11:49.923909
2996 20:11:49.923976
2997 20:11:49.924038 ==
2998 20:11:49.926964 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 20:11:49.929830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 20:11:49.929920 ==
3001 20:11:49.929987
3002 20:11:49.933349
3003 20:11:49.933435 TX Vref Scan disable
3004 20:11:49.936632 == TX Byte 0 ==
3005 20:11:49.940013 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3006 20:11:49.943132 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3007 20:11:49.946456 == TX Byte 1 ==
3008 20:11:49.950427 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3009 20:11:49.953853 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3010 20:11:49.954030 ==
3011 20:11:49.956809 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 20:11:49.960282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 20:11:49.963572 ==
3014 20:11:49.974052 TX Vref=22, minBit 0, minWin=25, winSum=424
3015 20:11:49.977474 TX Vref=24, minBit 3, minWin=25, winSum=425
3016 20:11:49.980617 TX Vref=26, minBit 0, minWin=26, winSum=432
3017 20:11:49.984488 TX Vref=28, minBit 2, minWin=26, winSum=434
3018 20:11:49.987784 TX Vref=30, minBit 2, minWin=26, winSum=436
3019 20:11:49.990965 TX Vref=32, minBit 0, minWin=27, winSum=438
3020 20:11:49.997394 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 32
3021 20:11:49.997563
3022 20:11:50.000904 Final TX Range 1 Vref 32
3023 20:11:50.001052
3024 20:11:50.001151 ==
3025 20:11:50.004439 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 20:11:50.007583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 20:11:50.007681 ==
3028 20:11:50.007749
3029 20:11:50.007811
3030 20:11:50.011558 TX Vref Scan disable
3031 20:11:50.014465 == TX Byte 0 ==
3032 20:11:50.017925 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3033 20:11:50.020925 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3034 20:11:50.024320 == TX Byte 1 ==
3035 20:11:50.027777 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3036 20:11:50.030960 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3037 20:11:50.031047
3038 20:11:50.034566 [DATLAT]
3039 20:11:50.034668 Freq=1200, CH0 RK1
3040 20:11:50.034763
3041 20:11:50.038364 DATLAT Default: 0xd
3042 20:11:50.038491 0, 0xFFFF, sum = 0
3043 20:11:50.041230 1, 0xFFFF, sum = 0
3044 20:11:50.041345 2, 0xFFFF, sum = 0
3045 20:11:50.044332 3, 0xFFFF, sum = 0
3046 20:11:50.044448 4, 0xFFFF, sum = 0
3047 20:11:50.048055 5, 0xFFFF, sum = 0
3048 20:11:50.048161 6, 0xFFFF, sum = 0
3049 20:11:50.051430 7, 0xFFFF, sum = 0
3050 20:11:50.051541 8, 0xFFFF, sum = 0
3051 20:11:50.054806 9, 0xFFFF, sum = 0
3052 20:11:50.054923 10, 0xFFFF, sum = 0
3053 20:11:50.058058 11, 0xFFFF, sum = 0
3054 20:11:50.058165 12, 0x0, sum = 1
3055 20:11:50.061175 13, 0x0, sum = 2
3056 20:11:50.061303 14, 0x0, sum = 3
3057 20:11:50.064618 15, 0x0, sum = 4
3058 20:11:50.064726 best_step = 13
3059 20:11:50.064818
3060 20:11:50.064906 ==
3061 20:11:50.068061 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 20:11:50.074578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 20:11:50.074680 ==
3064 20:11:50.074748 RX Vref Scan: 0
3065 20:11:50.074810
3066 20:11:50.078195 RX Vref 0 -> 0, step: 1
3067 20:11:50.078315
3068 20:11:50.081307 RX Delay -21 -> 252, step: 4
3069 20:11:50.084907 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3070 20:11:50.087994 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3071 20:11:50.092382 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
3072 20:11:50.098124 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3073 20:11:50.101483 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3074 20:11:50.105156 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3075 20:11:50.108991 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3076 20:11:50.111411 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3077 20:11:50.117928 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3078 20:11:50.121358 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3079 20:11:50.124943 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3080 20:11:50.128157 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3081 20:11:50.131968 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3082 20:11:50.137962 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3083 20:11:50.141528 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3084 20:11:50.144660 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3085 20:11:50.144773 ==
3086 20:11:50.148475 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 20:11:50.151441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 20:11:50.151548 ==
3089 20:11:50.154803 DQS Delay:
3090 20:11:50.154881 DQS0 = 0, DQS1 = 0
3091 20:11:50.158561 DQM Delay:
3092 20:11:50.158650 DQM0 = 114, DQM1 = 104
3093 20:11:50.158715 DQ Delay:
3094 20:11:50.161557 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
3095 20:11:50.165169 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3096 20:11:50.168650 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3097 20:11:50.174738 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3098 20:11:50.174825
3099 20:11:50.174891
3100 20:11:50.181487 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3101 20:11:50.185196 CH0 RK1: MR19=403, MR18=4F5
3102 20:11:50.191453 CH0_RK1: MR19=0x403, MR18=0x4F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3103 20:11:50.195241 [RxdqsGatingPostProcess] freq 1200
3104 20:11:50.198550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 20:11:50.201985 best DQS0 dly(2T, 0.5T) = (0, 12)
3106 20:11:50.205122 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 20:11:50.208820 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3108 20:11:50.212194 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 20:11:50.215231 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 20:11:50.218141 best DQS1 dly(2T, 0.5T) = (0, 12)
3111 20:11:50.221449 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 20:11:50.225099 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3113 20:11:50.228386 Pre-setting of DQS Precalculation
3114 20:11:50.231621 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 20:11:50.231706 ==
3116 20:11:50.235523 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 20:11:50.238636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 20:11:50.238723 ==
3119 20:11:50.245163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 20:11:50.252133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 20:11:50.259891 [CA 0] Center 38 (8~68) winsize 61
3122 20:11:50.263276 [CA 1] Center 38 (8~68) winsize 61
3123 20:11:50.267065 [CA 2] Center 35 (5~65) winsize 61
3124 20:11:50.269585 [CA 3] Center 34 (4~65) winsize 62
3125 20:11:50.273279 [CA 4] Center 34 (4~65) winsize 62
3126 20:11:50.276748 [CA 5] Center 34 (4~64) winsize 61
3127 20:11:50.276869
3128 20:11:50.279912 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 20:11:50.279994
3130 20:11:50.283505 [CATrainingPosCal] consider 1 rank data
3131 20:11:50.286375 u2DelayCellTimex100 = 270/100 ps
3132 20:11:50.289682 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3133 20:11:50.293141 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3134 20:11:50.296901 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3135 20:11:50.303797 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3136 20:11:50.306523 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3137 20:11:50.309926 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3138 20:11:50.310003
3139 20:11:50.313124 CA PerBit enable=1, Macro0, CA PI delay=34
3140 20:11:50.313224
3141 20:11:50.316753 [CBTSetCACLKResult] CA Dly = 34
3142 20:11:50.316854 CS Dly: 6 (0~37)
3143 20:11:50.316944 ==
3144 20:11:50.319777 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 20:11:50.326872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 20:11:50.326984 ==
3147 20:11:50.330112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 20:11:50.336802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3149 20:11:50.345330 [CA 0] Center 38 (8~68) winsize 61
3150 20:11:50.348818 [CA 1] Center 38 (8~68) winsize 61
3151 20:11:50.351739 [CA 2] Center 34 (4~65) winsize 62
3152 20:11:50.355479 [CA 3] Center 34 (4~65) winsize 62
3153 20:11:50.358828 [CA 4] Center 34 (4~65) winsize 62
3154 20:11:50.362777 [CA 5] Center 33 (3~63) winsize 61
3155 20:11:50.362940
3156 20:11:50.365284 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3157 20:11:50.365414
3158 20:11:50.368738 [CATrainingPosCal] consider 2 rank data
3159 20:11:50.371784 u2DelayCellTimex100 = 270/100 ps
3160 20:11:50.375316 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3161 20:11:50.378882 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3162 20:11:50.381966 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 20:11:50.388998 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3164 20:11:50.392829 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3165 20:11:50.395827 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 20:11:50.395917
3167 20:11:50.398938 CA PerBit enable=1, Macro0, CA PI delay=33
3168 20:11:50.399023
3169 20:11:50.402656 [CBTSetCACLKResult] CA Dly = 33
3170 20:11:50.402744 CS Dly: 7 (0~40)
3171 20:11:50.402812
3172 20:11:50.405553 ----->DramcWriteLeveling(PI) begin...
3173 20:11:50.405638 ==
3174 20:11:50.409059 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 20:11:50.415867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 20:11:50.415957 ==
3177 20:11:50.418954 Write leveling (Byte 0): 26 => 26
3178 20:11:50.419082 Write leveling (Byte 1): 31 => 31
3179 20:11:50.422382 DramcWriteLeveling(PI) end<-----
3180 20:11:50.422486
3181 20:11:50.422554 ==
3182 20:11:50.425844 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 20:11:50.433074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 20:11:50.433173 ==
3185 20:11:50.436010 [Gating] SW mode calibration
3186 20:11:50.442516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 20:11:50.445973 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 20:11:50.452956 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3189 20:11:50.455874 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 20:11:50.459167 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 20:11:50.462917 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 20:11:50.469802 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 20:11:50.473139 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 20:11:50.476627 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 20:11:50.482511 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3196 20:11:50.486203 1 0 0 | B1->B0 | 2525 2e2e | 0 0 | (1 1) (0 1)
3197 20:11:50.489676 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 20:11:50.496132 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 20:11:50.499117 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 20:11:50.502418 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 20:11:50.509670 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 20:11:50.512469 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 20:11:50.516028 1 0 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3204 20:11:50.523126 1 1 0 | B1->B0 | 4242 3939 | 0 0 | (0 0) (0 0)
3205 20:11:50.525932 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 20:11:50.529673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 20:11:50.535916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 20:11:50.539288 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 20:11:50.542890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 20:11:50.546772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 20:11:50.552868 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 20:11:50.556388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3213 20:11:50.559894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 20:11:50.566339 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 20:11:50.570347 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 20:11:50.572898 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 20:11:50.579952 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 20:11:50.583326 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 20:11:50.586762 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 20:11:50.593148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 20:11:50.596554 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 20:11:50.600053 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 20:11:50.603558 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 20:11:50.610133 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 20:11:50.613507 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 20:11:50.616838 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 20:11:50.623503 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3228 20:11:50.626804 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 20:11:50.630872 Total UI for P1: 0, mck2ui 16
3230 20:11:50.633760 best dqsien dly found for B0: ( 1, 3, 28)
3231 20:11:50.636867 Total UI for P1: 0, mck2ui 16
3232 20:11:50.640819 best dqsien dly found for B1: ( 1, 3, 30)
3233 20:11:50.644189 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3234 20:11:50.647521 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3235 20:11:50.647612
3236 20:11:50.650775 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3237 20:11:50.654047 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3238 20:11:50.657488 [Gating] SW calibration Done
3239 20:11:50.657593 ==
3240 20:11:50.660353 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 20:11:50.664008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 20:11:50.664110 ==
3243 20:11:50.667556 RX Vref Scan: 0
3244 20:11:50.667664
3245 20:11:50.670715 RX Vref 0 -> 0, step: 1
3246 20:11:50.670792
3247 20:11:50.670874 RX Delay -40 -> 252, step: 8
3248 20:11:50.677306 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3249 20:11:50.681174 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3250 20:11:50.684390 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3251 20:11:50.687512 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3252 20:11:50.690969 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3253 20:11:50.694140 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 20:11:50.700695 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3255 20:11:50.704392 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3256 20:11:50.707283 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3257 20:11:50.710667 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3258 20:11:50.714289 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3259 20:11:50.720772 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3260 20:11:50.724040 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3261 20:11:50.727298 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3262 20:11:50.730488 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3263 20:11:50.734028 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3264 20:11:50.737513 ==
3265 20:11:50.740798 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 20:11:50.744524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 20:11:50.744640 ==
3268 20:11:50.744735 DQS Delay:
3269 20:11:50.747396 DQS0 = 0, DQS1 = 0
3270 20:11:50.747514 DQM Delay:
3271 20:11:50.750788 DQM0 = 115, DQM1 = 108
3272 20:11:50.750873 DQ Delay:
3273 20:11:50.754189 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3274 20:11:50.758260 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3275 20:11:50.761179 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3276 20:11:50.764166 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3277 20:11:50.764249
3278 20:11:50.764314
3279 20:11:50.764373 ==
3280 20:11:50.767836 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 20:11:50.771023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 20:11:50.774746 ==
3283 20:11:50.774829
3284 20:11:50.774894
3285 20:11:50.774954 TX Vref Scan disable
3286 20:11:50.777630 == TX Byte 0 ==
3287 20:11:50.780949 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 20:11:50.784142 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 20:11:50.788261 == TX Byte 1 ==
3290 20:11:50.791618 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3291 20:11:50.794515 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3292 20:11:50.797884 ==
3293 20:11:50.797988 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 20:11:50.804508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 20:11:50.804648 ==
3296 20:11:50.815483 TX Vref=22, minBit 1, minWin=25, winSum=408
3297 20:11:50.819367 TX Vref=24, minBit 15, minWin=24, winSum=412
3298 20:11:50.822239 TX Vref=26, minBit 13, minWin=25, winSum=421
3299 20:11:50.825896 TX Vref=28, minBit 1, minWin=26, winSum=427
3300 20:11:50.828903 TX Vref=30, minBit 1, minWin=26, winSum=426
3301 20:11:50.836019 TX Vref=32, minBit 12, minWin=25, winSum=426
3302 20:11:50.839374 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3303 20:11:50.839502
3304 20:11:50.842175 Final TX Range 1 Vref 28
3305 20:11:50.842290
3306 20:11:50.842386 ==
3307 20:11:50.845647 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 20:11:50.849200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 20:11:50.849315 ==
3310 20:11:50.849407
3311 20:11:50.852842
3312 20:11:50.852936 TX Vref Scan disable
3313 20:11:50.855907 == TX Byte 0 ==
3314 20:11:50.859569 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 20:11:50.862693 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 20:11:50.865740 == TX Byte 1 ==
3317 20:11:50.869371 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3318 20:11:50.873274 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3319 20:11:50.873348
3320 20:11:50.875829 [DATLAT]
3321 20:11:50.875931 Freq=1200, CH1 RK0
3322 20:11:50.876023
3323 20:11:50.879831 DATLAT Default: 0xd
3324 20:11:50.879909 0, 0xFFFF, sum = 0
3325 20:11:50.882616 1, 0xFFFF, sum = 0
3326 20:11:50.882692 2, 0xFFFF, sum = 0
3327 20:11:50.886232 3, 0xFFFF, sum = 0
3328 20:11:50.886357 4, 0xFFFF, sum = 0
3329 20:11:50.890006 5, 0xFFFF, sum = 0
3330 20:11:50.890079 6, 0xFFFF, sum = 0
3331 20:11:50.893100 7, 0xFFFF, sum = 0
3332 20:11:50.893182 8, 0xFFFF, sum = 0
3333 20:11:50.896762 9, 0xFFFF, sum = 0
3334 20:11:50.896837 10, 0xFFFF, sum = 0
3335 20:11:50.899603 11, 0xFFFF, sum = 0
3336 20:11:50.899689 12, 0x0, sum = 1
3337 20:11:50.902788 13, 0x0, sum = 2
3338 20:11:50.902870 14, 0x0, sum = 3
3339 20:11:50.906629 15, 0x0, sum = 4
3340 20:11:50.906714 best_step = 13
3341 20:11:50.906781
3342 20:11:50.906843 ==
3343 20:11:50.909817 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 20:11:50.916545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 20:11:50.916679 ==
3346 20:11:50.916796 RX Vref Scan: 1
3347 20:11:50.916916
3348 20:11:50.919387 Set Vref Range= 32 -> 127
3349 20:11:50.919508
3350 20:11:50.923339 RX Vref 32 -> 127, step: 1
3351 20:11:50.923464
3352 20:11:50.923586 RX Delay -21 -> 252, step: 4
3353 20:11:50.926353
3354 20:11:50.926517 Set Vref, RX VrefLevel [Byte0]: 32
3355 20:11:50.929871 [Byte1]: 32
3356 20:11:50.934113
3357 20:11:50.934194 Set Vref, RX VrefLevel [Byte0]: 33
3358 20:11:50.937708 [Byte1]: 33
3359 20:11:50.941839
3360 20:11:50.941921 Set Vref, RX VrefLevel [Byte0]: 34
3361 20:11:50.945116 [Byte1]: 34
3362 20:11:50.949831
3363 20:11:50.949954 Set Vref, RX VrefLevel [Byte0]: 35
3364 20:11:50.953394 [Byte1]: 35
3365 20:11:50.957664
3366 20:11:50.957792 Set Vref, RX VrefLevel [Byte0]: 36
3367 20:11:50.960805 [Byte1]: 36
3368 20:11:50.966056
3369 20:11:50.966162 Set Vref, RX VrefLevel [Byte0]: 37
3370 20:11:50.968926 [Byte1]: 37
3371 20:11:50.973484
3372 20:11:50.973562 Set Vref, RX VrefLevel [Byte0]: 38
3373 20:11:50.976639 [Byte1]: 38
3374 20:11:50.981927
3375 20:11:50.982085 Set Vref, RX VrefLevel [Byte0]: 39
3376 20:11:50.984859 [Byte1]: 39
3377 20:11:50.989608
3378 20:11:50.989685 Set Vref, RX VrefLevel [Byte0]: 40
3379 20:11:50.992812 [Byte1]: 40
3380 20:11:50.997108
3381 20:11:50.997192 Set Vref, RX VrefLevel [Byte0]: 41
3382 20:11:51.000528 [Byte1]: 41
3383 20:11:51.005521
3384 20:11:51.005602 Set Vref, RX VrefLevel [Byte0]: 42
3385 20:11:51.008572 [Byte1]: 42
3386 20:11:51.013194
3387 20:11:51.013275 Set Vref, RX VrefLevel [Byte0]: 43
3388 20:11:51.016558 [Byte1]: 43
3389 20:11:51.021171
3390 20:11:51.021246 Set Vref, RX VrefLevel [Byte0]: 44
3391 20:11:51.024738 [Byte1]: 44
3392 20:11:51.029227
3393 20:11:51.029304 Set Vref, RX VrefLevel [Byte0]: 45
3394 20:11:51.032390 [Byte1]: 45
3395 20:11:51.037208
3396 20:11:51.037287 Set Vref, RX VrefLevel [Byte0]: 46
3397 20:11:51.040343 [Byte1]: 46
3398 20:11:51.044749
3399 20:11:51.044832 Set Vref, RX VrefLevel [Byte0]: 47
3400 20:11:51.048004 [Byte1]: 47
3401 20:11:51.053103
3402 20:11:51.053181 Set Vref, RX VrefLevel [Byte0]: 48
3403 20:11:51.056281 [Byte1]: 48
3404 20:11:51.061046
3405 20:11:51.061120 Set Vref, RX VrefLevel [Byte0]: 49
3406 20:11:51.064123 [Byte1]: 49
3407 20:11:51.069030
3408 20:11:51.069106 Set Vref, RX VrefLevel [Byte0]: 50
3409 20:11:51.071812 [Byte1]: 50
3410 20:11:51.076467
3411 20:11:51.076547 Set Vref, RX VrefLevel [Byte0]: 51
3412 20:11:51.080330 [Byte1]: 51
3413 20:11:51.084543
3414 20:11:51.084617 Set Vref, RX VrefLevel [Byte0]: 52
3415 20:11:51.087734 [Byte1]: 52
3416 20:11:51.092321
3417 20:11:51.092398 Set Vref, RX VrefLevel [Byte0]: 53
3418 20:11:51.096146 [Byte1]: 53
3419 20:11:51.100570
3420 20:11:51.100651 Set Vref, RX VrefLevel [Byte0]: 54
3421 20:11:51.103684 [Byte1]: 54
3422 20:11:51.108125
3423 20:11:51.111359 Set Vref, RX VrefLevel [Byte0]: 55
3424 20:11:51.111439 [Byte1]: 55
3425 20:11:51.116103
3426 20:11:51.116183 Set Vref, RX VrefLevel [Byte0]: 56
3427 20:11:51.119784 [Byte1]: 56
3428 20:11:51.124253
3429 20:11:51.124332 Set Vref, RX VrefLevel [Byte0]: 57
3430 20:11:51.127413 [Byte1]: 57
3431 20:11:51.131853
3432 20:11:51.131932 Set Vref, RX VrefLevel [Byte0]: 58
3433 20:11:51.135605 [Byte1]: 58
3434 20:11:51.140038
3435 20:11:51.140117 Set Vref, RX VrefLevel [Byte0]: 59
3436 20:11:51.143863 [Byte1]: 59
3437 20:11:51.147908
3438 20:11:51.147987 Set Vref, RX VrefLevel [Byte0]: 60
3439 20:11:51.151363 [Byte1]: 60
3440 20:11:51.155787
3441 20:11:51.155867 Set Vref, RX VrefLevel [Byte0]: 61
3442 20:11:51.159102 [Byte1]: 61
3443 20:11:51.163833
3444 20:11:51.163913 Set Vref, RX VrefLevel [Byte0]: 62
3445 20:11:51.166914 [Byte1]: 62
3446 20:11:51.171507
3447 20:11:51.171590 Set Vref, RX VrefLevel [Byte0]: 63
3448 20:11:51.174767 [Byte1]: 63
3449 20:11:51.179249
3450 20:11:51.179329 Set Vref, RX VrefLevel [Byte0]: 64
3451 20:11:51.182818 [Byte1]: 64
3452 20:11:51.187264
3453 20:11:51.187343 Set Vref, RX VrefLevel [Byte0]: 65
3454 20:11:51.190744 [Byte1]: 65
3455 20:11:51.195598
3456 20:11:51.195678 Set Vref, RX VrefLevel [Byte0]: 66
3457 20:11:51.198797 [Byte1]: 66
3458 20:11:51.203368
3459 20:11:51.203449 Set Vref, RX VrefLevel [Byte0]: 67
3460 20:11:51.206963 [Byte1]: 67
3461 20:11:51.211077
3462 20:11:51.211157 Set Vref, RX VrefLevel [Byte0]: 68
3463 20:11:51.214535 [Byte1]: 68
3464 20:11:51.219433
3465 20:11:51.219513 Set Vref, RX VrefLevel [Byte0]: 69
3466 20:11:51.223014 [Byte1]: 69
3467 20:11:51.227337
3468 20:11:51.227417 Final RX Vref Byte 0 = 56 to rank0
3469 20:11:51.230648 Final RX Vref Byte 1 = 51 to rank0
3470 20:11:51.233893 Final RX Vref Byte 0 = 56 to rank1
3471 20:11:51.237340 Final RX Vref Byte 1 = 51 to rank1==
3472 20:11:51.240312 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 20:11:51.247257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 20:11:51.247339 ==
3475 20:11:51.247403 DQS Delay:
3476 20:11:51.247461 DQS0 = 0, DQS1 = 0
3477 20:11:51.250575 DQM Delay:
3478 20:11:51.250654 DQM0 = 116, DQM1 = 109
3479 20:11:51.253634 DQ Delay:
3480 20:11:51.257276 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3481 20:11:51.260264 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3482 20:11:51.263707 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3483 20:11:51.267184 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3484 20:11:51.267265
3485 20:11:51.267388
3486 20:11:51.273786 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3487 20:11:51.277052 CH1 RK0: MR19=303, MR18=FCE0
3488 20:11:51.284031 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3489 20:11:51.284112
3490 20:11:51.287153 ----->DramcWriteLeveling(PI) begin...
3491 20:11:51.287235 ==
3492 20:11:51.290783 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 20:11:51.293894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 20:11:51.293974 ==
3495 20:11:51.297269 Write leveling (Byte 0): 27 => 27
3496 20:11:51.300593 Write leveling (Byte 1): 28 => 28
3497 20:11:51.303816 DramcWriteLeveling(PI) end<-----
3498 20:11:51.303896
3499 20:11:51.303960 ==
3500 20:11:51.307474 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 20:11:51.313746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 20:11:51.313831 ==
3503 20:11:51.313895 [Gating] SW mode calibration
3504 20:11:51.323910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 20:11:51.327521 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 20:11:51.330860 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3507 20:11:51.337465 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 20:11:51.340505 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3509 20:11:51.345052 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 20:11:51.351727 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 20:11:51.354360 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 20:11:51.357519 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (0 1) (0 1)
3513 20:11:51.364385 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3514 20:11:51.367464 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 20:11:51.371077 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 20:11:51.374362 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 20:11:51.381136 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 20:11:51.384069 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 20:11:51.387768 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3520 20:11:51.394194 1 0 24 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
3521 20:11:51.397689 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3522 20:11:51.400960 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 20:11:51.407367 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 20:11:51.410654 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 20:11:51.414362 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 20:11:51.421012 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 20:11:51.424161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3528 20:11:51.427708 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3529 20:11:51.434096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3530 20:11:51.437513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 20:11:51.440880 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 20:11:51.447514 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 20:11:51.450829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 20:11:51.455229 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 20:11:51.460885 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 20:11:51.463943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 20:11:51.467693 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 20:11:51.470940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 20:11:51.477493 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 20:11:51.481311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 20:11:51.484337 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 20:11:51.491037 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 20:11:51.494416 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 20:11:51.497838 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3545 20:11:51.501054 Total UI for P1: 0, mck2ui 16
3546 20:11:51.504031 best dqsien dly found for B0: ( 1, 3, 22)
3547 20:11:51.511043 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3548 20:11:51.513988 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 20:11:51.517780 Total UI for P1: 0, mck2ui 16
3550 20:11:51.521057 best dqsien dly found for B1: ( 1, 3, 26)
3551 20:11:51.524441 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3552 20:11:51.527434 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3553 20:11:51.527557
3554 20:11:51.530743 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3555 20:11:51.534589 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3556 20:11:51.537841 [Gating] SW calibration Done
3557 20:11:51.537965 ==
3558 20:11:51.540993 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 20:11:51.544569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 20:11:51.544707 ==
3561 20:11:51.547662 RX Vref Scan: 0
3562 20:11:51.547783
3563 20:11:51.550772 RX Vref 0 -> 0, step: 1
3564 20:11:51.550919
3565 20:11:51.551041 RX Delay -40 -> 252, step: 8
3566 20:11:51.557871 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3567 20:11:51.561951 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3568 20:11:51.564712 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3569 20:11:51.567545 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3570 20:11:51.571450 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3571 20:11:51.578063 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3572 20:11:51.581521 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3573 20:11:51.584672 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3574 20:11:51.587646 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3575 20:11:51.591121 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3576 20:11:51.597590 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3577 20:11:51.600941 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3578 20:11:51.604137 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3579 20:11:51.607759 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3580 20:11:51.610841 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3581 20:11:51.618032 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3582 20:11:51.618163 ==
3583 20:11:51.620849 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 20:11:51.624138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 20:11:51.624268 ==
3586 20:11:51.624390 DQS Delay:
3587 20:11:51.627772 DQS0 = 0, DQS1 = 0
3588 20:11:51.627903 DQM Delay:
3589 20:11:51.631121 DQM0 = 114, DQM1 = 111
3590 20:11:51.631253 DQ Delay:
3591 20:11:51.634160 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3592 20:11:51.637429 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3593 20:11:51.641134 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3594 20:11:51.644193 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3595 20:11:51.644282
3596 20:11:51.644346
3597 20:11:51.647479 ==
3598 20:11:51.650744 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 20:11:51.654821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 20:11:51.654902 ==
3601 20:11:51.654966
3602 20:11:51.655024
3603 20:11:51.658034 TX Vref Scan disable
3604 20:11:51.658115 == TX Byte 0 ==
3605 20:11:51.660919 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 20:11:51.667990 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 20:11:51.668071 == TX Byte 1 ==
3608 20:11:51.671307 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3609 20:11:51.677970 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3610 20:11:51.678051 ==
3611 20:11:51.681128 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 20:11:51.684487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 20:11:51.684568 ==
3614 20:11:51.696081 TX Vref=22, minBit 0, minWin=25, winSum=419
3615 20:11:51.699295 TX Vref=24, minBit 0, minWin=25, winSum=424
3616 20:11:51.703297 TX Vref=26, minBit 0, minWin=26, winSum=430
3617 20:11:51.706172 TX Vref=28, minBit 2, minWin=26, winSum=431
3618 20:11:51.709674 TX Vref=30, minBit 0, minWin=27, winSum=437
3619 20:11:51.712726 TX Vref=32, minBit 2, minWin=26, winSum=432
3620 20:11:51.719820 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 30
3621 20:11:51.719902
3622 20:11:51.722899 Final TX Range 1 Vref 30
3623 20:11:51.722980
3624 20:11:51.723043 ==
3625 20:11:51.726062 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 20:11:51.729935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 20:11:51.730016 ==
3628 20:11:51.730080
3629 20:11:51.730138
3630 20:11:51.733359 TX Vref Scan disable
3631 20:11:51.736291 == TX Byte 0 ==
3632 20:11:51.739703 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3633 20:11:51.742717 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3634 20:11:51.746088 == TX Byte 1 ==
3635 20:11:51.749596 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3636 20:11:51.753222 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3637 20:11:51.753303
3638 20:11:51.756411 [DATLAT]
3639 20:11:51.756491 Freq=1200, CH1 RK1
3640 20:11:51.756555
3641 20:11:51.759741 DATLAT Default: 0xd
3642 20:11:51.759822 0, 0xFFFF, sum = 0
3643 20:11:51.762713 1, 0xFFFF, sum = 0
3644 20:11:51.762795 2, 0xFFFF, sum = 0
3645 20:11:51.767017 3, 0xFFFF, sum = 0
3646 20:11:51.767099 4, 0xFFFF, sum = 0
3647 20:11:51.770322 5, 0xFFFF, sum = 0
3648 20:11:51.770425 6, 0xFFFF, sum = 0
3649 20:11:51.773187 7, 0xFFFF, sum = 0
3650 20:11:51.773280 8, 0xFFFF, sum = 0
3651 20:11:51.776399 9, 0xFFFF, sum = 0
3652 20:11:51.776480 10, 0xFFFF, sum = 0
3653 20:11:51.779394 11, 0xFFFF, sum = 0
3654 20:11:51.783331 12, 0x0, sum = 1
3655 20:11:51.783412 13, 0x0, sum = 2
3656 20:11:51.783477 14, 0x0, sum = 3
3657 20:11:51.786132 15, 0x0, sum = 4
3658 20:11:51.786213 best_step = 13
3659 20:11:51.786276
3660 20:11:51.786334 ==
3661 20:11:51.790218 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 20:11:51.796490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 20:11:51.796571 ==
3664 20:11:51.796635 RX Vref Scan: 0
3665 20:11:51.796694
3666 20:11:51.799502 RX Vref 0 -> 0, step: 1
3667 20:11:51.799582
3668 20:11:51.803008 RX Delay -21 -> 252, step: 4
3669 20:11:51.806174 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3670 20:11:51.809670 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3671 20:11:51.816024 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3672 20:11:51.819675 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3673 20:11:51.823101 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3674 20:11:51.826080 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3675 20:11:51.829709 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3676 20:11:51.835925 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3677 20:11:51.839565 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3678 20:11:51.842935 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3679 20:11:51.846078 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3680 20:11:51.849828 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3681 20:11:51.856380 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3682 20:11:51.859588 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3683 20:11:51.862566 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3684 20:11:51.866293 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3685 20:11:51.866408 ==
3686 20:11:51.869150 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 20:11:51.875928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 20:11:51.876009 ==
3689 20:11:51.876073 DQS Delay:
3690 20:11:51.879236 DQS0 = 0, DQS1 = 0
3691 20:11:51.879317 DQM Delay:
3692 20:11:51.879381 DQM0 = 113, DQM1 = 109
3693 20:11:51.882471 DQ Delay:
3694 20:11:51.885724 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3695 20:11:51.889042 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3696 20:11:51.892448 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3697 20:11:51.896222 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3698 20:11:51.896302
3699 20:11:51.896365
3700 20:11:51.905921 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3701 20:11:51.906004 CH1 RK1: MR19=304, MR18=FA01
3702 20:11:51.912773 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3703 20:11:51.915980 [RxdqsGatingPostProcess] freq 1200
3704 20:11:51.922630 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 20:11:51.926193 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 20:11:51.928983 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 20:11:51.932270 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 20:11:51.932422 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 20:11:51.936099 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 20:11:51.939263 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 20:11:51.942469 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 20:11:51.946039 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 20:11:51.949452 Pre-setting of DQS Precalculation
3714 20:11:51.955721 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 20:11:51.962861 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 20:11:51.969144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 20:11:51.969240
3718 20:11:51.969303
3719 20:11:51.972782 [Calibration Summary] 2400 Mbps
3720 20:11:51.972862 CH 0, Rank 0
3721 20:11:51.975906 SW Impedance : PASS
3722 20:11:51.979245 DUTY Scan : NO K
3723 20:11:51.979325 ZQ Calibration : PASS
3724 20:11:51.982521 Jitter Meter : NO K
3725 20:11:51.986426 CBT Training : PASS
3726 20:11:51.986509 Write leveling : PASS
3727 20:11:51.989076 RX DQS gating : PASS
3728 20:11:51.992280 RX DQ/DQS(RDDQC) : PASS
3729 20:11:51.992389 TX DQ/DQS : PASS
3730 20:11:51.996030 RX DATLAT : PASS
3731 20:11:51.996111 RX DQ/DQS(Engine): PASS
3732 20:11:51.999141 TX OE : NO K
3733 20:11:51.999222 All Pass.
3734 20:11:51.999286
3735 20:11:52.002252 CH 0, Rank 1
3736 20:11:52.002333 SW Impedance : PASS
3737 20:11:52.005945 DUTY Scan : NO K
3738 20:11:52.008940 ZQ Calibration : PASS
3739 20:11:52.009020 Jitter Meter : NO K
3740 20:11:52.012336 CBT Training : PASS
3741 20:11:52.016100 Write leveling : PASS
3742 20:11:52.016185 RX DQS gating : PASS
3743 20:11:52.019832 RX DQ/DQS(RDDQC) : PASS
3744 20:11:52.022727 TX DQ/DQS : PASS
3745 20:11:52.022809 RX DATLAT : PASS
3746 20:11:52.025899 RX DQ/DQS(Engine): PASS
3747 20:11:52.029271 TX OE : NO K
3748 20:11:52.029346 All Pass.
3749 20:11:52.029407
3750 20:11:52.029471 CH 1, Rank 0
3751 20:11:52.032607 SW Impedance : PASS
3752 20:11:52.035642 DUTY Scan : NO K
3753 20:11:52.035714 ZQ Calibration : PASS
3754 20:11:52.039328 Jitter Meter : NO K
3755 20:11:52.042465 CBT Training : PASS
3756 20:11:52.042539 Write leveling : PASS
3757 20:11:52.045607 RX DQS gating : PASS
3758 20:11:52.045683 RX DQ/DQS(RDDQC) : PASS
3759 20:11:52.048785 TX DQ/DQS : PASS
3760 20:11:52.052528 RX DATLAT : PASS
3761 20:11:52.052628 RX DQ/DQS(Engine): PASS
3762 20:11:52.056163 TX OE : NO K
3763 20:11:52.056242 All Pass.
3764 20:11:52.056306
3765 20:11:52.059221 CH 1, Rank 1
3766 20:11:52.059302 SW Impedance : PASS
3767 20:11:52.062736 DUTY Scan : NO K
3768 20:11:52.065755 ZQ Calibration : PASS
3769 20:11:52.065878 Jitter Meter : NO K
3770 20:11:52.068683 CBT Training : PASS
3771 20:11:52.072440 Write leveling : PASS
3772 20:11:52.072560 RX DQS gating : PASS
3773 20:11:52.075931 RX DQ/DQS(RDDQC) : PASS
3774 20:11:52.078715 TX DQ/DQS : PASS
3775 20:11:52.078834 RX DATLAT : PASS
3776 20:11:52.082311 RX DQ/DQS(Engine): PASS
3777 20:11:52.085606 TX OE : NO K
3778 20:11:52.085709 All Pass.
3779 20:11:52.085800
3780 20:11:52.085886 DramC Write-DBI off
3781 20:11:52.089255 PER_BANK_REFRESH: Hybrid Mode
3782 20:11:52.092365 TX_TRACKING: ON
3783 20:11:52.098743 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 20:11:52.102693 [FAST_K] Save calibration result to emmc
3785 20:11:52.109423 dramc_set_vcore_voltage set vcore to 650000
3786 20:11:52.109503 Read voltage for 600, 5
3787 20:11:52.109567 Vio18 = 0
3788 20:11:52.112210 Vcore = 650000
3789 20:11:52.112291 Vdram = 0
3790 20:11:52.112355 Vddq = 0
3791 20:11:52.115281 Vmddr = 0
3792 20:11:52.119072 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 20:11:52.125506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 20:11:52.125627 MEM_TYPE=3, freq_sel=19
3795 20:11:52.128747 sv_algorithm_assistance_LP4_1600
3796 20:11:52.135545 ============ PULL DRAM RESETB DOWN ============
3797 20:11:52.139115 ========== PULL DRAM RESETB DOWN end =========
3798 20:11:52.142854 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 20:11:52.146277 ===================================
3800 20:11:52.149745 LPDDR4 DRAM CONFIGURATION
3801 20:11:52.152273 ===================================
3802 20:11:52.156044 EX_ROW_EN[0] = 0x0
3803 20:11:52.156170 EX_ROW_EN[1] = 0x0
3804 20:11:52.158948 LP4Y_EN = 0x0
3805 20:11:52.159066 WORK_FSP = 0x0
3806 20:11:52.162357 WL = 0x2
3807 20:11:52.162487 RL = 0x2
3808 20:11:52.165713 BL = 0x2
3809 20:11:52.165834 RPST = 0x0
3810 20:11:52.169008 RD_PRE = 0x0
3811 20:11:52.169126 WR_PRE = 0x1
3812 20:11:52.172168 WR_PST = 0x0
3813 20:11:52.172287 DBI_WR = 0x0
3814 20:11:52.175787 DBI_RD = 0x0
3815 20:11:52.175911 OTF = 0x1
3816 20:11:52.179514 ===================================
3817 20:11:52.182494 ===================================
3818 20:11:52.186046 ANA top config
3819 20:11:52.189383 ===================================
3820 20:11:52.189482 DLL_ASYNC_EN = 0
3821 20:11:52.192486 ALL_SLAVE_EN = 1
3822 20:11:52.195948 NEW_RANK_MODE = 1
3823 20:11:52.199696 DLL_IDLE_MODE = 1
3824 20:11:52.199777 LP45_APHY_COMB_EN = 1
3825 20:11:52.202728 TX_ODT_DIS = 1
3826 20:11:52.205817 NEW_8X_MODE = 1
3827 20:11:52.209347 ===================================
3828 20:11:52.212902 ===================================
3829 20:11:52.216234 data_rate = 1200
3830 20:11:52.219521 CKR = 1
3831 20:11:52.223042 DQ_P2S_RATIO = 8
3832 20:11:52.226161 ===================================
3833 20:11:52.226242 CA_P2S_RATIO = 8
3834 20:11:52.229208 DQ_CA_OPEN = 0
3835 20:11:52.232577 DQ_SEMI_OPEN = 0
3836 20:11:52.236050 CA_SEMI_OPEN = 0
3837 20:11:52.239330 CA_FULL_RATE = 0
3838 20:11:52.239411 DQ_CKDIV4_EN = 1
3839 20:11:52.242466 CA_CKDIV4_EN = 1
3840 20:11:52.246365 CA_PREDIV_EN = 0
3841 20:11:52.249591 PH8_DLY = 0
3842 20:11:52.252559 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 20:11:52.256203 DQ_AAMCK_DIV = 4
3844 20:11:52.256283 CA_AAMCK_DIV = 4
3845 20:11:52.259553 CA_ADMCK_DIV = 4
3846 20:11:52.262637 DQ_TRACK_CA_EN = 0
3847 20:11:52.266328 CA_PICK = 600
3848 20:11:52.269347 CA_MCKIO = 600
3849 20:11:52.273122 MCKIO_SEMI = 0
3850 20:11:52.276204 PLL_FREQ = 2288
3851 20:11:52.276285 DQ_UI_PI_RATIO = 32
3852 20:11:52.279737 CA_UI_PI_RATIO = 0
3853 20:11:52.283321 ===================================
3854 20:11:52.286237 ===================================
3855 20:11:52.289692 memory_type:LPDDR4
3856 20:11:52.293015 GP_NUM : 10
3857 20:11:52.293096 SRAM_EN : 1
3858 20:11:52.296285 MD32_EN : 0
3859 20:11:52.300237 ===================================
3860 20:11:52.300317 [ANA_INIT] >>>>>>>>>>>>>>
3861 20:11:52.303298 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 20:11:52.306504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 20:11:52.310016 ===================================
3864 20:11:52.313172 data_rate = 1200,PCW = 0X5800
3865 20:11:52.316074 ===================================
3866 20:11:52.319865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 20:11:52.326277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 20:11:52.329411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 20:11:52.336633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 20:11:52.339642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 20:11:52.342895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 20:11:52.346371 [ANA_INIT] flow start
3873 20:11:52.346514 [ANA_INIT] PLL >>>>>>>>
3874 20:11:52.349890 [ANA_INIT] PLL <<<<<<<<
3875 20:11:52.352638 [ANA_INIT] MIDPI >>>>>>>>
3876 20:11:52.352720 [ANA_INIT] MIDPI <<<<<<<<
3877 20:11:52.356361 [ANA_INIT] DLL >>>>>>>>
3878 20:11:52.360219 [ANA_INIT] flow end
3879 20:11:52.362898 ============ LP4 DIFF to SE enter ============
3880 20:11:52.366028 ============ LP4 DIFF to SE exit ============
3881 20:11:52.369583 [ANA_INIT] <<<<<<<<<<<<<
3882 20:11:52.373091 [Flow] Enable top DCM control >>>>>
3883 20:11:52.375783 [Flow] Enable top DCM control <<<<<
3884 20:11:52.379366 Enable DLL master slave shuffle
3885 20:11:52.382900 ==============================================================
3886 20:11:52.385629 Gating Mode config
3887 20:11:52.392612 ==============================================================
3888 20:11:52.392694 Config description:
3889 20:11:52.402488 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 20:11:52.408977 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 20:11:52.413037 SELPH_MODE 0: By rank 1: By Phase
3892 20:11:52.419590 ==============================================================
3893 20:11:52.423188 GAT_TRACK_EN = 1
3894 20:11:52.426434 RX_GATING_MODE = 2
3895 20:11:52.429280 RX_GATING_TRACK_MODE = 2
3896 20:11:52.432456 SELPH_MODE = 1
3897 20:11:52.435712 PICG_EARLY_EN = 1
3898 20:11:52.439499 VALID_LAT_VALUE = 1
3899 20:11:52.442571 ==============================================================
3900 20:11:52.446145 Enter into Gating configuration >>>>
3901 20:11:52.449414 Exit from Gating configuration <<<<
3902 20:11:52.452334 Enter into DVFS_PRE_config >>>>>
3903 20:11:52.462880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 20:11:52.466071 Exit from DVFS_PRE_config <<<<<
3905 20:11:52.469821 Enter into PICG configuration >>>>
3906 20:11:52.472568 Exit from PICG configuration <<<<
3907 20:11:52.475727 [RX_INPUT] configuration >>>>>
3908 20:11:52.479806 [RX_INPUT] configuration <<<<<
3909 20:11:52.482662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 20:11:52.489461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 20:11:52.496070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 20:11:52.503060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 20:11:52.509255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 20:11:52.515635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 20:11:52.519642 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 20:11:52.522611 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 20:11:52.525882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 20:11:52.529025 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 20:11:52.535703 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 20:11:52.539309 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 20:11:52.542555 ===================================
3922 20:11:52.546236 LPDDR4 DRAM CONFIGURATION
3923 20:11:52.549158 ===================================
3924 20:11:52.549279 EX_ROW_EN[0] = 0x0
3925 20:11:52.552522 EX_ROW_EN[1] = 0x0
3926 20:11:52.552644 LP4Y_EN = 0x0
3927 20:11:52.555869 WORK_FSP = 0x0
3928 20:11:52.555991 WL = 0x2
3929 20:11:52.559257 RL = 0x2
3930 20:11:52.559379 BL = 0x2
3931 20:11:52.562590 RPST = 0x0
3932 20:11:52.562692 RD_PRE = 0x0
3933 20:11:52.566265 WR_PRE = 0x1
3934 20:11:52.566361 WR_PST = 0x0
3935 20:11:52.569835 DBI_WR = 0x0
3936 20:11:52.569946 DBI_RD = 0x0
3937 20:11:52.572681 OTF = 0x1
3938 20:11:52.576639 ===================================
3939 20:11:52.579479 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 20:11:52.582977 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 20:11:52.589817 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 20:11:52.593043 ===================================
3943 20:11:52.593160 LPDDR4 DRAM CONFIGURATION
3944 20:11:52.595823 ===================================
3945 20:11:52.599346 EX_ROW_EN[0] = 0x10
3946 20:11:52.602888 EX_ROW_EN[1] = 0x0
3947 20:11:52.602972 LP4Y_EN = 0x0
3948 20:11:52.605864 WORK_FSP = 0x0
3949 20:11:52.605941 WL = 0x2
3950 20:11:52.609236 RL = 0x2
3951 20:11:52.609308 BL = 0x2
3952 20:11:52.612660 RPST = 0x0
3953 20:11:52.612734 RD_PRE = 0x0
3954 20:11:52.616260 WR_PRE = 0x1
3955 20:11:52.616330 WR_PST = 0x0
3956 20:11:52.619449 DBI_WR = 0x0
3957 20:11:52.619522 DBI_RD = 0x0
3958 20:11:52.622511 OTF = 0x1
3959 20:11:52.625864 ===================================
3960 20:11:52.632519 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 20:11:52.635686 nWR fixed to 30
3962 20:11:52.639436 [ModeRegInit_LP4] CH0 RK0
3963 20:11:52.639541 [ModeRegInit_LP4] CH0 RK1
3964 20:11:52.642285 [ModeRegInit_LP4] CH1 RK0
3965 20:11:52.646123 [ModeRegInit_LP4] CH1 RK1
3966 20:11:52.646208 match AC timing 17
3967 20:11:52.652428 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 20:11:52.656173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 20:11:52.659125 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 20:11:52.665720 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 20:11:52.669304 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 20:11:52.669392 ==
3973 20:11:52.672585 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 20:11:52.675643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 20:11:52.675726 ==
3976 20:11:52.682878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 20:11:52.689391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3978 20:11:52.692596 [CA 0] Center 36 (6~66) winsize 61
3979 20:11:52.695770 [CA 1] Center 36 (6~66) winsize 61
3980 20:11:52.699092 [CA 2] Center 34 (4~65) winsize 62
3981 20:11:52.702128 [CA 3] Center 34 (4~64) winsize 61
3982 20:11:52.705545 [CA 4] Center 33 (3~64) winsize 62
3983 20:11:52.708978 [CA 5] Center 33 (3~64) winsize 62
3984 20:11:52.709060
3985 20:11:52.712224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3986 20:11:52.712306
3987 20:11:52.716466 [CATrainingPosCal] consider 1 rank data
3988 20:11:52.719847 u2DelayCellTimex100 = 270/100 ps
3989 20:11:52.723039 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3990 20:11:52.725821 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 20:11:52.728998 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 20:11:52.732284 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 20:11:52.735632 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 20:11:52.739235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 20:11:52.739321
3996 20:11:52.742310 CA PerBit enable=1, Macro0, CA PI delay=33
3997 20:11:52.745655
3998 20:11:52.745737 [CBTSetCACLKResult] CA Dly = 33
3999 20:11:52.748990 CS Dly: 4 (0~35)
4000 20:11:52.749071 ==
4001 20:11:52.752562 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 20:11:52.755825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 20:11:52.755908 ==
4004 20:11:52.762279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 20:11:52.769409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 20:11:52.772124 [CA 0] Center 36 (6~66) winsize 61
4007 20:11:52.775606 [CA 1] Center 35 (5~66) winsize 62
4008 20:11:52.778922 [CA 2] Center 34 (4~65) winsize 62
4009 20:11:52.782586 [CA 3] Center 34 (4~65) winsize 62
4010 20:11:52.785649 [CA 4] Center 33 (3~64) winsize 62
4011 20:11:52.789003 [CA 5] Center 33 (3~64) winsize 62
4012 20:11:52.789085
4013 20:11:52.792280 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 20:11:52.792361
4015 20:11:52.796189 [CATrainingPosCal] consider 2 rank data
4016 20:11:52.799244 u2DelayCellTimex100 = 270/100 ps
4017 20:11:52.802939 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4018 20:11:52.805652 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 20:11:52.809590 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4020 20:11:52.812711 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4021 20:11:52.815639 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 20:11:52.818955 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 20:11:52.819036
4024 20:11:52.825853 CA PerBit enable=1, Macro0, CA PI delay=33
4025 20:11:52.825934
4026 20:11:52.825998 [CBTSetCACLKResult] CA Dly = 33
4027 20:11:52.828837 CS Dly: 4 (0~36)
4028 20:11:52.828943
4029 20:11:52.832343 ----->DramcWriteLeveling(PI) begin...
4030 20:11:52.832442 ==
4031 20:11:52.835701 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 20:11:52.838982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 20:11:52.839089 ==
4034 20:11:52.842970 Write leveling (Byte 0): 33 => 33
4035 20:11:52.845636 Write leveling (Byte 1): 29 => 29
4036 20:11:52.849381 DramcWriteLeveling(PI) end<-----
4037 20:11:52.849462
4038 20:11:52.849525 ==
4039 20:11:52.852243 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 20:11:52.856399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 20:11:52.858967 ==
4042 20:11:52.859047 [Gating] SW mode calibration
4043 20:11:52.865582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 20:11:52.872394 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 20:11:52.876383 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 20:11:52.882864 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 20:11:52.885876 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 20:11:52.888976 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 20:11:52.895505 0 9 16 | B1->B0 | 3333 2d2d | 0 0 | (1 1) (1 1)
4050 20:11:52.899202 0 9 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4051 20:11:52.902308 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 20:11:52.905656 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 20:11:52.912282 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 20:11:52.915743 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 20:11:52.919107 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 20:11:52.925691 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 20:11:52.929311 0 10 16 | B1->B0 | 2f2f 3939 | 0 1 | (0 0) (0 0)
4058 20:11:52.932294 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
4059 20:11:52.939123 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 20:11:52.942215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 20:11:52.946115 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 20:11:52.952721 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 20:11:52.956210 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 20:11:52.959227 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 20:11:52.966340 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4066 20:11:52.969134 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 20:11:52.972460 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 20:11:52.979314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 20:11:52.982337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 20:11:52.985942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 20:11:52.989385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 20:11:52.996156 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 20:11:52.999661 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 20:11:53.002724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 20:11:53.009707 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 20:11:53.012358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 20:11:53.016347 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 20:11:53.023033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 20:11:53.026202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 20:11:53.029259 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 20:11:53.035973 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4082 20:11:53.036055 Total UI for P1: 0, mck2ui 16
4083 20:11:53.043085 best dqsien dly found for B0: ( 0, 13, 14)
4084 20:11:53.046278 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4085 20:11:53.049409 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 20:11:53.052477 Total UI for P1: 0, mck2ui 16
4087 20:11:53.056437 best dqsien dly found for B1: ( 0, 13, 18)
4088 20:11:53.059394 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4089 20:11:53.062697 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4090 20:11:53.062779
4091 20:11:53.069183 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4092 20:11:53.072928 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4093 20:11:53.073013 [Gating] SW calibration Done
4094 20:11:53.076152 ==
4095 20:11:53.076232 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 20:11:53.082963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 20:11:53.083044 ==
4098 20:11:53.083108 RX Vref Scan: 0
4099 20:11:53.083167
4100 20:11:53.086891 RX Vref 0 -> 0, step: 1
4101 20:11:53.086973
4102 20:11:53.089392 RX Delay -230 -> 252, step: 16
4103 20:11:53.092877 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4104 20:11:53.095935 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4105 20:11:53.102614 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4106 20:11:53.106070 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4107 20:11:53.109326 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4108 20:11:53.112749 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4109 20:11:53.116122 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4110 20:11:53.122666 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4111 20:11:53.126045 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4112 20:11:53.129408 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4113 20:11:53.132564 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4114 20:11:53.139282 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4115 20:11:53.142723 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4116 20:11:53.145762 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4117 20:11:53.149527 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4118 20:11:53.152446 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4119 20:11:53.155915 ==
4120 20:11:53.159812 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 20:11:53.162868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 20:11:53.162949 ==
4123 20:11:53.163012 DQS Delay:
4124 20:11:53.166109 DQS0 = 0, DQS1 = 0
4125 20:11:53.166189 DQM Delay:
4126 20:11:53.169518 DQM0 = 42, DQM1 = 32
4127 20:11:53.169598 DQ Delay:
4128 20:11:53.172982 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4129 20:11:53.176826 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4130 20:11:53.179336 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4131 20:11:53.183144 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4132 20:11:53.183257
4133 20:11:53.183374
4134 20:11:53.183445 ==
4135 20:11:53.186290 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 20:11:53.189894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 20:11:53.189975 ==
4138 20:11:53.190038
4139 20:11:53.190097
4140 20:11:53.193124 TX Vref Scan disable
4141 20:11:53.196377 == TX Byte 0 ==
4142 20:11:53.199790 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4143 20:11:53.203122 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4144 20:11:53.206154 == TX Byte 1 ==
4145 20:11:53.209556 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4146 20:11:53.213072 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4147 20:11:53.213153 ==
4148 20:11:53.216641 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 20:11:53.219718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 20:11:53.219823 ==
4151 20:11:53.223858
4152 20:11:53.223939
4153 20:11:53.224003 TX Vref Scan disable
4154 20:11:53.226670 == TX Byte 0 ==
4155 20:11:53.230153 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4156 20:11:53.237894 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4157 20:11:53.238012 == TX Byte 1 ==
4158 20:11:53.239989 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4159 20:11:53.246643 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4160 20:11:53.246724
4161 20:11:53.246788 [DATLAT]
4162 20:11:53.246847 Freq=600, CH0 RK0
4163 20:11:53.246904
4164 20:11:53.249832 DATLAT Default: 0x9
4165 20:11:53.249911 0, 0xFFFF, sum = 0
4166 20:11:53.253446 1, 0xFFFF, sum = 0
4167 20:11:53.253528 2, 0xFFFF, sum = 0
4168 20:11:53.256500 3, 0xFFFF, sum = 0
4169 20:11:53.259824 4, 0xFFFF, sum = 0
4170 20:11:53.259913 5, 0xFFFF, sum = 0
4171 20:11:53.263331 6, 0xFFFF, sum = 0
4172 20:11:53.263417 7, 0xFFFF, sum = 0
4173 20:11:53.263504 8, 0x0, sum = 1
4174 20:11:53.266858 9, 0x0, sum = 2
4175 20:11:53.266943 10, 0x0, sum = 3
4176 20:11:53.270216 11, 0x0, sum = 4
4177 20:11:53.270301 best_step = 9
4178 20:11:53.270423
4179 20:11:53.270517 ==
4180 20:11:53.273387 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 20:11:53.280130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 20:11:53.280215 ==
4183 20:11:53.280301 RX Vref Scan: 1
4184 20:11:53.280381
4185 20:11:53.283439 RX Vref 0 -> 0, step: 1
4186 20:11:53.283524
4187 20:11:53.286703 RX Delay -195 -> 252, step: 8
4188 20:11:53.286787
4189 20:11:53.289699 Set Vref, RX VrefLevel [Byte0]: 54
4190 20:11:53.293295 [Byte1]: 52
4191 20:11:53.293380
4192 20:11:53.296752 Final RX Vref Byte 0 = 54 to rank0
4193 20:11:53.300186 Final RX Vref Byte 1 = 52 to rank0
4194 20:11:53.303444 Final RX Vref Byte 0 = 54 to rank1
4195 20:11:53.306839 Final RX Vref Byte 1 = 52 to rank1==
4196 20:11:53.310298 Dram Type= 6, Freq= 0, CH_0, rank 0
4197 20:11:53.313337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 20:11:53.313425 ==
4199 20:11:53.316645 DQS Delay:
4200 20:11:53.316729 DQS0 = 0, DQS1 = 0
4201 20:11:53.316814 DQM Delay:
4202 20:11:53.320165 DQM0 = 42, DQM1 = 33
4203 20:11:53.320287 DQ Delay:
4204 20:11:53.323159 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4205 20:11:53.326599 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4206 20:11:53.329875 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4207 20:11:53.333492 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4208 20:11:53.333576
4209 20:11:53.333661
4210 20:11:53.343238 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4211 20:11:53.343323 CH0 RK0: MR19=808, MR18=4120
4212 20:11:53.350602 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4213 20:11:53.350686
4214 20:11:53.353305 ----->DramcWriteLeveling(PI) begin...
4215 20:11:53.353390 ==
4216 20:11:53.356780 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 20:11:53.363836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 20:11:53.363918 ==
4219 20:11:53.366873 Write leveling (Byte 0): 32 => 32
4220 20:11:53.369910 Write leveling (Byte 1): 30 => 30
4221 20:11:53.369992 DramcWriteLeveling(PI) end<-----
4222 20:11:53.373604
4223 20:11:53.373699 ==
4224 20:11:53.376536 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 20:11:53.379763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 20:11:53.379858 ==
4227 20:11:53.383199 [Gating] SW mode calibration
4228 20:11:53.389992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 20:11:53.394752 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4230 20:11:53.399973 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 20:11:53.403622 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 20:11:53.407102 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 20:11:53.413541 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
4234 20:11:53.416614 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
4235 20:11:53.421104 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 20:11:53.426721 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 20:11:53.430191 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 20:11:53.433449 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 20:11:53.439937 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 20:11:53.443208 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 20:11:53.446792 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4242 20:11:53.453775 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4243 20:11:53.457583 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 20:11:53.459864 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 20:11:53.463552 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 20:11:53.469912 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 20:11:53.473322 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 20:11:53.477052 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 20:11:53.483980 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 20:11:53.486497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4251 20:11:53.490152 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 20:11:53.496611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 20:11:53.500249 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 20:11:53.503414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 20:11:53.510236 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 20:11:53.513265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 20:11:53.516526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 20:11:53.523559 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 20:11:53.527039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 20:11:53.529935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 20:11:53.537676 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 20:11:53.540028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 20:11:53.543740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 20:11:53.546817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 20:11:53.553619 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4266 20:11:53.556779 Total UI for P1: 0, mck2ui 16
4267 20:11:53.559681 best dqsien dly found for B0: ( 0, 13, 10)
4268 20:11:53.563195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4269 20:11:53.566794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 20:11:53.570206 Total UI for P1: 0, mck2ui 16
4271 20:11:53.573641 best dqsien dly found for B1: ( 0, 13, 16)
4272 20:11:53.576892 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4273 20:11:53.583198 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4274 20:11:53.583279
4275 20:11:53.586611 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4276 20:11:53.590097 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4277 20:11:53.593033 [Gating] SW calibration Done
4278 20:11:53.593117 ==
4279 20:11:53.596184 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 20:11:53.600054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 20:11:53.600163 ==
4282 20:11:53.603534 RX Vref Scan: 0
4283 20:11:53.603615
4284 20:11:53.603679 RX Vref 0 -> 0, step: 1
4285 20:11:53.603768
4286 20:11:53.606575 RX Delay -230 -> 252, step: 16
4287 20:11:53.609783 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4288 20:11:53.616984 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4289 20:11:53.619775 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4290 20:11:53.623415 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4291 20:11:53.626530 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4292 20:11:53.629904 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4293 20:11:53.636495 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4294 20:11:53.639897 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4295 20:11:53.642864 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4296 20:11:53.646373 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4297 20:11:53.653198 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4298 20:11:53.656462 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4299 20:11:53.659696 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4300 20:11:53.662835 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4301 20:11:53.669561 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4302 20:11:53.673813 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4303 20:11:53.673894 ==
4304 20:11:53.676313 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 20:11:53.679804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 20:11:53.679885 ==
4307 20:11:53.679949 DQS Delay:
4308 20:11:53.683661 DQS0 = 0, DQS1 = 0
4309 20:11:53.683757 DQM Delay:
4310 20:11:53.686225 DQM0 = 40, DQM1 = 32
4311 20:11:53.686306 DQ Delay:
4312 20:11:53.689947 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4313 20:11:53.693231 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4314 20:11:53.696641 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4315 20:11:53.699639 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4316 20:11:53.699728
4317 20:11:53.699847
4318 20:11:53.699934 ==
4319 20:11:53.703523 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 20:11:53.706798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 20:11:53.709830 ==
4322 20:11:53.709923
4323 20:11:53.709987
4324 20:11:53.710045 TX Vref Scan disable
4325 20:11:53.713530 == TX Byte 0 ==
4326 20:11:53.716426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4327 20:11:53.720024 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4328 20:11:53.723485 == TX Byte 1 ==
4329 20:11:53.726942 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4330 20:11:53.730035 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4331 20:11:53.733570 ==
4332 20:11:53.733685 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 20:11:53.740154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 20:11:53.740247 ==
4335 20:11:53.740340
4336 20:11:53.740427
4337 20:11:53.743073 TX Vref Scan disable
4338 20:11:53.743153 == TX Byte 0 ==
4339 20:11:53.750549 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4340 20:11:53.753080 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4341 20:11:53.753154 == TX Byte 1 ==
4342 20:11:53.760035 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4343 20:11:53.762829 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4344 20:11:53.762924
4345 20:11:53.763001 [DATLAT]
4346 20:11:53.766116 Freq=600, CH0 RK1
4347 20:11:53.766223
4348 20:11:53.766316 DATLAT Default: 0x9
4349 20:11:53.769493 0, 0xFFFF, sum = 0
4350 20:11:53.769602 1, 0xFFFF, sum = 0
4351 20:11:53.772822 2, 0xFFFF, sum = 0
4352 20:11:53.772903 3, 0xFFFF, sum = 0
4353 20:11:53.776975 4, 0xFFFF, sum = 0
4354 20:11:53.777059 5, 0xFFFF, sum = 0
4355 20:11:53.779938 6, 0xFFFF, sum = 0
4356 20:11:53.783396 7, 0xFFFF, sum = 0
4357 20:11:53.783469 8, 0x0, sum = 1
4358 20:11:53.783531 9, 0x0, sum = 2
4359 20:11:53.786220 10, 0x0, sum = 3
4360 20:11:53.786351 11, 0x0, sum = 4
4361 20:11:53.789432 best_step = 9
4362 20:11:53.789553
4363 20:11:53.789663 ==
4364 20:11:53.792932 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 20:11:53.796060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 20:11:53.796187 ==
4367 20:11:53.799508 RX Vref Scan: 0
4368 20:11:53.799631
4369 20:11:53.799743 RX Vref 0 -> 0, step: 1
4370 20:11:53.799853
4371 20:11:53.802740 RX Delay -195 -> 252, step: 8
4372 20:11:53.810209 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4373 20:11:53.813557 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4374 20:11:53.816827 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4375 20:11:53.819965 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4376 20:11:53.826572 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4377 20:11:53.830189 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4378 20:11:53.833352 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4379 20:11:53.836778 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4380 20:11:53.840236 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4381 20:11:53.846949 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4382 20:11:53.850733 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4383 20:11:53.853659 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4384 20:11:53.856957 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4385 20:11:53.863169 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4386 20:11:53.866890 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4387 20:11:53.869934 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4388 20:11:53.870016 ==
4389 20:11:53.873412 Dram Type= 6, Freq= 0, CH_0, rank 1
4390 20:11:53.876757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 20:11:53.880104 ==
4392 20:11:53.880186 DQS Delay:
4393 20:11:53.880251 DQS0 = 0, DQS1 = 0
4394 20:11:53.883780 DQM Delay:
4395 20:11:53.883866 DQM0 = 41, DQM1 = 33
4396 20:11:53.883932 DQ Delay:
4397 20:11:53.886669 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4398 20:11:53.890333 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4399 20:11:53.893492 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4400 20:11:53.897073 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =44
4401 20:11:53.897154
4402 20:11:53.897217
4403 20:11:53.906754 [DQSOSCAuto] RK1, (LSB)MR18= 0x4627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4404 20:11:53.910086 CH0 RK1: MR19=808, MR18=4627
4405 20:11:53.916785 CH0_RK1: MR19=0x808, MR18=0x4627, DQSOSC=396, MR23=63, INC=167, DEC=111
4406 20:11:53.916867 [RxdqsGatingPostProcess] freq 600
4407 20:11:53.923173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4408 20:11:53.926381 Pre-setting of DQS Precalculation
4409 20:11:53.930127 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4410 20:11:53.933199 ==
4411 20:11:53.933321 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 20:11:53.939818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 20:11:53.939901 ==
4414 20:11:53.943552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 20:11:53.950102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4416 20:11:53.953598 [CA 0] Center 35 (5~66) winsize 62
4417 20:11:53.957161 [CA 1] Center 35 (5~66) winsize 62
4418 20:11:53.960190 [CA 2] Center 33 (3~64) winsize 62
4419 20:11:53.963639 [CA 3] Center 33 (3~64) winsize 62
4420 20:11:53.967382 [CA 4] Center 34 (3~65) winsize 63
4421 20:11:53.970304 [CA 5] Center 33 (3~64) winsize 62
4422 20:11:53.970433
4423 20:11:53.973537 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4424 20:11:53.973633
4425 20:11:53.976873 [CATrainingPosCal] consider 1 rank data
4426 20:11:53.980043 u2DelayCellTimex100 = 270/100 ps
4427 20:11:53.983658 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 20:11:53.986800 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 20:11:53.993418 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 20:11:53.996537 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 20:11:54.000318 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4432 20:11:54.003869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 20:11:54.003950
4434 20:11:54.006930 CA PerBit enable=1, Macro0, CA PI delay=33
4435 20:11:54.007012
4436 20:11:54.010062 [CBTSetCACLKResult] CA Dly = 33
4437 20:11:54.010142 CS Dly: 4 (0~35)
4438 20:11:54.013383 ==
4439 20:11:54.013463 Dram Type= 6, Freq= 0, CH_1, rank 1
4440 20:11:54.020196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 20:11:54.020277 ==
4442 20:11:54.023454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4443 20:11:54.030077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4444 20:11:54.034069 [CA 0] Center 35 (5~66) winsize 62
4445 20:11:54.037413 [CA 1] Center 35 (5~66) winsize 62
4446 20:11:54.040347 [CA 2] Center 34 (3~65) winsize 63
4447 20:11:54.043427 [CA 3] Center 34 (3~65) winsize 63
4448 20:11:54.047191 [CA 4] Center 34 (3~65) winsize 63
4449 20:11:54.050671 [CA 5] Center 33 (3~64) winsize 62
4450 20:11:54.050794
4451 20:11:54.053691 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4452 20:11:54.053771
4453 20:11:54.056818 [CATrainingPosCal] consider 2 rank data
4454 20:11:54.060170 u2DelayCellTimex100 = 270/100 ps
4455 20:11:54.063841 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 20:11:54.066965 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 20:11:54.073926 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 20:11:54.078006 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 20:11:54.080211 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4460 20:11:54.084191 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 20:11:54.084272
4462 20:11:54.086972 CA PerBit enable=1, Macro0, CA PI delay=33
4463 20:11:54.087053
4464 20:11:54.090835 [CBTSetCACLKResult] CA Dly = 33
4465 20:11:54.090916 CS Dly: 4 (0~36)
4466 20:11:54.090980
4467 20:11:54.093692 ----->DramcWriteLeveling(PI) begin...
4468 20:11:54.097086 ==
4469 20:11:54.100539 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 20:11:54.103869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 20:11:54.103950 ==
4472 20:11:54.107362 Write leveling (Byte 0): 31 => 31
4473 20:11:54.110913 Write leveling (Byte 1): 31 => 31
4474 20:11:54.114174 DramcWriteLeveling(PI) end<-----
4475 20:11:54.114272
4476 20:11:54.114338 ==
4477 20:11:54.117508 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 20:11:54.120387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 20:11:54.120469 ==
4480 20:11:54.123602 [Gating] SW mode calibration
4481 20:11:54.130339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4482 20:11:54.134144 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4483 20:11:54.140954 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 20:11:54.144075 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 20:11:54.147382 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 20:11:54.153893 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4487 20:11:54.156917 0 9 16 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
4488 20:11:54.160472 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4489 20:11:54.167776 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 20:11:54.170478 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 20:11:54.174189 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 20:11:54.180911 0 10 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
4493 20:11:54.183596 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 20:11:54.187476 0 10 12 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4495 20:11:54.193807 0 10 16 | B1->B0 | 3b3b 3e3e | 0 0 | (0 0) (0 0)
4496 20:11:54.196895 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 20:11:54.200398 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 20:11:54.203777 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 20:11:54.210392 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 20:11:54.214027 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 20:11:54.217497 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 20:11:54.223688 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 20:11:54.226913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4504 20:11:54.230808 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 20:11:54.237052 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 20:11:54.240558 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 20:11:54.243844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 20:11:54.250193 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 20:11:54.253910 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 20:11:54.257076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 20:11:54.263706 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 20:11:54.267218 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 20:11:54.270645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 20:11:54.277227 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 20:11:54.280459 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 20:11:54.284101 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 20:11:54.290576 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 20:11:54.293539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4519 20:11:54.297290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 20:11:54.300516 Total UI for P1: 0, mck2ui 16
4521 20:11:54.303916 best dqsien dly found for B0: ( 0, 13, 14)
4522 20:11:54.308188 Total UI for P1: 0, mck2ui 16
4523 20:11:54.310928 best dqsien dly found for B1: ( 0, 13, 12)
4524 20:11:54.314343 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4525 20:11:54.317708 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4526 20:11:54.317790
4527 20:11:54.321060 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4528 20:11:54.324272 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4529 20:11:54.327767 [Gating] SW calibration Done
4530 20:11:54.327864 ==
4531 20:11:54.331225 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 20:11:54.334333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 20:11:54.337876 ==
4534 20:11:54.337949 RX Vref Scan: 0
4535 20:11:54.338011
4536 20:11:54.340640 RX Vref 0 -> 0, step: 1
4537 20:11:54.340720
4538 20:11:54.344044 RX Delay -230 -> 252, step: 16
4539 20:11:54.347529 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4540 20:11:54.351190 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4541 20:11:54.354157 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4542 20:11:54.360897 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4543 20:11:54.364076 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4544 20:11:54.367856 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4545 20:11:54.371307 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4546 20:11:54.374614 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4547 20:11:54.380958 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4548 20:11:54.384208 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4549 20:11:54.387441 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4550 20:11:54.390856 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4551 20:11:54.397435 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4552 20:11:54.400940 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4553 20:11:54.404328 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4554 20:11:54.407693 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4555 20:11:54.407775 ==
4556 20:11:54.410795 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 20:11:54.417417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 20:11:54.417493 ==
4559 20:11:54.417555 DQS Delay:
4560 20:11:54.420862 DQS0 = 0, DQS1 = 0
4561 20:11:54.420977 DQM Delay:
4562 20:11:54.421080 DQM0 = 45, DQM1 = 36
4563 20:11:54.423836 DQ Delay:
4564 20:11:54.427179 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4565 20:11:54.430342 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4566 20:11:54.433882 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4567 20:11:54.437443 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4568 20:11:54.437513
4569 20:11:54.437572
4570 20:11:54.437629 ==
4571 20:11:54.440487 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 20:11:54.444167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 20:11:54.444279 ==
4574 20:11:54.444371
4575 20:11:54.444458
4576 20:11:54.447162 TX Vref Scan disable
4577 20:11:54.447261 == TX Byte 0 ==
4578 20:11:54.453890 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4579 20:11:54.457003 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4580 20:11:54.460185 == TX Byte 1 ==
4581 20:11:54.464360 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4582 20:11:54.468129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4583 20:11:54.468211 ==
4584 20:11:54.470743 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 20:11:54.473847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 20:11:54.473928 ==
4587 20:11:54.473992
4588 20:11:54.477210
4589 20:11:54.477290 TX Vref Scan disable
4590 20:11:54.480478 == TX Byte 0 ==
4591 20:11:54.483715 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4592 20:11:54.487044 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4593 20:11:54.491061 == TX Byte 1 ==
4594 20:11:54.494212 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4595 20:11:54.497345 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4596 20:11:54.500681
4597 20:11:54.500762 [DATLAT]
4598 20:11:54.500825 Freq=600, CH1 RK0
4599 20:11:54.500886
4600 20:11:54.503875 DATLAT Default: 0x9
4601 20:11:54.503975 0, 0xFFFF, sum = 0
4602 20:11:54.507105 1, 0xFFFF, sum = 0
4603 20:11:54.507187 2, 0xFFFF, sum = 0
4604 20:11:54.510780 3, 0xFFFF, sum = 0
4605 20:11:54.510863 4, 0xFFFF, sum = 0
4606 20:11:54.513721 5, 0xFFFF, sum = 0
4607 20:11:54.517061 6, 0xFFFF, sum = 0
4608 20:11:54.517143 7, 0xFFFF, sum = 0
4609 20:11:54.517222 8, 0x0, sum = 1
4610 20:11:54.520436 9, 0x0, sum = 2
4611 20:11:54.520519 10, 0x0, sum = 3
4612 20:11:54.523955 11, 0x0, sum = 4
4613 20:11:54.524037 best_step = 9
4614 20:11:54.524102
4615 20:11:54.524160 ==
4616 20:11:54.527142 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 20:11:54.534616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 20:11:54.534698 ==
4619 20:11:54.534800 RX Vref Scan: 1
4620 20:11:54.534891
4621 20:11:54.537326 RX Vref 0 -> 0, step: 1
4622 20:11:54.537409
4623 20:11:54.540373 RX Delay -179 -> 252, step: 8
4624 20:11:54.540453
4625 20:11:54.544185 Set Vref, RX VrefLevel [Byte0]: 56
4626 20:11:54.547770 [Byte1]: 51
4627 20:11:54.547852
4628 20:11:54.550605 Final RX Vref Byte 0 = 56 to rank0
4629 20:11:54.553777 Final RX Vref Byte 1 = 51 to rank0
4630 20:11:54.557390 Final RX Vref Byte 0 = 56 to rank1
4631 20:11:54.560900 Final RX Vref Byte 1 = 51 to rank1==
4632 20:11:54.563848 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 20:11:54.567531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 20:11:54.567629 ==
4635 20:11:54.570329 DQS Delay:
4636 20:11:54.570435 DQS0 = 0, DQS1 = 0
4637 20:11:54.570542 DQM Delay:
4638 20:11:54.573832 DQM0 = 41, DQM1 = 32
4639 20:11:54.573913 DQ Delay:
4640 20:11:54.577334 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4641 20:11:54.581078 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4642 20:11:54.584905 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4643 20:11:54.587388 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4644 20:11:54.587470
4645 20:11:54.587572
4646 20:11:54.597286 [DQSOSCAuto] RK0, (LSB)MR18= 0x4006, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4647 20:11:54.597370 CH1 RK0: MR19=808, MR18=4006
4648 20:11:54.603891 CH1_RK0: MR19=0x808, MR18=0x4006, DQSOSC=397, MR23=63, INC=166, DEC=110
4649 20:11:54.603977
4650 20:11:54.607531 ----->DramcWriteLeveling(PI) begin...
4651 20:11:54.607614 ==
4652 20:11:54.610911 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 20:11:54.617030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 20:11:54.617112 ==
4655 20:11:54.621176 Write leveling (Byte 0): 30 => 30
4656 20:11:54.623864 Write leveling (Byte 1): 31 => 31
4657 20:11:54.623969 DramcWriteLeveling(PI) end<-----
4658 20:11:54.627347
4659 20:11:54.627444 ==
4660 20:11:54.630544 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 20:11:54.634265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 20:11:54.634349 ==
4663 20:11:54.637382 [Gating] SW mode calibration
4664 20:11:54.643861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4665 20:11:54.647159 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4666 20:11:54.654914 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 20:11:54.657528 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 20:11:54.660816 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4669 20:11:54.667633 0 9 12 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (0 0)
4670 20:11:54.670650 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4671 20:11:54.674301 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 20:11:54.680894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 20:11:54.684976 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4674 20:11:54.687210 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4675 20:11:54.690954 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 20:11:54.697166 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4677 20:11:54.701468 0 10 12 | B1->B0 | 2e2e 4242 | 0 0 | (0 0) (0 0)
4678 20:11:54.703855 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4679 20:11:54.710801 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 20:11:54.713980 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 20:11:54.717288 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 20:11:54.724041 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 20:11:54.727928 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 20:11:54.731354 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 20:11:54.737687 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4686 20:11:54.741224 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 20:11:54.743973 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 20:11:54.750926 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 20:11:54.754568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 20:11:54.757494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 20:11:54.764058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 20:11:54.767461 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 20:11:54.771280 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 20:11:54.774193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 20:11:54.780786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 20:11:54.784222 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 20:11:54.787449 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 20:11:54.794234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 20:11:54.797790 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 20:11:54.801195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4701 20:11:54.808285 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4702 20:11:54.808406 Total UI for P1: 0, mck2ui 16
4703 20:11:54.814643 best dqsien dly found for B0: ( 0, 13, 8)
4704 20:11:54.817469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 20:11:54.821783 Total UI for P1: 0, mck2ui 16
4706 20:11:54.824158 best dqsien dly found for B1: ( 0, 13, 10)
4707 20:11:54.828326 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4708 20:11:54.830875 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4709 20:11:54.831079
4710 20:11:54.834430 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4711 20:11:54.837411 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4712 20:11:54.841075 [Gating] SW calibration Done
4713 20:11:54.841171 ==
4714 20:11:54.844572 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 20:11:54.847314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 20:11:54.850988 ==
4717 20:11:54.851070 RX Vref Scan: 0
4718 20:11:54.851133
4719 20:11:54.854616 RX Vref 0 -> 0, step: 1
4720 20:11:54.854697
4721 20:11:54.858063 RX Delay -230 -> 252, step: 16
4722 20:11:54.861316 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4723 20:11:54.864080 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4724 20:11:54.867838 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4725 20:11:54.871413 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4726 20:11:54.877874 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4727 20:11:54.881607 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4728 20:11:54.884632 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4729 20:11:54.887352 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4730 20:11:54.894404 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4731 20:11:54.898200 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4732 20:11:54.901646 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4733 20:11:54.904670 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4734 20:11:54.907899 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4735 20:11:54.914298 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4736 20:11:54.918352 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4737 20:11:54.921747 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4738 20:11:54.921846 ==
4739 20:11:54.924406 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 20:11:54.928157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 20:11:54.931654 ==
4742 20:11:54.931753 DQS Delay:
4743 20:11:54.931849 DQS0 = 0, DQS1 = 0
4744 20:11:54.934721 DQM Delay:
4745 20:11:54.934813 DQM0 = 43, DQM1 = 40
4746 20:11:54.934880 DQ Delay:
4747 20:11:54.937871 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4748 20:11:54.941157 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4749 20:11:54.944815 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4750 20:11:54.948039 DQ12 =41, DQ13 =57, DQ14 =49, DQ15 =49
4751 20:11:54.948116
4752 20:11:54.948184
4753 20:11:54.950942 ==
4754 20:11:54.954777 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 20:11:54.958194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 20:11:54.958299 ==
4757 20:11:54.958391
4758 20:11:54.958469
4759 20:11:54.961343 TX Vref Scan disable
4760 20:11:54.961445 == TX Byte 0 ==
4761 20:11:54.964931 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4762 20:11:54.971454 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4763 20:11:54.971536 == TX Byte 1 ==
4764 20:11:54.977832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4765 20:11:54.981240 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4766 20:11:54.981339 ==
4767 20:11:54.984852 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 20:11:54.988125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 20:11:54.988223 ==
4770 20:11:54.988316
4771 20:11:54.988407
4772 20:11:54.991219 TX Vref Scan disable
4773 20:11:54.994766 == TX Byte 0 ==
4774 20:11:54.997778 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 20:11:55.001348 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 20:11:55.004664 == TX Byte 1 ==
4777 20:11:55.007912 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4778 20:11:55.011449 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4779 20:11:55.011550
4780 20:11:55.014723 [DATLAT]
4781 20:11:55.014845 Freq=600, CH1 RK1
4782 20:11:55.014954
4783 20:11:55.018270 DATLAT Default: 0x9
4784 20:11:55.018370 0, 0xFFFF, sum = 0
4785 20:11:55.021844 1, 0xFFFF, sum = 0
4786 20:11:55.021942 2, 0xFFFF, sum = 0
4787 20:11:55.024481 3, 0xFFFF, sum = 0
4788 20:11:55.024559 4, 0xFFFF, sum = 0
4789 20:11:55.027995 5, 0xFFFF, sum = 0
4790 20:11:55.028098 6, 0xFFFF, sum = 0
4791 20:11:55.031745 7, 0xFFFF, sum = 0
4792 20:11:55.031852 8, 0x0, sum = 1
4793 20:11:55.034618 9, 0x0, sum = 2
4794 20:11:55.034716 10, 0x0, sum = 3
4795 20:11:55.037638 11, 0x0, sum = 4
4796 20:11:55.037755 best_step = 9
4797 20:11:55.037878
4798 20:11:55.037966 ==
4799 20:11:55.041293 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 20:11:55.044766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 20:11:55.044884 ==
4802 20:11:55.048239 RX Vref Scan: 0
4803 20:11:55.048325
4804 20:11:55.051236 RX Vref 0 -> 0, step: 1
4805 20:11:55.051360
4806 20:11:55.051513 RX Delay -179 -> 252, step: 8
4807 20:11:55.059095 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4808 20:11:55.062651 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4809 20:11:55.066282 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4810 20:11:55.069059 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4811 20:11:55.075598 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4812 20:11:55.078959 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4813 20:11:55.082301 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4814 20:11:55.085571 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4815 20:11:55.089436 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4816 20:11:55.096303 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4817 20:11:55.098980 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4818 20:11:55.102385 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4819 20:11:55.106024 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4820 20:11:55.112230 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4821 20:11:55.115852 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4822 20:11:55.119059 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4823 20:11:55.119161 ==
4824 20:11:55.122594 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 20:11:55.125938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 20:11:55.126016 ==
4827 20:11:55.129284 DQS Delay:
4828 20:11:55.129380 DQS0 = 0, DQS1 = 0
4829 20:11:55.133045 DQM Delay:
4830 20:11:55.133142 DQM0 = 39, DQM1 = 34
4831 20:11:55.133235 DQ Delay:
4832 20:11:55.135463 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4833 20:11:55.139250 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4834 20:11:55.142991 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4835 20:11:55.145984 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4836 20:11:55.146087
4837 20:11:55.148997
4838 20:11:55.155736 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4839 20:11:55.158782 CH1 RK1: MR19=808, MR18=3C4A
4840 20:11:55.165874 CH1_RK1: MR19=0x808, MR18=0x3C4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4841 20:11:55.165979 [RxdqsGatingPostProcess] freq 600
4842 20:11:55.172412 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4843 20:11:55.175965 Pre-setting of DQS Precalculation
4844 20:11:55.178928 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4845 20:11:55.188830 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4846 20:11:55.195690 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4847 20:11:55.195798
4848 20:11:55.195905
4849 20:11:55.199352 [Calibration Summary] 1200 Mbps
4850 20:11:55.199452 CH 0, Rank 0
4851 20:11:55.202431 SW Impedance : PASS
4852 20:11:55.202519 DUTY Scan : NO K
4853 20:11:55.205612 ZQ Calibration : PASS
4854 20:11:55.209280 Jitter Meter : NO K
4855 20:11:55.209382 CBT Training : PASS
4856 20:11:55.212223 Write leveling : PASS
4857 20:11:55.216143 RX DQS gating : PASS
4858 20:11:55.216244 RX DQ/DQS(RDDQC) : PASS
4859 20:11:55.219206 TX DQ/DQS : PASS
4860 20:11:55.222455 RX DATLAT : PASS
4861 20:11:55.222558 RX DQ/DQS(Engine): PASS
4862 20:11:55.225606 TX OE : NO K
4863 20:11:55.225703 All Pass.
4864 20:11:55.225794
4865 20:11:55.229230 CH 0, Rank 1
4866 20:11:55.229328 SW Impedance : PASS
4867 20:11:55.232597 DUTY Scan : NO K
4868 20:11:55.232692 ZQ Calibration : PASS
4869 20:11:55.235598 Jitter Meter : NO K
4870 20:11:55.238745 CBT Training : PASS
4871 20:11:55.238841 Write leveling : PASS
4872 20:11:55.242075 RX DQS gating : PASS
4873 20:11:55.245686 RX DQ/DQS(RDDQC) : PASS
4874 20:11:55.245785 TX DQ/DQS : PASS
4875 20:11:55.249306 RX DATLAT : PASS
4876 20:11:55.252625 RX DQ/DQS(Engine): PASS
4877 20:11:55.252727 TX OE : NO K
4878 20:11:55.255851 All Pass.
4879 20:11:55.255950
4880 20:11:55.256040 CH 1, Rank 0
4881 20:11:55.259272 SW Impedance : PASS
4882 20:11:55.259371 DUTY Scan : NO K
4883 20:11:55.262381 ZQ Calibration : PASS
4884 20:11:55.265771 Jitter Meter : NO K
4885 20:11:55.265872 CBT Training : PASS
4886 20:11:55.269080 Write leveling : PASS
4887 20:11:55.272455 RX DQS gating : PASS
4888 20:11:55.272552 RX DQ/DQS(RDDQC) : PASS
4889 20:11:55.275614 TX DQ/DQS : PASS
4890 20:11:55.275686 RX DATLAT : PASS
4891 20:11:55.279154 RX DQ/DQS(Engine): PASS
4892 20:11:55.282101 TX OE : NO K
4893 20:11:55.282197 All Pass.
4894 20:11:55.282285
4895 20:11:55.282386 CH 1, Rank 1
4896 20:11:55.285555 SW Impedance : PASS
4897 20:11:55.289181 DUTY Scan : NO K
4898 20:11:55.289281 ZQ Calibration : PASS
4899 20:11:55.292305 Jitter Meter : NO K
4900 20:11:55.295612 CBT Training : PASS
4901 20:11:55.295711 Write leveling : PASS
4902 20:11:55.299069 RX DQS gating : PASS
4903 20:11:55.303261 RX DQ/DQS(RDDQC) : PASS
4904 20:11:55.303343 TX DQ/DQS : PASS
4905 20:11:55.305975 RX DATLAT : PASS
4906 20:11:55.309370 RX DQ/DQS(Engine): PASS
4907 20:11:55.309471 TX OE : NO K
4908 20:11:55.309553 All Pass.
4909 20:11:55.312274
4910 20:11:55.312379 DramC Write-DBI off
4911 20:11:55.316188 PER_BANK_REFRESH: Hybrid Mode
4912 20:11:55.316259 TX_TRACKING: ON
4913 20:11:55.325764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4914 20:11:55.329361 [FAST_K] Save calibration result to emmc
4915 20:11:55.332383 dramc_set_vcore_voltage set vcore to 662500
4916 20:11:55.335890 Read voltage for 933, 3
4917 20:11:55.335988 Vio18 = 0
4918 20:11:55.338854 Vcore = 662500
4919 20:11:55.338966 Vdram = 0
4920 20:11:55.339087 Vddq = 0
4921 20:11:55.339208 Vmddr = 0
4922 20:11:55.345554 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4923 20:11:55.349041 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4924 20:11:55.352720 MEM_TYPE=3, freq_sel=17
4925 20:11:55.355836 sv_algorithm_assistance_LP4_1600
4926 20:11:55.359089 ============ PULL DRAM RESETB DOWN ============
4927 20:11:55.366067 ========== PULL DRAM RESETB DOWN end =========
4928 20:11:55.369355 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4929 20:11:55.372691 ===================================
4930 20:11:55.376184 LPDDR4 DRAM CONFIGURATION
4931 20:11:55.379566 ===================================
4932 20:11:55.379648 EX_ROW_EN[0] = 0x0
4933 20:11:55.382566 EX_ROW_EN[1] = 0x0
4934 20:11:55.382647 LP4Y_EN = 0x0
4935 20:11:55.385676 WORK_FSP = 0x0
4936 20:11:55.385757 WL = 0x3
4937 20:11:55.389256 RL = 0x3
4938 20:11:55.389362 BL = 0x2
4939 20:11:55.392380 RPST = 0x0
4940 20:11:55.392461 RD_PRE = 0x0
4941 20:11:55.395572 WR_PRE = 0x1
4942 20:11:55.395653 WR_PST = 0x0
4943 20:11:55.399053 DBI_WR = 0x0
4944 20:11:55.399134 DBI_RD = 0x0
4945 20:11:55.402550 OTF = 0x1
4946 20:11:55.406016 ===================================
4947 20:11:55.409034 ===================================
4948 20:11:55.409116 ANA top config
4949 20:11:55.412468 ===================================
4950 20:11:55.415897 DLL_ASYNC_EN = 0
4951 20:11:55.418964 ALL_SLAVE_EN = 1
4952 20:11:55.422604 NEW_RANK_MODE = 1
4953 20:11:55.422713 DLL_IDLE_MODE = 1
4954 20:11:55.426075 LP45_APHY_COMB_EN = 1
4955 20:11:55.429501 TX_ODT_DIS = 1
4956 20:11:55.432947 NEW_8X_MODE = 1
4957 20:11:55.435826 ===================================
4958 20:11:55.439725 ===================================
4959 20:11:55.443463 data_rate = 1866
4960 20:11:55.443545 CKR = 1
4961 20:11:55.445805 DQ_P2S_RATIO = 8
4962 20:11:55.449691 ===================================
4963 20:11:55.452895 CA_P2S_RATIO = 8
4964 20:11:55.455927 DQ_CA_OPEN = 0
4965 20:11:55.459544 DQ_SEMI_OPEN = 0
4966 20:11:55.462837 CA_SEMI_OPEN = 0
4967 20:11:55.462923 CA_FULL_RATE = 0
4968 20:11:55.465855 DQ_CKDIV4_EN = 1
4969 20:11:55.470336 CA_CKDIV4_EN = 1
4970 20:11:55.473013 CA_PREDIV_EN = 0
4971 20:11:55.476189 PH8_DLY = 0
4972 20:11:55.479026 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4973 20:11:55.479155 DQ_AAMCK_DIV = 4
4974 20:11:55.482770 CA_AAMCK_DIV = 4
4975 20:11:55.486078 CA_ADMCK_DIV = 4
4976 20:11:55.489532 DQ_TRACK_CA_EN = 0
4977 20:11:55.492493 CA_PICK = 933
4978 20:11:55.496186 CA_MCKIO = 933
4979 20:11:55.496301 MCKIO_SEMI = 0
4980 20:11:55.499100 PLL_FREQ = 3732
4981 20:11:55.502602 DQ_UI_PI_RATIO = 32
4982 20:11:55.506214 CA_UI_PI_RATIO = 0
4983 20:11:55.509870 ===================================
4984 20:11:55.512598 ===================================
4985 20:11:55.516352 memory_type:LPDDR4
4986 20:11:55.516483 GP_NUM : 10
4987 20:11:55.519292 SRAM_EN : 1
4988 20:11:55.519406 MD32_EN : 0
4989 20:11:55.523132 ===================================
4990 20:11:55.526561 [ANA_INIT] >>>>>>>>>>>>>>
4991 20:11:55.530066 <<<<<< [CONFIGURE PHASE]: ANA_TX
4992 20:11:55.532869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4993 20:11:55.535975 ===================================
4994 20:11:55.539265 data_rate = 1866,PCW = 0X8f00
4995 20:11:55.542657 ===================================
4996 20:11:55.546138 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4997 20:11:55.552836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 20:11:55.556313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 20:11:55.562626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5000 20:11:55.566547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5001 20:11:55.569687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5002 20:11:55.569785 [ANA_INIT] flow start
5003 20:11:55.572976 [ANA_INIT] PLL >>>>>>>>
5004 20:11:55.576225 [ANA_INIT] PLL <<<<<<<<
5005 20:11:55.576306 [ANA_INIT] MIDPI >>>>>>>>
5006 20:11:55.580166 [ANA_INIT] MIDPI <<<<<<<<
5007 20:11:55.583049 [ANA_INIT] DLL >>>>>>>>
5008 20:11:55.583162 [ANA_INIT] flow end
5009 20:11:55.585909 ============ LP4 DIFF to SE enter ============
5010 20:11:55.593009 ============ LP4 DIFF to SE exit ============
5011 20:11:55.593121 [ANA_INIT] <<<<<<<<<<<<<
5012 20:11:55.596456 [Flow] Enable top DCM control >>>>>
5013 20:11:55.599618 [Flow] Enable top DCM control <<<<<
5014 20:11:55.603704 Enable DLL master slave shuffle
5015 20:11:55.609943 ==============================================================
5016 20:11:55.610026 Gating Mode config
5017 20:11:55.616804 ==============================================================
5018 20:11:55.619874 Config description:
5019 20:11:55.629851 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5020 20:11:55.636041 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5021 20:11:55.639440 SELPH_MODE 0: By rank 1: By Phase
5022 20:11:55.646101 ==============================================================
5023 20:11:55.649662 GAT_TRACK_EN = 1
5024 20:11:55.649744 RX_GATING_MODE = 2
5025 20:11:55.653045 RX_GATING_TRACK_MODE = 2
5026 20:11:55.655992 SELPH_MODE = 1
5027 20:11:55.659618 PICG_EARLY_EN = 1
5028 20:11:55.662949 VALID_LAT_VALUE = 1
5029 20:11:55.670111 ==============================================================
5030 20:11:55.673064 Enter into Gating configuration >>>>
5031 20:11:55.676120 Exit from Gating configuration <<<<
5032 20:11:55.679757 Enter into DVFS_PRE_config >>>>>
5033 20:11:55.689273 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5034 20:11:55.693068 Exit from DVFS_PRE_config <<<<<
5035 20:11:55.696174 Enter into PICG configuration >>>>
5036 20:11:55.699711 Exit from PICG configuration <<<<
5037 20:11:55.702991 [RX_INPUT] configuration >>>>>
5038 20:11:55.703139 [RX_INPUT] configuration <<<<<
5039 20:11:55.709502 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5040 20:11:55.716451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5041 20:11:55.719589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 20:11:55.726319 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 20:11:55.733152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 20:11:55.739571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 20:11:55.743041 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5046 20:11:55.746297 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5047 20:11:55.753605 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5048 20:11:55.756426 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5049 20:11:55.759701 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5050 20:11:55.766719 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 20:11:55.770127 ===================================
5052 20:11:55.770270 LPDDR4 DRAM CONFIGURATION
5053 20:11:55.773142 ===================================
5054 20:11:55.776781 EX_ROW_EN[0] = 0x0
5055 20:11:55.776862 EX_ROW_EN[1] = 0x0
5056 20:11:55.779515 LP4Y_EN = 0x0
5057 20:11:55.779597 WORK_FSP = 0x0
5058 20:11:55.783244 WL = 0x3
5059 20:11:55.783325 RL = 0x3
5060 20:11:55.786353 BL = 0x2
5061 20:11:55.786457 RPST = 0x0
5062 20:11:55.789955 RD_PRE = 0x0
5063 20:11:55.792990 WR_PRE = 0x1
5064 20:11:55.793071 WR_PST = 0x0
5065 20:11:55.796381 DBI_WR = 0x0
5066 20:11:55.796463 DBI_RD = 0x0
5067 20:11:55.799685 OTF = 0x1
5068 20:11:55.803070 ===================================
5069 20:11:55.806205 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5070 20:11:55.809480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5071 20:11:55.813226 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 20:11:55.816380 ===================================
5073 20:11:55.819839 LPDDR4 DRAM CONFIGURATION
5074 20:11:55.823081 ===================================
5075 20:11:55.826914 EX_ROW_EN[0] = 0x10
5076 20:11:55.826994 EX_ROW_EN[1] = 0x0
5077 20:11:55.829845 LP4Y_EN = 0x0
5078 20:11:55.829925 WORK_FSP = 0x0
5079 20:11:55.833168 WL = 0x3
5080 20:11:55.833249 RL = 0x3
5081 20:11:55.836417 BL = 0x2
5082 20:11:55.836498 RPST = 0x0
5083 20:11:55.840059 RD_PRE = 0x0
5084 20:11:55.840140 WR_PRE = 0x1
5085 20:11:55.843494 WR_PST = 0x0
5086 20:11:55.843595 DBI_WR = 0x0
5087 20:11:55.846966 DBI_RD = 0x0
5088 20:11:55.847079 OTF = 0x1
5089 20:11:55.849939 ===================================
5090 20:11:55.856464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5091 20:11:55.861777 nWR fixed to 30
5092 20:11:55.864490 [ModeRegInit_LP4] CH0 RK0
5093 20:11:55.864570 [ModeRegInit_LP4] CH0 RK1
5094 20:11:55.867795 [ModeRegInit_LP4] CH1 RK0
5095 20:11:55.871613 [ModeRegInit_LP4] CH1 RK1
5096 20:11:55.871695 match AC timing 9
5097 20:11:55.878923 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5098 20:11:55.881430 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5099 20:11:55.884467 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5100 20:11:55.891034 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5101 20:11:55.894530 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5102 20:11:55.894633 ==
5103 20:11:55.898031 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 20:11:55.901094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 20:11:55.901226 ==
5106 20:11:55.907690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 20:11:55.914439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5108 20:11:55.918437 [CA 0] Center 38 (8~69) winsize 62
5109 20:11:55.921301 [CA 1] Center 37 (7~68) winsize 62
5110 20:11:55.924599 [CA 2] Center 35 (5~66) winsize 62
5111 20:11:55.928202 [CA 3] Center 35 (5~65) winsize 61
5112 20:11:55.931242 [CA 4] Center 34 (4~64) winsize 61
5113 20:11:55.934649 [CA 5] Center 34 (4~64) winsize 61
5114 20:11:55.934789
5115 20:11:55.938150 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5116 20:11:55.938293
5117 20:11:55.941751 [CATrainingPosCal] consider 1 rank data
5118 20:11:55.944533 u2DelayCellTimex100 = 270/100 ps
5119 20:11:55.947804 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5120 20:11:55.951409 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5121 20:11:55.954434 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5122 20:11:55.957893 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5123 20:11:55.961440 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5124 20:11:55.965656 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5125 20:11:55.965757
5126 20:11:55.968333 CA PerBit enable=1, Macro0, CA PI delay=34
5127 20:11:55.968417
5128 20:11:55.971706 [CBTSetCACLKResult] CA Dly = 34
5129 20:11:55.975070 CS Dly: 6 (0~37)
5130 20:11:55.975167 ==
5131 20:11:55.978141 Dram Type= 6, Freq= 0, CH_0, rank 1
5132 20:11:55.981571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 20:11:55.981673 ==
5134 20:11:55.988570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 20:11:55.994737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5136 20:11:55.998288 [CA 0] Center 38 (7~69) winsize 63
5137 20:11:56.001409 [CA 1] Center 38 (7~69) winsize 63
5138 20:11:56.005045 [CA 2] Center 35 (5~66) winsize 62
5139 20:11:56.008480 [CA 3] Center 35 (4~66) winsize 63
5140 20:11:56.011715 [CA 4] Center 34 (4~64) winsize 61
5141 20:11:56.011827 [CA 5] Center 33 (3~64) winsize 62
5142 20:11:56.014723
5143 20:11:56.018558 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5144 20:11:56.018676
5145 20:11:56.021849 [CATrainingPosCal] consider 2 rank data
5146 20:11:56.025195 u2DelayCellTimex100 = 270/100 ps
5147 20:11:56.028625 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5148 20:11:56.031866 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5149 20:11:56.034711 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5150 20:11:56.038570 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5151 20:11:56.041658 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 20:11:56.045461 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5153 20:11:56.045577
5154 20:11:56.048410 CA PerBit enable=1, Macro0, CA PI delay=34
5155 20:11:56.048517
5156 20:11:56.051450 [CBTSetCACLKResult] CA Dly = 34
5157 20:11:56.054516 CS Dly: 7 (0~39)
5158 20:11:56.054603
5159 20:11:56.058061 ----->DramcWriteLeveling(PI) begin...
5160 20:11:56.058148 ==
5161 20:11:56.061735 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 20:11:56.065141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 20:11:56.065227 ==
5164 20:11:56.068039 Write leveling (Byte 0): 33 => 33
5165 20:11:56.071734 Write leveling (Byte 1): 27 => 27
5166 20:11:56.074826 DramcWriteLeveling(PI) end<-----
5167 20:11:56.074920
5168 20:11:56.075008 ==
5169 20:11:56.077811 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 20:11:56.081212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 20:11:56.081302 ==
5172 20:11:56.084490 [Gating] SW mode calibration
5173 20:11:56.091602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5174 20:11:56.098195 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5175 20:11:56.101664 0 14 0 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5176 20:11:56.108026 0 14 4 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
5177 20:11:56.111499 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 20:11:56.114861 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 20:11:56.118308 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 20:11:56.124824 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 20:11:56.128534 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 20:11:56.131610 0 14 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5183 20:11:56.137930 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5184 20:11:56.141383 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5185 20:11:56.144836 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 20:11:56.151208 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 20:11:56.154489 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 20:11:56.157826 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 20:11:56.164596 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 20:11:56.168256 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5191 20:11:56.171329 1 0 0 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (1 1)
5192 20:11:56.178168 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5193 20:11:56.181398 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 20:11:56.184614 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 20:11:56.191594 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 20:11:56.194798 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 20:11:56.198381 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 20:11:56.204706 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5199 20:11:56.208023 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5200 20:11:56.212119 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5201 20:11:56.218560 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 20:11:56.221211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 20:11:56.224700 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 20:11:56.227861 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 20:11:56.235200 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 20:11:56.238352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 20:11:56.241573 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 20:11:56.248767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 20:11:56.251691 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 20:11:56.254516 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 20:11:56.261569 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 20:11:56.264490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 20:11:56.268085 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 20:11:56.274969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5215 20:11:56.278169 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 20:11:56.281055 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5217 20:11:56.288052 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 20:11:56.288137 Total UI for P1: 0, mck2ui 16
5219 20:11:56.294451 best dqsien dly found for B0: ( 1, 3, 4)
5220 20:11:56.294536 Total UI for P1: 0, mck2ui 16
5221 20:11:56.301197 best dqsien dly found for B1: ( 1, 3, 4)
5222 20:11:56.304696 best DQS0 dly(MCK, UI, PI) = (1, 3, 4)
5223 20:11:56.307948 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5224 20:11:56.308033
5225 20:11:56.311711 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 4)
5226 20:11:56.314569 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5227 20:11:56.317757 [Gating] SW calibration Done
5228 20:11:56.317841 ==
5229 20:11:56.321630 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 20:11:56.324748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 20:11:56.324833 ==
5232 20:11:56.324900 RX Vref Scan: 0
5233 20:11:56.324962
5234 20:11:56.327867 RX Vref 0 -> 0, step: 1
5235 20:11:56.327953
5236 20:11:56.331349 RX Delay -80 -> 252, step: 8
5237 20:11:56.335321 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5238 20:11:56.338056 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5239 20:11:56.342019 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5240 20:11:56.347924 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5241 20:11:56.351652 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5242 20:11:56.354733 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5243 20:11:56.358317 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5244 20:11:56.361375 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5245 20:11:56.364791 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5246 20:11:56.371490 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5247 20:11:56.374839 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5248 20:11:56.378210 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5249 20:11:56.381590 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5250 20:11:56.384795 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5251 20:11:56.391270 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5252 20:11:56.394453 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5253 20:11:56.394579 ==
5254 20:11:56.398061 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 20:11:56.401453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 20:11:56.401583 ==
5257 20:11:56.401700 DQS Delay:
5258 20:11:56.404605 DQS0 = 0, DQS1 = 0
5259 20:11:56.404727 DQM Delay:
5260 20:11:56.407876 DQM0 = 98, DQM1 = 87
5261 20:11:56.408001 DQ Delay:
5262 20:11:56.411603 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5263 20:11:56.414952 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5264 20:11:56.417787 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5265 20:11:56.421141 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5266 20:11:56.421266
5267 20:11:56.421382
5268 20:11:56.421494 ==
5269 20:11:56.424983 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 20:11:56.428151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 20:11:56.431273 ==
5272 20:11:56.431399
5273 20:11:56.431513
5274 20:11:56.431622 TX Vref Scan disable
5275 20:11:56.434802 == TX Byte 0 ==
5276 20:11:56.437856 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5277 20:11:56.441220 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5278 20:11:56.445171 == TX Byte 1 ==
5279 20:11:56.447997 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5280 20:11:56.451379 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5281 20:11:56.451504 ==
5282 20:11:56.455066 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 20:11:56.461285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 20:11:56.461369 ==
5285 20:11:56.461434
5286 20:11:56.461502
5287 20:11:56.464724 TX Vref Scan disable
5288 20:11:56.464804 == TX Byte 0 ==
5289 20:11:56.471302 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5290 20:11:56.474638 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5291 20:11:56.474722 == TX Byte 1 ==
5292 20:11:56.481407 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5293 20:11:56.484869 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5294 20:11:56.484946
5295 20:11:56.485010 [DATLAT]
5296 20:11:56.488230 Freq=933, CH0 RK0
5297 20:11:56.488343
5298 20:11:56.488439 DATLAT Default: 0xd
5299 20:11:56.491117 0, 0xFFFF, sum = 0
5300 20:11:56.491194 1, 0xFFFF, sum = 0
5301 20:11:56.495281 2, 0xFFFF, sum = 0
5302 20:11:56.495378 3, 0xFFFF, sum = 0
5303 20:11:56.498244 4, 0xFFFF, sum = 0
5304 20:11:56.498366 5, 0xFFFF, sum = 0
5305 20:11:56.501835 6, 0xFFFF, sum = 0
5306 20:11:56.501917 7, 0xFFFF, sum = 0
5307 20:11:56.504585 8, 0xFFFF, sum = 0
5308 20:11:56.504667 9, 0xFFFF, sum = 0
5309 20:11:56.508692 10, 0x0, sum = 1
5310 20:11:56.508798 11, 0x0, sum = 2
5311 20:11:56.511835 12, 0x0, sum = 3
5312 20:11:56.511947 13, 0x0, sum = 4
5313 20:11:56.514999 best_step = 11
5314 20:11:56.515112
5315 20:11:56.515180 ==
5316 20:11:56.518469 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 20:11:56.521438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 20:11:56.521539 ==
5319 20:11:56.524614 RX Vref Scan: 1
5320 20:11:56.524693
5321 20:11:56.524758 RX Vref 0 -> 0, step: 1
5322 20:11:56.524818
5323 20:11:56.528338 RX Delay -61 -> 252, step: 4
5324 20:11:56.528416
5325 20:11:56.531247 Set Vref, RX VrefLevel [Byte0]: 54
5326 20:11:56.535039 [Byte1]: 52
5327 20:11:56.538198
5328 20:11:56.538334 Final RX Vref Byte 0 = 54 to rank0
5329 20:11:56.541479 Final RX Vref Byte 1 = 52 to rank0
5330 20:11:56.545286 Final RX Vref Byte 0 = 54 to rank1
5331 20:11:56.548761 Final RX Vref Byte 1 = 52 to rank1==
5332 20:11:56.552063 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 20:11:56.558639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 20:11:56.558732 ==
5335 20:11:56.558796 DQS Delay:
5336 20:11:56.558855 DQS0 = 0, DQS1 = 0
5337 20:11:56.562350 DQM Delay:
5338 20:11:56.562475 DQM0 = 97, DQM1 = 88
5339 20:11:56.565108 DQ Delay:
5340 20:11:56.568504 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5341 20:11:56.571791 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5342 20:11:56.575005 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =82
5343 20:11:56.578581 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5344 20:11:56.578663
5345 20:11:56.578726
5346 20:11:56.585187 [DQSOSCAuto] RK0, (LSB)MR18= 0x1802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5347 20:11:56.588829 CH0 RK0: MR19=505, MR18=1802
5348 20:11:56.595463 CH0_RK0: MR19=0x505, MR18=0x1802, DQSOSC=414, MR23=63, INC=63, DEC=42
5349 20:11:56.595583
5350 20:11:56.598673 ----->DramcWriteLeveling(PI) begin...
5351 20:11:56.598756 ==
5352 20:11:56.602369 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 20:11:56.605402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 20:11:56.605484 ==
5355 20:11:56.608607 Write leveling (Byte 0): 30 => 30
5356 20:11:56.611762 Write leveling (Byte 1): 30 => 30
5357 20:11:56.615525 DramcWriteLeveling(PI) end<-----
5358 20:11:56.615606
5359 20:11:56.615669 ==
5360 20:11:56.618333 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 20:11:56.622100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 20:11:56.622184 ==
5363 20:11:56.625459 [Gating] SW mode calibration
5364 20:11:56.632211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 20:11:56.638770 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5366 20:11:56.641892 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5367 20:11:56.645315 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 20:11:56.652128 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 20:11:56.655526 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 20:11:56.658894 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 20:11:56.665051 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 20:11:56.669073 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 20:11:56.671695 0 14 28 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
5374 20:11:56.678767 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 1) (0 0)
5375 20:11:56.681775 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5376 20:11:56.685333 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 20:11:56.692287 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 20:11:56.695341 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 20:11:56.698723 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 20:11:56.701840 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 20:11:56.709231 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5382 20:11:56.711999 1 0 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
5383 20:11:56.715322 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 20:11:56.721954 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 20:11:56.725832 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 20:11:56.728860 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 20:11:56.735364 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 20:11:56.739731 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5389 20:11:56.742551 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5390 20:11:56.748769 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5391 20:11:56.752303 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5392 20:11:56.755837 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 20:11:56.762315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 20:11:56.765734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 20:11:56.768932 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 20:11:56.775584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 20:11:56.779455 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 20:11:56.782063 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 20:11:56.785146 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 20:11:56.792339 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 20:11:56.795412 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 20:11:56.798549 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 20:11:56.805215 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 20:11:56.808465 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 20:11:56.812446 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5406 20:11:56.818783 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5407 20:11:56.821860 Total UI for P1: 0, mck2ui 16
5408 20:11:56.825567 best dqsien dly found for B0: ( 1, 2, 28)
5409 20:11:56.828836 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 20:11:56.832113 Total UI for P1: 0, mck2ui 16
5411 20:11:56.835690 best dqsien dly found for B1: ( 1, 3, 0)
5412 20:11:56.838978 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5413 20:11:56.842249 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5414 20:11:56.842370
5415 20:11:56.845269 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5416 20:11:56.848873 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5417 20:11:56.852010 [Gating] SW calibration Done
5418 20:11:56.852139 ==
5419 20:11:56.855918 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 20:11:56.859024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 20:11:56.859107 ==
5422 20:11:56.862291 RX Vref Scan: 0
5423 20:11:56.862420
5424 20:11:56.865632 RX Vref 0 -> 0, step: 1
5425 20:11:56.865714
5426 20:11:56.865779 RX Delay -80 -> 252, step: 8
5427 20:11:56.872356 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5428 20:11:56.875578 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5429 20:11:56.878893 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5430 20:11:56.882350 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5431 20:11:56.886135 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5432 20:11:56.889196 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5433 20:11:56.895560 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5434 20:11:56.899142 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5435 20:11:56.902203 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5436 20:11:56.905718 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5437 20:11:56.909484 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5438 20:11:56.915338 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5439 20:11:56.918788 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5440 20:11:56.922265 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5441 20:11:56.925825 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5442 20:11:56.928956 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5443 20:11:56.929037 ==
5444 20:11:56.932491 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 20:11:56.935339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 20:11:56.938634 ==
5447 20:11:56.938714 DQS Delay:
5448 20:11:56.938778 DQS0 = 0, DQS1 = 0
5449 20:11:56.942059 DQM Delay:
5450 20:11:56.942140 DQM0 = 96, DQM1 = 87
5451 20:11:56.945354 DQ Delay:
5452 20:11:56.948590 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =91
5453 20:11:56.948671 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5454 20:11:56.952214 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5455 20:11:56.958557 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5456 20:11:56.958713
5457 20:11:56.958822
5458 20:11:56.958916 ==
5459 20:11:56.962627 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 20:11:56.965347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 20:11:56.965446 ==
5462 20:11:56.965546
5463 20:11:56.965648
5464 20:11:56.969721 TX Vref Scan disable
5465 20:11:56.969816 == TX Byte 0 ==
5466 20:11:56.975724 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5467 20:11:56.978765 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5468 20:11:56.978847 == TX Byte 1 ==
5469 20:11:56.985812 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5470 20:11:56.988965 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5471 20:11:56.989047 ==
5472 20:11:56.992203 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 20:11:56.995743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 20:11:56.995854 ==
5475 20:11:56.995948
5476 20:11:56.996043
5477 20:11:56.998870 TX Vref Scan disable
5478 20:11:57.002102 == TX Byte 0 ==
5479 20:11:57.005511 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5480 20:11:57.009163 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5481 20:11:57.011949 == TX Byte 1 ==
5482 20:11:57.015609 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5483 20:11:57.018563 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5484 20:11:57.018673
5485 20:11:57.022169 [DATLAT]
5486 20:11:57.022253 Freq=933, CH0 RK1
5487 20:11:57.022319
5488 20:11:57.025297 DATLAT Default: 0xb
5489 20:11:57.025381 0, 0xFFFF, sum = 0
5490 20:11:57.028605 1, 0xFFFF, sum = 0
5491 20:11:57.028690 2, 0xFFFF, sum = 0
5492 20:11:57.032228 3, 0xFFFF, sum = 0
5493 20:11:57.032313 4, 0xFFFF, sum = 0
5494 20:11:57.035608 5, 0xFFFF, sum = 0
5495 20:11:57.035694 6, 0xFFFF, sum = 0
5496 20:11:57.038572 7, 0xFFFF, sum = 0
5497 20:11:57.038656 8, 0xFFFF, sum = 0
5498 20:11:57.042118 9, 0xFFFF, sum = 0
5499 20:11:57.042231 10, 0x0, sum = 1
5500 20:11:57.045131 11, 0x0, sum = 2
5501 20:11:57.045217 12, 0x0, sum = 3
5502 20:11:57.048594 13, 0x0, sum = 4
5503 20:11:57.048679 best_step = 11
5504 20:11:57.048743
5505 20:11:57.048804 ==
5506 20:11:57.052531 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 20:11:57.055290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 20:11:57.058585 ==
5509 20:11:57.058668 RX Vref Scan: 0
5510 20:11:57.058734
5511 20:11:57.061970 RX Vref 0 -> 0, step: 1
5512 20:11:57.062051
5513 20:11:57.065871 RX Delay -69 -> 252, step: 4
5514 20:11:57.069068 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5515 20:11:57.072440 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5516 20:11:57.075699 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5517 20:11:57.082087 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5518 20:11:57.085308 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5519 20:11:57.089340 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5520 20:11:57.092325 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5521 20:11:57.095468 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5522 20:11:57.099063 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5523 20:11:57.106176 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5524 20:11:57.108942 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5525 20:11:57.112351 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5526 20:11:57.115622 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5527 20:11:57.118611 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5528 20:11:57.125462 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5529 20:11:57.128594 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5530 20:11:57.128700 ==
5531 20:11:57.132311 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 20:11:57.135713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 20:11:57.135798 ==
5534 20:11:57.135864 DQS Delay:
5535 20:11:57.138420 DQS0 = 0, DQS1 = 0
5536 20:11:57.138504 DQM Delay:
5537 20:11:57.142195 DQM0 = 95, DQM1 = 88
5538 20:11:57.142277 DQ Delay:
5539 20:11:57.145450 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5540 20:11:57.148647 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =104
5541 20:11:57.152116 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5542 20:11:57.155006 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5543 20:11:57.155094
5544 20:11:57.155160
5545 20:11:57.165350 [DQSOSCAuto] RK1, (LSB)MR18= 0x1705, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5546 20:11:57.165434 CH0 RK1: MR19=505, MR18=1705
5547 20:11:57.171835 CH0_RK1: MR19=0x505, MR18=0x1705, DQSOSC=414, MR23=63, INC=63, DEC=42
5548 20:11:57.175106 [RxdqsGatingPostProcess] freq 933
5549 20:11:57.182329 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5550 20:11:57.185099 best DQS0 dly(2T, 0.5T) = (0, 11)
5551 20:11:57.188912 best DQS1 dly(2T, 0.5T) = (0, 11)
5552 20:11:57.191965 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5553 20:11:57.195641 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5554 20:11:57.198868 best DQS0 dly(2T, 0.5T) = (0, 10)
5555 20:11:57.198988 best DQS1 dly(2T, 0.5T) = (0, 11)
5556 20:11:57.202153 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5557 20:11:57.205652 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5558 20:11:57.209132 Pre-setting of DQS Precalculation
5559 20:11:57.215104 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5560 20:11:57.215227 ==
5561 20:11:57.218409 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 20:11:57.221628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 20:11:57.221750 ==
5564 20:11:57.228807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5565 20:11:57.235144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5566 20:11:57.238705 [CA 0] Center 37 (7~67) winsize 61
5567 20:11:57.241614 [CA 1] Center 37 (7~67) winsize 61
5568 20:11:57.245093 [CA 2] Center 34 (4~65) winsize 62
5569 20:11:57.248776 [CA 3] Center 34 (4~64) winsize 61
5570 20:11:57.251842 [CA 4] Center 34 (4~65) winsize 62
5571 20:11:57.251963 [CA 5] Center 33 (3~63) winsize 61
5572 20:11:57.255143
5573 20:11:57.258568 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5574 20:11:57.258689
5575 20:11:57.261795 [CATrainingPosCal] consider 1 rank data
5576 20:11:57.265526 u2DelayCellTimex100 = 270/100 ps
5577 20:11:57.268518 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5578 20:11:57.272373 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5579 20:11:57.275259 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 20:11:57.278322 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 20:11:57.281604 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5582 20:11:57.284949 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5583 20:11:57.285073
5584 20:11:57.288458 CA PerBit enable=1, Macro0, CA PI delay=33
5585 20:11:57.288577
5586 20:11:57.291898 [CBTSetCACLKResult] CA Dly = 33
5587 20:11:57.294930 CS Dly: 5 (0~36)
5588 20:11:57.295035 ==
5589 20:11:57.298950 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 20:11:57.302026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 20:11:57.302153 ==
5592 20:11:57.308359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5593 20:11:57.315096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5594 20:11:57.318418 [CA 0] Center 37 (7~67) winsize 61
5595 20:11:57.321559 [CA 1] Center 37 (7~67) winsize 61
5596 20:11:57.324937 [CA 2] Center 34 (4~65) winsize 62
5597 20:11:57.328336 [CA 3] Center 33 (3~64) winsize 62
5598 20:11:57.332087 [CA 4] Center 34 (4~64) winsize 61
5599 20:11:57.332208 [CA 5] Center 32 (2~63) winsize 62
5600 20:11:57.335262
5601 20:11:57.338414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5602 20:11:57.338538
5603 20:11:57.341605 [CATrainingPosCal] consider 2 rank data
5604 20:11:57.344892 u2DelayCellTimex100 = 270/100 ps
5605 20:11:57.348460 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5606 20:11:57.351486 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5607 20:11:57.355146 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5608 20:11:57.358725 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 20:11:57.361639 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5610 20:11:57.365292 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5611 20:11:57.365415
5612 20:11:57.368247 CA PerBit enable=1, Macro0, CA PI delay=33
5613 20:11:57.368370
5614 20:11:57.372115 [CBTSetCACLKResult] CA Dly = 33
5615 20:11:57.375120 CS Dly: 6 (0~38)
5616 20:11:57.375241
5617 20:11:57.378391 ----->DramcWriteLeveling(PI) begin...
5618 20:11:57.378521 ==
5619 20:11:57.381761 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 20:11:57.384876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 20:11:57.385002 ==
5622 20:11:57.388160 Write leveling (Byte 0): 27 => 27
5623 20:11:57.392242 Write leveling (Byte 1): 27 => 27
5624 20:11:57.395048 DramcWriteLeveling(PI) end<-----
5625 20:11:57.395166
5626 20:11:57.395277 ==
5627 20:11:57.397865 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 20:11:57.401479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 20:11:57.401601 ==
5630 20:11:57.405148 [Gating] SW mode calibration
5631 20:11:57.411494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5632 20:11:57.418101 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5633 20:11:57.421097 0 14 0 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 1)
5634 20:11:57.428310 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 20:11:57.431316 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 20:11:57.435145 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 20:11:57.438641 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 20:11:57.444789 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 20:11:57.447982 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5640 20:11:57.451846 0 14 28 | B1->B0 | 2f2f 3333 | 0 0 | (1 0) (0 1)
5641 20:11:57.458199 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (1 1) (0 0)
5642 20:11:57.461202 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 20:11:57.464960 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 20:11:57.471279 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 20:11:57.474829 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 20:11:57.478423 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 20:11:57.484516 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 20:11:57.487839 0 15 28 | B1->B0 | 3333 2f2f | 0 0 | (1 1) (1 1)
5649 20:11:57.491629 1 0 0 | B1->B0 | 4343 4242 | 0 0 | (0 0) (1 1)
5650 20:11:57.498215 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 20:11:57.501463 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 20:11:57.505024 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 20:11:57.511520 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 20:11:57.514686 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 20:11:57.517959 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 20:11:57.524734 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5657 20:11:57.528068 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5658 20:11:57.531278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 20:11:57.534697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 20:11:57.541582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 20:11:57.545045 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 20:11:57.548388 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 20:11:57.554689 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 20:11:57.558063 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 20:11:57.561651 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 20:11:57.567882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 20:11:57.571575 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 20:11:57.575002 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 20:11:57.581750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 20:11:57.584987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 20:11:57.588282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5672 20:11:57.594715 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5673 20:11:57.598500 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 20:11:57.601554 Total UI for P1: 0, mck2ui 16
5675 20:11:57.604660 best dqsien dly found for B0: ( 1, 2, 30)
5676 20:11:57.608436 Total UI for P1: 0, mck2ui 16
5677 20:11:57.612197 best dqsien dly found for B1: ( 1, 2, 28)
5678 20:11:57.614853 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5679 20:11:57.617960 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5680 20:11:57.618070
5681 20:11:57.621663 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5682 20:11:57.624634 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5683 20:11:57.628109 [Gating] SW calibration Done
5684 20:11:57.628193 ==
5685 20:11:57.631698 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 20:11:57.634790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 20:11:57.634872 ==
5688 20:11:57.638072 RX Vref Scan: 0
5689 20:11:57.638153
5690 20:11:57.641497 RX Vref 0 -> 0, step: 1
5691 20:11:57.641620
5692 20:11:57.641727 RX Delay -80 -> 252, step: 8
5693 20:11:57.648053 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5694 20:11:57.651282 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5695 20:11:57.654682 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5696 20:11:57.658217 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5697 20:11:57.661290 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5698 20:11:57.664425 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5699 20:11:57.671496 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5700 20:11:57.674516 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5701 20:11:57.678056 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5702 20:11:57.680957 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5703 20:11:57.684643 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5704 20:11:57.691401 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5705 20:11:57.694974 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5706 20:11:57.697735 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5707 20:11:57.701273 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5708 20:11:57.704871 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5709 20:11:57.704988 ==
5710 20:11:57.707671 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 20:11:57.714266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 20:11:57.714373 ==
5713 20:11:57.714473 DQS Delay:
5714 20:11:57.714534 DQS0 = 0, DQS1 = 0
5715 20:11:57.717882 DQM Delay:
5716 20:11:57.717963 DQM0 = 94, DQM1 = 88
5717 20:11:57.721387 DQ Delay:
5718 20:11:57.724510 DQ0 =99, DQ1 =87, DQ2 =79, DQ3 =95
5719 20:11:57.727539 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5720 20:11:57.731300 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =87
5721 20:11:57.734299 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5722 20:11:57.734434
5723 20:11:57.734541
5724 20:11:57.734620 ==
5725 20:11:57.737674 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 20:11:57.740996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 20:11:57.741099 ==
5728 20:11:57.741180
5729 20:11:57.741279
5730 20:11:57.744442 TX Vref Scan disable
5731 20:11:57.744518 == TX Byte 0 ==
5732 20:11:57.751046 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5733 20:11:57.754237 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5734 20:11:57.754318 == TX Byte 1 ==
5735 20:11:57.761398 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 20:11:57.764890 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 20:11:57.764971 ==
5738 20:11:57.767970 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 20:11:57.771142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 20:11:57.771226 ==
5741 20:11:57.771291
5742 20:11:57.771349
5743 20:11:57.774710 TX Vref Scan disable
5744 20:11:57.778000 == TX Byte 0 ==
5745 20:11:57.781239 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5746 20:11:57.784710 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5747 20:11:57.788032 == TX Byte 1 ==
5748 20:11:57.791566 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 20:11:57.794654 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 20:11:57.794739
5751 20:11:57.798215 [DATLAT]
5752 20:11:57.798293 Freq=933, CH1 RK0
5753 20:11:57.798406
5754 20:11:57.801072 DATLAT Default: 0xd
5755 20:11:57.801148 0, 0xFFFF, sum = 0
5756 20:11:57.804557 1, 0xFFFF, sum = 0
5757 20:11:57.804642 2, 0xFFFF, sum = 0
5758 20:11:57.807471 3, 0xFFFF, sum = 0
5759 20:11:57.807555 4, 0xFFFF, sum = 0
5760 20:11:57.811051 5, 0xFFFF, sum = 0
5761 20:11:57.811136 6, 0xFFFF, sum = 0
5762 20:11:57.814269 7, 0xFFFF, sum = 0
5763 20:11:57.814393 8, 0xFFFF, sum = 0
5764 20:11:57.817718 9, 0xFFFF, sum = 0
5765 20:11:57.817800 10, 0x0, sum = 1
5766 20:11:57.821102 11, 0x0, sum = 2
5767 20:11:57.821184 12, 0x0, sum = 3
5768 20:11:57.824422 13, 0x0, sum = 4
5769 20:11:57.824504 best_step = 11
5770 20:11:57.824567
5771 20:11:57.824626 ==
5772 20:11:57.827990 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 20:11:57.834664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 20:11:57.834746 ==
5775 20:11:57.834810 RX Vref Scan: 1
5776 20:11:57.834870
5777 20:11:57.837812 RX Vref 0 -> 0, step: 1
5778 20:11:57.837915
5779 20:11:57.841036 RX Delay -69 -> 252, step: 4
5780 20:11:57.841117
5781 20:11:57.844861 Set Vref, RX VrefLevel [Byte0]: 56
5782 20:11:57.848039 [Byte1]: 51
5783 20:11:57.848120
5784 20:11:57.851423 Final RX Vref Byte 0 = 56 to rank0
5785 20:11:57.854336 Final RX Vref Byte 1 = 51 to rank0
5786 20:11:57.857870 Final RX Vref Byte 0 = 56 to rank1
5787 20:11:57.861155 Final RX Vref Byte 1 = 51 to rank1==
5788 20:11:57.864279 Dram Type= 6, Freq= 0, CH_1, rank 0
5789 20:11:57.868066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 20:11:57.868152 ==
5791 20:11:57.870892 DQS Delay:
5792 20:11:57.870971 DQS0 = 0, DQS1 = 0
5793 20:11:57.871053 DQM Delay:
5794 20:11:57.874859 DQM0 = 97, DQM1 = 90
5795 20:11:57.874942 DQ Delay:
5796 20:11:57.878023 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5797 20:11:57.880864 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5798 20:11:57.884313 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =86
5799 20:11:57.887998 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5800 20:11:57.888077
5801 20:11:57.888165
5802 20:11:57.897537 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5803 20:11:57.900917 CH1 RK0: MR19=504, MR18=14F0
5804 20:11:57.904794 CH1_RK0: MR19=0x504, MR18=0x14F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5805 20:11:57.904872
5806 20:11:57.907904 ----->DramcWriteLeveling(PI) begin...
5807 20:11:57.910983 ==
5808 20:11:57.911068 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 20:11:57.917729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 20:11:57.917811 ==
5811 20:11:57.921399 Write leveling (Byte 0): 26 => 26
5812 20:11:57.924463 Write leveling (Byte 1): 25 => 25
5813 20:11:57.927390 DramcWriteLeveling(PI) end<-----
5814 20:11:57.927471
5815 20:11:57.927553 ==
5816 20:11:57.930876 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 20:11:57.934211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 20:11:57.934289 ==
5819 20:11:57.937935 [Gating] SW mode calibration
5820 20:11:57.944431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5821 20:11:57.947597 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5822 20:11:57.954913 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 20:11:57.957893 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 20:11:57.960958 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 20:11:57.967626 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5826 20:11:57.970977 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 20:11:57.974299 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 20:11:57.981010 0 14 24 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 1)
5829 20:11:57.984218 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5830 20:11:57.988001 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 20:11:57.994888 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 20:11:57.997991 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 20:11:58.001036 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 20:11:58.007661 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 20:11:58.010954 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 20:11:58.014561 0 15 24 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
5837 20:11:58.021335 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5838 20:11:58.024396 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 20:11:58.027971 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 20:11:58.031177 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 20:11:58.037958 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 20:11:58.041547 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 20:11:58.044584 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 20:11:58.051056 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5845 20:11:58.054660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 20:11:58.058634 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 20:11:58.064505 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 20:11:58.067776 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 20:11:58.071178 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 20:11:58.077897 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 20:11:58.081372 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 20:11:58.084768 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 20:11:58.091381 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 20:11:58.094570 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 20:11:58.098263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 20:11:58.101329 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 20:11:58.107846 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 20:11:58.111321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 20:11:58.114618 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 20:11:58.121436 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5861 20:11:58.124833 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 20:11:58.128272 Total UI for P1: 0, mck2ui 16
5863 20:11:58.131391 best dqsien dly found for B0: ( 1, 2, 24)
5864 20:11:58.134885 Total UI for P1: 0, mck2ui 16
5865 20:11:58.138069 best dqsien dly found for B1: ( 1, 2, 26)
5866 20:11:58.141510 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5867 20:11:58.145064 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5868 20:11:58.145144
5869 20:11:58.148206 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5870 20:11:58.151711 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5871 20:11:58.155213 [Gating] SW calibration Done
5872 20:11:58.155380 ==
5873 20:11:58.157978 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 20:11:58.161162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 20:11:58.164854 ==
5876 20:11:58.164937 RX Vref Scan: 0
5877 20:11:58.165001
5878 20:11:58.168112 RX Vref 0 -> 0, step: 1
5879 20:11:58.168182
5880 20:11:58.171219 RX Delay -80 -> 252, step: 8
5881 20:11:58.174669 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5882 20:11:58.178142 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5883 20:11:58.181245 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5884 20:11:58.184541 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5885 20:11:58.187918 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5886 20:11:58.194994 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5887 20:11:58.198858 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5888 20:11:58.201080 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5889 20:11:58.204742 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5890 20:11:58.208115 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5891 20:11:58.211338 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5892 20:11:58.217800 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5893 20:11:58.221058 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5894 20:11:58.225062 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5895 20:11:58.227912 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5896 20:11:58.231174 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5897 20:11:58.231255 ==
5898 20:11:58.234909 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 20:11:58.241214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 20:11:58.241316 ==
5901 20:11:58.241428 DQS Delay:
5902 20:11:58.241547 DQS0 = 0, DQS1 = 0
5903 20:11:58.244777 DQM Delay:
5904 20:11:58.244858 DQM0 = 94, DQM1 = 89
5905 20:11:58.248119 DQ Delay:
5906 20:11:58.251166 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5907 20:11:58.254799 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5908 20:11:58.258386 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5909 20:11:58.261522 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5910 20:11:58.261604
5911 20:11:58.261675
5912 20:11:58.261740 ==
5913 20:11:58.264751 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 20:11:58.268000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 20:11:58.268076 ==
5916 20:11:58.268138
5917 20:11:58.268204
5918 20:11:58.271339 TX Vref Scan disable
5919 20:11:58.271416 == TX Byte 0 ==
5920 20:11:58.278582 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5921 20:11:58.281565 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5922 20:11:58.281650 == TX Byte 1 ==
5923 20:11:58.288017 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5924 20:11:58.291752 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5925 20:11:58.291845 ==
5926 20:11:58.294658 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 20:11:58.298008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 20:11:58.298089 ==
5929 20:11:58.298153
5930 20:11:58.298212
5931 20:11:58.302104 TX Vref Scan disable
5932 20:11:58.304668 == TX Byte 0 ==
5933 20:11:58.308711 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5934 20:11:58.311561 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5935 20:11:58.314893 == TX Byte 1 ==
5936 20:11:58.318150 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5937 20:11:58.321149 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5938 20:11:58.321227
5939 20:11:58.324688 [DATLAT]
5940 20:11:58.324771 Freq=933, CH1 RK1
5941 20:11:58.324836
5942 20:11:58.327840 DATLAT Default: 0xb
5943 20:11:58.327973 0, 0xFFFF, sum = 0
5944 20:11:58.331814 1, 0xFFFF, sum = 0
5945 20:11:58.331915 2, 0xFFFF, sum = 0
5946 20:11:58.334700 3, 0xFFFF, sum = 0
5947 20:11:58.334778 4, 0xFFFF, sum = 0
5948 20:11:58.338552 5, 0xFFFF, sum = 0
5949 20:11:58.338628 6, 0xFFFF, sum = 0
5950 20:11:58.341263 7, 0xFFFF, sum = 0
5951 20:11:58.341340 8, 0xFFFF, sum = 0
5952 20:11:58.345063 9, 0xFFFF, sum = 0
5953 20:11:58.345146 10, 0x0, sum = 1
5954 20:11:58.348364 11, 0x0, sum = 2
5955 20:11:58.348445 12, 0x0, sum = 3
5956 20:11:58.351205 13, 0x0, sum = 4
5957 20:11:58.351280 best_step = 11
5958 20:11:58.351398
5959 20:11:58.351461 ==
5960 20:11:58.354603 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 20:11:58.361481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 20:11:58.361559 ==
5963 20:11:58.361634 RX Vref Scan: 0
5964 20:11:58.361696
5965 20:11:58.364961 RX Vref 0 -> 0, step: 1
5966 20:11:58.365039
5967 20:11:58.368970 RX Delay -61 -> 252, step: 4
5968 20:11:58.371389 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5969 20:11:58.374745 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5970 20:11:58.381525 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5971 20:11:58.384883 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5972 20:11:58.388310 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5973 20:11:58.391257 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5974 20:11:58.394753 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5975 20:11:58.398575 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5976 20:11:58.404749 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5977 20:11:58.408914 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5978 20:11:58.411103 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5979 20:11:58.414512 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5980 20:11:58.418115 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5981 20:11:58.421637 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5982 20:11:58.427909 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5983 20:11:58.431168 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5984 20:11:58.431246 ==
5985 20:11:58.435050 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 20:11:58.438387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 20:11:58.438500 ==
5988 20:11:58.441193 DQS Delay:
5989 20:11:58.441274 DQS0 = 0, DQS1 = 0
5990 20:11:58.441362 DQM Delay:
5991 20:11:58.445058 DQM0 = 95, DQM1 = 91
5992 20:11:58.445151 DQ Delay:
5993 20:11:58.448075 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5994 20:11:58.451371 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =90
5995 20:11:58.454805 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =84
5996 20:11:58.458525 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5997 20:11:58.458605
5998 20:11:58.458669
5999 20:11:58.467673 [DQSOSCAuto] RK1, (LSB)MR18= 0xa13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
6000 20:11:58.471587 CH1 RK1: MR19=505, MR18=A13
6001 20:11:58.474308 CH1_RK1: MR19=0x505, MR18=0xA13, DQSOSC=415, MR23=63, INC=62, DEC=41
6002 20:11:58.478025 [RxdqsGatingPostProcess] freq 933
6003 20:11:58.484342 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 20:11:58.487773 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 20:11:58.491251 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 20:11:58.494839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 20:11:58.497953 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 20:11:58.501295 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 20:11:58.504593 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 20:11:58.508206 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 20:11:58.511353 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 20:11:58.511435 Pre-setting of DQS Precalculation
6013 20:11:58.518035 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 20:11:58.524505 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 20:11:58.531427 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 20:11:58.531524
6017 20:11:58.531618
6018 20:11:58.534620 [Calibration Summary] 1866 Mbps
6019 20:11:58.538088 CH 0, Rank 0
6020 20:11:58.538169 SW Impedance : PASS
6021 20:11:58.541480 DUTY Scan : NO K
6022 20:11:58.541562 ZQ Calibration : PASS
6023 20:11:58.544714 Jitter Meter : NO K
6024 20:11:58.547789 CBT Training : PASS
6025 20:11:58.547871 Write leveling : PASS
6026 20:11:58.551463 RX DQS gating : PASS
6027 20:11:58.554835 RX DQ/DQS(RDDQC) : PASS
6028 20:11:58.554916 TX DQ/DQS : PASS
6029 20:11:58.557981 RX DATLAT : PASS
6030 20:11:58.561777 RX DQ/DQS(Engine): PASS
6031 20:11:58.561859 TX OE : NO K
6032 20:11:58.564622 All Pass.
6033 20:11:58.564703
6034 20:11:58.564766 CH 0, Rank 1
6035 20:11:58.568000 SW Impedance : PASS
6036 20:11:58.568081 DUTY Scan : NO K
6037 20:11:58.571659 ZQ Calibration : PASS
6038 20:11:58.575233 Jitter Meter : NO K
6039 20:11:58.575319 CBT Training : PASS
6040 20:11:58.578002 Write leveling : PASS
6041 20:11:58.581813 RX DQS gating : PASS
6042 20:11:58.581920 RX DQ/DQS(RDDQC) : PASS
6043 20:11:58.585027 TX DQ/DQS : PASS
6044 20:11:58.585108 RX DATLAT : PASS
6045 20:11:58.588136 RX DQ/DQS(Engine): PASS
6046 20:11:58.591049 TX OE : NO K
6047 20:11:58.591130 All Pass.
6048 20:11:58.591194
6049 20:11:58.591252 CH 1, Rank 0
6050 20:11:58.594666 SW Impedance : PASS
6051 20:11:58.598356 DUTY Scan : NO K
6052 20:11:58.598471 ZQ Calibration : PASS
6053 20:11:58.601102 Jitter Meter : NO K
6054 20:11:58.605050 CBT Training : PASS
6055 20:11:58.605144 Write leveling : PASS
6056 20:11:58.608115 RX DQS gating : PASS
6057 20:11:58.611337 RX DQ/DQS(RDDQC) : PASS
6058 20:11:58.611448 TX DQ/DQS : PASS
6059 20:11:58.614875 RX DATLAT : PASS
6060 20:11:58.617999 RX DQ/DQS(Engine): PASS
6061 20:11:58.618151 TX OE : NO K
6062 20:11:58.621500 All Pass.
6063 20:11:58.621580
6064 20:11:58.621643 CH 1, Rank 1
6065 20:11:58.624373 SW Impedance : PASS
6066 20:11:58.624460 DUTY Scan : NO K
6067 20:11:58.628268 ZQ Calibration : PASS
6068 20:11:58.631965 Jitter Meter : NO K
6069 20:11:58.632046 CBT Training : PASS
6070 20:11:58.634696 Write leveling : PASS
6071 20:11:58.634777 RX DQS gating : PASS
6072 20:11:58.638145 RX DQ/DQS(RDDQC) : PASS
6073 20:11:58.641530 TX DQ/DQS : PASS
6074 20:11:58.641611 RX DATLAT : PASS
6075 20:11:58.644712 RX DQ/DQS(Engine): PASS
6076 20:11:58.648342 TX OE : NO K
6077 20:11:58.648422 All Pass.
6078 20:11:58.648485
6079 20:11:58.651533 DramC Write-DBI off
6080 20:11:58.651647 PER_BANK_REFRESH: Hybrid Mode
6081 20:11:58.654634 TX_TRACKING: ON
6082 20:11:58.661107 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 20:11:58.667794 [FAST_K] Save calibration result to emmc
6084 20:11:58.671153 dramc_set_vcore_voltage set vcore to 650000
6085 20:11:58.671233 Read voltage for 400, 6
6086 20:11:58.674891 Vio18 = 0
6087 20:11:58.674971 Vcore = 650000
6088 20:11:58.675034 Vdram = 0
6089 20:11:58.678245 Vddq = 0
6090 20:11:58.678358 Vmddr = 0
6091 20:11:58.681671 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 20:11:58.687872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 20:11:58.691117 MEM_TYPE=3, freq_sel=20
6094 20:11:58.694895 sv_algorithm_assistance_LP4_800
6095 20:11:58.698110 ============ PULL DRAM RESETB DOWN ============
6096 20:11:58.701622 ========== PULL DRAM RESETB DOWN end =========
6097 20:11:58.704613 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 20:11:58.707912 ===================================
6099 20:11:58.711016 LPDDR4 DRAM CONFIGURATION
6100 20:11:58.714468 ===================================
6101 20:11:58.717949 EX_ROW_EN[0] = 0x0
6102 20:11:58.718060 EX_ROW_EN[1] = 0x0
6103 20:11:58.721240 LP4Y_EN = 0x0
6104 20:11:58.721321 WORK_FSP = 0x0
6105 20:11:58.724253 WL = 0x2
6106 20:11:58.724347 RL = 0x2
6107 20:11:58.727870 BL = 0x2
6108 20:11:58.727985 RPST = 0x0
6109 20:11:58.731170 RD_PRE = 0x0
6110 20:11:58.731252 WR_PRE = 0x1
6111 20:11:58.734904 WR_PST = 0x0
6112 20:11:58.734986 DBI_WR = 0x0
6113 20:11:58.738014 DBI_RD = 0x0
6114 20:11:58.738160 OTF = 0x1
6115 20:11:58.741171 ===================================
6116 20:11:58.744555 ===================================
6117 20:11:58.748067 ANA top config
6118 20:11:58.750884 ===================================
6119 20:11:58.754631 DLL_ASYNC_EN = 0
6120 20:11:58.754713 ALL_SLAVE_EN = 1
6121 20:11:58.757843 NEW_RANK_MODE = 1
6122 20:11:58.761949 DLL_IDLE_MODE = 1
6123 20:11:58.764460 LP45_APHY_COMB_EN = 1
6124 20:11:58.767609 TX_ODT_DIS = 1
6125 20:11:58.767691 NEW_8X_MODE = 1
6126 20:11:58.771433 ===================================
6127 20:11:58.774755 ===================================
6128 20:11:58.778315 data_rate = 800
6129 20:11:58.781443 CKR = 1
6130 20:11:58.784922 DQ_P2S_RATIO = 4
6131 20:11:58.788078 ===================================
6132 20:11:58.791717 CA_P2S_RATIO = 4
6133 20:11:58.791798 DQ_CA_OPEN = 0
6134 20:11:58.794678 DQ_SEMI_OPEN = 1
6135 20:11:58.797783 CA_SEMI_OPEN = 1
6136 20:11:58.801902 CA_FULL_RATE = 0
6137 20:11:58.804417 DQ_CKDIV4_EN = 0
6138 20:11:58.807806 CA_CKDIV4_EN = 1
6139 20:11:58.807888 CA_PREDIV_EN = 0
6140 20:11:58.811351 PH8_DLY = 0
6141 20:11:58.814815 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 20:11:58.817759 DQ_AAMCK_DIV = 0
6143 20:11:58.821199 CA_AAMCK_DIV = 0
6144 20:11:58.824506 CA_ADMCK_DIV = 4
6145 20:11:58.824587 DQ_TRACK_CA_EN = 0
6146 20:11:58.827853 CA_PICK = 800
6147 20:11:58.831801 CA_MCKIO = 400
6148 20:11:58.834765 MCKIO_SEMI = 400
6149 20:11:58.837762 PLL_FREQ = 3016
6150 20:11:58.841209 DQ_UI_PI_RATIO = 32
6151 20:11:58.844925 CA_UI_PI_RATIO = 32
6152 20:11:58.848174 ===================================
6153 20:11:58.851309 ===================================
6154 20:11:58.851394 memory_type:LPDDR4
6155 20:11:58.854814 GP_NUM : 10
6156 20:11:58.858328 SRAM_EN : 1
6157 20:11:58.858417 MD32_EN : 0
6158 20:11:58.861353 ===================================
6159 20:11:58.864799 [ANA_INIT] >>>>>>>>>>>>>>
6160 20:11:58.868170 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 20:11:58.871031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 20:11:58.874826 ===================================
6163 20:11:58.877719 data_rate = 800,PCW = 0X7400
6164 20:11:58.877800 ===================================
6165 20:11:58.884598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 20:11:58.887909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 20:11:58.901552 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 20:11:58.904685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 20:11:58.908106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 20:11:58.911129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 20:11:58.914766 [ANA_INIT] flow start
6172 20:11:58.914847 [ANA_INIT] PLL >>>>>>>>
6173 20:11:58.917946 [ANA_INIT] PLL <<<<<<<<
6174 20:11:58.921094 [ANA_INIT] MIDPI >>>>>>>>
6175 20:11:58.921176 [ANA_INIT] MIDPI <<<<<<<<
6176 20:11:58.924447 [ANA_INIT] DLL >>>>>>>>
6177 20:11:58.927881 [ANA_INIT] flow end
6178 20:11:58.931317 ============ LP4 DIFF to SE enter ============
6179 20:11:58.934430 ============ LP4 DIFF to SE exit ============
6180 20:11:58.937735 [ANA_INIT] <<<<<<<<<<<<<
6181 20:11:58.941411 [Flow] Enable top DCM control >>>>>
6182 20:11:58.944759 [Flow] Enable top DCM control <<<<<
6183 20:11:58.948297 Enable DLL master slave shuffle
6184 20:11:58.951185 ==============================================================
6185 20:11:58.954873 Gating Mode config
6186 20:11:58.960929 ==============================================================
6187 20:11:58.961011 Config description:
6188 20:11:58.971324 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 20:11:58.978033 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 20:11:58.980959 SELPH_MODE 0: By rank 1: By Phase
6191 20:11:58.987850 ==============================================================
6192 20:11:58.990858 GAT_TRACK_EN = 0
6193 20:11:58.994725 RX_GATING_MODE = 2
6194 20:11:58.997731 RX_GATING_TRACK_MODE = 2
6195 20:11:59.001748 SELPH_MODE = 1
6196 20:11:59.004216 PICG_EARLY_EN = 1
6197 20:11:59.007581 VALID_LAT_VALUE = 1
6198 20:11:59.011119 ==============================================================
6199 20:11:59.014523 Enter into Gating configuration >>>>
6200 20:11:59.017592 Exit from Gating configuration <<<<
6201 20:11:59.021311 Enter into DVFS_PRE_config >>>>>
6202 20:11:59.034520 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 20:11:59.034633 Exit from DVFS_PRE_config <<<<<
6204 20:11:59.037959 Enter into PICG configuration >>>>
6205 20:11:59.040908 Exit from PICG configuration <<<<
6206 20:11:59.044547 [RX_INPUT] configuration >>>>>
6207 20:11:59.048173 [RX_INPUT] configuration <<<<<
6208 20:11:59.054280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 20:11:59.057743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 20:11:59.064836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 20:11:59.070831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 20:11:59.078128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 20:11:59.084861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 20:11:59.088365 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 20:11:59.091244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 20:11:59.094867 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 20:11:59.101456 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 20:11:59.104411 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 20:11:59.108477 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 20:11:59.111084 ===================================
6221 20:11:59.114240 LPDDR4 DRAM CONFIGURATION
6222 20:11:59.117846 ===================================
6223 20:11:59.117928 EX_ROW_EN[0] = 0x0
6224 20:11:59.120990 EX_ROW_EN[1] = 0x0
6225 20:11:59.121071 LP4Y_EN = 0x0
6226 20:11:59.124415 WORK_FSP = 0x0
6227 20:11:59.124497 WL = 0x2
6228 20:11:59.127788 RL = 0x2
6229 20:11:59.127870 BL = 0x2
6230 20:11:59.131465 RPST = 0x0
6231 20:11:59.134350 RD_PRE = 0x0
6232 20:11:59.134452 WR_PRE = 0x1
6233 20:11:59.138309 WR_PST = 0x0
6234 20:11:59.138392 DBI_WR = 0x0
6235 20:11:59.141946 DBI_RD = 0x0
6236 20:11:59.142029 OTF = 0x1
6237 20:11:59.144842 ===================================
6238 20:11:59.148064 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 20:11:59.151256 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 20:11:59.157878 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 20:11:59.161502 ===================================
6242 20:11:59.164750 LPDDR4 DRAM CONFIGURATION
6243 20:11:59.168188 ===================================
6244 20:11:59.168269 EX_ROW_EN[0] = 0x10
6245 20:11:59.171522 EX_ROW_EN[1] = 0x0
6246 20:11:59.171603 LP4Y_EN = 0x0
6247 20:11:59.174844 WORK_FSP = 0x0
6248 20:11:59.174926 WL = 0x2
6249 20:11:59.177716 RL = 0x2
6250 20:11:59.177798 BL = 0x2
6251 20:11:59.181304 RPST = 0x0
6252 20:11:59.181385 RD_PRE = 0x0
6253 20:11:59.185022 WR_PRE = 0x1
6254 20:11:59.185104 WR_PST = 0x0
6255 20:11:59.188056 DBI_WR = 0x0
6256 20:11:59.188164 DBI_RD = 0x0
6257 20:11:59.191225 OTF = 0x1
6258 20:11:59.194777 ===================================
6259 20:11:59.201803 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 20:11:59.204937 nWR fixed to 30
6261 20:11:59.208336 [ModeRegInit_LP4] CH0 RK0
6262 20:11:59.208421 [ModeRegInit_LP4] CH0 RK1
6263 20:11:59.211764 [ModeRegInit_LP4] CH1 RK0
6264 20:11:59.214649 [ModeRegInit_LP4] CH1 RK1
6265 20:11:59.214731 match AC timing 19
6266 20:11:59.220972 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 20:11:59.224738 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 20:11:59.227946 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 20:11:59.234292 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 20:11:59.238685 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 20:11:59.238766 ==
6272 20:11:59.241466 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 20:11:59.244503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 20:11:59.244609 ==
6275 20:11:59.250976 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 20:11:59.257680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6277 20:11:59.261051 [CA 0] Center 36 (8~64) winsize 57
6278 20:11:59.264796 [CA 1] Center 36 (8~64) winsize 57
6279 20:11:59.264916 [CA 2] Center 36 (8~64) winsize 57
6280 20:11:59.267627 [CA 3] Center 36 (8~64) winsize 57
6281 20:11:59.271059 [CA 4] Center 36 (8~64) winsize 57
6282 20:11:59.274568 [CA 5] Center 36 (8~64) winsize 57
6283 20:11:59.274652
6284 20:11:59.277567 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6285 20:11:59.277648
6286 20:11:59.285008 [CATrainingPosCal] consider 1 rank data
6287 20:11:59.285090 u2DelayCellTimex100 = 270/100 ps
6288 20:11:59.290860 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 20:11:59.294810 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 20:11:59.297639 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 20:11:59.301213 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 20:11:59.304496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 20:11:59.307840 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 20:11:59.307922
6295 20:11:59.311349 CA PerBit enable=1, Macro0, CA PI delay=36
6296 20:11:59.311460
6297 20:11:59.314633 [CBTSetCACLKResult] CA Dly = 36
6298 20:11:59.314743 CS Dly: 1 (0~32)
6299 20:11:59.317842 ==
6300 20:11:59.321003 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 20:11:59.324551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 20:11:59.324632 ==
6303 20:11:59.327656 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 20:11:59.334749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6305 20:11:59.338165 [CA 0] Center 36 (8~64) winsize 57
6306 20:11:59.341051 [CA 1] Center 36 (8~64) winsize 57
6307 20:11:59.344600 [CA 2] Center 36 (8~64) winsize 57
6308 20:11:59.347831 [CA 3] Center 36 (8~64) winsize 57
6309 20:11:59.351403 [CA 4] Center 36 (8~64) winsize 57
6310 20:11:59.354888 [CA 5] Center 36 (8~64) winsize 57
6311 20:11:59.354969
6312 20:11:59.357752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6313 20:11:59.357833
6314 20:11:59.361476 [CATrainingPosCal] consider 2 rank data
6315 20:11:59.364295 u2DelayCellTimex100 = 270/100 ps
6316 20:11:59.367781 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 20:11:59.371219 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 20:11:59.374668 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 20:11:59.377816 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 20:11:59.380855 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 20:11:59.387538 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 20:11:59.387619
6323 20:11:59.391036 CA PerBit enable=1, Macro0, CA PI delay=36
6324 20:11:59.391143
6325 20:11:59.394635 [CBTSetCACLKResult] CA Dly = 36
6326 20:11:59.394750 CS Dly: 1 (0~32)
6327 20:11:59.394843
6328 20:11:59.398008 ----->DramcWriteLeveling(PI) begin...
6329 20:11:59.398091 ==
6330 20:11:59.401552 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 20:11:59.404829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 20:11:59.408474 ==
6333 20:11:59.408574 Write leveling (Byte 0): 40 => 8
6334 20:11:59.411259 Write leveling (Byte 1): 32 => 0
6335 20:11:59.414420 DramcWriteLeveling(PI) end<-----
6336 20:11:59.414524
6337 20:11:59.414587 ==
6338 20:11:59.417739 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 20:11:59.424808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 20:11:59.424914 ==
6341 20:11:59.425006 [Gating] SW mode calibration
6342 20:11:59.434677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 20:11:59.438006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 20:11:59.441628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 20:11:59.447571 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 20:11:59.452178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 20:11:59.454324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 20:11:59.461361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 20:11:59.464717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 20:11:59.468172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 20:11:59.474558 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 20:11:59.477845 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 20:11:59.480938 Total UI for P1: 0, mck2ui 16
6354 20:11:59.484213 best dqsien dly found for B0: ( 0, 14, 24)
6355 20:11:59.487943 Total UI for P1: 0, mck2ui 16
6356 20:11:59.492100 best dqsien dly found for B1: ( 0, 14, 24)
6357 20:11:59.494585 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 20:11:59.497902 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 20:11:59.498007
6360 20:11:59.501289 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 20:11:59.504572 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 20:11:59.508019 [Gating] SW calibration Done
6363 20:11:59.508119 ==
6364 20:11:59.511301 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 20:11:59.515111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 20:11:59.515211 ==
6367 20:11:59.518389 RX Vref Scan: 0
6368 20:11:59.518506
6369 20:11:59.521467 RX Vref 0 -> 0, step: 1
6370 20:11:59.521562
6371 20:11:59.521651 RX Delay -410 -> 252, step: 16
6372 20:11:59.528949 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6373 20:11:59.531816 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6374 20:11:59.535251 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6375 20:11:59.538074 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6376 20:11:59.545344 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6377 20:11:59.548535 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6378 20:11:59.552394 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6379 20:11:59.555304 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6380 20:11:59.561814 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6381 20:11:59.565091 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6382 20:11:59.568491 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6383 20:11:59.572219 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6384 20:11:59.578308 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6385 20:11:59.581630 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6386 20:11:59.585172 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6387 20:11:59.588462 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6388 20:11:59.591814 ==
6389 20:11:59.591920 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 20:11:59.598929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 20:11:59.599006 ==
6392 20:11:59.599087 DQS Delay:
6393 20:11:59.602216 DQS0 = 35, DQS1 = 51
6394 20:11:59.602283 DQM Delay:
6395 20:11:59.605128 DQM0 = 7, DQM1 = 10
6396 20:11:59.605209 DQ Delay:
6397 20:11:59.608974 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6398 20:11:59.611724 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6399 20:11:59.611838 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6400 20:11:59.618387 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6401 20:11:59.618508
6402 20:11:59.618573
6403 20:11:59.618632 ==
6404 20:11:59.622120 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 20:11:59.625097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 20:11:59.625180 ==
6407 20:11:59.625244
6408 20:11:59.625304
6409 20:11:59.628395 TX Vref Scan disable
6410 20:11:59.628476 == TX Byte 0 ==
6411 20:11:59.632323 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 20:11:59.638354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 20:11:59.638471 == TX Byte 1 ==
6414 20:11:59.641988 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6415 20:11:59.648547 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6416 20:11:59.648631 ==
6417 20:11:59.651623 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 20:11:59.656031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 20:11:59.656113 ==
6420 20:11:59.656222
6421 20:11:59.656311
6422 20:11:59.658369 TX Vref Scan disable
6423 20:11:59.658508 == TX Byte 0 ==
6424 20:11:59.664863 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 20:11:59.668749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 20:11:59.668831 == TX Byte 1 ==
6427 20:11:59.675242 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 20:11:59.678643 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 20:11:59.678725
6430 20:11:59.678789 [DATLAT]
6431 20:11:59.681860 Freq=400, CH0 RK0
6432 20:11:59.681941
6433 20:11:59.682005 DATLAT Default: 0xf
6434 20:11:59.685112 0, 0xFFFF, sum = 0
6435 20:11:59.685194 1, 0xFFFF, sum = 0
6436 20:11:59.688287 2, 0xFFFF, sum = 0
6437 20:11:59.688385 3, 0xFFFF, sum = 0
6438 20:11:59.691541 4, 0xFFFF, sum = 0
6439 20:11:59.691624 5, 0xFFFF, sum = 0
6440 20:11:59.695319 6, 0xFFFF, sum = 0
6441 20:11:59.695401 7, 0xFFFF, sum = 0
6442 20:11:59.698316 8, 0xFFFF, sum = 0
6443 20:11:59.698462 9, 0xFFFF, sum = 0
6444 20:11:59.702065 10, 0xFFFF, sum = 0
6445 20:11:59.702147 11, 0xFFFF, sum = 0
6446 20:11:59.705128 12, 0xFFFF, sum = 0
6447 20:11:59.705227 13, 0x0, sum = 1
6448 20:11:59.708259 14, 0x0, sum = 2
6449 20:11:59.708341 15, 0x0, sum = 3
6450 20:11:59.712031 16, 0x0, sum = 4
6451 20:11:59.712113 best_step = 14
6452 20:11:59.712177
6453 20:11:59.712236 ==
6454 20:11:59.715081 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 20:11:59.722008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 20:11:59.722146 ==
6457 20:11:59.722283 RX Vref Scan: 1
6458 20:11:59.722372
6459 20:11:59.725432 RX Vref 0 -> 0, step: 1
6460 20:11:59.725513
6461 20:11:59.728357 RX Delay -343 -> 252, step: 8
6462 20:11:59.728438
6463 20:11:59.731396 Set Vref, RX VrefLevel [Byte0]: 54
6464 20:11:59.734895 [Byte1]: 52
6465 20:11:59.738171
6466 20:11:59.738278 Final RX Vref Byte 0 = 54 to rank0
6467 20:11:59.741784 Final RX Vref Byte 1 = 52 to rank0
6468 20:11:59.745389 Final RX Vref Byte 0 = 54 to rank1
6469 20:11:59.748083 Final RX Vref Byte 1 = 52 to rank1==
6470 20:11:59.751648 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 20:11:59.755706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 20:11:59.758230 ==
6473 20:11:59.758328 DQS Delay:
6474 20:11:59.758452 DQS0 = 44, DQS1 = 60
6475 20:11:59.761587 DQM Delay:
6476 20:11:59.761686 DQM0 = 12, DQM1 = 16
6477 20:11:59.765846 DQ Delay:
6478 20:11:59.765943 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6479 20:11:59.768629 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6480 20:11:59.772638 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6481 20:11:59.775480 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6482 20:11:59.775580
6483 20:11:59.775681
6484 20:11:59.785095 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f4d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6485 20:11:59.788159 CH0 RK0: MR19=C0C, MR18=7F4D
6486 20:11:59.795128 CH0_RK0: MR19=0xC0C, MR18=0x7F4D, DQSOSC=393, MR23=63, INC=382, DEC=254
6487 20:11:59.795208 ==
6488 20:11:59.798114 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 20:11:59.801767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 20:11:59.801871 ==
6491 20:11:59.805212 [Gating] SW mode calibration
6492 20:11:59.811773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 20:11:59.815151 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 20:11:59.822070 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 20:11:59.825017 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 20:11:59.828429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 20:11:59.835104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 20:11:59.838280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 20:11:59.842356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 20:11:59.848541 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 20:11:59.851590 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 20:11:59.855235 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 20:11:59.858581 Total UI for P1: 0, mck2ui 16
6504 20:11:59.862142 best dqsien dly found for B0: ( 0, 14, 24)
6505 20:11:59.865025 Total UI for P1: 0, mck2ui 16
6506 20:11:59.868523 best dqsien dly found for B1: ( 0, 14, 24)
6507 20:11:59.871501 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 20:11:59.874803 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 20:11:59.874885
6510 20:11:59.881580 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 20:11:59.884755 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 20:11:59.884836 [Gating] SW calibration Done
6513 20:11:59.888085 ==
6514 20:11:59.891694 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 20:11:59.895573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 20:11:59.895656 ==
6517 20:11:59.895719 RX Vref Scan: 0
6518 20:11:59.895779
6519 20:11:59.898133 RX Vref 0 -> 0, step: 1
6520 20:11:59.898214
6521 20:11:59.901712 RX Delay -410 -> 252, step: 16
6522 20:11:59.905476 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6523 20:11:59.908655 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6524 20:11:59.915213 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6525 20:11:59.918523 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6526 20:11:59.921768 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6527 20:11:59.925090 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6528 20:11:59.931666 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6529 20:11:59.934930 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6530 20:11:59.938602 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6531 20:11:59.941572 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6532 20:11:59.948210 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6533 20:11:59.951827 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6534 20:11:59.955204 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6535 20:11:59.958337 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6536 20:11:59.965169 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6537 20:11:59.968499 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6538 20:11:59.968573 ==
6539 20:11:59.972055 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 20:11:59.975382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 20:11:59.975485 ==
6542 20:11:59.978807 DQS Delay:
6543 20:11:59.978901 DQS0 = 43, DQS1 = 51
6544 20:11:59.981563 DQM Delay:
6545 20:11:59.981637 DQM0 = 11, DQM1 = 10
6546 20:11:59.981699 DQ Delay:
6547 20:11:59.985090 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6548 20:11:59.988604 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6549 20:11:59.992578 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6550 20:11:59.995061 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6551 20:11:59.995139
6552 20:11:59.995205
6553 20:11:59.995263 ==
6554 20:11:59.998554 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 20:12:00.001779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 20:12:00.005026 ==
6557 20:12:00.005125
6558 20:12:00.005222
6559 20:12:00.005309 TX Vref Scan disable
6560 20:12:00.008505 == TX Byte 0 ==
6561 20:12:00.011475 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6562 20:12:00.015371 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6563 20:12:00.018520 == TX Byte 1 ==
6564 20:12:00.021945 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6565 20:12:00.025154 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6566 20:12:00.025229 ==
6567 20:12:00.028807 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 20:12:00.031841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 20:12:00.035272 ==
6570 20:12:00.035372
6571 20:12:00.035460
6572 20:12:00.035547 TX Vref Scan disable
6573 20:12:00.038584 == TX Byte 0 ==
6574 20:12:00.042069 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6575 20:12:00.044915 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6576 20:12:00.048254 == TX Byte 1 ==
6577 20:12:00.051722 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6578 20:12:00.055247 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6579 20:12:00.055350
6580 20:12:00.055444 [DATLAT]
6581 20:12:00.058385 Freq=400, CH0 RK1
6582 20:12:00.058501
6583 20:12:00.061837 DATLAT Default: 0xe
6584 20:12:00.061934 0, 0xFFFF, sum = 0
6585 20:12:00.065017 1, 0xFFFF, sum = 0
6586 20:12:00.065121 2, 0xFFFF, sum = 0
6587 20:12:00.068816 3, 0xFFFF, sum = 0
6588 20:12:00.068921 4, 0xFFFF, sum = 0
6589 20:12:00.071720 5, 0xFFFF, sum = 0
6590 20:12:00.071824 6, 0xFFFF, sum = 0
6591 20:12:00.074796 7, 0xFFFF, sum = 0
6592 20:12:00.074870 8, 0xFFFF, sum = 0
6593 20:12:00.078130 9, 0xFFFF, sum = 0
6594 20:12:00.078228 10, 0xFFFF, sum = 0
6595 20:12:00.081588 11, 0xFFFF, sum = 0
6596 20:12:00.081689 12, 0xFFFF, sum = 0
6597 20:12:00.084790 13, 0x0, sum = 1
6598 20:12:00.084874 14, 0x0, sum = 2
6599 20:12:00.087984 15, 0x0, sum = 3
6600 20:12:00.088066 16, 0x0, sum = 4
6601 20:12:00.091608 best_step = 14
6602 20:12:00.091688
6603 20:12:00.091752 ==
6604 20:12:00.095180 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 20:12:00.098288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 20:12:00.098432 ==
6607 20:12:00.101694 RX Vref Scan: 0
6608 20:12:00.101775
6609 20:12:00.101839 RX Vref 0 -> 0, step: 1
6610 20:12:00.101899
6611 20:12:00.104772 RX Delay -343 -> 252, step: 8
6612 20:12:00.113358 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6613 20:12:00.116194 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6614 20:12:00.119195 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6615 20:12:00.122853 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6616 20:12:00.129376 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6617 20:12:00.132963 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6618 20:12:00.136358 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6619 20:12:00.139030 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6620 20:12:00.145941 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6621 20:12:00.149628 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6622 20:12:00.152634 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6623 20:12:00.155930 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6624 20:12:00.163171 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6625 20:12:00.166262 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6626 20:12:00.169688 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6627 20:12:00.172970 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6628 20:12:00.175901 ==
6629 20:12:00.179680 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 20:12:00.183092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 20:12:00.183174 ==
6632 20:12:00.183238 DQS Delay:
6633 20:12:00.186243 DQS0 = 48, DQS1 = 60
6634 20:12:00.186350 DQM Delay:
6635 20:12:00.189427 DQM0 = 13, DQM1 = 13
6636 20:12:00.189534 DQ Delay:
6637 20:12:00.192534 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6638 20:12:00.195837 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6639 20:12:00.199524 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6640 20:12:00.203252 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6641 20:12:00.203333
6642 20:12:00.203396
6643 20:12:00.209823 [DQSOSCAuto] RK1, (LSB)MR18= 0x9467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6644 20:12:00.212658 CH0 RK1: MR19=C0C, MR18=9467
6645 20:12:00.219597 CH0_RK1: MR19=0xC0C, MR18=0x9467, DQSOSC=391, MR23=63, INC=386, DEC=257
6646 20:12:00.222709 [RxdqsGatingPostProcess] freq 400
6647 20:12:00.226112 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 20:12:00.229145 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 20:12:00.232975 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 20:12:00.236467 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 20:12:00.239270 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 20:12:00.242608 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 20:12:00.245884 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 20:12:00.249109 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 20:12:00.252556 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 20:12:00.256443 Pre-setting of DQS Precalculation
6657 20:12:00.259256 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 20:12:00.263008 ==
6659 20:12:00.263090 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 20:12:00.269406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 20:12:00.269488 ==
6662 20:12:00.272745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 20:12:00.279348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6664 20:12:00.282893 [CA 0] Center 36 (8~64) winsize 57
6665 20:12:00.285998 [CA 1] Center 36 (8~64) winsize 57
6666 20:12:00.289567 [CA 2] Center 36 (8~64) winsize 57
6667 20:12:00.292826 [CA 3] Center 36 (8~64) winsize 57
6668 20:12:00.296107 [CA 4] Center 36 (8~64) winsize 57
6669 20:12:00.299515 [CA 5] Center 36 (8~64) winsize 57
6670 20:12:00.299596
6671 20:12:00.302937 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6672 20:12:00.303018
6673 20:12:00.306238 [CATrainingPosCal] consider 1 rank data
6674 20:12:00.309472 u2DelayCellTimex100 = 270/100 ps
6675 20:12:00.312769 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 20:12:00.315845 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 20:12:00.320172 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 20:12:00.323059 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 20:12:00.326864 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 20:12:00.329876 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 20:12:00.329959
6682 20:12:00.335994 CA PerBit enable=1, Macro0, CA PI delay=36
6683 20:12:00.336076
6684 20:12:00.339972 [CBTSetCACLKResult] CA Dly = 36
6685 20:12:00.340053 CS Dly: 1 (0~32)
6686 20:12:00.340118 ==
6687 20:12:00.342508 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 20:12:00.346194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 20:12:00.346275 ==
6690 20:12:00.352683 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 20:12:00.359116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6692 20:12:00.362765 [CA 0] Center 36 (8~64) winsize 57
6693 20:12:00.366197 [CA 1] Center 36 (8~64) winsize 57
6694 20:12:00.369346 [CA 2] Center 36 (8~64) winsize 57
6695 20:12:00.372855 [CA 3] Center 36 (8~64) winsize 57
6696 20:12:00.375861 [CA 4] Center 36 (8~64) winsize 57
6697 20:12:00.375943 [CA 5] Center 36 (8~64) winsize 57
6698 20:12:00.376007
6699 20:12:00.382439 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6700 20:12:00.382521
6701 20:12:00.386156 [CATrainingPosCal] consider 2 rank data
6702 20:12:00.389279 u2DelayCellTimex100 = 270/100 ps
6703 20:12:00.392909 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 20:12:00.396269 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 20:12:00.399342 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 20:12:00.402614 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 20:12:00.405867 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 20:12:00.409445 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 20:12:00.409527
6710 20:12:00.413290 CA PerBit enable=1, Macro0, CA PI delay=36
6711 20:12:00.413371
6712 20:12:00.415755 [CBTSetCACLKResult] CA Dly = 36
6713 20:12:00.419709 CS Dly: 1 (0~32)
6714 20:12:00.419790
6715 20:12:00.422664 ----->DramcWriteLeveling(PI) begin...
6716 20:12:00.422747 ==
6717 20:12:00.425953 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 20:12:00.429650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 20:12:00.429733 ==
6720 20:12:00.432603 Write leveling (Byte 0): 40 => 8
6721 20:12:00.435978 Write leveling (Byte 1): 40 => 8
6722 20:12:00.439294 DramcWriteLeveling(PI) end<-----
6723 20:12:00.439375
6724 20:12:00.439439 ==
6725 20:12:00.442555 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 20:12:00.445892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 20:12:00.445973 ==
6728 20:12:00.449085 [Gating] SW mode calibration
6729 20:12:00.456146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 20:12:00.462755 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 20:12:00.466051 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 20:12:00.469757 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6733 20:12:00.475948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 20:12:00.479259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 20:12:00.482904 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 20:12:00.489100 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 20:12:00.492414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 20:12:00.496622 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 20:12:00.502978 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 20:12:00.503060 Total UI for P1: 0, mck2ui 16
6741 20:12:00.509118 best dqsien dly found for B0: ( 0, 14, 24)
6742 20:12:00.509223 Total UI for P1: 0, mck2ui 16
6743 20:12:00.513066 best dqsien dly found for B1: ( 0, 14, 24)
6744 20:12:00.519216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 20:12:00.523056 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 20:12:00.523138
6747 20:12:00.526215 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 20:12:00.529404 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 20:12:00.532704 [Gating] SW calibration Done
6750 20:12:00.532815 ==
6751 20:12:00.536159 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 20:12:00.539279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 20:12:00.539362 ==
6754 20:12:00.542642 RX Vref Scan: 0
6755 20:12:00.542737
6756 20:12:00.542817 RX Vref 0 -> 0, step: 1
6757 20:12:00.542877
6758 20:12:00.545826 RX Delay -410 -> 252, step: 16
6759 20:12:00.549010 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6760 20:12:00.555923 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6761 20:12:00.559531 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6762 20:12:00.562873 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6763 20:12:00.565707 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6764 20:12:00.572377 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6765 20:12:00.575655 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6766 20:12:00.579112 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6767 20:12:00.582811 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6768 20:12:00.589434 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6769 20:12:00.592325 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6770 20:12:00.596064 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6771 20:12:00.598874 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6772 20:12:00.605762 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6773 20:12:00.609749 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6774 20:12:00.612587 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6775 20:12:00.612668 ==
6776 20:12:00.616172 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 20:12:00.622314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 20:12:00.622448 ==
6779 20:12:00.622547 DQS Delay:
6780 20:12:00.626026 DQS0 = 51, DQS1 = 59
6781 20:12:00.626134 DQM Delay:
6782 20:12:00.626226 DQM0 = 19, DQM1 = 16
6783 20:12:00.629088 DQ Delay:
6784 20:12:00.632461 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6785 20:12:00.632542 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6786 20:12:00.635990 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6787 20:12:00.639138 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6788 20:12:00.642621
6789 20:12:00.642702
6790 20:12:00.642780 ==
6791 20:12:00.646671 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 20:12:00.650179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 20:12:00.650286 ==
6794 20:12:00.650378
6795 20:12:00.650484
6796 20:12:00.652636 TX Vref Scan disable
6797 20:12:00.652744 == TX Byte 0 ==
6798 20:12:00.656025 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 20:12:00.662582 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 20:12:00.662665 == TX Byte 1 ==
6801 20:12:00.665958 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 20:12:00.672354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 20:12:00.672436 ==
6804 20:12:00.675871 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 20:12:00.679272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 20:12:00.679375 ==
6807 20:12:00.679453
6808 20:12:00.679512
6809 20:12:00.682652 TX Vref Scan disable
6810 20:12:00.682733 == TX Byte 0 ==
6811 20:12:00.686026 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 20:12:00.692457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 20:12:00.692564 == TX Byte 1 ==
6814 20:12:00.695948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 20:12:00.703162 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 20:12:00.703273
6817 20:12:00.703366 [DATLAT]
6818 20:12:00.703471 Freq=400, CH1 RK0
6819 20:12:00.703564
6820 20:12:00.706153 DATLAT Default: 0xf
6821 20:12:00.706256 0, 0xFFFF, sum = 0
6822 20:12:00.709329 1, 0xFFFF, sum = 0
6823 20:12:00.713682 2, 0xFFFF, sum = 0
6824 20:12:00.713766 3, 0xFFFF, sum = 0
6825 20:12:00.715893 4, 0xFFFF, sum = 0
6826 20:12:00.715993 5, 0xFFFF, sum = 0
6827 20:12:00.719609 6, 0xFFFF, sum = 0
6828 20:12:00.719692 7, 0xFFFF, sum = 0
6829 20:12:00.722805 8, 0xFFFF, sum = 0
6830 20:12:00.722888 9, 0xFFFF, sum = 0
6831 20:12:00.726154 10, 0xFFFF, sum = 0
6832 20:12:00.726264 11, 0xFFFF, sum = 0
6833 20:12:00.729608 12, 0xFFFF, sum = 0
6834 20:12:00.729691 13, 0x0, sum = 1
6835 20:12:00.732659 14, 0x0, sum = 2
6836 20:12:00.732753 15, 0x0, sum = 3
6837 20:12:00.736178 16, 0x0, sum = 4
6838 20:12:00.736260 best_step = 14
6839 20:12:00.736325
6840 20:12:00.736384 ==
6841 20:12:00.739552 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 20:12:00.742772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 20:12:00.742853 ==
6844 20:12:00.746174 RX Vref Scan: 1
6845 20:12:00.746279
6846 20:12:00.749711 RX Vref 0 -> 0, step: 1
6847 20:12:00.749793
6848 20:12:00.749857 RX Delay -359 -> 252, step: 8
6849 20:12:00.749917
6850 20:12:00.753038 Set Vref, RX VrefLevel [Byte0]: 56
6851 20:12:00.756471 [Byte1]: 51
6852 20:12:00.761787
6853 20:12:00.761868 Final RX Vref Byte 0 = 56 to rank0
6854 20:12:00.764790 Final RX Vref Byte 1 = 51 to rank0
6855 20:12:00.768445 Final RX Vref Byte 0 = 56 to rank1
6856 20:12:00.772115 Final RX Vref Byte 1 = 51 to rank1==
6857 20:12:00.774752 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 20:12:00.781793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 20:12:00.781874 ==
6860 20:12:00.781939 DQS Delay:
6861 20:12:00.785127 DQS0 = 48, DQS1 = 60
6862 20:12:00.785233 DQM Delay:
6863 20:12:00.785325 DQM0 = 12, DQM1 = 13
6864 20:12:00.788283 DQ Delay:
6865 20:12:00.792309 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6866 20:12:00.792390 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6867 20:12:00.794808 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6868 20:12:00.798347 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6869 20:12:00.798479
6870 20:12:00.798543
6871 20:12:00.808509 [DQSOSCAuto] RK0, (LSB)MR18= 0x852c, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6872 20:12:00.812241 CH1 RK0: MR19=C0C, MR18=852C
6873 20:12:00.818195 CH1_RK0: MR19=0xC0C, MR18=0x852C, DQSOSC=393, MR23=63, INC=382, DEC=254
6874 20:12:00.818303 ==
6875 20:12:00.821885 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 20:12:00.825465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 20:12:00.825551 ==
6878 20:12:00.828222 [Gating] SW mode calibration
6879 20:12:00.835044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 20:12:00.838305 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 20:12:00.845408 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 20:12:00.848953 0 11 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
6883 20:12:00.852207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 20:12:00.858780 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 20:12:00.862324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 20:12:00.865091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 20:12:00.872208 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 20:12:00.875750 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 20:12:00.878659 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 20:12:00.882345 Total UI for P1: 0, mck2ui 16
6891 20:12:00.885587 best dqsien dly found for B0: ( 0, 14, 24)
6892 20:12:00.888538 Total UI for P1: 0, mck2ui 16
6893 20:12:00.891931 best dqsien dly found for B1: ( 0, 14, 24)
6894 20:12:00.895463 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 20:12:00.898889 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 20:12:00.898971
6897 20:12:00.902799 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 20:12:00.908669 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 20:12:00.908750 [Gating] SW calibration Done
6900 20:12:00.908815 ==
6901 20:12:00.912230 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 20:12:00.918587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 20:12:00.918695 ==
6904 20:12:00.918774 RX Vref Scan: 0
6905 20:12:00.918835
6906 20:12:00.921903 RX Vref 0 -> 0, step: 1
6907 20:12:00.921984
6908 20:12:00.925319 RX Delay -410 -> 252, step: 16
6909 20:12:00.928365 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6910 20:12:00.932067 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6911 20:12:00.938421 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6912 20:12:00.941908 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6913 20:12:00.945297 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6914 20:12:00.948560 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6915 20:12:00.954991 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6916 20:12:00.958761 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6917 20:12:00.962166 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6918 20:12:00.965138 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6919 20:12:00.971623 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6920 20:12:00.974914 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6921 20:12:00.978568 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6922 20:12:00.982473 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6923 20:12:00.988196 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6924 20:12:00.992312 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6925 20:12:00.992393 ==
6926 20:12:00.995047 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 20:12:00.998196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 20:12:00.998277 ==
6929 20:12:01.001593 DQS Delay:
6930 20:12:01.001674 DQS0 = 43, DQS1 = 59
6931 20:12:01.005415 DQM Delay:
6932 20:12:01.005495 DQM0 = 9, DQM1 = 18
6933 20:12:01.005558 DQ Delay:
6934 20:12:01.008767 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6935 20:12:01.011965 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6936 20:12:01.015164 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6937 20:12:01.018554 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6938 20:12:01.018635
6939 20:12:01.018699
6940 20:12:01.018758 ==
6941 20:12:01.021473 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 20:12:01.025140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 20:12:01.025247 ==
6944 20:12:01.028353
6945 20:12:01.028452
6946 20:12:01.028543 TX Vref Scan disable
6947 20:12:01.031560 == TX Byte 0 ==
6948 20:12:01.035894 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6949 20:12:01.038807 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6950 20:12:01.042084 == TX Byte 1 ==
6951 20:12:01.045224 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6952 20:12:01.048881 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6953 20:12:01.048962 ==
6954 20:12:01.051737 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 20:12:01.055403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 20:12:01.055485 ==
6957 20:12:01.058730
6958 20:12:01.058811
6959 20:12:01.058913 TX Vref Scan disable
6960 20:12:01.061933 == TX Byte 0 ==
6961 20:12:01.065163 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 20:12:01.068826 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 20:12:01.072000 == TX Byte 1 ==
6964 20:12:01.075160 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6965 20:12:01.078594 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6966 20:12:01.078694
6967 20:12:01.078783 [DATLAT]
6968 20:12:01.082030 Freq=400, CH1 RK1
6969 20:12:01.082127
6970 20:12:01.082217 DATLAT Default: 0xe
6971 20:12:01.085171 0, 0xFFFF, sum = 0
6972 20:12:01.085269 1, 0xFFFF, sum = 0
6973 20:12:01.089072 2, 0xFFFF, sum = 0
6974 20:12:01.092238 3, 0xFFFF, sum = 0
6975 20:12:01.092327 4, 0xFFFF, sum = 0
6976 20:12:01.095338 5, 0xFFFF, sum = 0
6977 20:12:01.095425 6, 0xFFFF, sum = 0
6978 20:12:01.099082 7, 0xFFFF, sum = 0
6979 20:12:01.099185 8, 0xFFFF, sum = 0
6980 20:12:01.101854 9, 0xFFFF, sum = 0
6981 20:12:01.101956 10, 0xFFFF, sum = 0
6982 20:12:01.105496 11, 0xFFFF, sum = 0
6983 20:12:01.105598 12, 0xFFFF, sum = 0
6984 20:12:01.108436 13, 0x0, sum = 1
6985 20:12:01.108537 14, 0x0, sum = 2
6986 20:12:01.111744 15, 0x0, sum = 3
6987 20:12:01.111846 16, 0x0, sum = 4
6988 20:12:01.115586 best_step = 14
6989 20:12:01.115680
6990 20:12:01.115775 ==
6991 20:12:01.119013 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 20:12:01.121692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 20:12:01.121793 ==
6994 20:12:01.121892 RX Vref Scan: 0
6995 20:12:01.122011
6996 20:12:01.125679 RX Vref 0 -> 0, step: 1
6997 20:12:01.125779
6998 20:12:01.129010 RX Delay -359 -> 252, step: 8
6999 20:12:01.135662 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7000 20:12:01.138844 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7001 20:12:01.142612 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7002 20:12:01.145751 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7003 20:12:01.152450 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7004 20:12:01.155551 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7005 20:12:01.158900 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7006 20:12:01.162175 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7007 20:12:01.169379 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7008 20:12:01.172843 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7009 20:12:01.175835 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7010 20:12:01.179495 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7011 20:12:01.185597 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7012 20:12:01.189321 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7013 20:12:01.192575 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7014 20:12:01.195706 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7015 20:12:01.199719 ==
7016 20:12:01.203126 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 20:12:01.206005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 20:12:01.206113 ==
7019 20:12:01.206205 DQS Delay:
7020 20:12:01.209440 DQS0 = 52, DQS1 = 60
7021 20:12:01.209540 DQM Delay:
7022 20:12:01.212426 DQM0 = 13, DQM1 = 13
7023 20:12:01.212508 DQ Delay:
7024 20:12:01.215718 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7025 20:12:01.219264 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7026 20:12:01.222938 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
7027 20:12:01.225747 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7028 20:12:01.225829
7029 20:12:01.225893
7030 20:12:01.232301 [DQSOSCAuto] RK1, (LSB)MR18= 0x788e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7031 20:12:01.235610 CH1 RK1: MR19=C0C, MR18=788E
7032 20:12:01.242683 CH1_RK1: MR19=0xC0C, MR18=0x788E, DQSOSC=392, MR23=63, INC=384, DEC=256
7033 20:12:01.245757 [RxdqsGatingPostProcess] freq 400
7034 20:12:01.248966 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 20:12:01.252323 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 20:12:01.255783 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 20:12:01.259084 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 20:12:01.262536 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 20:12:01.265690 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 20:12:01.268846 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 20:12:01.272175 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 20:12:01.275462 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 20:12:01.278901 Pre-setting of DQS Precalculation
7044 20:12:01.282118 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 20:12:01.292092 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 20:12:01.299309 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 20:12:01.299392
7048 20:12:01.299456
7049 20:12:01.302285 [Calibration Summary] 800 Mbps
7050 20:12:01.302392 CH 0, Rank 0
7051 20:12:01.305642 SW Impedance : PASS
7052 20:12:01.305724 DUTY Scan : NO K
7053 20:12:01.308797 ZQ Calibration : PASS
7054 20:12:01.312228 Jitter Meter : NO K
7055 20:12:01.312310 CBT Training : PASS
7056 20:12:01.315528 Write leveling : PASS
7057 20:12:01.319230 RX DQS gating : PASS
7058 20:12:01.319312 RX DQ/DQS(RDDQC) : PASS
7059 20:12:01.322366 TX DQ/DQS : PASS
7060 20:12:01.325886 RX DATLAT : PASS
7061 20:12:01.325995 RX DQ/DQS(Engine): PASS
7062 20:12:01.328910 TX OE : NO K
7063 20:12:01.329056 All Pass.
7064 20:12:01.329127
7065 20:12:01.332222 CH 0, Rank 1
7066 20:12:01.332324 SW Impedance : PASS
7067 20:12:01.335496 DUTY Scan : NO K
7068 20:12:01.338780 ZQ Calibration : PASS
7069 20:12:01.338862 Jitter Meter : NO K
7070 20:12:01.342031 CBT Training : PASS
7071 20:12:01.342112 Write leveling : NO K
7072 20:12:01.345431 RX DQS gating : PASS
7073 20:12:01.348738 RX DQ/DQS(RDDQC) : PASS
7074 20:12:01.348820 TX DQ/DQS : PASS
7075 20:12:01.352211 RX DATLAT : PASS
7076 20:12:01.355795 RX DQ/DQS(Engine): PASS
7077 20:12:01.355909 TX OE : NO K
7078 20:12:01.358812 All Pass.
7079 20:12:01.358910
7080 20:12:01.358999 CH 1, Rank 0
7081 20:12:01.362346 SW Impedance : PASS
7082 20:12:01.362467 DUTY Scan : NO K
7083 20:12:01.365650 ZQ Calibration : PASS
7084 20:12:01.368733 Jitter Meter : NO K
7085 20:12:01.368821 CBT Training : PASS
7086 20:12:01.371914 Write leveling : PASS
7087 20:12:01.375714 RX DQS gating : PASS
7088 20:12:01.375846 RX DQ/DQS(RDDQC) : PASS
7089 20:12:01.378865 TX DQ/DQS : PASS
7090 20:12:01.378947 RX DATLAT : PASS
7091 20:12:01.382222 RX DQ/DQS(Engine): PASS
7092 20:12:01.385581 TX OE : NO K
7093 20:12:01.385663 All Pass.
7094 20:12:01.385727
7095 20:12:01.385786 CH 1, Rank 1
7096 20:12:01.388834 SW Impedance : PASS
7097 20:12:01.392198 DUTY Scan : NO K
7098 20:12:01.392305 ZQ Calibration : PASS
7099 20:12:01.395724 Jitter Meter : NO K
7100 20:12:01.398554 CBT Training : PASS
7101 20:12:01.398637 Write leveling : NO K
7102 20:12:01.402307 RX DQS gating : PASS
7103 20:12:01.405536 RX DQ/DQS(RDDQC) : PASS
7104 20:12:01.405618 TX DQ/DQS : PASS
7105 20:12:01.408740 RX DATLAT : PASS
7106 20:12:01.412400 RX DQ/DQS(Engine): PASS
7107 20:12:01.412482 TX OE : NO K
7108 20:12:01.415497 All Pass.
7109 20:12:01.415579
7110 20:12:01.415643 DramC Write-DBI off
7111 20:12:01.418699 PER_BANK_REFRESH: Hybrid Mode
7112 20:12:01.418782 TX_TRACKING: ON
7113 20:12:01.428764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 20:12:01.432289 [FAST_K] Save calibration result to emmc
7115 20:12:01.435861 dramc_set_vcore_voltage set vcore to 725000
7116 20:12:01.438675 Read voltage for 1600, 0
7117 20:12:01.438757 Vio18 = 0
7118 20:12:01.442218 Vcore = 725000
7119 20:12:01.442299 Vdram = 0
7120 20:12:01.442363 Vddq = 0
7121 20:12:01.442469 Vmddr = 0
7122 20:12:01.449094 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 20:12:01.455782 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 20:12:01.455863 MEM_TYPE=3, freq_sel=13
7125 20:12:01.459072 sv_algorithm_assistance_LP4_3733
7126 20:12:01.462674 ============ PULL DRAM RESETB DOWN ============
7127 20:12:01.468981 ========== PULL DRAM RESETB DOWN end =========
7128 20:12:01.472086 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 20:12:01.475730 ===================================
7130 20:12:01.478924 LPDDR4 DRAM CONFIGURATION
7131 20:12:01.482079 ===================================
7132 20:12:01.482161 EX_ROW_EN[0] = 0x0
7133 20:12:01.485847 EX_ROW_EN[1] = 0x0
7134 20:12:01.485929 LP4Y_EN = 0x0
7135 20:12:01.489096 WORK_FSP = 0x1
7136 20:12:01.489179 WL = 0x5
7137 20:12:01.492266 RL = 0x5
7138 20:12:01.492348 BL = 0x2
7139 20:12:01.495831 RPST = 0x0
7140 20:12:01.495913 RD_PRE = 0x0
7141 20:12:01.498634 WR_PRE = 0x1
7142 20:12:01.502663 WR_PST = 0x1
7143 20:12:01.502745 DBI_WR = 0x0
7144 20:12:01.505512 DBI_RD = 0x0
7145 20:12:01.505594 OTF = 0x1
7146 20:12:01.509336 ===================================
7147 20:12:01.512468 ===================================
7148 20:12:01.512551 ANA top config
7149 20:12:01.515487 ===================================
7150 20:12:01.519024 DLL_ASYNC_EN = 0
7151 20:12:01.522251 ALL_SLAVE_EN = 0
7152 20:12:01.526213 NEW_RANK_MODE = 1
7153 20:12:01.529014 DLL_IDLE_MODE = 1
7154 20:12:01.529096 LP45_APHY_COMB_EN = 1
7155 20:12:01.532356 TX_ODT_DIS = 0
7156 20:12:01.535627 NEW_8X_MODE = 1
7157 20:12:01.538852 ===================================
7158 20:12:01.542170 ===================================
7159 20:12:01.545586 data_rate = 3200
7160 20:12:01.548775 CKR = 1
7161 20:12:01.548858 DQ_P2S_RATIO = 8
7162 20:12:01.552686 ===================================
7163 20:12:01.556003 CA_P2S_RATIO = 8
7164 20:12:01.559166 DQ_CA_OPEN = 0
7165 20:12:01.562444 DQ_SEMI_OPEN = 0
7166 20:12:01.565344 CA_SEMI_OPEN = 0
7167 20:12:01.565426 CA_FULL_RATE = 0
7168 20:12:01.568836 DQ_CKDIV4_EN = 0
7169 20:12:01.572532 CA_CKDIV4_EN = 0
7170 20:12:01.575996 CA_PREDIV_EN = 0
7171 20:12:01.579142 PH8_DLY = 12
7172 20:12:01.582174 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 20:12:01.582256 DQ_AAMCK_DIV = 4
7174 20:12:01.585640 CA_AAMCK_DIV = 4
7175 20:12:01.589083 CA_ADMCK_DIV = 4
7176 20:12:01.592642 DQ_TRACK_CA_EN = 0
7177 20:12:01.595886 CA_PICK = 1600
7178 20:12:01.599119 CA_MCKIO = 1600
7179 20:12:01.602550 MCKIO_SEMI = 0
7180 20:12:01.602632 PLL_FREQ = 3068
7181 20:12:01.605875 DQ_UI_PI_RATIO = 32
7182 20:12:01.608827 CA_UI_PI_RATIO = 0
7183 20:12:01.612282 ===================================
7184 20:12:01.615861 ===================================
7185 20:12:01.618784 memory_type:LPDDR4
7186 20:12:01.622440 GP_NUM : 10
7187 20:12:01.622562 SRAM_EN : 1
7188 20:12:01.625530 MD32_EN : 0
7189 20:12:01.628992 ===================================
7190 20:12:01.629074 [ANA_INIT] >>>>>>>>>>>>>>
7191 20:12:01.632816 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 20:12:01.635650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 20:12:01.639157 ===================================
7194 20:12:01.642956 data_rate = 3200,PCW = 0X7600
7195 20:12:01.645758 ===================================
7196 20:12:01.648727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 20:12:01.655602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 20:12:01.659315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 20:12:01.666157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 20:12:01.669215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 20:12:01.672511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 20:12:01.672598 [ANA_INIT] flow start
7203 20:12:01.675662 [ANA_INIT] PLL >>>>>>>>
7204 20:12:01.678936 [ANA_INIT] PLL <<<<<<<<
7205 20:12:01.682566 [ANA_INIT] MIDPI >>>>>>>>
7206 20:12:01.682648 [ANA_INIT] MIDPI <<<<<<<<
7207 20:12:01.685615 [ANA_INIT] DLL >>>>>>>>
7208 20:12:01.688988 [ANA_INIT] DLL <<<<<<<<
7209 20:12:01.689070 [ANA_INIT] flow end
7210 20:12:01.692537 ============ LP4 DIFF to SE enter ============
7211 20:12:01.699488 ============ LP4 DIFF to SE exit ============
7212 20:12:01.699571 [ANA_INIT] <<<<<<<<<<<<<
7213 20:12:01.702546 [Flow] Enable top DCM control >>>>>
7214 20:12:01.705934 [Flow] Enable top DCM control <<<<<
7215 20:12:01.709066 Enable DLL master slave shuffle
7216 20:12:01.715539 ==============================================================
7217 20:12:01.715621 Gating Mode config
7218 20:12:01.722512 ==============================================================
7219 20:12:01.725822 Config description:
7220 20:12:01.735754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 20:12:01.739018 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 20:12:01.745780 SELPH_MODE 0: By rank 1: By Phase
7223 20:12:01.752337 ==============================================================
7224 20:12:01.755780 GAT_TRACK_EN = 1
7225 20:12:01.755862 RX_GATING_MODE = 2
7226 20:12:01.758788 RX_GATING_TRACK_MODE = 2
7227 20:12:01.762200 SELPH_MODE = 1
7228 20:12:01.766000 PICG_EARLY_EN = 1
7229 20:12:01.769677 VALID_LAT_VALUE = 1
7230 20:12:01.775234 ==============================================================
7231 20:12:01.779168 Enter into Gating configuration >>>>
7232 20:12:01.782421 Exit from Gating configuration <<<<
7233 20:12:01.785641 Enter into DVFS_PRE_config >>>>>
7234 20:12:01.795683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 20:12:01.798831 Exit from DVFS_PRE_config <<<<<
7236 20:12:01.802429 Enter into PICG configuration >>>>
7237 20:12:01.805388 Exit from PICG configuration <<<<
7238 20:12:01.808412 [RX_INPUT] configuration >>>>>
7239 20:12:01.811805 [RX_INPUT] configuration <<<<<
7240 20:12:01.815082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 20:12:01.822021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 20:12:01.828360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 20:12:01.832249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 20:12:01.838776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 20:12:01.845119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 20:12:01.848616 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 20:12:01.851922 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 20:12:01.858585 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 20:12:01.861910 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 20:12:01.865491 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 20:12:01.872187 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 20:12:01.875372 ===================================
7253 20:12:01.875455 LPDDR4 DRAM CONFIGURATION
7254 20:12:01.879081 ===================================
7255 20:12:01.881910 EX_ROW_EN[0] = 0x0
7256 20:12:01.881991 EX_ROW_EN[1] = 0x0
7257 20:12:01.885415 LP4Y_EN = 0x0
7258 20:12:01.885497 WORK_FSP = 0x1
7259 20:12:01.889054 WL = 0x5
7260 20:12:01.889135 RL = 0x5
7261 20:12:01.892200 BL = 0x2
7262 20:12:01.895947 RPST = 0x0
7263 20:12:01.896030 RD_PRE = 0x0
7264 20:12:01.898708 WR_PRE = 0x1
7265 20:12:01.898793 WR_PST = 0x1
7266 20:12:01.902336 DBI_WR = 0x0
7267 20:12:01.902455 DBI_RD = 0x0
7268 20:12:01.905866 OTF = 0x1
7269 20:12:01.908701 ===================================
7270 20:12:01.912316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 20:12:01.915146 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 20:12:01.918848 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 20:12:01.922360 ===================================
7274 20:12:01.925202 LPDDR4 DRAM CONFIGURATION
7275 20:12:01.929482 ===================================
7276 20:12:01.931872 EX_ROW_EN[0] = 0x10
7277 20:12:01.931953 EX_ROW_EN[1] = 0x0
7278 20:12:01.935485 LP4Y_EN = 0x0
7279 20:12:01.935567 WORK_FSP = 0x1
7280 20:12:01.938660 WL = 0x5
7281 20:12:01.938743 RL = 0x5
7282 20:12:01.941751 BL = 0x2
7283 20:12:01.941833 RPST = 0x0
7284 20:12:01.945099 RD_PRE = 0x0
7285 20:12:01.945180 WR_PRE = 0x1
7286 20:12:01.948362 WR_PST = 0x1
7287 20:12:01.951817 DBI_WR = 0x0
7288 20:12:01.951899 DBI_RD = 0x0
7289 20:12:01.955304 OTF = 0x1
7290 20:12:01.958521 ===================================
7291 20:12:01.961966 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 20:12:01.962066 ==
7293 20:12:01.965751 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 20:12:01.972095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 20:12:01.972177 ==
7296 20:12:01.972243 [Duty_Offset_Calibration]
7297 20:12:01.975623 B0:2 B1:-1 CA:1
7298 20:12:01.975704
7299 20:12:01.978616 [DutyScan_Calibration_Flow] k_type=0
7300 20:12:01.987577
7301 20:12:01.987658 ==CLK 0==
7302 20:12:01.990835 Final CLK duty delay cell = -4
7303 20:12:01.993621 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7304 20:12:01.997579 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7305 20:12:02.000412 [-4] AVG Duty = 4937%(X100)
7306 20:12:02.000497
7307 20:12:02.003841 CH0 CLK Duty spec in!! Max-Min= 187%
7308 20:12:02.007358 [DutyScan_Calibration_Flow] ====Done====
7309 20:12:02.007440
7310 20:12:02.010271 [DutyScan_Calibration_Flow] k_type=1
7311 20:12:02.026929
7312 20:12:02.027020 ==DQS 0 ==
7313 20:12:02.030714 Final DQS duty delay cell = 0
7314 20:12:02.033561 [0] MAX Duty = 5093%(X100), DQS PI = 18
7315 20:12:02.036819 [0] MIN Duty = 5031%(X100), DQS PI = 12
7316 20:12:02.036901 [0] AVG Duty = 5062%(X100)
7317 20:12:02.040240
7318 20:12:02.040322 ==DQS 1 ==
7319 20:12:02.043409 Final DQS duty delay cell = -4
7320 20:12:02.047198 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7321 20:12:02.050221 [-4] MIN Duty = 5031%(X100), DQS PI = 20
7322 20:12:02.053751 [-4] AVG Duty = 5062%(X100)
7323 20:12:02.053833
7324 20:12:02.057000 CH0 DQS 0 Duty spec in!! Max-Min= 62%
7325 20:12:02.057082
7326 20:12:02.060106 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7327 20:12:02.063742 [DutyScan_Calibration_Flow] ====Done====
7328 20:12:02.063824
7329 20:12:02.067220 [DutyScan_Calibration_Flow] k_type=3
7330 20:12:02.083996
7331 20:12:02.084078 ==DQM 0 ==
7332 20:12:02.087294 Final DQM duty delay cell = 0
7333 20:12:02.091238 [0] MAX Duty = 5000%(X100), DQS PI = 18
7334 20:12:02.094301 [0] MIN Duty = 4875%(X100), DQS PI = 4
7335 20:12:02.094383 [0] AVG Duty = 4937%(X100)
7336 20:12:02.097959
7337 20:12:02.098040 ==DQM 1 ==
7338 20:12:02.101078 Final DQM duty delay cell = 0
7339 20:12:02.104389 [0] MAX Duty = 5218%(X100), DQS PI = 58
7340 20:12:02.108002 [0] MIN Duty = 4969%(X100), DQS PI = 18
7341 20:12:02.108085 [0] AVG Duty = 5093%(X100)
7342 20:12:02.111526
7343 20:12:02.114169 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7344 20:12:02.114250
7345 20:12:02.117894 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7346 20:12:02.121145 [DutyScan_Calibration_Flow] ====Done====
7347 20:12:02.121226
7348 20:12:02.124282 [DutyScan_Calibration_Flow] k_type=2
7349 20:12:02.140554
7350 20:12:02.140636 ==DQ 0 ==
7351 20:12:02.144095 Final DQ duty delay cell = -4
7352 20:12:02.147046 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7353 20:12:02.150843 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7354 20:12:02.153996 [-4] AVG Duty = 4937%(X100)
7355 20:12:02.154080
7356 20:12:02.154144 ==DQ 1 ==
7357 20:12:02.157307 Final DQ duty delay cell = 0
7358 20:12:02.160989 [0] MAX Duty = 5031%(X100), DQS PI = 30
7359 20:12:02.164096 [0] MIN Duty = 4907%(X100), DQS PI = 42
7360 20:12:02.164179 [0] AVG Duty = 4969%(X100)
7361 20:12:02.167204
7362 20:12:02.170722 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7363 20:12:02.170803
7364 20:12:02.174157 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7365 20:12:02.178015 [DutyScan_Calibration_Flow] ====Done====
7366 20:12:02.178097 ==
7367 20:12:02.180809 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 20:12:02.183940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 20:12:02.184021 ==
7370 20:12:02.187289 [Duty_Offset_Calibration]
7371 20:12:02.187370 B0:1 B1:1 CA:2
7372 20:12:02.187434
7373 20:12:02.190960 [DutyScan_Calibration_Flow] k_type=0
7374 20:12:02.200955
7375 20:12:02.201065 ==CLK 0==
7376 20:12:02.204592 Final CLK duty delay cell = 0
7377 20:12:02.207929 [0] MAX Duty = 5125%(X100), DQS PI = 48
7378 20:12:02.211428 [0] MIN Duty = 4938%(X100), DQS PI = 10
7379 20:12:02.211510 [0] AVG Duty = 5031%(X100)
7380 20:12:02.214558
7381 20:12:02.217955 CH1 CLK Duty spec in!! Max-Min= 187%
7382 20:12:02.221040 [DutyScan_Calibration_Flow] ====Done====
7383 20:12:02.221120
7384 20:12:02.224532 [DutyScan_Calibration_Flow] k_type=1
7385 20:12:02.240920
7386 20:12:02.241001 ==DQS 0 ==
7387 20:12:02.244710 Final DQS duty delay cell = 0
7388 20:12:02.247479 [0] MAX Duty = 5000%(X100), DQS PI = 52
7389 20:12:02.251016 [0] MIN Duty = 4844%(X100), DQS PI = 20
7390 20:12:02.254160 [0] AVG Duty = 4922%(X100)
7391 20:12:02.254241
7392 20:12:02.254304 ==DQS 1 ==
7393 20:12:02.257735 Final DQS duty delay cell = 0
7394 20:12:02.261376 [0] MAX Duty = 5062%(X100), DQS PI = 18
7395 20:12:02.264341 [0] MIN Duty = 4907%(X100), DQS PI = 46
7396 20:12:02.264422 [0] AVG Duty = 4984%(X100)
7397 20:12:02.268389
7398 20:12:02.271099 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7399 20:12:02.271180
7400 20:12:02.274585 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7401 20:12:02.277626 [DutyScan_Calibration_Flow] ====Done====
7402 20:12:02.277706
7403 20:12:02.280867 [DutyScan_Calibration_Flow] k_type=3
7404 20:12:02.298222
7405 20:12:02.298302 ==DQM 0 ==
7406 20:12:02.301509 Final DQM duty delay cell = 0
7407 20:12:02.305423 [0] MAX Duty = 5124%(X100), DQS PI = 52
7408 20:12:02.307904 [0] MIN Duty = 4876%(X100), DQS PI = 18
7409 20:12:02.311108 [0] AVG Duty = 5000%(X100)
7410 20:12:02.311189
7411 20:12:02.311252 ==DQM 1 ==
7412 20:12:02.314343 Final DQM duty delay cell = 0
7413 20:12:02.317817 [0] MAX Duty = 5156%(X100), DQS PI = 24
7414 20:12:02.322084 [0] MIN Duty = 4875%(X100), DQS PI = 50
7415 20:12:02.325251 [0] AVG Duty = 5015%(X100)
7416 20:12:02.325347
7417 20:12:02.328125 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7418 20:12:02.328206
7419 20:12:02.331714 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7420 20:12:02.334445 [DutyScan_Calibration_Flow] ====Done====
7421 20:12:02.334529
7422 20:12:02.338351 [DutyScan_Calibration_Flow] k_type=2
7423 20:12:02.354430
7424 20:12:02.354510 ==DQ 0 ==
7425 20:12:02.357527 Final DQ duty delay cell = 0
7426 20:12:02.361069 [0] MAX Duty = 5093%(X100), DQS PI = 52
7427 20:12:02.363747 [0] MIN Duty = 4969%(X100), DQS PI = 0
7428 20:12:02.363827 [0] AVG Duty = 5031%(X100)
7429 20:12:02.363891
7430 20:12:02.367180 ==DQ 1 ==
7431 20:12:02.370580 Final DQ duty delay cell = -4
7432 20:12:02.374182 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7433 20:12:02.377568 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7434 20:12:02.377654 [-4] AVG Duty = 4938%(X100)
7435 20:12:02.381043
7436 20:12:02.383819 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7437 20:12:02.383899
7438 20:12:02.387475 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7439 20:12:02.390515 [DutyScan_Calibration_Flow] ====Done====
7440 20:12:02.394213 nWR fixed to 30
7441 20:12:02.394294 [ModeRegInit_LP4] CH0 RK0
7442 20:12:02.397511 [ModeRegInit_LP4] CH0 RK1
7443 20:12:02.400617 [ModeRegInit_LP4] CH1 RK0
7444 20:12:02.400698 [ModeRegInit_LP4] CH1 RK1
7445 20:12:02.403983 match AC timing 5
7446 20:12:02.407424 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 20:12:02.410736 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 20:12:02.417527 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 20:12:02.420596 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 20:12:02.427751 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 20:12:02.427832 [MiockJmeterHQA]
7452 20:12:02.427896
7453 20:12:02.431436 [DramcMiockJmeter] u1RxGatingPI = 0
7454 20:12:02.434252 0 : 4262, 4031
7455 20:12:02.434364 4 : 4366, 4140
7456 20:12:02.434467 8 : 4254, 4029
7457 20:12:02.437638 12 : 4363, 4137
7458 20:12:02.437752 16 : 4363, 4137
7459 20:12:02.441278 20 : 4253, 4027
7460 20:12:02.441361 24 : 4253, 4026
7461 20:12:02.444018 28 : 4252, 4027
7462 20:12:02.444170 32 : 4363, 4137
7463 20:12:02.444284 36 : 4363, 4137
7464 20:12:02.447486 40 : 4252, 4027
7465 20:12:02.447620 44 : 4252, 4026
7466 20:12:02.450762 48 : 4252, 4027
7467 20:12:02.450885 52 : 4252, 4027
7468 20:12:02.454162 56 : 4255, 4029
7469 20:12:02.454284 60 : 4363, 4137
7470 20:12:02.457216 64 : 4252, 4026
7471 20:12:02.457339 68 : 4250, 4027
7472 20:12:02.457464 72 : 4250, 4027
7473 20:12:02.460647 76 : 4253, 4029
7474 20:12:02.460770 80 : 4250, 4027
7475 20:12:02.464208 84 : 4361, 4137
7476 20:12:02.464332 88 : 4361, 4137
7477 20:12:02.467262 92 : 4250, 4027
7478 20:12:02.467384 96 : 4250, 3430
7479 20:12:02.467497 100 : 4250, 0
7480 20:12:02.470704 104 : 4362, 0
7481 20:12:02.470826 108 : 4252, 0
7482 20:12:02.473984 112 : 4252, 0
7483 20:12:02.474104 116 : 4252, 0
7484 20:12:02.474217 120 : 4250, 0
7485 20:12:02.477366 124 : 4252, 0
7486 20:12:02.477486 128 : 4250, 0
7487 20:12:02.481120 132 : 4252, 0
7488 20:12:02.481241 136 : 4363, 0
7489 20:12:02.481355 140 : 4250, 0
7490 20:12:02.484325 144 : 4250, 0
7491 20:12:02.484445 148 : 4253, 0
7492 20:12:02.484557 152 : 4361, 0
7493 20:12:02.487663 156 : 4361, 0
7494 20:12:02.487807 160 : 4253, 0
7495 20:12:02.491009 164 : 4250, 0
7496 20:12:02.491132 168 : 4250, 0
7497 20:12:02.491242 172 : 4252, 0
7498 20:12:02.494490 176 : 4361, 0
7499 20:12:02.494611 180 : 4250, 0
7500 20:12:02.497951 184 : 4250, 0
7501 20:12:02.498072 188 : 4360, 0
7502 20:12:02.498184 192 : 4250, 0
7503 20:12:02.501049 196 : 4249, 0
7504 20:12:02.501170 200 : 4252, 0
7505 20:12:02.504437 204 : 4361, 0
7506 20:12:02.504542 208 : 4361, 0
7507 20:12:02.504635 212 : 4250, 161
7508 20:12:02.507854 216 : 4250, 3816
7509 20:12:02.507953 220 : 4253, 4029
7510 20:12:02.511323 224 : 4250, 4026
7511 20:12:02.511404 228 : 4361, 4137
7512 20:12:02.514247 232 : 4250, 4026
7513 20:12:02.514356 236 : 4250, 4027
7514 20:12:02.517885 240 : 4360, 4138
7515 20:12:02.517966 244 : 4249, 4027
7516 20:12:02.520987 248 : 4250, 4027
7517 20:12:02.521116 252 : 4363, 4139
7518 20:12:02.521233 256 : 4250, 4027
7519 20:12:02.524171 260 : 4249, 4027
7520 20:12:02.524296 264 : 4250, 4026
7521 20:12:02.527411 268 : 4253, 4029
7522 20:12:02.527535 272 : 4250, 4027
7523 20:12:02.530841 276 : 4249, 4027
7524 20:12:02.530967 280 : 4360, 4137
7525 20:12:02.534216 284 : 4250, 4026
7526 20:12:02.534341 288 : 4250, 4027
7527 20:12:02.538233 292 : 4360, 4138
7528 20:12:02.538355 296 : 4250, 4027
7529 20:12:02.541342 300 : 4250, 4026
7530 20:12:02.541447 304 : 4363, 4140
7531 20:12:02.541542 308 : 4250, 4027
7532 20:12:02.544753 312 : 4250, 4027
7533 20:12:02.544852 316 : 4250, 4027
7534 20:12:02.548040 320 : 4253, 4029
7535 20:12:02.548123 324 : 4250, 4027
7536 20:12:02.551036 328 : 4250, 4027
7537 20:12:02.551120 332 : 4361, 3225
7538 20:12:02.554127 336 : 4250, 38
7539 20:12:02.554237
7540 20:12:02.554329 MIOCK jitter meter ch=0
7541 20:12:02.554458
7542 20:12:02.557674 1T = (336-100) = 236 dly cells
7543 20:12:02.563995 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7544 20:12:02.564079 ==
7545 20:12:02.567463 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 20:12:02.571150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 20:12:02.571259 ==
7548 20:12:02.577666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 20:12:02.580730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 20:12:02.587821 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 20:12:02.590788 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 20:12:02.600600 [CA 0] Center 44 (14~75) winsize 62
7553 20:12:02.604615 [CA 1] Center 43 (13~74) winsize 62
7554 20:12:02.607969 [CA 2] Center 39 (10~68) winsize 59
7555 20:12:02.610684 [CA 3] Center 39 (10~68) winsize 59
7556 20:12:02.614911 [CA 4] Center 37 (7~67) winsize 61
7557 20:12:02.617312 [CA 5] Center 37 (7~67) winsize 61
7558 20:12:02.617394
7559 20:12:02.621230 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7560 20:12:02.621312
7561 20:12:02.624148 [CATrainingPosCal] consider 1 rank data
7562 20:12:02.627295 u2DelayCellTimex100 = 275/100 ps
7563 20:12:02.630904 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7564 20:12:02.637310 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7565 20:12:02.640994 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7566 20:12:02.644754 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7567 20:12:02.647636 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7568 20:12:02.651027 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7569 20:12:02.651135
7570 20:12:02.654188 CA PerBit enable=1, Macro0, CA PI delay=37
7571 20:12:02.654271
7572 20:12:02.657571 [CBTSetCACLKResult] CA Dly = 37
7573 20:12:02.660732 CS Dly: 11 (0~42)
7574 20:12:02.664554 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 20:12:02.667834 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 20:12:02.667917 ==
7577 20:12:02.670743 Dram Type= 6, Freq= 0, CH_0, rank 1
7578 20:12:02.674400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 20:12:02.677590 ==
7580 20:12:02.681025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 20:12:02.684287 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 20:12:02.691033 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 20:12:02.694647 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 20:12:02.704368 [CA 0] Center 43 (13~74) winsize 62
7585 20:12:02.708269 [CA 1] Center 43 (13~74) winsize 62
7586 20:12:02.711338 [CA 2] Center 39 (10~69) winsize 60
7587 20:12:02.714472 [CA 3] Center 38 (9~68) winsize 60
7588 20:12:02.717973 [CA 4] Center 37 (7~67) winsize 61
7589 20:12:02.720923 [CA 5] Center 36 (6~67) winsize 62
7590 20:12:02.721005
7591 20:12:02.724721 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7592 20:12:02.724803
7593 20:12:02.727799 [CATrainingPosCal] consider 2 rank data
7594 20:12:02.731269 u2DelayCellTimex100 = 275/100 ps
7595 20:12:02.734797 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7596 20:12:02.741446 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7597 20:12:02.744670 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7598 20:12:02.748453 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7599 20:12:02.751409 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7600 20:12:02.754218 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7601 20:12:02.754300
7602 20:12:02.757845 CA PerBit enable=1, Macro0, CA PI delay=37
7603 20:12:02.757927
7604 20:12:02.761520 [CBTSetCACLKResult] CA Dly = 37
7605 20:12:02.764787 CS Dly: 12 (0~44)
7606 20:12:02.767987 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 20:12:02.771698 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 20:12:02.771806
7609 20:12:02.774518 ----->DramcWriteLeveling(PI) begin...
7610 20:12:02.774601 ==
7611 20:12:02.777987 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 20:12:02.784190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 20:12:02.784272 ==
7614 20:12:02.787957 Write leveling (Byte 0): 34 => 34
7615 20:12:02.788039 Write leveling (Byte 1): 28 => 28
7616 20:12:02.791177 DramcWriteLeveling(PI) end<-----
7617 20:12:02.791259
7618 20:12:02.794435 ==
7619 20:12:02.794532 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 20:12:02.800911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 20:12:02.800994 ==
7622 20:12:02.804316 [Gating] SW mode calibration
7623 20:12:02.811255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7624 20:12:02.814368 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7625 20:12:02.821144 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 20:12:02.824383 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 20:12:02.827981 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 20:12:02.834627 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 20:12:02.838152 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7630 20:12:02.840933 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7631 20:12:02.844377 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 20:12:02.850914 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 20:12:02.855413 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 20:12:02.857611 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 20:12:02.864700 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 20:12:02.867667 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 20:12:02.870866 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7638 20:12:02.877846 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7639 20:12:02.881310 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7640 20:12:02.884743 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7641 20:12:02.890870 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 20:12:02.894616 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 20:12:02.897916 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 20:12:02.904042 1 6 12 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7645 20:12:02.907648 1 6 16 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7646 20:12:02.911448 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (1 1) (0 0)
7647 20:12:02.917763 1 6 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7648 20:12:02.921601 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 20:12:02.924559 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 20:12:02.931055 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 20:12:02.934350 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 20:12:02.937961 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 20:12:02.944410 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 20:12:02.947573 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7655 20:12:02.950940 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 20:12:02.954432 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 20:12:02.960822 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 20:12:02.964465 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 20:12:02.967454 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 20:12:02.974739 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 20:12:02.977618 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 20:12:02.980691 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 20:12:02.987365 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 20:12:02.990793 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 20:12:02.994079 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 20:12:03.000613 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 20:12:03.004506 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 20:12:03.007325 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7669 20:12:03.013758 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7670 20:12:03.017347 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7671 20:12:03.020806 Total UI for P1: 0, mck2ui 16
7672 20:12:03.023918 best dqsien dly found for B0: ( 1, 9, 14)
7673 20:12:03.027657 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 20:12:03.033942 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 20:12:03.034067 Total UI for P1: 0, mck2ui 16
7676 20:12:03.040481 best dqsien dly found for B1: ( 1, 9, 20)
7677 20:12:03.043755 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7678 20:12:03.047029 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7679 20:12:03.047152
7680 20:12:03.051154 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7681 20:12:03.053810 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7682 20:12:03.057721 [Gating] SW calibration Done
7683 20:12:03.057847 ==
7684 20:12:03.060419 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 20:12:03.063734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 20:12:03.063857 ==
7687 20:12:03.067420 RX Vref Scan: 0
7688 20:12:03.067544
7689 20:12:03.067654 RX Vref 0 -> 0, step: 1
7690 20:12:03.067766
7691 20:12:03.070621 RX Delay 0 -> 252, step: 8
7692 20:12:03.074196 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7693 20:12:03.080961 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7694 20:12:03.083749 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7695 20:12:03.087565 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7696 20:12:03.090701 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7697 20:12:03.093926 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7698 20:12:03.097210 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7699 20:12:03.104181 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7700 20:12:03.107843 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7701 20:12:03.111024 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7702 20:12:03.113873 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7703 20:12:03.117274 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7704 20:12:03.124528 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7705 20:12:03.127789 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7706 20:12:03.130690 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7707 20:12:03.134218 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7708 20:12:03.134340 ==
7709 20:12:03.137361 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 20:12:03.143652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 20:12:03.143737 ==
7712 20:12:03.143802 DQS Delay:
7713 20:12:03.146939 DQS0 = 0, DQS1 = 0
7714 20:12:03.147021 DQM Delay:
7715 20:12:03.150391 DQM0 = 132, DQM1 = 123
7716 20:12:03.150514 DQ Delay:
7717 20:12:03.153919 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7718 20:12:03.156820 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7719 20:12:03.160493 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7720 20:12:03.163945 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7721 20:12:03.164068
7722 20:12:03.164181
7723 20:12:03.164291 ==
7724 20:12:03.166750 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 20:12:03.173959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 20:12:03.174084 ==
7727 20:12:03.174197
7728 20:12:03.174305
7729 20:12:03.174421 TX Vref Scan disable
7730 20:12:03.177774 == TX Byte 0 ==
7731 20:12:03.180557 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7732 20:12:03.184004 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7733 20:12:03.186992 == TX Byte 1 ==
7734 20:12:03.190727 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7735 20:12:03.194010 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7736 20:12:03.197190 ==
7737 20:12:03.200758 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 20:12:03.203833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 20:12:03.203937 ==
7740 20:12:03.217366
7741 20:12:03.220853 TX Vref early break, caculate TX vref
7742 20:12:03.224168 TX Vref=16, minBit 1, minWin=21, winSum=360
7743 20:12:03.228435 TX Vref=18, minBit 7, minWin=22, winSum=372
7744 20:12:03.231444 TX Vref=20, minBit 7, minWin=22, winSum=380
7745 20:12:03.234263 TX Vref=22, minBit 0, minWin=24, winSum=394
7746 20:12:03.238021 TX Vref=24, minBit 1, minWin=24, winSum=401
7747 20:12:03.244660 TX Vref=26, minBit 4, minWin=24, winSum=410
7748 20:12:03.248054 TX Vref=28, minBit 3, minWin=25, winSum=419
7749 20:12:03.250936 TX Vref=30, minBit 4, minWin=24, winSum=417
7750 20:12:03.254320 TX Vref=32, minBit 4, minWin=24, winSum=416
7751 20:12:03.258029 TX Vref=34, minBit 0, minWin=24, winSum=400
7752 20:12:03.261358 TX Vref=36, minBit 4, minWin=23, winSum=389
7753 20:12:03.267611 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 28
7754 20:12:03.267734
7755 20:12:03.271030 Final TX Range 0 Vref 28
7756 20:12:03.271155
7757 20:12:03.271268 ==
7758 20:12:03.274314 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 20:12:03.277401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 20:12:03.277506 ==
7761 20:12:03.277617
7762 20:12:03.277728
7763 20:12:03.280595 TX Vref Scan disable
7764 20:12:03.287552 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7765 20:12:03.287675 == TX Byte 0 ==
7766 20:12:03.290774 u2DelayCellOfst[0]=10 cells (3 PI)
7767 20:12:03.294147 u2DelayCellOfst[1]=17 cells (5 PI)
7768 20:12:03.297644 u2DelayCellOfst[2]=10 cells (3 PI)
7769 20:12:03.300831 u2DelayCellOfst[3]=10 cells (3 PI)
7770 20:12:03.304311 u2DelayCellOfst[4]=7 cells (2 PI)
7771 20:12:03.307318 u2DelayCellOfst[5]=0 cells (0 PI)
7772 20:12:03.310992 u2DelayCellOfst[6]=17 cells (5 PI)
7773 20:12:03.313970 u2DelayCellOfst[7]=17 cells (5 PI)
7774 20:12:03.317995 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7775 20:12:03.321000 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7776 20:12:03.324310 == TX Byte 1 ==
7777 20:12:03.327667 u2DelayCellOfst[8]=0 cells (0 PI)
7778 20:12:03.327790 u2DelayCellOfst[9]=0 cells (0 PI)
7779 20:12:03.330857 u2DelayCellOfst[10]=7 cells (2 PI)
7780 20:12:03.333936 u2DelayCellOfst[11]=0 cells (0 PI)
7781 20:12:03.337298 u2DelayCellOfst[12]=14 cells (4 PI)
7782 20:12:03.341402 u2DelayCellOfst[13]=14 cells (4 PI)
7783 20:12:03.344138 u2DelayCellOfst[14]=14 cells (4 PI)
7784 20:12:03.347214 u2DelayCellOfst[15]=10 cells (3 PI)
7785 20:12:03.351054 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7786 20:12:03.357173 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7787 20:12:03.357299 DramC Write-DBI on
7788 20:12:03.357413 ==
7789 20:12:03.360841 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 20:12:03.367228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 20:12:03.367353 ==
7792 20:12:03.367465
7793 20:12:03.367575
7794 20:12:03.367683 TX Vref Scan disable
7795 20:12:03.371229 == TX Byte 0 ==
7796 20:12:03.374557 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7797 20:12:03.377755 == TX Byte 1 ==
7798 20:12:03.381511 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7799 20:12:03.384406 DramC Write-DBI off
7800 20:12:03.384527
7801 20:12:03.384639 [DATLAT]
7802 20:12:03.384748 Freq=1600, CH0 RK0
7803 20:12:03.384889
7804 20:12:03.387626 DATLAT Default: 0xf
7805 20:12:03.387746 0, 0xFFFF, sum = 0
7806 20:12:03.391314 1, 0xFFFF, sum = 0
7807 20:12:03.391440 2, 0xFFFF, sum = 0
7808 20:12:03.394526 3, 0xFFFF, sum = 0
7809 20:12:03.397643 4, 0xFFFF, sum = 0
7810 20:12:03.397767 5, 0xFFFF, sum = 0
7811 20:12:03.401177 6, 0xFFFF, sum = 0
7812 20:12:03.401300 7, 0xFFFF, sum = 0
7813 20:12:03.404380 8, 0xFFFF, sum = 0
7814 20:12:03.404504 9, 0xFFFF, sum = 0
7815 20:12:03.408186 10, 0xFFFF, sum = 0
7816 20:12:03.408311 11, 0xFFFF, sum = 0
7817 20:12:03.410938 12, 0xFFFF, sum = 0
7818 20:12:03.411064 13, 0xFFFF, sum = 0
7819 20:12:03.415206 14, 0x0, sum = 1
7820 20:12:03.415331 15, 0x0, sum = 2
7821 20:12:03.417754 16, 0x0, sum = 3
7822 20:12:03.417877 17, 0x0, sum = 4
7823 20:12:03.421064 best_step = 15
7824 20:12:03.421184
7825 20:12:03.421298 ==
7826 20:12:03.424593 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 20:12:03.427537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 20:12:03.427660 ==
7829 20:12:03.427773 RX Vref Scan: 1
7830 20:12:03.427881
7831 20:12:03.431309 Set Vref Range= 24 -> 127
7832 20:12:03.431430
7833 20:12:03.434764 RX Vref 24 -> 127, step: 1
7834 20:12:03.434885
7835 20:12:03.437816 RX Delay 11 -> 252, step: 4
7836 20:12:03.437940
7837 20:12:03.441452 Set Vref, RX VrefLevel [Byte0]: 24
7838 20:12:03.444817 [Byte1]: 24
7839 20:12:03.444940
7840 20:12:03.447867 Set Vref, RX VrefLevel [Byte0]: 25
7841 20:12:03.451116 [Byte1]: 25
7842 20:12:03.451237
7843 20:12:03.454638 Set Vref, RX VrefLevel [Byte0]: 26
7844 20:12:03.458019 [Byte1]: 26
7845 20:12:03.461312
7846 20:12:03.461435 Set Vref, RX VrefLevel [Byte0]: 27
7847 20:12:03.464645 [Byte1]: 27
7848 20:12:03.469460
7849 20:12:03.469581 Set Vref, RX VrefLevel [Byte0]: 28
7850 20:12:03.472580 [Byte1]: 28
7851 20:12:03.476880
7852 20:12:03.477001 Set Vref, RX VrefLevel [Byte0]: 29
7853 20:12:03.480267 [Byte1]: 29
7854 20:12:03.484433
7855 20:12:03.484555 Set Vref, RX VrefLevel [Byte0]: 30
7856 20:12:03.487752 [Byte1]: 30
7857 20:12:03.492213
7858 20:12:03.492332 Set Vref, RX VrefLevel [Byte0]: 31
7859 20:12:03.495214 [Byte1]: 31
7860 20:12:03.499903
7861 20:12:03.500027 Set Vref, RX VrefLevel [Byte0]: 32
7862 20:12:03.502656 [Byte1]: 32
7863 20:12:03.507062
7864 20:12:03.507182 Set Vref, RX VrefLevel [Byte0]: 33
7865 20:12:03.510863 [Byte1]: 33
7866 20:12:03.515222
7867 20:12:03.515349 Set Vref, RX VrefLevel [Byte0]: 34
7868 20:12:03.518217 [Byte1]: 34
7869 20:12:03.522615
7870 20:12:03.522739 Set Vref, RX VrefLevel [Byte0]: 35
7871 20:12:03.525560 [Byte1]: 35
7872 20:12:03.530725
7873 20:12:03.530848 Set Vref, RX VrefLevel [Byte0]: 36
7874 20:12:03.533277 [Byte1]: 36
7875 20:12:03.537852
7876 20:12:03.537975 Set Vref, RX VrefLevel [Byte0]: 37
7877 20:12:03.540716 [Byte1]: 37
7878 20:12:03.544976
7879 20:12:03.545098 Set Vref, RX VrefLevel [Byte0]: 38
7880 20:12:03.548489 [Byte1]: 38
7881 20:12:03.552591
7882 20:12:03.552714 Set Vref, RX VrefLevel [Byte0]: 39
7883 20:12:03.556296 [Byte1]: 39
7884 20:12:03.560386
7885 20:12:03.560508 Set Vref, RX VrefLevel [Byte0]: 40
7886 20:12:03.563829 [Byte1]: 40
7887 20:12:03.568558
7888 20:12:03.568681 Set Vref, RX VrefLevel [Byte0]: 41
7889 20:12:03.571806 [Byte1]: 41
7890 20:12:03.575694
7891 20:12:03.575777 Set Vref, RX VrefLevel [Byte0]: 42
7892 20:12:03.579039 [Byte1]: 42
7893 20:12:03.583329
7894 20:12:03.583410 Set Vref, RX VrefLevel [Byte0]: 43
7895 20:12:03.586594 [Byte1]: 43
7896 20:12:03.591021
7897 20:12:03.591102 Set Vref, RX VrefLevel [Byte0]: 44
7898 20:12:03.594759 [Byte1]: 44
7899 20:12:03.598377
7900 20:12:03.598488 Set Vref, RX VrefLevel [Byte0]: 45
7901 20:12:03.601914 [Byte1]: 45
7902 20:12:03.606048
7903 20:12:03.606130 Set Vref, RX VrefLevel [Byte0]: 46
7904 20:12:03.609510 [Byte1]: 46
7905 20:12:03.614015
7906 20:12:03.614097 Set Vref, RX VrefLevel [Byte0]: 47
7907 20:12:03.616920 [Byte1]: 47
7908 20:12:03.621775
7909 20:12:03.621857 Set Vref, RX VrefLevel [Byte0]: 48
7910 20:12:03.624944 [Byte1]: 48
7911 20:12:03.629106
7912 20:12:03.629188 Set Vref, RX VrefLevel [Byte0]: 49
7913 20:12:03.632304 [Byte1]: 49
7914 20:12:03.636495
7915 20:12:03.636576 Set Vref, RX VrefLevel [Byte0]: 50
7916 20:12:03.640267 [Byte1]: 50
7917 20:12:03.643987
7918 20:12:03.644069 Set Vref, RX VrefLevel [Byte0]: 51
7919 20:12:03.647579 [Byte1]: 51
7920 20:12:03.652228
7921 20:12:03.652310 Set Vref, RX VrefLevel [Byte0]: 52
7922 20:12:03.655323 [Byte1]: 52
7923 20:12:03.659874
7924 20:12:03.659956 Set Vref, RX VrefLevel [Byte0]: 53
7925 20:12:03.662781 [Byte1]: 53
7926 20:12:03.667554
7927 20:12:03.667635 Set Vref, RX VrefLevel [Byte0]: 54
7928 20:12:03.670425 [Byte1]: 54
7929 20:12:03.674897
7930 20:12:03.674978 Set Vref, RX VrefLevel [Byte0]: 55
7931 20:12:03.678377 [Byte1]: 55
7932 20:12:03.682348
7933 20:12:03.682468 Set Vref, RX VrefLevel [Byte0]: 56
7934 20:12:03.685558 [Byte1]: 56
7935 20:12:03.689942
7936 20:12:03.690024 Set Vref, RX VrefLevel [Byte0]: 57
7937 20:12:03.692952 [Byte1]: 57
7938 20:12:03.698126
7939 20:12:03.698207 Set Vref, RX VrefLevel [Byte0]: 58
7940 20:12:03.700947 [Byte1]: 58
7941 20:12:03.705067
7942 20:12:03.705173 Set Vref, RX VrefLevel [Byte0]: 59
7943 20:12:03.708489 [Byte1]: 59
7944 20:12:03.712838
7945 20:12:03.712920 Set Vref, RX VrefLevel [Byte0]: 60
7946 20:12:03.715849 [Byte1]: 60
7947 20:12:03.720339
7948 20:12:03.720421 Set Vref, RX VrefLevel [Byte0]: 61
7949 20:12:03.723444 [Byte1]: 61
7950 20:12:03.727849
7951 20:12:03.727932 Set Vref, RX VrefLevel [Byte0]: 62
7952 20:12:03.731259 [Byte1]: 62
7953 20:12:03.735747
7954 20:12:03.735828 Set Vref, RX VrefLevel [Byte0]: 63
7955 20:12:03.738945 [Byte1]: 63
7956 20:12:03.743086
7957 20:12:03.743167 Set Vref, RX VrefLevel [Byte0]: 64
7958 20:12:03.746483 [Byte1]: 64
7959 20:12:03.751093
7960 20:12:03.751174 Set Vref, RX VrefLevel [Byte0]: 65
7961 20:12:03.754016 [Byte1]: 65
7962 20:12:03.758199
7963 20:12:03.758305 Set Vref, RX VrefLevel [Byte0]: 66
7964 20:12:03.761993 [Byte1]: 66
7965 20:12:03.766205
7966 20:12:03.766287 Set Vref, RX VrefLevel [Byte0]: 67
7967 20:12:03.769642 [Byte1]: 67
7968 20:12:03.773760
7969 20:12:03.773842 Set Vref, RX VrefLevel [Byte0]: 68
7970 20:12:03.776871 [Byte1]: 68
7971 20:12:03.781510
7972 20:12:03.781591 Set Vref, RX VrefLevel [Byte0]: 69
7973 20:12:03.784787 [Byte1]: 69
7974 20:12:03.788629
7975 20:12:03.788711 Set Vref, RX VrefLevel [Byte0]: 70
7976 20:12:03.792398 [Byte1]: 70
7977 20:12:03.796845
7978 20:12:03.796926 Set Vref, RX VrefLevel [Byte0]: 71
7979 20:12:03.800416 [Byte1]: 71
7980 20:12:03.803972
7981 20:12:03.804054 Set Vref, RX VrefLevel [Byte0]: 72
7982 20:12:03.807431 [Byte1]: 72
7983 20:12:03.811652
7984 20:12:03.811733 Set Vref, RX VrefLevel [Byte0]: 73
7985 20:12:03.814850 [Byte1]: 73
7986 20:12:03.819563
7987 20:12:03.819645 Set Vref, RX VrefLevel [Byte0]: 74
7988 20:12:03.822708 [Byte1]: 74
7989 20:12:03.827154
7990 20:12:03.827235 Set Vref, RX VrefLevel [Byte0]: 75
7991 20:12:03.829986 [Byte1]: 75
7992 20:12:03.834671
7993 20:12:03.834752 Set Vref, RX VrefLevel [Byte0]: 76
7994 20:12:03.837904 [Byte1]: 76
7995 20:12:03.842171
7996 20:12:03.842254 Final RX Vref Byte 0 = 56 to rank0
7997 20:12:03.845811 Final RX Vref Byte 1 = 62 to rank0
7998 20:12:03.849138 Final RX Vref Byte 0 = 56 to rank1
7999 20:12:03.852145 Final RX Vref Byte 1 = 62 to rank1==
8000 20:12:03.855737 Dram Type= 6, Freq= 0, CH_0, rank 0
8001 20:12:03.862100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 20:12:03.862183 ==
8003 20:12:03.862249 DQS Delay:
8004 20:12:03.862309 DQS0 = 0, DQS1 = 0
8005 20:12:03.865446 DQM Delay:
8006 20:12:03.865528 DQM0 = 130, DQM1 = 121
8007 20:12:03.869118 DQ Delay:
8008 20:12:03.872280 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
8009 20:12:03.875411 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8010 20:12:03.879322 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
8011 20:12:03.882240 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
8012 20:12:03.882322
8013 20:12:03.882386
8014 20:12:03.882488
8015 20:12:03.885520 [DramC_TX_OE_Calibration] TA2
8016 20:12:03.888867 Original DQ_B0 (3 6) =30, OEN = 27
8017 20:12:03.892666 Original DQ_B1 (3 6) =30, OEN = 27
8018 20:12:03.895518 24, 0x0, End_B0=24 End_B1=24
8019 20:12:03.895602 25, 0x0, End_B0=25 End_B1=25
8020 20:12:03.899769 26, 0x0, End_B0=26 End_B1=26
8021 20:12:03.902171 27, 0x0, End_B0=27 End_B1=27
8022 20:12:03.906270 28, 0x0, End_B0=28 End_B1=28
8023 20:12:03.906353 29, 0x0, End_B0=29 End_B1=29
8024 20:12:03.908734 30, 0x0, End_B0=30 End_B1=30
8025 20:12:03.912363 31, 0x4141, End_B0=30 End_B1=30
8026 20:12:03.915944 Byte0 end_step=30 best_step=27
8027 20:12:03.918818 Byte1 end_step=30 best_step=27
8028 20:12:03.922009 Byte0 TX OE(2T, 0.5T) = (3, 3)
8029 20:12:03.922090 Byte1 TX OE(2T, 0.5T) = (3, 3)
8030 20:12:03.922154
8031 20:12:03.925455
8032 20:12:03.932382 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
8033 20:12:03.935455 CH0 RK0: MR19=303, MR18=1105
8034 20:12:03.942231 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
8035 20:12:03.942314
8036 20:12:03.945376 ----->DramcWriteLeveling(PI) begin...
8037 20:12:03.945460 ==
8038 20:12:03.948509 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 20:12:03.951876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 20:12:03.951958 ==
8041 20:12:03.955055 Write leveling (Byte 0): 34 => 34
8042 20:12:03.958738 Write leveling (Byte 1): 27 => 27
8043 20:12:03.961858 DramcWriteLeveling(PI) end<-----
8044 20:12:03.961940
8045 20:12:03.962003 ==
8046 20:12:03.965315 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 20:12:03.968283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 20:12:03.968365 ==
8049 20:12:03.971891 [Gating] SW mode calibration
8050 20:12:03.978368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8051 20:12:03.984838 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8052 20:12:03.988336 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 20:12:03.991897 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 20:12:03.998855 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 20:12:04.001643 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8056 20:12:04.005178 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8057 20:12:04.011298 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8058 20:12:04.014993 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 20:12:04.018531 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 20:12:04.024776 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 20:12:04.028664 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 20:12:04.031569 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8063 20:12:04.038246 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8064 20:12:04.041633 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8065 20:12:04.044670 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8066 20:12:04.051869 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 20:12:04.054963 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 20:12:04.058254 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 20:12:04.064580 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 20:12:04.068111 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8071 20:12:04.071250 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8072 20:12:04.077940 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8073 20:12:04.081203 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8074 20:12:04.084570 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 20:12:04.091265 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 20:12:04.094603 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 20:12:04.097867 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 20:12:04.101204 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8079 20:12:04.107995 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 20:12:04.110907 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 20:12:04.117769 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 20:12:04.120779 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 20:12:04.124483 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 20:12:04.127672 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 20:12:04.134356 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 20:12:04.138248 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 20:12:04.141264 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 20:12:04.147727 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 20:12:04.151010 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 20:12:04.154260 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 20:12:04.161487 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 20:12:04.164601 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 20:12:04.167749 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 20:12:04.174759 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 20:12:04.178228 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 20:12:04.181197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 20:12:04.184476 Total UI for P1: 0, mck2ui 16
8098 20:12:04.187602 best dqsien dly found for B0: ( 1, 9, 10)
8099 20:12:04.194327 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 20:12:04.197948 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 20:12:04.201293 Total UI for P1: 0, mck2ui 16
8102 20:12:04.204657 best dqsien dly found for B1: ( 1, 9, 18)
8103 20:12:04.207894 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8104 20:12:04.211324 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8105 20:12:04.211407
8106 20:12:04.214653 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8107 20:12:04.217652 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8108 20:12:04.221632 [Gating] SW calibration Done
8109 20:12:04.221749 ==
8110 20:12:04.224984 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 20:12:04.228054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 20:12:04.228169 ==
8113 20:12:04.230862 RX Vref Scan: 0
8114 20:12:04.230944
8115 20:12:04.234313 RX Vref 0 -> 0, step: 1
8116 20:12:04.234418
8117 20:12:04.234496 RX Delay 0 -> 252, step: 8
8118 20:12:04.241391 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8119 20:12:04.244583 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8120 20:12:04.248138 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8121 20:12:04.251100 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8122 20:12:04.254631 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8123 20:12:04.260914 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8124 20:12:04.264216 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8125 20:12:04.268003 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8126 20:12:04.271303 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8127 20:12:04.274498 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8128 20:12:04.277720 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8129 20:12:04.284601 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8130 20:12:04.287854 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8131 20:12:04.291208 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8132 20:12:04.294306 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8133 20:12:04.301185 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8134 20:12:04.301267 ==
8135 20:12:04.304269 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 20:12:04.307893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 20:12:04.308015 ==
8138 20:12:04.308128 DQS Delay:
8139 20:12:04.311300 DQS0 = 0, DQS1 = 0
8140 20:12:04.311423 DQM Delay:
8141 20:12:04.314478 DQM0 = 130, DQM1 = 125
8142 20:12:04.314600 DQ Delay:
8143 20:12:04.317899 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8144 20:12:04.320967 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8145 20:12:04.324636 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8146 20:12:04.327737 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8147 20:12:04.327860
8148 20:12:04.327970
8149 20:12:04.330929 ==
8150 20:12:04.331049 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 20:12:04.337971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 20:12:04.338095 ==
8153 20:12:04.338208
8154 20:12:04.338317
8155 20:12:04.338480 TX Vref Scan disable
8156 20:12:04.341565 == TX Byte 0 ==
8157 20:12:04.345005 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8158 20:12:04.351514 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8159 20:12:04.351638 == TX Byte 1 ==
8160 20:12:04.355054 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8161 20:12:04.358321 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8162 20:12:04.361472 ==
8163 20:12:04.365028 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 20:12:04.368107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 20:12:04.368230 ==
8166 20:12:04.382700
8167 20:12:04.385855 TX Vref early break, caculate TX vref
8168 20:12:04.388957 TX Vref=16, minBit 3, minWin=22, winSum=370
8169 20:12:04.392423 TX Vref=18, minBit 9, minWin=22, winSum=377
8170 20:12:04.395510 TX Vref=20, minBit 2, minWin=23, winSum=390
8171 20:12:04.399557 TX Vref=22, minBit 0, minWin=24, winSum=396
8172 20:12:04.402308 TX Vref=24, minBit 4, minWin=24, winSum=408
8173 20:12:04.409366 TX Vref=26, minBit 0, minWin=25, winSum=416
8174 20:12:04.413010 TX Vref=28, minBit 2, minWin=25, winSum=418
8175 20:12:04.415696 TX Vref=30, minBit 4, minWin=25, winSum=417
8176 20:12:04.419199 TX Vref=32, minBit 0, minWin=25, winSum=410
8177 20:12:04.422328 TX Vref=34, minBit 4, minWin=24, winSum=402
8178 20:12:04.425853 TX Vref=36, minBit 4, minWin=23, winSum=390
8179 20:12:04.432429 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 28
8180 20:12:04.432551
8181 20:12:04.436388 Final TX Range 0 Vref 28
8182 20:12:04.436509
8183 20:12:04.436622 ==
8184 20:12:04.439244 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 20:12:04.442389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 20:12:04.442546 ==
8187 20:12:04.442660
8188 20:12:04.442769
8189 20:12:04.445843 TX Vref Scan disable
8190 20:12:04.452395 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8191 20:12:04.452518 == TX Byte 0 ==
8192 20:12:04.455847 u2DelayCellOfst[0]=14 cells (4 PI)
8193 20:12:04.459115 u2DelayCellOfst[1]=17 cells (5 PI)
8194 20:12:04.462321 u2DelayCellOfst[2]=10 cells (3 PI)
8195 20:12:04.465739 u2DelayCellOfst[3]=10 cells (3 PI)
8196 20:12:04.469147 u2DelayCellOfst[4]=10 cells (3 PI)
8197 20:12:04.472388 u2DelayCellOfst[5]=0 cells (0 PI)
8198 20:12:04.475535 u2DelayCellOfst[6]=17 cells (5 PI)
8199 20:12:04.479174 u2DelayCellOfst[7]=17 cells (5 PI)
8200 20:12:04.482367 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8201 20:12:04.486304 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8202 20:12:04.489355 == TX Byte 1 ==
8203 20:12:04.492359 u2DelayCellOfst[8]=0 cells (0 PI)
8204 20:12:04.492480 u2DelayCellOfst[9]=0 cells (0 PI)
8205 20:12:04.495526 u2DelayCellOfst[10]=7 cells (2 PI)
8206 20:12:04.499078 u2DelayCellOfst[11]=0 cells (0 PI)
8207 20:12:04.502541 u2DelayCellOfst[12]=14 cells (4 PI)
8208 20:12:04.505600 u2DelayCellOfst[13]=10 cells (3 PI)
8209 20:12:04.508899 u2DelayCellOfst[14]=17 cells (5 PI)
8210 20:12:04.512363 u2DelayCellOfst[15]=10 cells (3 PI)
8211 20:12:04.515389 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8212 20:12:04.521998 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8213 20:12:04.522122 DramC Write-DBI on
8214 20:12:04.522284 ==
8215 20:12:04.525483 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 20:12:04.532388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 20:12:04.532510 ==
8218 20:12:04.532624
8219 20:12:04.532733
8220 20:12:04.532838 TX Vref Scan disable
8221 20:12:04.535803 == TX Byte 0 ==
8222 20:12:04.539910 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8223 20:12:04.542310 == TX Byte 1 ==
8224 20:12:04.546086 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8225 20:12:04.549169 DramC Write-DBI off
8226 20:12:04.549283
8227 20:12:04.549380 [DATLAT]
8228 20:12:04.549483 Freq=1600, CH0 RK1
8229 20:12:04.549582
8230 20:12:04.552901 DATLAT Default: 0xf
8231 20:12:04.553022 0, 0xFFFF, sum = 0
8232 20:12:04.556133 1, 0xFFFF, sum = 0
8233 20:12:04.556257 2, 0xFFFF, sum = 0
8234 20:12:04.559352 3, 0xFFFF, sum = 0
8235 20:12:04.563030 4, 0xFFFF, sum = 0
8236 20:12:04.563160 5, 0xFFFF, sum = 0
8237 20:12:04.565834 6, 0xFFFF, sum = 0
8238 20:12:04.565956 7, 0xFFFF, sum = 0
8239 20:12:04.569205 8, 0xFFFF, sum = 0
8240 20:12:04.569305 9, 0xFFFF, sum = 0
8241 20:12:04.572707 10, 0xFFFF, sum = 0
8242 20:12:04.572817 11, 0xFFFF, sum = 0
8243 20:12:04.575724 12, 0xFFFF, sum = 0
8244 20:12:04.575823 13, 0xFFFF, sum = 0
8245 20:12:04.579348 14, 0x0, sum = 1
8246 20:12:04.579431 15, 0x0, sum = 2
8247 20:12:04.582758 16, 0x0, sum = 3
8248 20:12:04.582841 17, 0x0, sum = 4
8249 20:12:04.586557 best_step = 15
8250 20:12:04.586638
8251 20:12:04.586717 ==
8252 20:12:04.589756 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 20:12:04.592786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 20:12:04.592869 ==
8255 20:12:04.592933 RX Vref Scan: 0
8256 20:12:04.592993
8257 20:12:04.596042 RX Vref 0 -> 0, step: 1
8258 20:12:04.596168
8259 20:12:04.599310 RX Delay 11 -> 252, step: 4
8260 20:12:04.602708 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8261 20:12:04.609218 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8262 20:12:04.612762 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8263 20:12:04.615900 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8264 20:12:04.619203 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8265 20:12:04.622388 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8266 20:12:04.626640 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8267 20:12:04.632740 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8268 20:12:04.636439 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8269 20:12:04.639434 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8270 20:12:04.643406 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8271 20:12:04.645993 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8272 20:12:04.652699 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8273 20:12:04.656531 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8274 20:12:04.659714 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8275 20:12:04.662641 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8276 20:12:04.662723 ==
8277 20:12:04.666755 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 20:12:04.672922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 20:12:04.673005 ==
8280 20:12:04.673069 DQS Delay:
8281 20:12:04.676758 DQS0 = 0, DQS1 = 0
8282 20:12:04.676839 DQM Delay:
8283 20:12:04.676903 DQM0 = 126, DQM1 = 123
8284 20:12:04.679279 DQ Delay:
8285 20:12:04.682923 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8286 20:12:04.686159 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =134
8287 20:12:04.689465 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =118
8288 20:12:04.693010 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8289 20:12:04.693092
8290 20:12:04.693156
8291 20:12:04.693215
8292 20:12:04.696337 [DramC_TX_OE_Calibration] TA2
8293 20:12:04.699666 Original DQ_B0 (3 6) =30, OEN = 27
8294 20:12:04.703130 Original DQ_B1 (3 6) =30, OEN = 27
8295 20:12:04.706129 24, 0x0, End_B0=24 End_B1=24
8296 20:12:04.706212 25, 0x0, End_B0=25 End_B1=25
8297 20:12:04.709632 26, 0x0, End_B0=26 End_B1=26
8298 20:12:04.712663 27, 0x0, End_B0=27 End_B1=27
8299 20:12:04.716326 28, 0x0, End_B0=28 End_B1=28
8300 20:12:04.719260 29, 0x0, End_B0=29 End_B1=29
8301 20:12:04.719343 30, 0x0, End_B0=30 End_B1=30
8302 20:12:04.722910 31, 0x4141, End_B0=30 End_B1=30
8303 20:12:04.726264 Byte0 end_step=30 best_step=27
8304 20:12:04.729390 Byte1 end_step=30 best_step=27
8305 20:12:04.733162 Byte0 TX OE(2T, 0.5T) = (3, 3)
8306 20:12:04.736302 Byte1 TX OE(2T, 0.5T) = (3, 3)
8307 20:12:04.736383
8308 20:12:04.736447
8309 20:12:04.742302 [DQSOSCAuto] RK1, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8310 20:12:04.745673 CH0 RK1: MR19=303, MR18=170B
8311 20:12:04.752404 CH0_RK1: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
8312 20:12:04.755733 [RxdqsGatingPostProcess] freq 1600
8313 20:12:04.758921 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8314 20:12:04.762490 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 20:12:04.765880 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 20:12:04.769798 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 20:12:04.772658 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 20:12:04.775978 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 20:12:04.779379 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 20:12:04.782274 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 20:12:04.785829 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 20:12:04.789274 Pre-setting of DQS Precalculation
8323 20:12:04.792825 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8324 20:12:04.792908 ==
8325 20:12:04.796170 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 20:12:04.799479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 20:12:04.799586 ==
8328 20:12:04.805687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 20:12:04.809190 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 20:12:04.815864 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 20:12:04.818900 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 20:12:04.829179 [CA 0] Center 43 (15~72) winsize 58
8333 20:12:04.832286 [CA 1] Center 43 (15~72) winsize 58
8334 20:12:04.836212 [CA 2] Center 39 (11~67) winsize 57
8335 20:12:04.838771 [CA 3] Center 37 (8~67) winsize 60
8336 20:12:04.842634 [CA 4] Center 38 (9~68) winsize 60
8337 20:12:04.845582 [CA 5] Center 37 (8~66) winsize 59
8338 20:12:04.845667
8339 20:12:04.849029 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8340 20:12:04.849111
8341 20:12:04.852201 [CATrainingPosCal] consider 1 rank data
8342 20:12:04.855900 u2DelayCellTimex100 = 275/100 ps
8343 20:12:04.858908 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8344 20:12:04.865514 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8345 20:12:04.869246 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8346 20:12:04.872040 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 20:12:04.875533 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8348 20:12:04.878779 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8349 20:12:04.878864
8350 20:12:04.883105 CA PerBit enable=1, Macro0, CA PI delay=37
8351 20:12:04.883186
8352 20:12:04.885431 [CBTSetCACLKResult] CA Dly = 37
8353 20:12:04.888850 CS Dly: 8 (0~39)
8354 20:12:04.892159 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 20:12:04.895815 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 20:12:04.895897 ==
8357 20:12:04.899125 Dram Type= 6, Freq= 0, CH_1, rank 1
8358 20:12:04.902057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 20:12:04.905423 ==
8360 20:12:04.908832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 20:12:04.912315 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 20:12:04.918809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 20:12:04.922277 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 20:12:04.932636 [CA 0] Center 42 (13~72) winsize 60
8365 20:12:04.935630 [CA 1] Center 43 (14~72) winsize 59
8366 20:12:04.939176 [CA 2] Center 38 (9~67) winsize 59
8367 20:12:04.943038 [CA 3] Center 37 (8~66) winsize 59
8368 20:12:04.945525 [CA 4] Center 37 (8~67) winsize 60
8369 20:12:04.948923 [CA 5] Center 36 (7~66) winsize 60
8370 20:12:04.949002
8371 20:12:04.952421 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8372 20:12:04.952501
8373 20:12:04.955620 [CATrainingPosCal] consider 2 rank data
8374 20:12:04.959138 u2DelayCellTimex100 = 275/100 ps
8375 20:12:04.962355 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8376 20:12:04.968645 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8377 20:12:04.972351 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8378 20:12:04.975358 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8379 20:12:04.978914 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8380 20:12:04.982092 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8381 20:12:04.982172
8382 20:12:04.986348 CA PerBit enable=1, Macro0, CA PI delay=37
8383 20:12:04.986466
8384 20:12:04.988986 [CBTSetCACLKResult] CA Dly = 37
8385 20:12:04.992609 CS Dly: 10 (0~43)
8386 20:12:04.995442 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 20:12:04.998765 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 20:12:04.998847
8389 20:12:05.002519 ----->DramcWriteLeveling(PI) begin...
8390 20:12:05.002602 ==
8391 20:12:05.005644 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 20:12:05.008863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 20:12:05.012158 ==
8394 20:12:05.012239 Write leveling (Byte 0): 23 => 23
8395 20:12:05.015472 Write leveling (Byte 1): 27 => 27
8396 20:12:05.018984 DramcWriteLeveling(PI) end<-----
8397 20:12:05.019097
8398 20:12:05.019165 ==
8399 20:12:05.022404 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 20:12:05.028754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 20:12:05.028836 ==
8402 20:12:05.028899 [Gating] SW mode calibration
8403 20:12:05.038806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8404 20:12:05.042454 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8405 20:12:05.045492 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 20:12:05.052193 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 20:12:05.055453 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 20:12:05.058762 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 20:12:05.065699 1 4 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8410 20:12:05.068906 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 20:12:05.072248 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 20:12:05.079314 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 20:12:05.082773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 20:12:05.085703 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 20:12:05.092026 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 20:12:05.095526 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 20:12:05.098904 1 5 16 | B1->B0 | 3131 3333 | 0 1 | (0 1) (1 0)
8418 20:12:05.105447 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8419 20:12:05.109330 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 20:12:05.112329 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 20:12:05.118927 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 20:12:05.122351 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 20:12:05.125588 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 20:12:05.129091 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8425 20:12:05.135963 1 6 16 | B1->B0 | 4242 3434 | 0 1 | (0 0) (0 0)
8426 20:12:05.138796 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 20:12:05.142576 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 20:12:05.148909 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 20:12:05.152844 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 20:12:05.155453 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 20:12:05.162088 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 20:12:05.165646 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 20:12:05.170155 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8434 20:12:05.175836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8435 20:12:05.179294 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 20:12:05.182653 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 20:12:05.189117 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 20:12:05.192608 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 20:12:05.195772 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 20:12:05.202437 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 20:12:05.205708 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 20:12:05.209490 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 20:12:05.212663 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 20:12:05.219302 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 20:12:05.222674 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 20:12:05.226113 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 20:12:05.233514 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 20:12:05.236567 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8449 20:12:05.239673 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8450 20:12:05.246038 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8451 20:12:05.246120 Total UI for P1: 0, mck2ui 16
8452 20:12:05.252657 best dqsien dly found for B0: ( 1, 9, 14)
8453 20:12:05.256198 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 20:12:05.259954 Total UI for P1: 0, mck2ui 16
8455 20:12:05.262713 best dqsien dly found for B1: ( 1, 9, 16)
8456 20:12:05.266201 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8457 20:12:05.269018 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8458 20:12:05.269100
8459 20:12:05.272612 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8460 20:12:05.276207 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8461 20:12:05.279257 [Gating] SW calibration Done
8462 20:12:05.279338 ==
8463 20:12:05.282812 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 20:12:05.286021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 20:12:05.289419 ==
8466 20:12:05.289500 RX Vref Scan: 0
8467 20:12:05.289563
8468 20:12:05.292770 RX Vref 0 -> 0, step: 1
8469 20:12:05.292851
8470 20:12:05.292914 RX Delay 0 -> 252, step: 8
8471 20:12:05.299459 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8472 20:12:05.303174 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8473 20:12:05.306450 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8474 20:12:05.309747 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8475 20:12:05.312626 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8476 20:12:05.319431 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8477 20:12:05.322491 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8478 20:12:05.326012 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8479 20:12:05.329135 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8480 20:12:05.332457 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8481 20:12:05.339470 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8482 20:12:05.342672 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8483 20:12:05.345775 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8484 20:12:05.349451 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8485 20:12:05.352968 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8486 20:12:05.359525 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8487 20:12:05.359606 ==
8488 20:12:05.362738 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 20:12:05.365783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 20:12:05.365865 ==
8491 20:12:05.365929 DQS Delay:
8492 20:12:05.369449 DQS0 = 0, DQS1 = 0
8493 20:12:05.369530 DQM Delay:
8494 20:12:05.372670 DQM0 = 134, DQM1 = 127
8495 20:12:05.372751 DQ Delay:
8496 20:12:05.376091 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8497 20:12:05.379226 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8498 20:12:05.382777 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8499 20:12:05.386006 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8500 20:12:05.386086
8501 20:12:05.386149
8502 20:12:05.389545 ==
8503 20:12:05.392685 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 20:12:05.396163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 20:12:05.396244 ==
8506 20:12:05.396307
8507 20:12:05.396364
8508 20:12:05.399090 TX Vref Scan disable
8509 20:12:05.399169 == TX Byte 0 ==
8510 20:12:05.402812 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8511 20:12:05.409314 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8512 20:12:05.409395 == TX Byte 1 ==
8513 20:12:05.412475 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8514 20:12:05.419534 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8515 20:12:05.419619 ==
8516 20:12:05.422637 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 20:12:05.425649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 20:12:05.425732 ==
8519 20:12:05.439990
8520 20:12:05.443671 TX Vref early break, caculate TX vref
8521 20:12:05.447269 TX Vref=16, minBit 8, minWin=21, winSum=367
8522 20:12:05.450379 TX Vref=18, minBit 9, minWin=21, winSum=377
8523 20:12:05.453664 TX Vref=20, minBit 8, minWin=22, winSum=387
8524 20:12:05.456573 TX Vref=22, minBit 9, minWin=22, winSum=393
8525 20:12:05.460103 TX Vref=24, minBit 8, minWin=24, winSum=404
8526 20:12:05.466908 TX Vref=26, minBit 8, minWin=23, winSum=411
8527 20:12:05.470241 TX Vref=28, minBit 8, minWin=25, winSum=421
8528 20:12:05.473944 TX Vref=30, minBit 5, minWin=26, winSum=423
8529 20:12:05.476690 TX Vref=32, minBit 8, minWin=24, winSum=410
8530 20:12:05.480129 TX Vref=34, minBit 8, minWin=23, winSum=404
8531 20:12:05.483192 TX Vref=36, minBit 8, minWin=23, winSum=390
8532 20:12:05.490152 [TxChooseVref] Worse bit 5, Min win 26, Win sum 423, Final Vref 30
8533 20:12:05.490276
8534 20:12:05.493325 Final TX Range 0 Vref 30
8535 20:12:05.493448
8536 20:12:05.493560 ==
8537 20:12:05.496644 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 20:12:05.500348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 20:12:05.500469 ==
8540 20:12:05.500584
8541 20:12:05.500694
8542 20:12:05.503735 TX Vref Scan disable
8543 20:12:05.510531 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8544 20:12:05.510657 == TX Byte 0 ==
8545 20:12:05.513709 u2DelayCellOfst[0]=17 cells (5 PI)
8546 20:12:05.516937 u2DelayCellOfst[1]=10 cells (3 PI)
8547 20:12:05.520453 u2DelayCellOfst[2]=0 cells (0 PI)
8548 20:12:05.523620 u2DelayCellOfst[3]=7 cells (2 PI)
8549 20:12:05.526819 u2DelayCellOfst[4]=7 cells (2 PI)
8550 20:12:05.530378 u2DelayCellOfst[5]=17 cells (5 PI)
8551 20:12:05.533199 u2DelayCellOfst[6]=17 cells (5 PI)
8552 20:12:05.533319 u2DelayCellOfst[7]=7 cells (2 PI)
8553 20:12:05.540078 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8554 20:12:05.543325 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8555 20:12:05.543407 == TX Byte 1 ==
8556 20:12:05.546781 u2DelayCellOfst[8]=0 cells (0 PI)
8557 20:12:05.550029 u2DelayCellOfst[9]=3 cells (1 PI)
8558 20:12:05.554210 u2DelayCellOfst[10]=14 cells (4 PI)
8559 20:12:05.556717 u2DelayCellOfst[11]=7 cells (2 PI)
8560 20:12:05.560402 u2DelayCellOfst[12]=14 cells (4 PI)
8561 20:12:05.563582 u2DelayCellOfst[13]=17 cells (5 PI)
8562 20:12:05.567221 u2DelayCellOfst[14]=17 cells (5 PI)
8563 20:12:05.570157 u2DelayCellOfst[15]=17 cells (5 PI)
8564 20:12:05.573230 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8565 20:12:05.580624 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8566 20:12:05.580706 DramC Write-DBI on
8567 20:12:05.580770 ==
8568 20:12:05.583408 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 20:12:05.586672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 20:12:05.586753 ==
8571 20:12:05.586817
8572 20:12:05.590183
8573 20:12:05.590263 TX Vref Scan disable
8574 20:12:05.593369 == TX Byte 0 ==
8575 20:12:05.596964 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8576 20:12:05.600098 == TX Byte 1 ==
8577 20:12:05.604109 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8578 20:12:05.604210 DramC Write-DBI off
8579 20:12:05.604306
8580 20:12:05.606755 [DATLAT]
8581 20:12:05.606835 Freq=1600, CH1 RK0
8582 20:12:05.606898
8583 20:12:05.610552 DATLAT Default: 0xf
8584 20:12:05.610633 0, 0xFFFF, sum = 0
8585 20:12:05.614001 1, 0xFFFF, sum = 0
8586 20:12:05.614112 2, 0xFFFF, sum = 0
8587 20:12:05.616981 3, 0xFFFF, sum = 0
8588 20:12:05.617063 4, 0xFFFF, sum = 0
8589 20:12:05.620292 5, 0xFFFF, sum = 0
8590 20:12:05.620374 6, 0xFFFF, sum = 0
8591 20:12:05.623480 7, 0xFFFF, sum = 0
8592 20:12:05.623563 8, 0xFFFF, sum = 0
8593 20:12:05.627050 9, 0xFFFF, sum = 0
8594 20:12:05.630070 10, 0xFFFF, sum = 0
8595 20:12:05.630151 11, 0xFFFF, sum = 0
8596 20:12:05.633516 12, 0xFFFF, sum = 0
8597 20:12:05.633597 13, 0xFFFF, sum = 0
8598 20:12:05.636954 14, 0x0, sum = 1
8599 20:12:05.637035 15, 0x0, sum = 2
8600 20:12:05.640420 16, 0x0, sum = 3
8601 20:12:05.640533 17, 0x0, sum = 4
8602 20:12:05.640667 best_step = 15
8603 20:12:05.640756
8604 20:12:05.643616 ==
8605 20:12:05.647029 Dram Type= 6, Freq= 0, CH_1, rank 0
8606 20:12:05.650371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8607 20:12:05.650478 ==
8608 20:12:05.650567 RX Vref Scan: 1
8609 20:12:05.650645
8610 20:12:05.653528 Set Vref Range= 24 -> 127
8611 20:12:05.653609
8612 20:12:05.657093 RX Vref 24 -> 127, step: 1
8613 20:12:05.657219
8614 20:12:05.659990 RX Delay 11 -> 252, step: 4
8615 20:12:05.660088
8616 20:12:05.664042 Set Vref, RX VrefLevel [Byte0]: 24
8617 20:12:05.666741 [Byte1]: 24
8618 20:12:05.666822
8619 20:12:05.670578 Set Vref, RX VrefLevel [Byte0]: 25
8620 20:12:05.674234 [Byte1]: 25
8621 20:12:05.674316
8622 20:12:05.677088 Set Vref, RX VrefLevel [Byte0]: 26
8623 20:12:05.680258 [Byte1]: 26
8624 20:12:05.684098
8625 20:12:05.684239 Set Vref, RX VrefLevel [Byte0]: 27
8626 20:12:05.686861 [Byte1]: 27
8627 20:12:05.691832
8628 20:12:05.691955 Set Vref, RX VrefLevel [Byte0]: 28
8629 20:12:05.694505 [Byte1]: 28
8630 20:12:05.698576
8631 20:12:05.702231 Set Vref, RX VrefLevel [Byte0]: 29
8632 20:12:05.702384 [Byte1]: 29
8633 20:12:05.706522
8634 20:12:05.706644 Set Vref, RX VrefLevel [Byte0]: 30
8635 20:12:05.709457 [Byte1]: 30
8636 20:12:05.714241
8637 20:12:05.714323 Set Vref, RX VrefLevel [Byte0]: 31
8638 20:12:05.717472 [Byte1]: 31
8639 20:12:05.721464
8640 20:12:05.721544 Set Vref, RX VrefLevel [Byte0]: 32
8641 20:12:05.725307 [Byte1]: 32
8642 20:12:05.729820
8643 20:12:05.729900 Set Vref, RX VrefLevel [Byte0]: 33
8644 20:12:05.732712 [Byte1]: 33
8645 20:12:05.736943
8646 20:12:05.737027 Set Vref, RX VrefLevel [Byte0]: 34
8647 20:12:05.740379 [Byte1]: 34
8648 20:12:05.744328
8649 20:12:05.744408 Set Vref, RX VrefLevel [Byte0]: 35
8650 20:12:05.747832 [Byte1]: 35
8651 20:12:05.751920
8652 20:12:05.752000 Set Vref, RX VrefLevel [Byte0]: 36
8653 20:12:05.755541 [Byte1]: 36
8654 20:12:05.759831
8655 20:12:05.759956 Set Vref, RX VrefLevel [Byte0]: 37
8656 20:12:05.763539 [Byte1]: 37
8657 20:12:05.767449
8658 20:12:05.767529 Set Vref, RX VrefLevel [Byte0]: 38
8659 20:12:05.770933 [Byte1]: 38
8660 20:12:05.774924
8661 20:12:05.775004 Set Vref, RX VrefLevel [Byte0]: 39
8662 20:12:05.778313 [Byte1]: 39
8663 20:12:05.783383
8664 20:12:05.783472 Set Vref, RX VrefLevel [Byte0]: 40
8665 20:12:05.785979 [Byte1]: 40
8666 20:12:05.790010
8667 20:12:05.790092 Set Vref, RX VrefLevel [Byte0]: 41
8668 20:12:05.793824 [Byte1]: 41
8669 20:12:05.798042
8670 20:12:05.798122 Set Vref, RX VrefLevel [Byte0]: 42
8671 20:12:05.800964 [Byte1]: 42
8672 20:12:05.805861
8673 20:12:05.805942 Set Vref, RX VrefLevel [Byte0]: 43
8674 20:12:05.808789 [Byte1]: 43
8675 20:12:05.812784
8676 20:12:05.812865 Set Vref, RX VrefLevel [Byte0]: 44
8677 20:12:05.816388 [Byte1]: 44
8678 20:12:05.820308
8679 20:12:05.820403 Set Vref, RX VrefLevel [Byte0]: 45
8680 20:12:05.824028 [Byte1]: 45
8681 20:12:05.828299
8682 20:12:05.828380 Set Vref, RX VrefLevel [Byte0]: 46
8683 20:12:05.834807 [Byte1]: 46
8684 20:12:05.834887
8685 20:12:05.838160 Set Vref, RX VrefLevel [Byte0]: 47
8686 20:12:05.841409 [Byte1]: 47
8687 20:12:05.841489
8688 20:12:05.844828 Set Vref, RX VrefLevel [Byte0]: 48
8689 20:12:05.848435 [Byte1]: 48
8690 20:12:05.848515
8691 20:12:05.851226 Set Vref, RX VrefLevel [Byte0]: 49
8692 20:12:05.854837 [Byte1]: 49
8693 20:12:05.859209
8694 20:12:05.859289 Set Vref, RX VrefLevel [Byte0]: 50
8695 20:12:05.862362 [Byte1]: 50
8696 20:12:05.866248
8697 20:12:05.866353 Set Vref, RX VrefLevel [Byte0]: 51
8698 20:12:05.870039 [Byte1]: 51
8699 20:12:05.873612
8700 20:12:05.873691 Set Vref, RX VrefLevel [Byte0]: 52
8701 20:12:05.877820 [Byte1]: 52
8702 20:12:05.881499
8703 20:12:05.881579 Set Vref, RX VrefLevel [Byte0]: 53
8704 20:12:05.884858 [Byte1]: 53
8705 20:12:05.889790
8706 20:12:05.889870 Set Vref, RX VrefLevel [Byte0]: 54
8707 20:12:05.892635 [Byte1]: 54
8708 20:12:05.896678
8709 20:12:05.896760 Set Vref, RX VrefLevel [Byte0]: 55
8710 20:12:05.900010 [Byte1]: 55
8711 20:12:05.904833
8712 20:12:05.904914 Set Vref, RX VrefLevel [Byte0]: 56
8713 20:12:05.907745 [Byte1]: 56
8714 20:12:05.911962
8715 20:12:05.912044 Set Vref, RX VrefLevel [Byte0]: 57
8716 20:12:05.915216 [Byte1]: 57
8717 20:12:05.919742
8718 20:12:05.919823 Set Vref, RX VrefLevel [Byte0]: 58
8719 20:12:05.922851 [Byte1]: 58
8720 20:12:05.927192
8721 20:12:05.927274 Set Vref, RX VrefLevel [Byte0]: 59
8722 20:12:05.933276 [Byte1]: 59
8723 20:12:05.933357
8724 20:12:05.936688 Set Vref, RX VrefLevel [Byte0]: 60
8725 20:12:05.939957 [Byte1]: 60
8726 20:12:05.940069
8727 20:12:05.943641 Set Vref, RX VrefLevel [Byte0]: 61
8728 20:12:05.946849 [Byte1]: 61
8729 20:12:05.946930
8730 20:12:05.950256 Set Vref, RX VrefLevel [Byte0]: 62
8731 20:12:05.953355 [Byte1]: 62
8732 20:12:05.957563
8733 20:12:05.957642 Set Vref, RX VrefLevel [Byte0]: 63
8734 20:12:05.960978 [Byte1]: 63
8735 20:12:05.965152
8736 20:12:05.965233 Set Vref, RX VrefLevel [Byte0]: 64
8737 20:12:05.968252 [Byte1]: 64
8738 20:12:05.972995
8739 20:12:05.973075 Set Vref, RX VrefLevel [Byte0]: 65
8740 20:12:05.976385 [Byte1]: 65
8741 20:12:05.980276
8742 20:12:05.980355 Set Vref, RX VrefLevel [Byte0]: 66
8743 20:12:05.983667 [Byte1]: 66
8744 20:12:05.988112
8745 20:12:05.988191 Set Vref, RX VrefLevel [Byte0]: 67
8746 20:12:05.991187 [Byte1]: 67
8747 20:12:05.995656
8748 20:12:05.995735 Set Vref, RX VrefLevel [Byte0]: 68
8749 20:12:05.998816 [Byte1]: 68
8750 20:12:06.003099
8751 20:12:06.003178 Set Vref, RX VrefLevel [Byte0]: 69
8752 20:12:06.006820 [Byte1]: 69
8753 20:12:06.010717
8754 20:12:06.010797 Set Vref, RX VrefLevel [Byte0]: 70
8755 20:12:06.014286 [Byte1]: 70
8756 20:12:06.018726
8757 20:12:06.018805 Set Vref, RX VrefLevel [Byte0]: 71
8758 20:12:06.021952 [Byte1]: 71
8759 20:12:06.025964
8760 20:12:06.026051 Set Vref, RX VrefLevel [Byte0]: 72
8761 20:12:06.029484 [Byte1]: 72
8762 20:12:06.033460
8763 20:12:06.033540 Set Vref, RX VrefLevel [Byte0]: 73
8764 20:12:06.037543 [Byte1]: 73
8765 20:12:06.041012
8766 20:12:06.041092 Set Vref, RX VrefLevel [Byte0]: 74
8767 20:12:06.044795 [Byte1]: 74
8768 20:12:06.049341
8769 20:12:06.049421 Set Vref, RX VrefLevel [Byte0]: 75
8770 20:12:06.052206 [Byte1]: 75
8771 20:12:06.057015
8772 20:12:06.057095 Set Vref, RX VrefLevel [Byte0]: 76
8773 20:12:06.059785 [Byte1]: 76
8774 20:12:06.063946
8775 20:12:06.064036 Final RX Vref Byte 0 = 59 to rank0
8776 20:12:06.068022 Final RX Vref Byte 1 = 58 to rank0
8777 20:12:06.070976 Final RX Vref Byte 0 = 59 to rank1
8778 20:12:06.074572 Final RX Vref Byte 1 = 58 to rank1==
8779 20:12:06.077552 Dram Type= 6, Freq= 0, CH_1, rank 0
8780 20:12:06.083841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 20:12:06.083922 ==
8782 20:12:06.083985 DQS Delay:
8783 20:12:06.084044 DQS0 = 0, DQS1 = 0
8784 20:12:06.087366 DQM Delay:
8785 20:12:06.087445 DQM0 = 131, DQM1 = 124
8786 20:12:06.091005 DQ Delay:
8787 20:12:06.094155 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8788 20:12:06.097368 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8789 20:12:06.100489 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8790 20:12:06.103939 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132
8791 20:12:06.104028
8792 20:12:06.104092
8793 20:12:06.104149
8794 20:12:06.107754 [DramC_TX_OE_Calibration] TA2
8795 20:12:06.110418 Original DQ_B0 (3 6) =30, OEN = 27
8796 20:12:06.114017 Original DQ_B1 (3 6) =30, OEN = 27
8797 20:12:06.117535 24, 0x0, End_B0=24 End_B1=24
8798 20:12:06.117622 25, 0x0, End_B0=25 End_B1=25
8799 20:12:06.120872 26, 0x0, End_B0=26 End_B1=26
8800 20:12:06.124207 27, 0x0, End_B0=27 End_B1=27
8801 20:12:06.127211 28, 0x0, End_B0=28 End_B1=28
8802 20:12:06.127292 29, 0x0, End_B0=29 End_B1=29
8803 20:12:06.130840 30, 0x0, End_B0=30 End_B1=30
8804 20:12:06.133950 31, 0x4141, End_B0=30 End_B1=30
8805 20:12:06.137531 Byte0 end_step=30 best_step=27
8806 20:12:06.140600 Byte1 end_step=30 best_step=27
8807 20:12:06.143993 Byte0 TX OE(2T, 0.5T) = (3, 3)
8808 20:12:06.144118 Byte1 TX OE(2T, 0.5T) = (3, 3)
8809 20:12:06.147403
8810 20:12:06.147521
8811 20:12:06.153731 [DQSOSCAuto] RK0, (LSB)MR18= 0x1703, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 398 ps
8812 20:12:06.157330 CH1 RK0: MR19=303, MR18=1703
8813 20:12:06.163962 CH1_RK0: MR19=0x303, MR18=0x1703, DQSOSC=398, MR23=63, INC=23, DEC=15
8814 20:12:06.164086
8815 20:12:06.168227 ----->DramcWriteLeveling(PI) begin...
8816 20:12:06.168354 ==
8817 20:12:06.170643 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 20:12:06.174131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 20:12:06.174299 ==
8820 20:12:06.177552 Write leveling (Byte 0): 24 => 24
8821 20:12:06.180511 Write leveling (Byte 1): 27 => 27
8822 20:12:06.184065 DramcWriteLeveling(PI) end<-----
8823 20:12:06.184186
8824 20:12:06.184300 ==
8825 20:12:06.187770 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 20:12:06.190512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 20:12:06.190633 ==
8828 20:12:06.194213 [Gating] SW mode calibration
8829 20:12:06.201145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8830 20:12:06.207466 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8831 20:12:06.210870 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 20:12:06.214025 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 20:12:06.220600 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8834 20:12:06.223922 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
8835 20:12:06.227549 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 20:12:06.234427 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 20:12:06.237128 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 20:12:06.240801 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 20:12:06.247322 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 20:12:06.250854 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8841 20:12:06.254061 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
8842 20:12:06.257509 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8843 20:12:06.264419 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8844 20:12:06.267322 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 20:12:06.270939 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 20:12:06.277369 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 20:12:06.280709 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 20:12:06.284074 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 20:12:06.290718 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8850 20:12:06.294063 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8851 20:12:06.297322 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 20:12:06.303737 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 20:12:06.307443 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 20:12:06.310922 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 20:12:06.317824 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 20:12:06.320586 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8857 20:12:06.323911 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8858 20:12:06.330712 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8859 20:12:06.333906 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8860 20:12:06.337311 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 20:12:06.344127 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 20:12:06.347718 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 20:12:06.350611 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 20:12:06.357201 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 20:12:06.361023 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 20:12:06.364383 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 20:12:06.367419 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 20:12:06.373880 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 20:12:06.377299 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 20:12:06.380716 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 20:12:06.387536 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 20:12:06.390386 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8873 20:12:06.394321 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8874 20:12:06.400895 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8875 20:12:06.404062 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8876 20:12:06.407109 Total UI for P1: 0, mck2ui 16
8877 20:12:06.410782 best dqsien dly found for B0: ( 1, 9, 8)
8878 20:12:06.413982 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 20:12:06.417238 Total UI for P1: 0, mck2ui 16
8880 20:12:06.420896 best dqsien dly found for B1: ( 1, 9, 14)
8881 20:12:06.424877 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8882 20:12:06.427489 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8883 20:12:06.427569
8884 20:12:06.431075 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8885 20:12:06.437236 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8886 20:12:06.437317 [Gating] SW calibration Done
8887 20:12:06.437380 ==
8888 20:12:06.440660 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 20:12:06.447176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 20:12:06.447257 ==
8891 20:12:06.447320 RX Vref Scan: 0
8892 20:12:06.447379
8893 20:12:06.450633 RX Vref 0 -> 0, step: 1
8894 20:12:06.450751
8895 20:12:06.454112 RX Delay 0 -> 252, step: 8
8896 20:12:06.457542 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8897 20:12:06.460711 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8898 20:12:06.464051 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8899 20:12:06.468059 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8900 20:12:06.474473 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8901 20:12:06.477519 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8902 20:12:06.481007 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8903 20:12:06.484467 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8904 20:12:06.488242 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8905 20:12:06.494248 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8906 20:12:06.497711 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8907 20:12:06.500804 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8908 20:12:06.504355 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8909 20:12:06.508148 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8910 20:12:06.514486 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8911 20:12:06.517769 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8912 20:12:06.517849 ==
8913 20:12:06.520851 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 20:12:06.524424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 20:12:06.524538 ==
8916 20:12:06.527608 DQS Delay:
8917 20:12:06.527688 DQS0 = 0, DQS1 = 0
8918 20:12:06.527752 DQM Delay:
8919 20:12:06.530947 DQM0 = 132, DQM1 = 128
8920 20:12:06.531028 DQ Delay:
8921 20:12:06.534557 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8922 20:12:06.537416 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8923 20:12:06.540935 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8924 20:12:06.547552 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8925 20:12:06.547632
8926 20:12:06.547696
8927 20:12:06.547754 ==
8928 20:12:06.551265 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 20:12:06.554628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 20:12:06.554709 ==
8931 20:12:06.554780
8932 20:12:06.554857
8933 20:12:06.557876 TX Vref Scan disable
8934 20:12:06.557956 == TX Byte 0 ==
8935 20:12:06.564286 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8936 20:12:06.567436 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8937 20:12:06.567516 == TX Byte 1 ==
8938 20:12:06.574115 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8939 20:12:06.577628 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 20:12:06.577709 ==
8941 20:12:06.581058 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 20:12:06.584306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 20:12:06.584386 ==
8944 20:12:06.599012
8945 20:12:06.602177 TX Vref early break, caculate TX vref
8946 20:12:06.605766 TX Vref=16, minBit 8, minWin=22, winSum=375
8947 20:12:06.609266 TX Vref=18, minBit 8, minWin=22, winSum=384
8948 20:12:06.612769 TX Vref=20, minBit 8, minWin=23, winSum=398
8949 20:12:06.615833 TX Vref=22, minBit 9, minWin=24, winSum=404
8950 20:12:06.618855 TX Vref=24, minBit 5, minWin=25, winSum=411
8951 20:12:06.625836 TX Vref=26, minBit 8, minWin=25, winSum=417
8952 20:12:06.628913 TX Vref=28, minBit 8, minWin=25, winSum=422
8953 20:12:06.632374 TX Vref=30, minBit 8, minWin=25, winSum=418
8954 20:12:06.635506 TX Vref=32, minBit 0, minWin=25, winSum=414
8955 20:12:06.639087 TX Vref=34, minBit 0, minWin=24, winSum=404
8956 20:12:06.642007 TX Vref=36, minBit 9, minWin=23, winSum=396
8957 20:12:06.649220 [TxChooseVref] Worse bit 8, Min win 25, Win sum 422, Final Vref 28
8958 20:12:06.649327
8959 20:12:06.652039 Final TX Range 0 Vref 28
8960 20:12:06.652140
8961 20:12:06.652229 ==
8962 20:12:06.655670 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 20:12:06.658804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 20:12:06.658915 ==
8965 20:12:06.659084
8966 20:12:06.659219
8967 20:12:06.662198 TX Vref Scan disable
8968 20:12:06.669007 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8969 20:12:06.669139 == TX Byte 0 ==
8970 20:12:06.672428 u2DelayCellOfst[0]=17 cells (5 PI)
8971 20:12:06.675669 u2DelayCellOfst[1]=10 cells (3 PI)
8972 20:12:06.679131 u2DelayCellOfst[2]=0 cells (0 PI)
8973 20:12:06.682621 u2DelayCellOfst[3]=7 cells (2 PI)
8974 20:12:06.685398 u2DelayCellOfst[4]=10 cells (3 PI)
8975 20:12:06.689244 u2DelayCellOfst[5]=17 cells (5 PI)
8976 20:12:06.692426 u2DelayCellOfst[6]=17 cells (5 PI)
8977 20:12:06.695807 u2DelayCellOfst[7]=3 cells (1 PI)
8978 20:12:06.698876 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8979 20:12:06.702350 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8980 20:12:06.705758 == TX Byte 1 ==
8981 20:12:06.705888 u2DelayCellOfst[8]=0 cells (0 PI)
8982 20:12:06.709048 u2DelayCellOfst[9]=3 cells (1 PI)
8983 20:12:06.712481 u2DelayCellOfst[10]=14 cells (4 PI)
8984 20:12:06.715833 u2DelayCellOfst[11]=7 cells (2 PI)
8985 20:12:06.719131 u2DelayCellOfst[12]=14 cells (4 PI)
8986 20:12:06.723033 u2DelayCellOfst[13]=17 cells (5 PI)
8987 20:12:06.725769 u2DelayCellOfst[14]=17 cells (5 PI)
8988 20:12:06.729455 u2DelayCellOfst[15]=17 cells (5 PI)
8989 20:12:06.733254 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8990 20:12:06.739188 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8991 20:12:06.739314 DramC Write-DBI on
8992 20:12:06.739429 ==
8993 20:12:06.742225 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 20:12:06.745620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 20:12:06.745743 ==
8996 20:12:06.749174
8997 20:12:06.749296
8998 20:12:06.749408 TX Vref Scan disable
8999 20:12:06.752194 == TX Byte 0 ==
9000 20:12:06.755978 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9001 20:12:06.759093 == TX Byte 1 ==
9002 20:12:06.762587 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9003 20:12:06.762713 DramC Write-DBI off
9004 20:12:06.762833
9005 20:12:06.765630 [DATLAT]
9006 20:12:06.765754 Freq=1600, CH1 RK1
9007 20:12:06.765868
9008 20:12:06.769027 DATLAT Default: 0xf
9009 20:12:06.769171 0, 0xFFFF, sum = 0
9010 20:12:06.772193 1, 0xFFFF, sum = 0
9011 20:12:06.772319 2, 0xFFFF, sum = 0
9012 20:12:06.775766 3, 0xFFFF, sum = 0
9013 20:12:06.775893 4, 0xFFFF, sum = 0
9014 20:12:06.778795 5, 0xFFFF, sum = 0
9015 20:12:06.778921 6, 0xFFFF, sum = 0
9016 20:12:06.782232 7, 0xFFFF, sum = 0
9017 20:12:06.785724 8, 0xFFFF, sum = 0
9018 20:12:06.785929 9, 0xFFFF, sum = 0
9019 20:12:06.788828 10, 0xFFFF, sum = 0
9020 20:12:06.788957 11, 0xFFFF, sum = 0
9021 20:12:06.792266 12, 0xFFFF, sum = 0
9022 20:12:06.792390 13, 0xFFFF, sum = 0
9023 20:12:06.796047 14, 0x0, sum = 1
9024 20:12:06.796171 15, 0x0, sum = 2
9025 20:12:06.798787 16, 0x0, sum = 3
9026 20:12:06.798914 17, 0x0, sum = 4
9027 20:12:06.802656 best_step = 15
9028 20:12:06.802778
9029 20:12:06.802889 ==
9030 20:12:06.805706 Dram Type= 6, Freq= 0, CH_1, rank 1
9031 20:12:06.808929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9032 20:12:06.809051 ==
9033 20:12:06.809163 RX Vref Scan: 0
9034 20:12:06.809287
9035 20:12:06.812423 RX Vref 0 -> 0, step: 1
9036 20:12:06.812545
9037 20:12:06.816439 RX Delay 11 -> 252, step: 4
9038 20:12:06.819286 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9039 20:12:06.825874 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9040 20:12:06.828873 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9041 20:12:06.832415 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9042 20:12:06.835756 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9043 20:12:06.839192 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9044 20:12:06.842654 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9045 20:12:06.848826 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9046 20:12:06.852714 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9047 20:12:06.856103 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9048 20:12:06.859407 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9049 20:12:06.862318 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9050 20:12:06.869373 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9051 20:12:06.872371 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9052 20:12:06.875616 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9053 20:12:06.878787 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9054 20:12:06.878908 ==
9055 20:12:06.882200 Dram Type= 6, Freq= 0, CH_1, rank 1
9056 20:12:06.889060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9057 20:12:06.889185 ==
9058 20:12:06.889296 DQS Delay:
9059 20:12:06.892345 DQS0 = 0, DQS1 = 0
9060 20:12:06.892467 DQM Delay:
9061 20:12:06.892579 DQM0 = 129, DQM1 = 126
9062 20:12:06.895483 DQ Delay:
9063 20:12:06.899568 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9064 20:12:06.902237 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
9065 20:12:06.906065 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9066 20:12:06.909500 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9067 20:12:06.909621
9068 20:12:06.909732
9069 20:12:06.909839
9070 20:12:06.912498 [DramC_TX_OE_Calibration] TA2
9071 20:12:06.915901 Original DQ_B0 (3 6) =30, OEN = 27
9072 20:12:06.919285 Original DQ_B1 (3 6) =30, OEN = 27
9073 20:12:06.922503 24, 0x0, End_B0=24 End_B1=24
9074 20:12:06.922626 25, 0x0, End_B0=25 End_B1=25
9075 20:12:06.925746 26, 0x0, End_B0=26 End_B1=26
9076 20:12:06.928934 27, 0x0, End_B0=27 End_B1=27
9077 20:12:06.932510 28, 0x0, End_B0=28 End_B1=28
9078 20:12:06.932641 29, 0x0, End_B0=29 End_B1=29
9079 20:12:06.935650 30, 0x0, End_B0=30 End_B1=30
9080 20:12:06.939906 31, 0x4141, End_B0=30 End_B1=30
9081 20:12:06.942430 Byte0 end_step=30 best_step=27
9082 20:12:06.945711 Byte1 end_step=30 best_step=27
9083 20:12:06.949024 Byte0 TX OE(2T, 0.5T) = (3, 3)
9084 20:12:06.949149 Byte1 TX OE(2T, 0.5T) = (3, 3)
9085 20:12:06.952950
9086 20:12:06.953074
9087 20:12:06.958628 [DQSOSCAuto] RK1, (LSB)MR18= 0x1116, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9088 20:12:06.962492 CH1 RK1: MR19=303, MR18=1116
9089 20:12:06.968899 CH1_RK1: MR19=0x303, MR18=0x1116, DQSOSC=398, MR23=63, INC=23, DEC=15
9090 20:12:06.972526 [RxdqsGatingPostProcess] freq 1600
9091 20:12:06.975580 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9092 20:12:06.978813 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 20:12:06.982156 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 20:12:06.985449 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 20:12:06.988660 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 20:12:06.992041 best DQS0 dly(2T, 0.5T) = (1, 1)
9097 20:12:06.995296 best DQS1 dly(2T, 0.5T) = (1, 1)
9098 20:12:06.999007 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9099 20:12:07.002341 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9100 20:12:07.006009 Pre-setting of DQS Precalculation
9101 20:12:07.009000 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9102 20:12:07.015493 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9103 20:12:07.022033 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 20:12:07.022156
9105 20:12:07.022269
9106 20:12:07.025891 [Calibration Summary] 3200 Mbps
9107 20:12:07.029074 CH 0, Rank 0
9108 20:12:07.029195 SW Impedance : PASS
9109 20:12:07.032781 DUTY Scan : NO K
9110 20:12:07.035852 ZQ Calibration : PASS
9111 20:12:07.035974 Jitter Meter : NO K
9112 20:12:07.038937 CBT Training : PASS
9113 20:12:07.042268 Write leveling : PASS
9114 20:12:07.042391 RX DQS gating : PASS
9115 20:12:07.045615 RX DQ/DQS(RDDQC) : PASS
9116 20:12:07.048700 TX DQ/DQS : PASS
9117 20:12:07.048825 RX DATLAT : PASS
9118 20:12:07.052145 RX DQ/DQS(Engine): PASS
9119 20:12:07.052268 TX OE : PASS
9120 20:12:07.055390 All Pass.
9121 20:12:07.055506
9122 20:12:07.055614 CH 0, Rank 1
9123 20:12:07.058963 SW Impedance : PASS
9124 20:12:07.059084 DUTY Scan : NO K
9125 20:12:07.062381 ZQ Calibration : PASS
9126 20:12:07.065232 Jitter Meter : NO K
9127 20:12:07.065352 CBT Training : PASS
9128 20:12:07.069292 Write leveling : PASS
9129 20:12:07.072137 RX DQS gating : PASS
9130 20:12:07.072259 RX DQ/DQS(RDDQC) : PASS
9131 20:12:07.075365 TX DQ/DQS : PASS
9132 20:12:07.078830 RX DATLAT : PASS
9133 20:12:07.078948 RX DQ/DQS(Engine): PASS
9134 20:12:07.082176 TX OE : PASS
9135 20:12:07.082298 All Pass.
9136 20:12:07.082431
9137 20:12:07.085415 CH 1, Rank 0
9138 20:12:07.085540 SW Impedance : PASS
9139 20:12:07.089060 DUTY Scan : NO K
9140 20:12:07.092144 ZQ Calibration : PASS
9141 20:12:07.092266 Jitter Meter : NO K
9142 20:12:07.096076 CBT Training : PASS
9143 20:12:07.096197 Write leveling : PASS
9144 20:12:07.098982 RX DQS gating : PASS
9145 20:12:07.102151 RX DQ/DQS(RDDQC) : PASS
9146 20:12:07.102273 TX DQ/DQS : PASS
9147 20:12:07.106084 RX DATLAT : PASS
9148 20:12:07.109293 RX DQ/DQS(Engine): PASS
9149 20:12:07.109414 TX OE : PASS
9150 20:12:07.112086 All Pass.
9151 20:12:07.112209
9152 20:12:07.112322 CH 1, Rank 1
9153 20:12:07.115766 SW Impedance : PASS
9154 20:12:07.115889 DUTY Scan : NO K
9155 20:12:07.118947 ZQ Calibration : PASS
9156 20:12:07.122683 Jitter Meter : NO K
9157 20:12:07.122804 CBT Training : PASS
9158 20:12:07.125636 Write leveling : PASS
9159 20:12:07.128839 RX DQS gating : PASS
9160 20:12:07.128962 RX DQ/DQS(RDDQC) : PASS
9161 20:12:07.132965 TX DQ/DQS : PASS
9162 20:12:07.133089 RX DATLAT : PASS
9163 20:12:07.135547 RX DQ/DQS(Engine): PASS
9164 20:12:07.138728 TX OE : PASS
9165 20:12:07.138850 All Pass.
9166 20:12:07.138964
9167 20:12:07.142433 DramC Write-DBI on
9168 20:12:07.142568 PER_BANK_REFRESH: Hybrid Mode
9169 20:12:07.145905 TX_TRACKING: ON
9170 20:12:07.155736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9171 20:12:07.162487 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9172 20:12:07.168884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9173 20:12:07.172756 [FAST_K] Save calibration result to emmc
9174 20:12:07.176187 sync common calibartion params.
9175 20:12:07.178729 sync cbt_mode0:1, 1:1
9176 20:12:07.178850 dram_init: ddr_geometry: 2
9177 20:12:07.182467 dram_init: ddr_geometry: 2
9178 20:12:07.185874 dram_init: ddr_geometry: 2
9179 20:12:07.189036 0:dram_rank_size:100000000
9180 20:12:07.189159 1:dram_rank_size:100000000
9181 20:12:07.195982 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9182 20:12:07.198861 DFS_SHUFFLE_HW_MODE: ON
9183 20:12:07.202158 dramc_set_vcore_voltage set vcore to 725000
9184 20:12:07.202280 Read voltage for 1600, 0
9185 20:12:07.205799 Vio18 = 0
9186 20:12:07.205921 Vcore = 725000
9187 20:12:07.206032 Vdram = 0
9188 20:12:07.208924 Vddq = 0
9189 20:12:07.209048 Vmddr = 0
9190 20:12:07.212461 switch to 3200 Mbps bootup
9191 20:12:07.212582 [DramcRunTimeConfig]
9192 20:12:07.212695 PHYPLL
9193 20:12:07.215705 DPM_CONTROL_AFTERK: ON
9194 20:12:07.219659 PER_BANK_REFRESH: ON
9195 20:12:07.219782 REFRESH_OVERHEAD_REDUCTION: ON
9196 20:12:07.222586 CMD_PICG_NEW_MODE: OFF
9197 20:12:07.226528 XRTWTW_NEW_MODE: ON
9198 20:12:07.226652 XRTRTR_NEW_MODE: ON
9199 20:12:07.229277 TX_TRACKING: ON
9200 20:12:07.229400 RDSEL_TRACKING: OFF
9201 20:12:07.233353 DQS Precalculation for DVFS: ON
9202 20:12:07.233476 RX_TRACKING: OFF
9203 20:12:07.236160 HW_GATING DBG: ON
9204 20:12:07.236281 ZQCS_ENABLE_LP4: ON
9205 20:12:07.239407 RX_PICG_NEW_MODE: ON
9206 20:12:07.242525 TX_PICG_NEW_MODE: ON
9207 20:12:07.242650 ENABLE_RX_DCM_DPHY: ON
9208 20:12:07.245815 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9209 20:12:07.249310 DUMMY_READ_FOR_TRACKING: OFF
9210 20:12:07.252482 !!! SPM_CONTROL_AFTERK: OFF
9211 20:12:07.252616 !!! SPM could not control APHY
9212 20:12:07.256320 IMPEDANCE_TRACKING: ON
9213 20:12:07.259290 TEMP_SENSOR: ON
9214 20:12:07.259413 HW_SAVE_FOR_SR: OFF
9215 20:12:07.262353 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9216 20:12:07.265797 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9217 20:12:07.268987 Read ODT Tracking: ON
9218 20:12:07.269111 Refresh Rate DeBounce: ON
9219 20:12:07.272452 DFS_NO_QUEUE_FLUSH: ON
9220 20:12:07.276094 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9221 20:12:07.279332 ENABLE_DFS_RUNTIME_MRW: OFF
9222 20:12:07.279451 DDR_RESERVE_NEW_MODE: ON
9223 20:12:07.282792 MR_CBT_SWITCH_FREQ: ON
9224 20:12:07.285810 =========================
9225 20:12:07.303857 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9226 20:12:07.307303 dram_init: ddr_geometry: 2
9227 20:12:07.325651 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9228 20:12:07.328544 dram_init: dram init end (result: 0)
9229 20:12:07.335147 DRAM-K: Full calibration passed in 24593 msecs
9230 20:12:07.338465 MRC: failed to locate region type 0.
9231 20:12:07.338587 DRAM rank0 size:0x100000000,
9232 20:12:07.342447 DRAM rank1 size=0x100000000
9233 20:12:07.352131 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9234 20:12:07.358254 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9235 20:12:07.365805 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9236 20:12:07.371894 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9237 20:12:07.375095 DRAM rank0 size:0x100000000,
9238 20:12:07.378951 DRAM rank1 size=0x100000000
9239 20:12:07.379073 CBMEM:
9240 20:12:07.382267 IMD: root @ 0xfffff000 254 entries.
9241 20:12:07.385258 IMD: root @ 0xffffec00 62 entries.
9242 20:12:07.388721 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9243 20:12:07.391846 WARNING: RO_VPD is uninitialized or empty.
9244 20:12:07.398529 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9245 20:12:07.405028 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9246 20:12:07.418270 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9247 20:12:07.429822 BS: romstage times (exec / console): total (unknown) / 24094 ms
9248 20:12:07.429903
9249 20:12:07.429967
9250 20:12:07.439587 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9251 20:12:07.442797 ARM64: Exception handlers installed.
9252 20:12:07.446149 ARM64: Testing exception
9253 20:12:07.449422 ARM64: Done test exception
9254 20:12:07.449503 Enumerating buses...
9255 20:12:07.452730 Show all devs... Before device enumeration.
9256 20:12:07.456086 Root Device: enabled 1
9257 20:12:07.460193 CPU_CLUSTER: 0: enabled 1
9258 20:12:07.460273 CPU: 00: enabled 1
9259 20:12:07.463170 Compare with tree...
9260 20:12:07.463250 Root Device: enabled 1
9261 20:12:07.466563 CPU_CLUSTER: 0: enabled 1
9262 20:12:07.469538 CPU: 00: enabled 1
9263 20:12:07.469619 Root Device scanning...
9264 20:12:07.473438 scan_static_bus for Root Device
9265 20:12:07.476343 CPU_CLUSTER: 0 enabled
9266 20:12:07.479639 scan_static_bus for Root Device done
9267 20:12:07.482981 scan_bus: bus Root Device finished in 8 msecs
9268 20:12:07.483061 done
9269 20:12:07.489973 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9270 20:12:07.493335 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9271 20:12:07.496308 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9272 20:12:07.503434 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9273 20:12:07.506852 Allocating resources...
9274 20:12:07.506932 Reading resources...
9275 20:12:07.510243 Root Device read_resources bus 0 link: 0
9276 20:12:07.513398 DRAM rank0 size:0x100000000,
9277 20:12:07.516818 DRAM rank1 size=0x100000000
9278 20:12:07.519978 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9279 20:12:07.523341 CPU: 00 missing read_resources
9280 20:12:07.526538 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9281 20:12:07.530271 Root Device read_resources bus 0 link: 0 done
9282 20:12:07.533525 Done reading resources.
9283 20:12:07.540325 Show resources in subtree (Root Device)...After reading.
9284 20:12:07.544025 Root Device child on link 0 CPU_CLUSTER: 0
9285 20:12:07.546841 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 20:12:07.553963 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 20:12:07.557414 CPU: 00
9288 20:12:07.560023 Root Device assign_resources, bus 0 link: 0
9289 20:12:07.563427 CPU_CLUSTER: 0 missing set_resources
9290 20:12:07.567044 Root Device assign_resources, bus 0 link: 0 done
9291 20:12:07.570283 Done setting resources.
9292 20:12:07.576648 Show resources in subtree (Root Device)...After assigning values.
9293 20:12:07.580170 Root Device child on link 0 CPU_CLUSTER: 0
9294 20:12:07.584061 CPU_CLUSTER: 0 child on link 0 CPU: 00
9295 20:12:07.590266 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9296 20:12:07.593563 CPU: 00
9297 20:12:07.593645 Done allocating resources.
9298 20:12:07.600771 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9299 20:12:07.603607 Enabling resources...
9300 20:12:07.603687 done.
9301 20:12:07.607023 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9302 20:12:07.610536 Initializing devices...
9303 20:12:07.610616 Root Device init
9304 20:12:07.613989 init hardware done!
9305 20:12:07.614069 0x00000018: ctrlr->caps
9306 20:12:07.616852 52.000 MHz: ctrlr->f_max
9307 20:12:07.620329 0.400 MHz: ctrlr->f_min
9308 20:12:07.623801 0x40ff8080: ctrlr->voltages
9309 20:12:07.623883 sclk: 390625
9310 20:12:07.623947 Bus Width = 1
9311 20:12:07.627361 sclk: 390625
9312 20:12:07.627441 Bus Width = 1
9313 20:12:07.630062 Early init status = 3
9314 20:12:07.633908 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9315 20:12:07.637204 in-header: 03 fc 00 00 01 00 00 00
9316 20:12:07.640531 in-data: 00
9317 20:12:07.643811 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9318 20:12:07.648423 in-header: 03 fd 00 00 00 00 00 00
9319 20:12:07.651777 in-data:
9320 20:12:07.654858 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9321 20:12:07.658987 in-header: 03 fc 00 00 01 00 00 00
9322 20:12:07.661920 in-data: 00
9323 20:12:07.665524 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9324 20:12:07.669967 in-header: 03 fd 00 00 00 00 00 00
9325 20:12:07.672891 in-data:
9326 20:12:07.676283 [SSUSB] Setting up USB HOST controller...
9327 20:12:07.679995 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9328 20:12:07.683205 [SSUSB] phy power-on done.
9329 20:12:07.686775 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9330 20:12:07.693319 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9331 20:12:07.696521 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9332 20:12:07.703455 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9333 20:12:07.709846 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9334 20:12:07.716843 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9335 20:12:07.722987 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9336 20:12:07.729480 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9337 20:12:07.729561 SPM: binary array size = 0x9dc
9338 20:12:07.736580 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9339 20:12:07.742936 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9340 20:12:07.749338 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9341 20:12:07.752860 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9342 20:12:07.756038 configure_display: Starting display init
9343 20:12:07.792801 anx7625_power_on_init: Init interface.
9344 20:12:07.795885 anx7625_disable_pd_protocol: Disabled PD feature.
9345 20:12:07.799749 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9346 20:12:07.827208 anx7625_start_dp_work: Secure OCM version=00
9347 20:12:07.830866 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9348 20:12:07.845536 sp_tx_get_edid_block: EDID Block = 1
9349 20:12:07.947991 Extracted contents:
9350 20:12:07.951238 header: 00 ff ff ff ff ff ff 00
9351 20:12:07.954237 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9352 20:12:07.957734 version: 01 04
9353 20:12:07.961121 basic params: 95 1f 11 78 0a
9354 20:12:07.964355 chroma info: 76 90 94 55 54 90 27 21 50 54
9355 20:12:07.967619 established: 00 00 00
9356 20:12:07.974342 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9357 20:12:07.977476 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9358 20:12:07.984322 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 20:12:07.990789 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9360 20:12:07.997803 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9361 20:12:08.000952 extensions: 00
9362 20:12:08.001033 checksum: fb
9363 20:12:08.001096
9364 20:12:08.004373 Manufacturer: IVO Model 57d Serial Number 0
9365 20:12:08.007497 Made week 0 of 2020
9366 20:12:08.007582 EDID version: 1.4
9367 20:12:08.011181 Digital display
9368 20:12:08.014230 6 bits per primary color channel
9369 20:12:08.014338 DisplayPort interface
9370 20:12:08.017602 Maximum image size: 31 cm x 17 cm
9371 20:12:08.021320 Gamma: 220%
9372 20:12:08.021401 Check DPMS levels
9373 20:12:08.024245 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9374 20:12:08.027967 First detailed timing is preferred timing
9375 20:12:08.030796 Established timings supported:
9376 20:12:08.034286 Standard timings supported:
9377 20:12:08.034392 Detailed timings
9378 20:12:08.040922 Hex of detail: 383680a07038204018303c0035ae10000019
9379 20:12:08.044287 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9380 20:12:08.050950 0780 0798 07c8 0820 hborder 0
9381 20:12:08.054074 0438 043b 0447 0458 vborder 0
9382 20:12:08.057986 -hsync -vsync
9383 20:12:08.058067 Did detailed timing
9384 20:12:08.060646 Hex of detail: 000000000000000000000000000000000000
9385 20:12:08.064059 Manufacturer-specified data, tag 0
9386 20:12:08.071145 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9387 20:12:08.071226 ASCII string: InfoVision
9388 20:12:08.077867 Hex of detail: 000000fe00523134304e574635205248200a
9389 20:12:08.080483 ASCII string: R140NWF5 RH
9390 20:12:08.080596 Checksum
9391 20:12:08.080660 Checksum: 0xfb (valid)
9392 20:12:08.087610 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9393 20:12:08.090489 DSI data_rate: 832800000 bps
9394 20:12:08.093915 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9395 20:12:08.100914 anx7625_parse_edid: pixelclock(138800).
9396 20:12:08.103997 hactive(1920), hsync(48), hfp(24), hbp(88)
9397 20:12:08.107225 vactive(1080), vsync(12), vfp(3), vbp(17)
9398 20:12:08.110663 anx7625_dsi_config: config dsi.
9399 20:12:08.117312 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9400 20:12:08.130009 anx7625_dsi_config: success to config DSI
9401 20:12:08.133394 anx7625_dp_start: MIPI phy setup OK.
9402 20:12:08.136782 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9403 20:12:08.140134 mtk_ddp_mode_set invalid vrefresh 60
9404 20:12:08.143299 main_disp_path_setup
9405 20:12:08.143379 ovl_layer_smi_id_en
9406 20:12:08.146633 ovl_layer_smi_id_en
9407 20:12:08.146728 ccorr_config
9408 20:12:08.146792 aal_config
9409 20:12:08.149900 gamma_config
9410 20:12:08.149980 postmask_config
9411 20:12:08.153598 dither_config
9412 20:12:08.156589 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9413 20:12:08.163528 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9414 20:12:08.166824 Root Device init finished in 551 msecs
9415 20:12:08.166909 CPU_CLUSTER: 0 init
9416 20:12:08.176488 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9417 20:12:08.180163 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9418 20:12:08.183807 APU_MBOX 0x190000b0 = 0x10001
9419 20:12:08.186217 APU_MBOX 0x190001b0 = 0x10001
9420 20:12:08.189712 APU_MBOX 0x190005b0 = 0x10001
9421 20:12:08.193656 APU_MBOX 0x190006b0 = 0x10001
9422 20:12:08.196597 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9423 20:12:08.209168 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9424 20:12:08.221499 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9425 20:12:08.227733 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9426 20:12:08.239552 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9427 20:12:08.248684 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9428 20:12:08.251852 CPU_CLUSTER: 0 init finished in 81 msecs
9429 20:12:08.255172 Devices initialized
9430 20:12:08.258560 Show all devs... After init.
9431 20:12:08.258642 Root Device: enabled 1
9432 20:12:08.262035 CPU_CLUSTER: 0: enabled 1
9433 20:12:08.265607 CPU: 00: enabled 1
9434 20:12:08.269308 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9435 20:12:08.272267 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9436 20:12:08.275464 ELOG: NV offset 0x57f000 size 0x1000
9437 20:12:08.282271 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9438 20:12:08.288544 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9439 20:12:08.291734 ELOG: Event(17) added with size 13 at 2024-03-03 20:12:08 UTC
9440 20:12:08.295297 out: cmd=0x121: 03 db 21 01 00 00 00 00
9441 20:12:08.299176 in-header: 03 c8 00 00 2c 00 00 00
9442 20:12:08.312310 in-data: 97 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9443 20:12:08.319321 ELOG: Event(A1) added with size 10 at 2024-03-03 20:12:08 UTC
9444 20:12:08.325500 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9445 20:12:08.332288 ELOG: Event(A0) added with size 9 at 2024-03-03 20:12:08 UTC
9446 20:12:08.335693 elog_add_boot_reason: Logged dev mode boot
9447 20:12:08.338859 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9448 20:12:08.342140 Finalize devices...
9449 20:12:08.342221 Devices finalized
9450 20:12:08.348817 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9451 20:12:08.352794 Writing coreboot table at 0xffe64000
9452 20:12:08.355354 0. 000000000010a000-0000000000113fff: RAMSTAGE
9453 20:12:08.358863 1. 0000000040000000-00000000400fffff: RAM
9454 20:12:08.362296 2. 0000000040100000-000000004032afff: RAMSTAGE
9455 20:12:08.368775 3. 000000004032b000-00000000545fffff: RAM
9456 20:12:08.372274 4. 0000000054600000-000000005465ffff: BL31
9457 20:12:08.375926 5. 0000000054660000-00000000ffe63fff: RAM
9458 20:12:08.378896 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9459 20:12:08.385623 7. 0000000100000000-000000023fffffff: RAM
9460 20:12:08.385704 Passing 5 GPIOs to payload:
9461 20:12:08.392174 NAME | PORT | POLARITY | VALUE
9462 20:12:08.395887 EC in RW | 0x000000aa | low | undefined
9463 20:12:08.402792 EC interrupt | 0x00000005 | low | undefined
9464 20:12:08.405834 TPM interrupt | 0x000000ab | high | undefined
9465 20:12:08.408750 SD card detect | 0x00000011 | high | undefined
9466 20:12:08.415893 speaker enable | 0x00000093 | high | undefined
9467 20:12:08.418971 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9468 20:12:08.422225 in-header: 03 f9 00 00 02 00 00 00
9469 20:12:08.422306 in-data: 02 00
9470 20:12:08.425519 ADC[4]: Raw value=900590 ID=7
9471 20:12:08.428742 ADC[3]: Raw value=213336 ID=1
9472 20:12:08.428823 RAM Code: 0x71
9473 20:12:08.432737 ADC[6]: Raw value=74557 ID=0
9474 20:12:08.435564 ADC[5]: Raw value=211860 ID=1
9475 20:12:08.435645 SKU Code: 0x1
9476 20:12:08.442218 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum eb57
9477 20:12:08.445844 coreboot table: 964 bytes.
9478 20:12:08.448995 IMD ROOT 0. 0xfffff000 0x00001000
9479 20:12:08.452448 IMD SMALL 1. 0xffffe000 0x00001000
9480 20:12:08.455363 RO MCACHE 2. 0xffffc000 0x00001104
9481 20:12:08.458976 CONSOLE 3. 0xfff7c000 0x00080000
9482 20:12:08.462351 FMAP 4. 0xfff7b000 0x00000452
9483 20:12:08.465351 TIME STAMP 5. 0xfff7a000 0x00000910
9484 20:12:08.468988 VBOOT WORK 6. 0xfff66000 0x00014000
9485 20:12:08.472491 RAMOOPS 7. 0xffe66000 0x00100000
9486 20:12:08.475702 COREBOOT 8. 0xffe64000 0x00002000
9487 20:12:08.475783 IMD small region:
9488 20:12:08.478860 IMD ROOT 0. 0xffffec00 0x00000400
9489 20:12:08.482610 VPD 1. 0xffffeb80 0x0000006c
9490 20:12:08.485664 MMC STATUS 2. 0xffffeb60 0x00000004
9491 20:12:08.492028 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9492 20:12:08.492110 Probing TPM: done!
9493 20:12:08.499041 Connected to device vid:did:rid of 1ae0:0028:00
9494 20:12:08.505520 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9495 20:12:08.509227 Initialized TPM device CR50 revision 0
9496 20:12:08.513907 Checking cr50 for pending updates
9497 20:12:08.518347 Reading cr50 TPM mode
9498 20:12:08.527352 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9499 20:12:08.533906 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9500 20:12:08.573773 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9501 20:12:08.577206 Checking segment from ROM address 0x40100000
9502 20:12:08.580371 Checking segment from ROM address 0x4010001c
9503 20:12:08.587765 Loading segment from ROM address 0x40100000
9504 20:12:08.587846 code (compression=0)
9505 20:12:08.594138 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9506 20:12:08.604207 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9507 20:12:08.604288 it's not compressed!
9508 20:12:08.610723 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9509 20:12:08.614259 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9510 20:12:08.634218 Loading segment from ROM address 0x4010001c
9511 20:12:08.634299 Entry Point 0x80000000
9512 20:12:08.637598 Loaded segments
9513 20:12:08.641340 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9514 20:12:08.647963 Jumping to boot code at 0x80000000(0xffe64000)
9515 20:12:08.654684 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9516 20:12:08.661019 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9517 20:12:08.668927 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9518 20:12:08.672192 Checking segment from ROM address 0x40100000
9519 20:12:08.675880 Checking segment from ROM address 0x4010001c
9520 20:12:08.682047 Loading segment from ROM address 0x40100000
9521 20:12:08.682157 code (compression=1)
9522 20:12:08.688921 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9523 20:12:08.699316 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9524 20:12:08.699401 using LZMA
9525 20:12:08.707026 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9526 20:12:08.714010 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9527 20:12:08.717287 Loading segment from ROM address 0x4010001c
9528 20:12:08.717367 Entry Point 0x54601000
9529 20:12:08.721014 Loaded segments
9530 20:12:08.724107 NOTICE: MT8192 bl31_setup
9531 20:12:08.730452 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9532 20:12:08.734122 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9533 20:12:08.737301 WARNING: region 0:
9534 20:12:08.740623 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 20:12:08.740703 WARNING: region 1:
9536 20:12:08.747842 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9537 20:12:08.747923 WARNING: region 2:
9538 20:12:08.754425 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9539 20:12:08.758360 WARNING: region 3:
9540 20:12:08.761098 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 20:12:08.764360 WARNING: region 4:
9542 20:12:08.768929 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 20:12:08.770840 WARNING: region 5:
9544 20:12:08.774125 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 20:12:08.777715 WARNING: region 6:
9546 20:12:08.781016 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 20:12:08.781119 WARNING: region 7:
9548 20:12:08.787759 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 20:12:08.795103 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9550 20:12:08.797816 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9551 20:12:08.800981 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9552 20:12:08.807744 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9553 20:12:08.811885 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9554 20:12:08.814693 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9555 20:12:08.821557 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9556 20:12:08.824412 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9557 20:12:08.828061 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9558 20:12:08.834859 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9559 20:12:08.837980 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9560 20:12:08.841051 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9561 20:12:08.848349 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9562 20:12:08.851368 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9563 20:12:08.858084 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9564 20:12:08.861497 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9565 20:12:08.864538 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9566 20:12:08.871458 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9567 20:12:08.875454 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9568 20:12:08.878101 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9569 20:12:08.885022 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9570 20:12:08.888147 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9571 20:12:08.894716 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9572 20:12:08.898419 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9573 20:12:08.901773 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9574 20:12:08.908390 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9575 20:12:08.911826 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9576 20:12:08.915204 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9577 20:12:08.921849 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9578 20:12:08.925203 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9579 20:12:08.931979 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9580 20:12:08.935041 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9581 20:12:08.938375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9582 20:12:08.941892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9583 20:12:08.949370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9584 20:12:08.952604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9585 20:12:08.955540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9586 20:12:08.958999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9587 20:12:08.965534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9588 20:12:08.969276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9589 20:12:08.972443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9590 20:12:08.975430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9591 20:12:08.982234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9592 20:12:08.986068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9593 20:12:08.988942 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9594 20:12:08.992817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9595 20:12:08.999620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9596 20:12:09.002359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9597 20:12:09.005964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9598 20:12:09.012715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9599 20:12:09.015892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9600 20:12:09.019003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9601 20:12:09.025541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9602 20:12:09.029469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9603 20:12:09.035805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9604 20:12:09.039190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9605 20:12:09.045825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9606 20:12:09.049906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9607 20:12:09.052783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9608 20:12:09.059531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9609 20:12:09.062527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9610 20:12:09.069571 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9611 20:12:09.072840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9612 20:12:09.079483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9613 20:12:09.083257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9614 20:12:09.086213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9615 20:12:09.093223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9616 20:12:09.096765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9617 20:12:09.103413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9618 20:12:09.106054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9619 20:12:09.109774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9620 20:12:09.116340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9621 20:12:09.119498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9622 20:12:09.126508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9623 20:12:09.129572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9624 20:12:09.136224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9625 20:12:09.139880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9626 20:12:09.143203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9627 20:12:09.150195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9628 20:12:09.153433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9629 20:12:09.159921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9630 20:12:09.163303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9631 20:12:09.170114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9632 20:12:09.173179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9633 20:12:09.177140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9634 20:12:09.183138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9635 20:12:09.186782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9636 20:12:09.193318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9637 20:12:09.196978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9638 20:12:09.203200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9639 20:12:09.206643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9640 20:12:09.209973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9641 20:12:09.216690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9642 20:12:09.220300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9643 20:12:09.226896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9644 20:12:09.230645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9645 20:12:09.233758 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9646 20:12:09.240492 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9647 20:12:09.243747 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9648 20:12:09.247389 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9649 20:12:09.250233 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9650 20:12:09.257495 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9651 20:12:09.260792 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9652 20:12:09.267593 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9653 20:12:09.270645 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9654 20:12:09.273902 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9655 20:12:09.280397 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9656 20:12:09.283941 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9657 20:12:09.287513 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9658 20:12:09.294066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9659 20:12:09.297425 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9660 20:12:09.303953 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9661 20:12:09.307554 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9662 20:12:09.310639 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9663 20:12:09.317264 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9664 20:12:09.320723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9665 20:12:09.323895 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9666 20:12:09.330591 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9667 20:12:09.334282 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9668 20:12:09.337800 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9669 20:12:09.340966 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9670 20:12:09.348209 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9671 20:12:09.350936 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9672 20:12:09.354243 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9673 20:12:09.361481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9674 20:12:09.364547 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9675 20:12:09.367683 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9676 20:12:09.374460 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9677 20:12:09.377806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9678 20:12:09.384357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9679 20:12:09.387930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9680 20:12:09.391126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9681 20:12:09.397992 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9682 20:12:09.401143 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9683 20:12:09.404728 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9684 20:12:09.411387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9685 20:12:09.415020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9686 20:12:09.418052 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9687 20:12:09.424748 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9688 20:12:09.427920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9689 20:12:09.434741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9690 20:12:09.438485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9691 20:12:09.441247 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9692 20:12:09.447877 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9693 20:12:09.451534 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9694 20:12:09.454800 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9695 20:12:09.461731 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9696 20:12:09.464628 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9697 20:12:09.471405 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9698 20:12:09.475094 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9699 20:12:09.478644 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9700 20:12:09.485069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9701 20:12:09.488513 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9702 20:12:09.491905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9703 20:12:09.498332 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9704 20:12:09.501595 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9705 20:12:09.508827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9706 20:12:09.511983 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9707 20:12:09.515128 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9708 20:12:09.521834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9709 20:12:09.525122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9710 20:12:09.532093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9711 20:12:09.535423 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9712 20:12:09.538684 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9713 20:12:09.545167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9714 20:12:09.548485 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9715 20:12:09.552305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9716 20:12:09.558682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9717 20:12:09.562450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9718 20:12:09.569103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9719 20:12:09.572006 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9720 20:12:09.575937 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9721 20:12:09.582232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9722 20:12:09.585865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9723 20:12:09.589232 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9724 20:12:09.595698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9725 20:12:09.598827 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9726 20:12:09.605886 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9727 20:12:09.609268 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9728 20:12:09.612189 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9729 20:12:09.618974 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9730 20:12:09.622556 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9731 20:12:09.625638 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9732 20:12:09.632469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9733 20:12:09.635891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9734 20:12:09.642102 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9735 20:12:09.646133 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9736 20:12:09.649510 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9737 20:12:09.655741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9738 20:12:09.659331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9739 20:12:09.666470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9740 20:12:09.669393 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9741 20:12:09.672718 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9742 20:12:09.679237 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9743 20:12:09.683312 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9744 20:12:09.689376 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9745 20:12:09.692822 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9746 20:12:09.695935 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9747 20:12:09.702794 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9748 20:12:09.705973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9749 20:12:09.712707 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9750 20:12:09.715912 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9751 20:12:09.719624 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9752 20:12:09.725935 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9753 20:12:09.729317 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9754 20:12:09.736118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9755 20:12:09.739828 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9756 20:12:09.742800 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9757 20:12:09.749129 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9758 20:12:09.752678 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9759 20:12:09.759265 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9760 20:12:09.762808 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9761 20:12:09.769233 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9762 20:12:09.772671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9763 20:12:09.776287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9764 20:12:09.782552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9765 20:12:09.786236 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9766 20:12:09.793409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9767 20:12:09.796312 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9768 20:12:09.800081 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9769 20:12:09.806727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9770 20:12:09.809636 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9771 20:12:09.815992 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9772 20:12:09.819132 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9773 20:12:09.826175 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9774 20:12:09.829258 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9775 20:12:09.833076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9776 20:12:09.839253 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9777 20:12:09.843423 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9778 20:12:09.846354 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9779 20:12:09.853300 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9780 20:12:09.855708 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9781 20:12:09.859163 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9782 20:12:09.863110 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9783 20:12:09.869673 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9784 20:12:09.872637 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9785 20:12:09.875753 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9786 20:12:09.882987 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9787 20:12:09.885785 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9788 20:12:09.889532 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9789 20:12:09.896026 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9790 20:12:09.899574 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9791 20:12:09.905789 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9792 20:12:09.909086 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9793 20:12:09.912250 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9794 20:12:09.919621 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9795 20:12:09.922635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9796 20:12:09.925782 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9797 20:12:09.932396 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9798 20:12:09.936160 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9799 20:12:09.938956 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9800 20:12:09.946051 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9801 20:12:09.949178 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9802 20:12:09.952172 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9803 20:12:09.959705 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9804 20:12:09.962162 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9805 20:12:09.969053 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9806 20:12:09.972258 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9807 20:12:09.975867 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9808 20:12:09.982108 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9809 20:12:09.985834 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9810 20:12:09.989054 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9811 20:12:09.996111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9812 20:12:09.999415 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9813 20:12:10.002277 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9814 20:12:10.008945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9815 20:12:10.012809 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9816 20:12:10.019303 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9817 20:12:10.022597 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9818 20:12:10.025734 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9819 20:12:10.029104 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9820 20:12:10.032310 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9821 20:12:10.039505 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9822 20:12:10.042725 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9823 20:12:10.045806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9824 20:12:10.049328 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9825 20:12:10.056069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9826 20:12:10.059697 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9827 20:12:10.062665 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9828 20:12:10.066054 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9829 20:12:10.073240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9830 20:12:10.076474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9831 20:12:10.079311 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9832 20:12:10.085930 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9833 20:12:10.089554 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9834 20:12:10.096186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9835 20:12:10.099489 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9836 20:12:10.103128 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9837 20:12:10.109287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9838 20:12:10.113074 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9839 20:12:10.119500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9840 20:12:10.122662 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9841 20:12:10.126355 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9842 20:12:10.133063 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9843 20:12:10.136216 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9844 20:12:10.142876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9845 20:12:10.146014 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9846 20:12:10.149459 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9847 20:12:10.156836 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9848 20:12:10.160460 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9849 20:12:10.166187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9850 20:12:10.169697 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9851 20:12:10.172786 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9852 20:12:10.179839 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9853 20:12:10.182804 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9854 20:12:10.189781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9855 20:12:10.193465 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9856 20:12:10.196053 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9857 20:12:10.202923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9858 20:12:10.206702 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9859 20:12:10.213162 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9860 20:12:10.216270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9861 20:12:10.219556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9862 20:12:10.226378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9863 20:12:10.229369 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9864 20:12:10.236126 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9865 20:12:10.239721 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9866 20:12:10.243281 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9867 20:12:10.249931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9868 20:12:10.253278 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9869 20:12:10.259519 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9870 20:12:10.262837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9871 20:12:10.266342 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9872 20:12:10.273062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9873 20:12:10.276276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9874 20:12:10.283101 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9875 20:12:10.286642 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9876 20:12:10.289505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9877 20:12:10.296141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9878 20:12:10.299770 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9879 20:12:10.306207 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9880 20:12:10.309713 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9881 20:12:10.312962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9882 20:12:10.319729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9883 20:12:10.322909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9884 20:12:10.329358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9885 20:12:10.333231 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9886 20:12:10.336128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9887 20:12:10.342746 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9888 20:12:10.346358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9889 20:12:10.353120 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9890 20:12:10.356509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9891 20:12:10.359762 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9892 20:12:10.366330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9893 20:12:10.369719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9894 20:12:10.376140 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9895 20:12:10.379745 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9896 20:12:10.383341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9897 20:12:10.389990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9898 20:12:10.392863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9899 20:12:10.399508 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9900 20:12:10.403092 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9901 20:12:10.409958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9902 20:12:10.413222 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9903 20:12:10.416571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9904 20:12:10.423334 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9905 20:12:10.426244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9906 20:12:10.432878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9907 20:12:10.436727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9908 20:12:10.440199 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9909 20:12:10.446604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9910 20:12:10.449746 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9911 20:12:10.456685 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9912 20:12:10.459880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9913 20:12:10.466377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9914 20:12:10.469568 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9915 20:12:10.473481 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9916 20:12:10.479841 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9917 20:12:10.483693 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9918 20:12:10.490126 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9919 20:12:10.493207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9920 20:12:10.499834 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9921 20:12:10.503125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9922 20:12:10.506825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9923 20:12:10.513098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9924 20:12:10.516984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9925 20:12:10.523046 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9926 20:12:10.526659 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9927 20:12:10.529774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9928 20:12:10.536658 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9929 20:12:10.540256 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9930 20:12:10.546404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9931 20:12:10.550589 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9932 20:12:10.556446 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9933 20:12:10.560279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9934 20:12:10.563466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9935 20:12:10.569697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9936 20:12:10.573492 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9937 20:12:10.579965 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9938 20:12:10.583411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9939 20:12:10.590356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9940 20:12:10.593034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9941 20:12:10.599757 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9942 20:12:10.602942 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9943 20:12:10.606990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9944 20:12:10.613207 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9945 20:12:10.616410 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9946 20:12:10.623168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9947 20:12:10.626416 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9948 20:12:10.632947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9949 20:12:10.636434 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9950 20:12:10.639915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9951 20:12:10.646748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9952 20:12:10.650246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9953 20:12:10.656430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9954 20:12:10.659834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9955 20:12:10.663075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9956 20:12:10.669953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9957 20:12:10.673200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9958 20:12:10.680353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9959 20:12:10.684333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9960 20:12:10.689588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9961 20:12:10.693169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9962 20:12:10.700049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9963 20:12:10.703531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9964 20:12:10.709940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9965 20:12:10.713251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9966 20:12:10.719877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9967 20:12:10.723544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9968 20:12:10.730082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9969 20:12:10.733163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9970 20:12:10.739850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9971 20:12:10.743401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9972 20:12:10.749969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9973 20:12:10.753169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9974 20:12:10.759734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9975 20:12:10.763398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9976 20:12:10.770084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9977 20:12:10.773383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9978 20:12:10.780386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9979 20:12:10.783496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9980 20:12:10.790296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9981 20:12:10.793329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9982 20:12:10.799806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9983 20:12:10.803770 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9984 20:12:10.803852 INFO: [APUAPC] vio 0
9985 20:12:10.810567 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9986 20:12:10.814134 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9987 20:12:10.817092 INFO: [APUAPC] D0_APC_0: 0x400510
9988 20:12:10.820956 INFO: [APUAPC] D0_APC_1: 0x0
9989 20:12:10.824002 INFO: [APUAPC] D0_APC_2: 0x1540
9990 20:12:10.827079 INFO: [APUAPC] D0_APC_3: 0x0
9991 20:12:10.830230 INFO: [APUAPC] D1_APC_0: 0xffffffff
9992 20:12:10.833738 INFO: [APUAPC] D1_APC_1: 0xffffffff
9993 20:12:10.837517 INFO: [APUAPC] D1_APC_2: 0x3fffff
9994 20:12:10.841088 INFO: [APUAPC] D1_APC_3: 0x0
9995 20:12:10.844477 INFO: [APUAPC] D2_APC_0: 0xffffffff
9996 20:12:10.847240 INFO: [APUAPC] D2_APC_1: 0xffffffff
9997 20:12:10.850591 INFO: [APUAPC] D2_APC_2: 0x3fffff
9998 20:12:10.853856 INFO: [APUAPC] D2_APC_3: 0x0
9999 20:12:10.856920 INFO: [APUAPC] D3_APC_0: 0xffffffff
10000 20:12:10.860439 INFO: [APUAPC] D3_APC_1: 0xffffffff
10001 20:12:10.863663 INFO: [APUAPC] D3_APC_2: 0x3fffff
10002 20:12:10.863800 INFO: [APUAPC] D3_APC_3: 0x0
10003 20:12:10.870385 INFO: [APUAPC] D4_APC_0: 0xffffffff
10004 20:12:10.873857 INFO: [APUAPC] D4_APC_1: 0xffffffff
10005 20:12:10.877258 INFO: [APUAPC] D4_APC_2: 0x3fffff
10006 20:12:10.877359 INFO: [APUAPC] D4_APC_3: 0x0
10007 20:12:10.880421 INFO: [APUAPC] D5_APC_0: 0xffffffff
10008 20:12:10.884369 INFO: [APUAPC] D5_APC_1: 0xffffffff
10009 20:12:10.887625 INFO: [APUAPC] D5_APC_2: 0x3fffff
10010 20:12:10.890526 INFO: [APUAPC] D5_APC_3: 0x0
10011 20:12:10.894441 INFO: [APUAPC] D6_APC_0: 0xffffffff
10012 20:12:10.897304 INFO: [APUAPC] D6_APC_1: 0xffffffff
10013 20:12:10.900468 INFO: [APUAPC] D6_APC_2: 0x3fffff
10014 20:12:10.903747 INFO: [APUAPC] D6_APC_3: 0x0
10015 20:12:10.906905 INFO: [APUAPC] D7_APC_0: 0xffffffff
10016 20:12:10.910171 INFO: [APUAPC] D7_APC_1: 0xffffffff
10017 20:12:10.913562 INFO: [APUAPC] D7_APC_2: 0x3fffff
10018 20:12:10.917462 INFO: [APUAPC] D7_APC_3: 0x0
10019 20:12:10.920691 INFO: [APUAPC] D8_APC_0: 0xffffffff
10020 20:12:10.924244 INFO: [APUAPC] D8_APC_1: 0xffffffff
10021 20:12:10.927179 INFO: [APUAPC] D8_APC_2: 0x3fffff
10022 20:12:10.930821 INFO: [APUAPC] D8_APC_3: 0x0
10023 20:12:10.933534 INFO: [APUAPC] D9_APC_0: 0xffffffff
10024 20:12:10.936852 INFO: [APUAPC] D9_APC_1: 0xffffffff
10025 20:12:10.940782 INFO: [APUAPC] D9_APC_2: 0x3fffff
10026 20:12:10.943793 INFO: [APUAPC] D9_APC_3: 0x0
10027 20:12:10.947301 INFO: [APUAPC] D10_APC_0: 0xffffffff
10028 20:12:10.950714 INFO: [APUAPC] D10_APC_1: 0xffffffff
10029 20:12:10.953890 INFO: [APUAPC] D10_APC_2: 0x3fffff
10030 20:12:10.957316 INFO: [APUAPC] D10_APC_3: 0x0
10031 20:12:10.960680 INFO: [APUAPC] D11_APC_0: 0xffffffff
10032 20:12:10.964019 INFO: [APUAPC] D11_APC_1: 0xffffffff
10033 20:12:10.966997 INFO: [APUAPC] D11_APC_2: 0x3fffff
10034 20:12:10.970615 INFO: [APUAPC] D11_APC_3: 0x0
10035 20:12:10.973660 INFO: [APUAPC] D12_APC_0: 0xffffffff
10036 20:12:10.977181 INFO: [APUAPC] D12_APC_1: 0xffffffff
10037 20:12:10.980432 INFO: [APUAPC] D12_APC_2: 0x3fffff
10038 20:12:10.984119 INFO: [APUAPC] D12_APC_3: 0x0
10039 20:12:10.987248 INFO: [APUAPC] D13_APC_0: 0xffffffff
10040 20:12:10.990303 INFO: [APUAPC] D13_APC_1: 0xffffffff
10041 20:12:10.994219 INFO: [APUAPC] D13_APC_2: 0x3fffff
10042 20:12:10.997216 INFO: [APUAPC] D13_APC_3: 0x0
10043 20:12:11.000533 INFO: [APUAPC] D14_APC_0: 0xffffffff
10044 20:12:11.003911 INFO: [APUAPC] D14_APC_1: 0xffffffff
10045 20:12:11.006998 INFO: [APUAPC] D14_APC_2: 0x3fffff
10046 20:12:11.010229 INFO: [APUAPC] D14_APC_3: 0x0
10047 20:12:11.014076 INFO: [APUAPC] D15_APC_0: 0xffffffff
10048 20:12:11.016813 INFO: [APUAPC] D15_APC_1: 0xffffffff
10049 20:12:11.020507 INFO: [APUAPC] D15_APC_2: 0x3fffff
10050 20:12:11.023974 INFO: [APUAPC] D15_APC_3: 0x0
10051 20:12:11.026831 INFO: [APUAPC] APC_CON: 0x4
10052 20:12:11.031093 INFO: [NOCDAPC] D0_APC_0: 0x0
10053 20:12:11.033654 INFO: [NOCDAPC] D0_APC_1: 0x0
10054 20:12:11.033735 INFO: [NOCDAPC] D1_APC_0: 0x0
10055 20:12:11.036704 INFO: [NOCDAPC] D1_APC_1: 0xfff
10056 20:12:11.040191 INFO: [NOCDAPC] D2_APC_0: 0x0
10057 20:12:11.043729 INFO: [NOCDAPC] D2_APC_1: 0xfff
10058 20:12:11.046736 INFO: [NOCDAPC] D3_APC_0: 0x0
10059 20:12:11.050627 INFO: [NOCDAPC] D3_APC_1: 0xfff
10060 20:12:11.053627 INFO: [NOCDAPC] D4_APC_0: 0x0
10061 20:12:11.056974 INFO: [NOCDAPC] D4_APC_1: 0xfff
10062 20:12:11.060298 INFO: [NOCDAPC] D5_APC_0: 0x0
10063 20:12:11.063994 INFO: [NOCDAPC] D5_APC_1: 0xfff
10064 20:12:11.064075 INFO: [NOCDAPC] D6_APC_0: 0x0
10065 20:12:11.066680 INFO: [NOCDAPC] D6_APC_1: 0xfff
10066 20:12:11.070276 INFO: [NOCDAPC] D7_APC_0: 0x0
10067 20:12:11.073600 INFO: [NOCDAPC] D7_APC_1: 0xfff
10068 20:12:11.077211 INFO: [NOCDAPC] D8_APC_0: 0x0
10069 20:12:11.080239 INFO: [NOCDAPC] D8_APC_1: 0xfff
10070 20:12:11.084511 INFO: [NOCDAPC] D9_APC_0: 0x0
10071 20:12:11.087175 INFO: [NOCDAPC] D9_APC_1: 0xfff
10072 20:12:11.090089 INFO: [NOCDAPC] D10_APC_0: 0x0
10073 20:12:11.093680 INFO: [NOCDAPC] D10_APC_1: 0xfff
10074 20:12:11.097365 INFO: [NOCDAPC] D11_APC_0: 0x0
10075 20:12:11.100783 INFO: [NOCDAPC] D11_APC_1: 0xfff
10076 20:12:11.100865 INFO: [NOCDAPC] D12_APC_0: 0x0
10077 20:12:11.103632 INFO: [NOCDAPC] D12_APC_1: 0xfff
10078 20:12:11.106840 INFO: [NOCDAPC] D13_APC_0: 0x0
10079 20:12:11.110528 INFO: [NOCDAPC] D13_APC_1: 0xfff
10080 20:12:11.113396 INFO: [NOCDAPC] D14_APC_0: 0x0
10081 20:12:11.116724 INFO: [NOCDAPC] D14_APC_1: 0xfff
10082 20:12:11.120534 INFO: [NOCDAPC] D15_APC_0: 0x0
10083 20:12:11.123728 INFO: [NOCDAPC] D15_APC_1: 0xfff
10084 20:12:11.126757 INFO: [NOCDAPC] APC_CON: 0x4
10085 20:12:11.130583 INFO: [APUAPC] set_apusys_apc done
10086 20:12:11.134015 INFO: [DEVAPC] devapc_init done
10087 20:12:11.136990 INFO: GICv3 without legacy support detected.
10088 20:12:11.140481 INFO: ARM GICv3 driver initialized in EL3
10089 20:12:11.143759 INFO: Maximum SPI INTID supported: 639
10090 20:12:11.150483 INFO: BL31: Initializing runtime services
10091 20:12:11.153774 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10092 20:12:11.157201 INFO: SPM: enable CPC mode
10093 20:12:11.163862 INFO: mcdi ready for mcusys-off-idle and system suspend
10094 20:12:11.167431 INFO: BL31: Preparing for EL3 exit to normal world
10095 20:12:11.170887 INFO: Entry point address = 0x80000000
10096 20:12:11.173713 INFO: SPSR = 0x8
10097 20:12:11.178618
10098 20:12:11.178740
10099 20:12:11.178854
10100 20:12:11.181791 Starting depthcharge on Spherion...
10101 20:12:11.181896
10102 20:12:11.181989 Wipe memory regions:
10103 20:12:11.182078
10104 20:12:11.182926 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10105 20:12:11.183055 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10106 20:12:11.183463 Setting prompt string to ['asurada:']
10107 20:12:11.183572 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10108 20:12:11.184878 [0x00000040000000, 0x00000054600000)
10109 20:12:11.307444
10110 20:12:11.307564 [0x00000054660000, 0x00000080000000)
10111 20:12:11.568235
10112 20:12:11.568377 [0x000000821a7280, 0x000000ffe64000)
10113 20:12:12.313066
10114 20:12:12.313218 [0x00000100000000, 0x00000240000000)
10115 20:12:14.203714
10116 20:12:14.206873 Initializing XHCI USB controller at 0x11200000.
10117 20:12:15.245077
10118 20:12:15.247973 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10119 20:12:15.248112
10120 20:12:15.248225
10121 20:12:15.248334
10122 20:12:15.248695 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 20:12:15.349130 asurada: tftpboot 192.168.201.1 12928089/tftp-deploy-u_hjodma/kernel/image.itb 12928089/tftp-deploy-u_hjodma/kernel/cmdline
10125 20:12:15.349281 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 20:12:15.349393 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10127 20:12:15.353660 tftpboot 192.168.201.1 12928089/tftp-deploy-u_hjodma/kernel/image.itp-deploy-u_hjodma/kernel/cmdline
10128 20:12:15.353745
10129 20:12:15.353810 Waiting for link
10130 20:12:15.514010
10131 20:12:15.514142 R8152: Initializing
10132 20:12:15.514210
10133 20:12:15.517133 Version 6 (ocp_data = 5c30)
10134 20:12:15.517216
10135 20:12:15.521024 R8152: Done initializing
10136 20:12:15.521106
10137 20:12:15.521171 Adding net device
10138 20:12:17.391947
10139 20:12:17.392097 done.
10140 20:12:17.392166
10141 20:12:17.392226 MAC: 00:24:32:30:78:52
10142 20:12:17.392323
10143 20:12:17.395071 Sending DHCP discover... done.
10144 20:12:17.395154
10145 20:12:17.398673 Waiting for reply... done.
10146 20:12:17.398756
10147 20:12:17.402117 Sending DHCP request... done.
10148 20:12:17.402209
10149 20:12:17.406709 Waiting for reply... done.
10150 20:12:17.406791
10151 20:12:17.406856 My ip is 192.168.201.14
10152 20:12:17.406916
10153 20:12:17.409720 The DHCP server ip is 192.168.201.1
10154 20:12:17.409802
10155 20:12:17.416788 TFTP server IP predefined by user: 192.168.201.1
10156 20:12:17.416870
10157 20:12:17.423176 Bootfile predefined by user: 12928089/tftp-deploy-u_hjodma/kernel/image.itb
10158 20:12:17.423259
10159 20:12:17.423325 Sending tftp read request... done.
10160 20:12:17.426166
10161 20:12:17.430256 Waiting for the transfer...
10162 20:12:17.430384
10163 20:12:17.971569 00000000 ################################################################
10164 20:12:17.971712
10165 20:12:18.508701 00080000 ################################################################
10166 20:12:18.508835
10167 20:12:19.034507 00100000 ################################################################
10168 20:12:19.034676
10169 20:12:19.553531 00180000 ################################################################
10170 20:12:19.553676
10171 20:12:20.095547 00200000 ################################################################
10172 20:12:20.095711
10173 20:12:20.640857 00280000 ################################################################
10174 20:12:20.641031
10175 20:12:21.205177 00300000 ################################################################
10176 20:12:21.205345
10177 20:12:21.777469 00380000 ################################################################
10178 20:12:21.777621
10179 20:12:22.328369 00400000 ################################################################
10180 20:12:22.328512
10181 20:12:22.877559 00480000 ################################################################
10182 20:12:22.877705
10183 20:12:23.416567 00500000 ################################################################
10184 20:12:23.416704
10185 20:12:23.943842 00580000 ################################################################
10186 20:12:23.944102
10187 20:12:24.479767 00600000 ################################################################
10188 20:12:24.479990
10189 20:12:25.020135 00680000 ################################################################
10190 20:12:25.020448
10191 20:12:25.548721 00700000 ################################################################
10192 20:12:25.548861
10193 20:12:26.094294 00780000 ################################################################
10194 20:12:26.094506
10195 20:12:26.637246 00800000 ################################################################
10196 20:12:26.637382
10197 20:12:27.203659 00880000 ################################################################
10198 20:12:27.203849
10199 20:12:27.767928 00900000 ################################################################
10200 20:12:27.768065
10201 20:12:28.315328 00980000 ################################################################
10202 20:12:28.315492
10203 20:12:28.892543 00a00000 ################################################################
10204 20:12:28.892686
10205 20:12:29.459726 00a80000 ################################################################
10206 20:12:29.459920
10207 20:12:30.043226 00b00000 ################################################################
10208 20:12:30.043374
10209 20:12:30.606554 00b80000 ################################################################
10210 20:12:30.606775
10211 20:12:31.159289 00c00000 ################################################################
10212 20:12:31.159506
10213 20:12:31.728081 00c80000 ################################################################
10214 20:12:31.728291
10215 20:12:32.253823 00d00000 ################################################################
10216 20:12:32.254034
10217 20:12:32.784479 00d80000 ################################################################
10218 20:12:32.784697
10219 20:12:33.347648 00e00000 ################################################################
10220 20:12:33.347858
10221 20:12:33.923764 00e80000 ################################################################
10222 20:12:33.923915
10223 20:12:34.497813 00f00000 ################################################################
10224 20:12:34.497966
10225 20:12:35.070357 00f80000 ################################################################
10226 20:12:35.070540
10227 20:12:35.647119 01000000 ################################################################
10228 20:12:35.647332
10229 20:12:36.219562 01080000 ################################################################
10230 20:12:36.219771
10231 20:12:36.796119 01100000 ################################################################
10232 20:12:36.796329
10233 20:12:37.362559 01180000 ################################################################
10234 20:12:37.362770
10235 20:12:37.943135 01200000 ################################################################
10236 20:12:37.943343
10237 20:12:38.517531 01280000 ################################################################
10238 20:12:38.517747
10239 20:12:39.079243 01300000 ################################################################
10240 20:12:39.079389
10241 20:12:39.638236 01380000 ################################################################
10242 20:12:39.638383
10243 20:12:40.198582 01400000 ################################################################
10244 20:12:40.198729
10245 20:12:40.757636 01480000 ################################################################
10246 20:12:40.757772
10247 20:12:41.343831 01500000 ################################################################
10248 20:12:41.343959
10249 20:12:41.906173 01580000 ################################################################
10250 20:12:41.906307
10251 20:12:42.488258 01600000 ################################################################
10252 20:12:42.488402
10253 20:12:43.059895 01680000 ################################################################
10254 20:12:43.060041
10255 20:12:43.629124 01700000 ################################################################
10256 20:12:43.629272
10257 20:12:44.187288 01780000 ################################################################
10258 20:12:44.187432
10259 20:12:44.754160 01800000 ################################################################
10260 20:12:44.754307
10261 20:12:45.333982 01880000 ################################################################
10262 20:12:45.334124
10263 20:12:45.876250 01900000 ################################################################
10264 20:12:45.876401
10265 20:12:46.431127 01980000 ################################################################
10266 20:12:46.431321
10267 20:12:46.968191 01a00000 ################################################################
10268 20:12:46.968406
10269 20:12:47.502061 01a80000 ################################################################
10270 20:12:47.502213
10271 20:12:48.045728 01b00000 ################################################################
10272 20:12:48.045861
10273 20:12:48.583743 01b80000 ################################################################
10274 20:12:48.583878
10275 20:12:49.178335 01c00000 ################################################################
10276 20:12:49.178504
10277 20:12:49.217267 01c80000 #### done.
10278 20:12:49.217392
10279 20:12:49.220678 The bootfile was 29915402 bytes long.
10280 20:12:49.220766
10281 20:12:49.223878 Sending tftp read request... done.
10282 20:12:49.223961
10283 20:12:49.224026 Waiting for the transfer...
10284 20:12:49.224087
10285 20:12:49.227095 00000000 # done.
10286 20:12:49.227180
10287 20:12:49.234004 Command line loaded dynamically from TFTP file: 12928089/tftp-deploy-u_hjodma/kernel/cmdline
10288 20:12:49.234087
10289 20:12:49.257810 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10290 20:12:49.257903
10291 20:12:49.257968 Loading FIT.
10292 20:12:49.258028
10293 20:12:49.261142 Image ramdisk-1 has 17806052 bytes.
10294 20:12:49.261224
10295 20:12:49.264421 Image fdt-1 has 47278 bytes.
10296 20:12:49.264502
10297 20:12:49.267039 Image kernel-1 has 12060038 bytes.
10298 20:12:49.267122
10299 20:12:49.277039 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 20:12:49.277123
10301 20:12:49.294291 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 20:12:49.294389
10303 20:12:49.297165 Choosing best match conf-1 for compat google,spherion-rev2.
10304 20:12:49.303003
10305 20:12:49.307455 Connected to device vid:did:rid of 1ae0:0028:00
10306 20:12:49.314411
10307 20:12:49.317926 tpm_get_response: command 0x17b, return code 0x0
10308 20:12:49.318009
10309 20:12:49.320944 ec_init: CrosEC protocol v3 supported (256, 248)
10310 20:12:49.325139
10311 20:12:49.328652 tpm_cleanup: add release locality here.
10312 20:12:49.328735
10313 20:12:49.328800 Shutting down all USB controllers.
10314 20:12:49.332086
10315 20:12:49.332168 Removing current net device
10316 20:12:49.332233
10317 20:12:49.338232 Exiting depthcharge with code 4 at timestamp: 67571585
10318 20:12:49.338328
10319 20:12:49.341496 LZMA decompressing kernel-1 to 0x821a6718
10320 20:12:49.341593
10321 20:12:49.345087 LZMA decompressing kernel-1 to 0x40000000
10322 20:12:50.844494
10323 20:12:50.844648 jumping to kernel
10324 20:12:50.845117 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10325 20:12:50.845218 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10326 20:12:50.845294 Setting prompt string to ['Linux version [0-9]']
10327 20:12:50.845362 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 20:12:50.845431 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 20:12:50.925951
10330 20:12:50.929283 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 20:12:50.932742 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10332 20:12:50.932839 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 20:12:50.932909 Setting prompt string to []
10334 20:12:50.932984 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 20:12:50.933054 Using line separator: #'\n'#
10336 20:12:50.933113 No login prompt set.
10337 20:12:50.933173 Parsing kernel messages
10338 20:12:50.933228 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 20:12:50.933332 [login-action] Waiting for messages, (timeout 00:03:45)
10340 20:12:50.933395 Waiting using forced prompt support (timeout 00:01:53)
10341 20:12:50.953092 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10342 20:12:50.955940 [ 0.000000] random: crng init done
10343 20:12:50.962508 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 20:12:50.965800 [ 0.000000] efi: UEFI not found.
10345 20:12:50.972321 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 20:12:50.979431 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 20:12:50.989581 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 20:12:50.999106 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 20:12:51.006047 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 20:12:51.012720 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 20:12:51.019458 [ 0.000000] NUMA: No NUMA configuration found
10352 20:12:51.025776 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 20:12:51.029398 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10354 20:12:51.032801 [ 0.000000] Zone ranges:
10355 20:12:51.039639 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 20:12:51.042384 [ 0.000000] DMA32 empty
10357 20:12:51.049302 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 20:12:51.052856 [ 0.000000] Movable zone start for each node
10359 20:12:51.055748 [ 0.000000] Early memory node ranges
10360 20:12:51.062247 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 20:12:51.069247 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 20:12:51.076199 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 20:12:51.079354 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 20:12:51.086169 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 20:12:51.092151 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 20:12:51.151072 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 20:12:51.157517 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 20:12:51.164453 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 20:12:51.167646 [ 0.000000] psci: probing for conduit method from DT.
10370 20:12:51.174673 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 20:12:51.177954 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 20:12:51.184711 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 20:12:51.187831 [ 0.000000] psci: SMC Calling Convention v1.2
10374 20:12:51.194197 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10375 20:12:51.197415 [ 0.000000] Detected VIPT I-cache on CPU0
10376 20:12:51.204022 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 20:12:51.210959 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 20:12:51.217668 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 20:12:51.224429 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 20:12:51.230771 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 20:12:51.237495 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 20:12:51.244020 [ 0.000000] alternatives: applying boot alternatives
10383 20:12:51.248032 [ 0.000000] Fallback order for Node 0: 0
10384 20:12:51.257400 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 20:12:51.257530 [ 0.000000] Policy zone: Normal
10386 20:12:51.280426 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10387 20:12:51.293746 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 20:12:51.303737 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 20:12:51.314046 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 20:12:51.320866 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10391 20:12:51.323990 <6>[ 0.000000] software IO TLB: area num 8.
10392 20:12:51.381586 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 20:12:51.530807 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10394 20:12:51.537725 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 20:12:51.544743 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 20:12:51.547923 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 20:12:51.554337 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 20:12:51.561164 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 20:12:51.564131 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 20:12:51.574041 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 20:12:51.581143 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 20:12:51.584681 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 20:12:51.592410 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 20:12:51.595433 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 20:12:51.602177 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 20:12:51.605750 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 20:12:51.608349 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 20:12:51.618463 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 20:12:51.628361 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 20:12:51.641988 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 20:12:51.648248 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 20:12:51.657454 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 20:12:51.670748 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 20:12:51.677246 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 20:12:51.684289 <6>[ 0.009180] Console: colour dummy device 80x25
10416 20:12:51.693929 <6>[ 0.013930] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 20:12:51.697365 <6>[ 0.024436] pid_max: default: 32768 minimum: 301
10418 20:12:51.703875 <6>[ 0.029308] LSM: Security Framework initializing
10419 20:12:51.710964 <6>[ 0.034244] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 20:12:51.720457 <6>[ 0.042105] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 20:12:51.727010 <6>[ 0.051507] cblist_init_generic: Setting adjustable number of callback queues.
10422 20:12:51.733941 <6>[ 0.058951] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 20:12:51.744009 <6>[ 0.065314] cblist_init_generic: Setting adjustable number of callback queues.
10424 20:12:51.747158 <6>[ 0.072788] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 20:12:51.753814 <6>[ 0.079229] rcu: Hierarchical SRCU implementation.
10426 20:12:51.760511 <6>[ 0.079231] rcu: Max phase no-delay instances is 1000.
10427 20:12:51.764238 <6>[ 0.079255] printk: bootconsole [mtk8250] printing thread started
10428 20:12:51.772728 <6>[ 0.097575] EFI services will not be available.
10429 20:12:51.776636 <6>[ 0.097778] smp: Bringing up secondary CPUs ...
10430 20:12:51.782664 <6>[ 0.098084] Detected VIPT I-cache on CPU1
10431 20:12:51.789200 <6>[ 0.098151] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10432 20:12:51.796735 <6>[ 0.098182] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10433 20:12:51.805803 <6>[ 0.126046] Detected VIPT I-cache on CPU2
10434 20:12:51.812413 <6>[ 0.126095] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10435 20:12:51.822653 <6>[ 0.126112] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10436 20:12:51.826131 <6>[ 0.126374] Detected VIPT I-cache on CPU3
10437 20:12:51.832592 <6>[ 0.126420] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10438 20:12:51.839052 <6>[ 0.126433] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10439 20:12:51.842600 <6>[ 0.126747] CPU features: detected: Spectre-v4
10440 20:12:51.848967 <6>[ 0.126753] CPU features: detected: Spectre-BHB
10441 20:12:51.852645 <6>[ 0.126758] Detected PIPT I-cache on CPU4
10442 20:12:51.858723 <6>[ 0.126818] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10443 20:12:51.865857 <6>[ 0.126835] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10444 20:12:51.872350 <6>[ 0.127127] Detected PIPT I-cache on CPU5
10445 20:12:51.879105 <6>[ 0.127186] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10446 20:12:51.885589 <6>[ 0.127203] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10447 20:12:51.888812 <6>[ 0.127481] Detected PIPT I-cache on CPU6
10448 20:12:51.895270 <6>[ 0.127548] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10449 20:12:51.902184 <6>[ 0.127564] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10450 20:12:51.908944 <6>[ 0.127856] Detected PIPT I-cache on CPU7
10451 20:12:51.915160 <6>[ 0.127920] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10452 20:12:51.921809 <6>[ 0.127936] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10453 20:12:51.925595 <6>[ 0.127982] smp: Brought up 1 node, 8 CPUs
10454 20:12:51.931857 <6>[ 0.127986] SMP: Total of 8 processors activated.
10455 20:12:51.935326 <6>[ 0.127990] CPU features: detected: 32-bit EL0 Support
10456 20:12:51.945376 <6>[ 0.127991] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10457 20:12:51.951957 <6>[ 0.127994] CPU features: detected: Common not Private translations
10458 20:12:51.955523 <6>[ 0.127996] CPU features: detected: CRC32 instructions
10459 20:12:51.962166 <6>[ 0.127999] CPU features: detected: RCpc load-acquire (LDAPR)
10460 20:12:51.968768 <6>[ 0.128000] CPU features: detected: LSE atomic instructions
10461 20:12:51.975351 <6>[ 0.128002] CPU features: detected: Privileged Access Never
10462 20:12:51.978641 <6>[ 0.128003] CPU features: detected: RAS Extension Support
10463 20:12:51.985759 <6>[ 0.128007] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10464 20:12:51.992231 <6>[ 0.128075] CPU: All CPU(s) started at EL2
10465 20:12:52.020217 ��֭����,�,j5��}��չѕ�5R�<6>[ 0.344<472] printk: console [ttyS0] printing thread started
10466 20:12:52.023326 5<6>[ 0.344501] printk: console [ttyS0] enabled
10467 20:12:52.030154 >[ 0.225574] VFS: Disk quotas dquot_6.6.0
10468 20:12:52.037009 <6>[ 0.344504] printk: bootconsole [mtk8250] disabled
10469 20:12:52.043087 <6>[ 0.358919] printk: bootconsole [mtk8250] printing thread stopped
10470 20:12:52.046359 <6>[ 0.359973] SuperH (H)SCI(F) driver initialized
10471 20:12:52.052995 <6>[ 0.360452] msm_serial: driver initialized
10472 20:12:52.060107 <6>[ 0.364947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10473 20:12:52.069649 <6>[ 0.364975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10474 20:12:52.076164 <6>[ 0.365005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10475 20:12:52.095813 <6>[ 0.365034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10476 20:12:52.105172 <6>[ 0.365055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10477 20:12:52.105519 <6>[ 0.365082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10478 20:12:52.121909 <6>[ 0.365109] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10479 20:12:52.122004 <6>[ 0.365219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10480 20:12:52.131794 <6>[ 0.365248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10481 20:12:52.131877 <6>[ 0.376150] loop: module loaded
10482 20:12:52.142641 <6>[ 0.378760] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10483 20:12:52.146342 <4>[ 0.395481] mtk-pmic-keys: Failed to locate of_node [id: -1]
10484 20:12:52.149796 <6>[ 0.396273] megasas: 07.719.03.00-rc1
10485 20:12:52.156196 <6>[ 0.408846] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10486 20:12:52.159417 <6>[ 0.409007] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10487 20:12:52.166030 <6>[ 0.421106] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10488 20:12:52.176167 <6>[ 0.474758] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10489 20:12:52.652459 <6>[ 0.976260] Freeing initrd memory: 17384K
10490 20:12:52.660268 <6>[ 0.982313] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10491 20:12:52.666974 <6>[ 0.986881] tun: Universal TUN/TAP device driver, 1.6
10492 20:12:52.670069 <6>[ 0.987619] thunder_xcv, ver 1.0
10493 20:12:52.673596 <6>[ 0.987638] thunder_bgx, ver 1.0
10494 20:12:52.676735 <6>[ 0.987651] nicpf, ver 1.0
10495 20:12:52.683257 <6>[ 0.988679] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10496 20:12:52.689892 <6>[ 0.988682] hns3: Copyright (c) 2017 Huawei Corporation.
10497 20:12:52.693600 <6>[ 0.988710] hclge is initializing
10498 20:12:52.697196 <6>[ 0.988730] e1000: Intel(R) PRO/1000 Network Driver
10499 20:12:52.703624 <6>[ 0.988732] e1000: Copyright (c) 1999-2006 Intel Corporation.
10500 20:12:52.711023 <6>[ 0.988748] e1000e: Intel(R) PRO/1000 Network Driver
10501 20:12:52.714646 <6>[ 0.988750] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10502 20:12:52.721852 <6>[ 0.988765] igb: Intel(R) Gigabit Ethernet Network Driver
10503 20:12:52.728287 <6>[ 0.988767] igb: Copyright (c) 2007-2014 Intel Corporation.
10504 20:12:52.735683 <6>[ 0.988781] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10505 20:12:52.739781 <6>[ 0.988783] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10506 20:12:52.742281 <6>[ 0.989073] sky2: driver version 1.30
10507 20:12:52.749234 <6>[ 0.990139] VFIO - User Level meta-driver version: 0.3
10508 20:12:52.755760 <6>[ 0.992929] usbcore: registered new interface driver usb-storage
10509 20:12:52.762611 <6>[ 0.993109] usbcore: registered new device driver onboard-usb-hub
10510 20:12:52.766283 <6>[ 0.995846] mt6397-rtc mt6359-rtc: registered as rtc0
10511 20:12:52.775868 <6>[ 0.995998] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:12:53 UTC (1709496773)
10512 20:12:52.779104 <6>[ 0.996598] i2c_dev: i2c /dev entries driver
10513 20:12:52.789091 <6>[ 1.003583] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10514 20:12:52.792824 <6>[ 1.019559] cpu cpu0: EM: created perf domain
10515 20:12:52.798995 <6>[ 1.019867] cpu cpu4: EM: created perf domain
10516 20:12:52.805635 <6>[ 1.023662] sdhci: Secure Digital Host Controller Interface driver
10517 20:12:52.809834 <6>[ 1.023663] sdhci: Copyright(c) Pierre Ossman
10518 20:12:52.815727 <6>[ 1.024025] Synopsys Designware Multimedia Card Interface Driver
10519 20:12:52.822809 <6>[ 1.024407] sdhci-pltfm: SDHCI platform and OF driver helper
10520 20:12:52.826085 <6>[ 1.028672] ledtrig-cpu: registered to indicate activity on CPUs
10521 20:12:52.832108 <6>[ 1.029344] mmc0: CQHCI version 5.10
10522 20:12:52.839019 <6>[ 1.029381] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10523 20:12:52.843091 <6>[ 1.029666] usbcore: registered new interface driver usbhid
10524 20:12:52.848975 <6>[ 1.029668] usbhid: USB HID core driver
10525 20:12:52.855452 <6>[ 1.029770] spi_master spi0: will run message pump with realtime priority
10526 20:12:52.865544 <6>[ 1.061631] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10527 20:12:52.878986 <6>[ 1.063837] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10528 20:12:52.885790 <6>[ 1.064827] cros-ec-spi spi0.0: Chrome EC device registered
10529 20:12:52.896099 <6>[ 1.084449] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10530 20:12:52.902684 <6>[ 1.086669] NET: Registered PF_PACKET protocol family
10531 20:12:52.905641 <6>[ 1.086754] 9pnet: Installing 9P2000 support
10532 20:12:52.908971 <5>[ 1.086802] Key type dns_resolver registered
10533 20:12:52.915893 <6>[ 1.087202] registered taskstats version 1
10534 20:12:52.919452 <5>[ 1.087218] Loading compiled-in X.509 certificates
10535 20:12:52.929145 <4>[ 1.103264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 20:12:52.939108 <4>[ 1.103509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 20:12:52.945725 <3>[ 1.103537] debugfs: File 'uA_load' in directory '/' already present!
10538 20:12:52.952603 <3>[ 1.103549] debugfs: File 'min_uV' in directory '/' already present!
10539 20:12:52.959070 <3>[ 1.103555] debugfs: File 'max_uV' in directory '/' already present!
10540 20:12:52.969176 <3>[ 1.103562] debugfs: File 'constraint_flags' in directory '/' already present!
10541 20:12:52.975996 <3>[ 1.107112] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10542 20:12:52.983178 <6>[ 1.120104] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10543 20:12:52.989522 <6>[ 1.120681] xhci-mtk 11200000.usb: xHCI Host Controller
10544 20:12:52.996095 <6>[ 1.120697] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10545 20:12:53.006264 <6>[ 1.120905] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10546 20:12:53.009424 <6>[ 1.120952] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10547 20:12:53.016694 <6>[ 1.121051] xhci-mtk 11200000.usb: xHCI Host Controller
10548 20:12:53.022818 <6>[ 1.121058] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10549 20:12:53.029890 <6>[ 1.121066] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10550 20:12:53.036745 <6>[ 1.121555] hub 1-0:1.0: USB hub found
10551 20:12:53.039753 <6>[ 1.121597] hub 1-0:1.0: 1 port detected
10552 20:12:53.046156 <6>[ 1.121810] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10553 20:12:53.052979 <6>[ 1.122127] hub 2-0:1.0: USB hub found
10554 20:12:53.056778 <6>[ 1.122142] hub 2-0:1.0: 1 port detected
10555 20:12:53.059655 <6>[ 1.123532] mmc0: Command Queue Engine enabled
10556 20:12:53.066659 <6>[ 1.123542] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10557 20:12:53.073327 <6>[ 1.124053] mmcblk0: mmc0:0001 DA4128 116 GiB
10558 20:12:53.077032 <6>[ 1.127011] mtk-msdc 11f70000.mmc: Got CD GPIO
10559 20:12:53.083492 <6>[ 1.127158] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10560 20:12:53.086604 <6>[ 1.128488] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10561 20:12:53.093330 <6>[ 1.129280] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10562 20:12:53.099817 <6>[ 1.130026] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10563 20:12:53.106962 <6>[ 1.142440] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10564 20:12:53.116811 <6>[ 1.142447] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10565 20:12:53.123767 <4>[ 1.142595] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10566 20:12:53.133707 <6>[ 1.143225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10567 20:12:53.140177 <6>[ 1.143228] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10568 20:12:53.146790 <6>[ 1.143354] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10569 20:12:53.156898 <6>[ 1.143365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10570 20:12:53.163664 <6>[ 1.143369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10571 20:12:53.173541 <6>[ 1.143374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10572 20:12:53.179911 <6>[ 1.144808] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10573 20:12:53.189734 <6>[ 1.144823] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10574 20:12:53.197029 <6>[ 1.144828] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10575 20:12:53.207015 <6>[ 1.144834] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10576 20:12:53.213234 <6>[ 1.144839] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10577 20:12:53.223141 <6>[ 1.144844] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10578 20:12:53.229469 <6>[ 1.144849] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10579 20:12:53.239546 <6>[ 1.144854] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10580 20:12:53.246444 <6>[ 1.144859] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10581 20:12:53.256518 <6>[ 1.144864] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10582 20:12:53.263172 <6>[ 1.144869] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10583 20:12:53.273661 <6>[ 1.144874] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10584 20:12:53.283318 <6>[ 1.144879] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10585 20:12:53.289860 <6>[ 1.144884] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10586 20:12:53.299332 <6>[ 1.144889] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10587 20:12:53.302922 <6>[ 1.145372] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10588 20:12:53.309528 <6>[ 1.146339] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10589 20:12:53.316331 <6>[ 1.146892] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10590 20:12:53.322735 <6>[ 1.147508] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10591 20:12:53.329551 <6>[ 1.148128] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10592 20:12:53.339190 <6>[ 1.148348] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10593 20:12:53.349467 <6>[ 1.148364] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10594 20:12:53.359005 <6>[ 1.148369] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10595 20:12:53.369082 <6>[ 1.148376] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10596 20:12:53.379073 <6>[ 1.148382] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10597 20:12:53.385341 <6>[ 1.148388] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10598 20:12:53.395611 <6>[ 1.148394] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10599 20:12:53.405366 <6>[ 1.148399] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10600 20:12:53.415382 <6>[ 1.148404] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10601 20:12:53.425727 <6>[ 1.148412] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10602 20:12:53.435380 <6>[ 1.148416] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10603 20:12:53.441854 <6>[ 1.148984] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10604 20:12:53.448565 <6>[ 1.158123] Trying to probe devices needed for running init ...
10605 20:12:53.454727 <6>[ 1.549590] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10606 20:12:53.461502 <6>[ 1.705105] hub 1-1:1.0: USB hub found
10607 20:12:53.464641 <6>[ 1.705368] hub 1-1:1.0: 4 ports detected
10608 20:12:53.468133 <6>[ 1.708182] hub 1-1:1.0: USB hub found
10609 20:12:53.471541 <6>[ 1.708440] hub 1-1:1.0: 4 ports detected
10610 20:12:53.515360 <6>[ 1.833752] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10611 20:12:53.536502 <6>[ 1.858218] hub 2-1:1.0: USB hub found
10612 20:12:53.539509 <6>[ 1.858591] hub 2-1:1.0: 3 ports detected
10613 20:12:53.542728 <6>[ 1.861112] hub 2-1:1.0: USB hub found
10614 20:12:53.549189 <6>[ 1.861431] hub 2-1:1.0: 3 ports detected
10615 20:12:53.703447 <6>[ 2.021778] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10616 20:12:53.824103 <6>[ 2.149097] hub 1-1.4:1.0: USB hub found
10617 20:12:53.827410 <6>[ 2.149449] hub 1-1.4:1.0: 2 ports detected
10618 20:12:53.830658 <6>[ 2.152704] hub 1-1.4:1.0: USB hub found
10619 20:12:53.837399 <6>[ 2.153033] hub 1-1.4:1.0: 2 ports detected
10620 20:12:53.907287 <6>[ 2.225899] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10621 20:12:54.123481 <6>[ 2.441749] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10622 20:12:54.307725 <6>[ 2.625771] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10623 20:13:05.115352 <6>[ 13.442828] ALSA device list:
10624 20:13:05.122573 <6>[ 13.442851] No soundcards found.
10625 20:13:05.125427 <6>[ 13.447286] Freeing unused kernel memory: 8448K
10626 20:13:05.128885 <6>[ 13.447462] Run /init as init process
10627 20:13:05.132449 Loading, please wait...
10628 20:13:05.156519 Starting version 247.3-7+deb11u4
10629 20:13:05.361984 <3>[ 13.684563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 20:13:05.368426 <3>[ 13.684581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 20:13:05.379118 <3>[ 13.684585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 20:13:05.385017 <3>[ 13.690733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 20:13:05.395191 <3>[ 13.690795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 20:13:05.402082 <3>[ 13.690803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 20:13:05.411883 <3>[ 13.690822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 20:13:05.418153 <3>[ 13.690831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 20:13:05.424856 <3>[ 13.690968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10638 20:13:05.435192 <3>[ 13.691069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 20:13:05.441829 <3>[ 13.691077] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 20:13:05.452051 <3>[ 13.691083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 20:13:05.458194 <6>[ 13.719915] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10642 20:13:05.465079 <3>[ 13.735809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 20:13:05.475126 <3>[ 13.735828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 20:13:05.482162 <3>[ 13.735832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 20:13:05.488691 <3>[ 13.735837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 20:13:05.499520 <3>[ 13.735841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10647 20:13:05.505598 <3>[ 13.735884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 20:13:05.512725 <6>[ 13.744463] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10649 20:13:05.522889 <6>[ 13.744502] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10650 20:13:05.532830 <6>[ 13.744506] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10651 20:13:05.536046 <6>[ 13.754441] remoteproc remoteproc0: scp is available
10652 20:13:05.543290 <6>[ 13.754679] remoteproc remoteproc0: powering up scp
10653 20:13:05.549139 <6>[ 13.754685] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10654 20:13:05.555560 <6>[ 13.754699] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10655 20:13:05.562513 <6>[ 13.766511] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10656 20:13:05.569165 <6>[ 13.768223] mc: Linux media interface: v0.10
10657 20:13:05.575867 <4>[ 13.788471] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10658 20:13:05.582559 <4>[ 13.792487] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10659 20:13:05.592014 <4>[ 13.795736] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10660 20:13:05.595499 <4>[ 13.795736] Fallback method does not support PEC.
10661 20:13:05.602391 <6>[ 13.802581] videodev: Linux video capture interface: v2.00
10662 20:13:05.612208 <3>[ 13.811396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 20:13:05.618945 <6>[ 13.839520] usbcore: registered new device driver r8152-cfgselector
10664 20:13:05.625757 <3>[ 13.850298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 20:13:05.632122 <6>[ 13.866720] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10666 20:13:05.638695 <6>[ 13.866729] pci_bus 0000:00: root bus resource [bus 00-ff]
10667 20:13:05.645254 <6>[ 13.866733] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10668 20:13:05.655127 <6>[ 13.866737] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10669 20:13:05.662017 <6>[ 13.866764] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10670 20:13:05.668815 <6>[ 13.866777] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10671 20:13:05.675376 <6>[ 13.866847] pci 0000:00:00.0: supports D1 D2
10672 20:13:05.681876 <6>[ 13.866849] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10673 20:13:05.688850 <6>[ 13.867763] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10674 20:13:05.695823 <6>[ 13.867829] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10675 20:13:05.701395 <6>[ 13.867853] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10676 20:13:05.711638 <6>[ 13.867868] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10677 20:13:05.717927 <6>[ 13.867883] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10678 20:13:05.721755 <6>[ 13.867986] pci 0000:01:00.0: supports D1 D2
10679 20:13:05.728094 <6>[ 13.867987] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10680 20:13:05.735013 <6>[ 13.876828] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10681 20:13:05.744365 <6>[ 13.876865] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10682 20:13:05.751108 <6>[ 13.876872] remoteproc remoteproc0: remote processor scp is now up
10683 20:13:05.757814 <6>[ 13.881615] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10684 20:13:05.764344 <6>[ 13.881636] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10685 20:13:05.774655 <6>[ 13.881640] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10686 20:13:05.780893 <6>[ 13.881647] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10687 20:13:05.790988 <6>[ 13.881660] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10688 20:13:05.798223 <6>[ 13.881672] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10689 20:13:05.804557 <6>[ 13.881684] pci 0000:00:00.0: PCI bridge to [bus 01]
10690 20:13:05.811385 <6>[ 13.881689] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10691 20:13:05.817525 <6>[ 13.881810] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10692 20:13:05.824307 <6>[ 13.882280] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10693 20:13:05.831335 <6>[ 13.882763] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10694 20:13:05.837773 <6>[ 13.888846] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10695 20:13:05.847451 <6>[ 13.890277] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10696 20:13:05.853715 <6>[ 13.904591] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10697 20:13:05.863625 <6>[ 13.914528] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10698 20:13:05.873809 <6>[ 13.914817] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10699 20:13:05.883907 <6>[ 13.929842] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10700 20:13:05.890621 <5>[ 13.937303] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10701 20:13:05.897229 <5>[ 13.951611] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10702 20:13:05.906946 <5>[ 13.952706] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10703 20:13:05.913308 <4>[ 13.953512] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10704 20:13:05.919867 <6>[ 13.953572] cfg80211: failed to load regulatory.db
10705 20:13:05.929809 <4>[ 13.958861] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10706 20:13:05.936652 <4>[ 13.958873] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10707 20:13:05.940300 <6>[ 13.971307] Bluetooth: Core ver 2.22
10708 20:13:05.947240 <6>[ 13.971373] NET: Registered PF_BLUETOOTH protocol family
10709 20:13:05.953038 <6>[ 13.971375] Bluetooth: HCI device and connection manager initialized
10710 20:13:05.956300 <6>[ 13.971390] Bluetooth: HCI socket layer initialized
10711 20:13:05.962977 <6>[ 13.971394] Bluetooth: L2CAP socket layer initialized
10712 20:13:05.969957 <6>[ 13.971401] Bluetooth: SCO socket layer initialized
10713 20:13:05.976379 <6>[ 13.978935] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10714 20:13:05.986652 <6>[ 13.980041] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10715 20:13:05.993045 <6>[ 13.980134] usbcore: registered new interface driver uvcvideo
10716 20:13:05.999515 <6>[ 14.013890] r8152 2-1.3:1.0 eth0: v1.12.13
10717 20:13:06.002622 <6>[ 14.014097] usbcore: registered new interface driver r8152
10718 20:13:06.009207 <6>[ 14.014142] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10719 20:13:06.015903 <6>[ 14.034885] usbcore: registered new interface driver cdc_ether
10720 20:13:06.022651 <6>[ 14.042399] usbcore: registered new interface driver r8153_ecm
10721 20:13:06.029101 <6>[ 14.043172] usbcore: registered new interface driver btusb
10722 20:13:06.039362 <4>[ 14.044652] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10723 20:13:06.045735 <3>[ 14.044671] Bluetooth: hci0: Failed to load firmware file (-2)
10724 20:13:06.048664 <3>[ 14.044675] Bluetooth: hci0: Failed to set up firmware (-2)
10725 20:13:06.062194 <4>[ 14.044679] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10726 20:13:06.065724 <6>[ 14.066586] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10727 20:13:06.075483 <6>[ 14.070517] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10728 20:13:06.081875 <6>[ 14.070619] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10729 20:13:06.085489 <6>[ 14.089625] mt7921e 0000:01:00.0: ASIC revision: 79610010
10730 20:13:06.094999 <6>[ 14.184311] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10731 20:13:06.095082 <6>[ 14.184311]
10732 20:13:06.098455 Begin: Loading essential drivers ... done.
10733 20:13:06.105080 Begin: Running /scripts/init-premount ... done.
10734 20:13:06.111991 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10735 20:13:06.121652 Begin: Running /scripts/nfs-premoun<6>[ 14.443181] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10736 20:13:06.128487 t ... Waiting up to 60 secs for any ethernet to become available
10737 20:13:06.131763 Device /sys/class/net/enx002432307852 found
10738 20:13:06.134899 done.
10739 20:13:06.165914 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10740 20:13:06.962312 <6>[ 15.286657] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10741 20:13:07.278521 <6>[ 15.604295] r8152 2-1.3:1.0 enx002432307852: carrier on
10742 20:13:08.168832 IP-Config: no response after 2 secs - giving up
10743 20:13:08.217891 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10744 20:13:08.242883 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10745 20:13:08.968956 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10746 20:13:08.975176 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10747 20:13:08.981672 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10748 20:13:08.988404 host : mt8192-asurada-spherion-r0-cbg-3
10749 20:13:08.994832 domain : lava-rack
10750 20:13:08.998736 rootserver: 192.168.201.1 rootpath:
10751 20:13:09.001429 filename :
10752 20:13:09.089480 done.
10753 20:13:09.098085 Begin: Running /scripts/nfs-bottom ... done.
10754 20:13:09.116745 Begin: Running /scripts/init-bottom ... done.
10755 20:13:10.342770 <6>[ 18.666527] NET: Registered PF_INET6 protocol family
10756 20:13:10.345642 <6>[ 18.668265] Segment Routing with IPv6
10757 20:13:10.352402 <6>[ 18.668282] In-situ OAM (IOAM) with IPv6
10758 20:13:10.486663 <30>[ 18.796011] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10759 20:13:10.493279 <30>[ 18.797015] systemd[1]: Detected architecture arm64.
10760 20:13:10.493372
10761 20:13:10.499998 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10762 20:13:10.500081
10763 20:13:10.518053 <30>[ 18.844464] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10764 20:13:11.381301 <30>[ 19.703628] systemd[1]: Queued start job for default target Graphical Interface.
10765 20:13:11.404313 [[0;32m OK [<30>[ 19.728218] systemd[1]: Created slice system-getty.slice.
10766 20:13:11.407675 0m] Created slice [0;1;39msystem-getty.slice[0m.
10767 20:13:11.426733 [[0;32m OK [0m] Created slic<30>[ 19.751046] systemd[1]: Created slice system-modprobe.slice.
10768 20:13:11.430054 e [0;1;39msystem-modprobe.slice[0m.
10769 20:13:11.450673 [[0;32m OK [0m] Created slic<30>[ 19.774971] systemd[1]: Created slice system-serial\x2dgetty.slice.
10770 20:13:11.457322 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10771 20:13:11.475208 [[0;32m OK [0m] Created slic<30>[ 19.799478] systemd[1]: Created slice User and Session Slice.
10772 20:13:11.479112 e [0;1;39mUser and Session Slice[0m.
10773 20:13:11.502071 [[0;32m OK [0m] Started [0;<30>[ 19.822601] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10774 20:13:11.505196 1;39mDispatch Password …ts to Console Directory Watch[0m.
10775 20:13:11.528919 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.849937] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10776 20:13:11.532386 sword R…uests to Wall Directory Watch[0m.
10777 20:13:11.556436 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.873862] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10778 20:13:11.563099 <30>[ 19.874056] systemd[1]: Reached target Local Encrypted Volumes.
10779 20:13:11.566344 l Encrypted Volumes[0m.
10780 20:13:11.585500 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.909856] systemd[1]: Reached target Paths.
10781 20:13:11.585583 s[0m.
10782 20:13:11.609455 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.929745] systemd[1]: Reached target Remote File Systems.
10783 20:13:11.609538 te File Systems[0m.
10784 20:13:11.630582 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.954168] systemd[1]: Reached target Slices.
10785 20:13:11.630666 es[0m.
10786 20:13:11.649904 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.973807] systemd[1]: Reached target Swap.
10787 20:13:11.650011 [0m.
10788 20:13:11.673723 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.994218] systemd[1]: Listening on initctl Compatibility Named Pipe.
10789 20:13:11.677086 l Compatibility Named Pipe[0m.
10790 20:13:11.686648 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 20.010457] systemd[1]: Listening on Journal Audit Socket.
10791 20:13:11.690267 l Audit Socket[0m.
10792 20:13:11.711110 [[0;32m OK [0m] Listening on<30>[ 20.035189] systemd[1]: Listening on Journal Socket (/dev/log).
10793 20:13:11.715282 [0;1;39mJournal Socket (/dev/log)[0m.
10794 20:13:11.735877 [[0;32m OK [0m] Listening on<30>[ 20.059051] systemd[1]: Listening on Journal Socket.
10795 20:13:11.738736 [0;1;39mJournal Socket[0m.
10796 20:13:11.755679 [[0;32m OK [0m] Listening on<30>[ 20.079615] systemd[1]: Listening on Network Service Netlink Socket.
10797 20:13:11.762283 [0;1;39mNetwork Service Netlink Socket[0m.
10798 20:13:11.781790 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 20.105945] systemd[1]: Listening on udev Control Socket.
10799 20:13:11.785094 ontrol Socket[0m.
10800 20:13:11.805978 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.130274] systemd[1]: Listening on udev Kernel Socket.
10801 20:13:11.809432 ernel Socket[0m.
10802 20:13:11.853808 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.177851] systemd[1]: Mounting Huge Pages File System...
10803 20:13:11.857037 m[0m...
10804 20:13:11.881593 Mounting [0;1;39mPOSIX Message Queue F<30>[ 20.202096] systemd[1]: Mounting POSIX Message Queue File System...
10805 20:13:11.881711 ile System[0m...
10806 20:13:11.909780 Mounting [0;1;39mKernel Debug File Sys<30>[ 20.230204] systemd[1]: Mounting Kernel Debug File System...
10807 20:13:11.909864 tem[0m...
10808 20:13:11.929379 <30>[ 20.250201] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10809 20:13:11.969615 Starting [0;1;39mCreate list of st…o<30>[ 20.290572] systemd[1]: Starting Create list of static device nodes for the current kernel...
10810 20:13:11.973100 des for the current kernel[0m...
10811 20:13:12.002383 Starting [0;1;39mLoad <30>[ 20.326615] systemd[1]: Starting Load Kernel Module configfs...
10812 20:13:12.006294 Kernel Module configfs[0m...
10813 20:13:12.033181 Starting [0;1;39mLoad Kernel Module dr<30>[ 20.353756] systemd[1]: Starting Load Kernel Module drm...
10814 20:13:12.033266 m[0m...
10815 20:13:12.057952 Starting [0;1;39mLoad Kernel Module fu<30>[ 20.378452] systemd[1]: Starting Load Kernel Module fuse...
10816 20:13:12.058035 se[0m...
10817 20:13:12.081498 <30>[ 20.403149] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10818 20:13:12.094067 Starting [0;1;39mJournal Service[0m..<30>[ 20.418382] systemd[1]: Starting Journal Service...
10819 20:13:12.094174 .
10820 20:13:12.117538 <6>[ 20.442041] fuse: init (API version 7.37)
10821 20:13:12.127955 Starting [0;1;39mLoad Kernel Modules[<30>[ 20.447788] systemd[1]: Starting Load Kernel Modules...
10822 20:13:12.128042 0m...
10823 20:13:12.190608 Starting [0;1;39mRemou<30>[ 20.514680] systemd[1]: Starting Remount Root and Kernel File Systems...
10824 20:13:12.193868 nt Root and Kernel File Systems[0m...
10825 20:13:12.219161 Starting [0;1;39mColdp<30>[ 20.542767] systemd[1]: Starting Coldplug All udev Devices...
10826 20:13:12.222515 lug All udev Devices[0m...
10827 20:13:12.244572 [[0;32m OK [<30>[ 20.568335] systemd[1]: Mounted Huge Pages File System.
10828 20:13:12.248464 0m] Mounted [0;1;39mHuge Pages File System[0m.
10829 20:13:12.258270 <3>[ 20.580682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 20:13:12.268056 [[0;32m OK [0m] Mounted [0;<30>[ 20.591404] systemd[1]: Mounted POSIX Message Queue File System.
10831 20:13:12.271583 1;39mPOSIX Message Queue File System[0m.
10832 20:13:12.290204 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.614070] systemd[1]: Mounted Kernel Debug File System.
10833 20:13:12.300081 g File System[0<3>[ 20.617990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10834 20:13:12.303648 m.
10835 20:13:12.326104 [[0;32m OK [0m] Finished [0<30>[ 20.646698] systemd[1]: Finished Create list of static device nodes for the current kernel.
10836 20:13:12.329583 ;1;39mCreate list of st… nodes for the current kernel[0m.
10837 20:13:12.340906 <3>[ 20.663894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 20:13:12.353515 [[0;32m OK [<30>[ 20.675767] systemd[1]: modprobe@configfs.service: Succeeded.
10839 20:13:12.360141 0m] Finished [0<30>[ 20.676815] systemd[1]: Finished Load Kernel Module configfs.
10840 20:13:12.366639 <3>[ 20.683669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 20:13:12.369902 ;1;39mLoad Kernel Module configfs[0m.
10842 20:13:12.389354 <3>[ 20.710946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 20:13:12.400592 [[0;32m OK [0m] Finished [0<30>[ 20.723276] systemd[1]: modprobe@drm.service: Succeeded.
10844 20:13:12.407337 ;1;39mLoad Kerne<30>[ 20.723964] systemd[1]: Finished Load Kernel Module drm.
10845 20:13:12.417051 l Module drm[0m<3>[ 20.736492] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 20:13:12.417136 .
10847 20:13:12.443568 [[0;32m OK [0m] Finished [0<30>[ 20.767051] systemd[1]: modprobe@fuse.service: Succeeded.
10848 20:13:12.454624 ;1;39mLoad Kerne<3>[ 20.767195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 20:13:12.460777 l Module fuse[0<30>[ 20.767755] systemd[1]: Finished Load Kernel Module fuse.
10850 20:13:12.460859 m.
10851 20:13:12.471149 <3>[ 20.788767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 20:13:12.478368 [[0;32m OK [<30>[ 20.804791] systemd[1]: Finished Load Kernel Modules.
10853 20:13:12.488680 0m] Finished [0<3>[ 20.809234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 20:13:12.491941 ;1;39mLoad Kernel Modules[0m.
10855 20:13:12.509284 <3>[ 20.830958] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 20:13:12.520561 [[0;32m OK [0m] Finished [0<30>[ 20.843512] systemd[1]: Finished Remount Root and Kernel File Systems.
10857 20:13:12.523259 ;1;39mRemount Root and Kernel File Systems[0m.
10858 20:13:12.575000 [[0;32m OK [0m] Started [0;<30>[ 20.899326] systemd[1]: Started Journal Service.
10859 20:13:12.578754 1;39mJournal Service[0m.
10860 20:13:12.598848 Mounting [0;1;39mFUSE Control File System[0m...
10861 20:13:12.619835 Mounting [0;1;39mKernel Configuration File System[0m...
10862 20:13:12.645044 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10863 20:13:12.666169 Starting [0;1;39mLoad/Save Random Seed[0m...
10864 20:13:12.685771 Starting [0;1;39mApply Kernel Variables[0m...
10865 20:13:12.701022 <46>[ 21.024997] systemd-journald[310]: Received client request to flush runtime journal.
10866 20:13:12.735705 Starting [0;1;39mCreate System Users[<4>[ 21.052498] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10867 20:13:12.738966 0m...
10868 20:13:12.745391 <3>[ 21.052518] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10869 20:13:12.763350 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10870 20:13:12.774175 See 'systemctl status systemd-udev-trigger.service' for details.
10871 20:13:12.790843 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10872 20:13:12.806383 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10873 20:13:12.823312 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10874 20:13:13.458703 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10875 20:13:14.099867 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10876 20:13:14.157587 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10877 20:13:14.204452 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10878 20:13:14.298985 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10879 20:13:14.310483 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10880 20:13:14.325786 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10881 20:13:14.374512 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10882 20:13:14.400369 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10883 20:13:14.562585 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10884 20:13:14.633909 Starting [0;1;39mNetwork Service[0m...
10885 20:13:14.778882 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10886 20:13:14.910952 Starting [0;1;39mNetwork Time Synchronization[0m...
10887 20:13:14.931268 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10888 20:13:15.043985 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10889 20:13:15.347548 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10890 20:13:15.361945 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10891 20:13:15.381949 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10892 20:13:15.418227 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10893 20:13:15.435147 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10894 20:13:15.456686 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10895 20:13:15.474986 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10896 20:13:15.497197 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10897 20:13:15.514778 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10898 20:13:15.533586 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10899 20:13:15.546535 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10900 20:13:15.561825 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10901 20:13:15.591153 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10902 20:13:15.613062 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10903 20:13:16.154569 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10904 20:13:16.334095 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10905 20:13:16.345850 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10906 20:13:16.663914 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10907 20:13:16.677749 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10908 20:13:16.693749 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10909 20:13:16.758693 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10910 20:13:16.810361 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10911 20:13:16.887889 Starting [0;1;39mUser Login Management[0m...
10912 20:13:16.986216 Starting [0;1;39mNetwork Name Resolution[0m...
10913 20:13:17.006130 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10914 20:13:17.155000 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10915 20:13:17.171430 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10916 20:13:17.209590 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10917 20:13:17.682933 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10918 20:13:17.703677 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10919 20:13:17.725439 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10920 20:13:17.772992 Starting [0;1;39mPermit User Sessions[0m...
10921 20:13:17.807889 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10922 20:13:17.847904 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10923 20:13:17.896652 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10924 20:13:17.916010 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10925 20:13:17.930577 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10926 20:13:17.946675 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10927 20:13:18.000725 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10928 20:13:18.044275 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10929 20:13:18.114528
10930 20:13:18.114630
10931 20:13:18.118778 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10932 20:13:18.118863
10933 20:13:18.121790 debian-bullseye-arm64 login: root (automatic login)
10934 20:13:18.121874
10935 20:13:18.121960
10936 20:13:18.466693 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10937 20:13:18.466836
10938 20:13:18.473254 The programs included with the Debian GNU/Linux system are free software;
10939 20:13:18.480030 the exact distribution terms for each program are described in the
10940 20:13:18.483286 individual files in /usr/share/doc/*/copyright.
10941 20:13:18.483371
10942 20:13:18.489810 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10943 20:13:18.493481 permitted by applicable law.
10944 20:13:18.572290 Matched prompt #10: / #
10946 20:13:18.572587 Setting prompt string to ['/ #']
10947 20:13:18.572703 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10949 20:13:18.572935 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10950 20:13:18.573040 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10951 20:13:18.573123 Setting prompt string to ['/ #']
10952 20:13:18.573222 Forcing a shell prompt, looking for ['/ #']
10954 20:13:18.623513 / #
10955 20:13:18.623618 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10956 20:13:18.623718 Waiting using forced prompt support (timeout 00:02:30)
10957 20:13:18.628489
10958 20:13:18.628787 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10959 20:13:18.628929 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
10961 20:13:18.729304 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti'
10962 20:13:18.735175 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928089/extract-nfsrootfs-benhq7ti'
10964 20:13:18.835709 / # export NFS_SERVER_IP='192.168.201.1'
10965 20:13:18.840946 export NFS_SERVER_IP='192.168.201.1'
10966 20:13:18.841237 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10967 20:13:18.841341 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
10968 20:13:18.841429 end: 2 depthcharge-action (duration 00:01:43) [common]
10969 20:13:18.841520 start: 3 lava-test-retry (timeout 00:01:00) [common]
10970 20:13:18.841609 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10971 20:13:18.841686 Using namespace: common
10973 20:13:18.942016 / # #
10974 20:13:18.942130 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10975 20:13:18.947444 #
10976 20:13:18.947708 Using /lava-12928089
10978 20:13:19.048005 / # export SHELL=/bin/sh
10979 20:13:19.052893 export SHELL=/bin/sh
10981 20:13:19.153463 / # . /lava-12928089/environment
10982 20:13:19.158676 . /lava-12928089/environment
10984 20:13:19.265834 / # /lava-12928089/bin/lava-test-runner /lava-12928089/0
10985 20:13:19.265947 Test shell timeout: 10s (minimum of the action and connection timeout)
10986 20:13:19.270930 /lava-12928089/bin/lava-test-runner /lava-12928089/0
10987 20:13:19.515724 + export TESTRUN_ID=0_dmesg
10988 20:13:19.518939 + cd /lava-12928089/0/tests/0_dmesg
10989 20:13:19.522032 + cat uuid
10990 20:13:19.535982 + UUID=12928089_1.<8>[ 27.861030] <LAVA_SIGNAL_STARTRUN 0_dmesg 12928089_1.6.2.3.1>
10991 20:13:19.536153 6.2.3.1
10992 20:13:19.536283 + set +x
10993 20:13:19.536591 Received signal: <STARTRUN> 0_dmesg 12928089_1.6.2.3.1
10994 20:13:19.536709 Starting test lava.0_dmesg (12928089_1.6.2.3.1)
10995 20:13:19.536866 Skipping test definition patterns.
10996 20:13:19.542336 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10997 20:13:19.644044 <8>[ 27.965741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10998 20:13:19.644423 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11000 20:13:19.728291 <8>[ 28.051484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11001 20:13:19.728623 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11003 20:13:19.808565 + set +x
11004 20:13:19.814773 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11006 20:13:19.818145 <8>[ 28.139110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11007 20:13:19.824549 <8>[ 28.140102] <LAVA_SIGNAL_ENDRUN 0_dmesg 12928089_1.6.2.3.1>
11008 20:13:19.824851 Received signal: <ENDRUN> 0_dmesg 12928089_1.6.2.3.1
11009 20:13:19.824989 Ending use of test pattern.
11010 20:13:19.825103 Ending test lava.0_dmesg (12928089_1.6.2.3.1), duration 0.29
11012 20:13:19.828494 <LAVA_TEST_RUNNER EXIT>
11013 20:13:19.828794 ok: lava_test_shell seems to have completed
11014 20:13:19.828972 alert: pass
crit: pass
emerg: pass
11015 20:13:19.829121 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11016 20:13:19.829263 end: 3 lava-test-retry (duration 00:00:01) [common]
11017 20:13:19.829405 start: 4 lava-test-retry (timeout 00:01:00) [common]
11018 20:13:19.829546 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11019 20:13:19.829662 Using namespace: common
11021 20:13:19.930058 / # #
11022 20:13:19.930243 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11023 20:13:19.930430 Using /lava-12928089
11025 20:13:20.030816 export SHELL=/bin/sh
11026 20:13:20.031018 #
11028 20:13:20.131578 / # export SHELL=/bin/sh. /lava-12928089/environment
11029 20:13:20.131778
11031 20:13:20.232360 / # . /lava-12928089/environment/lava-12928089/bin/lava-test-runner /lava-12928089/1
11032 20:13:20.232517 Test shell timeout: 10s (minimum of the action and connection timeout)
11033 20:13:20.232692
11034 20:13:20.237558 / # /lava-12928089/bin/lava-test-runner /lava-12928089/1
11035 20:13:20.368515 + export TESTRUN_ID=1_bootrr
11036 20:13:20.371882 + cd /lava-12928089/1/tests/1_bootrr
11037 20:13:20.375059 + cat uuid
11038 20:13:20.381923 + UUID=12928089_1.6.2.3.5
11039 20:13:20.382006 + set +x
11040 20:13:20.392014 + export PATH<8>[ 28.714134] <LAVA_SIGNAL_STARTRUN 1_bootrr 12928089_1.6.2.3.5>
11041 20:13:20.392273 Received signal: <STARTRUN> 1_bootrr 12928089_1.6.2.3.5
11042 20:13:20.392343 Starting test lava.1_bootrr (12928089_1.6.2.3.5)
11043 20:13:20.392427 Skipping test definition patterns.
11044 20:13:20.401748 =/opt/bootrr/libexec/bootrr/helpers:/lava-12928089/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11045 20:13:20.404922 + cd /opt/bootrr/libexec/bootrr
11046 20:13:20.405005 + sh helpers/bootrr-auto
11047 20:13:20.468382 /lava-12928089/1/../bin/lava-test-case
11048 20:13:20.504642 <8>[ 28.828128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11049 20:13:20.504916 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11051 20:13:20.551638 /lava-12928089/1/../bin/lava-test-case
11052 20:13:20.584988 <8>[ 28.905652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11053 20:13:20.585255 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11055 20:13:20.607672 /lava-12928089/1/../bin/lava-test-case
11056 20:13:20.639921 <8>[ 28.963895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11057 20:13:20.640186 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11059 20:13:20.691638 /lava-12928089/1/../bin/lava-test-case
11060 20:13:20.725044 <8>[ 29.048868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11061 20:13:20.725403 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11063 20:13:20.765377 /lava-12928089/1/../bin/lava-test-case
11064 20:13:20.800244 <8>[ 29.122107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11065 20:13:20.800512 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11067 20:13:20.823619 /lava-12928089/1/../bin/lava-test-case
11068 20:13:20.856601 <8>[ 29.180009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11069 20:13:20.856868 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11071 20:13:20.892315 /lava-12928089/1/../bin/lava-test-case
11072 20:13:20.923881 <8>[ 29.248566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11073 20:13:20.924148 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11075 20:13:20.963723 /lava-12928089/1/../bin/lava-test-case
11076 20:13:20.996114 <8>[ 29.318881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11077 20:13:20.996378 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11079 20:13:21.017030 /lava-12928089/1/../bin/lava-test-case
11080 20:13:21.048445 <8>[ 29.372031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11081 20:13:21.048703 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11083 20:13:21.084299 /lava-12928089/1/../bin/lava-test-case
11084 20:13:21.116513 <8>[ 29.440332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11085 20:13:21.116806 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11087 20:13:21.148316 /lava-12928089/1/../bin/lava-test-case
11088 20:13:21.184320 <8>[ 29.507061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11089 20:13:21.184585 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11091 20:13:21.220917 /lava-12928089/1/../bin/lava-test-case
11092 20:13:21.255962 <8>[ 29.581012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11093 20:13:21.256258 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11095 20:13:21.296549 /lava-12928089/1/../bin/lava-test-case
11096 20:13:21.332461 <8>[ 29.655699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11097 20:13:21.332723 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11099 20:13:21.371680 /lava-12928089/1/../bin/lava-test-case
11100 20:13:21.408390 <8>[ 29.730291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11101 20:13:21.408656 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11103 20:13:21.450803 /lava-12928089/1/../bin/lava-test-case
11104 20:13:21.488404 <8>[ 29.810315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11105 20:13:21.488672 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11107 20:13:21.513509 /lava-12928089/1/../bin/lava-test-case
11108 20:13:21.548357 <8>[ 29.871273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11109 20:13:21.548620 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11111 20:13:21.588106 /lava-12928089/1/../bin/lava-test-case
11112 20:13:21.624127 <8>[ 29.947844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11113 20:13:21.624448 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11115 20:13:21.647628 /lava-12928089/1/../bin/lava-test-case
11116 20:13:21.679880 <8>[ 30.004660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11117 20:13:21.680190 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11119 20:13:21.719527 /lava-12928089/1/../bin/lava-test-case
11120 20:13:21.756229 <8>[ 30.077693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11121 20:13:21.756543 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11123 20:13:21.777777 /lava-12928089/1/../bin/lava-test-case
11124 20:13:21.812334 <8>[ 30.136177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11125 20:13:21.812601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11127 20:13:21.858087 /lava-12928089/1/../bin/lava-test-case
11128 20:13:21.892150 <8>[ 30.217377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11129 20:13:21.892413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11131 20:13:21.914725 /lava-12928089/1/../bin/lava-test-case
11132 20:13:21.948139 <8>[ 30.271549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11133 20:13:21.948463 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11135 20:13:21.986727 /lava-12928089/1/../bin/lava-test-case
11136 20:13:22.019952 <8>[ 30.343582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11137 20:13:22.020285 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11139 20:13:22.040480 /lava-12928089/1/../bin/lava-test-case
11140 20:13:22.079878 <8>[ 30.404417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11141 20:13:22.080180 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11143 20:13:22.120235 /lava-12928089/1/../bin/lava-test-case
11144 20:13:22.156028 <8>[ 30.478031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11145 20:13:22.156297 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11147 20:13:22.199856 /lava-12928089/1/../bin/lava-test-case
11148 20:13:22.235926 <8>[ 30.560034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11149 20:13:22.236191 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11151 20:13:22.259861 /lava-12928089/1/../bin/lava-test-case
11152 20:13:22.296121 <8>[ 30.618354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11153 20:13:22.296385 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11155 20:13:22.334722 /lava-12928089/1/../bin/lava-test-case
11156 20:13:22.367836 <8>[ 30.691839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11157 20:13:22.368098 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11159 20:13:22.392276 /lava-12928089/1/../bin/lava-test-case
11160 20:13:22.428477 <8>[ 30.750995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11161 20:13:22.428742 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11163 20:13:22.474052 /lava-12928089/1/../bin/lava-test-case
11164 20:13:22.508141 <8>[ 30.830180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11165 20:13:22.508405 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11167 20:13:22.542684 /lava-12928089/1/../bin/lava-test-case
11168 20:13:22.575840 <8>[ 30.899825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11169 20:13:22.576105 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11171 20:13:22.614996 /lava-12928089/1/../bin/lava-test-case
11172 20:13:22.648267 <8>[ 30.972668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11173 20:13:22.648542 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11175 20:13:22.687844 /lava-12928089/1/../bin/lava-test-case
11176 20:13:22.723997 <8>[ 31.046089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11177 20:13:22.724260 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11179 20:13:22.744557 /lava-12928089/1/../bin/lava-test-case
11180 20:13:22.779846 <8>[ 31.101744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11181 20:13:22.780110 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11183 20:13:22.820040 /lava-12928089/1/../bin/lava-test-case
11184 20:13:22.855930 <8>[ 31.179209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11185 20:13:22.856195 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11187 20:13:22.892962 /lava-12928089/1/../bin/lava-test-case
11188 20:13:22.928159 <8>[ 31.251302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11189 20:13:22.928422 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11191 20:13:22.950648 /lava-12928089/1/../bin/lava-test-case
11192 20:13:22.987888 <8>[ 31.309686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11193 20:13:22.988152 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11195 20:13:23.024107 /lava-12928089/1/../bin/lava-test-case
11196 20:13:23.059791 <8>[ 31.383105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11197 20:13:23.060082 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11199 20:13:23.088851 /lava-12928089/1/../bin/lava-test-case
11200 20:13:23.123799 <8>[ 31.448047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11201 20:13:23.124113 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11203 20:13:23.163012 /lava-12928089/1/../bin/lava-test-case
11204 20:13:23.200029 <8>[ 31.522206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11205 20:13:23.200361 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11207 20:13:23.222353 /lava-12928089/1/../bin/lava-test-case
11208 20:13:23.260582 <8>[ 31.584696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11209 20:13:23.260850 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11211 20:13:23.301037 /lava-12928089/1/../bin/lava-test-case
11212 20:13:23.335669 <8>[ 31.660482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11213 20:13:23.335933 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11215 20:13:23.359974 /lava-12928089/1/../bin/lava-test-case
11216 20:13:23.396589 <8>[ 31.717781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11217 20:13:23.396899 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11219 20:13:23.439263 /lava-12928089/1/../bin/lava-test-case
11220 20:13:23.475440 <8>[ 31.801013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11221 20:13:23.475758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11223 20:13:23.501500 /lava-12928089/1/../bin/lava-test-case
11224 20:13:23.535926 <8>[ 31.857614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11225 20:13:23.536233 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11227 20:13:23.571328 /lava-12928089/1/../bin/lava-test-case
11228 20:13:23.607741 <8>[ 31.930066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11229 20:13:23.608056 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11231 20:13:23.630015 /lava-12928089/1/../bin/lava-test-case
11232 20:13:23.663938 <8>[ 31.986673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11233 20:13:23.664247 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11235 20:13:23.701276 /lava-12928089/1/../bin/lava-test-case
11236 20:13:23.739976 <8>[ 32.063526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11237 20:13:23.740303 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11239 20:13:23.768518 /lava-12928089/1/../bin/lava-test-case
11240 20:13:23.799486 <8>[ 32.123843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11241 20:13:23.799799 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11243 20:13:23.839220 /lava-12928089/1/../bin/lava-test-case
11244 20:13:23.871723 <8>[ 32.196428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11245 20:13:23.872046 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11247 20:13:23.912815 /lava-12928089/1/../bin/lava-test-case
11248 20:13:23.952162 <8>[ 32.275051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11249 20:13:23.952481 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11251 20:13:23.975516 /lava-12928089/1/../bin/lava-test-case
11252 20:13:24.007674 <8>[ 32.331418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11253 20:13:24.007983 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11255 20:13:24.048013 /lava-12928089/1/../bin/lava-test-case
11256 20:13:24.084682 <8>[ 32.406140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11257 20:13:24.085014 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11259 20:13:24.112282 /lava-12928089/1/../bin/lava-test-case
11260 20:13:24.151802 <8>[ 32.473665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11261 20:13:24.152113 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11263 20:13:24.192638 /lava-12928089/1/../bin/lava-test-case
11264 20:13:24.227721 <8>[ 32.552746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11265 20:13:24.228040 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11267 20:13:24.266787 /lava-12928089/1/../bin/lava-test-case
11268 20:13:24.304138 <8>[ 32.627836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11269 20:13:24.304414 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11271 20:13:24.345586 /lava-12928089/1/../bin/lava-test-case
11272 20:13:24.384014 <8>[ 32.707311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11273 20:13:24.384292 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11275 20:13:24.424355 /lava-12928089/1/../bin/lava-test-case
11276 20:13:24.463570 <8>[ 32.787976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11277 20:13:24.463842 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11279 20:13:24.509377 /lava-12928089/1/../bin/lava-test-case
11280 20:13:24.547635 <8>[ 32.871216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11281 20:13:24.547900 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11283 20:13:24.570963 /lava-12928089/1/../bin/lava-test-case
11284 20:13:24.608227 <8>[ 32.932605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11285 20:13:24.608486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11287 20:13:24.649365 /lava-12928089/1/../bin/lava-test-case
11288 20:13:24.683814 <8>[ 33.007331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11289 20:13:24.684074 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11291 20:13:24.719260 /lava-12928089/1/../bin/lava-test-case
11292 20:13:24.755723 <8>[ 33.078104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11293 20:13:24.755985 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11295 20:13:24.776270 /lava-12928089/1/../bin/lava-test-case
11296 20:13:24.812115 <8>[ 33.135202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11297 20:13:24.812447 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11299 20:13:24.856601 /lava-12928089/1/../bin/lava-test-case
11300 20:13:24.891806 <8>[ 33.215635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11301 20:13:24.892120 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11303 20:13:24.913603 /lava-12928089/1/../bin/lava-test-case
11304 20:13:24.947309 <8>[ 33.270057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11305 20:13:24.947617 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11307 20:13:24.979518 /lava-12928089/1/../bin/lava-test-case
11308 20:13:25.011656 <8>[ 33.335194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11309 20:13:25.011968 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11311 20:13:25.033545 /lava-12928089/1/../bin/lava-test-case
11312 20:13:25.067275 <8>[ 33.392115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11313 20:13:25.067583 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11315 20:13:25.107099 /lava-12928089/1/../bin/lava-test-case
11316 20:13:25.147823 <8>[ 33.469584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11317 20:13:25.148148 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11319 20:13:25.192153 /lava-12928089/1/../bin/lava-test-case
11320 20:13:25.224327 <8>[ 33.548479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11321 20:13:25.224652 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11323 20:13:25.262757 /lava-12928089/1/../bin/lava-test-case
11324 20:13:25.299486 <8>[ 33.624872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11325 20:13:25.299802 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11327 20:13:25.341875 /lava-12928089/1/../bin/lava-test-case
11328 20:13:25.380183 <8>[ 33.702331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11329 20:13:25.380512 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11331 20:13:25.413416 /lava-12928089/1/../bin/lava-test-case
11332 20:13:25.447875 <8>[ 33.771702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11333 20:13:25.448186 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11335 20:13:25.484804 /lava-12928089/1/../bin/lava-test-case
11336 20:13:25.519577 <8>[ 33.841974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11337 20:13:25.519914 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11339 20:13:25.558346 /lava-12928089/1/../bin/lava-test-case
11340 20:13:25.591433 <8>[ 33.916735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11341 20:13:25.591751 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11343 20:13:25.632456 /lava-12928089/1/../bin/lava-test-case
11344 20:13:25.668053 <8>[ 33.991642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11345 20:13:25.668366 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11347 20:13:25.702580 /lava-12928089/1/../bin/lava-test-case
11348 20:13:25.739717 <8>[ 34.062549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11349 20:13:25.740035 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11351 20:13:25.775510 /lava-12928089/1/../bin/lava-test-case
11352 20:13:25.811679 <8>[ 34.134706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11353 20:13:25.811942 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11355 20:13:25.846364 /lava-12928089/1/../bin/lava-test-case
11356 20:13:25.879871 <8>[ 34.205135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11357 20:13:25.880200 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11359 20:13:25.922178 /lava-12928089/1/../bin/lava-test-case
11360 20:13:25.955461 <8>[ 34.281287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11361 20:13:25.955775 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11363 20:13:25.994511 /lava-12928089/1/../bin/lava-test-case
11364 20:13:26.031513 <8>[ 34.354980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11365 20:13:26.031830 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11367 20:13:26.068314 /lava-12928089/1/../bin/lava-test-case
11368 20:13:26.099486 <8>[ 34.424261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11369 20:13:26.099798 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11371 20:13:26.134920 /lava-12928089/1/../bin/lava-test-case
11372 20:13:26.167233 <8>[ 34.491341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11373 20:13:26.167543 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11375 20:13:26.191049 /lava-12928089/1/../bin/lava-test-case
11376 20:13:26.223510 <8>[ 34.547965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11377 20:13:26.223839 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11379 20:13:26.268704 /lava-12928089/1/../bin/lava-test-case
11380 20:13:26.303779 <8>[ 34.626786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11381 20:13:26.304093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11383 20:13:26.325199 /lava-12928089/1/../bin/lava-test-case
11384 20:13:26.359615 <8>[ 34.684035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11385 20:13:26.359874 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11387 20:13:26.399192 /lava-12928089/1/../bin/lava-test-case
11388 20:13:26.435829 <8>[ 34.760612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11389 20:13:26.436170 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11391 20:13:26.465090 /lava-12928089/1/../bin/lava-test-case
11392 20:13:26.499759 <8>[ 34.823712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11393 20:13:26.500077 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11395 20:13:26.537627 /lava-12928089/1/../bin/lava-test-case
11396 20:13:26.571168 <8>[ 34.896709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11397 20:13:26.571477 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11399 20:13:26.601250 /lava-12928089/1/../bin/lava-test-case
11400 20:13:26.635387 <8>[ 34.957642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11401 20:13:26.635708 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11403 20:13:26.669881 /lava-12928089/1/../bin/lava-test-case
11404 20:13:26.703053 <8>[ 35.025945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11405 20:13:26.703362 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11407 20:13:26.725500 /lava-12928089/1/../bin/lava-test-case
11408 20:13:26.759442 <8>[ 35.084616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11409 20:13:26.759755 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11411 20:13:26.798134 /lava-12928089/1/../bin/lava-test-case
11412 20:13:26.831529 <8>[ 35.157062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11413 20:13:26.831838 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11415 20:13:26.855654 /lava-12928089/1/../bin/lava-test-case
11416 20:13:26.891751 <8>[ 35.213889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11417 20:13:26.892072 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11419 20:13:26.933348 /lava-12928089/1/../bin/lava-test-case
11420 20:13:26.971732 <8>[ 35.294373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11421 20:13:26.972047 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11423 20:13:27.010506 /lava-12928089/1/../bin/lava-test-case
11424 20:13:27.047218 <8>[ 35.371911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11425 20:13:27.047532 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11427 20:13:27.072331 /lava-12928089/1/../bin/lava-test-case
11428 20:13:27.107208 <8>[ 35.433039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11429 20:13:27.107521 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11431 20:13:27.145566 /lava-12928089/1/../bin/lava-test-case
11432 20:13:27.179197 <8>[ 35.502820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11433 20:13:27.179505 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11435 20:13:27.201564 /lava-12928089/1/../bin/lava-test-case
11436 20:13:27.235089 <8>[ 35.558695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11437 20:13:27.235402 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11439 20:13:27.277092 /lava-12928089/1/../bin/lava-test-case
11440 20:13:27.315755 <8>[ 35.638442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11441 20:13:27.316066 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11443 20:13:27.337521 /lava-12928089/1/../bin/lava-test-case
11444 20:13:27.375245 <8>[ 35.699172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11445 20:13:27.375507 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11447 20:13:28.436383 /lava-12928089/1/../bin/lava-test-case
11448 20:13:28.471170 <8>[ 36.797142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11449 20:13:28.471460 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11451 20:13:28.490164 /lava-12928089/1/../bin/lava-test-case
11452 20:13:28.523233 <8>[ 36.849304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11453 20:13:28.523489 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11455 20:13:29.581700 /lava-12928089/1/../bin/lava-test-case
11456 20:13:29.619976 <8>[ 37.944766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11457 20:13:29.620247 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11459 20:13:29.637999 /lava-12928089/1/../bin/lava-test-case
11460 20:13:29.675001 <8>[ 38.000879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11461 20:13:29.675268 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11463 20:13:30.722958 /lava-12928089/1/../bin/lava-test-case
11464 20:13:30.758866 <8>[ 39.084999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11465 20:13:30.759233 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11467 20:13:30.777522 /lava-12928089/1/../bin/lava-test-case
11468 20:13:30.815243 <8>[ 39.137569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11469 20:13:30.815568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11471 20:13:31.852179 /lava-12928089/1/../bin/lava-test-case
11472 20:13:31.886663 <8>[ 40.212965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11473 20:13:31.887010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11475 20:13:31.900882 /lava-12928089/1/../bin/lava-test-case
11476 20:13:31.935949 <8>[ 40.257979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11477 20:13:31.936269 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11479 20:13:32.969018 /lava-12928089/1/../bin/lava-test-case
11480 20:13:33.003082 <8>[ 41.326355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11481 20:13:33.003428 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11483 20:13:33.015913 /lava-12928089/1/../bin/lava-test-case
11484 20:13:33.047119 <8>[ 41.372602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11485 20:13:33.047428 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11487 20:13:34.100380 /lava-12928089/1/../bin/lava-test-case
11488 20:13:34.139174 <8>[ 42.463681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11489 20:13:34.139520 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11491 20:13:34.153532 /lava-12928089/1/../bin/lava-test-case
11492 20:13:34.187478 <8>[ 42.511395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11493 20:13:34.187793 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11495 20:13:35.227036 /lava-12928089/1/../bin/lava-test-case
11496 20:13:35.262904 <8>[ 43.586961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11497 20:13:35.263179 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11499 20:13:35.276317 /lava-12928089/1/../bin/lava-test-case
11500 20:13:35.307049 <8>[ 43.632779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11501 20:13:35.307357 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11503 20:13:35.332051 /lava-12928089/1/../bin/lava-test-case
11504 20:13:35.367435 <8>[ 43.692716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11505 20:13:35.367754 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11507 20:13:35.704697 <6>[ 44.033883] vpu: disabling
11508 20:13:35.708240 <6>[ 44.034036] vproc2: disabling
11509 20:13:35.711988 <6>[ 44.034091] vproc1: disabling
11510 20:13:35.714879 <6>[ 44.034146] vaud18: disabling
11511 20:13:35.718567 <6>[ 44.034401] vsram_others: disabling
11512 20:13:35.721854 <6>[ 44.034581] va09: disabling
11513 20:13:35.724737 <6>[ 44.034659] vsram_md: disabling
11514 20:13:35.728390 <6>[ 44.034792] Vgpu: disabling
11515 20:13:36.414475 /lava-12928089/1/../bin/lava-test-case
11516 20:13:36.450750 <8>[ 44.775113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11517 20:13:36.451022 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11519 20:13:36.473207 /lava-12928089/1/../bin/lava-test-case
11520 20:13:36.506716 <8>[ 44.833273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11521 20:13:36.506974 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11523 20:13:36.545923 /lava-12928089/1/../bin/lava-test-case
11524 20:13:36.582796 <8>[ 44.907533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11525 20:13:36.583057 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11527 20:13:36.604745 /lava-12928089/1/../bin/lava-test-case
11528 20:13:36.638349 <8>[ 44.963190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11529 20:13:36.638652 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11531 20:13:36.666232 /lava-12928089/1/../bin/lava-test-case
11532 20:13:36.703745 <8>[ 45.026023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11533 20:13:36.704055 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11535 20:13:36.742173 /lava-12928089/1/../bin/lava-test-case
11536 20:13:36.779243 <8>[ 45.103645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11537 20:13:36.779506 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11539 20:13:36.809779 /lava-12928089/1/../bin/lava-test-case
11540 20:13:36.846744 <8>[ 45.171205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11541 20:13:36.847003 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11543 20:13:36.862940 /lava-12928089/1/../bin/lava-test-case
11544 20:13:36.898647 <8>[ 45.221825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11545 20:13:36.898913 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11547 20:13:36.930873 /lava-12928089/1/../bin/lava-test-case
11548 20:13:36.962980 <8>[ 45.289380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11549 20:13:36.963238 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11551 20:13:37.004135 /lava-12928089/1/../bin/lava-test-case
11552 20:13:37.039091 <8>[ 45.363696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11553 20:13:37.039351 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11555 20:13:37.057135 /lava-12928089/1/../bin/lava-test-case
11556 20:13:37.094983 <8>[ 45.417523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11557 20:13:37.095245 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11559 20:13:37.122580 /lava-12928089/1/../bin/lava-test-case
11560 20:13:37.154721 <8>[ 45.480808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11561 20:13:37.154983 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11563 20:13:37.170737 /lava-12928089/1/../bin/lava-test-case
11564 20:13:37.206838 <8>[ 45.531552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11565 20:13:37.207099 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11567 20:13:37.235903 /lava-12928089/1/../bin/lava-test-case
11568 20:13:37.270834 <8>[ 45.594226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11569 20:13:37.271134 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11571 20:13:37.283227 /lava-12928089/1/../bin/lava-test-case
11572 20:13:37.318624 <8>[ 45.642837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11573 20:13:37.318915 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11575 20:13:37.343534 /lava-12928089/1/../bin/lava-test-case
11576 20:13:37.379356 <8>[ 45.704814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11577 20:13:37.379663 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11579 20:13:37.398870 /lava-12928089/1/../bin/lava-test-case
11580 20:13:37.435119 <8>[ 45.757651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11581 20:13:37.435380 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11583 20:13:37.460576 /lava-12928089/1/../bin/lava-test-case
11584 20:13:37.494588 <8>[ 45.820000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11585 20:13:37.494845 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11587 20:13:37.509651 /lava-12928089/1/../bin/lava-test-case
11588 20:13:37.547459 <8>[ 45.870376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11589 20:13:37.547713 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11591 20:13:37.575059 /lava-12928089/1/../bin/lava-test-case
11592 20:13:37.610683 <8>[ 45.935883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11593 20:13:37.610945 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11595 20:13:37.624814 /lava-12928089/1/../bin/lava-test-case
11596 20:13:37.663047 <8>[ 45.985482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11597 20:13:37.663307 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11599 20:13:38.699767 /lava-12928089/1/../bin/lava-test-case
11600 20:13:38.739514 <8>[ 47.062428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11601 20:13:38.739856 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11603 20:13:39.779043 /lava-12928089/1/../bin/lava-test-case
11604 20:13:39.815027 <8>[ 48.140206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11605 20:13:39.815301 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11607 20:13:39.827228 /lava-12928089/1/../bin/lava-test-case
11608 20:13:39.858371 <8>[ 48.182559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11609 20:13:39.858654 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11611 20:13:39.882939 /lava-12928089/1/../bin/lava-test-case
11612 20:13:39.918639 <8>[ 48.241744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11613 20:13:39.918903 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11615 20:13:39.930043 /lava-12928089/1/../bin/lava-test-case
11616 20:13:39.966145 <8>[ 48.289787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11617 20:13:39.966410 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11619 20:13:39.992553 /lava-12928089/1/../bin/lava-test-case
11620 20:13:40.026381 <8>[ 48.351642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11621 20:13:40.026658 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11623 20:13:40.039690 /lava-12928089/1/../bin/lava-test-case
11624 20:13:40.074701 <8>[ 48.397524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11625 20:13:40.074959 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11627 20:13:40.104859 /lava-12928089/1/../bin/lava-test-case
11628 20:13:40.138825 <8>[ 48.465391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11629 20:13:40.139087 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11631 20:13:40.153615 /lava-12928089/1/../bin/lava-test-case
11632 20:13:40.186570 <8>[ 48.512773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11633 20:13:40.186831 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11635 20:13:40.217037 /lava-12928089/1/../bin/lava-test-case
11636 20:13:40.250591 <8>[ 48.577275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11637 20:13:40.250854 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11639 20:13:40.266267 /lava-12928089/1/../bin/lava-test-case
11640 20:13:40.302266 <8>[ 48.627000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11641 20:13:40.302551 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11643 20:13:40.331476 /lava-12928089/1/../bin/lava-test-case
11644 20:13:40.366081 <8>[ 48.691933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11645 20:13:40.366342 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11647 20:13:40.381768 /lava-12928089/1/../bin/lava-test-case
11648 20:13:40.418628 <8>[ 48.742935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11649 20:13:40.418886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11651 20:13:40.453401 /lava-12928089/1/../bin/lava-test-case
11652 20:13:40.490620 <8>[ 48.814165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11653 20:13:40.490887 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11655 20:13:40.504432 /lava-12928089/1/../bin/lava-test-case
11656 20:13:40.538531 <8>[ 48.864276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11657 20:13:40.538793 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11659 20:13:40.568265 /lava-12928089/1/../bin/lava-test-case
11660 20:13:40.606563 <8>[ 48.931347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11661 20:13:40.606862 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11663 20:13:40.621602 /lava-12928089/1/../bin/lava-test-case
11664 20:13:40.658255 <8>[ 48.983384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11665 20:13:40.658541 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11667 20:13:40.688282 /lava-12928089/1/../bin/lava-test-case
11668 20:13:40.722066 <8>[ 49.047585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11669 20:13:40.722327 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11671 20:13:40.737544 /lava-12928089/1/../bin/lava-test-case
11672 20:13:40.775035 <8>[ 49.099869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11673 20:13:40.775305 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11675 20:13:40.808817 /lava-12928089/1/../bin/lava-test-case
11676 20:13:40.842990 <8>[ 49.168233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11677 20:13:40.843250 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11679 20:13:40.855648 /lava-12928089/1/../bin/lava-test-case
11680 20:13:40.890262 <8>[ 49.214703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11681 20:13:40.890569 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11683 20:13:40.920382 /lava-12928089/1/../bin/lava-test-case
11684 20:13:40.953852 <8>[ 49.280600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11685 20:13:40.954113 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11687 20:13:41.981283 /lava-12928089/1/../bin/lava-test-case
11688 20:13:42.021919 <8>[ 50.345902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11689 20:13:42.022203 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11691 20:13:43.049993 /lava-12928089/1/../bin/lava-test-case
11692 20:13:43.086581 <8>[ 51.413230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11693 20:13:43.086872 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11694 20:13:43.086973 Bad test result: blocked
11695 20:13:43.105555 /lava-12928089/1/../bin/lava-test-case
11696 20:13:43.142483 <8>[ 51.465494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11697 20:13:43.142760 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11699 20:13:44.179458 /lava-12928089/1/../bin/lava-test-case
11700 20:13:44.218875 <8>[ 52.544752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11701 20:13:44.219172 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11703 20:13:44.236179 /lava-12928089/1/../bin/lava-test-case
11704 20:13:44.273676 <8>[ 52.597954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11705 20:13:44.273978 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11707 20:13:44.305038 /lava-12928089/1/../bin/lava-test-case
11708 20:13:44.345845 <8>[ 52.670000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11709 20:13:44.346135 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11711 20:13:44.375684 /lava-12928089/1/../bin/lava-test-case
11712 20:13:44.409866 <8>[ 52.737402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11713 20:13:44.410125 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11715 20:13:44.432875 /lava-12928089/1/../bin/lava-test-case
11716 20:13:44.473836 <8>[ 52.800785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11717 20:13:44.474103 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11719 20:13:44.516165 /lava-12928089/1/../bin/lava-test-case
11720 20:13:44.554821 <8>[ 52.881381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11721 20:13:44.555085 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11723 20:13:44.572414 /lava-12928089/1/../bin/lava-test-case
11724 20:13:44.611044 <8>[ 52.934197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11725 20:13:44.611304 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11727 20:13:45.651811 /lava-12928089/1/../bin/lava-test-case
11728 20:13:45.693641 <8>[ 54.018472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11729 20:13:45.693923 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11731 20:13:45.707200 /lava-12928089/1/../bin/lava-test-case
11732 20:13:45.741663 <8>[ 54.066703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11733 20:13:45.741930 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11735 20:13:46.778529 /lava-12928089/1/../bin/lava-test-case
11736 20:13:46.817615 <8>[ 55.142532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11737 20:13:46.817892 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11739 20:13:46.832106 /lava-12928089/1/../bin/lava-test-case
11740 20:13:46.869754 <8>[ 55.195729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11741 20:13:46.870018 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11743 20:13:47.917147 /lava-12928089/1/../bin/lava-test-case
11744 20:13:47.953539 <8>[ 56.280705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11745 20:13:47.953822 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11747 20:13:47.968074 /lava-12928089/1/../bin/lava-test-case
11748 20:13:48.005140 <8>[ 56.329681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11749 20:13:48.005407 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11751 20:13:49.046543 /lava-12928089/1/../bin/lava-test-case
11752 20:13:49.093418 <8>[ 57.417932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11753 20:13:49.093707 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11755 20:13:49.107040 /lava-12928089/1/../bin/lava-test-case
11756 20:13:49.141335 <8>[ 57.468488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11757 20:13:49.141594 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11759 20:13:49.171301 /lava-12928089/1/../bin/lava-test-case
11760 20:13:49.209953 <8>[ 57.534669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11761 20:13:49.210221 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11763 20:13:49.236633 /lava-12928089/1/../bin/lava-test-case
11764 20:13:49.273761 <8>[ 57.598536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11765 20:13:49.274025 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11767 20:13:49.286887 /lava-12928089/1/../bin/lava-test-case
11768 20:13:49.321516 <8>[ 57.646350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11769 20:13:49.321804 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11771 20:13:49.345962 /lava-12928089/1/../bin/lava-test-case
11772 20:13:49.381686 <8>[ 57.706384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11773 20:13:49.381964 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11775 20:13:49.402898 /lava-12928089/1/../bin/lava-test-case
11776 20:13:49.442046 <8>[ 57.766426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11777 20:13:49.442407 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11779 20:13:49.468136 /lava-12928089/1/../bin/lava-test-case
11780 20:13:49.502066 <8>[ 57.827054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11781 20:13:49.502329 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11783 20:13:49.513834 /lava-12928089/1/../bin/lava-test-case
11784 20:13:49.549715 <8>[ 57.874455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11785 20:13:49.549974 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11787 20:13:49.578899 /lava-12928089/1/../bin/lava-test-case
11788 20:13:49.617780 <8>[ 57.943460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11789 20:13:49.617895 + set +x
11790 20:13:49.618163 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11792 20:13:49.626179 <8>[ 57.954477] <LAVA_SIGNAL_ENDRUN 1_bootrr 12928089_1.6.2.3.5>
11793 20:13:49.626432 Received signal: <ENDRUN> 1_bootrr 12928089_1.6.2.3.5
11794 20:13:49.626521 Ending use of test pattern.
11795 20:13:49.626584 Ending test lava.1_bootrr (12928089_1.6.2.3.5), duration 29.23
11797 20:13:49.629296 <LAVA_TEST_RUNNER EXIT>
11798 20:13:49.629545 ok: lava_test_shell seems to have completed
11799 20:13:49.630783 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11800 20:13:49.630929 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11801 20:13:49.631015 end: 4 lava-test-retry (duration 00:00:30) [common]
11802 20:13:49.631102 start: 5 finalize (timeout 00:07:16) [common]
11803 20:13:49.631188 start: 5.1 power-off (timeout 00:00:30) [common]
11804 20:13:49.631337 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11805 20:13:49.707675 >> Command sent successfully.
11806 20:13:49.710185 Returned 0 in 0 seconds
11807 20:13:49.810578 end: 5.1 power-off (duration 00:00:00) [common]
11809 20:13:49.810887 start: 5.2 read-feedback (timeout 00:07:16) [common]
11810 20:13:49.811154 Listened to connection for namespace 'common' for up to 1s
11811 20:13:50.812116 Finalising connection for namespace 'common'
11812 20:13:50.812298 Disconnecting from shell: Finalise
11813 20:13:50.812382 / #
11814 20:13:50.912721 end: 5.2 read-feedback (duration 00:00:01) [common]
11815 20:13:50.912877 end: 5 finalize (duration 00:00:01) [common]
11816 20:13:50.912994 Cleaning after the job
11817 20:13:50.913094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/ramdisk
11818 20:13:50.916036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/kernel
11819 20:13:50.929056 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/dtb
11820 20:13:50.929233 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/nfsrootfs
11821 20:13:51.003313 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928089/tftp-deploy-u_hjodma/modules
11822 20:13:51.010445 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928089
11823 20:13:51.391786 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928089
11824 20:13:51.391969 Job finished correctly