Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 29
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 13
1 20:10:19.523673 lava-dispatcher, installed at version: 2024.01
2 20:10:19.523890 start: 0 validate
3 20:10:19.524019 Start time: 2024-03-03 20:10:19.524010+00:00 (UTC)
4 20:10:19.524136 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:10:19.524269 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240129.0%2Farm64%2Frootfs.cpio.gz exists
6 20:10:19.795745 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:10:19.796466 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:10:44.810724 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:10:44.811416 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:10:45.084793 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:10:45.085542 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:10:48.853072 validate duration: 29.33
14 20:10:48.853374 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:10:48.853489 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:10:48.853589 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:10:48.853727 Not decompressing ramdisk as can be used compressed.
18 20:10:48.853820 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240129.0/arm64/rootfs.cpio.gz
19 20:10:48.853893 saving as /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/ramdisk/rootfs.cpio.gz
20 20:10:48.853994 total size: 47861385 (45 MB)
21 20:10:48.855554 progress 0 % (0 MB)
22 20:10:48.868743 progress 5 % (2 MB)
23 20:10:48.882007 progress 10 % (4 MB)
24 20:10:48.894798 progress 15 % (6 MB)
25 20:10:48.907804 progress 20 % (9 MB)
26 20:10:48.920673 progress 25 % (11 MB)
27 20:10:48.933455 progress 30 % (13 MB)
28 20:10:48.946374 progress 35 % (16 MB)
29 20:10:48.959200 progress 40 % (18 MB)
30 20:10:48.972272 progress 45 % (20 MB)
31 20:10:48.984919 progress 50 % (22 MB)
32 20:10:48.997592 progress 55 % (25 MB)
33 20:10:49.010499 progress 60 % (27 MB)
34 20:10:49.023765 progress 65 % (29 MB)
35 20:10:49.036601 progress 70 % (31 MB)
36 20:10:49.049498 progress 75 % (34 MB)
37 20:10:49.062358 progress 80 % (36 MB)
38 20:10:49.075013 progress 85 % (38 MB)
39 20:10:49.087648 progress 90 % (41 MB)
40 20:10:49.099776 progress 95 % (43 MB)
41 20:10:49.111888 progress 100 % (45 MB)
42 20:10:49.112185 45 MB downloaded in 0.26 s (176.79 MB/s)
43 20:10:49.112420 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:10:49.112662 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:10:49.112823 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:10:49.112909 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:10:49.113049 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:10:49.113117 saving as /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/kernel/Image
50 20:10:49.113177 total size: 51601920 (49 MB)
51 20:10:49.113237 No compression specified
52 20:10:49.114355 progress 0 % (0 MB)
53 20:10:49.127689 progress 5 % (2 MB)
54 20:10:49.141360 progress 10 % (4 MB)
55 20:10:49.155161 progress 15 % (7 MB)
56 20:10:49.168584 progress 20 % (9 MB)
57 20:10:49.182085 progress 25 % (12 MB)
58 20:10:49.195620 progress 30 % (14 MB)
59 20:10:49.209271 progress 35 % (17 MB)
60 20:10:49.222654 progress 40 % (19 MB)
61 20:10:49.236157 progress 45 % (22 MB)
62 20:10:49.249756 progress 50 % (24 MB)
63 20:10:49.264291 progress 55 % (27 MB)
64 20:10:49.278967 progress 60 % (29 MB)
65 20:10:49.293243 progress 65 % (32 MB)
66 20:10:49.307560 progress 70 % (34 MB)
67 20:10:49.322245 progress 75 % (36 MB)
68 20:10:49.336528 progress 80 % (39 MB)
69 20:10:49.351014 progress 85 % (41 MB)
70 20:10:49.365367 progress 90 % (44 MB)
71 20:10:49.379811 progress 95 % (46 MB)
72 20:10:49.393738 progress 100 % (49 MB)
73 20:10:49.394014 49 MB downloaded in 0.28 s (175.23 MB/s)
74 20:10:49.394171 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:10:49.394456 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:10:49.394574 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:10:49.394660 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:10:49.394798 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:10:49.394872 saving as /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/dtb/mt8192-asurada-spherion-r0.dtb
81 20:10:49.394932 total size: 47278 (0 MB)
82 20:10:49.394992 No compression specified
83 20:10:49.396179 progress 69 % (0 MB)
84 20:10:49.396560 progress 100 % (0 MB)
85 20:10:49.396792 0 MB downloaded in 0.00 s (24.45 MB/s)
86 20:10:49.396915 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:10:49.397132 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:10:49.397220 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:10:49.397303 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:10:49.397415 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:10:49.397481 saving as /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/modules/modules.tar
93 20:10:49.397540 total size: 8632284 (8 MB)
94 20:10:49.397599 Using unxz to decompress xz
95 20:10:49.401884 progress 0 % (0 MB)
96 20:10:49.422416 progress 5 % (0 MB)
97 20:10:49.446635 progress 10 % (0 MB)
98 20:10:49.470889 progress 15 % (1 MB)
99 20:10:49.493746 progress 20 % (1 MB)
100 20:10:49.518862 progress 25 % (2 MB)
101 20:10:49.545293 progress 30 % (2 MB)
102 20:10:49.572097 progress 35 % (2 MB)
103 20:10:49.597726 progress 40 % (3 MB)
104 20:10:49.622572 progress 45 % (3 MB)
105 20:10:49.647956 progress 50 % (4 MB)
106 20:10:49.673138 progress 55 % (4 MB)
107 20:10:49.698720 progress 60 % (4 MB)
108 20:10:49.723528 progress 65 % (5 MB)
109 20:10:49.749289 progress 70 % (5 MB)
110 20:10:49.775558 progress 75 % (6 MB)
111 20:10:49.802832 progress 80 % (6 MB)
112 20:10:49.828340 progress 85 % (7 MB)
113 20:10:49.855489 progress 90 % (7 MB)
114 20:10:49.885563 progress 95 % (7 MB)
115 20:10:49.914403 progress 100 % (8 MB)
116 20:10:49.919875 8 MB downloaded in 0.52 s (15.76 MB/s)
117 20:10:49.920123 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:10:49.920385 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:10:49.920480 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:10:49.920578 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:10:49.920656 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:10:49.920788 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:10:49.921014 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z
125 20:10:49.921150 makedir: /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin
126 20:10:49.921256 makedir: /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/tests
127 20:10:49.921356 makedir: /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/results
128 20:10:49.921470 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-add-keys
129 20:10:49.921622 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-add-sources
130 20:10:49.921753 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-background-process-start
131 20:10:49.921884 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-background-process-stop
132 20:10:49.922013 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-common-functions
133 20:10:49.922141 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-echo-ipv4
134 20:10:49.922268 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-install-packages
135 20:10:49.922396 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-installed-packages
136 20:10:49.922522 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-os-build
137 20:10:49.922649 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-probe-channel
138 20:10:49.922777 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-probe-ip
139 20:10:49.922904 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-target-ip
140 20:10:49.923030 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-target-mac
141 20:10:49.923156 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-target-storage
142 20:10:49.923286 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-case
143 20:10:49.923413 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-event
144 20:10:49.923536 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-feedback
145 20:10:49.923662 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-raise
146 20:10:49.923786 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-reference
147 20:10:49.923914 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-runner
148 20:10:49.924041 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-set
149 20:10:49.924169 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-test-shell
150 20:10:49.924301 Updating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-install-packages (oe)
151 20:10:49.924454 Updating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/bin/lava-installed-packages (oe)
152 20:10:49.924580 Creating /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/environment
153 20:10:49.924683 LAVA metadata
154 20:10:49.924809 - LAVA_JOB_ID=12928083
155 20:10:49.924874 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:10:49.924978 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:10:49.925045 skipped lava-vland-overlay
158 20:10:49.925118 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:10:49.925201 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:10:49.925263 skipped lava-multinode-overlay
161 20:10:49.925335 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:10:49.925441 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:10:49.925518 Loading test definitions
164 20:10:49.925613 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 20:10:49.925684 Using /lava-12928083 at stage 0
166 20:10:49.925995 uuid=12928083_1.5.2.3.1 testdef=None
167 20:10:49.926083 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 20:10:49.926171 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 20:10:49.926714 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 20:10:49.926935 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 20:10:49.927586 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 20:10:49.927815 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 20:10:49.928504 runner path: /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/0/tests/0_igt-kms-mediatek test_uuid 12928083_1.5.2.3.1
176 20:10:49.928712 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 20:10:49.928957 Creating lava-test-runner.conf files
179 20:10:49.929019 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928083/lava-overlay-8fk742_z/lava-12928083/0 for stage 0
180 20:10:49.929110 - 0_igt-kms-mediatek
181 20:10:49.929207 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 20:10:49.929292 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 20:10:49.936550 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 20:10:49.936657 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 20:10:49.936796 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 20:10:49.936883 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 20:10:49.936969 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 20:10:51.780988 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 20:10:51.781382 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 20:10:51.781495 extracting modules file /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928083/extract-overlay-ramdisk-mgowgpei/ramdisk
191 20:10:52.013785 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 20:10:52.013956 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 20:10:52.014057 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928083/compress-overlay-zckez4dt/overlay-1.5.2.4.tar.gz to ramdisk
194 20:10:52.014129 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928083/compress-overlay-zckez4dt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928083/extract-overlay-ramdisk-mgowgpei/ramdisk
195 20:10:52.020997 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 20:10:52.021120 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 20:10:52.021215 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 20:10:52.021310 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 20:10:52.021389 Building ramdisk /var/lib/lava/dispatcher/tmp/12928083/extract-overlay-ramdisk-mgowgpei/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928083/extract-overlay-ramdisk-mgowgpei/ramdisk
200 20:10:53.291796 >> 465519 blocks
201 20:10:59.459944 rename /var/lib/lava/dispatcher/tmp/12928083/extract-overlay-ramdisk-mgowgpei/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/ramdisk/ramdisk.cpio.gz
202 20:10:59.460421 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 20:10:59.460557 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 20:10:59.460709 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 20:10:59.460875 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/kernel/Image'
206 20:11:12.647622 Returned 0 in 13 seconds
207 20:11:12.748297 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/kernel/image.itb
208 20:11:13.666367 output: FIT description: Kernel Image image with one or more FDT blobs
209 20:11:13.666740 output: Created: Sun Mar 3 20:11:13 2024
210 20:11:13.666845 output: Image 0 (kernel-1)
211 20:11:13.666934 output: Description:
212 20:11:13.667020 output: Created: Sun Mar 3 20:11:13 2024
213 20:11:13.667104 output: Type: Kernel Image
214 20:11:13.667185 output: Compression: lzma compressed
215 20:11:13.667265 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
216 20:11:13.667363 output: Architecture: AArch64
217 20:11:13.667458 output: OS: Linux
218 20:11:13.667552 output: Load Address: 0x00000000
219 20:11:13.667648 output: Entry Point: 0x00000000
220 20:11:13.667743 output: Hash algo: crc32
221 20:11:13.667839 output: Hash value: 91cb1a17
222 20:11:13.667936 output: Image 1 (fdt-1)
223 20:11:13.668032 output: Description: mt8192-asurada-spherion-r0
224 20:11:13.668128 output: Created: Sun Mar 3 20:11:13 2024
225 20:11:13.668220 output: Type: Flat Device Tree
226 20:11:13.668312 output: Compression: uncompressed
227 20:11:13.668404 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 20:11:13.668496 output: Architecture: AArch64
229 20:11:13.668588 output: Hash algo: crc32
230 20:11:13.668679 output: Hash value: cc4352de
231 20:11:13.668817 output: Image 2 (ramdisk-1)
232 20:11:13.668910 output: Description: unavailable
233 20:11:13.669002 output: Created: Sun Mar 3 20:11:13 2024
234 20:11:13.669101 output: Type: RAMDisk Image
235 20:11:13.669190 output: Compression: Unknown Compression
236 20:11:13.669282 output: Data Size: 61002098 Bytes = 59572.36 KiB = 58.18 MiB
237 20:11:13.669375 output: Architecture: AArch64
238 20:11:13.669466 output: OS: Linux
239 20:11:13.669551 output: Load Address: unavailable
240 20:11:13.669635 output: Entry Point: unavailable
241 20:11:13.669718 output: Hash algo: crc32
242 20:11:13.669801 output: Hash value: 2b159638
243 20:11:13.669883 output: Default Configuration: 'conf-1'
244 20:11:13.669965 output: Configuration 0 (conf-1)
245 20:11:13.670047 output: Description: mt8192-asurada-spherion-r0
246 20:11:13.670129 output: Kernel: kernel-1
247 20:11:13.670211 output: Init Ramdisk: ramdisk-1
248 20:11:13.670293 output: FDT: fdt-1
249 20:11:13.670375 output: Loadables: kernel-1
250 20:11:13.670456 output:
251 20:11:13.670699 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 20:11:13.670826 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 20:11:13.670962 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 20:11:13.671090 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 20:11:13.671200 No LXC device requested
256 20:11:13.671312 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 20:11:13.671430 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 20:11:13.671540 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 20:11:13.671641 Checking files for TFTP limit of 4294967296 bytes.
260 20:11:13.672272 end: 1 tftp-deploy (duration 00:00:25) [common]
261 20:11:13.672378 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 20:11:13.672472 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 20:11:13.672603 substitutions:
264 20:11:13.672672 - {DTB}: 12928083/tftp-deploy-mbpqjfca/dtb/mt8192-asurada-spherion-r0.dtb
265 20:11:13.672786 - {INITRD}: 12928083/tftp-deploy-mbpqjfca/ramdisk/ramdisk.cpio.gz
266 20:11:13.672848 - {KERNEL}: 12928083/tftp-deploy-mbpqjfca/kernel/Image
267 20:11:13.672906 - {LAVA_MAC}: None
268 20:11:13.672964 - {PRESEED_CONFIG}: None
269 20:11:13.673020 - {PRESEED_LOCAL}: None
270 20:11:13.673075 - {RAMDISK}: 12928083/tftp-deploy-mbpqjfca/ramdisk/ramdisk.cpio.gz
271 20:11:13.673130 - {ROOT_PART}: None
272 20:11:13.673184 - {ROOT}: None
273 20:11:13.673237 - {SERVER_IP}: 192.168.201.1
274 20:11:13.673291 - {TEE}: None
275 20:11:13.673345 Parsed boot commands:
276 20:11:13.673399 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 20:11:13.673582 Parsed boot commands: tftpboot 192.168.201.1 12928083/tftp-deploy-mbpqjfca/kernel/image.itb 12928083/tftp-deploy-mbpqjfca/kernel/cmdline
278 20:11:13.673671 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 20:11:13.673760 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 20:11:13.673855 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 20:11:13.673939 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 20:11:13.674013 Not connected, no need to disconnect.
283 20:11:13.674088 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 20:11:13.674170 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 20:11:13.674238 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 20:11:13.678399 Setting prompt string to ['lava-test: # ']
287 20:11:13.678805 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 20:11:13.678912 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 20:11:13.679025 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 20:11:13.679140 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 20:11:13.679362 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 20:11:18.817822 >> Command sent successfully.
293 20:11:18.828471 Returned 0 in 5 seconds
294 20:11:18.929731 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 20:11:18.931328 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 20:11:18.931993 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 20:11:18.932431 Setting prompt string to 'Starting depthcharge on Spherion...'
299 20:11:18.932835 Changing prompt to 'Starting depthcharge on Spherion...'
300 20:11:18.933193 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 20:11:18.934438 [Enter `^Ec?' for help]
302 20:11:19.105683
303 20:11:19.106262
304 20:11:19.106780 F0: 102B 0000
305 20:11:19.107266
306 20:11:19.107801 F3: 1001 0000 [0200]
307 20:11:19.108220
308 20:11:19.109641 F3: 1001 0000
309 20:11:19.110296
310 20:11:19.110833 F7: 102D 0000
311 20:11:19.111203
312 20:11:19.111530 F1: 0000 0000
313 20:11:19.111959
314 20:11:19.113120 V0: 0000 0000 [0001]
315 20:11:19.113545
316 20:11:19.113882 00: 0007 8000
317 20:11:19.114258
318 20:11:19.116671 01: 0000 0000
319 20:11:19.117202
320 20:11:19.117587 BP: 0C00 0209 [0000]
321 20:11:19.117935
322 20:11:19.120484 G0: 1182 0000
323 20:11:19.121017
324 20:11:19.121381 EC: 0000 0021 [4000]
325 20:11:19.121695
326 20:11:19.123776 S7: 0000 0000 [0000]
327 20:11:19.124202
328 20:11:19.124539 CC: 0000 0000 [0001]
329 20:11:19.124920
330 20:11:19.127456 T0: 0000 0040 [010F]
331 20:11:19.127893
332 20:11:19.128229 Jump to BL
333 20:11:19.128538
334 20:11:19.152781
335 20:11:19.153278
336 20:11:19.153665
337 20:11:19.159257 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 20:11:19.162969 ARM64: Exception handlers installed.
339 20:11:19.166344 ARM64: Testing exception
340 20:11:19.169995 ARM64: Done test exception
341 20:11:19.176385 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 20:11:19.186520 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 20:11:19.193414 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 20:11:19.204007 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 20:11:19.210427 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 20:11:19.216825 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 20:11:19.229313 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 20:11:19.235797 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 20:11:19.255067 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 20:11:19.258610 WDT: Last reset was cold boot
351 20:11:19.261566 SPI1(PAD0) initialized at 2873684 Hz
352 20:11:19.265282 SPI5(PAD0) initialized at 992727 Hz
353 20:11:19.268276 VBOOT: Loading verstage.
354 20:11:19.275057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 20:11:19.278175 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 20:11:19.281501 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 20:11:19.284958 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 20:11:19.292569 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 20:11:19.299839 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 20:11:19.310053 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 20:11:19.310542
362 20:11:19.310876
363 20:11:19.320657 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 20:11:19.323905 ARM64: Exception handlers installed.
365 20:11:19.326758 ARM64: Testing exception
366 20:11:19.327442 ARM64: Done test exception
367 20:11:19.334060 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 20:11:19.337097 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 20:11:19.351829 Probing TPM: . done!
370 20:11:19.352556 TPM ready after 0 ms
371 20:11:19.358362 Connected to device vid:did:rid of 1ae0:0028:00
372 20:11:19.364815 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 20:11:19.370073 Initialized TPM device CR50 revision 0
374 20:11:19.417818 tlcl_send_startup: Startup return code is 0
375 20:11:19.418379 TPM: setup succeeded
376 20:11:19.429307 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 20:11:19.438053 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 20:11:19.448952 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 20:11:19.457205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 20:11:19.460749 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 20:11:19.464098 in-header: 03 07 00 00 08 00 00 00
382 20:11:19.467342 in-data: aa e4 47 04 13 02 00 00
383 20:11:19.470647 Chrome EC: UHEPI supported
384 20:11:19.477456 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 20:11:19.480474 in-header: 03 9d 00 00 08 00 00 00
386 20:11:19.483506 in-data: 10 20 20 08 00 00 00 00
387 20:11:19.484069 Phase 1
388 20:11:19.487201 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 20:11:19.493875 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 20:11:19.500520 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 20:11:19.503429 Recovery requested (1009000e)
392 20:11:19.509965 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 20:11:19.515688 tlcl_extend: response is 0
394 20:11:19.523950 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 20:11:19.529131 tlcl_extend: response is 0
396 20:11:19.535986 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 20:11:19.556901 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 20:11:19.563570 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 20:11:19.564133
400 20:11:19.564501
401 20:11:19.573142 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 20:11:19.576283 ARM64: Exception handlers installed.
403 20:11:19.579535 ARM64: Testing exception
404 20:11:19.580133 ARM64: Done test exception
405 20:11:19.602373 pmic_efuse_setting: Set efuses in 11 msecs
406 20:11:19.606243 pmwrap_interface_init: Select PMIF_VLD_RDY
407 20:11:19.612049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 20:11:19.616252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 20:11:19.619326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 20:11:19.627047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 20:11:19.630349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 20:11:19.634019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 20:11:19.641428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 20:11:19.644917 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 20:11:19.648105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 20:11:19.654746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 20:11:19.657947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 20:11:19.664610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 20:11:19.667707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 20:11:19.674656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 20:11:19.680927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 20:11:19.684260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 20:11:19.692268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 20:11:19.698861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 20:11:19.702269 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 20:11:19.708956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 20:11:19.712832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 20:11:19.719099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 20:11:19.726003 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 20:11:19.729373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 20:11:19.736065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 20:11:19.742558 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 20:11:19.746018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 20:11:19.752424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 20:11:19.755483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 20:11:19.762454 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 20:11:19.765826 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 20:11:19.772593 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 20:11:19.775887 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 20:11:19.782474 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 20:11:19.785247 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 20:11:19.792697 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 20:11:19.795862 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 20:11:19.803066 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 20:11:19.805250 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 20:11:19.808945 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 20:11:19.815452 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 20:11:19.819626 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 20:11:19.822457 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 20:11:19.826086 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 20:11:19.832243 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 20:11:19.836439 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 20:11:19.839287 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 20:11:19.846079 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 20:11:19.849787 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 20:11:19.852948 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 20:11:19.856514 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 20:11:19.866334 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 20:11:19.872568 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 20:11:19.879563 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 20:11:19.886078 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 20:11:19.895850 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 20:11:19.899077 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 20:11:19.902078 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 20:11:19.909471 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 20:11:19.915814 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x5
467 20:11:19.919122 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 20:11:19.926644 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 20:11:19.930288 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 20:11:19.939559 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 20:11:19.948857 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 20:11:19.958171 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 20:11:19.968378 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 20:11:19.978001 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 20:11:19.986697 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 20:11:19.995947 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 20:11:19.999871 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 20:11:20.006859 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 20:11:20.010786 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 20:11:20.013402 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 20:11:20.020123 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 20:11:20.023165 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 20:11:20.026478 ADC[4]: Raw value=669695 ID=5
484 20:11:20.027037 ADC[3]: Raw value=212917 ID=1
485 20:11:20.030386 RAM Code: 0x51
486 20:11:20.032871 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 20:11:20.039418 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 20:11:20.046638 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 20:11:20.053355 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 20:11:20.056887 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 20:11:20.059978 in-header: 03 07 00 00 08 00 00 00
492 20:11:20.063265 in-data: aa e4 47 04 13 02 00 00
493 20:11:20.066719 Chrome EC: UHEPI supported
494 20:11:20.073175 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 20:11:20.076440 in-header: 03 d5 00 00 08 00 00 00
496 20:11:20.079415 in-data: 98 20 60 08 00 00 00 00
497 20:11:20.083567 MRC: failed to locate region type 0.
498 20:11:20.089931 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 20:11:20.090464 DRAM-K: Running full calibration
500 20:11:20.096534 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 20:11:20.099636 header.status = 0x0
502 20:11:20.102752 header.version = 0x6 (expected: 0x6)
503 20:11:20.106759 header.size = 0xd00 (expected: 0xd00)
504 20:11:20.107379 header.flags = 0x0
505 20:11:20.113179 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 20:11:20.131193 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 20:11:20.138112 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 20:11:20.141162 dram_init: ddr_geometry: 0
509 20:11:20.144117 [EMI] MDL number = 0
510 20:11:20.144625 [EMI] Get MDL freq = 0
511 20:11:20.148178 dram_init: ddr_type: 0
512 20:11:20.148774 is_discrete_lpddr4: 1
513 20:11:20.150916 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 20:11:20.151375
515 20:11:20.151736
516 20:11:20.154964 [Bian_co] ETT version 0.0.0.1
517 20:11:20.158359 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 20:11:20.161257
519 20:11:20.165131 dramc_set_vcore_voltage set vcore to 650000
520 20:11:20.165697 Read voltage for 800, 4
521 20:11:20.168448 Vio18 = 0
522 20:11:20.169050 Vcore = 650000
523 20:11:20.169422 Vdram = 0
524 20:11:20.171619 Vddq = 0
525 20:11:20.172162 Vmddr = 0
526 20:11:20.175304 dram_init: config_dvfs: 1
527 20:11:20.178534 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 20:11:20.185396 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 20:11:20.188233 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 20:11:20.191708 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 20:11:20.195133 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 20:11:20.198631 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 20:11:20.201563 MEM_TYPE=3, freq_sel=18
534 20:11:20.204849 sv_algorithm_assistance_LP4_1600
535 20:11:20.208406 ============ PULL DRAM RESETB DOWN ============
536 20:11:20.211634 ========== PULL DRAM RESETB DOWN end =========
537 20:11:20.218528 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 20:11:20.221420 ===================================
539 20:11:20.221878 LPDDR4 DRAM CONFIGURATION
540 20:11:20.224825 ===================================
541 20:11:20.229022 EX_ROW_EN[0] = 0x0
542 20:11:20.231617 EX_ROW_EN[1] = 0x0
543 20:11:20.232205 LP4Y_EN = 0x0
544 20:11:20.234801 WORK_FSP = 0x0
545 20:11:20.235370 WL = 0x2
546 20:11:20.238594 RL = 0x2
547 20:11:20.239177 BL = 0x2
548 20:11:20.241461 RPST = 0x0
549 20:11:20.241928 RD_PRE = 0x0
550 20:11:20.245303 WR_PRE = 0x1
551 20:11:20.245872 WR_PST = 0x0
552 20:11:20.248402 DBI_WR = 0x0
553 20:11:20.249033 DBI_RD = 0x0
554 20:11:20.251543 OTF = 0x1
555 20:11:20.255628 ===================================
556 20:11:20.258572 ===================================
557 20:11:20.259158 ANA top config
558 20:11:20.261636 ===================================
559 20:11:20.264916 DLL_ASYNC_EN = 0
560 20:11:20.268351 ALL_SLAVE_EN = 1
561 20:11:20.268969 NEW_RANK_MODE = 1
562 20:11:20.271579 DLL_IDLE_MODE = 1
563 20:11:20.274618 LP45_APHY_COMB_EN = 1
564 20:11:20.278445 TX_ODT_DIS = 1
565 20:11:20.282618 NEW_8X_MODE = 1
566 20:11:20.283201 ===================================
567 20:11:20.284679 ===================================
568 20:11:20.287940 data_rate = 1600
569 20:11:20.291276 CKR = 1
570 20:11:20.294993 DQ_P2S_RATIO = 8
571 20:11:20.298236 ===================================
572 20:11:20.301303 CA_P2S_RATIO = 8
573 20:11:20.304367 DQ_CA_OPEN = 0
574 20:11:20.308557 DQ_SEMI_OPEN = 0
575 20:11:20.309098 CA_SEMI_OPEN = 0
576 20:11:20.311059 CA_FULL_RATE = 0
577 20:11:20.314725 DQ_CKDIV4_EN = 1
578 20:11:20.318173 CA_CKDIV4_EN = 1
579 20:11:20.321674 CA_PREDIV_EN = 0
580 20:11:20.325340 PH8_DLY = 0
581 20:11:20.325808 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 20:11:20.328574 DQ_AAMCK_DIV = 4
583 20:11:20.331256 CA_AAMCK_DIV = 4
584 20:11:20.334366 CA_ADMCK_DIV = 4
585 20:11:20.337913 DQ_TRACK_CA_EN = 0
586 20:11:20.341127 CA_PICK = 800
587 20:11:20.341596 CA_MCKIO = 800
588 20:11:20.344761 MCKIO_SEMI = 0
589 20:11:20.347908 PLL_FREQ = 3068
590 20:11:20.350862 DQ_UI_PI_RATIO = 32
591 20:11:20.354814 CA_UI_PI_RATIO = 0
592 20:11:20.357592 ===================================
593 20:11:20.360993 ===================================
594 20:11:20.364565 memory_type:LPDDR4
595 20:11:20.364893 GP_NUM : 10
596 20:11:20.368350 SRAM_EN : 1
597 20:11:20.368673 MD32_EN : 0
598 20:11:20.371536 ===================================
599 20:11:20.374125 [ANA_INIT] >>>>>>>>>>>>>>
600 20:11:20.377834 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 20:11:20.381182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 20:11:20.384630 ===================================
603 20:11:20.388270 data_rate = 1600,PCW = 0X7600
604 20:11:20.391881 ===================================
605 20:11:20.394448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 20:11:20.397742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 20:11:20.404926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 20:11:20.408314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 20:11:20.411320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 20:11:20.414824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 20:11:20.418500 [ANA_INIT] flow start
612 20:11:20.421586 [ANA_INIT] PLL >>>>>>>>
613 20:11:20.422148 [ANA_INIT] PLL <<<<<<<<
614 20:11:20.424366 [ANA_INIT] MIDPI >>>>>>>>
615 20:11:20.428039 [ANA_INIT] MIDPI <<<<<<<<
616 20:11:20.431338 [ANA_INIT] DLL >>>>>>>>
617 20:11:20.431905 [ANA_INIT] flow end
618 20:11:20.434769 ============ LP4 DIFF to SE enter ============
619 20:11:20.442108 ============ LP4 DIFF to SE exit ============
620 20:11:20.442675 [ANA_INIT] <<<<<<<<<<<<<
621 20:11:20.444814 [Flow] Enable top DCM control >>>>>
622 20:11:20.448216 [Flow] Enable top DCM control <<<<<
623 20:11:20.451613 Enable DLL master slave shuffle
624 20:11:20.457785 ==============================================================
625 20:11:20.458361 Gating Mode config
626 20:11:20.464610 ==============================================================
627 20:11:20.468217 Config description:
628 20:11:20.477928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 20:11:20.485515 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 20:11:20.488082 SELPH_MODE 0: By rank 1: By Phase
631 20:11:20.494926 ==============================================================
632 20:11:20.495531 GAT_TRACK_EN = 1
633 20:11:20.497786 RX_GATING_MODE = 2
634 20:11:20.501262 RX_GATING_TRACK_MODE = 2
635 20:11:20.504895 SELPH_MODE = 1
636 20:11:20.507956 PICG_EARLY_EN = 1
637 20:11:20.511721 VALID_LAT_VALUE = 1
638 20:11:20.518123 ==============================================================
639 20:11:20.521030 Enter into Gating configuration >>>>
640 20:11:20.524897 Exit from Gating configuration <<<<
641 20:11:20.527757 Enter into DVFS_PRE_config >>>>>
642 20:11:20.538058 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 20:11:20.541431 Exit from DVFS_PRE_config <<<<<
644 20:11:20.545146 Enter into PICG configuration >>>>
645 20:11:20.547764 Exit from PICG configuration <<<<
646 20:11:20.551398 [RX_INPUT] configuration >>>>>
647 20:11:20.551990 [RX_INPUT] configuration <<<<<
648 20:11:20.557820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 20:11:20.564119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 20:11:20.568061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 20:11:20.574615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 20:11:20.581390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 20:11:20.587687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 20:11:20.590996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 20:11:20.594146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 20:11:20.601295 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 20:11:20.604687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 20:11:20.608075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 20:11:20.614124 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 20:11:20.618006 ===================================
661 20:11:20.618475 LPDDR4 DRAM CONFIGURATION
662 20:11:20.620804 ===================================
663 20:11:20.623961 EX_ROW_EN[0] = 0x0
664 20:11:20.624429 EX_ROW_EN[1] = 0x0
665 20:11:20.628155 LP4Y_EN = 0x0
666 20:11:20.628620 WORK_FSP = 0x0
667 20:11:20.631215 WL = 0x2
668 20:11:20.634181 RL = 0x2
669 20:11:20.634607 BL = 0x2
670 20:11:20.637962 RPST = 0x0
671 20:11:20.638482 RD_PRE = 0x0
672 20:11:20.640926 WR_PRE = 0x1
673 20:11:20.641353 WR_PST = 0x0
674 20:11:20.644874 DBI_WR = 0x0
675 20:11:20.645390 DBI_RD = 0x0
676 20:11:20.647705 OTF = 0x1
677 20:11:20.651005 ===================================
678 20:11:20.654575 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 20:11:20.657662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 20:11:20.661005 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 20:11:20.664550 ===================================
682 20:11:20.667931 LPDDR4 DRAM CONFIGURATION
683 20:11:20.671390 ===================================
684 20:11:20.674396 EX_ROW_EN[0] = 0x10
685 20:11:20.674821 EX_ROW_EN[1] = 0x0
686 20:11:20.677930 LP4Y_EN = 0x0
687 20:11:20.678469 WORK_FSP = 0x0
688 20:11:20.681226 WL = 0x2
689 20:11:20.681650 RL = 0x2
690 20:11:20.684298 BL = 0x2
691 20:11:20.684756 RPST = 0x0
692 20:11:20.687698 RD_PRE = 0x0
693 20:11:20.688322 WR_PRE = 0x1
694 20:11:20.690960 WR_PST = 0x0
695 20:11:20.691481 DBI_WR = 0x0
696 20:11:20.694170 DBI_RD = 0x0
697 20:11:20.697488 OTF = 0x1
698 20:11:20.700995 ===================================
699 20:11:20.704360 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 20:11:20.709220 nWR fixed to 40
701 20:11:20.712641 [ModeRegInit_LP4] CH0 RK0
702 20:11:20.713172 [ModeRegInit_LP4] CH0 RK1
703 20:11:20.715711 [ModeRegInit_LP4] CH1 RK0
704 20:11:20.719752 [ModeRegInit_LP4] CH1 RK1
705 20:11:20.720176 match AC timing 12
706 20:11:20.725809 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 20:11:20.729210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 20:11:20.732382 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 20:11:20.739343 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 20:11:20.742687 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 20:11:20.743129 [EMI DOE] emi_dcm 0
712 20:11:20.749472 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 20:11:20.749974 ==
714 20:11:20.752810 Dram Type= 6, Freq= 0, CH_0, rank 0
715 20:11:20.755965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 20:11:20.756483 ==
717 20:11:20.762557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 20:11:20.769526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 20:11:20.777664 [CA 0] Center 37 (7~68) winsize 62
720 20:11:20.779914 [CA 1] Center 37 (7~68) winsize 62
721 20:11:20.783184 [CA 2] Center 35 (5~66) winsize 62
722 20:11:20.786516 [CA 3] Center 35 (4~66) winsize 63
723 20:11:20.790295 [CA 4] Center 34 (4~65) winsize 62
724 20:11:20.793307 [CA 5] Center 34 (4~65) winsize 62
725 20:11:20.793773
726 20:11:20.797189 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 20:11:20.797759
728 20:11:20.799907 [CATrainingPosCal] consider 1 rank data
729 20:11:20.803046 u2DelayCellTimex100 = 270/100 ps
730 20:11:20.807088 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 20:11:20.809729 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 20:11:20.816777 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 20:11:20.819851 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 20:11:20.823732 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 20:11:20.826782 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
736 20:11:20.827346
737 20:11:20.830433 CA PerBit enable=1, Macro0, CA PI delay=34
738 20:11:20.831003
739 20:11:20.833434 [CBTSetCACLKResult] CA Dly = 34
740 20:11:20.833901 CS Dly: 5 (0~36)
741 20:11:20.834428 ==
742 20:11:20.837653 Dram Type= 6, Freq= 0, CH_0, rank 1
743 20:11:20.843955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 20:11:20.844520 ==
745 20:11:20.846563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 20:11:20.854055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 20:11:20.862211 [CA 0] Center 37 (7~68) winsize 62
748 20:11:20.866768 [CA 1] Center 37 (6~68) winsize 63
749 20:11:20.869244 [CA 2] Center 35 (4~66) winsize 63
750 20:11:20.872372 [CA 3] Center 34 (4~65) winsize 62
751 20:11:20.875471 [CA 4] Center 33 (3~64) winsize 62
752 20:11:20.879258 [CA 5] Center 33 (3~64) winsize 62
753 20:11:20.879756
754 20:11:20.882363 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 20:11:20.882930
756 20:11:20.885838 [CATrainingPosCal] consider 2 rank data
757 20:11:20.888947 u2DelayCellTimex100 = 270/100 ps
758 20:11:20.892794 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 20:11:20.895652 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 20:11:20.902132 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 20:11:20.906846 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 20:11:20.908910 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 20:11:20.912222 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 20:11:20.912689
765 20:11:20.915265 CA PerBit enable=1, Macro0, CA PI delay=34
766 20:11:20.915747
767 20:11:20.919338 [CBTSetCACLKResult] CA Dly = 34
768 20:11:20.919844 CS Dly: 6 (0~38)
769 20:11:20.920212
770 20:11:20.923111 ----->DramcWriteLeveling(PI) begin...
771 20:11:20.925170 ==
772 20:11:20.928562 Dram Type= 6, Freq= 0, CH_0, rank 0
773 20:11:20.931957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 20:11:20.932532 ==
775 20:11:20.935581 Write leveling (Byte 0): 30 => 30
776 20:11:20.938679 Write leveling (Byte 1): 25 => 25
777 20:11:20.942732 DramcWriteLeveling(PI) end<-----
778 20:11:20.943323
779 20:11:20.943822 ==
780 20:11:20.945550 Dram Type= 6, Freq= 0, CH_0, rank 0
781 20:11:20.949328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 20:11:20.949884 ==
783 20:11:20.952122 [Gating] SW mode calibration
784 20:11:20.958840 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 20:11:20.965670 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 20:11:20.968750 0 6 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
787 20:11:20.972504 0 6 4 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
788 20:11:20.979515 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 20:11:20.983092 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 20:11:20.985272 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 20:11:20.988755 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 20:11:20.996044 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 20:11:20.999090 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 20:11:21.002949 0 7 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
795 20:11:21.008316 0 7 4 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
796 20:11:21.012308 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 20:11:21.015415 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 20:11:21.022603 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 20:11:21.025346 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 20:11:21.029184 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 20:11:21.035474 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 20:11:21.039377 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
803 20:11:21.042768 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 20:11:21.049133 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 20:11:21.052925 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 20:11:21.055557 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 20:11:21.062101 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 20:11:21.065295 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 20:11:21.069567 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 20:11:21.072529 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 20:11:21.079516 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 20:11:21.082274 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 20:11:21.085405 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 20:11:21.093309 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 20:11:21.096368 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 20:11:21.099233 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 20:11:21.106007 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
818 20:11:21.108833 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
819 20:11:21.112439 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 20:11:21.116009 Total UI for P1: 0, mck2ui 16
821 20:11:21.119251 best dqsien dly found for B0: ( 0, 10, 2)
822 20:11:21.122426 Total UI for P1: 0, mck2ui 16
823 20:11:21.125891 best dqsien dly found for B1: ( 0, 10, 0)
824 20:11:21.128877 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 20:11:21.132871 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 20:11:21.133433
827 20:11:21.138647 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 20:11:21.143057 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 20:11:21.143615 [Gating] SW calibration Done
830 20:11:21.145132 ==
831 20:11:21.145601 Dram Type= 6, Freq= 0, CH_0, rank 0
832 20:11:21.152641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 20:11:21.153246 ==
834 20:11:21.153624 RX Vref Scan: 0
835 20:11:21.153973
836 20:11:21.156004 RX Vref 0 -> 0, step: 1
837 20:11:21.156562
838 20:11:21.159261 RX Delay -130 -> 252, step: 16
839 20:11:21.163227 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 20:11:21.166204 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 20:11:21.169399 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 20:11:21.172424 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 20:11:21.179039 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 20:11:21.182995 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 20:11:21.186528 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 20:11:21.189871 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 20:11:21.193538 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
848 20:11:21.199229 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 20:11:21.202388 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 20:11:21.206191 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 20:11:21.209266 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 20:11:21.212438 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 20:11:21.219466 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 20:11:21.223267 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 20:11:21.223866 ==
856 20:11:21.226299 Dram Type= 6, Freq= 0, CH_0, rank 0
857 20:11:21.229244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 20:11:21.229719 ==
859 20:11:21.232917 DQS Delay:
860 20:11:21.233549 DQS0 = 0, DQS1 = 0
861 20:11:21.233928 DQM Delay:
862 20:11:21.236409 DQM0 = 82, DQM1 = 73
863 20:11:21.237078 DQ Delay:
864 20:11:21.239676 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 20:11:21.242777 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 20:11:21.245999 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
867 20:11:21.249484 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 20:11:21.249955
869 20:11:21.250325
870 20:11:21.250669 ==
871 20:11:21.252474 Dram Type= 6, Freq= 0, CH_0, rank 0
872 20:11:21.258973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 20:11:21.259449 ==
874 20:11:21.259819
875 20:11:21.260160
876 20:11:21.260487 TX Vref Scan disable
877 20:11:21.262734 == TX Byte 0 ==
878 20:11:21.266247 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
879 20:11:21.269592 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
880 20:11:21.273365 == TX Byte 1 ==
881 20:11:21.276045 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
882 20:11:21.279532 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
883 20:11:21.282731 ==
884 20:11:21.286717 Dram Type= 6, Freq= 0, CH_0, rank 0
885 20:11:21.289551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 20:11:21.290123 ==
887 20:11:21.302968 TX Vref=22, minBit 0, minWin=27, winSum=440
888 20:11:21.305745 TX Vref=24, minBit 4, minWin=27, winSum=445
889 20:11:21.309345 TX Vref=26, minBit 11, minWin=27, winSum=450
890 20:11:21.312548 TX Vref=28, minBit 4, minWin=27, winSum=451
891 20:11:21.315384 TX Vref=30, minBit 0, minWin=28, winSum=456
892 20:11:21.322107 TX Vref=32, minBit 11, minWin=27, winSum=448
893 20:11:21.325628 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
894 20:11:21.326093
895 20:11:21.329001 Final TX Range 1 Vref 30
896 20:11:21.329526
897 20:11:21.329891 ==
898 20:11:21.332175 Dram Type= 6, Freq= 0, CH_0, rank 0
899 20:11:21.335416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 20:11:21.336048 ==
901 20:11:21.338587
902 20:11:21.339151
903 20:11:21.339533 TX Vref Scan disable
904 20:11:21.342577 == TX Byte 0 ==
905 20:11:21.345808 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
906 20:11:21.352315 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
907 20:11:21.352938 == TX Byte 1 ==
908 20:11:21.355802 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
909 20:11:21.362647 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
910 20:11:21.363183
911 20:11:21.363551 [DATLAT]
912 20:11:21.363889 Freq=800, CH0 RK0
913 20:11:21.364218
914 20:11:21.366125 DATLAT Default: 0xa
915 20:11:21.366587 0, 0xFFFF, sum = 0
916 20:11:21.368947 1, 0xFFFF, sum = 0
917 20:11:21.369547 2, 0xFFFF, sum = 0
918 20:11:21.372233 3, 0xFFFF, sum = 0
919 20:11:21.372843 4, 0xFFFF, sum = 0
920 20:11:21.375975 5, 0xFFFF, sum = 0
921 20:11:21.379245 6, 0xFFFF, sum = 0
922 20:11:21.379816 7, 0xFFFF, sum = 0
923 20:11:21.380188 8, 0x0, sum = 1
924 20:11:21.382384 9, 0x0, sum = 2
925 20:11:21.382953 10, 0x0, sum = 3
926 20:11:21.385689 11, 0x0, sum = 4
927 20:11:21.386160 best_step = 9
928 20:11:21.386526
929 20:11:21.386863 ==
930 20:11:21.389031 Dram Type= 6, Freq= 0, CH_0, rank 0
931 20:11:21.395849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 20:11:21.396416 ==
933 20:11:21.396843 RX Vref Scan: 1
934 20:11:21.397199
935 20:11:21.399114 Set Vref Range= 32 -> 127
936 20:11:21.399672
937 20:11:21.402493 RX Vref 32 -> 127, step: 1
938 20:11:21.403048
939 20:11:21.405610 RX Delay -111 -> 252, step: 8
940 20:11:21.406148
941 20:11:21.409420 Set Vref, RX VrefLevel [Byte0]: 32
942 20:11:21.410069 [Byte1]: 32
943 20:11:21.413575
944 20:11:21.414283 Set Vref, RX VrefLevel [Byte0]: 33
945 20:11:21.417185 [Byte1]: 33
946 20:11:21.421067
947 20:11:21.421533 Set Vref, RX VrefLevel [Byte0]: 34
948 20:11:21.424477 [Byte1]: 34
949 20:11:21.428923
950 20:11:21.429390 Set Vref, RX VrefLevel [Byte0]: 35
951 20:11:21.432397 [Byte1]: 35
952 20:11:21.436459
953 20:11:21.437119 Set Vref, RX VrefLevel [Byte0]: 36
954 20:11:21.439806 [Byte1]: 36
955 20:11:21.443822
956 20:11:21.444570 Set Vref, RX VrefLevel [Byte0]: 37
957 20:11:21.447575 [Byte1]: 37
958 20:11:21.451554
959 20:11:21.452016 Set Vref, RX VrefLevel [Byte0]: 38
960 20:11:21.454801 [Byte1]: 38
961 20:11:21.459219
962 20:11:21.459711 Set Vref, RX VrefLevel [Byte0]: 39
963 20:11:21.462357 [Byte1]: 39
964 20:11:21.466515
965 20:11:21.466976 Set Vref, RX VrefLevel [Byte0]: 40
966 20:11:21.469746 [Byte1]: 40
967 20:11:21.474564
968 20:11:21.475029 Set Vref, RX VrefLevel [Byte0]: 41
969 20:11:21.477959 [Byte1]: 41
970 20:11:21.482371
971 20:11:21.482947 Set Vref, RX VrefLevel [Byte0]: 42
972 20:11:21.485523 [Byte1]: 42
973 20:11:21.490000
974 20:11:21.490461 Set Vref, RX VrefLevel [Byte0]: 43
975 20:11:21.493246 [Byte1]: 43
976 20:11:21.497346
977 20:11:21.497830 Set Vref, RX VrefLevel [Byte0]: 44
978 20:11:21.501228 [Byte1]: 44
979 20:11:21.504970
980 20:11:21.505431 Set Vref, RX VrefLevel [Byte0]: 45
981 20:11:21.508171 [Byte1]: 45
982 20:11:21.513571
983 20:11:21.514143 Set Vref, RX VrefLevel [Byte0]: 46
984 20:11:21.516056 [Byte1]: 46
985 20:11:21.520123
986 20:11:21.520772 Set Vref, RX VrefLevel [Byte0]: 47
987 20:11:21.523672 [Byte1]: 47
988 20:11:21.528451
989 20:11:21.529041 Set Vref, RX VrefLevel [Byte0]: 48
990 20:11:21.531356 [Byte1]: 48
991 20:11:21.536035
992 20:11:21.536607 Set Vref, RX VrefLevel [Byte0]: 49
993 20:11:21.539284 [Byte1]: 49
994 20:11:21.543513
995 20:11:21.544077 Set Vref, RX VrefLevel [Byte0]: 50
996 20:11:21.546741 [Byte1]: 50
997 20:11:21.550686
998 20:11:21.551155 Set Vref, RX VrefLevel [Byte0]: 51
999 20:11:21.554504 [Byte1]: 51
1000 20:11:21.558460
1001 20:11:21.559047 Set Vref, RX VrefLevel [Byte0]: 52
1002 20:11:21.561621 [Byte1]: 52
1003 20:11:21.566117
1004 20:11:21.566581 Set Vref, RX VrefLevel [Byte0]: 53
1005 20:11:21.569391 [Byte1]: 53
1006 20:11:21.574068
1007 20:11:21.574620 Set Vref, RX VrefLevel [Byte0]: 54
1008 20:11:21.576989 [Byte1]: 54
1009 20:11:21.581416
1010 20:11:21.581955 Set Vref, RX VrefLevel [Byte0]: 55
1011 20:11:21.584759 [Byte1]: 55
1012 20:11:21.589483
1013 20:11:21.590021 Set Vref, RX VrefLevel [Byte0]: 56
1014 20:11:21.592310 [Byte1]: 56
1015 20:11:21.597351
1016 20:11:21.597920 Set Vref, RX VrefLevel [Byte0]: 57
1017 20:11:21.600057 [Byte1]: 57
1018 20:11:21.605133
1019 20:11:21.605590 Set Vref, RX VrefLevel [Byte0]: 58
1020 20:11:21.607595 [Byte1]: 58
1021 20:11:21.612512
1022 20:11:21.613117 Set Vref, RX VrefLevel [Byte0]: 59
1023 20:11:21.615632 [Byte1]: 59
1024 20:11:21.619847
1025 20:11:21.620363 Set Vref, RX VrefLevel [Byte0]: 60
1026 20:11:21.623128 [Byte1]: 60
1027 20:11:21.628302
1028 20:11:21.628886 Set Vref, RX VrefLevel [Byte0]: 61
1029 20:11:21.631681 [Byte1]: 61
1030 20:11:21.635591
1031 20:11:21.636155 Set Vref, RX VrefLevel [Byte0]: 62
1032 20:11:21.638450 [Byte1]: 62
1033 20:11:21.643070
1034 20:11:21.643622 Set Vref, RX VrefLevel [Byte0]: 63
1035 20:11:21.646567 [Byte1]: 63
1036 20:11:21.650865
1037 20:11:21.651457 Set Vref, RX VrefLevel [Byte0]: 64
1038 20:11:21.653404 [Byte1]: 64
1039 20:11:21.658364
1040 20:11:21.658818 Set Vref, RX VrefLevel [Byte0]: 65
1041 20:11:21.661730 [Byte1]: 65
1042 20:11:21.665663
1043 20:11:21.666207 Set Vref, RX VrefLevel [Byte0]: 66
1044 20:11:21.668869 [Byte1]: 66
1045 20:11:21.673477
1046 20:11:21.673990 Set Vref, RX VrefLevel [Byte0]: 67
1047 20:11:21.677326 [Byte1]: 67
1048 20:11:21.681622
1049 20:11:21.682164 Set Vref, RX VrefLevel [Byte0]: 68
1050 20:11:21.684998 [Byte1]: 68
1051 20:11:21.688425
1052 20:11:21.689041 Set Vref, RX VrefLevel [Byte0]: 69
1053 20:11:21.692171 [Byte1]: 69
1054 20:11:21.696100
1055 20:11:21.696576 Set Vref, RX VrefLevel [Byte0]: 70
1056 20:11:21.699779 [Byte1]: 70
1057 20:11:21.704093
1058 20:11:21.704639 Set Vref, RX VrefLevel [Byte0]: 71
1059 20:11:21.706973 [Byte1]: 71
1060 20:11:21.711714
1061 20:11:21.712274 Set Vref, RX VrefLevel [Byte0]: 72
1062 20:11:21.714550 [Byte1]: 72
1063 20:11:21.719498
1064 20:11:21.719952 Set Vref, RX VrefLevel [Byte0]: 73
1065 20:11:21.722235 [Byte1]: 73
1066 20:11:21.726792
1067 20:11:21.727348 Set Vref, RX VrefLevel [Byte0]: 74
1068 20:11:21.730589 [Byte1]: 74
1069 20:11:21.734449
1070 20:11:21.735000 Final RX Vref Byte 0 = 52 to rank0
1071 20:11:21.737765 Final RX Vref Byte 1 = 56 to rank0
1072 20:11:21.741364 Final RX Vref Byte 0 = 52 to rank1
1073 20:11:21.744845 Final RX Vref Byte 1 = 56 to rank1==
1074 20:11:21.748387 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 20:11:21.754851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 20:11:21.755408 ==
1077 20:11:21.755777 DQS Delay:
1078 20:11:21.756112 DQS0 = 0, DQS1 = 0
1079 20:11:21.758110 DQM Delay:
1080 20:11:21.758671 DQM0 = 83, DQM1 = 73
1081 20:11:21.761930 DQ Delay:
1082 20:11:21.764675 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 20:11:21.765281 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 20:11:21.768436 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1085 20:11:21.774732 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1086 20:11:21.775292
1087 20:11:21.775662
1088 20:11:21.781269 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1089 20:11:21.784913 CH0 RK0: MR19=606, MR18=3838
1090 20:11:21.791395 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1091 20:11:21.791974
1092 20:11:21.794637 ----->DramcWriteLeveling(PI) begin...
1093 20:11:21.795199 ==
1094 20:11:21.797980 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 20:11:21.801490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 20:11:21.802048 ==
1097 20:11:21.805141 Write leveling (Byte 0): 29 => 29
1098 20:11:21.807952 Write leveling (Byte 1): 28 => 28
1099 20:11:21.810954 DramcWriteLeveling(PI) end<-----
1100 20:11:21.811492
1101 20:11:21.811852 ==
1102 20:11:21.814567 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 20:11:21.817836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 20:11:21.818295 ==
1105 20:11:21.820952 [Gating] SW mode calibration
1106 20:11:21.827536 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 20:11:21.834369 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 20:11:21.837564 0 6 0 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 1)
1109 20:11:21.841228 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1110 20:11:21.847858 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 20:11:21.851005 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 20:11:21.854558 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 20:11:21.861777 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 20:11:21.864352 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 20:11:21.867957 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 20:11:21.874391 0 7 0 | B1->B0 | 2b2b 3030 | 1 1 | (0 0) (0 0)
1117 20:11:21.877654 0 7 4 | B1->B0 | 4343 4141 | 1 0 | (0 0) (0 0)
1118 20:11:21.881216 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 20:11:21.888329 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 20:11:21.890998 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 20:11:21.894518 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 20:11:21.898050 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 20:11:21.904852 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 20:11:21.907753 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 20:11:21.910917 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1126 20:11:21.917708 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 20:11:21.921232 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 20:11:21.924761 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 20:11:21.931271 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 20:11:21.935065 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 20:11:21.937893 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 20:11:21.944494 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 20:11:21.947873 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 20:11:21.951174 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 20:11:21.957649 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 20:11:21.961268 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 20:11:21.964914 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 20:11:21.971244 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 20:11:21.974389 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1140 20:11:21.977807 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1141 20:11:21.984811 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1142 20:11:21.985370 Total UI for P1: 0, mck2ui 16
1143 20:11:21.988030 best dqsien dly found for B0: ( 0, 9, 30)
1144 20:11:21.991857 Total UI for P1: 0, mck2ui 16
1145 20:11:21.994942 best dqsien dly found for B1: ( 0, 10, 0)
1146 20:11:21.997523 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1147 20:11:22.004485 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1148 20:11:22.005075
1149 20:11:22.008191 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1150 20:11:22.011107 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1151 20:11:22.014193 [Gating] SW calibration Done
1152 20:11:22.014645 ==
1153 20:11:22.017635 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 20:11:22.021630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1155 20:11:22.022095 ==
1156 20:11:22.022460 RX Vref Scan: 0
1157 20:11:22.024840
1158 20:11:22.025292 RX Vref 0 -> 0, step: 1
1159 20:11:22.025653
1160 20:11:22.027750 RX Delay -130 -> 252, step: 16
1161 20:11:22.072298 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1162 20:11:22.073256 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1163 20:11:22.073664 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1164 20:11:22.074084 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1165 20:11:22.074431 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1166 20:11:22.074753 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1167 20:11:22.075064 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1168 20:11:22.075431 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1169 20:11:22.075748 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1170 20:11:22.076048 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1171 20:11:22.076407 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1172 20:11:22.097953 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1173 20:11:22.098505 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1174 20:11:22.098870 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1175 20:11:22.099208 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1176 20:11:22.099870 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1177 20:11:22.100215 ==
1178 20:11:22.100538 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 20:11:22.101880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 20:11:22.102333 ==
1181 20:11:22.102693 DQS Delay:
1182 20:11:22.104980 DQS0 = 0, DQS1 = 0
1183 20:11:22.105455 DQM Delay:
1184 20:11:22.105830 DQM0 = 86, DQM1 = 75
1185 20:11:22.108164 DQ Delay:
1186 20:11:22.108612 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1187 20:11:22.112556 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1188 20:11:22.114738 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1189 20:11:22.119236 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1190 20:11:22.119690
1191 20:11:22.120050
1192 20:11:22.121886 ==
1193 20:11:22.124794 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 20:11:22.128269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1195 20:11:22.128862 ==
1196 20:11:22.129231
1197 20:11:22.129570
1198 20:11:22.131913 TX Vref Scan disable
1199 20:11:22.132467 == TX Byte 0 ==
1200 20:11:22.138058 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1201 20:11:22.141888 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1202 20:11:22.142453 == TX Byte 1 ==
1203 20:11:22.148431 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1204 20:11:22.151409 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1205 20:11:22.151958 ==
1206 20:11:22.155006 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 20:11:22.158064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1208 20:11:22.158619 ==
1209 20:11:22.171508 TX Vref=22, minBit 0, minWin=27, winSum=447
1210 20:11:22.175169 TX Vref=24, minBit 14, minWin=27, winSum=451
1211 20:11:22.178758 TX Vref=26, minBit 0, minWin=28, winSum=456
1212 20:11:22.181450 TX Vref=28, minBit 2, minWin=28, winSum=456
1213 20:11:22.184884 TX Vref=30, minBit 0, minWin=28, winSum=458
1214 20:11:22.191490 TX Vref=32, minBit 2, minWin=28, winSum=458
1215 20:11:22.194506 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1216 20:11:22.194963
1217 20:11:22.198301 Final TX Range 1 Vref 30
1218 20:11:22.198862
1219 20:11:22.199231 ==
1220 20:11:22.201217 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 20:11:22.204730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 20:11:22.205188 ==
1223 20:11:22.207757
1224 20:11:22.208233
1225 20:11:22.208592 TX Vref Scan disable
1226 20:11:22.211112 == TX Byte 0 ==
1227 20:11:22.214682 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1228 20:11:22.218241 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1229 20:11:22.221788 == TX Byte 1 ==
1230 20:11:22.225187 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1231 20:11:22.227941 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1232 20:11:22.231626
1233 20:11:22.232322 [DATLAT]
1234 20:11:22.232764 Freq=800, CH0 RK1
1235 20:11:22.233128
1236 20:11:22.235217 DATLAT Default: 0x9
1237 20:11:22.235834 0, 0xFFFF, sum = 0
1238 20:11:22.237838 1, 0xFFFF, sum = 0
1239 20:11:22.238377 2, 0xFFFF, sum = 0
1240 20:11:22.242298 3, 0xFFFF, sum = 0
1241 20:11:22.242866 4, 0xFFFF, sum = 0
1242 20:11:22.244615 5, 0xFFFF, sum = 0
1243 20:11:22.245233 6, 0xFFFF, sum = 0
1244 20:11:22.248215 7, 0xFFFF, sum = 0
1245 20:11:22.248846 8, 0x0, sum = 1
1246 20:11:22.251558 9, 0x0, sum = 2
1247 20:11:22.252117 10, 0x0, sum = 3
1248 20:11:22.254990 11, 0x0, sum = 4
1249 20:11:22.255554 best_step = 9
1250 20:11:22.255918
1251 20:11:22.256258 ==
1252 20:11:22.259025 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 20:11:22.265360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1254 20:11:22.265916 ==
1255 20:11:22.266285 RX Vref Scan: 0
1256 20:11:22.266625
1257 20:11:22.268434 RX Vref 0 -> 0, step: 1
1258 20:11:22.269038
1259 20:11:22.271931 RX Delay -111 -> 252, step: 8
1260 20:11:22.275111 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1261 20:11:22.278865 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1262 20:11:22.285021 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1263 20:11:22.289785 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1264 20:11:22.291338 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1265 20:11:22.295621 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1266 20:11:22.297881 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1267 20:11:22.302013 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1268 20:11:22.308486 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1269 20:11:22.311453 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1270 20:11:22.315028 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1271 20:11:22.318634 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1272 20:11:22.321254 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1273 20:11:22.327700 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1274 20:11:22.331415 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1275 20:11:22.334816 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1276 20:11:22.335359 ==
1277 20:11:22.338002 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 20:11:22.341228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 20:11:22.345347 ==
1280 20:11:22.345900 DQS Delay:
1281 20:11:22.346264 DQS0 = 0, DQS1 = 0
1282 20:11:22.348158 DQM Delay:
1283 20:11:22.348678 DQM0 = 86, DQM1 = 75
1284 20:11:22.352089 DQ Delay:
1285 20:11:22.352754 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1286 20:11:22.354885 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1287 20:11:22.358708 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1288 20:11:22.361637 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1289 20:11:22.362187
1290 20:11:22.364879
1291 20:11:22.372254 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1292 20:11:22.374729 CH0 RK1: MR19=606, MR18=4141
1293 20:11:22.381806 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1294 20:11:22.382273 [RxdqsGatingPostProcess] freq 800
1295 20:11:22.388137 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1296 20:11:22.391859 Pre-setting of DQS Precalculation
1297 20:11:22.394813 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1298 20:11:22.395263 ==
1299 20:11:22.398222 Dram Type= 6, Freq= 0, CH_1, rank 0
1300 20:11:22.405243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1301 20:11:22.405656 ==
1302 20:11:22.409033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1303 20:11:22.414796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1304 20:11:22.424360 [CA 0] Center 37 (6~68) winsize 63
1305 20:11:22.428150 [CA 1] Center 37 (6~68) winsize 63
1306 20:11:22.430800 [CA 2] Center 34 (4~65) winsize 62
1307 20:11:22.434458 [CA 3] Center 34 (4~65) winsize 62
1308 20:11:22.437694 [CA 4] Center 33 (3~64) winsize 62
1309 20:11:22.440896 [CA 5] Center 33 (3~64) winsize 62
1310 20:11:22.441439
1311 20:11:22.444345 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1312 20:11:22.444845
1313 20:11:22.447658 [CATrainingPosCal] consider 1 rank data
1314 20:11:22.450666 u2DelayCellTimex100 = 270/100 ps
1315 20:11:22.454843 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1316 20:11:22.457670 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1317 20:11:22.464197 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 20:11:22.467708 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 20:11:22.471429 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1320 20:11:22.474737 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 20:11:22.475445
1322 20:11:22.477574 CA PerBit enable=1, Macro0, CA PI delay=33
1323 20:11:22.478153
1324 20:11:22.481187 [CBTSetCACLKResult] CA Dly = 33
1325 20:11:22.481731 CS Dly: 4 (0~35)
1326 20:11:22.484096 ==
1327 20:11:22.484637 Dram Type= 6, Freq= 0, CH_1, rank 1
1328 20:11:22.491044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1329 20:11:22.491622 ==
1330 20:11:22.494610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1331 20:11:22.500989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1332 20:11:22.510033 [CA 0] Center 37 (6~68) winsize 63
1333 20:11:22.513697 [CA 1] Center 37 (6~68) winsize 63
1334 20:11:22.516931 [CA 2] Center 34 (4~65) winsize 62
1335 20:11:22.520244 [CA 3] Center 34 (4~65) winsize 62
1336 20:11:22.523137 [CA 4] Center 33 (3~64) winsize 62
1337 20:11:22.527140 [CA 5] Center 33 (2~64) winsize 63
1338 20:11:22.527703
1339 20:11:22.530075 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1340 20:11:22.530501
1341 20:11:22.533581 [CATrainingPosCal] consider 2 rank data
1342 20:11:22.536629 u2DelayCellTimex100 = 270/100 ps
1343 20:11:22.539854 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1344 20:11:22.543130 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1345 20:11:22.550142 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1346 20:11:22.553249 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 20:11:22.556632 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1348 20:11:22.560101 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 20:11:22.560643
1350 20:11:22.563298 CA PerBit enable=1, Macro0, CA PI delay=33
1351 20:11:22.563808
1352 20:11:22.567025 [CBTSetCACLKResult] CA Dly = 33
1353 20:11:22.567572 CS Dly: 5 (0~37)
1354 20:11:22.567939
1355 20:11:22.569829 ----->DramcWriteLeveling(PI) begin...
1356 20:11:22.573070 ==
1357 20:11:22.576651 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 20:11:22.579524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 20:11:22.579985 ==
1360 20:11:22.582939 Write leveling (Byte 0): 27 => 27
1361 20:11:22.586871 Write leveling (Byte 1): 24 => 24
1362 20:11:22.590433 DramcWriteLeveling(PI) end<-----
1363 20:11:22.590991
1364 20:11:22.591364 ==
1365 20:11:22.593342 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 20:11:22.596664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 20:11:22.597267 ==
1368 20:11:22.599942 [Gating] SW mode calibration
1369 20:11:22.606878 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1370 20:11:22.613655 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1371 20:11:22.616580 0 6 0 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
1372 20:11:22.619474 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 20:11:22.623091 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 20:11:22.629873 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 20:11:22.632989 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 20:11:22.636535 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 20:11:22.643224 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 20:11:22.646608 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1379 20:11:22.649674 0 7 0 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
1380 20:11:22.656070 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1381 20:11:22.659125 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 20:11:22.663185 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 20:11:22.669504 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 20:11:22.673081 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 20:11:22.676547 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 20:11:22.682893 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1387 20:11:22.686345 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1388 20:11:22.689354 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 20:11:22.696113 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 20:11:22.699412 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 20:11:22.702700 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 20:11:22.709712 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 20:11:22.713418 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 20:11:22.715737 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 20:11:22.722729 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 20:11:22.725922 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 20:11:22.729956 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 20:11:22.732881 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 20:11:22.739346 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 20:11:22.743798 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 20:11:22.746084 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 20:11:22.753382 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1403 20:11:22.756193 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1404 20:11:22.760272 Total UI for P1: 0, mck2ui 16
1405 20:11:22.763659 best dqsien dly found for B0: ( 0, 9, 28)
1406 20:11:22.766173 Total UI for P1: 0, mck2ui 16
1407 20:11:22.769619 best dqsien dly found for B1: ( 0, 9, 30)
1408 20:11:22.772698 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1409 20:11:22.776253 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1410 20:11:22.776859
1411 20:11:22.779874 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1412 20:11:22.782867 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1413 20:11:22.786169 [Gating] SW calibration Done
1414 20:11:22.786725 ==
1415 20:11:22.789433 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 20:11:22.793311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1417 20:11:22.796674 ==
1418 20:11:22.797273 RX Vref Scan: 0
1419 20:11:22.797647
1420 20:11:22.799849 RX Vref 0 -> 0, step: 1
1421 20:11:22.800423
1422 20:11:22.803095 RX Delay -130 -> 252, step: 16
1423 20:11:22.806072 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1424 20:11:22.809555 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1425 20:11:22.813419 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1426 20:11:22.816671 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1427 20:11:22.823202 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1428 20:11:22.826535 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1429 20:11:22.829334 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1430 20:11:22.833364 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1431 20:11:22.836604 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1432 20:11:22.843060 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1433 20:11:22.846193 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1434 20:11:22.849529 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1435 20:11:22.852928 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1436 20:11:22.856372 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1437 20:11:22.863322 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1438 20:11:22.866297 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1439 20:11:22.866864 ==
1440 20:11:22.869358 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 20:11:22.873266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1442 20:11:22.873831 ==
1443 20:11:22.876415 DQS Delay:
1444 20:11:22.876907 DQS0 = 0, DQS1 = 0
1445 20:11:22.877277 DQM Delay:
1446 20:11:22.879756 DQM0 = 80, DQM1 = 75
1447 20:11:22.880321 DQ Delay:
1448 20:11:22.883640 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1449 20:11:22.885757 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1450 20:11:22.889674 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1451 20:11:22.893588 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1452 20:11:22.894201
1453 20:11:22.894578
1454 20:11:22.894972 ==
1455 20:11:22.896512 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 20:11:22.903054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1457 20:11:22.903612 ==
1458 20:11:22.903983
1459 20:11:22.904324
1460 20:11:22.904648 TX Vref Scan disable
1461 20:11:22.906435 == TX Byte 0 ==
1462 20:11:22.909719 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1463 20:11:22.916540 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1464 20:11:22.917337 == TX Byte 1 ==
1465 20:11:22.919508 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1466 20:11:22.926676 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1467 20:11:22.927246 ==
1468 20:11:22.930802 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 20:11:22.932541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1470 20:11:22.933043 ==
1471 20:11:22.945746 TX Vref=22, minBit 0, minWin=27, winSum=447
1472 20:11:22.948894 TX Vref=24, minBit 0, minWin=28, winSum=450
1473 20:11:22.952476 TX Vref=26, minBit 3, minWin=27, winSum=453
1474 20:11:22.955721 TX Vref=28, minBit 0, minWin=28, winSum=457
1475 20:11:22.958669 TX Vref=30, minBit 0, minWin=28, winSum=460
1476 20:11:22.965698 TX Vref=32, minBit 0, minWin=28, winSum=456
1477 20:11:22.968485 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1478 20:11:22.969119
1479 20:11:22.972114 Final TX Range 1 Vref 30
1480 20:11:22.972796
1481 20:11:22.973305 ==
1482 20:11:22.975230 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 20:11:22.979243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1484 20:11:22.979808 ==
1485 20:11:22.982032
1486 20:11:22.982587
1487 20:11:22.982957 TX Vref Scan disable
1488 20:11:22.985551 == TX Byte 0 ==
1489 20:11:22.988623 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1490 20:11:22.992340 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1491 20:11:22.995381 == TX Byte 1 ==
1492 20:11:22.998706 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1493 20:11:23.005537 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1494 20:11:23.006096
1495 20:11:23.006461 [DATLAT]
1496 20:11:23.006802 Freq=800, CH1 RK0
1497 20:11:23.007135
1498 20:11:23.009085 DATLAT Default: 0xa
1499 20:11:23.009659 0, 0xFFFF, sum = 0
1500 20:11:23.012423 1, 0xFFFF, sum = 0
1501 20:11:23.013041 2, 0xFFFF, sum = 0
1502 20:11:23.015611 3, 0xFFFF, sum = 0
1503 20:11:23.018566 4, 0xFFFF, sum = 0
1504 20:11:23.019051 5, 0xFFFF, sum = 0
1505 20:11:23.021900 6, 0xFFFF, sum = 0
1506 20:11:23.022426 7, 0xFFFF, sum = 0
1507 20:11:23.022806 8, 0x0, sum = 1
1508 20:11:23.025173 9, 0x0, sum = 2
1509 20:11:23.025668 10, 0x0, sum = 3
1510 20:11:23.029192 11, 0x0, sum = 4
1511 20:11:23.029763 best_step = 9
1512 20:11:23.030132
1513 20:11:23.030472 ==
1514 20:11:23.031872 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 20:11:23.038830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1516 20:11:23.039396 ==
1517 20:11:23.039771 RX Vref Scan: 1
1518 20:11:23.040117
1519 20:11:23.042445 Set Vref Range= 32 -> 127
1520 20:11:23.043004
1521 20:11:23.045365 RX Vref 32 -> 127, step: 1
1522 20:11:23.045826
1523 20:11:23.048933 RX Delay -111 -> 252, step: 8
1524 20:11:23.049494
1525 20:11:23.052282 Set Vref, RX VrefLevel [Byte0]: 32
1526 20:11:23.052903 [Byte1]: 32
1527 20:11:23.056748
1528 20:11:23.057328 Set Vref, RX VrefLevel [Byte0]: 33
1529 20:11:23.059784 [Byte1]: 33
1530 20:11:23.064100
1531 20:11:23.064663 Set Vref, RX VrefLevel [Byte0]: 34
1532 20:11:23.067871 [Byte1]: 34
1533 20:11:23.072342
1534 20:11:23.072920 Set Vref, RX VrefLevel [Byte0]: 35
1535 20:11:23.074805 [Byte1]: 35
1536 20:11:23.079240
1537 20:11:23.079779 Set Vref, RX VrefLevel [Byte0]: 36
1538 20:11:23.082458 [Byte1]: 36
1539 20:11:23.087068
1540 20:11:23.087632 Set Vref, RX VrefLevel [Byte0]: 37
1541 20:11:23.090810 [Byte1]: 37
1542 20:11:23.094650
1543 20:11:23.095110 Set Vref, RX VrefLevel [Byte0]: 38
1544 20:11:23.097717 [Byte1]: 38
1545 20:11:23.102229
1546 20:11:23.102813 Set Vref, RX VrefLevel [Byte0]: 39
1547 20:11:23.105642 [Byte1]: 39
1548 20:11:23.110170
1549 20:11:23.110730 Set Vref, RX VrefLevel [Byte0]: 40
1550 20:11:23.113464 [Byte1]: 40
1551 20:11:23.117392
1552 20:11:23.117885 Set Vref, RX VrefLevel [Byte0]: 41
1553 20:11:23.120384 [Byte1]: 41
1554 20:11:23.125002
1555 20:11:23.125544 Set Vref, RX VrefLevel [Byte0]: 42
1556 20:11:23.128808 [Byte1]: 42
1557 20:11:23.133422
1558 20:11:23.134011 Set Vref, RX VrefLevel [Byte0]: 43
1559 20:11:23.136110 [Byte1]: 43
1560 20:11:23.140858
1561 20:11:23.141406 Set Vref, RX VrefLevel [Byte0]: 44
1562 20:11:23.143879 [Byte1]: 44
1563 20:11:23.148648
1564 20:11:23.149264 Set Vref, RX VrefLevel [Byte0]: 45
1565 20:11:23.151379 [Byte1]: 45
1566 20:11:23.155664
1567 20:11:23.156214 Set Vref, RX VrefLevel [Byte0]: 46
1568 20:11:23.159405 [Byte1]: 46
1569 20:11:23.163434
1570 20:11:23.164092 Set Vref, RX VrefLevel [Byte0]: 47
1571 20:11:23.166450 [Byte1]: 47
1572 20:11:23.171667
1573 20:11:23.172231 Set Vref, RX VrefLevel [Byte0]: 48
1574 20:11:23.174100 [Byte1]: 48
1575 20:11:23.180349
1576 20:11:23.180942 Set Vref, RX VrefLevel [Byte0]: 49
1577 20:11:23.181675 [Byte1]: 49
1578 20:11:23.185978
1579 20:11:23.189782 Set Vref, RX VrefLevel [Byte0]: 50
1580 20:11:23.190340 [Byte1]: 50
1581 20:11:23.193969
1582 20:11:23.194527 Set Vref, RX VrefLevel [Byte0]: 51
1583 20:11:23.197619 [Byte1]: 51
1584 20:11:23.201772
1585 20:11:23.202328 Set Vref, RX VrefLevel [Byte0]: 52
1586 20:11:23.205166 [Byte1]: 52
1587 20:11:23.209011
1588 20:11:23.209558 Set Vref, RX VrefLevel [Byte0]: 53
1589 20:11:23.212775 [Byte1]: 53
1590 20:11:23.216915
1591 20:11:23.217544 Set Vref, RX VrefLevel [Byte0]: 54
1592 20:11:23.219841 [Byte1]: 54
1593 20:11:23.224435
1594 20:11:23.225058 Set Vref, RX VrefLevel [Byte0]: 55
1595 20:11:23.227466 [Byte1]: 55
1596 20:11:23.232323
1597 20:11:23.232813 Set Vref, RX VrefLevel [Byte0]: 56
1598 20:11:23.235586 [Byte1]: 56
1599 20:11:23.239834
1600 20:11:23.240287 Set Vref, RX VrefLevel [Byte0]: 57
1601 20:11:23.243733 [Byte1]: 57
1602 20:11:23.247379
1603 20:11:23.247937 Set Vref, RX VrefLevel [Byte0]: 58
1604 20:11:23.251025 [Byte1]: 58
1605 20:11:23.255738
1606 20:11:23.256321 Set Vref, RX VrefLevel [Byte0]: 59
1607 20:11:23.258988 [Byte1]: 59
1608 20:11:23.262721
1609 20:11:23.263177 Set Vref, RX VrefLevel [Byte0]: 60
1610 20:11:23.266467 [Byte1]: 60
1611 20:11:23.270854
1612 20:11:23.271408 Set Vref, RX VrefLevel [Byte0]: 61
1613 20:11:23.273564 [Byte1]: 61
1614 20:11:23.278084
1615 20:11:23.278643 Set Vref, RX VrefLevel [Byte0]: 62
1616 20:11:23.281909 [Byte1]: 62
1617 20:11:23.285687
1618 20:11:23.288685 Set Vref, RX VrefLevel [Byte0]: 63
1619 20:11:23.292611 [Byte1]: 63
1620 20:11:23.293215
1621 20:11:23.295097 Set Vref, RX VrefLevel [Byte0]: 64
1622 20:11:23.299074 [Byte1]: 64
1623 20:11:23.299529
1624 20:11:23.302519 Set Vref, RX VrefLevel [Byte0]: 65
1625 20:11:23.305748 [Byte1]: 65
1626 20:11:23.306302
1627 20:11:23.309279 Set Vref, RX VrefLevel [Byte0]: 66
1628 20:11:23.311974 [Byte1]: 66
1629 20:11:23.316474
1630 20:11:23.317065 Set Vref, RX VrefLevel [Byte0]: 67
1631 20:11:23.319505 [Byte1]: 67
1632 20:11:23.323857
1633 20:11:23.324545 Set Vref, RX VrefLevel [Byte0]: 68
1634 20:11:23.327400 [Byte1]: 68
1635 20:11:23.331514
1636 20:11:23.332070 Set Vref, RX VrefLevel [Byte0]: 69
1637 20:11:23.335256 [Byte1]: 69
1638 20:11:23.340076
1639 20:11:23.340621 Set Vref, RX VrefLevel [Byte0]: 70
1640 20:11:23.342932 [Byte1]: 70
1641 20:11:23.347360
1642 20:11:23.347912 Set Vref, RX VrefLevel [Byte0]: 71
1643 20:11:23.350440 [Byte1]: 71
1644 20:11:23.354961
1645 20:11:23.355522 Set Vref, RX VrefLevel [Byte0]: 72
1646 20:11:23.357685 [Byte1]: 72
1647 20:11:23.362155
1648 20:11:23.362728 Set Vref, RX VrefLevel [Byte0]: 73
1649 20:11:23.365530 [Byte1]: 73
1650 20:11:23.369926
1651 20:11:23.370517 Set Vref, RX VrefLevel [Byte0]: 74
1652 20:11:23.373246 [Byte1]: 74
1653 20:11:23.377889
1654 20:11:23.378483 Set Vref, RX VrefLevel [Byte0]: 75
1655 20:11:23.380552 [Byte1]: 75
1656 20:11:23.385089
1657 20:11:23.385651 Set Vref, RX VrefLevel [Byte0]: 76
1658 20:11:23.388530 [Byte1]: 76
1659 20:11:23.393013
1660 20:11:23.393579 Set Vref, RX VrefLevel [Byte0]: 77
1661 20:11:23.396742 [Byte1]: 77
1662 20:11:23.400692
1663 20:11:23.401325 Set Vref, RX VrefLevel [Byte0]: 78
1664 20:11:23.404390 [Byte1]: 78
1665 20:11:23.409134
1666 20:11:23.409698 Final RX Vref Byte 0 = 61 to rank0
1667 20:11:23.411721 Final RX Vref Byte 1 = 60 to rank0
1668 20:11:23.414894 Final RX Vref Byte 0 = 61 to rank1
1669 20:11:23.417713 Final RX Vref Byte 1 = 60 to rank1==
1670 20:11:23.421414 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 20:11:23.427833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1672 20:11:23.428390 ==
1673 20:11:23.428809 DQS Delay:
1674 20:11:23.429157 DQS0 = 0, DQS1 = 0
1675 20:11:23.431529 DQM Delay:
1676 20:11:23.432077 DQM0 = 80, DQM1 = 74
1677 20:11:23.434769 DQ Delay:
1678 20:11:23.438310 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1679 20:11:23.441119 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
1680 20:11:23.444425 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1681 20:11:23.448513 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1682 20:11:23.449113
1683 20:11:23.449474
1684 20:11:23.454971 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1685 20:11:23.458105 CH1 RK0: MR19=606, MR18=5050
1686 20:11:23.465167 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1687 20:11:23.465723
1688 20:11:23.467953 ----->DramcWriteLeveling(PI) begin...
1689 20:11:23.468509 ==
1690 20:11:23.471390 Dram Type= 6, Freq= 0, CH_1, rank 1
1691 20:11:23.474275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1692 20:11:23.474811 ==
1693 20:11:23.477976 Write leveling (Byte 0): 25 => 25
1694 20:11:23.481129 Write leveling (Byte 1): 24 => 24
1695 20:11:23.485218 DramcWriteLeveling(PI) end<-----
1696 20:11:23.485743
1697 20:11:23.486104 ==
1698 20:11:23.487493 Dram Type= 6, Freq= 0, CH_1, rank 1
1699 20:11:23.491493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1700 20:11:23.492046 ==
1701 20:11:23.495108 [Gating] SW mode calibration
1702 20:11:23.501322 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1703 20:11:23.507533 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1704 20:11:23.511391 0 6 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
1705 20:11:23.514366 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 20:11:23.521185 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 20:11:23.524304 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 20:11:23.527842 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 20:11:23.534836 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 20:11:23.537993 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 20:11:23.541131 0 6 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1712 20:11:23.547262 0 7 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1713 20:11:23.551197 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 20:11:23.554673 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 20:11:23.561086 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 20:11:23.564362 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 20:11:23.567395 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 20:11:23.574372 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 20:11:23.577478 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1720 20:11:23.581233 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1721 20:11:23.587641 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 20:11:23.590729 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 20:11:23.594295 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 20:11:23.600881 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 20:11:23.604029 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 20:11:23.607456 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 20:11:23.614548 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 20:11:23.617982 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 20:11:23.622140 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 20:11:23.624059 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 20:11:23.630689 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 20:11:23.634020 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 20:11:23.637414 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 20:11:23.643767 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1735 20:11:23.647244 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1736 20:11:23.650140 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1737 20:11:23.653606 Total UI for P1: 0, mck2ui 16
1738 20:11:23.657139 best dqsien dly found for B0: ( 0, 9, 26)
1739 20:11:23.663575 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1740 20:11:23.663660 Total UI for P1: 0, mck2ui 16
1741 20:11:23.670041 best dqsien dly found for B1: ( 0, 10, 0)
1742 20:11:23.673839 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1743 20:11:23.677286 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1744 20:11:23.677369
1745 20:11:23.680983 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1746 20:11:23.683667 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1747 20:11:23.687035 [Gating] SW calibration Done
1748 20:11:23.687119 ==
1749 20:11:23.690962 Dram Type= 6, Freq= 0, CH_1, rank 1
1750 20:11:23.693935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1751 20:11:23.694019 ==
1752 20:11:23.696878 RX Vref Scan: 0
1753 20:11:23.696962
1754 20:11:23.697046 RX Vref 0 -> 0, step: 1
1755 20:11:23.697127
1756 20:11:23.700417 RX Delay -130 -> 252, step: 16
1757 20:11:23.703658 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1758 20:11:23.710813 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1759 20:11:23.713822 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1760 20:11:23.717340 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1761 20:11:23.720342 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1762 20:11:23.723610 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1763 20:11:23.729872 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1764 20:11:23.733248 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1765 20:11:23.736659 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1766 20:11:23.739872 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1767 20:11:23.743780 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1768 20:11:23.749867 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1769 20:11:23.753742 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1770 20:11:23.757359 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1771 20:11:23.760250 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1772 20:11:23.763928 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1773 20:11:23.766768 ==
1774 20:11:23.770444 Dram Type= 6, Freq= 0, CH_1, rank 1
1775 20:11:23.773499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1776 20:11:23.773572 ==
1777 20:11:23.773635 DQS Delay:
1778 20:11:23.777447 DQS0 = 0, DQS1 = 0
1779 20:11:23.777517 DQM Delay:
1780 20:11:23.780223 DQM0 = 85, DQM1 = 73
1781 20:11:23.780317 DQ Delay:
1782 20:11:23.783708 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1783 20:11:23.787204 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1784 20:11:23.790691 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1785 20:11:23.793625 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1786 20:11:23.793695
1787 20:11:23.793756
1788 20:11:23.793812 ==
1789 20:11:23.796696 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 20:11:23.800536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1791 20:11:23.800629 ==
1792 20:11:23.800739
1793 20:11:23.800811
1794 20:11:23.803285 TX Vref Scan disable
1795 20:11:23.806992 == TX Byte 0 ==
1796 20:11:23.810212 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1797 20:11:23.813662 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1798 20:11:23.817636 == TX Byte 1 ==
1799 20:11:23.820525 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1800 20:11:23.823860 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1801 20:11:23.823944 ==
1802 20:11:23.827289 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 20:11:23.830287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 20:11:23.830371 ==
1805 20:11:23.845371 TX Vref=22, minBit 0, minWin=27, winSum=450
1806 20:11:23.847726 TX Vref=24, minBit 0, minWin=28, winSum=451
1807 20:11:23.850964 TX Vref=26, minBit 2, minWin=28, winSum=459
1808 20:11:23.854993 TX Vref=28, minBit 0, minWin=28, winSum=455
1809 20:11:23.858258 TX Vref=30, minBit 0, minWin=28, winSum=457
1810 20:11:23.864607 TX Vref=32, minBit 9, minWin=27, winSum=452
1811 20:11:23.868012 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 26
1812 20:11:23.868093
1813 20:11:23.871094 Final TX Range 1 Vref 26
1814 20:11:23.871176
1815 20:11:23.871240 ==
1816 20:11:23.874567 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 20:11:23.878421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1818 20:11:23.878503 ==
1819 20:11:23.881939
1820 20:11:23.882020
1821 20:11:23.882084 TX Vref Scan disable
1822 20:11:23.884432 == TX Byte 0 ==
1823 20:11:23.887771 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1824 20:11:23.891582 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1825 20:11:23.894932 == TX Byte 1 ==
1826 20:11:23.898128 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1827 20:11:23.901109 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1828 20:11:23.905165
1829 20:11:23.905240 [DATLAT]
1830 20:11:23.905302 Freq=800, CH1 RK1
1831 20:11:23.905360
1832 20:11:23.908207 DATLAT Default: 0x9
1833 20:11:23.908274 0, 0xFFFF, sum = 0
1834 20:11:23.911406 1, 0xFFFF, sum = 0
1835 20:11:23.911480 2, 0xFFFF, sum = 0
1836 20:11:23.914438 3, 0xFFFF, sum = 0
1837 20:11:23.914507 4, 0xFFFF, sum = 0
1838 20:11:23.917573 5, 0xFFFF, sum = 0
1839 20:11:23.921304 6, 0xFFFF, sum = 0
1840 20:11:23.921384 7, 0xFFFF, sum = 0
1841 20:11:23.921447 8, 0x0, sum = 1
1842 20:11:23.924633 9, 0x0, sum = 2
1843 20:11:23.924703 10, 0x0, sum = 3
1844 20:11:23.927851 11, 0x0, sum = 4
1845 20:11:23.927924 best_step = 9
1846 20:11:23.927983
1847 20:11:23.928048 ==
1848 20:11:23.931607 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 20:11:23.937811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1850 20:11:23.937885 ==
1851 20:11:23.937947 RX Vref Scan: 0
1852 20:11:23.938006
1853 20:11:23.941170 RX Vref 0 -> 0, step: 1
1854 20:11:23.941239
1855 20:11:23.944281 RX Delay -111 -> 252, step: 8
1856 20:11:23.947692 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1857 20:11:23.951387 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1858 20:11:23.957603 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1859 20:11:23.961425 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1860 20:11:23.964656 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1861 20:11:23.968111 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1862 20:11:23.971312 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1863 20:11:23.978139 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1864 20:11:23.980637 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1865 20:11:23.984945 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1866 20:11:23.987874 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1867 20:11:23.991504 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1868 20:11:23.997838 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1869 20:11:24.000747 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1870 20:11:24.004232 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1871 20:11:24.007570 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1872 20:11:24.007638 ==
1873 20:11:24.010860 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 20:11:24.017464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1875 20:11:24.017543 ==
1876 20:11:24.017607 DQS Delay:
1877 20:11:24.017707 DQS0 = 0, DQS1 = 0
1878 20:11:24.020663 DQM Delay:
1879 20:11:24.020782 DQM0 = 84, DQM1 = 75
1880 20:11:24.024639 DQ Delay:
1881 20:11:24.028357 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80
1882 20:11:24.028429 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1883 20:11:24.030775 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1884 20:11:24.034233 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1885 20:11:24.037540
1886 20:11:24.037615
1887 20:11:24.044012 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1888 20:11:24.047741 CH1 RK1: MR19=606, MR18=3737
1889 20:11:24.053840 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1890 20:11:24.057825 [RxdqsGatingPostProcess] freq 800
1891 20:11:24.061807 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1892 20:11:24.065227 Pre-setting of DQS Precalculation
1893 20:11:24.071347 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1894 20:11:24.077256 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1895 20:11:24.084427 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1896 20:11:24.084506
1897 20:11:24.084569
1898 20:11:24.087496 [Calibration Summary] 1600 Mbps
1899 20:11:24.087575 CH 0, Rank 0
1900 20:11:24.090783 SW Impedance : PASS
1901 20:11:24.090860 DUTY Scan : NO K
1902 20:11:24.094384 ZQ Calibration : PASS
1903 20:11:24.098075 Jitter Meter : NO K
1904 20:11:24.098147 CBT Training : PASS
1905 20:11:24.101330 Write leveling : PASS
1906 20:11:24.103873 RX DQS gating : PASS
1907 20:11:24.103944 RX DQ/DQS(RDDQC) : PASS
1908 20:11:24.107789 TX DQ/DQS : PASS
1909 20:11:24.110828 RX DATLAT : PASS
1910 20:11:24.110900 RX DQ/DQS(Engine): PASS
1911 20:11:24.114562 TX OE : NO K
1912 20:11:24.114641 All Pass.
1913 20:11:24.114703
1914 20:11:24.117193 CH 0, Rank 1
1915 20:11:24.117262 SW Impedance : PASS
1916 20:11:24.121048 DUTY Scan : NO K
1917 20:11:24.124248 ZQ Calibration : PASS
1918 20:11:24.124323 Jitter Meter : NO K
1919 20:11:24.127578 CBT Training : PASS
1920 20:11:24.131039 Write leveling : PASS
1921 20:11:24.131115 RX DQS gating : PASS
1922 20:11:24.134111 RX DQ/DQS(RDDQC) : PASS
1923 20:11:24.134188 TX DQ/DQS : PASS
1924 20:11:24.137155 RX DATLAT : PASS
1925 20:11:24.140698 RX DQ/DQS(Engine): PASS
1926 20:11:24.140809 TX OE : NO K
1927 20:11:24.144185 All Pass.
1928 20:11:24.144256
1929 20:11:24.144315 CH 1, Rank 0
1930 20:11:24.147717 SW Impedance : PASS
1931 20:11:24.147794 DUTY Scan : NO K
1932 20:11:24.151076 ZQ Calibration : PASS
1933 20:11:24.154031 Jitter Meter : NO K
1934 20:11:24.154103 CBT Training : PASS
1935 20:11:24.157226 Write leveling : PASS
1936 20:11:24.160991 RX DQS gating : PASS
1937 20:11:24.161070 RX DQ/DQS(RDDQC) : PASS
1938 20:11:24.164040 TX DQ/DQS : PASS
1939 20:11:24.167854 RX DATLAT : PASS
1940 20:11:24.167932 RX DQ/DQS(Engine): PASS
1941 20:11:24.170667 TX OE : NO K
1942 20:11:24.170738 All Pass.
1943 20:11:24.170799
1944 20:11:24.174029 CH 1, Rank 1
1945 20:11:24.174140 SW Impedance : PASS
1946 20:11:24.177232 DUTY Scan : NO K
1947 20:11:24.181323 ZQ Calibration : PASS
1948 20:11:24.181397 Jitter Meter : NO K
1949 20:11:24.184306 CBT Training : PASS
1950 20:11:24.184377 Write leveling : PASS
1951 20:11:24.188056 RX DQS gating : PASS
1952 20:11:24.190751 RX DQ/DQS(RDDQC) : PASS
1953 20:11:24.190823 TX DQ/DQS : PASS
1954 20:11:24.194367 RX DATLAT : PASS
1955 20:11:24.197342 RX DQ/DQS(Engine): PASS
1956 20:11:24.197415 TX OE : NO K
1957 20:11:24.200938 All Pass.
1958 20:11:24.201011
1959 20:11:24.201077 DramC Write-DBI off
1960 20:11:24.204429 PER_BANK_REFRESH: Hybrid Mode
1961 20:11:24.206958 TX_TRACKING: ON
1962 20:11:24.210635 [GetDramInforAfterCalByMRR] Vendor 6.
1963 20:11:24.214233 [GetDramInforAfterCalByMRR] Revision 606.
1964 20:11:24.217049 [GetDramInforAfterCalByMRR] Revision 2 0.
1965 20:11:24.217119 MR0 0x3939
1966 20:11:24.217187 MR8 0x1111
1967 20:11:24.220654 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1968 20:11:24.223989
1969 20:11:24.224070 MR0 0x3939
1970 20:11:24.224133 MR8 0x1111
1971 20:11:24.227372 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1972 20:11:24.227446
1973 20:11:24.238171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1974 20:11:24.240347 [FAST_K] Save calibration result to emmc
1975 20:11:24.243684 [FAST_K] Save calibration result to emmc
1976 20:11:24.247394 dram_init: config_dvfs: 1
1977 20:11:24.251135 dramc_set_vcore_voltage set vcore to 662500
1978 20:11:24.254342 Read voltage for 1200, 2
1979 20:11:24.254413 Vio18 = 0
1980 20:11:24.254474 Vcore = 662500
1981 20:11:24.256916 Vdram = 0
1982 20:11:24.256988 Vddq = 0
1983 20:11:24.257048 Vmddr = 0
1984 20:11:24.263778 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1985 20:11:24.267603 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1986 20:11:24.270726 MEM_TYPE=3, freq_sel=15
1987 20:11:24.274032 sv_algorithm_assistance_LP4_1600
1988 20:11:24.277113 ============ PULL DRAM RESETB DOWN ============
1989 20:11:24.280820 ========== PULL DRAM RESETB DOWN end =========
1990 20:11:24.288086 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1991 20:11:24.290611 ===================================
1992 20:11:24.290686 LPDDR4 DRAM CONFIGURATION
1993 20:11:24.293626 ===================================
1994 20:11:24.296732 EX_ROW_EN[0] = 0x0
1995 20:11:24.300594 EX_ROW_EN[1] = 0x0
1996 20:11:24.300698 LP4Y_EN = 0x0
1997 20:11:24.304267 WORK_FSP = 0x0
1998 20:11:24.304342 WL = 0x4
1999 20:11:24.307177 RL = 0x4
2000 20:11:24.307250 BL = 0x2
2001 20:11:24.311081 RPST = 0x0
2002 20:11:24.311153 RD_PRE = 0x0
2003 20:11:24.313851 WR_PRE = 0x1
2004 20:11:24.313921 WR_PST = 0x0
2005 20:11:24.317426 DBI_WR = 0x0
2006 20:11:24.317497 DBI_RD = 0x0
2007 20:11:24.320444 OTF = 0x1
2008 20:11:24.324145 ===================================
2009 20:11:24.327418 ===================================
2010 20:11:24.327494 ANA top config
2011 20:11:24.330833 ===================================
2012 20:11:24.333927 DLL_ASYNC_EN = 0
2013 20:11:24.337142 ALL_SLAVE_EN = 0
2014 20:11:24.340604 NEW_RANK_MODE = 1
2015 20:11:24.340717 DLL_IDLE_MODE = 1
2016 20:11:24.344047 LP45_APHY_COMB_EN = 1
2017 20:11:24.348194 TX_ODT_DIS = 1
2018 20:11:24.350598 NEW_8X_MODE = 1
2019 20:11:24.354027 ===================================
2020 20:11:24.357328 ===================================
2021 20:11:24.357401 data_rate = 2400
2022 20:11:24.360436 CKR = 1
2023 20:11:24.363911 DQ_P2S_RATIO = 8
2024 20:11:24.367554 ===================================
2025 20:11:24.370245 CA_P2S_RATIO = 8
2026 20:11:24.373639 DQ_CA_OPEN = 0
2027 20:11:24.377434 DQ_SEMI_OPEN = 0
2028 20:11:24.377513 CA_SEMI_OPEN = 0
2029 20:11:24.380365 CA_FULL_RATE = 0
2030 20:11:24.383495 DQ_CKDIV4_EN = 0
2031 20:11:24.388092 CA_CKDIV4_EN = 0
2032 20:11:24.390225 CA_PREDIV_EN = 0
2033 20:11:24.393968 PH8_DLY = 17
2034 20:11:24.394045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2035 20:11:24.397094 DQ_AAMCK_DIV = 4
2036 20:11:24.400624 CA_AAMCK_DIV = 4
2037 20:11:24.403664 CA_ADMCK_DIV = 4
2038 20:11:24.407347 DQ_TRACK_CA_EN = 0
2039 20:11:24.410467 CA_PICK = 1200
2040 20:11:24.414261 CA_MCKIO = 1200
2041 20:11:24.414334 MCKIO_SEMI = 0
2042 20:11:24.416817 PLL_FREQ = 2366
2043 20:11:24.420803 DQ_UI_PI_RATIO = 32
2044 20:11:24.424079 CA_UI_PI_RATIO = 0
2045 20:11:24.427573 ===================================
2046 20:11:24.431094 ===================================
2047 20:11:24.433517 memory_type:LPDDR4
2048 20:11:24.433591 GP_NUM : 10
2049 20:11:24.437673 SRAM_EN : 1
2050 20:11:24.440258 MD32_EN : 0
2051 20:11:24.443793 ===================================
2052 20:11:24.443867 [ANA_INIT] >>>>>>>>>>>>>>
2053 20:11:24.447187 <<<<<< [CONFIGURE PHASE]: ANA_TX
2054 20:11:24.450111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2055 20:11:24.453464 ===================================
2056 20:11:24.456929 data_rate = 2400,PCW = 0X5b00
2057 20:11:24.460899 ===================================
2058 20:11:24.463707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2059 20:11:24.470500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2060 20:11:24.473321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2061 20:11:24.480375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2062 20:11:24.483261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2063 20:11:24.486907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2064 20:11:24.486987 [ANA_INIT] flow start
2065 20:11:24.490100 [ANA_INIT] PLL >>>>>>>>
2066 20:11:24.493169 [ANA_INIT] PLL <<<<<<<<
2067 20:11:24.493248 [ANA_INIT] MIDPI >>>>>>>>
2068 20:11:24.497048 [ANA_INIT] MIDPI <<<<<<<<
2069 20:11:24.500098 [ANA_INIT] DLL >>>>>>>>
2070 20:11:24.503206 [ANA_INIT] DLL <<<<<<<<
2071 20:11:24.503285 [ANA_INIT] flow end
2072 20:11:24.506520 ============ LP4 DIFF to SE enter ============
2073 20:11:24.513267 ============ LP4 DIFF to SE exit ============
2074 20:11:24.513346 [ANA_INIT] <<<<<<<<<<<<<
2075 20:11:24.517067 [Flow] Enable top DCM control >>>>>
2076 20:11:24.520465 [Flow] Enable top DCM control <<<<<
2077 20:11:24.523064 Enable DLL master slave shuffle
2078 20:11:24.530050 ==============================================================
2079 20:11:24.530129 Gating Mode config
2080 20:11:24.536556 ==============================================================
2081 20:11:24.540158 Config description:
2082 20:11:24.549631 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2083 20:11:24.553334 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2084 20:11:24.559658 SELPH_MODE 0: By rank 1: By Phase
2085 20:11:24.566505 ==============================================================
2086 20:11:24.570172 GAT_TRACK_EN = 1
2087 20:11:24.570251 RX_GATING_MODE = 2
2088 20:11:24.573130 RX_GATING_TRACK_MODE = 2
2089 20:11:24.576662 SELPH_MODE = 1
2090 20:11:24.579755 PICG_EARLY_EN = 1
2091 20:11:24.583019 VALID_LAT_VALUE = 1
2092 20:11:24.589789 ==============================================================
2093 20:11:24.592843 Enter into Gating configuration >>>>
2094 20:11:24.596329 Exit from Gating configuration <<<<
2095 20:11:24.600534 Enter into DVFS_PRE_config >>>>>
2096 20:11:24.609562 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2097 20:11:24.612694 Exit from DVFS_PRE_config <<<<<
2098 20:11:24.616307 Enter into PICG configuration >>>>
2099 20:11:24.619350 Exit from PICG configuration <<<<
2100 20:11:24.623071 [RX_INPUT] configuration >>>>>
2101 20:11:24.626417 [RX_INPUT] configuration <<<<<
2102 20:11:24.629682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2103 20:11:24.635988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2104 20:11:24.643204 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2105 20:11:24.646145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2106 20:11:24.652542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2107 20:11:24.659413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2108 20:11:24.662864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2109 20:11:24.666243 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2110 20:11:24.672867 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2111 20:11:24.676314 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2112 20:11:24.679098 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2113 20:11:24.685829 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 20:11:24.689415 ===================================
2115 20:11:24.689495 LPDDR4 DRAM CONFIGURATION
2116 20:11:24.692601 ===================================
2117 20:11:24.696015 EX_ROW_EN[0] = 0x0
2118 20:11:24.696094 EX_ROW_EN[1] = 0x0
2119 20:11:24.699480 LP4Y_EN = 0x0
2120 20:11:24.702854 WORK_FSP = 0x0
2121 20:11:24.702933 WL = 0x4
2122 20:11:24.705906 RL = 0x4
2123 20:11:24.705985 BL = 0x2
2124 20:11:24.709620 RPST = 0x0
2125 20:11:24.709699 RD_PRE = 0x0
2126 20:11:24.713184 WR_PRE = 0x1
2127 20:11:24.713264 WR_PST = 0x0
2128 20:11:24.716091 DBI_WR = 0x0
2129 20:11:24.716170 DBI_RD = 0x0
2130 20:11:24.719457 OTF = 0x1
2131 20:11:24.723041 ===================================
2132 20:11:24.726292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2133 20:11:24.729597 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2134 20:11:24.733825 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 20:11:24.735734 ===================================
2136 20:11:24.739165 LPDDR4 DRAM CONFIGURATION
2137 20:11:24.742748 ===================================
2138 20:11:24.745976 EX_ROW_EN[0] = 0x10
2139 20:11:24.746055 EX_ROW_EN[1] = 0x0
2140 20:11:24.749514 LP4Y_EN = 0x0
2141 20:11:24.749592 WORK_FSP = 0x0
2142 20:11:24.752807 WL = 0x4
2143 20:11:24.752887 RL = 0x4
2144 20:11:24.756183 BL = 0x2
2145 20:11:24.756262 RPST = 0x0
2146 20:11:24.759566 RD_PRE = 0x0
2147 20:11:24.759645 WR_PRE = 0x1
2148 20:11:24.762975 WR_PST = 0x0
2149 20:11:24.763054 DBI_WR = 0x0
2150 20:11:24.766465 DBI_RD = 0x0
2151 20:11:24.769908 OTF = 0x1
2152 20:11:24.772636 ===================================
2153 20:11:24.776851 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2154 20:11:24.776930 ==
2155 20:11:24.779847 Dram Type= 6, Freq= 0, CH_0, rank 0
2156 20:11:24.785898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2157 20:11:24.785978 ==
2158 20:11:24.786041 [Duty_Offset_Calibration]
2159 20:11:24.789256 B0:0 B1:2 CA:1
2160 20:11:24.789335
2161 20:11:24.792635 [DutyScan_Calibration_Flow] k_type=0
2162 20:11:24.801702
2163 20:11:24.801781 ==CLK 0==
2164 20:11:24.805082 Final CLK duty delay cell = 0
2165 20:11:24.808183 [0] MAX Duty = 5093%(X100), DQS PI = 12
2166 20:11:24.812602 [0] MIN Duty = 4938%(X100), DQS PI = 52
2167 20:11:24.812740 [0] AVG Duty = 5015%(X100)
2168 20:11:24.815357
2169 20:11:24.818381 CH0 CLK Duty spec in!! Max-Min= 155%
2170 20:11:24.822171 [DutyScan_Calibration_Flow] ====Done====
2171 20:11:24.822251
2172 20:11:24.825382 [DutyScan_Calibration_Flow] k_type=1
2173 20:11:24.840976
2174 20:11:24.841056 ==DQS 0 ==
2175 20:11:24.844523 Final DQS duty delay cell = 0
2176 20:11:24.847478 [0] MAX Duty = 5125%(X100), DQS PI = 32
2177 20:11:24.851531 [0] MIN Duty = 5031%(X100), DQS PI = 6
2178 20:11:24.851611 [0] AVG Duty = 5078%(X100)
2179 20:11:24.854674
2180 20:11:24.854755 ==DQS 1 ==
2181 20:11:24.857463 Final DQS duty delay cell = 0
2182 20:11:24.860787 [0] MAX Duty = 5062%(X100), DQS PI = 58
2183 20:11:24.864356 [0] MIN Duty = 4906%(X100), DQS PI = 16
2184 20:11:24.867786 [0] AVG Duty = 4984%(X100)
2185 20:11:24.867866
2186 20:11:24.871290 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2187 20:11:24.871369
2188 20:11:24.874572 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2189 20:11:24.878292 [DutyScan_Calibration_Flow] ====Done====
2190 20:11:24.878372
2191 20:11:24.881598 [DutyScan_Calibration_Flow] k_type=3
2192 20:11:24.898260
2193 20:11:24.898339 ==DQM 0 ==
2194 20:11:24.901882 Final DQM duty delay cell = 0
2195 20:11:24.904794 [0] MAX Duty = 5156%(X100), DQS PI = 22
2196 20:11:24.908429 [0] MIN Duty = 4969%(X100), DQS PI = 40
2197 20:11:24.911347 [0] AVG Duty = 5062%(X100)
2198 20:11:24.911426
2199 20:11:24.911489 ==DQM 1 ==
2200 20:11:24.914880 Final DQM duty delay cell = 4
2201 20:11:24.918057 [4] MAX Duty = 5187%(X100), DQS PI = 54
2202 20:11:24.921925 [4] MIN Duty = 5000%(X100), DQS PI = 16
2203 20:11:24.925312 [4] AVG Duty = 5093%(X100)
2204 20:11:24.925389
2205 20:11:24.928996 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2206 20:11:24.929071
2207 20:11:24.931460 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2208 20:11:24.934497 [DutyScan_Calibration_Flow] ====Done====
2209 20:11:24.934577
2210 20:11:24.937919 [DutyScan_Calibration_Flow] k_type=2
2211 20:11:24.953522
2212 20:11:24.953599 ==DQ 0 ==
2213 20:11:24.957052 Final DQ duty delay cell = -4
2214 20:11:24.960019 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2215 20:11:24.963388 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2216 20:11:24.966361 [-4] AVG Duty = 4937%(X100)
2217 20:11:24.966441
2218 20:11:24.966503 ==DQ 1 ==
2219 20:11:24.969700 Final DQ duty delay cell = -4
2220 20:11:24.973097 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2221 20:11:24.976595 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2222 20:11:24.980050 [-4] AVG Duty = 4984%(X100)
2223 20:11:24.980123
2224 20:11:24.983390 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2225 20:11:24.983472
2226 20:11:24.987126 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2227 20:11:24.989777 [DutyScan_Calibration_Flow] ====Done====
2228 20:11:24.989844 ==
2229 20:11:24.993980 Dram Type= 6, Freq= 0, CH_1, rank 0
2230 20:11:24.996642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2231 20:11:24.996714 ==
2232 20:11:25.000105 [Duty_Offset_Calibration]
2233 20:11:25.000171 B0:0 B1:4 CA:-5
2234 20:11:25.000235
2235 20:11:25.003328 [DutyScan_Calibration_Flow] k_type=0
2236 20:11:25.014014
2237 20:11:25.014080 ==CLK 0==
2238 20:11:25.017129 Final CLK duty delay cell = 0
2239 20:11:25.020654 [0] MAX Duty = 5125%(X100), DQS PI = 16
2240 20:11:25.024098 [0] MIN Duty = 4875%(X100), DQS PI = 46
2241 20:11:25.024185 [0] AVG Duty = 5000%(X100)
2242 20:11:25.027429
2243 20:11:25.030530 CH1 CLK Duty spec in!! Max-Min= 250%
2244 20:11:25.033846 [DutyScan_Calibration_Flow] ====Done====
2245 20:11:25.033926
2246 20:11:25.037149 [DutyScan_Calibration_Flow] k_type=1
2247 20:11:25.053339
2248 20:11:25.053418 ==DQS 0 ==
2249 20:11:25.055621 Final DQS duty delay cell = 0
2250 20:11:25.060191 [0] MAX Duty = 5125%(X100), DQS PI = 16
2251 20:11:25.062547 [0] MIN Duty = 4875%(X100), DQS PI = 40
2252 20:11:25.065783 [0] AVG Duty = 5000%(X100)
2253 20:11:25.065863
2254 20:11:25.065926 ==DQS 1 ==
2255 20:11:25.069157 Final DQS duty delay cell = -4
2256 20:11:25.072169 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2257 20:11:25.075958 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2258 20:11:25.079804 [-4] AVG Duty = 4953%(X100)
2259 20:11:25.079883
2260 20:11:25.082782 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2261 20:11:25.082853
2262 20:11:25.085403 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2263 20:11:25.089077 [DutyScan_Calibration_Flow] ====Done====
2264 20:11:25.089180
2265 20:11:25.092013 [DutyScan_Calibration_Flow] k_type=3
2266 20:11:25.107684
2267 20:11:25.107756 ==DQM 0 ==
2268 20:11:25.110967 Final DQM duty delay cell = -4
2269 20:11:25.113796 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2270 20:11:25.117382 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2271 20:11:25.120866 [-4] AVG Duty = 4969%(X100)
2272 20:11:25.120943
2273 20:11:25.121013 ==DQM 1 ==
2274 20:11:25.124299 Final DQM duty delay cell = -4
2275 20:11:25.127693 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2276 20:11:25.130537 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2277 20:11:25.134505 [-4] AVG Duty = 4968%(X100)
2278 20:11:25.134581
2279 20:11:25.137036 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2280 20:11:25.137108
2281 20:11:25.140957 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2282 20:11:25.143884 [DutyScan_Calibration_Flow] ====Done====
2283 20:11:25.143954
2284 20:11:25.147515 [DutyScan_Calibration_Flow] k_type=2
2285 20:11:25.165302
2286 20:11:25.165385 ==DQ 0 ==
2287 20:11:25.167754 Final DQ duty delay cell = 0
2288 20:11:25.170926 [0] MAX Duty = 5062%(X100), DQS PI = 0
2289 20:11:25.174255 [0] MIN Duty = 4969%(X100), DQS PI = 42
2290 20:11:25.174325 [0] AVG Duty = 5015%(X100)
2291 20:11:25.174387
2292 20:11:25.177666 ==DQ 1 ==
2293 20:11:25.180913 Final DQ duty delay cell = 0
2294 20:11:25.184384 [0] MAX Duty = 5000%(X100), DQS PI = 8
2295 20:11:25.187709 [0] MIN Duty = 4875%(X100), DQS PI = 30
2296 20:11:25.187787 [0] AVG Duty = 4937%(X100)
2297 20:11:25.187847
2298 20:11:25.190780 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2299 20:11:25.190856
2300 20:11:25.194470 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2301 20:11:25.201499 [DutyScan_Calibration_Flow] ====Done====
2302 20:11:25.204233 nWR fixed to 30
2303 20:11:25.204305 [ModeRegInit_LP4] CH0 RK0
2304 20:11:25.207971 [ModeRegInit_LP4] CH0 RK1
2305 20:11:25.211825 [ModeRegInit_LP4] CH1 RK0
2306 20:11:25.211900 [ModeRegInit_LP4] CH1 RK1
2307 20:11:25.214840 match AC timing 6
2308 20:11:25.217581 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2309 20:11:25.221444 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2310 20:11:25.227658 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2311 20:11:25.231364 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2312 20:11:25.237520 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2313 20:11:25.237596 ==
2314 20:11:25.241177 Dram Type= 6, Freq= 0, CH_0, rank 0
2315 20:11:25.244072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2316 20:11:25.244142 ==
2317 20:11:25.251508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2318 20:11:25.254392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2319 20:11:25.263975 [CA 0] Center 39 (9~70) winsize 62
2320 20:11:25.267676 [CA 1] Center 39 (8~70) winsize 63
2321 20:11:25.271025 [CA 2] Center 36 (5~67) winsize 63
2322 20:11:25.274304 [CA 3] Center 35 (4~66) winsize 63
2323 20:11:25.277226 [CA 4] Center 34 (3~65) winsize 63
2324 20:11:25.280628 [CA 5] Center 33 (3~64) winsize 62
2325 20:11:25.280734
2326 20:11:25.283923 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2327 20:11:25.284004
2328 20:11:25.287531 [CATrainingPosCal] consider 1 rank data
2329 20:11:25.290642 u2DelayCellTimex100 = 270/100 ps
2330 20:11:25.294095 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2331 20:11:25.297217 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2332 20:11:25.304324 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2333 20:11:25.307091 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2334 20:11:25.310446 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2335 20:11:25.313669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2336 20:11:25.313739
2337 20:11:25.317198 CA PerBit enable=1, Macro0, CA PI delay=33
2338 20:11:25.317270
2339 20:11:25.320869 [CBTSetCACLKResult] CA Dly = 33
2340 20:11:25.320970 CS Dly: 7 (0~38)
2341 20:11:25.324156 ==
2342 20:11:25.324231 Dram Type= 6, Freq= 0, CH_0, rank 1
2343 20:11:25.330633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2344 20:11:25.330709 ==
2345 20:11:25.334494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2346 20:11:25.340809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2347 20:11:25.350092 [CA 0] Center 39 (8~70) winsize 63
2348 20:11:25.352945 [CA 1] Center 39 (8~70) winsize 63
2349 20:11:25.356529 [CA 2] Center 35 (5~66) winsize 62
2350 20:11:25.359329 [CA 3] Center 35 (4~66) winsize 63
2351 20:11:25.363207 [CA 4] Center 33 (3~64) winsize 62
2352 20:11:25.366578 [CA 5] Center 33 (3~64) winsize 62
2353 20:11:25.366654
2354 20:11:25.369759 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2355 20:11:25.369827
2356 20:11:25.372951 [CATrainingPosCal] consider 2 rank data
2357 20:11:25.375829 u2DelayCellTimex100 = 270/100 ps
2358 20:11:25.380252 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2359 20:11:25.382584 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2360 20:11:25.389197 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2361 20:11:25.393049 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2362 20:11:25.395905 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2363 20:11:25.399500 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2364 20:11:25.399575
2365 20:11:25.403382 CA PerBit enable=1, Macro0, CA PI delay=33
2366 20:11:25.403461
2367 20:11:25.406157 [CBTSetCACLKResult] CA Dly = 33
2368 20:11:25.406236 CS Dly: 7 (0~39)
2369 20:11:25.406298
2370 20:11:25.410015 ----->DramcWriteLeveling(PI) begin...
2371 20:11:25.412533 ==
2372 20:11:25.412613 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 20:11:25.419755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2374 20:11:25.419861 ==
2375 20:11:25.422595 Write leveling (Byte 0): 26 => 26
2376 20:11:25.426094 Write leveling (Byte 1): 25 => 25
2377 20:11:25.429333 DramcWriteLeveling(PI) end<-----
2378 20:11:25.429412
2379 20:11:25.429473 ==
2380 20:11:25.432651 Dram Type= 6, Freq= 0, CH_0, rank 0
2381 20:11:25.436077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2382 20:11:25.436156 ==
2383 20:11:25.439026 [Gating] SW mode calibration
2384 20:11:25.446256 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2385 20:11:25.449557 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2386 20:11:25.455878 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 20:11:25.459050 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 20:11:25.462875 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 20:11:25.469316 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 20:11:25.472640 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2391 20:11:25.475935 0 11 20 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 0)
2392 20:11:25.482958 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 20:11:25.486674 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 20:11:25.489287 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 20:11:25.495806 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 20:11:25.499324 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 20:11:25.502853 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 20:11:25.509582 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2399 20:11:25.513255 0 12 20 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
2400 20:11:25.516062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 20:11:25.523267 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 20:11:25.526098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 20:11:25.529554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 20:11:25.535929 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 20:11:25.539116 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 20:11:25.542295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 20:11:25.545970 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2408 20:11:25.553357 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2409 20:11:25.556006 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 20:11:25.558949 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 20:11:25.565715 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 20:11:25.568879 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 20:11:25.572404 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 20:11:25.579002 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 20:11:25.582863 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 20:11:25.585811 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 20:11:25.592717 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 20:11:25.595861 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 20:11:25.599634 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 20:11:25.606885 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 20:11:25.609461 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 20:11:25.612514 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2423 20:11:25.619365 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2424 20:11:25.623045 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2425 20:11:25.626010 Total UI for P1: 0, mck2ui 16
2426 20:11:25.629031 best dqsien dly found for B0: ( 0, 15, 18)
2427 20:11:25.632528 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2428 20:11:25.635501 Total UI for P1: 0, mck2ui 16
2429 20:11:25.638876 best dqsien dly found for B1: ( 0, 15, 20)
2430 20:11:25.642272 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2431 20:11:25.646270 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2432 20:11:25.646346
2433 20:11:25.653004 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2434 20:11:25.656118 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2435 20:11:25.656210 [Gating] SW calibration Done
2436 20:11:25.659464 ==
2437 20:11:25.659543 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 20:11:25.665547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2439 20:11:25.665623 ==
2440 20:11:25.665686 RX Vref Scan: 0
2441 20:11:25.665745
2442 20:11:25.669159 RX Vref 0 -> 0, step: 1
2443 20:11:25.669245
2444 20:11:25.672964 RX Delay -40 -> 252, step: 8
2445 20:11:25.675771 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2446 20:11:25.678838 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2447 20:11:25.682663 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2448 20:11:25.688628 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2449 20:11:25.692469 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2450 20:11:25.695261 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2451 20:11:25.699344 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2452 20:11:25.702305 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2453 20:11:25.709414 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2454 20:11:25.712074 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2455 20:11:25.715371 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2456 20:11:25.718876 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2457 20:11:25.722261 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2458 20:11:25.728683 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2459 20:11:25.731927 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2460 20:11:25.735682 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2461 20:11:25.735784 ==
2462 20:11:25.738707 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 20:11:25.742247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2464 20:11:25.742331 ==
2465 20:11:25.745396 DQS Delay:
2466 20:11:25.745473 DQS0 = 0, DQS1 = 0
2467 20:11:25.749060 DQM Delay:
2468 20:11:25.749134 DQM0 = 116, DQM1 = 107
2469 20:11:25.752700 DQ Delay:
2470 20:11:25.756021 DQ0 =111, DQ1 =115, DQ2 =119, DQ3 =115
2471 20:11:25.759000 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2472 20:11:25.761881 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2473 20:11:25.765339 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2474 20:11:25.765411
2475 20:11:25.765473
2476 20:11:25.765539 ==
2477 20:11:25.768677 Dram Type= 6, Freq= 0, CH_0, rank 0
2478 20:11:25.772198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2479 20:11:25.772279 ==
2480 20:11:25.772341
2481 20:11:25.772399
2482 20:11:25.775263 TX Vref Scan disable
2483 20:11:25.778803 == TX Byte 0 ==
2484 20:11:25.781918 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2485 20:11:25.785347 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2486 20:11:25.789014 == TX Byte 1 ==
2487 20:11:25.792331 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2488 20:11:25.795531 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2489 20:11:25.795605 ==
2490 20:11:25.798622 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 20:11:25.801876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2492 20:11:25.801954 ==
2493 20:11:25.815213 TX Vref=22, minBit 5, minWin=25, winSum=411
2494 20:11:25.819228 TX Vref=24, minBit 5, minWin=25, winSum=411
2495 20:11:25.821727 TX Vref=26, minBit 8, minWin=25, winSum=425
2496 20:11:25.825251 TX Vref=28, minBit 5, minWin=26, winSum=430
2497 20:11:25.828877 TX Vref=30, minBit 1, minWin=26, winSum=429
2498 20:11:25.832077 TX Vref=32, minBit 5, minWin=26, winSum=430
2499 20:11:25.838250 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2500 20:11:25.838340
2501 20:11:25.842333 Final TX Range 1 Vref 28
2502 20:11:25.842409
2503 20:11:25.842478 ==
2504 20:11:25.845462 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 20:11:25.848496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2506 20:11:25.848596 ==
2507 20:11:25.848693
2508 20:11:25.848816
2509 20:11:25.851928 TX Vref Scan disable
2510 20:11:25.855499 == TX Byte 0 ==
2511 20:11:25.858347 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2512 20:11:25.861697 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2513 20:11:25.865074 == TX Byte 1 ==
2514 20:11:25.868604 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2515 20:11:25.871730 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2516 20:11:25.871801
2517 20:11:25.875653 [DATLAT]
2518 20:11:25.875723 Freq=1200, CH0 RK0
2519 20:11:25.875784
2520 20:11:25.878913 DATLAT Default: 0xd
2521 20:11:25.878979 0, 0xFFFF, sum = 0
2522 20:11:25.882089 1, 0xFFFF, sum = 0
2523 20:11:25.882160 2, 0xFFFF, sum = 0
2524 20:11:25.885102 3, 0xFFFF, sum = 0
2525 20:11:25.885170 4, 0xFFFF, sum = 0
2526 20:11:25.888795 5, 0xFFFF, sum = 0
2527 20:11:25.888864 6, 0xFFFF, sum = 0
2528 20:11:25.892182 7, 0xFFFF, sum = 0
2529 20:11:25.892249 8, 0xFFFF, sum = 0
2530 20:11:25.895343 9, 0xFFFF, sum = 0
2531 20:11:25.895409 10, 0xFFFF, sum = 0
2532 20:11:25.898520 11, 0x0, sum = 1
2533 20:11:25.898594 12, 0x0, sum = 2
2534 20:11:25.901854 13, 0x0, sum = 3
2535 20:11:25.901924 14, 0x0, sum = 4
2536 20:11:25.905072 best_step = 12
2537 20:11:25.905141
2538 20:11:25.905199 ==
2539 20:11:25.908486 Dram Type= 6, Freq= 0, CH_0, rank 0
2540 20:11:25.912626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2541 20:11:25.912726 ==
2542 20:11:25.915377 RX Vref Scan: 1
2543 20:11:25.915445
2544 20:11:25.915502 Set Vref Range= 32 -> 127
2545 20:11:25.915557
2546 20:11:25.919074 RX Vref 32 -> 127, step: 1
2547 20:11:25.919145
2548 20:11:25.922508 RX Delay -21 -> 252, step: 4
2549 20:11:25.922582
2550 20:11:25.925694 Set Vref, RX VrefLevel [Byte0]: 32
2551 20:11:25.928717 [Byte1]: 32
2552 20:11:25.928838
2553 20:11:25.931941 Set Vref, RX VrefLevel [Byte0]: 33
2554 20:11:25.935614 [Byte1]: 33
2555 20:11:25.939193
2556 20:11:25.939262 Set Vref, RX VrefLevel [Byte0]: 34
2557 20:11:25.942564 [Byte1]: 34
2558 20:11:25.947424
2559 20:11:25.947492 Set Vref, RX VrefLevel [Byte0]: 35
2560 20:11:25.951139 [Byte1]: 35
2561 20:11:25.955402
2562 20:11:25.955469 Set Vref, RX VrefLevel [Byte0]: 36
2563 20:11:25.958612 [Byte1]: 36
2564 20:11:25.963232
2565 20:11:25.963300 Set Vref, RX VrefLevel [Byte0]: 37
2566 20:11:25.966563 [Byte1]: 37
2567 20:11:25.971497
2568 20:11:25.971572 Set Vref, RX VrefLevel [Byte0]: 38
2569 20:11:25.974701 [Byte1]: 38
2570 20:11:25.979078
2571 20:11:25.979145 Set Vref, RX VrefLevel [Byte0]: 39
2572 20:11:25.982870 [Byte1]: 39
2573 20:11:25.986856
2574 20:11:25.986939 Set Vref, RX VrefLevel [Byte0]: 40
2575 20:11:25.990621 [Byte1]: 40
2576 20:11:25.994793
2577 20:11:25.994859 Set Vref, RX VrefLevel [Byte0]: 41
2578 20:11:25.998000 [Byte1]: 41
2579 20:11:26.003114
2580 20:11:26.003189 Set Vref, RX VrefLevel [Byte0]: 42
2581 20:11:26.006441 [Byte1]: 42
2582 20:11:26.011232
2583 20:11:26.011301 Set Vref, RX VrefLevel [Byte0]: 43
2584 20:11:26.013949 [Byte1]: 43
2585 20:11:26.018994
2586 20:11:26.019063 Set Vref, RX VrefLevel [Byte0]: 44
2587 20:11:26.021863 [Byte1]: 44
2588 20:11:26.026755
2589 20:11:26.026828 Set Vref, RX VrefLevel [Byte0]: 45
2590 20:11:26.030249 [Byte1]: 45
2591 20:11:26.034682
2592 20:11:26.034758 Set Vref, RX VrefLevel [Byte0]: 46
2593 20:11:26.038092 [Byte1]: 46
2594 20:11:26.042399
2595 20:11:26.042468 Set Vref, RX VrefLevel [Byte0]: 47
2596 20:11:26.046037 [Byte1]: 47
2597 20:11:26.050445
2598 20:11:26.050512 Set Vref, RX VrefLevel [Byte0]: 48
2599 20:11:26.053452 [Byte1]: 48
2600 20:11:26.058463
2601 20:11:26.058530 Set Vref, RX VrefLevel [Byte0]: 49
2602 20:11:26.061428 [Byte1]: 49
2603 20:11:26.066481
2604 20:11:26.066552 Set Vref, RX VrefLevel [Byte0]: 50
2605 20:11:26.069393 [Byte1]: 50
2606 20:11:26.075207
2607 20:11:26.075282 Set Vref, RX VrefLevel [Byte0]: 51
2608 20:11:26.078177 [Byte1]: 51
2609 20:11:26.082429
2610 20:11:26.082495 Set Vref, RX VrefLevel [Byte0]: 52
2611 20:11:26.085501 [Byte1]: 52
2612 20:11:26.090175
2613 20:11:26.090244 Set Vref, RX VrefLevel [Byte0]: 53
2614 20:11:26.093619 [Byte1]: 53
2615 20:11:26.097726
2616 20:11:26.097792 Set Vref, RX VrefLevel [Byte0]: 54
2617 20:11:26.100975 [Byte1]: 54
2618 20:11:26.106146
2619 20:11:26.106218 Set Vref, RX VrefLevel [Byte0]: 55
2620 20:11:26.109693 [Byte1]: 55
2621 20:11:26.114031
2622 20:11:26.114103 Set Vref, RX VrefLevel [Byte0]: 56
2623 20:11:26.117393 [Byte1]: 56
2624 20:11:26.121726
2625 20:11:26.121800 Set Vref, RX VrefLevel [Byte0]: 57
2626 20:11:26.124924 [Byte1]: 57
2627 20:11:26.129706
2628 20:11:26.129777 Set Vref, RX VrefLevel [Byte0]: 58
2629 20:11:26.133688 [Byte1]: 58
2630 20:11:26.137500
2631 20:11:26.137569 Set Vref, RX VrefLevel [Byte0]: 59
2632 20:11:26.140994 [Byte1]: 59
2633 20:11:26.145518
2634 20:11:26.145594 Set Vref, RX VrefLevel [Byte0]: 60
2635 20:11:26.149024 [Byte1]: 60
2636 20:11:26.153611
2637 20:11:26.153681 Set Vref, RX VrefLevel [Byte0]: 61
2638 20:11:26.156716 [Byte1]: 61
2639 20:11:26.160988
2640 20:11:26.161054 Set Vref, RX VrefLevel [Byte0]: 62
2641 20:11:26.165092 [Byte1]: 62
2642 20:11:26.169063
2643 20:11:26.169133 Set Vref, RX VrefLevel [Byte0]: 63
2644 20:11:26.172829 [Byte1]: 63
2645 20:11:26.177554
2646 20:11:26.177621 Set Vref, RX VrefLevel [Byte0]: 64
2647 20:11:26.180477 [Byte1]: 64
2648 20:11:26.184923
2649 20:11:26.184993 Set Vref, RX VrefLevel [Byte0]: 65
2650 20:11:26.188561 [Byte1]: 65
2651 20:11:26.192770
2652 20:11:26.192837 Set Vref, RX VrefLevel [Byte0]: 66
2653 20:11:26.196976 [Byte1]: 66
2654 20:11:26.201250
2655 20:11:26.201315 Final RX Vref Byte 0 = 47 to rank0
2656 20:11:26.204538 Final RX Vref Byte 1 = 46 to rank0
2657 20:11:26.207881 Final RX Vref Byte 0 = 47 to rank1
2658 20:11:26.211770 Final RX Vref Byte 1 = 46 to rank1==
2659 20:11:26.214512 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 20:11:26.220801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2661 20:11:26.220902 ==
2662 20:11:26.221000 DQS Delay:
2663 20:11:26.221094 DQS0 = 0, DQS1 = 0
2664 20:11:26.224031 DQM Delay:
2665 20:11:26.224100 DQM0 = 114, DQM1 = 104
2666 20:11:26.227574 DQ Delay:
2667 20:11:26.230730 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2668 20:11:26.234134 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2669 20:11:26.237826 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2670 20:11:26.240924 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2671 20:11:26.240991
2672 20:11:26.241049
2673 20:11:26.248375 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2674 20:11:26.251747 CH0 RK0: MR19=404, MR18=909
2675 20:11:26.257178 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2676 20:11:26.257253
2677 20:11:26.260723 ----->DramcWriteLeveling(PI) begin...
2678 20:11:26.260797 ==
2679 20:11:26.263860 Dram Type= 6, Freq= 0, CH_0, rank 1
2680 20:11:26.268005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2681 20:11:26.268071 ==
2682 20:11:26.270569 Write leveling (Byte 0): 29 => 29
2683 20:11:26.273735 Write leveling (Byte 1): 25 => 25
2684 20:11:26.277199 DramcWriteLeveling(PI) end<-----
2685 20:11:26.277266
2686 20:11:26.277325 ==
2687 20:11:26.281166 Dram Type= 6, Freq= 0, CH_0, rank 1
2688 20:11:26.287425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2689 20:11:26.287497 ==
2690 20:11:26.287560 [Gating] SW mode calibration
2691 20:11:26.297965 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2692 20:11:26.301389 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2693 20:11:26.304165 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2694 20:11:26.310730 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2695 20:11:26.314343 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2696 20:11:26.317086 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 20:11:26.324379 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2698 20:11:26.327120 0 11 20 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (1 0)
2699 20:11:26.330784 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 20:11:26.337786 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 20:11:26.340997 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 20:11:26.344195 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 20:11:26.350644 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 20:11:26.353759 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 20:11:26.357131 0 12 16 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
2706 20:11:26.363938 0 12 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2707 20:11:26.367642 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 20:11:26.370478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 20:11:26.377378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 20:11:26.380895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 20:11:26.384199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 20:11:26.387495 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 20:11:26.393975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2714 20:11:26.397175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2715 20:11:26.400586 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 20:11:26.407729 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 20:11:26.410511 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 20:11:26.413609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 20:11:26.420397 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 20:11:26.423823 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 20:11:26.426993 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 20:11:26.434341 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 20:11:26.437185 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 20:11:26.440913 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 20:11:26.447441 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 20:11:26.451037 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 20:11:26.454674 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 20:11:26.460910 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 20:11:26.464145 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2730 20:11:26.467189 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2731 20:11:26.470285 Total UI for P1: 0, mck2ui 16
2732 20:11:26.474451 best dqsien dly found for B1: ( 0, 15, 16)
2733 20:11:26.480839 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2734 20:11:26.480915 Total UI for P1: 0, mck2ui 16
2735 20:11:26.483610 best dqsien dly found for B0: ( 0, 15, 18)
2736 20:11:26.490707 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2737 20:11:26.494261 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2738 20:11:26.494331
2739 20:11:26.498138 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2740 20:11:26.500560 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2741 20:11:26.504575 [Gating] SW calibration Done
2742 20:11:26.504646 ==
2743 20:11:26.508720 Dram Type= 6, Freq= 0, CH_0, rank 1
2744 20:11:26.510913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2745 20:11:26.510981 ==
2746 20:11:26.513635 RX Vref Scan: 0
2747 20:11:26.513702
2748 20:11:26.513760 RX Vref 0 -> 0, step: 1
2749 20:11:26.513817
2750 20:11:26.517120 RX Delay -40 -> 252, step: 8
2751 20:11:26.520443 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2752 20:11:26.526860 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2753 20:11:26.530776 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2754 20:11:26.533598 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2755 20:11:26.537181 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2756 20:11:26.541062 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2757 20:11:26.543585 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2758 20:11:26.550174 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2759 20:11:26.553862 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2760 20:11:26.556971 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2761 20:11:26.559998 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2762 20:11:26.564074 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2763 20:11:26.570786 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2764 20:11:26.574305 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2765 20:11:26.577296 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2766 20:11:26.580152 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2767 20:11:26.580218 ==
2768 20:11:26.583912 Dram Type= 6, Freq= 0, CH_0, rank 1
2769 20:11:26.590570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2770 20:11:26.590641 ==
2771 20:11:26.590704 DQS Delay:
2772 20:11:26.594427 DQS0 = 0, DQS1 = 0
2773 20:11:26.594502 DQM Delay:
2774 20:11:26.596655 DQM0 = 114, DQM1 = 106
2775 20:11:26.596729 DQ Delay:
2776 20:11:26.600108 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =107
2777 20:11:26.603278 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2778 20:11:26.606743 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2779 20:11:26.610159 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2780 20:11:26.610223
2781 20:11:26.610283
2782 20:11:26.610339 ==
2783 20:11:26.613478 Dram Type= 6, Freq= 0, CH_0, rank 1
2784 20:11:26.616776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2785 20:11:26.620522 ==
2786 20:11:26.620589
2787 20:11:26.620647
2788 20:11:26.620715 TX Vref Scan disable
2789 20:11:26.624409 == TX Byte 0 ==
2790 20:11:26.626425 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2791 20:11:26.629761 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2792 20:11:26.634197 == TX Byte 1 ==
2793 20:11:26.637256 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2794 20:11:26.639798 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2795 20:11:26.643389 ==
2796 20:11:26.643456 Dram Type= 6, Freq= 0, CH_0, rank 1
2797 20:11:26.649914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2798 20:11:26.649985 ==
2799 20:11:26.660870 TX Vref=22, minBit 8, minWin=25, winSum=417
2800 20:11:26.664243 TX Vref=24, minBit 8, minWin=25, winSum=426
2801 20:11:26.668019 TX Vref=26, minBit 8, minWin=26, winSum=429
2802 20:11:26.671142 TX Vref=28, minBit 9, minWin=26, winSum=431
2803 20:11:26.674667 TX Vref=30, minBit 9, minWin=26, winSum=435
2804 20:11:26.678009 TX Vref=32, minBit 9, minWin=26, winSum=435
2805 20:11:26.684450 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
2806 20:11:26.684525
2807 20:11:26.688149 Final TX Range 1 Vref 30
2808 20:11:26.688216
2809 20:11:26.688275 ==
2810 20:11:26.692008 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 20:11:26.694244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2812 20:11:26.694337 ==
2813 20:11:26.694427
2814 20:11:26.697861
2815 20:11:26.697929 TX Vref Scan disable
2816 20:11:26.701546 == TX Byte 0 ==
2817 20:11:26.704439 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2818 20:11:26.707876 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2819 20:11:26.711220 == TX Byte 1 ==
2820 20:11:26.714378 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2821 20:11:26.717991 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2822 20:11:26.718058
2823 20:11:26.721029 [DATLAT]
2824 20:11:26.721122 Freq=1200, CH0 RK1
2825 20:11:26.721212
2826 20:11:26.724085 DATLAT Default: 0xc
2827 20:11:26.724177 0, 0xFFFF, sum = 0
2828 20:11:26.727369 1, 0xFFFF, sum = 0
2829 20:11:26.727447 2, 0xFFFF, sum = 0
2830 20:11:26.730945 3, 0xFFFF, sum = 0
2831 20:11:26.731020 4, 0xFFFF, sum = 0
2832 20:11:26.734385 5, 0xFFFF, sum = 0
2833 20:11:26.734462 6, 0xFFFF, sum = 0
2834 20:11:26.737355 7, 0xFFFF, sum = 0
2835 20:11:26.741014 8, 0xFFFF, sum = 0
2836 20:11:26.741088 9, 0xFFFF, sum = 0
2837 20:11:26.744293 10, 0xFFFF, sum = 0
2838 20:11:26.744365 11, 0x0, sum = 1
2839 20:11:26.748192 12, 0x0, sum = 2
2840 20:11:26.748265 13, 0x0, sum = 3
2841 20:11:26.748325 14, 0x0, sum = 4
2842 20:11:26.751011 best_step = 12
2843 20:11:26.751086
2844 20:11:26.751146 ==
2845 20:11:26.754929 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 20:11:26.757393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2847 20:11:26.757465 ==
2848 20:11:26.761010 RX Vref Scan: 0
2849 20:11:26.761080
2850 20:11:26.761138 RX Vref 0 -> 0, step: 1
2851 20:11:26.761195
2852 20:11:26.764053 RX Delay -21 -> 252, step: 4
2853 20:11:26.771199 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2854 20:11:26.774768 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2855 20:11:26.778059 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2856 20:11:26.781547 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2857 20:11:26.784353 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2858 20:11:26.791494 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2859 20:11:26.795088 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2860 20:11:26.798651 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2861 20:11:26.801532 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2862 20:11:26.804617 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2863 20:11:26.811941 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2864 20:11:26.814513 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2865 20:11:26.817912 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2866 20:11:26.821473 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2867 20:11:26.824175 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
2868 20:11:26.831330 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2869 20:11:26.831408 ==
2870 20:11:26.834107 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 20:11:26.837502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2872 20:11:26.837579 ==
2873 20:11:26.837641 DQS Delay:
2874 20:11:26.840979 DQS0 = 0, DQS1 = 0
2875 20:11:26.841051 DQM Delay:
2876 20:11:26.844576 DQM0 = 114, DQM1 = 104
2877 20:11:26.844653 DQ Delay:
2878 20:11:26.847849 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2879 20:11:26.850844 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2880 20:11:26.854495 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2881 20:11:26.857860 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =114
2882 20:11:26.857933
2883 20:11:26.857994
2884 20:11:26.867358 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2885 20:11:26.871311 CH0 RK1: MR19=404, MR18=E0E
2886 20:11:26.874402 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2887 20:11:26.877542 [RxdqsGatingPostProcess] freq 1200
2888 20:11:26.884532 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2889 20:11:26.887730 Pre-setting of DQS Precalculation
2890 20:11:26.890625 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2891 20:11:26.894223 ==
2892 20:11:26.894293 Dram Type= 6, Freq= 0, CH_1, rank 0
2893 20:11:26.900915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2894 20:11:26.900997 ==
2895 20:11:26.904692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2896 20:11:26.910734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2897 20:11:26.919958 [CA 0] Center 37 (7~68) winsize 62
2898 20:11:26.923004 [CA 1] Center 37 (7~68) winsize 62
2899 20:11:26.926394 [CA 2] Center 34 (4~65) winsize 62
2900 20:11:26.929569 [CA 3] Center 33 (3~64) winsize 62
2901 20:11:26.932939 [CA 4] Center 32 (2~63) winsize 62
2902 20:11:26.936184 [CA 5] Center 32 (2~63) winsize 62
2903 20:11:26.936265
2904 20:11:26.939535 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2905 20:11:26.939616
2906 20:11:26.942839 [CATrainingPosCal] consider 1 rank data
2907 20:11:26.946747 u2DelayCellTimex100 = 270/100 ps
2908 20:11:26.949700 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2909 20:11:26.953002 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2910 20:11:26.959733 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2911 20:11:26.963767 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2912 20:11:26.966998 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2913 20:11:26.969667 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2914 20:11:26.969747
2915 20:11:26.972846 CA PerBit enable=1, Macro0, CA PI delay=32
2916 20:11:26.972926
2917 20:11:26.976926 [CBTSetCACLKResult] CA Dly = 32
2918 20:11:26.977007 CS Dly: 5 (0~36)
2919 20:11:26.977072 ==
2920 20:11:26.979626 Dram Type= 6, Freq= 0, CH_1, rank 1
2921 20:11:26.986876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2922 20:11:26.986958 ==
2923 20:11:26.989905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2924 20:11:26.996490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2925 20:11:27.004737 [CA 0] Center 37 (7~68) winsize 62
2926 20:11:27.008116 [CA 1] Center 37 (7~68) winsize 62
2927 20:11:27.011686 [CA 2] Center 34 (3~65) winsize 63
2928 20:11:27.015432 [CA 3] Center 33 (3~64) winsize 62
2929 20:11:27.018529 [CA 4] Center 32 (2~63) winsize 62
2930 20:11:27.021822 [CA 5] Center 32 (1~63) winsize 63
2931 20:11:27.021903
2932 20:11:27.025117 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2933 20:11:27.025199
2934 20:11:27.028289 [CATrainingPosCal] consider 2 rank data
2935 20:11:27.032327 u2DelayCellTimex100 = 270/100 ps
2936 20:11:27.035242 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2937 20:11:27.038110 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2938 20:11:27.042587 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2939 20:11:27.047928 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2940 20:11:27.051454 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2941 20:11:27.054610 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2942 20:11:27.054691
2943 20:11:27.057952 CA PerBit enable=1, Macro0, CA PI delay=32
2944 20:11:27.058033
2945 20:11:27.061392 [CBTSetCACLKResult] CA Dly = 32
2946 20:11:27.061473 CS Dly: 6 (0~38)
2947 20:11:27.061538
2948 20:11:27.064680 ----->DramcWriteLeveling(PI) begin...
2949 20:11:27.068215 ==
2950 20:11:27.071405 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 20:11:27.074807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 20:11:27.074888 ==
2953 20:11:27.077824 Write leveling (Byte 0): 21 => 21
2954 20:11:27.081587 Write leveling (Byte 1): 22 => 22
2955 20:11:27.085035 DramcWriteLeveling(PI) end<-----
2956 20:11:27.085116
2957 20:11:27.085179 ==
2958 20:11:27.088009 Dram Type= 6, Freq= 0, CH_1, rank 0
2959 20:11:27.091263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2960 20:11:27.091344 ==
2961 20:11:27.094476 [Gating] SW mode calibration
2962 20:11:27.101283 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2963 20:11:27.107595 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2964 20:11:27.111983 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 20:11:27.114200 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 20:11:27.121353 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 20:11:27.124455 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2968 20:11:27.127876 0 11 16 | B1->B0 | 3030 2727 | 0 0 | (0 0) (1 0)
2969 20:11:27.134731 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2970 20:11:27.137899 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 20:11:27.141041 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 20:11:27.144296 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 20:11:27.150859 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 20:11:27.154078 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 20:11:27.157762 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2976 20:11:27.164783 0 12 16 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (1 1)
2977 20:11:27.168331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 20:11:27.170890 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 20:11:27.177583 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 20:11:27.180760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 20:11:27.184366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 20:11:27.191591 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 20:11:27.194362 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 20:11:27.198053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2985 20:11:27.204272 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2986 20:11:27.207363 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 20:11:27.211690 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 20:11:27.217333 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 20:11:27.221020 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 20:11:27.224276 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 20:11:27.230689 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 20:11:27.234217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 20:11:27.237702 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 20:11:27.240914 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 20:11:27.248927 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 20:11:27.250682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 20:11:27.254670 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 20:11:27.261102 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 20:11:27.264055 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3000 20:11:27.267647 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3001 20:11:27.274320 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3002 20:11:27.277518 Total UI for P1: 0, mck2ui 16
3003 20:11:27.280751 best dqsien dly found for B0: ( 0, 15, 14)
3004 20:11:27.284432 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3005 20:11:27.287836 Total UI for P1: 0, mck2ui 16
3006 20:11:27.291024 best dqsien dly found for B1: ( 0, 15, 20)
3007 20:11:27.294912 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3008 20:11:27.297897 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3009 20:11:27.297978
3010 20:11:27.301063 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3011 20:11:27.304750 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3012 20:11:27.307502 [Gating] SW calibration Done
3013 20:11:27.307582 ==
3014 20:11:27.311230 Dram Type= 6, Freq= 0, CH_1, rank 0
3015 20:11:27.314203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3016 20:11:27.318346 ==
3017 20:11:27.318426 RX Vref Scan: 0
3018 20:11:27.318490
3019 20:11:27.320828 RX Vref 0 -> 0, step: 1
3020 20:11:27.320908
3021 20:11:27.324637 RX Delay -40 -> 252, step: 8
3022 20:11:27.327316 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3023 20:11:27.332000 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3024 20:11:27.334078 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3025 20:11:27.337723 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3026 20:11:27.344254 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3027 20:11:27.347701 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3028 20:11:27.351491 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3029 20:11:27.354311 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3030 20:11:27.358712 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3031 20:11:27.360689 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3032 20:11:27.367556 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3033 20:11:27.371291 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3034 20:11:27.374132 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3035 20:11:27.377752 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3036 20:11:27.384126 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3037 20:11:27.387990 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3038 20:11:27.388071 ==
3039 20:11:27.390627 Dram Type= 6, Freq= 0, CH_1, rank 0
3040 20:11:27.394272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3041 20:11:27.394353 ==
3042 20:11:27.397447 DQS Delay:
3043 20:11:27.397556 DQS0 = 0, DQS1 = 0
3044 20:11:27.397638 DQM Delay:
3045 20:11:27.400395 DQM0 = 116, DQM1 = 109
3046 20:11:27.400475 DQ Delay:
3047 20:11:27.404099 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3048 20:11:27.407350 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3049 20:11:27.410823 DQ8 =87, DQ9 =99, DQ10 =107, DQ11 =103
3050 20:11:27.417694 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3051 20:11:27.417775
3052 20:11:27.417838
3053 20:11:27.417897 ==
3054 20:11:27.420600 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 20:11:27.423783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3056 20:11:27.423865 ==
3057 20:11:27.423929
3058 20:11:27.423988
3059 20:11:27.427185 TX Vref Scan disable
3060 20:11:27.427265 == TX Byte 0 ==
3061 20:11:27.433921 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3062 20:11:27.437213 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3063 20:11:27.437294 == TX Byte 1 ==
3064 20:11:27.443966 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3065 20:11:27.447237 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3066 20:11:27.447318 ==
3067 20:11:27.450798 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 20:11:27.454119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3069 20:11:27.454200 ==
3070 20:11:27.466548 TX Vref=22, minBit 3, minWin=25, winSum=414
3071 20:11:27.469659 TX Vref=24, minBit 9, minWin=25, winSum=421
3072 20:11:27.473013 TX Vref=26, minBit 11, minWin=25, winSum=425
3073 20:11:27.476144 TX Vref=28, minBit 1, minWin=26, winSum=431
3074 20:11:27.479776 TX Vref=30, minBit 1, minWin=26, winSum=430
3075 20:11:27.486487 TX Vref=32, minBit 8, minWin=26, winSum=431
3076 20:11:27.489138 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3077 20:11:27.489219
3078 20:11:27.492428 Final TX Range 1 Vref 28
3079 20:11:27.492535
3080 20:11:27.492629 ==
3081 20:11:27.496205 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 20:11:27.499435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3083 20:11:27.499517 ==
3084 20:11:27.502453
3085 20:11:27.502533
3086 20:11:27.502596 TX Vref Scan disable
3087 20:11:27.505950 == TX Byte 0 ==
3088 20:11:27.509879 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3089 20:11:27.516598 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3090 20:11:27.516730 == TX Byte 1 ==
3091 20:11:27.519258 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3092 20:11:27.525712 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3093 20:11:27.525793
3094 20:11:27.525857 [DATLAT]
3095 20:11:27.525917 Freq=1200, CH1 RK0
3096 20:11:27.525974
3097 20:11:27.529173 DATLAT Default: 0xd
3098 20:11:27.529254 0, 0xFFFF, sum = 0
3099 20:11:27.532232 1, 0xFFFF, sum = 0
3100 20:11:27.532343 2, 0xFFFF, sum = 0
3101 20:11:27.535588 3, 0xFFFF, sum = 0
3102 20:11:27.539537 4, 0xFFFF, sum = 0
3103 20:11:27.539619 5, 0xFFFF, sum = 0
3104 20:11:27.542578 6, 0xFFFF, sum = 0
3105 20:11:27.542659 7, 0xFFFF, sum = 0
3106 20:11:27.545659 8, 0xFFFF, sum = 0
3107 20:11:27.545741 9, 0xFFFF, sum = 0
3108 20:11:27.549045 10, 0xFFFF, sum = 0
3109 20:11:27.549127 11, 0x0, sum = 1
3110 20:11:27.552654 12, 0x0, sum = 2
3111 20:11:27.552808 13, 0x0, sum = 3
3112 20:11:27.555934 14, 0x0, sum = 4
3113 20:11:27.556015 best_step = 12
3114 20:11:27.556078
3115 20:11:27.556137 ==
3116 20:11:27.559114 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 20:11:27.562437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3118 20:11:27.562518 ==
3119 20:11:27.566473 RX Vref Scan: 1
3120 20:11:27.566554
3121 20:11:27.569490 Set Vref Range= 32 -> 127
3122 20:11:27.569571
3123 20:11:27.569635 RX Vref 32 -> 127, step: 1
3124 20:11:27.569694
3125 20:11:27.572504 RX Delay -29 -> 252, step: 4
3126 20:11:27.572585
3127 20:11:27.575639 Set Vref, RX VrefLevel [Byte0]: 32
3128 20:11:27.579332 [Byte1]: 32
3129 20:11:27.582975
3130 20:11:27.583055 Set Vref, RX VrefLevel [Byte0]: 33
3131 20:11:27.586422 [Byte1]: 33
3132 20:11:27.590963
3133 20:11:27.591043 Set Vref, RX VrefLevel [Byte0]: 34
3134 20:11:27.594329 [Byte1]: 34
3135 20:11:27.598422
3136 20:11:27.598502 Set Vref, RX VrefLevel [Byte0]: 35
3137 20:11:27.602129 [Byte1]: 35
3138 20:11:27.606728
3139 20:11:27.606836 Set Vref, RX VrefLevel [Byte0]: 36
3140 20:11:27.609745 [Byte1]: 36
3141 20:11:27.614588
3142 20:11:27.614668 Set Vref, RX VrefLevel [Byte0]: 37
3143 20:11:27.617665 [Byte1]: 37
3144 20:11:27.622394
3145 20:11:27.622474 Set Vref, RX VrefLevel [Byte0]: 38
3146 20:11:27.625780 [Byte1]: 38
3147 20:11:27.631078
3148 20:11:27.631158 Set Vref, RX VrefLevel [Byte0]: 39
3149 20:11:27.634292 [Byte1]: 39
3150 20:11:27.638365
3151 20:11:27.638445 Set Vref, RX VrefLevel [Byte0]: 40
3152 20:11:27.642081 [Byte1]: 40
3153 20:11:27.646298
3154 20:11:27.646378 Set Vref, RX VrefLevel [Byte0]: 41
3155 20:11:27.649577 [Byte1]: 41
3156 20:11:27.654028
3157 20:11:27.654108 Set Vref, RX VrefLevel [Byte0]: 42
3158 20:11:27.657339 [Byte1]: 42
3159 20:11:27.662381
3160 20:11:27.662462 Set Vref, RX VrefLevel [Byte0]: 43
3161 20:11:27.665723 [Byte1]: 43
3162 20:11:27.670107
3163 20:11:27.670187 Set Vref, RX VrefLevel [Byte0]: 44
3164 20:11:27.673300 [Byte1]: 44
3165 20:11:27.678085
3166 20:11:27.678169 Set Vref, RX VrefLevel [Byte0]: 45
3167 20:11:27.681807 [Byte1]: 45
3168 20:11:27.686045
3169 20:11:27.686125 Set Vref, RX VrefLevel [Byte0]: 46
3170 20:11:27.689193 [Byte1]: 46
3171 20:11:27.693803
3172 20:11:27.693886 Set Vref, RX VrefLevel [Byte0]: 47
3173 20:11:27.697744 [Byte1]: 47
3174 20:11:27.701932
3175 20:11:27.702012 Set Vref, RX VrefLevel [Byte0]: 48
3176 20:11:27.705429 [Byte1]: 48
3177 20:11:27.710021
3178 20:11:27.710118 Set Vref, RX VrefLevel [Byte0]: 49
3179 20:11:27.713241 [Byte1]: 49
3180 20:11:27.718601
3181 20:11:27.718696 Set Vref, RX VrefLevel [Byte0]: 50
3182 20:11:27.721387 [Byte1]: 50
3183 20:11:27.725763
3184 20:11:27.725843 Set Vref, RX VrefLevel [Byte0]: 51
3185 20:11:27.729092 [Byte1]: 51
3186 20:11:27.733676
3187 20:11:27.733757 Set Vref, RX VrefLevel [Byte0]: 52
3188 20:11:27.737360 [Byte1]: 52
3189 20:11:27.742322
3190 20:11:27.742401 Set Vref, RX VrefLevel [Byte0]: 53
3191 20:11:27.744962 [Byte1]: 53
3192 20:11:27.750458
3193 20:11:27.750538 Set Vref, RX VrefLevel [Byte0]: 54
3194 20:11:27.752858 [Byte1]: 54
3195 20:11:27.757851
3196 20:11:27.757931 Set Vref, RX VrefLevel [Byte0]: 55
3197 20:11:27.761365 [Byte1]: 55
3198 20:11:27.765623
3199 20:11:27.765703 Set Vref, RX VrefLevel [Byte0]: 56
3200 20:11:27.768790 [Byte1]: 56
3201 20:11:27.773413
3202 20:11:27.773493 Set Vref, RX VrefLevel [Byte0]: 57
3203 20:11:27.777047 [Byte1]: 57
3204 20:11:27.781775
3205 20:11:27.781856 Set Vref, RX VrefLevel [Byte0]: 58
3206 20:11:27.784976 [Byte1]: 58
3207 20:11:27.789693
3208 20:11:27.789773 Set Vref, RX VrefLevel [Byte0]: 59
3209 20:11:27.792634 [Byte1]: 59
3210 20:11:27.797319
3211 20:11:27.797400 Set Vref, RX VrefLevel [Byte0]: 60
3212 20:11:27.801098 [Byte1]: 60
3213 20:11:27.805520
3214 20:11:27.805599 Set Vref, RX VrefLevel [Byte0]: 61
3215 20:11:27.808747 [Byte1]: 61
3216 20:11:27.813934
3217 20:11:27.814015 Set Vref, RX VrefLevel [Byte0]: 62
3218 20:11:27.816535 [Byte1]: 62
3219 20:11:27.821196
3220 20:11:27.821276 Set Vref, RX VrefLevel [Byte0]: 63
3221 20:11:27.825279 [Byte1]: 63
3222 20:11:27.829466
3223 20:11:27.829582 Set Vref, RX VrefLevel [Byte0]: 64
3224 20:11:27.832989 [Byte1]: 64
3225 20:11:27.837598
3226 20:11:27.837701 Set Vref, RX VrefLevel [Byte0]: 65
3227 20:11:27.840360 [Byte1]: 65
3228 20:11:27.845456
3229 20:11:27.845539 Final RX Vref Byte 0 = 54 to rank0
3230 20:11:27.849013 Final RX Vref Byte 1 = 49 to rank0
3231 20:11:27.851868 Final RX Vref Byte 0 = 54 to rank1
3232 20:11:27.855989 Final RX Vref Byte 1 = 49 to rank1==
3233 20:11:27.858283 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 20:11:27.865456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3235 20:11:27.865538 ==
3236 20:11:27.865602 DQS Delay:
3237 20:11:27.865663 DQS0 = 0, DQS1 = 0
3238 20:11:27.868813 DQM Delay:
3239 20:11:27.868893 DQM0 = 115, DQM1 = 105
3240 20:11:27.872433 DQ Delay:
3241 20:11:27.875039 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3242 20:11:27.878568 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3243 20:11:27.881880 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3244 20:11:27.885194 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =114
3245 20:11:27.885275
3246 20:11:27.885353
3247 20:11:27.891765 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3248 20:11:27.895848 CH1 RK0: MR19=404, MR18=1C1C
3249 20:11:27.902791 CH1_RK0: MR19=0x404, MR18=0x1C1C, DQSOSC=399, MR23=63, INC=41, DEC=27
3250 20:11:27.902872
3251 20:11:27.905997 ----->DramcWriteLeveling(PI) begin...
3252 20:11:27.906080 ==
3253 20:11:27.908952 Dram Type= 6, Freq= 0, CH_1, rank 1
3254 20:11:27.912422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3255 20:11:27.915301 ==
3256 20:11:27.915382 Write leveling (Byte 0): 20 => 20
3257 20:11:27.918535 Write leveling (Byte 1): 22 => 22
3258 20:11:27.921969 DramcWriteLeveling(PI) end<-----
3259 20:11:27.922049
3260 20:11:27.922112 ==
3261 20:11:27.925419 Dram Type= 6, Freq= 0, CH_1, rank 1
3262 20:11:27.932008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3263 20:11:27.932091 ==
3264 20:11:27.932154 [Gating] SW mode calibration
3265 20:11:27.941892 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3266 20:11:27.945168 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3267 20:11:27.952000 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3268 20:11:27.955499 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3269 20:11:27.958447 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3270 20:11:27.961831 0 11 12 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (0 0)
3271 20:11:27.968630 0 11 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
3272 20:11:27.971672 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3273 20:11:27.975573 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 20:11:27.982186 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 20:11:27.984977 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 20:11:27.989141 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 20:11:27.995179 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 20:11:27.998202 0 12 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
3279 20:11:28.001878 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3280 20:11:28.008585 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 20:11:28.011657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 20:11:28.014946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 20:11:28.021761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 20:11:28.025303 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 20:11:28.028547 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 20:11:28.034850 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 20:11:28.038142 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3288 20:11:28.042116 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3289 20:11:28.048229 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 20:11:28.051805 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 20:11:28.055225 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 20:11:28.058765 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 20:11:28.065187 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 20:11:28.068417 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 20:11:28.071278 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 20:11:28.078759 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 20:11:28.081632 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 20:11:28.085041 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 20:11:28.092797 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 20:11:28.094509 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 20:11:28.098022 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 20:11:28.105544 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3303 20:11:28.108096 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3304 20:11:28.111219 Total UI for P1: 0, mck2ui 16
3305 20:11:28.114978 best dqsien dly found for B0: ( 0, 15, 12)
3306 20:11:28.118703 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3307 20:11:28.125122 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3308 20:11:28.125203 Total UI for P1: 0, mck2ui 16
3309 20:11:28.131369 best dqsien dly found for B1: ( 0, 15, 16)
3310 20:11:28.134741 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3311 20:11:28.138117 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3312 20:11:28.138197
3313 20:11:28.141019 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3314 20:11:28.145459 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3315 20:11:28.147930 [Gating] SW calibration Done
3316 20:11:28.148009 ==
3317 20:11:28.151054 Dram Type= 6, Freq= 0, CH_1, rank 1
3318 20:11:28.154633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3319 20:11:28.154713 ==
3320 20:11:28.158068 RX Vref Scan: 0
3321 20:11:28.158174
3322 20:11:28.158253 RX Vref 0 -> 0, step: 1
3323 20:11:28.158313
3324 20:11:28.161353 RX Delay -40 -> 252, step: 8
3325 20:11:28.164487 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3326 20:11:28.171575 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3327 20:11:28.174466 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3328 20:11:28.178037 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3329 20:11:28.181138 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3330 20:11:28.184313 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3331 20:11:28.191552 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3332 20:11:28.194458 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3333 20:11:28.198166 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3334 20:11:28.201170 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
3335 20:11:28.204546 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3336 20:11:28.210855 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3337 20:11:28.214151 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3338 20:11:28.217991 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3339 20:11:28.220802 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3340 20:11:28.224944 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3341 20:11:28.227574 ==
3342 20:11:28.227651 Dram Type= 6, Freq= 0, CH_1, rank 1
3343 20:11:28.234264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3344 20:11:28.234345 ==
3345 20:11:28.234409 DQS Delay:
3346 20:11:28.237710 DQS0 = 0, DQS1 = 0
3347 20:11:28.237791 DQM Delay:
3348 20:11:28.241221 DQM0 = 116, DQM1 = 104
3349 20:11:28.241301 DQ Delay:
3350 20:11:28.244407 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3351 20:11:28.247979 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3352 20:11:28.251101 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =95
3353 20:11:28.255037 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3354 20:11:28.255117
3355 20:11:28.255181
3356 20:11:28.255240 ==
3357 20:11:28.258298 Dram Type= 6, Freq= 0, CH_1, rank 1
3358 20:11:28.261483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3359 20:11:28.264324 ==
3360 20:11:28.264403
3361 20:11:28.264467
3362 20:11:28.264564 TX Vref Scan disable
3363 20:11:28.268079 == TX Byte 0 ==
3364 20:11:28.271246 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3365 20:11:28.275041 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3366 20:11:28.277729 == TX Byte 1 ==
3367 20:11:28.281133 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3368 20:11:28.285262 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3369 20:11:28.287538 ==
3370 20:11:28.287619 Dram Type= 6, Freq= 0, CH_1, rank 1
3371 20:11:28.294322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3372 20:11:28.294403 ==
3373 20:11:28.305729 TX Vref=22, minBit 0, minWin=25, winSum=424
3374 20:11:28.308418 TX Vref=24, minBit 8, minWin=25, winSum=424
3375 20:11:28.312487 TX Vref=26, minBit 3, minWin=26, winSum=429
3376 20:11:28.315360 TX Vref=28, minBit 8, minWin=26, winSum=432
3377 20:11:28.318919 TX Vref=30, minBit 8, minWin=26, winSum=431
3378 20:11:28.321984 TX Vref=32, minBit 3, minWin=26, winSum=432
3379 20:11:28.328497 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3380 20:11:28.328580
3381 20:11:28.331664 Final TX Range 1 Vref 28
3382 20:11:28.331745
3383 20:11:28.331809 ==
3384 20:11:28.336032 Dram Type= 6, Freq= 0, CH_1, rank 1
3385 20:11:28.338374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3386 20:11:28.338455 ==
3387 20:11:28.338519
3388 20:11:28.342751
3389 20:11:28.342855 TX Vref Scan disable
3390 20:11:28.346014 == TX Byte 0 ==
3391 20:11:28.348629 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3392 20:11:28.351781 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3393 20:11:28.355220 == TX Byte 1 ==
3394 20:11:28.359130 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3395 20:11:28.361765 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3396 20:11:28.361846
3397 20:11:28.365372 [DATLAT]
3398 20:11:28.365452 Freq=1200, CH1 RK1
3399 20:11:28.365516
3400 20:11:28.368360 DATLAT Default: 0xc
3401 20:11:28.368441 0, 0xFFFF, sum = 0
3402 20:11:28.372046 1, 0xFFFF, sum = 0
3403 20:11:28.372128 2, 0xFFFF, sum = 0
3404 20:11:28.375460 3, 0xFFFF, sum = 0
3405 20:11:28.378677 4, 0xFFFF, sum = 0
3406 20:11:28.378759 5, 0xFFFF, sum = 0
3407 20:11:28.381970 6, 0xFFFF, sum = 0
3408 20:11:28.382051 7, 0xFFFF, sum = 0
3409 20:11:28.385502 8, 0xFFFF, sum = 0
3410 20:11:28.385584 9, 0xFFFF, sum = 0
3411 20:11:28.388749 10, 0xFFFF, sum = 0
3412 20:11:28.388831 11, 0x0, sum = 1
3413 20:11:28.391699 12, 0x0, sum = 2
3414 20:11:28.391780 13, 0x0, sum = 3
3415 20:11:28.394715 14, 0x0, sum = 4
3416 20:11:28.394797 best_step = 12
3417 20:11:28.394861
3418 20:11:28.394920 ==
3419 20:11:28.398173 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 20:11:28.401666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 20:11:28.401747 ==
3422 20:11:28.404744 RX Vref Scan: 0
3423 20:11:28.404826
3424 20:11:28.408667 RX Vref 0 -> 0, step: 1
3425 20:11:28.408773
3426 20:11:28.408838 RX Delay -29 -> 252, step: 4
3427 20:11:28.415799 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3428 20:11:28.419098 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3429 20:11:28.422095 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3430 20:11:28.425420 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3431 20:11:28.428678 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3432 20:11:28.435453 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3433 20:11:28.439004 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3434 20:11:28.442184 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3435 20:11:28.446002 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3436 20:11:28.449281 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3437 20:11:28.455337 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3438 20:11:28.459392 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3439 20:11:28.462108 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3440 20:11:28.465976 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3441 20:11:28.469403 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3442 20:11:28.475679 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3443 20:11:28.475761 ==
3444 20:11:28.480064 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 20:11:28.482454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3446 20:11:28.482536 ==
3447 20:11:28.482601 DQS Delay:
3448 20:11:28.485571 DQS0 = 0, DQS1 = 0
3449 20:11:28.485652 DQM Delay:
3450 20:11:28.488629 DQM0 = 114, DQM1 = 103
3451 20:11:28.488731 DQ Delay:
3452 20:11:28.492246 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3453 20:11:28.495602 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3454 20:11:28.499497 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3455 20:11:28.502392 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3456 20:11:28.502473
3457 20:11:28.502536
3458 20:11:28.512052 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3459 20:11:28.515282 CH1 RK1: MR19=404, MR18=707
3460 20:11:28.518986 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3461 20:11:28.521960 [RxdqsGatingPostProcess] freq 1200
3462 20:11:28.529119 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3463 20:11:28.532401 Pre-setting of DQS Precalculation
3464 20:11:28.535606 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3465 20:11:28.546156 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3466 20:11:28.552109 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3467 20:11:28.552190
3468 20:11:28.552254
3469 20:11:28.555594 [Calibration Summary] 2400 Mbps
3470 20:11:28.555675 CH 0, Rank 0
3471 20:11:28.559046 SW Impedance : PASS
3472 20:11:28.559127 DUTY Scan : NO K
3473 20:11:28.562334 ZQ Calibration : PASS
3474 20:11:28.565278 Jitter Meter : NO K
3475 20:11:28.565359 CBT Training : PASS
3476 20:11:28.569361 Write leveling : PASS
3477 20:11:28.572166 RX DQS gating : PASS
3478 20:11:28.572246 RX DQ/DQS(RDDQC) : PASS
3479 20:11:28.575359 TX DQ/DQS : PASS
3480 20:11:28.575439 RX DATLAT : PASS
3481 20:11:28.579214 RX DQ/DQS(Engine): PASS
3482 20:11:28.582538 TX OE : NO K
3483 20:11:28.582619 All Pass.
3484 20:11:28.582683
3485 20:11:28.582742 CH 0, Rank 1
3486 20:11:28.585419 SW Impedance : PASS
3487 20:11:28.589317 DUTY Scan : NO K
3488 20:11:28.589397 ZQ Calibration : PASS
3489 20:11:28.592587 Jitter Meter : NO K
3490 20:11:28.595686 CBT Training : PASS
3491 20:11:28.595766 Write leveling : PASS
3492 20:11:28.599366 RX DQS gating : PASS
3493 20:11:28.601860 RX DQ/DQS(RDDQC) : PASS
3494 20:11:28.601940 TX DQ/DQS : PASS
3495 20:11:28.605340 RX DATLAT : PASS
3496 20:11:28.608902 RX DQ/DQS(Engine): PASS
3497 20:11:28.608983 TX OE : NO K
3498 20:11:28.612129 All Pass.
3499 20:11:28.612209
3500 20:11:28.612272 CH 1, Rank 0
3501 20:11:28.615127 SW Impedance : PASS
3502 20:11:28.615208 DUTY Scan : NO K
3503 20:11:28.618585 ZQ Calibration : PASS
3504 20:11:28.622363 Jitter Meter : NO K
3505 20:11:28.622444 CBT Training : PASS
3506 20:11:28.625585 Write leveling : PASS
3507 20:11:28.625666 RX DQS gating : PASS
3508 20:11:28.629001 RX DQ/DQS(RDDQC) : PASS
3509 20:11:28.632229 TX DQ/DQS : PASS
3510 20:11:28.632309 RX DATLAT : PASS
3511 20:11:28.635889 RX DQ/DQS(Engine): PASS
3512 20:11:28.639268 TX OE : NO K
3513 20:11:28.639350 All Pass.
3514 20:11:28.639413
3515 20:11:28.639473 CH 1, Rank 1
3516 20:11:28.642074 SW Impedance : PASS
3517 20:11:28.645576 DUTY Scan : NO K
3518 20:11:28.645657 ZQ Calibration : PASS
3519 20:11:28.649132 Jitter Meter : NO K
3520 20:11:28.652561 CBT Training : PASS
3521 20:11:28.652641 Write leveling : PASS
3522 20:11:28.655700 RX DQS gating : PASS
3523 20:11:28.658774 RX DQ/DQS(RDDQC) : PASS
3524 20:11:28.658854 TX DQ/DQS : PASS
3525 20:11:28.662045 RX DATLAT : PASS
3526 20:11:28.662126 RX DQ/DQS(Engine): PASS
3527 20:11:28.665668 TX OE : NO K
3528 20:11:28.665748 All Pass.
3529 20:11:28.665843
3530 20:11:28.669023 DramC Write-DBI off
3531 20:11:28.672353 PER_BANK_REFRESH: Hybrid Mode
3532 20:11:28.672434 TX_TRACKING: ON
3533 20:11:28.681942 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3534 20:11:28.685249 [FAST_K] Save calibration result to emmc
3535 20:11:28.688652 dramc_set_vcore_voltage set vcore to 650000
3536 20:11:28.692249 Read voltage for 600, 5
3537 20:11:28.692330 Vio18 = 0
3538 20:11:28.695144 Vcore = 650000
3539 20:11:28.695237 Vdram = 0
3540 20:11:28.695301 Vddq = 0
3541 20:11:28.695361 Vmddr = 0
3542 20:11:28.701934 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3543 20:11:28.705864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3544 20:11:28.709215 MEM_TYPE=3, freq_sel=19
3545 20:11:28.711924 sv_algorithm_assistance_LP4_1600
3546 20:11:28.715510 ============ PULL DRAM RESETB DOWN ============
3547 20:11:28.721874 ========== PULL DRAM RESETB DOWN end =========
3548 20:11:28.725203 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3549 20:11:28.729212 ===================================
3550 20:11:28.731619 LPDDR4 DRAM CONFIGURATION
3551 20:11:28.735220 ===================================
3552 20:11:28.735302 EX_ROW_EN[0] = 0x0
3553 20:11:28.738281 EX_ROW_EN[1] = 0x0
3554 20:11:28.738362 LP4Y_EN = 0x0
3555 20:11:28.741822 WORK_FSP = 0x0
3556 20:11:28.741903 WL = 0x2
3557 20:11:28.744863 RL = 0x2
3558 20:11:28.744944 BL = 0x2
3559 20:11:28.748593 RPST = 0x0
3560 20:11:28.751460 RD_PRE = 0x0
3561 20:11:28.751541 WR_PRE = 0x1
3562 20:11:28.754954 WR_PST = 0x0
3563 20:11:28.755035 DBI_WR = 0x0
3564 20:11:28.758101 DBI_RD = 0x0
3565 20:11:28.758181 OTF = 0x1
3566 20:11:28.761376 ===================================
3567 20:11:28.765539 ===================================
3568 20:11:28.768476 ANA top config
3569 20:11:28.771304 ===================================
3570 20:11:28.771384 DLL_ASYNC_EN = 0
3571 20:11:28.775375 ALL_SLAVE_EN = 1
3572 20:11:28.777996 NEW_RANK_MODE = 1
3573 20:11:28.781172 DLL_IDLE_MODE = 1
3574 20:11:28.781252 LP45_APHY_COMB_EN = 1
3575 20:11:28.784384 TX_ODT_DIS = 1
3576 20:11:28.788022 NEW_8X_MODE = 1
3577 20:11:28.791109 ===================================
3578 20:11:28.795447 ===================================
3579 20:11:28.798167 data_rate = 1200
3580 20:11:28.801057 CKR = 1
3581 20:11:28.804619 DQ_P2S_RATIO = 8
3582 20:11:28.807629 ===================================
3583 20:11:28.807711 CA_P2S_RATIO = 8
3584 20:11:28.811345 DQ_CA_OPEN = 0
3585 20:11:28.814502 DQ_SEMI_OPEN = 0
3586 20:11:28.817816 CA_SEMI_OPEN = 0
3587 20:11:28.821390 CA_FULL_RATE = 0
3588 20:11:28.821498 DQ_CKDIV4_EN = 1
3589 20:11:28.824641 CA_CKDIV4_EN = 1
3590 20:11:28.827595 CA_PREDIV_EN = 0
3591 20:11:28.830788 PH8_DLY = 0
3592 20:11:28.834307 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3593 20:11:28.837449 DQ_AAMCK_DIV = 4
3594 20:11:28.841117 CA_AAMCK_DIV = 4
3595 20:11:28.841199 CA_ADMCK_DIV = 4
3596 20:11:28.844412 DQ_TRACK_CA_EN = 0
3597 20:11:28.847998 CA_PICK = 600
3598 20:11:28.850835 CA_MCKIO = 600
3599 20:11:28.854461 MCKIO_SEMI = 0
3600 20:11:28.857238 PLL_FREQ = 2288
3601 20:11:28.860897 DQ_UI_PI_RATIO = 32
3602 20:11:28.860978 CA_UI_PI_RATIO = 0
3603 20:11:28.863940 ===================================
3604 20:11:28.867480 ===================================
3605 20:11:28.870639 memory_type:LPDDR4
3606 20:11:28.874062 GP_NUM : 10
3607 20:11:28.874143 SRAM_EN : 1
3608 20:11:28.877160 MD32_EN : 0
3609 20:11:28.880679 ===================================
3610 20:11:28.884244 [ANA_INIT] >>>>>>>>>>>>>>
3611 20:11:28.887060 <<<<<< [CONFIGURE PHASE]: ANA_TX
3612 20:11:28.890417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3613 20:11:28.893786 ===================================
3614 20:11:28.893867 data_rate = 1200,PCW = 0X5800
3615 20:11:28.896951 ===================================
3616 20:11:28.900283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3617 20:11:28.907342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3618 20:11:28.913498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3619 20:11:28.917072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3620 20:11:28.920581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3621 20:11:28.923369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3622 20:11:28.926979 [ANA_INIT] flow start
3623 20:11:28.929993 [ANA_INIT] PLL >>>>>>>>
3624 20:11:28.930074 [ANA_INIT] PLL <<<<<<<<
3625 20:11:28.933626 [ANA_INIT] MIDPI >>>>>>>>
3626 20:11:28.936958 [ANA_INIT] MIDPI <<<<<<<<
3627 20:11:28.937039 [ANA_INIT] DLL >>>>>>>>
3628 20:11:28.939991 [ANA_INIT] flow end
3629 20:11:28.942948 ============ LP4 DIFF to SE enter ============
3630 20:11:28.950759 ============ LP4 DIFF to SE exit ============
3631 20:11:28.950841 [ANA_INIT] <<<<<<<<<<<<<
3632 20:11:28.953141 [Flow] Enable top DCM control >>>>>
3633 20:11:28.956642 [Flow] Enable top DCM control <<<<<
3634 20:11:28.960480 Enable DLL master slave shuffle
3635 20:11:28.966056 ==============================================================
3636 20:11:28.966138 Gating Mode config
3637 20:11:28.974013 ==============================================================
3638 20:11:28.976484 Config description:
3639 20:11:28.982775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3640 20:11:28.989482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3641 20:11:28.996054 SELPH_MODE 0: By rank 1: By Phase
3642 20:11:29.003024 ==============================================================
3643 20:11:29.005897 GAT_TRACK_EN = 1
3644 20:11:29.005978 RX_GATING_MODE = 2
3645 20:11:29.010148 RX_GATING_TRACK_MODE = 2
3646 20:11:29.012927 SELPH_MODE = 1
3647 20:11:29.016153 PICG_EARLY_EN = 1
3648 20:11:29.019232 VALID_LAT_VALUE = 1
3649 20:11:29.026234 ==============================================================
3650 20:11:29.029318 Enter into Gating configuration >>>>
3651 20:11:29.032469 Exit from Gating configuration <<<<
3652 20:11:29.035514 Enter into DVFS_PRE_config >>>>>
3653 20:11:29.045412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3654 20:11:29.049009 Exit from DVFS_PRE_config <<<<<
3655 20:11:29.051873 Enter into PICG configuration >>>>
3656 20:11:29.055246 Exit from PICG configuration <<<<
3657 20:11:29.059170 [RX_INPUT] configuration >>>>>
3658 20:11:29.061979 [RX_INPUT] configuration <<<<<
3659 20:11:29.065857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3660 20:11:29.072050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3661 20:11:29.078588 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3662 20:11:29.085180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3663 20:11:29.088610 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3664 20:11:29.094957 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3665 20:11:29.098328 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3666 20:11:29.104837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3667 20:11:29.108854 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3668 20:11:29.111830 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3669 20:11:29.115010 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3670 20:11:29.121582 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3671 20:11:29.125314 ===================================
3672 20:11:29.128349 LPDDR4 DRAM CONFIGURATION
3673 20:11:29.131604 ===================================
3674 20:11:29.131685 EX_ROW_EN[0] = 0x0
3675 20:11:29.135150 EX_ROW_EN[1] = 0x0
3676 20:11:29.135231 LP4Y_EN = 0x0
3677 20:11:29.137913 WORK_FSP = 0x0
3678 20:11:29.137994 WL = 0x2
3679 20:11:29.141072 RL = 0x2
3680 20:11:29.141153 BL = 0x2
3681 20:11:29.145094 RPST = 0x0
3682 20:11:29.145174 RD_PRE = 0x0
3683 20:11:29.148157 WR_PRE = 0x1
3684 20:11:29.148238 WR_PST = 0x0
3685 20:11:29.151478 DBI_WR = 0x0
3686 20:11:29.151584 DBI_RD = 0x0
3687 20:11:29.154624 OTF = 0x1
3688 20:11:29.157729 ===================================
3689 20:11:29.161010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3690 20:11:29.164085 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3691 20:11:29.171021 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3692 20:11:29.174320 ===================================
3693 20:11:29.177887 LPDDR4 DRAM CONFIGURATION
3694 20:11:29.181327 ===================================
3695 20:11:29.181409 EX_ROW_EN[0] = 0x10
3696 20:11:29.184496 EX_ROW_EN[1] = 0x0
3697 20:11:29.184576 LP4Y_EN = 0x0
3698 20:11:29.188154 WORK_FSP = 0x0
3699 20:11:29.188234 WL = 0x2
3700 20:11:29.191551 RL = 0x2
3701 20:11:29.191657 BL = 0x2
3702 20:11:29.194036 RPST = 0x0
3703 20:11:29.194117 RD_PRE = 0x0
3704 20:11:29.197272 WR_PRE = 0x1
3705 20:11:29.197352 WR_PST = 0x0
3706 20:11:29.200892 DBI_WR = 0x0
3707 20:11:29.200972 DBI_RD = 0x0
3708 20:11:29.204088 OTF = 0x1
3709 20:11:29.207506 ===================================
3710 20:11:29.213633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3711 20:11:29.218370 nWR fixed to 30
3712 20:11:29.220514 [ModeRegInit_LP4] CH0 RK0
3713 20:11:29.220595 [ModeRegInit_LP4] CH0 RK1
3714 20:11:29.224132 [ModeRegInit_LP4] CH1 RK0
3715 20:11:29.227107 [ModeRegInit_LP4] CH1 RK1
3716 20:11:29.227188 match AC timing 16
3717 20:11:29.233606 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3718 20:11:29.237560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3719 20:11:29.240674 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3720 20:11:29.246915 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3721 20:11:29.250427 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3722 20:11:29.250508 ==
3723 20:11:29.254332 Dram Type= 6, Freq= 0, CH_0, rank 0
3724 20:11:29.257911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3725 20:11:29.257993 ==
3726 20:11:29.263366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3727 20:11:29.270691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3728 20:11:29.273478 [CA 0] Center 35 (5~66) winsize 62
3729 20:11:29.276667 [CA 1] Center 35 (5~66) winsize 62
3730 20:11:29.280445 [CA 2] Center 34 (4~65) winsize 62
3731 20:11:29.283383 [CA 3] Center 34 (4~65) winsize 62
3732 20:11:29.286478 [CA 4] Center 33 (3~64) winsize 62
3733 20:11:29.290784 [CA 5] Center 33 (3~64) winsize 62
3734 20:11:29.290865
3735 20:11:29.293421 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3736 20:11:29.293504
3737 20:11:29.296737 [CATrainingPosCal] consider 1 rank data
3738 20:11:29.299757 u2DelayCellTimex100 = 270/100 ps
3739 20:11:29.303510 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3740 20:11:29.306340 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3741 20:11:29.310381 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3742 20:11:29.313627 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3743 20:11:29.319714 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3744 20:11:29.323094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3745 20:11:29.323175
3746 20:11:29.326752 CA PerBit enable=1, Macro0, CA PI delay=33
3747 20:11:29.326834
3748 20:11:29.330009 [CBTSetCACLKResult] CA Dly = 33
3749 20:11:29.330091 CS Dly: 5 (0~36)
3750 20:11:29.330154 ==
3751 20:11:29.333626 Dram Type= 6, Freq= 0, CH_0, rank 1
3752 20:11:29.339195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3753 20:11:29.339276 ==
3754 20:11:29.343034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3755 20:11:29.349275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3756 20:11:29.352688 [CA 0] Center 36 (6~66) winsize 61
3757 20:11:29.356093 [CA 1] Center 35 (5~66) winsize 62
3758 20:11:29.359485 [CA 2] Center 34 (4~65) winsize 62
3759 20:11:29.362466 [CA 3] Center 34 (4~65) winsize 62
3760 20:11:29.365956 [CA 4] Center 33 (3~64) winsize 62
3761 20:11:29.369093 [CA 5] Center 33 (3~64) winsize 62
3762 20:11:29.369195
3763 20:11:29.372787 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3764 20:11:29.372868
3765 20:11:29.376354 [CATrainingPosCal] consider 2 rank data
3766 20:11:29.378820 u2DelayCellTimex100 = 270/100 ps
3767 20:11:29.382468 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3768 20:11:29.389094 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3769 20:11:29.392377 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3770 20:11:29.395533 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3771 20:11:29.398933 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3772 20:11:29.402048 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3773 20:11:29.402129
3774 20:11:29.405536 CA PerBit enable=1, Macro0, CA PI delay=33
3775 20:11:29.405617
3776 20:11:29.408637 [CBTSetCACLKResult] CA Dly = 33
3777 20:11:29.412377 CS Dly: 4 (0~35)
3778 20:11:29.412458
3779 20:11:29.415428 ----->DramcWriteLeveling(PI) begin...
3780 20:11:29.415511 ==
3781 20:11:29.418730 Dram Type= 6, Freq= 0, CH_0, rank 0
3782 20:11:29.421861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3783 20:11:29.421942 ==
3784 20:11:29.425450 Write leveling (Byte 0): 30 => 30
3785 20:11:29.428690 Write leveling (Byte 1): 30 => 30
3786 20:11:29.431673 DramcWriteLeveling(PI) end<-----
3787 20:11:29.431793
3788 20:11:29.431886 ==
3789 20:11:29.434967 Dram Type= 6, Freq= 0, CH_0, rank 0
3790 20:11:29.438152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3791 20:11:29.438233 ==
3792 20:11:29.441978 [Gating] SW mode calibration
3793 20:11:29.448614 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3794 20:11:29.455324 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3795 20:11:29.458712 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3796 20:11:29.462012 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3797 20:11:29.468303 0 5 8 | B1->B0 | 3333 2f2f | 0 0 | (1 0) (0 0)
3798 20:11:29.471845 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3799 20:11:29.474682 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 20:11:29.481504 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 20:11:29.484937 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 20:11:29.488147 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 20:11:29.494948 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 20:11:29.498314 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 20:11:29.501811 0 6 8 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 0)
3806 20:11:29.508259 0 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3807 20:11:29.511533 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 20:11:29.515101 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 20:11:29.521481 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 20:11:29.524783 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 20:11:29.528214 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 20:11:29.535132 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 20:11:29.538409 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3814 20:11:29.541188 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 20:11:29.548140 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 20:11:29.550930 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 20:11:29.554112 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 20:11:29.560935 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 20:11:29.564168 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 20:11:29.567872 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 20:11:29.574727 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 20:11:29.577956 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 20:11:29.580881 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 20:11:29.587450 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 20:11:29.590771 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 20:11:29.593847 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 20:11:29.600683 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 20:11:29.604100 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 20:11:29.607573 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3830 20:11:29.613937 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3831 20:11:29.614018 Total UI for P1: 0, mck2ui 16
3832 20:11:29.617408 best dqsien dly found for B0: ( 0, 9, 10)
3833 20:11:29.620594 Total UI for P1: 0, mck2ui 16
3834 20:11:29.623853 best dqsien dly found for B1: ( 0, 9, 8)
3835 20:11:29.627313 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3836 20:11:29.633726 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3837 20:11:29.633808
3838 20:11:29.637036 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3839 20:11:29.640746 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3840 20:11:29.643598 [Gating] SW calibration Done
3841 20:11:29.643678 ==
3842 20:11:29.647090 Dram Type= 6, Freq= 0, CH_0, rank 0
3843 20:11:29.650282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3844 20:11:29.650362 ==
3845 20:11:29.653483 RX Vref Scan: 0
3846 20:11:29.653563
3847 20:11:29.653627 RX Vref 0 -> 0, step: 1
3848 20:11:29.653688
3849 20:11:29.656909 RX Delay -230 -> 252, step: 16
3850 20:11:29.660238 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3851 20:11:29.666712 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3852 20:11:29.669958 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3853 20:11:29.673627 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3854 20:11:29.676619 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3855 20:11:29.680230 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3856 20:11:29.686674 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3857 20:11:29.689850 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3858 20:11:29.693503 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3859 20:11:29.696648 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3860 20:11:29.703695 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3861 20:11:29.707120 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3862 20:11:29.709917 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3863 20:11:29.713601 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3864 20:11:29.720185 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3865 20:11:29.723582 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3866 20:11:29.723662 ==
3867 20:11:29.726489 Dram Type= 6, Freq= 0, CH_0, rank 0
3868 20:11:29.729921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3869 20:11:29.730002 ==
3870 20:11:29.733107 DQS Delay:
3871 20:11:29.733187 DQS0 = 0, DQS1 = 0
3872 20:11:29.733252 DQM Delay:
3873 20:11:29.736889 DQM0 = 40, DQM1 = 33
3874 20:11:29.736970 DQ Delay:
3875 20:11:29.740621 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
3876 20:11:29.742996 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3877 20:11:29.746579 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3878 20:11:29.749888 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3879 20:11:29.749969
3880 20:11:29.750032
3881 20:11:29.750092 ==
3882 20:11:29.753081 Dram Type= 6, Freq= 0, CH_0, rank 0
3883 20:11:29.759178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3884 20:11:29.759259 ==
3885 20:11:29.759323
3886 20:11:29.759382
3887 20:11:29.759438 TX Vref Scan disable
3888 20:11:29.763063 == TX Byte 0 ==
3889 20:11:29.766428 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3890 20:11:29.774280 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3891 20:11:29.774362 == TX Byte 1 ==
3892 20:11:29.777709 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3893 20:11:29.783480 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3894 20:11:29.783561 ==
3895 20:11:29.786739 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 20:11:29.789623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3897 20:11:29.789704 ==
3898 20:11:29.789768
3899 20:11:29.789827
3900 20:11:29.793182 TX Vref Scan disable
3901 20:11:29.796648 == TX Byte 0 ==
3902 20:11:29.799422 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3903 20:11:29.803487 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3904 20:11:29.806913 == TX Byte 1 ==
3905 20:11:29.810218 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3906 20:11:29.812941 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3907 20:11:29.813023
3908 20:11:29.813087 [DATLAT]
3909 20:11:29.816468 Freq=600, CH0 RK0
3910 20:11:29.816549
3911 20:11:29.816612 DATLAT Default: 0x9
3912 20:11:29.819486 0, 0xFFFF, sum = 0
3913 20:11:29.819569 1, 0xFFFF, sum = 0
3914 20:11:29.823049 2, 0xFFFF, sum = 0
3915 20:11:29.826872 3, 0xFFFF, sum = 0
3916 20:11:29.826954 4, 0xFFFF, sum = 0
3917 20:11:29.829779 5, 0xFFFF, sum = 0
3918 20:11:29.829862 6, 0xFFFF, sum = 0
3919 20:11:29.832785 7, 0x0, sum = 1
3920 20:11:29.832867 8, 0x0, sum = 2
3921 20:11:29.832932 9, 0x0, sum = 3
3922 20:11:29.836432 10, 0x0, sum = 4
3923 20:11:29.836515 best_step = 8
3924 20:11:29.836578
3925 20:11:29.836638 ==
3926 20:11:29.839724 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 20:11:29.846277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3928 20:11:29.846358 ==
3929 20:11:29.846422 RX Vref Scan: 1
3930 20:11:29.846481
3931 20:11:29.849445 RX Vref 0 -> 0, step: 1
3932 20:11:29.849528
3933 20:11:29.852926 RX Delay -195 -> 252, step: 8
3934 20:11:29.853006
3935 20:11:29.856726 Set Vref, RX VrefLevel [Byte0]: 47
3936 20:11:29.859364 [Byte1]: 46
3937 20:11:29.859445
3938 20:11:29.862591 Final RX Vref Byte 0 = 47 to rank0
3939 20:11:29.866303 Final RX Vref Byte 1 = 46 to rank0
3940 20:11:29.869313 Final RX Vref Byte 0 = 47 to rank1
3941 20:11:29.873009 Final RX Vref Byte 1 = 46 to rank1==
3942 20:11:29.875729 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 20:11:29.879692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 20:11:29.879773 ==
3945 20:11:29.882879 DQS Delay:
3946 20:11:29.882959 DQS0 = 0, DQS1 = 0
3947 20:11:29.885692 DQM Delay:
3948 20:11:29.885772 DQM0 = 40, DQM1 = 31
3949 20:11:29.885835 DQ Delay:
3950 20:11:29.888958 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3951 20:11:29.892469 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
3952 20:11:29.896609 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
3953 20:11:29.899067 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =44
3954 20:11:29.899147
3955 20:11:29.899210
3956 20:11:29.909058 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3957 20:11:29.912336 CH0 RK0: MR19=808, MR18=5A5A
3958 20:11:29.919013 CH0_RK0: MR19=0x808, MR18=0x5A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
3959 20:11:29.919094
3960 20:11:29.922177 ----->DramcWriteLeveling(PI) begin...
3961 20:11:29.922259 ==
3962 20:11:29.926280 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 20:11:29.928939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 20:11:29.929036 ==
3965 20:11:29.932435 Write leveling (Byte 0): 29 => 29
3966 20:11:29.935543 Write leveling (Byte 1): 30 => 30
3967 20:11:29.938837 DramcWriteLeveling(PI) end<-----
3968 20:11:29.938917
3969 20:11:29.938981 ==
3970 20:11:29.942465 Dram Type= 6, Freq= 0, CH_0, rank 1
3971 20:11:29.946248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3972 20:11:29.946329 ==
3973 20:11:29.949390 [Gating] SW mode calibration
3974 20:11:29.955403 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 20:11:29.962031 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3976 20:11:29.965365 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 20:11:29.968934 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 20:11:29.975285 0 5 8 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
3979 20:11:29.978829 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3980 20:11:29.982427 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 20:11:29.988821 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 20:11:29.991564 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 20:11:29.995042 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 20:11:30.002203 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 20:11:30.004923 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 20:11:30.008757 0 6 8 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0)
3987 20:11:30.014652 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3988 20:11:30.017930 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 20:11:30.021442 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 20:11:30.027890 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 20:11:30.031389 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 20:11:30.034593 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 20:11:30.041622 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 20:11:30.044217 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3995 20:11:30.048037 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3996 20:11:30.054585 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 20:11:30.057826 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 20:11:30.061528 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 20:11:30.067635 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 20:11:30.070674 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 20:11:30.074510 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 20:11:30.080437 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 20:11:30.084087 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 20:11:30.087240 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 20:11:30.094535 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 20:11:30.097068 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 20:11:30.100690 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 20:11:30.107146 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 20:11:30.110857 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 20:11:30.114066 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4011 20:11:30.120813 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 20:11:30.120894 Total UI for P1: 0, mck2ui 16
4013 20:11:30.127664 best dqsien dly found for B0: ( 0, 9, 8)
4014 20:11:30.127745 Total UI for P1: 0, mck2ui 16
4015 20:11:30.133656 best dqsien dly found for B1: ( 0, 9, 8)
4016 20:11:30.137195 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4017 20:11:30.140395 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4018 20:11:30.140506
4019 20:11:30.143551 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4020 20:11:30.147062 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4021 20:11:30.150259 [Gating] SW calibration Done
4022 20:11:30.150340 ==
4023 20:11:30.153713 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 20:11:30.156898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 20:11:30.156980 ==
4026 20:11:30.160682 RX Vref Scan: 0
4027 20:11:30.160804
4028 20:11:30.160870 RX Vref 0 -> 0, step: 1
4029 20:11:30.160931
4030 20:11:30.163493 RX Delay -230 -> 252, step: 16
4031 20:11:30.166791 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4032 20:11:30.173729 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4033 20:11:30.177337 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4034 20:11:30.179893 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4035 20:11:30.183873 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4036 20:11:30.189859 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4037 20:11:30.193621 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4038 20:11:30.196558 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4039 20:11:30.200230 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4040 20:11:30.203627 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4041 20:11:30.209752 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4042 20:11:30.213103 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4043 20:11:30.216835 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4044 20:11:30.219573 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4045 20:11:30.226708 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4046 20:11:30.230060 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4047 20:11:30.230141 ==
4048 20:11:30.232644 Dram Type= 6, Freq= 0, CH_0, rank 1
4049 20:11:30.236200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4050 20:11:30.236282 ==
4051 20:11:30.239694 DQS Delay:
4052 20:11:30.239775 DQS0 = 0, DQS1 = 0
4053 20:11:30.242959 DQM Delay:
4054 20:11:30.243039 DQM0 = 42, DQM1 = 33
4055 20:11:30.243102 DQ Delay:
4056 20:11:30.246018 DQ0 =33, DQ1 =49, DQ2 =41, DQ3 =33
4057 20:11:30.250041 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4058 20:11:30.253021 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4059 20:11:30.255960 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4060 20:11:30.256040
4061 20:11:30.256103
4062 20:11:30.259965 ==
4063 20:11:30.260045 Dram Type= 6, Freq= 0, CH_0, rank 1
4064 20:11:30.266176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4065 20:11:30.266257 ==
4066 20:11:30.266322
4067 20:11:30.266382
4068 20:11:30.269548 TX Vref Scan disable
4069 20:11:30.269633 == TX Byte 0 ==
4070 20:11:30.272684 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4071 20:11:30.279396 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4072 20:11:30.279474 == TX Byte 1 ==
4073 20:11:30.282911 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4074 20:11:30.288966 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4075 20:11:30.289045 ==
4076 20:11:30.292667 Dram Type= 6, Freq= 0, CH_0, rank 1
4077 20:11:30.295829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4078 20:11:30.295909 ==
4079 20:11:30.295972
4080 20:11:30.296030
4081 20:11:30.299481 TX Vref Scan disable
4082 20:11:30.302551 == TX Byte 0 ==
4083 20:11:30.306137 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4084 20:11:30.309225 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4085 20:11:30.312647 == TX Byte 1 ==
4086 20:11:30.316235 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4087 20:11:30.319470 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4088 20:11:30.319550
4089 20:11:30.322567 [DATLAT]
4090 20:11:30.322654 Freq=600, CH0 RK1
4091 20:11:30.322717
4092 20:11:30.326238 DATLAT Default: 0x8
4093 20:11:30.326317 0, 0xFFFF, sum = 0
4094 20:11:30.329513 1, 0xFFFF, sum = 0
4095 20:11:30.329594 2, 0xFFFF, sum = 0
4096 20:11:30.332300 3, 0xFFFF, sum = 0
4097 20:11:30.332381 4, 0xFFFF, sum = 0
4098 20:11:30.335660 5, 0xFFFF, sum = 0
4099 20:11:30.335741 6, 0xFFFF, sum = 0
4100 20:11:30.339186 7, 0x0, sum = 1
4101 20:11:30.339266 8, 0x0, sum = 2
4102 20:11:30.343298 9, 0x0, sum = 3
4103 20:11:30.343379 10, 0x0, sum = 4
4104 20:11:30.343442 best_step = 8
4105 20:11:30.346231
4106 20:11:30.346310 ==
4107 20:11:30.349383 Dram Type= 6, Freq= 0, CH_0, rank 1
4108 20:11:30.352095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4109 20:11:30.352174 ==
4110 20:11:30.352237 RX Vref Scan: 0
4111 20:11:30.352295
4112 20:11:30.356073 RX Vref 0 -> 0, step: 1
4113 20:11:30.356152
4114 20:11:30.359078 RX Delay -179 -> 252, step: 8
4115 20:11:30.365423 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4116 20:11:30.368795 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4117 20:11:30.372031 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4118 20:11:30.376723 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4119 20:11:30.382012 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4120 20:11:30.385692 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4121 20:11:30.388948 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4122 20:11:30.392121 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4123 20:11:30.395525 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4124 20:11:30.401920 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4125 20:11:30.405165 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4126 20:11:30.408570 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4127 20:11:30.411933 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4128 20:11:30.418706 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4129 20:11:30.422602 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4130 20:11:30.425941 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4131 20:11:30.426020 ==
4132 20:11:30.428925 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 20:11:30.432056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4134 20:11:30.435605 ==
4135 20:11:30.435684 DQS Delay:
4136 20:11:30.435747 DQS0 = 0, DQS1 = 0
4137 20:11:30.438302 DQM Delay:
4138 20:11:30.438381 DQM0 = 41, DQM1 = 32
4139 20:11:30.442491 DQ Delay:
4140 20:11:30.442569 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4141 20:11:30.445704 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4142 20:11:30.448276 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4143 20:11:30.452117 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4144 20:11:30.452196
4145 20:11:30.455320
4146 20:11:30.461714 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4147 20:11:30.465620 CH0 RK1: MR19=808, MR18=6565
4148 20:11:30.471763 CH0_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4149 20:11:30.474991 [RxdqsGatingPostProcess] freq 600
4150 20:11:30.478864 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4151 20:11:30.481776 Pre-setting of DQS Precalculation
4152 20:11:30.488478 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4153 20:11:30.488551 ==
4154 20:11:30.491492 Dram Type= 6, Freq= 0, CH_1, rank 0
4155 20:11:30.494563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4156 20:11:30.494639 ==
4157 20:11:30.501517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4158 20:11:30.504647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4159 20:11:30.508968 [CA 0] Center 35 (5~66) winsize 62
4160 20:11:30.512293 [CA 1] Center 35 (5~66) winsize 62
4161 20:11:30.515153 [CA 2] Center 33 (3~64) winsize 62
4162 20:11:30.518870 [CA 3] Center 33 (3~64) winsize 62
4163 20:11:30.522122 [CA 4] Center 33 (2~64) winsize 63
4164 20:11:30.525664 [CA 5] Center 33 (2~64) winsize 63
4165 20:11:30.525745
4166 20:11:30.528314 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4167 20:11:30.528395
4168 20:11:30.532343 [CATrainingPosCal] consider 1 rank data
4169 20:11:30.535081 u2DelayCellTimex100 = 270/100 ps
4170 20:11:30.538983 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4171 20:11:30.545970 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4172 20:11:30.548348 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4173 20:11:30.551658 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4174 20:11:30.555596 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4175 20:11:30.558307 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4176 20:11:30.558387
4177 20:11:30.562105 CA PerBit enable=1, Macro0, CA PI delay=33
4178 20:11:30.562186
4179 20:11:30.565521 [CBTSetCACLKResult] CA Dly = 33
4180 20:11:30.568594 CS Dly: 4 (0~35)
4181 20:11:30.568674 ==
4182 20:11:30.571281 Dram Type= 6, Freq= 0, CH_1, rank 1
4183 20:11:30.575464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4184 20:11:30.575545 ==
4185 20:11:30.581272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4186 20:11:30.584857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4187 20:11:30.588628 [CA 0] Center 35 (4~66) winsize 63
4188 20:11:30.591867 [CA 1] Center 34 (4~65) winsize 62
4189 20:11:30.596089 [CA 2] Center 33 (3~64) winsize 62
4190 20:11:30.599069 [CA 3] Center 33 (3~64) winsize 62
4191 20:11:30.602207 [CA 4] Center 32 (2~63) winsize 62
4192 20:11:30.605748 [CA 5] Center 32 (2~63) winsize 62
4193 20:11:30.605840
4194 20:11:30.608750 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4195 20:11:30.608831
4196 20:11:30.612543 [CATrainingPosCal] consider 2 rank data
4197 20:11:30.615447 u2DelayCellTimex100 = 270/100 ps
4198 20:11:30.618567 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4199 20:11:30.625459 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4200 20:11:30.628385 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4201 20:11:30.632597 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4202 20:11:30.636502 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4203 20:11:30.638650 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4204 20:11:30.638731
4205 20:11:30.641862 CA PerBit enable=1, Macro0, CA PI delay=32
4206 20:11:30.641948
4207 20:11:30.645079 [CBTSetCACLKResult] CA Dly = 32
4208 20:11:30.645156 CS Dly: 4 (0~35)
4209 20:11:30.648135
4210 20:11:30.651610 ----->DramcWriteLeveling(PI) begin...
4211 20:11:30.651691 ==
4212 20:11:30.655077 Dram Type= 6, Freq= 0, CH_1, rank 0
4213 20:11:30.658284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4214 20:11:30.658354 ==
4215 20:11:30.661544 Write leveling (Byte 0): 28 => 28
4216 20:11:30.664967 Write leveling (Byte 1): 27 => 27
4217 20:11:30.668384 DramcWriteLeveling(PI) end<-----
4218 20:11:30.668454
4219 20:11:30.668514 ==
4220 20:11:30.671845 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 20:11:30.675494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 20:11:30.675591 ==
4223 20:11:30.678273 [Gating] SW mode calibration
4224 20:11:30.685580 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4225 20:11:30.691236 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4226 20:11:30.694709 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 20:11:30.698175 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4228 20:11:30.705039 0 5 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
4229 20:11:30.707917 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 20:11:30.711337 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 20:11:30.717929 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 20:11:30.721518 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 20:11:30.724824 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 20:11:30.731047 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 20:11:30.734525 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4236 20:11:30.738248 0 6 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4237 20:11:30.744299 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 20:11:30.748223 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 20:11:30.751125 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 20:11:30.757627 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 20:11:30.761658 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 20:11:30.764407 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 20:11:30.770798 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4244 20:11:30.774197 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 20:11:30.777410 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4246 20:11:30.780701 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 20:11:30.787314 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 20:11:30.790775 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 20:11:30.794086 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 20:11:30.801563 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 20:11:30.804249 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 20:11:30.807375 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 20:11:30.814003 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 20:11:30.817459 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 20:11:30.821011 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 20:11:30.827296 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 20:11:30.830208 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 20:11:30.833608 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 20:11:30.840234 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4260 20:11:30.844014 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 20:11:30.846976 Total UI for P1: 0, mck2ui 16
4262 20:11:30.850564 best dqsien dly found for B0: ( 0, 9, 4)
4263 20:11:30.854297 Total UI for P1: 0, mck2ui 16
4264 20:11:30.856672 best dqsien dly found for B1: ( 0, 9, 6)
4265 20:11:30.860405 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4266 20:11:30.863307 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4267 20:11:30.863390
4268 20:11:30.867310 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4269 20:11:30.870418 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4270 20:11:30.873937 [Gating] SW calibration Done
4271 20:11:30.874017 ==
4272 20:11:30.876905 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 20:11:30.883346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 20:11:30.883428 ==
4275 20:11:30.883493 RX Vref Scan: 0
4276 20:11:30.883555
4277 20:11:30.886530 RX Vref 0 -> 0, step: 1
4278 20:11:30.886611
4279 20:11:30.890301 RX Delay -230 -> 252, step: 16
4280 20:11:30.893637 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4281 20:11:30.896643 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4282 20:11:30.900319 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4283 20:11:30.907221 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4284 20:11:30.910216 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4285 20:11:30.913776 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4286 20:11:30.916226 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4287 20:11:30.919595 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4288 20:11:30.926723 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4289 20:11:30.929769 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4290 20:11:30.933030 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4291 20:11:30.936091 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4292 20:11:30.943284 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4293 20:11:30.946907 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4294 20:11:30.949391 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4295 20:11:30.952764 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4296 20:11:30.956175 ==
4297 20:11:30.956257 Dram Type= 6, Freq= 0, CH_1, rank 0
4298 20:11:30.963053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4299 20:11:30.963134 ==
4300 20:11:30.963197 DQS Delay:
4301 20:11:30.966135 DQS0 = 0, DQS1 = 0
4302 20:11:30.966215 DQM Delay:
4303 20:11:30.969477 DQM0 = 39, DQM1 = 32
4304 20:11:30.969556 DQ Delay:
4305 20:11:30.972823 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4306 20:11:30.976587 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4307 20:11:30.979413 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4308 20:11:30.982568 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4309 20:11:30.982648
4310 20:11:30.982710
4311 20:11:30.982768 ==
4312 20:11:30.986542 Dram Type= 6, Freq= 0, CH_1, rank 0
4313 20:11:30.989610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4314 20:11:30.989690 ==
4315 20:11:30.989753
4316 20:11:30.989812
4317 20:11:30.993071 TX Vref Scan disable
4318 20:11:30.995869 == TX Byte 0 ==
4319 20:11:30.999209 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4320 20:11:31.002536 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4321 20:11:31.006349 == TX Byte 1 ==
4322 20:11:31.009317 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4323 20:11:31.012883 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4324 20:11:31.012962 ==
4325 20:11:31.016022 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 20:11:31.019069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4327 20:11:31.022558 ==
4328 20:11:31.022638
4329 20:11:31.022700
4330 20:11:31.022758 TX Vref Scan disable
4331 20:11:31.026897 == TX Byte 0 ==
4332 20:11:31.029836 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4333 20:11:31.036842 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4334 20:11:31.036923 == TX Byte 1 ==
4335 20:11:31.040195 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4336 20:11:31.046794 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4337 20:11:31.046874
4338 20:11:31.046937 [DATLAT]
4339 20:11:31.046996 Freq=600, CH1 RK0
4340 20:11:31.047053
4341 20:11:31.049877 DATLAT Default: 0x9
4342 20:11:31.049957 0, 0xFFFF, sum = 0
4343 20:11:31.052801 1, 0xFFFF, sum = 0
4344 20:11:31.056152 2, 0xFFFF, sum = 0
4345 20:11:31.056233 3, 0xFFFF, sum = 0
4346 20:11:31.060098 4, 0xFFFF, sum = 0
4347 20:11:31.060179 5, 0xFFFF, sum = 0
4348 20:11:31.063253 6, 0xFFFF, sum = 0
4349 20:11:31.063334 7, 0x0, sum = 1
4350 20:11:31.063398 8, 0x0, sum = 2
4351 20:11:31.066309 9, 0x0, sum = 3
4352 20:11:31.066391 10, 0x0, sum = 4
4353 20:11:31.070128 best_step = 8
4354 20:11:31.070206
4355 20:11:31.070269 ==
4356 20:11:31.072627 Dram Type= 6, Freq= 0, CH_1, rank 0
4357 20:11:31.076613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4358 20:11:31.076693 ==
4359 20:11:31.079290 RX Vref Scan: 1
4360 20:11:31.079369
4361 20:11:31.079431 RX Vref 0 -> 0, step: 1
4362 20:11:31.079490
4363 20:11:31.083053 RX Delay -195 -> 252, step: 8
4364 20:11:31.083133
4365 20:11:31.086238 Set Vref, RX VrefLevel [Byte0]: 54
4366 20:11:31.089886 [Byte1]: 49
4367 20:11:31.094377
4368 20:11:31.094462 Final RX Vref Byte 0 = 54 to rank0
4369 20:11:31.096695 Final RX Vref Byte 1 = 49 to rank0
4370 20:11:31.100182 Final RX Vref Byte 0 = 54 to rank1
4371 20:11:31.103182 Final RX Vref Byte 1 = 49 to rank1==
4372 20:11:31.106962 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 20:11:31.113465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4374 20:11:31.113546 ==
4375 20:11:31.113609 DQS Delay:
4376 20:11:31.116757 DQS0 = 0, DQS1 = 0
4377 20:11:31.116837 DQM Delay:
4378 20:11:31.116901 DQM0 = 37, DQM1 = 30
4379 20:11:31.119903 DQ Delay:
4380 20:11:31.123035 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4381 20:11:31.126818 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4382 20:11:31.130106 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4383 20:11:31.133107 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4384 20:11:31.133187
4385 20:11:31.133250
4386 20:11:31.140001 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4387 20:11:31.142823 CH1 RK0: MR19=808, MR18=6E6E
4388 20:11:31.149732 CH1_RK0: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4389 20:11:31.149813
4390 20:11:31.153100 ----->DramcWriteLeveling(PI) begin...
4391 20:11:31.153181 ==
4392 20:11:31.156226 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 20:11:31.159598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 20:11:31.159679 ==
4395 20:11:31.163316 Write leveling (Byte 0): 30 => 30
4396 20:11:31.166359 Write leveling (Byte 1): 29 => 29
4397 20:11:31.169778 DramcWriteLeveling(PI) end<-----
4398 20:11:31.169858
4399 20:11:31.169921 ==
4400 20:11:31.172587 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 20:11:31.175947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4402 20:11:31.180083 ==
4403 20:11:31.180163 [Gating] SW mode calibration
4404 20:11:31.186460 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 20:11:31.192989 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4406 20:11:31.195844 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 20:11:31.202875 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4408 20:11:31.206359 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (1 1)
4409 20:11:31.209541 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 20:11:31.216145 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 20:11:31.219285 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 20:11:31.222711 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 20:11:31.229284 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 20:11:31.232427 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 20:11:31.235655 0 6 4 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
4416 20:11:31.242556 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4417 20:11:31.245712 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 20:11:31.248687 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 20:11:31.255919 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 20:11:31.258961 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 20:11:31.261858 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 20:11:31.268822 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 20:11:31.272264 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4424 20:11:31.275343 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 20:11:31.282207 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 20:11:31.285102 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 20:11:31.288376 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 20:11:31.294985 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 20:11:31.298153 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 20:11:31.302201 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 20:11:31.308626 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 20:11:31.311435 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 20:11:31.315146 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 20:11:31.321354 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 20:11:31.325157 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 20:11:31.327985 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 20:11:31.334577 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 20:11:31.338020 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 20:11:31.341766 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4440 20:11:31.344494 Total UI for P1: 0, mck2ui 16
4441 20:11:31.348385 best dqsien dly found for B0: ( 0, 9, 2)
4442 20:11:31.354915 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 20:11:31.355151 Total UI for P1: 0, mck2ui 16
4444 20:11:31.358060 best dqsien dly found for B1: ( 0, 9, 4)
4445 20:11:31.364956 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4446 20:11:31.368377 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4447 20:11:31.368882
4448 20:11:31.371671 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4449 20:11:31.375160 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4450 20:11:31.378060 [Gating] SW calibration Done
4451 20:11:31.378561 ==
4452 20:11:31.381788 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 20:11:31.385014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 20:11:31.385426 ==
4455 20:11:31.388264 RX Vref Scan: 0
4456 20:11:31.388738
4457 20:11:31.389071 RX Vref 0 -> 0, step: 1
4458 20:11:31.389373
4459 20:11:31.391675 RX Delay -230 -> 252, step: 16
4460 20:11:31.394760 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4461 20:11:31.401321 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4462 20:11:31.404817 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4463 20:11:31.407878 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4464 20:11:31.411009 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4465 20:11:31.417768 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4466 20:11:31.421488 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4467 20:11:31.424389 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4468 20:11:31.428316 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4469 20:11:31.430832 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4470 20:11:31.438171 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4471 20:11:31.440744 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4472 20:11:31.443898 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4473 20:11:31.447762 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4474 20:11:31.454547 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4475 20:11:31.457636 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4476 20:11:31.458043 ==
4477 20:11:31.460943 Dram Type= 6, Freq= 0, CH_1, rank 1
4478 20:11:31.463884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4479 20:11:31.464292 ==
4480 20:11:31.467519 DQS Delay:
4481 20:11:31.467924 DQS0 = 0, DQS1 = 0
4482 20:11:31.470257 DQM Delay:
4483 20:11:31.470667 DQM0 = 41, DQM1 = 34
4484 20:11:31.470991 DQ Delay:
4485 20:11:31.473834 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4486 20:11:31.477167 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4487 20:11:31.480387 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4488 20:11:31.483956 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4489 20:11:31.484389
4490 20:11:31.484772
4491 20:11:31.485087 ==
4492 20:11:31.487625 Dram Type= 6, Freq= 0, CH_1, rank 1
4493 20:11:31.493787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4494 20:11:31.494203 ==
4495 20:11:31.494532
4496 20:11:31.494840
4497 20:11:31.496757 TX Vref Scan disable
4498 20:11:31.497176 == TX Byte 0 ==
4499 20:11:31.500428 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 20:11:31.506852 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 20:11:31.507270 == TX Byte 1 ==
4502 20:11:31.510372 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4503 20:11:31.516778 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4504 20:11:31.517197 ==
4505 20:11:31.519927 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 20:11:31.523296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 20:11:31.523715 ==
4508 20:11:31.524048
4509 20:11:31.524516
4510 20:11:31.527208 TX Vref Scan disable
4511 20:11:31.530706 == TX Byte 0 ==
4512 20:11:31.534809 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 20:11:31.536885 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 20:11:31.540548 == TX Byte 1 ==
4515 20:11:31.543667 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 20:11:31.546575 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 20:11:31.546994
4518 20:11:31.550489 [DATLAT]
4519 20:11:31.550903 Freq=600, CH1 RK1
4520 20:11:31.551230
4521 20:11:31.553470 DATLAT Default: 0x8
4522 20:11:31.553888 0, 0xFFFF, sum = 0
4523 20:11:31.557105 1, 0xFFFF, sum = 0
4524 20:11:31.557523 2, 0xFFFF, sum = 0
4525 20:11:31.559930 3, 0xFFFF, sum = 0
4526 20:11:31.560350 4, 0xFFFF, sum = 0
4527 20:11:31.563416 5, 0xFFFF, sum = 0
4528 20:11:31.563841 6, 0xFFFF, sum = 0
4529 20:11:31.567204 7, 0x0, sum = 1
4530 20:11:31.567626 8, 0x0, sum = 2
4531 20:11:31.569593 9, 0x0, sum = 3
4532 20:11:31.570015 10, 0x0, sum = 4
4533 20:11:31.573615 best_step = 8
4534 20:11:31.574028
4535 20:11:31.574357 ==
4536 20:11:31.576440 Dram Type= 6, Freq= 0, CH_1, rank 1
4537 20:11:31.580158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4538 20:11:31.580577 ==
4539 20:11:31.580939 RX Vref Scan: 0
4540 20:11:31.583296
4541 20:11:31.583707 RX Vref 0 -> 0, step: 1
4542 20:11:31.584036
4543 20:11:31.586296 RX Delay -195 -> 252, step: 8
4544 20:11:31.592997 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4545 20:11:31.597753 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4546 20:11:31.599756 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4547 20:11:31.603085 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4548 20:11:31.609960 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4549 20:11:31.612694 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4550 20:11:31.615991 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4551 20:11:31.619475 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4552 20:11:31.626740 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4553 20:11:31.629472 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4554 20:11:31.632782 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4555 20:11:31.636426 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4556 20:11:31.640160 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4557 20:11:31.645898 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4558 20:11:31.649611 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4559 20:11:31.653191 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4560 20:11:31.653604 ==
4561 20:11:31.656469 Dram Type= 6, Freq= 0, CH_1, rank 1
4562 20:11:31.662907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4563 20:11:31.663327 ==
4564 20:11:31.663655 DQS Delay:
4565 20:11:31.663959 DQS0 = 0, DQS1 = 0
4566 20:11:31.665882 DQM Delay:
4567 20:11:31.666295 DQM0 = 37, DQM1 = 29
4568 20:11:31.669433 DQ Delay:
4569 20:11:31.672394 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4570 20:11:31.675701 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4571 20:11:31.679351 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4572 20:11:31.682478 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4573 20:11:31.682893
4574 20:11:31.683219
4575 20:11:31.688786 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4576 20:11:31.692088 CH1 RK1: MR19=808, MR18=5C5C
4577 20:11:31.698660 CH1_RK1: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4578 20:11:31.702880 [RxdqsGatingPostProcess] freq 600
4579 20:11:31.705377 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4580 20:11:31.709442 Pre-setting of DQS Precalculation
4581 20:11:31.715443 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4582 20:11:31.722368 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4583 20:11:31.728552 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4584 20:11:31.728999
4585 20:11:31.729364
4586 20:11:31.732004 [Calibration Summary] 1200 Mbps
4587 20:11:31.732425 CH 0, Rank 0
4588 20:11:31.735407 SW Impedance : PASS
4589 20:11:31.738433 DUTY Scan : NO K
4590 20:11:31.738841 ZQ Calibration : PASS
4591 20:11:31.742587 Jitter Meter : NO K
4592 20:11:31.745283 CBT Training : PASS
4593 20:11:31.745693 Write leveling : PASS
4594 20:11:31.748220 RX DQS gating : PASS
4595 20:11:31.751765 RX DQ/DQS(RDDQC) : PASS
4596 20:11:31.752182 TX DQ/DQS : PASS
4597 20:11:31.755369 RX DATLAT : PASS
4598 20:11:31.758203 RX DQ/DQS(Engine): PASS
4599 20:11:31.758618 TX OE : NO K
4600 20:11:31.761546 All Pass.
4601 20:11:31.761960
4602 20:11:31.762290 CH 0, Rank 1
4603 20:11:31.765095 SW Impedance : PASS
4604 20:11:31.765511 DUTY Scan : NO K
4605 20:11:31.768749 ZQ Calibration : PASS
4606 20:11:31.771575 Jitter Meter : NO K
4607 20:11:31.771990 CBT Training : PASS
4608 20:11:31.774846 Write leveling : PASS
4609 20:11:31.775260 RX DQS gating : PASS
4610 20:11:31.778192 RX DQ/DQS(RDDQC) : PASS
4611 20:11:31.781305 TX DQ/DQS : PASS
4612 20:11:31.781721 RX DATLAT : PASS
4613 20:11:31.784885 RX DQ/DQS(Engine): PASS
4614 20:11:31.787898 TX OE : NO K
4615 20:11:31.788315 All Pass.
4616 20:11:31.788646
4617 20:11:31.788990 CH 1, Rank 0
4618 20:11:31.792229 SW Impedance : PASS
4619 20:11:31.794488 DUTY Scan : NO K
4620 20:11:31.794901 ZQ Calibration : PASS
4621 20:11:31.798110 Jitter Meter : NO K
4622 20:11:31.801221 CBT Training : PASS
4623 20:11:31.801639 Write leveling : PASS
4624 20:11:31.804366 RX DQS gating : PASS
4625 20:11:31.808136 RX DQ/DQS(RDDQC) : PASS
4626 20:11:31.808552 TX DQ/DQS : PASS
4627 20:11:31.811316 RX DATLAT : PASS
4628 20:11:31.814431 RX DQ/DQS(Engine): PASS
4629 20:11:31.814845 TX OE : NO K
4630 20:11:31.818029 All Pass.
4631 20:11:31.818444
4632 20:11:31.818775 CH 1, Rank 1
4633 20:11:31.821430 SW Impedance : PASS
4634 20:11:31.821846 DUTY Scan : NO K
4635 20:11:31.824878 ZQ Calibration : PASS
4636 20:11:31.827944 Jitter Meter : NO K
4637 20:11:31.828440 CBT Training : PASS
4638 20:11:31.831609 Write leveling : PASS
4639 20:11:31.834369 RX DQS gating : PASS
4640 20:11:31.834782 RX DQ/DQS(RDDQC) : PASS
4641 20:11:31.838878 TX DQ/DQS : PASS
4642 20:11:31.839298 RX DATLAT : PASS
4643 20:11:31.841882 RX DQ/DQS(Engine): PASS
4644 20:11:31.844592 TX OE : NO K
4645 20:11:31.845056 All Pass.
4646 20:11:31.845415
4647 20:11:31.848852 DramC Write-DBI off
4648 20:11:31.849270 PER_BANK_REFRESH: Hybrid Mode
4649 20:11:31.850728 TX_TRACKING: ON
4650 20:11:31.860817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4651 20:11:31.864293 [FAST_K] Save calibration result to emmc
4652 20:11:31.867501 dramc_set_vcore_voltage set vcore to 662500
4653 20:11:31.867920 Read voltage for 933, 3
4654 20:11:31.871223 Vio18 = 0
4655 20:11:31.871776 Vcore = 662500
4656 20:11:31.872159 Vdram = 0
4657 20:11:31.874131 Vddq = 0
4658 20:11:31.874549 Vmddr = 0
4659 20:11:31.881247 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4660 20:11:31.884165 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4661 20:11:31.887562 MEM_TYPE=3, freq_sel=17
4662 20:11:31.891594 sv_algorithm_assistance_LP4_1600
4663 20:11:31.894489 ============ PULL DRAM RESETB DOWN ============
4664 20:11:31.897377 ========== PULL DRAM RESETB DOWN end =========
4665 20:11:31.903793 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4666 20:11:31.907157 ===================================
4667 20:11:31.907579 LPDDR4 DRAM CONFIGURATION
4668 20:11:31.910392 ===================================
4669 20:11:31.914121 EX_ROW_EN[0] = 0x0
4670 20:11:31.917085 EX_ROW_EN[1] = 0x0
4671 20:11:31.917503 LP4Y_EN = 0x0
4672 20:11:31.921029 WORK_FSP = 0x0
4673 20:11:31.921447 WL = 0x3
4674 20:11:31.924201 RL = 0x3
4675 20:11:31.924616 BL = 0x2
4676 20:11:31.926939 RPST = 0x0
4677 20:11:31.927353 RD_PRE = 0x0
4678 20:11:31.930270 WR_PRE = 0x1
4679 20:11:31.930688 WR_PST = 0x0
4680 20:11:31.934129 DBI_WR = 0x0
4681 20:11:31.934757 DBI_RD = 0x0
4682 20:11:31.937015 OTF = 0x1
4683 20:11:31.940545 ===================================
4684 20:11:31.943564 ===================================
4685 20:11:31.944181 ANA top config
4686 20:11:31.946749 ===================================
4687 20:11:31.949999 DLL_ASYNC_EN = 0
4688 20:11:31.953965 ALL_SLAVE_EN = 1
4689 20:11:31.956959 NEW_RANK_MODE = 1
4690 20:11:31.957558 DLL_IDLE_MODE = 1
4691 20:11:31.960757 LP45_APHY_COMB_EN = 1
4692 20:11:31.963299 TX_ODT_DIS = 1
4693 20:11:31.966687 NEW_8X_MODE = 1
4694 20:11:31.970023 ===================================
4695 20:11:31.973144 ===================================
4696 20:11:31.976403 data_rate = 1866
4697 20:11:31.976844 CKR = 1
4698 20:11:31.980143 DQ_P2S_RATIO = 8
4699 20:11:31.983924 ===================================
4700 20:11:31.986819 CA_P2S_RATIO = 8
4701 20:11:31.989777 DQ_CA_OPEN = 0
4702 20:11:31.993299 DQ_SEMI_OPEN = 0
4703 20:11:31.996823 CA_SEMI_OPEN = 0
4704 20:11:31.997241 CA_FULL_RATE = 0
4705 20:11:31.999930 DQ_CKDIV4_EN = 1
4706 20:11:32.003060 CA_CKDIV4_EN = 1
4707 20:11:32.006691 CA_PREDIV_EN = 0
4708 20:11:32.010048 PH8_DLY = 0
4709 20:11:32.013304 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4710 20:11:32.013776 DQ_AAMCK_DIV = 4
4711 20:11:32.016382 CA_AAMCK_DIV = 4
4712 20:11:32.019487 CA_ADMCK_DIV = 4
4713 20:11:32.022734 DQ_TRACK_CA_EN = 0
4714 20:11:32.026772 CA_PICK = 933
4715 20:11:32.029668 CA_MCKIO = 933
4716 20:11:32.030084 MCKIO_SEMI = 0
4717 20:11:32.033303 PLL_FREQ = 3732
4718 20:11:32.036532 DQ_UI_PI_RATIO = 32
4719 20:11:32.039722 CA_UI_PI_RATIO = 0
4720 20:11:32.043512 ===================================
4721 20:11:32.046244 ===================================
4722 20:11:32.050037 memory_type:LPDDR4
4723 20:11:32.050568 GP_NUM : 10
4724 20:11:32.053090 SRAM_EN : 1
4725 20:11:32.056103 MD32_EN : 0
4726 20:11:32.059699 ===================================
4727 20:11:32.060117 [ANA_INIT] >>>>>>>>>>>>>>
4728 20:11:32.063939 <<<<<< [CONFIGURE PHASE]: ANA_TX
4729 20:11:32.066718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4730 20:11:32.069676 ===================================
4731 20:11:32.072764 data_rate = 1866,PCW = 0X8f00
4732 20:11:32.077017 ===================================
4733 20:11:32.079542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4734 20:11:32.087072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4735 20:11:32.089873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4736 20:11:32.096270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4737 20:11:32.100366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4738 20:11:32.102571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4739 20:11:32.103030 [ANA_INIT] flow start
4740 20:11:32.106014 [ANA_INIT] PLL >>>>>>>>
4741 20:11:32.109174 [ANA_INIT] PLL <<<<<<<<
4742 20:11:32.112273 [ANA_INIT] MIDPI >>>>>>>>
4743 20:11:32.112689 [ANA_INIT] MIDPI <<<<<<<<
4744 20:11:32.116020 [ANA_INIT] DLL >>>>>>>>
4745 20:11:32.119381 [ANA_INIT] flow end
4746 20:11:32.122589 ============ LP4 DIFF to SE enter ============
4747 20:11:32.125751 ============ LP4 DIFF to SE exit ============
4748 20:11:32.128859 [ANA_INIT] <<<<<<<<<<<<<
4749 20:11:32.132332 [Flow] Enable top DCM control >>>>>
4750 20:11:32.135904 [Flow] Enable top DCM control <<<<<
4751 20:11:32.139009 Enable DLL master slave shuffle
4752 20:11:32.142270 ==============================================================
4753 20:11:32.145945 Gating Mode config
4754 20:11:32.152034 ==============================================================
4755 20:11:32.152601 Config description:
4756 20:11:32.161893 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4757 20:11:32.168610 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4758 20:11:32.175492 SELPH_MODE 0: By rank 1: By Phase
4759 20:11:32.179669 ==============================================================
4760 20:11:32.181741 GAT_TRACK_EN = 1
4761 20:11:32.185117 RX_GATING_MODE = 2
4762 20:11:32.188047 RX_GATING_TRACK_MODE = 2
4763 20:11:32.191462 SELPH_MODE = 1
4764 20:11:32.194843 PICG_EARLY_EN = 1
4765 20:11:32.197854 VALID_LAT_VALUE = 1
4766 20:11:32.201258 ==============================================================
4767 20:11:32.204507 Enter into Gating configuration >>>>
4768 20:11:32.208031 Exit from Gating configuration <<<<
4769 20:11:32.211344 Enter into DVFS_PRE_config >>>>>
4770 20:11:32.224438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4771 20:11:32.227726 Exit from DVFS_PRE_config <<<<<
4772 20:11:32.231412 Enter into PICG configuration >>>>
4773 20:11:32.231830 Exit from PICG configuration <<<<
4774 20:11:32.234919 [RX_INPUT] configuration >>>>>
4775 20:11:32.237375 [RX_INPUT] configuration <<<<<
4776 20:11:32.244546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4777 20:11:32.247687 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4778 20:11:32.254589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4779 20:11:32.261348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4780 20:11:32.267452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4781 20:11:32.274534 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4782 20:11:32.277751 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4783 20:11:32.281461 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4784 20:11:32.287316 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4785 20:11:32.290806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4786 20:11:32.293528 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4787 20:11:32.296826 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4788 20:11:32.300247 ===================================
4789 20:11:32.303679 LPDDR4 DRAM CONFIGURATION
4790 20:11:32.307191 ===================================
4791 20:11:32.310882 EX_ROW_EN[0] = 0x0
4792 20:11:32.311299 EX_ROW_EN[1] = 0x0
4793 20:11:32.314144 LP4Y_EN = 0x0
4794 20:11:32.314559 WORK_FSP = 0x0
4795 20:11:32.317241 WL = 0x3
4796 20:11:32.317658 RL = 0x3
4797 20:11:32.320310 BL = 0x2
4798 20:11:32.320754 RPST = 0x0
4799 20:11:32.324157 RD_PRE = 0x0
4800 20:11:32.324570 WR_PRE = 0x1
4801 20:11:32.326910 WR_PST = 0x0
4802 20:11:32.330147 DBI_WR = 0x0
4803 20:11:32.330580 DBI_RD = 0x0
4804 20:11:32.333774 OTF = 0x1
4805 20:11:32.336991 ===================================
4806 20:11:32.339972 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4807 20:11:32.343581 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4808 20:11:32.347384 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4809 20:11:32.350054 ===================================
4810 20:11:32.353431 LPDDR4 DRAM CONFIGURATION
4811 20:11:32.356489 ===================================
4812 20:11:32.360268 EX_ROW_EN[0] = 0x10
4813 20:11:32.360682 EX_ROW_EN[1] = 0x0
4814 20:11:32.363309 LP4Y_EN = 0x0
4815 20:11:32.363724 WORK_FSP = 0x0
4816 20:11:32.366540 WL = 0x3
4817 20:11:32.366956 RL = 0x3
4818 20:11:32.369573 BL = 0x2
4819 20:11:32.369989 RPST = 0x0
4820 20:11:32.373307 RD_PRE = 0x0
4821 20:11:32.376553 WR_PRE = 0x1
4822 20:11:32.377004 WR_PST = 0x0
4823 20:11:32.379700 DBI_WR = 0x0
4824 20:11:32.380114 DBI_RD = 0x0
4825 20:11:32.383372 OTF = 0x1
4826 20:11:32.386696 ===================================
4827 20:11:32.389573 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4828 20:11:32.395171 nWR fixed to 30
4829 20:11:32.398370 [ModeRegInit_LP4] CH0 RK0
4830 20:11:32.398920 [ModeRegInit_LP4] CH0 RK1
4831 20:11:32.401669 [ModeRegInit_LP4] CH1 RK0
4832 20:11:32.404671 [ModeRegInit_LP4] CH1 RK1
4833 20:11:32.405267 match AC timing 8
4834 20:11:32.411405 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4835 20:11:32.414895 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4836 20:11:32.418140 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4837 20:11:32.424572 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4838 20:11:32.428530 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4839 20:11:32.429175 ==
4840 20:11:32.431806 Dram Type= 6, Freq= 0, CH_0, rank 0
4841 20:11:32.434672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4842 20:11:32.435122 ==
4843 20:11:32.441548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4844 20:11:32.448235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4845 20:11:32.451050 [CA 0] Center 39 (8~70) winsize 63
4846 20:11:32.455249 [CA 1] Center 38 (8~69) winsize 62
4847 20:11:32.457589 [CA 2] Center 36 (6~67) winsize 62
4848 20:11:32.461208 [CA 3] Center 36 (6~66) winsize 61
4849 20:11:32.464849 [CA 4] Center 34 (4~65) winsize 62
4850 20:11:32.467886 [CA 5] Center 34 (4~65) winsize 62
4851 20:11:32.468300
4852 20:11:32.471406 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4853 20:11:32.471824
4854 20:11:32.474799 [CATrainingPosCal] consider 1 rank data
4855 20:11:32.477449 u2DelayCellTimex100 = 270/100 ps
4856 20:11:32.481133 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4857 20:11:32.484466 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4858 20:11:32.487884 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4859 20:11:32.491074 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4860 20:11:32.497534 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4861 20:11:32.501063 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4862 20:11:32.501481
4863 20:11:32.504665 CA PerBit enable=1, Macro0, CA PI delay=34
4864 20:11:32.505109
4865 20:11:32.507340 [CBTSetCACLKResult] CA Dly = 34
4866 20:11:32.507758 CS Dly: 7 (0~38)
4867 20:11:32.508092 ==
4868 20:11:32.511148 Dram Type= 6, Freq= 0, CH_0, rank 1
4869 20:11:32.517073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4870 20:11:32.517494 ==
4871 20:11:32.520896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4872 20:11:32.526995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4873 20:11:32.531049 [CA 0] Center 38 (8~69) winsize 62
4874 20:11:32.534039 [CA 1] Center 38 (7~69) winsize 63
4875 20:11:32.537142 [CA 2] Center 36 (5~67) winsize 63
4876 20:11:32.540606 [CA 3] Center 35 (5~66) winsize 62
4877 20:11:32.543848 [CA 4] Center 34 (3~65) winsize 63
4878 20:11:32.548163 [CA 5] Center 34 (3~65) winsize 63
4879 20:11:32.548654
4880 20:11:32.550163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4881 20:11:32.550652
4882 20:11:32.553763 [CATrainingPosCal] consider 2 rank data
4883 20:11:32.557148 u2DelayCellTimex100 = 270/100 ps
4884 20:11:32.560348 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4885 20:11:32.563440 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4886 20:11:32.570306 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4887 20:11:32.573246 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4888 20:11:32.577192 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4889 20:11:32.579894 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4890 20:11:32.580309
4891 20:11:32.583612 CA PerBit enable=1, Macro0, CA PI delay=34
4892 20:11:32.584029
4893 20:11:32.586890 [CBTSetCACLKResult] CA Dly = 34
4894 20:11:32.587308 CS Dly: 7 (0~39)
4895 20:11:32.587636
4896 20:11:32.590658 ----->DramcWriteLeveling(PI) begin...
4897 20:11:32.593550 ==
4898 20:11:32.596750 Dram Type= 6, Freq= 0, CH_0, rank 0
4899 20:11:32.600422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4900 20:11:32.600873 ==
4901 20:11:32.603485 Write leveling (Byte 0): 29 => 29
4902 20:11:32.606694 Write leveling (Byte 1): 29 => 29
4903 20:11:32.610675 DramcWriteLeveling(PI) end<-----
4904 20:11:32.611091
4905 20:11:32.611434 ==
4906 20:11:32.613137 Dram Type= 6, Freq= 0, CH_0, rank 0
4907 20:11:32.616330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4908 20:11:32.616769 ==
4909 20:11:32.619621 [Gating] SW mode calibration
4910 20:11:32.626852 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4911 20:11:32.632979 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4912 20:11:32.636207 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 20:11:32.639911 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4914 20:11:32.646721 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4915 20:11:32.649361 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4916 20:11:32.652695 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 20:11:32.659393 0 10 20 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 1)
4918 20:11:32.663432 0 10 24 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
4919 20:11:32.666037 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 20:11:32.672897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 20:11:32.676194 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 20:11:32.679142 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4923 20:11:32.686579 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 20:11:32.689165 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 20:11:32.693171 0 11 20 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (1 1)
4926 20:11:32.699028 0 11 24 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
4927 20:11:32.702569 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 20:11:32.705769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 20:11:32.713180 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 20:11:32.716527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4931 20:11:32.719300 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 20:11:32.722166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 20:11:32.729194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4934 20:11:32.732536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 20:11:32.735902 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 20:11:32.742672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 20:11:32.746006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 20:11:32.749583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 20:11:32.755512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 20:11:32.759722 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 20:11:32.762347 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 20:11:32.768580 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 20:11:32.772474 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 20:11:32.775466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 20:11:32.781825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 20:11:32.785443 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 20:11:32.788800 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 20:11:32.795299 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 20:11:32.799231 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4950 20:11:32.801964 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4951 20:11:32.805016 Total UI for P1: 0, mck2ui 16
4952 20:11:32.808189 best dqsien dly found for B1: ( 0, 14, 20)
4953 20:11:32.815342 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4954 20:11:32.815423 Total UI for P1: 0, mck2ui 16
4955 20:11:32.821299 best dqsien dly found for B0: ( 0, 14, 22)
4956 20:11:32.824858 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4957 20:11:32.828038 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4958 20:11:32.828118
4959 20:11:32.831417 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4960 20:11:32.834683 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4961 20:11:32.838138 [Gating] SW calibration Done
4962 20:11:32.838220 ==
4963 20:11:32.841406 Dram Type= 6, Freq= 0, CH_0, rank 0
4964 20:11:32.845422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4965 20:11:32.845504 ==
4966 20:11:32.847986 RX Vref Scan: 0
4967 20:11:32.848066
4968 20:11:32.848130 RX Vref 0 -> 0, step: 1
4969 20:11:32.848191
4970 20:11:32.851766 RX Delay -80 -> 252, step: 8
4971 20:11:32.854888 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4972 20:11:32.861559 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4973 20:11:32.864963 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4974 20:11:32.868194 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4975 20:11:32.871612 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4976 20:11:32.874362 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4977 20:11:32.877926 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4978 20:11:32.884539 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4979 20:11:32.887603 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4980 20:11:32.891750 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4981 20:11:32.894139 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4982 20:11:32.897841 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4983 20:11:32.904469 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4984 20:11:32.907604 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4985 20:11:32.911430 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4986 20:11:32.914299 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4987 20:11:32.914389 ==
4988 20:11:32.917880 Dram Type= 6, Freq= 0, CH_0, rank 0
4989 20:11:32.923791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4990 20:11:32.923872 ==
4991 20:11:32.923936 DQS Delay:
4992 20:11:32.928366 DQS0 = 0, DQS1 = 0
4993 20:11:32.928448 DQM Delay:
4994 20:11:32.928512 DQM0 = 96, DQM1 = 85
4995 20:11:32.930867 DQ Delay:
4996 20:11:32.934069 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
4997 20:11:32.937563 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
4998 20:11:32.941011 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
4999 20:11:32.943734 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5000 20:11:32.943817
5001 20:11:32.943902
5002 20:11:32.943983 ==
5003 20:11:32.947053 Dram Type= 6, Freq= 0, CH_0, rank 0
5004 20:11:32.950537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5005 20:11:32.950622 ==
5006 20:11:32.950707
5007 20:11:32.950787
5008 20:11:32.954035 TX Vref Scan disable
5009 20:11:32.954119 == TX Byte 0 ==
5010 20:11:32.960686 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5011 20:11:32.963990 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5012 20:11:32.967323 == TX Byte 1 ==
5013 20:11:32.970715 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5014 20:11:32.973396 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5015 20:11:32.973480 ==
5016 20:11:32.977575 Dram Type= 6, Freq= 0, CH_0, rank 0
5017 20:11:32.980178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5018 20:11:32.980263 ==
5019 20:11:32.984058
5020 20:11:32.984141
5021 20:11:32.984227 TX Vref Scan disable
5022 20:11:32.986811 == TX Byte 0 ==
5023 20:11:32.989834 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5024 20:11:32.996596 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5025 20:11:32.996680 == TX Byte 1 ==
5026 20:11:32.999946 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5027 20:11:33.006511 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5028 20:11:33.006594
5029 20:11:33.006679 [DATLAT]
5030 20:11:33.006760 Freq=933, CH0 RK0
5031 20:11:33.006838
5032 20:11:33.010439 DATLAT Default: 0xd
5033 20:11:33.013340 0, 0xFFFF, sum = 0
5034 20:11:33.013425 1, 0xFFFF, sum = 0
5035 20:11:33.017163 2, 0xFFFF, sum = 0
5036 20:11:33.017264 3, 0xFFFF, sum = 0
5037 20:11:33.019550 4, 0xFFFF, sum = 0
5038 20:11:33.019635 5, 0xFFFF, sum = 0
5039 20:11:33.023380 6, 0xFFFF, sum = 0
5040 20:11:33.023465 7, 0xFFFF, sum = 0
5041 20:11:33.026229 8, 0xFFFF, sum = 0
5042 20:11:33.026314 9, 0xFFFF, sum = 0
5043 20:11:33.030556 10, 0x0, sum = 1
5044 20:11:33.030655 11, 0x0, sum = 2
5045 20:11:33.032850 12, 0x0, sum = 3
5046 20:11:33.032935 13, 0x0, sum = 4
5047 20:11:33.036532 best_step = 11
5048 20:11:33.036615
5049 20:11:33.036741 ==
5050 20:11:33.039670 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 20:11:33.042792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5052 20:11:33.042913 ==
5053 20:11:33.043003 RX Vref Scan: 1
5054 20:11:33.045983
5055 20:11:33.046064 RX Vref 0 -> 0, step: 1
5056 20:11:33.046128
5057 20:11:33.050164 RX Delay -61 -> 252, step: 4
5058 20:11:33.050245
5059 20:11:33.052672 Set Vref, RX VrefLevel [Byte0]: 47
5060 20:11:33.055811 [Byte1]: 46
5061 20:11:33.059660
5062 20:11:33.059740 Final RX Vref Byte 0 = 47 to rank0
5063 20:11:33.063186 Final RX Vref Byte 1 = 46 to rank0
5064 20:11:33.066616 Final RX Vref Byte 0 = 47 to rank1
5065 20:11:33.069754 Final RX Vref Byte 1 = 46 to rank1==
5066 20:11:33.072799 Dram Type= 6, Freq= 0, CH_0, rank 0
5067 20:11:33.079012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5068 20:11:33.079093 ==
5069 20:11:33.079157 DQS Delay:
5070 20:11:33.079217 DQS0 = 0, DQS1 = 0
5071 20:11:33.082465 DQM Delay:
5072 20:11:33.082546 DQM0 = 97, DQM1 = 86
5073 20:11:33.085670 DQ Delay:
5074 20:11:33.089224 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5075 20:11:33.092863 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =106
5076 20:11:33.096306 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =80
5077 20:11:33.099476 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =96
5078 20:11:33.099557
5079 20:11:33.099621
5080 20:11:33.105800 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5081 20:11:33.109059 CH0 RK0: MR19=505, MR18=2222
5082 20:11:33.115727 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5083 20:11:33.115809
5084 20:11:33.119368 ----->DramcWriteLeveling(PI) begin...
5085 20:11:33.119450 ==
5086 20:11:33.122698 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 20:11:33.126097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5088 20:11:33.126178 ==
5089 20:11:33.129628 Write leveling (Byte 0): 31 => 31
5090 20:11:33.132480 Write leveling (Byte 1): 29 => 29
5091 20:11:33.135608 DramcWriteLeveling(PI) end<-----
5092 20:11:33.135689
5093 20:11:33.135753 ==
5094 20:11:33.138858 Dram Type= 6, Freq= 0, CH_0, rank 1
5095 20:11:33.142230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5096 20:11:33.145573 ==
5097 20:11:33.145653 [Gating] SW mode calibration
5098 20:11:33.152049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5099 20:11:33.159144 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5100 20:11:33.162050 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 20:11:33.168586 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 20:11:33.171702 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 20:11:33.175217 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 20:11:33.182840 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 20:11:33.185752 0 10 20 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
5106 20:11:33.188618 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5107 20:11:33.195230 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 20:11:33.198476 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 20:11:33.202016 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 20:11:33.208596 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 20:11:33.212322 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 20:11:33.215316 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5113 20:11:33.221516 0 11 20 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5114 20:11:33.225448 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5115 20:11:33.228136 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 20:11:33.234986 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 20:11:33.239033 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 20:11:33.241710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 20:11:33.248462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 20:11:33.251548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 20:11:33.254345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5122 20:11:33.261415 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5123 20:11:33.264583 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 20:11:33.267926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 20:11:33.274473 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 20:11:33.277403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 20:11:33.281510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 20:11:33.287573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 20:11:33.291177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 20:11:33.294127 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 20:11:33.300811 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 20:11:33.304427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 20:11:33.307375 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 20:11:33.313612 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 20:11:33.317446 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 20:11:33.320848 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 20:11:33.327341 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5138 20:11:33.330458 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5139 20:11:33.333380 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 20:11:33.337496 Total UI for P1: 0, mck2ui 16
5141 20:11:33.340635 best dqsien dly found for B0: ( 0, 14, 22)
5142 20:11:33.344244 Total UI for P1: 0, mck2ui 16
5143 20:11:33.347367 best dqsien dly found for B1: ( 0, 14, 22)
5144 20:11:33.350232 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5145 20:11:33.353851 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5146 20:11:33.353932
5147 20:11:33.360255 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5148 20:11:33.363512 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5149 20:11:33.363593 [Gating] SW calibration Done
5150 20:11:33.367017 ==
5151 20:11:33.370055 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 20:11:33.373316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5153 20:11:33.373418 ==
5154 20:11:33.373484 RX Vref Scan: 0
5155 20:11:33.373544
5156 20:11:33.376970 RX Vref 0 -> 0, step: 1
5157 20:11:33.377096
5158 20:11:33.379741 RX Delay -80 -> 252, step: 8
5159 20:11:33.383608 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5160 20:11:33.386872 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5161 20:11:33.389628 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5162 20:11:33.396600 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5163 20:11:33.399524 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5164 20:11:33.402844 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5165 20:11:33.406053 iDelay=200, Bit 6, Center 99 (0 ~ 199) 200
5166 20:11:33.409399 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5167 20:11:33.413129 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5168 20:11:33.419669 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5169 20:11:33.422984 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5170 20:11:33.426221 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5171 20:11:33.429492 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5172 20:11:33.433181 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5173 20:11:33.440405 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5174 20:11:33.442945 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5175 20:11:33.443027 ==
5176 20:11:33.446344 Dram Type= 6, Freq= 0, CH_0, rank 1
5177 20:11:33.449878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5178 20:11:33.449961 ==
5179 20:11:33.453000 DQS Delay:
5180 20:11:33.453080 DQS0 = 0, DQS1 = 0
5181 20:11:33.453144 DQM Delay:
5182 20:11:33.456212 DQM0 = 95, DQM1 = 84
5183 20:11:33.456293 DQ Delay:
5184 20:11:33.459483 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5185 20:11:33.463279 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =103
5186 20:11:33.466377 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5187 20:11:33.469751 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5188 20:11:33.469832
5189 20:11:33.469895
5190 20:11:33.469954 ==
5191 20:11:33.472980 Dram Type= 6, Freq= 0, CH_0, rank 1
5192 20:11:33.479464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5193 20:11:33.479546 ==
5194 20:11:33.479610
5195 20:11:33.479669
5196 20:11:33.479727 TX Vref Scan disable
5197 20:11:33.482904 == TX Byte 0 ==
5198 20:11:33.485657 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5199 20:11:33.492407 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5200 20:11:33.492488 == TX Byte 1 ==
5201 20:11:33.495786 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5202 20:11:33.502741 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5203 20:11:33.502822 ==
5204 20:11:33.505985 Dram Type= 6, Freq= 0, CH_0, rank 1
5205 20:11:33.509447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5206 20:11:33.509528 ==
5207 20:11:33.509592
5208 20:11:33.509652
5209 20:11:33.512672 TX Vref Scan disable
5210 20:11:33.512808 == TX Byte 0 ==
5211 20:11:33.519563 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5212 20:11:33.522611 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5213 20:11:33.522692 == TX Byte 1 ==
5214 20:11:33.529048 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5215 20:11:33.532641 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5216 20:11:33.532781
5217 20:11:33.532851 [DATLAT]
5218 20:11:33.535616 Freq=933, CH0 RK1
5219 20:11:33.535700
5220 20:11:33.535785 DATLAT Default: 0xb
5221 20:11:33.538937 0, 0xFFFF, sum = 0
5222 20:11:33.539023 1, 0xFFFF, sum = 0
5223 20:11:33.542754 2, 0xFFFF, sum = 0
5224 20:11:33.545767 3, 0xFFFF, sum = 0
5225 20:11:33.545851 4, 0xFFFF, sum = 0
5226 20:11:33.548910 5, 0xFFFF, sum = 0
5227 20:11:33.548995 6, 0xFFFF, sum = 0
5228 20:11:33.552558 7, 0xFFFF, sum = 0
5229 20:11:33.552643 8, 0xFFFF, sum = 0
5230 20:11:33.555712 9, 0xFFFF, sum = 0
5231 20:11:33.555797 10, 0x0, sum = 1
5232 20:11:33.558620 11, 0x0, sum = 2
5233 20:11:33.558705 12, 0x0, sum = 3
5234 20:11:33.558792 13, 0x0, sum = 4
5235 20:11:33.562420 best_step = 11
5236 20:11:33.562504
5237 20:11:33.562589 ==
5238 20:11:33.565755 Dram Type= 6, Freq= 0, CH_0, rank 1
5239 20:11:33.569538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5240 20:11:33.569621 ==
5241 20:11:33.571902 RX Vref Scan: 0
5242 20:11:33.571991
5243 20:11:33.575541 RX Vref 0 -> 0, step: 1
5244 20:11:33.575621
5245 20:11:33.575685 RX Delay -69 -> 252, step: 4
5246 20:11:33.583290 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5247 20:11:33.586571 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5248 20:11:33.589929 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5249 20:11:33.593094 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5250 20:11:33.596328 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5251 20:11:33.599589 iDelay=199, Bit 5, Center 92 (-1 ~ 186) 188
5252 20:11:33.606010 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5253 20:11:33.609866 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5254 20:11:33.612792 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5255 20:11:33.616087 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5256 20:11:33.619843 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5257 20:11:33.626286 iDelay=199, Bit 11, Center 78 (-5 ~ 162) 168
5258 20:11:33.629188 iDelay=199, Bit 12, Center 92 (7 ~ 178) 172
5259 20:11:33.632634 iDelay=199, Bit 13, Center 90 (3 ~ 178) 176
5260 20:11:33.636560 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5261 20:11:33.639260 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5262 20:11:33.639363 ==
5263 20:11:33.642644 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 20:11:33.649200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5265 20:11:33.649301 ==
5266 20:11:33.649395 DQS Delay:
5267 20:11:33.652941 DQS0 = 0, DQS1 = 0
5268 20:11:33.653042 DQM Delay:
5269 20:11:33.653133 DQM0 = 98, DQM1 = 85
5270 20:11:33.656002 DQ Delay:
5271 20:11:33.659414 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =94
5272 20:11:33.662813 DQ4 =100, DQ5 =92, DQ6 =104, DQ7 =106
5273 20:11:33.667079 DQ8 =74, DQ9 =70, DQ10 =86, DQ11 =78
5274 20:11:33.669691 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5275 20:11:33.669780
5276 20:11:33.669842
5277 20:11:33.675991 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5278 20:11:33.679283 CH0 RK1: MR19=505, MR18=2929
5279 20:11:33.685947 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5280 20:11:33.689230 [RxdqsGatingPostProcess] freq 933
5281 20:11:33.692555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5282 20:11:33.696055 Pre-setting of DQS Precalculation
5283 20:11:33.702597 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5284 20:11:33.702673 ==
5285 20:11:33.705723 Dram Type= 6, Freq= 0, CH_1, rank 0
5286 20:11:33.709135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5287 20:11:33.709217 ==
5288 20:11:33.715568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5289 20:11:33.722347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5290 20:11:33.726160 [CA 0] Center 37 (6~68) winsize 63
5291 20:11:33.729248 [CA 1] Center 37 (6~68) winsize 63
5292 20:11:33.732131 [CA 2] Center 34 (4~65) winsize 62
5293 20:11:33.735748 [CA 3] Center 34 (4~65) winsize 62
5294 20:11:33.738599 [CA 4] Center 33 (2~64) winsize 63
5295 20:11:33.742137 [CA 5] Center 33 (3~64) winsize 62
5296 20:11:33.742220
5297 20:11:33.746211 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5298 20:11:33.746292
5299 20:11:33.749082 [CATrainingPosCal] consider 1 rank data
5300 20:11:33.751997 u2DelayCellTimex100 = 270/100 ps
5301 20:11:33.755932 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5302 20:11:33.759287 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5303 20:11:33.762025 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5304 20:11:33.765957 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5305 20:11:33.768568 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5306 20:11:33.772252 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5307 20:11:33.772333
5308 20:11:33.778887 CA PerBit enable=1, Macro0, CA PI delay=33
5309 20:11:33.778982
5310 20:11:33.779045 [CBTSetCACLKResult] CA Dly = 33
5311 20:11:33.782603 CS Dly: 5 (0~36)
5312 20:11:33.782753 ==
5313 20:11:33.785813 Dram Type= 6, Freq= 0, CH_1, rank 1
5314 20:11:33.788619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5315 20:11:33.788701 ==
5316 20:11:33.795706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5317 20:11:33.802058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5318 20:11:33.805157 [CA 0] Center 37 (6~68) winsize 63
5319 20:11:33.808630 [CA 1] Center 37 (6~68) winsize 63
5320 20:11:33.811840 [CA 2] Center 34 (4~65) winsize 62
5321 20:11:33.815997 [CA 3] Center 34 (4~64) winsize 61
5322 20:11:33.818658 [CA 4] Center 33 (3~64) winsize 62
5323 20:11:33.821852 [CA 5] Center 32 (2~63) winsize 62
5324 20:11:33.821932
5325 20:11:33.825162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5326 20:11:33.825242
5327 20:11:33.828190 [CATrainingPosCal] consider 2 rank data
5328 20:11:33.832064 u2DelayCellTimex100 = 270/100 ps
5329 20:11:33.835668 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5330 20:11:33.839007 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5331 20:11:33.841735 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5332 20:11:33.845285 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5333 20:11:33.848901 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5334 20:11:33.851967 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5335 20:11:33.855385
5336 20:11:33.858821 CA PerBit enable=1, Macro0, CA PI delay=33
5337 20:11:33.858902
5338 20:11:33.861344 [CBTSetCACLKResult] CA Dly = 33
5339 20:11:33.861424 CS Dly: 5 (0~37)
5340 20:11:33.861491
5341 20:11:33.865014 ----->DramcWriteLeveling(PI) begin...
5342 20:11:33.865096 ==
5343 20:11:33.868063 Dram Type= 6, Freq= 0, CH_1, rank 0
5344 20:11:33.871437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5345 20:11:33.875064 ==
5346 20:11:33.875144 Write leveling (Byte 0): 25 => 25
5347 20:11:33.878068 Write leveling (Byte 1): 25 => 25
5348 20:11:33.881350 DramcWriteLeveling(PI) end<-----
5349 20:11:33.881430
5350 20:11:33.881492 ==
5351 20:11:33.884697 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 20:11:33.891077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 20:11:33.891158 ==
5354 20:11:33.895275 [Gating] SW mode calibration
5355 20:11:33.901610 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5356 20:11:33.904250 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5357 20:11:33.912397 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 20:11:33.914634 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 20:11:33.917747 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 20:11:33.925110 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 20:11:33.928125 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5362 20:11:33.931138 0 10 20 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
5363 20:11:33.937501 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5364 20:11:33.940738 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 20:11:33.943845 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 20:11:33.950997 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 20:11:33.954031 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 20:11:33.957358 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 20:11:33.963751 0 11 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5370 20:11:33.966947 0 11 20 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
5371 20:11:33.970989 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5372 20:11:33.976896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 20:11:33.980601 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 20:11:33.983914 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 20:11:33.990211 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 20:11:33.993925 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 20:11:33.997916 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 20:11:34.003726 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 20:11:34.007226 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 20:11:34.010217 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 20:11:34.013951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 20:11:34.020982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 20:11:34.023740 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 20:11:34.027574 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 20:11:34.033632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 20:11:34.037232 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 20:11:34.040298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 20:11:34.047011 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 20:11:34.050081 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 20:11:34.053201 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 20:11:34.059703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 20:11:34.063943 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 20:11:34.066685 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5394 20:11:34.073816 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5395 20:11:34.076594 Total UI for P1: 0, mck2ui 16
5396 20:11:34.080037 best dqsien dly found for B0: ( 0, 14, 16)
5397 20:11:34.083574 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 20:11:34.086786 Total UI for P1: 0, mck2ui 16
5399 20:11:34.089682 best dqsien dly found for B1: ( 0, 14, 20)
5400 20:11:34.092927 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5401 20:11:34.095996 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5402 20:11:34.096078
5403 20:11:34.099597 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5404 20:11:34.103027 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5405 20:11:34.106632 [Gating] SW calibration Done
5406 20:11:34.106712 ==
5407 20:11:34.109447 Dram Type= 6, Freq= 0, CH_1, rank 0
5408 20:11:34.116164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5409 20:11:34.116264 ==
5410 20:11:34.116342 RX Vref Scan: 0
5411 20:11:34.116402
5412 20:11:34.119196 RX Vref 0 -> 0, step: 1
5413 20:11:34.119277
5414 20:11:34.122758 RX Delay -80 -> 252, step: 8
5415 20:11:34.126353 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5416 20:11:34.129284 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5417 20:11:34.132769 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5418 20:11:34.136139 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5419 20:11:34.143350 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5420 20:11:34.146441 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5421 20:11:34.149364 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5422 20:11:34.152742 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5423 20:11:34.155920 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5424 20:11:34.162323 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5425 20:11:34.165978 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5426 20:11:34.169044 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5427 20:11:34.172296 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5428 20:11:34.175578 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5429 20:11:34.179090 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5430 20:11:34.186245 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5431 20:11:34.186325 ==
5432 20:11:34.189484 Dram Type= 6, Freq= 0, CH_1, rank 0
5433 20:11:34.192229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5434 20:11:34.192309 ==
5435 20:11:34.192372 DQS Delay:
5436 20:11:34.195780 DQS0 = 0, DQS1 = 0
5437 20:11:34.195861 DQM Delay:
5438 20:11:34.199414 DQM0 = 95, DQM1 = 88
5439 20:11:34.199494 DQ Delay:
5440 20:11:34.202317 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5441 20:11:34.205868 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5442 20:11:34.209474 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5443 20:11:34.212071 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5444 20:11:34.212151
5445 20:11:34.212254
5446 20:11:34.212330 ==
5447 20:11:34.215159 Dram Type= 6, Freq= 0, CH_1, rank 0
5448 20:11:34.218602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5449 20:11:34.222135 ==
5450 20:11:34.222215
5451 20:11:34.222280
5452 20:11:34.222340 TX Vref Scan disable
5453 20:11:34.225871 == TX Byte 0 ==
5454 20:11:34.228462 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5455 20:11:34.232520 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5456 20:11:34.234969 == TX Byte 1 ==
5457 20:11:34.238340 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5458 20:11:34.242207 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5459 20:11:34.245324 ==
5460 20:11:34.248374 Dram Type= 6, Freq= 0, CH_1, rank 0
5461 20:11:34.252739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5462 20:11:34.252821 ==
5463 20:11:34.252885
5464 20:11:34.252944
5465 20:11:34.255412 TX Vref Scan disable
5466 20:11:34.255497 == TX Byte 0 ==
5467 20:11:34.261339 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5468 20:11:34.264820 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5469 20:11:34.264902 == TX Byte 1 ==
5470 20:11:34.271295 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5471 20:11:34.274725 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5472 20:11:34.274806
5473 20:11:34.274870 [DATLAT]
5474 20:11:34.278241 Freq=933, CH1 RK0
5475 20:11:34.278362
5476 20:11:34.278426 DATLAT Default: 0xd
5477 20:11:34.281484 0, 0xFFFF, sum = 0
5478 20:11:34.281566 1, 0xFFFF, sum = 0
5479 20:11:34.284523 2, 0xFFFF, sum = 0
5480 20:11:34.284605 3, 0xFFFF, sum = 0
5481 20:11:34.288167 4, 0xFFFF, sum = 0
5482 20:11:34.291384 5, 0xFFFF, sum = 0
5483 20:11:34.291467 6, 0xFFFF, sum = 0
5484 20:11:34.294554 7, 0xFFFF, sum = 0
5485 20:11:34.294637 8, 0xFFFF, sum = 0
5486 20:11:34.297830 9, 0xFFFF, sum = 0
5487 20:11:34.297913 10, 0x0, sum = 1
5488 20:11:34.301283 11, 0x0, sum = 2
5489 20:11:34.301364 12, 0x0, sum = 3
5490 20:11:34.301430 13, 0x0, sum = 4
5491 20:11:34.304529 best_step = 11
5492 20:11:34.304610
5493 20:11:34.304674 ==
5494 20:11:34.307663 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 20:11:34.311201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5496 20:11:34.311283 ==
5497 20:11:34.315044 RX Vref Scan: 1
5498 20:11:34.315140
5499 20:11:34.315218 RX Vref 0 -> 0, step: 1
5500 20:11:34.317855
5501 20:11:34.317950 RX Delay -69 -> 252, step: 4
5502 20:11:34.318029
5503 20:11:34.321452 Set Vref, RX VrefLevel [Byte0]: 54
5504 20:11:34.324319 [Byte1]: 49
5505 20:11:34.329107
5506 20:11:34.329189 Final RX Vref Byte 0 = 54 to rank0
5507 20:11:34.332501 Final RX Vref Byte 1 = 49 to rank0
5508 20:11:34.335715 Final RX Vref Byte 0 = 54 to rank1
5509 20:11:34.339313 Final RX Vref Byte 1 = 49 to rank1==
5510 20:11:34.341913 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 20:11:34.348732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5512 20:11:34.348855 ==
5513 20:11:34.348937 DQS Delay:
5514 20:11:34.348998 DQS0 = 0, DQS1 = 0
5515 20:11:34.351889 DQM Delay:
5516 20:11:34.351970 DQM0 = 94, DQM1 = 88
5517 20:11:34.355327 DQ Delay:
5518 20:11:34.358830 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5519 20:11:34.361930 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5520 20:11:34.365389 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5521 20:11:34.368557 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5522 20:11:34.368638
5523 20:11:34.368702
5524 20:11:34.375350 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5525 20:11:34.378476 CH1 RK0: MR19=505, MR18=3939
5526 20:11:34.385469 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5527 20:11:34.385551
5528 20:11:34.388417 ----->DramcWriteLeveling(PI) begin...
5529 20:11:34.388501 ==
5530 20:11:34.392605 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 20:11:34.395275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5532 20:11:34.395357 ==
5533 20:11:34.398823 Write leveling (Byte 0): 27 => 27
5534 20:11:34.401634 Write leveling (Byte 1): 27 => 27
5535 20:11:34.405091 DramcWriteLeveling(PI) end<-----
5536 20:11:34.405172
5537 20:11:34.405236 ==
5538 20:11:34.408882 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 20:11:34.411596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5540 20:11:34.411677 ==
5541 20:11:34.415064 [Gating] SW mode calibration
5542 20:11:34.421467 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5543 20:11:34.428075 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5544 20:11:34.431628 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 20:11:34.438246 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 20:11:34.441536 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 20:11:34.444656 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5548 20:11:34.451729 0 10 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
5549 20:11:34.455154 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5550 20:11:34.458821 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 20:11:34.465505 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 20:11:34.468774 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 20:11:34.471937 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 20:11:34.478356 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 20:11:34.481367 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 20:11:34.484590 0 11 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
5557 20:11:34.488643 0 11 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
5558 20:11:34.494939 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 20:11:34.498240 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 20:11:34.501341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 20:11:34.507872 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 20:11:34.512101 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 20:11:34.514267 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 20:11:34.521370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5565 20:11:34.524732 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5566 20:11:34.528032 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 20:11:34.534248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 20:11:34.537836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 20:11:34.540931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 20:11:34.547844 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 20:11:34.551499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 20:11:34.554038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 20:11:34.560361 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 20:11:34.563966 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 20:11:34.567063 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 20:11:34.573999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 20:11:34.577074 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 20:11:34.580716 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 20:11:34.588049 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5580 20:11:34.590633 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5581 20:11:34.593653 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5582 20:11:34.596964 Total UI for P1: 0, mck2ui 16
5583 20:11:34.600899 best dqsien dly found for B0: ( 0, 14, 14)
5584 20:11:34.606980 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 20:11:34.607061 Total UI for P1: 0, mck2ui 16
5586 20:11:34.613721 best dqsien dly found for B1: ( 0, 14, 20)
5587 20:11:34.617273 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5588 20:11:34.620291 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5589 20:11:34.620372
5590 20:11:34.623829 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5591 20:11:34.627148 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5592 20:11:34.630259 [Gating] SW calibration Done
5593 20:11:34.630340 ==
5594 20:11:34.633577 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 20:11:34.636954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5596 20:11:34.637036 ==
5597 20:11:34.640132 RX Vref Scan: 0
5598 20:11:34.640216
5599 20:11:34.643656 RX Vref 0 -> 0, step: 1
5600 20:11:34.643737
5601 20:11:34.643801 RX Delay -80 -> 252, step: 8
5602 20:11:34.649832 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5603 20:11:34.653224 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5604 20:11:34.656488 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5605 20:11:34.660243 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5606 20:11:34.663349 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5607 20:11:34.666739 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5608 20:11:34.673495 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5609 20:11:34.676610 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5610 20:11:34.680104 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5611 20:11:34.683188 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5612 20:11:34.686481 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5613 20:11:34.689973 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5614 20:11:34.696648 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5615 20:11:34.700042 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5616 20:11:34.703036 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5617 20:11:34.706231 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5618 20:11:34.706312 ==
5619 20:11:34.709513 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 20:11:34.716223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5621 20:11:34.716304 ==
5622 20:11:34.716385 DQS Delay:
5623 20:11:34.716460 DQS0 = 0, DQS1 = 0
5624 20:11:34.719341 DQM Delay:
5625 20:11:34.719421 DQM0 = 98, DQM1 = 89
5626 20:11:34.722726 DQ Delay:
5627 20:11:34.726184 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5628 20:11:34.729323 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5629 20:11:34.732741 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =83
5630 20:11:34.736025 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5631 20:11:34.736106
5632 20:11:34.736171
5633 20:11:34.736230 ==
5634 20:11:34.739043 Dram Type= 6, Freq= 0, CH_1, rank 1
5635 20:11:34.742804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5636 20:11:34.742886 ==
5637 20:11:34.742950
5638 20:11:34.743010
5639 20:11:34.746039 TX Vref Scan disable
5640 20:11:34.746121 == TX Byte 0 ==
5641 20:11:34.752334 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5642 20:11:34.755801 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5643 20:11:34.755882 == TX Byte 1 ==
5644 20:11:34.762319 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5645 20:11:34.765627 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5646 20:11:34.765752 ==
5647 20:11:34.768813 Dram Type= 6, Freq= 0, CH_1, rank 1
5648 20:11:34.772632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5649 20:11:34.772720 ==
5650 20:11:34.772785
5651 20:11:34.775593
5652 20:11:34.775673 TX Vref Scan disable
5653 20:11:34.779722 == TX Byte 0 ==
5654 20:11:34.782603 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5655 20:11:34.786428 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5656 20:11:34.788869 == TX Byte 1 ==
5657 20:11:34.792368 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5658 20:11:34.795352 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5659 20:11:34.799467
5660 20:11:34.799547 [DATLAT]
5661 20:11:34.799611 Freq=933, CH1 RK1
5662 20:11:34.799673
5663 20:11:34.802729 DATLAT Default: 0xb
5664 20:11:34.802810 0, 0xFFFF, sum = 0
5665 20:11:34.806369 1, 0xFFFF, sum = 0
5666 20:11:34.806451 2, 0xFFFF, sum = 0
5667 20:11:34.808988 3, 0xFFFF, sum = 0
5668 20:11:34.809071 4, 0xFFFF, sum = 0
5669 20:11:34.812471 5, 0xFFFF, sum = 0
5670 20:11:34.812553 6, 0xFFFF, sum = 0
5671 20:11:34.815647 7, 0xFFFF, sum = 0
5672 20:11:34.818873 8, 0xFFFF, sum = 0
5673 20:11:34.818955 9, 0xFFFF, sum = 0
5674 20:11:34.822852 10, 0x0, sum = 1
5675 20:11:34.822935 11, 0x0, sum = 2
5676 20:11:34.823001 12, 0x0, sum = 3
5677 20:11:34.826162 13, 0x0, sum = 4
5678 20:11:34.826245 best_step = 11
5679 20:11:34.826309
5680 20:11:34.826369 ==
5681 20:11:34.828574 Dram Type= 6, Freq= 0, CH_1, rank 1
5682 20:11:34.835712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5683 20:11:34.835794 ==
5684 20:11:34.835859 RX Vref Scan: 0
5685 20:11:34.835919
5686 20:11:34.838666 RX Vref 0 -> 0, step: 1
5687 20:11:34.838749
5688 20:11:34.841911 RX Delay -77 -> 252, step: 4
5689 20:11:34.845896 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5690 20:11:34.851941 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5691 20:11:34.856066 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5692 20:11:34.858789 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5693 20:11:34.861764 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5694 20:11:34.865358 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5695 20:11:34.868711 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5696 20:11:34.875315 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5697 20:11:34.878525 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5698 20:11:34.881927 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5699 20:11:34.884905 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5700 20:11:34.888343 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5701 20:11:34.895437 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5702 20:11:34.898248 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5703 20:11:34.901732 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5704 20:11:34.905159 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5705 20:11:34.905239 ==
5706 20:11:34.908544 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 20:11:34.911854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 20:11:34.914605 ==
5709 20:11:34.914684 DQS Delay:
5710 20:11:34.914768 DQS0 = 0, DQS1 = 0
5711 20:11:34.918099 DQM Delay:
5712 20:11:34.918179 DQM0 = 96, DQM1 = 87
5713 20:11:34.921789 DQ Delay:
5714 20:11:34.921869 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5715 20:11:34.925057 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
5716 20:11:34.927922 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5717 20:11:34.934598 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5718 20:11:34.934679
5719 20:11:34.934763
5720 20:11:34.940966 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5721 20:11:34.944495 CH1 RK1: MR19=505, MR18=2222
5722 20:11:34.950908 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5723 20:11:34.954401 [RxdqsGatingPostProcess] freq 933
5724 20:11:34.957678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5725 20:11:34.961123 Pre-setting of DQS Precalculation
5726 20:11:34.967475 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5727 20:11:34.973921 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5728 20:11:34.980915 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5729 20:11:34.980995
5730 20:11:34.981058
5731 20:11:34.984477 [Calibration Summary] 1866 Mbps
5732 20:11:34.984557 CH 0, Rank 0
5733 20:11:34.988169 SW Impedance : PASS
5734 20:11:34.990537 DUTY Scan : NO K
5735 20:11:34.990616 ZQ Calibration : PASS
5736 20:11:34.993786 Jitter Meter : NO K
5737 20:11:34.997368 CBT Training : PASS
5738 20:11:34.997449 Write leveling : PASS
5739 20:11:35.000539 RX DQS gating : PASS
5740 20:11:35.003924 RX DQ/DQS(RDDQC) : PASS
5741 20:11:35.004003 TX DQ/DQS : PASS
5742 20:11:35.007228 RX DATLAT : PASS
5743 20:11:35.010604 RX DQ/DQS(Engine): PASS
5744 20:11:35.010683 TX OE : NO K
5745 20:11:35.013846 All Pass.
5746 20:11:35.013925
5747 20:11:35.013989 CH 0, Rank 1
5748 20:11:35.017202 SW Impedance : PASS
5749 20:11:35.017292 DUTY Scan : NO K
5750 20:11:35.020205 ZQ Calibration : PASS
5751 20:11:35.024147 Jitter Meter : NO K
5752 20:11:35.024227 CBT Training : PASS
5753 20:11:35.026869 Write leveling : PASS
5754 20:11:35.030706 RX DQS gating : PASS
5755 20:11:35.030785 RX DQ/DQS(RDDQC) : PASS
5756 20:11:35.033634 TX DQ/DQS : PASS
5757 20:11:35.033717 RX DATLAT : PASS
5758 20:11:35.036541 RX DQ/DQS(Engine): PASS
5759 20:11:35.039820 TX OE : NO K
5760 20:11:35.039914 All Pass.
5761 20:11:35.039978
5762 20:11:35.043971 CH 1, Rank 0
5763 20:11:35.044051 SW Impedance : PASS
5764 20:11:35.046979 DUTY Scan : NO K
5765 20:11:35.047059 ZQ Calibration : PASS
5766 20:11:35.050246 Jitter Meter : NO K
5767 20:11:35.053926 CBT Training : PASS
5768 20:11:35.054006 Write leveling : PASS
5769 20:11:35.056640 RX DQS gating : PASS
5770 20:11:35.060250 RX DQ/DQS(RDDQC) : PASS
5771 20:11:35.060330 TX DQ/DQS : PASS
5772 20:11:35.063489 RX DATLAT : PASS
5773 20:11:35.066591 RX DQ/DQS(Engine): PASS
5774 20:11:35.066670 TX OE : NO K
5775 20:11:35.069715 All Pass.
5776 20:11:35.069795
5777 20:11:35.069858 CH 1, Rank 1
5778 20:11:35.072926 SW Impedance : PASS
5779 20:11:35.073006 DUTY Scan : NO K
5780 20:11:35.076177 ZQ Calibration : PASS
5781 20:11:35.079687 Jitter Meter : NO K
5782 20:11:35.079767 CBT Training : PASS
5783 20:11:35.083058 Write leveling : PASS
5784 20:11:35.086259 RX DQS gating : PASS
5785 20:11:35.086339 RX DQ/DQS(RDDQC) : PASS
5786 20:11:35.089633 TX DQ/DQS : PASS
5787 20:11:35.093185 RX DATLAT : PASS
5788 20:11:35.093265 RX DQ/DQS(Engine): PASS
5789 20:11:35.096165 TX OE : NO K
5790 20:11:35.096246 All Pass.
5791 20:11:35.096310
5792 20:11:35.099166 DramC Write-DBI off
5793 20:11:35.102875 PER_BANK_REFRESH: Hybrid Mode
5794 20:11:35.102956 TX_TRACKING: ON
5795 20:11:35.112761 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5796 20:11:35.115719 [FAST_K] Save calibration result to emmc
5797 20:11:35.119359 dramc_set_vcore_voltage set vcore to 650000
5798 20:11:35.122663 Read voltage for 400, 6
5799 20:11:35.122746 Vio18 = 0
5800 20:11:35.122810 Vcore = 650000
5801 20:11:35.126072 Vdram = 0
5802 20:11:35.126153 Vddq = 0
5803 20:11:35.126217 Vmddr = 0
5804 20:11:35.133113 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5805 20:11:35.135591 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5806 20:11:35.139606 MEM_TYPE=3, freq_sel=20
5807 20:11:35.142592 sv_algorithm_assistance_LP4_800
5808 20:11:35.146083 ============ PULL DRAM RESETB DOWN ============
5809 20:11:35.149150 ========== PULL DRAM RESETB DOWN end =========
5810 20:11:35.156213 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5811 20:11:35.159346 ===================================
5812 20:11:35.159427 LPDDR4 DRAM CONFIGURATION
5813 20:11:35.163435 ===================================
5814 20:11:35.165858 EX_ROW_EN[0] = 0x0
5815 20:11:35.168853 EX_ROW_EN[1] = 0x0
5816 20:11:35.168934 LP4Y_EN = 0x0
5817 20:11:35.172285 WORK_FSP = 0x0
5818 20:11:35.172366 WL = 0x2
5819 20:11:35.175377 RL = 0x2
5820 20:11:35.175458 BL = 0x2
5821 20:11:35.178827 RPST = 0x0
5822 20:11:35.178953 RD_PRE = 0x0
5823 20:11:35.182368 WR_PRE = 0x1
5824 20:11:35.182448 WR_PST = 0x0
5825 20:11:35.185160 DBI_WR = 0x0
5826 20:11:35.185241 DBI_RD = 0x0
5827 20:11:35.188787 OTF = 0x1
5828 20:11:35.192197 ===================================
5829 20:11:35.195115 ===================================
5830 20:11:35.195196 ANA top config
5831 20:11:35.198363 ===================================
5832 20:11:35.201644 DLL_ASYNC_EN = 0
5833 20:11:35.205326 ALL_SLAVE_EN = 1
5834 20:11:35.208431 NEW_RANK_MODE = 1
5835 20:11:35.211638 DLL_IDLE_MODE = 1
5836 20:11:35.211719 LP45_APHY_COMB_EN = 1
5837 20:11:35.214898 TX_ODT_DIS = 1
5838 20:11:35.218225 NEW_8X_MODE = 1
5839 20:11:35.221321 ===================================
5840 20:11:35.225089 ===================================
5841 20:11:35.228343 data_rate = 800
5842 20:11:35.231928 CKR = 1
5843 20:11:35.232029 DQ_P2S_RATIO = 4
5844 20:11:35.234942 ===================================
5845 20:11:35.238829 CA_P2S_RATIO = 4
5846 20:11:35.241552 DQ_CA_OPEN = 0
5847 20:11:35.244666 DQ_SEMI_OPEN = 1
5848 20:11:35.248727 CA_SEMI_OPEN = 1
5849 20:11:35.251633 CA_FULL_RATE = 0
5850 20:11:35.251714 DQ_CKDIV4_EN = 0
5851 20:11:35.254879 CA_CKDIV4_EN = 1
5852 20:11:35.258300 CA_PREDIV_EN = 0
5853 20:11:35.261570 PH8_DLY = 0
5854 20:11:35.264646 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5855 20:11:35.268210 DQ_AAMCK_DIV = 0
5856 20:11:35.268291 CA_AAMCK_DIV = 0
5857 20:11:35.271622 CA_ADMCK_DIV = 4
5858 20:11:35.274776 DQ_TRACK_CA_EN = 0
5859 20:11:35.277711 CA_PICK = 800
5860 20:11:35.281749 CA_MCKIO = 400
5861 20:11:35.284728 MCKIO_SEMI = 400
5862 20:11:35.287585 PLL_FREQ = 3016
5863 20:11:35.287666 DQ_UI_PI_RATIO = 32
5864 20:11:35.291489 CA_UI_PI_RATIO = 32
5865 20:11:35.294541 ===================================
5866 20:11:35.297746 ===================================
5867 20:11:35.301126 memory_type:LPDDR4
5868 20:11:35.304594 GP_NUM : 10
5869 20:11:35.304674 SRAM_EN : 1
5870 20:11:35.307371 MD32_EN : 0
5871 20:11:35.310801 ===================================
5872 20:11:35.314553 [ANA_INIT] >>>>>>>>>>>>>>
5873 20:11:35.317475 <<<<<< [CONFIGURE PHASE]: ANA_TX
5874 20:11:35.320914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5875 20:11:35.323922 ===================================
5876 20:11:35.324003 data_rate = 800,PCW = 0X7400
5877 20:11:35.327039 ===================================
5878 20:11:35.330410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5879 20:11:35.337476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5880 20:11:35.350909 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5881 20:11:35.353738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5882 20:11:35.357376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5883 20:11:35.360200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5884 20:11:35.363470 [ANA_INIT] flow start
5885 20:11:35.363551 [ANA_INIT] PLL >>>>>>>>
5886 20:11:35.366643 [ANA_INIT] PLL <<<<<<<<
5887 20:11:35.370398 [ANA_INIT] MIDPI >>>>>>>>
5888 20:11:35.370479 [ANA_INIT] MIDPI <<<<<<<<
5889 20:11:35.373554 [ANA_INIT] DLL >>>>>>>>
5890 20:11:35.376905 [ANA_INIT] flow end
5891 20:11:35.380459 ============ LP4 DIFF to SE enter ============
5892 20:11:35.383788 ============ LP4 DIFF to SE exit ============
5893 20:11:35.387200 [ANA_INIT] <<<<<<<<<<<<<
5894 20:11:35.390515 [Flow] Enable top DCM control >>>>>
5895 20:11:35.393743 [Flow] Enable top DCM control <<<<<
5896 20:11:35.396719 Enable DLL master slave shuffle
5897 20:11:35.400107 ==============================================================
5898 20:11:35.403727 Gating Mode config
5899 20:11:35.410376 ==============================================================
5900 20:11:35.410458 Config description:
5901 20:11:35.420068 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5902 20:11:35.426939 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5903 20:11:35.433177 SELPH_MODE 0: By rank 1: By Phase
5904 20:11:35.436421 ==============================================================
5905 20:11:35.439699 GAT_TRACK_EN = 0
5906 20:11:35.442810 RX_GATING_MODE = 2
5907 20:11:35.446281 RX_GATING_TRACK_MODE = 2
5908 20:11:35.449722 SELPH_MODE = 1
5909 20:11:35.453256 PICG_EARLY_EN = 1
5910 20:11:35.455989 VALID_LAT_VALUE = 1
5911 20:11:35.460092 ==============================================================
5912 20:11:35.462801 Enter into Gating configuration >>>>
5913 20:11:35.466691 Exit from Gating configuration <<<<
5914 20:11:35.469844 Enter into DVFS_PRE_config >>>>>
5915 20:11:35.482771 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5916 20:11:35.485874 Exit from DVFS_PRE_config <<<<<
5917 20:11:35.489801 Enter into PICG configuration >>>>
5918 20:11:35.492833 Exit from PICG configuration <<<<
5919 20:11:35.492915 [RX_INPUT] configuration >>>>>
5920 20:11:35.496076 [RX_INPUT] configuration <<<<<
5921 20:11:35.503002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5922 20:11:35.505858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5923 20:11:35.513046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5924 20:11:35.519574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5925 20:11:35.525854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5926 20:11:35.532012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5927 20:11:35.535611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5928 20:11:35.538607 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5929 20:11:35.545500 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5930 20:11:35.549192 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5931 20:11:35.552386 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5932 20:11:35.558880 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5933 20:11:35.562149 ===================================
5934 20:11:35.562231 LPDDR4 DRAM CONFIGURATION
5935 20:11:35.564924 ===================================
5936 20:11:35.568436 EX_ROW_EN[0] = 0x0
5937 20:11:35.568517 EX_ROW_EN[1] = 0x0
5938 20:11:35.571995 LP4Y_EN = 0x0
5939 20:11:35.572076 WORK_FSP = 0x0
5940 20:11:35.575403 WL = 0x2
5941 20:11:35.578525 RL = 0x2
5942 20:11:35.578606 BL = 0x2
5943 20:11:35.581924 RPST = 0x0
5944 20:11:35.582005 RD_PRE = 0x0
5945 20:11:35.584919 WR_PRE = 0x1
5946 20:11:35.585000 WR_PST = 0x0
5947 20:11:35.588145 DBI_WR = 0x0
5948 20:11:35.588256 DBI_RD = 0x0
5949 20:11:35.591378 OTF = 0x1
5950 20:11:35.595352 ===================================
5951 20:11:35.598394 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5952 20:11:35.601493 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5953 20:11:35.608446 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5954 20:11:35.611165 ===================================
5955 20:11:35.611247 LPDDR4 DRAM CONFIGURATION
5956 20:11:35.615063 ===================================
5957 20:11:35.617852 EX_ROW_EN[0] = 0x10
5958 20:11:35.617933 EX_ROW_EN[1] = 0x0
5959 20:11:35.621322 LP4Y_EN = 0x0
5960 20:11:35.621403 WORK_FSP = 0x0
5961 20:11:35.624813 WL = 0x2
5962 20:11:35.628766 RL = 0x2
5963 20:11:35.628847 BL = 0x2
5964 20:11:35.631381 RPST = 0x0
5965 20:11:35.631462 RD_PRE = 0x0
5966 20:11:35.634630 WR_PRE = 0x1
5967 20:11:35.634710 WR_PST = 0x0
5968 20:11:35.638238 DBI_WR = 0x0
5969 20:11:35.638319 DBI_RD = 0x0
5970 20:11:35.641248 OTF = 0x1
5971 20:11:35.644361 ===================================
5972 20:11:35.651361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5973 20:11:35.654125 nWR fixed to 30
5974 20:11:35.654206 [ModeRegInit_LP4] CH0 RK0
5975 20:11:35.657275 [ModeRegInit_LP4] CH0 RK1
5976 20:11:35.661196 [ModeRegInit_LP4] CH1 RK0
5977 20:11:35.661307 [ModeRegInit_LP4] CH1 RK1
5978 20:11:35.663964 match AC timing 18
5979 20:11:35.667265 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5980 20:11:35.674037 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5981 20:11:35.677450 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5982 20:11:35.680683 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5983 20:11:35.687121 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5984 20:11:35.687216 ==
5985 20:11:35.690526 Dram Type= 6, Freq= 0, CH_0, rank 0
5986 20:11:35.694391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5987 20:11:35.694473 ==
5988 20:11:35.700873 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5989 20:11:35.706961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5990 20:11:35.707043 [CA 0] Center 36 (8~64) winsize 57
5991 20:11:35.710833 [CA 1] Center 36 (8~64) winsize 57
5992 20:11:35.714084 [CA 2] Center 36 (8~64) winsize 57
5993 20:11:35.717030 [CA 3] Center 36 (8~64) winsize 57
5994 20:11:35.720221 [CA 4] Center 36 (8~64) winsize 57
5995 20:11:35.724022 [CA 5] Center 36 (8~64) winsize 57
5996 20:11:35.724103
5997 20:11:35.726995 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5998 20:11:35.727077
5999 20:11:35.730829 [CATrainingPosCal] consider 1 rank data
6000 20:11:35.733677 u2DelayCellTimex100 = 270/100 ps
6001 20:11:35.736669 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 20:11:35.743753 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6003 20:11:35.746879 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 20:11:35.750782 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 20:11:35.753580 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 20:11:35.757153 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 20:11:35.757234
6008 20:11:35.759963 CA PerBit enable=1, Macro0, CA PI delay=36
6009 20:11:35.760044
6010 20:11:35.763404 [CBTSetCACLKResult] CA Dly = 36
6011 20:11:35.766454 CS Dly: 1 (0~32)
6012 20:11:35.766535 ==
6013 20:11:35.770118 Dram Type= 6, Freq= 0, CH_0, rank 1
6014 20:11:35.773049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6015 20:11:35.773130 ==
6016 20:11:35.779749 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6017 20:11:35.783262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6018 20:11:35.786701 [CA 0] Center 36 (8~64) winsize 57
6019 20:11:35.790087 [CA 1] Center 36 (8~64) winsize 57
6020 20:11:35.793334 [CA 2] Center 36 (8~64) winsize 57
6021 20:11:35.796315 [CA 3] Center 36 (8~64) winsize 57
6022 20:11:35.799326 [CA 4] Center 36 (8~64) winsize 57
6023 20:11:35.803024 [CA 5] Center 36 (8~64) winsize 57
6024 20:11:35.803105
6025 20:11:35.806699 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6026 20:11:35.806781
6027 20:11:35.810078 [CATrainingPosCal] consider 2 rank data
6028 20:11:35.812552 u2DelayCellTimex100 = 270/100 ps
6029 20:11:35.816934 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 20:11:35.819721 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 20:11:35.823238 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 20:11:35.829146 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 20:11:35.833099 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 20:11:35.836742 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 20:11:35.836838
6036 20:11:35.839868 CA PerBit enable=1, Macro0, CA PI delay=36
6037 20:11:35.839974
6038 20:11:35.843212 [CBTSetCACLKResult] CA Dly = 36
6039 20:11:35.843323 CS Dly: 1 (0~32)
6040 20:11:35.843429
6041 20:11:35.845927 ----->DramcWriteLeveling(PI) begin...
6042 20:11:35.846100 ==
6043 20:11:35.849432 Dram Type= 6, Freq= 0, CH_0, rank 0
6044 20:11:35.856388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6045 20:11:35.856470 ==
6046 20:11:35.859883 Write leveling (Byte 0): 32 => 0
6047 20:11:35.862659 Write leveling (Byte 1): 32 => 0
6048 20:11:35.862740 DramcWriteLeveling(PI) end<-----
6049 20:11:35.862808
6050 20:11:35.865720 ==
6051 20:11:35.869449 Dram Type= 6, Freq= 0, CH_0, rank 0
6052 20:11:35.872501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6053 20:11:35.872582 ==
6054 20:11:35.876698 [Gating] SW mode calibration
6055 20:11:35.882407 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6056 20:11:35.885909 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6057 20:11:35.892750 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6058 20:11:35.895953 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6059 20:11:35.898910 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6060 20:11:35.905735 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6061 20:11:35.909229 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6062 20:11:35.913070 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6063 20:11:35.919357 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6064 20:11:35.922279 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6065 20:11:35.925410 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6066 20:11:35.929070 Total UI for P1: 0, mck2ui 16
6067 20:11:35.931931 best dqsien dly found for B0: ( 0, 10, 16)
6068 20:11:35.935573 Total UI for P1: 0, mck2ui 16
6069 20:11:35.938516 best dqsien dly found for B1: ( 0, 10, 16)
6070 20:11:35.942143 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6071 20:11:35.945665 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6072 20:11:35.945747
6073 20:11:35.951710 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6074 20:11:35.954874 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6075 20:11:35.958592 [Gating] SW calibration Done
6076 20:11:35.958673 ==
6077 20:11:35.961942 Dram Type= 6, Freq= 0, CH_0, rank 0
6078 20:11:35.964904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6079 20:11:35.964985 ==
6080 20:11:35.965049 RX Vref Scan: 0
6081 20:11:35.968454
6082 20:11:35.968535 RX Vref 0 -> 0, step: 1
6083 20:11:35.968599
6084 20:11:35.972155 RX Delay -410 -> 252, step: 16
6085 20:11:35.975331 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6086 20:11:35.982307 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6087 20:11:35.985492 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6088 20:11:35.988530 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6089 20:11:35.991455 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6090 20:11:35.998469 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6091 20:11:36.001823 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6092 20:11:36.005006 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6093 20:11:36.008082 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6094 20:11:36.015059 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6095 20:11:36.017898 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6096 20:11:36.021337 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6097 20:11:36.024675 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6098 20:11:36.031694 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6099 20:11:36.034986 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6100 20:11:36.037829 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6101 20:11:36.037911 ==
6102 20:11:36.041711 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 20:11:36.048083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 20:11:36.048164 ==
6105 20:11:36.048229 DQS Delay:
6106 20:11:36.051384 DQS0 = 51, DQS1 = 59
6107 20:11:36.051491 DQM Delay:
6108 20:11:36.051563 DQM0 = 12, DQM1 = 15
6109 20:11:36.054383 DQ Delay:
6110 20:11:36.057958 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6111 20:11:36.061478 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6112 20:11:36.061559 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6113 20:11:36.064529 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6114 20:11:36.067784
6115 20:11:36.067864
6116 20:11:36.067928 ==
6117 20:11:36.071088 Dram Type= 6, Freq= 0, CH_0, rank 0
6118 20:11:36.074551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6119 20:11:36.074632 ==
6120 20:11:36.074697
6121 20:11:36.074756
6122 20:11:36.077883 TX Vref Scan disable
6123 20:11:36.077981 == TX Byte 0 ==
6124 20:11:36.081163 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6125 20:11:36.087866 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6126 20:11:36.087948 == TX Byte 1 ==
6127 20:11:36.091033 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6128 20:11:36.098023 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6129 20:11:36.098104 ==
6130 20:11:36.101381 Dram Type= 6, Freq= 0, CH_0, rank 0
6131 20:11:36.104512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6132 20:11:36.104594 ==
6133 20:11:36.104689
6134 20:11:36.104803
6135 20:11:36.107499 TX Vref Scan disable
6136 20:11:36.107622 == TX Byte 0 ==
6137 20:11:36.114315 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6138 20:11:36.117519 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6139 20:11:36.117600 == TX Byte 1 ==
6140 20:11:36.124043 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6141 20:11:36.127482 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6142 20:11:36.127588
6143 20:11:36.127653 [DATLAT]
6144 20:11:36.130818 Freq=400, CH0 RK0
6145 20:11:36.130898
6146 20:11:36.130962 DATLAT Default: 0xf
6147 20:11:36.133916 0, 0xFFFF, sum = 0
6148 20:11:36.134006 1, 0xFFFF, sum = 0
6149 20:11:36.137503 2, 0xFFFF, sum = 0
6150 20:11:36.137584 3, 0xFFFF, sum = 0
6151 20:11:36.141113 4, 0xFFFF, sum = 0
6152 20:11:36.141211 5, 0xFFFF, sum = 0
6153 20:11:36.144027 6, 0xFFFF, sum = 0
6154 20:11:36.144109 7, 0xFFFF, sum = 0
6155 20:11:36.147085 8, 0xFFFF, sum = 0
6156 20:11:36.150690 9, 0xFFFF, sum = 0
6157 20:11:36.150772 10, 0xFFFF, sum = 0
6158 20:11:36.154055 11, 0xFFFF, sum = 0
6159 20:11:36.154137 12, 0x0, sum = 1
6160 20:11:36.157318 13, 0x0, sum = 2
6161 20:11:36.157400 14, 0x0, sum = 3
6162 20:11:36.157466 15, 0x0, sum = 4
6163 20:11:36.161269 best_step = 13
6164 20:11:36.161350
6165 20:11:36.161413 ==
6166 20:11:36.163888 Dram Type= 6, Freq= 0, CH_0, rank 0
6167 20:11:36.167136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6168 20:11:36.167217 ==
6169 20:11:36.170379 RX Vref Scan: 1
6170 20:11:36.170465
6171 20:11:36.173616 RX Vref 0 -> 0, step: 1
6172 20:11:36.173697
6173 20:11:36.173762 RX Delay -359 -> 252, step: 8
6174 20:11:36.173822
6175 20:11:36.177248 Set Vref, RX VrefLevel [Byte0]: 47
6176 20:11:36.181069 [Byte1]: 46
6177 20:11:36.186281
6178 20:11:36.186362 Final RX Vref Byte 0 = 47 to rank0
6179 20:11:36.189297 Final RX Vref Byte 1 = 46 to rank0
6180 20:11:36.192641 Final RX Vref Byte 0 = 47 to rank1
6181 20:11:36.195477 Final RX Vref Byte 1 = 46 to rank1==
6182 20:11:36.200110 Dram Type= 6, Freq= 0, CH_0, rank 0
6183 20:11:36.205402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6184 20:11:36.205524 ==
6185 20:11:36.205588 DQS Delay:
6186 20:11:36.209136 DQS0 = 52, DQS1 = 68
6187 20:11:36.209217 DQM Delay:
6188 20:11:36.209282 DQM0 = 9, DQM1 = 17
6189 20:11:36.211944 DQ Delay:
6190 20:11:36.215313 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6191 20:11:36.215394 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6192 20:11:36.218513 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6193 20:11:36.222638 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6194 20:11:36.222719
6195 20:11:36.225729
6196 20:11:36.232095 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6197 20:11:36.235053 CH0 RK0: MR19=C0C, MR18=A1A1
6198 20:11:36.241961 CH0_RK0: MR19=0xC0C, MR18=0xA1A1, DQSOSC=389, MR23=63, INC=390, DEC=260
6199 20:11:36.242046 ==
6200 20:11:36.245219 Dram Type= 6, Freq= 0, CH_0, rank 1
6201 20:11:36.249056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6202 20:11:36.249138 ==
6203 20:11:36.251851 [Gating] SW mode calibration
6204 20:11:36.258671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6205 20:11:36.266120 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6206 20:11:36.268676 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6207 20:11:36.271536 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6208 20:11:36.278273 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6209 20:11:36.281798 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6210 20:11:36.284793 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6211 20:11:36.291590 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6212 20:11:36.294750 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6213 20:11:36.298217 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6214 20:11:36.304929 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6215 20:11:36.305010 Total UI for P1: 0, mck2ui 16
6216 20:11:36.311428 best dqsien dly found for B0: ( 0, 10, 16)
6217 20:11:36.311509 Total UI for P1: 0, mck2ui 16
6218 20:11:36.314703 best dqsien dly found for B1: ( 0, 10, 16)
6219 20:11:36.321298 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6220 20:11:36.324642 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6221 20:11:36.324781
6222 20:11:36.327752 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6223 20:11:36.331598 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6224 20:11:36.334895 [Gating] SW calibration Done
6225 20:11:36.335018 ==
6226 20:11:36.337849 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 20:11:36.341497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6228 20:11:36.341631 ==
6229 20:11:36.344507 RX Vref Scan: 0
6230 20:11:36.344608
6231 20:11:36.344699 RX Vref 0 -> 0, step: 1
6232 20:11:36.344807
6233 20:11:36.347538 RX Delay -410 -> 252, step: 16
6234 20:11:36.355658 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6235 20:11:36.357808 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6236 20:11:36.361891 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6237 20:11:36.364261 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6238 20:11:36.370574 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6239 20:11:36.374082 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6240 20:11:36.378180 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6241 20:11:36.380581 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6242 20:11:36.387497 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6243 20:11:36.390402 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6244 20:11:36.393737 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6245 20:11:36.397373 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6246 20:11:36.403736 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6247 20:11:36.407016 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6248 20:11:36.411055 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6249 20:11:36.417471 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6250 20:11:36.417553 ==
6251 20:11:36.420817 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 20:11:36.423451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 20:11:36.423537 ==
6254 20:11:36.423602 DQS Delay:
6255 20:11:36.427805 DQS0 = 51, DQS1 = 59
6256 20:11:36.427886 DQM Delay:
6257 20:11:36.430443 DQM0 = 14, DQM1 = 15
6258 20:11:36.430555 DQ Delay:
6259 20:11:36.433996 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6260 20:11:36.436984 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6261 20:11:36.439992 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6262 20:11:36.443460 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6263 20:11:36.443541
6264 20:11:36.443605
6265 20:11:36.443664 ==
6266 20:11:36.446592 Dram Type= 6, Freq= 0, CH_0, rank 1
6267 20:11:36.450468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6268 20:11:36.450550 ==
6269 20:11:36.450614
6270 20:11:36.450673
6271 20:11:36.453438 TX Vref Scan disable
6272 20:11:36.453518 == TX Byte 0 ==
6273 20:11:36.460574 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6274 20:11:36.464740 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6275 20:11:36.464837 == TX Byte 1 ==
6276 20:11:36.470370 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6277 20:11:36.473067 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6278 20:11:36.473212 ==
6279 20:11:36.477026 Dram Type= 6, Freq= 0, CH_0, rank 1
6280 20:11:36.479854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6281 20:11:36.479939 ==
6282 20:11:36.480005
6283 20:11:36.480064
6284 20:11:36.483648 TX Vref Scan disable
6285 20:11:36.486307 == TX Byte 0 ==
6286 20:11:36.489878 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6287 20:11:36.492850 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6288 20:11:36.496198 == TX Byte 1 ==
6289 20:11:36.499370 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6290 20:11:36.503356 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6291 20:11:36.503437
6292 20:11:36.503502 [DATLAT]
6293 20:11:36.506205 Freq=400, CH0 RK1
6294 20:11:36.506286
6295 20:11:36.506349 DATLAT Default: 0xd
6296 20:11:36.509505 0, 0xFFFF, sum = 0
6297 20:11:36.509587 1, 0xFFFF, sum = 0
6298 20:11:36.513131 2, 0xFFFF, sum = 0
6299 20:11:36.516815 3, 0xFFFF, sum = 0
6300 20:11:36.516912 4, 0xFFFF, sum = 0
6301 20:11:36.519344 5, 0xFFFF, sum = 0
6302 20:11:36.519426 6, 0xFFFF, sum = 0
6303 20:11:36.523058 7, 0xFFFF, sum = 0
6304 20:11:36.523140 8, 0xFFFF, sum = 0
6305 20:11:36.525969 9, 0xFFFF, sum = 0
6306 20:11:36.526051 10, 0xFFFF, sum = 0
6307 20:11:36.529057 11, 0xFFFF, sum = 0
6308 20:11:36.529139 12, 0x0, sum = 1
6309 20:11:36.532340 13, 0x0, sum = 2
6310 20:11:36.532422 14, 0x0, sum = 3
6311 20:11:36.535670 15, 0x0, sum = 4
6312 20:11:36.535752 best_step = 13
6313 20:11:36.535816
6314 20:11:36.535875 ==
6315 20:11:36.539645 Dram Type= 6, Freq= 0, CH_0, rank 1
6316 20:11:36.543220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6317 20:11:36.545840 ==
6318 20:11:36.545949 RX Vref Scan: 0
6319 20:11:36.546044
6320 20:11:36.548958 RX Vref 0 -> 0, step: 1
6321 20:11:36.549038
6322 20:11:36.552598 RX Delay -359 -> 252, step: 8
6323 20:11:36.559261 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6324 20:11:36.562655 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6325 20:11:36.565728 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6326 20:11:36.569125 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6327 20:11:36.572412 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6328 20:11:36.579785 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6329 20:11:36.582581 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6330 20:11:36.585359 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6331 20:11:36.592210 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6332 20:11:36.595224 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6333 20:11:36.598774 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6334 20:11:36.602325 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6335 20:11:36.608394 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6336 20:11:36.612371 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6337 20:11:36.615690 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6338 20:11:36.618540 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6339 20:11:36.622445 ==
6340 20:11:36.625253 Dram Type= 6, Freq= 0, CH_0, rank 1
6341 20:11:36.628647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6342 20:11:36.628766 ==
6343 20:11:36.628831 DQS Delay:
6344 20:11:36.631674 DQS0 = 52, DQS1 = 64
6345 20:11:36.631753 DQM Delay:
6346 20:11:36.634959 DQM0 = 9, DQM1 = 13
6347 20:11:36.635055 DQ Delay:
6348 20:11:36.638813 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6349 20:11:36.641794 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6350 20:11:36.644679 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6351 20:11:36.648275 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6352 20:11:36.648355
6353 20:11:36.648418
6354 20:11:36.654847 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6355 20:11:36.658661 CH0 RK1: MR19=C0C, MR18=CDCD
6356 20:11:36.664951 CH0_RK1: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6357 20:11:36.668011 [RxdqsGatingPostProcess] freq 400
6358 20:11:36.671595 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6359 20:11:36.674735 Pre-setting of DQS Precalculation
6360 20:11:36.681029 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6361 20:11:36.681111 ==
6362 20:11:36.684623 Dram Type= 6, Freq= 0, CH_1, rank 0
6363 20:11:36.688489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6364 20:11:36.688570 ==
6365 20:11:36.694009 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6366 20:11:36.701167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6367 20:11:36.704209 [CA 0] Center 36 (8~64) winsize 57
6368 20:11:36.707663 [CA 1] Center 36 (8~64) winsize 57
6369 20:11:36.710605 [CA 2] Center 36 (8~64) winsize 57
6370 20:11:36.714161 [CA 3] Center 36 (8~64) winsize 57
6371 20:11:36.714242 [CA 4] Center 36 (8~64) winsize 57
6372 20:11:36.717923 [CA 5] Center 36 (8~64) winsize 57
6373 20:11:36.718005
6374 20:11:36.724720 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6375 20:11:36.724864
6376 20:11:36.727118 [CATrainingPosCal] consider 1 rank data
6377 20:11:36.730714 u2DelayCellTimex100 = 270/100 ps
6378 20:11:36.734286 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 20:11:36.737405 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 20:11:36.740918 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 20:11:36.744225 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 20:11:36.747115 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 20:11:36.750789 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 20:11:36.750869
6385 20:11:36.754130 CA PerBit enable=1, Macro0, CA PI delay=36
6386 20:11:36.754211
6387 20:11:36.757363 [CBTSetCACLKResult] CA Dly = 36
6388 20:11:36.760722 CS Dly: 1 (0~32)
6389 20:11:36.760847 ==
6390 20:11:36.763786 Dram Type= 6, Freq= 0, CH_1, rank 1
6391 20:11:36.767539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6392 20:11:36.767667 ==
6393 20:11:36.773712 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6394 20:11:36.780461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6395 20:11:36.783937 [CA 0] Center 36 (8~64) winsize 57
6396 20:11:36.784018 [CA 1] Center 36 (8~64) winsize 57
6397 20:11:36.787534 [CA 2] Center 36 (8~64) winsize 57
6398 20:11:36.789920 [CA 3] Center 36 (8~64) winsize 57
6399 20:11:36.794452 [CA 4] Center 36 (8~64) winsize 57
6400 20:11:36.798125 [CA 5] Center 36 (8~64) winsize 57
6401 20:11:36.798206
6402 20:11:36.799964 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6403 20:11:36.800046
6404 20:11:36.806736 [CATrainingPosCal] consider 2 rank data
6405 20:11:36.806817 u2DelayCellTimex100 = 270/100 ps
6406 20:11:36.809901 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 20:11:36.816686 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 20:11:36.819937 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 20:11:36.823977 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 20:11:36.826284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 20:11:36.829915 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 20:11:36.830013
6413 20:11:36.833075 CA PerBit enable=1, Macro0, CA PI delay=36
6414 20:11:36.833156
6415 20:11:36.836478 [CBTSetCACLKResult] CA Dly = 36
6416 20:11:36.839714 CS Dly: 1 (0~32)
6417 20:11:36.839793
6418 20:11:36.843259 ----->DramcWriteLeveling(PI) begin...
6419 20:11:36.843368 ==
6420 20:11:36.846187 Dram Type= 6, Freq= 0, CH_1, rank 0
6421 20:11:36.849831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6422 20:11:36.849914 ==
6423 20:11:36.852699 Write leveling (Byte 0): 32 => 0
6424 20:11:36.857034 Write leveling (Byte 1): 32 => 0
6425 20:11:36.859883 DramcWriteLeveling(PI) end<-----
6426 20:11:36.859964
6427 20:11:36.860028 ==
6428 20:11:36.862827 Dram Type= 6, Freq= 0, CH_1, rank 0
6429 20:11:36.866019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6430 20:11:36.866103 ==
6431 20:11:36.869690 [Gating] SW mode calibration
6432 20:11:36.875997 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 20:11:36.882775 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6434 20:11:36.885927 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 20:11:36.889502 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 20:11:36.896267 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 20:11:36.899389 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6438 20:11:36.902407 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 20:11:36.909407 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 20:11:36.912484 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 20:11:36.915827 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6442 20:11:36.922172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 20:11:36.922253 Total UI for P1: 0, mck2ui 16
6444 20:11:36.928912 best dqsien dly found for B0: ( 0, 10, 16)
6445 20:11:36.928994 Total UI for P1: 0, mck2ui 16
6446 20:11:36.935763 best dqsien dly found for B1: ( 0, 10, 16)
6447 20:11:36.939675 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6448 20:11:36.941902 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6449 20:11:36.942031
6450 20:11:36.945327 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6451 20:11:36.948891 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6452 20:11:36.951826 [Gating] SW calibration Done
6453 20:11:36.951906 ==
6454 20:11:36.955064 Dram Type= 6, Freq= 0, CH_1, rank 0
6455 20:11:36.958520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6456 20:11:36.958602 ==
6457 20:11:36.962098 RX Vref Scan: 0
6458 20:11:36.962179
6459 20:11:36.965167 RX Vref 0 -> 0, step: 1
6460 20:11:36.965247
6461 20:11:36.965311 RX Delay -410 -> 252, step: 16
6462 20:11:36.971911 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6463 20:11:36.975328 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6464 20:11:36.979159 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6465 20:11:36.985384 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6466 20:11:36.988338 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6467 20:11:36.991345 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6468 20:11:36.994973 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6469 20:11:37.001554 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6470 20:11:37.004543 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6471 20:11:37.008686 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6472 20:11:37.011658 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6473 20:11:37.018651 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6474 20:11:37.021324 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6475 20:11:37.024484 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6476 20:11:37.028048 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6477 20:11:37.034707 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6478 20:11:37.034789 ==
6479 20:11:37.037837 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 20:11:37.041055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 20:11:37.041164 ==
6482 20:11:37.041262 DQS Delay:
6483 20:11:37.044390 DQS0 = 43, DQS1 = 59
6484 20:11:37.044470 DQM Delay:
6485 20:11:37.048837 DQM0 = 6, DQM1 = 15
6486 20:11:37.048918 DQ Delay:
6487 20:11:37.051270 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6488 20:11:37.054401 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6489 20:11:37.057602 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6490 20:11:37.061335 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6491 20:11:37.061416
6492 20:11:37.061479
6493 20:11:37.061539 ==
6494 20:11:37.064552 Dram Type= 6, Freq= 0, CH_1, rank 0
6495 20:11:37.067566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6496 20:11:37.067659 ==
6497 20:11:37.067725
6498 20:11:37.067785
6499 20:11:37.070990 TX Vref Scan disable
6500 20:11:37.074091 == TX Byte 0 ==
6501 20:11:37.077654 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6502 20:11:37.081036 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6503 20:11:37.084363 == TX Byte 1 ==
6504 20:11:37.087518 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6505 20:11:37.091243 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6506 20:11:37.091324 ==
6507 20:11:37.094026 Dram Type= 6, Freq= 0, CH_1, rank 0
6508 20:11:37.097279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6509 20:11:37.101242 ==
6510 20:11:37.101322
6511 20:11:37.101420
6512 20:11:37.101511 TX Vref Scan disable
6513 20:11:37.104134 == TX Byte 0 ==
6514 20:11:37.108129 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6515 20:11:37.111064 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6516 20:11:37.114057 == TX Byte 1 ==
6517 20:11:37.117247 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6518 20:11:37.120991 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6519 20:11:37.121072
6520 20:11:37.124114 [DATLAT]
6521 20:11:37.124197 Freq=400, CH1 RK0
6522 20:11:37.124261
6523 20:11:37.127397 DATLAT Default: 0xf
6524 20:11:37.127478 0, 0xFFFF, sum = 0
6525 20:11:37.130339 1, 0xFFFF, sum = 0
6526 20:11:37.130421 2, 0xFFFF, sum = 0
6527 20:11:37.133742 3, 0xFFFF, sum = 0
6528 20:11:37.133854 4, 0xFFFF, sum = 0
6529 20:11:37.137254 5, 0xFFFF, sum = 0
6530 20:11:37.137336 6, 0xFFFF, sum = 0
6531 20:11:37.140764 7, 0xFFFF, sum = 0
6532 20:11:37.140847 8, 0xFFFF, sum = 0
6533 20:11:37.143946 9, 0xFFFF, sum = 0
6534 20:11:37.144029 10, 0xFFFF, sum = 0
6535 20:11:37.147430 11, 0xFFFF, sum = 0
6536 20:11:37.147512 12, 0x0, sum = 1
6537 20:11:37.150202 13, 0x0, sum = 2
6538 20:11:37.150284 14, 0x0, sum = 3
6539 20:11:37.153621 15, 0x0, sum = 4
6540 20:11:37.153703 best_step = 13
6541 20:11:37.153768
6542 20:11:37.153828 ==
6543 20:11:37.156838 Dram Type= 6, Freq= 0, CH_1, rank 0
6544 20:11:37.163369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6545 20:11:37.163450 ==
6546 20:11:37.163515 RX Vref Scan: 1
6547 20:11:37.163575
6548 20:11:37.167847 RX Vref 0 -> 0, step: 1
6549 20:11:37.167928
6550 20:11:37.170213 RX Delay -359 -> 252, step: 8
6551 20:11:37.170317
6552 20:11:37.173478 Set Vref, RX VrefLevel [Byte0]: 54
6553 20:11:37.177229 [Byte1]: 49
6554 20:11:37.180277
6555 20:11:37.180357 Final RX Vref Byte 0 = 54 to rank0
6556 20:11:37.183567 Final RX Vref Byte 1 = 49 to rank0
6557 20:11:37.186589 Final RX Vref Byte 0 = 54 to rank1
6558 20:11:37.190170 Final RX Vref Byte 1 = 49 to rank1==
6559 20:11:37.193849 Dram Type= 6, Freq= 0, CH_1, rank 0
6560 20:11:37.199978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6561 20:11:37.200077 ==
6562 20:11:37.200143 DQS Delay:
6563 20:11:37.203188 DQS0 = 48, DQS1 = 64
6564 20:11:37.203257 DQM Delay:
6565 20:11:37.203316 DQM0 = 8, DQM1 = 16
6566 20:11:37.206804 DQ Delay:
6567 20:11:37.210342 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6568 20:11:37.210418 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6569 20:11:37.213394 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6570 20:11:37.216496 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6571 20:11:37.216570
6572 20:11:37.216632
6573 20:11:37.226661 [DQSOSCAuto] RK0, (LSB)MR18= 0xd3d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6574 20:11:37.230861 CH1 RK0: MR19=C0C, MR18=D3D3
6575 20:11:37.236596 CH1_RK0: MR19=0xC0C, MR18=0xD3D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6576 20:11:37.236681 ==
6577 20:11:37.239824 Dram Type= 6, Freq= 0, CH_1, rank 1
6578 20:11:37.243355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6579 20:11:37.243452 ==
6580 20:11:37.246331 [Gating] SW mode calibration
6581 20:11:37.253529 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6582 20:11:37.256413 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6583 20:11:37.263418 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6584 20:11:37.266308 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6585 20:11:37.270242 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6586 20:11:37.276305 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6587 20:11:37.279821 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6588 20:11:37.283360 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6589 20:11:37.289633 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6590 20:11:37.292916 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6591 20:11:37.296097 Total UI for P1: 0, mck2ui 16
6592 20:11:37.299835 best dqsien dly found for B0: ( 0, 10, 8)
6593 20:11:37.302758 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6594 20:11:37.306315 Total UI for P1: 0, mck2ui 16
6595 20:11:37.309502 best dqsien dly found for B1: ( 0, 10, 16)
6596 20:11:37.312603 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6597 20:11:37.316326 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6598 20:11:37.319762
6599 20:11:37.322475 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6600 20:11:37.326055 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6601 20:11:37.329233 [Gating] SW calibration Done
6602 20:11:37.329314 ==
6603 20:11:37.332288 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 20:11:37.336236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6605 20:11:37.336318 ==
6606 20:11:37.336382 RX Vref Scan: 0
6607 20:11:37.340512
6608 20:11:37.340593 RX Vref 0 -> 0, step: 1
6609 20:11:37.340657
6610 20:11:37.342714 RX Delay -410 -> 252, step: 16
6611 20:11:37.345544 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6612 20:11:37.352196 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6613 20:11:37.356252 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6614 20:11:37.358939 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6615 20:11:37.362457 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6616 20:11:37.369107 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6617 20:11:37.372927 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6618 20:11:37.375409 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6619 20:11:37.379341 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6620 20:11:37.385651 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6621 20:11:37.388664 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6622 20:11:37.392299 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6623 20:11:37.395150 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6624 20:11:37.401935 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6625 20:11:37.406028 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6626 20:11:37.408366 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6627 20:11:37.408466 ==
6628 20:11:37.412102 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 20:11:37.418339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 20:11:37.418416 ==
6631 20:11:37.418483 DQS Delay:
6632 20:11:37.421720 DQS0 = 43, DQS1 = 59
6633 20:11:37.421801 DQM Delay:
6634 20:11:37.425080 DQM0 = 10, DQM1 = 18
6635 20:11:37.425161 DQ Delay:
6636 20:11:37.428190 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6637 20:11:37.432619 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6638 20:11:37.432700 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6639 20:11:37.435115 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6640 20:11:37.438426
6641 20:11:37.438506
6642 20:11:37.438571 ==
6643 20:11:37.441613 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 20:11:37.444909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6645 20:11:37.444990 ==
6646 20:11:37.445054
6647 20:11:37.445114
6648 20:11:37.447997 TX Vref Scan disable
6649 20:11:37.448078 == TX Byte 0 ==
6650 20:11:37.451551 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6651 20:11:37.458602 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6652 20:11:37.458684 == TX Byte 1 ==
6653 20:11:37.461774 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6654 20:11:37.468254 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6655 20:11:37.468335 ==
6656 20:11:37.471286 Dram Type= 6, Freq= 0, CH_1, rank 1
6657 20:11:37.474917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6658 20:11:37.474998 ==
6659 20:11:37.475062
6660 20:11:37.475121
6661 20:11:37.477948 TX Vref Scan disable
6662 20:11:37.478029 == TX Byte 0 ==
6663 20:11:37.481167 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6664 20:11:37.487728 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6665 20:11:37.487810 == TX Byte 1 ==
6666 20:11:37.491719 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6667 20:11:37.498041 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6668 20:11:37.498122
6669 20:11:37.498187 [DATLAT]
6670 20:11:37.501076 Freq=400, CH1 RK1
6671 20:11:37.501156
6672 20:11:37.501221 DATLAT Default: 0xd
6673 20:11:37.505169 0, 0xFFFF, sum = 0
6674 20:11:37.505251 1, 0xFFFF, sum = 0
6675 20:11:37.507831 2, 0xFFFF, sum = 0
6676 20:11:37.507913 3, 0xFFFF, sum = 0
6677 20:11:37.511349 4, 0xFFFF, sum = 0
6678 20:11:37.511458 5, 0xFFFF, sum = 0
6679 20:11:37.514644 6, 0xFFFF, sum = 0
6680 20:11:37.514769 7, 0xFFFF, sum = 0
6681 20:11:37.517539 8, 0xFFFF, sum = 0
6682 20:11:37.517621 9, 0xFFFF, sum = 0
6683 20:11:37.521565 10, 0xFFFF, sum = 0
6684 20:11:37.521647 11, 0xFFFF, sum = 0
6685 20:11:37.524538 12, 0x0, sum = 1
6686 20:11:37.524636 13, 0x0, sum = 2
6687 20:11:37.527582 14, 0x0, sum = 3
6688 20:11:37.527665 15, 0x0, sum = 4
6689 20:11:37.531227 best_step = 13
6690 20:11:37.531308
6691 20:11:37.531372 ==
6692 20:11:37.534342 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 20:11:37.538354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6694 20:11:37.538466 ==
6695 20:11:37.540958 RX Vref Scan: 0
6696 20:11:37.541058
6697 20:11:37.541156 RX Vref 0 -> 0, step: 1
6698 20:11:37.541231
6699 20:11:37.544138 RX Delay -359 -> 252, step: 8
6700 20:11:37.552602 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6701 20:11:37.555787 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6702 20:11:37.558933 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6703 20:11:37.562842 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6704 20:11:37.569241 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6705 20:11:37.572229 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6706 20:11:37.575567 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6707 20:11:37.579298 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6708 20:11:37.585395 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6709 20:11:37.588691 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6710 20:11:37.591735 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6711 20:11:37.598419 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6712 20:11:37.601971 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6713 20:11:37.605385 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6714 20:11:37.608610 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6715 20:11:37.615079 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6716 20:11:37.615186 ==
6717 20:11:37.619011 Dram Type= 6, Freq= 0, CH_1, rank 1
6718 20:11:37.621789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6719 20:11:37.621871 ==
6720 20:11:37.621935 DQS Delay:
6721 20:11:37.625286 DQS0 = 48, DQS1 = 64
6722 20:11:37.625366 DQM Delay:
6723 20:11:37.628235 DQM0 = 9, DQM1 = 15
6724 20:11:37.628315 DQ Delay:
6725 20:11:37.632092 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6726 20:11:37.635769 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6727 20:11:37.638527 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6728 20:11:37.641904 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6729 20:11:37.641990
6730 20:11:37.642054
6731 20:11:37.648431 [DQSOSCAuto] RK1, (LSB)MR18= 0xb4b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6732 20:11:37.652111 CH1 RK1: MR19=C0C, MR18=B4B4
6733 20:11:37.659176 CH1_RK1: MR19=0xC0C, MR18=0xB4B4, DQSOSC=387, MR23=63, INC=394, DEC=262
6734 20:11:37.662243 [RxdqsGatingPostProcess] freq 400
6735 20:11:37.668701 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6736 20:11:37.668821 Pre-setting of DQS Precalculation
6737 20:11:37.674716 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6738 20:11:37.681597 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6739 20:11:37.688261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6740 20:11:37.688370
6741 20:11:37.688462
6742 20:11:37.691507 [Calibration Summary] 800 Mbps
6743 20:11:37.694696 CH 0, Rank 0
6744 20:11:37.694777 SW Impedance : PASS
6745 20:11:37.698000 DUTY Scan : NO K
6746 20:11:37.701826 ZQ Calibration : PASS
6747 20:11:37.701907 Jitter Meter : NO K
6748 20:11:37.704542 CBT Training : PASS
6749 20:11:37.708218 Write leveling : PASS
6750 20:11:37.708298 RX DQS gating : PASS
6751 20:11:37.711482 RX DQ/DQS(RDDQC) : PASS
6752 20:11:37.711590 TX DQ/DQS : PASS
6753 20:11:37.714350 RX DATLAT : PASS
6754 20:11:37.718410 RX DQ/DQS(Engine): PASS
6755 20:11:37.718491 TX OE : NO K
6756 20:11:37.721731 All Pass.
6757 20:11:37.721811
6758 20:11:37.721875 CH 0, Rank 1
6759 20:11:37.724355 SW Impedance : PASS
6760 20:11:37.724436 DUTY Scan : NO K
6761 20:11:37.727722 ZQ Calibration : PASS
6762 20:11:37.730891 Jitter Meter : NO K
6763 20:11:37.730971 CBT Training : PASS
6764 20:11:37.735152 Write leveling : NO K
6765 20:11:37.737796 RX DQS gating : PASS
6766 20:11:37.737877 RX DQ/DQS(RDDQC) : PASS
6767 20:11:37.741189 TX DQ/DQS : PASS
6768 20:11:37.744157 RX DATLAT : PASS
6769 20:11:37.744238 RX DQ/DQS(Engine): PASS
6770 20:11:37.747501 TX OE : NO K
6771 20:11:37.747583 All Pass.
6772 20:11:37.747646
6773 20:11:37.751007 CH 1, Rank 0
6774 20:11:37.751088 SW Impedance : PASS
6775 20:11:37.754305 DUTY Scan : NO K
6776 20:11:37.757464 ZQ Calibration : PASS
6777 20:11:37.757545 Jitter Meter : NO K
6778 20:11:37.760662 CBT Training : PASS
6779 20:11:37.763971 Write leveling : PASS
6780 20:11:37.764051 RX DQS gating : PASS
6781 20:11:37.767997 RX DQ/DQS(RDDQC) : PASS
6782 20:11:37.770577 TX DQ/DQS : PASS
6783 20:11:37.770659 RX DATLAT : PASS
6784 20:11:37.774114 RX DQ/DQS(Engine): PASS
6785 20:11:37.777436 TX OE : NO K
6786 20:11:37.777517 All Pass.
6787 20:11:37.777581
6788 20:11:37.777641 CH 1, Rank 1
6789 20:11:37.780616 SW Impedance : PASS
6790 20:11:37.783649 DUTY Scan : NO K
6791 20:11:37.783729 ZQ Calibration : PASS
6792 20:11:37.787205 Jitter Meter : NO K
6793 20:11:37.787287 CBT Training : PASS
6794 20:11:37.790442 Write leveling : NO K
6795 20:11:37.793731 RX DQS gating : PASS
6796 20:11:37.793812 RX DQ/DQS(RDDQC) : PASS
6797 20:11:37.797593 TX DQ/DQS : PASS
6798 20:11:37.800441 RX DATLAT : PASS
6799 20:11:37.800522 RX DQ/DQS(Engine): PASS
6800 20:11:37.803690 TX OE : NO K
6801 20:11:37.803770 All Pass.
6802 20:11:37.803835
6803 20:11:37.807318 DramC Write-DBI off
6804 20:11:37.810527 PER_BANK_REFRESH: Hybrid Mode
6805 20:11:37.810608 TX_TRACKING: ON
6806 20:11:37.820557 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6807 20:11:37.823887 [FAST_K] Save calibration result to emmc
6808 20:11:37.827168 dramc_set_vcore_voltage set vcore to 725000
6809 20:11:37.830307 Read voltage for 1600, 0
6810 20:11:37.830387 Vio18 = 0
6811 20:11:37.830451 Vcore = 725000
6812 20:11:37.833393 Vdram = 0
6813 20:11:37.833473 Vddq = 0
6814 20:11:37.833537 Vmddr = 0
6815 20:11:37.839995 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6816 20:11:37.843803 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6817 20:11:37.846558 MEM_TYPE=3, freq_sel=13
6818 20:11:37.850222 sv_algorithm_assistance_LP4_3733
6819 20:11:37.853399 ============ PULL DRAM RESETB DOWN ============
6820 20:11:37.859964 ========== PULL DRAM RESETB DOWN end =========
6821 20:11:37.863070 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6822 20:11:37.866647 ===================================
6823 20:11:37.870143 LPDDR4 DRAM CONFIGURATION
6824 20:11:37.873152 ===================================
6825 20:11:37.873233 EX_ROW_EN[0] = 0x0
6826 20:11:37.876709 EX_ROW_EN[1] = 0x0
6827 20:11:37.876833 LP4Y_EN = 0x0
6828 20:11:37.879756 WORK_FSP = 0x1
6829 20:11:37.879837 WL = 0x5
6830 20:11:37.883089 RL = 0x5
6831 20:11:37.883169 BL = 0x2
6832 20:11:37.887013 RPST = 0x0
6833 20:11:37.890269 RD_PRE = 0x0
6834 20:11:37.890349 WR_PRE = 0x1
6835 20:11:37.893490 WR_PST = 0x1
6836 20:11:37.893571 DBI_WR = 0x0
6837 20:11:37.896210 DBI_RD = 0x0
6838 20:11:37.896300 OTF = 0x1
6839 20:11:37.899481 ===================================
6840 20:11:37.903827 ===================================
6841 20:11:37.907066 ANA top config
6842 20:11:37.909375 ===================================
6843 20:11:37.909456 DLL_ASYNC_EN = 0
6844 20:11:37.912615 ALL_SLAVE_EN = 0
6845 20:11:37.916101 NEW_RANK_MODE = 1
6846 20:11:37.919472 DLL_IDLE_MODE = 1
6847 20:11:37.919573 LP45_APHY_COMB_EN = 1
6848 20:11:37.922729 TX_ODT_DIS = 0
6849 20:11:37.926264 NEW_8X_MODE = 1
6850 20:11:37.929448 ===================================
6851 20:11:37.933003 ===================================
6852 20:11:37.936508 data_rate = 3200
6853 20:11:37.938961 CKR = 1
6854 20:11:37.942299 DQ_P2S_RATIO = 8
6855 20:11:37.945701 ===================================
6856 20:11:37.945783 CA_P2S_RATIO = 8
6857 20:11:37.949581 DQ_CA_OPEN = 0
6858 20:11:37.953001 DQ_SEMI_OPEN = 0
6859 20:11:37.955826 CA_SEMI_OPEN = 0
6860 20:11:37.959069 CA_FULL_RATE = 0
6861 20:11:37.962066 DQ_CKDIV4_EN = 0
6862 20:11:37.962161 CA_CKDIV4_EN = 0
6863 20:11:37.965519 CA_PREDIV_EN = 0
6864 20:11:37.968588 PH8_DLY = 12
6865 20:11:37.972130 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6866 20:11:37.975398 DQ_AAMCK_DIV = 4
6867 20:11:37.979278 CA_AAMCK_DIV = 4
6868 20:11:37.979359 CA_ADMCK_DIV = 4
6869 20:11:37.982656 DQ_TRACK_CA_EN = 0
6870 20:11:37.985207 CA_PICK = 1600
6871 20:11:37.988644 CA_MCKIO = 1600
6872 20:11:37.992209 MCKIO_SEMI = 0
6873 20:11:37.994848 PLL_FREQ = 3068
6874 20:11:37.998996 DQ_UI_PI_RATIO = 32
6875 20:11:38.001876 CA_UI_PI_RATIO = 0
6876 20:11:38.005017 ===================================
6877 20:11:38.008312 ===================================
6878 20:11:38.008419 memory_type:LPDDR4
6879 20:11:38.011857 GP_NUM : 10
6880 20:11:38.014866 SRAM_EN : 1
6881 20:11:38.014946 MD32_EN : 0
6882 20:11:38.018154 ===================================
6883 20:11:38.021752 [ANA_INIT] >>>>>>>>>>>>>>
6884 20:11:38.024837 <<<<<< [CONFIGURE PHASE]: ANA_TX
6885 20:11:38.027900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6886 20:11:38.031580 ===================================
6887 20:11:38.035213 data_rate = 3200,PCW = 0X7600
6888 20:11:38.037952 ===================================
6889 20:11:38.041462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6890 20:11:38.044664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6891 20:11:38.051214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6892 20:11:38.054320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6893 20:11:38.058177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6894 20:11:38.061060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6895 20:11:38.065012 [ANA_INIT] flow start
6896 20:11:38.067763 [ANA_INIT] PLL >>>>>>>>
6897 20:11:38.067836 [ANA_INIT] PLL <<<<<<<<
6898 20:11:38.071135 [ANA_INIT] MIDPI >>>>>>>>
6899 20:11:38.074444 [ANA_INIT] MIDPI <<<<<<<<
6900 20:11:38.078069 [ANA_INIT] DLL >>>>>>>>
6901 20:11:38.078175 [ANA_INIT] DLL <<<<<<<<
6902 20:11:38.081634 [ANA_INIT] flow end
6903 20:11:38.084041 ============ LP4 DIFF to SE enter ============
6904 20:11:38.088001 ============ LP4 DIFF to SE exit ============
6905 20:11:38.091016 [ANA_INIT] <<<<<<<<<<<<<
6906 20:11:38.094031 [Flow] Enable top DCM control >>>>>
6907 20:11:38.097645 [Flow] Enable top DCM control <<<<<
6908 20:11:38.100992 Enable DLL master slave shuffle
6909 20:11:38.107797 ==============================================================
6910 20:11:38.107878 Gating Mode config
6911 20:11:38.114332 ==============================================================
6912 20:11:38.114414 Config description:
6913 20:11:38.123759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6914 20:11:38.130639 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6915 20:11:38.137031 SELPH_MODE 0: By rank 1: By Phase
6916 20:11:38.140543 ==============================================================
6917 20:11:38.143617 GAT_TRACK_EN = 1
6918 20:11:38.147227 RX_GATING_MODE = 2
6919 20:11:38.150634 RX_GATING_TRACK_MODE = 2
6920 20:11:38.153515 SELPH_MODE = 1
6921 20:11:38.157030 PICG_EARLY_EN = 1
6922 20:11:38.160560 VALID_LAT_VALUE = 1
6923 20:11:38.167039 ==============================================================
6924 20:11:38.169812 Enter into Gating configuration >>>>
6925 20:11:38.173500 Exit from Gating configuration <<<<
6926 20:11:38.176905 Enter into DVFS_PRE_config >>>>>
6927 20:11:38.186674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6928 20:11:38.190280 Exit from DVFS_PRE_config <<<<<
6929 20:11:38.193375 Enter into PICG configuration >>>>
6930 20:11:38.196642 Exit from PICG configuration <<<<
6931 20:11:38.200116 [RX_INPUT] configuration >>>>>
6932 20:11:38.200196 [RX_INPUT] configuration <<<<<
6933 20:11:38.206322 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6934 20:11:38.213083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6935 20:11:38.216477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6936 20:11:38.223296 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6937 20:11:38.229997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6938 20:11:38.236388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6939 20:11:38.239418 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6940 20:11:38.242675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6941 20:11:38.249833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6942 20:11:38.253869 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6943 20:11:38.255861 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6944 20:11:38.262422 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6945 20:11:38.265975 ===================================
6946 20:11:38.266057 LPDDR4 DRAM CONFIGURATION
6947 20:11:38.269138 ===================================
6948 20:11:38.272625 EX_ROW_EN[0] = 0x0
6949 20:11:38.275471 EX_ROW_EN[1] = 0x0
6950 20:11:38.275552 LP4Y_EN = 0x0
6951 20:11:38.279250 WORK_FSP = 0x1
6952 20:11:38.279331 WL = 0x5
6953 20:11:38.283135 RL = 0x5
6954 20:11:38.283218 BL = 0x2
6955 20:11:38.285713 RPST = 0x0
6956 20:11:38.285820 RD_PRE = 0x0
6957 20:11:38.289471 WR_PRE = 0x1
6958 20:11:38.289577 WR_PST = 0x1
6959 20:11:38.292485 DBI_WR = 0x0
6960 20:11:38.292566 DBI_RD = 0x0
6961 20:11:38.296126 OTF = 0x1
6962 20:11:38.299447 ===================================
6963 20:11:38.302232 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6964 20:11:38.305747 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6965 20:11:38.312523 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6966 20:11:38.315500 ===================================
6967 20:11:38.315581 LPDDR4 DRAM CONFIGURATION
6968 20:11:38.318926 ===================================
6969 20:11:38.321916 EX_ROW_EN[0] = 0x10
6970 20:11:38.325210 EX_ROW_EN[1] = 0x0
6971 20:11:38.325290 LP4Y_EN = 0x0
6972 20:11:38.329038 WORK_FSP = 0x1
6973 20:11:38.329119 WL = 0x5
6974 20:11:38.331981 RL = 0x5
6975 20:11:38.332061 BL = 0x2
6976 20:11:38.335687 RPST = 0x0
6977 20:11:38.335787 RD_PRE = 0x0
6978 20:11:38.338737 WR_PRE = 0x1
6979 20:11:38.338835 WR_PST = 0x1
6980 20:11:38.341568 DBI_WR = 0x0
6981 20:11:38.341666 DBI_RD = 0x0
6982 20:11:38.345106 OTF = 0x1
6983 20:11:38.348566 ===================================
6984 20:11:38.354984 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6985 20:11:38.355105 ==
6986 20:11:38.358642 Dram Type= 6, Freq= 0, CH_0, rank 0
6987 20:11:38.361427 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6988 20:11:38.361530 ==
6989 20:11:38.365094 [Duty_Offset_Calibration]
6990 20:11:38.365171 B0:0 B1:2 CA:1
6991 20:11:38.365234
6992 20:11:38.369192 [DutyScan_Calibration_Flow] k_type=0
6993 20:11:38.379414
6994 20:11:38.379515 ==CLK 0==
6995 20:11:38.382642 Final CLK duty delay cell = 0
6996 20:11:38.385936 [0] MAX Duty = 5187%(X100), DQS PI = 24
6997 20:11:38.388923 [0] MIN Duty = 4938%(X100), DQS PI = 54
6998 20:11:38.392562 [0] AVG Duty = 5062%(X100)
6999 20:11:38.392661
7000 20:11:38.395493 CH0 CLK Duty spec in!! Max-Min= 249%
7001 20:11:38.398944 [DutyScan_Calibration_Flow] ====Done====
7002 20:11:38.399052
7003 20:11:38.402190 [DutyScan_Calibration_Flow] k_type=1
7004 20:11:38.419299
7005 20:11:38.419373 ==DQS 0 ==
7006 20:11:38.422601 Final DQS duty delay cell = 0
7007 20:11:38.425890 [0] MAX Duty = 5156%(X100), DQS PI = 30
7008 20:11:38.429145 [0] MIN Duty = 5031%(X100), DQS PI = 8
7009 20:11:38.429242 [0] AVG Duty = 5093%(X100)
7010 20:11:38.432081
7011 20:11:38.432179 ==DQS 1 ==
7012 20:11:38.435847 Final DQS duty delay cell = 0
7013 20:11:38.438846 [0] MAX Duty = 5031%(X100), DQS PI = 4
7014 20:11:38.441924 [0] MIN Duty = 4876%(X100), DQS PI = 16
7015 20:11:38.445705 [0] AVG Duty = 4953%(X100)
7016 20:11:38.445809
7017 20:11:38.448578 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7018 20:11:38.448678
7019 20:11:38.451849 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7020 20:11:38.455704 [DutyScan_Calibration_Flow] ====Done====
7021 20:11:38.455805
7022 20:11:38.458957 [DutyScan_Calibration_Flow] k_type=3
7023 20:11:38.476296
7024 20:11:38.476376 ==DQM 0 ==
7025 20:11:38.479753 Final DQM duty delay cell = 0
7026 20:11:38.482525 [0] MAX Duty = 5187%(X100), DQS PI = 22
7027 20:11:38.486073 [0] MIN Duty = 4907%(X100), DQS PI = 56
7028 20:11:38.489822 [0] AVG Duty = 5047%(X100)
7029 20:11:38.489903
7030 20:11:38.489966 ==DQM 1 ==
7031 20:11:38.492859 Final DQM duty delay cell = 0
7032 20:11:38.495864 [0] MAX Duty = 5031%(X100), DQS PI = 50
7033 20:11:38.499203 [0] MIN Duty = 4782%(X100), DQS PI = 16
7034 20:11:38.503096 [0] AVG Duty = 4906%(X100)
7035 20:11:38.503211
7036 20:11:38.505923 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7037 20:11:38.506004
7038 20:11:38.509287 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7039 20:11:38.512588 [DutyScan_Calibration_Flow] ====Done====
7040 20:11:38.512694
7041 20:11:38.516231 [DutyScan_Calibration_Flow] k_type=2
7042 20:11:38.532692
7043 20:11:38.532797 ==DQ 0 ==
7044 20:11:38.535523 Final DQ duty delay cell = 0
7045 20:11:38.539167 [0] MAX Duty = 5218%(X100), DQS PI = 18
7046 20:11:38.542150 [0] MIN Duty = 4938%(X100), DQS PI = 56
7047 20:11:38.542232 [0] AVG Duty = 5078%(X100)
7048 20:11:38.545674
7049 20:11:38.545754 ==DQ 1 ==
7050 20:11:38.549703 Final DQ duty delay cell = -4
7051 20:11:38.552400 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7052 20:11:38.556233 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7053 20:11:38.558853 [-4] AVG Duty = 4953%(X100)
7054 20:11:38.558934
7055 20:11:38.562036 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7056 20:11:38.562117
7057 20:11:38.565402 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7058 20:11:38.569317 [DutyScan_Calibration_Flow] ====Done====
7059 20:11:38.569398 ==
7060 20:11:38.571984 Dram Type= 6, Freq= 0, CH_1, rank 0
7061 20:11:38.575539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7062 20:11:38.575621 ==
7063 20:11:38.578958 [Duty_Offset_Calibration]
7064 20:11:38.579038 B0:0 B1:4 CA:-5
7065 20:11:38.579103
7066 20:11:38.582147 [DutyScan_Calibration_Flow] k_type=0
7067 20:11:38.593367
7068 20:11:38.593447 ==CLK 0==
7069 20:11:38.596976 Final CLK duty delay cell = 0
7070 20:11:38.599621 [0] MAX Duty = 5156%(X100), DQS PI = 20
7071 20:11:38.603139 [0] MIN Duty = 4906%(X100), DQS PI = 52
7072 20:11:38.603220 [0] AVG Duty = 5031%(X100)
7073 20:11:38.606512
7074 20:11:38.609762 CH1 CLK Duty spec in!! Max-Min= 250%
7075 20:11:38.613448 [DutyScan_Calibration_Flow] ====Done====
7076 20:11:38.613528
7077 20:11:38.616549 [DutyScan_Calibration_Flow] k_type=1
7078 20:11:38.632007
7079 20:11:38.632089 ==DQS 0 ==
7080 20:11:38.634966 Final DQS duty delay cell = 0
7081 20:11:38.639057 [0] MAX Duty = 5156%(X100), DQS PI = 18
7082 20:11:38.642185 [0] MIN Duty = 4876%(X100), DQS PI = 42
7083 20:11:38.645360 [0] AVG Duty = 5016%(X100)
7084 20:11:38.645468
7085 20:11:38.645559 ==DQS 1 ==
7086 20:11:38.648714 Final DQS duty delay cell = -4
7087 20:11:38.652362 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7088 20:11:38.655123 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7089 20:11:38.658955 [-4] AVG Duty = 4937%(X100)
7090 20:11:38.659038
7091 20:11:38.662168 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7092 20:11:38.662310
7093 20:11:38.665060 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7094 20:11:38.668126 [DutyScan_Calibration_Flow] ====Done====
7095 20:11:38.668207
7096 20:11:38.671683 [DutyScan_Calibration_Flow] k_type=3
7097 20:11:38.687508
7098 20:11:38.687588 ==DQM 0 ==
7099 20:11:38.690912 Final DQM duty delay cell = -4
7100 20:11:38.694145 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7101 20:11:38.697497 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7102 20:11:38.701149 [-4] AVG Duty = 4922%(X100)
7103 20:11:38.701230
7104 20:11:38.701294 ==DQM 1 ==
7105 20:11:38.704946 Final DQM duty delay cell = -4
7106 20:11:38.707524 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7107 20:11:38.710996 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7108 20:11:38.714311 [-4] AVG Duty = 4984%(X100)
7109 20:11:38.714392
7110 20:11:38.717891 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7111 20:11:38.717972
7112 20:11:38.720606 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7113 20:11:38.724527 [DutyScan_Calibration_Flow] ====Done====
7114 20:11:38.724608
7115 20:11:38.727608 [DutyScan_Calibration_Flow] k_type=2
7116 20:11:38.745455
7117 20:11:38.745538 ==DQ 0 ==
7118 20:11:38.748320 Final DQ duty delay cell = 0
7119 20:11:38.751594 [0] MAX Duty = 5093%(X100), DQS PI = 20
7120 20:11:38.755604 [0] MIN Duty = 4938%(X100), DQS PI = 46
7121 20:11:38.755684 [0] AVG Duty = 5015%(X100)
7122 20:11:38.758319
7123 20:11:38.758399 ==DQ 1 ==
7124 20:11:38.761865 Final DQ duty delay cell = 0
7125 20:11:38.764997 [0] MAX Duty = 5062%(X100), DQS PI = 6
7126 20:11:38.769009 [0] MIN Duty = 4876%(X100), DQS PI = 28
7127 20:11:38.769116 [0] AVG Duty = 4969%(X100)
7128 20:11:38.771762
7129 20:11:38.774793 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7130 20:11:38.774874
7131 20:11:38.778215 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7132 20:11:38.781385 [DutyScan_Calibration_Flow] ====Done====
7133 20:11:38.784527 nWR fixed to 30
7134 20:11:38.784634 [ModeRegInit_LP4] CH0 RK0
7135 20:11:38.788452 [ModeRegInit_LP4] CH0 RK1
7136 20:11:38.791653 [ModeRegInit_LP4] CH1 RK0
7137 20:11:38.794599 [ModeRegInit_LP4] CH1 RK1
7138 20:11:38.794680 match AC timing 4
7139 20:11:38.801274 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7140 20:11:38.805406 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7141 20:11:38.807740 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7142 20:11:38.814459 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7143 20:11:38.817670 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7144 20:11:38.817752 [MiockJmeterHQA]
7145 20:11:38.817815
7146 20:11:38.821097 [DramcMiockJmeter] u1RxGatingPI = 0
7147 20:11:38.824479 0 : 4252, 4027
7148 20:11:38.824562 4 : 4252, 4027
7149 20:11:38.827971 8 : 4364, 4137
7150 20:11:38.828052 12 : 4253, 4027
7151 20:11:38.828118 16 : 4363, 4137
7152 20:11:38.830887 20 : 4252, 4027
7153 20:11:38.830969 24 : 4363, 4137
7154 20:11:38.834530 28 : 4253, 4027
7155 20:11:38.834612 32 : 4253, 4026
7156 20:11:38.838297 36 : 4252, 4027
7157 20:11:38.838396 40 : 4252, 4027
7158 20:11:38.841485 44 : 4363, 4137
7159 20:11:38.841566 48 : 4250, 4027
7160 20:11:38.844489 52 : 4363, 4137
7161 20:11:38.844571 56 : 4250, 4027
7162 20:11:38.844636 60 : 4250, 4027
7163 20:11:38.848033 64 : 4250, 4026
7164 20:11:38.848115 68 : 4360, 4138
7165 20:11:38.851133 72 : 4250, 4027
7166 20:11:38.851215 76 : 4361, 4137
7167 20:11:38.853869 80 : 4250, 4026
7168 20:11:38.853951 84 : 4250, 4026
7169 20:11:38.854016 88 : 4250, 4027
7170 20:11:38.857608 92 : 4249, 4027
7171 20:11:38.857690 96 : 4361, 4137
7172 20:11:38.860596 100 : 4250, 2840
7173 20:11:38.860710 104 : 4250, 0
7174 20:11:38.863993 108 : 4250, 0
7175 20:11:38.864074 112 : 4252, 0
7176 20:11:38.864140 116 : 4250, 0
7177 20:11:38.867962 120 : 4361, 0
7178 20:11:38.868044 124 : 4360, 0
7179 20:11:38.870863 128 : 4360, 0
7180 20:11:38.870945 132 : 4250, 0
7181 20:11:38.871009 136 : 4251, 0
7182 20:11:38.874274 140 : 4250, 0
7183 20:11:38.874355 144 : 4250, 0
7184 20:11:38.877219 148 : 4250, 0
7185 20:11:38.877328 152 : 4250, 0
7186 20:11:38.877422 156 : 4253, 0
7187 20:11:38.880630 160 : 4360, 0
7188 20:11:38.880773 164 : 4250, 0
7189 20:11:38.880840 168 : 4250, 0
7190 20:11:38.884099 172 : 4250, 0
7191 20:11:38.884181 176 : 4361, 0
7192 20:11:38.887509 180 : 4361, 0
7193 20:11:38.887592 184 : 4250, 0
7194 20:11:38.887657 188 : 4250, 0
7195 20:11:38.890632 192 : 4250, 0
7196 20:11:38.890714 196 : 4250, 0
7197 20:11:38.893658 200 : 4250, 0
7198 20:11:38.893740 204 : 4250, 0
7199 20:11:38.893805 208 : 4250, 0
7200 20:11:38.897216 212 : 4360, 0
7201 20:11:38.897298 216 : 4250, 0
7202 20:11:38.901083 220 : 4250, 427
7203 20:11:38.901165 224 : 4361, 4091
7204 20:11:38.904631 228 : 4361, 4137
7205 20:11:38.904737 232 : 4250, 4027
7206 20:11:38.904819 236 : 4361, 4138
7207 20:11:38.906919 240 : 4361, 4137
7208 20:11:38.907001 244 : 4250, 4027
7209 20:11:38.910504 248 : 4250, 4026
7210 20:11:38.910585 252 : 4250, 4027
7211 20:11:38.913521 256 : 4250, 4026
7212 20:11:38.913603 260 : 4250, 4027
7213 20:11:38.917629 264 : 4250, 4027
7214 20:11:38.917711 268 : 4249, 4027
7215 20:11:38.920333 272 : 4250, 4026
7216 20:11:38.920415 276 : 4361, 4137
7217 20:11:38.923650 280 : 4360, 4137
7218 20:11:38.923731 284 : 4247, 4024
7219 20:11:38.927331 288 : 4360, 4137
7220 20:11:38.927412 292 : 4361, 4138
7221 20:11:38.930272 296 : 4250, 4027
7222 20:11:38.930355 300 : 4250, 4027
7223 20:11:38.930420 304 : 4249, 4027
7224 20:11:38.933351 308 : 4250, 4026
7225 20:11:38.933433 312 : 4250, 4027
7226 20:11:38.937377 316 : 4250, 4027
7227 20:11:38.937486 320 : 4250, 4027
7228 20:11:38.940501 324 : 4250, 4026
7229 20:11:38.940583 328 : 4361, 4137
7230 20:11:38.943518 332 : 4360, 4138
7231 20:11:38.943599 336 : 4251, 3968
7232 20:11:38.946601 340 : 4360, 1979
7233 20:11:38.946684
7234 20:11:38.946747 MIOCK jitter meter ch=0
7235 20:11:38.946807
7236 20:11:38.950585 1T = (340-104) = 236 dly cells
7237 20:11:38.956995 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7238 20:11:38.957102 ==
7239 20:11:38.959779 Dram Type= 6, Freq= 0, CH_0, rank 0
7240 20:11:38.963475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7241 20:11:38.963556 ==
7242 20:11:38.970223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7243 20:11:38.973498 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7244 20:11:38.980302 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7245 20:11:38.983108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7246 20:11:38.992529 [CA 0] Center 42 (12~73) winsize 62
7247 20:11:38.995584 [CA 1] Center 42 (12~73) winsize 62
7248 20:11:38.999413 [CA 2] Center 39 (9~69) winsize 61
7249 20:11:39.002447 [CA 3] Center 38 (9~68) winsize 60
7250 20:11:39.005863 [CA 4] Center 37 (7~67) winsize 61
7251 20:11:39.008989 [CA 5] Center 36 (6~66) winsize 61
7252 20:11:39.009070
7253 20:11:39.012115 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7254 20:11:39.012195
7255 20:11:39.015319 [CATrainingPosCal] consider 1 rank data
7256 20:11:39.018847 u2DelayCellTimex100 = 275/100 ps
7257 20:11:39.025635 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7258 20:11:39.028962 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7259 20:11:39.032764 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7260 20:11:39.035341 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7261 20:11:39.039063 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7262 20:11:39.043007 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7263 20:11:39.043088
7264 20:11:39.045164 CA PerBit enable=1, Macro0, CA PI delay=36
7265 20:11:39.045245
7266 20:11:39.048424 [CBTSetCACLKResult] CA Dly = 36
7267 20:11:39.052020 CS Dly: 10 (0~41)
7268 20:11:39.055036 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7269 20:11:39.058442 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7270 20:11:39.058523 ==
7271 20:11:39.062201 Dram Type= 6, Freq= 0, CH_0, rank 1
7272 20:11:39.068403 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7273 20:11:39.068485 ==
7274 20:11:39.071894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7275 20:11:39.078739 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7276 20:11:39.082135 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7277 20:11:39.088423 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7278 20:11:39.095115 [CA 0] Center 42 (12~73) winsize 62
7279 20:11:39.098339 [CA 1] Center 42 (12~73) winsize 62
7280 20:11:39.101878 [CA 2] Center 38 (9~68) winsize 60
7281 20:11:39.104971 [CA 3] Center 38 (9~67) winsize 59
7282 20:11:39.108532 [CA 4] Center 36 (6~66) winsize 61
7283 20:11:39.112210 [CA 5] Center 36 (6~66) winsize 61
7284 20:11:39.112290
7285 20:11:39.115161 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7286 20:11:39.115275
7287 20:11:39.118269 [CATrainingPosCal] consider 2 rank data
7288 20:11:39.121779 u2DelayCellTimex100 = 275/100 ps
7289 20:11:39.125391 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7290 20:11:39.131555 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7291 20:11:39.135410 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7292 20:11:39.138288 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7293 20:11:39.142087 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7294 20:11:39.145249 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7295 20:11:39.145325
7296 20:11:39.148070 CA PerBit enable=1, Macro0, CA PI delay=36
7297 20:11:39.148187
7298 20:11:39.151492 [CBTSetCACLKResult] CA Dly = 36
7299 20:11:39.154719 CS Dly: 10 (0~42)
7300 20:11:39.158152 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7301 20:11:39.161837 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7302 20:11:39.161918
7303 20:11:39.164654 ----->DramcWriteLeveling(PI) begin...
7304 20:11:39.164758 ==
7305 20:11:39.167889 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 20:11:39.175255 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7307 20:11:39.175336 ==
7308 20:11:39.177692 Write leveling (Byte 0): 29 => 29
7309 20:11:39.177772 Write leveling (Byte 1): 26 => 26
7310 20:11:39.181636 DramcWriteLeveling(PI) end<-----
7311 20:11:39.181731
7312 20:11:39.184719 ==
7313 20:11:39.187873 Dram Type= 6, Freq= 0, CH_0, rank 0
7314 20:11:39.191375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7315 20:11:39.191455 ==
7316 20:11:39.194367 [Gating] SW mode calibration
7317 20:11:39.201103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7318 20:11:39.204236 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7319 20:11:39.210959 0 12 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7320 20:11:39.214567 0 12 4 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
7321 20:11:39.217635 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7322 20:11:39.224219 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7323 20:11:39.227817 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 20:11:39.230712 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 20:11:39.237991 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 20:11:39.241028 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 20:11:39.243982 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
7328 20:11:39.250700 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7329 20:11:39.253871 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7330 20:11:39.257780 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7331 20:11:39.263950 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7332 20:11:39.267686 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 20:11:39.271006 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 20:11:39.277307 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 20:11:39.280161 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7336 20:11:39.283813 0 14 4 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
7337 20:11:39.290948 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 20:11:39.293770 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 20:11:39.297080 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 20:11:39.303732 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 20:11:39.307187 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 20:11:39.310435 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7343 20:11:39.317110 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7344 20:11:39.320284 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7345 20:11:39.323277 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7346 20:11:39.329969 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 20:11:39.333346 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 20:11:39.336626 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 20:11:39.343407 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 20:11:39.347610 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 20:11:39.350064 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 20:11:39.356615 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 20:11:39.360321 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 20:11:39.363095 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 20:11:39.366818 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 20:11:39.373327 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 20:11:39.376567 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7358 20:11:39.380194 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 20:11:39.386241 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7360 20:11:39.390156 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7361 20:11:39.392894 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7362 20:11:39.396791 Total UI for P1: 0, mck2ui 16
7363 20:11:39.399962 best dqsien dly found for B0: ( 1, 1, 2)
7364 20:11:39.402942 Total UI for P1: 0, mck2ui 16
7365 20:11:39.406073 best dqsien dly found for B1: ( 1, 1, 4)
7366 20:11:39.409317 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7367 20:11:39.413057 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7368 20:11:39.413138
7369 20:11:39.419179 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7370 20:11:39.422796 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7371 20:11:39.425832 [Gating] SW calibration Done
7372 20:11:39.425912 ==
7373 20:11:39.429335 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 20:11:39.432615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 20:11:39.432696 ==
7376 20:11:39.432798 RX Vref Scan: 0
7377 20:11:39.432859
7378 20:11:39.436181 RX Vref 0 -> 0, step: 1
7379 20:11:39.436262
7380 20:11:39.439532 RX Delay 0 -> 252, step: 8
7381 20:11:39.442868 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7382 20:11:39.445792 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7383 20:11:39.450440 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7384 20:11:39.455981 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7385 20:11:39.459192 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7386 20:11:39.462901 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7387 20:11:39.465602 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7388 20:11:39.469550 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7389 20:11:39.475795 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7390 20:11:39.479419 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7391 20:11:39.482482 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7392 20:11:39.485528 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7393 20:11:39.492725 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7394 20:11:39.496136 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7395 20:11:39.499334 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7396 20:11:39.502252 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7397 20:11:39.502351 ==
7398 20:11:39.505698 Dram Type= 6, Freq= 0, CH_0, rank 0
7399 20:11:39.509080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7400 20:11:39.512462 ==
7401 20:11:39.512562 DQS Delay:
7402 20:11:39.512655 DQS0 = 0, DQS1 = 0
7403 20:11:39.515496 DQM Delay:
7404 20:11:39.515594 DQM0 = 129, DQM1 = 124
7405 20:11:39.519495 DQ Delay:
7406 20:11:39.522479 DQ0 =123, DQ1 =131, DQ2 =123, DQ3 =127
7407 20:11:39.525571 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7408 20:11:39.528681 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7409 20:11:39.532085 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7410 20:11:39.532156
7411 20:11:39.532217
7412 20:11:39.532303 ==
7413 20:11:39.535238 Dram Type= 6, Freq= 0, CH_0, rank 0
7414 20:11:39.538689 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7415 20:11:39.538767 ==
7416 20:11:39.542144
7417 20:11:39.542243
7418 20:11:39.542333 TX Vref Scan disable
7419 20:11:39.545531 == TX Byte 0 ==
7420 20:11:39.548435 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7421 20:11:39.551848 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7422 20:11:39.555763 == TX Byte 1 ==
7423 20:11:39.559680 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7424 20:11:39.561904 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7425 20:11:39.562002 ==
7426 20:11:39.565409 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 20:11:39.571913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 20:11:39.572011 ==
7429 20:11:39.584937
7430 20:11:39.588192 TX Vref early break, caculate TX vref
7431 20:11:39.591571 TX Vref=16, minBit 8, minWin=21, winSum=371
7432 20:11:39.595408 TX Vref=18, minBit 8, minWin=22, winSum=381
7433 20:11:39.598564 TX Vref=20, minBit 8, minWin=23, winSum=388
7434 20:11:39.601677 TX Vref=22, minBit 8, minWin=23, winSum=399
7435 20:11:39.604626 TX Vref=24, minBit 9, minWin=24, winSum=405
7436 20:11:39.611284 TX Vref=26, minBit 8, minWin=24, winSum=413
7437 20:11:39.615213 TX Vref=28, minBit 3, minWin=25, winSum=414
7438 20:11:39.618161 TX Vref=30, minBit 1, minWin=25, winSum=407
7439 20:11:39.621570 TX Vref=32, minBit 6, minWin=24, winSum=400
7440 20:11:39.624895 TX Vref=34, minBit 8, minWin=23, winSum=394
7441 20:11:39.628459 TX Vref=36, minBit 8, minWin=22, winSum=383
7442 20:11:39.634266 [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 28
7443 20:11:39.634381
7444 20:11:39.637856 Final TX Range 0 Vref 28
7445 20:11:39.637939
7446 20:11:39.638034 ==
7447 20:11:39.641169 Dram Type= 6, Freq= 0, CH_0, rank 0
7448 20:11:39.644408 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7449 20:11:39.644489 ==
7450 20:11:39.644572
7451 20:11:39.647561
7452 20:11:39.647659 TX Vref Scan disable
7453 20:11:39.654113 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7454 20:11:39.654211 == TX Byte 0 ==
7455 20:11:39.657964 u2DelayCellOfst[0]=14 cells (4 PI)
7456 20:11:39.661332 u2DelayCellOfst[1]=17 cells (5 PI)
7457 20:11:39.664919 u2DelayCellOfst[2]=14 cells (4 PI)
7458 20:11:39.667990 u2DelayCellOfst[3]=10 cells (3 PI)
7459 20:11:39.670811 u2DelayCellOfst[4]=10 cells (3 PI)
7460 20:11:39.674821 u2DelayCellOfst[5]=0 cells (0 PI)
7461 20:11:39.677426 u2DelayCellOfst[6]=17 cells (5 PI)
7462 20:11:39.680865 u2DelayCellOfst[7]=17 cells (5 PI)
7463 20:11:39.684415 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7464 20:11:39.687670 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7465 20:11:39.690636 == TX Byte 1 ==
7466 20:11:39.694028 u2DelayCellOfst[8]=3 cells (1 PI)
7467 20:11:39.697520 u2DelayCellOfst[9]=0 cells (0 PI)
7468 20:11:39.701401 u2DelayCellOfst[10]=10 cells (3 PI)
7469 20:11:39.703935 u2DelayCellOfst[11]=3 cells (1 PI)
7470 20:11:39.707185 u2DelayCellOfst[12]=17 cells (5 PI)
7471 20:11:39.707266 u2DelayCellOfst[13]=14 cells (4 PI)
7472 20:11:39.710639 u2DelayCellOfst[14]=17 cells (5 PI)
7473 20:11:39.713706 u2DelayCellOfst[15]=14 cells (4 PI)
7474 20:11:39.720695 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7475 20:11:39.723878 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7476 20:11:39.727147 DramC Write-DBI on
7477 20:11:39.727244 ==
7478 20:11:39.730269 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 20:11:39.733397 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7480 20:11:39.733496 ==
7481 20:11:39.733593
7482 20:11:39.733668
7483 20:11:39.737363 TX Vref Scan disable
7484 20:11:39.737460 == TX Byte 0 ==
7485 20:11:39.743859 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7486 20:11:39.743965 == TX Byte 1 ==
7487 20:11:39.746801 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7488 20:11:39.750635 DramC Write-DBI off
7489 20:11:39.750739
7490 20:11:39.750830 [DATLAT]
7491 20:11:39.753622 Freq=1600, CH0 RK0
7492 20:11:39.753693
7493 20:11:39.753753 DATLAT Default: 0xf
7494 20:11:39.756827 0, 0xFFFF, sum = 0
7495 20:11:39.756900 1, 0xFFFF, sum = 0
7496 20:11:39.760150 2, 0xFFFF, sum = 0
7497 20:11:39.760250 3, 0xFFFF, sum = 0
7498 20:11:39.763336 4, 0xFFFF, sum = 0
7499 20:11:39.766467 5, 0xFFFF, sum = 0
7500 20:11:39.766543 6, 0xFFFF, sum = 0
7501 20:11:39.769624 7, 0xFFFF, sum = 0
7502 20:11:39.769701 8, 0xFFFF, sum = 0
7503 20:11:39.773050 9, 0xFFFF, sum = 0
7504 20:11:39.773122 10, 0xFFFF, sum = 0
7505 20:11:39.776931 11, 0xFFFF, sum = 0
7506 20:11:39.777002 12, 0xFFF, sum = 0
7507 20:11:39.780189 13, 0x0, sum = 1
7508 20:11:39.780284 14, 0x0, sum = 2
7509 20:11:39.782741 15, 0x0, sum = 3
7510 20:11:39.782815 16, 0x0, sum = 4
7511 20:11:39.786637 best_step = 14
7512 20:11:39.786712
7513 20:11:39.786772 ==
7514 20:11:39.789773 Dram Type= 6, Freq= 0, CH_0, rank 0
7515 20:11:39.792607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7516 20:11:39.792677 ==
7517 20:11:39.792784 RX Vref Scan: 1
7518 20:11:39.796058
7519 20:11:39.796122 Set Vref Range= 24 -> 127
7520 20:11:39.796179
7521 20:11:39.799853 RX Vref 24 -> 127, step: 1
7522 20:11:39.799921
7523 20:11:39.802807 RX Delay 11 -> 252, step: 4
7524 20:11:39.802875
7525 20:11:39.806278 Set Vref, RX VrefLevel [Byte0]: 24
7526 20:11:39.809488 [Byte1]: 24
7527 20:11:39.809557
7528 20:11:39.812585 Set Vref, RX VrefLevel [Byte0]: 25
7529 20:11:39.815783 [Byte1]: 25
7530 20:11:39.815849
7531 20:11:39.819296 Set Vref, RX VrefLevel [Byte0]: 26
7532 20:11:39.822629 [Byte1]: 26
7533 20:11:39.826761
7534 20:11:39.826834 Set Vref, RX VrefLevel [Byte0]: 27
7535 20:11:39.830636 [Byte1]: 27
7536 20:11:39.834442
7537 20:11:39.834544 Set Vref, RX VrefLevel [Byte0]: 28
7538 20:11:39.838215 [Byte1]: 28
7539 20:11:39.842006
7540 20:11:39.842080 Set Vref, RX VrefLevel [Byte0]: 29
7541 20:11:39.845549 [Byte1]: 29
7542 20:11:39.850012
7543 20:11:39.850090 Set Vref, RX VrefLevel [Byte0]: 30
7544 20:11:39.853002 [Byte1]: 30
7545 20:11:39.857290
7546 20:11:39.860425 Set Vref, RX VrefLevel [Byte0]: 31
7547 20:11:39.863775 [Byte1]: 31
7548 20:11:39.863873
7549 20:11:39.866923 Set Vref, RX VrefLevel [Byte0]: 32
7550 20:11:39.870222 [Byte1]: 32
7551 20:11:39.870301
7552 20:11:39.873639 Set Vref, RX VrefLevel [Byte0]: 33
7553 20:11:39.876836 [Byte1]: 33
7554 20:11:39.876913
7555 20:11:39.880650 Set Vref, RX VrefLevel [Byte0]: 34
7556 20:11:39.883567 [Byte1]: 34
7557 20:11:39.887435
7558 20:11:39.887513 Set Vref, RX VrefLevel [Byte0]: 35
7559 20:11:39.890961 [Byte1]: 35
7560 20:11:39.895435
7561 20:11:39.895543 Set Vref, RX VrefLevel [Byte0]: 36
7562 20:11:39.898285 [Byte1]: 36
7563 20:11:39.902848
7564 20:11:39.902943 Set Vref, RX VrefLevel [Byte0]: 37
7565 20:11:39.906295 [Byte1]: 37
7566 20:11:39.910854
7567 20:11:39.911018 Set Vref, RX VrefLevel [Byte0]: 38
7568 20:11:39.913893 [Byte1]: 38
7569 20:11:39.918309
7570 20:11:39.918375 Set Vref, RX VrefLevel [Byte0]: 39
7571 20:11:39.921280 [Byte1]: 39
7572 20:11:39.925716
7573 20:11:39.925788 Set Vref, RX VrefLevel [Byte0]: 40
7574 20:11:39.929105 [Byte1]: 40
7575 20:11:39.933498
7576 20:11:39.933594 Set Vref, RX VrefLevel [Byte0]: 41
7577 20:11:39.936965 [Byte1]: 41
7578 20:11:39.940914
7579 20:11:39.941032 Set Vref, RX VrefLevel [Byte0]: 42
7580 20:11:39.944320 [Byte1]: 42
7581 20:11:39.948240
7582 20:11:39.948347 Set Vref, RX VrefLevel [Byte0]: 43
7583 20:11:39.952045 [Byte1]: 43
7584 20:11:39.956075
7585 20:11:39.959457 Set Vref, RX VrefLevel [Byte0]: 44
7586 20:11:39.959560 [Byte1]: 44
7587 20:11:39.963568
7588 20:11:39.963669 Set Vref, RX VrefLevel [Byte0]: 45
7589 20:11:39.967064 [Byte1]: 45
7590 20:11:39.971319
7591 20:11:39.971420 Set Vref, RX VrefLevel [Byte0]: 46
7592 20:11:39.974502 [Byte1]: 46
7593 20:11:39.978952
7594 20:11:39.979054 Set Vref, RX VrefLevel [Byte0]: 47
7595 20:11:39.982537 [Byte1]: 47
7596 20:11:39.986715
7597 20:11:39.986791 Set Vref, RX VrefLevel [Byte0]: 48
7598 20:11:39.989939 [Byte1]: 48
7599 20:11:39.994902
7600 20:11:39.994979 Set Vref, RX VrefLevel [Byte0]: 49
7601 20:11:39.997587 [Byte1]: 49
7602 20:11:40.002078
7603 20:11:40.002181 Set Vref, RX VrefLevel [Byte0]: 50
7604 20:11:40.005344 [Byte1]: 50
7605 20:11:40.009444
7606 20:11:40.009521 Set Vref, RX VrefLevel [Byte0]: 51
7607 20:11:40.012610 [Byte1]: 51
7608 20:11:40.016694
7609 20:11:40.016805 Set Vref, RX VrefLevel [Byte0]: 52
7610 20:11:40.020307 [Byte1]: 52
7611 20:11:40.025222
7612 20:11:40.025300 Set Vref, RX VrefLevel [Byte0]: 53
7613 20:11:40.027706 [Byte1]: 53
7614 20:11:40.032830
7615 20:11:40.032938 Set Vref, RX VrefLevel [Byte0]: 54
7616 20:11:40.035966 [Byte1]: 54
7617 20:11:40.039946
7618 20:11:40.040052 Set Vref, RX VrefLevel [Byte0]: 55
7619 20:11:40.042820 [Byte1]: 55
7620 20:11:40.047411
7621 20:11:40.047490 Set Vref, RX VrefLevel [Byte0]: 56
7622 20:11:40.051121 [Byte1]: 56
7623 20:11:40.054920
7624 20:11:40.055026 Set Vref, RX VrefLevel [Byte0]: 57
7625 20:11:40.058428 [Byte1]: 57
7626 20:11:40.063095
7627 20:11:40.063195 Set Vref, RX VrefLevel [Byte0]: 58
7628 20:11:40.066592 [Byte1]: 58
7629 20:11:40.070582
7630 20:11:40.070681 Set Vref, RX VrefLevel [Byte0]: 59
7631 20:11:40.074412 [Byte1]: 59
7632 20:11:40.078027
7633 20:11:40.078099 Set Vref, RX VrefLevel [Byte0]: 60
7634 20:11:40.081516 [Byte1]: 60
7635 20:11:40.085492
7636 20:11:40.085590 Set Vref, RX VrefLevel [Byte0]: 61
7637 20:11:40.089474 [Byte1]: 61
7638 20:11:40.092976
7639 20:11:40.093055 Set Vref, RX VrefLevel [Byte0]: 62
7640 20:11:40.096778 [Byte1]: 62
7641 20:11:40.100617
7642 20:11:40.100724 Set Vref, RX VrefLevel [Byte0]: 63
7643 20:11:40.104459 [Byte1]: 63
7644 20:11:40.108298
7645 20:11:40.108396 Set Vref, RX VrefLevel [Byte0]: 64
7646 20:11:40.111649 [Byte1]: 64
7647 20:11:40.116177
7648 20:11:40.116254 Set Vref, RX VrefLevel [Byte0]: 65
7649 20:11:40.119172 [Byte1]: 65
7650 20:11:40.123564
7651 20:11:40.123667 Set Vref, RX VrefLevel [Byte0]: 66
7652 20:11:40.126652 [Byte1]: 66
7653 20:11:40.131718
7654 20:11:40.131819 Set Vref, RX VrefLevel [Byte0]: 67
7655 20:11:40.135205 [Byte1]: 67
7656 20:11:40.139300
7657 20:11:40.139419 Set Vref, RX VrefLevel [Byte0]: 68
7658 20:11:40.142006 [Byte1]: 68
7659 20:11:40.146311
7660 20:11:40.146419 Set Vref, RX VrefLevel [Byte0]: 69
7661 20:11:40.149590 [Byte1]: 69
7662 20:11:40.154686
7663 20:11:40.154788 Set Vref, RX VrefLevel [Byte0]: 70
7664 20:11:40.157568 [Byte1]: 70
7665 20:11:40.161647
7666 20:11:40.161742 Set Vref, RX VrefLevel [Byte0]: 71
7667 20:11:40.165221 [Byte1]: 71
7668 20:11:40.169504
7669 20:11:40.169574 Final RX Vref Byte 0 = 53 to rank0
7670 20:11:40.172526 Final RX Vref Byte 1 = 54 to rank0
7671 20:11:40.175987 Final RX Vref Byte 0 = 53 to rank1
7672 20:11:40.179084 Final RX Vref Byte 1 = 54 to rank1==
7673 20:11:40.182487 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 20:11:40.189026 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7675 20:11:40.189101 ==
7676 20:11:40.189163 DQS Delay:
7677 20:11:40.192293 DQS0 = 0, DQS1 = 0
7678 20:11:40.192367 DQM Delay:
7679 20:11:40.192427 DQM0 = 126, DQM1 = 121
7680 20:11:40.195661 DQ Delay:
7681 20:11:40.198574 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7682 20:11:40.202284 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7683 20:11:40.205740 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7684 20:11:40.208839 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7685 20:11:40.208911
7686 20:11:40.208974
7687 20:11:40.209031
7688 20:11:40.211910 [DramC_TX_OE_Calibration] TA2
7689 20:11:40.215700 Original DQ_B0 (3 6) =30, OEN = 27
7690 20:11:40.218891 Original DQ_B1 (3 6) =30, OEN = 27
7691 20:11:40.222058 24, 0x0, End_B0=24 End_B1=24
7692 20:11:40.222132 25, 0x0, End_B0=25 End_B1=25
7693 20:11:40.225301 26, 0x0, End_B0=26 End_B1=26
7694 20:11:40.229084 27, 0x0, End_B0=27 End_B1=27
7695 20:11:40.231908 28, 0x0, End_B0=28 End_B1=28
7696 20:11:40.235578 29, 0x0, End_B0=29 End_B1=29
7697 20:11:40.235680 30, 0x0, End_B0=30 End_B1=30
7698 20:11:40.238713 31, 0x4141, End_B0=30 End_B1=30
7699 20:11:40.242092 Byte0 end_step=30 best_step=27
7700 20:11:40.245948 Byte1 end_step=30 best_step=27
7701 20:11:40.248612 Byte0 TX OE(2T, 0.5T) = (3, 3)
7702 20:11:40.252069 Byte1 TX OE(2T, 0.5T) = (3, 3)
7703 20:11:40.252173
7704 20:11:40.252274
7705 20:11:40.258377 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7706 20:11:40.261601 CH0 RK0: MR19=303, MR18=1D1D
7707 20:11:40.269274 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7708 20:11:40.269348
7709 20:11:40.272056 ----->DramcWriteLeveling(PI) begin...
7710 20:11:40.272152 ==
7711 20:11:40.275269 Dram Type= 6, Freq= 0, CH_0, rank 1
7712 20:11:40.278535 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7713 20:11:40.278607 ==
7714 20:11:40.282206 Write leveling (Byte 0): 29 => 29
7715 20:11:40.284945 Write leveling (Byte 1): 26 => 26
7716 20:11:40.288616 DramcWriteLeveling(PI) end<-----
7717 20:11:40.288717
7718 20:11:40.288816 ==
7719 20:11:40.291963 Dram Type= 6, Freq= 0, CH_0, rank 1
7720 20:11:40.294940 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7721 20:11:40.295050 ==
7722 20:11:40.298504 [Gating] SW mode calibration
7723 20:11:40.305244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7724 20:11:40.311881 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7725 20:11:40.314929 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7726 20:11:40.321617 0 12 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7727 20:11:40.324918 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 20:11:40.328025 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 20:11:40.334797 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 20:11:40.338958 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 20:11:40.342249 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7732 20:11:40.348178 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7733 20:11:40.351462 0 13 0 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
7734 20:11:40.354796 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7735 20:11:40.361841 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 20:11:40.364436 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 20:11:40.368114 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7738 20:11:40.374615 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 20:11:40.378138 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 20:11:40.381280 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7741 20:11:40.384615 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7742 20:11:40.391218 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7743 20:11:40.394270 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 20:11:40.397547 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 20:11:40.404547 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 20:11:40.407753 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 20:11:40.410627 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 20:11:40.417413 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7749 20:11:40.420907 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7750 20:11:40.424448 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7751 20:11:40.431716 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 20:11:40.434574 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 20:11:40.437174 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 20:11:40.443944 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 20:11:40.447075 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 20:11:40.450960 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 20:11:40.457691 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 20:11:40.460880 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 20:11:40.463774 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 20:11:40.470708 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 20:11:40.474111 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 20:11:40.476693 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 20:11:40.484129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7764 20:11:40.487272 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7765 20:11:40.490005 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7766 20:11:40.497643 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7767 20:11:40.500145 Total UI for P1: 0, mck2ui 16
7768 20:11:40.503966 best dqsien dly found for B0: ( 1, 0, 28)
7769 20:11:40.506686 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7770 20:11:40.509897 Total UI for P1: 0, mck2ui 16
7771 20:11:40.514124 best dqsien dly found for B1: ( 1, 1, 2)
7772 20:11:40.516837 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7773 20:11:40.519866 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7774 20:11:40.519959
7775 20:11:40.524003 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7776 20:11:40.527047 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7777 20:11:40.530076 [Gating] SW calibration Done
7778 20:11:40.530173 ==
7779 20:11:40.532921 Dram Type= 6, Freq= 0, CH_0, rank 1
7780 20:11:40.539614 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7781 20:11:40.539720 ==
7782 20:11:40.539813 RX Vref Scan: 0
7783 20:11:40.539908
7784 20:11:40.543020 RX Vref 0 -> 0, step: 1
7785 20:11:40.543119
7786 20:11:40.546097 RX Delay 0 -> 252, step: 8
7787 20:11:40.549785 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7788 20:11:40.552917 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7789 20:11:40.556503 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7790 20:11:40.559348 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7791 20:11:40.566033 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7792 20:11:40.569296 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7793 20:11:40.573610 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7794 20:11:40.576399 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7795 20:11:40.579546 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7796 20:11:40.585777 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7797 20:11:40.588890 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7798 20:11:40.592463 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7799 20:11:40.596219 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7800 20:11:40.602560 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7801 20:11:40.605404 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7802 20:11:40.609184 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7803 20:11:40.609259 ==
7804 20:11:40.613023 Dram Type= 6, Freq= 0, CH_0, rank 1
7805 20:11:40.615530 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7806 20:11:40.615604 ==
7807 20:11:40.618601 DQS Delay:
7808 20:11:40.618671 DQS0 = 0, DQS1 = 0
7809 20:11:40.622109 DQM Delay:
7810 20:11:40.622181 DQM0 = 130, DQM1 = 124
7811 20:11:40.622243 DQ Delay:
7812 20:11:40.629172 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7813 20:11:40.632244 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7814 20:11:40.635215 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7815 20:11:40.638441 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7816 20:11:40.638538
7817 20:11:40.638626
7818 20:11:40.638713 ==
7819 20:11:40.642178 Dram Type= 6, Freq= 0, CH_0, rank 1
7820 20:11:40.645438 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7821 20:11:40.645535 ==
7822 20:11:40.645634
7823 20:11:40.645786
7824 20:11:40.649223 TX Vref Scan disable
7825 20:11:40.652157 == TX Byte 0 ==
7826 20:11:40.655134 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7827 20:11:40.658186 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7828 20:11:40.662070 == TX Byte 1 ==
7829 20:11:40.665027 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7830 20:11:40.668695 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7831 20:11:40.668807 ==
7832 20:11:40.672107 Dram Type= 6, Freq= 0, CH_0, rank 1
7833 20:11:40.678943 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7834 20:11:40.679043 ==
7835 20:11:40.689804
7836 20:11:40.693277 TX Vref early break, caculate TX vref
7837 20:11:40.696554 TX Vref=16, minBit 8, minWin=21, winSum=367
7838 20:11:40.699839 TX Vref=18, minBit 8, minWin=22, winSum=386
7839 20:11:40.703283 TX Vref=20, minBit 8, minWin=23, winSum=394
7840 20:11:40.706399 TX Vref=22, minBit 6, minWin=24, winSum=397
7841 20:11:40.709526 TX Vref=24, minBit 8, minWin=23, winSum=402
7842 20:11:40.716824 TX Vref=26, minBit 0, minWin=25, winSum=409
7843 20:11:40.719803 TX Vref=28, minBit 8, minWin=25, winSum=416
7844 20:11:40.722911 TX Vref=30, minBit 8, minWin=24, winSum=411
7845 20:11:40.727271 TX Vref=32, minBit 1, minWin=24, winSum=400
7846 20:11:40.730073 TX Vref=34, minBit 8, minWin=23, winSum=394
7847 20:11:40.736430 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
7848 20:11:40.736532
7849 20:11:40.740194 Final TX Range 0 Vref 28
7850 20:11:40.740310
7851 20:11:40.740404 ==
7852 20:11:40.742847 Dram Type= 6, Freq= 0, CH_0, rank 1
7853 20:11:40.746357 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7854 20:11:40.746462 ==
7855 20:11:40.746570
7856 20:11:40.746661
7857 20:11:40.750208 TX Vref Scan disable
7858 20:11:40.756441 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7859 20:11:40.756542 == TX Byte 0 ==
7860 20:11:40.759452 u2DelayCellOfst[0]=14 cells (4 PI)
7861 20:11:40.763067 u2DelayCellOfst[1]=17 cells (5 PI)
7862 20:11:40.766565 u2DelayCellOfst[2]=14 cells (4 PI)
7863 20:11:40.769446 u2DelayCellOfst[3]=14 cells (4 PI)
7864 20:11:40.772781 u2DelayCellOfst[4]=10 cells (3 PI)
7865 20:11:40.776566 u2DelayCellOfst[5]=0 cells (0 PI)
7866 20:11:40.779734 u2DelayCellOfst[6]=17 cells (5 PI)
7867 20:11:40.782535 u2DelayCellOfst[7]=17 cells (5 PI)
7868 20:11:40.785925 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7869 20:11:40.789232 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7870 20:11:40.792339 == TX Byte 1 ==
7871 20:11:40.795908 u2DelayCellOfst[8]=3 cells (1 PI)
7872 20:11:40.796009 u2DelayCellOfst[9]=0 cells (0 PI)
7873 20:11:40.798922 u2DelayCellOfst[10]=7 cells (2 PI)
7874 20:11:40.802865 u2DelayCellOfst[11]=3 cells (1 PI)
7875 20:11:40.806236 u2DelayCellOfst[12]=14 cells (4 PI)
7876 20:11:40.809085 u2DelayCellOfst[13]=14 cells (4 PI)
7877 20:11:40.812142 u2DelayCellOfst[14]=17 cells (5 PI)
7878 20:11:40.815670 u2DelayCellOfst[15]=14 cells (4 PI)
7879 20:11:40.818891 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7880 20:11:40.825825 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7881 20:11:40.825902 DramC Write-DBI on
7882 20:11:40.825963 ==
7883 20:11:40.829499 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 20:11:40.835259 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 20:11:40.835358 ==
7886 20:11:40.835446
7887 20:11:40.835533
7888 20:11:40.835619 TX Vref Scan disable
7889 20:11:40.839033 == TX Byte 0 ==
7890 20:11:40.843330 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7891 20:11:40.845725 == TX Byte 1 ==
7892 20:11:40.849592 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7893 20:11:40.852676 DramC Write-DBI off
7894 20:11:40.852796
7895 20:11:40.852864 [DATLAT]
7896 20:11:40.852924 Freq=1600, CH0 RK1
7897 20:11:40.852982
7898 20:11:40.855946 DATLAT Default: 0xe
7899 20:11:40.859028 0, 0xFFFF, sum = 0
7900 20:11:40.859130 1, 0xFFFF, sum = 0
7901 20:11:40.862727 2, 0xFFFF, sum = 0
7902 20:11:40.862800 3, 0xFFFF, sum = 0
7903 20:11:40.865712 4, 0xFFFF, sum = 0
7904 20:11:40.865784 5, 0xFFFF, sum = 0
7905 20:11:40.869060 6, 0xFFFF, sum = 0
7906 20:11:40.869141 7, 0xFFFF, sum = 0
7907 20:11:40.872090 8, 0xFFFF, sum = 0
7908 20:11:40.872190 9, 0xFFFF, sum = 0
7909 20:11:40.876158 10, 0xFFFF, sum = 0
7910 20:11:40.876257 11, 0xFFFF, sum = 0
7911 20:11:40.879057 12, 0x8FFF, sum = 0
7912 20:11:40.879132 13, 0x0, sum = 1
7913 20:11:40.883036 14, 0x0, sum = 2
7914 20:11:40.883108 15, 0x0, sum = 3
7915 20:11:40.885394 16, 0x0, sum = 4
7916 20:11:40.885470 best_step = 14
7917 20:11:40.885531
7918 20:11:40.885588 ==
7919 20:11:40.888847 Dram Type= 6, Freq= 0, CH_0, rank 1
7920 20:11:40.895385 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7921 20:11:40.895459 ==
7922 20:11:40.895520 RX Vref Scan: 0
7923 20:11:40.895578
7924 20:11:40.898978 RX Vref 0 -> 0, step: 1
7925 20:11:40.899048
7926 20:11:40.902222 RX Delay 11 -> 252, step: 4
7927 20:11:40.905106 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7928 20:11:40.908635 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7929 20:11:40.911866 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7930 20:11:40.918922 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7931 20:11:40.921561 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7932 20:11:40.925164 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7933 20:11:40.928629 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7934 20:11:40.931895 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7935 20:11:40.938107 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7936 20:11:40.941799 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7937 20:11:40.944865 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7938 20:11:40.948285 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7939 20:11:40.951856 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7940 20:11:40.958169 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7941 20:11:40.961862 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7942 20:11:40.964835 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7943 20:11:40.964940 ==
7944 20:11:40.968664 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 20:11:40.971481 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7946 20:11:40.974585 ==
7947 20:11:40.974656 DQS Delay:
7948 20:11:40.974717 DQS0 = 0, DQS1 = 0
7949 20:11:40.978148 DQM Delay:
7950 20:11:40.978248 DQM0 = 128, DQM1 = 120
7951 20:11:40.981548 DQ Delay:
7952 20:11:40.985857 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7953 20:11:40.988592 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7954 20:11:40.991144 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
7955 20:11:40.994994 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7956 20:11:40.995067
7957 20:11:40.995127
7958 20:11:40.995184
7959 20:11:40.997898 [DramC_TX_OE_Calibration] TA2
7960 20:11:41.001641 Original DQ_B0 (3 6) =30, OEN = 27
7961 20:11:41.005014 Original DQ_B1 (3 6) =30, OEN = 27
7962 20:11:41.007666 24, 0x0, End_B0=24 End_B1=24
7963 20:11:41.007763 25, 0x0, End_B0=25 End_B1=25
7964 20:11:41.011118 26, 0x0, End_B0=26 End_B1=26
7965 20:11:41.014501 27, 0x0, End_B0=27 End_B1=27
7966 20:11:41.018110 28, 0x0, End_B0=28 End_B1=28
7967 20:11:41.018215 29, 0x0, End_B0=29 End_B1=29
7968 20:11:41.020874 30, 0x0, End_B0=30 End_B1=30
7969 20:11:41.024571 31, 0x4545, End_B0=30 End_B1=30
7970 20:11:41.027904 Byte0 end_step=30 best_step=27
7971 20:11:41.031709 Byte1 end_step=30 best_step=27
7972 20:11:41.034289 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 20:11:41.034356 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 20:11:41.037706
7975 20:11:41.037799
7976 20:11:41.044120 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7977 20:11:41.047586 CH0 RK1: MR19=303, MR18=2020
7978 20:11:41.054244 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
7979 20:11:41.057820 [RxdqsGatingPostProcess] freq 1600
7980 20:11:41.060914 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7981 20:11:41.063808 Pre-setting of DQS Precalculation
7982 20:11:41.070596 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7983 20:11:41.070707 ==
7984 20:11:41.073823 Dram Type= 6, Freq= 0, CH_1, rank 0
7985 20:11:41.077356 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7986 20:11:41.077433 ==
7987 20:11:41.083834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7988 20:11:41.086972 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7989 20:11:41.090304 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7990 20:11:41.097551 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7991 20:11:41.105717 [CA 0] Center 41 (11~71) winsize 61
7992 20:11:41.109052 [CA 1] Center 39 (9~70) winsize 62
7993 20:11:41.111791 [CA 2] Center 36 (6~66) winsize 61
7994 20:11:41.114998 [CA 3] Center 35 (5~65) winsize 61
7995 20:11:41.119104 [CA 4] Center 33 (4~63) winsize 60
7996 20:11:41.121814 [CA 5] Center 33 (4~63) winsize 60
7997 20:11:41.121888
7998 20:11:41.124730 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7999 20:11:41.124805
8000 20:11:41.128843 [CATrainingPosCal] consider 1 rank data
8001 20:11:41.131500 u2DelayCellTimex100 = 275/100 ps
8002 20:11:41.134915 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8003 20:11:41.141407 CA1 delay=39 (9~70),Diff = 6 PI (21 cell)
8004 20:11:41.144653 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8005 20:11:41.148051 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
8006 20:11:41.151322 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8007 20:11:41.154679 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8008 20:11:41.154788
8009 20:11:41.158129 CA PerBit enable=1, Macro0, CA PI delay=33
8010 20:11:41.158230
8011 20:11:41.161841 [CBTSetCACLKResult] CA Dly = 33
8012 20:11:41.164513 CS Dly: 8 (0~39)
8013 20:11:41.168286 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8014 20:11:41.171193 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8015 20:11:41.171268 ==
8016 20:11:41.175023 Dram Type= 6, Freq= 0, CH_1, rank 1
8017 20:11:41.178237 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8018 20:11:41.181089 ==
8019 20:11:41.184857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8020 20:11:41.188067 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8021 20:11:41.194702 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8022 20:11:41.201182 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8023 20:11:41.207599 [CA 0] Center 41 (12~71) winsize 60
8024 20:11:41.210982 [CA 1] Center 40 (10~71) winsize 62
8025 20:11:41.214728 [CA 2] Center 36 (7~66) winsize 60
8026 20:11:41.218033 [CA 3] Center 36 (7~65) winsize 59
8027 20:11:41.221134 [CA 4] Center 34 (5~64) winsize 60
8028 20:11:41.223994 [CA 5] Center 34 (4~64) winsize 61
8029 20:11:41.224060
8030 20:11:41.227524 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8031 20:11:41.227589
8032 20:11:41.231300 [CATrainingPosCal] consider 2 rank data
8033 20:11:41.234367 u2DelayCellTimex100 = 275/100 ps
8034 20:11:41.237526 CA0 delay=41 (12~71),Diff = 8 PI (28 cell)
8035 20:11:41.245052 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8036 20:11:41.247094 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8037 20:11:41.250792 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8038 20:11:41.253625 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8039 20:11:41.257707 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8040 20:11:41.257783
8041 20:11:41.260869 CA PerBit enable=1, Macro0, CA PI delay=33
8042 20:11:41.260941
8043 20:11:41.263794 [CBTSetCACLKResult] CA Dly = 33
8044 20:11:41.268012 CS Dly: 9 (0~41)
8045 20:11:41.270150 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8046 20:11:41.274134 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8047 20:11:41.274202
8048 20:11:41.277140 ----->DramcWriteLeveling(PI) begin...
8049 20:11:41.277214 ==
8050 20:11:41.280679 Dram Type= 6, Freq= 0, CH_1, rank 0
8051 20:11:41.287062 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8052 20:11:41.287140 ==
8053 20:11:41.290187 Write leveling (Byte 0): 23 => 23
8054 20:11:41.294060 Write leveling (Byte 1): 21 => 21
8055 20:11:41.294127 DramcWriteLeveling(PI) end<-----
8056 20:11:41.294186
8057 20:11:41.296661 ==
8058 20:11:41.299903 Dram Type= 6, Freq= 0, CH_1, rank 0
8059 20:11:41.303219 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8060 20:11:41.303285 ==
8061 20:11:41.306949 [Gating] SW mode calibration
8062 20:11:41.313491 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 20:11:41.317488 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8064 20:11:41.323249 0 12 0 | B1->B0 | 2525 3434 | 0 1 | (1 1) (1 1)
8065 20:11:41.326920 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 20:11:41.329697 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 20:11:41.336236 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 20:11:41.339622 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 20:11:41.343077 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 20:11:41.349695 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 20:11:41.352605 0 12 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8072 20:11:41.356661 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
8073 20:11:41.362933 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8074 20:11:41.366509 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 20:11:41.369900 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 20:11:41.375942 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 20:11:41.379651 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 20:11:41.382719 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 20:11:41.389037 0 13 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8080 20:11:41.393054 0 14 0 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
8081 20:11:41.395911 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 20:11:41.402940 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 20:11:41.405895 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 20:11:41.409215 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 20:11:41.416076 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 20:11:41.419529 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 20:11:41.422188 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 20:11:41.428910 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 20:11:41.432399 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 20:11:41.436230 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 20:11:41.442890 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 20:11:41.445215 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 20:11:41.448743 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 20:11:41.455908 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 20:11:41.458737 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 20:11:41.461705 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 20:11:41.469054 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 20:11:41.471732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 20:11:41.475124 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 20:11:41.482125 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 20:11:41.485368 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 20:11:41.488529 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 20:11:41.495349 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 20:11:41.499257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 20:11:41.501674 Total UI for P1: 0, mck2ui 16
8106 20:11:41.504813 best dqsien dly found for B0: ( 1, 0, 26)
8107 20:11:41.508656 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 20:11:41.515117 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 20:11:41.515193 Total UI for P1: 0, mck2ui 16
8110 20:11:41.521870 best dqsien dly found for B1: ( 1, 1, 2)
8111 20:11:41.524640 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8112 20:11:41.527956 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8113 20:11:41.528024
8114 20:11:41.531626 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8115 20:11:41.534570 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8116 20:11:41.537976 [Gating] SW calibration Done
8117 20:11:41.538047 ==
8118 20:11:41.541421 Dram Type= 6, Freq= 0, CH_1, rank 0
8119 20:11:41.545301 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8120 20:11:41.545372 ==
8121 20:11:41.547717 RX Vref Scan: 0
8122 20:11:41.547790
8123 20:11:41.547852 RX Vref 0 -> 0, step: 1
8124 20:11:41.547916
8125 20:11:41.551133 RX Delay 0 -> 252, step: 8
8126 20:11:41.554699 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8127 20:11:41.557659 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8128 20:11:41.564268 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8129 20:11:41.567780 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8130 20:11:41.571417 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8131 20:11:41.574193 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8132 20:11:41.577693 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8133 20:11:41.584678 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8134 20:11:41.587487 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8135 20:11:41.590953 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8136 20:11:41.594318 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8137 20:11:41.601115 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8138 20:11:41.604971 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8139 20:11:41.607334 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8140 20:11:41.610932 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8141 20:11:41.613870 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8142 20:11:41.617690 ==
8143 20:11:41.620409 Dram Type= 6, Freq= 0, CH_1, rank 0
8144 20:11:41.623680 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8145 20:11:41.623756 ==
8146 20:11:41.623816 DQS Delay:
8147 20:11:41.627046 DQS0 = 0, DQS1 = 0
8148 20:11:41.627118 DQM Delay:
8149 20:11:41.630446 DQM0 = 129, DQM1 = 125
8150 20:11:41.630518 DQ Delay:
8151 20:11:41.634042 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8152 20:11:41.636930 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8153 20:11:41.640646 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8154 20:11:41.643754 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8155 20:11:41.643864
8156 20:11:41.643955
8157 20:11:41.644040 ==
8158 20:11:41.647373 Dram Type= 6, Freq= 0, CH_1, rank 0
8159 20:11:41.654166 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8160 20:11:41.654266 ==
8161 20:11:41.654363
8162 20:11:41.654439
8163 20:11:41.654496 TX Vref Scan disable
8164 20:11:41.657369 == TX Byte 0 ==
8165 20:11:41.661110 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8166 20:11:41.667532 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8167 20:11:41.667613 == TX Byte 1 ==
8168 20:11:41.670758 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8169 20:11:41.676976 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8170 20:11:41.677076 ==
8171 20:11:41.680530 Dram Type= 6, Freq= 0, CH_1, rank 0
8172 20:11:41.683543 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8173 20:11:41.683624 ==
8174 20:11:41.695951
8175 20:11:41.699476 TX Vref early break, caculate TX vref
8176 20:11:41.702479 TX Vref=16, minBit 3, minWin=21, winSum=367
8177 20:11:41.706114 TX Vref=18, minBit 3, minWin=21, winSum=373
8178 20:11:41.709055 TX Vref=20, minBit 3, minWin=23, winSum=391
8179 20:11:41.712341 TX Vref=22, minBit 0, minWin=24, winSum=394
8180 20:11:41.715815 TX Vref=24, minBit 3, minWin=24, winSum=407
8181 20:11:41.722496 TX Vref=26, minBit 3, minWin=24, winSum=414
8182 20:11:41.725559 TX Vref=28, minBit 0, minWin=25, winSum=411
8183 20:11:41.729367 TX Vref=30, minBit 3, minWin=24, winSum=407
8184 20:11:41.732014 TX Vref=32, minBit 3, minWin=23, winSum=397
8185 20:11:41.735358 TX Vref=34, minBit 3, minWin=23, winSum=391
8186 20:11:41.742386 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
8187 20:11:41.742468
8188 20:11:41.745978 Final TX Range 0 Vref 28
8189 20:11:41.746059
8190 20:11:41.746121 ==
8191 20:11:41.748757 Dram Type= 6, Freq= 0, CH_1, rank 0
8192 20:11:41.752474 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8193 20:11:41.752556 ==
8194 20:11:41.752620
8195 20:11:41.752679
8196 20:11:41.755621 TX Vref Scan disable
8197 20:11:41.762130 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8198 20:11:41.762211 == TX Byte 0 ==
8199 20:11:41.765827 u2DelayCellOfst[0]=14 cells (4 PI)
8200 20:11:41.768643 u2DelayCellOfst[1]=10 cells (3 PI)
8201 20:11:41.772575 u2DelayCellOfst[2]=0 cells (0 PI)
8202 20:11:41.775150 u2DelayCellOfst[3]=7 cells (2 PI)
8203 20:11:41.778329 u2DelayCellOfst[4]=7 cells (2 PI)
8204 20:11:41.781545 u2DelayCellOfst[5]=14 cells (4 PI)
8205 20:11:41.785549 u2DelayCellOfst[6]=17 cells (5 PI)
8206 20:11:41.788401 u2DelayCellOfst[7]=7 cells (2 PI)
8207 20:11:41.791513 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8208 20:11:41.794784 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8209 20:11:41.798134 == TX Byte 1 ==
8210 20:11:41.802206 u2DelayCellOfst[8]=0 cells (0 PI)
8211 20:11:41.802287 u2DelayCellOfst[9]=7 cells (2 PI)
8212 20:11:41.805207 u2DelayCellOfst[10]=10 cells (3 PI)
8213 20:11:41.808166 u2DelayCellOfst[11]=3 cells (1 PI)
8214 20:11:41.811222 u2DelayCellOfst[12]=17 cells (5 PI)
8215 20:11:41.815030 u2DelayCellOfst[13]=21 cells (6 PI)
8216 20:11:41.818450 u2DelayCellOfst[14]=21 cells (6 PI)
8217 20:11:41.822195 u2DelayCellOfst[15]=21 cells (6 PI)
8218 20:11:41.824703 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8219 20:11:41.831606 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8220 20:11:41.831691 DramC Write-DBI on
8221 20:11:41.831770 ==
8222 20:11:41.834532 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 20:11:41.841569 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 20:11:41.841650 ==
8225 20:11:41.841726
8226 20:11:41.841789
8227 20:11:41.841847 TX Vref Scan disable
8228 20:11:41.845132 == TX Byte 0 ==
8229 20:11:41.848357 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8230 20:11:41.851617 == TX Byte 1 ==
8231 20:11:41.855933 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8232 20:11:41.858467 DramC Write-DBI off
8233 20:11:41.858555
8234 20:11:41.858619 [DATLAT]
8235 20:11:41.858679 Freq=1600, CH1 RK0
8236 20:11:41.858740
8237 20:11:41.862104 DATLAT Default: 0xf
8238 20:11:41.862175 0, 0xFFFF, sum = 0
8239 20:11:41.865794 1, 0xFFFF, sum = 0
8240 20:11:41.868046 2, 0xFFFF, sum = 0
8241 20:11:41.868130 3, 0xFFFF, sum = 0
8242 20:11:41.871765 4, 0xFFFF, sum = 0
8243 20:11:41.871837 5, 0xFFFF, sum = 0
8244 20:11:41.875041 6, 0xFFFF, sum = 0
8245 20:11:41.875107 7, 0xFFFF, sum = 0
8246 20:11:41.878631 8, 0xFFFF, sum = 0
8247 20:11:41.878697 9, 0xFFFF, sum = 0
8248 20:11:41.881581 10, 0xFFFF, sum = 0
8249 20:11:41.881652 11, 0xFFFF, sum = 0
8250 20:11:41.885144 12, 0xF7F, sum = 0
8251 20:11:41.885210 13, 0x0, sum = 1
8252 20:11:41.888314 14, 0x0, sum = 2
8253 20:11:41.888379 15, 0x0, sum = 3
8254 20:11:41.891453 16, 0x0, sum = 4
8255 20:11:41.891522 best_step = 14
8256 20:11:41.891580
8257 20:11:41.891642 ==
8258 20:11:41.894777 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 20:11:41.898160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8260 20:11:41.901126 ==
8261 20:11:41.901201 RX Vref Scan: 1
8262 20:11:41.901261
8263 20:11:41.904737 Set Vref Range= 24 -> 127
8264 20:11:41.904801
8265 20:11:41.907817 RX Vref 24 -> 127, step: 1
8266 20:11:41.907881
8267 20:11:41.907937 RX Delay 3 -> 252, step: 4
8268 20:11:41.907992
8269 20:11:41.911064 Set Vref, RX VrefLevel [Byte0]: 24
8270 20:11:41.914726 [Byte1]: 24
8271 20:11:41.918456
8272 20:11:41.918525 Set Vref, RX VrefLevel [Byte0]: 25
8273 20:11:41.921614 [Byte1]: 25
8274 20:11:41.925771
8275 20:11:41.925846 Set Vref, RX VrefLevel [Byte0]: 26
8276 20:11:41.929116 [Byte1]: 26
8277 20:11:41.934030
8278 20:11:41.934096 Set Vref, RX VrefLevel [Byte0]: 27
8279 20:11:41.936871 [Byte1]: 27
8280 20:11:41.942282
8281 20:11:41.942359 Set Vref, RX VrefLevel [Byte0]: 28
8282 20:11:41.944885 [Byte1]: 28
8283 20:11:41.948830
8284 20:11:41.948918 Set Vref, RX VrefLevel [Byte0]: 29
8285 20:11:41.952596 [Byte1]: 29
8286 20:11:41.956410
8287 20:11:41.956486 Set Vref, RX VrefLevel [Byte0]: 30
8288 20:11:41.959813 [Byte1]: 30
8289 20:11:41.965221
8290 20:11:41.965290 Set Vref, RX VrefLevel [Byte0]: 31
8291 20:11:41.967280 [Byte1]: 31
8292 20:11:41.972225
8293 20:11:41.972309 Set Vref, RX VrefLevel [Byte0]: 32
8294 20:11:41.975246 [Byte1]: 32
8295 20:11:41.979751
8296 20:11:41.979831 Set Vref, RX VrefLevel [Byte0]: 33
8297 20:11:41.982861 [Byte1]: 33
8298 20:11:41.987273
8299 20:11:41.987355 Set Vref, RX VrefLevel [Byte0]: 34
8300 20:11:41.990927 [Byte1]: 34
8301 20:11:41.995287
8302 20:11:41.995367 Set Vref, RX VrefLevel [Byte0]: 35
8303 20:11:41.997992 [Byte1]: 35
8304 20:11:42.002431
8305 20:11:42.002507 Set Vref, RX VrefLevel [Byte0]: 36
8306 20:11:42.005956 [Byte1]: 36
8307 20:11:42.010635
8308 20:11:42.010708 Set Vref, RX VrefLevel [Byte0]: 37
8309 20:11:42.013356 [Byte1]: 37
8310 20:11:42.017889
8311 20:11:42.017962 Set Vref, RX VrefLevel [Byte0]: 38
8312 20:11:42.021323 [Byte1]: 38
8313 20:11:42.025614
8314 20:11:42.025688 Set Vref, RX VrefLevel [Byte0]: 39
8315 20:11:42.028824 [Byte1]: 39
8316 20:11:42.032855
8317 20:11:42.032937 Set Vref, RX VrefLevel [Byte0]: 40
8318 20:11:42.036044 [Byte1]: 40
8319 20:11:42.040727
8320 20:11:42.040843 Set Vref, RX VrefLevel [Byte0]: 41
8321 20:11:42.044288 [Byte1]: 41
8322 20:11:42.048353
8323 20:11:42.048432 Set Vref, RX VrefLevel [Byte0]: 42
8324 20:11:42.051761 [Byte1]: 42
8325 20:11:42.056264
8326 20:11:42.056344 Set Vref, RX VrefLevel [Byte0]: 43
8327 20:11:42.059617 [Byte1]: 43
8328 20:11:42.064174
8329 20:11:42.064253 Set Vref, RX VrefLevel [Byte0]: 44
8330 20:11:42.067234 [Byte1]: 44
8331 20:11:42.071335
8332 20:11:42.071415 Set Vref, RX VrefLevel [Byte0]: 45
8333 20:11:42.074996 [Byte1]: 45
8334 20:11:42.079517
8335 20:11:42.079597 Set Vref, RX VrefLevel [Byte0]: 46
8336 20:11:42.082127 [Byte1]: 46
8337 20:11:42.086575
8338 20:11:42.086655 Set Vref, RX VrefLevel [Byte0]: 47
8339 20:11:42.090109 [Byte1]: 47
8340 20:11:42.094375
8341 20:11:42.094448 Set Vref, RX VrefLevel [Byte0]: 48
8342 20:11:42.097622 [Byte1]: 48
8343 20:11:42.102366
8344 20:11:42.102435 Set Vref, RX VrefLevel [Byte0]: 49
8345 20:11:42.105366 [Byte1]: 49
8346 20:11:42.109498
8347 20:11:42.109569 Set Vref, RX VrefLevel [Byte0]: 50
8348 20:11:42.113320 [Byte1]: 50
8349 20:11:42.117215
8350 20:11:42.117287 Set Vref, RX VrefLevel [Byte0]: 51
8351 20:11:42.120717 [Byte1]: 51
8352 20:11:42.125024
8353 20:11:42.125097 Set Vref, RX VrefLevel [Byte0]: 52
8354 20:11:42.128356 [Byte1]: 52
8355 20:11:42.132330
8356 20:11:42.132409 Set Vref, RX VrefLevel [Byte0]: 53
8357 20:11:42.135811 [Byte1]: 53
8358 20:11:42.140013
8359 20:11:42.140086 Set Vref, RX VrefLevel [Byte0]: 54
8360 20:11:42.143699 [Byte1]: 54
8361 20:11:42.148006
8362 20:11:42.148091 Set Vref, RX VrefLevel [Byte0]: 55
8363 20:11:42.151295 [Byte1]: 55
8364 20:11:42.155934
8365 20:11:42.156005 Set Vref, RX VrefLevel [Byte0]: 56
8366 20:11:42.159006 [Byte1]: 56
8367 20:11:42.163421
8368 20:11:42.163493 Set Vref, RX VrefLevel [Byte0]: 57
8369 20:11:42.166698 [Byte1]: 57
8370 20:11:42.171147
8371 20:11:42.171231 Set Vref, RX VrefLevel [Byte0]: 58
8372 20:11:42.174635 [Byte1]: 58
8373 20:11:42.178751
8374 20:11:42.178822 Set Vref, RX VrefLevel [Byte0]: 59
8375 20:11:42.181711 [Byte1]: 59
8376 20:11:42.185960
8377 20:11:42.186031 Set Vref, RX VrefLevel [Byte0]: 60
8378 20:11:42.189482 [Byte1]: 60
8379 20:11:42.194337
8380 20:11:42.194410 Set Vref, RX VrefLevel [Byte0]: 61
8381 20:11:42.196955 [Byte1]: 61
8382 20:11:42.201296
8383 20:11:42.201386 Set Vref, RX VrefLevel [Byte0]: 62
8384 20:11:42.204909 [Byte1]: 62
8385 20:11:42.209020
8386 20:11:42.209098 Set Vref, RX VrefLevel [Byte0]: 63
8387 20:11:42.212618 [Byte1]: 63
8388 20:11:42.217051
8389 20:11:42.217129 Set Vref, RX VrefLevel [Byte0]: 64
8390 20:11:42.220104 [Byte1]: 64
8391 20:11:42.224220
8392 20:11:42.224292 Set Vref, RX VrefLevel [Byte0]: 65
8393 20:11:42.228112 [Byte1]: 65
8394 20:11:42.232627
8395 20:11:42.232700 Set Vref, RX VrefLevel [Byte0]: 66
8396 20:11:42.235334 [Byte1]: 66
8397 20:11:42.239891
8398 20:11:42.239965 Set Vref, RX VrefLevel [Byte0]: 67
8399 20:11:42.243092 [Byte1]: 67
8400 20:11:42.247777
8401 20:11:42.247849 Set Vref, RX VrefLevel [Byte0]: 68
8402 20:11:42.250359 [Byte1]: 68
8403 20:11:42.255012
8404 20:11:42.255091 Set Vref, RX VrefLevel [Byte0]: 69
8405 20:11:42.258274 [Byte1]: 69
8406 20:11:42.262610
8407 20:11:42.262686 Set Vref, RX VrefLevel [Byte0]: 70
8408 20:11:42.269346 [Byte1]: 70
8409 20:11:42.269431
8410 20:11:42.272863 Set Vref, RX VrefLevel [Byte0]: 71
8411 20:11:42.276320 [Byte1]: 71
8412 20:11:42.276387
8413 20:11:42.279301 Set Vref, RX VrefLevel [Byte0]: 72
8414 20:11:42.282259 [Byte1]: 72
8415 20:11:42.282326
8416 20:11:42.286195 Set Vref, RX VrefLevel [Byte0]: 73
8417 20:11:42.288742 [Byte1]: 73
8418 20:11:42.293403
8419 20:11:42.293480 Set Vref, RX VrefLevel [Byte0]: 74
8420 20:11:42.296805 [Byte1]: 74
8421 20:11:42.301184
8422 20:11:42.301253 Final RX Vref Byte 0 = 60 to rank0
8423 20:11:42.304154 Final RX Vref Byte 1 = 54 to rank0
8424 20:11:42.307474 Final RX Vref Byte 0 = 60 to rank1
8425 20:11:42.310681 Final RX Vref Byte 1 = 54 to rank1==
8426 20:11:42.314186 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 20:11:42.320745 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8428 20:11:42.320829 ==
8429 20:11:42.320900 DQS Delay:
8430 20:11:42.324307 DQS0 = 0, DQS1 = 0
8431 20:11:42.324376 DQM Delay:
8432 20:11:42.324435 DQM0 = 129, DQM1 = 122
8433 20:11:42.327870 DQ Delay:
8434 20:11:42.330597 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =126
8435 20:11:42.333858 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8436 20:11:42.337489 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8437 20:11:42.340653 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8438 20:11:42.340803
8439 20:11:42.340892
8440 20:11:42.340993
8441 20:11:42.344038 [DramC_TX_OE_Calibration] TA2
8442 20:11:42.347244 Original DQ_B0 (3 6) =30, OEN = 27
8443 20:11:42.350536 Original DQ_B1 (3 6) =30, OEN = 27
8444 20:11:42.353648 24, 0x0, End_B0=24 End_B1=24
8445 20:11:42.353724 25, 0x0, End_B0=25 End_B1=25
8446 20:11:42.356925 26, 0x0, End_B0=26 End_B1=26
8447 20:11:42.360553 27, 0x0, End_B0=27 End_B1=27
8448 20:11:42.363808 28, 0x0, End_B0=28 End_B1=28
8449 20:11:42.367600 29, 0x0, End_B0=29 End_B1=29
8450 20:11:42.367697 30, 0x0, End_B0=30 End_B1=30
8451 20:11:42.370385 31, 0x4141, End_B0=30 End_B1=30
8452 20:11:42.373630 Byte0 end_step=30 best_step=27
8453 20:11:42.377043 Byte1 end_step=30 best_step=27
8454 20:11:42.380181 Byte0 TX OE(2T, 0.5T) = (3, 3)
8455 20:11:42.383576 Byte1 TX OE(2T, 0.5T) = (3, 3)
8456 20:11:42.383649
8457 20:11:42.383709
8458 20:11:42.390278 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8459 20:11:42.393409 CH1 RK0: MR19=303, MR18=2424
8460 20:11:42.400436 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8461 20:11:42.400520
8462 20:11:42.403698 ----->DramcWriteLeveling(PI) begin...
8463 20:11:42.403784 ==
8464 20:11:42.406629 Dram Type= 6, Freq= 0, CH_1, rank 1
8465 20:11:42.409863 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8466 20:11:42.409940 ==
8467 20:11:42.413422 Write leveling (Byte 0): 24 => 24
8468 20:11:42.417319 Write leveling (Byte 1): 20 => 20
8469 20:11:42.421124 DramcWriteLeveling(PI) end<-----
8470 20:11:42.421198
8471 20:11:42.421258 ==
8472 20:11:42.423434 Dram Type= 6, Freq= 0, CH_1, rank 1
8473 20:11:42.426742 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8474 20:11:42.426848 ==
8475 20:11:42.430250 [Gating] SW mode calibration
8476 20:11:42.436376 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8477 20:11:42.442927 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8478 20:11:42.446774 0 12 0 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
8479 20:11:42.453749 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 20:11:42.456105 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 20:11:42.459714 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 20:11:42.466299 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 20:11:42.469795 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8484 20:11:42.472831 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8485 20:11:42.479539 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8486 20:11:42.482656 0 13 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8487 20:11:42.486378 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 20:11:42.492512 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 20:11:42.496396 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 20:11:42.499595 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 20:11:42.506301 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8492 20:11:42.509189 0 13 24 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8493 20:11:42.512412 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8494 20:11:42.518986 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8495 20:11:42.522840 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 20:11:42.525913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 20:11:42.533204 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 20:11:42.535626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 20:11:42.539235 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 20:11:42.545576 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8501 20:11:42.548763 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 20:11:42.552241 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8503 20:11:42.558762 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 20:11:42.562104 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 20:11:42.565838 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 20:11:42.572026 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 20:11:42.575512 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 20:11:42.578743 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 20:11:42.585516 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 20:11:42.588884 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 20:11:42.591767 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 20:11:42.598439 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 20:11:42.602006 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 20:11:42.605232 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 20:11:42.608240 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 20:11:42.615065 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8517 20:11:42.618401 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8518 20:11:42.621400 Total UI for P1: 0, mck2ui 16
8519 20:11:42.625570 best dqsien dly found for B0: ( 1, 0, 22)
8520 20:11:42.629153 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8521 20:11:42.632325 Total UI for P1: 0, mck2ui 16
8522 20:11:42.634646 best dqsien dly found for B1: ( 1, 0, 28)
8523 20:11:42.638134 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8524 20:11:42.645512 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8525 20:11:42.645593
8526 20:11:42.648186 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8527 20:11:42.652267 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8528 20:11:42.654380 [Gating] SW calibration Done
8529 20:11:42.654492 ==
8530 20:11:42.658071 Dram Type= 6, Freq= 0, CH_1, rank 1
8531 20:11:42.661523 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8532 20:11:42.661604 ==
8533 20:11:42.664938 RX Vref Scan: 0
8534 20:11:42.665017
8535 20:11:42.665082 RX Vref 0 -> 0, step: 1
8536 20:11:42.665143
8537 20:11:42.667829 RX Delay 0 -> 252, step: 8
8538 20:11:42.671402 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8539 20:11:42.674252 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8540 20:11:42.681166 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8541 20:11:42.684945 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8542 20:11:42.687889 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8543 20:11:42.691181 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8544 20:11:42.694145 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8545 20:11:42.701044 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8546 20:11:42.704633 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8547 20:11:42.707715 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8548 20:11:42.710920 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8549 20:11:42.713871 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8550 20:11:42.720616 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8551 20:11:42.723828 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8552 20:11:42.727246 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8553 20:11:42.730761 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8554 20:11:42.734217 ==
8555 20:11:42.734298 Dram Type= 6, Freq= 0, CH_1, rank 1
8556 20:11:42.740672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8557 20:11:42.740791 ==
8558 20:11:42.740884 DQS Delay:
8559 20:11:42.743838 DQS0 = 0, DQS1 = 0
8560 20:11:42.743970 DQM Delay:
8561 20:11:42.747590 DQM0 = 130, DQM1 = 124
8562 20:11:42.747670 DQ Delay:
8563 20:11:42.750227 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8564 20:11:42.753941 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8565 20:11:42.756873 DQ8 =107, DQ9 =107, DQ10 =127, DQ11 =115
8566 20:11:42.760359 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8567 20:11:42.760440
8568 20:11:42.760504
8569 20:11:42.760563 ==
8570 20:11:42.763787 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 20:11:42.770412 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 20:11:42.770493 ==
8573 20:11:42.770557
8574 20:11:42.770617
8575 20:11:42.770675 TX Vref Scan disable
8576 20:11:42.773777 == TX Byte 0 ==
8577 20:11:42.777528 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8578 20:11:42.783711 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8579 20:11:42.783792 == TX Byte 1 ==
8580 20:11:42.787406 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8581 20:11:42.794153 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8582 20:11:42.794234 ==
8583 20:11:42.796932 Dram Type= 6, Freq= 0, CH_1, rank 1
8584 20:11:42.801261 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8585 20:11:42.801342 ==
8586 20:11:42.814282
8587 20:11:42.817145 TX Vref early break, caculate TX vref
8588 20:11:42.820402 TX Vref=16, minBit 0, minWin=22, winSum=381
8589 20:11:42.824403 TX Vref=18, minBit 0, minWin=22, winSum=385
8590 20:11:42.827042 TX Vref=20, minBit 5, minWin=23, winSum=396
8591 20:11:42.830568 TX Vref=22, minBit 0, minWin=24, winSum=403
8592 20:11:42.833879 TX Vref=24, minBit 0, minWin=24, winSum=408
8593 20:11:42.840776 TX Vref=26, minBit 0, minWin=25, winSum=421
8594 20:11:42.843610 TX Vref=28, minBit 0, minWin=23, winSum=420
8595 20:11:42.846801 TX Vref=30, minBit 0, minWin=24, winSum=414
8596 20:11:42.850705 TX Vref=32, minBit 0, minWin=22, winSum=410
8597 20:11:42.853982 TX Vref=34, minBit 0, minWin=22, winSum=400
8598 20:11:42.856773 TX Vref=36, minBit 0, minWin=22, winSum=392
8599 20:11:42.863618 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8600 20:11:42.863700
8601 20:11:42.867268 Final TX Range 0 Vref 26
8602 20:11:42.867350
8603 20:11:42.867413 ==
8604 20:11:42.870329 Dram Type= 6, Freq= 0, CH_1, rank 1
8605 20:11:42.873780 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8606 20:11:42.873861 ==
8607 20:11:42.873926
8608 20:11:42.876926
8609 20:11:42.877007 TX Vref Scan disable
8610 20:11:42.883454 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8611 20:11:42.883539 == TX Byte 0 ==
8612 20:11:42.886645 u2DelayCellOfst[0]=17 cells (5 PI)
8613 20:11:42.890030 u2DelayCellOfst[1]=7 cells (2 PI)
8614 20:11:42.893316 u2DelayCellOfst[2]=0 cells (0 PI)
8615 20:11:42.896654 u2DelayCellOfst[3]=7 cells (2 PI)
8616 20:11:42.900075 u2DelayCellOfst[4]=7 cells (2 PI)
8617 20:11:42.903406 u2DelayCellOfst[5]=17 cells (5 PI)
8618 20:11:42.906596 u2DelayCellOfst[6]=17 cells (5 PI)
8619 20:11:42.910010 u2DelayCellOfst[7]=3 cells (1 PI)
8620 20:11:42.913887 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8621 20:11:42.917166 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8622 20:11:42.919705 == TX Byte 1 ==
8623 20:11:42.923666 u2DelayCellOfst[8]=0 cells (0 PI)
8624 20:11:42.926541 u2DelayCellOfst[9]=3 cells (1 PI)
8625 20:11:42.926651 u2DelayCellOfst[10]=10 cells (3 PI)
8626 20:11:42.930270 u2DelayCellOfst[11]=3 cells (1 PI)
8627 20:11:42.932890 u2DelayCellOfst[12]=14 cells (4 PI)
8628 20:11:42.936370 u2DelayCellOfst[13]=17 cells (5 PI)
8629 20:11:42.939744 u2DelayCellOfst[14]=17 cells (5 PI)
8630 20:11:42.943594 u2DelayCellOfst[15]=17 cells (5 PI)
8631 20:11:42.949508 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8632 20:11:42.953183 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8633 20:11:42.953271 DramC Write-DBI on
8634 20:11:42.953357 ==
8635 20:11:42.956607 Dram Type= 6, Freq= 0, CH_1, rank 1
8636 20:11:42.963643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8637 20:11:42.963727 ==
8638 20:11:42.963813
8639 20:11:42.963895
8640 20:11:42.963975 TX Vref Scan disable
8641 20:11:42.967360 == TX Byte 0 ==
8642 20:11:42.970274 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8643 20:11:42.973957 == TX Byte 1 ==
8644 20:11:42.977185 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8645 20:11:42.977269 DramC Write-DBI off
8646 20:11:42.980883
8647 20:11:42.980966 [DATLAT]
8648 20:11:42.981052 Freq=1600, CH1 RK1
8649 20:11:42.981134
8650 20:11:42.983539 DATLAT Default: 0xe
8651 20:11:42.983621 0, 0xFFFF, sum = 0
8652 20:11:42.986809 1, 0xFFFF, sum = 0
8653 20:11:42.986894 2, 0xFFFF, sum = 0
8654 20:11:42.990437 3, 0xFFFF, sum = 0
8655 20:11:42.993964 4, 0xFFFF, sum = 0
8656 20:11:42.994076 5, 0xFFFF, sum = 0
8657 20:11:42.997406 6, 0xFFFF, sum = 0
8658 20:11:42.997517 7, 0xFFFF, sum = 0
8659 20:11:43.000387 8, 0xFFFF, sum = 0
8660 20:11:43.000469 9, 0xFFFF, sum = 0
8661 20:11:43.004237 10, 0xFFFF, sum = 0
8662 20:11:43.004319 11, 0xFFFF, sum = 0
8663 20:11:43.006808 12, 0xFFF, sum = 0
8664 20:11:43.006889 13, 0x0, sum = 1
8665 20:11:43.010095 14, 0x0, sum = 2
8666 20:11:43.010178 15, 0x0, sum = 3
8667 20:11:43.013564 16, 0x0, sum = 4
8668 20:11:43.013648 best_step = 14
8669 20:11:43.013728
8670 20:11:43.013804 ==
8671 20:11:43.017430 Dram Type= 6, Freq= 0, CH_1, rank 1
8672 20:11:43.019828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8673 20:11:43.023079 ==
8674 20:11:43.023161 RX Vref Scan: 0
8675 20:11:43.023242
8676 20:11:43.026667 RX Vref 0 -> 0, step: 1
8677 20:11:43.026778
8678 20:11:43.026877 RX Delay 3 -> 252, step: 4
8679 20:11:43.034037 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8680 20:11:43.037247 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8681 20:11:43.040632 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8682 20:11:43.044109 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8683 20:11:43.047231 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8684 20:11:43.053917 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8685 20:11:43.057528 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8686 20:11:43.061044 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8687 20:11:43.064058 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8688 20:11:43.070177 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8689 20:11:43.073556 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8690 20:11:43.077003 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8691 20:11:43.080191 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8692 20:11:43.083423 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8693 20:11:43.090215 iDelay=195, Bit 14, Center 136 (79 ~ 194) 116
8694 20:11:43.093843 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8695 20:11:43.093924 ==
8696 20:11:43.096580 Dram Type= 6, Freq= 0, CH_1, rank 1
8697 20:11:43.099948 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8698 20:11:43.100030 ==
8699 20:11:43.103247 DQS Delay:
8700 20:11:43.103335 DQS0 = 0, DQS1 = 0
8701 20:11:43.103400 DQM Delay:
8702 20:11:43.106669 DQM0 = 127, DQM1 = 123
8703 20:11:43.106791 DQ Delay:
8704 20:11:43.109927 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8705 20:11:43.113223 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8706 20:11:43.119864 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8707 20:11:43.123061 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8708 20:11:43.123142
8709 20:11:43.123205
8710 20:11:43.123264
8711 20:11:43.126195 [DramC_TX_OE_Calibration] TA2
8712 20:11:43.129951 Original DQ_B0 (3 6) =30, OEN = 27
8713 20:11:43.132840 Original DQ_B1 (3 6) =30, OEN = 27
8714 20:11:43.132921 24, 0x0, End_B0=24 End_B1=24
8715 20:11:43.136166 25, 0x0, End_B0=25 End_B1=25
8716 20:11:43.139733 26, 0x0, End_B0=26 End_B1=26
8717 20:11:43.142964 27, 0x0, End_B0=27 End_B1=27
8718 20:11:43.143072 28, 0x0, End_B0=28 End_B1=28
8719 20:11:43.146451 29, 0x0, End_B0=29 End_B1=29
8720 20:11:43.149748 30, 0x0, End_B0=30 End_B1=30
8721 20:11:43.152994 31, 0x4141, End_B0=30 End_B1=30
8722 20:11:43.156276 Byte0 end_step=30 best_step=27
8723 20:11:43.159434 Byte1 end_step=30 best_step=27
8724 20:11:43.159514 Byte0 TX OE(2T, 0.5T) = (3, 3)
8725 20:11:43.162600 Byte1 TX OE(2T, 0.5T) = (3, 3)
8726 20:11:43.162706
8727 20:11:43.162797
8728 20:11:43.172947 [DQSOSCAuto] RK1, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
8729 20:11:43.175723 CH1 RK1: MR19=303, MR18=1919
8730 20:11:43.179829 CH1_RK1: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
8731 20:11:43.183024 [RxdqsGatingPostProcess] freq 1600
8732 20:11:43.188894 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8733 20:11:43.193011 Pre-setting of DQS Precalculation
8734 20:11:43.195552 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8735 20:11:43.205813 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8736 20:11:43.212383 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8737 20:11:43.212464
8738 20:11:43.212528
8739 20:11:43.215641 [Calibration Summary] 3200 Mbps
8740 20:11:43.215722 CH 0, Rank 0
8741 20:11:43.218637 SW Impedance : PASS
8742 20:11:43.221841 DUTY Scan : NO K
8743 20:11:43.221922 ZQ Calibration : PASS
8744 20:11:43.225647 Jitter Meter : NO K
8745 20:11:43.228457 CBT Training : PASS
8746 20:11:43.228537 Write leveling : PASS
8747 20:11:43.231784 RX DQS gating : PASS
8748 20:11:43.231864 RX DQ/DQS(RDDQC) : PASS
8749 20:11:43.235933 TX DQ/DQS : PASS
8750 20:11:43.238623 RX DATLAT : PASS
8751 20:11:43.238702 RX DQ/DQS(Engine): PASS
8752 20:11:43.241758 TX OE : PASS
8753 20:11:43.241839 All Pass.
8754 20:11:43.241903
8755 20:11:43.245856 CH 0, Rank 1
8756 20:11:43.245937 SW Impedance : PASS
8757 20:11:43.248529 DUTY Scan : NO K
8758 20:11:43.252382 ZQ Calibration : PASS
8759 20:11:43.252490 Jitter Meter : NO K
8760 20:11:43.255295 CBT Training : PASS
8761 20:11:43.258681 Write leveling : PASS
8762 20:11:43.258761 RX DQS gating : PASS
8763 20:11:43.261587 RX DQ/DQS(RDDQC) : PASS
8764 20:11:43.265584 TX DQ/DQS : PASS
8765 20:11:43.265678 RX DATLAT : PASS
8766 20:11:43.268343 RX DQ/DQS(Engine): PASS
8767 20:11:43.272340 TX OE : PASS
8768 20:11:43.272421 All Pass.
8769 20:11:43.272485
8770 20:11:43.272545 CH 1, Rank 0
8771 20:11:43.275160 SW Impedance : PASS
8772 20:11:43.279123 DUTY Scan : NO K
8773 20:11:43.279204 ZQ Calibration : PASS
8774 20:11:43.282072 Jitter Meter : NO K
8775 20:11:43.285299 CBT Training : PASS
8776 20:11:43.285379 Write leveling : PASS
8777 20:11:43.288153 RX DQS gating : PASS
8778 20:11:43.291183 RX DQ/DQS(RDDQC) : PASS
8779 20:11:43.291294 TX DQ/DQS : PASS
8780 20:11:43.294663 RX DATLAT : PASS
8781 20:11:43.294789 RX DQ/DQS(Engine): PASS
8782 20:11:43.298074 TX OE : PASS
8783 20:11:43.298155 All Pass.
8784 20:11:43.298219
8785 20:11:43.301130 CH 1, Rank 1
8786 20:11:43.301211 SW Impedance : PASS
8787 20:11:43.304779 DUTY Scan : NO K
8788 20:11:43.308045 ZQ Calibration : PASS
8789 20:11:43.308139 Jitter Meter : NO K
8790 20:11:43.311002 CBT Training : PASS
8791 20:11:43.314774 Write leveling : PASS
8792 20:11:43.314886 RX DQS gating : PASS
8793 20:11:43.318195 RX DQ/DQS(RDDQC) : PASS
8794 20:11:43.320961 TX DQ/DQS : PASS
8795 20:11:43.321046 RX DATLAT : PASS
8796 20:11:43.324408 RX DQ/DQS(Engine): PASS
8797 20:11:43.327971 TX OE : PASS
8798 20:11:43.328052 All Pass.
8799 20:11:43.328116
8800 20:11:43.331156 DramC Write-DBI on
8801 20:11:43.331237 PER_BANK_REFRESH: Hybrid Mode
8802 20:11:43.334145 TX_TRACKING: ON
8803 20:11:43.344019 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8804 20:11:43.350563 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8805 20:11:43.357534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8806 20:11:43.361089 [FAST_K] Save calibration result to emmc
8807 20:11:43.364195 sync common calibartion params.
8808 20:11:43.367147 sync cbt_mode0:0, 1:0
8809 20:11:43.367228 dram_init: ddr_geometry: 0
8810 20:11:43.370804 dram_init: ddr_geometry: 0
8811 20:11:43.373738 dram_init: ddr_geometry: 0
8812 20:11:43.377634 0:dram_rank_size:80000000
8813 20:11:43.377716 1:dram_rank_size:80000000
8814 20:11:43.383665 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8815 20:11:43.387375 DFS_SHUFFLE_HW_MODE: ON
8816 20:11:43.390946 dramc_set_vcore_voltage set vcore to 725000
8817 20:11:43.391027 Read voltage for 1600, 0
8818 20:11:43.394135 Vio18 = 0
8819 20:11:43.394216 Vcore = 725000
8820 20:11:43.394279 Vdram = 0
8821 20:11:43.397242 Vddq = 0
8822 20:11:43.397337 Vmddr = 0
8823 20:11:43.400077 switch to 3200 Mbps bootup
8824 20:11:43.400157 [DramcRunTimeConfig]
8825 20:11:43.400221 PHYPLL
8826 20:11:43.403657 DPM_CONTROL_AFTERK: ON
8827 20:11:43.406771 PER_BANK_REFRESH: ON
8828 20:11:43.406852 REFRESH_OVERHEAD_REDUCTION: ON
8829 20:11:43.410257 CMD_PICG_NEW_MODE: OFF
8830 20:11:43.413654 XRTWTW_NEW_MODE: ON
8831 20:11:43.413734 XRTRTR_NEW_MODE: ON
8832 20:11:43.416809 TX_TRACKING: ON
8833 20:11:43.416890 RDSEL_TRACKING: OFF
8834 20:11:43.420351 DQS Precalculation for DVFS: ON
8835 20:11:43.423481 RX_TRACKING: OFF
8836 20:11:43.423561 HW_GATING DBG: ON
8837 20:11:43.427082 ZQCS_ENABLE_LP4: ON
8838 20:11:43.427162 RX_PICG_NEW_MODE: ON
8839 20:11:43.431189 TX_PICG_NEW_MODE: ON
8840 20:11:43.431269 ENABLE_RX_DCM_DPHY: ON
8841 20:11:43.433723 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8842 20:11:43.436754 DUMMY_READ_FOR_TRACKING: OFF
8843 20:11:43.439734 !!! SPM_CONTROL_AFTERK: OFF
8844 20:11:43.443203 !!! SPM could not control APHY
8845 20:11:43.443284 IMPEDANCE_TRACKING: ON
8846 20:11:43.446573 TEMP_SENSOR: ON
8847 20:11:43.446654 HW_SAVE_FOR_SR: OFF
8848 20:11:43.449964 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8849 20:11:43.453030 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8850 20:11:43.456869 Read ODT Tracking: ON
8851 20:11:43.459827 Refresh Rate DeBounce: ON
8852 20:11:43.459908 DFS_NO_QUEUE_FLUSH: ON
8853 20:11:43.463177 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8854 20:11:43.466323 ENABLE_DFS_RUNTIME_MRW: OFF
8855 20:11:43.469816 DDR_RESERVE_NEW_MODE: ON
8856 20:11:43.469897 MR_CBT_SWITCH_FREQ: ON
8857 20:11:43.472567 =========================
8858 20:11:43.492200 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8859 20:11:43.495167 dram_init: ddr_geometry: 0
8860 20:11:43.513368 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8861 20:11:43.516245 dram_init: dram init end (result: 0)
8862 20:11:43.522664 DRAM-K: Full calibration passed in 23420 msecs
8863 20:11:43.526394 MRC: failed to locate region type 0.
8864 20:11:43.526475 DRAM rank0 size:0x80000000,
8865 20:11:43.529547 DRAM rank1 size=0x80000000
8866 20:11:43.539954 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8867 20:11:43.546290 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8868 20:11:43.552836 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8869 20:11:43.559717 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8870 20:11:43.562601 DRAM rank0 size:0x80000000,
8871 20:11:43.566114 DRAM rank1 size=0x80000000
8872 20:11:43.566194 CBMEM:
8873 20:11:43.569836 IMD: root @ 0xfffff000 254 entries.
8874 20:11:43.572727 IMD: root @ 0xffffec00 62 entries.
8875 20:11:43.576076 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8876 20:11:43.579359 WARNING: RO_VPD is uninitialized or empty.
8877 20:11:43.586102 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8878 20:11:43.592310 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8879 20:11:43.605168 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8880 20:11:43.617765 BS: romstage times (exec / console): total (unknown) / 22957 ms
8881 20:11:43.617846
8882 20:11:43.617910
8883 20:11:43.626479 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8884 20:11:43.630429 ARM64: Exception handlers installed.
8885 20:11:43.633168 ARM64: Testing exception
8886 20:11:43.636360 ARM64: Done test exception
8887 20:11:43.636441 Enumerating buses...
8888 20:11:43.640179 Show all devs... Before device enumeration.
8889 20:11:43.643201 Root Device: enabled 1
8890 20:11:43.646706 CPU_CLUSTER: 0: enabled 1
8891 20:11:43.646799 CPU: 00: enabled 1
8892 20:11:43.649536 Compare with tree...
8893 20:11:43.649632 Root Device: enabled 1
8894 20:11:43.653313 CPU_CLUSTER: 0: enabled 1
8895 20:11:43.656943 CPU: 00: enabled 1
8896 20:11:43.657053 Root Device scanning...
8897 20:11:43.659660 scan_static_bus for Root Device
8898 20:11:43.662775 CPU_CLUSTER: 0 enabled
8899 20:11:43.666057 scan_static_bus for Root Device done
8900 20:11:43.669518 scan_bus: bus Root Device finished in 8 msecs
8901 20:11:43.669600 done
8902 20:11:43.675910 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8903 20:11:43.679829 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8904 20:11:43.685934 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8905 20:11:43.689112 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8906 20:11:43.692597 Allocating resources...
8907 20:11:43.695832 Reading resources...
8908 20:11:43.698945 Root Device read_resources bus 0 link: 0
8909 20:11:43.702248 DRAM rank0 size:0x80000000,
8910 20:11:43.702318 DRAM rank1 size=0x80000000
8911 20:11:43.706330 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8912 20:11:43.709019 CPU: 00 missing read_resources
8913 20:11:43.715833 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8914 20:11:43.719107 Root Device read_resources bus 0 link: 0 done
8915 20:11:43.719205 Done reading resources.
8916 20:11:43.726038 Show resources in subtree (Root Device)...After reading.
8917 20:11:43.728885 Root Device child on link 0 CPU_CLUSTER: 0
8918 20:11:43.732556 CPU_CLUSTER: 0 child on link 0 CPU: 00
8919 20:11:43.742044 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8920 20:11:43.742145 CPU: 00
8921 20:11:43.745200 Root Device assign_resources, bus 0 link: 0
8922 20:11:43.748826 CPU_CLUSTER: 0 missing set_resources
8923 20:11:43.755576 Root Device assign_resources, bus 0 link: 0 done
8924 20:11:43.755690 Done setting resources.
8925 20:11:43.762393 Show resources in subtree (Root Device)...After assigning values.
8926 20:11:43.765531 Root Device child on link 0 CPU_CLUSTER: 0
8927 20:11:43.768813 CPU_CLUSTER: 0 child on link 0 CPU: 00
8928 20:11:43.778598 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8929 20:11:43.778683 CPU: 00
8930 20:11:43.782246 Done allocating resources.
8931 20:11:43.788385 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8932 20:11:43.788467 Enabling resources...
8933 20:11:43.788531 done.
8934 20:11:43.794901 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8935 20:11:43.794982 Initializing devices...
8936 20:11:43.798321 Root Device init
8937 20:11:43.801596 init hardware done!
8938 20:11:43.801677 0x00000018: ctrlr->caps
8939 20:11:43.805782 52.000 MHz: ctrlr->f_max
8940 20:11:43.805864 0.400 MHz: ctrlr->f_min
8941 20:11:43.808652 0x40ff8080: ctrlr->voltages
8942 20:11:43.811753 sclk: 390625
8943 20:11:43.811833 Bus Width = 1
8944 20:11:43.811897 sclk: 390625
8945 20:11:43.815542 Bus Width = 1
8946 20:11:43.815643 Early init status = 3
8947 20:11:43.821627 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8948 20:11:43.824678 in-header: 03 fc 00 00 01 00 00 00
8949 20:11:43.828265 in-data: 00
8950 20:11:43.831433 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8951 20:11:43.836528 in-header: 03 fd 00 00 00 00 00 00
8952 20:11:43.839887 in-data:
8953 20:11:43.842715 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8954 20:11:43.846673 in-header: 03 fc 00 00 01 00 00 00
8955 20:11:43.850171 in-data: 00
8956 20:11:43.852962 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8957 20:11:43.858152 in-header: 03 fd 00 00 00 00 00 00
8958 20:11:43.861792 in-data:
8959 20:11:43.864574 [SSUSB] Setting up USB HOST controller...
8960 20:11:43.868177 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8961 20:11:43.871760 [SSUSB] phy power-on done.
8962 20:11:43.874628 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8963 20:11:43.881650 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8964 20:11:43.884502 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8965 20:11:43.891637 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8966 20:11:43.898262 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8967 20:11:43.904721 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8968 20:11:43.912401 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8969 20:11:43.918715 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8970 20:11:43.918786 SPM: binary array size = 0x9dc
8971 20:11:43.924870 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8972 20:11:43.931354 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8973 20:11:43.937896 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8974 20:11:43.941154 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8975 20:11:43.947734 configure_display: Starting display init
8976 20:11:43.981369 anx7625_power_on_init: Init interface.
8977 20:11:43.984940 anx7625_disable_pd_protocol: Disabled PD feature.
8978 20:11:43.987808 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8979 20:11:44.015579 anx7625_start_dp_work: Secure OCM version=00
8980 20:11:44.019412 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8981 20:11:44.033800 sp_tx_get_edid_block: EDID Block = 1
8982 20:11:44.136970 Extracted contents:
8983 20:11:44.139530 header: 00 ff ff ff ff ff ff 00
8984 20:11:44.142967 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8985 20:11:44.146522 version: 01 04
8986 20:11:44.150112 basic params: 95 1f 11 78 0a
8987 20:11:44.152788 chroma info: 76 90 94 55 54 90 27 21 50 54
8988 20:11:44.156649 established: 00 00 00
8989 20:11:44.162683 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8990 20:11:44.169706 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8991 20:11:44.172479 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8992 20:11:44.179096 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8993 20:11:44.186134 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8994 20:11:44.188902 extensions: 00
8995 20:11:44.188979 checksum: fb
8996 20:11:44.189041
8997 20:11:44.195680 Manufacturer: IVO Model 57d Serial Number 0
8998 20:11:44.195759 Made week 0 of 2020
8999 20:11:44.199270 EDID version: 1.4
9000 20:11:44.199341 Digital display
9001 20:11:44.202493 6 bits per primary color channel
9002 20:11:44.202561 DisplayPort interface
9003 20:11:44.205665 Maximum image size: 31 cm x 17 cm
9004 20:11:44.208954 Gamma: 220%
9005 20:11:44.209025 Check DPMS levels
9006 20:11:44.212660 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9007 20:11:44.218849 First detailed timing is preferred timing
9008 20:11:44.218924 Established timings supported:
9009 20:11:44.222135 Standard timings supported:
9010 20:11:44.225908 Detailed timings
9011 20:11:44.229031 Hex of detail: 383680a07038204018303c0035ae10000019
9012 20:11:44.235841 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9013 20:11:44.239041 0780 0798 07c8 0820 hborder 0
9014 20:11:44.241961 0438 043b 0447 0458 vborder 0
9015 20:11:44.245013 -hsync -vsync
9016 20:11:44.245082 Did detailed timing
9017 20:11:44.251926 Hex of detail: 000000000000000000000000000000000000
9018 20:11:44.254885 Manufacturer-specified data, tag 0
9019 20:11:44.258967 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9020 20:11:44.261906 ASCII string: InfoVision
9021 20:11:44.265217 Hex of detail: 000000fe00523134304e574635205248200a
9022 20:11:44.268879 ASCII string: R140NWF5 RH
9023 20:11:44.268954 Checksum
9024 20:11:44.271862 Checksum: 0xfb (valid)
9025 20:11:44.274806 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9026 20:11:44.278282 DSI data_rate: 832800000 bps
9027 20:11:44.284909 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9028 20:11:44.288613 anx7625_parse_edid: pixelclock(138800).
9029 20:11:44.291461 hactive(1920), hsync(48), hfp(24), hbp(88)
9030 20:11:44.295881 vactive(1080), vsync(12), vfp(3), vbp(17)
9031 20:11:44.298251 anx7625_dsi_config: config dsi.
9032 20:11:44.304946 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9033 20:11:44.318142 anx7625_dsi_config: success to config DSI
9034 20:11:44.321829 anx7625_dp_start: MIPI phy setup OK.
9035 20:11:44.325018 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9036 20:11:44.328331 mtk_ddp_mode_set invalid vrefresh 60
9037 20:11:44.332068 main_disp_path_setup
9038 20:11:44.332140 ovl_layer_smi_id_en
9039 20:11:44.335507 ovl_layer_smi_id_en
9040 20:11:44.335574 ccorr_config
9041 20:11:44.335639 aal_config
9042 20:11:44.338825 gamma_config
9043 20:11:44.338890 postmask_config
9044 20:11:44.341909 dither_config
9045 20:11:44.344803 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9046 20:11:44.351553 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9047 20:11:44.354918 Root Device init finished in 553 msecs
9048 20:11:44.358064 CPU_CLUSTER: 0 init
9049 20:11:44.364852 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9050 20:11:44.371384 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9051 20:11:44.371456 APU_MBOX 0x190000b0 = 0x10001
9052 20:11:44.374921 APU_MBOX 0x190001b0 = 0x10001
9053 20:11:44.378069 APU_MBOX 0x190005b0 = 0x10001
9054 20:11:44.381065 APU_MBOX 0x190006b0 = 0x10001
9055 20:11:44.387626 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9056 20:11:44.397259 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9057 20:11:44.409832 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9058 20:11:44.416613 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9059 20:11:44.427918 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9060 20:11:44.437763 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9061 20:11:44.440985 CPU_CLUSTER: 0 init finished in 81 msecs
9062 20:11:44.444427 Devices initialized
9063 20:11:44.447511 Show all devs... After init.
9064 20:11:44.447585 Root Device: enabled 1
9065 20:11:44.450364 CPU_CLUSTER: 0: enabled 1
9066 20:11:44.453816 CPU: 00: enabled 1
9067 20:11:44.457435 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9068 20:11:44.460116 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9069 20:11:44.463404 ELOG: NV offset 0x57f000 size 0x1000
9070 20:11:44.470406 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9071 20:11:44.477128 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9072 20:11:44.480493 ELOG: Event(17) added with size 13 at 2024-03-03 20:11:44 UTC
9073 20:11:44.486849 out: cmd=0x121: 03 db 21 01 00 00 00 00
9074 20:11:44.490165 in-header: 03 02 00 00 2c 00 00 00
9075 20:11:44.500137 in-data: 61 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9076 20:11:44.507001 ELOG: Event(A1) added with size 10 at 2024-03-03 20:11:44 UTC
9077 20:11:44.513053 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9078 20:11:44.520399 ELOG: Event(A0) added with size 9 at 2024-03-03 20:11:44 UTC
9079 20:11:44.523239 elog_add_boot_reason: Logged dev mode boot
9080 20:11:44.530352 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9081 20:11:44.530437 Finalize devices...
9082 20:11:44.533673 Devices finalized
9083 20:11:44.536981 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9084 20:11:44.539813 Writing coreboot table at 0xffe64000
9085 20:11:44.543464 0. 000000000010a000-0000000000113fff: RAMSTAGE
9086 20:11:44.549476 1. 0000000040000000-00000000400fffff: RAM
9087 20:11:44.552891 2. 0000000040100000-000000004032afff: RAMSTAGE
9088 20:11:44.556406 3. 000000004032b000-00000000545fffff: RAM
9089 20:11:44.559879 4. 0000000054600000-000000005465ffff: BL31
9090 20:11:44.563031 5. 0000000054660000-00000000ffe63fff: RAM
9091 20:11:44.570104 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9092 20:11:44.573375 7. 0000000100000000-000000013fffffff: RAM
9093 20:11:44.576543 Passing 5 GPIOs to payload:
9094 20:11:44.579339 NAME | PORT | POLARITY | VALUE
9095 20:11:44.586030 EC in RW | 0x000000aa | low | undefined
9096 20:11:44.589429 EC interrupt | 0x00000005 | low | undefined
9097 20:11:44.592468 TPM interrupt | 0x000000ab | high | undefined
9098 20:11:44.598924 SD card detect | 0x00000011 | high | undefined
9099 20:11:44.602086 speaker enable | 0x00000093 | high | undefined
9100 20:11:44.605586 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9101 20:11:44.609418 in-header: 03 ef 00 00 02 00 00 00
9102 20:11:44.612094 in-data: 0c 00
9103 20:11:44.615938 ADC[4]: Raw value=668958 ID=5
9104 20:11:44.616011 ADC[3]: Raw value=212917 ID=1
9105 20:11:44.619008 RAM Code: 0x51
9106 20:11:44.621931 ADC[6]: Raw value=74778 ID=0
9107 20:11:44.622001 ADC[5]: Raw value=211812 ID=1
9108 20:11:44.625931 SKU Code: 0x1
9109 20:11:44.632956 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c2b6
9110 20:11:44.633031 coreboot table: 964 bytes.
9111 20:11:44.635267 IMD ROOT 0. 0xfffff000 0x00001000
9112 20:11:44.638684 IMD SMALL 1. 0xffffe000 0x00001000
9113 20:11:44.642020 RO MCACHE 2. 0xffffc000 0x00001104
9114 20:11:44.646336 CONSOLE 3. 0xfff7c000 0x00080000
9115 20:11:44.648997 FMAP 4. 0xfff7b000 0x00000452
9116 20:11:44.651750 TIME STAMP 5. 0xfff7a000 0x00000910
9117 20:11:44.655569 VBOOT WORK 6. 0xfff66000 0x00014000
9118 20:11:44.658587 RAMOOPS 7. 0xffe66000 0x00100000
9119 20:11:44.661674 COREBOOT 8. 0xffe64000 0x00002000
9120 20:11:44.665737 IMD small region:
9121 20:11:44.668163 IMD ROOT 0. 0xffffec00 0x00000400
9122 20:11:44.672084 VPD 1. 0xffffeb80 0x0000006c
9123 20:11:44.675346 MMC STATUS 2. 0xffffeb60 0x00000004
9124 20:11:44.678398 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9125 20:11:44.681898 Probing TPM: done!
9126 20:11:44.685740 Connected to device vid:did:rid of 1ae0:0028:00
9127 20:11:44.696290 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9128 20:11:44.699271 Initialized TPM device CR50 revision 0
9129 20:11:44.702870 Checking cr50 for pending updates
9130 20:11:44.706851 Reading cr50 TPM mode
9131 20:11:44.715693 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9132 20:11:44.722157 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9133 20:11:44.761903 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9134 20:11:44.765461 Checking segment from ROM address 0x40100000
9135 20:11:44.769212 Checking segment from ROM address 0x4010001c
9136 20:11:44.775434 Loading segment from ROM address 0x40100000
9137 20:11:44.775544 code (compression=0)
9138 20:11:44.785574 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9139 20:11:44.791814 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9140 20:11:44.791915 it's not compressed!
9141 20:11:44.798725 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9142 20:11:44.803026 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9143 20:11:44.822827 Loading segment from ROM address 0x4010001c
9144 20:11:44.822934 Entry Point 0x80000000
9145 20:11:44.826185 Loaded segments
9146 20:11:44.829288 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9147 20:11:44.835528 Jumping to boot code at 0x80000000(0xffe64000)
9148 20:11:44.843349 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9149 20:11:44.848971 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9150 20:11:44.857091 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9151 20:11:44.860597 Checking segment from ROM address 0x40100000
9152 20:11:44.863607 Checking segment from ROM address 0x4010001c
9153 20:11:44.870180 Loading segment from ROM address 0x40100000
9154 20:11:44.870282 code (compression=1)
9155 20:11:44.876894 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9156 20:11:44.886973 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9157 20:11:44.887074 using LZMA
9158 20:11:44.895802 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9159 20:11:44.902551 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9160 20:11:44.905122 Loading segment from ROM address 0x4010001c
9161 20:11:44.905199 Entry Point 0x54601000
9162 20:11:44.908466 Loaded segments
9163 20:11:44.911963 NOTICE: MT8192 bl31_setup
9164 20:11:44.918715 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9165 20:11:44.922087 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9166 20:11:44.925569 WARNING: region 0:
9167 20:11:44.929112 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 20:11:44.929183 WARNING: region 1:
9169 20:11:44.935543 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9170 20:11:44.938632 WARNING: region 2:
9171 20:11:44.942581 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9172 20:11:44.945187 WARNING: region 3:
9173 20:11:44.949065 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9174 20:11:44.952311 WARNING: region 4:
9175 20:11:44.958410 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9176 20:11:44.958489 WARNING: region 5:
9177 20:11:44.962626 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9178 20:11:44.965527 WARNING: region 6:
9179 20:11:44.968826 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 20:11:44.971957 WARNING: region 7:
9181 20:11:44.975317 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9182 20:11:44.981814 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9183 20:11:44.985233 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9184 20:11:44.989007 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9185 20:11:44.995188 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9186 20:11:44.998522 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9187 20:11:45.002060 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9188 20:11:45.008851 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9189 20:11:45.011908 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9190 20:11:45.018907 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9191 20:11:45.021882 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9192 20:11:45.025016 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9193 20:11:45.032396 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9194 20:11:45.035185 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9195 20:11:45.038887 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9196 20:11:45.045645 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9197 20:11:45.048614 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9198 20:11:45.055490 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9199 20:11:45.059859 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9200 20:11:45.062586 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9201 20:11:45.068540 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9202 20:11:45.071950 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9203 20:11:45.075428 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9204 20:11:45.082496 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9205 20:11:45.084830 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9206 20:11:45.091625 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9207 20:11:45.094813 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9208 20:11:45.102199 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9209 20:11:45.104832 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9210 20:11:45.108371 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9211 20:11:45.114842 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9212 20:11:45.118281 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9213 20:11:45.121710 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9214 20:11:45.128926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9215 20:11:45.132052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9216 20:11:45.135068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9217 20:11:45.138822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9218 20:11:45.145359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9219 20:11:45.148631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9220 20:11:45.151733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9221 20:11:45.155256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9222 20:11:45.161514 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9223 20:11:45.165044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9224 20:11:45.168569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9225 20:11:45.171809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9226 20:11:45.178896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9227 20:11:45.181840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9228 20:11:45.185206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9229 20:11:45.188713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9230 20:11:45.194975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9231 20:11:45.198760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9232 20:11:45.204896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9233 20:11:45.208080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9234 20:11:45.215823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9235 20:11:45.218549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9236 20:11:45.222003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9237 20:11:45.228185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9238 20:11:45.231593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9239 20:11:45.238576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9240 20:11:45.241345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9241 20:11:45.248143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9242 20:11:45.251207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9243 20:11:45.258365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9244 20:11:45.261288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9245 20:11:45.264547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9246 20:11:45.271427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9247 20:11:45.274437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9248 20:11:45.280828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9249 20:11:45.284412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9250 20:11:45.290789 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9251 20:11:45.294528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9252 20:11:45.301435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9253 20:11:45.304154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9254 20:11:45.307554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9255 20:11:45.314406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9256 20:11:45.317910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9257 20:11:45.324229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9258 20:11:45.327343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9259 20:11:45.334583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9260 20:11:45.337881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9261 20:11:45.341209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9262 20:11:45.347749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9263 20:11:45.350777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9264 20:11:45.357300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9265 20:11:45.360979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9266 20:11:45.367850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9267 20:11:45.371315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9268 20:11:45.377753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9269 20:11:45.380989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9270 20:11:45.383951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9271 20:11:45.390761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9272 20:11:45.394389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9273 20:11:45.400694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9274 20:11:45.404167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9275 20:11:45.410917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9276 20:11:45.413918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9277 20:11:45.417392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9278 20:11:45.424234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9279 20:11:45.427413 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9280 20:11:45.430639 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9281 20:11:45.434211 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9282 20:11:45.440872 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9283 20:11:45.444436 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9284 20:11:45.451217 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9285 20:11:45.453733 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9286 20:11:45.457885 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9287 20:11:45.463977 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9288 20:11:45.467116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9289 20:11:45.470597 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9290 20:11:45.477792 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9291 20:11:45.480924 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9292 20:11:45.487501 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9293 20:11:45.491140 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9294 20:11:45.494342 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9295 20:11:45.501227 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9296 20:11:45.503814 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9297 20:11:45.510976 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9298 20:11:45.513850 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9299 20:11:45.517404 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9300 20:11:45.524183 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9301 20:11:45.527517 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9302 20:11:45.530918 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9303 20:11:45.533756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9304 20:11:45.537532 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9305 20:11:45.543924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9306 20:11:45.547507 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9307 20:11:45.553626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9308 20:11:45.557150 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9309 20:11:45.560367 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9310 20:11:45.566918 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9311 20:11:45.570115 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9312 20:11:45.573608 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9313 20:11:45.580649 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9314 20:11:45.583484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9315 20:11:45.590572 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9316 20:11:45.593441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9317 20:11:45.600946 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9318 20:11:45.603860 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9319 20:11:45.606837 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9320 20:11:45.613895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9321 20:11:45.616634 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9322 20:11:45.620364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9323 20:11:45.626633 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9324 20:11:45.630065 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9325 20:11:45.637116 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9326 20:11:45.640319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9327 20:11:45.643543 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9328 20:11:45.650385 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9329 20:11:45.653382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9330 20:11:45.660384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9331 20:11:45.663584 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9332 20:11:45.666937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9333 20:11:45.673874 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9334 20:11:45.676637 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9335 20:11:45.680330 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9336 20:11:45.686464 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9337 20:11:45.689873 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9338 20:11:45.697203 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9339 20:11:45.700674 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9340 20:11:45.703628 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9341 20:11:45.709906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9342 20:11:45.713831 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9343 20:11:45.719912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9344 20:11:45.723080 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9345 20:11:45.726633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9346 20:11:45.733625 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9347 20:11:45.736444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9348 20:11:45.743005 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9349 20:11:45.746464 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9350 20:11:45.750190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9351 20:11:45.756276 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9352 20:11:45.759988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9353 20:11:45.766279 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9354 20:11:45.769465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9355 20:11:45.772948 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9356 20:11:45.779352 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9357 20:11:45.782728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9358 20:11:45.789468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9359 20:11:45.793009 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9360 20:11:45.796038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9361 20:11:45.802357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9362 20:11:45.805782 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9363 20:11:45.812343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9364 20:11:45.815867 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9365 20:11:45.819204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9366 20:11:45.826075 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9367 20:11:45.829082 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9368 20:11:45.832469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9369 20:11:45.840267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9370 20:11:45.842507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9371 20:11:45.848762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9372 20:11:45.852257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9373 20:11:45.858921 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9374 20:11:45.861913 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9375 20:11:45.865998 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9376 20:11:45.871846 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9377 20:11:45.875165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9378 20:11:45.881723 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9379 20:11:45.884726 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9380 20:11:45.891987 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9381 20:11:45.895571 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9382 20:11:45.898450 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9383 20:11:45.905370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9384 20:11:45.908158 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9385 20:11:45.915236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9386 20:11:45.918049 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9387 20:11:45.924955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9388 20:11:45.928250 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9389 20:11:45.931335 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9390 20:11:45.937762 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9391 20:11:45.941218 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9392 20:11:45.947647 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9393 20:11:45.950934 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9394 20:11:45.958026 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9395 20:11:45.961209 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9396 20:11:45.964148 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9397 20:11:45.971305 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9398 20:11:45.974901 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9399 20:11:45.980975 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9400 20:11:45.984675 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9401 20:11:45.987513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9402 20:11:45.993855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9403 20:11:45.997418 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9404 20:11:46.004319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9405 20:11:46.007317 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9406 20:11:46.013795 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9407 20:11:46.018443 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9408 20:11:46.020585 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9409 20:11:46.027152 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9410 20:11:46.030765 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9411 20:11:46.033856 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9412 20:11:46.040645 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9413 20:11:46.043450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9414 20:11:46.047500 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9415 20:11:46.050071 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9416 20:11:46.057411 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9417 20:11:46.060542 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9418 20:11:46.067183 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9419 20:11:46.069859 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9420 20:11:46.073623 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9421 20:11:46.080254 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9422 20:11:46.083710 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9423 20:11:46.086979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9424 20:11:46.093868 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9425 20:11:46.096875 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9426 20:11:46.103525 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9427 20:11:46.106815 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9428 20:11:46.109723 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9429 20:11:46.116251 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9430 20:11:46.119778 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9431 20:11:46.122816 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9432 20:11:46.129630 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9433 20:11:46.132857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9434 20:11:46.139849 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9435 20:11:46.142856 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9436 20:11:46.145748 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9437 20:11:46.152611 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9438 20:11:46.156375 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9439 20:11:46.159459 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9440 20:11:46.165848 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9441 20:11:46.169905 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9442 20:11:46.176199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9443 20:11:46.179225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9444 20:11:46.182450 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9445 20:11:46.188740 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9446 20:11:46.192435 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9447 20:11:46.195274 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9448 20:11:46.202021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9449 20:11:46.205415 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9450 20:11:46.209072 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9451 20:11:46.215230 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9452 20:11:46.218719 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9453 20:11:46.221778 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9454 20:11:46.225393 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9455 20:11:46.228981 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9456 20:11:46.235392 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9457 20:11:46.238385 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9458 20:11:46.241781 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9459 20:11:46.248990 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9460 20:11:46.251845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9461 20:11:46.255403 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9462 20:11:46.261814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9463 20:11:46.265279 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9464 20:11:46.268484 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9465 20:11:46.275058 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9466 20:11:46.277766 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9467 20:11:46.284508 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9468 20:11:46.287958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9469 20:11:46.291728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9470 20:11:46.298108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9471 20:11:46.300991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9472 20:11:46.307362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9473 20:11:46.310886 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9474 20:11:46.313948 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9475 20:11:46.320761 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9476 20:11:46.324347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9477 20:11:46.331366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9478 20:11:46.334595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9479 20:11:46.337764 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9480 20:11:46.344021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9481 20:11:46.347134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9482 20:11:46.353861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9483 20:11:46.357455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9484 20:11:46.363416 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9485 20:11:46.367311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9486 20:11:46.374324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9487 20:11:46.377444 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9488 20:11:46.380520 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9489 20:11:46.386883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9490 20:11:46.390747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9491 20:11:46.396925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9492 20:11:46.400244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9493 20:11:46.402960 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9494 20:11:46.409601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9495 20:11:46.413339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9496 20:11:46.420066 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9497 20:11:46.422792 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9498 20:11:46.426810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9499 20:11:46.433276 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9500 20:11:46.436502 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9501 20:11:46.443231 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9502 20:11:46.446572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9503 20:11:46.449727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9504 20:11:46.456254 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9505 20:11:46.459697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9506 20:11:46.466704 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9507 20:11:46.469986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9508 20:11:46.476423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9509 20:11:46.479184 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9510 20:11:46.482551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9511 20:11:46.489527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9512 20:11:46.492576 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9513 20:11:46.498861 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9514 20:11:46.502497 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9515 20:11:46.505547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9516 20:11:46.512203 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9517 20:11:46.516080 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9518 20:11:46.522763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9519 20:11:46.525585 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9520 20:11:46.529836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9521 20:11:46.535823 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9522 20:11:46.538658 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9523 20:11:46.545985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9524 20:11:46.548847 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9525 20:11:46.555135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9526 20:11:46.558575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9527 20:11:46.561851 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9528 20:11:46.568257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9529 20:11:46.572267 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9530 20:11:46.578476 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9531 20:11:46.582209 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9532 20:11:46.588441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9533 20:11:46.591638 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9534 20:11:46.594928 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9535 20:11:46.601206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9536 20:11:46.605170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9537 20:11:46.612472 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9538 20:11:46.614436 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9539 20:11:46.621526 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9540 20:11:46.624958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9541 20:11:46.627947 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9542 20:11:46.634673 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9543 20:11:46.637950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9544 20:11:46.644454 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9545 20:11:46.647582 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9546 20:11:46.654600 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9547 20:11:46.657477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9548 20:11:46.664531 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9549 20:11:46.667654 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9550 20:11:46.670749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9551 20:11:46.677223 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9552 20:11:46.680453 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9553 20:11:46.687249 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9554 20:11:46.690929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9555 20:11:46.697542 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9556 20:11:46.700373 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9557 20:11:46.706864 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9558 20:11:46.710116 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9559 20:11:46.713716 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9560 20:11:46.720203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9561 20:11:46.723653 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9562 20:11:46.730253 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9563 20:11:46.733396 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9564 20:11:46.739671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9565 20:11:46.743613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9566 20:11:46.749599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9567 20:11:46.752549 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9568 20:11:46.759402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9569 20:11:46.762477 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9570 20:11:46.766569 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9571 20:11:46.772699 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9572 20:11:46.775982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9573 20:11:46.783001 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9574 20:11:46.785615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9575 20:11:46.792261 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9576 20:11:46.795703 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9577 20:11:46.802120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9578 20:11:46.805875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9579 20:11:46.809448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9580 20:11:46.816103 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9581 20:11:46.819207 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9582 20:11:46.825346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9583 20:11:46.828464 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9584 20:11:46.832601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9585 20:11:46.839382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9586 20:11:46.842197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9587 20:11:46.848586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9588 20:11:46.851909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9589 20:11:46.858308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9590 20:11:46.861869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9591 20:11:46.868676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9592 20:11:46.871508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9593 20:11:46.878167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9594 20:11:46.881731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9595 20:11:46.888319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9596 20:11:46.891819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9597 20:11:46.897750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9598 20:11:46.901399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9599 20:11:46.908277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9600 20:11:46.911701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9601 20:11:46.917673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9602 20:11:46.920939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9603 20:11:46.927739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9604 20:11:46.931006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9605 20:11:46.937529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9606 20:11:46.940685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9607 20:11:46.947944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9608 20:11:46.950807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9609 20:11:46.957491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9610 20:11:46.960683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9611 20:11:46.967327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9612 20:11:46.970565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9613 20:11:46.977533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9614 20:11:46.980547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9615 20:11:46.987184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9616 20:11:46.990916 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9617 20:11:46.993575 INFO: [APUAPC] vio 0
9618 20:11:46.997199 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9619 20:11:47.004312 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9620 20:11:47.006650 INFO: [APUAPC] D0_APC_0: 0x400510
9621 20:11:47.010004 INFO: [APUAPC] D0_APC_1: 0x0
9622 20:11:47.010081 INFO: [APUAPC] D0_APC_2: 0x1540
9623 20:11:47.013204 INFO: [APUAPC] D0_APC_3: 0x0
9624 20:11:47.017130 INFO: [APUAPC] D1_APC_0: 0xffffffff
9625 20:11:47.019977 INFO: [APUAPC] D1_APC_1: 0xffffffff
9626 20:11:47.023589 INFO: [APUAPC] D1_APC_2: 0x3fffff
9627 20:11:47.027015 INFO: [APUAPC] D1_APC_3: 0x0
9628 20:11:47.030379 INFO: [APUAPC] D2_APC_0: 0xffffffff
9629 20:11:47.032985 INFO: [APUAPC] D2_APC_1: 0xffffffff
9630 20:11:47.036517 INFO: [APUAPC] D2_APC_2: 0x3fffff
9631 20:11:47.039627 INFO: [APUAPC] D2_APC_3: 0x0
9632 20:11:47.043189 INFO: [APUAPC] D3_APC_0: 0xffffffff
9633 20:11:47.046533 INFO: [APUAPC] D3_APC_1: 0xffffffff
9634 20:11:47.049873 INFO: [APUAPC] D3_APC_2: 0x3fffff
9635 20:11:47.052894 INFO: [APUAPC] D3_APC_3: 0x0
9636 20:11:47.056599 INFO: [APUAPC] D4_APC_0: 0xffffffff
9637 20:11:47.060133 INFO: [APUAPC] D4_APC_1: 0xffffffff
9638 20:11:47.062723 INFO: [APUAPC] D4_APC_2: 0x3fffff
9639 20:11:47.067101 INFO: [APUAPC] D4_APC_3: 0x0
9640 20:11:47.069637 INFO: [APUAPC] D5_APC_0: 0xffffffff
9641 20:11:47.073077 INFO: [APUAPC] D5_APC_1: 0xffffffff
9642 20:11:47.076520 INFO: [APUAPC] D5_APC_2: 0x3fffff
9643 20:11:47.079517 INFO: [APUAPC] D5_APC_3: 0x0
9644 20:11:47.082523 INFO: [APUAPC] D6_APC_0: 0xffffffff
9645 20:11:47.085733 INFO: [APUAPC] D6_APC_1: 0xffffffff
9646 20:11:47.088923 INFO: [APUAPC] D6_APC_2: 0x3fffff
9647 20:11:47.092376 INFO: [APUAPC] D6_APC_3: 0x0
9648 20:11:47.095956 INFO: [APUAPC] D7_APC_0: 0xffffffff
9649 20:11:47.099202 INFO: [APUAPC] D7_APC_1: 0xffffffff
9650 20:11:47.102498 INFO: [APUAPC] D7_APC_2: 0x3fffff
9651 20:11:47.106216 INFO: [APUAPC] D7_APC_3: 0x0
9652 20:11:47.109514 INFO: [APUAPC] D8_APC_0: 0xffffffff
9653 20:11:47.112225 INFO: [APUAPC] D8_APC_1: 0xffffffff
9654 20:11:47.115858 INFO: [APUAPC] D8_APC_2: 0x3fffff
9655 20:11:47.118997 INFO: [APUAPC] D8_APC_3: 0x0
9656 20:11:47.123204 INFO: [APUAPC] D9_APC_0: 0xffffffff
9657 20:11:47.125766 INFO: [APUAPC] D9_APC_1: 0xffffffff
9658 20:11:47.129603 INFO: [APUAPC] D9_APC_2: 0x3fffff
9659 20:11:47.132598 INFO: [APUAPC] D9_APC_3: 0x0
9660 20:11:47.135883 INFO: [APUAPC] D10_APC_0: 0xffffffff
9661 20:11:47.139250 INFO: [APUAPC] D10_APC_1: 0xffffffff
9662 20:11:47.142227 INFO: [APUAPC] D10_APC_2: 0x3fffff
9663 20:11:47.145621 INFO: [APUAPC] D10_APC_3: 0x0
9664 20:11:47.149179 INFO: [APUAPC] D11_APC_0: 0xffffffff
9665 20:11:47.152048 INFO: [APUAPC] D11_APC_1: 0xffffffff
9666 20:11:47.155225 INFO: [APUAPC] D11_APC_2: 0x3fffff
9667 20:11:47.158887 INFO: [APUAPC] D11_APC_3: 0x0
9668 20:11:47.161966 INFO: [APUAPC] D12_APC_0: 0xffffffff
9669 20:11:47.165345 INFO: [APUAPC] D12_APC_1: 0xffffffff
9670 20:11:47.168585 INFO: [APUAPC] D12_APC_2: 0x3fffff
9671 20:11:47.172209 INFO: [APUAPC] D12_APC_3: 0x0
9672 20:11:47.175109 INFO: [APUAPC] D13_APC_0: 0xffffffff
9673 20:11:47.178359 INFO: [APUAPC] D13_APC_1: 0xffffffff
9674 20:11:47.181832 INFO: [APUAPC] D13_APC_2: 0x3fffff
9675 20:11:47.185563 INFO: [APUAPC] D13_APC_3: 0x0
9676 20:11:47.188227 INFO: [APUAPC] D14_APC_0: 0xffffffff
9677 20:11:47.191294 INFO: [APUAPC] D14_APC_1: 0xffffffff
9678 20:11:47.194866 INFO: [APUAPC] D14_APC_2: 0x3fffff
9679 20:11:47.197824 INFO: [APUAPC] D14_APC_3: 0x0
9680 20:11:47.201857 INFO: [APUAPC] D15_APC_0: 0xffffffff
9681 20:11:47.204683 INFO: [APUAPC] D15_APC_1: 0xffffffff
9682 20:11:47.207934 INFO: [APUAPC] D15_APC_2: 0x3fffff
9683 20:11:47.211130 INFO: [APUAPC] D15_APC_3: 0x0
9684 20:11:47.214595 INFO: [APUAPC] APC_CON: 0x4
9685 20:11:47.218463 INFO: [NOCDAPC] D0_APC_0: 0x0
9686 20:11:47.221665 INFO: [NOCDAPC] D0_APC_1: 0x0
9687 20:11:47.224656 INFO: [NOCDAPC] D1_APC_0: 0x0
9688 20:11:47.228411 INFO: [NOCDAPC] D1_APC_1: 0xfff
9689 20:11:47.228484 INFO: [NOCDAPC] D2_APC_0: 0x0
9690 20:11:47.231289 INFO: [NOCDAPC] D2_APC_1: 0xfff
9691 20:11:47.234282 INFO: [NOCDAPC] D3_APC_0: 0x0
9692 20:11:47.238300 INFO: [NOCDAPC] D3_APC_1: 0xfff
9693 20:11:47.241080 INFO: [NOCDAPC] D4_APC_0: 0x0
9694 20:11:47.244513 INFO: [NOCDAPC] D4_APC_1: 0xfff
9695 20:11:47.247461 INFO: [NOCDAPC] D5_APC_0: 0x0
9696 20:11:47.250866 INFO: [NOCDAPC] D5_APC_1: 0xfff
9697 20:11:47.254153 INFO: [NOCDAPC] D6_APC_0: 0x0
9698 20:11:47.257234 INFO: [NOCDAPC] D6_APC_1: 0xfff
9699 20:11:47.261165 INFO: [NOCDAPC] D7_APC_0: 0x0
9700 20:11:47.263887 INFO: [NOCDAPC] D7_APC_1: 0xfff
9701 20:11:47.263960 INFO: [NOCDAPC] D8_APC_0: 0x0
9702 20:11:47.267634 INFO: [NOCDAPC] D8_APC_1: 0xfff
9703 20:11:47.271322 INFO: [NOCDAPC] D9_APC_0: 0x0
9704 20:11:47.274242 INFO: [NOCDAPC] D9_APC_1: 0xfff
9705 20:11:47.277116 INFO: [NOCDAPC] D10_APC_0: 0x0
9706 20:11:47.280772 INFO: [NOCDAPC] D10_APC_1: 0xfff
9707 20:11:47.284067 INFO: [NOCDAPC] D11_APC_0: 0x0
9708 20:11:47.287081 INFO: [NOCDAPC] D11_APC_1: 0xfff
9709 20:11:47.290962 INFO: [NOCDAPC] D12_APC_0: 0x0
9710 20:11:47.293476 INFO: [NOCDAPC] D12_APC_1: 0xfff
9711 20:11:47.297169 INFO: [NOCDAPC] D13_APC_0: 0x0
9712 20:11:47.300034 INFO: [NOCDAPC] D13_APC_1: 0xfff
9713 20:11:47.303443 INFO: [NOCDAPC] D14_APC_0: 0x0
9714 20:11:47.307108 INFO: [NOCDAPC] D14_APC_1: 0xfff
9715 20:11:47.310236 INFO: [NOCDAPC] D15_APC_0: 0x0
9716 20:11:47.313403 INFO: [NOCDAPC] D15_APC_1: 0xfff
9717 20:11:47.313477 INFO: [NOCDAPC] APC_CON: 0x4
9718 20:11:47.316655 INFO: [APUAPC] set_apusys_apc done
9719 20:11:47.320006 INFO: [DEVAPC] devapc_init done
9720 20:11:47.327181 INFO: GICv3 without legacy support detected.
9721 20:11:47.330421 INFO: ARM GICv3 driver initialized in EL3
9722 20:11:47.333261 INFO: Maximum SPI INTID supported: 639
9723 20:11:47.336573 INFO: BL31: Initializing runtime services
9724 20:11:47.343544 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9725 20:11:47.346710 INFO: SPM: enable CPC mode
9726 20:11:47.349703 INFO: mcdi ready for mcusys-off-idle and system suspend
9727 20:11:47.356681 INFO: BL31: Preparing for EL3 exit to normal world
9728 20:11:47.359843 INFO: Entry point address = 0x80000000
9729 20:11:47.359921 INFO: SPSR = 0x8
9730 20:11:47.366916
9731 20:11:47.367013
9732 20:11:47.367105
9733 20:11:47.370203 Starting depthcharge on Spherion...
9734 20:11:47.370301
9735 20:11:47.370388 Wipe memory regions:
9736 20:11:47.370472
9737 20:11:47.371363 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9738 20:11:47.371493 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9739 20:11:47.371606 Setting prompt string to ['asurada:']
9740 20:11:47.371713 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9741 20:11:47.373382 [0x00000040000000, 0x00000054600000)
9742 20:11:47.495861
9743 20:11:47.496009 [0x00000054660000, 0x00000080000000)
9744 20:11:47.756194
9745 20:11:47.756350 [0x000000821a7280, 0x000000ffe64000)
9746 20:11:48.501239
9747 20:11:48.501376 [0x00000100000000, 0x00000140000000)
9748 20:11:48.882535
9749 20:11:48.885424 Initializing XHCI USB controller at 0x11200000.
9750 20:11:49.923734
9751 20:11:49.926913 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9752 20:11:49.927382
9753 20:11:49.927755
9754 20:11:49.928106
9755 20:11:49.928964 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9757 20:11:50.030181 asurada: tftpboot 192.168.201.1 12928083/tftp-deploy-mbpqjfca/kernel/image.itb 12928083/tftp-deploy-mbpqjfca/kernel/cmdline
9758 20:11:50.030804 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9759 20:11:50.031263 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9760 20:11:50.036595 tftpboot 192.168.201.1 12928083/tftp-deploy-mbpqjfca/kernel/image.ittp-deploy-mbpqjfca/kernel/cmdline
9761 20:11:50.037141
9762 20:11:50.037530 Waiting for link
9763 20:11:50.195933
9764 20:11:50.196399 R8152: Initializing
9765 20:11:50.196751
9766 20:11:50.199931 Version 9 (ocp_data = 6010)
9767 20:11:50.200344
9768 20:11:50.202593 R8152: Done initializing
9769 20:11:50.203008
9770 20:11:50.203328 Adding net device
9771 20:11:52.141079
9772 20:11:52.141217 done.
9773 20:11:52.141282
9774 20:11:52.141341 MAC: 00:e0:4c:68:03:bd
9775 20:11:52.141398
9776 20:11:52.144863 Sending DHCP discover... done.
9777 20:11:52.144947
9778 20:11:52.147601 Waiting for reply... done.
9779 20:11:52.147691
9780 20:11:52.151538 Sending DHCP request... done.
9781 20:11:52.151617
9782 20:11:52.151681 Waiting for reply... done.
9783 20:11:52.151740
9784 20:11:52.153986 My ip is 192.168.201.16
9785 20:11:52.154066
9786 20:11:52.157717 The DHCP server ip is 192.168.201.1
9787 20:11:52.157797
9788 20:11:52.161116 TFTP server IP predefined by user: 192.168.201.1
9789 20:11:52.161196
9790 20:11:52.167810 Bootfile predefined by user: 12928083/tftp-deploy-mbpqjfca/kernel/image.itb
9791 20:11:52.167894
9792 20:11:52.170556 Sending tftp read request... done.
9793 20:11:52.170635
9794 20:11:52.173936 Waiting for the transfer...
9795 20:11:52.174017
9796 20:11:52.435771 00000000 ################################################################
9797 20:11:52.435905
9798 20:11:52.689707 00080000 ################################################################
9799 20:11:52.689844
9800 20:11:52.944156 00100000 ################################################################
9801 20:11:52.944313
9802 20:11:53.198009 00180000 ################################################################
9803 20:11:53.198138
9804 20:11:53.449917 00200000 ################################################################
9805 20:11:53.450050
9806 20:11:53.706198 00280000 ################################################################
9807 20:11:53.706335
9808 20:11:53.972782 00300000 ################################################################
9809 20:11:53.972924
9810 20:11:54.233723 00380000 ################################################################
9811 20:11:54.233857
9812 20:11:54.488695 00400000 ################################################################
9813 20:11:54.488833
9814 20:11:54.741598 00480000 ################################################################
9815 20:11:54.741755
9816 20:11:54.993292 00500000 ################################################################
9817 20:11:54.993427
9818 20:11:55.251756 00580000 ################################################################
9819 20:11:55.251889
9820 20:11:55.506806 00600000 ################################################################
9821 20:11:55.506967
9822 20:11:55.765095 00680000 ################################################################
9823 20:11:55.765225
9824 20:11:56.017464 00700000 ################################################################
9825 20:11:56.017593
9826 20:11:56.270858 00780000 ################################################################
9827 20:11:56.271028
9828 20:11:56.526740 00800000 ################################################################
9829 20:11:56.526871
9830 20:11:56.778476 00880000 ################################################################
9831 20:11:56.778610
9832 20:11:57.031168 00900000 ################################################################
9833 20:11:57.031310
9834 20:11:57.284404 00980000 ################################################################
9835 20:11:57.284556
9836 20:11:57.534145 00a00000 ################################################################
9837 20:11:57.534290
9838 20:11:57.783402 00a80000 ################################################################
9839 20:11:57.783555
9840 20:11:58.028576 00b00000 ################################################################
9841 20:11:58.028724
9842 20:11:58.281459 00b80000 ################################################################
9843 20:11:58.281602
9844 20:11:58.533287 00c00000 ################################################################
9845 20:11:58.533430
9846 20:11:58.789029 00c80000 ################################################################
9847 20:11:58.789166
9848 20:11:59.043131 00d00000 ################################################################
9849 20:11:59.043259
9850 20:11:59.297051 00d80000 ################################################################
9851 20:11:59.297192
9852 20:11:59.551991 00e00000 ################################################################
9853 20:11:59.552127
9854 20:11:59.813603 00e80000 ################################################################
9855 20:11:59.813740
9856 20:12:00.066156 00f00000 ################################################################
9857 20:12:00.066296
9858 20:12:00.338983 00f80000 ################################################################
9859 20:12:00.339129
9860 20:12:00.598265 01000000 ################################################################
9861 20:12:00.598400
9862 20:12:00.872960 01080000 ################################################################
9863 20:12:00.873092
9864 20:12:01.126534 01100000 ################################################################
9865 20:12:01.126666
9866 20:12:01.381128 01180000 ################################################################
9867 20:12:01.381268
9868 20:12:01.635245 01200000 ################################################################
9869 20:12:01.635383
9870 20:12:01.888921 01280000 ################################################################
9871 20:12:01.889059
9872 20:12:02.182698 01300000 ################################################################
9873 20:12:02.182836
9874 20:12:02.461778 01380000 ################################################################
9875 20:12:02.461953
9876 20:12:02.745679 01400000 ################################################################
9877 20:12:02.745826
9878 20:12:03.042788 01480000 ################################################################
9879 20:12:03.042926
9880 20:12:03.338962 01500000 ################################################################
9881 20:12:03.339095
9882 20:12:03.607892 01580000 ################################################################
9883 20:12:03.608026
9884 20:12:03.883387 01600000 ################################################################
9885 20:12:03.883521
9886 20:12:04.153209 01680000 ################################################################
9887 20:12:04.153342
9888 20:12:04.407527 01700000 ################################################################
9889 20:12:04.407660
9890 20:12:04.676608 01780000 ################################################################
9891 20:12:04.676778
9892 20:12:04.954009 01800000 ################################################################
9893 20:12:04.954140
9894 20:12:05.211512 01880000 ################################################################
9895 20:12:05.211660
9896 20:12:05.463615 01900000 ################################################################
9897 20:12:05.463742
9898 20:12:05.751697 01980000 ################################################################
9899 20:12:05.751830
9900 20:12:06.015168 01a00000 ################################################################
9901 20:12:06.015330
9902 20:12:06.290930 01a80000 ################################################################
9903 20:12:06.291061
9904 20:12:06.572002 01b00000 ################################################################
9905 20:12:06.572136
9906 20:12:06.830228 01b80000 ################################################################
9907 20:12:06.830366
9908 20:12:07.116479 01c00000 ################################################################
9909 20:12:07.116608
9910 20:12:07.386608 01c80000 ################################################################
9911 20:12:07.386739
9912 20:12:07.651319 01d00000 ################################################################
9913 20:12:07.651450
9914 20:12:07.917840 01d80000 ################################################################
9915 20:12:07.917975
9916 20:12:08.182501 01e00000 ################################################################
9917 20:12:08.182631
9918 20:12:08.462250 01e80000 ################################################################
9919 20:12:08.462388
9920 20:12:08.725967 01f00000 ################################################################
9921 20:12:08.726105
9922 20:12:08.986461 01f80000 ################################################################
9923 20:12:08.986602
9924 20:12:09.237705 02000000 ################################################################
9925 20:12:09.237837
9926 20:12:09.487610 02080000 ################################################################
9927 20:12:09.487747
9928 20:12:09.739338 02100000 ################################################################
9929 20:12:09.739495
9930 20:12:10.005944 02180000 ################################################################
9931 20:12:10.006090
9932 20:12:10.298536 02200000 ################################################################
9933 20:12:10.298683
9934 20:12:10.595813 02280000 ################################################################
9935 20:12:10.595975
9936 20:12:10.877517 02300000 ################################################################
9937 20:12:10.877646
9938 20:12:11.156286 02380000 ################################################################
9939 20:12:11.156423
9940 20:12:11.451001 02400000 ################################################################
9941 20:12:11.451143
9942 20:12:11.729115 02480000 ################################################################
9943 20:12:11.729249
9944 20:12:12.012319 02500000 ################################################################
9945 20:12:12.012456
9946 20:12:12.285050 02580000 ################################################################
9947 20:12:12.285192
9948 20:12:12.579620 02600000 ################################################################
9949 20:12:12.579829
9950 20:12:12.869350 02680000 ################################################################
9951 20:12:12.869490
9952 20:12:13.149848 02700000 ################################################################
9953 20:12:13.149983
9954 20:12:13.407215 02780000 ################################################################
9955 20:12:13.407354
9956 20:12:13.660025 02800000 ################################################################
9957 20:12:13.660155
9958 20:12:13.920309 02880000 ################################################################
9959 20:12:13.920446
9960 20:12:14.212985 02900000 ################################################################
9961 20:12:14.213121
9962 20:12:14.487081 02980000 ################################################################
9963 20:12:14.487218
9964 20:12:14.763383 02a00000 ################################################################
9965 20:12:14.763519
9966 20:12:15.040811 02a80000 ################################################################
9967 20:12:15.040944
9968 20:12:15.318816 02b00000 ################################################################
9969 20:12:15.318951
9970 20:12:15.586057 02b80000 ################################################################
9971 20:12:15.586193
9972 20:12:15.870615 02c00000 ################################################################
9973 20:12:15.870744
9974 20:12:16.136395 02c80000 ################################################################
9975 20:12:16.136529
9976 20:12:16.423084 02d00000 ################################################################
9977 20:12:16.423218
9978 20:12:16.708440 02d80000 ################################################################
9979 20:12:16.708584
9980 20:12:17.001726 02e00000 ################################################################
9981 20:12:17.001858
9982 20:12:17.280392 02e80000 ################################################################
9983 20:12:17.280531
9984 20:12:17.575273 02f00000 ################################################################
9985 20:12:17.575413
9986 20:12:17.854373 02f80000 ################################################################
9987 20:12:17.854507
9988 20:12:18.151689 03000000 ################################################################
9989 20:12:18.151826
9990 20:12:18.447545 03080000 ################################################################
9991 20:12:18.447698
9992 20:12:18.717908 03100000 ################################################################
9993 20:12:18.718051
9994 20:12:18.991615 03180000 ################################################################
9995 20:12:18.991749
9996 20:12:19.275821 03200000 ################################################################
9997 20:12:19.275960
9998 20:12:19.528483 03280000 ################################################################
9999 20:12:19.528606
10000 20:12:19.792011 03300000 ################################################################
10001 20:12:19.792147
10002 20:12:20.063269 03380000 ################################################################
10003 20:12:20.063406
10004 20:12:20.333335 03400000 ################################################################
10005 20:12:20.333464
10006 20:12:20.615181 03480000 ################################################################
10007 20:12:20.615312
10008 20:12:20.909471 03500000 ################################################################
10009 20:12:20.909608
10010 20:12:21.191873 03580000 ################################################################
10011 20:12:21.192003
10012 20:12:21.452841 03600000 ################################################################
10013 20:12:21.452969
10014 20:12:21.711431 03680000 ################################################################
10015 20:12:21.711572
10016 20:12:21.973550 03700000 ################################################################
10017 20:12:21.973687
10018 20:12:22.238299 03780000 ################################################################
10019 20:12:22.238432
10020 20:12:22.520251 03800000 ################################################################
10021 20:12:22.520383
10022 20:12:22.789777 03880000 ################################################################
10023 20:12:22.789907
10024 20:12:23.075445 03900000 ################################################################
10025 20:12:23.075581
10026 20:12:23.360881 03980000 ################################################################
10027 20:12:23.361016
10028 20:12:23.644167 03a00000 ################################################################
10029 20:12:23.644303
10030 20:12:23.900386 03a80000 ################################################################
10031 20:12:23.900542
10032 20:12:24.186195 03b00000 ################################################################
10033 20:12:24.186328
10034 20:12:24.463045 03b80000 ################################################################
10035 20:12:24.463179
10036 20:12:24.728001 03c00000 ################################################################
10037 20:12:24.728129
10038 20:12:24.983496 03c80000 ################################################################
10039 20:12:24.983621
10040 20:12:25.253113 03d00000 ################################################################
10041 20:12:25.253244
10042 20:12:25.506915 03d80000 ################################################################
10043 20:12:25.507044
10044 20:12:25.776605 03e00000 ################################################################
10045 20:12:25.776765
10046 20:12:26.062340 03e80000 ################################################################
10047 20:12:26.062477
10048 20:12:26.344379 03f00000 ################################################################
10049 20:12:26.344514
10050 20:12:26.643694 03f80000 ################################################################
10051 20:12:26.643827
10052 20:12:26.939855 04000000 ################################################################
10053 20:12:26.939991
10054 20:12:27.210162 04080000 ################################################################
10055 20:12:27.210291
10056 20:12:27.486470 04100000 ################################################################
10057 20:12:27.486615
10058 20:12:27.746006 04180000 ################################################################
10059 20:12:27.746144
10060 20:12:28.026064 04200000 ################################################################
10061 20:12:28.026206
10062 20:12:28.314908 04280000 ################################################################
10063 20:12:28.315057
10064 20:12:28.586675 04300000 ################################################################
10065 20:12:28.586823
10066 20:12:28.844294 04380000 ################################################################
10067 20:12:28.844432
10068 20:12:29.134779 04400000 ################################################################
10069 20:12:29.134913
10070 20:12:29.401433 04480000 ################################################################
10071 20:12:29.401568
10072 20:12:29.655169 04500000 ################################################################
10073 20:12:29.655308
10074 20:12:29.767103 04580000 ############################# done.
10075 20:12:29.772003
10076 20:12:29.774226 The bootfile was 73111450 bytes long.
10077 20:12:29.774655
10078 20:12:29.775173 Sending tftp read request... done.
10079 20:12:29.777641
10080 20:12:29.778153 Waiting for the transfer...
10081 20:12:29.778605
10082 20:12:29.781826 00000000 # done.
10083 20:12:29.782304
10084 20:12:29.788308 Command line loaded dynamically from TFTP file: 12928083/tftp-deploy-mbpqjfca/kernel/cmdline
10085 20:12:29.788933
10086 20:12:29.800389 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10087 20:12:29.804083
10088 20:12:29.804643 Loading FIT.
10089 20:12:29.805173
10090 20:12:29.808271 Image ramdisk-1 has 61002098 bytes.
10091 20:12:29.808771
10092 20:12:29.810636 Image fdt-1 has 47278 bytes.
10093 20:12:29.811050
10094 20:12:29.813923 Image kernel-1 has 12060038 bytes.
10095 20:12:29.814390
10096 20:12:29.821221 Compat preference: google,spherion-rev12-sku1 google,spherion-rev12 google,spherion-sku1 google,spherion
10097 20:12:29.821691
10098 20:12:29.840524 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10099 20:12:29.841190
10100 20:12:29.843384 Choosing best match conf-1 for compat google,spherion.
10101 20:12:29.848364
10102 20:12:29.852904 Connected to device vid:did:rid of 1ae0:0028:00
10103 20:12:29.860781
10104 20:12:29.864017 tpm_get_response: command 0x17b, return code 0x0
10105 20:12:29.864583
10106 20:12:29.867792 ec_init: CrosEC protocol v3 supported (256, 248)
10107 20:12:29.871652
10108 20:12:29.874966 tpm_cleanup: add release locality here.
10109 20:12:29.875530
10110 20:12:29.876010 Shutting down all USB controllers.
10111 20:12:29.878270
10112 20:12:29.878736 Removing current net device
10113 20:12:29.879212
10114 20:12:29.885261 Exiting depthcharge with code 4 at timestamp: 70728800
10115 20:12:29.885821
10116 20:12:29.889093 LZMA decompressing kernel-1 to 0x821a6718
10117 20:12:29.889657
10118 20:12:29.891484 LZMA decompressing kernel-1 to 0x40000000
10119 20:12:31.389335
10120 20:12:31.389901 jumping to kernel
10121 20:12:31.392164 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10122 20:12:31.392813 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10123 20:12:31.393271 Setting prompt string to ['Linux version [0-9]']
10124 20:12:31.393742 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 20:12:31.394207 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10126 20:12:31.439344
10127 20:12:31.442963 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10128 20:12:31.446360 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10129 20:12:31.447099 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10130 20:12:31.447532 Setting prompt string to []
10131 20:12:31.447973 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10132 20:12:31.448378 Using line separator: #'\n'#
10133 20:12:31.448743 No login prompt set.
10134 20:12:31.449092 Parsing kernel messages
10135 20:12:31.449400 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10136 20:12:31.449947 [login-action] Waiting for messages, (timeout 00:03:42)
10137 20:12:31.450302 Waiting using forced prompt support (timeout 00:01:51)
10138 20:12:31.467079 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10139 20:12:31.469930 [ 0.000000] random: crng init done
10140 20:12:31.475498 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10141 20:12:31.478623 [ 0.000000] efi: UEFI not found.
10142 20:12:31.485288 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10143 20:12:31.495906 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10144 20:12:31.506171 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10145 20:12:31.512297 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10146 20:12:31.518472 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10147 20:12:31.525391 [ 0.000000] printk: bootconsole [mtk8250] enabled
10148 20:12:31.532489 [ 0.000000] NUMA: No NUMA configuration found
10149 20:12:31.539835 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10150 20:12:31.545176 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10151 20:12:31.545731 [ 0.000000] Zone ranges:
10152 20:12:31.551614 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10153 20:12:31.554853 [ 0.000000] DMA32 empty
10154 20:12:31.561210 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10155 20:12:31.564438 [ 0.000000] Movable zone start for each node
10156 20:12:31.568858 [ 0.000000] Early memory node ranges
10157 20:12:31.574697 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10158 20:12:31.582637 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10159 20:12:31.587782 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10160 20:12:31.594421 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10161 20:12:31.602267 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10162 20:12:31.609270 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10163 20:12:31.638416 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10164 20:12:31.644907 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10165 20:12:31.652535 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10166 20:12:31.655775 [ 0.000000] psci: probing for conduit method from DT.
10167 20:12:31.661485 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10168 20:12:31.665042 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10169 20:12:31.671647 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10170 20:12:31.675753 [ 0.000000] psci: SMC Calling Convention v1.2
10171 20:12:31.681104 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10172 20:12:31.685110 [ 0.000000] Detected VIPT I-cache on CPU0
10173 20:12:31.691463 [ 0.000000] CPU features: detected: GIC system register CPU interface
10174 20:12:31.697760 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10175 20:12:31.704894 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10176 20:12:31.712879 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10177 20:12:31.721420 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10178 20:12:31.727781 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10179 20:12:31.731072 [ 0.000000] alternatives: applying boot alternatives
10180 20:12:31.737216 [ 0.000000] Fallback order for Node 0: 0
10181 20:12:31.744081 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10182 20:12:31.747504 [ 0.000000] Policy zone: Normal
10183 20:12:31.760269 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10184 20:12:31.770496 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10185 20:12:31.781125 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10186 20:12:31.792094 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10187 20:12:31.798088 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10188 20:12:31.801243 <6>[ 0.000000] software IO TLB: area num 8.
10189 20:12:31.856990 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10190 20:12:31.937589 <6>[ 0.000000] Memory: 3793208K/4191232K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 365256K reserved, 32768K cma-reserved)
10191 20:12:31.943012 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10192 20:12:31.949907 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10193 20:12:31.954233 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10194 20:12:31.960247 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10195 20:12:31.966642 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10196 20:12:31.970238 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10197 20:12:31.979648 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10198 20:12:31.986883 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10199 20:12:31.993892 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10200 20:12:32.000223 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10201 20:12:32.002986 <6>[ 0.000000] GICv3: 608 SPIs implemented
10202 20:12:32.006415 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10203 20:12:32.012911 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10204 20:12:32.016226 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10205 20:12:32.022849 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10206 20:12:32.036072 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10207 20:12:32.049718 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10208 20:12:32.055490 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10209 20:12:32.063400 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10210 20:12:32.076818 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10211 20:12:32.083186 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10212 20:12:32.090402 <6>[ 0.009174] Console: colour dummy device 80x25
10213 20:12:32.099517 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10214 20:12:32.106406 <6>[ 0.024406] pid_max: default: 32768 minimum: 301
10215 20:12:32.110006 <6>[ 0.029278] LSM: Security Framework initializing
10216 20:12:32.116064 <6>[ 0.034189] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10217 20:12:32.126978 <6>[ 0.041824] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10218 20:12:32.133522 <6>[ 0.051047] cblist_init_generic: Setting adjustable number of callback queues.
10219 20:12:32.139066 <6>[ 0.058490] cblist_init_generic: Setting shift to 3 and lim to 1.
10220 20:12:32.150738 <6>[ 0.064828] cblist_init_generic: Setting adjustable number of callback queues.
10221 20:12:32.156173 <6>[ 0.072255] cblist_init_generic: Setting shift to 3 and lim to 1.
10222 20:12:32.160424 <6>[ 0.078732] rcu: Hierarchical SRCU implementation.
10223 20:12:32.165640 <6>[ 0.078734] rcu: Max phase no-delay instances is 1000.
10224 20:12:32.172403 <6>[ 0.078758] printk: bootconsole [mtk8250] printing thread started
10225 20:12:32.178931 <6>[ 0.097089] EFI services will not be available.
10226 20:12:32.182169 <6>[ 0.097288] smp: Bringing up secondary CPUs ...
10227 20:12:32.185592 <6>[ 0.097599] Detected VIPT I-cache on CPU1
10228 20:12:32.195723 <6>[ 0.097666] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10229 20:12:32.202015 <6>[ 0.097698] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10230 20:12:32.211159 <6>[ 0.125590] Detected VIPT I-cache on CPU2
10231 20:12:32.217740 <6>[ 0.125637] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10232 20:12:32.224923 <6>[ 0.125653] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10233 20:12:32.231565 <6>[ 0.125911] Detected VIPT I-cache on CPU3
10234 20:12:32.237650 <6>[ 0.125958] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10235 20:12:32.244329 <6>[ 0.125971] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10236 20:12:32.248104 <6>[ 0.126282] CPU features: detected: Spectre-v4
10237 20:12:32.254591 <6>[ 0.126288] CPU features: detected: Spectre-BHB
10238 20:12:32.257893 <6>[ 0.126292] Detected PIPT I-cache on CPU4
10239 20:12:32.264762 <6>[ 0.126348] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10240 20:12:32.271928 <6>[ 0.126365] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10241 20:12:32.277648 <6>[ 0.126657] Detected PIPT I-cache on CPU5
10242 20:12:32.283839 <6>[ 0.126717] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10243 20:12:32.290497 <6>[ 0.126733] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10244 20:12:32.293639 <6>[ 0.127009] Detected PIPT I-cache on CPU6
10245 20:12:32.300109 <6>[ 0.127070] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10246 20:12:32.311558 <6>[ 0.127085] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10247 20:12:32.314103 <6>[ 0.127378] Detected PIPT I-cache on CPU7
10248 20:12:32.321223 <6>[ 0.127440] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10249 20:12:32.326901 <6>[ 0.127457] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10250 20:12:32.330779 <6>[ 0.127503] smp: Brought up 1 node, 8 CPUs
10251 20:12:32.337295 <6>[ 0.127508] SMP: Total of 8 processors activated.
10252 20:12:32.340169 <6>[ 0.127511] CPU features: detected: 32-bit EL0 Support
10253 20:12:32.351062 <6>[ 0.127513] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10254 20:12:32.357521 <6>[ 0.127516] CPU features: detected: Common not Private translations
10255 20:12:32.363832 <6>[ 0.127518] CPU features: detected: CRC32 instructions
10256 20:12:32.370214 <6>[ 0.127520] CPU features: detected: RCpc load-acquire (LDAPR)
10257 20:12:32.373629 <6>[ 0.127522] CPU features: detected: LSE atomic instructions
10258 20:12:32.380304 <6>[ 0.127524] CPU features: detected: Privileged Access Never
10259 20:12:32.386328 <6>[ 0.127525] CPU features: detected: RAS Extension Support
10260 20:12:32.393515 <6>[ 0.127529] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10261 20:12:32.396203 <6>[ 0.127597] CPU: All CPU(s) started at EL2
10262 20:12:32.402679 <6>[ 0.127599] alternatives: applying system-wide alternatives
10263 20:12:32.406417 <6>[ 0.139932] devtmpfs: initialized
10264 20:12:32.431877 �K�.ZH�X��e entries: 512 (order 0, 4096 bytes)
10265 20:12:32.435328 <6>[ 0.355071] printk: console [ttyS0] enabled
10266 20:12:32.441468 <6>[ 0.355078] printk: bootconsole [mtk8250] disabled
10267 20:12:32.445025 <6>[ 0.355083] printk: console [ttyS0] printing thread started
10268 20:12:32.451494 <6>[ 0.355093] printk: bootconsole [mtk8250] printing thread stopped
10269 20:12:32.458789 <6>[ 0.360762] SuperH (H)SCI(F) driver initialized
10270 20:12:32.461384 <6>[ 0.361235] msm_serial: driver initialized
10271 20:12:32.471445 <6>[ 0.365772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10272 20:12:32.477968 <6>[ 0.365801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10273 20:12:32.490972 <6>[ 0.365830] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10274 20:12:32.499629 <6>[ 0.365859] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10275 20:12:32.507970 <6>[ 0.365881] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10276 20:12:32.524422 <6>[ 0.365908] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10277 20:12:32.525071 <6>[ 0.365937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10278 20:12:32.533615 <6>[ 0.366047] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10279 20:12:32.538656 <6>[ 0.366075] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10280 20:12:32.542088 <6>[ 0.374096] loop: module loaded
10281 20:12:32.547211 <6>[ 0.376675] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10282 20:12:32.553332 <4>[ 0.393465] mtk-pmic-keys: Failed to locate of_node [id: -1]
10283 20:12:32.557888 <6>[ 0.394416] megasas: 07.719.03.00-rc1
10284 20:12:32.563713 <6>[ 0.404307] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10285 20:12:32.570844 <6>[ 0.406814] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10286 20:12:32.577317 <6>[ 0.418948] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10287 20:12:32.588976 <6>[ 0.472841] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10288 20:12:35.011883 <6>[ 2.928798] Freeing initrd memory: 59568K
10289 20:12:35.019490 <6>[ 2.936083] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10290 20:12:35.026098 <6>[ 2.940694] tun: Universal TUN/TAP device driver, 1.6
10291 20:12:35.029804 <6>[ 2.941434] thunder_xcv, ver 1.0
10292 20:12:35.033304 <6>[ 2.941451] thunder_bgx, ver 1.0
10293 20:12:35.036636 <6>[ 2.941467] nicpf, ver 1.0
10294 20:12:35.043659 <6>[ 2.942495] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10295 20:12:35.049542 <6>[ 2.942499] hns3: Copyright (c) 2017 Huawei Corporation.
10296 20:12:35.052980 <6>[ 2.942522] hclge is initializing
10297 20:12:35.056290 <6>[ 2.942536] e1000: Intel(R) PRO/1000 Network Driver
10298 20:12:35.063582 <6>[ 2.942538] e1000: Copyright (c) 1999-2006 Intel Corporation.
10299 20:12:35.070180 <6>[ 2.942557] e1000e: Intel(R) PRO/1000 Network Driver
10300 20:12:35.077228 <6>[ 2.942558] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10301 20:12:35.080229 <6>[ 2.942573] igb: Intel(R) Gigabit Ethernet Network Driver
10302 20:12:35.086879 <6>[ 2.942575] igb: Copyright (c) 2007-2014 Intel Corporation.
10303 20:12:35.093378 <6>[ 2.942588] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10304 20:12:35.099866 <6>[ 2.942590] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10305 20:12:35.104191 <6>[ 2.942878] sky2: driver version 1.30
10306 20:12:35.110229 <6>[ 2.943931] VFIO - User Level meta-driver version: 0.3
10307 20:12:35.116284 <6>[ 2.946708] usbcore: registered new interface driver usb-storage
10308 20:12:35.124206 <6>[ 2.946886] usbcore: registered new device driver onboard-usb-hub
10309 20:12:35.126154 <6>[ 2.949626] mt6397-rtc mt6359-rtc: registered as rtc0
10310 20:12:35.136544 <6>[ 2.949779] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:12:35 UTC (1709496755)
10311 20:12:35.140105 <6>[ 2.950381] i2c_dev: i2c /dev entries driver
10312 20:12:35.149913 <6>[ 2.957386] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10313 20:12:35.154740 <6>[ 2.972341] cpu cpu0: EM: created perf domain
10314 20:12:35.156062 <6>[ 2.972645] cpu cpu4: EM: created perf domain
10315 20:12:35.162934 <6>[ 2.974002] sdhci: Secure Digital Host Controller Interface driver
10316 20:12:35.171202 <6>[ 2.974003] sdhci: Copyright(c) Pierre Ossman
10317 20:12:35.176026 <6>[ 2.974313] Synopsys Designware Multimedia Card Interface Driver
10318 20:12:35.179539 <6>[ 2.974634] sdhci-pltfm: SDHCI platform and OF driver helper
10319 20:12:35.186562 <6>[ 2.977472] ledtrig-cpu: registered to indicate activity on CPUs
10320 20:12:35.192929 <6>[ 2.978061] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10321 20:12:35.196101 <6>[ 2.978059] mmc0: CQHCI version 5.10
10322 20:12:35.202565 <6>[ 2.978307] usbcore: registered new interface driver usbhid
10323 20:12:35.205878 <6>[ 2.978308] usbhid: USB HID core driver
10324 20:12:35.216300 <6>[ 2.978434] spi_master spi0: will run message pump with realtime priority
10325 20:12:35.219666 <6>[ 3.072994] mmc0: Command Queue Engine enabled
10326 20:12:35.226038 <6>[ 3.073007] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10327 20:12:35.230137 <6>[ 3.073536] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10328 20:12:35.235925 <6>[ 3.077619] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10329 20:12:35.242546 <6>[ 3.079437] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10330 20:12:35.246426 <6>[ 3.080225] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10331 20:12:35.252666 <6>[ 3.081002] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10332 20:12:35.278791 <6>[ 3.188294] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10333 20:12:35.291748 <6>[ 3.191318] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10334 20:12:35.300265 <6>[ 3.218474] cros-ec-spi spi0.0: Chrome EC device registered
10335 20:12:35.335122 <6>[ 3.248688] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10336 20:12:35.341835 <6>[ 3.254457] NET: Registered PF_PACKET protocol family
10337 20:12:35.345644 <6>[ 3.254654] 9pnet: Installing 9P2000 support
10338 20:12:35.352007 <5>[ 3.254719] Key type dns_resolver registered
10339 20:12:35.355485 <6>[ 3.255505] registered taskstats version 1
10340 20:12:35.358916 <5>[ 3.255541] Loading compiled-in X.509 certificates
10341 20:12:35.371544 <4>[ 3.272159] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10342 20:12:35.382937 <4>[ 3.272372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10343 20:12:35.388247 <3>[ 3.272387] debugfs: File 'uA_load' in directory '/' already present!
10344 20:12:35.395197 <3>[ 3.272396] debugfs: File 'min_uV' in directory '/' already present!
10345 20:12:35.400906 <3>[ 3.272401] debugfs: File 'max_uV' in directory '/' already present!
10346 20:12:35.407908 <3>[ 3.272406] debugfs: File 'constraint_flags' in directory '/' already present!
10347 20:12:35.417893 <3>[ 3.275481] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10348 20:12:35.424367 <6>[ 3.290608] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10349 20:12:35.428161 <6>[ 3.291373] xhci-mtk 11200000.usb: xHCI Host Controller
10350 20:12:35.438509 <6>[ 3.291419] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10351 20:12:35.444303 <6>[ 3.291671] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10352 20:12:35.450737 <6>[ 3.291740] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10353 20:12:35.457717 <6>[ 3.291898] xhci-mtk 11200000.usb: xHCI Host Controller
10354 20:12:35.465752 <6>[ 3.291914] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10355 20:12:35.471213 <6>[ 3.291929] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10356 20:12:35.477371 <6>[ 3.292717] hub 1-0:1.0: USB hub found
10357 20:12:35.480881 <6>[ 3.292753] hub 1-0:1.0: 1 port detected
10358 20:12:35.487935 <6>[ 3.293181] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10359 20:12:35.493710 <6>[ 3.293838] hub 2-0:1.0: USB hub found
10360 20:12:35.497627 <6>[ 3.293870] hub 2-0:1.0: 1 port detected
10361 20:12:35.500044 <6>[ 3.300302] mtk-msdc 11f70000.mmc: Got CD GPIO
10362 20:12:35.511323 <6>[ 3.332816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10363 20:12:35.516884 <6>[ 3.332829] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10364 20:12:35.526543 <4>[ 3.333132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10365 20:12:35.533385 <6>[ 3.334033] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10366 20:12:35.543959 <6>[ 3.334040] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10367 20:12:35.549885 <6>[ 3.334217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10368 20:12:35.556659 <6>[ 3.334239] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10369 20:12:35.566982 <6>[ 3.334247] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10370 20:12:35.576331 <6>[ 3.334256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10371 20:12:35.583242 <6>[ 3.336896] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10372 20:12:35.593068 <6>[ 3.336919] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10373 20:12:35.599538 <6>[ 3.336929] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10374 20:12:35.609596 <6>[ 3.336939] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10375 20:12:35.615854 <6>[ 3.336949] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10376 20:12:35.625688 <6>[ 3.336959] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10377 20:12:35.632189 <6>[ 3.336968] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10378 20:12:35.642000 <6>[ 3.336977] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10379 20:12:35.649719 <6>[ 3.336993] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10380 20:12:35.658807 <6>[ 3.337003] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10381 20:12:35.665398 <6>[ 3.337013] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10382 20:12:35.675703 <6>[ 3.337022] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10383 20:12:35.681679 <6>[ 3.337031] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10384 20:12:35.692121 <6>[ 3.337041] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10385 20:12:35.698458 <6>[ 3.337051] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10386 20:12:35.705573 <6>[ 3.337993] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10387 20:12:35.711849 <6>[ 3.339447] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10388 20:12:35.718887 <6>[ 3.340520] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10389 20:12:35.724923 <6>[ 3.341724] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10390 20:12:35.730978 <6>[ 3.342916] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10391 20:12:35.741909 <6>[ 3.343186] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10392 20:12:35.750992 <6>[ 3.343208] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10393 20:12:35.761009 <6>[ 3.343219] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10394 20:12:35.771489 <6>[ 3.343230] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10395 20:12:35.778292 <6>[ 3.343242] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10396 20:12:35.787370 <6>[ 3.343253] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10397 20:12:35.797632 <6>[ 3.343263] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10398 20:12:35.807446 <6>[ 3.343274] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10399 20:12:35.817063 <6>[ 3.343288] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10400 20:12:35.829197 <6>[ 3.343300] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10401 20:12:35.837038 <6>[ 3.343308] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10402 20:12:35.844157 <6>[ 3.344260] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10403 20:12:35.849980 <6>[ 3.715535] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10404 20:12:35.951901 <6>[ 3.869206] hub 1-1:1.0: USB hub found
10405 20:12:35.956525 <6>[ 3.869671] hub 1-1:1.0: 4 ports detected
10406 20:12:35.958186 <6>[ 3.873909] hub 1-1:1.0: USB hub found
10407 20:12:35.962532 <6>[ 3.874264] hub 1-1:1.0: 4 ports detected
10408 20:12:36.078861 <6>[ 3.991910] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10409 20:12:36.099557 <6>[ 4.016610] hub 2-1:1.0: USB hub found
10410 20:12:36.102923 <6>[ 4.017003] hub 2-1:1.0: 3 ports detected
10411 20:12:36.106212 <6>[ 4.020384] hub 2-1:1.0: USB hub found
10412 20:12:36.109589 <6>[ 4.020835] hub 2-1:1.0: 3 ports detected
10413 20:12:36.275537 <6>[ 4.187690] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10414 20:12:36.395694 <6>[ 4.314809] hub 1-1.4:1.0: USB hub found
10415 20:12:36.399197 <6>[ 4.315154] hub 1-1.4:1.0: 2 ports detected
10416 20:12:36.402340 <6>[ 4.317672] hub 1-1.4:1.0: USB hub found
10417 20:12:36.409305 <6>[ 4.317965] hub 1-1.4:1.0: 2 ports detected
10418 20:12:36.483360 <6>[ 4.395794] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10419 20:12:36.691745 <6>[ 4.603692] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10420 20:12:36.874746 <6>[ 4.787679] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10421 20:12:47.695133 <6>[ 15.616923] ALSA device list:
10422 20:12:47.701824 <6>[ 15.616945] No soundcards found.
10423 20:12:47.705206 <6>[ 15.621232] Freeing unused kernel memory: 8448K
10424 20:12:47.709102 <6>[ 15.621412] Run /init as init process
10425 20:12:47.750408 <6>[ 15.670441] NET: Registered PF_INET6 protocol family
10426 20:12:47.754004 <6>[ 15.671322] Segment Routing with IPv6
10427 20:12:47.761078 <6>[ 15.671339] In-situ OAM (IOAM) with IPv6
10428 20:12:47.770687
10429 20:12:47.803408 Welcome to [1mD<30>[ 15.694336] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10430 20:12:47.810773 <30>[ 15.694360] systemd[1]: Detected architecture arm64.
10431 20:12:47.811329 ebian GNU/Linux 12 (bookworm)[0m!
10432 20:12:47.813115
10433 20:12:47.830569 <30>[ 15.747820] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10434 20:12:48.022155 <30>[ 15.936611] systemd[1]: Queued start job for default target graphical.target.
10435 20:12:48.055882 [[0;32m OK [0m] Created slic<30>[ 15.969435] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10436 20:12:48.058808 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10437 20:12:48.087198 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.000693] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10438 20:12:48.089988 m-modpr…lice[0m - Slice /system/modprobe.
10439 20:12:48.115486 [[0;32m OK [0m] Created slic<30>[ 16.029098] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10440 20:12:48.121403 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10441 20:12:48.142549 [[0;32m OK [0m] Created slic<30>[ 16.056870] systemd[1]: Created slice user.slice - User and Session Slice.
10442 20:12:48.145970 e [0;1;39muser.slice[0m - User and Session Slice.
10443 20:12:48.169608 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 16.080394] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10444 20:12:48.172416 -passwo…quests to Console Directory Watch.
10445 20:12:48.196794 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 16.107952] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10446 20:12:48.200514 -passwo… Requests to Wall Directory Watch.
10447 20:12:48.235131 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 16.135817] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10448 20:12:48.242184 <30>[ 16.136082] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10449 20:12:48.244645 tsetup.…get[0m - Local Encrypted Volumes.
10450 20:12:48.268703 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 16.179791] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10451 20:12:48.272656 grityse…Local Integrity Protected Volumes.
10452 20:12:48.293465 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 16.207801] systemd[1]: Reached target paths.target - Path Units.
10453 20:12:48.294033 s.target[0m - Path Units.
10454 20:12:48.317979 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 16.232196] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10455 20:12:48.321985 te-fs.target[0m - Remote File Systems.
10456 20:12:48.341393 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 16.255736] systemd[1]: Reached target slices.target - Slice Units.
10457 20:12:48.345343 es.target[0m - Slice Units.
10458 20:12:48.365534 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 16.280192] systemd[1]: Reached target swap.target - Swaps.
10459 20:12:48.366098 .target[0m - Swaps.
10460 20:12:48.389658 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 16.304039] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10461 20:12:48.396163 tysetup… - Local Verity Protected Volumes.
10462 20:12:48.417718 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.331873] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10463 20:12:48.424009 d-initc… initctl Compatibility Named Pipe.
10464 20:12:48.446416 [[0;32m OK [0m] Listening on<30>[ 16.360737] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10465 20:12:48.452681 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10466 20:12:48.478227 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.388373] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10467 20:12:48.480534 d-journ…t[0m - Journal Socket (/dev/log).
10468 20:12:48.502193 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.416107] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10469 20:12:48.504973 d-journald.socket[0m - Journal Socket.
10470 20:12:48.526126 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.440094] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10471 20:12:48.532152 d-udevd….socket[0m - udev Control Socket.
10472 20:12:48.554617 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.468260] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10473 20:12:48.557525 d-udevd…l.socket[0m - udev Kernel Socket.
10474 20:12:48.613880 Mounting [0;1;39mdev-hugepages.mount[<30>[ 16.527866] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10475 20:12:48.616735 0m - Huge Pages File System...
10476 20:12:48.642397 Mounting [0;1;39mdev-mqueue.mount…P<30>[ 16.556340] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10477 20:12:48.645373 OSIX Message Queue File System...
10478 20:12:48.674537 Mounting [0;1;39msys-k<30>[ 16.588562] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10479 20:12:48.677442 ernel-debug.…[0m - Kernel Debug File System...
10480 20:12:48.708751 <30>[ 16.616202] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10481 20:12:48.717847 <30>[ 16.621905] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10482 20:12:48.724703 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10483 20:12:48.750463 Starting [0;1;39mmodpr<30>[ 16.664894] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10484 20:12:48.753668 obe@configfs…m - Load Kernel Module configfs...
10485 20:12:48.782596 Starting [0;1;39mmodprobe@dm_mod.s…[<30>[ 16.696261] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10486 20:12:48.786168 0m - Load Kernel Module dm_mod...
10487 20:12:48.797607 <6>[ 16.712346] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10488 20:12:48.809557 Startin<30>[ 16.726975] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10489 20:12:48.816384 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10490 20:12:48.839661 Startin<30>[ 16.754570] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10491 20:12:48.843419 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10492 20:12:48.865410 Startin<30>[ 16.782975] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10493 20:12:48.873457 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10494 20:12:48.918124 Starting [0;1;39msyste<30>[ 16.832606] systemd[1]: Starting systemd-journald.service - Journal Service...
10495 20:12:48.922163 md-journald.service[0m - Journal Service...
10496 20:12:48.946555 <30>[ 16.863183] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10497 20:12:48.952348 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10498 20:12:48.983130 Starting [0;1;39msyste<30>[ 16.893478] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10499 20:12:48.985907 md-network-g… units from Kernel command line...
10500 20:12:49.015707 Starting [0;1;39msyste<30>[ 16.929598] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10501 20:12:49.022833 md-remount-f…nt Root and Kernel File Systems...
10502 20:12:49.047971 Startin<30>[ 16.962360] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10503 20:12:49.052224 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10504 20:12:49.077435 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 16.991789] systemd[1]: Started systemd-journald.service - Journal Service.
10505 20:12:49.080605 rnald.service[0m - Journal Service.
10506 20:12:49.102855 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10507 20:12:49.118983 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10508 20:12:49.138767 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10509 20:12:49.160903 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10510 20:12:49.179770 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10511 20:12:49.205083 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10512 20:12:49.225192 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10513 20:12:49.245331 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10514 20:12:49.268417 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10515 20:12:49.289289 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10516 20:12:49.307507 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10517 20:12:49.329497 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10518 20:12:49.342800 See 'systemctl status systemd-remount-fs.service' for details.
10519 20:12:49.363717 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10520 20:12:49.385278 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10521 20:12:49.430485 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10522 20:12:49.450925 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10523 20:12:49.473514 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10524 20:12:49.485638 <46>[ 17.392102] systemd-journald[181]: Received client request to flush runtime journal.
10525 20:12:49.500289 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10526 20:12:49.521457 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10527 20:12:49.545687 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10528 20:12:49.568806 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10529 20:12:49.591209 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10530 20:12:49.611381 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10531 20:12:49.634964 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10532 20:12:49.686056 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10533 20:12:49.703634 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10534 20:12:49.722412 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10535 20:12:49.740391 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10536 20:12:49.795469 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10537 20:12:49.822116 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10538 20:12:49.863412 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10539 20:12:49.884262 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10540 20:12:49.928859 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10541 20:12:50.095438 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10542 20:12:50.122454 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10543 20:12:50.163135 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10544 20:12:50.187545 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10545 20:12:50.209144 <3>[ 18.125026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10546 20:12:50.216606 <3>[ 18.125049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10547 20:12:50.225426 <3>[ 18.125057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10548 20:12:50.232767 <6>[ 18.129915] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10549 20:12:50.242294 <6>[ 18.130000] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10550 20:12:50.252109 <6>[ 18.130011] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10551 20:12:50.258644 <3>[ 18.136191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10552 20:12:50.268612 [[0;32m OK [<3>[ 18.136209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10553 20:12:50.278923 0m] Created slic<3>[ 18.136212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10554 20:12:50.285609 <3>[ 18.136218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10555 20:12:50.295706 <3>[ 18.136221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10556 20:12:50.305136 e [0;1;39msyste<3>[ 18.143512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10557 20:12:50.311650 m-syste…- Slic<3>[ 18.148665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10558 20:12:50.321445 e /system/system<3>[ 18.148678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10559 20:12:50.332258 <3>[ 18.148683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10560 20:12:50.332806 d-backlight.
10561 20:12:50.339526 <6>[ 18.150248] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10562 20:12:50.347697 <3>[ 18.157203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10563 20:12:50.355051 <3>[ 18.157232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10564 20:12:50.364384 <3>[ 18.157242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10565 20:12:50.371399 <3>[ 18.157258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10566 20:12:50.381600 <3>[ 18.157265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10567 20:12:50.384738 <6>[ 18.162115] remoteproc remoteproc0: scp is available
10568 20:12:50.391770 <6>[ 18.162375] remoteproc remoteproc0: powering up scp
10569 20:12:50.398140 <6>[ 18.162387] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10570 20:12:50.403983 <6>[ 18.162437] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10571 20:12:50.414562 [[0;32m OK [<3>[ 18.186912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10572 20:12:50.421223 <6>[ 18.267849] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10573 20:12:50.425321 <6>[ 18.267867] pci_bus 0000:00: root bus resource [bus 00-ff]
10574 20:12:50.435780 0m] Reached targ<6>[ 18.267875] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10575 20:12:50.445462 <6>[ 18.267878] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10576 20:12:50.449056 <6>[ 18.267928] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10577 20:12:50.458843 et [0;1;39mtime<6>[ 18.267946] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10578 20:12:50.465909 <6>[ 18.268034] pci 0000:00:00.0: supports D1 D2
10579 20:12:50.473093 -set.target[0m <6>[ 18.268036] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10580 20:12:50.479654 - System Time Se<6>[ 18.269729] mc: Linux media interface: v0.10
10581 20:12:50.485417 <6>[ 18.288064] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10582 20:12:50.493022 <6>[ 18.288130] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10583 20:12:50.499504 <6>[ 18.288136] remoteproc remoteproc0: remote processor scp is now up
10584 20:12:50.510068 <6>[ 18.291530] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10585 20:12:50.515761 <6>[ 18.292508] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10586 20:12:50.522664 <6>[ 18.292561] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10587 20:12:50.528959 <6>[ 18.292589] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10588 20:12:50.535695 <6>[ 18.292610] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10589 20:12:50.542664 <6>[ 18.292751] pci 0000:01:00.0: supports D1 D2
10590 20:12:50.548360 <6>[ 18.292755] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10591 20:12:50.554967 <6>[ 18.295458] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10592 20:12:50.561767 <4>[ 18.295714] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10593 20:12:50.572378 <4>[ 18.295844] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10594 20:12:50.578460 <4>[ 18.325187] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10595 20:12:50.588608 <4>[ 18.325187] Fallback method does not support PEC.
10596 20:12:50.595753 <6>[ 18.325659] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10597 20:12:50.596227 t.
10598 20:12:50.605943 <6>[ 18.331273] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10599 20:12:50.612064 <3>[ 18.339263] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10600 20:12:50.618841 <6>[ 18.340439] usbcore: registered new device driver r8152-cfgselector
10601 20:12:50.625589 <6>[ 18.342756] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10602 20:12:50.632588 <6>[ 18.342799] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10603 20:12:50.642698 <6>[ 18.342806] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10604 20:12:50.649406 <6>[ 18.342820] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10605 20:12:50.656552 <6>[ 18.342837] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10606 20:12:50.667285 <6>[ 18.342853] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10607 20:12:50.670321 <6>[ 18.342868] pci 0000:00:00.0: PCI bridge to [bus 01]
10608 20:12:50.678006 <6>[ 18.342877] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10609 20:12:50.685715 <6>[ 18.354136] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10610 20:12:50.690968 <6>[ 18.363257] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10611 20:12:50.699090 <6>[ 18.363557] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10612 20:12:50.702237 <6>[ 18.377718] videodev: Linux video capture interface: v2.00
10613 20:12:50.711748 <3>[ 18.378396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10614 20:12:50.719308 <3>[ 18.379274] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10615 20:12:50.729174 <3>[ 18.401739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10616 20:12:50.739780 <6>[ 18.403387] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10617 20:12:50.745888 <5>[ 18.421981] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10618 20:12:50.752847 <6>[ 18.428770] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10619 20:12:50.763938 <6>[ 18.431058] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10620 20:12:50.769937 <5>[ 18.435362] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10621 20:12:50.776870 <5>[ 18.435603] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10622 20:12:50.786518 <4>[ 18.435675] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10623 20:12:50.793447 <6>[ 18.435682] cfg80211: failed to load regulatory.db
10624 20:12:50.800170 <6>[ 18.448578] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10625 20:12:50.803294 <6>[ 18.465036] Bluetooth: Core ver 2.22
10626 20:12:50.809673 <6>[ 18.465102] NET: Registered PF_BLUETOOTH protocol family
10627 20:12:50.816291 <6>[ 18.465105] Bluetooth: HCI device and connection manager initialized
10628 20:12:50.820090 <6>[ 18.465124] Bluetooth: HCI socket layer initialized
10629 20:12:50.826008 <6>[ 18.465137] Bluetooth: L2CAP socket layer initialized
10630 20:12:50.832666 <6>[ 18.465152] Bluetooth: SCO socket layer initialized
10631 20:12:50.839343 <6>[ 18.469691] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10632 20:12:50.852204 <6>[ 18.470739] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10633 20:12:50.855780 <6>[ 18.470839] usbcore: registered new interface driver uvcvideo
10634 20:12:50.865499 <4>[ 18.479972] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10635 20:12:50.875924 <4>[ 18.479985] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10636 20:12:50.882316 <6>[ 18.521291] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10637 20:12:50.886756 <6>[ 18.543635] r8152 2-1.3:1.0 eth0: v1.12.13
10638 20:12:50.892502 <6>[ 18.543782] usbcore: registered new interface driver r8152
10639 20:12:50.895458 <6>[ 18.546479] usbcore: registered new interface driver btusb
10640 20:12:50.905362 <4>[ 18.547283] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10641 20:12:50.912285 <3>[ 18.547302] Bluetooth: hci0: Failed to load firmware file (-2)
10642 20:12:50.918983 <3>[ 18.547305] Bluetooth: hci0: Failed to set up firmware (-2)
10643 20:12:50.928658 <4>[ 18.547308] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10644 20:12:50.937896 <3>[ 18.548172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10645 20:12:50.945004 <3>[ 18.549421] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10646 20:12:50.954903 <6>[ 18.559448] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10647 20:12:50.961040 <6>[ 18.559574] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10648 20:12:50.968581 <3>[ 18.560891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10649 20:12:50.978966 <3>[ 18.561600] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10650 20:12:50.984241 <6>[ 18.576625] usbcore: registered new interface driver cdc_ether
10651 20:12:50.988566 <6>[ 18.579579] mt7921e 0000:01:00.0: ASIC revision: 79610010
10652 20:12:50.997331 <3>[ 18.585359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 20:12:51.004281 <6>[ 18.592423] usbcore: registered new interface driver r8153_ecm
10654 20:12:51.011516 <3>[ 18.604735] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10655 20:12:51.017908 <6>[ 18.623115] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10656 20:12:51.027391 <6>[ 18.673681] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10657 20:12:51.028005 <6>[ 18.673681]
10658 20:12:51.037133 <6>[ 18.933738] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10659 20:12:51.043632 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10660 20:12:51.062552 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10661 20:12:51.122379 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10662 20:12:51.142212 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10663 20:12:51.159654 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10664 20:12:51.178325 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10665 20:12:51.194356 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10666 20:12:51.210292 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10667 20:12:51.225263 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10668 20:12:51.242099 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10669 20:12:51.257434 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10670 20:12:51.294852 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10671 20:12:51.323478 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10672 20:12:51.348148 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10673 20:12:51.383567 [[0;32m OK [0m] Started [0;1;39mdbus.servic<46>[ 19.285166] systemd-journald[181]: Data hash table of /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
10674 20:12:51.400285 e[0m - D-Bus Sy<46>[ 19.285184] systemd-journald[181]: /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal: Journal header limits reached or header out-of-date, rotating.
10675 20:12:51.403284 stem Message Bus.
10676 20:12:51.438774 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10677 20:12:51.487070 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10678 20:12:51.504564 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10679 20:12:51.521652 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10680 20:12:51.540429 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10681 20:12:51.558342 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10682 20:12:51.582774 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10683 20:12:51.608967 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10684 20:12:51.626634 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10685 20:12:51.674560 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10686 20:12:51.706701 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10687 20:12:51.747564
10688 20:12:51.748129
10689 20:12:51.751332 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10690 20:12:51.751805
10691 20:12:51.753945 debian-bookworm-arm64 login: root (automatic login)
10692 20:12:51.754485
10693 20:12:51.754942
10694 20:12:51.769716 Linux debian-bookworm-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10695 20:12:51.770328
10696 20:12:51.776046 The programs included with the Debian GNU/Linux system are free software;
10697 20:12:51.782158 the exact distribution terms for each program are described in the
10698 20:12:51.785580 individual files in /usr/share/doc/*/copyright.
10699 20:12:51.786099
10700 20:12:51.792092 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10701 20:12:51.795125 permitted by applicable law.
10702 20:12:51.796638 Matched prompt #10: / #
10704 20:12:51.797941 Setting prompt string to ['/ #']
10705 20:12:51.798519 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10707 20:12:51.799781 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10708 20:12:51.800354 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
10709 20:12:51.800911 Setting prompt string to ['/ #']
10710 20:12:51.801345 Forcing a shell prompt, looking for ['/ #']
10712 20:12:51.852411 / #
10713 20:12:51.853134 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10714 20:12:51.853805 Waiting using forced prompt support (timeout 00:02:30)
10715 20:12:51.860041
10716 20:12:51.861016 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10717 20:12:51.861667 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10718 20:12:51.862197 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10719 20:12:51.862673 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10720 20:12:51.863122 end: 2 depthcharge-action (duration 00:01:38) [common]
10721 20:12:51.863594 start: 3 lava-test-retry (timeout 00:07:57) [common]
10722 20:12:51.864060 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
10723 20:12:51.864470 Using namespace: common
10725 20:12:51.965700 / # #
10726 20:12:51.966331 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10727 20:12:51.966920 <6>[ 19.795773] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10728 20:12:51.972569 #
10729 20:12:51.973474 Using /lava-12928083
10731 20:12:52.074706 / # export SHELL=/bin/sh
10732 20:12:52.081705 export SHELL=/bin/sh
10734 20:12:52.183522 / # . /lava-12928083/environment
10735 20:12:52.191667 . /lava-12928083/environment
10737 20:12:52.293643 / # /lava-12928083/bin/lava-test-runner /lava-12928083/0
10738 20:12:52.294463 Test shell timeout: 10s (minimum of the action and connection timeout)
10739 20:12:52.300954 /lava-12928083/bin/lava-test-runner /lava-12928083/0
10740 20:12:52.326319 + export TESTRUN_ID=0_igt-kms-medi<8>[ 20.246767] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12928083_1.5.2.3.1>
10741 20:12:52.327186 Received signal: <STARTRUN> 0_igt-kms-mediatek 12928083_1.5.2.3.1
10742 20:12:52.327624 Starting test lava.0_igt-kms-mediatek (12928083_1.5.2.3.1)
10743 20:12:52.328201 Skipping test definition patterns.
10744 20:12:52.330091 atek
10745 20:12:52.333074 + cd /lava-12928083/0/tests/0_igt-kms-mediatek
10746 20:12:52.333783 + cat uuid
10747 20:12:52.337133 + UUID=12928083_1.5.2.3.1
10748 20:12:52.337651 + set +x
10749 20:12:52.355976 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic<8>[ 20.273726] <LAVA_SIGNAL_TESTSET START core_auth>
10750 20:12:52.356862 Received signal: <TESTSET> START core_auth
10751 20:12:52.357325 Starting test_set core_auth
10752 20:12:52.363873 kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
10753 20:12:52.369451 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1<14>[ 20.288790] [IGT] core_auth: executing
10754 20:12:52.378937 .80-cip16-rt9 aa<14>[ 20.289033] [IGT] core_auth: starting subtest getclient-simple
10755 20:12:52.379404 rch64)
10756 20:12:52.385304 Using IG<14>[ 20.289187] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
10757 20:12:52.393154 T_SRANDOM=170949<14>[ 20.289246] [IGT] core_auth: exiting, ret=0
10758 20:12:52.402209 6772 for randomi<8>[ 20.293731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
10759 20:12:52.402932 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
10761 20:12:52.405475 <14>[ 20.319335] [IGT] core_auth: executing
10762 20:12:52.411831 <14>[ 20.328073] [IGT] core_auth: starting subtest getclient-master-drop
10763 20:12:52.412344 sation
10764 20:12:52.422054 Starting<14>[ 20.338812] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
10765 20:12:52.428378 subtest: getcli<14>[ 20.338872] [IGT] core_auth: exiting, ret=0
10766 20:12:52.435389 <8>[ 20.344165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
10767 20:12:52.435959 ent-simple
10768 20:12:52.436609 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
10770 20:12:52.441835 Opened device: /dev/<14>[ 20.361299] [IGT] core_auth: executing
10771 20:12:52.448591 <14>[ 20.361628] [IGT] core_auth: starting subtest basic-auth
10772 20:12:52.454833 <14>[ 20.361751] [IGT] core_auth: finished subtest basic-auth, SUCCESS
10773 20:12:52.458263 <14>[ 20.361791] [IGT] core_auth: exiting, ret=0
10774 20:12:52.464430 <8>[ 20.365763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
10775 20:12:52.465201 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
10777 20:12:52.468056 <14>[ 20.380320] [IGT] core_auth: executing
10778 20:12:52.471740 dri/card0
10779 20:12:52.478311 [1mSubtest getclient-simple: SUCCESS<14>[ 20.395891] [IGT] core_auth: starting subtest many-magics
10780 20:12:52.481418 (0.000s)[0m
10781 20:12:52.491804 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aar<14>[ 20.407679] [IGT] core_auth: finished subtest many-magics, SUCCESS
10782 20:12:52.500072 <14>[ 20.407748] [IGT] core_auth: exiting, ret=0
10783 20:12:52.505800 <8>[ 20.411665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
10784 20:12:52.506538 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
10786 20:12:52.507976 <8>[ 20.412870] <LAVA_SIGNAL_TESTSET STOP>
10787 20:12:52.508394 ch64)
10788 20:12:52.509055 Received signal: <TESTSET> STOP
10789 20:12:52.509431 Closing test_set core_auth
10790 20:12:52.511070 Using IGT_SRANDOM=1709496772 for randomisation
10791 20:12:52.518486 Starting subtest: getclient-master-drop
10792 20:12:52.519045 Opened device: /dev/dri/card0
10793 20:12:52.524292 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
10794 20:12:52.530879 IGT-Version: 1.28-g0830a<14>[ 20.450486] [IGT] core_getclient: executing
10795 20:12:52.534568 <14>[ 20.450787] [IGT] core_getclient: exiting, ret=0
10796 20:12:52.541054 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
10798 20:12:52.544070 <8>[ 20.455298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
10799 20:12:52.548448 a7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10800 20:12:52.551006 Using IGT_SRANDOM=1709496772 for randomisation
10801 20:12:52.553739 Opened device: /dev/dri/card0
10802 20:12:52.557597 Starting subtest: basic-auth
10803 20:12:52.561327 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
10804 20:12:52.570500 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64<14>[ 20.489692] [IGT] core_getstats: executing
10805 20:12:52.571056 )
10806 20:12:52.577333 Using IGT_SRA<14>[ 20.490175] [IGT] core_getstats: exiting, ret=0
10807 20:12:52.584613 <8>[ 20.496477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
10808 20:12:52.585520 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
10810 20:12:52.587111 NDOM=1709496772 for randomisation
10811 20:12:52.591196 Opened device: /dev/dri/card0
10812 20:12:52.593791 Starting subtest: many-magics
10813 20:12:52.597618 Reopening device failed after 1020 opens
10814 20:12:52.604116 [1mSubtest many-magi<14>[ 20.520820] [IGT] core_getversion: executing
10815 20:12:52.607641 <14>[ 20.521094] [IGT] core_getversion: exiting, ret=0
10816 20:12:52.614667 <8>[ 20.526719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
10817 20:12:52.615518 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
10819 20:12:52.616766 cs: SUCCESS (0.012s)[0m
10820 20:12:52.623457 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10821 20:12:52.627139 Using IGT_SRANDOM=1709496772 for randomisation
10822 20:12:52.630233 Opened device: /dev/dri/card0
10823 20:12:52.634018 SUCCESS (0.000s)
10824 20:12:52.637542 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10825 20:12:52.643296 Using IGT_SRANDOM=1709496773 for randomisation
10826 20:12:52.643847 Opened device: /dev/dri/card0
10827 20:12:52.650172 SUCCES<14>[ 20.569747] [IGT] core_setmaster_vs_auth: executing
10828 20:12:52.656539 <14>[ 20.570350] [IGT] core_setmaster_vs_auth: exiting, ret=0
10829 20:12:52.663326 <8>[ 20.577421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
10830 20:12:52.664155 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
10832 20:12:52.667019 S (0.000s)
10833 20:12:52.673548 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10834 20:12:52.676582 Using IGT_SRANDOM=1709496773 for randomisation
10835 20:12:52.680318 Opened device: /dev/dri/card0
10836 20:12:52.680934 SUCCESS (0.000s)
10837 20:12:52.686890 IGT-Version: 1.28-g0830aa7 <8>[ 20.604986] <LAVA_SIGNAL_TESTSET START drm_read>
10838 20:12:52.687738 Received signal: <TESTSET> START drm_read
10839 20:12:52.688130 Starting test_set drm_read
10840 20:12:52.689333 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10841 20:12:52.697348 Using IGT_SRANDOM=1709496773 for randomisation
10842 20:12:52.701115 Opened device: /dev/dri/card0
10843 20:12:52.701576 SUCCESS (0.000s)
10844 20:12:52.705946 IGT-Version: 1.2<14>[ 20.626482] [IGT] drm_read: executing
10845 20:12:52.709508 <14>[ 20.627083] [IGT] drm_read: exiting, ret=77
10846 20:12:52.717005 <8>[ 20.633024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
10847 20:12:52.717737 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
10849 20:12:52.726566 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aa<14>[ 20.647004] [IGT] drm_read: executing
10850 20:12:52.727134 rch64)
10851 20:12:52.732798 Using IGT_SRANDOM=1709496773 for randomi<14>[ 20.647499] [IGT] drm_read: exiting, ret=77
10852 20:12:52.739431 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
10854 20:12:52.742849 <8>[ 20.658768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
10855 20:12:52.743409 sation
10856 20:12:52.745340 Opened device: /dev/dri/card0
10857 20:12:52.748512 No KMS driver or no outputs, pipes: 16, outputs: 0
10858 20:12:52.751980 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
10859 20:12:52.762670 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-ci<14>[ 20.682663] [IGT] drm_read: executing
10860 20:12:52.766460 <14>[ 20.683345] [IGT] drm_read: exiting, ret=77
10861 20:12:52.769121 p16-rt9 aarch64)
10862 20:12:52.775908 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
10864 20:12:52.779357 Using IGT_SRANDOM=1709496773 f<8>[ 20.693157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
10865 20:12:52.779925 or randomisation
10866 20:12:52.782072 Opened device: /dev/dri/card0
10867 20:12:52.785393 No KMS driver or no outputs, pipes: 16, outputs: 0
10868 20:12:52.788820 [1mSubtest fault-buffer: SKIP (0.000s)[0m
10869 20:12:52.799380 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6<14>[ 20.717068] [IGT] drm_read: executing
10870 20:12:52.802238 <14>[ 20.717636] [IGT] drm_read: exiting, ret=77
10871 20:12:52.808553 <8>[ 20.723119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
10872 20:12:52.809442 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
10874 20:12:52.812394 .1.80-cip16-rt9 aarch64)
10875 20:12:52.819110 Using IGT_SRANDOM=1709<14>[ 20.736889] [IGT] drm_read: executing
10876 20:12:52.821767 <14>[ 20.737292] [IGT] drm_read: exiting, ret=77
10877 20:12:52.828558 <8>[ 20.743989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
10878 20:12:52.829453 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
10880 20:12:52.831693 496773 for randomisation
10881 20:12:52.838306 Opened device: /dev/dr<14>[ 20.758535] [IGT] drm_read: executing
10882 20:12:52.841733 <14>[ 20.758955] [IGT] drm_read: exiting, ret=77
10883 20:12:52.851882 <8>[ 20.763155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
10884 20:12:52.852458 i/card0
10885 20:12:52.853159 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
10887 20:12:52.855609 No KMS driver or no outputs, pipes: 16, outputs: 0
10888 20:12:52.858310 [1mSubtest empty-block: SKIP (0.000s)[0m
10889 20:12:52.864563 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10890 20:12:52.871568 <14>[ 20.787658] [IGT] drm_read: executing
10891 20:12:52.875306 <14>[ 20.788286] [IGT] drm_read: exiting, ret=77
10892 20:12:52.881283 <8>[ 20.793936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
10893 20:12:52.882140 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
10895 20:12:52.885781 <8>[ 20.795414] <LAVA_SIGNAL_TESTSET STOP>
10896 20:12:52.886247
10897 20:12:52.886872 Received signal: <TESTSET> STOP
10898 20:12:52.887239 Closing test_set drm_read
10899 20:12:52.891269 Using IGT_SRANDOM=1709496773 for randomisation
10900 20:12:52.896097 <8>[ 20.812662] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
10901 20:12:52.896672
10902 20:12:52.897366 Received signal: <TESTSET> START kms_addfb_basic
10903 20:12:52.897743 Starting test_set kms_addfb_basic
10904 20:12:52.898444 Opened device: /dev/dri/card0
10905 20:12:52.905209 No KMS driver or no outputs, pipes: 16, outputs: 0
10906 20:12:52.907651 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
10907 20:12:52.914554 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10908 20:12:52.917543 Using IGT_SRANDOM=1709496773 for randomisation
10909 20:12:52.921596 Opene<14>[ 20.841855] [IGT] kms_addfb_basic: executing
10910 20:12:52.927637 <14>[ 20.846601] [IGT] kms_addfb_basic: starting subtest unused-handle
10911 20:12:52.930671 d device: /dev/dri/card0
10912 20:12:52.941415 No KMS driver or no ou<14>[ 20.855657] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
10913 20:12:52.947537 tputs, pipes: 16<14>[ 20.867349] [IGT] kms_addfb_basic: exiting, ret=0
10914 20:12:52.953790 <8>[ 20.873213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
10915 20:12:52.954348 , outputs: 0
10916 20:12:52.955001 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
10918 20:12:52.960367 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
10919 20:12:52.968239 IGT-Version: 1.<14>[ 20.885960] [IGT] kms_addfb_basic: executing
10920 20:12:52.973426 <14>[ 20.890376] [IGT] kms_addfb_basic: starting subtest unused-pitches
10921 20:12:52.980524 28-g0830aa7 (aar<14>[ 20.898735] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
10922 20:12:52.983509 ch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10923 20:12:52.990796 Using IGT_SRANDOM=17094<14>[ 20.907695] [IGT] kms_addfb_basic: exiting, ret=0
10924 20:12:52.999605 <8>[ 20.913200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
10925 20:12:53.000163 96773 for randomisation
10926 20:12:53.000860 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
10928 20:12:53.006609 Opened <14>[ 20.925741] [IGT] kms_addfb_basic: executing
10929 20:12:53.013648 <14>[ 20.930038] [IGT] kms_addfb_basic: starting subtest unused-offsets
10930 20:12:53.022769 device: /dev/dri<14>[ 20.939357] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
10931 20:12:53.023328 /card0
10932 20:12:53.029446 No KMS driver or no outputs, pipes: 16, <14>[ 20.948355] [IGT] kms_addfb_basic: exiting, ret=0
10933 20:12:53.037531 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
10935 20:12:53.039371 <8>[ 20.953800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
10936 20:12:53.039837 outputs: 0
10937 20:12:53.047338 [1mSubtest short-buffer-nonblock: S<14>[ 20.965193] [IGT] kms_addfb_basic: executing
10938 20:12:53.052608 <14>[ 20.969483] [IGT] kms_addfb_basic: starting subtest unused-modifier
10939 20:12:53.055990 KIP (0.000s)[0m
10940 20:12:53.065571 IGT-Version: 1.28-g0830aa7 (aa<14>[ 20.980163] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
10941 20:12:53.068974 rch64) (Linux: 6.1.80-cip16-rt9 aarch64)
10942 20:12:53.075962 Using <14>[ 20.992069] [IGT] kms_addfb_basic: exiting, ret=0
10943 20:12:53.083077 <8>[ 20.997072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
10944 20:12:53.083911 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
10946 20:12:53.085780 IGT_SRANDOM=1709496773 for randomisation
10947 20:12:53.089790 Opened<14>[ 21.008343] [IGT] kms_addfb_basic: executing
10948 20:12:53.098639 <14>[ 21.012673] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
10949 20:12:53.099244 device: /dev/dri/card0
10950 20:12:53.108920 No KMS driver or no out<14>[ 21.024153] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
10951 20:12:53.111977 puts, pipes: 16, outputs: 0
10952 20:12:53.119632 [1mSubtest short-b<14>[ 21.036089] [IGT] kms_addfb_basic: exiting, ret=77
10953 20:12:53.125250 <8>[ 21.041460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
10954 20:12:53.126093 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
10956 20:12:53.128856 uffer-wakeup: SKIP (0.000s)[0m
10957 20:12:53.135386 IGT-Version: 1.<14>[ 21.052833] [IGT] kms_addfb_basic: executing
10958 20:12:53.141638 <14>[ 21.057219] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
10959 20:12:53.154863 28-g0830aa7 (aarch64) (Linux: 6.<14>[ 21.069297] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
10960 20:12:53.155440 1.80-cip16-rt9 aarch64)
10961 20:12:53.161662 Using IGT_SRANDOM=17094<14>[ 21.080529] [IGT] kms_addfb_basic: exiting, ret=77
10962 20:12:53.171342 <8>[ 21.087088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
10963 20:12:53.172193 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
10965 20:12:53.174254 96773 for randomisation
10966 20:12:53.178030 Opened <14>[ 21.097975] [IGT] kms_addfb_basic: executing
10967 20:12:53.184342 <14>[ 21.102269] [IGT] kms_addfb_basic: starting subtest legacy-format
10968 20:12:53.187758 device: /dev/dri/card0
10969 20:12:53.190775 Starting subtest: unused-handle
10970 20:12:53.200592 [1mSubtest unused-handle: SUCCESS (0.0<14>[ 21.116325] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
10971 20:12:53.201189 00s)[0m
10972 20:12:53.210848 Test requirement not met in function igt_require_intel<14>[ 21.127710] [IGT] kms_addfb_basic: exiting, ret=0
10973 20:12:53.217534 <8>[ 21.132957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
10974 20:12:53.218391 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
10976 20:12:53.220472 , file ../lib/drmtest.c:880:
10977 20:12:53.223795 Test requirement: is_intel_device(fd)
10978 20:12:53.230628 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
10979 20:12:53.237301 Test requirement: is_in<14>[ 21.156277] [IGT] kms_addfb_basic: executing
10980 20:12:53.243969 <14>[ 21.163178] [IGT] kms_addfb_basic: starting subtest no-handle
10981 20:12:53.247748 tel_device(fd)
10982 20:12:53.253839 <14>[ 21.171251] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
10983 20:12:53.257431 No KMS driver or no outputs, pipes: 16, outputs: 0
10984 20:12:53.264175 IGT-Version:<14>[ 21.179774] [IGT] kms_addfb_basic: exiting, ret=0
10985 20:12:53.270880 <8>[ 21.185054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
10986 20:12:53.271734 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
10988 20:12:53.277440 1.28-g0830aa7 (aarch64) (Linux:<14>[ 21.197015] [IGT] kms_addfb_basic: executing
10989 20:12:53.280113 6.1.80-cip16-rt9 aarch64)
10990 20:12:53.283688 Using IGT_SRANDOM=1709496773 for randomisation
10991 20:12:53.286822 Opened device: /dev/dri/card0
10992 20:12:53.290211 Starting subtest: unused-pitches
10993 20:12:53.293261 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
10994 20:12:53.303152 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
10995 20:12:53.307042 Test requirement: is_intel_device(fd)
10996 20:12:53.313534 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
10997 20:12:53.316808 Test requirement: is_intel_device(fd)
10998 20:12:53.319821 No KMS driver or no outputs, pipes: 16, outputs: 0
10999 20:12:53.325980 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11000 20:12:53.329683 Using IGT_SRANDOM=1709496773 for randomisation
11001 20:12:53.332532 Opened device: /dev/dri/card0
11002 20:12:53.335962 Starting subtest: unused-offsets
11003 20:12:53.339460 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11004 20:12:53.349313 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11005 20:12:53.352896 Test requirement: is_intel_device(fd)
11006 20:12:53.359539 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11007 20:12:53.363248 Test requirement: is_intel_device(fd)
11008 20:12:53.365990 No KMS driver or no outputs, pipes: 16, outputs: 0
11009 20:12:53.373177 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11010 20:12:53.376311 Using IGT_SRANDOM=1709496773 for randomisation
11011 20:12:53.379118 Opened device: /dev/dri/card0
11012 20:12:53.382547 Starting subtest: unused-modifier
11013 20:12:53.385697 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11014 20:12:53.395226 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11015 20:12:53.398704 Test requirement: is_intel_device(fd)
11016 20:12:53.405179 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11017 20:12:53.408665 Test requirement: is_intel_device(fd)
11018 20:12:53.411986 No KMS driver or no outputs, pipes: 16, outputs: 0
11019 20:12:53.418345 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11020 20:12:53.422992 Using IGT_SRANDOM=1709496773 for randomisation
11021 20:12:53.424927 Opened device: /dev/dri/card0
11022 20:12:53.429070 Starting subtest: clobberred-modifier
11023 20:12:53.435661 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:885:
11024 20:12:53.438282 Test requirement: is_i915_device(fd)
11025 20:12:53.444862 [1mSubtest clobberred-modifier: SKIP (0.007s)[0m
11026 20:12:53.451247 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11027 20:12:53.454724 Test requirement: is_intel_device(fd)
11028 20:12:53.461677 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11029 20:12:53.465260 Test requirement: is_intel_device(fd)
11030 20:12:53.471398 No KMS driver or no outputs, pipes: 16, outputs: 0
11031 20:12:53.477978 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11032 20:12:53.481545 Using IGT_SRANDOM=1709496773 for randomisation
11033 20:12:53.484469 Opened device: /dev/dri/card0
11034 20:12:53.488301 Starting subtest: invalid-smem-bo-on-discrete
11035 20:12:53.494352 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11036 20:12:53.497693 Test requirement: is_intel_device(fd)
11037 20:12:53.504631 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.008s)[0m
11038 20:12:53.510914 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11039 20:12:53.514628 Test requirement: is_intel_device(fd)
11040 20:12:53.522189 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11041 20:12:53.523564 Test requirement: is_intel_device(fd)
11042 20:12:53.530531 No KMS driver or no outputs, pipes: 16, outputs: 0
11043 20:12:53.534104 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11044 20:12:53.540240 Using IGT_SRANDOM=1709496773 for randomisation
11045 20:12:53.544869 Opened device: /dev/dri/card0
11046 20:12:53.545425 Starting subtest: legacy-format
11047 20:12:53.550674 Successfully fuzzed 10000 {bpp, depth} variations
11048 20:12:53.553567 [1mSubtest legacy-format: SUCCESS (0.004s)[0m
11049 20:12:53.560058 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11050 20:12:53.564095 Test requirement: is_intel_device(fd)
11051 20:12:53.569777 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11052 20:12:53.573523 Test requirement: is_intel_device(fd)
11053 20:12:53.580914 No KMS driver or no outputs, pipes: 16, outputs: 0
11054 20:12:53.586544 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11055 20:12:53.590203 Using IGT_SRANDOM=1709496773 for randomisation
11056 20:12:53.593249 Opened device: /dev/dri/card0
11057 20:12:53.596573 Starting subtest: no-handle
11058 20:12:53.601208 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11059 20:12:53.607370 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11060 20:12:53.609659 Test requirement: is_intel_device(fd)
11061 20:12:53.617156 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11062 20:12:53.623714 Test requ<14>[ 21.541378] [IGT] kms_addfb_basic: starting subtest basic
11063 20:12:53.630300 <14>[ 21.541447] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11064 20:12:53.633979 irement: is_intel_device(fd)
11065 20:12:53.639782 No<14>[ 21.557104] [IGT] kms_addfb_basic: exiting, ret=0
11066 20:12:53.643083 <8>[ 21.562852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11067 20:12:53.643958 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11069 20:12:53.649172 KMS driver or no outputs, pipes: 16, outputs: 0
11070 20:12:53.659723 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 <14>[ 21.576313] [IGT] kms_addfb_basic: executing
11071 20:12:53.666171 <14>[ 21.582658] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11072 20:12:53.666679 aarch64)
11073 20:12:53.675815 Using IGT_SRANDOM=1709496773 for rando<14>[ 21.591965] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11074 20:12:53.676378 misation
11075 20:12:53.679700 Opened device: /dev/dri/card0
11076 20:12:53.687062 Starting subtest: basic<14>[ 21.603631] [IGT] kms_addfb_basic: exiting, ret=0
11077 20:12:53.692738 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11079 20:12:53.696262 <8>[ 21.608975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11080 20:12:53.696861
11081 20:12:53.699726 [1mSubtest basic: SUCCESS (0.000s)[0m
11082 20:12:53.702283 Test <14>[ 21.620955] [IGT] kms_addfb_basic: executing
11083 20:12:53.709038 <14>[ 21.627456] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11084 20:12:53.721947 requirement not met in function igt_require_inte<14>[ 21.636038] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11085 20:12:53.722513 l, file ../lib/drmtest.c:880:
11086 20:12:53.732312 Test requirement: is_intel_device<14>[ 21.647863] [IGT] kms_addfb_basic: exiting, ret=0
11087 20:12:53.738758 <8>[ 21.653198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11088 20:12:53.739318 (fd)
11089 20:12:53.739973 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11091 20:12:53.745224 Test requirement not met i<14>[ 21.665139] [IGT] kms_addfb_basic: executing
11092 20:12:53.752243 <14>[ 21.671592] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11093 20:12:53.761462 n function igt_r<14>[ 21.678899] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11094 20:12:53.764910 equire_intel, file ../lib/drmtest.c:880:
11095 20:12:53.772479 Test r<14>[ 21.687933] [IGT] kms_addfb_basic: exiting, ret=0
11096 20:12:53.777906 <8>[ 21.693188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11097 20:12:53.778816 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11099 20:12:53.782073 equirement: is_intel_device(fd)
11100 20:12:53.785219 No KMS driver or no outputs, pipes: 16, outputs: 0
11101 20:12:53.791748 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11102 20:12:53.797798 Using IGT_SRANDOM=1709496774 for ra<14>[ 21.716659] [IGT] kms_addfb_basic: executing
11103 20:12:53.804379 <14>[ 21.724196] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11104 20:12:53.804975 ndomisation
11105 20:12:53.808579 Opened device: /dev/dri/card0
11106 20:12:53.817531 Star<14>[ 21.731646] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11107 20:12:53.825103 ting subtest: ba<14>[ 21.743203] [IGT] kms_addfb_basic: exiting, ret=0
11108 20:12:53.825658 d-pitch-0
11109 20:12:53.831831 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11111 20:12:53.834956 [1mSubtest bad-pitch<8>[ 21.749715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11112 20:12:53.835533 -0: SUCCESS (0.000s)[0m
11113 20:12:53.841018 Test requirement not m<14>[ 21.761350] [IGT] kms_addfb_basic: executing
11114 20:12:53.848216 <14>[ 21.767913] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11115 20:12:53.857142 et in function i<14>[ 21.774676] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11116 20:12:53.861195 gt_require_intel, file ../lib/drmtest.c:880:
11117 20:12:53.866851 Test requirement: <14>[ 21.783612] [IGT] kms_addfb_basic: exiting, ret=0
11118 20:12:53.873548 <8>[ 21.789050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11119 20:12:53.874297 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11121 20:12:53.876883 is_intel_device(fd)
11122 20:12:53.880494 Test requir<14>[ 21.801151] [IGT] kms_addfb_basic: executing
11123 20:12:53.887200 <14>[ 21.807514] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11124 20:12:53.896853 ement not met in<14>[ 21.815087] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11125 20:12:53.907017 function igt_require_intel, file ../lib/drmtest<14>[ 21.824052] [IGT] kms_addfb_basic: exiting, ret=0
11126 20:12:53.913394 <8>[ 21.829284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11127 20:12:53.913958 .c:880:
11128 20:12:53.914621 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11130 20:12:53.916603 Test requirement: is_intel_device(fd)
11131 20:12:53.923511 <14>[ 21.840317] [IGT] kms_addfb_basic: executing
11132 20:12:53.929636 <14>[ 21.846799] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11133 20:12:53.939795 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 21.855576] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11134 20:12:53.940359 0
11135 20:12:53.946672 IGT-Version:<14>[ 21.867305] [IGT] kms_addfb_basic: exiting, ret=0
11136 20:12:53.952855 <8>[ 21.872869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11137 20:12:53.953702 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11139 20:12:53.959201 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11140 20:12:53.966441 Using IGT_SRANDOM=17<14>[ 21.883660] [IGT] kms_addfb_basic: executing
11141 20:12:53.972696 <14>[ 21.889876] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11142 20:12:53.979611 09496774 for ran<14>[ 21.898984] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11143 20:12:53.982773 domisation
11144 20:12:53.986121 Opened device: /dev/dri/card0
11145 20:12:53.989231 Start<14>[ 21.907987] [IGT] kms_addfb_basic: exiting, ret=0
11146 20:12:53.996199 <8>[ 21.913289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11147 20:12:53.997083 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11149 20:12:53.998974 ing subtest: bad-pitch-32
11150 20:12:54.005956 [1mSubtest bad-pitch<14>[ 21.924347] [IGT] kms_addfb_basic: executing
11151 20:12:54.012447 <14>[ 21.932570] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11152 20:12:54.015444 -32: SUCCESS (0.000s)[0m
11153 20:12:54.025303 Test requirement not <14>[ 21.940162] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11154 20:12:54.035375 met in function igt_require_intel, file ../lib/d<14>[ 21.952614] [IGT] kms_addfb_basic: exiting, ret=0
11155 20:12:54.042326 <8>[ 21.958008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11156 20:12:54.043311 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11158 20:12:54.045028 rmtest.c:880:
11159 20:12:54.049160 Test requirement:<14>[ 21.969264] [IGT] kms_addfb_basic: executing
11160 20:12:54.052292 is_intel_device(fd)
11161 20:12:54.059110 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11162 20:12:54.061885 Test requirement: is_intel_device(fd)
11163 20:12:54.069336 No KMS driver or no outputs, pipes: 16, outputs: 0
11164 20:12:54.071872 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11165 20:12:54.078201 Using IGT_SRANDOM=1709496774 for randomisation
11166 20:12:54.082143 Opened device: /dev/dri/card0
11167 20:12:54.082702 Starting subtest: bad-pitch-63
11168 20:12:54.088171 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11169 20:12:54.094980 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11170 20:12:54.097996 Test requirement: is_intel_device(fd)
11171 20:12:54.104665 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11172 20:12:54.108753 Test requirement: is_intel_device(fd)
11173 20:12:54.115005 No KMS driver or no outputs, pipes: 16, outputs: 0
11174 20:12:54.117507 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11175 20:12:54.125147 Using IGT_SRANDOM=1709496774 for randomisation
11176 20:12:54.125700 Opened device: /dev/dri/card0
11177 20:12:54.128232 Starting subtest: bad-pitch-128
11178 20:12:54.134101 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11179 20:12:54.141223 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11180 20:12:54.144485 Test requirement: is_intel_device(fd)
11181 20:12:54.152576 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11182 20:12:54.153729 Test requirement: is_intel_device(fd)
11183 20:12:54.157110 No KMS driver or no outputs, pipes: 16, outputs: 0
11184 20:12:54.164781 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11185 20:12:54.170565 Using IGT_SRANDOM=1709496774 for randomisation
11186 20:12:54.171142 Opened device: /dev/dri/card0
11187 20:12:54.173762 Starting subtest: bad-pitch-256
11188 20:12:54.181560 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11189 20:12:54.187302 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11190 20:12:54.190498 Test requirement: is_intel_device(fd)
11191 20:12:54.197067 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11192 20:12:54.201123 Test requirement: is_intel_device(fd)
11193 20:12:54.203754 No KMS driver or no outputs, pipes: 16, outputs: 0
11194 20:12:54.211314 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11195 20:12:54.216859 Using IGT_SRANDOM=1709496774 for randomisation
11196 20:12:54.217415 Opened device: /dev/dri/card0
11197 20:12:54.220170 Starting subtest: bad-pitch-1024
11198 20:12:54.226754 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11199 20:12:54.233291 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11200 20:12:54.236534 Test requirement: is_intel_device(fd)
11201 20:12:54.243143 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11202 20:12:54.247275 Test requirement: is_intel_device(fd)
11203 20:12:54.249948 No KMS driver or no outputs, pipes: 16, outputs: 0
11204 20:12:54.256001 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11205 20:12:54.262698 Using IGT_SRANDOM=1709496774 for randomisation
11206 20:12:54.263159 Opened device: /dev/dri/card0
11207 20:12:54.266135 Starting subtest: bad-pitch-999
11208 20:12:54.273538 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11209 20:12:54.279800 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11210 20:12:54.283060 Test requirement: is_intel_device(fd)
11211 20:12:54.289630 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11212 20:12:54.292603 Test requirement: is_intel_device(fd)
11213 20:12:54.296220 No KMS driver or no outputs, pipes: 16, outputs: 0
11214 20:12:54.302648 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11215 20:12:54.309332 Using IGT_SRANDOM=1709496774 for randomisation
11216 20:12:54.309885 Opened device: /dev/dri/card0
11217 20:12:54.312675 Starting subtest: bad-pitch-65536
11218 20:12:54.319796 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11219 20:12:54.325397 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11220 20:12:54.328742 Test requirement: is_intel_device(fd)
11221 20:12:54.335701 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11222 20:12:54.339388 Test requirement: is_intel_device(fd)
11223 20:12:54.345580 No KMS driver or no outputs, pipes: 16, outputs: 0
11224 20:12:54.348567 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11225 20:12:54.355330 Using IGT_SRANDOM=1709496774 for randomisation
11226 20:12:54.355882 Opened device: /dev/dri/card0
11227 20:12:54.361796 Starting subtest: invalid-get-prop-any
11228 20:12:54.365411 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11229 20:12:54.371538 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11230 20:12:54.375589 Test requirement: is_intel_device(fd)
11231 20:12:54.381684 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11232 20:12:54.388378 Test requirement: is_intel_device(fd)
11233 20:12:54.391892 No KMS driver or no outputs, pipes: 16, outputs: 0
11234 20:12:54.398656 IGT-Version: 1.28-g0<14>[ 22.315421] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11235 20:12:54.408093 <14>[ 22.315505] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11236 20:12:54.411134 <14>[ 22.319452] [IGT] kms_addfb_basic: exiting, ret=0
11237 20:12:54.418493 <8>[ 22.331535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11238 20:12:54.419365 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11240 20:12:54.424794 830aa7 (aarch64)<14>[ 22.346378] [IGT] kms_addfb_basic: executing
11241 20:12:54.428011 (Linux: 6.1.80-cip16-rt9 aarch64)
11242 20:12:54.437935 Using IGT_SR<14>[ 22.354592] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11243 20:12:54.444121 <14>[ 22.354664] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11244 20:12:54.448432 ANDOM=1709496774 for randomisation
11245 20:12:54.454531 Opened devic<14>[ 22.371756] [IGT] kms_addfb_basic: exiting, ret=0
11246 20:12:54.460778 <8>[ 22.377271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11247 20:12:54.461598 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11249 20:12:54.463722 e: /dev/dri/card0
11250 20:12:54.470465 Starting subtest: invalid-get<14>[ 22.388646] [IGT] kms_addfb_basic: executing
11251 20:12:54.477436 <14>[ 22.396861] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11252 20:12:54.477981 -prop
11253 20:12:54.487510 [1mSubtest invalid-get-prop: SUCCESS (0.<14>[ 22.404166] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11254 20:12:54.490509 000s)[0m
11255 20:12:54.497259 Test requirement not met in function <14>[ 22.416064] [IGT] kms_addfb_basic: exiting, ret=0
11256 20:12:54.504557 <8>[ 22.421289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11257 20:12:54.505458 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11259 20:12:54.510725 igt_require_intel, file ../lib/drmtest.c:880:
11260 20:12:54.513801 T<14>[ 22.432475] [IGT] kms_addfb_basic: executing
11261 20:12:54.524083 est requirement: is_intel_device<14>[ 22.442601] [IGT] kms_addfb_basic: starting subtest master-rmfb
11262 20:12:54.530102 <14>[ 22.442756] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11263 20:12:54.530650 (fd)
11264 20:12:54.537119 Test requirement not met i<14>[ 22.457541] [IGT] kms_addfb_basic: exiting, ret=0
11265 20:12:54.546832 <8>[ 22.463057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11266 20:12:54.547670 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11268 20:12:54.549800 n function igt_require_intel, file ../lib/drmtest.c:880:
11269 20:12:54.553600 Test requirement: is_intel_device(fd)
11270 20:12:54.560086 No KMS driver or no outputs, pipes: 16, outputs: 0
11271 20:12:54.567095 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux<14>[ 22.486692] [IGT] kms_addfb_basic: executing
11272 20:12:54.569667 : 6.1.80-cip16-rt9 aarch64)
11273 20:12:54.574710 Using IGT_SRANDOM=1709496774 for randomisation
11274 20:12:54.579599 Ope<14>[ 22.499187] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11275 20:12:54.589624 <14>[ 22.499268] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11276 20:12:54.592651 <14>[ 22.499661] [IGT] kms_addfb_basic: exiting, ret=0
11277 20:12:54.602699 <8>[ 22.513137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11278 20:12:54.603551 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11280 20:12:54.606302 ned device: /dev/dri/card0
11281 20:12:54.610813 Star<14>[ 22.529186] [IGT] kms_addfb_basic: executing
11282 20:12:54.613423 ting subtest: invalid-set-prop-any
11283 20:12:54.622930 [1mSubtest invalid-set-prop-any: SUCCESS (0<14>[ 22.541167] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11284 20:12:54.625895 .000s)[0m
11285 20:12:54.635658 Test requirement not met in function igt_require_int<14>[ 22.553481] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11286 20:12:54.639142 el, file ../lib/drmtest.c:880:
11287 20:12:54.643159 Test requirement: is_intel_device(fd)
11288 20:12:54.649334 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11289 20:12:54.655651 Test requirement: is_intel_device(fd)
11290 20:12:54.658446 No KMS driver or no outputs, pipes: 16, outputs: 0
11291 20:12:54.665046 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11292 20:12:54.669005 Using IGT_SRANDOM=1709496774 for randomisation
11293 20:12:54.672085 Opened device: /dev/dri/card0
11294 20:12:54.675077 Starting subtest: invalid-set-prop
11295 20:12:54.680533 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11296 20:12:54.685345 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11297 20:12:54.688471 Test requirement: is_intel_device(fd)
11298 20:12:54.698183 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11299 20:12:54.701397 Test requirement: is_intel_device(fd)
11300 20:12:54.704795 No KMS driver or no outputs, pipes: 16, outputs: 0
11301 20:12:54.711876 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11302 20:12:54.714827 Using IGT_SRANDOM=1709496774 for randomisation
11303 20:12:54.718060 Opened device: /dev/dri/card0
11304 20:12:54.721850 Starting subtest: master-rmfb
11305 20:12:54.724647 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11306 20:12:54.731160 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11307 20:12:54.735141 Test requirement: is_intel_device(fd)
11308 20:12:54.745097 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11309 20:12:54.747689 Test requirement: is_intel_device(fd)
11310 20:12:54.752676 No KMS driver or no outputs, pipes: 16, outputs: 0
11311 20:12:54.757655 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11312 20:12:54.761017 Using IGT_SRANDOM=1709496775 for randomisation
11313 20:12:54.764218 Opened device: /dev/dri/card0
11314 20:12:54.768079 Starting subtest: addfb25-modifier-no-flag
11315 20:12:54.774250 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11316 20:12:54.781040 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11317 20:12:54.784059 Test requirement: is_intel_device(fd)
11318 20:12:54.793073 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11319 20:12:54.794973 Test requirement: is_intel_device(fd)
11320 20:12:54.797456 No KMS driver or no outputs, pipes: 16, outputs: 0
11321 20:12:54.804149 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11322 20:12:54.810596 Using IGT_SRANDOM=1709496775 for randomisation
11323 20:12:54.811153 Opened device: /dev/dri/card0
11324 20:12:54.813670 Starting subtest: addfb25-bad-modifier
11325 20:12:54.827168 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11326 20:12:54.843604 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11327 20:12:54.846893 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11328 20:12:54.850199 Stack trace:
11329 20:12:54.854083 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11330 20:12:54.856582 #1 [<unknown>+0xb8594358]
11331 20:12:54.857177 #2 [<unknown>+0xb8595fbc]
11332 20:12:54.860495 #3 [<unknown>+0xb859156c]
11333 20:12:54.863309 #4 [__libc_init_first+0x80]
11334 20:12:54.866922 #5 [__libc_start_main+0x98]
11335 20:12:54.870497 #6 [<unknown>+0xb85915b0]
11336 20:12:54.874036 Subtest addfb25-bad-modifier failed.
11337 20:12:54.874512 **** DEBUG ****
11338 20:12:54.883548 (kms_addfb_basic:431) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11339 20:12:54.893933 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11340 20:12:54.909282 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11341 20:12:54.912579 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11342 20:12:54.919751 (kms_addfb_basic:431) igt_core-INFO: Stack trace:
11343 20:12:54.926537 (kms_addfb_basic:431) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11344 20:12:54.932829 (kms_addfb_basic:431) igt_core-INFO: #1 [<unknown>+0xb8594358]
11345 20:12:54.935631 (kms_addfb_basic:431) igt_core-INFO: #2 [<unknown>+0xb8595fbc]
11346 20:12:54.942715 (kms_addfb_basic:431) igt_core-INFO: #3 [<unknown>+0xb859156c]
11347 20:12:54.949608 (kms_addfb_basic:431) igt_core-INFO: #4 [__libc_init_first+0x80]
11348 20:12:54.955906 (kms_addfb_basic:431) igt_core-INFO: #5 [__libc_start_main+0x98]
11349 20:12:54.958634 (kms_addfb_basic:431) igt_core-INFO: #6 [<unknown>+0xb85915b0]
11350 20:12:54.963747 **** END ****
11351 20:12:54.965856 [1mSubtest addfb25-bad-modifier: FAIL (0.012s)[0m
11352 20:12:54.975403 Test requirement not met in fu<14>[ 22.895076] [IGT] kms_addfb_basic: exiting, ret=98
11353 20:12:54.982298 <8>[ 22.900459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11354 20:12:54.983174 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11356 20:12:54.992451 nction igt_require_intel, file ../lib/drmtest.c:<14>[ 22.911134] [IGT] kms_addfb_basic: executing
11357 20:12:54.993071 880:
11358 20:12:54.995894 Test requirement: is_intel_device(fd)
11359 20:12:55.002678 Test requirement not met in functio<14>[ 22.923371] [IGT] kms_addfb_basic: exiting, ret=77
11360 20:12:55.009090 n igt_require_intel, file ../lib/drmtest.c:880:
11361 20:12:55.012153 Test requirement: is_intel_device(fd)
11362 20:12:55.021340 No KMS driver or no outputs, pipes: 16, <8>[ 22.935428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11363 20:12:55.022168 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11365 20:12:55.024766 outputs: 0
11366 20:12:55.033864 IGT-Version: 1.28-g0<14>[ 22.949762] [IGT] kms_addfb_basic: executing
11367 20:12:55.034702 830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11368 20:12:55.041444 Using IGT_SRANDOM=1709496775<14>[ 22.962081] [IGT] kms_addfb_basic: exiting, ret=77
11369 20:12:55.050987 <8>[ 22.967213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11370 20:12:55.051546 for randomisation
11371 20:12:55.052194 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11373 20:12:55.054370 Opened device: /dev/dri/card0
11374 20:12:55.061255 Test requirement not met in f<14>[ 22.979619] [IGT] kms_addfb_basic: executing
11375 20:12:55.068042 unction igt_require_intel, file ../lib/drmtest.c:880:
11376 20:12:55.071150 Test requirement: is_intel_device(fd)
11377 20:12:55.075041 [<14>[ 22.992097] [IGT] kms_addfb_basic: exiting, ret=77
11378 20:12:55.085020 <8>[ 22.997802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11379 20:12:55.085765 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11381 20:12:55.091205 1mSubtest addfb2<14>[ 23.011064] [IGT] kms_addfb_basic: executing
11382 20:12:55.094420 5-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11383 20:12:55.107858 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<14>[ 23.023437] [IGT] kms_addfb_basic: exiting, ret=77
11384 20:12:55.113965 <8>[ 23.029169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11385 20:12:55.114537
11386 20:12:55.115187 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11388 20:12:55.121031 Test requirement: is_intel_dev<14>[ 23.041860] [IGT] kms_addfb_basic: executing
11389 20:12:55.124939 ice(fd)
11390 20:12:55.128064 No KMS driver or no outputs, pipes: 16, outputs: 0
11391 20:12:55.133690 IGT-Version: 1.28-g0830aa7 (aarch64<14>[ 23.054256] [IGT] kms_addfb_basic: exiting, ret=77
11392 20:12:55.144501 <8>[ 23.059533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11393 20:12:55.145391 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11395 20:12:55.146709 ) (Linux: 6.1.80-cip16-rt9 aarch64)
11396 20:12:55.154207 Using IGT_SRANDOM=170949677<14>[ 23.072646] [IGT] kms_addfb_basic: executing
11397 20:12:55.156991 5 for randomisation
11398 20:12:55.157548 Opened device: /dev/dri/card0
11399 20:12:55.166987 Test requirement not met in function igt_req<14>[ 23.085049] [IGT] kms_addfb_basic: exiting, ret=77
11400 20:12:55.173296 <8>[ 23.090341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11401 20:12:55.174245 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11403 20:12:55.184365 uire_intel, file ../lib/drmtest.<14>[ 23.102693] [IGT] kms_addfb_basic: executing
11404 20:12:55.184971 c:880:
11405 20:12:55.187210 Test requirement: is_intel_device(fd)
11406 20:12:55.193655 [1mSubtest addfb25-x-tiled-legac<14>[ 23.115130] [IGT] kms_addfb_basic: exiting, ret=77
11407 20:12:55.207379 <8>[ 23.120417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11408 20:12:55.207971 y: SKIP (0.000s)[0m
11409 20:12:55.208857 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11411 20:12:55.213368 Test requirement not met in function igt_require_intel, fi<14>[ 23.132790] [IGT] kms_addfb_basic: executing
11412 20:12:55.216378 le ../lib/drmtest.c:880:
11413 20:12:55.220220 Test requirement: is_intel_device(fd)
11414 20:12:55.226574 No KMS driver or no outputs, pi<14>[ 23.145066] [IGT] kms_addfb_basic: exiting, ret=77
11415 20:12:55.233176 <8>[ 23.150599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11416 20:12:55.234073 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11418 20:12:55.236129 pes: 16, outputs: 0
11419 20:12:55.243169 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11420 20:12:55.246255 Using IGT_SRANDOM=1709496775 for randomisation
11421 20:12:55.249318 Opened device: /dev/dri/card0
11422 20:12:55.252935 Test<14>[ 23.174568] [IGT] kms_addfb_basic: executing
11423 20:12:55.259348 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11424 20:12:55.265693 Test requirement: is_intel_device(fd)
11425 20:12:55.268985 [1mSubte<14>[ 23.188188] [IGT] kms_addfb_basic: exiting, ret=77
11426 20:12:55.275317 <8>[ 23.195214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11427 20:12:55.276056 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11429 20:12:55.282115 st addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11430 20:12:55.289299 Test requirement not met in function ig<14>[ 23.208022] [IGT] kms_addfb_basic: executing
11431 20:12:55.292088 t_require_intel, file ../lib/drmtest.c:880:
11432 20:12:55.299009 Test requirement: is_intel_device(fd)
11433 20:12:55.302657 No KMS drive<14>[ 23.220271] [IGT] kms_addfb_basic: exiting, ret=77
11434 20:12:55.309720 <8>[ 23.226009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11435 20:12:55.310560 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11437 20:12:55.319614 r or no outputs, pipes: 16, outp<14>[ 23.239255] [IGT] kms_addfb_basic: executing
11438 20:12:55.320165 uts: 0
11439 20:12:55.324752 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11440 20:12:55.328290 Using IGT_SRANDOM=1709496775 for randomisation
11441 20:12:55.331927 Opened device: /dev/dri/card0
11442 20:12:55.338439 Test requirement <14>[ 23.256411] [IGT] kms_addfb_basic: exiting, ret=77
11443 20:12:55.346047 <8>[ 23.262290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11444 20:12:55.346886 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11446 20:12:55.352346 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11447 20:12:55.358003 Test requirement: is_intel_de<14>[ 23.275723] [IGT] kms_addfb_basic: executing
11448 20:12:55.358560 vice(fd)
11449 20:12:55.364548 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11450 20:12:55.367922 Test requirement: is_intel_device(fd)
11451 20:12:55.374339 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11452 20:12:55.378083 No KMS driver or no outputs, pipes: 16, outputs: 0
11453 20:12:55.384226 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11454 20:12:55.387631 Using IGT_SRANDOM=1709496775 for randomisation
11455 20:12:55.391043 Opened device: /dev/dri/card0
11456 20:12:55.397632 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11457 20:12:55.401973 Test requirement: is_intel_device(fd)
11458 20:12:55.413418 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11459 20:12:55.414618 Test requirement: is_intel_device(fd)
11460 20:12:55.417312 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11461 20:12:55.424955 No KMS driver or no outputs, pipes: 16, outputs: 0
11462 20:12:55.427622 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11463 20:12:55.434297 Using IGT_SRANDOM=1709496775 for randomisation
11464 20:12:55.437007 Opened device: /dev/dri/card0
11465 20:12:55.445556 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11466 20:12:55.447286 Test requirement: is_intel_device(fd)
11467 20:12:55.453600 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11468 20:12:55.456955 Test requirement: is_intel_device(fd)
11469 20:12:55.460592 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11470 20:12:55.467478 No KMS driver or no outputs, pipes: 16, outputs: 0
11471 20:12:55.473542 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11472 20:12:55.476582 Using IGT_SRANDOM=1709496775 for randomisation
11473 20:12:55.480045 Opened device: /dev/dri/card0
11474 20:12:55.486552 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11475 20:12:55.490052 Test requirement: is_intel_device(fd)
11476 20:12:55.496278 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11477 20:12:55.499802 Test requirement: is_intel_device(fd)
11478 20:12:55.506713 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11479 20:12:55.510144 No KMS driver or no outputs, pipes: 16, outputs: 0
11480 20:12:55.517595 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11481 20:12:55.520646 Using IGT_SRANDOM=1709496775 for randomisation
11482 20:12:55.522954 Opened device: /dev/dri/card0
11483 20:12:55.529897 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11484 20:12:55.532913 Test requirement: is_intel_device(fd)
11485 20:12:55.539199 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11486 20:12:55.542862 Test requirement: is_intel_device(fd)
11487 20:12:55.549645 No KMS driver or no outputs, pipes: 16, outputs: 0
11488 20:12:55.553247 [1mSubtest size-max: SKIP (0.000s)[0m
11489 20:12:55.559474 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11490 20:12:55.563201 Using IGT_SRANDOM=1709496775 for randomisation
11491 20:12:55.565685 Opened device: /dev/dri/card0
11492 20:12:55.574216 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11493 20:12:55.576795 Test requirement: is_intel_device(fd)
11494 20:12:55.582862 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11495 20:12:55.585728 Test requirement: is_intel_device(fd)
11496 20:12:55.592468 No KMS driver or no outputs, pipes: 16, outputs: 0
11497 20:12:55.597955 [1mSubtest too-wide: SKIP (0.000s)[0m
11498 20:12:55.602268 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11499 20:12:55.605744 Using IGT_SRANDOM=1709496775 for randomisation
11500 20:12:55.608816 Opened device: /dev/dri/card0
11501 20:12:55.615487 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11502 20:12:55.619198 Test requirement: is_intel_device(fd)
11503 20:12:55.625360 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11504 20:12:55.628402 Test requirement: is_intel_device(fd)
11505 20:12:55.635147 No KMS driver or no outputs, pipes: 16, outputs: 0
11506 20:12:55.638493 [1mSubtest too-high: SKIP (0.000s)[0m
11507 20:12:55.644614 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11508 20:12:55.648019 Using IGT_SRANDOM=1709496775 for randomisation
11509 20:12:55.651472 Opened device: /dev/dri/card0
11510 20:12:55.657774 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11511 20:12:55.661727 Test requirement: is_intel_device(fd)
11512 20:12:55.668071 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11513 20:12:55.671554 Test requirement: is_intel_device(fd)
11514 20:12:55.678512 No KMS driver or no outputs, pipes: 16, outputs: 0
11515 20:12:55.681168 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11516 20:12:55.688496 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11517 20:12:55.690914 Using IGT_SRANDOM=1709496775 for randomisation
11518 20:12:55.694653 Opened device: /dev/dri/card0
11519 20:12:55.701192 Test requirement not met in function igt_<14>[ 23.621536] [IGT] kms_addfb_basic: exiting, ret=77
11520 20:12:55.707908 <8>[ 23.627046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11521 20:12:55.708850 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11523 20:12:55.711287 require_intel, file ../lib/drmtest.c:880:
11524 20:12:55.714541 Test requirement: is_intel_device(fd)
11525 20:12:55.724005 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11526 20:12:55.731755 Test requirement: is_intel<14>[ 23.651133] [IGT] kms_addfb_basic: executing
11527 20:12:55.732314 _device(fd)
11528 20:12:55.737724 No KMS driver or no outputs, pipes: 16, outputs: 0
11529 20:12:55.740980 [1mSubtest small-bo: SKIP (0.000s)[0m
11530 20:12:55.750380 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)<14>[ 23.670230] [IGT] kms_addfb_basic: exiting, ret=77
11531 20:12:55.756844 <8>[ 23.677287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11532 20:12:55.757694 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11534 20:12:55.760869
11535 20:12:55.763949 Using IGT_SRANDOM=1709496776 for randomisation
11536 20:12:55.767369 Opened device: /dev/dri/card0
11537 20:12:55.771445 <14>[ 23.690131] [IGT] kms_addfb_basic: executing
11538 20:12:55.771907
11539 20:12:55.783549 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 23.702524] [IGT] kms_addfb_basic: exiting, ret=77
11540 20:12:55.790133 <8>[ 23.707916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11541 20:12:55.790680 80:
11542 20:12:55.791329 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11544 20:12:55.794040 Test requirement: is_intel_device(fd)
11545 20:12:55.802890 Test requirement not met in function<14>[ 23.720364] [IGT] kms_addfb_basic: executing
11546 20:12:55.806914 igt_require_intel, file ../lib/drmtest.c:880:
11547 20:12:55.813412 Test requirement: is_intel_devic<14>[ 23.732770] [IGT] kms_addfb_basic: exiting, ret=77
11548 20:12:55.822894 <8>[ 23.738637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11549 20:12:55.823457 e(fd)
11550 20:12:55.824141 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11552 20:12:55.826294 No KMS driver or no outputs, pipes: 16, outputs: 0
11553 20:12:55.833678 [1mSubtest bo-too-sm<14>[ 23.752578] [IGT] kms_addfb_basic: executing
11554 20:12:55.835944 all-due-to-tiling: SKIP (0.000s)[0m
11555 20:12:55.846130 IGT-Version: 1.28-g0830aa7 (aarch64) (Linu<14>[ 23.765112] [IGT] kms_addfb_basic: exiting, ret=77
11556 20:12:55.853115 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11558 20:12:55.856559 <8>[ 23.770407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11559 20:12:55.857177 x: 6.1.80-cip16-rt9 aarch64)
11560 20:12:55.863070 Us<14>[ 23.782831] [IGT] kms_addfb_basic: executing
11561 20:12:55.867280 ing IGT_SRANDOM=1709496776 for randomisation
11562 20:12:55.869917 Opened device: /dev/dri/card0
11563 20:12:55.872583 Tes<14>[ 23.794958] [IGT] kms_addfb_basic: exiting, ret=77
11564 20:12:55.882465 <8>[ 23.800509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11565 20:12:55.883308 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11567 20:12:55.885335 <8>[ 23.801838] <LAVA_SIGNAL_TESTSET STOP>
11568 20:12:55.886060 Received signal: <TESTSET> STOP
11569 20:12:55.886447 Closing test_set kms_addfb_basic
11570 20:12:55.892102 t requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11571 20:12:55.898765 Test requiremen<8>[ 23.817188] <LAVA_SIGNAL_TESTSET START kms_atomic>
11572 20:12:55.899599 Received signal: <TESTSET> START kms_atomic
11573 20:12:55.899992 Starting test_set kms_atomic
11574 20:12:55.902912 t: is_intel_device(fd)
11575 20:12:55.908505 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11576 20:12:55.911945 Test requirement: is_intel_device(fd)
11577 20:12:55.915474 No KMS driver or no outputs, pipes: 16, outputs: 0
11578 20:12:55.921999 [1mSubte<14>[ 23.840710] [IGT] kms_atomic: executing
11579 20:12:55.925320 <14>[ 23.841345] [IGT] kms_atomic: exiting, ret=77
11580 20:12:55.932181 <8>[ 23.847097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11581 20:12:55.933060 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11583 20:12:55.939034 st addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11584 20:12:55.941782 IG<14>[ 23.860315] [IGT] kms_atomic: executing
11585 20:12:55.945006 <14>[ 23.860753] [IGT] kms_atomic: exiting, ret=77
11586 20:12:55.954886 <8>[ 23.868053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11587 20:12:55.955727 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11589 20:12:55.961542 T-Version: 1.28-g0830aa7 (aarch6<14>[ 23.881139] [IGT] kms_atomic: executing
11590 20:12:55.965092 <14>[ 23.881578] [IGT] kms_atomic: exiting, ret=77
11591 20:12:55.974765 <8>[ 23.887966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11592 20:12:55.975585 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11594 20:12:55.981530 4) (Linux: 6.1.80-cip16-rt9 aarc<14>[ 23.901707] [IGT] kms_atomic: executing
11595 20:12:55.982003 h64)
11596 20:12:55.987884 Using IGT_<14>[ 23.902110] [IGT] kms_atomic: exiting, ret=77
11597 20:12:55.995502 <8>[ 23.906118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11598 20:12:55.996339 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11600 20:12:55.997521 SRANDOM=1709496776 for randomisation
11601 20:12:56.000769 Opened device: /dev/dri/card0
11602 20:12:56.007698 Test requirement not met in function igt_re<14>[ 23.930549] [IGT] kms_atomic: executing
11603 20:12:56.014427 <14>[ 23.931192] [IGT] kms_atomic: exiting, ret=77
11604 20:12:56.020873 <8>[ 23.936045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11605 20:12:56.021709 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11607 20:12:56.024627 quire_intel, file ../lib/drmtest.c:880:
11608 20:12:56.027205 Test re<14>[ 23.947764] [IGT] kms_atomic: executing
11609 20:12:56.033670 quirement: is_in<14>[ 23.948170] [IGT] kms_atomic: exiting, ret=77
11610 20:12:56.043730 <8>[ 23.954321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11611 20:12:56.044196 tel_device(fd)
11612 20:12:56.044840 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11614 20:12:56.050631 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11615 20:12:56.053942 Test requirement: is_intel_device(fd)
11616 20:12:56.060370 No KMS driver or no outputs, pipes: 16, outputs: 0
11617 20:12:56.064021 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11618 20:12:56.070826 IGT-Versi<14>[ 23.988110] [IGT] kms_atomic: executing
11619 20:12:56.074468 <14>[ 23.988722] [IGT] kms_atomic: exiting, ret=77
11620 20:12:56.080131 <8>[ 23.993938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11621 20:12:56.080883 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11623 20:12:56.090158 on: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16<14>[ 24.008541] [IGT] kms_atomic: executing
11624 20:12:56.093492 <14>[ 24.008951] [IGT] kms_atomic: exiting, ret=77
11625 20:12:56.103949 <8>[ 24.015042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11626 20:12:56.104514 -rt9 aarch64)
11627 20:12:56.105217 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11629 20:12:56.110229 Using IGT_SRANDOM<14>[ 24.029811] [IGT] kms_atomic: executing
11630 20:12:56.116875 =1709496776 for <14>[ 24.030225] [IGT] kms_atomic: exiting, ret=77
11631 20:12:56.123202 <8>[ 24.035042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11632 20:12:56.123763 randomisation
11633 20:12:56.124415 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11635 20:12:56.126052 Opened device: /dev/dri/card0
11636 20:12:56.136422 Test requirement not met in function igt_require_intel, file ../li<14>[ 24.059117] [IGT] kms_atomic: executing
11637 20:12:56.140036 b/drmtest.c:880:
11638 20:12:56.146121 Test requirement: is_intel_dev<14>[ 24.064625] [IGT] kms_atomic: exiting, ret=77
11639 20:12:56.152480 <8>[ 24.070707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11640 20:12:56.153433 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11642 20:12:56.156009 ice(fd)
11643 20:12:56.162535 Test requirement not me<14>[ 24.082043] [IGT] kms_atomic: executing
11644 20:12:56.165765 t in function ig<14>[ 24.082410] [IGT] kms_atomic: exiting, ret=77
11645 20:12:56.176022 <8>[ 24.087325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11646 20:12:56.176856 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11648 20:12:56.179610 t_require_intel, file ../lib/drmtest.c:880:
11649 20:12:56.182175 Test requirement: is_intel_device(fd)
11650 20:12:56.185865 No KMS driver or no outputs, pipes: 16, outputs: 0
11651 20:12:56.192669 [1mSubtest addfb25-y-ti<14>[ 24.111813] [IGT] kms_atomic: executing
11652 20:12:56.199589 led-small-legacy<14>[ 24.112382] [IGT] kms_atomic: exiting, ret=77
11653 20:12:56.209101 : SKIP (0.000s)<8>[ 24.116697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
11654 20:12:56.209945 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
11656 20:12:56.211883 <8>[ 24.117798] <LAVA_SIGNAL_TESTSET STOP>
11657 20:12:56.212342 [0m
11658 20:12:56.212997 Received signal: <TESTSET> STOP
11659 20:12:56.213367 Closing test_set kms_atomic
11660 20:12:56.219581 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11661 20:12:56.229098 Using IGT_SRANDOM=1709496776 for ra<8>[ 24.144509] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11662 20:12:56.229659 ndomisation
11663 20:12:56.230307 Received signal: <TESTSET> START kms_flip_event_leak
11664 20:12:56.230685 Starting test_set kms_flip_event_leak
11665 20:12:56.231859 Opened device: /dev/dri/card0
11666 20:12:56.238100 Test requirement not<14>[ 24.155768] [IGT] kms_flip_event_leak: executing
11667 20:12:56.244760 met in function<14>[ 24.156175] [IGT] kms_flip_event_leak: exiting, ret=77
11668 20:12:56.253630 <8>[ 24.161571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11669 20:12:56.254549 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11671 20:12:56.255871 <8>[ 24.162791] <LAVA_SIGNAL_TESTSET STOP>
11672 20:12:56.256528 Received signal: <TESTSET> STOP
11673 20:12:56.256951 Closing test_set kms_flip_event_leak
11674 20:12:56.257969 igt_require_intel, file ../lib/drmtest.c:880:
11675 20:12:56.265027 Test requirement: is_intel_device(fd)
11676 20:12:56.271563 Test requirement not met <8>[ 24.189465] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11677 20:12:56.272407 Received signal: <TESTSET> START kms_prop_blob
11678 20:12:56.272843 Starting test_set kms_prop_blob
11679 20:12:56.274579 in function igt_require_intel, file ../lib/drmtest.c:880:
11680 20:12:56.281819 Test requirement: is_<14>[ 24.200365] [IGT] kms_prop_blob: executing
11681 20:12:56.288104 <14>[ 24.200637] [IGT] kms_prop_blob: starting subtest basic
11682 20:12:56.294822 intel_device(fd)<14>[ 24.200677] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
11683 20:12:56.301177 <14>[ 24.200736] [IGT] kms_prop_blob: exiting, ret=0
11684 20:12:56.308596 <8>[ 24.205941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11685 20:12:56.309480 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11687 20:12:56.311036 <14>[ 24.222562] [IGT] kms_prop_blob: executing
11688 20:12:56.311501
11689 20:12:56.317652 No KMS driver <14>[ 24.238371] [IGT] kms_prop_blob: starting subtest blob-prop-core
11690 20:12:56.327714 <14>[ 24.238418] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
11691 20:12:56.330891 <14>[ 24.238478] [IGT] kms_prop_blob: exiting, ret=0
11692 20:12:56.337293 <8>[ 24.243335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11693 20:12:56.338141 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11695 20:12:56.344122 <14>[ 24.258019] [IGT] kms_prop_blob: executing
11696 20:12:56.350668 or no outputs, pipes: 16, output<14>[ 24.269767] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11697 20:12:56.360450 <14>[ 24.269865] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
11698 20:12:56.364928 <14>[ 24.269940] [IGT] kms_prop_blob: exiting, ret=0
11699 20:12:56.370351 <8>[ 24.274793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11700 20:12:56.371193 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11702 20:12:56.376641 <14>[ 24.286616] [IGT] kms_prop_blob: executing
11703 20:12:56.377356 s: 0
11704 20:12:56.380366 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11705 20:12:56.386929 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11706 20:12:56.390569 Using IGT_SRANDOM=1709496776 for randomisation
11707 20:12:56.393615 Opened device: /dev/dri/card0
11708 20:12:56.401420 No KMS driver or no outputs, pipes: 16, outputs: 0
11709 20:12:56.403083 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11710 20:12:56.410201 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11711 20:12:56.413444 Using IGT_SRANDOM=1709496776 for randomisation
11712 20:12:56.417969 Opened device: /dev/dri/card0
11713 20:12:56.420036 No KMS driver or no outputs, pipes: 16, outputs: 0
11714 20:12:56.427190 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11715 20:12:56.433432 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11716 20:12:56.436928 Using IGT_SRANDOM=1709496776 for randomisation
11717 20:12:56.439589 Opened device: /dev/dri/card0
11718 20:12:56.442895 No KMS driver or no outputs, pipes: 16, outputs: 0
11719 20:12:56.449491 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11720 20:12:56.456372 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11721 20:12:56.459567 Using IGT_SRANDOM=1709496776 for randomisation
11722 20:12:56.462819 Opened device: /dev/dri/card0
11723 20:12:56.465920 No KMS driver or no outputs, pipes: 16, outputs: 0
11724 20:12:56.473315 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11725 20:12:56.477041 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11726 20:12:56.482576 Using IGT_SRANDOM=1709496776 for randomisation
11727 20:12:56.486806 Opened device: /dev/dri/card0
11728 20:12:56.489383 No KMS driver or no outputs, pipes: 16, outputs: 0
11729 20:12:56.492529 [1mSubtest test-only: SKIP (0.000s)[0m
11730 20:12:56.499700 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11731 20:12:56.502348 Using IGT_SRANDOM=1709496776 for randomisation
11732 20:12:56.505679 Opened device: /dev/dri/card0
11733 20:12:56.508920 No KMS driver or no outputs, pipes: 16, outputs: 0
11734 20:12:56.516310 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11735 20:12:56.522563 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11736 20:12:56.526115 Using IGT_SRANDOM=1709496776 for randomisation
11737 20:12:56.528866 Opened device: /dev/dri/card0
11738 20:12:56.532149 No KMS driver or no outputs, pipes: 16, outputs: 0
11739 20:12:56.535631 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11740 20:12:56.541766 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11741 20:12:56.548620 Using IGT_SRANDOM=1709496776 for randomisation
11742 20:12:56.549209 Opened device: /dev/dri/card0
11743 20:12:56.554601 No KMS driver or no outputs, pipes: 16, outputs: 0
11744 20:12:56.558311 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11745 20:12:56.564810 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11746 20:12:56.571464 Using IGT_SRANDOM=1709496776 for randomisation
11747 20:12:56.572027 Opened device: /dev/dri/card0
11748 20:12:56.578152 No KMS driver or no outputs, pipes: 16, outputs: 0
11749 20:12:56.581394 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11750 20:12:56.589157 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11751 20:12:56.591605 Using IGT_SRANDOM=1709496776 for randomisation
11752 20:12:56.594587 Opened device: /dev/dri/card0
11753 20:12:56.597685 No KMS driver or no outputs, pipes: 16, outputs: 0
11754 20:12:56.604210 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11755 20:12:56.611372 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11756 20:12:56.614556 Using IGT_SRANDOM=1709496776 for randomisation
11757 20:12:56.617348 Opened device: /dev/dri/card0
11758 20:12:56.621373 No KMS driver or no outputs, pipes: 16, outputs: 0
11759 20:12:56.627905 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11760 20:12:56.634609 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11761 20:12:56.637646 Using IGT_SRANDOM=1709496776 for randomisation
11762 20:12:56.640433 Opened device: /dev/dri/card0
11763 20:12:56.644854 No KMS driver or no outputs, pipes: 16, outputs: 0
11764 20:12:56.647611 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
11765 20:12:56.655305 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11766 20:12:56.661095 Using IGT_SRANDOM=1709496776 for randomisation
11767 20:12:56.661646 Opened device: /dev/dri/card0
11768 20:12:56.666907 No KMS driver or no outputs, pipes: 16, outputs: 0
11769 20:12:56.670821 [1mSubtest basic: SKIP (0.000s)[0m
11770 20:12:56.677609 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11771 20:12:56.680456 Using IGT_SRANDOM=1709496776 for randomisation
11772 20:12:56.683105 Opened device: /dev/dri/card0
11773 20:12:56.683570 Starting subtest: basic
11774 20:12:56.686701 [1mSubtest basic: SUCCESS (0.000s)[0m
11775 20:12:56.693519 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11776 20:12:56.699789 Using IGT_SRANDOM=1709496776 for randomisation
11777 20:12:56.700249 Opened device: /dev/dri/card0
11778 20:12:56.704626 Starting subtest: blob-prop-core
11779 20:12:56.710354 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11780 20:12:56.719767 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16<14>[ 24.635775] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
11781 20:12:56.726906 <14>[ 24.635895] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
11782 20:12:56.732685 <14>[ 24.635943] [IGT] kms_prop_blob: exiting, ret=0
11783 20:12:56.740029 <8>[ 24.641980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
11784 20:12:56.740887 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11786 20:12:56.745962 <14>[ 24.655157] [IGT] kms_prop_blob: executing
11787 20:12:56.746426 -rt9 aarch64)
11788 20:12:56.756434 Using IGT_SRANDOM=1709496776 for <14>[ 24.672120] [IGT] kms_prop_blob: starting subtest blob-multiple
11789 20:12:56.762686 <14>[ 24.672254] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
11790 20:12:56.765953 <14>[ 24.672296] [IGT] kms_prop_blob: exiting, ret=0
11791 20:12:56.772263 <8>[ 24.677564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
11792 20:12:56.773052 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
11794 20:12:56.779325 <14>[ 24.689561] [IGT] kms_prop_blob: executing
11795 20:12:56.779868 randomisation
11796 20:12:56.789109 Opened device: /d<14>[ 24.706097] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
11797 20:12:56.796307 <14>[ 24.706152] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
11798 20:12:56.802501 <14>[ 24.706220] [IGT] kms_prop_blob: exiting, ret=0
11799 20:12:56.808958 <8>[ 24.711584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11800 20:12:56.809782 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11802 20:12:56.813173 <14>[ 24.723280] [IGT] kms_prop_blob: executing
11803 20:12:56.815393 ev/dri/card0
11804 20:12:56.825348 Starting subtest: blob-prop-valida<14>[ 24.740437] [IGT] kms_prop_blob: starting subtest invalid-get-prop
11805 20:12:56.832598 <14>[ 24.740488] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
11806 20:12:56.835124 <14>[ 24.740559] [IGT] kms_prop_blob: exiting, ret=0
11807 20:12:56.835587 te
11808 20:12:56.844850 [1mSubtest <8>[ 24.745672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11809 20:12:56.845670 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11811 20:12:56.848701 <14>[ 24.763229] [IGT] kms_prop_blob: executing
11812 20:12:56.851811 blob-prop-validate: SUCCESS (0.000s)[0m
11813 20:12:56.861767 IGT-Ve<14>[ 24.776443] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
11814 20:12:56.868864 rsion: 1.28-g083<14>[ 24.776533] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
11815 20:12:56.875589 <14>[ 24.776657] [IGT] kms_prop_blob: exiting, ret=0
11816 20:12:56.882848 <8>[ 24.782824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11817 20:12:56.883689 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11819 20:12:56.887857 0aa7 (aarch64) (Linux: 6.1.80-ci<14>[ 24.809218] [IGT] kms_prop_blob: executing
11820 20:12:56.897726 p16-rt9 aarch64)<14>[ 24.809662] [IGT] kms_prop_blob: starting subtest invalid-set-prop
11821 20:12:56.904877 <14>[ 24.809757] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
11822 20:12:56.908848 <14>[ 24.809874] [IGT] kms_prop_blob: exiting, ret=0
11823 20:12:56.917914 <8>[ 24.815543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11824 20:12:56.918763 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11826 20:12:56.921444 <8>[ 24.818705] <LAVA_SIGNAL_TESTSET STOP>
11827 20:12:56.922164 Received signal: <TESTSET> STOP
11828 20:12:56.922550 Closing test_set kms_prop_blob
11829 20:12:56.926172 <8>[ 24.832168] <LAVA_SIGNAL_TESTSET START kms_setmode>
11830 20:12:56.926728
11831 20:12:56.927373 Received signal: <TESTSET> START kms_setmode
11832 20:12:56.927760 Starting test_set kms_setmode
11833 20:12:56.933896 Using IGT_SRANDOM=1709496777 for randomisation<14>[ 24.855140] [IGT] kms_setmode: executing
11834 20:12:56.934459
11835 20:12:56.937501 Opened device: /dev/dri/card0
11836 20:12:56.940867 <14>[ 24.861496] [IGT] kms_setmode: starting subtest basic
11837 20:12:56.944161
11838 20:12:56.950857 Starting subtes<14>[ 24.861544] [IGT] kms_setmode: finished subtest basic, SKIP
11839 20:12:56.954020 <14>[ 24.861610] [IGT] kms_setmode: exiting, ret=77
11840 20:12:56.961240 <8>[ 24.866267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11841 20:12:56.962085 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11843 20:12:56.964034 t: blob-prop-lifetime
11844 20:12:56.966907 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
11845 20:12:56.974530 IGT-Version: 1.28-g<14>[ 24.894348] [IGT] kms_setmode: executing
11846 20:12:56.980096 0830aa7 (aarch64<14>[ 24.894842] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
11847 20:12:56.990796 ) (Linux: 6.1.80<14>[ 24.894923] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
11848 20:12:56.996698 <14>[ 24.895022] [IGT] kms_setmode: exiting, ret=77
11849 20:12:57.004022 <8>[ 24.899817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
11850 20:12:57.004600 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
11852 20:12:57.009801 -cip16-rt9 aarch<14>[ 24.930669] [IGT] kms_setmode: executing
11853 20:12:57.010045 64)
11854 20:12:57.016472 Using IGT_S<14>[ 24.931021] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
11855 20:12:57.026648 RANDOM=170949677<14>[ 24.931068] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
11856 20:12:57.030755 <14>[ 24.931126] [IGT] kms_setmode: exiting, ret=77
11857 20:12:57.039947 <8>[ 24.936418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
11858 20:12:57.040825 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
11860 20:12:57.043196 <14>[ 24.958579] [IGT] kms_setmode: executing
11861 20:12:57.053114 7 for randomisat<14>[ 24.971110] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
11862 20:12:57.059542 <14>[ 24.971148] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
11863 20:12:57.066133 <14>[ 24.971199] [IGT] kms_setmode: exiting, ret=77
11864 20:12:57.073062 <8>[ 24.976434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
11865 20:12:57.073975 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
11867 20:12:57.080019 <14>[ 24.992445] [IGT] kms_setmode: executing
11868 20:12:57.080576 ion
11869 20:12:57.088157 Opened device: /dev/dri/car<14>[ 25.005279] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
11870 20:12:57.095564 <14>[ 25.005325] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
11871 20:12:57.098863 <14>[ 25.005387] [IGT] kms_setmode: exiting, ret=77
11872 20:12:57.105593 <8>[ 25.010293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
11873 20:12:57.106498 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
11875 20:12:57.112195 <14>[ 25.026572] [IGT] kms_setmode: executing
11876 20:12:57.112794 d0
11877 20:12:57.122458 Starting sub<14>[ 25.038710] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
11878 20:12:57.129073 test: blob-multi<14>[ 25.038758] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
11879 20:12:57.135345 <14>[ 25.038824] [IGT] kms_setmode: exiting, ret=77
11880 20:12:57.145400 <8>[ 25.044058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
11881 20:12:57.146245 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
11883 20:12:57.148762 <8>[ 25.045151] <LAVA_SIGNAL_TESTSET STOP>
11884 20:12:57.149598 Received signal: <TESTSET> STOP
11885 20:12:57.149987 Closing test_set kms_setmode
11886 20:12:57.151681 <8>[ 25.071791] <LAVA_SIGNAL_TESTSET START kms_vblank>
11887 20:12:57.152408 Received signal: <TESTSET> START kms_vblank
11888 20:12:57.152849 Starting test_set kms_vblank
11889 20:12:57.155409 ple
11890 20:12:57.161905 [1mSubtest blob-multiple: SUCCESS (0.000s)<14>[ 25.082297] [IGT] kms_vblank: executing
11891 20:12:57.162461 [0m
11892 20:12:57.168015 IGT-Versio<14>[ 25.082656] [IGT] kms_vblank: exiting, ret=77
11893 20:12:57.175224 <8>[ 25.086766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
11894 20:12:57.175958 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
11896 20:12:57.177890 n: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11897 20:12:57.184792 Using IGT_SRANDOM=1709496777 for randomisation
11898 20:12:57.188405 Opened device: /dev/dri/card0
11899 20:12:57.192438 Starting subtest: invalid-get-prop-any
11900 20:12:57.194725 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11901 20:12:57.201351 IGT-Version: 1.28-g<14>[ 25.122155] [IGT] kms_vblank: executing
11902 20:12:57.207752 0830aa7 (aarch64<14>[ 25.122756] [IGT] kms_vblank: exiting, ret=77
11903 20:12:57.214620 <8>[ 25.129189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
11904 20:12:57.215459 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
11906 20:12:57.218179 ) (Linux: 6.1.80-cip16-rt9 aarch64)
11907 20:12:57.223136 Using IGT_SRANDOM=1709496777 for randomisation
11908 20:12:57.224179 Opened device: /dev/dri/card0
11909 20:12:57.227854 Starting subtest: invalid-get-prop
11910 20:12:57.234171 [1mSubtest invalid-get-<14>[ 25.152636] [IGT] kms_vblank: executing
11911 20:12:57.238467 <14>[ 25.153255] [IGT] kms_vblank: exiting, ret=77
11912 20:12:57.244247 <8>[ 25.159228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
11913 20:12:57.245123 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
11915 20:12:57.247580 prop: SUCCESS (0.000s)[0m
11916 20:12:57.254370 IGT-Version: 1.28-g0<14>[ 25.171928] [IGT] kms_vblank: executing
11917 20:12:57.257533 <14>[ 25.172314] [IGT] kms_vblank: exiting, ret=77
11918 20:12:57.264568 <8>[ 25.178281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
11919 20:12:57.265477 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
11921 20:12:57.273780 830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch6<14>[ 25.191796] [IGT] kms_vblank: executing
11922 20:12:57.277695 <14>[ 25.192185] [IGT] kms_vblank: exiting, ret=77
11923 20:12:57.283730 <8>[ 25.198054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
11924 20:12:57.284291 4)
11925 20:12:57.284926 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
11927 20:12:57.290428 Using IGT_SRANDOM=1709496777 for randomisation
11928 20:12:57.293665 Opened device: /dev/dri/card0
11929 20:12:57.296905 Starting subtest: invalid-set-prop-any
11930 20:12:57.300554 [1mSubtest invalid-s<14>[ 25.221681] [IGT] kms_vblank: executing
11931 20:12:57.306829 <14>[ 25.222304] [IGT] kms_vblank: exiting, ret=77
11932 20:12:57.313799 <8>[ 25.227380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
11933 20:12:57.314642 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
11935 20:12:57.316860 et-prop-any: SUCCESS (0.000s)[0m
11936 20:12:57.320671 IGT-Version: <14>[ 25.240475] [IGT] kms_vblank: executing
11937 20:12:57.327692 <14>[ 25.240874] [IGT] kms_vblank: exiting, ret=77
11938 20:12:57.333668 <8>[ 25.250049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
11939 20:12:57.334501 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
11941 20:12:57.339781 1.28-g0830aa7 (aarch64) (Linux: <14>[ 25.261123] [IGT] kms_vblank: executing
11942 20:12:57.346383 <14>[ 25.261514] [IGT] kms_vblank: exiting, ret=77
11943 20:12:57.354090 <8>[ 25.267365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
11944 20:12:57.354659 6.1.80-cip16-rt9 aarch64)
11945 20:12:57.355319 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
11947 20:12:57.363246 Using IGT_SRANDOM=1709496777 for rand<14>[ 25.279537] [IGT] kms_vblank: executing
11948 20:12:57.366541 <14>[ 25.279930] [IGT] kms_vblank: exiting, ret=77
11949 20:12:57.372782 <8>[ 25.286139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
11950 20:12:57.373624 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
11952 20:12:57.376329 omisation
11953 20:12:57.376925 Opened device: /dev/dri/card0
11954 20:12:57.379922 Starting subtest: invalid-set-prop
11955 20:12:57.386310 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11956 20:12:57.392829 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6<14>[ 25.313900] [IGT] kms_vblank: executing
11957 20:12:57.396267 .1.80-cip16-rt9 aarch64)
11958 20:12:57.399215 Using IGT_SRANDOM=1709496777 for randomisation
11959 20:12:57.402985 Opened device: /dev/dri/card0
11960 20:12:57.405886 Starting subtest: basic
11961 20:12:57.406344 No dynamic tests executed.
11962 20:12:57.409000 [1mSubtest basic: SKIP (0.000s)[0m
11963 20:12:57.415706 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11964 20:12:57.422745 Using IGT_SRANDOM=1709496777 for randomisation
11965 20:12:57.423300 Opened device: /dev/dri/card0
11966 20:12:57.425766 Starting subtest: basic-clone-single-crtc
11967 20:12:57.429149 No dynamic tests executed.
11968 20:12:57.435675 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
11969 20:12:57.442190 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11970 20:12:57.445587 Using IGT_SRANDOM=1709496777 for randomisation
11971 20:12:57.448531 Opened device: /dev/dri/card0
11972 20:12:57.452257 Starting subtest: invalid-clone-single-crtc
11973 20:12:57.455121 No dynamic tests executed.
11974 20:12:57.460861 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
11975 20:12:57.464911 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11976 20:12:57.468362 Using IGT_SRANDOM=1709496777 for randomisation
11977 20:12:57.472392 Opened device: /dev/dri/card0
11978 20:12:57.475396 Starting subtest: invalid-clone-exclusive-crtc
11979 20:12:57.479234 No dynamic tests executed.
11980 20:12:57.485305 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
11981 20:12:57.491589 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11982 20:12:57.495098 Using IGT_SRANDOM=1709496777 for randomisation
11983 20:12:57.498282 Opened device: /dev/dri/card0
11984 20:12:57.502421 Starting subtest: clone-exclusive-crtc
11985 20:12:57.502972 No dynamic tests executed.
11986 20:12:57.507947 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
11987 20:12:57.515178 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11988 20:12:57.517925 Using IGT_SRANDOM=1709496777 for randomisation
11989 20:12:57.521896 Opened device: /dev/dri/card0
11990 20:12:57.524928 Starting subtest: invalid-clone-single-crtc-stealing
11991 20:12:57.528009 No dynamic tests executed.
11992 20:12:57.534883 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
11993 20:12:57.541428 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11994 20:12:57.544869 Using IGT_SRANDOM=1709496777 for randomisation
11995 20:12:57.547768 Opened device: /dev/dri/card0
11996 20:12:57.551395 No KMS driver or no outputs, pipes: 16, outputs: 0
11997 20:12:57.554196 [1mSubtest invalid: SKIP (0.000s)[0m
11998 20:12:57.560694 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11999 20:12:57.564674 Using IGT_SRANDOM=1709496777 for randomisation
12000 20:12:57.567893 Opened device: /dev/dri/card0
12001 20:12:57.574717 No KMS driver or no outputs, pipes: 16, outputs: 0
12002 20:12:57.577968 [1mSubtest crtc-id: SKIP (0.000s)[0m
12003 20:12:57.580969 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12004 20:12:57.587205 Using IGT_SRANDOM=1709496777 for randomisation
12005 20:12:57.590438 Opened device: /dev/dri/card0
12006 20:12:57.594964 No KMS driver or no outputs, pipes: 16, outputs: 0
12007 20:12:57.597563 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12008 20:12:57.603757 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12009 20:12:57.608624 Using IGT_SRANDOM=1709496777 for randomisation
12010 20:12:57.610419 Opened device: /dev/dri/card0
12011 20:12:57.613778 No KMS driver or no outputs, pipes: 16, outputs: 0
12012 20:12:57.620749 [1mSubtest query-idle: SKIP (0.000s)[0m
12013 20:12:57.623630 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12014 20:12:57.630493 Using IGT_SRANDOM=1709496777 for randomisation
12015 20:12:57.633476 Opened device: /dev/dri/card0
12016 20:12:57.636697 No KMS driver or no outputs, pipes: 16, outputs: 0
12017 20:12:57.640075 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12018 20:12:57.646523 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12019 20:12:57.650990 Using IGT_SRANDOM=1709496777 for randomisation
12020 20:12:57.653416 Opened device: /dev/dri/card0
12021 20:12:57.660060 No KMS driver or no outputs, pipes: 16, outputs: 0
12022 20:12:57.663175 [1mSubtest query-forked: SKIP (0.000s)[0m
12023 20:12:57.670156 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12024 20:12:57.672881 Using IGT_SRANDOM=1709496777 for randomisation
12025 20:12:57.676309 Opened device: /dev/dri/card0
12026 20:12:57.679714 No KMS driver or no outputs, pipes: 16, outputs: 0
12027 20:12:57.682814 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12028 20:12:57.689014 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12029 20:12:57.696555 Using IGT_SRANDOM=1709496777 for randomisation
12030 20:12:57.697152 Opened device: /dev/dri/card0
12031 20:12:57.704918 No KMS driver or no outputs, pipes: 16, outputs: 0
12032 20:12:57.706091 [1mSubtest query-busy: SKIP (0.000s)[0m
12033 20:12:57.713043 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12034 20:12:57.715862 Using IGT_SRANDOM=1709496777 for randomisation
12035 20:12:57.719624 Opened device: /dev/dri/card0
12036 20:12:57.722378 No KMS driver or no outputs, pipes: 16, outputs: 0
12037 20:12:57.728967 [1mSubtest query-busy-han<14>[ 25.651374] [IGT] kms_vblank: exiting, ret=77
12038 20:12:57.732521 g: SKIP (0.000s)[0m
12039 20:12:57.746905 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-<8>[ 25.662278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12040 20:12:57.747447 rt9 aarch64)
12041 20:12:57.748118 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12043 20:12:57.749294 Using IGT_SRANDOM=1709496777 for randomisation
12044 20:12:57.751554 Opened device: /dev/dri/card0
12045 20:12:57.758273 No KMS driver or no outputs, pipes: 16, outputs: 0
12046 20:12:57.761894 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12047 20:12:57.772381 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1<14>[ 25.691687] [IGT] kms_vblank: executing
12048 20:12:57.775781 <14>[ 25.692300] [IGT] kms_vblank: exiting, ret=77
12049 20:12:57.786007 <8>[ 25.697701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12050 20:12:57.786244 .80-cip16-rt9 aarch64)
12051 20:12:57.786588 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12053 20:12:57.792771 Using IGT_SRANDOM=1709496778 for randomisation
12054 20:12:57.795766 Opened device: /dev/dri/card0
12055 20:12:57.799594 No KMS driver or no outputs, pipes: 16, outputs: 0
12056 20:12:57.806285 [1mSubtest query-for<14>[ 25.727522] [IGT] kms_vblank: executing
12057 20:12:57.808930 ked-busy-hang: SKIP (0.000s)[0m
12058 20:12:57.813175 IGT-Version: 1<14>[ 25.732850] [IGT] kms_vblank: exiting, ret=77
12059 20:12:57.822317 .28-g0830aa7 (aarch64) (Linux: 6<8>[ 25.742684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12060 20:12:57.823147 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12062 20:12:57.825917 .1.80-cip16-rt9 aarch64)
12063 20:12:57.829893 Using IGT_SRANDOM=1709496778 for randomisation
12064 20:12:57.832648 Opened device: /dev/dri/card0
12065 20:12:57.839119 No KMS <14>[ 25.756993] [IGT] kms_vblank: executing
12066 20:12:57.841976 <14>[ 25.757440] [IGT] kms_vblank: exiting, ret=77
12067 20:12:57.848863 <8>[ 25.767093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12068 20:12:57.849607 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12070 20:12:57.852015 driver or no outputs, pipes: 16, outputs: 0
12071 20:12:57.855379 [1mSubtest wait-idle: SKIP (0.000s)[0m
12072 20:12:57.862456 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12073 20:12:57.868778 Using IGT_SRANDOM=1709496778 for randomisation
12074 20:12:57.872871 Opened device: /d<14>[ 25.793884] [IGT] kms_vblank: executing
12075 20:12:57.875342 ev/dri/card0
12076 20:12:57.878212 No<14>[ 25.794560] [IGT] kms_vblank: exiting, ret=77
12077 20:12:57.885219 <8>[ 25.801038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12078 20:12:57.885912 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12080 20:12:57.891888 KMS driver or no outputs, pipes: 16, outputs: 0
12081 20:12:57.894865 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12082 20:12:57.902028 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12083 20:12:57.904816 Using I<14>[ 25.823864] [IGT] kms_vblank: executing
12084 20:12:57.911622 <14>[ 25.824473] [IGT] kms_vblank: exiting, ret=77
12085 20:12:57.919789 <8>[ 25.830547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12086 20:12:57.920591 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12088 20:12:57.921800 GT_SRANDOM=1709496778 for randomisation
12089 20:12:57.924793 Opened device: /dev/dri/card0
12090 20:12:57.929356 No KMS driver or no outputs, pipes: 16, outputs: 0
12091 20:12:57.932018 [1mSubtest wait-forked: SKIP (0.000s)[0m
12092 20:12:57.942326 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip1<14>[ 25.860372] [IGT] kms_vblank: executing
12093 20:12:57.945541 <14>[ 25.860976] [IGT] kms_vblank: exiting, ret=77
12094 20:12:57.951914 <8>[ 25.866975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12095 20:12:57.952810 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12097 20:12:57.955873 6-rt9 aarch64)
12098 20:12:57.958546 Using IGT_SRANDOM=1709496778 for randomisation
12099 20:12:57.961767 Opened device: /dev/dri/card0
12100 20:12:57.964848 No KMS driver or no outputs, pipes: 16, outputs: 0
12101 20:12:57.968613 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12102 20:12:57.977584 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux:<14>[ 25.896776] [IGT] kms_vblank: executing
12103 20:12:57.981017 <14>[ 25.897378] [IGT] kms_vblank: exiting, ret=77
12104 20:12:57.988178 <8>[ 25.903777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12105 20:12:57.989084 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12107 20:12:57.990891 6.1.80-cip16-rt9 aarch64)
12108 20:12:57.994263 Using IGT_SRANDOM=1709496778 for randomisation
12109 20:12:57.997343 Opened device: /dev/dri/card0
12110 20:12:58.004537 No KMS driver or no outputs, pipes: 16, outputs: 0
12111 20:12:58.008531 [1mSubtest wait-busy: SKIP (0.000s)[0m
12112 20:12:58.014340 IGT-Version: 1.28-g0830<14>[ 25.932693] [IGT] kms_vblank: executing
12113 20:12:58.017301 <14>[ 25.933302] [IGT] kms_vblank: exiting, ret=77
12114 20:12:58.024376 <8>[ 25.939723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12115 20:12:58.025245 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12117 20:12:58.031503 aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12118 20:12:58.034071 Using IGT_SRANDOM=1709496778 for randomisation
12119 20:12:58.037696 Opened device: /dev/dri/card0
12120 20:12:58.041066 No KMS driver or no outputs, pipes: 16, outputs: 0
12121 20:12:58.048697 [1mSubtest <14>[ 25.963779] [IGT] kms_vblank: executing
12122 20:12:58.051425 <14>[ 25.964436] [IGT] kms_vblank: exiting, ret=77
12123 20:12:58.057505 <8>[ 25.970327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12124 20:12:58.058399 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12126 20:12:58.060979 wait-busy-hang: SKIP (0.000s)[0m
12127 20:12:58.067005 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12128 20:12:58.073586 Using IGT_SRANDOM=170<14>[ 25.992056] [IGT] kms_vblank: executing
12129 20:12:58.077318 <14>[ 25.992653] [IGT] kms_vblank: exiting, ret=77
12130 20:12:58.086844 <8>[ 25.998627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12131 20:12:58.087449 9496778 for randomisation
12132 20:12:58.088106 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12134 20:12:58.090788 Opened device: /dev/dri/card0
12135 20:12:58.097040 No KMS driver or no outputs, pipes: 16, outputs: 0
12136 20:12:58.100007 [1mSubtest wait-f<14>[ 26.022284] [IGT] kms_vblank: executing
12137 20:12:58.107113 <14>[ 26.022941] [IGT] kms_vblank: exiting, ret=77
12138 20:12:58.113588 <8>[ 26.029016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12139 20:12:58.114407 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12141 20:12:58.116666 orked-busy: SKIP (0.000s)[0m
12142 20:12:58.124388 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12143 20:12:58.130407 Using IGT_SRANDOM=1709496<14>[ 26.050894] [IGT] kms_vblank: executing
12144 20:12:58.130962 778 for randomisation
12145 20:12:58.140131 Opened device: /dev/dri/c<14>[ 26.056972] [IGT] kms_vblank: exiting, ret=77
12146 20:12:58.140693 ard0
12147 20:12:58.149655 No KMS driver or no output<8>[ 26.066459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12148 20:12:58.150218 s, pipes: 16, outputs: 0
12149 20:12:58.150865 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12151 20:12:58.156836 [1mSubtest wait-forke<14>[ 26.079525] [IGT] kms_vblank: executing
12152 20:12:58.159979 d-busy-hang: SKIP (0.000s)[0m
12153 20:12:58.165999 <14>[ 26.085246] [IGT] kms_vblank: exiting, ret=77
12154 20:12:58.175963 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1<8>[ 26.094530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12155 20:12:58.176879 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12157 20:12:58.179681 .80-cip16-rt9 aarch64)
12158 20:12:58.183221 Using IGT_SRANDOM=1709496778 for randomisation
12159 20:12:58.189798 Opened d<14>[ 26.108581] [IGT] kms_vblank: executing
12160 20:12:58.192747 <14>[ 26.109034] [IGT] kms_vblank: exiting, ret=77
12161 20:12:58.202680 <8>[ 26.117749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12162 20:12:58.203233 evice: /dev/dri/card0
12163 20:12:58.203882 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12165 20:12:58.210001 No KMS dr<14>[ 26.131445] [IGT] kms_vblank: executing
12166 20:12:58.212667 iver or no outputs, pipes: 16, outputs: 0
12167 20:12:58.216245 [1mS<14>[ 26.136244] [IGT] kms_vblank: exiting, ret=77
12168 20:12:58.226470 <8>[ 26.142743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12169 20:12:58.227313 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12171 20:12:58.229665 ubtest ts-continuation-idle: SKIP (0.000s)[0m
12172 20:12:58.232626 <14>[ 26.153901] [IGT] kms_vblank: executing
12173 20:12:58.239254 <14>[ 26.154296] [IGT] kms_vblank: exiting, ret=77
12174 20:12:58.245891 <8>[ 26.163368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12175 20:12:58.246731 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12177 20:12:58.252267 IGT-Version: 1.28-g0830aa7 (aarc<14>[ 26.174860] [IGT] kms_vblank: executing
12178 20:12:58.259625 <14>[ 26.175254] [IGT] kms_vblank: exiting, ret=77
12179 20:12:58.266216 <8>[ 26.184355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12180 20:12:58.267076 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12182 20:12:58.272487 <8>[ 26.185732] <LAVA_SIGNAL_TESTSET STOP>
12183 20:12:58.273399 Received signal: <TESTSET> STOP
12184 20:12:58.273792 Closing test_set kms_vblank
12185 20:12:58.278811 h64) (Linux: 6.1.80-cip16-rt9 aa<8>[ 26.198192] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12928083_1.5.2.3.1>
12186 20:12:58.279654 Received signal: <ENDRUN> 0_igt-kms-mediatek 12928083_1.5.2.3.1
12187 20:12:58.280102 Ending use of test pattern.
12188 20:12:58.280453 Ending test lava.0_igt-kms-mediatek (12928083_1.5.2.3.1), duration 5.95
12190 20:12:58.282532 rch64)
12191 20:12:58.286096 Using IGT_SRANDOM=1709496778 for randomisation
12192 20:12:58.288837 Opened device: /dev/dri/card0
12193 20:12:58.292207 No KMS driver or no outputs, pipes: 16, outputs: 0
12194 20:12:58.298150 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12195 20:12:58.305093 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12196 20:12:58.308560 Using IGT_SRANDOM=1709496778 for randomisation
12197 20:12:58.312065 Opened device: /dev/dri/card0
12198 20:12:58.315164 No KMS driver or no outputs, pipes: 16, outputs: 0
12199 20:12:58.322883 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12200 20:12:58.324970 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12201 20:12:58.333114 Using IGT_SRANDOM=1709496778 for randomisation
12202 20:12:58.333675 Opened device: /dev/dri/card0
12203 20:12:58.338035 No KMS driver or no outputs, pipes: 16, outputs: 0
12204 20:12:58.341647 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12205 20:12:58.348604 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12206 20:12:58.355569 Using IGT_SRANDOM=1709496778 for randomisation
12207 20:12:58.356131 Opened device: /dev/dri/card0
12208 20:12:58.361696 No KMS driver or no outputs, pipes: 16, outputs: 0
12209 20:12:58.364662 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12210 20:12:58.371846 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12211 20:12:58.375310 Using IGT_SRANDOM=1709496778 for randomisation
12212 20:12:58.377306 Opened device: /dev/dri/card0
12213 20:12:58.384222 No KMS driver or no outputs, pipes: 16, outputs: 0
12214 20:12:58.388132 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12215 20:12:58.393890 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12216 20:12:58.397308 Using IGT_SRANDOM=1709496778 for randomisation
12217 20:12:58.400619 Opened device: /dev/dri/card0
12218 20:12:58.404460 No KMS driver or no outputs, pipes: 16, outputs: 0
12219 20:12:58.411472 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12220 20:12:58.417698 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
12221 20:12:58.421141 Using IGT_SRANDOM=1709496778 for randomisation
12222 20:12:58.424068 Opened device: /dev/dri/card0
12223 20:12:58.428387 No KMS driver or no outputs, pipes: 16, outputs: 0
12224 20:12:58.434961 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12225 20:12:58.435562 + set +x
12226 20:12:58.436913 <LAVA_TEST_RUNNER EXIT>
12227 20:12:58.437670 ok: lava_test_shell seems to have completed
12228 20:12:58.446537 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12229 20:12:58.447347 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12230 20:12:58.447831 end: 3 lava-test-retry (duration 00:00:07) [common]
12231 20:12:58.448318 start: 4 finalize (timeout 00:07:50) [common]
12232 20:12:58.448856 start: 4.1 power-off (timeout 00:00:30) [common]
12233 20:12:58.449694 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
12234 20:12:58.576989 >> Command sent successfully.
12235 20:12:58.581283 Returned 0 in 0 seconds
12236 20:12:58.682242 end: 4.1 power-off (duration 00:00:00) [common]
12238 20:12:58.683811 start: 4.2 read-feedback (timeout 00:07:50) [common]
12239 20:12:58.685210 Listened to connection for namespace 'common' for up to 1s
12240 20:12:59.685018 Finalising connection for namespace 'common'
12241 20:12:59.685714 Disconnecting from shell: Finalise
12242 20:12:59.686125 / #
12243 20:12:59.787152 end: 4.2 read-feedback (duration 00:00:01) [common]
12244 20:12:59.787885 end: 4 finalize (duration 00:00:01) [common]
12245 20:12:59.788534 Cleaning after the job
12246 20:12:59.789082 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/ramdisk
12247 20:12:59.827407 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/kernel
12248 20:12:59.844170 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/dtb
12249 20:12:59.844453 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928083/tftp-deploy-mbpqjfca/modules
12250 20:12:59.853819 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928083
12251 20:12:59.982524 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928083
12252 20:12:59.982706 Job finished correctly