Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 36
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 14
1 20:10:35.375348 lava-dispatcher, installed at version: 2024.01
2 20:10:35.375609 start: 0 validate
3 20:10:35.375741 Start time: 2024-03-03 20:10:35.375733+00:00 (UTC)
4 20:10:35.375862 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:10:35.375992 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 20:10:35.643284 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:10:35.643498 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:10:35.909470 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:10:35.909625 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:11:05.644480 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:11:05.644653 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:11:06.174163 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:11:06.174330 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:11:06.442079 validate duration: 31.07
16 20:11:06.442339 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:11:06.442434 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:11:06.442518 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:11:06.442648 Not decompressing ramdisk as can be used compressed.
20 20:11:06.442732 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 20:11:06.442795 saving as /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/ramdisk/initrd.cpio.gz
22 20:11:06.442859 total size: 4663047 (4 MB)
23 20:11:09.440485 progress 0 % (0 MB)
24 20:11:09.442095 progress 5 % (0 MB)
25 20:11:09.443389 progress 10 % (0 MB)
26 20:11:09.444696 progress 15 % (0 MB)
27 20:11:09.445929 progress 20 % (0 MB)
28 20:11:09.447160 progress 25 % (1 MB)
29 20:11:09.448467 progress 30 % (1 MB)
30 20:11:09.449700 progress 35 % (1 MB)
31 20:11:09.450936 progress 40 % (1 MB)
32 20:11:09.452400 progress 45 % (2 MB)
33 20:11:09.453639 progress 50 % (2 MB)
34 20:11:09.454875 progress 55 % (2 MB)
35 20:11:09.456106 progress 60 % (2 MB)
36 20:11:09.457331 progress 65 % (2 MB)
37 20:11:09.458550 progress 70 % (3 MB)
38 20:11:09.459781 progress 75 % (3 MB)
39 20:11:09.461004 progress 80 % (3 MB)
40 20:11:09.462238 progress 85 % (3 MB)
41 20:11:09.463638 progress 90 % (4 MB)
42 20:11:09.464863 progress 95 % (4 MB)
43 20:11:09.466099 progress 100 % (4 MB)
44 20:11:09.466240 4 MB downloaded in 3.02 s (1.47 MB/s)
45 20:11:09.466386 end: 1.1.1 http-download (duration 00:00:03) [common]
47 20:11:09.466620 end: 1.1 download-retry (duration 00:00:03) [common]
48 20:11:09.466706 start: 1.2 download-retry (timeout 00:09:57) [common]
49 20:11:09.466789 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 20:11:09.466924 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:11:09.466991 saving as /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/kernel/Image
52 20:11:09.467050 total size: 51601920 (49 MB)
53 20:11:09.467113 No compression specified
54 20:11:09.468309 progress 0 % (0 MB)
55 20:11:09.482039 progress 5 % (2 MB)
56 20:11:09.495842 progress 10 % (4 MB)
57 20:11:09.509567 progress 15 % (7 MB)
58 20:11:09.522966 progress 20 % (9 MB)
59 20:11:09.537699 progress 25 % (12 MB)
60 20:11:09.551851 progress 30 % (14 MB)
61 20:11:09.566675 progress 35 % (17 MB)
62 20:11:09.580612 progress 40 % (19 MB)
63 20:11:09.594250 progress 45 % (22 MB)
64 20:11:09.608048 progress 50 % (24 MB)
65 20:11:09.622123 progress 55 % (27 MB)
66 20:11:09.636385 progress 60 % (29 MB)
67 20:11:09.650318 progress 65 % (32 MB)
68 20:11:09.664392 progress 70 % (34 MB)
69 20:11:09.680797 progress 75 % (36 MB)
70 20:11:09.695231 progress 80 % (39 MB)
71 20:11:09.709439 progress 85 % (41 MB)
72 20:11:09.723721 progress 90 % (44 MB)
73 20:11:09.737765 progress 95 % (46 MB)
74 20:11:09.753827 progress 100 % (49 MB)
75 20:11:09.754141 49 MB downloaded in 0.29 s (171.42 MB/s)
76 20:11:09.754326 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:11:09.754748 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:11:09.754920 start: 1.3 download-retry (timeout 00:09:57) [common]
80 20:11:09.755086 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 20:11:09.755295 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:11:09.755458 saving as /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/dtb/mt8192-asurada-spherion-r0.dtb
83 20:11:09.755571 total size: 47278 (0 MB)
84 20:11:09.755687 No compression specified
85 20:11:09.757551 progress 69 % (0 MB)
86 20:11:09.757963 progress 100 % (0 MB)
87 20:11:09.758211 0 MB downloaded in 0.00 s (17.10 MB/s)
88 20:11:09.758445 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:11:09.758853 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:11:09.758996 start: 1.4 download-retry (timeout 00:09:57) [common]
92 20:11:09.759140 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 20:11:09.759350 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 20:11:09.759495 saving as /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/nfsrootfs/full.rootfs.tar
95 20:11:09.759608 total size: 200856304 (191 MB)
96 20:11:09.759719 Using unxz to decompress xz
97 20:11:09.765663 progress 0 % (0 MB)
98 20:11:10.338465 progress 5 % (9 MB)
99 20:11:10.931408 progress 10 % (19 MB)
100 20:11:11.658106 progress 15 % (28 MB)
101 20:11:12.097713 progress 20 % (38 MB)
102 20:11:12.470594 progress 25 % (47 MB)
103 20:11:13.225777 progress 30 % (57 MB)
104 20:11:13.880996 progress 35 % (67 MB)
105 20:11:14.600166 progress 40 % (76 MB)
106 20:11:15.218513 progress 45 % (86 MB)
107 20:11:15.994067 progress 50 % (95 MB)
108 20:11:16.697630 progress 55 % (105 MB)
109 20:11:17.437778 progress 60 % (114 MB)
110 20:11:17.586953 progress 65 % (124 MB)
111 20:11:17.760451 progress 70 % (134 MB)
112 20:11:17.877781 progress 75 % (143 MB)
113 20:11:17.961568 progress 80 % (153 MB)
114 20:11:18.048296 progress 85 % (162 MB)
115 20:11:18.163402 progress 90 % (172 MB)
116 20:11:18.544212 progress 95 % (182 MB)
117 20:11:19.250742 progress 100 % (191 MB)
118 20:11:19.256681 191 MB downloaded in 9.50 s (20.17 MB/s)
119 20:11:19.257117 end: 1.4.1 http-download (duration 00:00:09) [common]
121 20:11:19.257618 end: 1.4 download-retry (duration 00:00:09) [common]
122 20:11:19.257782 start: 1.5 download-retry (timeout 00:09:47) [common]
123 20:11:19.257934 start: 1.5.1 http-download (timeout 00:09:47) [common]
124 20:11:19.258163 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:11:19.258280 saving as /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/modules/modules.tar
126 20:11:19.258390 total size: 8632284 (8 MB)
127 20:11:19.258509 Using unxz to decompress xz
128 20:11:19.542630 progress 0 % (0 MB)
129 20:11:19.564576 progress 5 % (0 MB)
130 20:11:19.590831 progress 10 % (0 MB)
131 20:11:19.617654 progress 15 % (1 MB)
132 20:11:19.642147 progress 20 % (1 MB)
133 20:11:19.667767 progress 25 % (2 MB)
134 20:11:19.694701 progress 30 % (2 MB)
135 20:11:19.729044 progress 35 % (2 MB)
136 20:11:19.765257 progress 40 % (3 MB)
137 20:11:19.799081 progress 45 % (3 MB)
138 20:11:19.827757 progress 50 % (4 MB)
139 20:11:19.863497 progress 55 % (4 MB)
140 20:11:19.896496 progress 60 % (4 MB)
141 20:11:19.931792 progress 65 % (5 MB)
142 20:11:19.968320 progress 70 % (5 MB)
143 20:11:19.997187 progress 75 % (6 MB)
144 20:11:20.033063 progress 80 % (6 MB)
145 20:11:20.068637 progress 85 % (7 MB)
146 20:11:20.104045 progress 90 % (7 MB)
147 20:11:20.145978 progress 95 % (7 MB)
148 20:11:20.183411 progress 100 % (8 MB)
149 20:11:20.189184 8 MB downloaded in 0.93 s (8.84 MB/s)
150 20:11:20.189552 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:11:20.189974 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:11:20.190103 start: 1.6 prepare-tftp-overlay (timeout 00:09:46) [common]
154 20:11:20.190240 start: 1.6.1 extract-nfsrootfs (timeout 00:09:46) [common]
155 20:11:24.849121 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit
156 20:11:24.849363 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
157 20:11:24.849466 start: 1.6.2 lava-overlay (timeout 00:09:42) [common]
158 20:11:24.849647 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc
159 20:11:24.849784 makedir: /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin
160 20:11:24.849890 makedir: /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/tests
161 20:11:24.849991 makedir: /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/results
162 20:11:24.850097 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-add-keys
163 20:11:24.850249 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-add-sources
164 20:11:24.850392 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-background-process-start
165 20:11:24.850521 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-background-process-stop
166 20:11:24.850655 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-common-functions
167 20:11:24.850824 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-echo-ipv4
168 20:11:24.850958 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-install-packages
169 20:11:24.851084 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-installed-packages
170 20:11:24.851209 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-os-build
171 20:11:24.851333 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-probe-channel
172 20:11:24.851770 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-probe-ip
173 20:11:24.851898 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-target-ip
174 20:11:24.852043 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-target-mac
175 20:11:24.852184 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-target-storage
176 20:11:24.852311 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-case
177 20:11:24.852440 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-event
178 20:11:24.852565 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-feedback
179 20:11:24.852689 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-raise
180 20:11:24.852813 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-reference
181 20:11:24.852956 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-runner
182 20:11:24.853096 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-set
183 20:11:24.853220 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-test-shell
184 20:11:24.853377 Updating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-add-keys (debian)
185 20:11:24.853530 Updating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-add-sources (debian)
186 20:11:24.853674 Updating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-install-packages (debian)
187 20:11:24.853814 Updating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-installed-packages (debian)
188 20:11:24.853951 Updating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/bin/lava-os-build (debian)
189 20:11:24.854073 Creating /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/environment
190 20:11:24.854170 LAVA metadata
191 20:11:24.854241 - LAVA_JOB_ID=12928085
192 20:11:24.854303 - LAVA_DISPATCHER_IP=192.168.201.1
193 20:11:24.854418 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:42) [common]
194 20:11:24.854484 skipped lava-vland-overlay
195 20:11:24.854558 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 20:11:24.854652 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:42) [common]
197 20:11:24.854713 skipped lava-multinode-overlay
198 20:11:24.854798 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 20:11:24.854917 start: 1.6.2.3 test-definition (timeout 00:09:42) [common]
200 20:11:24.854993 Loading test definitions
201 20:11:24.855081 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:42) [common]
202 20:11:24.855151 Using /lava-12928085 at stage 0
203 20:11:24.855480 uuid=12928085_1.6.2.3.1 testdef=None
204 20:11:24.855569 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 20:11:24.855657 start: 1.6.2.3.2 test-overlay (timeout 00:09:42) [common]
206 20:11:24.856123 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 20:11:24.856342 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:42) [common]
209 20:11:24.856975 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 20:11:24.857203 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:42) [common]
212 20:11:24.857745 runner path: /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/0/tests/0_timesync-off test_uuid 12928085_1.6.2.3.1
213 20:11:24.857907 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 20:11:24.858128 start: 1.6.2.3.5 git-repo-action (timeout 00:09:42) [common]
216 20:11:24.858200 Using /lava-12928085 at stage 0
217 20:11:24.858298 Fetching tests from https://github.com/kernelci/test-definitions.git
218 20:11:24.858382 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/0/tests/1_kselftest-tpm2'
219 20:11:30.020888 Running '/usr/bin/git checkout kernelci.org
220 20:11:30.035508 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 20:11:30.036349 uuid=12928085_1.6.2.3.5 testdef=None
222 20:11:30.036545 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 20:11:30.036852 start: 1.6.2.3.6 test-overlay (timeout 00:09:36) [common]
225 20:11:30.037799 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 20:11:30.038036 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:36) [common]
228 20:11:30.039643 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 20:11:30.039885 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:36) [common]
231 20:11:30.041449 runner path: /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/0/tests/1_kselftest-tpm2 test_uuid 12928085_1.6.2.3.5
232 20:11:30.041603 BOARD='mt8192-asurada-spherion-r0'
233 20:11:30.041717 BRANCH='cip-gitlab'
234 20:11:30.041826 SKIPFILE='/dev/null'
235 20:11:30.041936 SKIP_INSTALL='True'
236 20:11:30.042048 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 20:11:30.042162 TST_CASENAME=''
238 20:11:30.042272 TST_CMDFILES='tpm2'
239 20:11:30.042505 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 20:11:30.042906 Creating lava-test-runner.conf files
242 20:11:30.043026 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928085/lava-overlay-svb076sc/lava-12928085/0 for stage 0
243 20:11:30.043188 - 0_timesync-off
244 20:11:30.043311 - 1_kselftest-tpm2
245 20:11:30.043477 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 20:11:30.043633 start: 1.6.2.4 compress-overlay (timeout 00:09:36) [common]
247 20:11:37.957812 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 20:11:37.957978 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:28) [common]
249 20:11:37.958093 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 20:11:37.958212 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 20:11:37.958320 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:28) [common]
252 20:11:38.094418 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 20:11:38.094908 start: 1.6.4 extract-modules (timeout 00:09:28) [common]
254 20:11:38.095062 extracting modules file /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit
255 20:11:38.330822 extracting modules file /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928085/extract-overlay-ramdisk-xpm4k_rs/ramdisk
256 20:11:38.565760 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 20:11:38.565947 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
258 20:11:38.566071 [common] Applying overlay to NFS
259 20:11:38.566168 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928085/compress-overlay-7htqg2pe/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit
260 20:11:39.508412 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 20:11:39.508572 start: 1.6.6 configure-preseed-file (timeout 00:09:27) [common]
262 20:11:39.508674 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 20:11:39.508766 start: 1.6.7 compress-ramdisk (timeout 00:09:27) [common]
264 20:11:39.508849 Building ramdisk /var/lib/lava/dispatcher/tmp/12928085/extract-overlay-ramdisk-xpm4k_rs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928085/extract-overlay-ramdisk-xpm4k_rs/ramdisk
265 20:11:39.829251 >> 119447 blocks
266 20:11:41.882976 rename /var/lib/lava/dispatcher/tmp/12928085/extract-overlay-ramdisk-xpm4k_rs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/ramdisk/ramdisk.cpio.gz
267 20:11:41.883476 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 20:11:41.883601 start: 1.6.8 prepare-kernel (timeout 00:09:25) [common]
269 20:11:41.883714 start: 1.6.8.1 prepare-fit (timeout 00:09:25) [common]
270 20:11:41.883830 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/kernel/Image'
271 20:11:56.252020 Returned 0 in 14 seconds
272 20:11:56.352658 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/kernel/image.itb
273 20:11:56.735780 output: FIT description: Kernel Image image with one or more FDT blobs
274 20:11:56.736303 output: Created: Sun Mar 3 20:11:56 2024
275 20:11:56.736443 output: Image 0 (kernel-1)
276 20:11:56.736569 output: Description:
277 20:11:56.736692 output: Created: Sun Mar 3 20:11:56 2024
278 20:11:56.736812 output: Type: Kernel Image
279 20:11:56.736935 output: Compression: lzma compressed
280 20:11:56.737058 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
281 20:11:56.737184 output: Architecture: AArch64
282 20:11:56.737301 output: OS: Linux
283 20:11:56.737422 output: Load Address: 0x00000000
284 20:11:56.737543 output: Entry Point: 0x00000000
285 20:11:56.737665 output: Hash algo: crc32
286 20:11:56.737780 output: Hash value: 91cb1a17
287 20:11:56.737900 output: Image 1 (fdt-1)
288 20:11:56.738008 output: Description: mt8192-asurada-spherion-r0
289 20:11:56.738124 output: Created: Sun Mar 3 20:11:56 2024
290 20:11:56.738236 output: Type: Flat Device Tree
291 20:11:56.738352 output: Compression: uncompressed
292 20:11:56.738460 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 20:11:56.738573 output: Architecture: AArch64
294 20:11:56.738687 output: Hash algo: crc32
295 20:11:56.738794 output: Hash value: cc4352de
296 20:11:56.738911 output: Image 2 (ramdisk-1)
297 20:11:56.739020 output: Description: unavailable
298 20:11:56.739134 output: Created: Sun Mar 3 20:11:56 2024
299 20:11:56.739247 output: Type: RAMDisk Image
300 20:11:56.739367 output: Compression: Unknown Compression
301 20:11:56.739480 output: Data Size: 17799638 Bytes = 17382.46 KiB = 16.98 MiB
302 20:11:56.739593 output: Architecture: AArch64
303 20:11:56.739703 output: OS: Linux
304 20:11:56.739811 output: Load Address: unavailable
305 20:11:56.739928 output: Entry Point: unavailable
306 20:11:56.740038 output: Hash algo: crc32
307 20:11:56.740150 output: Hash value: 859a31e1
308 20:11:56.740260 output: Default Configuration: 'conf-1'
309 20:11:56.740373 output: Configuration 0 (conf-1)
310 20:11:56.740481 output: Description: mt8192-asurada-spherion-r0
311 20:11:56.740589 output: Kernel: kernel-1
312 20:11:56.740702 output: Init Ramdisk: ramdisk-1
313 20:11:56.740815 output: FDT: fdt-1
314 20:11:56.740929 output: Loadables: kernel-1
315 20:11:56.741034 output:
316 20:11:56.741349 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 20:11:56.741526 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 20:11:56.741712 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 20:11:56.741887 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:10) [common]
320 20:11:56.742029 No LXC device requested
321 20:11:56.742176 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 20:11:56.742339 start: 1.8 deploy-device-env (timeout 00:09:10) [common]
323 20:11:56.742482 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 20:11:56.742615 Checking files for TFTP limit of 4294967296 bytes.
325 20:11:56.743462 end: 1 tftp-deploy (duration 00:00:50) [common]
326 20:11:56.743642 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 20:11:56.743797 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 20:11:56.744018 substitutions:
329 20:11:56.744142 - {DTB}: 12928085/tftp-deploy-w2rggnd5/dtb/mt8192-asurada-spherion-r0.dtb
330 20:11:56.744266 - {INITRD}: 12928085/tftp-deploy-w2rggnd5/ramdisk/ramdisk.cpio.gz
331 20:11:56.744386 - {KERNEL}: 12928085/tftp-deploy-w2rggnd5/kernel/Image
332 20:11:56.744497 - {LAVA_MAC}: None
333 20:11:56.744615 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit
334 20:11:56.744728 - {NFS_SERVER_IP}: 192.168.201.1
335 20:11:56.744836 - {PRESEED_CONFIG}: None
336 20:11:56.744953 - {PRESEED_LOCAL}: None
337 20:11:56.745065 - {RAMDISK}: 12928085/tftp-deploy-w2rggnd5/ramdisk/ramdisk.cpio.gz
338 20:11:56.745180 - {ROOT_PART}: None
339 20:11:56.745291 - {ROOT}: None
340 20:11:56.745406 - {SERVER_IP}: 192.168.201.1
341 20:11:56.745517 - {TEE}: None
342 20:11:56.745631 Parsed boot commands:
343 20:11:56.745736 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 20:11:56.746031 Parsed boot commands: tftpboot 192.168.201.1 12928085/tftp-deploy-w2rggnd5/kernel/image.itb 12928085/tftp-deploy-w2rggnd5/kernel/cmdline
345 20:11:56.746187 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 20:11:56.746343 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 20:11:56.746509 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 20:11:56.746671 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 20:11:56.746808 Not connected, no need to disconnect.
350 20:11:56.746952 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 20:11:56.747102 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 20:11:56.747232 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 20:11:56.752362 Setting prompt string to ['lava-test: # ']
354 20:11:56.752898 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 20:11:56.753082 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 20:11:56.753259 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 20:11:56.753424 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 20:11:56.753803 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 20:12:01.879586 >> Command sent successfully.
360 20:12:01.883055 Returned 0 in 5 seconds
361 20:12:01.983469 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 20:12:01.983936 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 20:12:01.984058 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 20:12:01.984156 Setting prompt string to 'Starting depthcharge on Spherion...'
366 20:12:01.984224 Changing prompt to 'Starting depthcharge on Spherion...'
367 20:12:01.984293 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 20:12:01.984674 [Enter `^Ec?' for help]
369 20:12:02.157892
370 20:12:02.158035
371 20:12:02.158109 F0: 102B 0000
372 20:12:02.158176
373 20:12:02.158243 F3: 1001 0000 [0200]
374 20:12:02.158307
375 20:12:02.160826 F3: 1001 0000
376 20:12:02.160904
377 20:12:02.160968 F7: 102D 0000
378 20:12:02.161032
379 20:12:02.164363 F1: 0000 0000
380 20:12:02.164435
381 20:12:02.164500 V0: 0000 0000 [0001]
382 20:12:02.164561
383 20:12:02.167403 00: 0007 8000
384 20:12:02.167480
385 20:12:02.167540 01: 0000 0000
386 20:12:02.167600
387 20:12:02.171188 BP: 0C00 0209 [0000]
388 20:12:02.171288
389 20:12:02.171388 G0: 1182 0000
390 20:12:02.171479
391 20:12:02.171566 EC: 0000 0021 [4000]
392 20:12:02.174565
393 20:12:02.174632 S7: 0000 0000 [0000]
394 20:12:02.174692
395 20:12:02.177959 CC: 0000 0000 [0001]
396 20:12:02.178034
397 20:12:02.178094 T0: 0000 0040 [010F]
398 20:12:02.178156
399 20:12:02.178221 Jump to BL
400 20:12:02.178278
401 20:12:02.204437
402 20:12:02.204562
403 20:12:02.204659
404 20:12:02.211300 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 20:12:02.214509 ARM64: Exception handlers installed.
406 20:12:02.218466 ARM64: Testing exception
407 20:12:02.221852 ARM64: Done test exception
408 20:12:02.228266 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 20:12:02.238011 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 20:12:02.245117 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 20:12:02.255356 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 20:12:02.261982 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 20:12:02.272117 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 20:12:02.282683 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 20:12:02.289115 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 20:12:02.307344 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 20:12:02.310670 WDT: Last reset was cold boot
418 20:12:02.313794 SPI1(PAD0) initialized at 2873684 Hz
419 20:12:02.317124 SPI5(PAD0) initialized at 992727 Hz
420 20:12:02.320592 VBOOT: Loading verstage.
421 20:12:02.327385 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:12:02.330478 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:12:02.333660 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:12:02.337029 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:12:02.344682 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:12:02.350985 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:12:02.362144 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 20:12:02.362245
429 20:12:02.362321
430 20:12:02.372078 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:12:02.375297 ARM64: Exception handlers installed.
432 20:12:02.378717 ARM64: Testing exception
433 20:12:02.378804 ARM64: Done test exception
434 20:12:02.385775 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:12:02.389675 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:12:02.403236 Probing TPM: . done!
437 20:12:02.403357 TPM ready after 0 ms
438 20:12:02.411465 Connected to device vid:did:rid of 1ae0:0028:00
439 20:12:02.417830 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 20:12:02.474832 Initialized TPM device CR50 revision 0
441 20:12:02.486086 tlcl_send_startup: Startup return code is 0
442 20:12:02.486220 TPM: setup succeeded
443 20:12:02.497466 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:12:02.506237 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:12:02.518417 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:12:02.528256 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:12:02.531664 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:12:02.537422 in-header: 03 07 00 00 08 00 00 00
449 20:12:02.540730 in-data: aa e4 47 04 13 02 00 00
450 20:12:02.544440 Chrome EC: UHEPI supported
451 20:12:02.551620 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:12:02.555332 in-header: 03 95 00 00 08 00 00 00
453 20:12:02.559214 in-data: 18 20 20 08 00 00 00 00
454 20:12:02.559331 Phase 1
455 20:12:02.562717 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:12:02.569803 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:12:02.573655 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:12:02.577185 Recovery requested (1009000e)
459 20:12:02.586360 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:12:02.591517 tlcl_extend: response is 0
461 20:12:02.600565 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:12:02.606382 tlcl_extend: response is 0
463 20:12:02.613323 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:12:02.633193 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 20:12:02.640022 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 20:12:02.640148
467 20:12:02.640258
468 20:12:02.649443 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:12:02.653197 ARM64: Exception handlers installed.
470 20:12:02.656484 ARM64: Testing exception
471 20:12:02.656570 ARM64: Done test exception
472 20:12:02.678602 pmic_efuse_setting: Set efuses in 11 msecs
473 20:12:02.681615 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:12:02.688753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:12:02.691535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:12:02.698538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:12:02.701935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:12:02.705778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:12:02.712608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:12:02.716038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:12:02.720310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:12:02.727549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:12:02.730554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:12:02.734328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:12:02.738644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:12:02.745236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:12:02.752559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:12:02.756212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:12:02.763691 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:12:02.767454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:12:02.774862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:12:02.778763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:12:02.786229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:12:02.789428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:12:02.796503 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:12:02.800429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:12:02.807669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:12:02.811705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:12:02.818945 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:12:02.823015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:12:02.826356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:12:02.833227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:12:02.837327 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:12:02.844250 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:12:02.847998 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:12:02.851462 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:12:02.858754 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:12:02.862391 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:12:02.866254 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:12:02.873786 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:12:02.876798 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:12:02.880546 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:12:02.888018 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:12:02.891720 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:12:02.895088 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:12:02.899321 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:12:02.902801 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:12:02.910529 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:12:02.914300 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:12:02.917350 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:12:02.920963 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:12:02.924561 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:12:02.928335 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:12:02.931428 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:12:02.942212 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:12:02.949853 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:12:02.952880 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:12:02.963643 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:12:02.971880 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:12:02.975231 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:12:02.978819 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:12:02.986002 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:12:02.993679 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 20:12:02.996915 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:12:03.000736 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 20:12:03.004588 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:12:03.015959 [RTC]rtc_get_frequency_meter,154: input=15, output=853
538 20:12:03.025660 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 20:12:03.034853 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 20:12:03.044163 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 20:12:03.053617 [RTC]rtc_get_frequency_meter,154: input=12, output=806
542 20:12:03.063213 [RTC]rtc_get_frequency_meter,154: input=11, output=790
543 20:12:03.073216 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 20:12:03.076658 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 20:12:03.080410 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 20:12:03.084659 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 20:12:03.091643 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 20:12:03.095764 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 20:12:03.099387 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 20:12:03.103157 ADC[4]: Raw value=903325 ID=7
551 20:12:03.106745 ADC[3]: Raw value=213916 ID=1
552 20:12:03.106887 RAM Code: 0x71
553 20:12:03.110302 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 20:12:03.117545 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 20:12:03.124612 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 20:12:03.132543 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 20:12:03.132632 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 20:12:03.136312 in-header: 03 07 00 00 08 00 00 00
559 20:12:03.139960 in-data: aa e4 47 04 13 02 00 00
560 20:12:03.143930 Chrome EC: UHEPI supported
561 20:12:03.151114 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 20:12:03.154258 in-header: 03 95 00 00 08 00 00 00
563 20:12:03.158076 in-data: 18 20 20 08 00 00 00 00
564 20:12:03.161488 MRC: failed to locate region type 0.
565 20:12:03.165016 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 20:12:03.169032 DRAM-K: Running full calibration
567 20:12:03.176339 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 20:12:03.176428 header.status = 0x0
569 20:12:03.179639 header.version = 0x6 (expected: 0x6)
570 20:12:03.183210 header.size = 0xd00 (expected: 0xd00)
571 20:12:03.187135 header.flags = 0x0
572 20:12:03.190749 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 20:12:03.210197 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
574 20:12:03.217741 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 20:12:03.221682 dram_init: ddr_geometry: 2
576 20:12:03.221795 [EMI] MDL number = 2
577 20:12:03.224937 [EMI] Get MDL freq = 0
578 20:12:03.225014 dram_init: ddr_type: 0
579 20:12:03.229630 is_discrete_lpddr4: 1
580 20:12:03.229719 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 20:12:03.229787
582 20:12:03.233126
583 20:12:03.233205 [Bian_co] ETT version 0.0.0.1
584 20:12:03.236592 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 20:12:03.240445
586 20:12:03.244230 dramc_set_vcore_voltage set vcore to 650000
587 20:12:03.244320 Read voltage for 800, 4
588 20:12:03.244387 Vio18 = 0
589 20:12:03.247346 Vcore = 650000
590 20:12:03.247435 Vdram = 0
591 20:12:03.247500 Vddq = 0
592 20:12:03.250770 Vmddr = 0
593 20:12:03.250853 dram_init: config_dvfs: 1
594 20:12:03.257499 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 20:12:03.260611 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 20:12:03.267872 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 20:12:03.271052 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 20:12:03.274816 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 20:12:03.278719 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 20:12:03.278830 MEM_TYPE=3, freq_sel=18
601 20:12:03.282108 sv_algorithm_assistance_LP4_1600
602 20:12:03.285799 ============ PULL DRAM RESETB DOWN ============
603 20:12:03.292904 ========== PULL DRAM RESETB DOWN end =========
604 20:12:03.295537 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 20:12:03.299071 ===================================
606 20:12:03.302668 LPDDR4 DRAM CONFIGURATION
607 20:12:03.305610 ===================================
608 20:12:03.305721 EX_ROW_EN[0] = 0x0
609 20:12:03.309154 EX_ROW_EN[1] = 0x0
610 20:12:03.309248 LP4Y_EN = 0x0
611 20:12:03.311992 WORK_FSP = 0x0
612 20:12:03.312077 WL = 0x2
613 20:12:03.315432 RL = 0x2
614 20:12:03.319033 BL = 0x2
615 20:12:03.319119 RPST = 0x0
616 20:12:03.322247 RD_PRE = 0x0
617 20:12:03.322360 WR_PRE = 0x1
618 20:12:03.325465 WR_PST = 0x0
619 20:12:03.325566 DBI_WR = 0x0
620 20:12:03.328577 DBI_RD = 0x0
621 20:12:03.328659 OTF = 0x1
622 20:12:03.332372 ===================================
623 20:12:03.335231 ===================================
624 20:12:03.338748 ANA top config
625 20:12:03.341934 ===================================
626 20:12:03.342045 DLL_ASYNC_EN = 0
627 20:12:03.345194 ALL_SLAVE_EN = 1
628 20:12:03.348600 NEW_RANK_MODE = 1
629 20:12:03.351929 DLL_IDLE_MODE = 1
630 20:12:03.352013 LP45_APHY_COMB_EN = 1
631 20:12:03.355383 TX_ODT_DIS = 1
632 20:12:03.358659 NEW_8X_MODE = 1
633 20:12:03.361917 ===================================
634 20:12:03.365523 ===================================
635 20:12:03.368326 data_rate = 1600
636 20:12:03.371865 CKR = 1
637 20:12:03.374908 DQ_P2S_RATIO = 8
638 20:12:03.378166 ===================================
639 20:12:03.378247 CA_P2S_RATIO = 8
640 20:12:03.381903 DQ_CA_OPEN = 0
641 20:12:03.385294 DQ_SEMI_OPEN = 0
642 20:12:03.388961 CA_SEMI_OPEN = 0
643 20:12:03.391562 CA_FULL_RATE = 0
644 20:12:03.391646 DQ_CKDIV4_EN = 1
645 20:12:03.394933 CA_CKDIV4_EN = 1
646 20:12:03.398931 CA_PREDIV_EN = 0
647 20:12:03.401729 PH8_DLY = 0
648 20:12:03.405138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 20:12:03.408283 DQ_AAMCK_DIV = 4
650 20:12:03.408396 CA_AAMCK_DIV = 4
651 20:12:03.411947 CA_ADMCK_DIV = 4
652 20:12:03.415099 DQ_TRACK_CA_EN = 0
653 20:12:03.418044 CA_PICK = 800
654 20:12:03.422018 CA_MCKIO = 800
655 20:12:03.425497 MCKIO_SEMI = 0
656 20:12:03.428987 PLL_FREQ = 3068
657 20:12:03.429071 DQ_UI_PI_RATIO = 32
658 20:12:03.432703 CA_UI_PI_RATIO = 0
659 20:12:03.436354 ===================================
660 20:12:03.440095 ===================================
661 20:12:03.444034 memory_type:LPDDR4
662 20:12:03.444120 GP_NUM : 10
663 20:12:03.447316 SRAM_EN : 1
664 20:12:03.447428 MD32_EN : 0
665 20:12:03.450786 ===================================
666 20:12:03.454394 [ANA_INIT] >>>>>>>>>>>>>>
667 20:12:03.458003 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 20:12:03.461446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 20:12:03.461531 ===================================
670 20:12:03.465048 data_rate = 1600,PCW = 0X7600
671 20:12:03.468323 ===================================
672 20:12:03.471535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 20:12:03.478215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 20:12:03.484765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 20:12:03.487989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 20:12:03.491390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 20:12:03.495039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 20:12:03.498343 [ANA_INIT] flow start
679 20:12:03.498433 [ANA_INIT] PLL >>>>>>>>
680 20:12:03.501414 [ANA_INIT] PLL <<<<<<<<
681 20:12:03.505306 [ANA_INIT] MIDPI >>>>>>>>
682 20:12:03.505387 [ANA_INIT] MIDPI <<<<<<<<
683 20:12:03.508022 [ANA_INIT] DLL >>>>>>>>
684 20:12:03.511267 [ANA_INIT] flow end
685 20:12:03.514603 ============ LP4 DIFF to SE enter ============
686 20:12:03.518441 ============ LP4 DIFF to SE exit ============
687 20:12:03.521210 [ANA_INIT] <<<<<<<<<<<<<
688 20:12:03.525105 [Flow] Enable top DCM control >>>>>
689 20:12:03.527944 [Flow] Enable top DCM control <<<<<
690 20:12:03.531440 Enable DLL master slave shuffle
691 20:12:03.534716 ==============================================================
692 20:12:03.538055 Gating Mode config
693 20:12:03.544655 ==============================================================
694 20:12:03.544803 Config description:
695 20:12:03.554740 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 20:12:03.561157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 20:12:03.567870 SELPH_MODE 0: By rank 1: By Phase
698 20:12:03.571264 ==============================================================
699 20:12:03.574705 GAT_TRACK_EN = 1
700 20:12:03.577824 RX_GATING_MODE = 2
701 20:12:03.581208 RX_GATING_TRACK_MODE = 2
702 20:12:03.584664 SELPH_MODE = 1
703 20:12:03.587889 PICG_EARLY_EN = 1
704 20:12:03.591609 VALID_LAT_VALUE = 1
705 20:12:03.594749 ==============================================================
706 20:12:03.597989 Enter into Gating configuration >>>>
707 20:12:03.601149 Exit from Gating configuration <<<<
708 20:12:03.604664 Enter into DVFS_PRE_config >>>>>
709 20:12:03.617603 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 20:12:03.617757 Exit from DVFS_PRE_config <<<<<
711 20:12:03.620917 Enter into PICG configuration >>>>
712 20:12:03.624291 Exit from PICG configuration <<<<
713 20:12:03.627892 [RX_INPUT] configuration >>>>>
714 20:12:03.631221 [RX_INPUT] configuration <<<<<
715 20:12:03.637706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 20:12:03.641028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 20:12:03.647563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 20:12:03.654494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 20:12:03.661041 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 20:12:03.667544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 20:12:03.670939 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 20:12:03.674551 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 20:12:03.678139 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 20:12:03.684230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 20:12:03.688053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 20:12:03.691444 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 20:12:03.694620 ===================================
728 20:12:03.697751 LPDDR4 DRAM CONFIGURATION
729 20:12:03.700992 ===================================
730 20:12:03.701099 EX_ROW_EN[0] = 0x0
731 20:12:03.704502 EX_ROW_EN[1] = 0x0
732 20:12:03.704590 LP4Y_EN = 0x0
733 20:12:03.707673 WORK_FSP = 0x0
734 20:12:03.711388 WL = 0x2
735 20:12:03.711515 RL = 0x2
736 20:12:03.714370 BL = 0x2
737 20:12:03.714462 RPST = 0x0
738 20:12:03.718346 RD_PRE = 0x0
739 20:12:03.718436 WR_PRE = 0x1
740 20:12:03.721532 WR_PST = 0x0
741 20:12:03.721626 DBI_WR = 0x0
742 20:12:03.724696 DBI_RD = 0x0
743 20:12:03.724784 OTF = 0x1
744 20:12:03.727771 ===================================
745 20:12:03.731061 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 20:12:03.738196 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 20:12:03.741462 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 20:12:03.744807 ===================================
749 20:12:03.747761 LPDDR4 DRAM CONFIGURATION
750 20:12:03.751212 ===================================
751 20:12:03.751293 EX_ROW_EN[0] = 0x10
752 20:12:03.754287 EX_ROW_EN[1] = 0x0
753 20:12:03.754373 LP4Y_EN = 0x0
754 20:12:03.757639 WORK_FSP = 0x0
755 20:12:03.757725 WL = 0x2
756 20:12:03.760819 RL = 0x2
757 20:12:03.760936 BL = 0x2
758 20:12:03.764617 RPST = 0x0
759 20:12:03.764722 RD_PRE = 0x0
760 20:12:03.768034 WR_PRE = 0x1
761 20:12:03.771028 WR_PST = 0x0
762 20:12:03.771140 DBI_WR = 0x0
763 20:12:03.774400 DBI_RD = 0x0
764 20:12:03.774518 OTF = 0x1
765 20:12:03.777760 ===================================
766 20:12:03.784123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 20:12:03.788141 nWR fixed to 40
768 20:12:03.791139 [ModeRegInit_LP4] CH0 RK0
769 20:12:03.791226 [ModeRegInit_LP4] CH0 RK1
770 20:12:03.794895 [ModeRegInit_LP4] CH1 RK0
771 20:12:03.797901 [ModeRegInit_LP4] CH1 RK1
772 20:12:03.798032 match AC timing 13
773 20:12:03.804527 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 20:12:03.807906 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 20:12:03.811108 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 20:12:03.817790 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 20:12:03.821124 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 20:12:03.824271 [EMI DOE] emi_dcm 0
779 20:12:03.827582 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 20:12:03.827711 ==
781 20:12:03.830981 Dram Type= 6, Freq= 0, CH_0, rank 0
782 20:12:03.834383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 20:12:03.834512 ==
784 20:12:03.841050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 20:12:03.847613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 20:12:03.855699 [CA 0] Center 37 (7~68) winsize 62
787 20:12:03.858871 [CA 1] Center 37 (7~68) winsize 62
788 20:12:03.862395 [CA 2] Center 34 (4~65) winsize 62
789 20:12:03.865403 [CA 3] Center 35 (4~66) winsize 63
790 20:12:03.868753 [CA 4] Center 33 (3~64) winsize 62
791 20:12:03.872476 [CA 5] Center 33 (3~64) winsize 62
792 20:12:03.872607
793 20:12:03.875535 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 20:12:03.875666
795 20:12:03.878568 [CATrainingPosCal] consider 1 rank data
796 20:12:03.881962 u2DelayCellTimex100 = 270/100 ps
797 20:12:03.885094 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 20:12:03.891690 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 20:12:03.895308 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 20:12:03.898487 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 20:12:03.901704 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 20:12:03.905002 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 20:12:03.905119
804 20:12:03.908468 CA PerBit enable=1, Macro0, CA PI delay=33
805 20:12:03.908576
806 20:12:03.911694 [CBTSetCACLKResult] CA Dly = 33
807 20:12:03.911781 CS Dly: 5 (0~36)
808 20:12:03.915143 ==
809 20:12:03.918394 Dram Type= 6, Freq= 0, CH_0, rank 1
810 20:12:03.921585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 20:12:03.921693 ==
812 20:12:03.924915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 20:12:03.931562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 20:12:03.942372 [CA 0] Center 38 (7~69) winsize 63
815 20:12:03.944969 [CA 1] Center 37 (7~68) winsize 62
816 20:12:03.948221 [CA 2] Center 35 (4~66) winsize 63
817 20:12:03.951497 [CA 3] Center 35 (4~66) winsize 63
818 20:12:03.954734 [CA 4] Center 34 (3~65) winsize 63
819 20:12:03.958534 [CA 5] Center 33 (3~64) winsize 62
820 20:12:03.958620
821 20:12:03.961776 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 20:12:03.961862
823 20:12:03.965028 [CATrainingPosCal] consider 2 rank data
824 20:12:03.968044 u2DelayCellTimex100 = 270/100 ps
825 20:12:03.971723 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 20:12:03.978531 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 20:12:03.981156 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 20:12:03.984574 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 20:12:03.987852 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 20:12:03.991665 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 20:12:03.991791
832 20:12:03.994944 CA PerBit enable=1, Macro0, CA PI delay=33
833 20:12:03.995053
834 20:12:03.998050 [CBTSetCACLKResult] CA Dly = 33
835 20:12:04.001319 CS Dly: 5 (0~37)
836 20:12:04.001406
837 20:12:04.004921 ----->DramcWriteLeveling(PI) begin...
838 20:12:04.005040 ==
839 20:12:04.008239 Dram Type= 6, Freq= 0, CH_0, rank 0
840 20:12:04.011654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 20:12:04.011741 ==
842 20:12:04.015173 Write leveling (Byte 0): 30 => 30
843 20:12:04.019157 Write leveling (Byte 1): 26 => 26
844 20:12:04.019294 DramcWriteLeveling(PI) end<-----
845 20:12:04.019419
846 20:12:04.019538 ==
847 20:12:04.022965 Dram Type= 6, Freq= 0, CH_0, rank 0
848 20:12:04.029793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 20:12:04.029908 ==
850 20:12:04.030006 [Gating] SW mode calibration
851 20:12:04.036631 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 20:12:04.043340 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 20:12:04.046826 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 20:12:04.054279 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 20:12:04.056966 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 20:12:04.060386 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 20:12:04.066811 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:12:04.070168 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:12:04.073385 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:12:04.079982 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:12:04.083253 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:12:04.086510 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:12:04.093410 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 20:12:04.096668 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 20:12:04.099898 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 20:12:04.106166 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 20:12:04.110103 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 20:12:04.112767 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 20:12:04.116265 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 20:12:04.123018 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 20:12:04.126082 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 20:12:04.129445 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 20:12:04.135968 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 20:12:04.139257 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 20:12:04.142886 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 20:12:04.149007 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 20:12:04.152402 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 20:12:04.155950 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 20:12:04.162905 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
880 20:12:04.166108 0 9 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
881 20:12:04.169529 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 20:12:04.175780 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 20:12:04.179035 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 20:12:04.182412 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 20:12:04.189028 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 20:12:04.192225 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
887 20:12:04.196062 0 10 8 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
888 20:12:04.202634 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 20:12:04.205979 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 20:12:04.209474 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 20:12:04.215629 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 20:12:04.219224 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 20:12:04.222740 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 20:12:04.229125 0 11 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
895 20:12:04.232590 0 11 8 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
896 20:12:04.235572 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
897 20:12:04.242560 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 20:12:04.246107 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 20:12:04.249441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 20:12:04.255953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 20:12:04.258972 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 20:12:04.262613 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 20:12:04.265839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 20:12:04.272499 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 20:12:04.275605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 20:12:04.278909 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 20:12:04.285773 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 20:12:04.288827 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 20:12:04.292621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 20:12:04.299177 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 20:12:04.302069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 20:12:04.305679 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 20:12:04.312301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 20:12:04.315979 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 20:12:04.319288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 20:12:04.326012 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 20:12:04.329053 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 20:12:04.332310 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 20:12:04.339203 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 20:12:04.339312 Total UI for P1: 0, mck2ui 16
921 20:12:04.345469 best dqsien dly found for B0: ( 0, 14, 4)
922 20:12:04.348709 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 20:12:04.352132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 20:12:04.355392 Total UI for P1: 0, mck2ui 16
925 20:12:04.359132 best dqsien dly found for B1: ( 0, 14, 10)
926 20:12:04.362650 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
927 20:12:04.365310 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 20:12:04.365404
929 20:12:04.369084 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
930 20:12:04.375470 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 20:12:04.375582 [Gating] SW calibration Done
932 20:12:04.375660 ==
933 20:12:04.379227 Dram Type= 6, Freq= 0, CH_0, rank 0
934 20:12:04.386172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 20:12:04.386289 ==
936 20:12:04.386384 RX Vref Scan: 0
937 20:12:04.386449
938 20:12:04.389345 RX Vref 0 -> 0, step: 1
939 20:12:04.389442
940 20:12:04.392571 RX Delay -130 -> 252, step: 16
941 20:12:04.396048 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 20:12:04.399518 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 20:12:04.402468 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 20:12:04.405710 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 20:12:04.412468 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 20:12:04.416006 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 20:12:04.419091 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 20:12:04.422931 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 20:12:04.425652 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 20:12:04.432482 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
951 20:12:04.435890 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 20:12:04.439750 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 20:12:04.442617 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 20:12:04.448872 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 20:12:04.452202 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 20:12:04.455420 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 20:12:04.455503 ==
958 20:12:04.458808 Dram Type= 6, Freq= 0, CH_0, rank 0
959 20:12:04.462021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 20:12:04.462164 ==
961 20:12:04.465394 DQS Delay:
962 20:12:04.465477 DQS0 = 0, DQS1 = 0
963 20:12:04.469118 DQM Delay:
964 20:12:04.469203 DQM0 = 88, DQM1 = 75
965 20:12:04.469270 DQ Delay:
966 20:12:04.472370 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 20:12:04.475598 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
968 20:12:04.479013 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
969 20:12:04.482356 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 20:12:04.482441
971 20:12:04.482507
972 20:12:04.485233 ==
973 20:12:04.488678 Dram Type= 6, Freq= 0, CH_0, rank 0
974 20:12:04.492408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 20:12:04.492492 ==
976 20:12:04.492558
977 20:12:04.492618
978 20:12:04.495693 TX Vref Scan disable
979 20:12:04.495819 == TX Byte 0 ==
980 20:12:04.498951 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
981 20:12:04.505436 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
982 20:12:04.505525 == TX Byte 1 ==
983 20:12:04.508832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
984 20:12:04.515162 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
985 20:12:04.515245 ==
986 20:12:04.518316 Dram Type= 6, Freq= 0, CH_0, rank 0
987 20:12:04.521730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 20:12:04.521816 ==
989 20:12:04.535655 TX Vref=22, minBit 1, minWin=26, winSum=434
990 20:12:04.538862 TX Vref=24, minBit 4, minWin=26, winSum=442
991 20:12:04.542428 TX Vref=26, minBit 0, minWin=27, winSum=445
992 20:12:04.545448 TX Vref=28, minBit 1, minWin=27, winSum=445
993 20:12:04.548750 TX Vref=30, minBit 6, minWin=27, winSum=449
994 20:12:04.555374 TX Vref=32, minBit 2, minWin=27, winSum=448
995 20:12:04.558651 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 30
996 20:12:04.558752
997 20:12:04.561993 Final TX Range 1 Vref 30
998 20:12:04.562078
999 20:12:04.562145 ==
1000 20:12:04.565820 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 20:12:04.569034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 20:12:04.569118 ==
1003 20:12:04.569184
1004 20:12:04.571991
1005 20:12:04.572091 TX Vref Scan disable
1006 20:12:04.575311 == TX Byte 0 ==
1007 20:12:04.578573 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1008 20:12:04.586188 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1009 20:12:04.586269 == TX Byte 1 ==
1010 20:12:04.588870 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1011 20:12:04.595014 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1012 20:12:04.595133
1013 20:12:04.595228 [DATLAT]
1014 20:12:04.595320 Freq=800, CH0 RK0
1015 20:12:04.595420
1016 20:12:04.598911 DATLAT Default: 0xa
1017 20:12:04.599022 0, 0xFFFF, sum = 0
1018 20:12:04.601731 1, 0xFFFF, sum = 0
1019 20:12:04.605204 2, 0xFFFF, sum = 0
1020 20:12:04.605320 3, 0xFFFF, sum = 0
1021 20:12:04.608252 4, 0xFFFF, sum = 0
1022 20:12:04.608366 5, 0xFFFF, sum = 0
1023 20:12:04.612043 6, 0xFFFF, sum = 0
1024 20:12:04.612149 7, 0xFFFF, sum = 0
1025 20:12:04.615412 8, 0xFFFF, sum = 0
1026 20:12:04.615489 9, 0x0, sum = 1
1027 20:12:04.618739 10, 0x0, sum = 2
1028 20:12:04.618812 11, 0x0, sum = 3
1029 20:12:04.618874 12, 0x0, sum = 4
1030 20:12:04.622016 best_step = 10
1031 20:12:04.622100
1032 20:12:04.622165 ==
1033 20:12:04.625168 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 20:12:04.629140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 20:12:04.629249 ==
1036 20:12:04.631747 RX Vref Scan: 1
1037 20:12:04.631826
1038 20:12:04.635191 Set Vref Range= 32 -> 127
1039 20:12:04.635303
1040 20:12:04.635404 RX Vref 32 -> 127, step: 1
1041 20:12:04.635468
1042 20:12:04.638455 RX Delay -111 -> 252, step: 8
1043 20:12:04.638549
1044 20:12:04.641887 Set Vref, RX VrefLevel [Byte0]: 32
1045 20:12:04.645308 [Byte1]: 32
1046 20:12:04.645392
1047 20:12:04.648255 Set Vref, RX VrefLevel [Byte0]: 33
1048 20:12:04.651518 [Byte1]: 33
1049 20:12:04.656086
1050 20:12:04.656171 Set Vref, RX VrefLevel [Byte0]: 34
1051 20:12:04.659193 [Byte1]: 34
1052 20:12:04.663953
1053 20:12:04.664033 Set Vref, RX VrefLevel [Byte0]: 35
1054 20:12:04.666802 [Byte1]: 35
1055 20:12:04.671636
1056 20:12:04.671724 Set Vref, RX VrefLevel [Byte0]: 36
1057 20:12:04.675266 [Byte1]: 36
1058 20:12:04.678951
1059 20:12:04.682239 Set Vref, RX VrefLevel [Byte0]: 37
1060 20:12:04.682346 [Byte1]: 37
1061 20:12:04.686752
1062 20:12:04.686861 Set Vref, RX VrefLevel [Byte0]: 38
1063 20:12:04.690460 [Byte1]: 38
1064 20:12:04.694268
1065 20:12:04.694374 Set Vref, RX VrefLevel [Byte0]: 39
1066 20:12:04.697992 [Byte1]: 39
1067 20:12:04.702214
1068 20:12:04.702319 Set Vref, RX VrefLevel [Byte0]: 40
1069 20:12:04.705775 [Byte1]: 40
1070 20:12:04.709842
1071 20:12:04.709962 Set Vref, RX VrefLevel [Byte0]: 41
1072 20:12:04.712767 [Byte1]: 41
1073 20:12:04.716855
1074 20:12:04.716961 Set Vref, RX VrefLevel [Byte0]: 42
1075 20:12:04.720636 [Byte1]: 42
1076 20:12:04.724836
1077 20:12:04.724939 Set Vref, RX VrefLevel [Byte0]: 43
1078 20:12:04.728301 [Byte1]: 43
1079 20:12:04.732610
1080 20:12:04.732712 Set Vref, RX VrefLevel [Byte0]: 44
1081 20:12:04.735633 [Byte1]: 44
1082 20:12:04.740171
1083 20:12:04.740248 Set Vref, RX VrefLevel [Byte0]: 45
1084 20:12:04.743438 [Byte1]: 45
1085 20:12:04.747855
1086 20:12:04.747934 Set Vref, RX VrefLevel [Byte0]: 46
1087 20:12:04.750866 [Byte1]: 46
1088 20:12:04.755186
1089 20:12:04.755295 Set Vref, RX VrefLevel [Byte0]: 47
1090 20:12:04.758321 [Byte1]: 47
1091 20:12:04.763048
1092 20:12:04.763174 Set Vref, RX VrefLevel [Byte0]: 48
1093 20:12:04.766036 [Byte1]: 48
1094 20:12:04.770618
1095 20:12:04.770744 Set Vref, RX VrefLevel [Byte0]: 49
1096 20:12:04.773663 [Byte1]: 49
1097 20:12:04.778241
1098 20:12:04.778367 Set Vref, RX VrefLevel [Byte0]: 50
1099 20:12:04.781615 [Byte1]: 50
1100 20:12:04.785787
1101 20:12:04.785874 Set Vref, RX VrefLevel [Byte0]: 51
1102 20:12:04.789183 [Byte1]: 51
1103 20:12:04.793288
1104 20:12:04.793392 Set Vref, RX VrefLevel [Byte0]: 52
1105 20:12:04.797231 [Byte1]: 52
1106 20:12:04.801184
1107 20:12:04.801291 Set Vref, RX VrefLevel [Byte0]: 53
1108 20:12:04.804595 [Byte1]: 53
1109 20:12:04.808703
1110 20:12:04.808780 Set Vref, RX VrefLevel [Byte0]: 54
1111 20:12:04.812058 [Byte1]: 54
1112 20:12:04.816349
1113 20:12:04.816427 Set Vref, RX VrefLevel [Byte0]: 55
1114 20:12:04.820065 [Byte1]: 55
1115 20:12:04.824438
1116 20:12:04.824522 Set Vref, RX VrefLevel [Byte0]: 56
1117 20:12:04.827326 [Byte1]: 56
1118 20:12:04.831974
1119 20:12:04.832057 Set Vref, RX VrefLevel [Byte0]: 57
1120 20:12:04.834981 [Byte1]: 57
1121 20:12:04.839457
1122 20:12:04.839538 Set Vref, RX VrefLevel [Byte0]: 58
1123 20:12:04.842856 [Byte1]: 58
1124 20:12:04.847256
1125 20:12:04.847338 Set Vref, RX VrefLevel [Byte0]: 59
1126 20:12:04.850242 [Byte1]: 59
1127 20:12:04.855320
1128 20:12:04.855452 Set Vref, RX VrefLevel [Byte0]: 60
1129 20:12:04.857936 [Byte1]: 60
1130 20:12:04.862270
1131 20:12:04.862351 Set Vref, RX VrefLevel [Byte0]: 61
1132 20:12:04.865733 [Byte1]: 61
1133 20:12:04.869785
1134 20:12:04.869866 Set Vref, RX VrefLevel [Byte0]: 62
1135 20:12:04.873193 [Byte1]: 62
1136 20:12:04.878058
1137 20:12:04.878154 Set Vref, RX VrefLevel [Byte0]: 63
1138 20:12:04.881321 [Byte1]: 63
1139 20:12:04.885546
1140 20:12:04.885669 Set Vref, RX VrefLevel [Byte0]: 64
1141 20:12:04.888487 [Byte1]: 64
1142 20:12:04.892809
1143 20:12:04.892890 Set Vref, RX VrefLevel [Byte0]: 65
1144 20:12:04.896277 [Byte1]: 65
1145 20:12:04.900731
1146 20:12:04.900811 Set Vref, RX VrefLevel [Byte0]: 66
1147 20:12:04.903834 [Byte1]: 66
1148 20:12:04.908472
1149 20:12:04.908570 Set Vref, RX VrefLevel [Byte0]: 67
1150 20:12:04.911396 [Byte1]: 67
1151 20:12:04.915746
1152 20:12:04.915826 Set Vref, RX VrefLevel [Byte0]: 68
1153 20:12:04.918916 [Byte1]: 68
1154 20:12:04.923801
1155 20:12:04.923882 Set Vref, RX VrefLevel [Byte0]: 69
1156 20:12:04.926669 [Byte1]: 69
1157 20:12:04.931300
1158 20:12:04.931424 Set Vref, RX VrefLevel [Byte0]: 70
1159 20:12:04.934770 [Byte1]: 70
1160 20:12:04.938572
1161 20:12:04.938676 Set Vref, RX VrefLevel [Byte0]: 71
1162 20:12:04.942344 [Byte1]: 71
1163 20:12:04.946252
1164 20:12:04.946335 Set Vref, RX VrefLevel [Byte0]: 72
1165 20:12:04.949821 [Byte1]: 72
1166 20:12:04.954245
1167 20:12:04.954390 Set Vref, RX VrefLevel [Byte0]: 73
1168 20:12:04.957564 [Byte1]: 73
1169 20:12:04.961753
1170 20:12:04.961836 Final RX Vref Byte 0 = 55 to rank0
1171 20:12:04.965213 Final RX Vref Byte 1 = 60 to rank0
1172 20:12:04.968498 Final RX Vref Byte 0 = 55 to rank1
1173 20:12:04.971747 Final RX Vref Byte 1 = 60 to rank1==
1174 20:12:04.974973 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 20:12:04.981764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 20:12:04.981848 ==
1177 20:12:04.981912 DQS Delay:
1178 20:12:04.981973 DQS0 = 0, DQS1 = 0
1179 20:12:04.985065 DQM Delay:
1180 20:12:04.985147 DQM0 = 88, DQM1 = 76
1181 20:12:04.988108 DQ Delay:
1182 20:12:04.991577 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1183 20:12:04.994839 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1184 20:12:04.997989 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1185 20:12:05.001618 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1186 20:12:05.001701
1187 20:12:05.001765
1188 20:12:05.007942 [DQSOSCAuto] RK0, (LSB)MR18= 0x312a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1189 20:12:05.011303 CH0 RK0: MR19=606, MR18=312A
1190 20:12:05.017838 CH0_RK0: MR19=0x606, MR18=0x312A, DQSOSC=397, MR23=63, INC=93, DEC=62
1191 20:12:05.017970
1192 20:12:05.021444 ----->DramcWriteLeveling(PI) begin...
1193 20:12:05.021570 ==
1194 20:12:05.024389 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 20:12:05.027929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 20:12:05.028054 ==
1197 20:12:05.031235 Write leveling (Byte 0): 31 => 31
1198 20:12:05.034532 Write leveling (Byte 1): 30 => 30
1199 20:12:05.038129 DramcWriteLeveling(PI) end<-----
1200 20:12:05.038284
1201 20:12:05.038399 ==
1202 20:12:05.041127 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 20:12:05.044438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 20:12:05.044561 ==
1205 20:12:05.048140 [Gating] SW mode calibration
1206 20:12:05.054419 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 20:12:05.061105 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 20:12:05.064744 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 20:12:05.071267 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1210 20:12:05.115112 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1211 20:12:05.115657 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 20:12:05.115782 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 20:12:05.116097 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 20:12:05.116215 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 20:12:05.116346 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 20:12:05.116460 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 20:12:05.116569 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 20:12:05.116940 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 20:12:05.117262 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 20:12:05.140521 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 20:12:05.140649 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 20:12:05.140964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 20:12:05.141085 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 20:12:05.141404 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 20:12:05.144108 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1226 20:12:05.144230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1227 20:12:05.147294 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 20:12:05.153902 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 20:12:05.157475 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 20:12:05.161024 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 20:12:05.167432 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 20:12:05.170829 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 20:12:05.173932 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1234 20:12:05.180793 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
1235 20:12:05.184145 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 20:12:05.187314 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 20:12:05.194122 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 20:12:05.197285 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 20:12:05.200662 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 20:12:05.207167 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 20:12:05.210465 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1242 20:12:05.214142 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
1243 20:12:05.220578 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 20:12:05.223744 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 20:12:05.226959 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 20:12:05.233668 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 20:12:05.237295 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 20:12:05.240421 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 20:12:05.246755 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1250 20:12:05.250383 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1251 20:12:05.253782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 20:12:05.257462 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 20:12:05.261358 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 20:12:05.268687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 20:12:05.271756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 20:12:05.274978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 20:12:05.282548 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1258 20:12:05.285779 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1259 20:12:05.289309 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 20:12:05.292543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 20:12:05.299142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 20:12:05.302542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 20:12:05.305678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 20:12:05.312543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 20:12:05.315680 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 20:12:05.319102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 20:12:05.325606 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 20:12:05.329253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 20:12:05.332262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 20:12:05.338680 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 20:12:05.342097 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 20:12:05.345735 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 20:12:05.352012 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1274 20:12:05.355265 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1275 20:12:05.358514 Total UI for P1: 0, mck2ui 16
1276 20:12:05.362080 best dqsien dly found for B0: ( 0, 14, 4)
1277 20:12:05.365660 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 20:12:05.368881 Total UI for P1: 0, mck2ui 16
1279 20:12:05.372129 best dqsien dly found for B1: ( 0, 14, 8)
1280 20:12:05.375058 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1281 20:12:05.378681 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1282 20:12:05.378763
1283 20:12:05.381890 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1284 20:12:05.388736 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1285 20:12:05.388833 [Gating] SW calibration Done
1286 20:12:05.388898 ==
1287 20:12:05.391891 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 20:12:05.398256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 20:12:05.398340 ==
1290 20:12:05.398404 RX Vref Scan: 0
1291 20:12:05.398465
1292 20:12:05.402125 RX Vref 0 -> 0, step: 1
1293 20:12:05.402208
1294 20:12:05.405029 RX Delay -130 -> 252, step: 16
1295 20:12:05.408777 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1296 20:12:05.411854 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1297 20:12:05.414879 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1298 20:12:05.421541 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1299 20:12:05.424790 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1300 20:12:05.428057 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1301 20:12:05.431763 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1302 20:12:05.435113 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1303 20:12:05.441605 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1304 20:12:05.444963 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1305 20:12:05.448033 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1306 20:12:05.451717 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1307 20:12:05.454883 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1308 20:12:05.461714 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1309 20:12:05.464678 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1310 20:12:05.468030 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1311 20:12:05.468155 ==
1312 20:12:05.471261 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 20:12:05.474534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 20:12:05.478132 ==
1315 20:12:05.478236 DQS Delay:
1316 20:12:05.478329 DQS0 = 0, DQS1 = 0
1317 20:12:05.481135 DQM Delay:
1318 20:12:05.481237 DQM0 = 86, DQM1 = 77
1319 20:12:05.484611 DQ Delay:
1320 20:12:05.484693 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1321 20:12:05.488106 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1322 20:12:05.491142 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1323 20:12:05.494524 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1324 20:12:05.497807
1325 20:12:05.497889
1326 20:12:05.497952 ==
1327 20:12:05.501085 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 20:12:05.504522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 20:12:05.504605 ==
1330 20:12:05.504692
1331 20:12:05.504803
1332 20:12:05.507826 TX Vref Scan disable
1333 20:12:05.507908 == TX Byte 0 ==
1334 20:12:05.514707 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1335 20:12:05.517603 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1336 20:12:05.517685 == TX Byte 1 ==
1337 20:12:05.524740 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1338 20:12:05.527754 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1339 20:12:05.527837 ==
1340 20:12:05.530782 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 20:12:05.534394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 20:12:05.534477 ==
1343 20:12:05.547928 TX Vref=22, minBit 1, minWin=27, winSum=442
1344 20:12:05.550886 TX Vref=24, minBit 1, minWin=27, winSum=442
1345 20:12:05.554485 TX Vref=26, minBit 2, minWin=27, winSum=447
1346 20:12:05.557656 TX Vref=28, minBit 1, minWin=27, winSum=448
1347 20:12:05.561082 TX Vref=30, minBit 1, minWin=27, winSum=448
1348 20:12:05.568077 TX Vref=32, minBit 4, minWin=27, winSum=447
1349 20:12:05.570920 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 28
1350 20:12:05.571044
1351 20:12:05.574390 Final TX Range 1 Vref 28
1352 20:12:05.574514
1353 20:12:05.574626 ==
1354 20:12:05.577817 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 20:12:05.581106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 20:12:05.581229 ==
1357 20:12:05.584688
1358 20:12:05.584793
1359 20:12:05.584885 TX Vref Scan disable
1360 20:12:05.587821 == TX Byte 0 ==
1361 20:12:05.591072 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1362 20:12:05.594456 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1363 20:12:05.597623 == TX Byte 1 ==
1364 20:12:05.600870 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1365 20:12:05.604227 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1366 20:12:05.607943
1367 20:12:05.608046 [DATLAT]
1368 20:12:05.608139 Freq=800, CH0 RK1
1369 20:12:05.608227
1370 20:12:05.610854 DATLAT Default: 0xa
1371 20:12:05.610978 0, 0xFFFF, sum = 0
1372 20:12:05.614542 1, 0xFFFF, sum = 0
1373 20:12:05.614625 2, 0xFFFF, sum = 0
1374 20:12:05.617363 3, 0xFFFF, sum = 0
1375 20:12:05.620883 4, 0xFFFF, sum = 0
1376 20:12:05.621011 5, 0xFFFF, sum = 0
1377 20:12:05.624277 6, 0xFFFF, sum = 0
1378 20:12:05.624361 7, 0xFFFF, sum = 0
1379 20:12:05.627549 8, 0xFFFF, sum = 0
1380 20:12:05.627631 9, 0x0, sum = 1
1381 20:12:05.630706 10, 0x0, sum = 2
1382 20:12:05.630788 11, 0x0, sum = 3
1383 20:12:05.630985 12, 0x0, sum = 4
1384 20:12:05.634325 best_step = 10
1385 20:12:05.634447
1386 20:12:05.634559 ==
1387 20:12:05.637641 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 20:12:05.640842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 20:12:05.640997 ==
1390 20:12:05.644467 RX Vref Scan: 0
1391 20:12:05.644595
1392 20:12:05.644710 RX Vref 0 -> 0, step: 1
1393 20:12:05.647414
1394 20:12:05.647518 RX Delay -95 -> 252, step: 8
1395 20:12:05.654667 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1396 20:12:05.657600 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1397 20:12:05.661373 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1398 20:12:05.664236 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1399 20:12:05.667903 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1400 20:12:05.674016 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1401 20:12:05.677978 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1402 20:12:05.680762 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1403 20:12:05.684405 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1404 20:12:05.687532 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1405 20:12:05.694361 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1406 20:12:05.697469 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1407 20:12:05.700679 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1408 20:12:05.704046 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1409 20:12:05.710714 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1410 20:12:05.713832 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1411 20:12:05.713915 ==
1412 20:12:05.717164 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 20:12:05.720523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 20:12:05.720606 ==
1415 20:12:05.723719 DQS Delay:
1416 20:12:05.723800 DQS0 = 0, DQS1 = 0
1417 20:12:05.723864 DQM Delay:
1418 20:12:05.727547 DQM0 = 86, DQM1 = 78
1419 20:12:05.727628 DQ Delay:
1420 20:12:05.730844 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1421 20:12:05.734085 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1422 20:12:05.737300 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1423 20:12:05.740712 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1424 20:12:05.740793
1425 20:12:05.740858
1426 20:12:05.750613 [DQSOSCAuto] RK1, (LSB)MR18= 0x2421, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1427 20:12:05.750743 CH0 RK1: MR19=606, MR18=2421
1428 20:12:05.757319 CH0_RK1: MR19=0x606, MR18=0x2421, DQSOSC=400, MR23=63, INC=92, DEC=61
1429 20:12:05.760412 [RxdqsGatingPostProcess] freq 800
1430 20:12:05.767080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1431 20:12:05.770705 Pre-setting of DQS Precalculation
1432 20:12:05.774051 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1433 20:12:05.774134 ==
1434 20:12:05.777225 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 20:12:05.783715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 20:12:05.783800 ==
1437 20:12:05.787045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 20:12:05.793933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 20:12:05.802614 [CA 0] Center 37 (6~68) winsize 63
1440 20:12:05.805749 [CA 1] Center 36 (6~67) winsize 62
1441 20:12:05.809597 [CA 2] Center 35 (5~66) winsize 62
1442 20:12:05.812549 [CA 3] Center 34 (4~65) winsize 62
1443 20:12:05.816342 [CA 4] Center 35 (4~66) winsize 63
1444 20:12:05.819481 [CA 5] Center 34 (4~65) winsize 62
1445 20:12:05.819562
1446 20:12:05.822938 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1447 20:12:05.823020
1448 20:12:05.825909 [CATrainingPosCal] consider 1 rank data
1449 20:12:05.829230 u2DelayCellTimex100 = 270/100 ps
1450 20:12:05.832477 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1451 20:12:05.835811 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 20:12:05.842456 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1453 20:12:05.845734 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 20:12:05.848883 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1455 20:12:05.852796 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 20:12:05.852921
1457 20:12:05.855991 CA PerBit enable=1, Macro0, CA PI delay=34
1458 20:12:05.856113
1459 20:12:05.858968 [CBTSetCACLKResult] CA Dly = 34
1460 20:12:05.859087 CS Dly: 4 (0~35)
1461 20:12:05.862234 ==
1462 20:12:05.865597 Dram Type= 6, Freq= 0, CH_1, rank 1
1463 20:12:05.868914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 20:12:05.868996 ==
1465 20:12:05.872073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1466 20:12:05.878728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1467 20:12:05.888610 [CA 0] Center 36 (6~67) winsize 62
1468 20:12:05.892221 [CA 1] Center 36 (6~67) winsize 62
1469 20:12:05.895238 [CA 2] Center 34 (4~65) winsize 62
1470 20:12:05.898549 [CA 3] Center 34 (4~65) winsize 62
1471 20:12:05.902390 [CA 4] Center 34 (4~65) winsize 62
1472 20:12:05.905121 [CA 5] Center 34 (4~65) winsize 62
1473 20:12:05.905203
1474 20:12:05.908374 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1475 20:12:05.908456
1476 20:12:05.912052 [CATrainingPosCal] consider 2 rank data
1477 20:12:05.915157 u2DelayCellTimex100 = 270/100 ps
1478 20:12:05.918895 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1479 20:12:05.922769 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 20:12:05.926227 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1481 20:12:05.929440 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 20:12:05.933213 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 20:12:05.936907 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 20:12:05.936994
1485 20:12:05.940840 CA PerBit enable=1, Macro0, CA PI delay=34
1486 20:12:05.940922
1487 20:12:05.944702 [CBTSetCACLKResult] CA Dly = 34
1488 20:12:05.948449 CS Dly: 5 (0~37)
1489 20:12:05.948531
1490 20:12:05.951723 ----->DramcWriteLeveling(PI) begin...
1491 20:12:05.951807 ==
1492 20:12:05.955544 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 20:12:05.958528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 20:12:05.958611 ==
1495 20:12:05.962319 Write leveling (Byte 0): 26 => 26
1496 20:12:05.965505 Write leveling (Byte 1): 27 => 27
1497 20:12:05.968572 DramcWriteLeveling(PI) end<-----
1498 20:12:05.968655
1499 20:12:05.968719 ==
1500 20:12:05.971759 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 20:12:05.975685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 20:12:05.975769 ==
1503 20:12:05.978656 [Gating] SW mode calibration
1504 20:12:05.984948 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1505 20:12:05.991998 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1506 20:12:05.995032 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1507 20:12:05.998361 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1508 20:12:06.004813 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 20:12:06.008404 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 20:12:06.011773 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 20:12:06.018064 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 20:12:06.021794 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 20:12:06.024851 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 20:12:06.031559 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 20:12:06.034832 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 20:12:06.037913 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 20:12:06.044529 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 20:12:06.047907 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 20:12:06.051092 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 20:12:06.057588 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 20:12:06.060961 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 20:12:06.064230 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 20:12:06.070692 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1524 20:12:06.074508 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 20:12:06.077487 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 20:12:06.084049 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 20:12:06.087229 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 20:12:06.090639 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 20:12:06.097149 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 20:12:06.100481 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 20:12:06.103801 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1532 20:12:06.110390 0 9 8 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)
1533 20:12:06.114080 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 20:12:06.117124 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 20:12:06.123498 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 20:12:06.126950 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 20:12:06.130434 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 20:12:06.133792 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1539 20:12:06.140324 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
1540 20:12:06.143630 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1541 20:12:06.146775 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 20:12:06.153774 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 20:12:06.157005 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 20:12:06.160539 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 20:12:06.166976 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 20:12:06.170181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 20:12:06.173215 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
1548 20:12:06.180619 0 11 8 | B1->B0 | 3a3a 4444 | 0 0 | (1 1) (0 0)
1549 20:12:06.183296 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 20:12:06.186807 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 20:12:06.193508 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 20:12:06.196629 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 20:12:06.199964 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 20:12:06.206982 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 20:12:06.209992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1556 20:12:06.213413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 20:12:06.220008 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 20:12:06.223588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 20:12:06.226661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 20:12:06.233179 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 20:12:06.236470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 20:12:06.239972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 20:12:06.246583 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 20:12:06.249651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 20:12:06.252972 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 20:12:06.259700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 20:12:06.262855 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 20:12:06.266957 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 20:12:06.272919 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 20:12:06.276247 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 20:12:06.279835 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 20:12:06.283007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1573 20:12:06.286106 Total UI for P1: 0, mck2ui 16
1574 20:12:06.289851 best dqsien dly found for B0: ( 0, 14, 6)
1575 20:12:06.296300 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 20:12:06.299955 Total UI for P1: 0, mck2ui 16
1577 20:12:06.303570 best dqsien dly found for B1: ( 0, 14, 8)
1578 20:12:06.306074 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1579 20:12:06.309947 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1580 20:12:06.310029
1581 20:12:06.313022 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1582 20:12:06.316646 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1583 20:12:06.319512 [Gating] SW calibration Done
1584 20:12:06.319594 ==
1585 20:12:06.322979 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 20:12:06.326374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 20:12:06.326457 ==
1588 20:12:06.329527 RX Vref Scan: 0
1589 20:12:06.329608
1590 20:12:06.329673 RX Vref 0 -> 0, step: 1
1591 20:12:06.329733
1592 20:12:06.333467 RX Delay -130 -> 252, step: 16
1593 20:12:06.339651 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1594 20:12:06.342614 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1595 20:12:06.346177 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1596 20:12:06.349409 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1597 20:12:06.353216 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1598 20:12:06.359374 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1599 20:12:06.363057 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1600 20:12:06.366234 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1601 20:12:06.369344 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1602 20:12:06.373029 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1603 20:12:06.379843 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1604 20:12:06.382508 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1605 20:12:06.386188 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1606 20:12:06.389517 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1607 20:12:06.392694 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1608 20:12:06.399289 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1609 20:12:06.399397 ==
1610 20:12:06.402755 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 20:12:06.406204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 20:12:06.406286 ==
1613 20:12:06.406351 DQS Delay:
1614 20:12:06.408982 DQS0 = 0, DQS1 = 0
1615 20:12:06.409063 DQM Delay:
1616 20:12:06.412580 DQM0 = 88, DQM1 = 79
1617 20:12:06.412662 DQ Delay:
1618 20:12:06.415959 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1619 20:12:06.418987 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1620 20:12:06.422693 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1621 20:12:06.425918 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 20:12:06.426001
1623 20:12:06.426064
1624 20:12:06.426123 ==
1625 20:12:06.429412 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 20:12:06.433292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 20:12:06.435798 ==
1628 20:12:06.435879
1629 20:12:06.435944
1630 20:12:06.436003 TX Vref Scan disable
1631 20:12:06.439158 == TX Byte 0 ==
1632 20:12:06.442741 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1633 20:12:06.445996 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1634 20:12:06.449118 == TX Byte 1 ==
1635 20:12:06.452734 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1636 20:12:06.455757 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1637 20:12:06.458950 ==
1638 20:12:06.459032 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 20:12:06.465607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 20:12:06.465690 ==
1641 20:12:06.477784 TX Vref=22, minBit 1, minWin=27, winSum=444
1642 20:12:06.480849 TX Vref=24, minBit 1, minWin=27, winSum=447
1643 20:12:06.484207 TX Vref=26, minBit 1, minWin=27, winSum=447
1644 20:12:06.487845 TX Vref=28, minBit 1, minWin=27, winSum=451
1645 20:12:06.491130 TX Vref=30, minBit 1, minWin=27, winSum=456
1646 20:12:06.497587 TX Vref=32, minBit 1, minWin=27, winSum=454
1647 20:12:06.501542 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 30
1648 20:12:06.501625
1649 20:12:06.504816 Final TX Range 1 Vref 30
1650 20:12:06.504899
1651 20:12:06.504965 ==
1652 20:12:06.508256 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 20:12:06.511898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 20:12:06.511981 ==
1655 20:12:06.512045
1656 20:12:06.512105
1657 20:12:06.515050 TX Vref Scan disable
1658 20:12:06.518303 == TX Byte 0 ==
1659 20:12:06.521713 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1660 20:12:06.524951 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1661 20:12:06.528237 == TX Byte 1 ==
1662 20:12:06.531695 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 20:12:06.534883 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 20:12:06.534965
1665 20:12:06.538315 [DATLAT]
1666 20:12:06.538397 Freq=800, CH1 RK0
1667 20:12:06.538462
1668 20:12:06.541939 DATLAT Default: 0xa
1669 20:12:06.542036 0, 0xFFFF, sum = 0
1670 20:12:06.544828 1, 0xFFFF, sum = 0
1671 20:12:06.544917 2, 0xFFFF, sum = 0
1672 20:12:06.548178 3, 0xFFFF, sum = 0
1673 20:12:06.548276 4, 0xFFFF, sum = 0
1674 20:12:06.551270 5, 0xFFFF, sum = 0
1675 20:12:06.551355 6, 0xFFFF, sum = 0
1676 20:12:06.554748 7, 0xFFFF, sum = 0
1677 20:12:06.554831 8, 0xFFFF, sum = 0
1678 20:12:06.558341 9, 0x0, sum = 1
1679 20:12:06.558423 10, 0x0, sum = 2
1680 20:12:06.561324 11, 0x0, sum = 3
1681 20:12:06.561420 12, 0x0, sum = 4
1682 20:12:06.564457 best_step = 10
1683 20:12:06.564611
1684 20:12:06.564738 ==
1685 20:12:06.568043 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 20:12:06.571345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 20:12:06.571451 ==
1688 20:12:06.574592 RX Vref Scan: 1
1689 20:12:06.574668
1690 20:12:06.574731 Set Vref Range= 32 -> 127
1691 20:12:06.574799
1692 20:12:06.577899 RX Vref 32 -> 127, step: 1
1693 20:12:06.577980
1694 20:12:06.580981 RX Delay -95 -> 252, step: 8
1695 20:12:06.581071
1696 20:12:06.584511 Set Vref, RX VrefLevel [Byte0]: 32
1697 20:12:06.587948 [Byte1]: 32
1698 20:12:06.588073
1699 20:12:06.591516 Set Vref, RX VrefLevel [Byte0]: 33
1700 20:12:06.594599 [Byte1]: 33
1701 20:12:06.598079
1702 20:12:06.598218 Set Vref, RX VrefLevel [Byte0]: 34
1703 20:12:06.601206 [Byte1]: 34
1704 20:12:06.605843
1705 20:12:06.605967 Set Vref, RX VrefLevel [Byte0]: 35
1706 20:12:06.609210 [Byte1]: 35
1707 20:12:06.613323
1708 20:12:06.613442 Set Vref, RX VrefLevel [Byte0]: 36
1709 20:12:06.616216 [Byte1]: 36
1710 20:12:06.621314
1711 20:12:06.621437 Set Vref, RX VrefLevel [Byte0]: 37
1712 20:12:06.624045 [Byte1]: 37
1713 20:12:06.628637
1714 20:12:06.628758 Set Vref, RX VrefLevel [Byte0]: 38
1715 20:12:06.631481 [Byte1]: 38
1716 20:12:06.635927
1717 20:12:06.636037 Set Vref, RX VrefLevel [Byte0]: 39
1718 20:12:06.639087 [Byte1]: 39
1719 20:12:06.643508
1720 20:12:06.643615 Set Vref, RX VrefLevel [Byte0]: 40
1721 20:12:06.646831 [Byte1]: 40
1722 20:12:06.650977
1723 20:12:06.651085 Set Vref, RX VrefLevel [Byte0]: 41
1724 20:12:06.654509 [Byte1]: 41
1725 20:12:06.658712
1726 20:12:06.658831 Set Vref, RX VrefLevel [Byte0]: 42
1727 20:12:06.661976 [Byte1]: 42
1728 20:12:06.666860
1729 20:12:06.666956 Set Vref, RX VrefLevel [Byte0]: 43
1730 20:12:06.669459 [Byte1]: 43
1731 20:12:06.673677
1732 20:12:06.673802 Set Vref, RX VrefLevel [Byte0]: 44
1733 20:12:06.677206 [Byte1]: 44
1734 20:12:06.681848
1735 20:12:06.681968 Set Vref, RX VrefLevel [Byte0]: 45
1736 20:12:06.684697 [Byte1]: 45
1737 20:12:06.688841
1738 20:12:06.688964 Set Vref, RX VrefLevel [Byte0]: 46
1739 20:12:06.692262 [Byte1]: 46
1740 20:12:06.696675
1741 20:12:06.696791 Set Vref, RX VrefLevel [Byte0]: 47
1742 20:12:06.699909 [Byte1]: 47
1743 20:12:06.704476
1744 20:12:06.704608 Set Vref, RX VrefLevel [Byte0]: 48
1745 20:12:06.707661 [Byte1]: 48
1746 20:12:06.712059
1747 20:12:06.712174 Set Vref, RX VrefLevel [Byte0]: 49
1748 20:12:06.715296 [Byte1]: 49
1749 20:12:06.719210
1750 20:12:06.719357 Set Vref, RX VrefLevel [Byte0]: 50
1751 20:12:06.722703 [Byte1]: 50
1752 20:12:06.726924
1753 20:12:06.727024 Set Vref, RX VrefLevel [Byte0]: 51
1754 20:12:06.730542 [Byte1]: 51
1755 20:12:06.734926
1756 20:12:06.735014 Set Vref, RX VrefLevel [Byte0]: 52
1757 20:12:06.738011 [Byte1]: 52
1758 20:12:06.742110
1759 20:12:06.742194 Set Vref, RX VrefLevel [Byte0]: 53
1760 20:12:06.745392 [Byte1]: 53
1761 20:12:06.749802
1762 20:12:06.749886 Set Vref, RX VrefLevel [Byte0]: 54
1763 20:12:06.753375 [Byte1]: 54
1764 20:12:06.757287
1765 20:12:06.757398 Set Vref, RX VrefLevel [Byte0]: 55
1766 20:12:06.761148 [Byte1]: 55
1767 20:12:06.764855
1768 20:12:06.764962 Set Vref, RX VrefLevel [Byte0]: 56
1769 20:12:06.768211 [Byte1]: 56
1770 20:12:06.772507
1771 20:12:06.772590 Set Vref, RX VrefLevel [Byte0]: 57
1772 20:12:06.775883 [Byte1]: 57
1773 20:12:06.780384
1774 20:12:06.780467 Set Vref, RX VrefLevel [Byte0]: 58
1775 20:12:06.783539 [Byte1]: 58
1776 20:12:06.787834
1777 20:12:06.787917 Set Vref, RX VrefLevel [Byte0]: 59
1778 20:12:06.790908 [Byte1]: 59
1779 20:12:06.795395
1780 20:12:06.795509 Set Vref, RX VrefLevel [Byte0]: 60
1781 20:12:06.798525 [Byte1]: 60
1782 20:12:06.802922
1783 20:12:06.803005 Set Vref, RX VrefLevel [Byte0]: 61
1784 20:12:06.806286 [Byte1]: 61
1785 20:12:06.810970
1786 20:12:06.811054 Set Vref, RX VrefLevel [Byte0]: 62
1787 20:12:06.813822 [Byte1]: 62
1788 20:12:06.818129
1789 20:12:06.818212 Set Vref, RX VrefLevel [Byte0]: 63
1790 20:12:06.821611 [Byte1]: 63
1791 20:12:06.825771
1792 20:12:06.825854 Set Vref, RX VrefLevel [Byte0]: 64
1793 20:12:06.829390 [Byte1]: 64
1794 20:12:06.833550
1795 20:12:06.833633 Set Vref, RX VrefLevel [Byte0]: 65
1796 20:12:06.836617 [Byte1]: 65
1797 20:12:06.840780
1798 20:12:06.840876 Set Vref, RX VrefLevel [Byte0]: 66
1799 20:12:06.844111 [Byte1]: 66
1800 20:12:06.848520
1801 20:12:06.848603 Set Vref, RX VrefLevel [Byte0]: 67
1802 20:12:06.852078 [Byte1]: 67
1803 20:12:06.856165
1804 20:12:06.856260 Set Vref, RX VrefLevel [Byte0]: 68
1805 20:12:06.859750 [Byte1]: 68
1806 20:12:06.863578
1807 20:12:06.863682 Set Vref, RX VrefLevel [Byte0]: 69
1808 20:12:06.866915 [Byte1]: 69
1809 20:12:06.871979
1810 20:12:06.872092 Set Vref, RX VrefLevel [Byte0]: 70
1811 20:12:06.874536 [Byte1]: 70
1812 20:12:06.878915
1813 20:12:06.878991 Set Vref, RX VrefLevel [Byte0]: 71
1814 20:12:06.882661 [Byte1]: 71
1815 20:12:06.886584
1816 20:12:06.886689 Set Vref, RX VrefLevel [Byte0]: 72
1817 20:12:06.890165 [Byte1]: 72
1818 20:12:06.894385
1819 20:12:06.894481 Set Vref, RX VrefLevel [Byte0]: 73
1820 20:12:06.897661 [Byte1]: 73
1821 20:12:06.901830
1822 20:12:06.901912 Set Vref, RX VrefLevel [Byte0]: 74
1823 20:12:06.905229 [Byte1]: 74
1824 20:12:06.909747
1825 20:12:06.909832 Set Vref, RX VrefLevel [Byte0]: 75
1826 20:12:06.913060 [Byte1]: 75
1827 20:12:06.917174
1828 20:12:06.917260 Set Vref, RX VrefLevel [Byte0]: 76
1829 20:12:06.920712 [Byte1]: 76
1830 20:12:06.924693
1831 20:12:06.924769 Final RX Vref Byte 0 = 60 to rank0
1832 20:12:06.927787 Final RX Vref Byte 1 = 56 to rank0
1833 20:12:06.931063 Final RX Vref Byte 0 = 60 to rank1
1834 20:12:06.934711 Final RX Vref Byte 1 = 56 to rank1==
1835 20:12:06.937996 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 20:12:06.944697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 20:12:06.944780 ==
1838 20:12:06.944845 DQS Delay:
1839 20:12:06.944906 DQS0 = 0, DQS1 = 0
1840 20:12:06.947833 DQM Delay:
1841 20:12:06.947916 DQM0 = 87, DQM1 = 81
1842 20:12:06.951291 DQ Delay:
1843 20:12:06.954813 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1844 20:12:06.954903 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1845 20:12:06.958019 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1846 20:12:06.964440 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1847 20:12:06.964591
1848 20:12:06.964687
1849 20:12:06.971424 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1850 20:12:06.974806 CH1 RK0: MR19=606, MR18=1D30
1851 20:12:06.981486 CH1_RK0: MR19=0x606, MR18=0x1D30, DQSOSC=397, MR23=63, INC=93, DEC=62
1852 20:12:06.981574
1853 20:12:06.984577 ----->DramcWriteLeveling(PI) begin...
1854 20:12:06.984660 ==
1855 20:12:06.987980 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 20:12:06.991286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 20:12:06.991414 ==
1858 20:12:06.995124 Write leveling (Byte 0): 27 => 27
1859 20:12:06.997584 Write leveling (Byte 1): 28 => 28
1860 20:12:07.001530 DramcWriteLeveling(PI) end<-----
1861 20:12:07.001637
1862 20:12:07.001733 ==
1863 20:12:07.004960 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 20:12:07.007734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 20:12:07.007822 ==
1866 20:12:07.011020 [Gating] SW mode calibration
1867 20:12:07.017791 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 20:12:07.024040 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 20:12:07.027761 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1870 20:12:07.030939 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1871 20:12:07.037619 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 20:12:07.040655 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 20:12:07.044167 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 20:12:07.050904 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 20:12:07.054111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 20:12:07.057406 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 20:12:07.063612 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 20:12:07.066951 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 20:12:07.070454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 20:12:07.077073 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 20:12:07.080137 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 20:12:07.083476 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 20:12:07.090215 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 20:12:07.093346 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 20:12:07.096638 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1886 20:12:07.103302 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1887 20:12:07.107132 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1888 20:12:07.110028 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 20:12:07.116727 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 20:12:07.119933 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 20:12:07.123208 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 20:12:07.129847 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 20:12:07.133219 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 20:12:07.136765 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1895 20:12:07.143247 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1896 20:12:07.146702 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 20:12:07.150363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 20:12:07.157179 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 20:12:07.160271 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 20:12:07.163204 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 20:12:07.170539 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1902 20:12:07.173310 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
1903 20:12:07.177057 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1904 20:12:07.183301 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 20:12:07.186604 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 20:12:07.189955 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 20:12:07.196835 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 20:12:07.200107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 20:12:07.203539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 20:12:07.206346 0 11 4 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
1911 20:12:07.212896 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1912 20:12:07.216301 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 20:12:07.219946 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 20:12:07.226263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 20:12:07.229516 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 20:12:07.232881 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 20:12:07.239802 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 20:12:07.242749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 20:12:07.246722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 20:12:07.253047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 20:12:07.256199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 20:12:07.259428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 20:12:07.265959 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 20:12:07.269373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 20:12:07.272659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 20:12:07.279447 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 20:12:07.282906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 20:12:07.285843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 20:12:07.292866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 20:12:07.296110 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 20:12:07.299325 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 20:12:07.306130 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 20:12:07.309341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1934 20:12:07.312401 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 20:12:07.315867 Total UI for P1: 0, mck2ui 16
1936 20:12:07.319339 best dqsien dly found for B0: ( 0, 14, 0)
1937 20:12:07.322467 Total UI for P1: 0, mck2ui 16
1938 20:12:07.326032 best dqsien dly found for B1: ( 0, 14, 2)
1939 20:12:07.329211 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1940 20:12:07.332248 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1941 20:12:07.332331
1942 20:12:07.335763 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1943 20:12:07.342581 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1944 20:12:07.342666 [Gating] SW calibration Done
1945 20:12:07.346075 ==
1946 20:12:07.346172 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 20:12:07.352485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 20:12:07.352593 ==
1949 20:12:07.352696 RX Vref Scan: 0
1950 20:12:07.352787
1951 20:12:07.355816 RX Vref 0 -> 0, step: 1
1952 20:12:07.355891
1953 20:12:07.359190 RX Delay -130 -> 252, step: 16
1954 20:12:07.362586 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1955 20:12:07.365683 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1956 20:12:07.368911 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1957 20:12:07.375589 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1958 20:12:07.378901 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1959 20:12:07.382208 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1960 20:12:07.385963 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1961 20:12:07.389231 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1962 20:12:07.396008 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1963 20:12:07.398758 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1964 20:12:07.402129 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1965 20:12:07.405376 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1966 20:12:07.408735 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1967 20:12:07.415575 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1968 20:12:07.418978 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1969 20:12:07.422145 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1970 20:12:07.422272 ==
1971 20:12:07.425401 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 20:12:07.428922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 20:12:07.432400 ==
1974 20:12:07.432527 DQS Delay:
1975 20:12:07.432642 DQS0 = 0, DQS1 = 0
1976 20:12:07.435181 DQM Delay:
1977 20:12:07.435306 DQM0 = 84, DQM1 = 82
1978 20:12:07.438965 DQ Delay:
1979 20:12:07.439071 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1980 20:12:07.442518 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1981 20:12:07.445214 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1982 20:12:07.448904 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1983 20:12:07.448994
1984 20:12:07.452359
1985 20:12:07.452442 ==
1986 20:12:07.455122 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 20:12:07.458817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 20:12:07.458927 ==
1989 20:12:07.459027
1990 20:12:07.459126
1991 20:12:07.462751 TX Vref Scan disable
1992 20:12:07.462868 == TX Byte 0 ==
1993 20:12:07.468454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1994 20:12:07.471865 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1995 20:12:07.471955 == TX Byte 1 ==
1996 20:12:07.478984 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 20:12:07.482148 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 20:12:07.482235 ==
1999 20:12:07.485524 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 20:12:07.488685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 20:12:07.488784 ==
2002 20:12:07.501859 TX Vref=22, minBit 1, minWin=27, winSum=443
2003 20:12:07.505245 TX Vref=24, minBit 1, minWin=27, winSum=445
2004 20:12:07.508988 TX Vref=26, minBit 2, minWin=27, winSum=451
2005 20:12:07.512247 TX Vref=28, minBit 3, minWin=27, winSum=453
2006 20:12:07.515596 TX Vref=30, minBit 2, minWin=27, winSum=454
2007 20:12:07.518989 TX Vref=32, minBit 0, minWin=27, winSum=448
2008 20:12:07.525309 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
2009 20:12:07.525426
2010 20:12:07.528601 Final TX Range 1 Vref 30
2011 20:12:07.528677
2012 20:12:07.528740 ==
2013 20:12:07.532005 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 20:12:07.535570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 20:12:07.535673 ==
2016 20:12:07.538790
2017 20:12:07.538897
2018 20:12:07.539010 TX Vref Scan disable
2019 20:12:07.541674 == TX Byte 0 ==
2020 20:12:07.545364 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2021 20:12:07.551867 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2022 20:12:07.551968 == TX Byte 1 ==
2023 20:12:07.555152 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 20:12:07.561880 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 20:12:07.561955
2026 20:12:07.562017 [DATLAT]
2027 20:12:07.562075 Freq=800, CH1 RK1
2028 20:12:07.562132
2029 20:12:07.565278 DATLAT Default: 0xa
2030 20:12:07.565373 0, 0xFFFF, sum = 0
2031 20:12:07.568481 1, 0xFFFF, sum = 0
2032 20:12:07.568553 2, 0xFFFF, sum = 0
2033 20:12:07.571907 3, 0xFFFF, sum = 0
2034 20:12:07.575128 4, 0xFFFF, sum = 0
2035 20:12:07.575206 5, 0xFFFF, sum = 0
2036 20:12:07.578575 6, 0xFFFF, sum = 0
2037 20:12:07.578648 7, 0xFFFF, sum = 0
2038 20:12:07.581831 8, 0xFFFF, sum = 0
2039 20:12:07.581905 9, 0x0, sum = 1
2040 20:12:07.581967 10, 0x0, sum = 2
2041 20:12:07.585026 11, 0x0, sum = 3
2042 20:12:07.585095 12, 0x0, sum = 4
2043 20:12:07.588356 best_step = 10
2044 20:12:07.588436
2045 20:12:07.588500 ==
2046 20:12:07.591771 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 20:12:07.595528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 20:12:07.595610 ==
2049 20:12:07.598236 RX Vref Scan: 0
2050 20:12:07.598316
2051 20:12:07.598379 RX Vref 0 -> 0, step: 1
2052 20:12:07.598439
2053 20:12:07.601887 RX Delay -95 -> 252, step: 8
2054 20:12:07.608431 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2055 20:12:07.611755 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2056 20:12:07.615016 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2057 20:12:07.618886 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2058 20:12:07.622257 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2059 20:12:07.628516 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2060 20:12:07.631979 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2061 20:12:07.635284 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2062 20:12:07.638648 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2063 20:12:07.641821 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2064 20:12:07.648416 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2065 20:12:07.652041 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2066 20:12:07.655000 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2067 20:12:07.658626 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2068 20:12:07.665335 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2069 20:12:07.668175 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2070 20:12:07.668248 ==
2071 20:12:07.671681 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 20:12:07.674838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 20:12:07.674912 ==
2074 20:12:07.674972 DQS Delay:
2075 20:12:07.678268 DQS0 = 0, DQS1 = 0
2076 20:12:07.678343 DQM Delay:
2077 20:12:07.681520 DQM0 = 86, DQM1 = 83
2078 20:12:07.681592 DQ Delay:
2079 20:12:07.684539 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2080 20:12:07.687955 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2081 20:12:07.691706 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =76
2082 20:12:07.694793 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =88
2083 20:12:07.694885
2084 20:12:07.694947
2085 20:12:07.704591 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2086 20:12:07.704669 CH1 RK1: MR19=606, MR18=1C37
2087 20:12:07.711052 CH1_RK1: MR19=0x606, MR18=0x1C37, DQSOSC=395, MR23=63, INC=94, DEC=63
2088 20:12:07.714343 [RxdqsGatingPostProcess] freq 800
2089 20:12:07.721354 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 20:12:07.724655 Pre-setting of DQS Precalculation
2091 20:12:07.727854 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 20:12:07.734682 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 20:12:07.744328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 20:12:07.744407
2095 20:12:07.744478
2096 20:12:07.748096 [Calibration Summary] 1600 Mbps
2097 20:12:07.748167 CH 0, Rank 0
2098 20:12:07.751344 SW Impedance : PASS
2099 20:12:07.751439 DUTY Scan : NO K
2100 20:12:07.754366 ZQ Calibration : PASS
2101 20:12:07.757373 Jitter Meter : NO K
2102 20:12:07.757469 CBT Training : PASS
2103 20:12:07.761076 Write leveling : PASS
2104 20:12:07.763996 RX DQS gating : PASS
2105 20:12:07.764077 RX DQ/DQS(RDDQC) : PASS
2106 20:12:07.767288 TX DQ/DQS : PASS
2107 20:12:07.767430 RX DATLAT : PASS
2108 20:12:07.771186 RX DQ/DQS(Engine): PASS
2109 20:12:07.774595 TX OE : NO K
2110 20:12:07.774677 All Pass.
2111 20:12:07.774741
2112 20:12:07.774799 CH 0, Rank 1
2113 20:12:07.777575 SW Impedance : PASS
2114 20:12:07.781336 DUTY Scan : NO K
2115 20:12:07.781417 ZQ Calibration : PASS
2116 20:12:07.784557 Jitter Meter : NO K
2117 20:12:07.787814 CBT Training : PASS
2118 20:12:07.787895 Write leveling : PASS
2119 20:12:07.790843 RX DQS gating : PASS
2120 20:12:07.794634 RX DQ/DQS(RDDQC) : PASS
2121 20:12:07.794742 TX DQ/DQS : PASS
2122 20:12:07.797398 RX DATLAT : PASS
2123 20:12:07.801021 RX DQ/DQS(Engine): PASS
2124 20:12:07.801128 TX OE : NO K
2125 20:12:07.804082 All Pass.
2126 20:12:07.804163
2127 20:12:07.804239 CH 1, Rank 0
2128 20:12:07.807590 SW Impedance : PASS
2129 20:12:07.807720 DUTY Scan : NO K
2130 20:12:07.810834 ZQ Calibration : PASS
2131 20:12:07.814102 Jitter Meter : NO K
2132 20:12:07.814186 CBT Training : PASS
2133 20:12:07.817368 Write leveling : PASS
2134 20:12:07.820698 RX DQS gating : PASS
2135 20:12:07.820779 RX DQ/DQS(RDDQC) : PASS
2136 20:12:07.824039 TX DQ/DQS : PASS
2137 20:12:07.824153 RX DATLAT : PASS
2138 20:12:07.827274 RX DQ/DQS(Engine): PASS
2139 20:12:07.830382 TX OE : NO K
2140 20:12:07.830463 All Pass.
2141 20:12:07.830532
2142 20:12:07.830591 CH 1, Rank 1
2143 20:12:07.833545 SW Impedance : PASS
2144 20:12:07.836796 DUTY Scan : NO K
2145 20:12:07.836872 ZQ Calibration : PASS
2146 20:12:07.840468 Jitter Meter : NO K
2147 20:12:07.843270 CBT Training : PASS
2148 20:12:07.843379 Write leveling : PASS
2149 20:12:07.846987 RX DQS gating : PASS
2150 20:12:07.850331 RX DQ/DQS(RDDQC) : PASS
2151 20:12:07.850409 TX DQ/DQS : PASS
2152 20:12:07.853500 RX DATLAT : PASS
2153 20:12:07.856710 RX DQ/DQS(Engine): PASS
2154 20:12:07.856831 TX OE : NO K
2155 20:12:07.860236 All Pass.
2156 20:12:07.860346
2157 20:12:07.860439 DramC Write-DBI off
2158 20:12:07.863175 PER_BANK_REFRESH: Hybrid Mode
2159 20:12:07.863278 TX_TRACKING: ON
2160 20:12:07.869826 [GetDramInforAfterCalByMRR] Vendor 6.
2161 20:12:07.873214 [GetDramInforAfterCalByMRR] Revision 606.
2162 20:12:07.876400 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 20:12:07.876522 MR0 0x3b3b
2164 20:12:07.876631 MR8 0x5151
2165 20:12:07.883025 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 20:12:07.883150
2167 20:12:07.883263 MR0 0x3b3b
2168 20:12:07.883396 MR8 0x5151
2169 20:12:07.886320 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 20:12:07.886439
2171 20:12:07.896581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 20:12:07.899565 [FAST_K] Save calibration result to emmc
2173 20:12:07.902899 [FAST_K] Save calibration result to emmc
2174 20:12:07.906427 dram_init: config_dvfs: 1
2175 20:12:07.909415 dramc_set_vcore_voltage set vcore to 662500
2176 20:12:07.912634 Read voltage for 1200, 2
2177 20:12:07.912753 Vio18 = 0
2178 20:12:07.916209 Vcore = 662500
2179 20:12:07.916291 Vdram = 0
2180 20:12:07.916356 Vddq = 0
2181 20:12:07.916415 Vmddr = 0
2182 20:12:07.922928 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 20:12:07.925940 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 20:12:07.929462 MEM_TYPE=3, freq_sel=15
2185 20:12:07.932630 sv_algorithm_assistance_LP4_1600
2186 20:12:07.935618 ============ PULL DRAM RESETB DOWN ============
2187 20:12:07.942520 ========== PULL DRAM RESETB DOWN end =========
2188 20:12:07.945864 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 20:12:07.949528 ===================================
2190 20:12:07.953015 LPDDR4 DRAM CONFIGURATION
2191 20:12:07.955914 ===================================
2192 20:12:07.956010 EX_ROW_EN[0] = 0x0
2193 20:12:07.959335 EX_ROW_EN[1] = 0x0
2194 20:12:07.959458 LP4Y_EN = 0x0
2195 20:12:07.962723 WORK_FSP = 0x0
2196 20:12:07.962805 WL = 0x4
2197 20:12:07.965933 RL = 0x4
2198 20:12:07.966065 BL = 0x2
2199 20:12:07.968967 RPST = 0x0
2200 20:12:07.972284 RD_PRE = 0x0
2201 20:12:07.972380 WR_PRE = 0x1
2202 20:12:07.975630 WR_PST = 0x0
2203 20:12:07.975754 DBI_WR = 0x0
2204 20:12:07.978716 DBI_RD = 0x0
2205 20:12:07.978837 OTF = 0x1
2206 20:12:07.982121 ===================================
2207 20:12:07.985424 ===================================
2208 20:12:07.988759 ANA top config
2209 20:12:07.992009 ===================================
2210 20:12:07.992091 DLL_ASYNC_EN = 0
2211 20:12:07.995349 ALL_SLAVE_EN = 0
2212 20:12:07.998515 NEW_RANK_MODE = 1
2213 20:12:08.002279 DLL_IDLE_MODE = 1
2214 20:12:08.002379 LP45_APHY_COMB_EN = 1
2215 20:12:08.005582 TX_ODT_DIS = 1
2216 20:12:08.009011 NEW_8X_MODE = 1
2217 20:12:08.012209 ===================================
2218 20:12:08.015338 ===================================
2219 20:12:08.018939 data_rate = 2400
2220 20:12:08.021995 CKR = 1
2221 20:12:08.025439 DQ_P2S_RATIO = 8
2222 20:12:08.028747 ===================================
2223 20:12:08.028849 CA_P2S_RATIO = 8
2224 20:12:08.031880 DQ_CA_OPEN = 0
2225 20:12:08.035104 DQ_SEMI_OPEN = 0
2226 20:12:08.038393 CA_SEMI_OPEN = 0
2227 20:12:08.041863 CA_FULL_RATE = 0
2228 20:12:08.041975 DQ_CKDIV4_EN = 0
2229 20:12:08.045470 CA_CKDIV4_EN = 0
2230 20:12:08.048282 CA_PREDIV_EN = 0
2231 20:12:08.051947 PH8_DLY = 17
2232 20:12:08.055512 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 20:12:08.058723 DQ_AAMCK_DIV = 4
2234 20:12:08.061676 CA_AAMCK_DIV = 4
2235 20:12:08.061786 CA_ADMCK_DIV = 4
2236 20:12:08.064841 DQ_TRACK_CA_EN = 0
2237 20:12:08.068356 CA_PICK = 1200
2238 20:12:08.071817 CA_MCKIO = 1200
2239 20:12:08.074904 MCKIO_SEMI = 0
2240 20:12:08.078420 PLL_FREQ = 2366
2241 20:12:08.081923 DQ_UI_PI_RATIO = 32
2242 20:12:08.082006 CA_UI_PI_RATIO = 0
2243 20:12:08.084949 ===================================
2244 20:12:08.088799 ===================================
2245 20:12:08.091836 memory_type:LPDDR4
2246 20:12:08.095167 GP_NUM : 10
2247 20:12:08.095249 SRAM_EN : 1
2248 20:12:08.098644 MD32_EN : 0
2249 20:12:08.101936 ===================================
2250 20:12:08.105139 [ANA_INIT] >>>>>>>>>>>>>>
2251 20:12:08.108275 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 20:12:08.111643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 20:12:08.114977 ===================================
2254 20:12:08.115060 data_rate = 2400,PCW = 0X5b00
2255 20:12:08.118336 ===================================
2256 20:12:08.121402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 20:12:08.128568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 20:12:08.134955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 20:12:08.138068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 20:12:08.141228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 20:12:08.144751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 20:12:08.148062 [ANA_INIT] flow start
2263 20:12:08.148173 [ANA_INIT] PLL >>>>>>>>
2264 20:12:08.151696 [ANA_INIT] PLL <<<<<<<<
2265 20:12:08.154805 [ANA_INIT] MIDPI >>>>>>>>
2266 20:12:08.157817 [ANA_INIT] MIDPI <<<<<<<<
2267 20:12:08.157927 [ANA_INIT] DLL >>>>>>>>
2268 20:12:08.161433 [ANA_INIT] DLL <<<<<<<<
2269 20:12:08.164440 [ANA_INIT] flow end
2270 20:12:08.168241 ============ LP4 DIFF to SE enter ============
2271 20:12:08.171102 ============ LP4 DIFF to SE exit ============
2272 20:12:08.174509 [ANA_INIT] <<<<<<<<<<<<<
2273 20:12:08.177770 [Flow] Enable top DCM control >>>>>
2274 20:12:08.180968 [Flow] Enable top DCM control <<<<<
2275 20:12:08.184040 Enable DLL master slave shuffle
2276 20:12:08.187521 ==============================================================
2277 20:12:08.191095 Gating Mode config
2278 20:12:08.197429 ==============================================================
2279 20:12:08.197542 Config description:
2280 20:12:08.207366 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 20:12:08.214349 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 20:12:08.217588 SELPH_MODE 0: By rank 1: By Phase
2283 20:12:08.224013 ==============================================================
2284 20:12:08.227453 GAT_TRACK_EN = 1
2285 20:12:08.230839 RX_GATING_MODE = 2
2286 20:12:08.234044 RX_GATING_TRACK_MODE = 2
2287 20:12:08.237329 SELPH_MODE = 1
2288 20:12:08.240647 PICG_EARLY_EN = 1
2289 20:12:08.243755 VALID_LAT_VALUE = 1
2290 20:12:08.247130 ==============================================================
2291 20:12:08.250517 Enter into Gating configuration >>>>
2292 20:12:08.253866 Exit from Gating configuration <<<<
2293 20:12:08.257162 Enter into DVFS_PRE_config >>>>>
2294 20:12:08.270454 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 20:12:08.270546 Exit from DVFS_PRE_config <<<<<
2296 20:12:08.273777 Enter into PICG configuration >>>>
2297 20:12:08.277337 Exit from PICG configuration <<<<
2298 20:12:08.280673 [RX_INPUT] configuration >>>>>
2299 20:12:08.283808 [RX_INPUT] configuration <<<<<
2300 20:12:08.290319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 20:12:08.293782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 20:12:08.300752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 20:12:08.307014 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 20:12:08.313750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 20:12:08.320478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 20:12:08.323668 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 20:12:08.327074 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 20:12:08.330000 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 20:12:08.336763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 20:12:08.340493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 20:12:08.343588 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 20:12:08.346707 ===================================
2313 20:12:08.350516 LPDDR4 DRAM CONFIGURATION
2314 20:12:08.353222 ===================================
2315 20:12:08.356529 EX_ROW_EN[0] = 0x0
2316 20:12:08.356613 EX_ROW_EN[1] = 0x0
2317 20:12:08.359823 LP4Y_EN = 0x0
2318 20:12:08.359906 WORK_FSP = 0x0
2319 20:12:08.363021 WL = 0x4
2320 20:12:08.363105 RL = 0x4
2321 20:12:08.366917 BL = 0x2
2322 20:12:08.366997 RPST = 0x0
2323 20:12:08.369735 RD_PRE = 0x0
2324 20:12:08.369810 WR_PRE = 0x1
2325 20:12:08.373305 WR_PST = 0x0
2326 20:12:08.373416 DBI_WR = 0x0
2327 20:12:08.376566 DBI_RD = 0x0
2328 20:12:08.376646 OTF = 0x1
2329 20:12:08.379745 ===================================
2330 20:12:08.386482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 20:12:08.389371 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 20:12:08.392705 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 20:12:08.395978 ===================================
2334 20:12:08.399328 LPDDR4 DRAM CONFIGURATION
2335 20:12:08.402946 ===================================
2336 20:12:08.406530 EX_ROW_EN[0] = 0x10
2337 20:12:08.406614 EX_ROW_EN[1] = 0x0
2338 20:12:08.409263 LP4Y_EN = 0x0
2339 20:12:08.409347 WORK_FSP = 0x0
2340 20:12:08.412734 WL = 0x4
2341 20:12:08.412818 RL = 0x4
2342 20:12:08.416406 BL = 0x2
2343 20:12:08.416490 RPST = 0x0
2344 20:12:08.419388 RD_PRE = 0x0
2345 20:12:08.419472 WR_PRE = 0x1
2346 20:12:08.422620 WR_PST = 0x0
2347 20:12:08.422703 DBI_WR = 0x0
2348 20:12:08.426368 DBI_RD = 0x0
2349 20:12:08.426451 OTF = 0x1
2350 20:12:08.429086 ===================================
2351 20:12:08.436064 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 20:12:08.436149 ==
2353 20:12:08.439127 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 20:12:08.446121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 20:12:08.446203 ==
2356 20:12:08.446268 [Duty_Offset_Calibration]
2357 20:12:08.449096 B0:2 B1:0 CA:4
2358 20:12:08.449178
2359 20:12:08.452310 [DutyScan_Calibration_Flow] k_type=0
2360 20:12:08.460662
2361 20:12:08.460746 ==CLK 0==
2362 20:12:08.463917 Final CLK duty delay cell = -4
2363 20:12:08.467000 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2364 20:12:08.470316 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2365 20:12:08.473989 [-4] AVG Duty = 4937%(X100)
2366 20:12:08.474087
2367 20:12:08.477100 CH0 CLK Duty spec in!! Max-Min= 187%
2368 20:12:08.480464 [DutyScan_Calibration_Flow] ====Done====
2369 20:12:08.480555
2370 20:12:08.483748 [DutyScan_Calibration_Flow] k_type=1
2371 20:12:08.499983
2372 20:12:08.500066 ==DQS 0 ==
2373 20:12:08.503341 Final DQS duty delay cell = 0
2374 20:12:08.506593 [0] MAX Duty = 5156%(X100), DQS PI = 18
2375 20:12:08.509967 [0] MIN Duty = 5093%(X100), DQS PI = 2
2376 20:12:08.510048 [0] AVG Duty = 5124%(X100)
2377 20:12:08.513184
2378 20:12:08.513265 ==DQS 1 ==
2379 20:12:08.516841 Final DQS duty delay cell = 0
2380 20:12:08.520047 [0] MAX Duty = 5093%(X100), DQS PI = 6
2381 20:12:08.523317 [0] MIN Duty = 5000%(X100), DQS PI = 0
2382 20:12:08.523420 [0] AVG Duty = 5046%(X100)
2383 20:12:08.526476
2384 20:12:08.530297 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2385 20:12:08.530378
2386 20:12:08.533625 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2387 20:12:08.536963 [DutyScan_Calibration_Flow] ====Done====
2388 20:12:08.537044
2389 20:12:08.539944 [DutyScan_Calibration_Flow] k_type=3
2390 20:12:08.556504
2391 20:12:08.556627 ==DQM 0 ==
2392 20:12:08.559510 Final DQM duty delay cell = 0
2393 20:12:08.563013 [0] MAX Duty = 5125%(X100), DQS PI = 20
2394 20:12:08.566149 [0] MIN Duty = 4844%(X100), DQS PI = 44
2395 20:12:08.569351 [0] AVG Duty = 4984%(X100)
2396 20:12:08.569470
2397 20:12:08.569582 ==DQM 1 ==
2398 20:12:08.572627 Final DQM duty delay cell = 0
2399 20:12:08.576969 [0] MAX Duty = 5000%(X100), DQS PI = 8
2400 20:12:08.579614 [0] MIN Duty = 4875%(X100), DQS PI = 18
2401 20:12:08.582933 [0] AVG Duty = 4937%(X100)
2402 20:12:08.583054
2403 20:12:08.586290 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2404 20:12:08.586416
2405 20:12:08.589463 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2406 20:12:08.592902 [DutyScan_Calibration_Flow] ====Done====
2407 20:12:08.593022
2408 20:12:08.596063 [DutyScan_Calibration_Flow] k_type=2
2409 20:12:08.611857
2410 20:12:08.611973 ==DQ 0 ==
2411 20:12:08.615421 Final DQ duty delay cell = -4
2412 20:12:08.618782 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2413 20:12:08.621693 [-4] MIN Duty = 4844%(X100), DQS PI = 52
2414 20:12:08.625086 [-4] AVG Duty = 4922%(X100)
2415 20:12:08.625209
2416 20:12:08.625322 ==DQ 1 ==
2417 20:12:08.628749 Final DQ duty delay cell = 0
2418 20:12:08.632110 [0] MAX Duty = 5156%(X100), DQS PI = 4
2419 20:12:08.635011 [0] MIN Duty = 4938%(X100), DQS PI = 14
2420 20:12:08.638739 [0] AVG Duty = 5047%(X100)
2421 20:12:08.638858
2422 20:12:08.641952 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2423 20:12:08.642073
2424 20:12:08.645061 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2425 20:12:08.648418 [DutyScan_Calibration_Flow] ====Done====
2426 20:12:08.648540 ==
2427 20:12:08.651961 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 20:12:08.655090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 20:12:08.655212 ==
2430 20:12:08.658642 [Duty_Offset_Calibration]
2431 20:12:08.658763 B0:0 B1:-1 CA:3
2432 20:12:08.658874
2433 20:12:08.661597 [DutyScan_Calibration_Flow] k_type=0
2434 20:12:08.671453
2435 20:12:08.671574 ==CLK 0==
2436 20:12:08.674932 Final CLK duty delay cell = -4
2437 20:12:08.678220 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2438 20:12:08.681521 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2439 20:12:08.684703 [-4] AVG Duty = 4938%(X100)
2440 20:12:08.684787
2441 20:12:08.688623 CH1 CLK Duty spec in!! Max-Min= 124%
2442 20:12:08.691713 [DutyScan_Calibration_Flow] ====Done====
2443 20:12:08.691796
2444 20:12:08.695002 [DutyScan_Calibration_Flow] k_type=1
2445 20:12:08.710242
2446 20:12:08.710367 ==DQS 0 ==
2447 20:12:08.713486 Final DQS duty delay cell = 0
2448 20:12:08.716846 [0] MAX Duty = 5156%(X100), DQS PI = 18
2449 20:12:08.720081 [0] MIN Duty = 4907%(X100), DQS PI = 38
2450 20:12:08.723357 [0] AVG Duty = 5031%(X100)
2451 20:12:08.723510
2452 20:12:08.723622 ==DQS 1 ==
2453 20:12:08.727180 Final DQS duty delay cell = -4
2454 20:12:08.730240 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2455 20:12:08.733494 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2456 20:12:08.736924 [-4] AVG Duty = 4953%(X100)
2457 20:12:08.737059
2458 20:12:08.739953 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2459 20:12:08.740078
2460 20:12:08.743507 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2461 20:12:08.746845 [DutyScan_Calibration_Flow] ====Done====
2462 20:12:08.746965
2463 20:12:08.749929 [DutyScan_Calibration_Flow] k_type=3
2464 20:12:08.767371
2465 20:12:08.767523 ==DQM 0 ==
2466 20:12:08.770578 Final DQM duty delay cell = 0
2467 20:12:08.774082 [0] MAX Duty = 5031%(X100), DQS PI = 26
2468 20:12:08.777791 [0] MIN Duty = 4813%(X100), DQS PI = 38
2469 20:12:08.777916 [0] AVG Duty = 4922%(X100)
2470 20:12:08.780558
2471 20:12:08.780680 ==DQM 1 ==
2472 20:12:08.783797 Final DQM duty delay cell = 0
2473 20:12:08.787023 [0] MAX Duty = 5000%(X100), DQS PI = 34
2474 20:12:08.790586 [0] MIN Duty = 4844%(X100), DQS PI = 0
2475 20:12:08.790710 [0] AVG Duty = 4922%(X100)
2476 20:12:08.794082
2477 20:12:08.797018 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2478 20:12:08.797143
2479 20:12:08.800608 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2480 20:12:08.803670 [DutyScan_Calibration_Flow] ====Done====
2481 20:12:08.803791
2482 20:12:08.806790 [DutyScan_Calibration_Flow] k_type=2
2483 20:12:08.822803
2484 20:12:08.822938 ==DQ 0 ==
2485 20:12:08.826144 Final DQ duty delay cell = -4
2486 20:12:08.829516 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2487 20:12:08.833055 [-4] MIN Duty = 4876%(X100), DQS PI = 34
2488 20:12:08.836105 [-4] AVG Duty = 4938%(X100)
2489 20:12:08.836258
2490 20:12:08.836365 ==DQ 1 ==
2491 20:12:08.839673 Final DQ duty delay cell = 0
2492 20:12:08.842688 [0] MAX Duty = 5031%(X100), DQS PI = 26
2493 20:12:08.846106 [0] MIN Duty = 4844%(X100), DQS PI = 62
2494 20:12:08.849444 [0] AVG Duty = 4937%(X100)
2495 20:12:08.849550
2496 20:12:08.852652 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 20:12:08.852753
2498 20:12:08.856467 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2499 20:12:08.859272 [DutyScan_Calibration_Flow] ====Done====
2500 20:12:08.862907 nWR fixed to 30
2501 20:12:08.863012 [ModeRegInit_LP4] CH0 RK0
2502 20:12:08.866559 [ModeRegInit_LP4] CH0 RK1
2503 20:12:08.869339 [ModeRegInit_LP4] CH1 RK0
2504 20:12:08.873035 [ModeRegInit_LP4] CH1 RK1
2505 20:12:08.873115 match AC timing 7
2506 20:12:08.879582 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 20:12:08.882615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 20:12:08.886162 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 20:12:08.892358 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 20:12:08.895893 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 20:12:08.896004 ==
2512 20:12:08.899257 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 20:12:08.902616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 20:12:08.902716 ==
2515 20:12:08.909053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 20:12:08.916079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 20:12:08.923259 [CA 0] Center 39 (9~70) winsize 62
2518 20:12:08.926276 [CA 1] Center 39 (9~69) winsize 61
2519 20:12:08.929813 [CA 2] Center 35 (5~66) winsize 62
2520 20:12:08.932986 [CA 3] Center 35 (5~66) winsize 62
2521 20:12:08.936298 [CA 4] Center 33 (3~64) winsize 62
2522 20:12:08.939593 [CA 5] Center 33 (3~64) winsize 62
2523 20:12:08.939679
2524 20:12:08.942886 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 20:12:08.943008
2526 20:12:08.946390 [CATrainingPosCal] consider 1 rank data
2527 20:12:08.949450 u2DelayCellTimex100 = 270/100 ps
2528 20:12:08.953018 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 20:12:08.959469 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2530 20:12:08.962670 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 20:12:08.966226 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 20:12:08.969350 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2533 20:12:08.972948 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2534 20:12:08.973073
2535 20:12:08.976253 CA PerBit enable=1, Macro0, CA PI delay=33
2536 20:12:08.976381
2537 20:12:08.979242 [CBTSetCACLKResult] CA Dly = 33
2538 20:12:08.979368 CS Dly: 7 (0~38)
2539 20:12:08.982543 ==
2540 20:12:08.985941 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 20:12:08.989543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 20:12:08.989667 ==
2543 20:12:08.992841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 20:12:08.999194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 20:12:09.008941 [CA 0] Center 39 (9~70) winsize 62
2546 20:12:09.012475 [CA 1] Center 39 (9~70) winsize 62
2547 20:12:09.015572 [CA 2] Center 35 (5~66) winsize 62
2548 20:12:09.018773 [CA 3] Center 35 (5~66) winsize 62
2549 20:12:09.022154 [CA 4] Center 34 (4~65) winsize 62
2550 20:12:09.025642 [CA 5] Center 33 (3~64) winsize 62
2551 20:12:09.025772
2552 20:12:09.029222 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2553 20:12:09.029348
2554 20:12:09.032217 [CATrainingPosCal] consider 2 rank data
2555 20:12:09.035399 u2DelayCellTimex100 = 270/100 ps
2556 20:12:09.038768 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 20:12:09.045407 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2558 20:12:09.048926 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2559 20:12:09.051806 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 20:12:09.055082 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2561 20:12:09.058477 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2562 20:12:09.058605
2563 20:12:09.061947 CA PerBit enable=1, Macro0, CA PI delay=33
2564 20:12:09.062069
2565 20:12:09.065278 [CBTSetCACLKResult] CA Dly = 33
2566 20:12:09.065402 CS Dly: 8 (0~41)
2567 20:12:09.068390
2568 20:12:09.071793 ----->DramcWriteLeveling(PI) begin...
2569 20:12:09.071881 ==
2570 20:12:09.074968 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 20:12:09.078454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 20:12:09.078540 ==
2573 20:12:09.081660 Write leveling (Byte 0): 32 => 32
2574 20:12:09.084844 Write leveling (Byte 1): 25 => 25
2575 20:12:09.088422 DramcWriteLeveling(PI) end<-----
2576 20:12:09.088547
2577 20:12:09.088663 ==
2578 20:12:09.091387 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 20:12:09.094922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 20:12:09.095028 ==
2581 20:12:09.098267 [Gating] SW mode calibration
2582 20:12:09.104945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 20:12:09.111343 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 20:12:09.114562 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2585 20:12:09.118081 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2586 20:12:09.124705 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 20:12:09.128080 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 20:12:09.131322 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 20:12:09.138144 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 20:12:09.141173 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2591 20:12:09.144563 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2592 20:12:09.151063 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2593 20:12:09.154590 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2594 20:12:09.157661 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 20:12:09.164437 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 20:12:09.167779 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 20:12:09.170799 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 20:12:09.177488 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2599 20:12:09.181102 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2600 20:12:09.183959 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2601 20:12:09.190889 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2602 20:12:09.193827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 20:12:09.197522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 20:12:09.204052 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 20:12:09.207603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 20:12:09.211146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2607 20:12:09.217540 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 20:12:09.220754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 20:12:09.224157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 20:12:09.230848 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 20:12:09.234099 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 20:12:09.237052 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 20:12:09.244016 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 20:12:09.247007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 20:12:09.250350 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 20:12:09.256779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 20:12:09.260141 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 20:12:09.263959 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 20:12:09.267354 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 20:12:09.273688 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 20:12:09.276690 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 20:12:09.280210 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 20:12:09.287148 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 20:12:09.290133 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 20:12:09.293433 Total UI for P1: 0, mck2ui 16
2626 20:12:09.297235 best dqsien dly found for B0: ( 1, 3, 26)
2627 20:12:09.300504 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 20:12:09.303609 Total UI for P1: 0, mck2ui 16
2629 20:12:09.306771 best dqsien dly found for B1: ( 1, 4, 0)
2630 20:12:09.310161 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 20:12:09.313596 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 20:12:09.313677
2633 20:12:09.319878 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 20:12:09.323735 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 20:12:09.326763 [Gating] SW calibration Done
2636 20:12:09.326845 ==
2637 20:12:09.330218 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 20:12:09.333350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 20:12:09.333432 ==
2640 20:12:09.333495 RX Vref Scan: 0
2641 20:12:09.333554
2642 20:12:09.336876 RX Vref 0 -> 0, step: 1
2643 20:12:09.336957
2644 20:12:09.340427 RX Delay -40 -> 252, step: 8
2645 20:12:09.342978 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2646 20:12:09.346432 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2647 20:12:09.353049 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2648 20:12:09.356225 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2649 20:12:09.359557 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 20:12:09.363156 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2651 20:12:09.366557 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2652 20:12:09.373139 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2653 20:12:09.376275 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2654 20:12:09.379638 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2655 20:12:09.383207 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2656 20:12:09.386014 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2657 20:12:09.393019 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 20:12:09.396319 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2659 20:12:09.399697 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2660 20:12:09.402762 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2661 20:12:09.402843 ==
2662 20:12:09.405882 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 20:12:09.413320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 20:12:09.413445 ==
2665 20:12:09.413557 DQS Delay:
2666 20:12:09.416028 DQS0 = 0, DQS1 = 0
2667 20:12:09.416188 DQM Delay:
2668 20:12:09.416305 DQM0 = 117, DQM1 = 107
2669 20:12:09.419415 DQ Delay:
2670 20:12:09.422612 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2671 20:12:09.425970 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2672 20:12:09.429260 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2673 20:12:09.432561 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2674 20:12:09.432680
2675 20:12:09.432791
2676 20:12:09.432895 ==
2677 20:12:09.435657 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 20:12:09.439117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 20:12:09.442422 ==
2680 20:12:09.442544
2681 20:12:09.442656
2682 20:12:09.442761 TX Vref Scan disable
2683 20:12:09.445933 == TX Byte 0 ==
2684 20:12:09.449108 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2685 20:12:09.452325 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2686 20:12:09.455711 == TX Byte 1 ==
2687 20:12:09.458954 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2688 20:12:09.462102 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2689 20:12:09.465376 ==
2690 20:12:09.468975 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 20:12:09.472293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 20:12:09.472414 ==
2693 20:12:09.483810 TX Vref=22, minBit 8, minWin=25, winSum=417
2694 20:12:09.487072 TX Vref=24, minBit 10, minWin=25, winSum=421
2695 20:12:09.490422 TX Vref=26, minBit 1, minWin=26, winSum=428
2696 20:12:09.493679 TX Vref=28, minBit 10, minWin=26, winSum=430
2697 20:12:09.497166 TX Vref=30, minBit 10, minWin=26, winSum=435
2698 20:12:09.503591 TX Vref=32, minBit 4, minWin=26, winSum=432
2699 20:12:09.506949 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2700 20:12:09.507076
2701 20:12:09.510343 Final TX Range 1 Vref 30
2702 20:12:09.510463
2703 20:12:09.510571 ==
2704 20:12:09.513680 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 20:12:09.517008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 20:12:09.520423 ==
2707 20:12:09.520545
2708 20:12:09.520655
2709 20:12:09.520764 TX Vref Scan disable
2710 20:12:09.523984 == TX Byte 0 ==
2711 20:12:09.527266 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2712 20:12:09.530840 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2713 20:12:09.534056 == TX Byte 1 ==
2714 20:12:09.537075 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2715 20:12:09.543849 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2716 20:12:09.543970
2717 20:12:09.544083 [DATLAT]
2718 20:12:09.544191 Freq=1200, CH0 RK0
2719 20:12:09.544307
2720 20:12:09.547089 DATLAT Default: 0xd
2721 20:12:09.547209 0, 0xFFFF, sum = 0
2722 20:12:09.550660 1, 0xFFFF, sum = 0
2723 20:12:09.554124 2, 0xFFFF, sum = 0
2724 20:12:09.554206 3, 0xFFFF, sum = 0
2725 20:12:09.557295 4, 0xFFFF, sum = 0
2726 20:12:09.557378 5, 0xFFFF, sum = 0
2727 20:12:09.560475 6, 0xFFFF, sum = 0
2728 20:12:09.560558 7, 0xFFFF, sum = 0
2729 20:12:09.564105 8, 0xFFFF, sum = 0
2730 20:12:09.564188 9, 0xFFFF, sum = 0
2731 20:12:09.567229 10, 0xFFFF, sum = 0
2732 20:12:09.567312 11, 0xFFFF, sum = 0
2733 20:12:09.570501 12, 0x0, sum = 1
2734 20:12:09.570583 13, 0x0, sum = 2
2735 20:12:09.574010 14, 0x0, sum = 3
2736 20:12:09.574092 15, 0x0, sum = 4
2737 20:12:09.576928 best_step = 13
2738 20:12:09.577010
2739 20:12:09.577073 ==
2740 20:12:09.580172 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 20:12:09.583691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 20:12:09.583774 ==
2743 20:12:09.583838 RX Vref Scan: 1
2744 20:12:09.586749
2745 20:12:09.586830 Set Vref Range= 32 -> 127
2746 20:12:09.586893
2747 20:12:09.590491 RX Vref 32 -> 127, step: 1
2748 20:12:09.590573
2749 20:12:09.593675 RX Delay -21 -> 252, step: 4
2750 20:12:09.593772
2751 20:12:09.597036 Set Vref, RX VrefLevel [Byte0]: 32
2752 20:12:09.600201 [Byte1]: 32
2753 20:12:09.600282
2754 20:12:09.603376 Set Vref, RX VrefLevel [Byte0]: 33
2755 20:12:09.606846 [Byte1]: 33
2756 20:12:09.610714
2757 20:12:09.610795 Set Vref, RX VrefLevel [Byte0]: 34
2758 20:12:09.614065 [Byte1]: 34
2759 20:12:09.618243
2760 20:12:09.618324 Set Vref, RX VrefLevel [Byte0]: 35
2761 20:12:09.621519 [Byte1]: 35
2762 20:12:09.626383
2763 20:12:09.626463 Set Vref, RX VrefLevel [Byte0]: 36
2764 20:12:09.629620 [Byte1]: 36
2765 20:12:09.634287
2766 20:12:09.634412 Set Vref, RX VrefLevel [Byte0]: 37
2767 20:12:09.637588 [Byte1]: 37
2768 20:12:09.642212
2769 20:12:09.642336 Set Vref, RX VrefLevel [Byte0]: 38
2770 20:12:09.645544 [Byte1]: 38
2771 20:12:09.650182
2772 20:12:09.650303 Set Vref, RX VrefLevel [Byte0]: 39
2773 20:12:09.653337 [Byte1]: 39
2774 20:12:09.657868
2775 20:12:09.657998 Set Vref, RX VrefLevel [Byte0]: 40
2776 20:12:09.661079 [Byte1]: 40
2777 20:12:09.666055
2778 20:12:09.666175 Set Vref, RX VrefLevel [Byte0]: 41
2779 20:12:09.669318 [Byte1]: 41
2780 20:12:09.673605
2781 20:12:09.673728 Set Vref, RX VrefLevel [Byte0]: 42
2782 20:12:09.677240 [Byte1]: 42
2783 20:12:09.681778
2784 20:12:09.681905 Set Vref, RX VrefLevel [Byte0]: 43
2785 20:12:09.685119 [Byte1]: 43
2786 20:12:09.689847
2787 20:12:09.689969 Set Vref, RX VrefLevel [Byte0]: 44
2788 20:12:09.693653 [Byte1]: 44
2789 20:12:09.697429
2790 20:12:09.697552 Set Vref, RX VrefLevel [Byte0]: 45
2791 20:12:09.700639 [Byte1]: 45
2792 20:12:09.705765
2793 20:12:09.705885 Set Vref, RX VrefLevel [Byte0]: 46
2794 20:12:09.708772 [Byte1]: 46
2795 20:12:09.713386
2796 20:12:09.713507 Set Vref, RX VrefLevel [Byte0]: 47
2797 20:12:09.716847 [Byte1]: 47
2798 20:12:09.721167
2799 20:12:09.721289 Set Vref, RX VrefLevel [Byte0]: 48
2800 20:12:09.724462 [Byte1]: 48
2801 20:12:09.729392
2802 20:12:09.729516 Set Vref, RX VrefLevel [Byte0]: 49
2803 20:12:09.732614 [Byte1]: 49
2804 20:12:09.736953
2805 20:12:09.737073 Set Vref, RX VrefLevel [Byte0]: 50
2806 20:12:09.740671 [Byte1]: 50
2807 20:12:09.745298
2808 20:12:09.745419 Set Vref, RX VrefLevel [Byte0]: 51
2809 20:12:09.748346 [Byte1]: 51
2810 20:12:09.752894
2811 20:12:09.753017 Set Vref, RX VrefLevel [Byte0]: 52
2812 20:12:09.756786 [Byte1]: 52
2813 20:12:09.761119
2814 20:12:09.761245 Set Vref, RX VrefLevel [Byte0]: 53
2815 20:12:09.764286 [Byte1]: 53
2816 20:12:09.769342
2817 20:12:09.769461 Set Vref, RX VrefLevel [Byte0]: 54
2818 20:12:09.772253 [Byte1]: 54
2819 20:12:09.777209
2820 20:12:09.777333 Set Vref, RX VrefLevel [Byte0]: 55
2821 20:12:09.780370 [Byte1]: 55
2822 20:12:09.785021
2823 20:12:09.785141 Set Vref, RX VrefLevel [Byte0]: 56
2824 20:12:09.788058 [Byte1]: 56
2825 20:12:09.792606
2826 20:12:09.792730 Set Vref, RX VrefLevel [Byte0]: 57
2827 20:12:09.796006 [Byte1]: 57
2828 20:12:09.800768
2829 20:12:09.800885 Set Vref, RX VrefLevel [Byte0]: 58
2830 20:12:09.804084 [Byte1]: 58
2831 20:12:09.808428
2832 20:12:09.808548 Set Vref, RX VrefLevel [Byte0]: 59
2833 20:12:09.811835 [Byte1]: 59
2834 20:12:09.816226
2835 20:12:09.816347 Set Vref, RX VrefLevel [Byte0]: 60
2836 20:12:09.819548 [Byte1]: 60
2837 20:12:09.824590
2838 20:12:09.824711 Set Vref, RX VrefLevel [Byte0]: 61
2839 20:12:09.827561 [Byte1]: 61
2840 20:12:09.832398
2841 20:12:09.832519 Set Vref, RX VrefLevel [Byte0]: 62
2842 20:12:09.835694 [Byte1]: 62
2843 20:12:09.840526
2844 20:12:09.840645 Set Vref, RX VrefLevel [Byte0]: 63
2845 20:12:09.843661 [Byte1]: 63
2846 20:12:09.848309
2847 20:12:09.848431 Set Vref, RX VrefLevel [Byte0]: 64
2848 20:12:09.851407 [Byte1]: 64
2849 20:12:09.856583
2850 20:12:09.856741 Set Vref, RX VrefLevel [Byte0]: 65
2851 20:12:09.859437 [Byte1]: 65
2852 20:12:09.863814
2853 20:12:09.863888 Set Vref, RX VrefLevel [Byte0]: 66
2854 20:12:09.867243 [Byte1]: 66
2855 20:12:09.871970
2856 20:12:09.872055 Set Vref, RX VrefLevel [Byte0]: 67
2857 20:12:09.875335 [Byte1]: 67
2858 20:12:09.880424
2859 20:12:09.880499 Set Vref, RX VrefLevel [Byte0]: 68
2860 20:12:09.883341 [Byte1]: 68
2861 20:12:09.887842
2862 20:12:09.887914 Final RX Vref Byte 0 = 54 to rank0
2863 20:12:09.891231 Final RX Vref Byte 1 = 59 to rank0
2864 20:12:09.894481 Final RX Vref Byte 0 = 54 to rank1
2865 20:12:09.897749 Final RX Vref Byte 1 = 59 to rank1==
2866 20:12:09.901442 Dram Type= 6, Freq= 0, CH_0, rank 0
2867 20:12:09.908033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 20:12:09.908155 ==
2869 20:12:09.908266 DQS Delay:
2870 20:12:09.908381 DQS0 = 0, DQS1 = 0
2871 20:12:09.911181 DQM Delay:
2872 20:12:09.911301 DQM0 = 117, DQM1 = 105
2873 20:12:09.914754 DQ Delay:
2874 20:12:09.918009 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2875 20:12:09.921321 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2876 20:12:09.924586 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2877 20:12:09.927683 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2878 20:12:09.927807
2879 20:12:09.927915
2880 20:12:09.934637 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2881 20:12:09.937842 CH0 RK0: MR19=404, MR18=500
2882 20:12:09.944459 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2883 20:12:09.944582
2884 20:12:09.947670 ----->DramcWriteLeveling(PI) begin...
2885 20:12:09.947792 ==
2886 20:12:09.951017 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 20:12:09.954953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 20:12:09.955074 ==
2889 20:12:09.958025 Write leveling (Byte 0): 29 => 29
2890 20:12:09.961065 Write leveling (Byte 1): 27 => 27
2891 20:12:09.964540 DramcWriteLeveling(PI) end<-----
2892 20:12:09.964662
2893 20:12:09.964771 ==
2894 20:12:09.968077 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 20:12:09.971173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 20:12:09.974247 ==
2897 20:12:09.974363 [Gating] SW mode calibration
2898 20:12:09.984371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2899 20:12:09.987912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2900 20:12:09.990656 0 15 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2901 20:12:09.997824 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2902 20:12:10.001250 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 20:12:10.004465 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 20:12:10.010932 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 20:12:10.013686 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 20:12:10.017658 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2907 20:12:10.023850 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2908 20:12:10.027031 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2909 20:12:10.030730 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 20:12:10.037146 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 20:12:10.040570 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 20:12:10.043728 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 20:12:10.050672 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 20:12:10.053753 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2915 20:12:10.057137 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2916 20:12:10.063548 1 1 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2917 20:12:10.067184 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 20:12:10.070487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 20:12:10.076614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 20:12:10.080538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 20:12:10.083428 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 20:12:10.090149 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2923 20:12:10.093330 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2924 20:12:10.096775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 20:12:10.103346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 20:12:10.106641 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 20:12:10.109755 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 20:12:10.116553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 20:12:10.119821 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 20:12:10.123012 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 20:12:10.129826 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 20:12:10.133126 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 20:12:10.136293 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 20:12:10.142981 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 20:12:10.146263 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 20:12:10.149530 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 20:12:10.156010 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 20:12:10.159294 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2939 20:12:10.162630 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2940 20:12:10.169379 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2941 20:12:10.169504 Total UI for P1: 0, mck2ui 16
2942 20:12:10.175853 best dqsien dly found for B0: ( 1, 3, 26)
2943 20:12:10.179225 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 20:12:10.182526 Total UI for P1: 0, mck2ui 16
2945 20:12:10.185827 best dqsien dly found for B1: ( 1, 4, 0)
2946 20:12:10.189145 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2947 20:12:10.192445 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2948 20:12:10.192520
2949 20:12:10.195872 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2950 20:12:10.198955 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2951 20:12:10.202358 [Gating] SW calibration Done
2952 20:12:10.202463 ==
2953 20:12:10.205491 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 20:12:10.208944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 20:12:10.209046 ==
2956 20:12:10.212619 RX Vref Scan: 0
2957 20:12:10.212694
2958 20:12:10.215999 RX Vref 0 -> 0, step: 1
2959 20:12:10.216118
2960 20:12:10.216233 RX Delay -40 -> 252, step: 8
2961 20:12:10.222634 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2962 20:12:10.225762 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2963 20:12:10.229266 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2964 20:12:10.232709 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2965 20:12:10.236074 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2966 20:12:10.242396 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2967 20:12:10.245847 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2968 20:12:10.249160 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2969 20:12:10.252216 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2970 20:12:10.256023 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2971 20:12:10.262275 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2972 20:12:10.265773 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2973 20:12:10.268883 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2974 20:12:10.272307 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2975 20:12:10.275663 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2976 20:12:10.282228 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2977 20:12:10.282327 ==
2978 20:12:10.285634 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 20:12:10.289205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 20:12:10.289290 ==
2981 20:12:10.289354 DQS Delay:
2982 20:12:10.292275 DQS0 = 0, DQS1 = 0
2983 20:12:10.292374 DQM Delay:
2984 20:12:10.295576 DQM0 = 116, DQM1 = 109
2985 20:12:10.295674 DQ Delay:
2986 20:12:10.298510 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2987 20:12:10.302139 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =119
2988 20:12:10.305520 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2989 20:12:10.308712 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2990 20:12:10.308804
2991 20:12:10.312032
2992 20:12:10.312136 ==
2993 20:12:10.315203 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 20:12:10.318433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 20:12:10.318515 ==
2996 20:12:10.318605
2997 20:12:10.318667
2998 20:12:10.321752 TX Vref Scan disable
2999 20:12:10.321851 == TX Byte 0 ==
3000 20:12:10.328332 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3001 20:12:10.331912 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3002 20:12:10.331993 == TX Byte 1 ==
3003 20:12:10.338187 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3004 20:12:10.341899 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3005 20:12:10.341991 ==
3006 20:12:10.345437 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 20:12:10.348422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 20:12:10.348521 ==
3009 20:12:10.360990 TX Vref=22, minBit 1, minWin=25, winSum=413
3010 20:12:10.364094 TX Vref=24, minBit 2, minWin=25, winSum=422
3011 20:12:10.367665 TX Vref=26, minBit 0, minWin=25, winSum=416
3012 20:12:10.370891 TX Vref=28, minBit 0, minWin=26, winSum=423
3013 20:12:10.374027 TX Vref=30, minBit 3, minWin=26, winSum=429
3014 20:12:10.377396 TX Vref=32, minBit 5, minWin=26, winSum=428
3015 20:12:10.384292 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
3016 20:12:10.384391
3017 20:12:10.387204 Final TX Range 1 Vref 30
3018 20:12:10.387286
3019 20:12:10.387350 ==
3020 20:12:10.390760 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 20:12:10.393909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 20:12:10.394000 ==
3023 20:12:10.394063
3024 20:12:10.397997
3025 20:12:10.398104 TX Vref Scan disable
3026 20:12:10.400626 == TX Byte 0 ==
3027 20:12:10.403958 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3028 20:12:10.407280 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3029 20:12:10.410511 == TX Byte 1 ==
3030 20:12:10.414263 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3031 20:12:10.417857 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3032 20:12:10.420972
3033 20:12:10.421053 [DATLAT]
3034 20:12:10.421117 Freq=1200, CH0 RK1
3035 20:12:10.421177
3036 20:12:10.423820 DATLAT Default: 0xd
3037 20:12:10.423902 0, 0xFFFF, sum = 0
3038 20:12:10.427636 1, 0xFFFF, sum = 0
3039 20:12:10.427719 2, 0xFFFF, sum = 0
3040 20:12:10.430478 3, 0xFFFF, sum = 0
3041 20:12:10.430561 4, 0xFFFF, sum = 0
3042 20:12:10.434211 5, 0xFFFF, sum = 0
3043 20:12:10.437323 6, 0xFFFF, sum = 0
3044 20:12:10.437406 7, 0xFFFF, sum = 0
3045 20:12:10.440617 8, 0xFFFF, sum = 0
3046 20:12:10.440699 9, 0xFFFF, sum = 0
3047 20:12:10.443924 10, 0xFFFF, sum = 0
3048 20:12:10.444007 11, 0xFFFF, sum = 0
3049 20:12:10.447253 12, 0x0, sum = 1
3050 20:12:10.447335 13, 0x0, sum = 2
3051 20:12:10.450464 14, 0x0, sum = 3
3052 20:12:10.450547 15, 0x0, sum = 4
3053 20:12:10.450611 best_step = 13
3054 20:12:10.453784
3055 20:12:10.453865 ==
3056 20:12:10.457292 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 20:12:10.460463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 20:12:10.460545 ==
3059 20:12:10.460609 RX Vref Scan: 0
3060 20:12:10.460668
3061 20:12:10.463993 RX Vref 0 -> 0, step: 1
3062 20:12:10.464075
3063 20:12:10.466813 RX Delay -21 -> 252, step: 4
3064 20:12:10.470183 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3065 20:12:10.476645 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3066 20:12:10.480545 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3067 20:12:10.483698 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3068 20:12:10.486905 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3069 20:12:10.490326 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3070 20:12:10.496770 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3071 20:12:10.500237 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3072 20:12:10.503600 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3073 20:12:10.506800 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3074 20:12:10.510103 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3075 20:12:10.516883 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3076 20:12:10.520080 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3077 20:12:10.523433 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3078 20:12:10.526537 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3079 20:12:10.530148 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3080 20:12:10.533303 ==
3081 20:12:10.536817 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 20:12:10.539662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 20:12:10.539744 ==
3084 20:12:10.539808 DQS Delay:
3085 20:12:10.543290 DQS0 = 0, DQS1 = 0
3086 20:12:10.543384 DQM Delay:
3087 20:12:10.546747 DQM0 = 116, DQM1 = 106
3088 20:12:10.546829 DQ Delay:
3089 20:12:10.549888 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3090 20:12:10.553213 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3091 20:12:10.556631 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3092 20:12:10.559641 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3093 20:12:10.559723
3094 20:12:10.559786
3095 20:12:10.569884 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3096 20:12:10.572916 CH0 RK1: MR19=403, MR18=1FF
3097 20:12:10.576498 CH0_RK1: MR19=0x403, MR18=0x1FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3098 20:12:10.579606 [RxdqsGatingPostProcess] freq 1200
3099 20:12:10.586265 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3100 20:12:10.589679 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 20:12:10.592792 best DQS1 dly(2T, 0.5T) = (0, 12)
3102 20:12:10.596441 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 20:12:10.599820 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3104 20:12:10.602927 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 20:12:10.606248 best DQS1 dly(2T, 0.5T) = (0, 12)
3106 20:12:10.609634 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 20:12:10.609716 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3108 20:12:10.612722 Pre-setting of DQS Precalculation
3109 20:12:10.619391 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3110 20:12:10.619488 ==
3111 20:12:10.622537 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 20:12:10.625835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 20:12:10.625917 ==
3114 20:12:10.632961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 20:12:10.639372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3116 20:12:10.646539 [CA 0] Center 38 (8~68) winsize 61
3117 20:12:10.649897 [CA 1] Center 37 (7~68) winsize 62
3118 20:12:10.653312 [CA 2] Center 35 (5~65) winsize 61
3119 20:12:10.656988 [CA 3] Center 34 (4~64) winsize 61
3120 20:12:10.659627 [CA 4] Center 34 (4~64) winsize 61
3121 20:12:10.662986 [CA 5] Center 34 (4~64) winsize 61
3122 20:12:10.663067
3123 20:12:10.666528 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3124 20:12:10.666609
3125 20:12:10.669911 [CATrainingPosCal] consider 1 rank data
3126 20:12:10.672875 u2DelayCellTimex100 = 270/100 ps
3127 20:12:10.676103 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3128 20:12:10.682822 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3129 20:12:10.686501 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3130 20:12:10.689687 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3131 20:12:10.693334 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3132 20:12:10.695946 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3133 20:12:10.696026
3134 20:12:10.699416 CA PerBit enable=1, Macro0, CA PI delay=34
3135 20:12:10.699498
3136 20:12:10.702949 [CBTSetCACLKResult] CA Dly = 34
3137 20:12:10.706134 CS Dly: 4 (0~35)
3138 20:12:10.706214 ==
3139 20:12:10.709269 Dram Type= 6, Freq= 0, CH_1, rank 1
3140 20:12:10.712531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 20:12:10.712613 ==
3142 20:12:10.719704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 20:12:10.722568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3144 20:12:10.732413 [CA 0] Center 37 (7~68) winsize 62
3145 20:12:10.735821 [CA 1] Center 38 (8~68) winsize 61
3146 20:12:10.738608 [CA 2] Center 34 (4~65) winsize 62
3147 20:12:10.741974 [CA 3] Center 33 (3~64) winsize 62
3148 20:12:10.745680 [CA 4] Center 34 (4~64) winsize 61
3149 20:12:10.748660 [CA 5] Center 33 (3~63) winsize 61
3150 20:12:10.748742
3151 20:12:10.752432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3152 20:12:10.752513
3153 20:12:10.755294 [CATrainingPosCal] consider 2 rank data
3154 20:12:10.759481 u2DelayCellTimex100 = 270/100 ps
3155 20:12:10.762222 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3156 20:12:10.768958 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3157 20:12:10.772187 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3158 20:12:10.775602 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 20:12:10.778763 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 20:12:10.781655 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3161 20:12:10.781736
3162 20:12:10.785099 CA PerBit enable=1, Macro0, CA PI delay=33
3163 20:12:10.785188
3164 20:12:10.788363 [CBTSetCACLKResult] CA Dly = 33
3165 20:12:10.788444 CS Dly: 6 (0~39)
3166 20:12:10.791788
3167 20:12:10.795333 ----->DramcWriteLeveling(PI) begin...
3168 20:12:10.795446 ==
3169 20:12:10.798881 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 20:12:10.801809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 20:12:10.801891 ==
3172 20:12:10.805227 Write leveling (Byte 0): 25 => 25
3173 20:12:10.808427 Write leveling (Byte 1): 27 => 27
3174 20:12:10.811928 DramcWriteLeveling(PI) end<-----
3175 20:12:10.812009
3176 20:12:10.812071 ==
3177 20:12:10.815238 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 20:12:10.818236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 20:12:10.818317 ==
3180 20:12:10.821976 [Gating] SW mode calibration
3181 20:12:10.828293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3182 20:12:10.834901 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3183 20:12:10.838636 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3184 20:12:10.841903 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 20:12:10.848202 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 20:12:10.851846 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 20:12:10.854784 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 20:12:10.861280 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 20:12:10.864701 0 15 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
3190 20:12:10.867940 0 15 28 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (0 0)
3191 20:12:10.874801 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 20:12:10.877912 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 20:12:10.881280 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 20:12:10.888055 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 20:12:10.891190 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 20:12:10.894944 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 20:12:10.898022 1 0 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
3198 20:12:10.904636 1 0 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3199 20:12:10.908078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 20:12:10.911337 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 20:12:10.918113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 20:12:10.921043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 20:12:10.924329 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 20:12:10.930875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 20:12:10.934075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3206 20:12:10.937457 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3207 20:12:10.944384 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3208 20:12:10.947830 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 20:12:10.950895 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 20:12:10.957509 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 20:12:10.961170 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 20:12:10.964523 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 20:12:10.971293 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 20:12:10.974208 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 20:12:10.977940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 20:12:10.984177 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 20:12:10.987888 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 20:12:10.990647 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 20:12:10.997266 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 20:12:11.000587 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 20:12:11.004016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3222 20:12:11.010615 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 20:12:11.013782 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 20:12:11.016946 Total UI for P1: 0, mck2ui 16
3225 20:12:11.020423 best dqsien dly found for B0: ( 1, 3, 26)
3226 20:12:11.023476 Total UI for P1: 0, mck2ui 16
3227 20:12:11.026645 best dqsien dly found for B1: ( 1, 3, 28)
3228 20:12:11.030405 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3229 20:12:11.033610 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3230 20:12:11.033692
3231 20:12:11.037056 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3232 20:12:11.039971 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3233 20:12:11.043726 [Gating] SW calibration Done
3234 20:12:11.043807 ==
3235 20:12:11.046729 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 20:12:11.053848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 20:12:11.053929 ==
3238 20:12:11.053992 RX Vref Scan: 0
3239 20:12:11.054050
3240 20:12:11.057000 RX Vref 0 -> 0, step: 1
3241 20:12:11.057080
3242 20:12:11.059906 RX Delay -40 -> 252, step: 8
3243 20:12:11.063342 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3244 20:12:11.066902 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3245 20:12:11.069790 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3246 20:12:11.073089 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3247 20:12:11.079933 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3248 20:12:11.083609 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3249 20:12:11.086444 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3250 20:12:11.089855 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3251 20:12:11.093381 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3252 20:12:11.099854 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3253 20:12:11.103555 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3254 20:12:11.106711 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3255 20:12:11.109732 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3256 20:12:11.113149 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3257 20:12:11.119955 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3258 20:12:11.123145 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3259 20:12:11.123226 ==
3260 20:12:11.126321 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 20:12:11.129648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 20:12:11.129730 ==
3263 20:12:11.133019 DQS Delay:
3264 20:12:11.133100 DQS0 = 0, DQS1 = 0
3265 20:12:11.133163 DQM Delay:
3266 20:12:11.136511 DQM0 = 115, DQM1 = 113
3267 20:12:11.136593 DQ Delay:
3268 20:12:11.139597 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3269 20:12:11.142868 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3270 20:12:11.149606 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3271 20:12:11.152980 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3272 20:12:11.153062
3273 20:12:11.153125
3274 20:12:11.153184 ==
3275 20:12:11.156540 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 20:12:11.159240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 20:12:11.159324 ==
3278 20:12:11.159425
3279 20:12:11.159487
3280 20:12:11.162433 TX Vref Scan disable
3281 20:12:11.166019 == TX Byte 0 ==
3282 20:12:11.169722 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3283 20:12:11.173065 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3284 20:12:11.175993 == TX Byte 1 ==
3285 20:12:11.179281 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 20:12:11.182652 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 20:12:11.182734 ==
3288 20:12:11.186042 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 20:12:11.189443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 20:12:11.192345 ==
3291 20:12:11.202343 TX Vref=22, minBit 3, minWin=24, winSum=405
3292 20:12:11.205556 TX Vref=24, minBit 9, minWin=25, winSum=416
3293 20:12:11.208988 TX Vref=26, minBit 2, minWin=25, winSum=420
3294 20:12:11.212147 TX Vref=28, minBit 9, minWin=25, winSum=425
3295 20:12:11.215689 TX Vref=30, minBit 2, minWin=26, winSum=427
3296 20:12:11.222430 TX Vref=32, minBit 8, minWin=25, winSum=422
3297 20:12:11.225486 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
3298 20:12:11.225569
3299 20:12:11.228928 Final TX Range 1 Vref 30
3300 20:12:11.229011
3301 20:12:11.229074 ==
3302 20:12:11.232046 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 20:12:11.235292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 20:12:11.239114 ==
3305 20:12:11.239196
3306 20:12:11.239259
3307 20:12:11.239333 TX Vref Scan disable
3308 20:12:11.242314 == TX Byte 0 ==
3309 20:12:11.245567 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3310 20:12:11.249253 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3311 20:12:11.252267 == TX Byte 1 ==
3312 20:12:11.255516 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3313 20:12:11.262414 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3314 20:12:11.262496
3315 20:12:11.262560 [DATLAT]
3316 20:12:11.262619 Freq=1200, CH1 RK0
3317 20:12:11.262676
3318 20:12:11.265062 DATLAT Default: 0xd
3319 20:12:11.265148 0, 0xFFFF, sum = 0
3320 20:12:11.268580 1, 0xFFFF, sum = 0
3321 20:12:11.268664 2, 0xFFFF, sum = 0
3322 20:12:11.271759 3, 0xFFFF, sum = 0
3323 20:12:11.275303 4, 0xFFFF, sum = 0
3324 20:12:11.275426 5, 0xFFFF, sum = 0
3325 20:12:11.278599 6, 0xFFFF, sum = 0
3326 20:12:11.278699 7, 0xFFFF, sum = 0
3327 20:12:11.281781 8, 0xFFFF, sum = 0
3328 20:12:11.281865 9, 0xFFFF, sum = 0
3329 20:12:11.285262 10, 0xFFFF, sum = 0
3330 20:12:11.285346 11, 0xFFFF, sum = 0
3331 20:12:11.288482 12, 0x0, sum = 1
3332 20:12:11.288566 13, 0x0, sum = 2
3333 20:12:11.291966 14, 0x0, sum = 3
3334 20:12:11.292051 15, 0x0, sum = 4
3335 20:12:11.292118 best_step = 13
3336 20:12:11.295180
3337 20:12:11.295263 ==
3338 20:12:11.298508 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 20:12:11.301846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 20:12:11.301931 ==
3341 20:12:11.301997 RX Vref Scan: 1
3342 20:12:11.302058
3343 20:12:11.304990 Set Vref Range= 32 -> 127
3344 20:12:11.305074
3345 20:12:11.308609 RX Vref 32 -> 127, step: 1
3346 20:12:11.308693
3347 20:12:11.311952 RX Delay -13 -> 252, step: 4
3348 20:12:11.312036
3349 20:12:11.315250 Set Vref, RX VrefLevel [Byte0]: 32
3350 20:12:11.318451 [Byte1]: 32
3351 20:12:11.318590
3352 20:12:11.321920 Set Vref, RX VrefLevel [Byte0]: 33
3353 20:12:11.325228 [Byte1]: 33
3354 20:12:11.328558
3355 20:12:11.328640 Set Vref, RX VrefLevel [Byte0]: 34
3356 20:12:11.331868 [Byte1]: 34
3357 20:12:11.336365
3358 20:12:11.336447 Set Vref, RX VrefLevel [Byte0]: 35
3359 20:12:11.339522 [Byte1]: 35
3360 20:12:11.344500
3361 20:12:11.344581 Set Vref, RX VrefLevel [Byte0]: 36
3362 20:12:11.348321 [Byte1]: 36
3363 20:12:11.352070
3364 20:12:11.352152 Set Vref, RX VrefLevel [Byte0]: 37
3365 20:12:11.358759 [Byte1]: 37
3366 20:12:11.358840
3367 20:12:11.361895 Set Vref, RX VrefLevel [Byte0]: 38
3368 20:12:11.365097 [Byte1]: 38
3369 20:12:11.365178
3370 20:12:11.368721 Set Vref, RX VrefLevel [Byte0]: 39
3371 20:12:11.371559 [Byte1]: 39
3372 20:12:11.375843
3373 20:12:11.375992 Set Vref, RX VrefLevel [Byte0]: 40
3374 20:12:11.379275 [Byte1]: 40
3375 20:12:11.383524
3376 20:12:11.383605 Set Vref, RX VrefLevel [Byte0]: 41
3377 20:12:11.386819 [Byte1]: 41
3378 20:12:11.391357
3379 20:12:11.391461 Set Vref, RX VrefLevel [Byte0]: 42
3380 20:12:11.394665 [Byte1]: 42
3381 20:12:11.399577
3382 20:12:11.399659 Set Vref, RX VrefLevel [Byte0]: 43
3383 20:12:11.402711 [Byte1]: 43
3384 20:12:11.407471
3385 20:12:11.407551 Set Vref, RX VrefLevel [Byte0]: 44
3386 20:12:11.410496 [Byte1]: 44
3387 20:12:11.415566
3388 20:12:11.415647 Set Vref, RX VrefLevel [Byte0]: 45
3389 20:12:11.418511 [Byte1]: 45
3390 20:12:11.422965
3391 20:12:11.423046 Set Vref, RX VrefLevel [Byte0]: 46
3392 20:12:11.426273 [Byte1]: 46
3393 20:12:11.430793
3394 20:12:11.430873 Set Vref, RX VrefLevel [Byte0]: 47
3395 20:12:11.434215 [Byte1]: 47
3396 20:12:11.438835
3397 20:12:11.438916 Set Vref, RX VrefLevel [Byte0]: 48
3398 20:12:11.442436 [Byte1]: 48
3399 20:12:11.446663
3400 20:12:11.446743 Set Vref, RX VrefLevel [Byte0]: 49
3401 20:12:11.449850 [Byte1]: 49
3402 20:12:11.455087
3403 20:12:11.455168 Set Vref, RX VrefLevel [Byte0]: 50
3404 20:12:11.457926 [Byte1]: 50
3405 20:12:11.462175
3406 20:12:11.462256 Set Vref, RX VrefLevel [Byte0]: 51
3407 20:12:11.465535 [Byte1]: 51
3408 20:12:11.470220
3409 20:12:11.470300 Set Vref, RX VrefLevel [Byte0]: 52
3410 20:12:11.473376 [Byte1]: 52
3411 20:12:11.477897
3412 20:12:11.477977 Set Vref, RX VrefLevel [Byte0]: 53
3413 20:12:11.481585 [Byte1]: 53
3414 20:12:11.486242
3415 20:12:11.486354 Set Vref, RX VrefLevel [Byte0]: 54
3416 20:12:11.489535 [Byte1]: 54
3417 20:12:11.493855
3418 20:12:11.493935 Set Vref, RX VrefLevel [Byte0]: 55
3419 20:12:11.497035 [Byte1]: 55
3420 20:12:11.501898
3421 20:12:11.501979 Set Vref, RX VrefLevel [Byte0]: 56
3422 20:12:11.505434 [Byte1]: 56
3423 20:12:11.509778
3424 20:12:11.509859 Set Vref, RX VrefLevel [Byte0]: 57
3425 20:12:11.512940 [Byte1]: 57
3426 20:12:11.517301
3427 20:12:11.517382 Set Vref, RX VrefLevel [Byte0]: 58
3428 20:12:11.520912 [Byte1]: 58
3429 20:12:11.525191
3430 20:12:11.525271 Set Vref, RX VrefLevel [Byte0]: 59
3431 20:12:11.528661 [Byte1]: 59
3432 20:12:11.533649
3433 20:12:11.533730 Set Vref, RX VrefLevel [Byte0]: 60
3434 20:12:11.536934 [Byte1]: 60
3435 20:12:11.541062
3436 20:12:11.541142 Set Vref, RX VrefLevel [Byte0]: 61
3437 20:12:11.544990 [Byte1]: 61
3438 20:12:11.549131
3439 20:12:11.549212 Set Vref, RX VrefLevel [Byte0]: 62
3440 20:12:11.552459 [Byte1]: 62
3441 20:12:11.556767
3442 20:12:11.556847 Set Vref, RX VrefLevel [Byte0]: 63
3443 20:12:11.560384 [Byte1]: 63
3444 20:12:11.564693
3445 20:12:11.564809 Set Vref, RX VrefLevel [Byte0]: 64
3446 20:12:11.568402 [Byte1]: 64
3447 20:12:11.572679
3448 20:12:11.572800 Final RX Vref Byte 0 = 51 to rank0
3449 20:12:11.576466 Final RX Vref Byte 1 = 51 to rank0
3450 20:12:11.579502 Final RX Vref Byte 0 = 51 to rank1
3451 20:12:11.583044 Final RX Vref Byte 1 = 51 to rank1==
3452 20:12:11.586296 Dram Type= 6, Freq= 0, CH_1, rank 0
3453 20:12:11.593026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 20:12:11.593112 ==
3455 20:12:11.593177 DQS Delay:
3456 20:12:11.593238 DQS0 = 0, DQS1 = 0
3457 20:12:11.596244 DQM Delay:
3458 20:12:11.596326 DQM0 = 114, DQM1 = 113
3459 20:12:11.599609 DQ Delay:
3460 20:12:11.602609 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3461 20:12:11.606359 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3462 20:12:11.609339 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =108
3463 20:12:11.612532 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3464 20:12:11.612614
3465 20:12:11.612678
3466 20:12:11.622349 [DQSOSCAuto] RK0, (LSB)MR18= 0xf602, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3467 20:12:11.622433 CH1 RK0: MR19=304, MR18=F602
3468 20:12:11.629520 CH1_RK0: MR19=0x304, MR18=0xF602, DQSOSC=409, MR23=63, INC=39, DEC=26
3469 20:12:11.629603
3470 20:12:11.632480 ----->DramcWriteLeveling(PI) begin...
3471 20:12:11.632563 ==
3472 20:12:11.635537 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 20:12:11.642366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 20:12:11.642449 ==
3475 20:12:11.645936 Write leveling (Byte 0): 25 => 25
3476 20:12:11.646018 Write leveling (Byte 1): 27 => 27
3477 20:12:11.648725 DramcWriteLeveling(PI) end<-----
3478 20:12:11.648806
3479 20:12:11.652347 ==
3480 20:12:11.652428 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 20:12:11.658735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 20:12:11.658818 ==
3483 20:12:11.662116 [Gating] SW mode calibration
3484 20:12:11.668724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3485 20:12:11.672052 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3486 20:12:11.678918 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 20:12:11.682028 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 20:12:11.685484 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 20:12:11.692059 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 20:12:11.695257 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 20:12:11.698836 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3492 20:12:11.705589 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
3493 20:12:11.709001 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3494 20:12:11.711880 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 20:12:11.718523 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 20:12:11.721912 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 20:12:11.725108 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 20:12:11.732396 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 20:12:11.734975 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3500 20:12:11.738495 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3501 20:12:11.745284 1 0 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
3502 20:12:11.748459 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 20:12:11.751657 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 20:12:11.757933 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 20:12:11.761457 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 20:12:11.764964 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 20:12:11.770942 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 20:12:11.774935 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3509 20:12:11.778053 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3510 20:12:11.784681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 20:12:11.787754 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 20:12:11.790882 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 20:12:11.797824 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 20:12:11.800694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 20:12:11.803891 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 20:12:11.810571 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 20:12:11.813807 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 20:12:11.817247 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 20:12:11.823580 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 20:12:11.827012 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 20:12:11.830335 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 20:12:11.837101 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 20:12:11.840491 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3524 20:12:11.843230 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3525 20:12:11.850187 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3526 20:12:11.850269 Total UI for P1: 0, mck2ui 16
3527 20:12:11.856543 best dqsien dly found for B0: ( 1, 3, 22)
3528 20:12:11.859849 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 20:12:11.863012 Total UI for P1: 0, mck2ui 16
3530 20:12:11.866305 best dqsien dly found for B1: ( 1, 3, 26)
3531 20:12:11.870117 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3532 20:12:11.873011 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3533 20:12:11.873093
3534 20:12:11.876398 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3535 20:12:11.879894 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3536 20:12:11.882709 [Gating] SW calibration Done
3537 20:12:11.882791 ==
3538 20:12:11.886278 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 20:12:11.892778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 20:12:11.892860 ==
3541 20:12:11.892925 RX Vref Scan: 0
3542 20:12:11.892985
3543 20:12:11.896000 RX Vref 0 -> 0, step: 1
3544 20:12:11.896082
3545 20:12:11.899728 RX Delay -40 -> 252, step: 8
3546 20:12:11.902761 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3547 20:12:11.905963 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3548 20:12:11.909407 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3549 20:12:11.916032 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3550 20:12:11.919044 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3551 20:12:11.922634 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3552 20:12:11.926053 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3553 20:12:11.928874 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3554 20:12:11.935347 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3555 20:12:11.939022 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3556 20:12:11.942080 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3557 20:12:11.945651 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3558 20:12:11.948624 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3559 20:12:11.955525 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3560 20:12:11.958611 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3561 20:12:11.962117 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3562 20:12:11.962200 ==
3563 20:12:11.965466 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 20:12:11.968485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 20:12:11.971962 ==
3566 20:12:11.972045 DQS Delay:
3567 20:12:11.972109 DQS0 = 0, DQS1 = 0
3568 20:12:11.975025 DQM Delay:
3569 20:12:11.975106 DQM0 = 114, DQM1 = 111
3570 20:12:11.978401 DQ Delay:
3571 20:12:11.981955 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3572 20:12:11.985164 DQ4 =119, DQ5 =123, DQ6 =119, DQ7 =111
3573 20:12:11.988450 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3574 20:12:11.991897 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3575 20:12:11.992026
3576 20:12:11.992090
3577 20:12:11.992149 ==
3578 20:12:11.994848 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 20:12:11.998246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 20:12:11.998330 ==
3581 20:12:11.998395
3582 20:12:12.001483
3583 20:12:12.001565 TX Vref Scan disable
3584 20:12:12.004661 == TX Byte 0 ==
3585 20:12:12.008059 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3586 20:12:12.011072 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3587 20:12:12.014849 == TX Byte 1 ==
3588 20:12:12.017848 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3589 20:12:12.021462 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3590 20:12:12.021546 ==
3591 20:12:12.024689 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 20:12:12.030781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 20:12:12.030864 ==
3594 20:12:12.041939 TX Vref=22, minBit 3, minWin=25, winSum=419
3595 20:12:12.045334 TX Vref=24, minBit 9, minWin=25, winSum=422
3596 20:12:12.048291 TX Vref=26, minBit 9, minWin=25, winSum=425
3597 20:12:12.051537 TX Vref=28, minBit 1, minWin=26, winSum=430
3598 20:12:12.054882 TX Vref=30, minBit 8, minWin=25, winSum=430
3599 20:12:12.061872 TX Vref=32, minBit 8, minWin=25, winSum=429
3600 20:12:12.065015 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3601 20:12:12.065098
3602 20:12:12.068158 Final TX Range 1 Vref 28
3603 20:12:12.068241
3604 20:12:12.068306 ==
3605 20:12:12.071756 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 20:12:12.074657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 20:12:12.074741 ==
3608 20:12:12.077849
3609 20:12:12.077931
3610 20:12:12.077995 TX Vref Scan disable
3611 20:12:12.081475 == TX Byte 0 ==
3612 20:12:12.084471 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3613 20:12:12.091309 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3614 20:12:12.091448 == TX Byte 1 ==
3615 20:12:12.094727 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 20:12:12.100977 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 20:12:12.101060
3618 20:12:12.101125 [DATLAT]
3619 20:12:12.101184 Freq=1200, CH1 RK1
3620 20:12:12.101242
3621 20:12:12.104495 DATLAT Default: 0xd
3622 20:12:12.107855 0, 0xFFFF, sum = 0
3623 20:12:12.107940 1, 0xFFFF, sum = 0
3624 20:12:12.111057 2, 0xFFFF, sum = 0
3625 20:12:12.111140 3, 0xFFFF, sum = 0
3626 20:12:12.114035 4, 0xFFFF, sum = 0
3627 20:12:12.114119 5, 0xFFFF, sum = 0
3628 20:12:12.117337 6, 0xFFFF, sum = 0
3629 20:12:12.117422 7, 0xFFFF, sum = 0
3630 20:12:12.120609 8, 0xFFFF, sum = 0
3631 20:12:12.120693 9, 0xFFFF, sum = 0
3632 20:12:12.123894 10, 0xFFFF, sum = 0
3633 20:12:12.123978 11, 0xFFFF, sum = 0
3634 20:12:12.127313 12, 0x0, sum = 1
3635 20:12:12.127444 13, 0x0, sum = 2
3636 20:12:12.130769 14, 0x0, sum = 3
3637 20:12:12.130853 15, 0x0, sum = 4
3638 20:12:12.133774 best_step = 13
3639 20:12:12.133857
3640 20:12:12.133921 ==
3641 20:12:12.136920 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 20:12:12.140416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 20:12:12.140499 ==
3644 20:12:12.144047 RX Vref Scan: 0
3645 20:12:12.144129
3646 20:12:12.144193 RX Vref 0 -> 0, step: 1
3647 20:12:12.144254
3648 20:12:12.146907 RX Delay -13 -> 252, step: 4
3649 20:12:12.153875 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3650 20:12:12.156739 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3651 20:12:12.160170 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3652 20:12:12.163793 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3653 20:12:12.169950 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3654 20:12:12.173580 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3655 20:12:12.176784 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3656 20:12:12.180077 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3657 20:12:12.183391 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3658 20:12:12.189947 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3659 20:12:12.193080 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3660 20:12:12.196085 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3661 20:12:12.199457 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3662 20:12:12.202692 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3663 20:12:12.209820 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3664 20:12:12.212657 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3665 20:12:12.212740 ==
3666 20:12:12.216070 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 20:12:12.219805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 20:12:12.219889 ==
3669 20:12:12.223032 DQS Delay:
3670 20:12:12.223141 DQS0 = 0, DQS1 = 0
3671 20:12:12.226055 DQM Delay:
3672 20:12:12.226137 DQM0 = 115, DQM1 = 112
3673 20:12:12.226201 DQ Delay:
3674 20:12:12.229487 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3675 20:12:12.235796 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3676 20:12:12.238974 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3677 20:12:12.242273 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3678 20:12:12.242357
3679 20:12:12.242422
3680 20:12:12.248858 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3681 20:12:12.252207 CH1 RK1: MR19=304, MR18=F90B
3682 20:12:12.258942 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3683 20:12:12.262225 [RxdqsGatingPostProcess] freq 1200
3684 20:12:12.268750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3685 20:12:12.272137 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 20:12:12.272221 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 20:12:12.275461 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 20:12:12.278328 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 20:12:12.281859 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 20:12:12.284872 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 20:12:12.288510 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 20:12:12.291653 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 20:12:12.295210 Pre-setting of DQS Precalculation
3694 20:12:12.301500 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3695 20:12:12.307952 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3696 20:12:12.314766 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3697 20:12:12.314849
3698 20:12:12.314914
3699 20:12:12.318058 [Calibration Summary] 2400 Mbps
3700 20:12:12.321005 CH 0, Rank 0
3701 20:12:12.321088 SW Impedance : PASS
3702 20:12:12.324861 DUTY Scan : NO K
3703 20:12:12.324943 ZQ Calibration : PASS
3704 20:12:12.327627 Jitter Meter : NO K
3705 20:12:12.331014 CBT Training : PASS
3706 20:12:12.331097 Write leveling : PASS
3707 20:12:12.334140 RX DQS gating : PASS
3708 20:12:12.338035 RX DQ/DQS(RDDQC) : PASS
3709 20:12:12.338116 TX DQ/DQS : PASS
3710 20:12:12.340617 RX DATLAT : PASS
3711 20:12:12.344333 RX DQ/DQS(Engine): PASS
3712 20:12:12.344415 TX OE : NO K
3713 20:12:12.347646 All Pass.
3714 20:12:12.347727
3715 20:12:12.347791 CH 0, Rank 1
3716 20:12:12.350796 SW Impedance : PASS
3717 20:12:12.350877 DUTY Scan : NO K
3718 20:12:12.354130 ZQ Calibration : PASS
3719 20:12:12.357644 Jitter Meter : NO K
3720 20:12:12.357726 CBT Training : PASS
3721 20:12:12.360774 Write leveling : PASS
3722 20:12:12.364230 RX DQS gating : PASS
3723 20:12:12.364311 RX DQ/DQS(RDDQC) : PASS
3724 20:12:12.367270 TX DQ/DQS : PASS
3725 20:12:12.370511 RX DATLAT : PASS
3726 20:12:12.370593 RX DQ/DQS(Engine): PASS
3727 20:12:12.374092 TX OE : NO K
3728 20:12:12.374175 All Pass.
3729 20:12:12.374239
3730 20:12:12.377409 CH 1, Rank 0
3731 20:12:12.377490 SW Impedance : PASS
3732 20:12:12.380295 DUTY Scan : NO K
3733 20:12:12.384149 ZQ Calibration : PASS
3734 20:12:12.384230 Jitter Meter : NO K
3735 20:12:12.387146 CBT Training : PASS
3736 20:12:12.390295 Write leveling : PASS
3737 20:12:12.390402 RX DQS gating : PASS
3738 20:12:12.393663 RX DQ/DQS(RDDQC) : PASS
3739 20:12:12.396785 TX DQ/DQS : PASS
3740 20:12:12.396867 RX DATLAT : PASS
3741 20:12:12.400271 RX DQ/DQS(Engine): PASS
3742 20:12:12.400352 TX OE : NO K
3743 20:12:12.403303 All Pass.
3744 20:12:12.403408
3745 20:12:12.403473 CH 1, Rank 1
3746 20:12:12.406499 SW Impedance : PASS
3747 20:12:12.409772 DUTY Scan : NO K
3748 20:12:12.409853 ZQ Calibration : PASS
3749 20:12:12.413162 Jitter Meter : NO K
3750 20:12:12.413243 CBT Training : PASS
3751 20:12:12.417000 Write leveling : PASS
3752 20:12:12.419937 RX DQS gating : PASS
3753 20:12:12.420019 RX DQ/DQS(RDDQC) : PASS
3754 20:12:12.422972 TX DQ/DQS : PASS
3755 20:12:12.426846 RX DATLAT : PASS
3756 20:12:12.426927 RX DQ/DQS(Engine): PASS
3757 20:12:12.429790 TX OE : NO K
3758 20:12:12.429891 All Pass.
3759 20:12:12.429998
3760 20:12:12.433285 DramC Write-DBI off
3761 20:12:12.436158 PER_BANK_REFRESH: Hybrid Mode
3762 20:12:12.436244 TX_TRACKING: ON
3763 20:12:12.446304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3764 20:12:12.449434 [FAST_K] Save calibration result to emmc
3765 20:12:12.452739 dramc_set_vcore_voltage set vcore to 650000
3766 20:12:12.455918 Read voltage for 600, 5
3767 20:12:12.455999 Vio18 = 0
3768 20:12:12.459268 Vcore = 650000
3769 20:12:12.459415 Vdram = 0
3770 20:12:12.459509 Vddq = 0
3771 20:12:12.459570 Vmddr = 0
3772 20:12:12.465682 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3773 20:12:12.472483 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3774 20:12:12.472630 MEM_TYPE=3, freq_sel=19
3775 20:12:12.475535 sv_algorithm_assistance_LP4_1600
3776 20:12:12.479199 ============ PULL DRAM RESETB DOWN ============
3777 20:12:12.485685 ========== PULL DRAM RESETB DOWN end =========
3778 20:12:12.488979 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3779 20:12:12.492294 ===================================
3780 20:12:12.495335 LPDDR4 DRAM CONFIGURATION
3781 20:12:12.498705 ===================================
3782 20:12:12.498790 EX_ROW_EN[0] = 0x0
3783 20:12:12.502151 EX_ROW_EN[1] = 0x0
3784 20:12:12.505345 LP4Y_EN = 0x0
3785 20:12:12.505429 WORK_FSP = 0x0
3786 20:12:12.508431 WL = 0x2
3787 20:12:12.508515 RL = 0x2
3788 20:12:12.511621 BL = 0x2
3789 20:12:12.511705 RPST = 0x0
3790 20:12:12.514953 RD_PRE = 0x0
3791 20:12:12.515063 WR_PRE = 0x1
3792 20:12:12.518380 WR_PST = 0x0
3793 20:12:12.518463 DBI_WR = 0x0
3794 20:12:12.521421 DBI_RD = 0x0
3795 20:12:12.521505 OTF = 0x1
3796 20:12:12.524827 ===================================
3797 20:12:12.528423 ===================================
3798 20:12:12.531406 ANA top config
3799 20:12:12.534599 ===================================
3800 20:12:12.538700 DLL_ASYNC_EN = 0
3801 20:12:12.538782 ALL_SLAVE_EN = 1
3802 20:12:12.541599 NEW_RANK_MODE = 1
3803 20:12:12.544632 DLL_IDLE_MODE = 1
3804 20:12:12.548009 LP45_APHY_COMB_EN = 1
3805 20:12:12.548092 TX_ODT_DIS = 1
3806 20:12:12.551163 NEW_8X_MODE = 1
3807 20:12:12.554371 ===================================
3808 20:12:12.557712 ===================================
3809 20:12:12.560911 data_rate = 1200
3810 20:12:12.564280 CKR = 1
3811 20:12:12.567561 DQ_P2S_RATIO = 8
3812 20:12:12.571433 ===================================
3813 20:12:12.574363 CA_P2S_RATIO = 8
3814 20:12:12.574448 DQ_CA_OPEN = 0
3815 20:12:12.577583 DQ_SEMI_OPEN = 0
3816 20:12:12.580849 CA_SEMI_OPEN = 0
3817 20:12:12.584265 CA_FULL_RATE = 0
3818 20:12:12.587411 DQ_CKDIV4_EN = 1
3819 20:12:12.590628 CA_CKDIV4_EN = 1
3820 20:12:12.594252 CA_PREDIV_EN = 0
3821 20:12:12.594335 PH8_DLY = 0
3822 20:12:12.597400 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3823 20:12:12.600691 DQ_AAMCK_DIV = 4
3824 20:12:12.603972 CA_AAMCK_DIV = 4
3825 20:12:12.607115 CA_ADMCK_DIV = 4
3826 20:12:12.610697 DQ_TRACK_CA_EN = 0
3827 20:12:12.610779 CA_PICK = 600
3828 20:12:12.613949 CA_MCKIO = 600
3829 20:12:12.617247 MCKIO_SEMI = 0
3830 20:12:12.620723 PLL_FREQ = 2288
3831 20:12:12.624382 DQ_UI_PI_RATIO = 32
3832 20:12:12.627182 CA_UI_PI_RATIO = 0
3833 20:12:12.630580 ===================================
3834 20:12:12.633497 ===================================
3835 20:12:12.633579 memory_type:LPDDR4
3836 20:12:12.637201 GP_NUM : 10
3837 20:12:12.640274 SRAM_EN : 1
3838 20:12:12.640356 MD32_EN : 0
3839 20:12:12.643653 ===================================
3840 20:12:12.646903 [ANA_INIT] >>>>>>>>>>>>>>
3841 20:12:12.650115 <<<<<< [CONFIGURE PHASE]: ANA_TX
3842 20:12:12.653122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3843 20:12:12.656577 ===================================
3844 20:12:12.659928 data_rate = 1200,PCW = 0X5800
3845 20:12:12.663389 ===================================
3846 20:12:12.666380 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3847 20:12:12.673109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 20:12:12.676280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 20:12:12.682782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3850 20:12:12.686468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3851 20:12:12.689395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3852 20:12:12.689478 [ANA_INIT] flow start
3853 20:12:12.693130 [ANA_INIT] PLL >>>>>>>>
3854 20:12:12.696104 [ANA_INIT] PLL <<<<<<<<
3855 20:12:12.696186 [ANA_INIT] MIDPI >>>>>>>>
3856 20:12:12.699330 [ANA_INIT] MIDPI <<<<<<<<
3857 20:12:12.702614 [ANA_INIT] DLL >>>>>>>>
3858 20:12:12.702696 [ANA_INIT] flow end
3859 20:12:12.709289 ============ LP4 DIFF to SE enter ============
3860 20:12:12.712720 ============ LP4 DIFF to SE exit ============
3861 20:12:12.716221 [ANA_INIT] <<<<<<<<<<<<<
3862 20:12:12.719395 [Flow] Enable top DCM control >>>>>
3863 20:12:12.722436 [Flow] Enable top DCM control <<<<<
3864 20:12:12.722532 Enable DLL master slave shuffle
3865 20:12:12.729113 ==============================================================
3866 20:12:12.732802 Gating Mode config
3867 20:12:12.735967 ==============================================================
3868 20:12:12.738838 Config description:
3869 20:12:12.749058 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3870 20:12:12.755145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3871 20:12:12.759082 SELPH_MODE 0: By rank 1: By Phase
3872 20:12:12.765522 ==============================================================
3873 20:12:12.768253 GAT_TRACK_EN = 1
3874 20:12:12.771620 RX_GATING_MODE = 2
3875 20:12:12.774893 RX_GATING_TRACK_MODE = 2
3876 20:12:12.778160 SELPH_MODE = 1
3877 20:12:12.781327 PICG_EARLY_EN = 1
3878 20:12:12.784670 VALID_LAT_VALUE = 1
3879 20:12:12.788290 ==============================================================
3880 20:12:12.791380 Enter into Gating configuration >>>>
3881 20:12:12.794754 Exit from Gating configuration <<<<
3882 20:12:12.797987 Enter into DVFS_PRE_config >>>>>
3883 20:12:12.810790 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3884 20:12:12.814024 Exit from DVFS_PRE_config <<<<<
3885 20:12:12.817703 Enter into PICG configuration >>>>
3886 20:12:12.820548 Exit from PICG configuration <<<<
3887 20:12:12.820630 [RX_INPUT] configuration >>>>>
3888 20:12:12.823823 [RX_INPUT] configuration <<<<<
3889 20:12:12.830443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3890 20:12:12.834220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3891 20:12:12.840526 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 20:12:12.847131 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 20:12:12.853823 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 20:12:12.860466 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 20:12:12.863647 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3896 20:12:12.867023 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3897 20:12:12.873592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3898 20:12:12.876838 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3899 20:12:12.880089 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3900 20:12:12.883410 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 20:12:12.886625 ===================================
3902 20:12:12.889917 LPDDR4 DRAM CONFIGURATION
3903 20:12:12.893494 ===================================
3904 20:12:12.896496 EX_ROW_EN[0] = 0x0
3905 20:12:12.896578 EX_ROW_EN[1] = 0x0
3906 20:12:12.899821 LP4Y_EN = 0x0
3907 20:12:12.899903 WORK_FSP = 0x0
3908 20:12:12.903223 WL = 0x2
3909 20:12:12.906529 RL = 0x2
3910 20:12:12.906611 BL = 0x2
3911 20:12:12.909869 RPST = 0x0
3912 20:12:12.909951 RD_PRE = 0x0
3913 20:12:12.913294 WR_PRE = 0x1
3914 20:12:12.913376 WR_PST = 0x0
3915 20:12:12.916335 DBI_WR = 0x0
3916 20:12:12.916417 DBI_RD = 0x0
3917 20:12:12.919777 OTF = 0x1
3918 20:12:12.922898 ===================================
3919 20:12:12.926180 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3920 20:12:12.929424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3921 20:12:12.936205 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 20:12:12.939322 ===================================
3923 20:12:12.939429 LPDDR4 DRAM CONFIGURATION
3924 20:12:12.942456 ===================================
3925 20:12:12.946212 EX_ROW_EN[0] = 0x10
3926 20:12:12.946333 EX_ROW_EN[1] = 0x0
3927 20:12:12.949145 LP4Y_EN = 0x0
3928 20:12:12.952468 WORK_FSP = 0x0
3929 20:12:12.952550 WL = 0x2
3930 20:12:12.955480 RL = 0x2
3931 20:12:12.955562 BL = 0x2
3932 20:12:12.958790 RPST = 0x0
3933 20:12:12.958871 RD_PRE = 0x0
3934 20:12:12.962370 WR_PRE = 0x1
3935 20:12:12.962508 WR_PST = 0x0
3936 20:12:12.965381 DBI_WR = 0x0
3937 20:12:12.965464 DBI_RD = 0x0
3938 20:12:12.968721 OTF = 0x1
3939 20:12:12.971933 ===================================
3940 20:12:12.978638 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3941 20:12:12.982034 nWR fixed to 30
3942 20:12:12.982120 [ModeRegInit_LP4] CH0 RK0
3943 20:12:12.985341 [ModeRegInit_LP4] CH0 RK1
3944 20:12:12.988313 [ModeRegInit_LP4] CH1 RK0
3945 20:12:12.991911 [ModeRegInit_LP4] CH1 RK1
3946 20:12:12.992021 match AC timing 17
3947 20:12:12.998403 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3948 20:12:13.001581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3949 20:12:13.005163 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3950 20:12:13.011472 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3951 20:12:13.015340 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3952 20:12:13.015458 ==
3953 20:12:13.018435 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 20:12:13.021301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 20:12:13.021383 ==
3956 20:12:13.028034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 20:12:13.034615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 20:12:13.037824 [CA 0] Center 36 (6~67) winsize 62
3959 20:12:13.041182 [CA 1] Center 36 (5~67) winsize 63
3960 20:12:13.044246 [CA 2] Center 34 (4~65) winsize 62
3961 20:12:13.047773 [CA 3] Center 34 (3~65) winsize 63
3962 20:12:13.051127 [CA 4] Center 33 (3~64) winsize 62
3963 20:12:13.054136 [CA 5] Center 33 (3~64) winsize 62
3964 20:12:13.054218
3965 20:12:13.057864 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 20:12:13.057946
3967 20:12:13.061116 [CATrainingPosCal] consider 1 rank data
3968 20:12:13.064379 u2DelayCellTimex100 = 270/100 ps
3969 20:12:13.067352 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3970 20:12:13.070863 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3971 20:12:13.073822 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 20:12:13.077350 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3973 20:12:13.083879 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 20:12:13.087464 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 20:12:13.087547
3976 20:12:13.090774 CA PerBit enable=1, Macro0, CA PI delay=33
3977 20:12:13.090856
3978 20:12:13.093595 [CBTSetCACLKResult] CA Dly = 33
3979 20:12:13.093667 CS Dly: 5 (0~36)
3980 20:12:13.093728 ==
3981 20:12:13.097375 Dram Type= 6, Freq= 0, CH_0, rank 1
3982 20:12:13.103637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 20:12:13.103711 ==
3984 20:12:13.107206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 20:12:13.113710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3986 20:12:13.117086 [CA 0] Center 36 (6~67) winsize 62
3987 20:12:13.120284 [CA 1] Center 36 (6~67) winsize 62
3988 20:12:13.123272 [CA 2] Center 34 (4~65) winsize 62
3989 20:12:13.126877 [CA 3] Center 34 (4~65) winsize 62
3990 20:12:13.130151 [CA 4] Center 33 (3~64) winsize 62
3991 20:12:13.133530 [CA 5] Center 33 (3~64) winsize 62
3992 20:12:13.133613
3993 20:12:13.136442 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3994 20:12:13.136528
3995 20:12:13.139727 [CATrainingPosCal] consider 2 rank data
3996 20:12:13.143212 u2DelayCellTimex100 = 270/100 ps
3997 20:12:13.146828 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 20:12:13.153247 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3999 20:12:13.156507 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 20:12:13.159901 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 20:12:13.163288 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 20:12:13.166054 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 20:12:13.166136
4004 20:12:13.169679 CA PerBit enable=1, Macro0, CA PI delay=33
4005 20:12:13.169761
4006 20:12:13.172491 [CBTSetCACLKResult] CA Dly = 33
4007 20:12:13.176578 CS Dly: 5 (0~36)
4008 20:12:13.176660
4009 20:12:13.179266 ----->DramcWriteLeveling(PI) begin...
4010 20:12:13.179349 ==
4011 20:12:13.182492 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 20:12:13.185807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 20:12:13.185890 ==
4014 20:12:13.188992 Write leveling (Byte 0): 31 => 31
4015 20:12:13.192597 Write leveling (Byte 1): 30 => 30
4016 20:12:13.195654 DramcWriteLeveling(PI) end<-----
4017 20:12:13.195736
4018 20:12:13.195799 ==
4019 20:12:13.199271 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 20:12:13.202362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 20:12:13.202445 ==
4022 20:12:13.205717 [Gating] SW mode calibration
4023 20:12:13.212356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4024 20:12:13.218655 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4025 20:12:13.221962 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 20:12:13.228876 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 20:12:13.232228 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 20:12:13.235448 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4029 20:12:13.238680 0 9 16 | B1->B0 | 2e2e 2a2a | 1 1 | (1 1) (1 0)
4030 20:12:13.244961 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 20:12:13.248538 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 20:12:13.251969 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 20:12:13.258277 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 20:12:13.261496 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 20:12:13.264773 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 20:12:13.271865 0 10 12 | B1->B0 | 2323 2e2e | 1 0 | (0 0) (0 0)
4037 20:12:13.274832 0 10 16 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
4038 20:12:13.281345 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 20:12:13.284807 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 20:12:13.287685 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 20:12:13.294563 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 20:12:13.297582 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 20:12:13.300950 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 20:12:13.307590 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4045 20:12:13.311007 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4046 20:12:13.314012 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 20:12:13.320641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 20:12:13.324328 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 20:12:13.327870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 20:12:13.333825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 20:12:13.337633 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 20:12:13.340478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 20:12:13.347519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 20:12:13.350440 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 20:12:13.353680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 20:12:13.360430 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 20:12:13.363680 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 20:12:13.366757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 20:12:13.373379 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 20:12:13.377301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4061 20:12:13.380189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4062 20:12:13.383693 Total UI for P1: 0, mck2ui 16
4063 20:12:13.386593 best dqsien dly found for B0: ( 0, 13, 12)
4064 20:12:13.393685 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 20:12:13.393767 Total UI for P1: 0, mck2ui 16
4066 20:12:13.396798 best dqsien dly found for B1: ( 0, 13, 16)
4067 20:12:13.403178 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4068 20:12:13.406531 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4069 20:12:13.406614
4070 20:12:13.409841 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4071 20:12:13.412930 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4072 20:12:13.415871 [Gating] SW calibration Done
4073 20:12:13.415993 ==
4074 20:12:13.419209 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 20:12:13.422789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 20:12:13.422872 ==
4077 20:12:13.426211 RX Vref Scan: 0
4078 20:12:13.426292
4079 20:12:13.426356 RX Vref 0 -> 0, step: 1
4080 20:12:13.426415
4081 20:12:13.429656 RX Delay -230 -> 252, step: 16
4082 20:12:13.435932 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4083 20:12:13.439258 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4084 20:12:13.442567 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4085 20:12:13.445874 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4086 20:12:13.452322 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4087 20:12:13.456177 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4088 20:12:13.459231 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4089 20:12:13.462336 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4090 20:12:13.465791 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4091 20:12:13.472019 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4092 20:12:13.475277 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4093 20:12:13.478739 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4094 20:12:13.482041 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4095 20:12:13.488529 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4096 20:12:13.491762 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4097 20:12:13.495122 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4098 20:12:13.495205 ==
4099 20:12:13.498451 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 20:12:13.505053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 20:12:13.505135 ==
4102 20:12:13.505200 DQS Delay:
4103 20:12:13.505260 DQS0 = 0, DQS1 = 0
4104 20:12:13.508394 DQM Delay:
4105 20:12:13.508476 DQM0 = 43, DQM1 = 33
4106 20:12:13.511482 DQ Delay:
4107 20:12:13.514676 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4108 20:12:13.518041 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4109 20:12:13.521165 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4110 20:12:13.525196 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4111 20:12:13.525278
4112 20:12:13.525341
4113 20:12:13.525401 ==
4114 20:12:13.528318 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 20:12:13.531271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 20:12:13.531396 ==
4117 20:12:13.531466
4118 20:12:13.531529
4119 20:12:13.534843 TX Vref Scan disable
4120 20:12:13.537745 == TX Byte 0 ==
4121 20:12:13.541324 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4122 20:12:13.544328 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4123 20:12:13.548025 == TX Byte 1 ==
4124 20:12:13.551011 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4125 20:12:13.554574 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4126 20:12:13.554661 ==
4127 20:12:13.557789 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 20:12:13.561508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 20:12:13.564376 ==
4130 20:12:13.564459
4131 20:12:13.564524
4132 20:12:13.564583 TX Vref Scan disable
4133 20:12:13.568262 == TX Byte 0 ==
4134 20:12:13.571351 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 20:12:13.577906 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 20:12:13.577988 == TX Byte 1 ==
4137 20:12:13.581243 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4138 20:12:13.588148 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4139 20:12:13.588231
4140 20:12:13.588294 [DATLAT]
4141 20:12:13.588354 Freq=600, CH0 RK0
4142 20:12:13.588412
4143 20:12:13.591402 DATLAT Default: 0x9
4144 20:12:13.594209 0, 0xFFFF, sum = 0
4145 20:12:13.594291 1, 0xFFFF, sum = 0
4146 20:12:13.597478 2, 0xFFFF, sum = 0
4147 20:12:13.597562 3, 0xFFFF, sum = 0
4148 20:12:13.600796 4, 0xFFFF, sum = 0
4149 20:12:13.600880 5, 0xFFFF, sum = 0
4150 20:12:13.604061 6, 0xFFFF, sum = 0
4151 20:12:13.604145 7, 0xFFFF, sum = 0
4152 20:12:13.607318 8, 0x0, sum = 1
4153 20:12:13.607427 9, 0x0, sum = 2
4154 20:12:13.610866 10, 0x0, sum = 3
4155 20:12:13.610949 11, 0x0, sum = 4
4156 20:12:13.611014 best_step = 9
4157 20:12:13.613973
4158 20:12:13.614054 ==
4159 20:12:13.617208 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 20:12:13.620555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 20:12:13.620653 ==
4162 20:12:13.620719 RX Vref Scan: 1
4163 20:12:13.620779
4164 20:12:13.623801 RX Vref 0 -> 0, step: 1
4165 20:12:13.623883
4166 20:12:13.627077 RX Delay -195 -> 252, step: 8
4167 20:12:13.627164
4168 20:12:13.630451 Set Vref, RX VrefLevel [Byte0]: 54
4169 20:12:13.633389 [Byte1]: 59
4170 20:12:13.636927
4171 20:12:13.637009 Final RX Vref Byte 0 = 54 to rank0
4172 20:12:13.640201 Final RX Vref Byte 1 = 59 to rank0
4173 20:12:13.643309 Final RX Vref Byte 0 = 54 to rank1
4174 20:12:13.646697 Final RX Vref Byte 1 = 59 to rank1==
4175 20:12:13.650001 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 20:12:13.656904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 20:12:13.656987 ==
4178 20:12:13.657051 DQS Delay:
4179 20:12:13.659725 DQS0 = 0, DQS1 = 0
4180 20:12:13.659808 DQM Delay:
4181 20:12:13.659873 DQM0 = 41, DQM1 = 32
4182 20:12:13.663213 DQ Delay:
4183 20:12:13.666198 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4184 20:12:13.669950 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4185 20:12:13.673099 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4186 20:12:13.676126 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4187 20:12:13.676207
4188 20:12:13.676271
4189 20:12:13.682794 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4190 20:12:13.685958 CH0 RK0: MR19=808, MR18=4B43
4191 20:12:13.692883 CH0_RK0: MR19=0x808, MR18=0x4B43, DQSOSC=395, MR23=63, INC=168, DEC=112
4192 20:12:13.692965
4193 20:12:13.696121 ----->DramcWriteLeveling(PI) begin...
4194 20:12:13.696205 ==
4195 20:12:13.699306 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 20:12:13.702736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 20:12:13.702818 ==
4198 20:12:13.705680 Write leveling (Byte 0): 34 => 34
4199 20:12:13.709580 Write leveling (Byte 1): 32 => 32
4200 20:12:13.712465 DramcWriteLeveling(PI) end<-----
4201 20:12:13.712547
4202 20:12:13.712611 ==
4203 20:12:13.715634 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 20:12:13.722370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 20:12:13.722453 ==
4206 20:12:13.722518 [Gating] SW mode calibration
4207 20:12:13.732400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4208 20:12:13.735286 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4209 20:12:13.742215 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 20:12:13.745603 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 20:12:13.748727 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 20:12:13.752092 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4213 20:12:13.758691 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4214 20:12:13.761888 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 20:12:13.768589 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 20:12:13.771891 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 20:12:13.774908 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 20:12:13.781387 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 20:12:13.785367 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4220 20:12:13.787943 0 10 12 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
4221 20:12:13.794565 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
4222 20:12:13.797906 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 20:12:13.801210 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 20:12:13.807551 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 20:12:13.810980 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 20:12:13.814671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 20:12:13.820997 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4228 20:12:13.824102 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4229 20:12:13.827319 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4230 20:12:13.833810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 20:12:13.837248 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 20:12:13.840338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 20:12:13.847197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 20:12:13.850119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 20:12:13.853481 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 20:12:13.860002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 20:12:13.863330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 20:12:13.866861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 20:12:13.873833 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 20:12:13.876548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 20:12:13.879799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 20:12:13.886571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 20:12:13.889947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 20:12:13.893029 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4245 20:12:13.900186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 20:12:13.900262 Total UI for P1: 0, mck2ui 16
4247 20:12:13.906166 best dqsien dly found for B0: ( 0, 13, 12)
4248 20:12:13.906240 Total UI for P1: 0, mck2ui 16
4249 20:12:13.913002 best dqsien dly found for B1: ( 0, 13, 14)
4250 20:12:13.916542 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4251 20:12:13.919309 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4252 20:12:13.919433
4253 20:12:13.922738 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4254 20:12:13.926297 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4255 20:12:13.929435 [Gating] SW calibration Done
4256 20:12:13.929518 ==
4257 20:12:13.932630 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 20:12:13.936119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 20:12:13.936200 ==
4260 20:12:13.939000 RX Vref Scan: 0
4261 20:12:13.939075
4262 20:12:13.942424 RX Vref 0 -> 0, step: 1
4263 20:12:13.942523
4264 20:12:13.942612 RX Delay -230 -> 252, step: 16
4265 20:12:13.949029 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4266 20:12:13.952276 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4267 20:12:13.955483 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4268 20:12:13.958885 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4269 20:12:13.965481 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4270 20:12:13.968518 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4271 20:12:13.972204 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4272 20:12:13.975484 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4273 20:12:13.981924 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4274 20:12:13.985140 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4275 20:12:13.988495 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4276 20:12:13.991632 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4277 20:12:13.998529 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4278 20:12:14.001841 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4279 20:12:14.005083 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4280 20:12:14.008407 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4281 20:12:14.008489 ==
4282 20:12:14.011718 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 20:12:14.018216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 20:12:14.018299 ==
4285 20:12:14.018393 DQS Delay:
4286 20:12:14.021679 DQS0 = 0, DQS1 = 0
4287 20:12:14.021787 DQM Delay:
4288 20:12:14.021879 DQM0 = 42, DQM1 = 31
4289 20:12:14.024761 DQ Delay:
4290 20:12:14.028234 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4291 20:12:14.031255 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4292 20:12:14.034372 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4293 20:12:14.038089 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =33
4294 20:12:14.038172
4295 20:12:14.038235
4296 20:12:14.038294 ==
4297 20:12:14.040967 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 20:12:14.044596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 20:12:14.044680 ==
4300 20:12:14.044745
4301 20:12:14.044805
4302 20:12:14.047635 TX Vref Scan disable
4303 20:12:14.050890 == TX Byte 0 ==
4304 20:12:14.054040 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4305 20:12:14.057401 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4306 20:12:14.060776 == TX Byte 1 ==
4307 20:12:14.064333 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4308 20:12:14.067296 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4309 20:12:14.067436 ==
4310 20:12:14.070688 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 20:12:14.077398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 20:12:14.077482 ==
4313 20:12:14.077546
4314 20:12:14.077606
4315 20:12:14.077663 TX Vref Scan disable
4316 20:12:14.081650 == TX Byte 0 ==
4317 20:12:14.084911 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4318 20:12:14.091815 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4319 20:12:14.091898 == TX Byte 1 ==
4320 20:12:14.094526 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4321 20:12:14.101677 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4322 20:12:14.101761
4323 20:12:14.101825 [DATLAT]
4324 20:12:14.101884 Freq=600, CH0 RK1
4325 20:12:14.101943
4326 20:12:14.104431 DATLAT Default: 0x9
4327 20:12:14.104513 0, 0xFFFF, sum = 0
4328 20:12:14.107741 1, 0xFFFF, sum = 0
4329 20:12:14.111107 2, 0xFFFF, sum = 0
4330 20:12:14.111201 3, 0xFFFF, sum = 0
4331 20:12:14.114899 4, 0xFFFF, sum = 0
4332 20:12:14.114982 5, 0xFFFF, sum = 0
4333 20:12:14.117677 6, 0xFFFF, sum = 0
4334 20:12:14.117776 7, 0xFFFF, sum = 0
4335 20:12:14.120900 8, 0x0, sum = 1
4336 20:12:14.120987 9, 0x0, sum = 2
4337 20:12:14.124698 10, 0x0, sum = 3
4338 20:12:14.124782 11, 0x0, sum = 4
4339 20:12:14.124847 best_step = 9
4340 20:12:14.124906
4341 20:12:14.127839 ==
4342 20:12:14.131184 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 20:12:14.134206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 20:12:14.134305 ==
4345 20:12:14.134371 RX Vref Scan: 0
4346 20:12:14.134431
4347 20:12:14.137246 RX Vref 0 -> 0, step: 1
4348 20:12:14.137327
4349 20:12:14.140957 RX Delay -195 -> 252, step: 8
4350 20:12:14.147220 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4351 20:12:14.150726 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4352 20:12:14.153741 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4353 20:12:14.157255 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4354 20:12:14.163785 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4355 20:12:14.166929 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4356 20:12:14.170748 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4357 20:12:14.173810 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4358 20:12:14.177048 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4359 20:12:14.183570 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4360 20:12:14.186666 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4361 20:12:14.190602 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4362 20:12:14.193412 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4363 20:12:14.200374 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4364 20:12:14.203548 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4365 20:12:14.206480 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4366 20:12:14.206562 ==
4367 20:12:14.209861 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 20:12:14.213099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 20:12:14.216394 ==
4370 20:12:14.216476 DQS Delay:
4371 20:12:14.216540 DQS0 = 0, DQS1 = 0
4372 20:12:14.219882 DQM Delay:
4373 20:12:14.219963 DQM0 = 41, DQM1 = 34
4374 20:12:14.223024 DQ Delay:
4375 20:12:14.226181 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4376 20:12:14.226262 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4377 20:12:14.229946 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4378 20:12:14.236371 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4379 20:12:14.236453
4380 20:12:14.236516
4381 20:12:14.242740 [DQSOSCAuto] RK1, (LSB)MR18= 0x4540, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4382 20:12:14.246302 CH0 RK1: MR19=808, MR18=4540
4383 20:12:14.252441 CH0_RK1: MR19=0x808, MR18=0x4540, DQSOSC=396, MR23=63, INC=167, DEC=111
4384 20:12:14.256213 [RxdqsGatingPostProcess] freq 600
4385 20:12:14.259111 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4386 20:12:14.263069 Pre-setting of DQS Precalculation
4387 20:12:14.269187 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4388 20:12:14.269269 ==
4389 20:12:14.272335 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 20:12:14.275846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 20:12:14.275929 ==
4392 20:12:14.282549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 20:12:14.288761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4394 20:12:14.291894 [CA 0] Center 35 (5~66) winsize 62
4395 20:12:14.295600 [CA 1] Center 35 (5~66) winsize 62
4396 20:12:14.298967 [CA 2] Center 34 (4~65) winsize 62
4397 20:12:14.301925 [CA 3] Center 34 (3~65) winsize 63
4398 20:12:14.305342 [CA 4] Center 34 (4~65) winsize 62
4399 20:12:14.308527 [CA 5] Center 33 (3~64) winsize 62
4400 20:12:14.308609
4401 20:12:14.312034 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4402 20:12:14.312115
4403 20:12:14.315016 [CATrainingPosCal] consider 1 rank data
4404 20:12:14.318382 u2DelayCellTimex100 = 270/100 ps
4405 20:12:14.321696 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 20:12:14.325019 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 20:12:14.328582 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 20:12:14.331227 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4409 20:12:14.334633 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 20:12:14.341231 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 20:12:14.341317
4412 20:12:14.344690 CA PerBit enable=1, Macro0, CA PI delay=33
4413 20:12:14.344775
4414 20:12:14.348342 [CBTSetCACLKResult] CA Dly = 33
4415 20:12:14.348427 CS Dly: 5 (0~36)
4416 20:12:14.348511 ==
4417 20:12:14.351192 Dram Type= 6, Freq= 0, CH_1, rank 1
4418 20:12:14.354370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 20:12:14.357669 ==
4420 20:12:14.361019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 20:12:14.367501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4422 20:12:14.370783 [CA 0] Center 36 (6~66) winsize 61
4423 20:12:14.374050 [CA 1] Center 35 (5~66) winsize 62
4424 20:12:14.377436 [CA 2] Center 34 (4~65) winsize 62
4425 20:12:14.381138 [CA 3] Center 34 (3~65) winsize 63
4426 20:12:14.384388 [CA 4] Center 34 (3~65) winsize 63
4427 20:12:14.387440 [CA 5] Center 33 (3~64) winsize 62
4428 20:12:14.387527
4429 20:12:14.390769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4430 20:12:14.390853
4431 20:12:14.394305 [CATrainingPosCal] consider 2 rank data
4432 20:12:14.397357 u2DelayCellTimex100 = 270/100 ps
4433 20:12:14.400745 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4434 20:12:14.404404 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 20:12:14.410581 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 20:12:14.413632 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4437 20:12:14.417014 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 20:12:14.420328 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 20:12:14.420412
4440 20:12:14.423979 CA PerBit enable=1, Macro0, CA PI delay=33
4441 20:12:14.424063
4442 20:12:14.427135 [CBTSetCACLKResult] CA Dly = 33
4443 20:12:14.427219 CS Dly: 5 (0~36)
4444 20:12:14.427320
4445 20:12:14.430313 ----->DramcWriteLeveling(PI) begin...
4446 20:12:14.433502 ==
4447 20:12:14.437187 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 20:12:14.440330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 20:12:14.440415 ==
4450 20:12:14.443502 Write leveling (Byte 0): 30 => 30
4451 20:12:14.446785 Write leveling (Byte 1): 30 => 30
4452 20:12:14.449943 DramcWriteLeveling(PI) end<-----
4453 20:12:14.450027
4454 20:12:14.450112 ==
4455 20:12:14.453367 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 20:12:14.456688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 20:12:14.456787 ==
4458 20:12:14.459776 [Gating] SW mode calibration
4459 20:12:14.466499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4460 20:12:14.473055 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4461 20:12:14.476393 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 20:12:14.479698 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 20:12:14.486681 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 20:12:14.489698 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
4465 20:12:14.492816 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 20:12:14.499589 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 20:12:14.502950 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 20:12:14.506082 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 20:12:14.512558 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 20:12:14.515774 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 20:12:14.519454 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 20:12:14.525641 0 10 12 | B1->B0 | 3131 3636 | 0 0 | (0 0) (0 0)
4473 20:12:14.528996 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 20:12:14.532554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 20:12:14.539035 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 20:12:14.542576 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 20:12:14.545707 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 20:12:14.552171 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 20:12:14.555527 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 20:12:14.558875 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 20:12:14.565314 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 20:12:14.568451 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 20:12:14.572210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 20:12:14.578645 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 20:12:14.581925 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 20:12:14.585263 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 20:12:14.591717 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 20:12:14.595100 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 20:12:14.598233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 20:12:14.604835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 20:12:14.607898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 20:12:14.611134 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 20:12:14.617948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 20:12:14.621563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 20:12:14.624753 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 20:12:14.631168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4497 20:12:14.634578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 20:12:14.637941 Total UI for P1: 0, mck2ui 16
4499 20:12:14.640888 best dqsien dly found for B0: ( 0, 13, 12)
4500 20:12:14.644516 Total UI for P1: 0, mck2ui 16
4501 20:12:14.647574 best dqsien dly found for B1: ( 0, 13, 12)
4502 20:12:14.651106 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4503 20:12:14.654295 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4504 20:12:14.654366
4505 20:12:14.657614 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4506 20:12:14.664315 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4507 20:12:14.664387 [Gating] SW calibration Done
4508 20:12:14.664447 ==
4509 20:12:14.667061 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 20:12:14.673678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 20:12:14.673752 ==
4512 20:12:14.673820 RX Vref Scan: 0
4513 20:12:14.673878
4514 20:12:14.676857 RX Vref 0 -> 0, step: 1
4515 20:12:14.676930
4516 20:12:14.680824 RX Delay -230 -> 252, step: 16
4517 20:12:14.683991 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4518 20:12:14.687154 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4519 20:12:14.693886 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4520 20:12:14.696990 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4521 20:12:14.700286 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4522 20:12:14.703050 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4523 20:12:14.709796 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4524 20:12:14.712993 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4525 20:12:14.716666 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4526 20:12:14.719664 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4527 20:12:14.723114 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 20:12:14.729595 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4529 20:12:14.733004 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4530 20:12:14.735970 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4531 20:12:14.742772 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4532 20:12:14.745844 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4533 20:12:14.745917 ==
4534 20:12:14.749825 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 20:12:14.753477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 20:12:14.753548 ==
4537 20:12:14.753608 DQS Delay:
4538 20:12:14.755941 DQS0 = 0, DQS1 = 0
4539 20:12:14.756009 DQM Delay:
4540 20:12:14.759301 DQM0 = 41, DQM1 = 38
4541 20:12:14.759393 DQ Delay:
4542 20:12:14.762613 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4543 20:12:14.765654 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4544 20:12:14.769050 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4545 20:12:14.772391 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4546 20:12:14.772462
4547 20:12:14.772522
4548 20:12:14.772578 ==
4549 20:12:14.775596 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 20:12:14.782486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 20:12:14.782565 ==
4552 20:12:14.782626
4553 20:12:14.782683
4554 20:12:14.782810 TX Vref Scan disable
4555 20:12:14.785958 == TX Byte 0 ==
4556 20:12:14.789076 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4557 20:12:14.795758 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4558 20:12:14.795836 == TX Byte 1 ==
4559 20:12:14.799009 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4560 20:12:14.805722 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4561 20:12:14.805796 ==
4562 20:12:14.808632 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 20:12:14.812223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 20:12:14.812298 ==
4565 20:12:14.812357
4566 20:12:14.812414
4567 20:12:14.815477 TX Vref Scan disable
4568 20:12:14.818893 == TX Byte 0 ==
4569 20:12:14.821748 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4570 20:12:14.825055 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4571 20:12:14.828397 == TX Byte 1 ==
4572 20:12:14.832154 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4573 20:12:14.835269 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4574 20:12:14.835376
4575 20:12:14.838405 [DATLAT]
4576 20:12:14.838488 Freq=600, CH1 RK0
4577 20:12:14.838574
4578 20:12:14.841759 DATLAT Default: 0x9
4579 20:12:14.841843 0, 0xFFFF, sum = 0
4580 20:12:14.845257 1, 0xFFFF, sum = 0
4581 20:12:14.845342 2, 0xFFFF, sum = 0
4582 20:12:14.848681 3, 0xFFFF, sum = 0
4583 20:12:14.848766 4, 0xFFFF, sum = 0
4584 20:12:14.851492 5, 0xFFFF, sum = 0
4585 20:12:14.851577 6, 0xFFFF, sum = 0
4586 20:12:14.854642 7, 0xFFFF, sum = 0
4587 20:12:14.854727 8, 0x0, sum = 1
4588 20:12:14.858267 9, 0x0, sum = 2
4589 20:12:14.858345 10, 0x0, sum = 3
4590 20:12:14.861357 11, 0x0, sum = 4
4591 20:12:14.861430 best_step = 9
4592 20:12:14.861490
4593 20:12:14.861547 ==
4594 20:12:14.864661 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 20:12:14.867872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 20:12:14.870980 ==
4597 20:12:14.871087 RX Vref Scan: 1
4598 20:12:14.871182
4599 20:12:14.874394 RX Vref 0 -> 0, step: 1
4600 20:12:14.874474
4601 20:12:14.877753 RX Delay -179 -> 252, step: 8
4602 20:12:14.877834
4603 20:12:14.880932 Set Vref, RX VrefLevel [Byte0]: 51
4604 20:12:14.884430 [Byte1]: 51
4605 20:12:14.884508
4606 20:12:14.887693 Final RX Vref Byte 0 = 51 to rank0
4607 20:12:14.890709 Final RX Vref Byte 1 = 51 to rank0
4608 20:12:14.894534 Final RX Vref Byte 0 = 51 to rank1
4609 20:12:14.897707 Final RX Vref Byte 1 = 51 to rank1==
4610 20:12:14.900916 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 20:12:14.904346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 20:12:14.904416 ==
4613 20:12:14.907650 DQS Delay:
4614 20:12:14.907719 DQS0 = 0, DQS1 = 0
4615 20:12:14.907778 DQM Delay:
4616 20:12:14.910822 DQM0 = 41, DQM1 = 33
4617 20:12:14.910888 DQ Delay:
4618 20:12:14.913855 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4619 20:12:14.917023 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4620 20:12:14.921050 DQ8 =16, DQ9 =24, DQ10 =32, DQ11 =28
4621 20:12:14.923867 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4622 20:12:14.923948
4623 20:12:14.924011
4624 20:12:14.933878 [DQSOSCAuto] RK0, (LSB)MR18= 0x334c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4625 20:12:14.936983 CH1 RK0: MR19=808, MR18=334C
4626 20:12:14.940179 CH1_RK0: MR19=0x808, MR18=0x334C, DQSOSC=395, MR23=63, INC=168, DEC=112
4627 20:12:14.943630
4628 20:12:14.946651 ----->DramcWriteLeveling(PI) begin...
4629 20:12:14.946724 ==
4630 20:12:14.950039 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 20:12:14.953480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 20:12:14.953551 ==
4633 20:12:14.956722 Write leveling (Byte 0): 29 => 29
4634 20:12:14.960061 Write leveling (Byte 1): 29 => 29
4635 20:12:14.963324 DramcWriteLeveling(PI) end<-----
4636 20:12:14.963448
4637 20:12:14.963508 ==
4638 20:12:14.966514 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 20:12:14.969979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 20:12:14.970049 ==
4641 20:12:14.972984 [Gating] SW mode calibration
4642 20:12:14.979762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4643 20:12:14.986552 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4644 20:12:14.989421 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 20:12:14.993092 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 20:12:14.999466 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 20:12:15.002550 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4648 20:12:15.006070 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4649 20:12:15.012737 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 20:12:15.015824 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 20:12:15.019295 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 20:12:15.025477 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 20:12:15.028770 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 20:12:15.032087 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4655 20:12:15.038858 0 10 12 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4656 20:12:15.042263 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4657 20:12:15.045492 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 20:12:15.052059 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 20:12:15.055032 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 20:12:15.058960 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 20:12:15.065249 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 20:12:15.068595 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4663 20:12:15.071888 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4664 20:12:15.078323 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 20:12:15.081716 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 20:12:15.085189 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 20:12:15.091799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 20:12:15.094974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 20:12:15.097722 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 20:12:15.104695 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 20:12:15.107836 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 20:12:15.111223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 20:12:15.117836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 20:12:15.121152 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 20:12:15.124262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 20:12:15.130761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 20:12:15.134159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 20:12:15.140712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 20:12:15.143808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4680 20:12:15.147249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 20:12:15.150447 Total UI for P1: 0, mck2ui 16
4682 20:12:15.153708 best dqsien dly found for B0: ( 0, 13, 14)
4683 20:12:15.157158 Total UI for P1: 0, mck2ui 16
4684 20:12:15.160568 best dqsien dly found for B1: ( 0, 13, 12)
4685 20:12:15.163829 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4686 20:12:15.166920 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4687 20:12:15.166992
4688 20:12:15.173684 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4689 20:12:15.176950 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4690 20:12:15.177031 [Gating] SW calibration Done
4691 20:12:15.180009 ==
4692 20:12:15.183394 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 20:12:15.187142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 20:12:15.187224 ==
4695 20:12:15.187297 RX Vref Scan: 0
4696 20:12:15.187356
4697 20:12:15.189980 RX Vref 0 -> 0, step: 1
4698 20:12:15.190068
4699 20:12:15.193056 RX Delay -230 -> 252, step: 16
4700 20:12:15.196477 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4701 20:12:15.199613 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4702 20:12:15.206385 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4703 20:12:15.210084 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4704 20:12:15.213239 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4705 20:12:15.216398 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4706 20:12:15.222952 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4707 20:12:15.226152 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4708 20:12:15.229935 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4709 20:12:15.232674 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4710 20:12:15.239247 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4711 20:12:15.242482 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4712 20:12:15.245896 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4713 20:12:15.249541 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4714 20:12:15.256061 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4715 20:12:15.259077 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4716 20:12:15.259159 ==
4717 20:12:15.262302 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 20:12:15.265654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 20:12:15.265736 ==
4720 20:12:15.269252 DQS Delay:
4721 20:12:15.269333 DQS0 = 0, DQS1 = 0
4722 20:12:15.269405 DQM Delay:
4723 20:12:15.272397 DQM0 = 42, DQM1 = 39
4724 20:12:15.272478 DQ Delay:
4725 20:12:15.275801 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4726 20:12:15.279258 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4727 20:12:15.282372 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4728 20:12:15.285732 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4729 20:12:15.285812
4730 20:12:15.285875
4731 20:12:15.285934 ==
4732 20:12:15.289290 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 20:12:15.295650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 20:12:15.295732 ==
4735 20:12:15.295832
4736 20:12:15.295921
4737 20:12:15.296006 TX Vref Scan disable
4738 20:12:15.299172 == TX Byte 0 ==
4739 20:12:15.302553 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4740 20:12:15.309205 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4741 20:12:15.309334 == TX Byte 1 ==
4742 20:12:15.312502 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4743 20:12:15.318814 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4744 20:12:15.318972 ==
4745 20:12:15.322012 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 20:12:15.325602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 20:12:15.325726 ==
4748 20:12:15.325838
4749 20:12:15.325945
4750 20:12:15.329016 TX Vref Scan disable
4751 20:12:15.332028 == TX Byte 0 ==
4752 20:12:15.335290 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4753 20:12:15.338729 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4754 20:12:15.342085 == TX Byte 1 ==
4755 20:12:15.345463 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4756 20:12:15.348642 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4757 20:12:15.348765
4758 20:12:15.348878 [DATLAT]
4759 20:12:15.351945 Freq=600, CH1 RK1
4760 20:12:15.352065
4761 20:12:15.355190 DATLAT Default: 0x9
4762 20:12:15.355308 0, 0xFFFF, sum = 0
4763 20:12:15.358220 1, 0xFFFF, sum = 0
4764 20:12:15.358343 2, 0xFFFF, sum = 0
4765 20:12:15.362034 3, 0xFFFF, sum = 0
4766 20:12:15.362156 4, 0xFFFF, sum = 0
4767 20:12:15.365105 5, 0xFFFF, sum = 0
4768 20:12:15.365227 6, 0xFFFF, sum = 0
4769 20:12:15.368286 7, 0xFFFF, sum = 0
4770 20:12:15.368410 8, 0x0, sum = 1
4771 20:12:15.371787 9, 0x0, sum = 2
4772 20:12:15.371911 10, 0x0, sum = 3
4773 20:12:15.374714 11, 0x0, sum = 4
4774 20:12:15.374836 best_step = 9
4775 20:12:15.374947
4776 20:12:15.375053 ==
4777 20:12:15.378058 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 20:12:15.381306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 20:12:15.381429 ==
4780 20:12:15.384999 RX Vref Scan: 0
4781 20:12:15.385120
4782 20:12:15.388355 RX Vref 0 -> 0, step: 1
4783 20:12:15.388559
4784 20:12:15.388673 RX Delay -179 -> 252, step: 8
4785 20:12:15.396260 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4786 20:12:15.399543 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4787 20:12:15.403002 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4788 20:12:15.406157 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4789 20:12:15.412532 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4790 20:12:15.415856 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4791 20:12:15.419064 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4792 20:12:15.422530 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4793 20:12:15.428861 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4794 20:12:15.432261 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4795 20:12:15.435551 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4796 20:12:15.438656 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4797 20:12:15.445197 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4798 20:12:15.448846 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4799 20:12:15.451974 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4800 20:12:15.455183 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4801 20:12:15.455266 ==
4802 20:12:15.458311 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 20:12:15.464973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 20:12:15.465062 ==
4805 20:12:15.465127 DQS Delay:
4806 20:12:15.468591 DQS0 = 0, DQS1 = 0
4807 20:12:15.468673 DQM Delay:
4808 20:12:15.471860 DQM0 = 37, DQM1 = 36
4809 20:12:15.471941 DQ Delay:
4810 20:12:15.474847 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =40
4811 20:12:15.478321 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4812 20:12:15.481402 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4813 20:12:15.484881 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4814 20:12:15.484964
4815 20:12:15.485028
4816 20:12:15.491317 [DQSOSCAuto] RK1, (LSB)MR18= 0x375b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4817 20:12:15.494822 CH1 RK1: MR19=808, MR18=375B
4818 20:12:15.501193 CH1_RK1: MR19=0x808, MR18=0x375B, DQSOSC=392, MR23=63, INC=170, DEC=113
4819 20:12:15.504790 [RxdqsGatingPostProcess] freq 600
4820 20:12:15.511063 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 20:12:15.514523 Pre-setting of DQS Precalculation
4822 20:12:15.517492 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 20:12:15.524119 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 20:12:15.530859 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 20:12:15.530942
4826 20:12:15.531006
4827 20:12:15.533872 [Calibration Summary] 1200 Mbps
4828 20:12:15.537110 CH 0, Rank 0
4829 20:12:15.537192 SW Impedance : PASS
4830 20:12:15.540752 DUTY Scan : NO K
4831 20:12:15.543914 ZQ Calibration : PASS
4832 20:12:15.543996 Jitter Meter : NO K
4833 20:12:15.547315 CBT Training : PASS
4834 20:12:15.550730 Write leveling : PASS
4835 20:12:15.550813 RX DQS gating : PASS
4836 20:12:15.553861 RX DQ/DQS(RDDQC) : PASS
4837 20:12:15.557232 TX DQ/DQS : PASS
4838 20:12:15.557315 RX DATLAT : PASS
4839 20:12:15.560500 RX DQ/DQS(Engine): PASS
4840 20:12:15.563851 TX OE : NO K
4841 20:12:15.563933 All Pass.
4842 20:12:15.563998
4843 20:12:15.564057 CH 0, Rank 1
4844 20:12:15.566925 SW Impedance : PASS
4845 20:12:15.570261 DUTY Scan : NO K
4846 20:12:15.570369 ZQ Calibration : PASS
4847 20:12:15.573913 Jitter Meter : NO K
4848 20:12:15.576529 CBT Training : PASS
4849 20:12:15.576627 Write leveling : PASS
4850 20:12:15.580218 RX DQS gating : PASS
4851 20:12:15.583537 RX DQ/DQS(RDDQC) : PASS
4852 20:12:15.583647 TX DQ/DQS : PASS
4853 20:12:15.587110 RX DATLAT : PASS
4854 20:12:15.587193 RX DQ/DQS(Engine): PASS
4855 20:12:15.589973 TX OE : NO K
4856 20:12:15.590056 All Pass.
4857 20:12:15.590120
4858 20:12:15.593248 CH 1, Rank 0
4859 20:12:15.593329 SW Impedance : PASS
4860 20:12:15.596461 DUTY Scan : NO K
4861 20:12:15.599638 ZQ Calibration : PASS
4862 20:12:15.599746 Jitter Meter : NO K
4863 20:12:15.603272 CBT Training : PASS
4864 20:12:15.606591 Write leveling : PASS
4865 20:12:15.606715 RX DQS gating : PASS
4866 20:12:15.609990 RX DQ/DQS(RDDQC) : PASS
4867 20:12:15.613362 TX DQ/DQS : PASS
4868 20:12:15.613444 RX DATLAT : PASS
4869 20:12:15.616230 RX DQ/DQS(Engine): PASS
4870 20:12:15.620099 TX OE : NO K
4871 20:12:15.620182 All Pass.
4872 20:12:15.620246
4873 20:12:15.620305 CH 1, Rank 1
4874 20:12:15.622833 SW Impedance : PASS
4875 20:12:15.626153 DUTY Scan : NO K
4876 20:12:15.626235 ZQ Calibration : PASS
4877 20:12:15.629479 Jitter Meter : NO K
4878 20:12:15.632792 CBT Training : PASS
4879 20:12:15.632874 Write leveling : PASS
4880 20:12:15.636007 RX DQS gating : PASS
4881 20:12:15.639450 RX DQ/DQS(RDDQC) : PASS
4882 20:12:15.639533 TX DQ/DQS : PASS
4883 20:12:15.642832 RX DATLAT : PASS
4884 20:12:15.646267 RX DQ/DQS(Engine): PASS
4885 20:12:15.646349 TX OE : NO K
4886 20:12:15.649407 All Pass.
4887 20:12:15.649513
4888 20:12:15.649579 DramC Write-DBI off
4889 20:12:15.652380 PER_BANK_REFRESH: Hybrid Mode
4890 20:12:15.652462 TX_TRACKING: ON
4891 20:12:15.662639 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 20:12:15.666434 [FAST_K] Save calibration result to emmc
4893 20:12:15.669070 dramc_set_vcore_voltage set vcore to 662500
4894 20:12:15.672359 Read voltage for 933, 3
4895 20:12:15.672441 Vio18 = 0
4896 20:12:15.676048 Vcore = 662500
4897 20:12:15.676130 Vdram = 0
4898 20:12:15.676195 Vddq = 0
4899 20:12:15.676255 Vmddr = 0
4900 20:12:15.682360 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 20:12:15.688827 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 20:12:15.688922 MEM_TYPE=3, freq_sel=17
4903 20:12:15.692163 sv_algorithm_assistance_LP4_1600
4904 20:12:15.698946 ============ PULL DRAM RESETB DOWN ============
4905 20:12:15.702204 ========== PULL DRAM RESETB DOWN end =========
4906 20:12:15.705479 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 20:12:15.708465 ===================================
4908 20:12:15.711859 LPDDR4 DRAM CONFIGURATION
4909 20:12:15.714974 ===================================
4910 20:12:15.718373 EX_ROW_EN[0] = 0x0
4911 20:12:15.718455 EX_ROW_EN[1] = 0x0
4912 20:12:15.721569 LP4Y_EN = 0x0
4913 20:12:15.721651 WORK_FSP = 0x0
4914 20:12:15.724692 WL = 0x3
4915 20:12:15.724775 RL = 0x3
4916 20:12:15.728062 BL = 0x2
4917 20:12:15.728145 RPST = 0x0
4918 20:12:15.731421 RD_PRE = 0x0
4919 20:12:15.731504 WR_PRE = 0x1
4920 20:12:15.734806 WR_PST = 0x0
4921 20:12:15.734888 DBI_WR = 0x0
4922 20:12:15.738058 DBI_RD = 0x0
4923 20:12:15.738140 OTF = 0x1
4924 20:12:15.741479 ===================================
4925 20:12:15.744925 ===================================
4926 20:12:15.748385 ANA top config
4927 20:12:15.751354 ===================================
4928 20:12:15.754880 DLL_ASYNC_EN = 0
4929 20:12:15.754963 ALL_SLAVE_EN = 1
4930 20:12:15.757915 NEW_RANK_MODE = 1
4931 20:12:15.761294 DLL_IDLE_MODE = 1
4932 20:12:15.764576 LP45_APHY_COMB_EN = 1
4933 20:12:15.764658 TX_ODT_DIS = 1
4934 20:12:15.767697 NEW_8X_MODE = 1
4935 20:12:15.771108 ===================================
4936 20:12:15.774342 ===================================
4937 20:12:15.777788 data_rate = 1866
4938 20:12:15.781103 CKR = 1
4939 20:12:15.784166 DQ_P2S_RATIO = 8
4940 20:12:15.787423 ===================================
4941 20:12:15.790808 CA_P2S_RATIO = 8
4942 20:12:15.790891 DQ_CA_OPEN = 0
4943 20:12:15.794408 DQ_SEMI_OPEN = 0
4944 20:12:15.797424 CA_SEMI_OPEN = 0
4945 20:12:15.801189 CA_FULL_RATE = 0
4946 20:12:15.804517 DQ_CKDIV4_EN = 1
4947 20:12:15.807532 CA_CKDIV4_EN = 1
4948 20:12:15.811276 CA_PREDIV_EN = 0
4949 20:12:15.811369 PH8_DLY = 0
4950 20:12:15.813963 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 20:12:15.817423 DQ_AAMCK_DIV = 4
4952 20:12:15.820831 CA_AAMCK_DIV = 4
4953 20:12:15.823889 CA_ADMCK_DIV = 4
4954 20:12:15.827286 DQ_TRACK_CA_EN = 0
4955 20:12:15.827392 CA_PICK = 933
4956 20:12:15.830512 CA_MCKIO = 933
4957 20:12:15.833959 MCKIO_SEMI = 0
4958 20:12:15.837081 PLL_FREQ = 3732
4959 20:12:15.840307 DQ_UI_PI_RATIO = 32
4960 20:12:15.843899 CA_UI_PI_RATIO = 0
4961 20:12:15.846691 ===================================
4962 20:12:15.850282 ===================================
4963 20:12:15.853465 memory_type:LPDDR4
4964 20:12:15.853567 GP_NUM : 10
4965 20:12:15.856815 SRAM_EN : 1
4966 20:12:15.856926 MD32_EN : 0
4967 20:12:15.860041 ===================================
4968 20:12:15.863276 [ANA_INIT] >>>>>>>>>>>>>>
4969 20:12:15.866779 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 20:12:15.870228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 20:12:15.873533 ===================================
4972 20:12:15.876679 data_rate = 1866,PCW = 0X8f00
4973 20:12:15.880213 ===================================
4974 20:12:15.883617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 20:12:15.889613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 20:12:15.893012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 20:12:15.899626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 20:12:15.902987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 20:12:15.906159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 20:12:15.906272 [ANA_INIT] flow start
4981 20:12:15.909475 [ANA_INIT] PLL >>>>>>>>
4982 20:12:15.912845 [ANA_INIT] PLL <<<<<<<<
4983 20:12:15.912928 [ANA_INIT] MIDPI >>>>>>>>
4984 20:12:15.916187 [ANA_INIT] MIDPI <<<<<<<<
4985 20:12:15.919294 [ANA_INIT] DLL >>>>>>>>
4986 20:12:15.919438 [ANA_INIT] flow end
4987 20:12:15.926074 ============ LP4 DIFF to SE enter ============
4988 20:12:15.929229 ============ LP4 DIFF to SE exit ============
4989 20:12:15.932562 [ANA_INIT] <<<<<<<<<<<<<
4990 20:12:15.935900 [Flow] Enable top DCM control >>>>>
4991 20:12:15.939301 [Flow] Enable top DCM control <<<<<
4992 20:12:15.939439 Enable DLL master slave shuffle
4993 20:12:15.945825 ==============================================================
4994 20:12:15.949149 Gating Mode config
4995 20:12:15.952304 ==============================================================
4996 20:12:15.955757 Config description:
4997 20:12:15.965804 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 20:12:15.972325 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 20:12:15.975744 SELPH_MODE 0: By rank 1: By Phase
5000 20:12:15.981976 ==============================================================
5001 20:12:15.985185 GAT_TRACK_EN = 1
5002 20:12:15.988906 RX_GATING_MODE = 2
5003 20:12:15.991699 RX_GATING_TRACK_MODE = 2
5004 20:12:15.995409 SELPH_MODE = 1
5005 20:12:15.998717 PICG_EARLY_EN = 1
5006 20:12:16.001590 VALID_LAT_VALUE = 1
5007 20:12:16.004994 ==============================================================
5008 20:12:16.008417 Enter into Gating configuration >>>>
5009 20:12:16.011620 Exit from Gating configuration <<<<
5010 20:12:16.014621 Enter into DVFS_PRE_config >>>>>
5011 20:12:16.027793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 20:12:16.027878 Exit from DVFS_PRE_config <<<<<
5013 20:12:16.031324 Enter into PICG configuration >>>>
5014 20:12:16.034561 Exit from PICG configuration <<<<
5015 20:12:16.037917 [RX_INPUT] configuration >>>>>
5016 20:12:16.041097 [RX_INPUT] configuration <<<<<
5017 20:12:16.047830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 20:12:16.051146 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 20:12:16.057372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 20:12:16.064199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 20:12:16.070435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 20:12:16.077021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 20:12:16.080398 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 20:12:16.083703 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 20:12:16.090380 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 20:12:16.093577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 20:12:16.096741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 20:12:16.103781 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 20:12:16.106756 ===================================
5030 20:12:16.106839 LPDDR4 DRAM CONFIGURATION
5031 20:12:16.110013 ===================================
5032 20:12:16.113239 EX_ROW_EN[0] = 0x0
5033 20:12:16.113322 EX_ROW_EN[1] = 0x0
5034 20:12:16.116357 LP4Y_EN = 0x0
5035 20:12:16.116439 WORK_FSP = 0x0
5036 20:12:16.119517 WL = 0x3
5037 20:12:16.123223 RL = 0x3
5038 20:12:16.123332 BL = 0x2
5039 20:12:16.126658 RPST = 0x0
5040 20:12:16.126740 RD_PRE = 0x0
5041 20:12:16.129973 WR_PRE = 0x1
5042 20:12:16.130055 WR_PST = 0x0
5043 20:12:16.132860 DBI_WR = 0x0
5044 20:12:16.132943 DBI_RD = 0x0
5045 20:12:16.136073 OTF = 0x1
5046 20:12:16.140017 ===================================
5047 20:12:16.142893 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 20:12:16.145801 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 20:12:16.152726 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 20:12:16.156182 ===================================
5051 20:12:16.156265 LPDDR4 DRAM CONFIGURATION
5052 20:12:16.158928 ===================================
5053 20:12:16.162645 EX_ROW_EN[0] = 0x10
5054 20:12:16.165666 EX_ROW_EN[1] = 0x0
5055 20:12:16.165748 LP4Y_EN = 0x0
5056 20:12:16.169363 WORK_FSP = 0x0
5057 20:12:16.169445 WL = 0x3
5058 20:12:16.172575 RL = 0x3
5059 20:12:16.172657 BL = 0x2
5060 20:12:16.175336 RPST = 0x0
5061 20:12:16.175499 RD_PRE = 0x0
5062 20:12:16.178702 WR_PRE = 0x1
5063 20:12:16.178784 WR_PST = 0x0
5064 20:12:16.181987 DBI_WR = 0x0
5065 20:12:16.182078 DBI_RD = 0x0
5066 20:12:16.185287 OTF = 0x1
5067 20:12:16.188412 ===================================
5068 20:12:16.195137 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 20:12:16.198426 nWR fixed to 30
5070 20:12:16.202052 [ModeRegInit_LP4] CH0 RK0
5071 20:12:16.202134 [ModeRegInit_LP4] CH0 RK1
5072 20:12:16.205067 [ModeRegInit_LP4] CH1 RK0
5073 20:12:16.208371 [ModeRegInit_LP4] CH1 RK1
5074 20:12:16.208453 match AC timing 9
5075 20:12:16.215030 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 20:12:16.217981 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 20:12:16.221432 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 20:12:16.227919 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 20:12:16.231329 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 20:12:16.231450 ==
5081 20:12:16.234962 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 20:12:16.238212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 20:12:16.238317 ==
5084 20:12:16.245018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 20:12:16.251211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 20:12:16.254437 [CA 0] Center 37 (7~68) winsize 62
5087 20:12:16.257947 [CA 1] Center 37 (7~68) winsize 62
5088 20:12:16.261072 [CA 2] Center 34 (4~65) winsize 62
5089 20:12:16.264376 [CA 3] Center 34 (4~65) winsize 62
5090 20:12:16.267637 [CA 4] Center 33 (3~64) winsize 62
5091 20:12:16.270965 [CA 5] Center 33 (3~63) winsize 61
5092 20:12:16.271075
5093 20:12:16.274332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 20:12:16.274414
5095 20:12:16.277765 [CATrainingPosCal] consider 1 rank data
5096 20:12:16.281013 u2DelayCellTimex100 = 270/100 ps
5097 20:12:16.284342 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5098 20:12:16.287603 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5099 20:12:16.290945 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5100 20:12:16.294273 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5101 20:12:16.297796 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5102 20:12:16.303821 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5103 20:12:16.303903
5104 20:12:16.307196 CA PerBit enable=1, Macro0, CA PI delay=33
5105 20:12:16.307293
5106 20:12:16.310592 [CBTSetCACLKResult] CA Dly = 33
5107 20:12:16.310668 CS Dly: 5 (0~36)
5108 20:12:16.310730 ==
5109 20:12:16.314017 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 20:12:16.317161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 20:12:16.320523 ==
5112 20:12:16.323915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 20:12:16.330133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5114 20:12:16.333776 [CA 0] Center 37 (7~68) winsize 62
5115 20:12:16.337085 [CA 1] Center 37 (7~68) winsize 62
5116 20:12:16.340274 [CA 2] Center 34 (4~65) winsize 62
5117 20:12:16.343577 [CA 3] Center 34 (4~65) winsize 62
5118 20:12:16.346839 [CA 4] Center 33 (3~64) winsize 62
5119 20:12:16.350123 [CA 5] Center 32 (2~63) winsize 62
5120 20:12:16.350205
5121 20:12:16.353405 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5122 20:12:16.353487
5123 20:12:16.356465 [CATrainingPosCal] consider 2 rank data
5124 20:12:16.359766 u2DelayCellTimex100 = 270/100 ps
5125 20:12:16.363094 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5126 20:12:16.366587 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5127 20:12:16.372990 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5128 20:12:16.376460 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5129 20:12:16.379657 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5130 20:12:16.382757 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5131 20:12:16.382839
5132 20:12:16.387152 CA PerBit enable=1, Macro0, CA PI delay=33
5133 20:12:16.387234
5134 20:12:16.389695 [CBTSetCACLKResult] CA Dly = 33
5135 20:12:16.389847 CS Dly: 6 (0~39)
5136 20:12:16.393283
5137 20:12:16.396543 ----->DramcWriteLeveling(PI) begin...
5138 20:12:16.396626 ==
5139 20:12:16.399300 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 20:12:16.402624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 20:12:16.402707 ==
5142 20:12:16.405925 Write leveling (Byte 0): 34 => 34
5143 20:12:16.409376 Write leveling (Byte 1): 27 => 27
5144 20:12:16.412670 DramcWriteLeveling(PI) end<-----
5145 20:12:16.412751
5146 20:12:16.412816 ==
5147 20:12:16.416530 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 20:12:16.419274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 20:12:16.419381 ==
5150 20:12:16.422609 [Gating] SW mode calibration
5151 20:12:16.429076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 20:12:16.435406 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 20:12:16.438778 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5154 20:12:16.441993 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5155 20:12:16.448874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 20:12:16.451884 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 20:12:16.455336 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 20:12:16.461680 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 20:12:16.465599 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5160 20:12:16.468717 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5161 20:12:16.474800 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
5162 20:12:16.478510 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 20:12:16.481849 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 20:12:16.488276 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 20:12:16.491391 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 20:12:16.495165 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 20:12:16.501339 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 20:12:16.504848 0 15 28 | B1->B0 | 2424 3a3a | 0 1 | (0 0) (0 0)
5169 20:12:16.508049 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5170 20:12:16.514696 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 20:12:16.517776 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 20:12:16.521431 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 20:12:16.527821 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 20:12:16.531251 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 20:12:16.534332 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5176 20:12:16.540692 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5177 20:12:16.544304 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5178 20:12:16.547823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5179 20:12:16.554102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 20:12:16.557582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 20:12:16.560356 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 20:12:16.567441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 20:12:16.570439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 20:12:16.573831 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 20:12:16.580369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 20:12:16.583574 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 20:12:16.587016 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 20:12:16.593459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 20:12:16.596831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 20:12:16.600199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 20:12:16.606877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 20:12:16.610099 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 20:12:16.613255 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5194 20:12:16.616930 Total UI for P1: 0, mck2ui 16
5195 20:12:16.620227 best dqsien dly found for B0: ( 1, 2, 28)
5196 20:12:16.626462 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 20:12:16.629646 Total UI for P1: 0, mck2ui 16
5198 20:12:16.633252 best dqsien dly found for B1: ( 1, 3, 2)
5199 20:12:16.636196 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5200 20:12:16.639515 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5201 20:12:16.639640
5202 20:12:16.643249 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5203 20:12:16.646039 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5204 20:12:16.649646 [Gating] SW calibration Done
5205 20:12:16.649770 ==
5206 20:12:16.652719 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 20:12:16.656052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 20:12:16.656175 ==
5209 20:12:16.659084 RX Vref Scan: 0
5210 20:12:16.659205
5211 20:12:16.662334 RX Vref 0 -> 0, step: 1
5212 20:12:16.662454
5213 20:12:16.662567 RX Delay -80 -> 252, step: 8
5214 20:12:16.669311 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5215 20:12:16.672451 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5216 20:12:16.675742 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5217 20:12:16.678929 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5218 20:12:16.682222 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5219 20:12:16.686003 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5220 20:12:16.692393 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5221 20:12:16.695904 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5222 20:12:16.699016 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5223 20:12:16.702125 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5224 20:12:16.705694 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5225 20:12:16.711870 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5226 20:12:16.715682 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5227 20:12:16.719148 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5228 20:12:16.722286 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5229 20:12:16.725499 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5230 20:12:16.725576 ==
5231 20:12:16.728188 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 20:12:16.735095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 20:12:16.735174 ==
5234 20:12:16.735277 DQS Delay:
5235 20:12:16.738509 DQS0 = 0, DQS1 = 0
5236 20:12:16.738588 DQM Delay:
5237 20:12:16.741761 DQM0 = 100, DQM1 = 88
5238 20:12:16.741834 DQ Delay:
5239 20:12:16.745056 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5240 20:12:16.748392 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5241 20:12:16.751378 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5242 20:12:16.755042 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5243 20:12:16.755118
5244 20:12:16.755201
5245 20:12:16.755295 ==
5246 20:12:16.757983 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 20:12:16.761726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 20:12:16.761805 ==
5249 20:12:16.761886
5250 20:12:16.764985
5251 20:12:16.765065 TX Vref Scan disable
5252 20:12:16.768275 == TX Byte 0 ==
5253 20:12:16.771498 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5254 20:12:16.774932 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5255 20:12:16.778090 == TX Byte 1 ==
5256 20:12:16.781099 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5257 20:12:16.784324 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5258 20:12:16.784450 ==
5259 20:12:16.788023 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 20:12:16.794647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 20:12:16.794775 ==
5262 20:12:16.794888
5263 20:12:16.794996
5264 20:12:16.797864 TX Vref Scan disable
5265 20:12:16.797987 == TX Byte 0 ==
5266 20:12:16.803926 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5267 20:12:16.807095 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5268 20:12:16.807219 == TX Byte 1 ==
5269 20:12:16.813851 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5270 20:12:16.817656 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5271 20:12:16.817779
5272 20:12:16.817890 [DATLAT]
5273 20:12:16.820960 Freq=933, CH0 RK0
5274 20:12:16.821084
5275 20:12:16.821196 DATLAT Default: 0xd
5276 20:12:16.824199 0, 0xFFFF, sum = 0
5277 20:12:16.824304 1, 0xFFFF, sum = 0
5278 20:12:16.827153 2, 0xFFFF, sum = 0
5279 20:12:16.827252 3, 0xFFFF, sum = 0
5280 20:12:16.830663 4, 0xFFFF, sum = 0
5281 20:12:16.830763 5, 0xFFFF, sum = 0
5282 20:12:16.833647 6, 0xFFFF, sum = 0
5283 20:12:16.837225 7, 0xFFFF, sum = 0
5284 20:12:16.837308 8, 0xFFFF, sum = 0
5285 20:12:16.840457 9, 0xFFFF, sum = 0
5286 20:12:16.840541 10, 0x0, sum = 1
5287 20:12:16.843755 11, 0x0, sum = 2
5288 20:12:16.843838 12, 0x0, sum = 3
5289 20:12:16.843904 13, 0x0, sum = 4
5290 20:12:16.847071 best_step = 11
5291 20:12:16.847151
5292 20:12:16.847215 ==
5293 20:12:16.850200 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 20:12:16.853862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 20:12:16.853944 ==
5296 20:12:16.856983 RX Vref Scan: 1
5297 20:12:16.857064
5298 20:12:16.860232 RX Vref 0 -> 0, step: 1
5299 20:12:16.860341
5300 20:12:16.860469 RX Delay -61 -> 252, step: 4
5301 20:12:16.860558
5302 20:12:16.863343 Set Vref, RX VrefLevel [Byte0]: 54
5303 20:12:16.866497 [Byte1]: 59
5304 20:12:16.871178
5305 20:12:16.871263 Final RX Vref Byte 0 = 54 to rank0
5306 20:12:16.874497 Final RX Vref Byte 1 = 59 to rank0
5307 20:12:16.878229 Final RX Vref Byte 0 = 54 to rank1
5308 20:12:16.881281 Final RX Vref Byte 1 = 59 to rank1==
5309 20:12:16.884167 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 20:12:16.891259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 20:12:16.891391 ==
5312 20:12:16.891476 DQS Delay:
5313 20:12:16.894599 DQS0 = 0, DQS1 = 0
5314 20:12:16.894681 DQM Delay:
5315 20:12:16.894745 DQM0 = 98, DQM1 = 88
5316 20:12:16.897502 DQ Delay:
5317 20:12:16.900710 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5318 20:12:16.904009 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5319 20:12:16.907901 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5320 20:12:16.911198 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =92
5321 20:12:16.911281
5322 20:12:16.911346
5323 20:12:16.917139 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5324 20:12:16.920438 CH0 RK0: MR19=505, MR18=1610
5325 20:12:16.927180 CH0_RK0: MR19=0x505, MR18=0x1610, DQSOSC=414, MR23=63, INC=63, DEC=42
5326 20:12:16.927263
5327 20:12:16.930219 ----->DramcWriteLeveling(PI) begin...
5328 20:12:16.930302 ==
5329 20:12:16.934024 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 20:12:16.937106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 20:12:16.940161 ==
5332 20:12:16.940283 Write leveling (Byte 0): 31 => 31
5333 20:12:16.943997 Write leveling (Byte 1): 29 => 29
5334 20:12:16.946765 DramcWriteLeveling(PI) end<-----
5335 20:12:16.946871
5336 20:12:16.946949 ==
5337 20:12:16.950007 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 20:12:16.957032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 20:12:16.957115 ==
5340 20:12:16.957179 [Gating] SW mode calibration
5341 20:12:16.966755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 20:12:16.970063 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5343 20:12:16.976278 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5344 20:12:16.979776 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 20:12:16.983112 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 20:12:16.989742 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 20:12:16.992854 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 20:12:16.996042 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 20:12:17.002635 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5350 20:12:17.005917 0 14 28 | B1->B0 | 3333 2a2a | 1 1 | (1 1) (1 0)
5351 20:12:17.009382 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5352 20:12:17.016032 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5353 20:12:17.019342 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 20:12:17.022620 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 20:12:17.029175 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 20:12:17.032188 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 20:12:17.035510 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5358 20:12:17.042143 0 15 28 | B1->B0 | 2727 4343 | 0 1 | (0 0) (0 0)
5359 20:12:17.045354 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 20:12:17.049261 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 20:12:17.055543 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 20:12:17.058805 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 20:12:17.062051 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 20:12:17.068755 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 20:12:17.071869 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 20:12:17.075205 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5367 20:12:17.081881 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5368 20:12:17.084977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 20:12:17.088513 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 20:12:17.095052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 20:12:17.098248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 20:12:17.101450 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 20:12:17.108427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 20:12:17.111513 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 20:12:17.114791 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 20:12:17.121622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 20:12:17.125182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 20:12:17.127989 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 20:12:17.135129 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 20:12:17.138306 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 20:12:17.141438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 20:12:17.147857 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5383 20:12:17.151414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5384 20:12:17.154197 Total UI for P1: 0, mck2ui 16
5385 20:12:17.157934 best dqsien dly found for B0: ( 1, 2, 26)
5386 20:12:17.161338 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 20:12:17.164379 Total UI for P1: 0, mck2ui 16
5388 20:12:17.167418 best dqsien dly found for B1: ( 1, 2, 30)
5389 20:12:17.170894 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5390 20:12:17.174167 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5391 20:12:17.174249
5392 20:12:17.180618 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5393 20:12:17.183743 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5394 20:12:17.183826 [Gating] SW calibration Done
5395 20:12:17.187307 ==
5396 20:12:17.190461 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 20:12:17.193833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 20:12:17.193915 ==
5399 20:12:17.193978 RX Vref Scan: 0
5400 20:12:17.194038
5401 20:12:17.197464 RX Vref 0 -> 0, step: 1
5402 20:12:17.197546
5403 20:12:17.200721 RX Delay -80 -> 252, step: 8
5404 20:12:17.203890 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5405 20:12:17.207034 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5406 20:12:17.210144 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5407 20:12:17.216571 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5408 20:12:17.219820 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5409 20:12:17.223239 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5410 20:12:17.226413 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5411 20:12:17.230223 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5412 20:12:17.236466 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5413 20:12:17.239596 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5414 20:12:17.243222 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5415 20:12:17.246471 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5416 20:12:17.249678 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5417 20:12:17.253027 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5418 20:12:17.259679 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5419 20:12:17.263012 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5420 20:12:17.263108 ==
5421 20:12:17.266021 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 20:12:17.269929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 20:12:17.270011 ==
5424 20:12:17.272680 DQS Delay:
5425 20:12:17.272795 DQS0 = 0, DQS1 = 0
5426 20:12:17.272859 DQM Delay:
5427 20:12:17.276299 DQM0 = 97, DQM1 = 90
5428 20:12:17.276381 DQ Delay:
5429 20:12:17.279355 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5430 20:12:17.282551 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5431 20:12:17.285915 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5432 20:12:17.289227 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5433 20:12:17.289309
5434 20:12:17.289373
5435 20:12:17.289432 ==
5436 20:12:17.292415 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 20:12:17.299255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 20:12:17.299356 ==
5439 20:12:17.299447
5440 20:12:17.299508
5441 20:12:17.299566 TX Vref Scan disable
5442 20:12:17.302541 == TX Byte 0 ==
5443 20:12:17.306169 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5444 20:12:17.312680 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5445 20:12:17.312763 == TX Byte 1 ==
5446 20:12:17.316311 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5447 20:12:17.322465 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5448 20:12:17.322548 ==
5449 20:12:17.325799 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 20:12:17.329078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 20:12:17.329164 ==
5452 20:12:17.329229
5453 20:12:17.329288
5454 20:12:17.332763 TX Vref Scan disable
5455 20:12:17.332845 == TX Byte 0 ==
5456 20:12:17.339321 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5457 20:12:17.342518 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5458 20:12:17.342600 == TX Byte 1 ==
5459 20:12:17.349216 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5460 20:12:17.352634 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5461 20:12:17.352717
5462 20:12:17.352780 [DATLAT]
5463 20:12:17.355655 Freq=933, CH0 RK1
5464 20:12:17.355736
5465 20:12:17.355801 DATLAT Default: 0xb
5466 20:12:17.358769 0, 0xFFFF, sum = 0
5467 20:12:17.362154 1, 0xFFFF, sum = 0
5468 20:12:17.362238 2, 0xFFFF, sum = 0
5469 20:12:17.365547 3, 0xFFFF, sum = 0
5470 20:12:17.365630 4, 0xFFFF, sum = 0
5471 20:12:17.368664 5, 0xFFFF, sum = 0
5472 20:12:17.368748 6, 0xFFFF, sum = 0
5473 20:12:17.372107 7, 0xFFFF, sum = 0
5474 20:12:17.372191 8, 0xFFFF, sum = 0
5475 20:12:17.375556 9, 0xFFFF, sum = 0
5476 20:12:17.375639 10, 0x0, sum = 1
5477 20:12:17.379093 11, 0x0, sum = 2
5478 20:12:17.379174 12, 0x0, sum = 3
5479 20:12:17.381999 13, 0x0, sum = 4
5480 20:12:17.382089 best_step = 11
5481 20:12:17.382151
5482 20:12:17.382209 ==
5483 20:12:17.385189 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 20:12:17.388777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 20:12:17.391483 ==
5486 20:12:17.391558 RX Vref Scan: 0
5487 20:12:17.391619
5488 20:12:17.394927 RX Vref 0 -> 0, step: 1
5489 20:12:17.395030
5490 20:12:17.398417 RX Delay -53 -> 252, step: 4
5491 20:12:17.401746 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5492 20:12:17.404776 iDelay=199, Bit 1, Center 98 (7 ~ 190) 184
5493 20:12:17.407960 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5494 20:12:17.414685 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5495 20:12:17.418108 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5496 20:12:17.421309 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5497 20:12:17.424780 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5498 20:12:17.427807 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5499 20:12:17.434189 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5500 20:12:17.437773 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5501 20:12:17.441000 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5502 20:12:17.444395 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5503 20:12:17.447545 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5504 20:12:17.450887 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5505 20:12:17.457877 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5506 20:12:17.461017 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5507 20:12:17.461091 ==
5508 20:12:17.464009 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 20:12:17.467803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 20:12:17.467876 ==
5511 20:12:17.471015 DQS Delay:
5512 20:12:17.471116 DQS0 = 0, DQS1 = 0
5513 20:12:17.471210 DQM Delay:
5514 20:12:17.474259 DQM0 = 97, DQM1 = 89
5515 20:12:17.474329 DQ Delay:
5516 20:12:17.477392 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5517 20:12:17.480580 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5518 20:12:17.483793 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5519 20:12:17.487114 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =96
5520 20:12:17.487209
5521 20:12:17.487298
5522 20:12:17.497306 [DQSOSCAuto] RK1, (LSB)MR18= 0x120f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5523 20:12:17.500288 CH0 RK1: MR19=505, MR18=120F
5524 20:12:17.506872 CH0_RK1: MR19=0x505, MR18=0x120F, DQSOSC=416, MR23=63, INC=62, DEC=41
5525 20:12:17.506979 [RxdqsGatingPostProcess] freq 933
5526 20:12:17.513621 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5527 20:12:17.516723 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 20:12:17.520022 best DQS1 dly(2T, 0.5T) = (0, 11)
5529 20:12:17.523530 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 20:12:17.526713 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5531 20:12:17.530088 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 20:12:17.533335 best DQS1 dly(2T, 0.5T) = (0, 10)
5533 20:12:17.536467 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 20:12:17.540037 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5535 20:12:17.543182 Pre-setting of DQS Precalculation
5536 20:12:17.546458 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5537 20:12:17.546565 ==
5538 20:12:17.550117 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 20:12:17.556243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 20:12:17.556324 ==
5541 20:12:17.559370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 20:12:17.565862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5543 20:12:17.569844 [CA 0] Center 36 (6~67) winsize 62
5544 20:12:17.573038 [CA 1] Center 36 (6~67) winsize 62
5545 20:12:17.575953 [CA 2] Center 34 (4~65) winsize 62
5546 20:12:17.579636 [CA 3] Center 33 (3~64) winsize 62
5547 20:12:17.582692 [CA 4] Center 33 (3~64) winsize 62
5548 20:12:17.586309 [CA 5] Center 33 (3~64) winsize 62
5549 20:12:17.586432
5550 20:12:17.589000 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5551 20:12:17.589121
5552 20:12:17.592321 [CATrainingPosCal] consider 1 rank data
5553 20:12:17.596204 u2DelayCellTimex100 = 270/100 ps
5554 20:12:17.599064 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5555 20:12:17.605483 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5556 20:12:17.608810 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5557 20:12:17.612334 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 20:12:17.615775 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 20:12:17.618891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 20:12:17.619013
5561 20:12:17.622312 CA PerBit enable=1, Macro0, CA PI delay=33
5562 20:12:17.622436
5563 20:12:17.625471 [CBTSetCACLKResult] CA Dly = 33
5564 20:12:17.629067 CS Dly: 4 (0~35)
5565 20:12:17.629147 ==
5566 20:12:17.632128 Dram Type= 6, Freq= 0, CH_1, rank 1
5567 20:12:17.635496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 20:12:17.635580 ==
5569 20:12:17.642160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 20:12:17.645127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5571 20:12:17.649099 [CA 0] Center 36 (6~67) winsize 62
5572 20:12:17.652208 [CA 1] Center 36 (6~67) winsize 62
5573 20:12:17.655537 [CA 2] Center 34 (4~65) winsize 62
5574 20:12:17.658959 [CA 3] Center 33 (3~64) winsize 62
5575 20:12:17.662263 [CA 4] Center 33 (3~64) winsize 62
5576 20:12:17.665293 [CA 5] Center 33 (3~64) winsize 62
5577 20:12:17.665412
5578 20:12:17.668825 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5579 20:12:17.668947
5580 20:12:17.672027 [CATrainingPosCal] consider 2 rank data
5581 20:12:17.675226 u2DelayCellTimex100 = 270/100 ps
5582 20:12:17.678614 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 20:12:17.685139 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5584 20:12:17.688726 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5585 20:12:17.691613 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5586 20:12:17.694906 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 20:12:17.698390 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5588 20:12:17.698509
5589 20:12:17.702050 CA PerBit enable=1, Macro0, CA PI delay=33
5590 20:12:17.702172
5591 20:12:17.705289 [CBTSetCACLKResult] CA Dly = 33
5592 20:12:17.708526 CS Dly: 5 (0~37)
5593 20:12:17.708646
5594 20:12:17.711906 ----->DramcWriteLeveling(PI) begin...
5595 20:12:17.712028 ==
5596 20:12:17.715063 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 20:12:17.718129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 20:12:17.718250 ==
5599 20:12:17.721618 Write leveling (Byte 0): 27 => 27
5600 20:12:17.724821 Write leveling (Byte 1): 27 => 27
5601 20:12:17.728086 DramcWriteLeveling(PI) end<-----
5602 20:12:17.728209
5603 20:12:17.728320 ==
5604 20:12:17.731657 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 20:12:17.735055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 20:12:17.735176 ==
5607 20:12:17.738046 [Gating] SW mode calibration
5608 20:12:17.744481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5609 20:12:17.751536 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5610 20:12:17.754752 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 20:12:17.757774 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 20:12:17.764555 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 20:12:17.767542 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 20:12:17.770890 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 20:12:17.777794 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 20:12:17.780784 0 14 24 | B1->B0 | 3232 3232 | 1 1 | (1 1) (1 1)
5617 20:12:17.787291 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (1 0)
5618 20:12:17.790423 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 20:12:17.793690 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 20:12:17.800353 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 20:12:17.803741 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 20:12:17.806718 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 20:12:17.813545 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 20:12:17.816683 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5625 20:12:17.820109 0 15 28 | B1->B0 | 3636 3a3a | 0 0 | (0 0) (0 0)
5626 20:12:17.826989 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 20:12:17.829897 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 20:12:17.833490 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 20:12:17.840234 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 20:12:17.843232 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 20:12:17.846553 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 20:12:17.853018 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5633 20:12:17.856561 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5634 20:12:17.859939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5635 20:12:17.866015 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 20:12:17.869319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 20:12:17.872850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 20:12:17.879563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 20:12:17.882404 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 20:12:17.885739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 20:12:17.892406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 20:12:17.895913 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 20:12:17.898820 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 20:12:17.905626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 20:12:17.909020 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 20:12:17.911916 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 20:12:17.918783 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 20:12:17.922176 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5649 20:12:17.925167 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5650 20:12:17.932386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 20:12:17.932468 Total UI for P1: 0, mck2ui 16
5652 20:12:17.938438 best dqsien dly found for B0: ( 1, 2, 26)
5653 20:12:17.938520 Total UI for P1: 0, mck2ui 16
5654 20:12:17.944809 best dqsien dly found for B1: ( 1, 2, 26)
5655 20:12:17.948408 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5656 20:12:17.951527 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5657 20:12:17.951609
5658 20:12:17.954894 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5659 20:12:17.958393 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5660 20:12:17.961649 [Gating] SW calibration Done
5661 20:12:17.961731 ==
5662 20:12:17.964788 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 20:12:17.968184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 20:12:17.968266 ==
5665 20:12:17.971295 RX Vref Scan: 0
5666 20:12:17.971402
5667 20:12:17.971480 RX Vref 0 -> 0, step: 1
5668 20:12:17.974339
5669 20:12:17.974419 RX Delay -80 -> 252, step: 8
5670 20:12:17.981004 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5671 20:12:17.984590 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5672 20:12:17.987762 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5673 20:12:17.990837 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5674 20:12:17.994564 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5675 20:12:17.998229 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5676 20:12:18.003966 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5677 20:12:18.007269 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5678 20:12:18.010622 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5679 20:12:18.013811 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5680 20:12:18.017449 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5681 20:12:18.024212 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5682 20:12:18.027191 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5683 20:12:18.030527 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5684 20:12:18.033697 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5685 20:12:18.036975 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5686 20:12:18.037094 ==
5687 20:12:18.040182 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 20:12:18.047081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 20:12:18.047203 ==
5690 20:12:18.047314 DQS Delay:
5691 20:12:18.049981 DQS0 = 0, DQS1 = 0
5692 20:12:18.050100 DQM Delay:
5693 20:12:18.053458 DQM0 = 99, DQM1 = 95
5694 20:12:18.053577 DQ Delay:
5695 20:12:18.056513 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5696 20:12:18.060447 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5697 20:12:18.063284 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5698 20:12:18.066704 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5699 20:12:18.066786
5700 20:12:18.066849
5701 20:12:18.066908 ==
5702 20:12:18.070227 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 20:12:18.073266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 20:12:18.076417 ==
5705 20:12:18.076498
5706 20:12:18.076562
5707 20:12:18.076621 TX Vref Scan disable
5708 20:12:18.079697 == TX Byte 0 ==
5709 20:12:18.082970 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5710 20:12:18.086411 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5711 20:12:18.089480 == TX Byte 1 ==
5712 20:12:18.092865 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5713 20:12:18.096182 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5714 20:12:18.099667 ==
5715 20:12:18.102807 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 20:12:18.106216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 20:12:18.106322 ==
5718 20:12:18.106400
5719 20:12:18.106458
5720 20:12:18.109240 TX Vref Scan disable
5721 20:12:18.109366 == TX Byte 0 ==
5722 20:12:18.116196 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5723 20:12:18.119515 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5724 20:12:18.119637 == TX Byte 1 ==
5725 20:12:18.125810 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5726 20:12:18.129364 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5727 20:12:18.129487
5728 20:12:18.129598 [DATLAT]
5729 20:12:18.132474 Freq=933, CH1 RK0
5730 20:12:18.132595
5731 20:12:18.132704 DATLAT Default: 0xd
5732 20:12:18.135786 0, 0xFFFF, sum = 0
5733 20:12:18.135910 1, 0xFFFF, sum = 0
5734 20:12:18.139131 2, 0xFFFF, sum = 0
5735 20:12:18.139253 3, 0xFFFF, sum = 0
5736 20:12:18.142391 4, 0xFFFF, sum = 0
5737 20:12:18.145754 5, 0xFFFF, sum = 0
5738 20:12:18.145875 6, 0xFFFF, sum = 0
5739 20:12:18.148827 7, 0xFFFF, sum = 0
5740 20:12:18.148949 8, 0xFFFF, sum = 0
5741 20:12:18.151930 9, 0xFFFF, sum = 0
5742 20:12:18.152049 10, 0x0, sum = 1
5743 20:12:18.155734 11, 0x0, sum = 2
5744 20:12:18.155885 12, 0x0, sum = 3
5745 20:12:18.158891 13, 0x0, sum = 4
5746 20:12:18.159012 best_step = 11
5747 20:12:18.159121
5748 20:12:18.159229 ==
5749 20:12:18.162097 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 20:12:18.165407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 20:12:18.165530 ==
5752 20:12:18.168711 RX Vref Scan: 1
5753 20:12:18.168831
5754 20:12:18.171999 RX Vref 0 -> 0, step: 1
5755 20:12:18.172120
5756 20:12:18.172231 RX Delay -53 -> 252, step: 4
5757 20:12:18.172337
5758 20:12:18.175465 Set Vref, RX VrefLevel [Byte0]: 51
5759 20:12:18.178527 [Byte1]: 51
5760 20:12:18.182986
5761 20:12:18.183109 Final RX Vref Byte 0 = 51 to rank0
5762 20:12:18.186385 Final RX Vref Byte 1 = 51 to rank0
5763 20:12:18.190042 Final RX Vref Byte 0 = 51 to rank1
5764 20:12:18.193322 Final RX Vref Byte 1 = 51 to rank1==
5765 20:12:18.196438 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 20:12:18.203284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 20:12:18.203371 ==
5768 20:12:18.203435 DQS Delay:
5769 20:12:18.206369 DQS0 = 0, DQS1 = 0
5770 20:12:18.206480 DQM Delay:
5771 20:12:18.206574 DQM0 = 98, DQM1 = 94
5772 20:12:18.209429 DQ Delay:
5773 20:12:18.212559 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =100
5774 20:12:18.215974 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5775 20:12:18.219671 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5776 20:12:18.222400 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5777 20:12:18.222481
5778 20:12:18.222543
5779 20:12:18.229549 [DQSOSCAuto] RK0, (LSB)MR18= 0x414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5780 20:12:18.232677 CH1 RK0: MR19=505, MR18=414
5781 20:12:18.239338 CH1_RK0: MR19=0x505, MR18=0x414, DQSOSC=415, MR23=63, INC=62, DEC=41
5782 20:12:18.239437
5783 20:12:18.242650 ----->DramcWriteLeveling(PI) begin...
5784 20:12:18.242736 ==
5785 20:12:18.245857 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 20:12:18.249153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 20:12:18.249239 ==
5788 20:12:18.252565 Write leveling (Byte 0): 26 => 26
5789 20:12:18.255656 Write leveling (Byte 1): 28 => 28
5790 20:12:18.259309 DramcWriteLeveling(PI) end<-----
5791 20:12:18.259417
5792 20:12:18.259520 ==
5793 20:12:18.262292 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 20:12:18.268890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 20:12:18.268975 ==
5796 20:12:18.269061 [Gating] SW mode calibration
5797 20:12:18.278859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5798 20:12:18.282035 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5799 20:12:18.288786 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 20:12:18.291884 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 20:12:18.295111 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 20:12:18.301703 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 20:12:18.304929 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 20:12:18.308388 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 20:12:18.315325 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5806 20:12:18.318505 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5807 20:12:18.321608 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 20:12:18.328415 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 20:12:18.331262 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 20:12:18.334730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 20:12:18.341199 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 20:12:18.344628 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 20:12:18.347987 0 15 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (1 1)
5814 20:12:18.354480 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5815 20:12:18.357813 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 20:12:18.361225 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 20:12:18.367402 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 20:12:18.370947 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 20:12:18.374250 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 20:12:18.381003 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 20:12:18.383857 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5822 20:12:18.387297 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5823 20:12:18.393956 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 20:12:18.397158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 20:12:18.400377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 20:12:18.407128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 20:12:18.410300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 20:12:18.413468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 20:12:18.419919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 20:12:18.423763 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 20:12:18.426812 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 20:12:18.433420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 20:12:18.436432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 20:12:18.440100 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 20:12:18.446230 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 20:12:18.450006 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 20:12:18.453348 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5838 20:12:18.459774 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5839 20:12:18.459860 Total UI for P1: 0, mck2ui 16
5840 20:12:18.466380 best dqsien dly found for B0: ( 1, 2, 24)
5841 20:12:18.469620 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 20:12:18.472884 Total UI for P1: 0, mck2ui 16
5843 20:12:18.476345 best dqsien dly found for B1: ( 1, 2, 26)
5844 20:12:18.479536 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5845 20:12:18.482525 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5846 20:12:18.482611
5847 20:12:18.485767 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5848 20:12:18.489694 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5849 20:12:18.492375 [Gating] SW calibration Done
5850 20:12:18.492485 ==
5851 20:12:18.495901 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 20:12:18.502512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 20:12:18.502596 ==
5854 20:12:18.502661 RX Vref Scan: 0
5855 20:12:18.502721
5856 20:12:18.505564 RX Vref 0 -> 0, step: 1
5857 20:12:18.505646
5858 20:12:18.508937 RX Delay -80 -> 252, step: 8
5859 20:12:18.512358 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5860 20:12:18.515640 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5861 20:12:18.518986 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5862 20:12:18.522290 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5863 20:12:18.528628 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5864 20:12:18.532826 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5865 20:12:18.535813 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5866 20:12:18.539064 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5867 20:12:18.541994 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5868 20:12:18.545086 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5869 20:12:18.551786 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5870 20:12:18.555029 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5871 20:12:18.558953 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5872 20:12:18.561648 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5873 20:12:18.564770 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5874 20:12:18.571544 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5875 20:12:18.571652 ==
5876 20:12:18.575000 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 20:12:18.578383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 20:12:18.578466 ==
5879 20:12:18.578530 DQS Delay:
5880 20:12:18.581569 DQS0 = 0, DQS1 = 0
5881 20:12:18.581651 DQM Delay:
5882 20:12:18.584704 DQM0 = 97, DQM1 = 94
5883 20:12:18.584786 DQ Delay:
5884 20:12:18.587888 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5885 20:12:18.591587 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5886 20:12:18.594821 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5887 20:12:18.598313 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5888 20:12:18.598398
5889 20:12:18.598484
5890 20:12:18.598565 ==
5891 20:12:18.601204 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 20:12:18.607497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 20:12:18.607583 ==
5894 20:12:18.607669
5895 20:12:18.607750
5896 20:12:18.607827 TX Vref Scan disable
5897 20:12:18.610914 == TX Byte 0 ==
5898 20:12:18.614525 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5899 20:12:18.621095 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5900 20:12:18.621193 == TX Byte 1 ==
5901 20:12:18.624331 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5902 20:12:18.630876 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5903 20:12:18.630961 ==
5904 20:12:18.634247 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 20:12:18.637513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 20:12:18.637598 ==
5907 20:12:18.637684
5908 20:12:18.637764
5909 20:12:18.640821 TX Vref Scan disable
5910 20:12:18.644492 == TX Byte 0 ==
5911 20:12:18.647275 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5912 20:12:18.650424 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5913 20:12:18.653669 == TX Byte 1 ==
5914 20:12:18.656920 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 20:12:18.660214 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 20:12:18.660297
5917 20:12:18.660383 [DATLAT]
5918 20:12:18.663400 Freq=933, CH1 RK1
5919 20:12:18.663488
5920 20:12:18.666800 DATLAT Default: 0xb
5921 20:12:18.666922 0, 0xFFFF, sum = 0
5922 20:12:18.670045 1, 0xFFFF, sum = 0
5923 20:12:18.670125 2, 0xFFFF, sum = 0
5924 20:12:18.673625 3, 0xFFFF, sum = 0
5925 20:12:18.673699 4, 0xFFFF, sum = 0
5926 20:12:18.677073 5, 0xFFFF, sum = 0
5927 20:12:18.677147 6, 0xFFFF, sum = 0
5928 20:12:18.679930 7, 0xFFFF, sum = 0
5929 20:12:18.680002 8, 0xFFFF, sum = 0
5930 20:12:18.683722 9, 0xFFFF, sum = 0
5931 20:12:18.683809 10, 0x0, sum = 1
5932 20:12:18.686540 11, 0x0, sum = 2
5933 20:12:18.686626 12, 0x0, sum = 3
5934 20:12:18.690126 13, 0x0, sum = 4
5935 20:12:18.690213 best_step = 11
5936 20:12:18.690298
5937 20:12:18.690379 ==
5938 20:12:18.693351 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 20:12:18.696460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 20:12:18.699901 ==
5941 20:12:18.699986 RX Vref Scan: 0
5942 20:12:18.700072
5943 20:12:18.703108 RX Vref 0 -> 0, step: 1
5944 20:12:18.703193
5945 20:12:18.706793 RX Delay -53 -> 252, step: 4
5946 20:12:18.710060 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5947 20:12:18.713250 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5948 20:12:18.719696 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5949 20:12:18.722956 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5950 20:12:18.726252 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5951 20:12:18.729582 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5952 20:12:18.732783 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5953 20:12:18.736079 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5954 20:12:18.742962 iDelay=203, Bit 8, Center 82 (-5 ~ 170) 176
5955 20:12:18.746106 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5956 20:12:18.749221 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5957 20:12:18.752938 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5958 20:12:18.755775 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5959 20:12:18.762444 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5960 20:12:18.766203 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5961 20:12:18.769297 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5962 20:12:18.769378 ==
5963 20:12:18.772419 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 20:12:18.775776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 20:12:18.775858 ==
5966 20:12:18.778906 DQS Delay:
5967 20:12:18.778986 DQS0 = 0, DQS1 = 0
5968 20:12:18.782263 DQM Delay:
5969 20:12:18.782343 DQM0 = 97, DQM1 = 92
5970 20:12:18.782406 DQ Delay:
5971 20:12:18.785959 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5972 20:12:18.788903 DQ4 =96, DQ5 =108, DQ6 =102, DQ7 =94
5973 20:12:18.791936 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =86
5974 20:12:18.799168 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5975 20:12:18.799250
5976 20:12:18.799312
5977 20:12:18.805213 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5978 20:12:18.808977 CH1 RK1: MR19=505, MR18=A21
5979 20:12:18.815082 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5980 20:12:18.818570 [RxdqsGatingPostProcess] freq 933
5981 20:12:18.821827 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5982 20:12:18.824845 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 20:12:18.828247 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 20:12:18.831579 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 20:12:18.834808 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 20:12:18.837980 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 20:12:18.841258 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 20:12:18.844506 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 20:12:18.848067 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 20:12:18.850993 Pre-setting of DQS Precalculation
5991 20:12:18.854300 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5992 20:12:18.864351 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5993 20:12:18.870916 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5994 20:12:18.871004
5995 20:12:18.871068
5996 20:12:18.874299 [Calibration Summary] 1866 Mbps
5997 20:12:18.874383 CH 0, Rank 0
5998 20:12:18.877724 SW Impedance : PASS
5999 20:12:18.877805 DUTY Scan : NO K
6000 20:12:18.880716 ZQ Calibration : PASS
6001 20:12:18.884026 Jitter Meter : NO K
6002 20:12:18.884107 CBT Training : PASS
6003 20:12:18.887211 Write leveling : PASS
6004 20:12:18.890900 RX DQS gating : PASS
6005 20:12:18.890981 RX DQ/DQS(RDDQC) : PASS
6006 20:12:18.894007 TX DQ/DQS : PASS
6007 20:12:18.897623 RX DATLAT : PASS
6008 20:12:18.897704 RX DQ/DQS(Engine): PASS
6009 20:12:18.900485 TX OE : NO K
6010 20:12:18.900574 All Pass.
6011 20:12:18.900697
6012 20:12:18.904244 CH 0, Rank 1
6013 20:12:18.904325 SW Impedance : PASS
6014 20:12:18.907265 DUTY Scan : NO K
6015 20:12:18.910533 ZQ Calibration : PASS
6016 20:12:18.910614 Jitter Meter : NO K
6017 20:12:18.914036 CBT Training : PASS
6018 20:12:18.917380 Write leveling : PASS
6019 20:12:18.917464 RX DQS gating : PASS
6020 20:12:18.920979 RX DQ/DQS(RDDQC) : PASS
6021 20:12:18.923893 TX DQ/DQS : PASS
6022 20:12:18.923980 RX DATLAT : PASS
6023 20:12:18.927287 RX DQ/DQS(Engine): PASS
6024 20:12:18.930227 TX OE : NO K
6025 20:12:18.930333 All Pass.
6026 20:12:18.930424
6027 20:12:18.930510 CH 1, Rank 0
6028 20:12:18.933602 SW Impedance : PASS
6029 20:12:18.937124 DUTY Scan : NO K
6030 20:12:18.937205 ZQ Calibration : PASS
6031 20:12:18.940413 Jitter Meter : NO K
6032 20:12:18.943813 CBT Training : PASS
6033 20:12:18.943893 Write leveling : PASS
6034 20:12:18.946670 RX DQS gating : PASS
6035 20:12:18.946754 RX DQ/DQS(RDDQC) : PASS
6036 20:12:18.950219 TX DQ/DQS : PASS
6037 20:12:18.953373 RX DATLAT : PASS
6038 20:12:18.953456 RX DQ/DQS(Engine): PASS
6039 20:12:18.956782 TX OE : NO K
6040 20:12:18.956864 All Pass.
6041 20:12:18.956948
6042 20:12:18.959943 CH 1, Rank 1
6043 20:12:18.960027 SW Impedance : PASS
6044 20:12:18.963403 DUTY Scan : NO K
6045 20:12:18.966976 ZQ Calibration : PASS
6046 20:12:18.967058 Jitter Meter : NO K
6047 20:12:18.969907 CBT Training : PASS
6048 20:12:18.973273 Write leveling : PASS
6049 20:12:18.973355 RX DQS gating : PASS
6050 20:12:18.976379 RX DQ/DQS(RDDQC) : PASS
6051 20:12:18.980114 TX DQ/DQS : PASS
6052 20:12:18.980197 RX DATLAT : PASS
6053 20:12:18.983570 RX DQ/DQS(Engine): PASS
6054 20:12:18.986129 TX OE : NO K
6055 20:12:18.986212 All Pass.
6056 20:12:18.986276
6057 20:12:18.989615 DramC Write-DBI off
6058 20:12:18.989713 PER_BANK_REFRESH: Hybrid Mode
6059 20:12:18.992651 TX_TRACKING: ON
6060 20:12:18.999357 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6061 20:12:19.006065 [FAST_K] Save calibration result to emmc
6062 20:12:19.009453 dramc_set_vcore_voltage set vcore to 650000
6063 20:12:19.009544 Read voltage for 400, 6
6064 20:12:19.012917 Vio18 = 0
6065 20:12:19.012999 Vcore = 650000
6066 20:12:19.013063 Vdram = 0
6067 20:12:19.016218 Vddq = 0
6068 20:12:19.016302 Vmddr = 0
6069 20:12:19.019587 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6070 20:12:19.025631 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6071 20:12:19.029514 MEM_TYPE=3, freq_sel=20
6072 20:12:19.032712 sv_algorithm_assistance_LP4_800
6073 20:12:19.035849 ============ PULL DRAM RESETB DOWN ============
6074 20:12:19.039352 ========== PULL DRAM RESETB DOWN end =========
6075 20:12:19.045481 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6076 20:12:19.049011 ===================================
6077 20:12:19.049093 LPDDR4 DRAM CONFIGURATION
6078 20:12:19.052225 ===================================
6079 20:12:19.055410 EX_ROW_EN[0] = 0x0
6080 20:12:19.055508 EX_ROW_EN[1] = 0x0
6081 20:12:19.058960 LP4Y_EN = 0x0
6082 20:12:19.062190 WORK_FSP = 0x0
6083 20:12:19.062273 WL = 0x2
6084 20:12:19.065657 RL = 0x2
6085 20:12:19.065740 BL = 0x2
6086 20:12:19.068743 RPST = 0x0
6087 20:12:19.068825 RD_PRE = 0x0
6088 20:12:19.071995 WR_PRE = 0x1
6089 20:12:19.072077 WR_PST = 0x0
6090 20:12:19.075207 DBI_WR = 0x0
6091 20:12:19.075315 DBI_RD = 0x0
6092 20:12:19.078926 OTF = 0x1
6093 20:12:19.082603 ===================================
6094 20:12:19.085283 ===================================
6095 20:12:19.085365 ANA top config
6096 20:12:19.088445 ===================================
6097 20:12:19.092128 DLL_ASYNC_EN = 0
6098 20:12:19.095011 ALL_SLAVE_EN = 1
6099 20:12:19.095094 NEW_RANK_MODE = 1
6100 20:12:19.098552 DLL_IDLE_MODE = 1
6101 20:12:19.101858 LP45_APHY_COMB_EN = 1
6102 20:12:19.104990 TX_ODT_DIS = 1
6103 20:12:19.108700 NEW_8X_MODE = 1
6104 20:12:19.112108 ===================================
6105 20:12:19.115227 ===================================
6106 20:12:19.118467 data_rate = 800
6107 20:12:19.118553 CKR = 1
6108 20:12:19.121864 DQ_P2S_RATIO = 4
6109 20:12:19.125009 ===================================
6110 20:12:19.128036 CA_P2S_RATIO = 4
6111 20:12:19.131872 DQ_CA_OPEN = 0
6112 20:12:19.135244 DQ_SEMI_OPEN = 1
6113 20:12:19.137880 CA_SEMI_OPEN = 1
6114 20:12:19.137954 CA_FULL_RATE = 0
6115 20:12:19.141668 DQ_CKDIV4_EN = 0
6116 20:12:19.144870 CA_CKDIV4_EN = 1
6117 20:12:19.147939 CA_PREDIV_EN = 0
6118 20:12:19.151338 PH8_DLY = 0
6119 20:12:19.154491 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6120 20:12:19.154573 DQ_AAMCK_DIV = 0
6121 20:12:19.157848 CA_AAMCK_DIV = 0
6122 20:12:19.161381 CA_ADMCK_DIV = 4
6123 20:12:19.164720 DQ_TRACK_CA_EN = 0
6124 20:12:19.167712 CA_PICK = 800
6125 20:12:19.171118 CA_MCKIO = 400
6126 20:12:19.174598 MCKIO_SEMI = 400
6127 20:12:19.174679 PLL_FREQ = 3016
6128 20:12:19.177595 DQ_UI_PI_RATIO = 32
6129 20:12:19.181102 CA_UI_PI_RATIO = 32
6130 20:12:19.184359 ===================================
6131 20:12:19.187845 ===================================
6132 20:12:19.191084 memory_type:LPDDR4
6133 20:12:19.194409 GP_NUM : 10
6134 20:12:19.194489 SRAM_EN : 1
6135 20:12:19.197853 MD32_EN : 0
6136 20:12:19.201058 ===================================
6137 20:12:19.201140 [ANA_INIT] >>>>>>>>>>>>>>
6138 20:12:19.204300 <<<<<< [CONFIGURE PHASE]: ANA_TX
6139 20:12:19.207573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6140 20:12:19.210674 ===================================
6141 20:12:19.213924 data_rate = 800,PCW = 0X7400
6142 20:12:19.216993 ===================================
6143 20:12:19.220494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6144 20:12:19.226963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 20:12:19.237290 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6146 20:12:19.243702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6147 20:12:19.246992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6148 20:12:19.249952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6149 20:12:19.253086 [ANA_INIT] flow start
6150 20:12:19.253168 [ANA_INIT] PLL >>>>>>>>
6151 20:12:19.256555 [ANA_INIT] PLL <<<<<<<<
6152 20:12:19.260108 [ANA_INIT] MIDPI >>>>>>>>
6153 20:12:19.260226 [ANA_INIT] MIDPI <<<<<<<<
6154 20:12:19.263326 [ANA_INIT] DLL >>>>>>>>
6155 20:12:19.266256 [ANA_INIT] flow end
6156 20:12:19.269734 ============ LP4 DIFF to SE enter ============
6157 20:12:19.273102 ============ LP4 DIFF to SE exit ============
6158 20:12:19.276751 [ANA_INIT] <<<<<<<<<<<<<
6159 20:12:19.279779 [Flow] Enable top DCM control >>>>>
6160 20:12:19.282890 [Flow] Enable top DCM control <<<<<
6161 20:12:19.286019 Enable DLL master slave shuffle
6162 20:12:19.289459 ==============================================================
6163 20:12:19.292988 Gating Mode config
6164 20:12:19.299306 ==============================================================
6165 20:12:19.299437 Config description:
6166 20:12:19.309138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6167 20:12:19.316080 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6168 20:12:19.322145 SELPH_MODE 0: By rank 1: By Phase
6169 20:12:19.325780 ==============================================================
6170 20:12:19.328999 GAT_TRACK_EN = 0
6171 20:12:19.332379 RX_GATING_MODE = 2
6172 20:12:19.335716 RX_GATING_TRACK_MODE = 2
6173 20:12:19.338739 SELPH_MODE = 1
6174 20:12:19.342016 PICG_EARLY_EN = 1
6175 20:12:19.345353 VALID_LAT_VALUE = 1
6176 20:12:19.351955 ==============================================================
6177 20:12:19.355050 Enter into Gating configuration >>>>
6178 20:12:19.358333 Exit from Gating configuration <<<<
6179 20:12:19.358414 Enter into DVFS_PRE_config >>>>>
6180 20:12:19.371689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6181 20:12:19.374964 Exit from DVFS_PRE_config <<<<<
6182 20:12:19.377992 Enter into PICG configuration >>>>
6183 20:12:19.381406 Exit from PICG configuration <<<<
6184 20:12:19.384692 [RX_INPUT] configuration >>>>>
6185 20:12:19.384792 [RX_INPUT] configuration <<<<<
6186 20:12:19.391234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6187 20:12:19.397884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6188 20:12:19.401477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 20:12:19.407802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 20:12:19.414520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 20:12:19.421221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 20:12:19.424007 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6193 20:12:19.427309 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6194 20:12:19.434072 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6195 20:12:19.437237 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6196 20:12:19.440428 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6197 20:12:19.447076 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 20:12:19.450761 ===================================
6199 20:12:19.450832 LPDDR4 DRAM CONFIGURATION
6200 20:12:19.454078 ===================================
6201 20:12:19.457144 EX_ROW_EN[0] = 0x0
6202 20:12:19.460027 EX_ROW_EN[1] = 0x0
6203 20:12:19.460100 LP4Y_EN = 0x0
6204 20:12:19.463857 WORK_FSP = 0x0
6205 20:12:19.463925 WL = 0x2
6206 20:12:19.466589 RL = 0x2
6207 20:12:19.466660 BL = 0x2
6208 20:12:19.469860 RPST = 0x0
6209 20:12:19.469928 RD_PRE = 0x0
6210 20:12:19.473513 WR_PRE = 0x1
6211 20:12:19.473596 WR_PST = 0x0
6212 20:12:19.477049 DBI_WR = 0x0
6213 20:12:19.477131 DBI_RD = 0x0
6214 20:12:19.480205 OTF = 0x1
6215 20:12:19.483249 ===================================
6216 20:12:19.486464 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6217 20:12:19.490044 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6218 20:12:19.496337 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 20:12:19.499823 ===================================
6220 20:12:19.499905 LPDDR4 DRAM CONFIGURATION
6221 20:12:19.502876 ===================================
6222 20:12:19.506229 EX_ROW_EN[0] = 0x10
6223 20:12:19.509466 EX_ROW_EN[1] = 0x0
6224 20:12:19.509548 LP4Y_EN = 0x0
6225 20:12:19.513008 WORK_FSP = 0x0
6226 20:12:19.513091 WL = 0x2
6227 20:12:19.516591 RL = 0x2
6228 20:12:19.516675 BL = 0x2
6229 20:12:19.519531 RPST = 0x0
6230 20:12:19.519607 RD_PRE = 0x0
6231 20:12:19.523338 WR_PRE = 0x1
6232 20:12:19.523454 WR_PST = 0x0
6233 20:12:19.526058 DBI_WR = 0x0
6234 20:12:19.526128 DBI_RD = 0x0
6235 20:12:19.529421 OTF = 0x1
6236 20:12:19.532977 ===================================
6237 20:12:19.539305 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6238 20:12:19.542549 nWR fixed to 30
6239 20:12:19.545776 [ModeRegInit_LP4] CH0 RK0
6240 20:12:19.545850 [ModeRegInit_LP4] CH0 RK1
6241 20:12:19.549451 [ModeRegInit_LP4] CH1 RK0
6242 20:12:19.552328 [ModeRegInit_LP4] CH1 RK1
6243 20:12:19.552403 match AC timing 19
6244 20:12:19.558996 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6245 20:12:19.562356 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6246 20:12:19.565992 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6247 20:12:19.572505 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6248 20:12:19.575398 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6249 20:12:19.575483 ==
6250 20:12:19.579113 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 20:12:19.582162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 20:12:19.582234 ==
6253 20:12:19.588902 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 20:12:19.595743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6255 20:12:19.598737 [CA 0] Center 36 (8~64) winsize 57
6256 20:12:19.602152 [CA 1] Center 36 (8~64) winsize 57
6257 20:12:19.605414 [CA 2] Center 36 (8~64) winsize 57
6258 20:12:19.608716 [CA 3] Center 36 (8~64) winsize 57
6259 20:12:19.612021 [CA 4] Center 36 (8~64) winsize 57
6260 20:12:19.615116 [CA 5] Center 36 (8~64) winsize 57
6261 20:12:19.615197
6262 20:12:19.618269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6263 20:12:19.618350
6264 20:12:19.621598 [CATrainingPosCal] consider 1 rank data
6265 20:12:19.625273 u2DelayCellTimex100 = 270/100 ps
6266 20:12:19.628224 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 20:12:19.631445 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 20:12:19.634741 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 20:12:19.638278 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 20:12:19.641192 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 20:12:19.644709 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 20:12:19.644785
6273 20:12:19.650911 CA PerBit enable=1, Macro0, CA PI delay=36
6274 20:12:19.650987
6275 20:12:19.651048 [CBTSetCACLKResult] CA Dly = 36
6276 20:12:19.654510 CS Dly: 1 (0~32)
6277 20:12:19.654586 ==
6278 20:12:19.657867 Dram Type= 6, Freq= 0, CH_0, rank 1
6279 20:12:19.661367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 20:12:19.661441 ==
6281 20:12:19.667596 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6282 20:12:19.674611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6283 20:12:19.677685 [CA 0] Center 36 (8~64) winsize 57
6284 20:12:19.681066 [CA 1] Center 36 (8~64) winsize 57
6285 20:12:19.684428 [CA 2] Center 36 (8~64) winsize 57
6286 20:12:19.687369 [CA 3] Center 36 (8~64) winsize 57
6287 20:12:19.690830 [CA 4] Center 36 (8~64) winsize 57
6288 20:12:19.694101 [CA 5] Center 36 (8~64) winsize 57
6289 20:12:19.694177
6290 20:12:19.697508 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6291 20:12:19.697578
6292 20:12:19.700551 [CATrainingPosCal] consider 2 rank data
6293 20:12:19.703722 u2DelayCellTimex100 = 270/100 ps
6294 20:12:19.707014 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 20:12:19.710132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 20:12:19.713590 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 20:12:19.716681 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 20:12:19.720269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 20:12:19.723277 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 20:12:19.723400
6301 20:12:19.729958 CA PerBit enable=1, Macro0, CA PI delay=36
6302 20:12:19.730037
6303 20:12:19.730101 [CBTSetCACLKResult] CA Dly = 36
6304 20:12:19.733043 CS Dly: 1 (0~32)
6305 20:12:19.733143
6306 20:12:19.736318 ----->DramcWriteLeveling(PI) begin...
6307 20:12:19.736396 ==
6308 20:12:19.739679 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 20:12:19.743218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 20:12:19.743293 ==
6311 20:12:19.746204 Write leveling (Byte 0): 40 => 8
6312 20:12:19.749980 Write leveling (Byte 1): 40 => 8
6313 20:12:19.753176 DramcWriteLeveling(PI) end<-----
6314 20:12:19.753251
6315 20:12:19.753311 ==
6316 20:12:19.756539 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 20:12:19.759888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 20:12:19.762992 ==
6319 20:12:19.763069 [Gating] SW mode calibration
6320 20:12:19.772796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6321 20:12:19.776610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6322 20:12:19.779571 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 20:12:19.786200 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6324 20:12:19.789719 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 20:12:19.793033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 20:12:19.799156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 20:12:19.802799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 20:12:19.806071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 20:12:19.812904 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 20:12:19.815888 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 20:12:19.819004 Total UI for P1: 0, mck2ui 16
6332 20:12:19.822657 best dqsien dly found for B0: ( 0, 14, 24)
6333 20:12:19.825931 Total UI for P1: 0, mck2ui 16
6334 20:12:19.829228 best dqsien dly found for B1: ( 0, 14, 24)
6335 20:12:19.832416 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6336 20:12:19.835847 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6337 20:12:19.835962
6338 20:12:19.838977 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 20:12:19.845465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6340 20:12:19.845551 [Gating] SW calibration Done
6341 20:12:19.845615 ==
6342 20:12:19.848801 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 20:12:19.855009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 20:12:19.855091 ==
6345 20:12:19.855156 RX Vref Scan: 0
6346 20:12:19.855216
6347 20:12:19.858579 RX Vref 0 -> 0, step: 1
6348 20:12:19.858661
6349 20:12:19.861810 RX Delay -410 -> 252, step: 16
6350 20:12:19.865367 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6351 20:12:19.868575 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6352 20:12:19.874750 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6353 20:12:19.878192 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6354 20:12:19.881263 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6355 20:12:19.885018 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6356 20:12:19.891561 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6357 20:12:19.894542 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6358 20:12:19.898088 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6359 20:12:19.901440 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6360 20:12:19.907803 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6361 20:12:19.911133 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6362 20:12:19.914411 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6363 20:12:19.921376 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6364 20:12:19.924249 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6365 20:12:19.927692 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6366 20:12:19.927774 ==
6367 20:12:19.930917 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 20:12:19.934276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 20:12:19.937919 ==
6370 20:12:19.938000 DQS Delay:
6371 20:12:19.938064 DQS0 = 35, DQS1 = 59
6372 20:12:19.940982 DQM Delay:
6373 20:12:19.941063 DQM0 = 5, DQM1 = 18
6374 20:12:19.944476 DQ Delay:
6375 20:12:19.944557 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6376 20:12:19.947656 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6377 20:12:19.950668 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6378 20:12:19.953819 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6379 20:12:19.953900
6380 20:12:19.953964
6381 20:12:19.957158 ==
6382 20:12:19.960441 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 20:12:19.963923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 20:12:19.964006 ==
6385 20:12:19.964069
6386 20:12:19.964128
6387 20:12:19.967207 TX Vref Scan disable
6388 20:12:19.967289 == TX Byte 0 ==
6389 20:12:19.970306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 20:12:19.976866 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 20:12:19.976948 == TX Byte 1 ==
6392 20:12:19.980508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 20:12:19.987024 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 20:12:19.987109 ==
6395 20:12:19.990144 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 20:12:19.994050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 20:12:19.994133 ==
6398 20:12:19.994196
6399 20:12:19.994254
6400 20:12:19.997049 TX Vref Scan disable
6401 20:12:19.997131 == TX Byte 0 ==
6402 20:12:20 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 20:12:20.007172 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 20:12:20.007279 == TX Byte 1 ==
6405 20:12:20.009991 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 20:12:20.016870 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 20:12:20.016952
6408 20:12:20.017014 [DATLAT]
6409 20:12:20.020095 Freq=400, CH0 RK0
6410 20:12:20.020177
6411 20:12:20.020240 DATLAT Default: 0xf
6412 20:12:20.023087 0, 0xFFFF, sum = 0
6413 20:12:20.023169 1, 0xFFFF, sum = 0
6414 20:12:20.026337 2, 0xFFFF, sum = 0
6415 20:12:20.026420 3, 0xFFFF, sum = 0
6416 20:12:20.029555 4, 0xFFFF, sum = 0
6417 20:12:20.029637 5, 0xFFFF, sum = 0
6418 20:12:20.033245 6, 0xFFFF, sum = 0
6419 20:12:20.033327 7, 0xFFFF, sum = 0
6420 20:12:20.036620 8, 0xFFFF, sum = 0
6421 20:12:20.036703 9, 0xFFFF, sum = 0
6422 20:12:20.039878 10, 0xFFFF, sum = 0
6423 20:12:20.039959 11, 0xFFFF, sum = 0
6424 20:12:20.043217 12, 0xFFFF, sum = 0
6425 20:12:20.043298 13, 0x0, sum = 1
6426 20:12:20.046198 14, 0x0, sum = 2
6427 20:12:20.046279 15, 0x0, sum = 3
6428 20:12:20.049558 16, 0x0, sum = 4
6429 20:12:20.049640 best_step = 14
6430 20:12:20.049702
6431 20:12:20.049769 ==
6432 20:12:20.052713 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 20:12:20.059369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 20:12:20.059457 ==
6435 20:12:20.059520 RX Vref Scan: 1
6436 20:12:20.059577
6437 20:12:20.063009 RX Vref 0 -> 0, step: 1
6438 20:12:20.063096
6439 20:12:20.066071 RX Delay -359 -> 252, step: 8
6440 20:12:20.066192
6441 20:12:20.069181 Set Vref, RX VrefLevel [Byte0]: 54
6442 20:12:20.072370 [Byte1]: 59
6443 20:12:20.075990
6444 20:12:20.076069 Final RX Vref Byte 0 = 54 to rank0
6445 20:12:20.079243 Final RX Vref Byte 1 = 59 to rank0
6446 20:12:20.082683 Final RX Vref Byte 0 = 54 to rank1
6447 20:12:20.085972 Final RX Vref Byte 1 = 59 to rank1==
6448 20:12:20.089154 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 20:12:20.095591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 20:12:20.095680 ==
6451 20:12:20.095742 DQS Delay:
6452 20:12:20.099282 DQS0 = 44, DQS1 = 60
6453 20:12:20.099385 DQM Delay:
6454 20:12:20.099465 DQM0 = 10, DQM1 = 16
6455 20:12:20.102389 DQ Delay:
6456 20:12:20.105712 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6457 20:12:20.108885 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6458 20:12:20.108967 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6459 20:12:20.115466 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6460 20:12:20.115565
6461 20:12:20.115643
6462 20:12:20.122370 [DQSOSCAuto] RK0, (LSB)MR18= 0x978a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6463 20:12:20.125188 CH0 RK0: MR19=C0C, MR18=978A
6464 20:12:20.132098 CH0_RK0: MR19=0xC0C, MR18=0x978A, DQSOSC=390, MR23=63, INC=388, DEC=258
6465 20:12:20.132183 ==
6466 20:12:20.135116 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 20:12:20.138543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 20:12:20.138625 ==
6469 20:12:20.142374 [Gating] SW mode calibration
6470 20:12:20.148295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6471 20:12:20.155021 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6472 20:12:20.158304 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 20:12:20.161747 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6474 20:12:20.168424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 20:12:20.171652 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 20:12:20.175035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 20:12:20.181120 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 20:12:20.184436 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 20:12:20.187720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 20:12:20.194327 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 20:12:20.197604 Total UI for P1: 0, mck2ui 16
6482 20:12:20.201225 best dqsien dly found for B0: ( 0, 14, 24)
6483 20:12:20.204245 Total UI for P1: 0, mck2ui 16
6484 20:12:20.207745 best dqsien dly found for B1: ( 0, 14, 24)
6485 20:12:20.211379 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6486 20:12:20.214176 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6487 20:12:20.214258
6488 20:12:20.217300 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 20:12:20.220835 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6490 20:12:20.224027 [Gating] SW calibration Done
6491 20:12:20.224109 ==
6492 20:12:20.227115 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 20:12:20.230486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 20:12:20.233693 ==
6495 20:12:20.233775 RX Vref Scan: 0
6496 20:12:20.233839
6497 20:12:20.237309 RX Vref 0 -> 0, step: 1
6498 20:12:20.237391
6499 20:12:20.240438 RX Delay -410 -> 252, step: 16
6500 20:12:20.243878 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6501 20:12:20.246748 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6502 20:12:20.250330 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6503 20:12:20.256985 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6504 20:12:20.260036 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6505 20:12:20.263357 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6506 20:12:20.267106 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6507 20:12:20.273229 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6508 20:12:20.276794 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6509 20:12:20.279687 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6510 20:12:20.286292 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6511 20:12:20.289495 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6512 20:12:20.292986 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6513 20:12:20.296261 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6514 20:12:20.302972 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6515 20:12:20.306122 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6516 20:12:20.306204 ==
6517 20:12:20.309214 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 20:12:20.313310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 20:12:20.313393 ==
6520 20:12:20.315738 DQS Delay:
6521 20:12:20.315820 DQS0 = 35, DQS1 = 59
6522 20:12:20.319528 DQM Delay:
6523 20:12:20.319611 DQM0 = 7, DQM1 = 16
6524 20:12:20.319675 DQ Delay:
6525 20:12:20.322356 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6526 20:12:20.326141 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6527 20:12:20.329064 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6528 20:12:20.332253 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6529 20:12:20.332334
6530 20:12:20.332398
6531 20:12:20.332457 ==
6532 20:12:20.335444 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 20:12:20.342105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 20:12:20.342188 ==
6535 20:12:20.342251
6536 20:12:20.342311
6537 20:12:20.342368 TX Vref Scan disable
6538 20:12:20.345709 == TX Byte 0 ==
6539 20:12:20.348663 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6540 20:12:20.351849 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6541 20:12:20.355467 == TX Byte 1 ==
6542 20:12:20.358757 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6543 20:12:20.362062 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6544 20:12:20.365173 ==
6545 20:12:20.365255 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 20:12:20.371726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 20:12:20.371809 ==
6548 20:12:20.371873
6549 20:12:20.371933
6550 20:12:20.375237 TX Vref Scan disable
6551 20:12:20.375336 == TX Byte 0 ==
6552 20:12:20.378457 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6553 20:12:20.385072 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6554 20:12:20.385155 == TX Byte 1 ==
6555 20:12:20.388241 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6556 20:12:20.394856 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6557 20:12:20.394940
6558 20:12:20.395005 [DATLAT]
6559 20:12:20.395065 Freq=400, CH0 RK1
6560 20:12:20.395124
6561 20:12:20.398400 DATLAT Default: 0xe
6562 20:12:20.398482 0, 0xFFFF, sum = 0
6563 20:12:20.401223 1, 0xFFFF, sum = 0
6564 20:12:20.404539 2, 0xFFFF, sum = 0
6565 20:12:20.404622 3, 0xFFFF, sum = 0
6566 20:12:20.407927 4, 0xFFFF, sum = 0
6567 20:12:20.408011 5, 0xFFFF, sum = 0
6568 20:12:20.411091 6, 0xFFFF, sum = 0
6569 20:12:20.411176 7, 0xFFFF, sum = 0
6570 20:12:20.414220 8, 0xFFFF, sum = 0
6571 20:12:20.414304 9, 0xFFFF, sum = 0
6572 20:12:20.417901 10, 0xFFFF, sum = 0
6573 20:12:20.417984 11, 0xFFFF, sum = 0
6574 20:12:20.420803 12, 0xFFFF, sum = 0
6575 20:12:20.420886 13, 0x0, sum = 1
6576 20:12:20.424512 14, 0x0, sum = 2
6577 20:12:20.424595 15, 0x0, sum = 3
6578 20:12:20.427612 16, 0x0, sum = 4
6579 20:12:20.427696 best_step = 14
6580 20:12:20.427760
6581 20:12:20.427819 ==
6582 20:12:20.431031 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 20:12:20.437481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 20:12:20.437564 ==
6585 20:12:20.437629 RX Vref Scan: 0
6586 20:12:20.437689
6587 20:12:20.440719 RX Vref 0 -> 0, step: 1
6588 20:12:20.440802
6589 20:12:20.444312 RX Delay -359 -> 252, step: 8
6590 20:12:20.450520 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6591 20:12:20.454096 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6592 20:12:20.456978 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6593 20:12:20.460584 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6594 20:12:20.466874 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6595 20:12:20.470313 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6596 20:12:20.473881 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6597 20:12:20.476644 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6598 20:12:20.483197 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6599 20:12:20.487006 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6600 20:12:20.490195 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6601 20:12:20.496677 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6602 20:12:20.499797 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6603 20:12:20.503346 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6604 20:12:20.506623 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6605 20:12:20.513049 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6606 20:12:20.513147 ==
6607 20:12:20.516597 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 20:12:20.519632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 20:12:20.519715 ==
6610 20:12:20.519812 DQS Delay:
6611 20:12:20.523454 DQS0 = 44, DQS1 = 60
6612 20:12:20.523536 DQM Delay:
6613 20:12:20.526731 DQM0 = 10, DQM1 = 16
6614 20:12:20.526813 DQ Delay:
6615 20:12:20.530177 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6616 20:12:20.533503 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6617 20:12:20.536597 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6618 20:12:20.539842 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6619 20:12:20.539924
6620 20:12:20.539987
6621 20:12:20.546621 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6622 20:12:20.549753 CH0 RK1: MR19=C0C, MR18=8C85
6623 20:12:20.556133 CH0_RK1: MR19=0xC0C, MR18=0x8C85, DQSOSC=392, MR23=63, INC=384, DEC=256
6624 20:12:20.559235 [RxdqsGatingPostProcess] freq 400
6625 20:12:20.566122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6626 20:12:20.569058 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 20:12:20.572378 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 20:12:20.575859 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 20:12:20.579072 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 20:12:20.581989 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 20:12:20.582072 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 20:12:20.585400 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 20:12:20.588645 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 20:12:20.592475 Pre-setting of DQS Precalculation
6635 20:12:20.599355 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6636 20:12:20.599501 ==
6637 20:12:20.602375 Dram Type= 6, Freq= 0, CH_1, rank 0
6638 20:12:20.605196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 20:12:20.605279 ==
6640 20:12:20.611612 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 20:12:20.618295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6642 20:12:20.621464 [CA 0] Center 36 (8~64) winsize 57
6643 20:12:20.625157 [CA 1] Center 36 (8~64) winsize 57
6644 20:12:20.628139 [CA 2] Center 36 (8~64) winsize 57
6645 20:12:20.632007 [CA 3] Center 36 (8~64) winsize 57
6646 20:12:20.632089 [CA 4] Center 36 (8~64) winsize 57
6647 20:12:20.634986 [CA 5] Center 36 (8~64) winsize 57
6648 20:12:20.635068
6649 20:12:20.641868 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6650 20:12:20.641951
6651 20:12:20.644817 [CATrainingPosCal] consider 1 rank data
6652 20:12:20.648346 u2DelayCellTimex100 = 270/100 ps
6653 20:12:20.651385 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 20:12:20.654739 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 20:12:20.657870 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 20:12:20.661072 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 20:12:20.664553 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 20:12:20.667533 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 20:12:20.667615
6660 20:12:20.671034 CA PerBit enable=1, Macro0, CA PI delay=36
6661 20:12:20.671164
6662 20:12:20.674415 [CBTSetCACLKResult] CA Dly = 36
6663 20:12:20.677338 CS Dly: 1 (0~32)
6664 20:12:20.677421 ==
6665 20:12:20.680534 Dram Type= 6, Freq= 0, CH_1, rank 1
6666 20:12:20.684046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 20:12:20.684129 ==
6668 20:12:20.690497 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6669 20:12:20.697567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6670 20:12:20.700730 [CA 0] Center 36 (8~64) winsize 57
6671 20:12:20.703789 [CA 1] Center 36 (8~64) winsize 57
6672 20:12:20.707515 [CA 2] Center 36 (8~64) winsize 57
6673 20:12:20.707598 [CA 3] Center 36 (8~64) winsize 57
6674 20:12:20.710760 [CA 4] Center 36 (8~64) winsize 57
6675 20:12:20.713494 [CA 5] Center 36 (8~64) winsize 57
6676 20:12:20.713577
6677 20:12:20.720400 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6678 20:12:20.720482
6679 20:12:20.723340 [CATrainingPosCal] consider 2 rank data
6680 20:12:20.727156 u2DelayCellTimex100 = 270/100 ps
6681 20:12:20.730423 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 20:12:20.733434 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 20:12:20.736591 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 20:12:20.739978 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 20:12:20.743111 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 20:12:20.746355 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 20:12:20.746471
6688 20:12:20.749617 CA PerBit enable=1, Macro0, CA PI delay=36
6689 20:12:20.749699
6690 20:12:20.752960 [CBTSetCACLKResult] CA Dly = 36
6691 20:12:20.756305 CS Dly: 1 (0~32)
6692 20:12:20.756388
6693 20:12:20.759722 ----->DramcWriteLeveling(PI) begin...
6694 20:12:20.759806 ==
6695 20:12:20.763307 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 20:12:20.766389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 20:12:20.766472 ==
6698 20:12:20.769578 Write leveling (Byte 0): 40 => 8
6699 20:12:20.772861 Write leveling (Byte 1): 40 => 8
6700 20:12:20.776207 DramcWriteLeveling(PI) end<-----
6701 20:12:20.776304
6702 20:12:20.776369 ==
6703 20:12:20.779690 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 20:12:20.783029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 20:12:20.783141 ==
6706 20:12:20.786237 [Gating] SW mode calibration
6707 20:12:20.792902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6708 20:12:20.799059 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6709 20:12:20.802514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 20:12:20.809127 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6711 20:12:20.812683 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 20:12:20.815486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 20:12:20.822184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 20:12:20.825575 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 20:12:20.829103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 20:12:20.835183 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 20:12:20.838706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 20:12:20.841883 Total UI for P1: 0, mck2ui 16
6719 20:12:20.845493 best dqsien dly found for B0: ( 0, 14, 24)
6720 20:12:20.848539 Total UI for P1: 0, mck2ui 16
6721 20:12:20.851810 best dqsien dly found for B1: ( 0, 14, 24)
6722 20:12:20.854995 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6723 20:12:20.858414 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6724 20:12:20.858539
6725 20:12:20.861803 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 20:12:20.864992 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6727 20:12:20.868471 [Gating] SW calibration Done
6728 20:12:20.868594 ==
6729 20:12:20.871783 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 20:12:20.878075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 20:12:20.878199 ==
6732 20:12:20.878313 RX Vref Scan: 0
6733 20:12:20.878422
6734 20:12:20.881299 RX Vref 0 -> 0, step: 1
6735 20:12:20.881420
6736 20:12:20.884834 RX Delay -410 -> 252, step: 16
6737 20:12:20.888344 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6738 20:12:20.891380 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6739 20:12:20.898060 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6740 20:12:20.901405 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6741 20:12:20.905296 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6742 20:12:20.907799 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6743 20:12:20.914465 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6744 20:12:20.917936 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6745 20:12:20.920806 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6746 20:12:20.924443 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6747 20:12:20.930819 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6748 20:12:20.933917 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6749 20:12:20.937736 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6750 20:12:20.940774 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6751 20:12:20.947704 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6752 20:12:20.950760 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6753 20:12:20.950842 ==
6754 20:12:20.954236 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 20:12:20.956988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 20:12:20.957074 ==
6757 20:12:20.960644 DQS Delay:
6758 20:12:20.960726 DQS0 = 35, DQS1 = 51
6759 20:12:20.963547 DQM Delay:
6760 20:12:20.963630 DQM0 = 6, DQM1 = 13
6761 20:12:20.967252 DQ Delay:
6762 20:12:20.967334 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6763 20:12:20.970192 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6764 20:12:20.973605 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6765 20:12:20.976942 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6766 20:12:20.977025
6767 20:12:20.977089
6768 20:12:20.977148 ==
6769 20:12:20.980402 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 20:12:20.986540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 20:12:20.986623 ==
6772 20:12:20.986687
6773 20:12:20.986746
6774 20:12:20.990204 TX Vref Scan disable
6775 20:12:20.990286 == TX Byte 0 ==
6776 20:12:20.993157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 20:12:20.999809 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 20:12:20.999892 == TX Byte 1 ==
6779 20:12:21.003475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 20:12:21.009921 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 20:12:21.010003 ==
6782 20:12:21.013265 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 20:12:21.016485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 20:12:21.016567 ==
6785 20:12:21.016631
6786 20:12:21.016691
6787 20:12:21.019999 TX Vref Scan disable
6788 20:12:21.020081 == TX Byte 0 ==
6789 20:12:21.023157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 20:12:21.029699 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 20:12:21.029782 == TX Byte 1 ==
6792 20:12:21.033125 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 20:12:21.039521 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 20:12:21.039604
6795 20:12:21.039668 [DATLAT]
6796 20:12:21.039728 Freq=400, CH1 RK0
6797 20:12:21.039787
6798 20:12:21.042628 DATLAT Default: 0xf
6799 20:12:21.045969 0, 0xFFFF, sum = 0
6800 20:12:21.046052 1, 0xFFFF, sum = 0
6801 20:12:21.049455 2, 0xFFFF, sum = 0
6802 20:12:21.049538 3, 0xFFFF, sum = 0
6803 20:12:21.052474 4, 0xFFFF, sum = 0
6804 20:12:21.052557 5, 0xFFFF, sum = 0
6805 20:12:21.055649 6, 0xFFFF, sum = 0
6806 20:12:21.055732 7, 0xFFFF, sum = 0
6807 20:12:21.059005 8, 0xFFFF, sum = 0
6808 20:12:21.059088 9, 0xFFFF, sum = 0
6809 20:12:21.062167 10, 0xFFFF, sum = 0
6810 20:12:21.062251 11, 0xFFFF, sum = 0
6811 20:12:21.065699 12, 0xFFFF, sum = 0
6812 20:12:21.065782 13, 0x0, sum = 1
6813 20:12:21.069583 14, 0x0, sum = 2
6814 20:12:21.069666 15, 0x0, sum = 3
6815 20:12:21.072662 16, 0x0, sum = 4
6816 20:12:21.072745 best_step = 14
6817 20:12:21.072810
6818 20:12:21.072906 ==
6819 20:12:21.075284 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 20:12:21.082463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 20:12:21.082546 ==
6822 20:12:21.082610 RX Vref Scan: 1
6823 20:12:21.082670
6824 20:12:21.085519 RX Vref 0 -> 0, step: 1
6825 20:12:21.085601
6826 20:12:21.088621 RX Delay -343 -> 252, step: 8
6827 20:12:21.088703
6828 20:12:21.092126 Set Vref, RX VrefLevel [Byte0]: 51
6829 20:12:21.095011 [Byte1]: 51
6830 20:12:21.098580
6831 20:12:21.098668 Final RX Vref Byte 0 = 51 to rank0
6832 20:12:21.101809 Final RX Vref Byte 1 = 51 to rank0
6833 20:12:21.105187 Final RX Vref Byte 0 = 51 to rank1
6834 20:12:21.108515 Final RX Vref Byte 1 = 51 to rank1==
6835 20:12:21.111791 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 20:12:21.118487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 20:12:21.118569 ==
6838 20:12:21.118633 DQS Delay:
6839 20:12:21.121661 DQS0 = 44, DQS1 = 52
6840 20:12:21.121743 DQM Delay:
6841 20:12:21.121807 DQM0 = 9, DQM1 = 11
6842 20:12:21.125006 DQ Delay:
6843 20:12:21.128116 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6844 20:12:21.131333 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6845 20:12:21.131452 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6846 20:12:21.135060 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6847 20:12:21.137920
6848 20:12:21.138002
6849 20:12:21.144880 [DQSOSCAuto] RK0, (LSB)MR18= 0x648b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6850 20:12:21.148210 CH1 RK0: MR19=C0C, MR18=648B
6851 20:12:21.154687 CH1_RK0: MR19=0xC0C, MR18=0x648B, DQSOSC=392, MR23=63, INC=384, DEC=256
6852 20:12:21.154769 ==
6853 20:12:21.157674 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 20:12:21.161127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 20:12:21.161210 ==
6856 20:12:21.164351 [Gating] SW mode calibration
6857 20:12:21.170857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6858 20:12:21.177656 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6859 20:12:21.181016 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 20:12:21.184541 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6861 20:12:21.190903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 20:12:21.194528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 20:12:21.197364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 20:12:21.203651 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 20:12:21.207370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 20:12:21.210581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 20:12:21.216923 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 20:12:21.220562 Total UI for P1: 0, mck2ui 16
6869 20:12:21.223499 best dqsien dly found for B0: ( 0, 14, 24)
6870 20:12:21.226567 Total UI for P1: 0, mck2ui 16
6871 20:12:21.230183 best dqsien dly found for B1: ( 0, 14, 24)
6872 20:12:21.233183 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6873 20:12:21.236455 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6874 20:12:21.236583
6875 20:12:21.240296 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 20:12:21.243565 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6877 20:12:21.246861 [Gating] SW calibration Done
6878 20:12:21.246980 ==
6879 20:12:21.250034 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 20:12:21.253272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 20:12:21.253395 ==
6882 20:12:21.256469 RX Vref Scan: 0
6883 20:12:21.256591
6884 20:12:21.259748 RX Vref 0 -> 0, step: 1
6885 20:12:21.259871
6886 20:12:21.259985 RX Delay -410 -> 252, step: 16
6887 20:12:21.266459 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6888 20:12:21.269879 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6889 20:12:21.273016 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6890 20:12:21.279710 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6891 20:12:21.283294 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6892 20:12:21.286433 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6893 20:12:21.290509 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6894 20:12:21.296402 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6895 20:12:21.299642 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6896 20:12:21.302616 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6897 20:12:21.306070 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6898 20:12:21.312552 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6899 20:12:21.315979 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6900 20:12:21.319061 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6901 20:12:21.325685 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6902 20:12:21.329194 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6903 20:12:21.329276 ==
6904 20:12:21.332775 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 20:12:21.335786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 20:12:21.335870 ==
6907 20:12:21.339014 DQS Delay:
6908 20:12:21.339096 DQS0 = 43, DQS1 = 51
6909 20:12:21.339161 DQM Delay:
6910 20:12:21.342233 DQM0 = 10, DQM1 = 16
6911 20:12:21.342315 DQ Delay:
6912 20:12:21.345590 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6913 20:12:21.348903 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6914 20:12:21.352298 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6915 20:12:21.355342 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6916 20:12:21.355462
6917 20:12:21.355526
6918 20:12:21.355585 ==
6919 20:12:21.358610 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 20:12:21.362198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 20:12:21.365183 ==
6922 20:12:21.365265
6923 20:12:21.365329
6924 20:12:21.365388 TX Vref Scan disable
6925 20:12:21.368551 == TX Byte 0 ==
6926 20:12:21.371843 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6927 20:12:21.375353 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6928 20:12:21.378502 == TX Byte 1 ==
6929 20:12:21.381995 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6930 20:12:21.385108 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6931 20:12:21.385190 ==
6932 20:12:21.388339 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 20:12:21.395096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 20:12:21.395224 ==
6935 20:12:21.395341
6936 20:12:21.395487
6937 20:12:21.395598 TX Vref Scan disable
6938 20:12:21.398460 == TX Byte 0 ==
6939 20:12:21.401650 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6940 20:12:21.404899 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6941 20:12:21.408398 == TX Byte 1 ==
6942 20:12:21.411354 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6943 20:12:21.414822 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6944 20:12:21.414944
6945 20:12:21.418186 [DATLAT]
6946 20:12:21.418308 Freq=400, CH1 RK1
6947 20:12:21.418421
6948 20:12:21.421409 DATLAT Default: 0xe
6949 20:12:21.421528 0, 0xFFFF, sum = 0
6950 20:12:21.424655 1, 0xFFFF, sum = 0
6951 20:12:21.424780 2, 0xFFFF, sum = 0
6952 20:12:21.428175 3, 0xFFFF, sum = 0
6953 20:12:21.428299 4, 0xFFFF, sum = 0
6954 20:12:21.431251 5, 0xFFFF, sum = 0
6955 20:12:21.431352 6, 0xFFFF, sum = 0
6956 20:12:21.434599 7, 0xFFFF, sum = 0
6957 20:12:21.434698 8, 0xFFFF, sum = 0
6958 20:12:21.437514 9, 0xFFFF, sum = 0
6959 20:12:21.441234 10, 0xFFFF, sum = 0
6960 20:12:21.441343 11, 0xFFFF, sum = 0
6961 20:12:21.444486 12, 0xFFFF, sum = 0
6962 20:12:21.444570 13, 0x0, sum = 1
6963 20:12:21.447550 14, 0x0, sum = 2
6964 20:12:21.447634 15, 0x0, sum = 3
6965 20:12:21.450938 16, 0x0, sum = 4
6966 20:12:21.451021 best_step = 14
6967 20:12:21.451086
6968 20:12:21.451145 ==
6969 20:12:21.454091 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 20:12:21.457552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 20:12:21.457635 ==
6972 20:12:21.460675 RX Vref Scan: 0
6973 20:12:21.460757
6974 20:12:21.463956 RX Vref 0 -> 0, step: 1
6975 20:12:21.464047
6976 20:12:21.464157 RX Delay -343 -> 252, step: 8
6977 20:12:21.472607 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6978 20:12:21.475888 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6979 20:12:21.479321 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6980 20:12:21.485851 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6981 20:12:21.489126 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6982 20:12:21.492399 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6983 20:12:21.495686 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6984 20:12:21.502433 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6985 20:12:21.505975 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6986 20:12:21.509066 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6987 20:12:21.512620 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6988 20:12:21.519297 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6989 20:12:21.522409 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6990 20:12:21.525815 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6991 20:12:21.529131 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6992 20:12:21.535992 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6993 20:12:21.536075 ==
6994 20:12:21.538932 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 20:12:21.542189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 20:12:21.542272 ==
6997 20:12:21.542337 DQS Delay:
6998 20:12:21.545748 DQS0 = 48, DQS1 = 52
6999 20:12:21.545830 DQM Delay:
7000 20:12:21.548896 DQM0 = 11, DQM1 = 10
7001 20:12:21.548978 DQ Delay:
7002 20:12:21.552067 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7003 20:12:21.555514 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7004 20:12:21.558639 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7005 20:12:21.561868 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7006 20:12:21.561968
7007 20:12:21.562057
7008 20:12:21.571998 [DQSOSCAuto] RK1, (LSB)MR18= 0x72ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7009 20:12:21.572125 CH1 RK1: MR19=C0C, MR18=72AB
7010 20:12:21.578422 CH1_RK1: MR19=0xC0C, MR18=0x72AB, DQSOSC=388, MR23=63, INC=392, DEC=261
7011 20:12:21.582043 [RxdqsGatingPostProcess] freq 400
7012 20:12:21.588382 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7013 20:12:21.591295 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 20:12:21.594944 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 20:12:21.598201 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 20:12:21.601449 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 20:12:21.604721 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 20:12:21.604803 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 20:12:21.607827 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 20:12:21.611053 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 20:12:21.614717 Pre-setting of DQS Precalculation
7022 20:12:21.620869 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7023 20:12:21.627652 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7024 20:12:21.634907 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7025 20:12:21.634991
7026 20:12:21.635054
7027 20:12:21.637681 [Calibration Summary] 800 Mbps
7028 20:12:21.640832 CH 0, Rank 0
7029 20:12:21.640914 SW Impedance : PASS
7030 20:12:21.644114 DUTY Scan : NO K
7031 20:12:21.647380 ZQ Calibration : PASS
7032 20:12:21.647476 Jitter Meter : NO K
7033 20:12:21.650677 CBT Training : PASS
7034 20:12:21.654126 Write leveling : PASS
7035 20:12:21.654207 RX DQS gating : PASS
7036 20:12:21.657736 RX DQ/DQS(RDDQC) : PASS
7037 20:12:21.657821 TX DQ/DQS : PASS
7038 20:12:21.660405 RX DATLAT : PASS
7039 20:12:21.663638 RX DQ/DQS(Engine): PASS
7040 20:12:21.663745 TX OE : NO K
7041 20:12:21.667238 All Pass.
7042 20:12:21.667343
7043 20:12:21.667452 CH 0, Rank 1
7044 20:12:21.670434 SW Impedance : PASS
7045 20:12:21.670514 DUTY Scan : NO K
7046 20:12:21.674070 ZQ Calibration : PASS
7047 20:12:21.677012 Jitter Meter : NO K
7048 20:12:21.677093 CBT Training : PASS
7049 20:12:21.680305 Write leveling : NO K
7050 20:12:21.683835 RX DQS gating : PASS
7051 20:12:21.683916 RX DQ/DQS(RDDQC) : PASS
7052 20:12:21.686958 TX DQ/DQS : PASS
7053 20:12:21.690359 RX DATLAT : PASS
7054 20:12:21.690439 RX DQ/DQS(Engine): PASS
7055 20:12:21.693661 TX OE : NO K
7056 20:12:21.693742 All Pass.
7057 20:12:21.693804
7058 20:12:21.696871 CH 1, Rank 0
7059 20:12:21.696953 SW Impedance : PASS
7060 20:12:21.700073 DUTY Scan : NO K
7061 20:12:21.703563 ZQ Calibration : PASS
7062 20:12:21.703644 Jitter Meter : NO K
7063 20:12:21.706652 CBT Training : PASS
7064 20:12:21.709624 Write leveling : PASS
7065 20:12:21.709705 RX DQS gating : PASS
7066 20:12:21.712954 RX DQ/DQS(RDDQC) : PASS
7067 20:12:21.716156 TX DQ/DQS : PASS
7068 20:12:21.716240 RX DATLAT : PASS
7069 20:12:21.719348 RX DQ/DQS(Engine): PASS
7070 20:12:21.723084 TX OE : NO K
7071 20:12:21.723183 All Pass.
7072 20:12:21.723267
7073 20:12:21.723330 CH 1, Rank 1
7074 20:12:21.726159 SW Impedance : PASS
7075 20:12:21.729785 DUTY Scan : NO K
7076 20:12:21.729867 ZQ Calibration : PASS
7077 20:12:21.733132 Jitter Meter : NO K
7078 20:12:21.736267 CBT Training : PASS
7079 20:12:21.736367 Write leveling : NO K
7080 20:12:21.739552 RX DQS gating : PASS
7081 20:12:21.742493 RX DQ/DQS(RDDQC) : PASS
7082 20:12:21.742576 TX DQ/DQS : PASS
7083 20:12:21.746117 RX DATLAT : PASS
7084 20:12:21.749201 RX DQ/DQS(Engine): PASS
7085 20:12:21.749283 TX OE : NO K
7086 20:12:21.749348 All Pass.
7087 20:12:21.749407
7088 20:12:21.752552 DramC Write-DBI off
7089 20:12:21.755929 PER_BANK_REFRESH: Hybrid Mode
7090 20:12:21.756012 TX_TRACKING: ON
7091 20:12:21.765801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7092 20:12:21.769149 [FAST_K] Save calibration result to emmc
7093 20:12:21.772437 dramc_set_vcore_voltage set vcore to 725000
7094 20:12:21.775755 Read voltage for 1600, 0
7095 20:12:21.775837 Vio18 = 0
7096 20:12:21.779106 Vcore = 725000
7097 20:12:21.779189 Vdram = 0
7098 20:12:21.779252 Vddq = 0
7099 20:12:21.779311 Vmddr = 0
7100 20:12:21.785523 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7101 20:12:21.792389 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7102 20:12:21.792477 MEM_TYPE=3, freq_sel=13
7103 20:12:21.795166 sv_algorithm_assistance_LP4_3733
7104 20:12:21.801627 ============ PULL DRAM RESETB DOWN ============
7105 20:12:21.805413 ========== PULL DRAM RESETB DOWN end =========
7106 20:12:21.808526 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7107 20:12:21.811714 ===================================
7108 20:12:21.815051 LPDDR4 DRAM CONFIGURATION
7109 20:12:21.818888 ===================================
7110 20:12:21.818970 EX_ROW_EN[0] = 0x0
7111 20:12:21.821679 EX_ROW_EN[1] = 0x0
7112 20:12:21.824989 LP4Y_EN = 0x0
7113 20:12:21.825072 WORK_FSP = 0x1
7114 20:12:21.828013 WL = 0x5
7115 20:12:21.828108 RL = 0x5
7116 20:12:21.831481 BL = 0x2
7117 20:12:21.831564 RPST = 0x0
7118 20:12:21.834966 RD_PRE = 0x0
7119 20:12:21.835053 WR_PRE = 0x1
7120 20:12:21.838038 WR_PST = 0x1
7121 20:12:21.838120 DBI_WR = 0x0
7122 20:12:21.841768 DBI_RD = 0x0
7123 20:12:21.841850 OTF = 0x1
7124 20:12:21.844984 ===================================
7125 20:12:21.848179 ===================================
7126 20:12:21.851133 ANA top config
7127 20:12:21.854755 ===================================
7128 20:12:21.858011 DLL_ASYNC_EN = 0
7129 20:12:21.858094 ALL_SLAVE_EN = 0
7130 20:12:21.861144 NEW_RANK_MODE = 1
7131 20:12:21.864598 DLL_IDLE_MODE = 1
7132 20:12:21.867541 LP45_APHY_COMB_EN = 1
7133 20:12:21.867624 TX_ODT_DIS = 0
7134 20:12:21.870887 NEW_8X_MODE = 1
7135 20:12:21.874410 ===================================
7136 20:12:21.877503 ===================================
7137 20:12:21.880956 data_rate = 3200
7138 20:12:21.884375 CKR = 1
7139 20:12:21.887759 DQ_P2S_RATIO = 8
7140 20:12:21.891115 ===================================
7141 20:12:21.894308 CA_P2S_RATIO = 8
7142 20:12:21.897450 DQ_CA_OPEN = 0
7143 20:12:21.897583 DQ_SEMI_OPEN = 0
7144 20:12:21.900831 CA_SEMI_OPEN = 0
7145 20:12:21.904113 CA_FULL_RATE = 0
7146 20:12:21.907093 DQ_CKDIV4_EN = 0
7147 20:12:21.910291 CA_CKDIV4_EN = 0
7148 20:12:21.914163 CA_PREDIV_EN = 0
7149 20:12:21.914255 PH8_DLY = 12
7150 20:12:21.917431 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7151 20:12:21.920444 DQ_AAMCK_DIV = 4
7152 20:12:21.923506 CA_AAMCK_DIV = 4
7153 20:12:21.927073 CA_ADMCK_DIV = 4
7154 20:12:21.930299 DQ_TRACK_CA_EN = 0
7155 20:12:21.933691 CA_PICK = 1600
7156 20:12:21.933774 CA_MCKIO = 1600
7157 20:12:21.936770 MCKIO_SEMI = 0
7158 20:12:21.940249 PLL_FREQ = 3068
7159 20:12:21.943312 DQ_UI_PI_RATIO = 32
7160 20:12:21.947111 CA_UI_PI_RATIO = 0
7161 20:12:21.949971 ===================================
7162 20:12:21.953437 ===================================
7163 20:12:21.956883 memory_type:LPDDR4
7164 20:12:21.956965 GP_NUM : 10
7165 20:12:21.960016 SRAM_EN : 1
7166 20:12:21.960097 MD32_EN : 0
7167 20:12:21.963754 ===================================
7168 20:12:21.966748 [ANA_INIT] >>>>>>>>>>>>>>
7169 20:12:21.970022 <<<<<< [CONFIGURE PHASE]: ANA_TX
7170 20:12:21.973159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7171 20:12:21.976672 ===================================
7172 20:12:21.979677 data_rate = 3200,PCW = 0X7600
7173 20:12:21.983027 ===================================
7174 20:12:21.986287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7175 20:12:21.993190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 20:12:21.996258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7177 20:12:22.002593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7178 20:12:22.006213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7179 20:12:22.009421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7180 20:12:22.009502 [ANA_INIT] flow start
7181 20:12:22.012926 [ANA_INIT] PLL >>>>>>>>
7182 20:12:22.015835 [ANA_INIT] PLL <<<<<<<<
7183 20:12:22.019472 [ANA_INIT] MIDPI >>>>>>>>
7184 20:12:22.019551 [ANA_INIT] MIDPI <<<<<<<<
7185 20:12:22.022570 [ANA_INIT] DLL >>>>>>>>
7186 20:12:22.025687 [ANA_INIT] DLL <<<<<<<<
7187 20:12:22.025769 [ANA_INIT] flow end
7188 20:12:22.028967 ============ LP4 DIFF to SE enter ============
7189 20:12:22.035262 ============ LP4 DIFF to SE exit ============
7190 20:12:22.035397 [ANA_INIT] <<<<<<<<<<<<<
7191 20:12:22.038670 [Flow] Enable top DCM control >>>>>
7192 20:12:22.041899 [Flow] Enable top DCM control <<<<<
7193 20:12:22.045488 Enable DLL master slave shuffle
7194 20:12:22.052175 ==============================================================
7195 20:12:22.055310 Gating Mode config
7196 20:12:22.058822 ==============================================================
7197 20:12:22.061987 Config description:
7198 20:12:22.071493 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7199 20:12:22.078312 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7200 20:12:22.081552 SELPH_MODE 0: By rank 1: By Phase
7201 20:12:22.088515 ==============================================================
7202 20:12:22.091334 GAT_TRACK_EN = 1
7203 20:12:22.094776 RX_GATING_MODE = 2
7204 20:12:22.097893 RX_GATING_TRACK_MODE = 2
7205 20:12:22.101664 SELPH_MODE = 1
7206 20:12:22.101746 PICG_EARLY_EN = 1
7207 20:12:22.104706 VALID_LAT_VALUE = 1
7208 20:12:22.111261 ==============================================================
7209 20:12:22.114676 Enter into Gating configuration >>>>
7210 20:12:22.117784 Exit from Gating configuration <<<<
7211 20:12:22.121625 Enter into DVFS_PRE_config >>>>>
7212 20:12:22.131187 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7213 20:12:22.134331 Exit from DVFS_PRE_config <<<<<
7214 20:12:22.137576 Enter into PICG configuration >>>>
7215 20:12:22.141112 Exit from PICG configuration <<<<
7216 20:12:22.144254 [RX_INPUT] configuration >>>>>
7217 20:12:22.147647 [RX_INPUT] configuration <<<<<
7218 20:12:22.154218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7219 20:12:22.157621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7220 20:12:22.164513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 20:12:22.170647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 20:12:22.177415 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 20:12:22.183598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 20:12:22.187121 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7225 20:12:22.190632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7226 20:12:22.193633 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7227 20:12:22.200381 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7228 20:12:22.203693 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7229 20:12:22.206672 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 20:12:22.209842 ===================================
7231 20:12:22.213144 LPDDR4 DRAM CONFIGURATION
7232 20:12:22.216583 ===================================
7233 20:12:22.220002 EX_ROW_EN[0] = 0x0
7234 20:12:22.220084 EX_ROW_EN[1] = 0x0
7235 20:12:22.222963 LP4Y_EN = 0x0
7236 20:12:22.223044 WORK_FSP = 0x1
7237 20:12:22.226349 WL = 0x5
7238 20:12:22.226431 RL = 0x5
7239 20:12:22.229709 BL = 0x2
7240 20:12:22.229807 RPST = 0x0
7241 20:12:22.233162 RD_PRE = 0x0
7242 20:12:22.233244 WR_PRE = 0x1
7243 20:12:22.236032 WR_PST = 0x1
7244 20:12:22.236113 DBI_WR = 0x0
7245 20:12:22.239594 DBI_RD = 0x0
7246 20:12:22.242694 OTF = 0x1
7247 20:12:22.245968 ===================================
7248 20:12:22.249309 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7249 20:12:22.252482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7250 20:12:22.255771 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 20:12:22.259214 ===================================
7252 20:12:22.262478 LPDDR4 DRAM CONFIGURATION
7253 20:12:22.265566 ===================================
7254 20:12:22.268885 EX_ROW_EN[0] = 0x10
7255 20:12:22.268983 EX_ROW_EN[1] = 0x0
7256 20:12:22.272087 LP4Y_EN = 0x0
7257 20:12:22.272200 WORK_FSP = 0x1
7258 20:12:22.275658 WL = 0x5
7259 20:12:22.275741 RL = 0x5
7260 20:12:22.278591 BL = 0x2
7261 20:12:22.278673 RPST = 0x0
7262 20:12:22.282425 RD_PRE = 0x0
7263 20:12:22.282507 WR_PRE = 0x1
7264 20:12:22.285911 WR_PST = 0x1
7265 20:12:22.289242 DBI_WR = 0x0
7266 20:12:22.289325 DBI_RD = 0x0
7267 20:12:22.292380 OTF = 0x1
7268 20:12:22.295539 ===================================
7269 20:12:22.299173 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7270 20:12:22.301792 ==
7271 20:12:22.301881 Dram Type= 6, Freq= 0, CH_0, rank 0
7272 20:12:22.308352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7273 20:12:22.308448 ==
7274 20:12:22.312200 [Duty_Offset_Calibration]
7275 20:12:22.312281 B0:2 B1:0 CA:4
7276 20:12:22.312344
7277 20:12:22.314926 [DutyScan_Calibration_Flow] k_type=0
7278 20:12:22.324727
7279 20:12:22.324808 ==CLK 0==
7280 20:12:22.327475 Final CLK duty delay cell = -4
7281 20:12:22.330974 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7282 20:12:22.333884 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7283 20:12:22.337190 [-4] AVG Duty = 4937%(X100)
7284 20:12:22.337286
7285 20:12:22.340354 CH0 CLK Duty spec in!! Max-Min= 187%
7286 20:12:22.344104 [DutyScan_Calibration_Flow] ====Done====
7287 20:12:22.344186
7288 20:12:22.346933 [DutyScan_Calibration_Flow] k_type=1
7289 20:12:22.364495
7290 20:12:22.364576 ==DQS 0 ==
7291 20:12:22.367672 Final DQS duty delay cell = 0
7292 20:12:22.371074 [0] MAX Duty = 5218%(X100), DQS PI = 24
7293 20:12:22.374173 [0] MIN Duty = 5093%(X100), DQS PI = 14
7294 20:12:22.377630 [0] AVG Duty = 5155%(X100)
7295 20:12:22.377712
7296 20:12:22.377774 ==DQS 1 ==
7297 20:12:22.381070 Final DQS duty delay cell = 0
7298 20:12:22.384211 [0] MAX Duty = 5156%(X100), DQS PI = 2
7299 20:12:22.387515 [0] MIN Duty = 4969%(X100), DQS PI = 10
7300 20:12:22.390800 [0] AVG Duty = 5062%(X100)
7301 20:12:22.390893
7302 20:12:22.393869 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7303 20:12:22.393940
7304 20:12:22.397216 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7305 20:12:22.400396 [DutyScan_Calibration_Flow] ====Done====
7306 20:12:22.400473
7307 20:12:22.403879 [DutyScan_Calibration_Flow] k_type=3
7308 20:12:22.421475
7309 20:12:22.421556 ==DQM 0 ==
7310 20:12:22.424925 Final DQM duty delay cell = 0
7311 20:12:22.428109 [0] MAX Duty = 5124%(X100), DQS PI = 22
7312 20:12:22.431392 [0] MIN Duty = 4875%(X100), DQS PI = 54
7313 20:12:22.434891 [0] AVG Duty = 4999%(X100)
7314 20:12:22.434965
7315 20:12:22.435027 ==DQM 1 ==
7316 20:12:22.438034 Final DQM duty delay cell = 0
7317 20:12:22.441630 [0] MAX Duty = 5000%(X100), DQS PI = 2
7318 20:12:22.444732 [0] MIN Duty = 4844%(X100), DQS PI = 14
7319 20:12:22.447941 [0] AVG Duty = 4922%(X100)
7320 20:12:22.448022
7321 20:12:22.451515 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7322 20:12:22.451597
7323 20:12:22.454274 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7324 20:12:22.457508 [DutyScan_Calibration_Flow] ====Done====
7325 20:12:22.457589
7326 20:12:22.460732 [DutyScan_Calibration_Flow] k_type=2
7327 20:12:22.478930
7328 20:12:22.479013 ==DQ 0 ==
7329 20:12:22.482212 Final DQ duty delay cell = 0
7330 20:12:22.485285 [0] MAX Duty = 5156%(X100), DQS PI = 22
7331 20:12:22.489113 [0] MIN Duty = 4938%(X100), DQS PI = 12
7332 20:12:22.489195 [0] AVG Duty = 5047%(X100)
7333 20:12:22.491990
7334 20:12:22.492071 ==DQ 1 ==
7335 20:12:22.495233 Final DQ duty delay cell = 0
7336 20:12:22.498723 [0] MAX Duty = 5187%(X100), DQS PI = 2
7337 20:12:22.501542 [0] MIN Duty = 4938%(X100), DQS PI = 12
7338 20:12:22.501623 [0] AVG Duty = 5062%(X100)
7339 20:12:22.504866
7340 20:12:22.508100 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7341 20:12:22.508182
7342 20:12:22.511627 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7343 20:12:22.514769 [DutyScan_Calibration_Flow] ====Done====
7344 20:12:22.514850 ==
7345 20:12:22.518335 Dram Type= 6, Freq= 0, CH_1, rank 0
7346 20:12:22.521451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7347 20:12:22.521533 ==
7348 20:12:22.524943 [Duty_Offset_Calibration]
7349 20:12:22.525025 B0:0 B1:-1 CA:3
7350 20:12:22.525089
7351 20:12:22.528278 [DutyScan_Calibration_Flow] k_type=0
7352 20:12:22.538163
7353 20:12:22.538244 ==CLK 0==
7354 20:12:22.541432 Final CLK duty delay cell = -4
7355 20:12:22.544803 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7356 20:12:22.548222 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7357 20:12:22.551513 [-4] AVG Duty = 4922%(X100)
7358 20:12:22.551594
7359 20:12:22.554723 CH1 CLK Duty spec in!! Max-Min= 156%
7360 20:12:22.558096 [DutyScan_Calibration_Flow] ====Done====
7361 20:12:22.558177
7362 20:12:22.561130 [DutyScan_Calibration_Flow] k_type=1
7363 20:12:22.577252
7364 20:12:22.577334 ==DQS 0 ==
7365 20:12:22.580668 Final DQS duty delay cell = 0
7366 20:12:22.583910 [0] MAX Duty = 5218%(X100), DQS PI = 20
7367 20:12:22.587477 [0] MIN Duty = 4907%(X100), DQS PI = 58
7368 20:12:22.590226 [0] AVG Duty = 5062%(X100)
7369 20:12:22.590306
7370 20:12:22.590368 ==DQS 1 ==
7371 20:12:22.594014 Final DQS duty delay cell = -4
7372 20:12:22.596872 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7373 20:12:22.600309 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7374 20:12:22.603519 [-4] AVG Duty = 4922%(X100)
7375 20:12:22.603599
7376 20:12:22.606731 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7377 20:12:22.606812
7378 20:12:22.610142 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7379 20:12:22.613320 [DutyScan_Calibration_Flow] ====Done====
7380 20:12:22.613402
7381 20:12:22.616738 [DutyScan_Calibration_Flow] k_type=3
7382 20:12:22.634668
7383 20:12:22.634749 ==DQM 0 ==
7384 20:12:22.637804 Final DQM duty delay cell = 0
7385 20:12:22.640954 [0] MAX Duty = 5031%(X100), DQS PI = 30
7386 20:12:22.644286 [0] MIN Duty = 4750%(X100), DQS PI = 40
7387 20:12:22.647601 [0] AVG Duty = 4890%(X100)
7388 20:12:22.647681
7389 20:12:22.647778 ==DQM 1 ==
7390 20:12:22.650846 Final DQM duty delay cell = 0
7391 20:12:22.654446 [0] MAX Duty = 4969%(X100), DQS PI = 30
7392 20:12:22.657387 [0] MIN Duty = 4813%(X100), DQS PI = 0
7393 20:12:22.661154 [0] AVG Duty = 4891%(X100)
7394 20:12:22.661235
7395 20:12:22.664222 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7396 20:12:22.664302
7397 20:12:22.667635 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7398 20:12:22.670953 [DutyScan_Calibration_Flow] ====Done====
7399 20:12:22.671064
7400 20:12:22.674031 [DutyScan_Calibration_Flow] k_type=2
7401 20:12:22.690515
7402 20:12:22.690596 ==DQ 0 ==
7403 20:12:22.693747 Final DQ duty delay cell = -4
7404 20:12:22.697291 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7405 20:12:22.700424 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7406 20:12:22.703790 [-4] AVG Duty = 4875%(X100)
7407 20:12:22.703899
7408 20:12:22.703983 ==DQ 1 ==
7409 20:12:22.706950 Final DQ duty delay cell = 0
7410 20:12:22.710502 [0] MAX Duty = 5062%(X100), DQS PI = 32
7411 20:12:22.714046 [0] MIN Duty = 4844%(X100), DQS PI = 60
7412 20:12:22.716876 [0] AVG Duty = 4953%(X100)
7413 20:12:22.716958
7414 20:12:22.720313 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7415 20:12:22.720424
7416 20:12:22.723489 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7417 20:12:22.726689 [DutyScan_Calibration_Flow] ====Done====
7418 20:12:22.730028 nWR fixed to 30
7419 20:12:22.733414 [ModeRegInit_LP4] CH0 RK0
7420 20:12:22.733497 [ModeRegInit_LP4] CH0 RK1
7421 20:12:22.736620 [ModeRegInit_LP4] CH1 RK0
7422 20:12:22.739893 [ModeRegInit_LP4] CH1 RK1
7423 20:12:22.739975 match AC timing 5
7424 20:12:22.746647 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7425 20:12:22.749817 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7426 20:12:22.753362 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7427 20:12:22.759942 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7428 20:12:22.762827 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7429 20:12:22.766450 [MiockJmeterHQA]
7430 20:12:22.766577
7431 20:12:22.769391 [DramcMiockJmeter] u1RxGatingPI = 0
7432 20:12:22.769520 0 : 4365, 4138
7433 20:12:22.769635 4 : 4363, 4138
7434 20:12:22.773143 8 : 4252, 4027
7435 20:12:22.773272 12 : 4258, 4030
7436 20:12:22.776201 16 : 4258, 4029
7437 20:12:22.776329 20 : 4257, 4029
7438 20:12:22.779385 24 : 4363, 4137
7439 20:12:22.779510 28 : 4363, 4137
7440 20:12:22.779629 32 : 4252, 4027
7441 20:12:22.782960 36 : 4253, 4026
7442 20:12:22.783085 40 : 4252, 4027
7443 20:12:22.786203 44 : 4252, 4027
7444 20:12:22.786330 48 : 4253, 4027
7445 20:12:22.789079 52 : 4361, 4138
7446 20:12:22.789252 56 : 4250, 4026
7447 20:12:22.792687 60 : 4250, 4027
7448 20:12:22.792813 64 : 4252, 4029
7449 20:12:22.792990 68 : 4250, 4026
7450 20:12:22.796191 72 : 4250, 4027
7451 20:12:22.796317 76 : 4363, 4140
7452 20:12:22.799262 80 : 4361, 4137
7453 20:12:22.799422 84 : 4249, 4027
7454 20:12:22.802447 88 : 4252, 4029
7455 20:12:22.802554 92 : 4250, 4027
7456 20:12:22.805750 96 : 4250, 2831
7457 20:12:22.805875 100 : 4250, 0
7458 20:12:22.805991 104 : 4249, 0
7459 20:12:22.809076 108 : 4363, 0
7460 20:12:22.809199 112 : 4361, 0
7461 20:12:22.809313 116 : 4250, 0
7462 20:12:22.812464 120 : 4250, 0
7463 20:12:22.812588 124 : 4250, 0
7464 20:12:22.815517 128 : 4250, 0
7465 20:12:22.815641 132 : 4249, 0
7466 20:12:22.815752 136 : 4250, 0
7467 20:12:22.819211 140 : 4253, 0
7468 20:12:22.819355 144 : 4249, 0
7469 20:12:22.822591 148 : 4250, 0
7470 20:12:22.822715 152 : 4253, 0
7471 20:12:22.822829 156 : 4249, 0
7472 20:12:22.825679 160 : 4360, 0
7473 20:12:22.825829 164 : 4360, 0
7474 20:12:22.829237 168 : 4250, 0
7475 20:12:22.829376 172 : 4252, 0
7476 20:12:22.829485 176 : 4250, 0
7477 20:12:22.832554 180 : 4250, 0
7478 20:12:22.832681 184 : 4249, 0
7479 20:12:22.835604 188 : 4361, 0
7480 20:12:22.835745 192 : 4250, 0
7481 20:12:22.835855 196 : 4249, 0
7482 20:12:22.838682 200 : 4250, 0
7483 20:12:22.838807 204 : 4250, 0
7484 20:12:22.842104 208 : 4252, 0
7485 20:12:22.842230 212 : 4250, 0
7486 20:12:22.842348 216 : 4250, 0
7487 20:12:22.845347 220 : 4250, 1043
7488 20:12:22.845471 224 : 4253, 4017
7489 20:12:22.848729 228 : 4250, 4027
7490 20:12:22.848856 232 : 4249, 4027
7491 20:12:22.852021 236 : 4360, 4137
7492 20:12:22.852147 240 : 4250, 4026
7493 20:12:22.855398 244 : 4250, 4027
7494 20:12:22.855525 248 : 4360, 4138
7495 20:12:22.858525 252 : 4249, 4027
7496 20:12:22.858653 256 : 4250, 4026
7497 20:12:22.858768 260 : 4363, 4140
7498 20:12:22.861868 264 : 4250, 4027
7499 20:12:22.861996 268 : 4249, 4027
7500 20:12:22.865222 272 : 4250, 4026
7501 20:12:22.865349 276 : 4253, 4029
7502 20:12:22.868476 280 : 4250, 4027
7503 20:12:22.868602 284 : 4249, 4027
7504 20:12:22.871573 288 : 4360, 4137
7505 20:12:22.871694 292 : 4250, 4027
7506 20:12:22.875019 296 : 4250, 4027
7507 20:12:22.875143 300 : 4361, 4138
7508 20:12:22.877912 304 : 4250, 4027
7509 20:12:22.878036 308 : 4250, 4026
7510 20:12:22.881751 312 : 4363, 4140
7511 20:12:22.881880 316 : 4250, 4027
7512 20:12:22.884588 320 : 4250, 4027
7513 20:12:22.884720 324 : 4250, 4026
7514 20:12:22.887740 328 : 4253, 4029
7515 20:12:22.887867 332 : 4250, 3969
7516 20:12:22.887984 336 : 4249, 1767
7517 20:12:22.891139
7518 20:12:22.891262 MIOCK jitter meter ch=0
7519 20:12:22.891383
7520 20:12:22.894395 1T = (336-100) = 236 dly cells
7521 20:12:22.901322 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7522 20:12:22.901407 ==
7523 20:12:22.904473 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 20:12:22.907802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 20:12:22.907927 ==
7526 20:12:22.914574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 20:12:22.917833 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 20:12:22.921111 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 20:12:22.927525 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 20:12:22.937356 [CA 0] Center 43 (13~74) winsize 62
7531 20:12:22.940642 [CA 1] Center 42 (12~73) winsize 62
7532 20:12:22.943484 [CA 2] Center 37 (8~67) winsize 60
7533 20:12:22.947154 [CA 3] Center 37 (8~67) winsize 60
7534 20:12:22.950466 [CA 4] Center 36 (6~66) winsize 61
7535 20:12:22.953362 [CA 5] Center 35 (5~66) winsize 62
7536 20:12:22.953446
7537 20:12:22.956700 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 20:12:22.956785
7539 20:12:22.960201 [CATrainingPosCal] consider 1 rank data
7540 20:12:22.963357 u2DelayCellTimex100 = 275/100 ps
7541 20:12:22.969852 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7542 20:12:22.973517 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7543 20:12:22.976556 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7544 20:12:22.980104 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7545 20:12:22.983092 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7546 20:12:22.986800 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7547 20:12:22.986887
7548 20:12:22.990172 CA PerBit enable=1, Macro0, CA PI delay=35
7549 20:12:22.990256
7550 20:12:22.992925 [CBTSetCACLKResult] CA Dly = 35
7551 20:12:22.996452 CS Dly: 10 (0~41)
7552 20:12:22.999611 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 20:12:23.003181 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 20:12:23.003263 ==
7555 20:12:23.006134 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 20:12:23.013002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 20:12:23.013090 ==
7558 20:12:23.015697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 20:12:23.023260 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 20:12:23.026246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 20:12:23.032983 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 20:12:23.040759 [CA 0] Center 44 (14~75) winsize 62
7563 20:12:23.044135 [CA 1] Center 44 (14~74) winsize 61
7564 20:12:23.047295 [CA 2] Center 39 (10~69) winsize 60
7565 20:12:23.050512 [CA 3] Center 39 (10~68) winsize 59
7566 20:12:23.053922 [CA 4] Center 37 (7~67) winsize 61
7567 20:12:23.057235 [CA 5] Center 36 (6~66) winsize 61
7568 20:12:23.057320
7569 20:12:23.060301 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 20:12:23.060384
7571 20:12:23.067079 [CATrainingPosCal] consider 2 rank data
7572 20:12:23.067192 u2DelayCellTimex100 = 275/100 ps
7573 20:12:23.074019 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7574 20:12:23.076845 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7575 20:12:23.079724 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7576 20:12:23.083516 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7577 20:12:23.086738 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 20:12:23.089798 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7579 20:12:23.089898
7580 20:12:23.093426 CA PerBit enable=1, Macro0, CA PI delay=36
7581 20:12:23.093535
7582 20:12:23.096264 [CBTSetCACLKResult] CA Dly = 36
7583 20:12:23.100081 CS Dly: 11 (0~43)
7584 20:12:23.103474 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 20:12:23.106922 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 20:12:23.107007
7587 20:12:23.109934 ----->DramcWriteLeveling(PI) begin...
7588 20:12:23.113220 ==
7589 20:12:23.113304 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 20:12:23.119625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 20:12:23.119709 ==
7592 20:12:23.122729 Write leveling (Byte 0): 35 => 35
7593 20:12:23.126047 Write leveling (Byte 1): 24 => 24
7594 20:12:23.129864 DramcWriteLeveling(PI) end<-----
7595 20:12:23.129947
7596 20:12:23.130012 ==
7597 20:12:23.133182 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 20:12:23.136190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 20:12:23.136274 ==
7600 20:12:23.139555 [Gating] SW mode calibration
7601 20:12:23.145939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 20:12:23.152604 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 20:12:23.156017 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 20:12:23.159264 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 20:12:23.165817 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 20:12:23.168815 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7607 20:12:23.172231 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 20:12:23.179024 1 4 20 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
7609 20:12:23.182096 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 20:12:23.185363 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 20:12:23.191907 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 20:12:23.195439 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 20:12:23.198614 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7614 20:12:23.205248 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7615 20:12:23.208503 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7616 20:12:23.211737 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7617 20:12:23.218099 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 20:12:23.221588 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 20:12:23.224986 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 20:12:23.231901 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 20:12:23.234878 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7622 20:12:23.238346 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7623 20:12:23.244481 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7624 20:12:23.248123 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7625 20:12:23.251258 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 20:12:23.257797 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 20:12:23.261162 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 20:12:23.264156 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 20:12:23.271053 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 20:12:23.274546 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 20:12:23.277552 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7632 20:12:23.284019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7633 20:12:23.287199 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 20:12:23.290437 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 20:12:23.296967 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 20:12:23.300497 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 20:12:23.303944 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 20:12:23.310420 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 20:12:23.313581 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 20:12:23.317078 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 20:12:23.323690 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 20:12:23.326821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 20:12:23.330003 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 20:12:23.336767 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 20:12:23.339722 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 20:12:23.343581 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 20:12:23.349822 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 20:12:23.352883 Total UI for P1: 0, mck2ui 16
7649 20:12:23.356144 best dqsien dly found for B0: ( 1, 9, 12)
7650 20:12:23.359433 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 20:12:23.363013 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 20:12:23.369522 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 20:12:23.372851 Total UI for P1: 0, mck2ui 16
7654 20:12:23.376112 best dqsien dly found for B1: ( 1, 9, 22)
7655 20:12:23.379204 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7656 20:12:23.382726 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7657 20:12:23.382808
7658 20:12:23.385969 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7659 20:12:23.389370 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7660 20:12:23.392405 [Gating] SW calibration Done
7661 20:12:23.392505 ==
7662 20:12:23.395877 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 20:12:23.399027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 20:12:23.399173 ==
7665 20:12:23.402382 RX Vref Scan: 0
7666 20:12:23.402506
7667 20:12:23.405840 RX Vref 0 -> 0, step: 1
7668 20:12:23.405941
7669 20:12:23.406007 RX Delay 0 -> 252, step: 8
7670 20:12:23.412535 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7671 20:12:23.415513 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7672 20:12:23.419155 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7673 20:12:23.422081 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7674 20:12:23.425658 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7675 20:12:23.431949 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7676 20:12:23.435272 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7677 20:12:23.438868 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7678 20:12:23.441764 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7679 20:12:23.448633 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7680 20:12:23.452100 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7681 20:12:23.455641 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7682 20:12:23.458393 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7683 20:12:23.461328 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7684 20:12:23.468170 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7685 20:12:23.472122 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7686 20:12:23.472206 ==
7687 20:12:23.475193 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 20:12:23.478004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 20:12:23.478120 ==
7690 20:12:23.481649 DQS Delay:
7691 20:12:23.481731 DQS0 = 0, DQS1 = 0
7692 20:12:23.481796 DQM Delay:
7693 20:12:23.484712 DQM0 = 131, DQM1 = 125
7694 20:12:23.484794 DQ Delay:
7695 20:12:23.488389 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7696 20:12:23.491493 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7697 20:12:23.498280 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7698 20:12:23.502012 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7699 20:12:23.502094
7700 20:12:23.502158
7701 20:12:23.502218 ==
7702 20:12:23.504505 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 20:12:23.507697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 20:12:23.507780 ==
7705 20:12:23.507844
7706 20:12:23.507904
7707 20:12:23.511179 TX Vref Scan disable
7708 20:12:23.514636 == TX Byte 0 ==
7709 20:12:23.517663 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7710 20:12:23.520891 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7711 20:12:23.524401 == TX Byte 1 ==
7712 20:12:23.527746 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7713 20:12:23.531276 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7714 20:12:23.531367 ==
7715 20:12:23.534538 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 20:12:23.537451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 20:12:23.541172 ==
7718 20:12:23.554857
7719 20:12:23.557614 TX Vref early break, caculate TX vref
7720 20:12:23.561161 TX Vref=16, minBit 7, minWin=21, winSum=365
7721 20:12:23.564106 TX Vref=18, minBit 8, minWin=22, winSum=376
7722 20:12:23.567422 TX Vref=20, minBit 7, minWin=23, winSum=388
7723 20:12:23.570505 TX Vref=22, minBit 1, minWin=23, winSum=396
7724 20:12:23.574131 TX Vref=24, minBit 7, minWin=24, winSum=405
7725 20:12:23.580571 TX Vref=26, minBit 1, minWin=24, winSum=409
7726 20:12:23.583952 TX Vref=28, minBit 2, minWin=25, winSum=414
7727 20:12:23.587320 TX Vref=30, minBit 4, minWin=24, winSum=409
7728 20:12:23.590438 TX Vref=32, minBit 0, minWin=25, winSum=406
7729 20:12:23.593711 TX Vref=34, minBit 1, minWin=24, winSum=396
7730 20:12:23.600476 TX Vref=36, minBit 2, minWin=23, winSum=385
7731 20:12:23.603225 [TxChooseVref] Worse bit 2, Min win 25, Win sum 414, Final Vref 28
7732 20:12:23.603308
7733 20:12:23.606787 Final TX Range 0 Vref 28
7734 20:12:23.606869
7735 20:12:23.606932 ==
7736 20:12:23.609772 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 20:12:23.613381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 20:12:23.616323 ==
7739 20:12:23.616405
7740 20:12:23.616467
7741 20:12:23.616525 TX Vref Scan disable
7742 20:12:23.623708 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7743 20:12:23.623789 == TX Byte 0 ==
7744 20:12:23.627081 u2DelayCellOfst[0]=14 cells (4 PI)
7745 20:12:23.629932 u2DelayCellOfst[1]=21 cells (6 PI)
7746 20:12:23.633204 u2DelayCellOfst[2]=14 cells (4 PI)
7747 20:12:23.636914 u2DelayCellOfst[3]=14 cells (4 PI)
7748 20:12:23.639936 u2DelayCellOfst[4]=10 cells (3 PI)
7749 20:12:23.643707 u2DelayCellOfst[5]=0 cells (0 PI)
7750 20:12:23.646498 u2DelayCellOfst[6]=21 cells (6 PI)
7751 20:12:23.649735 u2DelayCellOfst[7]=17 cells (5 PI)
7752 20:12:23.653290 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7753 20:12:23.656551 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7754 20:12:23.659542 == TX Byte 1 ==
7755 20:12:23.662808 u2DelayCellOfst[8]=0 cells (0 PI)
7756 20:12:23.666086 u2DelayCellOfst[9]=3 cells (1 PI)
7757 20:12:23.670160 u2DelayCellOfst[10]=7 cells (2 PI)
7758 20:12:23.672879 u2DelayCellOfst[11]=3 cells (1 PI)
7759 20:12:23.676578 u2DelayCellOfst[12]=10 cells (3 PI)
7760 20:12:23.679681 u2DelayCellOfst[13]=10 cells (3 PI)
7761 20:12:23.682904 u2DelayCellOfst[14]=17 cells (5 PI)
7762 20:12:23.686170 u2DelayCellOfst[15]=10 cells (3 PI)
7763 20:12:23.689819 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7764 20:12:23.693117 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7765 20:12:23.696063 DramC Write-DBI on
7766 20:12:23.696144 ==
7767 20:12:23.699143 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 20:12:23.702415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 20:12:23.702497 ==
7770 20:12:23.702560
7771 20:12:23.702619
7772 20:12:23.705984 TX Vref Scan disable
7773 20:12:23.709007 == TX Byte 0 ==
7774 20:12:23.712438 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7775 20:12:23.712519 == TX Byte 1 ==
7776 20:12:23.719233 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7777 20:12:23.719317 DramC Write-DBI off
7778 20:12:23.719404
7779 20:12:23.719465 [DATLAT]
7780 20:12:23.722345 Freq=1600, CH0 RK0
7781 20:12:23.722439
7782 20:12:23.725830 DATLAT Default: 0xf
7783 20:12:23.725911 0, 0xFFFF, sum = 0
7784 20:12:23.728816 1, 0xFFFF, sum = 0
7785 20:12:23.728898 2, 0xFFFF, sum = 0
7786 20:12:23.731970 3, 0xFFFF, sum = 0
7787 20:12:23.732090 4, 0xFFFF, sum = 0
7788 20:12:23.735234 5, 0xFFFF, sum = 0
7789 20:12:23.735317 6, 0xFFFF, sum = 0
7790 20:12:23.738678 7, 0xFFFF, sum = 0
7791 20:12:23.738761 8, 0xFFFF, sum = 0
7792 20:12:23.742586 9, 0xFFFF, sum = 0
7793 20:12:23.742669 10, 0xFFFF, sum = 0
7794 20:12:23.745437 11, 0xFFFF, sum = 0
7795 20:12:23.748927 12, 0xFFFF, sum = 0
7796 20:12:23.749021 13, 0xFFFF, sum = 0
7797 20:12:23.751651 14, 0x0, sum = 1
7798 20:12:23.751737 15, 0x0, sum = 2
7799 20:12:23.751802 16, 0x0, sum = 3
7800 20:12:23.754899 17, 0x0, sum = 4
7801 20:12:23.754982 best_step = 15
7802 20:12:23.755045
7803 20:12:23.758289 ==
7804 20:12:23.761944 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 20:12:23.765394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 20:12:23.765476 ==
7807 20:12:23.765540 RX Vref Scan: 1
7808 20:12:23.765598
7809 20:12:23.767875 Set Vref Range= 24 -> 127
7810 20:12:23.767955
7811 20:12:23.771187 RX Vref 24 -> 127, step: 1
7812 20:12:23.771269
7813 20:12:23.774741 RX Delay 11 -> 252, step: 4
7814 20:12:23.774835
7815 20:12:23.777867 Set Vref, RX VrefLevel [Byte0]: 24
7816 20:12:23.781232 [Byte1]: 24
7817 20:12:23.781313
7818 20:12:23.784382 Set Vref, RX VrefLevel [Byte0]: 25
7819 20:12:23.787697 [Byte1]: 25
7820 20:12:23.787779
7821 20:12:23.791328 Set Vref, RX VrefLevel [Byte0]: 26
7822 20:12:23.794778 [Byte1]: 26
7823 20:12:23.797984
7824 20:12:23.798065 Set Vref, RX VrefLevel [Byte0]: 27
7825 20:12:23.801461 [Byte1]: 27
7826 20:12:23.805591
7827 20:12:23.805672 Set Vref, RX VrefLevel [Byte0]: 28
7828 20:12:23.809284 [Byte1]: 28
7829 20:12:23.813373
7830 20:12:23.813454 Set Vref, RX VrefLevel [Byte0]: 29
7831 20:12:23.816628 [Byte1]: 29
7832 20:12:23.820929
7833 20:12:23.821009 Set Vref, RX VrefLevel [Byte0]: 30
7834 20:12:23.824118 [Byte1]: 30
7835 20:12:23.828787
7836 20:12:23.828869 Set Vref, RX VrefLevel [Byte0]: 31
7837 20:12:23.832132 [Byte1]: 31
7838 20:12:23.836670
7839 20:12:23.836762 Set Vref, RX VrefLevel [Byte0]: 32
7840 20:12:23.839633 [Byte1]: 32
7841 20:12:23.844156
7842 20:12:23.844237 Set Vref, RX VrefLevel [Byte0]: 33
7843 20:12:23.847284 [Byte1]: 33
7844 20:12:23.852189
7845 20:12:23.852270 Set Vref, RX VrefLevel [Byte0]: 34
7846 20:12:23.854845 [Byte1]: 34
7847 20:12:23.859152
7848 20:12:23.859284 Set Vref, RX VrefLevel [Byte0]: 35
7849 20:12:23.862446 [Byte1]: 35
7850 20:12:23.866496
7851 20:12:23.866577 Set Vref, RX VrefLevel [Byte0]: 36
7852 20:12:23.870050 [Byte1]: 36
7853 20:12:23.874303
7854 20:12:23.874441 Set Vref, RX VrefLevel [Byte0]: 37
7855 20:12:23.877503 [Byte1]: 37
7856 20:12:23.881781
7857 20:12:23.881862 Set Vref, RX VrefLevel [Byte0]: 38
7858 20:12:23.885358 [Byte1]: 38
7859 20:12:23.889673
7860 20:12:23.889754 Set Vref, RX VrefLevel [Byte0]: 39
7861 20:12:23.892948 [Byte1]: 39
7862 20:12:23.897104
7863 20:12:23.897213 Set Vref, RX VrefLevel [Byte0]: 40
7864 20:12:23.900281 [Byte1]: 40
7865 20:12:23.905073
7866 20:12:23.905158 Set Vref, RX VrefLevel [Byte0]: 41
7867 20:12:23.907870 [Byte1]: 41
7868 20:12:23.912604
7869 20:12:23.912731 Set Vref, RX VrefLevel [Byte0]: 42
7870 20:12:23.915632 [Byte1]: 42
7871 20:12:23.919976
7872 20:12:23.920099 Set Vref, RX VrefLevel [Byte0]: 43
7873 20:12:23.923286 [Byte1]: 43
7874 20:12:23.927510
7875 20:12:23.927633 Set Vref, RX VrefLevel [Byte0]: 44
7876 20:12:23.930934 [Byte1]: 44
7877 20:12:23.934920
7878 20:12:23.935045 Set Vref, RX VrefLevel [Byte0]: 45
7879 20:12:23.938501 [Byte1]: 45
7880 20:12:23.942695
7881 20:12:23.942818 Set Vref, RX VrefLevel [Byte0]: 46
7882 20:12:23.945980 [Byte1]: 46
7883 20:12:23.950708
7884 20:12:23.950833 Set Vref, RX VrefLevel [Byte0]: 47
7885 20:12:23.953974 [Byte1]: 47
7886 20:12:23.957919
7887 20:12:23.958024 Set Vref, RX VrefLevel [Byte0]: 48
7888 20:12:23.961437 [Byte1]: 48
7889 20:12:23.965421
7890 20:12:23.965503 Set Vref, RX VrefLevel [Byte0]: 49
7891 20:12:23.969058 [Byte1]: 49
7892 20:12:23.973726
7893 20:12:23.973848 Set Vref, RX VrefLevel [Byte0]: 50
7894 20:12:23.976475 [Byte1]: 50
7895 20:12:23.980748
7896 20:12:23.980871 Set Vref, RX VrefLevel [Byte0]: 51
7897 20:12:23.983887 [Byte1]: 51
7898 20:12:23.988368
7899 20:12:23.988487 Set Vref, RX VrefLevel [Byte0]: 52
7900 20:12:23.991883 [Byte1]: 52
7901 20:12:23.996315
7902 20:12:23.996438 Set Vref, RX VrefLevel [Byte0]: 53
7903 20:12:23.999443 [Byte1]: 53
7904 20:12:24.003664
7905 20:12:24.003768 Set Vref, RX VrefLevel [Byte0]: 54
7906 20:12:24.006854 [Byte1]: 54
7907 20:12:24.011041
7908 20:12:24.011122 Set Vref, RX VrefLevel [Byte0]: 55
7909 20:12:24.014670 [Byte1]: 55
7910 20:12:24.018820
7911 20:12:24.018902 Set Vref, RX VrefLevel [Byte0]: 56
7912 20:12:24.021949 [Byte1]: 56
7913 20:12:24.026784
7914 20:12:24.026866 Set Vref, RX VrefLevel [Byte0]: 57
7915 20:12:24.029628 [Byte1]: 57
7916 20:12:24.034593
7917 20:12:24.034735 Set Vref, RX VrefLevel [Byte0]: 58
7918 20:12:24.037186 [Byte1]: 58
7919 20:12:24.041723
7920 20:12:24.041805 Set Vref, RX VrefLevel [Byte0]: 59
7921 20:12:24.045176 [Byte1]: 59
7922 20:12:24.049329
7923 20:12:24.049411 Set Vref, RX VrefLevel [Byte0]: 60
7924 20:12:24.052717 [Byte1]: 60
7925 20:12:24.057311
7926 20:12:24.057393 Set Vref, RX VrefLevel [Byte0]: 61
7927 20:12:24.060233 [Byte1]: 61
7928 20:12:24.064766
7929 20:12:24.064893 Set Vref, RX VrefLevel [Byte0]: 62
7930 20:12:24.067874 [Byte1]: 62
7931 20:12:24.072496
7932 20:12:24.072579 Set Vref, RX VrefLevel [Byte0]: 63
7933 20:12:24.075404 [Byte1]: 63
7934 20:12:24.079905
7935 20:12:24.079988 Set Vref, RX VrefLevel [Byte0]: 64
7936 20:12:24.082877 [Byte1]: 64
7937 20:12:24.087776
7938 20:12:24.087908 Set Vref, RX VrefLevel [Byte0]: 65
7939 20:12:24.090616 [Byte1]: 65
7940 20:12:24.095099
7941 20:12:24.095181 Set Vref, RX VrefLevel [Byte0]: 66
7942 20:12:24.098562 [Byte1]: 66
7943 20:12:24.102915
7944 20:12:24.102997 Set Vref, RX VrefLevel [Byte0]: 67
7945 20:12:24.105944 [Byte1]: 67
7946 20:12:24.110253
7947 20:12:24.110335 Set Vref, RX VrefLevel [Byte0]: 68
7948 20:12:24.113582 [Byte1]: 68
7949 20:12:24.118003
7950 20:12:24.118085 Set Vref, RX VrefLevel [Byte0]: 69
7951 20:12:24.121406 [Byte1]: 69
7952 20:12:24.125687
7953 20:12:24.125768 Set Vref, RX VrefLevel [Byte0]: 70
7954 20:12:24.129003 [Byte1]: 70
7955 20:12:24.133210
7956 20:12:24.133291 Set Vref, RX VrefLevel [Byte0]: 71
7957 20:12:24.136203 [Byte1]: 71
7958 20:12:24.140907
7959 20:12:24.140988 Set Vref, RX VrefLevel [Byte0]: 72
7960 20:12:24.147011 [Byte1]: 72
7961 20:12:24.147092
7962 20:12:24.150402 Set Vref, RX VrefLevel [Byte0]: 73
7963 20:12:24.153736 [Byte1]: 73
7964 20:12:24.153818
7965 20:12:24.156905 Final RX Vref Byte 0 = 55 to rank0
7966 20:12:24.161204 Final RX Vref Byte 1 = 57 to rank0
7967 20:12:24.163251 Final RX Vref Byte 0 = 55 to rank1
7968 20:12:24.166767 Final RX Vref Byte 1 = 57 to rank1==
7969 20:12:24.170164 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 20:12:24.173111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 20:12:24.173198 ==
7972 20:12:24.176917 DQS Delay:
7973 20:12:24.176998 DQS0 = 0, DQS1 = 0
7974 20:12:24.179808 DQM Delay:
7975 20:12:24.179889 DQM0 = 128, DQM1 = 124
7976 20:12:24.179953 DQ Delay:
7977 20:12:24.186491 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7978 20:12:24.189885 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7979 20:12:24.193501 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7980 20:12:24.196889 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
7981 20:12:24.196976
7982 20:12:24.197040
7983 20:12:24.197099
7984 20:12:24.199794 [DramC_TX_OE_Calibration] TA2
7985 20:12:24.203488 Original DQ_B0 (3 6) =30, OEN = 27
7986 20:12:24.206633 Original DQ_B1 (3 6) =30, OEN = 27
7987 20:12:24.206714 24, 0x0, End_B0=24 End_B1=24
7988 20:12:24.209924 25, 0x0, End_B0=25 End_B1=25
7989 20:12:24.213393 26, 0x0, End_B0=26 End_B1=26
7990 20:12:24.216354 27, 0x0, End_B0=27 End_B1=27
7991 20:12:24.219574 28, 0x0, End_B0=28 End_B1=28
7992 20:12:24.219657 29, 0x0, End_B0=29 End_B1=29
7993 20:12:24.222756 30, 0x0, End_B0=30 End_B1=30
7994 20:12:24.225969 31, 0x4141, End_B0=30 End_B1=30
7995 20:12:24.229195 Byte0 end_step=30 best_step=27
7996 20:12:24.232987 Byte1 end_step=30 best_step=27
7997 20:12:24.236033 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 20:12:24.236159 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 20:12:24.236226
8000 20:12:24.238981
8001 20:12:24.245750 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8002 20:12:24.248937 CH0 RK0: MR19=303, MR18=1714
8003 20:12:24.255552 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
8004 20:12:24.255635
8005 20:12:24.259072 ----->DramcWriteLeveling(PI) begin...
8006 20:12:24.259184 ==
8007 20:12:24.262120 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 20:12:24.265906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 20:12:24.266011 ==
8010 20:12:24.269421 Write leveling (Byte 0): 32 => 32
8011 20:12:24.272380 Write leveling (Byte 1): 25 => 25
8012 20:12:24.275623 DramcWriteLeveling(PI) end<-----
8013 20:12:24.275705
8014 20:12:24.275768 ==
8015 20:12:24.278792 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 20:12:24.282034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 20:12:24.282116 ==
8018 20:12:24.285428 [Gating] SW mode calibration
8019 20:12:24.291852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 20:12:24.298682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 20:12:24.301509 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 20:12:24.308567 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 20:12:24.311550 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8024 20:12:24.314985 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8025 20:12:24.321115 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8026 20:12:24.324530 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8027 20:12:24.327712 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 20:12:24.334809 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 20:12:24.337739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 20:12:24.341513 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 20:12:24.347735 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8032 20:12:24.350896 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8033 20:12:24.354505 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8034 20:12:24.360796 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8035 20:12:24.364779 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 20:12:24.367526 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 20:12:24.373939 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 20:12:24.377771 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8039 20:12:24.380936 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8040 20:12:24.387178 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8041 20:12:24.390580 1 6 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8042 20:12:24.394011 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8043 20:12:24.400642 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 20:12:24.403807 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 20:12:24.407056 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 20:12:24.413788 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 20:12:24.417235 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 20:12:24.420324 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8049 20:12:24.426851 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8050 20:12:24.429918 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8051 20:12:24.433560 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 20:12:24.439926 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 20:12:24.443045 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 20:12:24.447025 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 20:12:24.452940 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 20:12:24.456200 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 20:12:24.459579 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 20:12:24.466883 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 20:12:24.469620 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 20:12:24.473033 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 20:12:24.479281 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 20:12:24.482994 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 20:12:24.486255 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8064 20:12:24.492978 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8065 20:12:24.493060 Total UI for P1: 0, mck2ui 16
8066 20:12:24.499151 best dqsien dly found for B0: ( 1, 9, 8)
8067 20:12:24.502364 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8068 20:12:24.505471 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8069 20:12:24.512102 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 20:12:24.512221 Total UI for P1: 0, mck2ui 16
8071 20:12:24.518737 best dqsien dly found for B1: ( 1, 9, 18)
8072 20:12:24.522523 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8073 20:12:24.525572 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8074 20:12:24.525654
8075 20:12:24.528515 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8076 20:12:24.532144 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8077 20:12:24.535263 [Gating] SW calibration Done
8078 20:12:24.535344 ==
8079 20:12:24.538354 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 20:12:24.541906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 20:12:24.541988 ==
8082 20:12:24.545113 RX Vref Scan: 0
8083 20:12:24.545194
8084 20:12:24.545257 RX Vref 0 -> 0, step: 1
8085 20:12:24.548685
8086 20:12:24.548766 RX Delay 0 -> 252, step: 8
8087 20:12:24.554815 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8088 20:12:24.558298 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8089 20:12:24.562219 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8090 20:12:24.564949 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8091 20:12:24.568194 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8092 20:12:24.575072 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8093 20:12:24.578044 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8094 20:12:24.581793 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8095 20:12:24.584670 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8096 20:12:24.587759 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8097 20:12:24.594894 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8098 20:12:24.597968 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8099 20:12:24.601199 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8100 20:12:24.604506 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8101 20:12:24.611020 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8102 20:12:24.614728 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8103 20:12:24.614809 ==
8104 20:12:24.617606 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 20:12:24.621152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 20:12:24.621234 ==
8107 20:12:24.621298 DQS Delay:
8108 20:12:24.624452 DQS0 = 0, DQS1 = 0
8109 20:12:24.624533 DQM Delay:
8110 20:12:24.627757 DQM0 = 131, DQM1 = 127
8111 20:12:24.627838 DQ Delay:
8112 20:12:24.630707 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8113 20:12:24.633896 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8114 20:12:24.637468 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8115 20:12:24.643884 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8116 20:12:24.643966
8117 20:12:24.644029
8118 20:12:24.644088 ==
8119 20:12:24.646936 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 20:12:24.650291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 20:12:24.650373 ==
8122 20:12:24.650437
8123 20:12:24.650496
8124 20:12:24.653598 TX Vref Scan disable
8125 20:12:24.653679 == TX Byte 0 ==
8126 20:12:24.660443 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8127 20:12:24.663607 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8128 20:12:24.663688 == TX Byte 1 ==
8129 20:12:24.670204 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8130 20:12:24.673454 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8131 20:12:24.673535 ==
8132 20:12:24.676618 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 20:12:24.680080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 20:12:24.682930 ==
8135 20:12:24.694878
8136 20:12:24.698278 TX Vref early break, caculate TX vref
8137 20:12:24.702212 TX Vref=16, minBit 1, minWin=23, winSum=382
8138 20:12:24.704862 TX Vref=18, minBit 9, minWin=23, winSum=392
8139 20:12:24.708166 TX Vref=20, minBit 0, minWin=24, winSum=400
8140 20:12:24.711642 TX Vref=22, minBit 13, minWin=24, winSum=403
8141 20:12:24.717811 TX Vref=24, minBit 1, minWin=25, winSum=409
8142 20:12:24.721364 TX Vref=26, minBit 11, minWin=25, winSum=417
8143 20:12:24.724238 TX Vref=28, minBit 10, minWin=25, winSum=417
8144 20:12:24.727782 TX Vref=30, minBit 4, minWin=25, winSum=412
8145 20:12:24.731027 TX Vref=32, minBit 1, minWin=24, winSum=404
8146 20:12:24.737634 TX Vref=34, minBit 11, minWin=23, winSum=389
8147 20:12:24.740726 [TxChooseVref] Worse bit 11, Min win 25, Win sum 417, Final Vref 26
8148 20:12:24.740808
8149 20:12:24.743921 Final TX Range 0 Vref 26
8150 20:12:24.744033
8151 20:12:24.744126 ==
8152 20:12:24.747483 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 20:12:24.750651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 20:12:24.754066 ==
8155 20:12:24.754148
8156 20:12:24.754212
8157 20:12:24.754271 TX Vref Scan disable
8158 20:12:24.761099 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8159 20:12:24.761181 == TX Byte 0 ==
8160 20:12:24.763993 u2DelayCellOfst[0]=10 cells (3 PI)
8161 20:12:24.767159 u2DelayCellOfst[1]=14 cells (4 PI)
8162 20:12:24.770320 u2DelayCellOfst[2]=7 cells (2 PI)
8163 20:12:24.774009 u2DelayCellOfst[3]=10 cells (3 PI)
8164 20:12:24.777141 u2DelayCellOfst[4]=7 cells (2 PI)
8165 20:12:24.780842 u2DelayCellOfst[5]=0 cells (0 PI)
8166 20:12:24.783961 u2DelayCellOfst[6]=14 cells (4 PI)
8167 20:12:24.787040 u2DelayCellOfst[7]=14 cells (4 PI)
8168 20:12:24.790149 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8169 20:12:24.793921 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8170 20:12:24.797073 == TX Byte 1 ==
8171 20:12:24.800519 u2DelayCellOfst[8]=0 cells (0 PI)
8172 20:12:24.804103 u2DelayCellOfst[9]=0 cells (0 PI)
8173 20:12:24.806976 u2DelayCellOfst[10]=3 cells (1 PI)
8174 20:12:24.810258 u2DelayCellOfst[11]=0 cells (0 PI)
8175 20:12:24.813200 u2DelayCellOfst[12]=7 cells (2 PI)
8176 20:12:24.813282 u2DelayCellOfst[13]=7 cells (2 PI)
8177 20:12:24.816723 u2DelayCellOfst[14]=10 cells (3 PI)
8178 20:12:24.819961 u2DelayCellOfst[15]=10 cells (3 PI)
8179 20:12:24.826765 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8180 20:12:24.829992 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8181 20:12:24.833378 DramC Write-DBI on
8182 20:12:24.833460 ==
8183 20:12:24.836632 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 20:12:24.839937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 20:12:24.840020 ==
8186 20:12:24.840085
8187 20:12:24.840144
8188 20:12:24.843028 TX Vref Scan disable
8189 20:12:24.843113 == TX Byte 0 ==
8190 20:12:24.849670 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8191 20:12:24.849752 == TX Byte 1 ==
8192 20:12:24.853026 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8193 20:12:24.856111 DramC Write-DBI off
8194 20:12:24.856194
8195 20:12:24.856258 [DATLAT]
8196 20:12:24.859392 Freq=1600, CH0 RK1
8197 20:12:24.859489
8198 20:12:24.859554 DATLAT Default: 0xf
8199 20:12:24.862974 0, 0xFFFF, sum = 0
8200 20:12:24.866002 1, 0xFFFF, sum = 0
8201 20:12:24.866085 2, 0xFFFF, sum = 0
8202 20:12:24.869524 3, 0xFFFF, sum = 0
8203 20:12:24.869608 4, 0xFFFF, sum = 0
8204 20:12:24.872501 5, 0xFFFF, sum = 0
8205 20:12:24.872585 6, 0xFFFF, sum = 0
8206 20:12:24.876102 7, 0xFFFF, sum = 0
8207 20:12:24.876213 8, 0xFFFF, sum = 0
8208 20:12:24.878823 9, 0xFFFF, sum = 0
8209 20:12:24.878907 10, 0xFFFF, sum = 0
8210 20:12:24.882897 11, 0xFFFF, sum = 0
8211 20:12:24.882981 12, 0xFFFF, sum = 0
8212 20:12:24.885546 13, 0xFFFF, sum = 0
8213 20:12:24.885630 14, 0x0, sum = 1
8214 20:12:24.889062 15, 0x0, sum = 2
8215 20:12:24.889145 16, 0x0, sum = 3
8216 20:12:24.892531 17, 0x0, sum = 4
8217 20:12:24.892614 best_step = 15
8218 20:12:24.892678
8219 20:12:24.892737 ==
8220 20:12:24.895480 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 20:12:24.901963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 20:12:24.902046 ==
8223 20:12:24.902110 RX Vref Scan: 0
8224 20:12:24.902170
8225 20:12:24.905600 RX Vref 0 -> 0, step: 1
8226 20:12:24.905682
8227 20:12:24.908702 RX Delay 11 -> 252, step: 4
8228 20:12:24.911828 iDelay=191, Bit 0, Center 124 (75 ~ 174) 100
8229 20:12:24.915305 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8230 20:12:24.921794 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8231 20:12:24.925547 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8232 20:12:24.928534 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8233 20:12:24.931779 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8234 20:12:24.935229 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8235 20:12:24.941807 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8236 20:12:24.944704 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8237 20:12:24.948094 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8238 20:12:24.951189 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8239 20:12:24.954720 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8240 20:12:24.961619 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8241 20:12:24.964362 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8242 20:12:24.967981 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8243 20:12:24.971527 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8244 20:12:24.974432 ==
8245 20:12:24.974515 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 20:12:24.980694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 20:12:24.980777 ==
8248 20:12:24.980841 DQS Delay:
8249 20:12:24.984123 DQS0 = 0, DQS1 = 0
8250 20:12:24.984205 DQM Delay:
8251 20:12:24.987558 DQM0 = 128, DQM1 = 124
8252 20:12:24.987641 DQ Delay:
8253 20:12:24.990948 DQ0 =124, DQ1 =132, DQ2 =122, DQ3 =126
8254 20:12:24.994034 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8255 20:12:24.997327 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
8256 20:12:25.000938 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8257 20:12:25.001020
8258 20:12:25.001083
8259 20:12:25.001141
8260 20:12:25.003917 [DramC_TX_OE_Calibration] TA2
8261 20:12:25.007240 Original DQ_B0 (3 6) =30, OEN = 27
8262 20:12:25.010605 Original DQ_B1 (3 6) =30, OEN = 27
8263 20:12:25.014113 24, 0x0, End_B0=24 End_B1=24
8264 20:12:25.017256 25, 0x0, End_B0=25 End_B1=25
8265 20:12:25.017366 26, 0x0, End_B0=26 End_B1=26
8266 20:12:25.020268 27, 0x0, End_B0=27 End_B1=27
8267 20:12:25.023579 28, 0x0, End_B0=28 End_B1=28
8268 20:12:25.027202 29, 0x0, End_B0=29 End_B1=29
8269 20:12:25.030202 30, 0x0, End_B0=30 End_B1=30
8270 20:12:25.030314 31, 0x4141, End_B0=30 End_B1=30
8271 20:12:25.033243 Byte0 end_step=30 best_step=27
8272 20:12:25.036560 Byte1 end_step=30 best_step=27
8273 20:12:25.039919 Byte0 TX OE(2T, 0.5T) = (3, 3)
8274 20:12:25.043113 Byte1 TX OE(2T, 0.5T) = (3, 3)
8275 20:12:25.043194
8276 20:12:25.043257
8277 20:12:25.050310 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8278 20:12:25.052919 CH0 RK1: MR19=303, MR18=1210
8279 20:12:25.060114 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8280 20:12:25.063064 [RxdqsGatingPostProcess] freq 1600
8281 20:12:25.069677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8282 20:12:25.072828 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 20:12:25.076195 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 20:12:25.079505 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 20:12:25.082740 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 20:12:25.082882 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 20:12:25.085997 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 20:12:25.089194 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 20:12:25.092948 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 20:12:25.095738 Pre-setting of DQS Precalculation
8291 20:12:25.102877 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8292 20:12:25.102960 ==
8293 20:12:25.105894 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 20:12:25.108941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 20:12:25.109024 ==
8296 20:12:25.115509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 20:12:25.119284 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 20:12:25.122120 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 20:12:25.128507 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 20:12:25.137495 [CA 0] Center 42 (12~72) winsize 61
8301 20:12:25.141017 [CA 1] Center 42 (12~72) winsize 61
8302 20:12:25.144335 [CA 2] Center 38 (9~67) winsize 59
8303 20:12:25.147725 [CA 3] Center 37 (8~66) winsize 59
8304 20:12:25.150647 [CA 4] Center 37 (7~68) winsize 62
8305 20:12:25.153899 [CA 5] Center 36 (7~66) winsize 60
8306 20:12:25.153981
8307 20:12:25.157527 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8308 20:12:25.157608
8309 20:12:25.163968 [CATrainingPosCal] consider 1 rank data
8310 20:12:25.164050 u2DelayCellTimex100 = 275/100 ps
8311 20:12:25.170511 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8312 20:12:25.173828 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8313 20:12:25.176870 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8314 20:12:25.180406 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8315 20:12:25.183588 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8316 20:12:25.186942 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 20:12:25.187025
8318 20:12:25.190434 CA PerBit enable=1, Macro0, CA PI delay=36
8319 20:12:25.190515
8320 20:12:25.193618 [CBTSetCACLKResult] CA Dly = 36
8321 20:12:25.196826 CS Dly: 7 (0~38)
8322 20:12:25.200054 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 20:12:25.203345 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 20:12:25.203463 ==
8325 20:12:25.206557 Dram Type= 6, Freq= 0, CH_1, rank 1
8326 20:12:25.213314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 20:12:25.213396 ==
8328 20:12:25.216459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 20:12:25.222861 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 20:12:25.226779 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 20:12:25.232876 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 20:12:25.240741 [CA 0] Center 41 (11~71) winsize 61
8333 20:12:25.244270 [CA 1] Center 41 (12~71) winsize 60
8334 20:12:25.247221 [CA 2] Center 37 (8~67) winsize 60
8335 20:12:25.250414 [CA 3] Center 36 (7~65) winsize 59
8336 20:12:25.254144 [CA 4] Center 37 (7~67) winsize 61
8337 20:12:25.257210 [CA 5] Center 35 (6~65) winsize 60
8338 20:12:25.257292
8339 20:12:25.260514 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8340 20:12:25.260595
8341 20:12:25.264108 [CATrainingPosCal] consider 2 rank data
8342 20:12:25.267398 u2DelayCellTimex100 = 275/100 ps
8343 20:12:25.273789 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8344 20:12:25.276971 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8345 20:12:25.280543 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8346 20:12:25.284023 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8347 20:12:25.286801 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8348 20:12:25.290479 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8349 20:12:25.290561
8350 20:12:25.293644 CA PerBit enable=1, Macro0, CA PI delay=36
8351 20:12:25.293726
8352 20:12:25.296874 [CBTSetCACLKResult] CA Dly = 36
8353 20:12:25.300049 CS Dly: 9 (0~42)
8354 20:12:25.303349 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 20:12:25.306445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 20:12:25.306526
8357 20:12:25.309763 ----->DramcWriteLeveling(PI) begin...
8358 20:12:25.309846 ==
8359 20:12:25.313455 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 20:12:25.320150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 20:12:25.320258 ==
8362 20:12:25.323254 Write leveling (Byte 0): 24 => 24
8363 20:12:25.326483 Write leveling (Byte 1): 26 => 26
8364 20:12:25.329697 DramcWriteLeveling(PI) end<-----
8365 20:12:25.329778
8366 20:12:25.329841 ==
8367 20:12:25.332868 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 20:12:25.336218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 20:12:25.336299 ==
8370 20:12:25.339319 [Gating] SW mode calibration
8371 20:12:25.345902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8372 20:12:25.352611 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8373 20:12:25.355753 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 20:12:25.359758 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 20:12:25.365679 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8376 20:12:25.369297 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8377 20:12:25.372588 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 20:12:25.378857 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 20:12:25.382488 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 20:12:25.385604 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 20:12:25.392419 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 20:12:25.395109 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 20:12:25.398878 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8384 20:12:25.405921 1 5 12 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (1 0)
8385 20:12:25.408501 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8386 20:12:25.411877 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 20:12:25.418315 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 20:12:25.421816 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 20:12:25.425066 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 20:12:25.431548 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 20:12:25.434881 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8392 20:12:25.438284 1 6 12 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
8393 20:12:25.444566 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 20:12:25.448222 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 20:12:25.451344 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 20:12:25.457767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 20:12:25.461485 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 20:12:25.464341 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 20:12:25.471492 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8400 20:12:25.474017 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8401 20:12:25.477512 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8402 20:12:25.484611 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 20:12:25.487414 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 20:12:25.490772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 20:12:25.497772 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 20:12:25.500705 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 20:12:25.503720 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 20:12:25.510867 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 20:12:25.513786 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 20:12:25.516908 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 20:12:25.523491 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 20:12:25.527060 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 20:12:25.530130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 20:12:25.536685 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 20:12:25.540720 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8416 20:12:25.543140 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 20:12:25.550278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 20:12:25.550364 Total UI for P1: 0, mck2ui 16
8419 20:12:25.556880 best dqsien dly found for B0: ( 1, 9, 10)
8420 20:12:25.556965 Total UI for P1: 0, mck2ui 16
8421 20:12:25.562965 best dqsien dly found for B1: ( 1, 9, 12)
8422 20:12:25.566141 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8423 20:12:25.569718 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8424 20:12:25.569802
8425 20:12:25.572877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 20:12:25.576229 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8427 20:12:25.579336 [Gating] SW calibration Done
8428 20:12:25.579464 ==
8429 20:12:25.583195 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 20:12:25.586047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 20:12:25.586134 ==
8432 20:12:25.589816 RX Vref Scan: 0
8433 20:12:25.589902
8434 20:12:25.589988 RX Vref 0 -> 0, step: 1
8435 20:12:25.592668
8436 20:12:25.592753 RX Delay 0 -> 252, step: 8
8437 20:12:25.596363 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8438 20:12:25.603140 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8439 20:12:25.606038 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8440 20:12:25.609880 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 20:12:25.612651 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8442 20:12:25.618875 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8443 20:12:25.622477 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8444 20:12:25.625411 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8445 20:12:25.629084 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8446 20:12:25.632309 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8447 20:12:25.638659 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8448 20:12:25.641747 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8449 20:12:25.645205 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8450 20:12:25.648506 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8451 20:12:25.654892 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8452 20:12:25.658851 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8453 20:12:25.658934 ==
8454 20:12:25.661819 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 20:12:25.664826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 20:12:25.664909 ==
8457 20:12:25.668131 DQS Delay:
8458 20:12:25.668213 DQS0 = 0, DQS1 = 0
8459 20:12:25.668277 DQM Delay:
8460 20:12:25.671279 DQM0 = 135, DQM1 = 129
8461 20:12:25.671411 DQ Delay:
8462 20:12:25.674775 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8463 20:12:25.678300 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8464 20:12:25.684695 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =127
8465 20:12:25.687641 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8466 20:12:25.687857
8467 20:12:25.687991
8468 20:12:25.688113 ==
8469 20:12:25.691265 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 20:12:25.695012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 20:12:25.695236 ==
8472 20:12:25.695350
8473 20:12:25.695558
8474 20:12:25.697948 TX Vref Scan disable
8475 20:12:25.700881 == TX Byte 0 ==
8476 20:12:25.704214 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 20:12:25.707603 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 20:12:25.710953 == TX Byte 1 ==
8479 20:12:25.713993 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8480 20:12:25.717929 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8481 20:12:25.718013 ==
8482 20:12:25.720976 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 20:12:25.724442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 20:12:25.727672 ==
8485 20:12:25.740120
8486 20:12:25.743125 TX Vref early break, caculate TX vref
8487 20:12:25.746021 TX Vref=16, minBit 8, minWin=21, winSum=369
8488 20:12:25.749537 TX Vref=18, minBit 8, minWin=21, winSum=377
8489 20:12:25.752673 TX Vref=20, minBit 8, minWin=23, winSum=387
8490 20:12:25.755756 TX Vref=22, minBit 8, minWin=24, winSum=399
8491 20:12:25.759194 TX Vref=24, minBit 8, minWin=24, winSum=404
8492 20:12:25.765613 TX Vref=26, minBit 8, minWin=24, winSum=411
8493 20:12:25.768875 TX Vref=28, minBit 6, minWin=25, winSum=420
8494 20:12:25.772611 TX Vref=30, minBit 0, minWin=25, winSum=416
8495 20:12:25.775685 TX Vref=32, minBit 11, minWin=23, winSum=407
8496 20:12:25.779064 TX Vref=34, minBit 11, minWin=23, winSum=399
8497 20:12:25.785712 TX Vref=36, minBit 0, minWin=23, winSum=387
8498 20:12:25.788729 [TxChooseVref] Worse bit 6, Min win 25, Win sum 420, Final Vref 28
8499 20:12:25.788815
8500 20:12:25.791925 Final TX Range 0 Vref 28
8501 20:12:25.792010
8502 20:12:25.792076 ==
8503 20:12:25.795110 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 20:12:25.801761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 20:12:25.801846 ==
8506 20:12:25.801912
8507 20:12:25.801972
8508 20:12:25.802030 TX Vref Scan disable
8509 20:12:25.808858 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8510 20:12:25.808960 == TX Byte 0 ==
8511 20:12:25.812746 u2DelayCellOfst[0]=14 cells (4 PI)
8512 20:12:25.815488 u2DelayCellOfst[1]=7 cells (2 PI)
8513 20:12:25.818500 u2DelayCellOfst[2]=0 cells (0 PI)
8514 20:12:25.822284 u2DelayCellOfst[3]=3 cells (1 PI)
8515 20:12:25.825106 u2DelayCellOfst[4]=7 cells (2 PI)
8516 20:12:25.828511 u2DelayCellOfst[5]=14 cells (4 PI)
8517 20:12:25.831674 u2DelayCellOfst[6]=10 cells (3 PI)
8518 20:12:25.835016 u2DelayCellOfst[7]=3 cells (1 PI)
8519 20:12:25.838395 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8520 20:12:25.841856 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 20:12:25.844686 == TX Byte 1 ==
8522 20:12:25.848255 u2DelayCellOfst[8]=0 cells (0 PI)
8523 20:12:25.851646 u2DelayCellOfst[9]=3 cells (1 PI)
8524 20:12:25.854830 u2DelayCellOfst[10]=10 cells (3 PI)
8525 20:12:25.858030 u2DelayCellOfst[11]=3 cells (1 PI)
8526 20:12:25.861493 u2DelayCellOfst[12]=14 cells (4 PI)
8527 20:12:25.864546 u2DelayCellOfst[13]=14 cells (4 PI)
8528 20:12:25.867946 u2DelayCellOfst[14]=14 cells (4 PI)
8529 20:12:25.868027 u2DelayCellOfst[15]=17 cells (5 PI)
8530 20:12:25.874338 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8531 20:12:25.877726 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8532 20:12:25.880957 DramC Write-DBI on
8533 20:12:25.881043 ==
8534 20:12:25.885153 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 20:12:25.887857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 20:12:25.887939 ==
8537 20:12:25.888002
8538 20:12:25.888062
8539 20:12:25.891150 TX Vref Scan disable
8540 20:12:25.891232 == TX Byte 0 ==
8541 20:12:25.897609 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 20:12:25.897691 == TX Byte 1 ==
8543 20:12:25.901008 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8544 20:12:25.904093 DramC Write-DBI off
8545 20:12:25.904174
8546 20:12:25.904238 [DATLAT]
8547 20:12:25.907383 Freq=1600, CH1 RK0
8548 20:12:25.907478
8549 20:12:25.907542 DATLAT Default: 0xf
8550 20:12:25.910667 0, 0xFFFF, sum = 0
8551 20:12:25.914318 1, 0xFFFF, sum = 0
8552 20:12:25.914402 2, 0xFFFF, sum = 0
8553 20:12:25.917217 3, 0xFFFF, sum = 0
8554 20:12:25.917300 4, 0xFFFF, sum = 0
8555 20:12:25.920593 5, 0xFFFF, sum = 0
8556 20:12:25.920677 6, 0xFFFF, sum = 0
8557 20:12:25.924210 7, 0xFFFF, sum = 0
8558 20:12:25.924293 8, 0xFFFF, sum = 0
8559 20:12:25.926951 9, 0xFFFF, sum = 0
8560 20:12:25.927034 10, 0xFFFF, sum = 0
8561 20:12:25.930340 11, 0xFFFF, sum = 0
8562 20:12:25.930423 12, 0xFFFF, sum = 0
8563 20:12:25.934486 13, 0xFFFF, sum = 0
8564 20:12:25.934569 14, 0x0, sum = 1
8565 20:12:25.937064 15, 0x0, sum = 2
8566 20:12:25.937150 16, 0x0, sum = 3
8567 20:12:25.940025 17, 0x0, sum = 4
8568 20:12:25.940108 best_step = 15
8569 20:12:25.940173
8570 20:12:25.940233 ==
8571 20:12:25.943584 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 20:12:25.950031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 20:12:25.950114 ==
8574 20:12:25.950177 RX Vref Scan: 1
8575 20:12:25.950237
8576 20:12:25.953326 Set Vref Range= 24 -> 127
8577 20:12:25.953409
8578 20:12:25.956561 RX Vref 24 -> 127, step: 1
8579 20:12:25.956643
8580 20:12:25.959743 RX Delay 11 -> 252, step: 4
8581 20:12:25.959825
8582 20:12:25.962963 Set Vref, RX VrefLevel [Byte0]: 24
8583 20:12:25.966350 [Byte1]: 24
8584 20:12:25.966433
8585 20:12:25.969516 Set Vref, RX VrefLevel [Byte0]: 25
8586 20:12:25.973076 [Byte1]: 25
8587 20:12:25.973158
8588 20:12:25.976257 Set Vref, RX VrefLevel [Byte0]: 26
8589 20:12:25.979494 [Byte1]: 26
8590 20:12:25.983450
8591 20:12:25.983532 Set Vref, RX VrefLevel [Byte0]: 27
8592 20:12:25.986405 [Byte1]: 27
8593 20:12:25.990342
8594 20:12:25.990423 Set Vref, RX VrefLevel [Byte0]: 28
8595 20:12:25.994128 [Byte1]: 28
8596 20:12:25.998126
8597 20:12:25.998208 Set Vref, RX VrefLevel [Byte0]: 29
8598 20:12:26.001706 [Byte1]: 29
8599 20:12:26.005652
8600 20:12:26.005753 Set Vref, RX VrefLevel [Byte0]: 30
8601 20:12:26.008906 [Byte1]: 30
8602 20:12:26.013230
8603 20:12:26.013312 Set Vref, RX VrefLevel [Byte0]: 31
8604 20:12:26.016786 [Byte1]: 31
8605 20:12:26.021022
8606 20:12:26.021104 Set Vref, RX VrefLevel [Byte0]: 32
8607 20:12:26.024641 [Byte1]: 32
8608 20:12:26.028365
8609 20:12:26.028447 Set Vref, RX VrefLevel [Byte0]: 33
8610 20:12:26.032235 [Byte1]: 33
8611 20:12:26.036264
8612 20:12:26.036346 Set Vref, RX VrefLevel [Byte0]: 34
8613 20:12:26.039938 [Byte1]: 34
8614 20:12:26.044014
8615 20:12:26.044096 Set Vref, RX VrefLevel [Byte0]: 35
8616 20:12:26.046995 [Byte1]: 35
8617 20:12:26.051539
8618 20:12:26.051621 Set Vref, RX VrefLevel [Byte0]: 36
8619 20:12:26.054776 [Byte1]: 36
8620 20:12:26.059229
8621 20:12:26.059311 Set Vref, RX VrefLevel [Byte0]: 37
8622 20:12:26.062212 [Byte1]: 37
8623 20:12:26.066668
8624 20:12:26.066750 Set Vref, RX VrefLevel [Byte0]: 38
8625 20:12:26.070240 [Byte1]: 38
8626 20:12:26.074377
8627 20:12:26.074459 Set Vref, RX VrefLevel [Byte0]: 39
8628 20:12:26.077791 [Byte1]: 39
8629 20:12:26.081835
8630 20:12:26.081918 Set Vref, RX VrefLevel [Byte0]: 40
8631 20:12:26.085040 [Byte1]: 40
8632 20:12:26.089372
8633 20:12:26.089454 Set Vref, RX VrefLevel [Byte0]: 41
8634 20:12:26.093022 [Byte1]: 41
8635 20:12:26.097408
8636 20:12:26.097490 Set Vref, RX VrefLevel [Byte0]: 42
8637 20:12:26.100369 [Byte1]: 42
8638 20:12:26.105105
8639 20:12:26.105191 Set Vref, RX VrefLevel [Byte0]: 43
8640 20:12:26.108006 [Byte1]: 43
8641 20:12:26.112246
8642 20:12:26.112328 Set Vref, RX VrefLevel [Byte0]: 44
8643 20:12:26.115552 [Byte1]: 44
8644 20:12:26.119771
8645 20:12:26.119853 Set Vref, RX VrefLevel [Byte0]: 45
8646 20:12:26.123229 [Byte1]: 45
8647 20:12:26.127523
8648 20:12:26.127605 Set Vref, RX VrefLevel [Byte0]: 46
8649 20:12:26.130879 [Byte1]: 46
8650 20:12:26.135022
8651 20:12:26.135104 Set Vref, RX VrefLevel [Byte0]: 47
8652 20:12:26.139146 [Byte1]: 47
8653 20:12:26.142645
8654 20:12:26.142727 Set Vref, RX VrefLevel [Byte0]: 48
8655 20:12:26.146347 [Byte1]: 48
8656 20:12:26.150494
8657 20:12:26.150576 Set Vref, RX VrefLevel [Byte0]: 49
8658 20:12:26.153785 [Byte1]: 49
8659 20:12:26.158055
8660 20:12:26.158137 Set Vref, RX VrefLevel [Byte0]: 50
8661 20:12:26.161527 [Byte1]: 50
8662 20:12:26.165636
8663 20:12:26.165720 Set Vref, RX VrefLevel [Byte0]: 51
8664 20:12:26.168894 [Byte1]: 51
8665 20:12:26.173582
8666 20:12:26.173665 Set Vref, RX VrefLevel [Byte0]: 52
8667 20:12:26.176642 [Byte1]: 52
8668 20:12:26.181015
8669 20:12:26.181099 Set Vref, RX VrefLevel [Byte0]: 53
8670 20:12:26.184265 [Byte1]: 53
8671 20:12:26.188627
8672 20:12:26.188711 Set Vref, RX VrefLevel [Byte0]: 54
8673 20:12:26.192128 [Byte1]: 54
8674 20:12:26.195926
8675 20:12:26.196011 Set Vref, RX VrefLevel [Byte0]: 55
8676 20:12:26.199553 [Byte1]: 55
8677 20:12:26.203920
8678 20:12:26.204046 Set Vref, RX VrefLevel [Byte0]: 56
8679 20:12:26.207294 [Byte1]: 56
8680 20:12:26.211378
8681 20:12:26.211540 Set Vref, RX VrefLevel [Byte0]: 57
8682 20:12:26.214778 [Byte1]: 57
8683 20:12:26.219215
8684 20:12:26.219386 Set Vref, RX VrefLevel [Byte0]: 58
8685 20:12:26.222266 [Byte1]: 58
8686 20:12:26.226539
8687 20:12:26.226664 Set Vref, RX VrefLevel [Byte0]: 59
8688 20:12:26.229751 [Byte1]: 59
8689 20:12:26.234015
8690 20:12:26.234140 Set Vref, RX VrefLevel [Byte0]: 60
8691 20:12:26.237291 [Byte1]: 60
8692 20:12:26.241804
8693 20:12:26.241928 Set Vref, RX VrefLevel [Byte0]: 61
8694 20:12:26.245095 [Byte1]: 61
8695 20:12:26.249187
8696 20:12:26.249312 Set Vref, RX VrefLevel [Byte0]: 62
8697 20:12:26.252506 [Byte1]: 62
8698 20:12:26.257426
8699 20:12:26.257549 Set Vref, RX VrefLevel [Byte0]: 63
8700 20:12:26.260346 [Byte1]: 63
8701 20:12:26.264313
8702 20:12:26.264422 Set Vref, RX VrefLevel [Byte0]: 64
8703 20:12:26.268327 [Byte1]: 64
8704 20:12:26.272232
8705 20:12:26.272313 Set Vref, RX VrefLevel [Byte0]: 65
8706 20:12:26.275507 [Byte1]: 65
8707 20:12:26.279680
8708 20:12:26.279761 Set Vref, RX VrefLevel [Byte0]: 66
8709 20:12:26.283230 [Byte1]: 66
8710 20:12:26.287704
8711 20:12:26.287786 Set Vref, RX VrefLevel [Byte0]: 67
8712 20:12:26.290666 [Byte1]: 67
8713 20:12:26.294969
8714 20:12:26.295050 Set Vref, RX VrefLevel [Byte0]: 68
8715 20:12:26.298540 [Byte1]: 68
8716 20:12:26.302854
8717 20:12:26.302935 Set Vref, RX VrefLevel [Byte0]: 69
8718 20:12:26.305813 [Byte1]: 69
8719 20:12:26.310205
8720 20:12:26.310286 Set Vref, RX VrefLevel [Byte0]: 70
8721 20:12:26.313401 [Byte1]: 70
8722 20:12:26.317743
8723 20:12:26.317824 Set Vref, RX VrefLevel [Byte0]: 71
8724 20:12:26.321160 [Byte1]: 71
8725 20:12:26.325558
8726 20:12:26.325639 Final RX Vref Byte 0 = 56 to rank0
8727 20:12:26.329015 Final RX Vref Byte 1 = 61 to rank0
8728 20:12:26.332109 Final RX Vref Byte 0 = 56 to rank1
8729 20:12:26.335621 Final RX Vref Byte 1 = 61 to rank1==
8730 20:12:26.338946 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 20:12:26.345542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 20:12:26.345625 ==
8733 20:12:26.345690 DQS Delay:
8734 20:12:26.348378 DQS0 = 0, DQS1 = 0
8735 20:12:26.348459 DQM Delay:
8736 20:12:26.348523 DQM0 = 132, DQM1 = 128
8737 20:12:26.351925 DQ Delay:
8738 20:12:26.354962 DQ0 =140, DQ1 =130, DQ2 =116, DQ3 =130
8739 20:12:26.358240 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8740 20:12:26.361601 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8741 20:12:26.364856 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8742 20:12:26.364938
8743 20:12:26.365000
8744 20:12:26.365059
8745 20:12:26.368482 [DramC_TX_OE_Calibration] TA2
8746 20:12:26.371699 Original DQ_B0 (3 6) =30, OEN = 27
8747 20:12:26.374855 Original DQ_B1 (3 6) =30, OEN = 27
8748 20:12:26.378354 24, 0x0, End_B0=24 End_B1=24
8749 20:12:26.381697 25, 0x0, End_B0=25 End_B1=25
8750 20:12:26.381780 26, 0x0, End_B0=26 End_B1=26
8751 20:12:26.384640 27, 0x0, End_B0=27 End_B1=27
8752 20:12:26.387975 28, 0x0, End_B0=28 End_B1=28
8753 20:12:26.391418 29, 0x0, End_B0=29 End_B1=29
8754 20:12:26.391500 30, 0x0, End_B0=30 End_B1=30
8755 20:12:26.394465 31, 0x4141, End_B0=30 End_B1=30
8756 20:12:26.398368 Byte0 end_step=30 best_step=27
8757 20:12:26.401448 Byte1 end_step=30 best_step=27
8758 20:12:26.404493 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 20:12:26.407708 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 20:12:26.407793
8761 20:12:26.407857
8762 20:12:26.414461 [DQSOSCAuto] RK0, (LSB)MR18= 0xd16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8763 20:12:26.417923 CH1 RK0: MR19=303, MR18=D16
8764 20:12:26.424212 CH1_RK0: MR19=0x303, MR18=0xD16, DQSOSC=398, MR23=63, INC=23, DEC=15
8765 20:12:26.424300
8766 20:12:26.427520 ----->DramcWriteLeveling(PI) begin...
8767 20:12:26.427630 ==
8768 20:12:26.430732 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 20:12:26.434525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 20:12:26.434607 ==
8771 20:12:26.437398 Write leveling (Byte 0): 22 => 22
8772 20:12:26.440824 Write leveling (Byte 1): 25 => 25
8773 20:12:26.444108 DramcWriteLeveling(PI) end<-----
8774 20:12:26.444189
8775 20:12:26.444252 ==
8776 20:12:26.447638 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 20:12:26.450494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 20:12:26.454322 ==
8779 20:12:26.454404 [Gating] SW mode calibration
8780 20:12:26.463976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 20:12:26.467256 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 20:12:26.470492 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 20:12:26.476724 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 20:12:26.480343 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8785 20:12:26.483880 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8786 20:12:26.490282 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 20:12:26.493450 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 20:12:26.496831 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 20:12:26.503201 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 20:12:26.506763 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 20:12:26.510069 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8792 20:12:26.516823 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8793 20:12:26.519868 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
8794 20:12:26.523504 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 20:12:26.529328 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 20:12:26.533071 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 20:12:26.536269 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 20:12:26.542767 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 20:12:26.546440 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8800 20:12:26.549415 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8801 20:12:26.556060 1 6 12 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8802 20:12:26.559219 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 20:12:26.562816 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 20:12:26.568945 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 20:12:26.572615 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 20:12:26.575878 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 20:12:26.582011 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 20:12:26.585616 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8809 20:12:26.588958 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 20:12:26.595561 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8811 20:12:26.598537 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 20:12:26.601981 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 20:12:26.608872 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 20:12:26.612022 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 20:12:26.615764 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 20:12:26.622007 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 20:12:26.625361 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 20:12:26.628131 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 20:12:26.635087 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 20:12:26.638152 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 20:12:26.641689 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 20:12:26.648253 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 20:12:26.651626 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8824 20:12:26.654782 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8825 20:12:26.658574 Total UI for P1: 0, mck2ui 16
8826 20:12:26.661252 best dqsien dly found for B0: ( 1, 9, 4)
8827 20:12:26.668203 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8828 20:12:26.671500 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 20:12:26.674631 Total UI for P1: 0, mck2ui 16
8830 20:12:26.677988 best dqsien dly found for B1: ( 1, 9, 10)
8831 20:12:26.681105 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8832 20:12:26.684242 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8833 20:12:26.684327
8834 20:12:26.687804 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8835 20:12:26.694136 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8836 20:12:26.694218 [Gating] SW calibration Done
8837 20:12:26.694281 ==
8838 20:12:26.697717 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 20:12:26.704331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 20:12:26.704414 ==
8841 20:12:26.704477 RX Vref Scan: 0
8842 20:12:26.704537
8843 20:12:26.707341 RX Vref 0 -> 0, step: 1
8844 20:12:26.707446
8845 20:12:26.710502 RX Delay 0 -> 252, step: 8
8846 20:12:26.713779 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8847 20:12:26.717406 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8848 20:12:26.720667 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8849 20:12:26.727333 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8850 20:12:26.730230 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8851 20:12:26.733544 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8852 20:12:26.737052 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8853 20:12:26.740309 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8854 20:12:26.746743 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8855 20:12:26.749990 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8856 20:12:26.753289 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8857 20:12:26.756884 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8858 20:12:26.763469 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8859 20:12:26.766399 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8860 20:12:26.770246 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8861 20:12:26.773372 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8862 20:12:26.773453 ==
8863 20:12:26.776426 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 20:12:26.783579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 20:12:26.783661 ==
8866 20:12:26.783725 DQS Delay:
8867 20:12:26.786393 DQS0 = 0, DQS1 = 0
8868 20:12:26.786475 DQM Delay:
8869 20:12:26.786538 DQM0 = 133, DQM1 = 130
8870 20:12:26.789747 DQ Delay:
8871 20:12:26.792936 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8872 20:12:26.796236 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =135
8873 20:12:26.799612 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8874 20:12:26.802405 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8875 20:12:26.802492
8876 20:12:26.802555
8877 20:12:26.802614 ==
8878 20:12:26.806400 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 20:12:26.812836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 20:12:26.812919 ==
8881 20:12:26.812982
8882 20:12:26.813041
8883 20:12:26.813098 TX Vref Scan disable
8884 20:12:26.815975 == TX Byte 0 ==
8885 20:12:26.818938 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8886 20:12:26.822488 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8887 20:12:26.825907 == TX Byte 1 ==
8888 20:12:26.829254 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8889 20:12:26.835664 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8890 20:12:26.835746 ==
8891 20:12:26.838951 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 20:12:26.842154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 20:12:26.842235 ==
8894 20:12:26.855741
8895 20:12:26.859502 TX Vref early break, caculate TX vref
8896 20:12:26.862526 TX Vref=16, minBit 9, minWin=21, winSum=377
8897 20:12:26.866078 TX Vref=18, minBit 9, minWin=22, winSum=385
8898 20:12:26.868982 TX Vref=20, minBit 9, minWin=22, winSum=396
8899 20:12:26.872354 TX Vref=22, minBit 9, minWin=23, winSum=403
8900 20:12:26.875948 TX Vref=24, minBit 9, minWin=24, winSum=410
8901 20:12:26.881978 TX Vref=26, minBit 9, minWin=23, winSum=415
8902 20:12:26.885542 TX Vref=28, minBit 9, minWin=23, winSum=418
8903 20:12:26.888950 TX Vref=30, minBit 9, minWin=25, winSum=419
8904 20:12:26.892457 TX Vref=32, minBit 8, minWin=24, winSum=406
8905 20:12:26.895863 TX Vref=34, minBit 0, minWin=24, winSum=400
8906 20:12:26.899691 TX Vref=36, minBit 9, minWin=23, winSum=395
8907 20:12:26.905460 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 30
8908 20:12:26.905542
8909 20:12:26.908451 Final TX Range 0 Vref 30
8910 20:12:26.908533
8911 20:12:26.908597 ==
8912 20:12:26.911788 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 20:12:26.915176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 20:12:26.915284 ==
8915 20:12:26.918358
8916 20:12:26.918439
8917 20:12:26.918502 TX Vref Scan disable
8918 20:12:26.925021 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8919 20:12:26.925103 == TX Byte 0 ==
8920 20:12:26.928273 u2DelayCellOfst[0]=14 cells (4 PI)
8921 20:12:26.931874 u2DelayCellOfst[1]=10 cells (3 PI)
8922 20:12:26.935382 u2DelayCellOfst[2]=0 cells (0 PI)
8923 20:12:26.938002 u2DelayCellOfst[3]=7 cells (2 PI)
8924 20:12:26.941715 u2DelayCellOfst[4]=10 cells (3 PI)
8925 20:12:26.944818 u2DelayCellOfst[5]=14 cells (4 PI)
8926 20:12:26.948493 u2DelayCellOfst[6]=14 cells (4 PI)
8927 20:12:26.951861 u2DelayCellOfst[7]=7 cells (2 PI)
8928 20:12:26.954914 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8929 20:12:26.958494 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8930 20:12:26.961585 == TX Byte 1 ==
8931 20:12:26.964631 u2DelayCellOfst[8]=0 cells (0 PI)
8932 20:12:26.967948 u2DelayCellOfst[9]=3 cells (1 PI)
8933 20:12:26.971034 u2DelayCellOfst[10]=10 cells (3 PI)
8934 20:12:26.974767 u2DelayCellOfst[11]=3 cells (1 PI)
8935 20:12:26.977696 u2DelayCellOfst[12]=10 cells (3 PI)
8936 20:12:26.981157 u2DelayCellOfst[13]=14 cells (4 PI)
8937 20:12:26.984341 u2DelayCellOfst[14]=17 cells (5 PI)
8938 20:12:26.984448 u2DelayCellOfst[15]=17 cells (5 PI)
8939 20:12:26.991240 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8940 20:12:26.994154 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8941 20:12:26.997276 DramC Write-DBI on
8942 20:12:26.997358 ==
8943 20:12:27.000769 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 20:12:27.003997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 20:12:27.004079 ==
8946 20:12:27.004143
8947 20:12:27.004201
8948 20:12:27.007631 TX Vref Scan disable
8949 20:12:27.007713 == TX Byte 0 ==
8950 20:12:27.014264 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8951 20:12:27.014348 == TX Byte 1 ==
8952 20:12:27.017624 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8953 20:12:27.020967 DramC Write-DBI off
8954 20:12:27.021048
8955 20:12:27.021111 [DATLAT]
8956 20:12:27.024307 Freq=1600, CH1 RK1
8957 20:12:27.024399
8958 20:12:27.024463 DATLAT Default: 0xf
8959 20:12:27.027154 0, 0xFFFF, sum = 0
8960 20:12:27.027236 1, 0xFFFF, sum = 0
8961 20:12:27.030410 2, 0xFFFF, sum = 0
8962 20:12:27.034061 3, 0xFFFF, sum = 0
8963 20:12:27.034144 4, 0xFFFF, sum = 0
8964 20:12:27.037371 5, 0xFFFF, sum = 0
8965 20:12:27.037454 6, 0xFFFF, sum = 0
8966 20:12:27.040394 7, 0xFFFF, sum = 0
8967 20:12:27.040486 8, 0xFFFF, sum = 0
8968 20:12:27.043835 9, 0xFFFF, sum = 0
8969 20:12:27.043918 10, 0xFFFF, sum = 0
8970 20:12:27.046884 11, 0xFFFF, sum = 0
8971 20:12:27.046983 12, 0xFFFF, sum = 0
8972 20:12:27.050115 13, 0xFFFF, sum = 0
8973 20:12:27.050197 14, 0x0, sum = 1
8974 20:12:27.053633 15, 0x0, sum = 2
8975 20:12:27.053716 16, 0x0, sum = 3
8976 20:12:27.057086 17, 0x0, sum = 4
8977 20:12:27.057186 best_step = 15
8978 20:12:27.057251
8979 20:12:27.057310 ==
8980 20:12:27.060294 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 20:12:27.066769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 20:12:27.066896 ==
8983 20:12:27.067008 RX Vref Scan: 0
8984 20:12:27.067117
8985 20:12:27.069855 RX Vref 0 -> 0, step: 1
8986 20:12:27.069976
8987 20:12:27.073650 RX Delay 11 -> 252, step: 4
8988 20:12:27.076653 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8989 20:12:27.079832 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8990 20:12:27.086626 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8991 20:12:27.089890 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8992 20:12:27.093164 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8993 20:12:27.096269 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8994 20:12:27.099471 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8995 20:12:27.106612 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8996 20:12:27.109657 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8997 20:12:27.112686 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8998 20:12:27.115985 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8999 20:12:27.119238 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9000 20:12:27.126433 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9001 20:12:27.129120 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9002 20:12:27.132753 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9003 20:12:27.135687 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9004 20:12:27.135810 ==
9005 20:12:27.138899 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 20:12:27.145682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 20:12:27.145808 ==
9008 20:12:27.145923 DQS Delay:
9009 20:12:27.148716 DQS0 = 0, DQS1 = 0
9010 20:12:27.148837 DQM Delay:
9011 20:12:27.152222 DQM0 = 131, DQM1 = 128
9012 20:12:27.152346 DQ Delay:
9013 20:12:27.155628 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
9014 20:12:27.158764 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9015 20:12:27.162099 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9016 20:12:27.165224 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =140
9017 20:12:27.165337
9018 20:12:27.165404
9019 20:12:27.165502
9020 20:12:27.168609 [DramC_TX_OE_Calibration] TA2
9021 20:12:27.172024 Original DQ_B0 (3 6) =30, OEN = 27
9022 20:12:27.175145 Original DQ_B1 (3 6) =30, OEN = 27
9023 20:12:27.178320 24, 0x0, End_B0=24 End_B1=24
9024 20:12:27.181672 25, 0x0, End_B0=25 End_B1=25
9025 20:12:27.181799 26, 0x0, End_B0=26 End_B1=26
9026 20:12:27.185100 27, 0x0, End_B0=27 End_B1=27
9027 20:12:27.188044 28, 0x0, End_B0=28 End_B1=28
9028 20:12:27.191270 29, 0x0, End_B0=29 End_B1=29
9029 20:12:27.194733 30, 0x0, End_B0=30 End_B1=30
9030 20:12:27.194859 31, 0x4141, End_B0=30 End_B1=30
9031 20:12:27.198420 Byte0 end_step=30 best_step=27
9032 20:12:27.201260 Byte1 end_step=30 best_step=27
9033 20:12:27.205006 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 20:12:27.208032 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 20:12:27.208156
9036 20:12:27.208269
9037 20:12:27.214768 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9038 20:12:27.217831 CH1 RK1: MR19=303, MR18=F1D
9039 20:12:27.224344 CH1_RK1: MR19=0x303, MR18=0xF1D, DQSOSC=395, MR23=63, INC=23, DEC=15
9040 20:12:27.228340 [RxdqsGatingPostProcess] freq 1600
9041 20:12:27.235119 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 20:12:27.235246 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 20:12:27.237870 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 20:12:27.241082 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 20:12:27.244281 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 20:12:27.247612 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 20:12:27.251046 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 20:12:27.254505 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 20:12:27.257254 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 20:12:27.260812 Pre-setting of DQS Precalculation
9051 20:12:27.264369 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 20:12:27.274048 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 20:12:27.280438 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 20:12:27.280521
9055 20:12:27.280584
9056 20:12:27.284160 [Calibration Summary] 3200 Mbps
9057 20:12:27.284269 CH 0, Rank 0
9058 20:12:27.286949 SW Impedance : PASS
9059 20:12:27.287099 DUTY Scan : NO K
9060 20:12:27.290262 ZQ Calibration : PASS
9061 20:12:27.293771 Jitter Meter : NO K
9062 20:12:27.293895 CBT Training : PASS
9063 20:12:27.296778 Write leveling : PASS
9064 20:12:27.300443 RX DQS gating : PASS
9065 20:12:27.300568 RX DQ/DQS(RDDQC) : PASS
9066 20:12:27.303522 TX DQ/DQS : PASS
9067 20:12:27.306867 RX DATLAT : PASS
9068 20:12:27.306969 RX DQ/DQS(Engine): PASS
9069 20:12:27.310297 TX OE : PASS
9070 20:12:27.310408 All Pass.
9071 20:12:27.310524
9072 20:12:27.313544 CH 0, Rank 1
9073 20:12:27.313626 SW Impedance : PASS
9074 20:12:27.317302 DUTY Scan : NO K
9075 20:12:27.320243 ZQ Calibration : PASS
9076 20:12:27.320325 Jitter Meter : NO K
9077 20:12:27.323182 CBT Training : PASS
9078 20:12:27.326735 Write leveling : PASS
9079 20:12:27.326864 RX DQS gating : PASS
9080 20:12:27.329821 RX DQ/DQS(RDDQC) : PASS
9081 20:12:27.333008 TX DQ/DQS : PASS
9082 20:12:27.333113 RX DATLAT : PASS
9083 20:12:27.337004 RX DQ/DQS(Engine): PASS
9084 20:12:27.339883 TX OE : PASS
9085 20:12:27.339966 All Pass.
9086 20:12:27.340054
9087 20:12:27.340144 CH 1, Rank 0
9088 20:12:27.343155 SW Impedance : PASS
9089 20:12:27.346678 DUTY Scan : NO K
9090 20:12:27.346760 ZQ Calibration : PASS
9091 20:12:27.349749 Jitter Meter : NO K
9092 20:12:27.352938 CBT Training : PASS
9093 20:12:27.353020 Write leveling : PASS
9094 20:12:27.356282 RX DQS gating : PASS
9095 20:12:27.359602 RX DQ/DQS(RDDQC) : PASS
9096 20:12:27.359685 TX DQ/DQS : PASS
9097 20:12:27.362929 RX DATLAT : PASS
9098 20:12:27.365922 RX DQ/DQS(Engine): PASS
9099 20:12:27.366046 TX OE : PASS
9100 20:12:27.366161 All Pass.
9101 20:12:27.369128
9102 20:12:27.369251 CH 1, Rank 1
9103 20:12:27.372634 SW Impedance : PASS
9104 20:12:27.372757 DUTY Scan : NO K
9105 20:12:27.375792 ZQ Calibration : PASS
9106 20:12:27.379331 Jitter Meter : NO K
9107 20:12:27.379489 CBT Training : PASS
9108 20:12:27.382291 Write leveling : PASS
9109 20:12:27.382410 RX DQS gating : PASS
9110 20:12:27.385967 RX DQ/DQS(RDDQC) : PASS
9111 20:12:27.389206 TX DQ/DQS : PASS
9112 20:12:27.389328 RX DATLAT : PASS
9113 20:12:27.392230 RX DQ/DQS(Engine): PASS
9114 20:12:27.395779 TX OE : PASS
9115 20:12:27.395900 All Pass.
9116 20:12:27.396014
9117 20:12:27.399830 DramC Write-DBI on
9118 20:12:27.399953 PER_BANK_REFRESH: Hybrid Mode
9119 20:12:27.402450 TX_TRACKING: ON
9120 20:12:27.412829 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 20:12:27.418497 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 20:12:27.425369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 20:12:27.428498 [FAST_K] Save calibration result to emmc
9124 20:12:27.431712 sync common calibartion params.
9125 20:12:27.435324 sync cbt_mode0:1, 1:1
9126 20:12:27.438592 dram_init: ddr_geometry: 2
9127 20:12:27.438710 dram_init: ddr_geometry: 2
9128 20:12:27.441637 dram_init: ddr_geometry: 2
9129 20:12:27.444975 0:dram_rank_size:100000000
9130 20:12:27.445100 1:dram_rank_size:100000000
9131 20:12:27.451916 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 20:12:27.455337 DFS_SHUFFLE_HW_MODE: ON
9133 20:12:27.458302 dramc_set_vcore_voltage set vcore to 725000
9134 20:12:27.461669 Read voltage for 1600, 0
9135 20:12:27.461792 Vio18 = 0
9136 20:12:27.461905 Vcore = 725000
9137 20:12:27.464722 Vdram = 0
9138 20:12:27.464844 Vddq = 0
9139 20:12:27.464956 Vmddr = 0
9140 20:12:27.468416 switch to 3200 Mbps bootup
9141 20:12:27.471164 [DramcRunTimeConfig]
9142 20:12:27.471287 PHYPLL
9143 20:12:27.471442 DPM_CONTROL_AFTERK: ON
9144 20:12:27.474756 PER_BANK_REFRESH: ON
9145 20:12:27.477705 REFRESH_OVERHEAD_REDUCTION: ON
9146 20:12:27.477827 CMD_PICG_NEW_MODE: OFF
9147 20:12:27.481400 XRTWTW_NEW_MODE: ON
9148 20:12:27.481522 XRTRTR_NEW_MODE: ON
9149 20:12:27.484650 TX_TRACKING: ON
9150 20:12:27.484773 RDSEL_TRACKING: OFF
9151 20:12:27.487834 DQS Precalculation for DVFS: ON
9152 20:12:27.491554 RX_TRACKING: OFF
9153 20:12:27.491677 HW_GATING DBG: ON
9154 20:12:27.494650 ZQCS_ENABLE_LP4: ON
9155 20:12:27.494773 RX_PICG_NEW_MODE: ON
9156 20:12:27.497557 TX_PICG_NEW_MODE: ON
9157 20:12:27.500806 ENABLE_RX_DCM_DPHY: ON
9158 20:12:27.504358 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 20:12:27.504481 DUMMY_READ_FOR_TRACKING: OFF
9160 20:12:27.508248 !!! SPM_CONTROL_AFTERK: OFF
9161 20:12:27.511030 !!! SPM could not control APHY
9162 20:12:27.514244 IMPEDANCE_TRACKING: ON
9163 20:12:27.514366 TEMP_SENSOR: ON
9164 20:12:27.517406 HW_SAVE_FOR_SR: OFF
9165 20:12:27.517529 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 20:12:27.523946 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 20:12:27.524070 Read ODT Tracking: ON
9168 20:12:27.527699 Refresh Rate DeBounce: ON
9169 20:12:27.530669 DFS_NO_QUEUE_FLUSH: ON
9170 20:12:27.530790 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 20:12:27.534041 ENABLE_DFS_RUNTIME_MRW: OFF
9172 20:12:27.537239 DDR_RESERVE_NEW_MODE: ON
9173 20:12:27.540657 MR_CBT_SWITCH_FREQ: ON
9174 20:12:27.540778 =========================
9175 20:12:27.560157 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 20:12:27.563746 dram_init: ddr_geometry: 2
9177 20:12:27.581974 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 20:12:27.585198 dram_init: dram init end (result: 0)
9179 20:12:27.591618 DRAM-K: Full calibration passed in 24410 msecs
9180 20:12:27.595451 MRC: failed to locate region type 0.
9181 20:12:27.595576 DRAM rank0 size:0x100000000,
9182 20:12:27.598557 DRAM rank1 size=0x100000000
9183 20:12:27.608566 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 20:12:27.614662 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 20:12:27.621204 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 20:12:27.631833 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 20:12:27.631959 DRAM rank0 size:0x100000000,
9188 20:12:27.634705 DRAM rank1 size=0x100000000
9189 20:12:27.634828 CBMEM:
9190 20:12:27.637962 IMD: root @ 0xfffff000 254 entries.
9191 20:12:27.641016 IMD: root @ 0xffffec00 62 entries.
9192 20:12:27.644615 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 20:12:27.651033 WARNING: RO_VPD is uninitialized or empty.
9194 20:12:27.654302 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 20:12:27.662055 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 20:12:27.674540 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9197 20:12:27.686115 BS: romstage times (exec / console): total (unknown) / 23942 ms
9198 20:12:27.686238
9199 20:12:27.686346
9200 20:12:27.695898 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 20:12:27.699312 ARM64: Exception handlers installed.
9202 20:12:27.702416 ARM64: Testing exception
9203 20:12:27.705907 ARM64: Done test exception
9204 20:12:27.706031 Enumerating buses...
9205 20:12:27.709163 Show all devs... Before device enumeration.
9206 20:12:27.712581 Root Device: enabled 1
9207 20:12:27.715745 CPU_CLUSTER: 0: enabled 1
9208 20:12:27.715864 CPU: 00: enabled 1
9209 20:12:27.718855 Compare with tree...
9210 20:12:27.718978 Root Device: enabled 1
9211 20:12:27.722436 CPU_CLUSTER: 0: enabled 1
9212 20:12:27.725671 CPU: 00: enabled 1
9213 20:12:27.725787 Root Device scanning...
9214 20:12:27.728897 scan_static_bus for Root Device
9215 20:12:27.732173 CPU_CLUSTER: 0 enabled
9216 20:12:27.735974 scan_static_bus for Root Device done
9217 20:12:27.738623 scan_bus: bus Root Device finished in 8 msecs
9218 20:12:27.738746 done
9219 20:12:27.745255 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 20:12:27.748874 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 20:12:27.755534 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 20:12:27.761687 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 20:12:27.761812 Allocating resources...
9224 20:12:27.764839 Reading resources...
9225 20:12:27.768294 Root Device read_resources bus 0 link: 0
9226 20:12:27.771538 DRAM rank0 size:0x100000000,
9227 20:12:27.771662 DRAM rank1 size=0x100000000
9228 20:12:27.778143 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 20:12:27.778298 CPU: 00 missing read_resources
9230 20:12:27.784776 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 20:12:27.788216 Root Device read_resources bus 0 link: 0 done
9232 20:12:27.791535 Done reading resources.
9233 20:12:27.794609 Show resources in subtree (Root Device)...After reading.
9234 20:12:27.797740 Root Device child on link 0 CPU_CLUSTER: 0
9235 20:12:27.801474 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 20:12:27.811010 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 20:12:27.811137 CPU: 00
9238 20:12:27.817602 Root Device assign_resources, bus 0 link: 0
9239 20:12:27.821021 CPU_CLUSTER: 0 missing set_resources
9240 20:12:27.824562 Root Device assign_resources, bus 0 link: 0 done
9241 20:12:27.827268 Done setting resources.
9242 20:12:27.830803 Show resources in subtree (Root Device)...After assigning values.
9243 20:12:27.834479 Root Device child on link 0 CPU_CLUSTER: 0
9244 20:12:27.840790 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 20:12:27.847568 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 20:12:27.851372 CPU: 00
9247 20:12:27.851528 Done allocating resources.
9248 20:12:27.856912 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 20:12:27.857035 Enabling resources...
9250 20:12:27.860589 done.
9251 20:12:27.863816 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 20:12:27.866875 Initializing devices...
9253 20:12:27.866999 Root Device init
9254 20:12:27.870275 init hardware done!
9255 20:12:27.870400 0x00000018: ctrlr->caps
9256 20:12:27.873849 52.000 MHz: ctrlr->f_max
9257 20:12:27.876759 0.400 MHz: ctrlr->f_min
9258 20:12:27.880070 0x40ff8080: ctrlr->voltages
9259 20:12:27.880193 sclk: 390625
9260 20:12:27.880308 Bus Width = 1
9261 20:12:27.883641 sclk: 390625
9262 20:12:27.883762 Bus Width = 1
9263 20:12:27.886741 Early init status = 3
9264 20:12:27.889943 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 20:12:27.893672 in-header: 03 fc 00 00 01 00 00 00
9266 20:12:27.896810 in-data: 00
9267 20:12:27.900275 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 20:12:27.904729 in-header: 03 fd 00 00 00 00 00 00
9269 20:12:27.908550 in-data:
9270 20:12:27.911646 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 20:12:27.914946 in-header: 03 fc 00 00 01 00 00 00
9272 20:12:27.918348 in-data: 00
9273 20:12:27.921322 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 20:12:27.926095 in-header: 03 fd 00 00 00 00 00 00
9275 20:12:27.929535 in-data:
9276 20:12:27.932713 [SSUSB] Setting up USB HOST controller...
9277 20:12:27.935855 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 20:12:27.939548 [SSUSB] phy power-on done.
9279 20:12:27.942677 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 20:12:27.948921 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 20:12:27.952993 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 20:12:27.959015 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 20:12:27.965312 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9284 20:12:27.972402 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 20:12:27.978740 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 20:12:27.985166 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9287 20:12:27.988914 SPM: binary array size = 0x9dc
9288 20:12:27.991965 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 20:12:27.998580 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 20:12:28.005270 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 20:12:28.011315 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 20:12:28.014783 configure_display: Starting display init
9293 20:12:28.049179 anx7625_power_on_init: Init interface.
9294 20:12:28.052806 anx7625_disable_pd_protocol: Disabled PD feature.
9295 20:12:28.057430 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 20:12:28.084029 anx7625_start_dp_work: Secure OCM version=00
9297 20:12:28.087211 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 20:12:28.101849 sp_tx_get_edid_block: EDID Block = 1
9299 20:12:28.204707 Extracted contents:
9300 20:12:28.207542 header: 00 ff ff ff ff ff ff 00
9301 20:12:28.211178 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 20:12:28.214069 version: 01 04
9303 20:12:28.217616 basic params: 95 1f 11 78 0a
9304 20:12:28.220955 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 20:12:28.224149 established: 00 00 00
9306 20:12:28.230710 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 20:12:28.233840 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 20:12:28.240591 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 20:12:28.247065 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 20:12:28.253490 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 20:12:28.257049 extensions: 00
9312 20:12:28.257172 checksum: fb
9313 20:12:28.257286
9314 20:12:28.260605 Manufacturer: IVO Model 57d Serial Number 0
9315 20:12:28.263599 Made week 0 of 2020
9316 20:12:28.267028 EDID version: 1.4
9317 20:12:28.267152 Digital display
9318 20:12:28.270465 6 bits per primary color channel
9319 20:12:28.270591 DisplayPort interface
9320 20:12:28.273341 Maximum image size: 31 cm x 17 cm
9321 20:12:28.276501 Gamma: 220%
9322 20:12:28.276623 Check DPMS levels
9323 20:12:28.283206 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 20:12:28.286608 First detailed timing is preferred timing
9325 20:12:28.290008 Established timings supported:
9326 20:12:28.290131 Standard timings supported:
9327 20:12:28.293192 Detailed timings
9328 20:12:28.296533 Hex of detail: 383680a07038204018303c0035ae10000019
9329 20:12:28.303116 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 20:12:28.306405 0780 0798 07c8 0820 hborder 0
9331 20:12:28.309412 0438 043b 0447 0458 vborder 0
9332 20:12:28.312806 -hsync -vsync
9333 20:12:28.312930 Did detailed timing
9334 20:12:28.319693 Hex of detail: 000000000000000000000000000000000000
9335 20:12:28.322738 Manufacturer-specified data, tag 0
9336 20:12:28.326570 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 20:12:28.329626 ASCII string: InfoVision
9338 20:12:28.332811 Hex of detail: 000000fe00523134304e574635205248200a
9339 20:12:28.335809 ASCII string: R140NWF5 RH
9340 20:12:28.335933 Checksum
9341 20:12:28.339845 Checksum: 0xfb (valid)
9342 20:12:28.342878 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 20:12:28.346157 DSI data_rate: 832800000 bps
9344 20:12:28.352964 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 20:12:28.356190 anx7625_parse_edid: pixelclock(138800).
9346 20:12:28.359153 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 20:12:28.362574 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 20:12:28.365695 anx7625_dsi_config: config dsi.
9349 20:12:28.372960 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 20:12:28.386060 anx7625_dsi_config: success to config DSI
9351 20:12:28.389824 anx7625_dp_start: MIPI phy setup OK.
9352 20:12:28.392787 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 20:12:28.396005 mtk_ddp_mode_set invalid vrefresh 60
9354 20:12:28.399456 main_disp_path_setup
9355 20:12:28.399538 ovl_layer_smi_id_en
9356 20:12:28.402629 ovl_layer_smi_id_en
9357 20:12:28.402737 ccorr_config
9358 20:12:28.402846 aal_config
9359 20:12:28.406341 gamma_config
9360 20:12:28.406423 postmask_config
9361 20:12:28.409431 dither_config
9362 20:12:28.412734 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 20:12:28.419096 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 20:12:28.422643 Root Device init finished in 551 msecs
9365 20:12:28.426442 CPU_CLUSTER: 0 init
9366 20:12:28.432580 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 20:12:28.438868 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 20:12:28.438968 APU_MBOX 0x190000b0 = 0x10001
9369 20:12:28.442592 APU_MBOX 0x190001b0 = 0x10001
9370 20:12:28.446171 APU_MBOX 0x190005b0 = 0x10001
9371 20:12:28.448819 APU_MBOX 0x190006b0 = 0x10001
9372 20:12:28.455152 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 20:12:28.465356 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9374 20:12:28.477758 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 20:12:28.484162 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 20:12:28.495926 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9377 20:12:28.505102 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 20:12:28.508375 CPU_CLUSTER: 0 init finished in 81 msecs
9379 20:12:28.511511 Devices initialized
9380 20:12:28.515044 Show all devs... After init.
9381 20:12:28.515165 Root Device: enabled 1
9382 20:12:28.518478 CPU_CLUSTER: 0: enabled 1
9383 20:12:28.521408 CPU: 00: enabled 1
9384 20:12:28.524673 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9385 20:12:28.527966 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 20:12:28.531166 ELOG: NV offset 0x57f000 size 0x1000
9387 20:12:28.538251 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9388 20:12:28.545014 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 20:12:28.548462 ELOG: Event(17) added with size 13 at 2024-03-03 20:12:28 UTC
9390 20:12:28.551406 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 20:12:28.555775 in-header: 03 3e 00 00 2c 00 00 00
9392 20:12:28.569207 in-data: 21 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 20:12:28.575069 ELOG: Event(A1) added with size 10 at 2024-03-03 20:12:28 UTC
9394 20:12:28.581958 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9395 20:12:28.588375 ELOG: Event(A0) added with size 9 at 2024-03-03 20:12:28 UTC
9396 20:12:28.591789 elog_add_boot_reason: Logged dev mode boot
9397 20:12:28.595094 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9398 20:12:28.598312 Finalize devices...
9399 20:12:28.598395 Devices finalized
9400 20:12:28.605367 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 20:12:28.608144 Writing coreboot table at 0xffe64000
9402 20:12:28.611647 0. 000000000010a000-0000000000113fff: RAMSTAGE
9403 20:12:28.614926 1. 0000000040000000-00000000400fffff: RAM
9404 20:12:28.621702 2. 0000000040100000-000000004032afff: RAMSTAGE
9405 20:12:28.624895 3. 000000004032b000-00000000545fffff: RAM
9406 20:12:28.628628 4. 0000000054600000-000000005465ffff: BL31
9407 20:12:28.631341 5. 0000000054660000-00000000ffe63fff: RAM
9408 20:12:28.637718 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9409 20:12:28.641165 7. 0000000100000000-000000023fffffff: RAM
9410 20:12:28.644780 Passing 5 GPIOs to payload:
9411 20:12:28.647741 NAME | PORT | POLARITY | VALUE
9412 20:12:28.650814 EC in RW | 0x000000aa | low | undefined
9413 20:12:28.657711 EC interrupt | 0x00000005 | low | undefined
9414 20:12:28.660853 TPM interrupt | 0x000000ab | high | undefined
9415 20:12:28.667561 SD card detect | 0x00000011 | high | undefined
9416 20:12:28.670824 speaker enable | 0x00000093 | high | undefined
9417 20:12:28.673983 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9418 20:12:28.677106 in-header: 03 f9 00 00 02 00 00 00
9419 20:12:28.681112 in-data: 02 00
9420 20:12:28.683903 ADC[4]: Raw value=903694 ID=7
9421 20:12:28.683985 ADC[3]: Raw value=213546 ID=1
9422 20:12:28.687568 RAM Code: 0x71
9423 20:12:28.690715 ADC[6]: Raw value=74630 ID=0
9424 20:12:28.690797 ADC[5]: Raw value=214285 ID=1
9425 20:12:28.693903 SKU Code: 0x1
9426 20:12:28.700206 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 74a3
9427 20:12:28.700288 coreboot table: 964 bytes.
9428 20:12:28.704010 IMD ROOT 0. 0xfffff000 0x00001000
9429 20:12:28.707098 IMD SMALL 1. 0xffffe000 0x00001000
9430 20:12:28.710839 RO MCACHE 2. 0xffffc000 0x00001104
9431 20:12:28.713681 CONSOLE 3. 0xfff7c000 0x00080000
9432 20:12:28.717089 FMAP 4. 0xfff7b000 0x00000452
9433 20:12:28.719948 TIME STAMP 5. 0xfff7a000 0x00000910
9434 20:12:28.723338 VBOOT WORK 6. 0xfff66000 0x00014000
9435 20:12:28.727107 RAMOOPS 7. 0xffe66000 0x00100000
9436 20:12:28.729962 COREBOOT 8. 0xffe64000 0x00002000
9437 20:12:28.733611 IMD small region:
9438 20:12:28.736991 IMD ROOT 0. 0xffffec00 0x00000400
9439 20:12:28.739949 VPD 1. 0xffffeb80 0x0000006c
9440 20:12:28.743000 MMC STATUS 2. 0xffffeb60 0x00000004
9441 20:12:28.746227 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9442 20:12:28.749895 Probing TPM: done!
9443 20:12:28.753277 Connected to device vid:did:rid of 1ae0:0028:00
9444 20:12:28.764405 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9445 20:12:28.767336 Initialized TPM device CR50 revision 0
9446 20:12:28.771181 Checking cr50 for pending updates
9447 20:12:28.774927 Reading cr50 TPM mode
9448 20:12:28.783371 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9449 20:12:28.790239 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9450 20:12:28.830680 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9451 20:12:28.833785 Checking segment from ROM address 0x40100000
9452 20:12:28.837020 Checking segment from ROM address 0x4010001c
9453 20:12:28.843890 Loading segment from ROM address 0x40100000
9454 20:12:28.844014 code (compression=0)
9455 20:12:28.853899 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9456 20:12:28.860281 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9457 20:12:28.860404 it's not compressed!
9458 20:12:28.866900 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9459 20:12:28.873314 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9460 20:12:28.890703 Loading segment from ROM address 0x4010001c
9461 20:12:28.890831 Entry Point 0x80000000
9462 20:12:28.894006 Loaded segments
9463 20:12:28.897490 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9464 20:12:28.903858 Jumping to boot code at 0x80000000(0xffe64000)
9465 20:12:28.910754 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9466 20:12:28.917096 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9467 20:12:28.925262 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9468 20:12:28.928352 Checking segment from ROM address 0x40100000
9469 20:12:28.931640 Checking segment from ROM address 0x4010001c
9470 20:12:28.938302 Loading segment from ROM address 0x40100000
9471 20:12:28.938429 code (compression=1)
9472 20:12:28.945303 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9473 20:12:28.954954 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9474 20:12:28.955079 using LZMA
9475 20:12:28.963463 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9476 20:12:28.969858 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9477 20:12:28.973721 Loading segment from ROM address 0x4010001c
9478 20:12:28.973845 Entry Point 0x54601000
9479 20:12:28.976879 Loaded segments
9480 20:12:28.979899 NOTICE: MT8192 bl31_setup
9481 20:12:28.987213 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9482 20:12:28.990388 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9483 20:12:28.993978 WARNING: region 0:
9484 20:12:28.997369 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 20:12:28.997494 WARNING: region 1:
9486 20:12:29.003763 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9487 20:12:29.007318 WARNING: region 2:
9488 20:12:29.010501 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9489 20:12:29.013566 WARNING: region 3:
9490 20:12:29.016796 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 20:12:29.020332 WARNING: region 4:
9492 20:12:29.027199 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 20:12:29.027323 WARNING: region 5:
9494 20:12:29.029984 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 20:12:29.033727 WARNING: region 6:
9496 20:12:29.036553 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 20:12:29.039984 WARNING: region 7:
9498 20:12:29.043461 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 20:12:29.050122 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9500 20:12:29.053445 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9501 20:12:29.056721 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9502 20:12:29.063134 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9503 20:12:29.066782 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9504 20:12:29.070222 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9505 20:12:29.076519 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9506 20:12:29.079919 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9507 20:12:29.086809 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9508 20:12:29.090003 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9509 20:12:29.093106 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9510 20:12:29.099604 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9511 20:12:29.103126 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9512 20:12:29.109925 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9513 20:12:29.112975 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9514 20:12:29.116616 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9515 20:12:29.123032 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9516 20:12:29.126460 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9517 20:12:29.129578 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9518 20:12:29.136506 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9519 20:12:29.139758 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9520 20:12:29.146424 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9521 20:12:29.149784 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9522 20:12:29.152840 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9523 20:12:29.159967 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9524 20:12:29.162922 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9525 20:12:29.169313 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9526 20:12:29.172986 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9527 20:12:29.176352 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9528 20:12:29.183257 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9529 20:12:29.186119 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9530 20:12:29.193131 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9531 20:12:29.196766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9532 20:12:29.199853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9533 20:12:29.202594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9534 20:12:29.209981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9535 20:12:29.212546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9536 20:12:29.216222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9537 20:12:29.219396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9538 20:12:29.225621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9539 20:12:29.229392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9540 20:12:29.232976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9541 20:12:29.235800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9542 20:12:29.242270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9543 20:12:29.245940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9544 20:12:29.249008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9545 20:12:29.255268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9546 20:12:29.258630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9547 20:12:29.261975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9548 20:12:29.268845 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9549 20:12:29.271838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9550 20:12:29.278870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9551 20:12:29.281986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9552 20:12:29.285031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9553 20:12:29.291963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9554 20:12:29.295340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9555 20:12:29.301816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9556 20:12:29.305079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9557 20:12:29.311829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9558 20:12:29.314909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9559 20:12:29.321727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9560 20:12:29.324928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9561 20:12:29.328221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9562 20:12:29.334813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9563 20:12:29.338189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9564 20:12:29.344844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9565 20:12:29.348276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9566 20:12:29.354812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9567 20:12:29.357738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9568 20:12:29.364357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9569 20:12:29.368113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9570 20:12:29.371260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9571 20:12:29.377846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9572 20:12:29.380812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9573 20:12:29.387991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9574 20:12:29.391084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9575 20:12:29.397472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9576 20:12:29.401352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9577 20:12:29.407223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9578 20:12:29.411122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9579 20:12:29.414060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9580 20:12:29.420892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9581 20:12:29.424553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9582 20:12:29.430856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9583 20:12:29.433944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9584 20:12:29.440705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9585 20:12:29.443789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9586 20:12:29.447250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9587 20:12:29.454077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9588 20:12:29.457180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9589 20:12:29.463753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9590 20:12:29.466949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9591 20:12:29.473785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9592 20:12:29.476972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9593 20:12:29.483886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9594 20:12:29.486854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9595 20:12:29.490410 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9596 20:12:29.496666 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9597 20:12:29.500389 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9598 20:12:29.503557 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9599 20:12:29.507311 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9600 20:12:29.513791 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9601 20:12:29.517206 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9602 20:12:29.523814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9603 20:12:29.526814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9604 20:12:29.530154 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9605 20:12:29.536988 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9606 20:12:29.540093 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9607 20:12:29.547061 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9608 20:12:29.550463 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9609 20:12:29.553413 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9610 20:12:29.559904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9611 20:12:29.563533 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9612 20:12:29.570148 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9613 20:12:29.573278 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9614 20:12:29.576768 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9615 20:12:29.582995 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9616 20:12:29.586552 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9617 20:12:29.589466 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9618 20:12:29.596597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9619 20:12:29.599799 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9620 20:12:29.603149 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9621 20:12:29.606109 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9622 20:12:29.613015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9623 20:12:29.616132 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9624 20:12:29.619653 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9625 20:12:29.625940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9626 20:12:29.629717 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9627 20:12:29.635822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9628 20:12:29.639466 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9629 20:12:29.642529 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9630 20:12:29.649439 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9631 20:12:29.652484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9632 20:12:29.659043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9633 20:12:29.662686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9634 20:12:29.666150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9635 20:12:29.672548 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9636 20:12:29.675552 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9637 20:12:29.679130 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9638 20:12:29.686093 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9639 20:12:29.688799 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9640 20:12:29.695680 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9641 20:12:29.698762 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9642 20:12:29.702362 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9643 20:12:29.708910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9644 20:12:29.712079 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9645 20:12:29.719126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9646 20:12:29.722573 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9647 20:12:29.725456 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9648 20:12:29.732153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9649 20:12:29.735354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9650 20:12:29.742000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9651 20:12:29.745332 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9652 20:12:29.749121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9653 20:12:29.755334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9654 20:12:29.758932 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9655 20:12:29.765361 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9656 20:12:29.768584 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9657 20:12:29.771875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9658 20:12:29.778455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9659 20:12:29.782053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9660 20:12:29.788427 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9661 20:12:29.791548 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9662 20:12:29.795144 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9663 20:12:29.801535 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9664 20:12:29.805045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9665 20:12:29.811294 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9666 20:12:29.814533 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9667 20:12:29.818001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9668 20:12:29.824856 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9669 20:12:29.827979 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9670 20:12:29.834178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9671 20:12:29.837743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9672 20:12:29.840746 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9673 20:12:29.847287 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9674 20:12:29.850761 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9675 20:12:29.857314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9676 20:12:29.860859 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9677 20:12:29.864269 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9678 20:12:29.870678 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9679 20:12:29.873842 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9680 20:12:29.880825 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9681 20:12:29.883912 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9682 20:12:29.886750 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9683 20:12:29.893914 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9684 20:12:29.896801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9685 20:12:29.903910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9686 20:12:29.906934 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9687 20:12:29.910022 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9688 20:12:29.916433 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9689 20:12:29.920331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9690 20:12:29.926502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9691 20:12:29.929927 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9692 20:12:29.937013 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9693 20:12:29.939504 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9694 20:12:29.942917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9695 20:12:29.949468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9696 20:12:29.952992 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9697 20:12:29.959776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9698 20:12:29.963183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9699 20:12:29.969531 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9700 20:12:29.972880 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9701 20:12:29.976025 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9702 20:12:29.983072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9703 20:12:29.986096 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9704 20:12:29.992626 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9705 20:12:29.995727 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9706 20:12:30.002238 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9707 20:12:30.006099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9708 20:12:30.008937 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9709 20:12:30.015500 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9710 20:12:30.018656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9711 20:12:30.025495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9712 20:12:30.029155 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9713 20:12:30.035287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9714 20:12:30.038531 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9715 20:12:30.041845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9716 20:12:30.048290 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9717 20:12:30.051845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9718 20:12:30.058494 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9719 20:12:30.061858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9720 20:12:30.065391 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9721 20:12:30.071404 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9722 20:12:30.074865 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9723 20:12:30.081225 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9724 20:12:30.084907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9725 20:12:30.091070 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9726 20:12:30.094514 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9727 20:12:30.101352 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9728 20:12:30.104674 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9729 20:12:30.107855 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9730 20:12:30.111203 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9731 20:12:30.114501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9732 20:12:30.121387 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9733 20:12:30.124211 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9734 20:12:30.130544 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9735 20:12:30.134034 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9736 20:12:30.137184 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9737 20:12:30.144050 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9738 20:12:30.147227 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9739 20:12:30.150545 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9740 20:12:30.157782 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9741 20:12:30.160390 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9742 20:12:30.163942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9743 20:12:30.170257 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9744 20:12:30.173272 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9745 20:12:30.180327 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9746 20:12:30.183600 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9747 20:12:30.186769 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9748 20:12:30.193862 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9749 20:12:30.196760 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9750 20:12:30.203080 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9751 20:12:30.206449 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9752 20:12:30.209468 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9753 20:12:30.216310 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9754 20:12:30.219586 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9755 20:12:30.223341 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9756 20:12:30.229496 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9757 20:12:30.232552 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9758 20:12:30.239158 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9759 20:12:30.242770 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9760 20:12:30.246328 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9761 20:12:30.252516 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9762 20:12:30.255693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9763 20:12:30.259141 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9764 20:12:30.265721 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9765 20:12:30.268825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9766 20:12:30.275585 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9767 20:12:30.278879 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9768 20:12:30.282581 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9769 20:12:30.285188 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9770 20:12:30.291770 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9771 20:12:30.295103 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9772 20:12:30.298437 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9773 20:12:30.301887 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9774 20:12:30.308420 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9775 20:12:30.312023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9776 20:12:30.315203 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9777 20:12:30.318231 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9778 20:12:30.324714 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9779 20:12:30.328189 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9780 20:12:30.331269 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9781 20:12:30.338447 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9782 20:12:30.341268 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9783 20:12:30.348019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9784 20:12:30.350940 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9785 20:12:30.354673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9786 20:12:30.360733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9787 20:12:30.364335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9788 20:12:30.371033 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9789 20:12:30.374205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9790 20:12:30.380556 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9791 20:12:30.384001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9792 20:12:30.387162 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9793 20:12:30.393652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9794 20:12:30.397087 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9795 20:12:30.403271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9796 20:12:30.406829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9797 20:12:30.413119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9798 20:12:30.416568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9799 20:12:30.419814 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9800 20:12:30.426295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9801 20:12:30.430299 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9802 20:12:30.436609 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9803 20:12:30.439621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9804 20:12:30.443022 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9805 20:12:30.450024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9806 20:12:30.452771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9807 20:12:30.459339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9808 20:12:30.462756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9809 20:12:30.469271 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9810 20:12:30.473368 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9811 20:12:30.476414 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9812 20:12:30.482674 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9813 20:12:30.485869 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9814 20:12:30.492519 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9815 20:12:30.497077 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9816 20:12:30.499146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9817 20:12:30.505600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9818 20:12:30.509259 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9819 20:12:30.516426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9820 20:12:30.518860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9821 20:12:30.525838 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9822 20:12:30.528770 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9823 20:12:30.531713 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9824 20:12:30.539154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9825 20:12:30.541451 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9826 20:12:30.548330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9827 20:12:30.551501 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9828 20:12:30.558173 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9829 20:12:30.561219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9830 20:12:30.565635 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9831 20:12:30.571301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9832 20:12:30.575011 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9833 20:12:30.581135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9834 20:12:30.584629 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9835 20:12:30.591313 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9836 20:12:30.594371 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9837 20:12:30.597668 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9838 20:12:30.604286 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9839 20:12:30.607787 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9840 20:12:30.613901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9841 20:12:30.617831 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9842 20:12:30.623817 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9843 20:12:30.627164 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9844 20:12:30.630991 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9845 20:12:30.637064 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9846 20:12:30.640464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9847 20:12:30.647101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9848 20:12:30.650320 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9849 20:12:30.653514 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9850 20:12:30.660621 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9851 20:12:30.663658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9852 20:12:30.670146 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9853 20:12:30.673355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9854 20:12:30.680269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9855 20:12:30.683224 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9856 20:12:30.686919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9857 20:12:30.693182 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9858 20:12:30.696550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9859 20:12:30.702913 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9860 20:12:30.706171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9861 20:12:30.713132 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9862 20:12:30.715988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9863 20:12:30.723092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9864 20:12:30.726054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9865 20:12:30.732793 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9866 20:12:30.735796 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9867 20:12:30.739096 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9868 20:12:30.745892 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9869 20:12:30.749485 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9870 20:12:30.756070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9871 20:12:30.759019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9872 20:12:30.765484 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9873 20:12:30.769289 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9874 20:12:30.775529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9875 20:12:30.778661 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9876 20:12:30.782257 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9877 20:12:30.789078 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9878 20:12:30.792062 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9879 20:12:30.798442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9880 20:12:30.801856 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9881 20:12:30.808717 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9882 20:12:30.811823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9883 20:12:30.818205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9884 20:12:30.821707 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9885 20:12:30.824917 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9886 20:12:30.831601 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9887 20:12:30.834493 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9888 20:12:30.841366 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9889 20:12:30.844586 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9890 20:12:30.851706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9891 20:12:30.854677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9892 20:12:30.857771 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9893 20:12:30.864448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9894 20:12:30.867527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9895 20:12:30.874153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9896 20:12:30.877188 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9897 20:12:30.883955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9898 20:12:30.887209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9899 20:12:30.894003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9900 20:12:30.897227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9901 20:12:30.900214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9902 20:12:30.906890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9903 20:12:30.910613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9904 20:12:30.916857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9905 20:12:30.920996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9906 20:12:30.926895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9907 20:12:30.930319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9908 20:12:30.936780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9909 20:12:30.940475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9910 20:12:30.946914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9911 20:12:30.950029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9912 20:12:30.956530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9913 20:12:30.960057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9914 20:12:30.966150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9915 20:12:30.969490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9916 20:12:30.976468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9917 20:12:30.979311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9918 20:12:30.986129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9919 20:12:30.989081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9920 20:12:30.995855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9921 20:12:30.999326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9922 20:12:31.005760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9923 20:12:31.009358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9924 20:12:31.015990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9925 20:12:31.018817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9926 20:12:31.025567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9927 20:12:31.028792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9928 20:12:31.035655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9929 20:12:31.039118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9930 20:12:31.045372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9931 20:12:31.048961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9932 20:12:31.055238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9933 20:12:31.058590 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9934 20:12:31.061733 INFO: [APUAPC] vio 0
9935 20:12:31.064865 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9936 20:12:31.071823 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9937 20:12:31.075173 INFO: [APUAPC] D0_APC_0: 0x400510
9938 20:12:31.078318 INFO: [APUAPC] D0_APC_1: 0x0
9939 20:12:31.078400 INFO: [APUAPC] D0_APC_2: 0x1540
9940 20:12:31.081532 INFO: [APUAPC] D0_APC_3: 0x0
9941 20:12:31.085065 INFO: [APUAPC] D1_APC_0: 0xffffffff
9942 20:12:31.088007 INFO: [APUAPC] D1_APC_1: 0xffffffff
9943 20:12:31.091646 INFO: [APUAPC] D1_APC_2: 0x3fffff
9944 20:12:31.094450 INFO: [APUAPC] D1_APC_3: 0x0
9945 20:12:31.097819 INFO: [APUAPC] D2_APC_0: 0xffffffff
9946 20:12:31.101409 INFO: [APUAPC] D2_APC_1: 0xffffffff
9947 20:12:31.104347 INFO: [APUAPC] D2_APC_2: 0x3fffff
9948 20:12:31.108015 INFO: [APUAPC] D2_APC_3: 0x0
9949 20:12:31.111272 INFO: [APUAPC] D3_APC_0: 0xffffffff
9950 20:12:31.114511 INFO: [APUAPC] D3_APC_1: 0xffffffff
9951 20:12:31.117474 INFO: [APUAPC] D3_APC_2: 0x3fffff
9952 20:12:31.121020 INFO: [APUAPC] D3_APC_3: 0x0
9953 20:12:31.124128 INFO: [APUAPC] D4_APC_0: 0xffffffff
9954 20:12:31.127966 INFO: [APUAPC] D4_APC_1: 0xffffffff
9955 20:12:31.130892 INFO: [APUAPC] D4_APC_2: 0x3fffff
9956 20:12:31.134108 INFO: [APUAPC] D4_APC_3: 0x0
9957 20:12:31.137416 INFO: [APUAPC] D5_APC_0: 0xffffffff
9958 20:12:31.141502 INFO: [APUAPC] D5_APC_1: 0xffffffff
9959 20:12:31.143717 INFO: [APUAPC] D5_APC_2: 0x3fffff
9960 20:12:31.147356 INFO: [APUAPC] D5_APC_3: 0x0
9961 20:12:31.150398 INFO: [APUAPC] D6_APC_0: 0xffffffff
9962 20:12:31.154317 INFO: [APUAPC] D6_APC_1: 0xffffffff
9963 20:12:31.157194 INFO: [APUAPC] D6_APC_2: 0x3fffff
9964 20:12:31.160414 INFO: [APUAPC] D6_APC_3: 0x0
9965 20:12:31.164006 INFO: [APUAPC] D7_APC_0: 0xffffffff
9966 20:12:31.167792 INFO: [APUAPC] D7_APC_1: 0xffffffff
9967 20:12:31.170288 INFO: [APUAPC] D7_APC_2: 0x3fffff
9968 20:12:31.174188 INFO: [APUAPC] D7_APC_3: 0x0
9969 20:12:31.177056 INFO: [APUAPC] D8_APC_0: 0xffffffff
9970 20:12:31.180476 INFO: [APUAPC] D8_APC_1: 0xffffffff
9971 20:12:31.183881 INFO: [APUAPC] D8_APC_2: 0x3fffff
9972 20:12:31.186860 INFO: [APUAPC] D8_APC_3: 0x0
9973 20:12:31.190464 INFO: [APUAPC] D9_APC_0: 0xffffffff
9974 20:12:31.193300 INFO: [APUAPC] D9_APC_1: 0xffffffff
9975 20:12:31.196656 INFO: [APUAPC] D9_APC_2: 0x3fffff
9976 20:12:31.200605 INFO: [APUAPC] D9_APC_3: 0x0
9977 20:12:31.203480 INFO: [APUAPC] D10_APC_0: 0xffffffff
9978 20:12:31.206491 INFO: [APUAPC] D10_APC_1: 0xffffffff
9979 20:12:31.209947 INFO: [APUAPC] D10_APC_2: 0x3fffff
9980 20:12:31.213119 INFO: [APUAPC] D10_APC_3: 0x0
9981 20:12:31.216717 INFO: [APUAPC] D11_APC_0: 0xffffffff
9982 20:12:31.219952 INFO: [APUAPC] D11_APC_1: 0xffffffff
9983 20:12:31.223034 INFO: [APUAPC] D11_APC_2: 0x3fffff
9984 20:12:31.226747 INFO: [APUAPC] D11_APC_3: 0x0
9985 20:12:31.229340 INFO: [APUAPC] D12_APC_0: 0xffffffff
9986 20:12:31.232872 INFO: [APUAPC] D12_APC_1: 0xffffffff
9987 20:12:31.236212 INFO: [APUAPC] D12_APC_2: 0x3fffff
9988 20:12:31.239565 INFO: [APUAPC] D12_APC_3: 0x0
9989 20:12:31.242467 INFO: [APUAPC] D13_APC_0: 0xffffffff
9990 20:12:31.245786 INFO: [APUAPC] D13_APC_1: 0xffffffff
9991 20:12:31.249357 INFO: [APUAPC] D13_APC_2: 0x3fffff
9992 20:12:31.252471 INFO: [APUAPC] D13_APC_3: 0x0
9993 20:12:31.255601 INFO: [APUAPC] D14_APC_0: 0xffffffff
9994 20:12:31.258989 INFO: [APUAPC] D14_APC_1: 0xffffffff
9995 20:12:31.262418 INFO: [APUAPC] D14_APC_2: 0x3fffff
9996 20:12:31.265861 INFO: [APUAPC] D14_APC_3: 0x0
9997 20:12:31.269005 INFO: [APUAPC] D15_APC_0: 0xffffffff
9998 20:12:31.272351 INFO: [APUAPC] D15_APC_1: 0xffffffff
9999 20:12:31.275902 INFO: [APUAPC] D15_APC_2: 0x3fffff
10000 20:12:31.278918 INFO: [APUAPC] D15_APC_3: 0x0
10001 20:12:31.282751 INFO: [APUAPC] APC_CON: 0x4
10002 20:12:31.285432 INFO: [NOCDAPC] D0_APC_0: 0x0
10003 20:12:31.288868 INFO: [NOCDAPC] D0_APC_1: 0x0
10004 20:12:31.291866 INFO: [NOCDAPC] D1_APC_0: 0x0
10005 20:12:31.295897 INFO: [NOCDAPC] D1_APC_1: 0xfff
10006 20:12:31.298976 INFO: [NOCDAPC] D2_APC_0: 0x0
10007 20:12:31.302261 INFO: [NOCDAPC] D2_APC_1: 0xfff
10008 20:12:31.302344 INFO: [NOCDAPC] D3_APC_0: 0x0
10009 20:12:31.305219 INFO: [NOCDAPC] D3_APC_1: 0xfff
10010 20:12:31.308635 INFO: [NOCDAPC] D4_APC_0: 0x0
10011 20:12:31.311826 INFO: [NOCDAPC] D4_APC_1: 0xfff
10012 20:12:31.315205 INFO: [NOCDAPC] D5_APC_0: 0x0
10013 20:12:31.318823 INFO: [NOCDAPC] D5_APC_1: 0xfff
10014 20:12:31.321862 INFO: [NOCDAPC] D6_APC_0: 0x0
10015 20:12:31.325168 INFO: [NOCDAPC] D6_APC_1: 0xfff
10016 20:12:31.328786 INFO: [NOCDAPC] D7_APC_0: 0x0
10017 20:12:31.332142 INFO: [NOCDAPC] D7_APC_1: 0xfff
10018 20:12:31.335400 INFO: [NOCDAPC] D8_APC_0: 0x0
10019 20:12:31.338270 INFO: [NOCDAPC] D8_APC_1: 0xfff
10020 20:12:31.338352 INFO: [NOCDAPC] D9_APC_0: 0x0
10021 20:12:31.341807 INFO: [NOCDAPC] D9_APC_1: 0xfff
10022 20:12:31.345071 INFO: [NOCDAPC] D10_APC_0: 0x0
10023 20:12:31.348602 INFO: [NOCDAPC] D10_APC_1: 0xfff
10024 20:12:31.351480 INFO: [NOCDAPC] D11_APC_0: 0x0
10025 20:12:31.354834 INFO: [NOCDAPC] D11_APC_1: 0xfff
10026 20:12:31.358135 INFO: [NOCDAPC] D12_APC_0: 0x0
10027 20:12:31.361647 INFO: [NOCDAPC] D12_APC_1: 0xfff
10028 20:12:31.364686 INFO: [NOCDAPC] D13_APC_0: 0x0
10029 20:12:31.368763 INFO: [NOCDAPC] D13_APC_1: 0xfff
10030 20:12:31.371274 INFO: [NOCDAPC] D14_APC_0: 0x0
10031 20:12:31.375023 INFO: [NOCDAPC] D14_APC_1: 0xfff
10032 20:12:31.378072 INFO: [NOCDAPC] D15_APC_0: 0x0
10033 20:12:31.381676 INFO: [NOCDAPC] D15_APC_1: 0xfff
10034 20:12:31.384703 INFO: [NOCDAPC] APC_CON: 0x4
10035 20:12:31.388005 INFO: [APUAPC] set_apusys_apc done
10036 20:12:31.388090 INFO: [DEVAPC] devapc_init done
10037 20:12:31.394599 INFO: GICv3 without legacy support detected.
10038 20:12:31.398307 INFO: ARM GICv3 driver initialized in EL3
10039 20:12:31.400872 INFO: Maximum SPI INTID supported: 639
10040 20:12:31.404125 INFO: BL31: Initializing runtime services
10041 20:12:31.410787 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10042 20:12:31.414084 INFO: SPM: enable CPC mode
10043 20:12:31.420617 INFO: mcdi ready for mcusys-off-idle and system suspend
10044 20:12:31.423881 INFO: BL31: Preparing for EL3 exit to normal world
10045 20:12:31.427158 INFO: Entry point address = 0x80000000
10046 20:12:31.430064 INFO: SPSR = 0x8
10047 20:12:31.434999
10048 20:12:31.435083
10049 20:12:31.435168
10050 20:12:31.438394 Starting depthcharge on Spherion...
10051 20:12:31.438480
10052 20:12:31.438565 Wipe memory regions:
10053 20:12:31.438647
10054 20:12:31.439527 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10055 20:12:31.439641 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10056 20:12:31.439734 Setting prompt string to ['asurada:']
10057 20:12:31.439835 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10058 20:12:31.441945 [0x00000040000000, 0x00000054600000)
10059 20:12:31.564451
10060 20:12:31.564567 [0x00000054660000, 0x00000080000000)
10061 20:12:31.825010
10062 20:12:31.825154 [0x000000821a7280, 0x000000ffe64000)
10063 20:12:32.569503
10064 20:12:32.569651 [0x00000100000000, 0x00000240000000)
10065 20:12:34.459695
10066 20:12:34.462742 Initializing XHCI USB controller at 0x11200000.
10067 20:12:35.500789
10068 20:12:35.503737 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10069 20:12:35.503826
10070 20:12:35.503912
10071 20:12:35.503994
10072 20:12:35.504310 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 20:12:35.604720 asurada: tftpboot 192.168.201.1 12928085/tftp-deploy-w2rggnd5/kernel/image.itb 12928085/tftp-deploy-w2rggnd5/kernel/cmdline
10075 20:12:35.604848 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 20:12:35.604946 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10077 20:12:35.609381 tftpboot 192.168.201.1 12928085/tftp-deploy-w2rggnd5/kernel/image.itp-deploy-w2rggnd5/kernel/cmdline
10078 20:12:35.609470
10079 20:12:35.609555 Waiting for link
10080 20:12:35.769892
10081 20:12:35.770009 R8152: Initializing
10082 20:12:35.770101
10083 20:12:35.773275 Version 6 (ocp_data = 5c30)
10084 20:12:35.773361
10085 20:12:35.776418 R8152: Done initializing
10086 20:12:35.776503
10087 20:12:35.776589 Adding net device
10088 20:12:37.710718
10089 20:12:37.710871 done.
10090 20:12:37.710965
10091 20:12:37.711048 MAC: 00:24:32:30:7c:7b
10092 20:12:37.711129
10093 20:12:37.713693 Sending DHCP discover... done.
10094 20:12:37.713780
10095 20:12:37.716992 Waiting for reply... done.
10096 20:12:37.717078
10097 20:12:37.720656 Sending DHCP request... done.
10098 20:12:37.720742
10099 20:12:37.725589 Waiting for reply... done.
10100 20:12:37.725675
10101 20:12:37.725762 My ip is 192.168.201.14
10102 20:12:37.725843
10103 20:12:37.728644 The DHCP server ip is 192.168.201.1
10104 20:12:37.728730
10105 20:12:37.735108 TFTP server IP predefined by user: 192.168.201.1
10106 20:12:37.735194
10107 20:12:37.742015 Bootfile predefined by user: 12928085/tftp-deploy-w2rggnd5/kernel/image.itb
10108 20:12:37.742101
10109 20:12:37.745307 Sending tftp read request... done.
10110 20:12:37.745392
10111 20:12:37.749165 Waiting for the transfer...
10112 20:12:37.749251
10113 20:12:38.304298 00000000 ################################################################
10114 20:12:38.304510
10115 20:12:38.836802 00080000 ################################################################
10116 20:12:38.836973
10117 20:12:39.391611 00100000 ################################################################
10118 20:12:39.391756
10119 20:12:39.925766 00180000 ################################################################
10120 20:12:39.925918
10121 20:12:40.472098 00200000 ################################################################
10122 20:12:40.472251
10123 20:12:41.030811 00280000 ################################################################
10124 20:12:41.030951
10125 20:12:41.625409 00300000 ################################################################
10126 20:12:41.625559
10127 20:12:42.204591 00380000 ################################################################
10128 20:12:42.204739
10129 20:12:42.754927 00400000 ################################################################
10130 20:12:42.755110
10131 20:12:43.333032 00480000 ################################################################
10132 20:12:43.333176
10133 20:12:43.896569 00500000 ################################################################
10134 20:12:43.896702
10135 20:12:44.470460 00580000 ################################################################
10136 20:12:44.470652
10137 20:12:45.048135 00600000 ################################################################
10138 20:12:45.048270
10139 20:12:45.635773 00680000 ################################################################
10140 20:12:45.635905
10141 20:12:46.218519 00700000 ################################################################
10142 20:12:46.218702
10143 20:12:46.804041 00780000 ################################################################
10144 20:12:46.804189
10145 20:12:47.378933 00800000 ################################################################
10146 20:12:47.379083
10147 20:12:47.948459 00880000 ################################################################
10148 20:12:47.948676
10149 20:12:48.523166 00900000 ################################################################
10150 20:12:48.523341
10151 20:12:49.098246 00980000 ################################################################
10152 20:12:49.098496
10153 20:12:49.673319 00a00000 ################################################################
10154 20:12:49.673474
10155 20:12:50.238695 00a80000 ################################################################
10156 20:12:50.238845
10157 20:12:50.788338 00b00000 ################################################################
10158 20:12:50.788489
10159 20:12:51.326809 00b80000 ################################################################
10160 20:12:51.326955
10161 20:12:51.881542 00c00000 ################################################################
10162 20:12:51.881692
10163 20:12:52.436489 00c80000 ################################################################
10164 20:12:52.436640
10165 20:12:52.965780 00d00000 ################################################################
10166 20:12:52.965928
10167 20:12:53.521206 00d80000 ################################################################
10168 20:12:53.521356
10169 20:12:54.100415 00e00000 ################################################################
10170 20:12:54.100559
10171 20:12:54.678035 00e80000 ################################################################
10172 20:12:54.678183
10173 20:12:55.258437 00f00000 ################################################################
10174 20:12:55.258583
10175 20:12:55.852220 00f80000 ################################################################
10176 20:12:55.852368
10177 20:12:56.433651 01000000 ################################################################
10178 20:12:56.433860
10179 20:12:56.990236 01080000 ################################################################
10180 20:12:56.990389
10181 20:12:57.565624 01100000 ################################################################
10182 20:12:57.565774
10183 20:12:58.134410 01180000 ################################################################
10184 20:12:58.134562
10185 20:12:58.702840 01200000 ################################################################
10186 20:12:58.702970
10187 20:12:59.286877 01280000 ################################################################
10188 20:12:59.287016
10189 20:12:59.876733 01300000 ################################################################
10190 20:12:59.876902
10191 20:13:00.468348 01380000 ################################################################
10192 20:13:00.468500
10193 20:13:01.060892 01400000 ################################################################
10194 20:13:01.061159
10195 20:13:01.635188 01480000 ################################################################
10196 20:13:01.635348
10197 20:13:02.219260 01500000 ################################################################
10198 20:13:02.219451
10199 20:13:02.784106 01580000 ################################################################
10200 20:13:02.784258
10201 20:13:03.379239 01600000 ################################################################
10202 20:13:03.379427
10203 20:13:03.968551 01680000 ################################################################
10204 20:13:03.968750
10205 20:13:04.553135 01700000 ################################################################
10206 20:13:04.553330
10207 20:13:05.119320 01780000 ################################################################
10208 20:13:05.119554
10209 20:13:05.669576 01800000 ################################################################
10210 20:13:05.669795
10211 20:13:06.218087 01880000 ################################################################
10212 20:13:06.218245
10213 20:13:06.770132 01900000 ################################################################
10214 20:13:06.770283
10215 20:13:07.341175 01980000 ################################################################
10216 20:13:07.341319
10217 20:13:07.910983 01a00000 ################################################################
10218 20:13:07.911130
10219 20:13:08.492409 01a80000 ################################################################
10220 20:13:08.492605
10221 20:13:09.054873 01b00000 ################################################################
10222 20:13:09.055095
10223 20:13:09.623123 01b80000 ################################################################
10224 20:13:09.623286
10225 20:13:10.204556 01c00000 ################################################################
10226 20:13:10.204720
10227 20:13:10.232097 01c80000 ### done.
10228 20:13:10.232225
10229 20:13:10.235490 The bootfile was 29908990 bytes long.
10230 20:13:10.235617
10231 20:13:10.238291 Sending tftp read request... done.
10232 20:13:10.238365
10233 20:13:10.238427 Waiting for the transfer...
10234 20:13:10.238486
10235 20:13:10.242039 00000000 # done.
10236 20:13:10.242132
10237 20:13:10.248385 Command line loaded dynamically from TFTP file: 12928085/tftp-deploy-w2rggnd5/kernel/cmdline
10238 20:13:10.248478
10239 20:13:10.271617 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 20:13:10.271705
10241 20:13:10.271772 Loading FIT.
10242 20:13:10.271867
10243 20:13:10.275253 Image ramdisk-1 has 17799638 bytes.
10244 20:13:10.275337
10245 20:13:10.278312 Image fdt-1 has 47278 bytes.
10246 20:13:10.278420
10247 20:13:10.281354 Image kernel-1 has 12060038 bytes.
10248 20:13:10.281436
10249 20:13:10.292003 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 20:13:10.292087
10251 20:13:10.308398 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 20:13:10.308489
10253 20:13:10.314900 Choosing best match conf-1 for compat google,spherion-rev2.
10254 20:13:10.314984
10255 20:13:10.322485 Connected to device vid:did:rid of 1ae0:0028:00
10256 20:13:10.330158
10257 20:13:10.333621 tpm_get_response: command 0x17b, return code 0x0
10258 20:13:10.333706
10259 20:13:10.337292 ec_init: CrosEC protocol v3 supported (256, 248)
10260 20:13:10.342229
10261 20:13:10.345217 tpm_cleanup: add release locality here.
10262 20:13:10.345301
10263 20:13:10.345386 Shutting down all USB controllers.
10264 20:13:10.348867
10265 20:13:10.348950 Removing current net device
10266 20:13:10.349035
10267 20:13:10.355257 Exiting depthcharge with code 4 at timestamp: 68147217
10268 20:13:10.355416
10269 20:13:10.358630 LZMA decompressing kernel-1 to 0x821a6718
10270 20:13:10.358715
10271 20:13:10.361941 LZMA decompressing kernel-1 to 0x40000000
10272 20:13:11.862211
10273 20:13:11.862366 jumping to kernel
10274 20:13:11.862999 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10275 20:13:11.863134 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10276 20:13:11.863244 Setting prompt string to ['Linux version [0-9]']
10277 20:13:11.863351 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 20:13:11.863501 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 20:13:11.944224
10280 20:13:11.947054 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 20:13:11.950559 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10282 20:13:11.950651 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 20:13:11.950721 Setting prompt string to []
10284 20:13:11.950796 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 20:13:11.950868 Using line separator: #'\n'#
10286 20:13:11.950926 No login prompt set.
10287 20:13:11.950985 Parsing kernel messages
10288 20:13:11.951038 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 20:13:11.951138 [login-action] Waiting for messages, (timeout 00:03:45)
10290 20:13:11.951200 Waiting using forced prompt support (timeout 00:01:52)
10291 20:13:11.970340 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10292 20:13:11.973341 [ 0.000000] random: crng init done
10293 20:13:11.980052 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10294 20:13:11.983395 [ 0.000000] efi: UEFI not found.
10295 20:13:11.990607 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10296 20:13:11.999950 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10297 20:13:12.009541 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10298 20:13:12.016220 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10299 20:13:12.022981 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10300 20:13:12.029408 [ 0.000000] printk: bootconsole [mtk8250] enabled
10301 20:13:12.036809 [ 0.000000] NUMA: No NUMA configuration found
10302 20:13:12.043048 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10303 20:13:12.049366 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10304 20:13:12.049450 [ 0.000000] Zone ranges:
10305 20:13:12.056060 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10306 20:13:12.059197 [ 0.000000] DMA32 empty
10307 20:13:12.065716 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10308 20:13:12.069274 [ 0.000000] Movable zone start for each node
10309 20:13:12.072290 [ 0.000000] Early memory node ranges
10310 20:13:12.078905 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10311 20:13:12.085917 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10312 20:13:12.092337 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10313 20:13:12.099209 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10314 20:13:12.105393 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10315 20:13:12.112193 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10316 20:13:12.168746 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10317 20:13:12.175590 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10318 20:13:12.182016 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10319 20:13:12.185813 [ 0.000000] psci: probing for conduit method from DT.
10320 20:13:12.191740 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10321 20:13:12.195664 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10322 20:13:12.202084 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10323 20:13:12.205598 [ 0.000000] psci: SMC Calling Convention v1.2
10324 20:13:12.211960 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10325 20:13:12.215175 [ 0.000000] Detected VIPT I-cache on CPU0
10326 20:13:12.221870 [ 0.000000] CPU features: detected: GIC system register CPU interface
10327 20:13:12.228611 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10328 20:13:12.235277 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10329 20:13:12.241907 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10330 20:13:12.251615 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10331 20:13:12.258263 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10332 20:13:12.261367 [ 0.000000] alternatives: applying boot alternatives
10333 20:13:12.268130 [ 0.000000] Fallback order for Node 0: 0
10334 20:13:12.274589 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10335 20:13:12.277842 [ 0.000000] Policy zone: Normal
10336 20:13:12.301405 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10337 20:13:12.310656 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10338 20:13:12.321802 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10339 20:13:12.331628 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10340 20:13:12.338379 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10341 20:13:12.341752 <6>[ 0.000000] software IO TLB: area num 8.
10342 20:13:12.398463 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10343 20:13:12.547943 <6>[ 0.000000] Memory: 7949808K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 402960K reserved, 32768K cma-reserved)
10344 20:13:12.554530 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10345 20:13:12.561322 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10346 20:13:12.564253 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10347 20:13:12.571288 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10348 20:13:12.577544 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10349 20:13:12.580918 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10350 20:13:12.590827 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10351 20:13:12.597516 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10352 20:13:12.604258 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10353 20:13:12.610484 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10354 20:13:12.613975 <6>[ 0.000000] GICv3: 608 SPIs implemented
10355 20:13:12.617638 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10356 20:13:12.623779 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10357 20:13:12.626700 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10358 20:13:12.633232 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10359 20:13:12.646610 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10360 20:13:12.659934 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10361 20:13:12.666245 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10362 20:13:12.674528 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10363 20:13:12.687813 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10364 20:13:12.694743 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10365 20:13:12.701119 <6>[ 0.009236] Console: colour dummy device 80x25
10366 20:13:12.711217 <6>[ 0.013985] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10367 20:13:12.717595 <6>[ 0.024427] pid_max: default: 32768 minimum: 301
10368 20:13:12.720974 <6>[ 0.029329] LSM: Security Framework initializing
10369 20:13:12.727905 <6>[ 0.034266] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 20:13:12.737904 <6>[ 0.042082] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10371 20:13:12.747532 <6>[ 0.051488] cblist_init_generic: Setting adjustable number of callback queues.
10372 20:13:12.751174 <6>[ 0.058976] cblist_init_generic: Setting shift to 3 and lim to 1.
10373 20:13:12.760764 <6>[ 0.065316] cblist_init_generic: Setting adjustable number of callback queues.
10374 20:13:12.767266 <6>[ 0.072743] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 20:13:12.770505 <6>[ 0.079190] rcu: Hierarchical SRCU implementation.
10376 20:13:12.777103 <6>[ 0.079193] rcu: Max phase no-delay instances is 1000.
10377 20:13:12.783347 <6>[ 0.079217] printk: bootconsole [mtk8250] printing thread started
10378 20:13:12.790145 <6>[ 0.097521] EFI services will not be available.
10379 20:13:12.793510 <6>[ 0.097723] smp: Bringing up secondary CPUs ...
10380 20:13:12.800169 <6>[ 0.098038] Detected VIPT I-cache on CPU1
10381 20:13:12.806800 <6>[ 0.098103] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10382 20:13:12.813598 <6>[ 0.098137] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10383 20:13:12.822824 <6>[ 0.126040] Detected VIPT I-cache on CPU2
10384 20:13:12.832721 <6>[ 0.126091] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10385 20:13:12.839383 <6>[ 0.126108] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10386 20:13:12.842873 <6>[ 0.126366] Detected VIPT I-cache on CPU3
10387 20:13:12.849416 <6>[ 0.126412] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10388 20:13:12.856408 <6>[ 0.126426] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10389 20:13:12.858993 <6>[ 0.126738] CPU features: detected: Spectre-v4
10390 20:13:12.865979 <6>[ 0.126746] CPU features: detected: Spectre-BHB
10391 20:13:12.869121 <6>[ 0.126750] Detected PIPT I-cache on CPU4
10392 20:13:12.875691 <6>[ 0.126810] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10393 20:13:12.882468 <6>[ 0.126827] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10394 20:13:12.888791 <6>[ 0.127120] Detected PIPT I-cache on CPU5
10395 20:13:12.895581 <6>[ 0.127181] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10396 20:13:12.902098 <6>[ 0.127198] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10397 20:13:12.904943 <6>[ 0.127471] Detected PIPT I-cache on CPU6
10398 20:13:12.915248 <6>[ 0.127537] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10399 20:13:12.922105 <6>[ 0.127553] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10400 20:13:12.925485 <6>[ 0.127845] Detected PIPT I-cache on CPU7
10401 20:13:12.932002 <6>[ 0.127910] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10402 20:13:12.938030 <6>[ 0.127926] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10403 20:13:12.941496 <6>[ 0.127973] smp: Brought up 1 node, 8 CPUs
10404 20:13:12.947847 <6>[ 0.127977] SMP: Total of 8 processors activated.
10405 20:13:12.955265 <6>[ 0.127980] CPU features: detected: 32-bit EL0 Support
10406 20:13:12.961215 <6>[ 0.127982] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10407 20:13:12.967597 <6>[ 0.127985] CPU features: detected: Common not Private translations
10408 20:13:12.974358 <6>[ 0.127987] CPU features: detected: CRC32 instructions
10409 20:13:12.981341 <6>[ 0.127989] CPU features: detected: RCpc load-acquire (LDAPR)
10410 20:13:12.984237 <6>[ 0.127991] CPU features: detected: LSE atomic instructions
10411 20:13:12.990676 <6>[ 0.127993] CPU features: detected: Privileged Access Never
10412 20:13:12.997802 <6>[ 0.127994] CPU features: detected: RAS Extension Support
10413 20:13:13.004265 <6>[ 0.127997] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10414 20:13:13.007093 <6>[ 0.128062] CPU: All CPU(s) started at EL2
10415 20:13:13.013923 <6>[ 0.128063] alternatives: applying system-wide alternatives
10416 20:13:13.016922 <6>[ 0.141176] devtmpfs: initialized
10417 20:13:13.027124 <6>[ 0.147382] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10418 20:13:13.049987 �B�YV�.]Y�Y��PF_INET protocol family
10419 20:13:13.056339 <6>[ 0.36453<0] printk: console [ttyS0] printing thread started
10420 20:13:13.066016 6>[ 0.229071] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10421 20:13:13.073692 <6>[ 0.364540] printk: console [ttyS0] enabled
10422 20:13:13.077021 <6>[ 0.364543] printk: bootconsole [mtk8250] disabled
10423 20:13:13.083265 <6>[ 0.378218] printk: bootconsole [mtk8250] printing thread stopped
10424 20:13:13.090482 <6>[ 0.379512] SuperH (H)SCI(F) driver initialized
10425 20:13:13.093739 <6>[ 0.380020] msm_serial: driver initialized
10426 20:13:13.103553 <6>[ 0.384705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10427 20:13:13.109952 <6>[ 0.384733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10428 20:13:13.118035 <6>[ 0.384763] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10429 20:13:13.127523 <6>[ 0.384791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10430 20:13:13.141765 <6>[ 0.384813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10431 20:13:13.146397 <6>[ 0.384840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10432 20:13:13.158310 <6>[ 0.384868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10433 20:13:13.163297 <6>[ 0.384991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10434 20:13:13.175847 <6>[ 0.385021] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10435 20:13:13.179912 <6>[ 0.394801] loop: module loaded
10436 20:13:13.183655 <6>[ 0.397400] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10437 20:13:13.186475 <4>[ 0.414535] mtk-pmic-keys: Failed to locate of_node [id: -1]
10438 20:13:13.190092 <6>[ 0.415464] megasas: 07.719.03.00-rc1
10439 20:13:13.196250 <6>[ 0.425047] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10440 20:13:13.202932 <6>[ 0.429105] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10441 20:13:13.209503 <6>[ 0.441310] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10442 20:13:13.219517 <6>[ 0.494654] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10443 20:13:13.697813 <6>[ 1.004015] Freeing initrd memory: 17376K
10444 20:13:13.705433 <6>[ 1.010030] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10445 20:13:13.712427 <6>[ 1.014669] tun: Universal TUN/TAP device driver, 1.6
10446 20:13:13.715486 <6>[ 1.015437] thunder_xcv, ver 1.0
10447 20:13:13.718944 <6>[ 1.015453] thunder_bgx, ver 1.0
10448 20:13:13.721938 <6>[ 1.015466] nicpf, ver 1.0
10449 20:13:13.728521 <6>[ 1.016533] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10450 20:13:13.735078 <6>[ 1.016536] hns3: Copyright (c) 2017 Huawei Corporation.
10451 20:13:13.738613 <6>[ 1.016560] hclge is initializing
10452 20:13:13.745304 <6>[ 1.016574] e1000: Intel(R) PRO/1000 Network Driver
10453 20:13:13.749131 <6>[ 1.016576] e1000: Copyright (c) 1999-2006 Intel Corporation.
10454 20:13:13.756270 <6>[ 1.016595] e1000e: Intel(R) PRO/1000 Network Driver
10455 20:13:13.760107 <6>[ 1.016596] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10456 20:13:13.766468 <6>[ 1.016612] igb: Intel(R) Gigabit Ethernet Network Driver
10457 20:13:13.773362 <6>[ 1.016615] igb: Copyright (c) 2007-2014 Intel Corporation.
10458 20:13:13.780335 <6>[ 1.016629] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10459 20:13:13.784132 <6>[ 1.016631] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10460 20:13:13.790352 <6>[ 1.016926] sky2: driver version 1.30
10461 20:13:13.793327 <6>[ 1.018028] VFIO - User Level meta-driver version: 0.3
10462 20:13:13.800260 <6>[ 1.020937] usbcore: registered new interface driver usb-storage
10463 20:13:13.806578 <6>[ 1.021115] usbcore: registered new device driver onboard-usb-hub
10464 20:13:13.813375 <6>[ 1.023944] mt6397-rtc mt6359-rtc: registered as rtc0
10465 20:13:13.820184 <6>[ 1.024098] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:13:14 UTC (1709496794)
10466 20:13:13.826549 <6>[ 1.024723] i2c_dev: i2c /dev entries driver
10467 20:13:13.833470 <6>[ 1.031965] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10468 20:13:13.839781 <6>[ 1.047965] cpu cpu0: EM: created perf domain
10469 20:13:13.842995 <6>[ 1.048282] cpu cpu4: EM: created perf domain
10470 20:13:13.849845 <6>[ 1.051962] sdhci: Secure Digital Host Controller Interface driver
10471 20:13:13.854143 <6>[ 1.051963] sdhci: Copyright(c) Pierre Ossman
10472 20:13:13.859693 <6>[ 1.052337] Synopsys Designware Multimedia Card Interface Driver
10473 20:13:13.866294 <6>[ 1.052728] sdhci-pltfm: SDHCI platform and OF driver helper
10474 20:13:13.872917 <6>[ 1.057063] ledtrig-cpu: registered to indicate activity on CPUs
10475 20:13:13.876179 <6>[ 1.057407] mmc0: CQHCI version 5.10
10476 20:13:13.882982 <6>[ 1.057898] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10477 20:13:13.889616 <6>[ 1.058173] usbcore: registered new interface driver usbhid
10478 20:13:13.892756 <6>[ 1.058175] usbhid: USB HID core driver
10479 20:13:13.899320 <6>[ 1.058319] spi_master spi0: will run message pump with realtime priority
10480 20:13:13.912507 <6>[ 1.087961] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10481 20:13:13.925641 <6>[ 1.089962] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10482 20:13:13.932540 <6>[ 1.091074] cros-ec-spi spi0.0: Chrome EC device registered
10483 20:13:13.942301 <6>[ 1.108657] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10484 20:13:13.945820 <6>[ 1.111111] NET: Registered PF_PACKET protocol family
10485 20:13:13.952338 <6>[ 1.111219] 9pnet: Installing 9P2000 support
10486 20:13:13.956553 <5>[ 1.111257] Key type dns_resolver registered
10487 20:13:13.958980 <6>[ 1.111720] registered taskstats version 1
10488 20:13:13.965335 <5>[ 1.111738] Loading compiled-in X.509 certificates
10489 20:13:13.975802 <4>[ 1.134316] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10490 20:13:13.985200 <4>[ 1.134507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10491 20:13:13.992108 <3>[ 1.134519] debugfs: File 'uA_load' in directory '/' already present!
10492 20:13:13.998320 <3>[ 1.134527] debugfs: File 'min_uV' in directory '/' already present!
10493 20:13:14.004803 <3>[ 1.134530] debugfs: File 'max_uV' in directory '/' already present!
10494 20:13:14.011475 <3>[ 1.134534] debugfs: File 'constraint_flags' in directory '/' already present!
10495 20:13:14.021547 <3>[ 1.136760] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10496 20:13:14.028306 <6>[ 1.145360] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10497 20:13:14.035196 <6>[ 1.146086] xhci-mtk 11200000.usb: xHCI Host Controller
10498 20:13:14.041481 <6>[ 1.146104] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10499 20:13:14.051501 <6>[ 1.146354] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10500 20:13:14.058289 <6>[ 1.146406] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10501 20:13:14.061300 <6>[ 1.146510] xhci-mtk 11200000.usb: xHCI Host Controller
10502 20:13:14.067981 <6>[ 1.146519] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10503 20:13:14.077705 <6>[ 1.146532] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10504 20:13:14.081263 <6>[ 1.147085] hub 1-0:1.0: USB hub found
10505 20:13:14.085142 <6>[ 1.147104] hub 1-0:1.0: 1 port detected
10506 20:13:14.094343 <6>[ 1.147303] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10507 20:13:14.097928 <6>[ 1.147552] hub 2-0:1.0: USB hub found
10508 20:13:14.101168 <6>[ 1.147566] hub 2-0:1.0: 1 port detected
10509 20:13:14.107925 <6>[ 1.150866] mtk-msdc 11f70000.mmc: Got CD GPIO
10510 20:13:14.110925 <6>[ 1.156359] mmc0: Command Queue Engine enabled
10511 20:13:14.117419 <6>[ 1.156370] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10512 20:13:14.121223 <6>[ 1.156814] mmcblk0: mmc0:0001 DA4128 116 GiB
10513 20:13:14.127737 <6>[ 1.160062] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10514 20:13:14.134072 <6>[ 1.161114] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10515 20:13:14.137401 <6>[ 1.162023] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10516 20:13:14.144249 <6>[ 1.162750] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10517 20:13:14.154016 <6>[ 1.168004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10518 20:13:14.160452 <6>[ 1.168010] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10519 20:13:14.171004 <4>[ 1.168174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10520 20:13:14.177175 <6>[ 1.168808] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10521 20:13:14.187200 <6>[ 1.168811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10522 20:13:14.193107 <6>[ 1.168932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10523 20:13:14.203467 <6>[ 1.168944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10524 20:13:14.209707 <6>[ 1.168948] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10525 20:13:14.219595 <6>[ 1.168953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10526 20:13:14.226055 <6>[ 1.170553] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10527 20:13:14.236068 <6>[ 1.170575] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10528 20:13:14.242649 <6>[ 1.170580] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10529 20:13:14.252757 <6>[ 1.170586] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10530 20:13:14.259248 <6>[ 1.170591] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10531 20:13:14.269367 <6>[ 1.170596] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10532 20:13:14.276045 <6>[ 1.170601] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10533 20:13:14.285838 <6>[ 1.170607] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10534 20:13:14.292211 <6>[ 1.170612] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10535 20:13:14.302271 <6>[ 1.170617] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10536 20:13:14.308885 <6>[ 1.170622] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10537 20:13:14.318437 <6>[ 1.170627] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10538 20:13:14.328196 <6>[ 1.170632] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10539 20:13:14.334990 <6>[ 1.170637] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10540 20:13:14.344628 <6>[ 1.170642] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10541 20:13:14.351239 <6>[ 1.171168] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10542 20:13:14.358192 <6>[ 1.172041] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10543 20:13:14.364432 <6>[ 1.172591] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10544 20:13:14.371535 <6>[ 1.173207] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10545 20:13:14.377901 <6>[ 1.173866] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10546 20:13:14.385071 <6>[ 1.174050] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10547 20:13:14.394787 <6>[ 1.174066] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10548 20:13:14.404206 <6>[ 1.174072] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10549 20:13:14.414280 <6>[ 1.174078] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10550 20:13:14.424061 <6>[ 1.174084] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10551 20:13:14.430481 <6>[ 1.174090] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10552 20:13:14.440405 <6>[ 1.174099] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10553 20:13:14.450474 <6>[ 1.174105] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10554 20:13:14.460378 <6>[ 1.174110] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10555 20:13:14.470223 <6>[ 1.174117] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10556 20:13:14.480012 <6>[ 1.174122] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10557 20:13:14.489835 <6>[ 1.175167] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10558 20:13:14.493082 <6>[ 1.182544] Trying to probe devices needed for running init ...
10559 20:13:14.499707 <6>[ 1.565847] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10560 20:13:14.506531 <6>[ 1.729585] hub 1-1:1.0: USB hub found
10561 20:13:14.509692 <6>[ 1.729970] hub 1-1:1.0: 4 ports detected
10562 20:13:14.512971 <6>[ 1.733163] hub 1-1:1.0: USB hub found
10563 20:13:14.516405 <6>[ 1.733414] hub 1-1:1.0: 4 ports detected
10564 20:13:14.556730 <6>[ 1.857949] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10565 20:13:14.577332 <6>[ 1.882128] hub 2-1:1.0: USB hub found
10566 20:13:14.580642 <6>[ 1.882483] hub 2-1:1.0: 3 ports detected
10567 20:13:14.583949 <6>[ 1.885043] hub 2-1:1.0: USB hub found
10568 20:13:14.590516 <6>[ 1.885364] hub 2-1:1.0: 3 ports detected
10569 20:13:14.744904 <6>[ 2.046018] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10570 20:13:14.865504 <6>[ 2.173286] hub 1-1.4:1.0: USB hub found
10571 20:13:14.869004 <6>[ 2.173647] hub 1-1.4:1.0: 2 ports detected
10572 20:13:14.872071 <6>[ 2.177121] hub 1-1.4:1.0: USB hub found
10573 20:13:14.878538 <6>[ 2.177460] hub 1-1.4:1.0: 2 ports detected
10574 20:13:14.948837 <6>[ 2.250106] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10575 20:13:15.164827 <6>[ 2.465987] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10576 20:13:15.349178 <6>[ 2.649992] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10577 20:13:26.165107 <6>[ 13.475025] ALSA device list:
10578 20:13:26.171511 <6>[ 13.475048] No soundcards found.
10579 20:13:26.175351 <6>[ 13.479437] Freeing unused kernel memory: 8448K
10580 20:13:26.178211 <6>[ 13.479613] Run /init as init process
10581 20:13:26.181588 Loading, please wait...
10582 20:13:26.202166 Starting version 247.3-7+deb11u4
10583 20:13:26.391304 <6>[ 13.697096] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10584 20:13:26.412209 <6>[ 13.719405] remoteproc remoteproc0: scp is available
10585 20:13:26.418761 <6>[ 13.719495] remoteproc remoteproc0: powering up scp
10586 20:13:26.425333 <6>[ 13.719502] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10587 20:13:26.434966 <6>[ 13.719533] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10588 20:13:26.444735 <6>[ 13.725485] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10589 20:13:26.451529 <6>[ 13.725527] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10590 20:13:26.461388 <6>[ 13.725537] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10591 20:13:26.468254 <4>[ 13.751711] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10592 20:13:26.475080 <4>[ 13.751834] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10593 20:13:26.481661 <6>[ 13.759098] mc: Linux media interface: v0.10
10594 20:13:26.488125 <3>[ 13.759945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10595 20:13:26.494705 <3>[ 13.759972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10596 20:13:26.504859 <3>[ 13.759983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10597 20:13:26.511488 <3>[ 13.760213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10598 20:13:26.522290 <3>[ 13.760225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 20:13:26.528815 <3>[ 13.760237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 20:13:26.535755 <3>[ 13.760254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10601 20:13:26.545346 <3>[ 13.760261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 20:13:26.551841 <3>[ 13.760374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10603 20:13:26.561901 <3>[ 13.760450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10604 20:13:26.568344 <3>[ 13.760457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10605 20:13:26.578543 <3>[ 13.760465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10606 20:13:26.585225 <3>[ 13.760534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10607 20:13:26.591772 <3>[ 13.760542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 20:13:26.601259 <3>[ 13.760549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 20:13:26.608037 <3>[ 13.760557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 20:13:26.618407 <3>[ 13.760563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 20:13:26.624410 <3>[ 13.762146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 20:13:26.630957 <6>[ 13.771954] usbcore: registered new device driver r8152-cfgselector
10613 20:13:26.641086 <6>[ 13.775254] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10614 20:13:26.644780 <6>[ 13.783381] videodev: Linux video capture interface: v2.00
10615 20:13:26.654473 <4>[ 13.800326] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10616 20:13:26.657416 <4>[ 13.800326] Fallback method does not support PEC.
10617 20:13:26.667631 <3>[ 13.815515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10618 20:13:26.677317 <3>[ 13.838825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 20:13:26.684172 <6>[ 13.847099] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10620 20:13:26.691292 <6>[ 13.847112] pci_bus 0000:00: root bus resource [bus 00-ff]
10621 20:13:26.696974 <6>[ 13.847119] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10622 20:13:26.707110 <6>[ 13.847124] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10623 20:13:26.713487 <6>[ 13.847162] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10624 20:13:26.720434 <6>[ 13.847188] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10625 20:13:26.723682 <6>[ 13.847272] pci 0000:00:00.0: supports D1 D2
10626 20:13:26.730067 <6>[ 13.847276] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10627 20:13:26.740164 <6>[ 13.848939] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10628 20:13:26.746613 <6>[ 13.849044] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10629 20:13:26.753716 <6>[ 13.849074] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10630 20:13:26.759681 <6>[ 13.849094] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10631 20:13:26.769512 <6>[ 13.849112] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10632 20:13:26.773028 <6>[ 13.849225] pci 0000:01:00.0: supports D1 D2
10633 20:13:26.780035 <6>[ 13.849228] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10634 20:13:26.785954 <6>[ 13.852579] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10635 20:13:26.796018 <6>[ 13.852624] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10636 20:13:26.802878 <6>[ 13.852632] remoteproc remoteproc0: remote processor scp is now up
10637 20:13:26.809424 <6>[ 13.857827] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10638 20:13:26.815873 <6>[ 13.857901] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10639 20:13:26.825615 <6>[ 13.857908] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10640 20:13:26.832777 <6>[ 13.857923] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10641 20:13:26.839180 <6>[ 13.857939] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10642 20:13:26.848945 <6>[ 13.857955] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10643 20:13:26.852263 <6>[ 13.857971] pci 0000:00:00.0: PCI bridge to [bus 01]
10644 20:13:26.862989 <6>[ 13.857979] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10645 20:13:26.868644 <6>[ 13.858141] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10646 20:13:26.875217 <6>[ 13.858205] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10647 20:13:26.881925 <6>[ 13.859174] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10648 20:13:26.888505 <6>[ 13.859625] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10649 20:13:26.898617 <6>[ 13.864746] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10650 20:13:26.905165 <6>[ 13.868433] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10651 20:13:26.914808 <6>[ 13.870686] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10652 20:13:26.924748 <6>[ 13.879006] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10653 20:13:26.934681 <6>[ 13.879319] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10654 20:13:26.941309 <4>[ 13.893125] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10655 20:13:26.951785 <4>[ 13.893156] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10656 20:13:26.954771 <6>[ 13.900857] Bluetooth: Core ver 2.22
10657 20:13:26.961182 <6>[ 13.901057] NET: Registered PF_BLUETOOTH protocol family
10658 20:13:26.968003 <6>[ 13.901066] Bluetooth: HCI device and connection manager initialized
10659 20:13:26.971147 <6>[ 13.901119] Bluetooth: HCI socket layer initialized
10660 20:13:26.977556 <6>[ 13.901135] Bluetooth: L2CAP socket layer initialized
10661 20:13:26.981154 <6>[ 13.901158] Bluetooth: SCO socket layer initialized
10662 20:13:26.990681 <5>[ 13.909885] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10663 20:13:26.997373 <5>[ 13.921546] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10664 20:13:27.003723 <5>[ 13.921789] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10665 20:13:27.014046 <4>[ 13.921853] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10666 20:13:27.020554 <6>[ 13.921862] cfg80211: failed to load regulatory.db
10667 20:13:27.027148 <6>[ 13.935180] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10668 20:13:27.037047 <6>[ 13.936627] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10669 20:13:27.043479 <6>[ 13.936752] usbcore: registered new interface driver uvcvideo
10670 20:13:27.050411 <6>[ 13.941853] r8152 2-1.3:1.0 eth0: v1.12.13
10671 20:13:27.053173 <6>[ 13.941917] usbcore: registered new interface driver r8152
10672 20:13:27.060443 <6>[ 13.961077] usbcore: registered new interface driver cdc_ether
10673 20:13:27.066736 <6>[ 13.961734] usbcore: registered new interface driver btusb
10674 20:13:27.076672 <4>[ 13.962228] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10675 20:13:27.083228 Begin: Loading e<3>[ 13.962238] Bluetooth: hci0: Failed to load firmware file (-2)
10676 20:13:27.089591 <3>[ 13.962240] Bluetooth: hci0: Failed to set up firmware (-2)
10677 20:13:27.099824 <4>[ 13.962243] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10678 20:13:27.106253 <6>[ 13.982935] usbcore: registered new interface driver r8153_ecm
10679 20:13:27.112706 <6>[ 13.983773] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10680 20:13:27.119719 <6>[ 13.998637] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10681 20:13:27.126592 <6>[ 14.031313] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10682 20:13:27.132466 <6>[ 14.031416] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10683 20:13:27.139010 <6>[ 14.049897] mt7921e 0000:01:00.0: ASIC revision: 79610010
10684 20:13:27.145763 <6>[ 14.144528] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10685 20:13:27.148996 <6>[ 14.144528]
10686 20:13:27.159305 <6>[ 14.406349] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10687 20:13:27.159467 ssential drivers ... done.
10688 20:13:27.165496 Begin: Running /scripts/init-premount ... done.
10689 20:13:27.172816 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10690 20:13:27.178752 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10691 20:13:27.185396 Device /sys/class/net/enx002432307c7b found
10692 20:13:27.185562 done.
10693 20:13:27.192123 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10694 20:13:27.935862 <6>[ 15.243715] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10695 20:13:28.213959 IP-Config: no response after 2 secs - giving up
10696 20:13:28.239893 <6>[ 15.549453] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10697 20:13:28.263185 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10698 20:13:28.283800 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10699 20:13:29.026055 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10700 20:13:29.032389 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10701 20:13:29.042381 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10702 20:13:29.048595 host : mt8192-asurada-spherion-r0-cbg-2
10703 20:13:29.055352 domain : lava-rack
10704 20:13:29.058354 rootserver: 192.168.201.1 rootpath:
10705 20:13:29.058474 filename :
10706 20:13:29.154312 done.
10707 20:13:29.162159 Begin: Running /scripts/nfs-bottom ... done.
10708 20:13:29.181168 Begin: Running /scripts/init-bottom ... done.
10709 20:13:30.401495 <6>[ 17.707693] NET: Registered PF_INET6 protocol family
10710 20:13:30.404831 <6>[ 17.711715] Segment Routing with IPv6
10711 20:13:30.411547 <6>[ 17.711763] In-situ OAM (IOAM) with IPv6
10712 20:13:30.547565 <30>[ 17.834967] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10713 20:13:30.550641 <30>[ 17.835950] systemd[1]: Detected architecture arm64.
10714 20:13:30.550735
10715 20:13:30.557346 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10716 20:13:30.557428
10717 20:13:30.575492 <30>[ 17.884420] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10718 20:13:31.442592 <30>[ 18.747734] systemd[1]: Queued start job for default target Graphical Interface.
10719 20:13:31.470378 [[0;32m OK [<30>[ 18.776373] systemd[1]: Created slice system-getty.slice.
10720 20:13:31.473005 0m] Created slice [0;1;39msystem-getty.slice[0m.
10721 20:13:31.492485 [[0;32m OK [0m] Created slic<30>[ 18.799293] systemd[1]: Created slice system-modprobe.slice.
10722 20:13:31.495974 e [0;1;39msystem-modprobe.slice[0m.
10723 20:13:31.516513 [[0;32m OK [0m] Created slic<30>[ 18.823228] systemd[1]: Created slice system-serial\x2dgetty.slice.
10724 20:13:31.522798 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10725 20:13:31.541241 [[0;32m OK [0m] Created slic<30>[ 18.847735] systemd[1]: Created slice User and Session Slice.
10726 20:13:31.544687 e [0;1;39mUser and Session Slice[0m.
10727 20:13:31.567574 [[0;32m OK [0m] Started [0;<30>[ 18.870793] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10728 20:13:31.570646 1;39mDispatch Password …ts to Console Directory Watch[0m.
10729 20:13:31.595040 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.898188] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10730 20:13:31.597941 sword R…uests to Wall Directory Watch[0m.
10731 20:13:31.621930 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.922136] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10732 20:13:31.628765 <30>[ 18.922313] systemd[1]: Reached target Local Encrypted Volumes.
10733 20:13:31.631682 l Encrypted Volumes[0m.
10734 20:13:31.651403 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.958302] systemd[1]: Reached target Paths.
10735 20:13:31.651540 s[0m.
10736 20:13:31.674430 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.977991] systemd[1]: Reached target Remote File Systems.
10737 20:13:31.674589 te File Systems[0m.
10738 20:13:31.695261 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.001957] systemd[1]: Reached target Slices.
10739 20:13:31.695420 es[0m.
10740 20:13:31.715159 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.021989] systemd[1]: Reached target Swap.
10741 20:13:31.715304 [0m.
10742 20:13:31.738843 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.042408] systemd[1]: Listening on initctl Compatibility Named Pipe.
10743 20:13:31.742218 l Compatibility Named Pipe[0m.
10744 20:13:31.752015 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.058538] systemd[1]: Listening on Journal Audit Socket.
10745 20:13:31.755655 l Audit Socket[0m.
10746 20:13:31.776590 [[0;32m OK [0m] Listening on<30>[ 19.083294] systemd[1]: Listening on Journal Socket (/dev/log).
10747 20:13:31.779643 [0;1;39mJournal Socket (/dev/log)[0m.
10748 20:13:31.800632 [[0;32m OK [0m] Listening on<30>[ 19.107311] systemd[1]: Listening on Journal Socket.
10749 20:13:31.803817 [0;1;39mJournal Socket[0m.
10750 20:13:31.820806 [[0;32m OK [0m] Listening on<30>[ 19.127777] systemd[1]: Listening on Network Service Netlink Socket.
10751 20:13:31.827326 [0;1;39mNetwork Service Netlink Socket[0m.
10752 20:13:31.847234 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.153949] systemd[1]: Listening on udev Control Socket.
10753 20:13:31.850488 ontrol Socket[0m.
10754 20:13:31.867499 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.174464] systemd[1]: Listening on udev Kernel Socket.
10755 20:13:31.870858 ernel Socket[0m.
10756 20:13:31.934579 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.238161] systemd[1]: Mounting Huge Pages File System...
10757 20:13:31.934795 m[0m...
10758 20:13:31.958284 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.261787] systemd[1]: Mounting POSIX Message Queue File System...
10759 20:13:31.958463 ile System[0m...
10760 20:13:31.987146 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.290573] systemd[1]: Mounting Kernel Debug File System...
10761 20:13:31.987311 tem[0m...
10762 20:13:32.006598 <30>[ 19.310212] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10763 20:13:32.016959 <30>[ 19.320529] systemd[1]: Starting Create list of static device nodes for the current kernel...
10764 20:13:32.023293 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10765 20:13:32.048316 Starting [0;1;39mLoad <30>[ 19.355304] systemd[1]: Starting Load Kernel Module configfs...
10766 20:13:32.052731 Kernel Module configfs[0m...
10767 20:13:32.110814 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.414556] systemd[1]: Starting Load Kernel Module drm...
10768 20:13:32.110956 m[0m...
10769 20:13:32.137174 Starting [0;1;39mLoad <30>[ 19.442968] systemd[1]: Starting Load Kernel Module fuse...
10770 20:13:32.139369 Kernel Module fuse[0m...
10771 20:13:32.171394 <6>[ 19.481238] fuse: init (API version 7.37)
10772 20:13:32.181245 <30>[ 19.481978] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10773 20:13:32.231848 Starting [0;1;39mJournal Service[0m..<30>[ 19.538790] systemd[1]: Starting Journal Service...
10774 20:13:32.231980 .
10775 20:13:32.259433 Starting [0;1;39mLoad Kernel Modules[<30>[ 19.566366] systemd[1]: Starting Load Kernel Modules...
10776 20:13:32.262893 0m...
10777 20:13:32.282964 Startin<30>[ 19.589301] systemd[1]: Starting Remount Root and Kernel File Systems...
10778 20:13:32.289354 g [0;1;39mRemount Root and Kernel File Systems[0m...
10779 20:13:32.340518 Starting [0;1;39mColdp<30>[ 19.647098] systemd[1]: Starting Coldplug All udev Devices...
10780 20:13:32.344737 lug All udev Devices[0m...
10781 20:13:32.372169 [[0;32m OK [0m] Mounted [0;<30>[ 19.678968] systemd[1]: Mounted Huge Pages File System.
10782 20:13:32.375194 1;39mHuge Pages File System[0m.
10783 20:13:32.399248 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 19.702777] systemd[1]: Mounted POSIX Message Queue File System.
10784 20:13:32.399423 ge Queue File System[0m.
10785 20:13:32.419238 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.726388] systemd[1]: Mounted Kernel Debug File System.
10786 20:13:32.423105 g File System[0m.
10787 20:13:32.449006 [[0;32m OK [<30>[ 19.752466] systemd[1]: Finished Create list of static device nodes for the current kernel.
10788 20:13:32.452633 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10789 20:13:32.463104 <3>[ 19.766133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 20:13:32.474748 [[0;32m OK [<30>[ 19.779862] systemd[1]: modprobe@configfs.service: Succeeded.
10791 20:13:32.481024 0m] Finished [0<30>[ 19.780716] systemd[1]: Finished Load Kernel Module configfs.
10792 20:13:32.490835 <3>[ 19.787591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10793 20:13:32.494287 ;1;39mLoad Kernel Module configfs[0m.
10794 20:13:32.513460 [[0;32m OK [0m] Finished [0<30>[ 19.818939] systemd[1]: modprobe@drm.service: Succeeded.
10795 20:13:32.520294 ;1;39mLoad Kerne<30>[ 19.819604] systemd[1]: Finished Load Kernel Module drm.
10796 20:13:32.530408 l Module drm[0m<3>[ 19.830772] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10797 20:13:32.530519 .
10798 20:13:32.549732 [[0;32m OK [0m] Finished [0<30>[ 19.855077] systemd[1]: modprobe@fuse.service: Succeeded.
10799 20:13:32.556404 ;1;39mLoad Kerne<30>[ 19.856033] systemd[1]: Finished Load Kernel Module fuse.
10800 20:13:32.566876 <3>[ 19.862686] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 20:13:32.567035 l Module fuse[0m.
10802 20:13:32.583100 <3>[ 19.889400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 20:13:32.593185 [[0;32m OK [0m] Finished [0<30>[ 19.900054] systemd[1]: Finished Load Kernel Modules.
10804 20:13:32.596314 ;1;39mLoad Kernel Modules[0m.
10805 20:13:32.610594 <3>[ 19.916578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 20:13:32.621753 [[0;32m OK [0m] Finished [0<30>[ 19.928148] systemd[1]: Finished Remount Root and Kernel File Systems.
10807 20:13:32.628510 ;1;39mRemount Root and Kernel File Systems[0m.
10808 20:13:32.638518 <3>[ 19.942105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10809 20:13:32.658701 <3>[ 19.963991] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 20:13:32.678784 <3>[ 19.984427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 20:13:32.689201 Mounting [0;1;39mFUSE Control File Sys<30>[ 19.991356] systemd[1]: Mounting FUSE Control File System...
10812 20:13:32.689388 tem[0m...
10813 20:13:32.699597 <3>[ 20.005594] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 20:13:32.714969 Mounting [0;1;39mKernel Configuration <30>[ 20.017768] systemd[1]: Mounting Kernel Configuration File System...
10815 20:13:32.715151 File System[0m...
10816 20:13:32.742492 <30>[ 20.047486] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10817 20:13:32.752734 <30>[ 20.047707] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10818 20:13:32.758923 Startin<30>[ 20.050736] systemd[1]: Starting Load/Save Random Seed...
10819 20:13:32.762543 g [0;1;39mLoad/Save Random Seed[0m...
10820 20:13:32.787396 Starting [0;1;39mApply Kernel Variable<30>[ 20.093950] systemd[1]: Starting Apply Kernel Variables...
10821 20:13:32.791174 s[0m...
10822 20:13:32.816522 Starting [0;1;39mCreate System Users[<30>[ 20.122602] systemd[1]: Starting Create System Users...
10823 20:13:32.816716 0m...
10824 20:13:32.832677 <4>[ 20.132126] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10825 20:13:32.842719 <3>[ 20.132136] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10826 20:13:32.852505 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.158995] systemd[1]: Started Journal Service.
10827 20:13:32.852696 vice[0m.
10828 20:13:32.873517 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10829 20:13:32.891647 See 'systemctl status systemd-udev-trigger.service' for details.
10830 20:13:32.908706 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10831 20:13:32.928576 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10832 20:13:32.945099 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10833 20:13:32.964573 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10834 20:13:32.981297 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10835 20:13:33.024486 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10836 20:13:33.047832 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10837 20:13:33.106380 <46>[ 20.411904] systemd-journald[308]: Received client request to flush runtime journal.
10838 20:13:33.153269 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10839 20:13:33.172143 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10840 20:13:33.187411 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10841 20:13:33.247941 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10842 20:13:34.508460 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10843 20:13:34.543909 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10844 20:13:34.603751 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10845 20:13:34.644212 Starting [0;1;39mNetwork Service[0m...
10846 20:13:34.947691 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10847 20:13:34.968254 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10848 20:13:35.023490 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10849 20:13:35.321861 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10850 20:13:35.339321 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10851 20:13:35.369189 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10852 20:13:35.408168 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10853 20:13:35.424251 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10854 20:13:35.463912 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10855 20:13:35.479703 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10856 20:13:35.544011 Starting [0;1;39mNetwork Name Resolution[0m...
10857 20:13:35.573158 Starting [0;1;39mNetwork Time Synchronization[0m...
10858 20:13:35.594974 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10859 20:13:35.655307 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10860 20:13:35.781604 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10861 20:13:35.801314 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10862 20:13:35.819627 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10863 20:13:35.837261 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10864 20:13:35.852616 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10865 20:13:35.986274 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10866 20:13:36.016458 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10867 20:13:36.045247 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10868 20:13:36.072273 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10869 20:13:36.083350 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10870 20:13:36.349359 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10871 20:13:36.363025 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10872 20:13:36.379615 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10873 20:13:36.436827 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10874 20:13:36.836594 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10875 20:13:37.252760 Starting [0;1;39mUser Login Management[0m...
10876 20:13:37.272196 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10877 20:13:37.292670 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10878 20:13:37.310981 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10879 20:13:37.364799 Starting [0;1;39mPermit User Sessions[0m...
10880 20:13:37.423703 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10881 20:13:37.444762 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10882 20:13:37.500304 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10883 20:13:37.518313 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10884 20:13:37.535930 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10885 20:13:37.595115 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10886 20:13:37.613151 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10887 20:13:37.632323 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10888 20:13:37.696503 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10889 20:13:37.742536 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10890 20:13:37.847846
10891 20:13:37.847978
10892 20:13:37.851210 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10893 20:13:37.851318
10894 20:13:37.854666 debian-bullseye-arm64 login: root (automatic login)
10895 20:13:37.854747
10896 20:13:37.854810
10897 20:13:38.228988 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10898 20:13:38.229131
10899 20:13:38.235419 The programs included with the Debian GNU/Linux system are free software;
10900 20:13:38.242483 the exact distribution terms for each program are described in the
10901 20:13:38.245870 individual files in /usr/share/doc/*/copyright.
10902 20:13:38.245951
10903 20:13:38.252189 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10904 20:13:38.255430 permitted by applicable law.
10905 20:13:39.212336 Matched prompt #10: / #
10907 20:13:39.212660 Setting prompt string to ['/ #']
10908 20:13:39.212782 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10910 20:13:39.213031 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10911 20:13:39.213118 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10912 20:13:39.213187 Setting prompt string to ['/ #']
10913 20:13:39.213246 Forcing a shell prompt, looking for ['/ #']
10915 20:13:39.263422 / #
10916 20:13:39.263611 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10917 20:13:39.263765 Waiting using forced prompt support (timeout 00:02:30)
10918 20:13:39.268330
10919 20:13:39.268678 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10920 20:13:39.268814 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
10922 20:13:39.369181 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit'
10923 20:13:39.374628 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928085/extract-nfsrootfs-p07r8qit'
10925 20:13:39.475182 / # export NFS_SERVER_IP='192.168.201.1'
10926 20:13:39.480841 export NFS_SERVER_IP='192.168.201.1'
10927 20:13:39.481214 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10928 20:13:39.481359 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
10929 20:13:39.481493 end: 2 depthcharge-action (duration 00:01:43) [common]
10930 20:13:39.481635 start: 3 lava-test-retry (timeout 00:07:27) [common]
10931 20:13:39.481769 start: 3.1 lava-test-shell (timeout 00:07:27) [common]
10932 20:13:39.481884 Using namespace: common
10934 20:13:39.582247 / # #
10935 20:13:39.582443 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10936 20:13:39.587421 #
10937 20:13:39.587735 Using /lava-12928085
10939 20:13:39.688097 / # export SHELL=/bin/bash
10940 20:13:39.693409 export SHELL=/bin/bash
10942 20:13:39.793955 / # . /lava-12928085/environment
10943 20:13:39.799207 . /lava-12928085/environment
10945 20:13:39.906211 / # /lava-12928085/bin/lava-test-runner /lava-12928085/0
10946 20:13:39.906382 Test shell timeout: 10s (minimum of the action and connection timeout)
10947 20:13:39.911767 /lava-12928085/bin/lava-test-runner /lava-12928085/0
10948 20:13:40.228560 + export TESTRUN_ID=0_timesync-off
10949 20:13:40.231957 + TESTRUN_ID=0_timesync-off
10950 20:13:40.235553 + cd /lava-12928085/0/tests/0_timesync-off
10951 20:13:40.238641 ++ cat uuid
10952 20:13:40.245025 + UUID=12928085_1.6.2.3.1
10953 20:13:40.245141 + set +x
10954 20:13:40.251699 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12928085_1.6.2.3.1>
10955 20:13:40.252000 Received signal: <STARTRUN> 0_timesync-off 12928085_1.6.2.3.1
10956 20:13:40.252115 Starting test lava.0_timesync-off (12928085_1.6.2.3.1)
10957 20:13:40.252239 Skipping test definition patterns.
10958 20:13:40.254634 + systemctl stop systemd-timesyncd
10959 20:13:40.313554 + set +x
10960 20:13:40.316252 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12928085_1.6.2.3.1>
10961 20:13:40.316548 Received signal: <ENDRUN> 0_timesync-off 12928085_1.6.2.3.1
10962 20:13:40.316682 Ending use of test pattern.
10963 20:13:40.316791 Ending test lava.0_timesync-off (12928085_1.6.2.3.1), duration 0.06
10965 20:13:40.399203 + export TESTRUN_ID=1_kselftest-tpm2
10966 20:13:40.401552 + TESTRUN_ID=1_kselftest-tpm2
10967 20:13:40.408297 + cd /lava-12928085/0/tests/1_kselftest-tpm2
10968 20:13:40.408418 ++ cat uuid
10969 20:13:40.416191 + UUID=12928085_1.6.2.3.5
10970 20:13:40.416307 + set +x
10971 20:13:40.422484 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12928085_1.6.2.3.5>
10972 20:13:40.422781 Received signal: <STARTRUN> 1_kselftest-tpm2 12928085_1.6.2.3.5
10973 20:13:40.422887 Starting test lava.1_kselftest-tpm2 (12928085_1.6.2.3.5)
10974 20:13:40.423008 Skipping test definition patterns.
10975 20:13:40.426057 + cd ./automated/linux/kselftest/
10976 20:13:40.456249 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10977 20:13:40.500560 INFO: install_deps skipped
10978 20:13:40.627214 --2024-03-03 20:13:40-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10979 20:13:40.663062 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10980 20:13:40.796247 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10981 20:13:40.931677 HTTP request sent, awaiting response... 200 OK
10982 20:13:40.935104 Length: 1746752 (1.7M) [application/octet-stream]
10983 20:13:40.938488 Saving to: 'kselftest.tar.xz'
10984 20:13:40.938640
10985 20:13:40.938786
10986 20:13:41.199379 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10987 20:13:41.466998 kselftest.tar.xz 2%[ ] 43.57K 164KB/s
10988 20:13:41.783343 kselftest.tar.xz 12%[=> ] 216.08K 405KB/s
10989 20:13:42.001968 kselftest.tar.xz 48%[========> ] 822.71K 969KB/s
10990 20:13:42.008311 kselftest.tar.xz 95%[==================> ] 1.59M 1.49MB/s
10991 20:13:42.015067 kselftest.tar.xz 100%[===================>] 1.67M 1.56MB/s in 1.1s
10992 20:13:42.015192
10993 20:13:42.164864 2024-03-03 20:13:42 (1.56 MB/s) - 'kselftest.tar.xz' saved [1746752/1746752]
10994 20:13:42.165010
10995 20:13:47.078523 skiplist:
10996 20:13:47.081296 ========================================
10997 20:13:47.084947 ========================================
10998 20:13:47.138912 tpm2:test_smoke.sh
10999 20:13:47.142291 tpm2:test_space.sh
11000 20:13:47.160853 ============== Tests to run ===============
11001 20:13:47.164423 tpm2:test_smoke.sh
11002 20:13:47.164568 tpm2:test_space.sh
11003 20:13:47.170373 ===========End Tests to run ===============
11004 20:13:47.174451 shardfile-tpm2 pass
11005 20:13:47.294282 <12>[ 34.602643] kselftest: Running tests in tpm2
11006 20:13:47.302920 TAP version 13
11007 20:13:47.317376 1..2
11008 20:13:47.351132 # selftests: tpm2: test_smoke.sh
11009 20:13:48.817130 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11010 20:13:48.819877 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11011 20:13:48.826928 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11012 20:13:48.830076 # Traceback (most recent call last):
11013 20:13:48.839838 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11014 20:13:48.843274 # if self.tpm:
11015 20:13:48.846280 # AttributeError: 'Client' object has no attribute 'tpm'
11016 20:13:48.853380 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11017 20:13:48.856717 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11018 20:13:48.859498 # Traceback (most recent call last):
11019 20:13:48.869413 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11020 20:13:48.872783 # if self.tpm:
11021 20:13:48.876082 # AttributeError: 'Client' object has no attribute 'tpm'
11022 20:13:48.882616 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11023 20:13:48.889628 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11024 20:13:48.892857 # Traceback (most recent call last):
11025 20:13:48.902575 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11026 20:13:48.902733 # if self.tpm:
11027 20:13:48.909680 # AttributeError: 'Client' object has no attribute 'tpm'
11028 20:13:48.912526 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11029 20:13:48.919195 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11030 20:13:48.922670 # Traceback (most recent call last):
11031 20:13:48.932947 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11032 20:13:48.935967 # if self.tpm:
11033 20:13:48.939338 # AttributeError: 'Client' object has no attribute 'tpm'
11034 20:13:48.945450 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11035 20:13:48.949126 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11036 20:13:48.953008 # Traceback (most recent call last):
11037 20:13:48.961968 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11038 20:13:48.965545 # if self.tpm:
11039 20:13:48.968562 # AttributeError: 'Client' object has no attribute 'tpm'
11040 20:13:48.975488 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11041 20:13:48.981847 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11042 20:13:48.985826 # Traceback (most recent call last):
11043 20:13:48.995583 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11044 20:13:48.995745 # if self.tpm:
11045 20:13:49.001578 # AttributeError: 'Client' object has no attribute 'tpm'
11046 20:13:49.005711 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11047 20:13:49.012108 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11048 20:13:49.015020 # Traceback (most recent call last):
11049 20:13:49.024833 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11050 20:13:49.028066 # if self.tpm:
11051 20:13:49.031346 # AttributeError: 'Client' object has no attribute 'tpm'
11052 20:13:49.038462 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11053 20:13:49.045134 # Exception ignored in: <function Client.__del__ at 0xffffaa2a1d30>
11054 20:13:49.048617 # Traceback (most recent call last):
11055 20:13:49.057959 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11056 20:13:49.058131 # if self.tpm:
11057 20:13:49.064589 # AttributeError: 'Client' object has no attribute 'tpm'
11058 20:13:49.064796 #
11059 20:13:49.070856 # ======================================================================
11060 20:13:49.077706 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11061 20:13:49.081037 # ----------------------------------------------------------------------
11062 20:13:49.084296 # Traceback (most recent call last):
11063 20:13:49.097603 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11064 20:13:49.100948 # self.root_key = self.client.create_root_key()
11065 20:13:49.110491 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11066 20:13:49.117350 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11067 20:13:49.125404 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11068 20:13:49.128697 # raise ProtocolError(cc, rc)
11069 20:13:49.135290 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11070 20:13:49.135456 #
11071 20:13:49.142017 # ======================================================================
11072 20:13:49.145684 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11073 20:13:49.152350 # ----------------------------------------------------------------------
11074 20:13:49.155663 # Traceback (most recent call last):
11075 20:13:49.165594 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11076 20:13:49.168727 # self.client = tpm2.Client()
11077 20:13:49.178449 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11078 20:13:49.186047 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11079 20:13:49.188552 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11080 20:13:49.191699 #
11081 20:13:49.198592 # ======================================================================
11082 20:13:49.201810 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11083 20:13:49.208326 # ----------------------------------------------------------------------
11084 20:13:49.211611 # Traceback (most recent call last):
11085 20:13:49.221292 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11086 20:13:49.225131 # self.client = tpm2.Client()
11087 20:13:49.234639 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11088 20:13:49.238118 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11089 20:13:49.244438 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11090 20:13:49.244658 #
11091 20:13:49.251675 # ======================================================================
11092 20:13:49.254368 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11093 20:13:49.261100 # ----------------------------------------------------------------------
11094 20:13:49.264300 # Traceback (most recent call last):
11095 20:13:49.274919 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11096 20:13:49.278033 # self.client = tpm2.Client()
11097 20:13:49.287800 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11098 20:13:49.294077 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11099 20:13:49.297391 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11100 20:13:49.297521 #
11101 20:13:49.304470 # ======================================================================
11102 20:13:49.310842 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11103 20:13:49.317487 # ----------------------------------------------------------------------
11104 20:13:49.320483 # Traceback (most recent call last):
11105 20:13:49.331089 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11106 20:13:49.334155 # self.client = tpm2.Client()
11107 20:13:49.343660 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11108 20:13:49.346785 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11109 20:13:49.353775 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11110 20:13:49.353990 #
11111 20:13:49.360296 # ======================================================================
11112 20:13:49.363557 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11113 20:13:49.370227 # ----------------------------------------------------------------------
11114 20:13:49.373543 # Traceback (most recent call last):
11115 20:13:49.383171 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11116 20:13:49.386416 # self.client = tpm2.Client()
11117 20:13:49.396304 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11118 20:13:49.403483 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11119 20:13:49.406410 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11120 20:13:49.406584 #
11121 20:13:49.413040 # ======================================================================
11122 20:13:49.420047 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11123 20:13:49.426289 # ----------------------------------------------------------------------
11124 20:13:49.429979 # Traceback (most recent call last):
11125 20:13:49.439495 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11126 20:13:49.442792 # self.client = tpm2.Client()
11127 20:13:49.452775 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11128 20:13:49.456019 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11129 20:13:49.462792 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11130 20:13:49.463001 #
11131 20:13:49.467633 # ======================================================================
11132 20:13:49.474869 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11133 20:13:49.478620 # ----------------------------------------------------------------------
11134 20:13:49.482438 # Traceback (most recent call last):
11135 20:13:49.494506 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11136 20:13:49.498544 # self.client = tpm2.Client()
11137 20:13:49.506859 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11138 20:13:49.510132 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11139 20:13:49.517057 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11140 20:13:49.517248 #
11141 20:13:49.524183 # ======================================================================
11142 20:13:49.527792 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11143 20:13:49.534610 # ----------------------------------------------------------------------
11144 20:13:49.537584 # Traceback (most recent call last):
11145 20:13:49.547839 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11146 20:13:49.551479 # self.client = tpm2.Client()
11147 20:13:49.560737 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11148 20:13:49.567827 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11149 20:13:49.570885 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11150 20:13:49.571032 #
11151 20:13:49.577308 # ----------------------------------------------------------------------
11152 20:13:49.581529 # Ran 9 tests in 0.045s
11153 20:13:49.581690 #
11154 20:13:49.583897 # FAILED (errors=9)
11155 20:13:49.587463 # test_async (tpm2_tests.AsyncTest) ... ok
11156 20:13:49.590505 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11157 20:13:49.590647 #
11158 20:13:49.596914 # ----------------------------------------------------------------------
11159 20:13:49.601175 # Ran 2 tests in 0.040s
11160 20:13:49.601337 #
11161 20:13:49.601439 # OK
11162 20:13:49.605017 ok 1 selftests: tpm2: test_smoke.sh
11163 20:13:49.606911 # selftests: tpm2: test_space.sh
11164 20:13:49.613896 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11165 20:13:49.616928 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11166 20:13:49.620693 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11167 20:13:49.626795 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11168 20:13:49.626980 #
11169 20:13:49.633700 # ======================================================================
11170 20:13:49.637078 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11171 20:13:49.643742 # ----------------------------------------------------------------------
11172 20:13:49.646842 # Traceback (most recent call last):
11173 20:13:49.660324 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11174 20:13:49.663325 # root1 = space1.create_root_key()
11175 20:13:49.673611 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11176 20:13:49.676636 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11177 20:13:49.686528 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11178 20:13:49.690494 # raise ProtocolError(cc, rc)
11179 20:13:49.696569 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11180 20:13:49.696748 #
11181 20:13:49.703218 # ======================================================================
11182 20:13:49.710581 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11183 20:13:49.713391 # ----------------------------------------------------------------------
11184 20:13:49.716544 # Traceback (most recent call last):
11185 20:13:49.729778 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11186 20:13:49.733213 # space1.create_root_key()
11187 20:13:49.742821 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11188 20:13:49.746419 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11189 20:13:49.756545 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11190 20:13:49.759342 # raise ProtocolError(cc, rc)
11191 20:13:49.766286 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11192 20:13:49.766478 #
11193 20:13:49.773004 # ======================================================================
11194 20:13:49.779695 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11195 20:13:49.782940 # ----------------------------------------------------------------------
11196 20:13:49.786697 # Traceback (most recent call last):
11197 20:13:49.799118 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11198 20:13:49.802778 # root1 = space1.create_root_key()
11199 20:13:49.813523 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11200 20:13:49.819221 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11201 20:13:49.828971 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11202 20:13:49.832426 # raise ProtocolError(cc, rc)
11203 20:13:49.835506 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11204 20:13:49.839285 #
11205 20:13:49.842684 # ======================================================================
11206 20:13:49.848580 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11207 20:13:49.855562 # ----------------------------------------------------------------------
11208 20:13:49.858585 # Traceback (most recent call last):
11209 20:13:49.868697 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11210 20:13:49.871799 # root1 = space1.create_root_key()
11211 20:13:49.885345 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11212 20:13:49.888932 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11213 20:13:49.898242 # File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11214 20:13:49.901932 # raise ProtocolError(cc, rc)
11215 20:13:49.908444 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11216 20:13:49.908635 #
11217 20:13:49.915084 # ----------------------------------------------------------------------
11218 20:13:49.918257 # Ran 4 tests in 0.082s
11219 20:13:49.918412 #
11220 20:13:49.918541 # FAILED (errors=4)
11221 20:13:49.924784 not ok 2 selftests: tpm2: test_space.sh # exit=1
11222 20:13:50.002002 Traceback (most recent call last):
11223 20:13:50.011876 File "/lava-12928085/0/tests/1_kselftest-tpm2/automated/linux/kselftest/./parse-output.py", line 4, in <module>
11224 20:13:50.015080 from tap import parser
11225 20:13:50.018204 ModuleNotFoundError: No module named 'tap'
11226 20:13:50.025241 + ../../utils/send-to-lava.sh ./output/result.txt
11227 20:13:50.101828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11228 20:13:50.102027 + set +x
11229 20:13:50.102346 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11231 20:13:50.109712 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12928085_1.6.2.3.5>
11232 20:13:50.110096 Received signal: <ENDRUN> 1_kselftest-tpm2 12928085_1.6.2.3.5
11233 20:13:50.110220 Ending use of test pattern.
11234 20:13:50.110315 Ending test lava.1_kselftest-tpm2 (12928085_1.6.2.3.5), duration 9.69
11236 20:13:50.112021 <LAVA_TEST_RUNNER EXIT>
11237 20:13:50.112306 ok: lava_test_shell seems to have completed
11238 20:13:50.112444 shardfile-tpm2: pass
11239 20:13:50.112570 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11240 20:13:50.112689 end: 3 lava-test-retry (duration 00:00:11) [common]
11241 20:13:50.112817 start: 4 finalize (timeout 00:07:16) [common]
11242 20:13:50.112946 start: 4.1 power-off (timeout 00:00:30) [common]
11243 20:13:50.113184 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11244 20:13:50.195836 >> Command sent successfully.
11245 20:13:50.198434 Returned 0 in 0 seconds
11246 20:13:50.298912 end: 4.1 power-off (duration 00:00:00) [common]
11248 20:13:50.299428 start: 4.2 read-feedback (timeout 00:07:16) [common]
11249 20:13:50.299817 Listened to connection for namespace 'common' for up to 1s
11250 20:13:51.300720 Finalising connection for namespace 'common'
11251 20:13:51.300960 Disconnecting from shell: Finalise
11252 20:13:51.301085 / #
11253 20:13:51.401471 end: 4.2 read-feedback (duration 00:00:01) [common]
11254 20:13:51.401708 end: 4 finalize (duration 00:00:01) [common]
11255 20:13:51.401878 Cleaning after the job
11256 20:13:51.402016 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/ramdisk
11257 20:13:51.405836 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/kernel
11258 20:13:51.423489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/dtb
11259 20:13:51.423807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/nfsrootfs
11260 20:13:51.532626 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928085/tftp-deploy-w2rggnd5/modules
11261 20:13:51.540604 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928085
11262 20:13:52.239220 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928085
11263 20:13:52.239453 Job finished correctly