Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 30
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 12
1 20:14:35.516038 lava-dispatcher, installed at version: 2024.01
2 20:14:35.516258 start: 0 validate
3 20:14:35.516388 Start time: 2024-03-03 20:14:35.516380+00:00 (UTC)
4 20:14:35.516509 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:14:35.516637 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 20:14:35.785882 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:14:35.786043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:14:36.052325 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:14:36.052484 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:14:36.317946 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:14:36.318119 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:14:36.585656 validate duration: 1.07
14 20:14:36.585959 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:14:36.586058 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:14:36.586142 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:14:36.586264 Not decompressing ramdisk as can be used compressed.
18 20:14:36.586346 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 20:14:36.586408 saving as /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/ramdisk/rootfs.cpio.gz
20 20:14:36.586476 total size: 26246609 (25 MB)
21 20:14:36.587546 progress 0 % (0 MB)
22 20:14:36.594928 progress 5 % (1 MB)
23 20:14:36.601784 progress 10 % (2 MB)
24 20:14:36.608588 progress 15 % (3 MB)
25 20:14:36.615434 progress 20 % (5 MB)
26 20:14:36.622221 progress 25 % (6 MB)
27 20:14:36.629063 progress 30 % (7 MB)
28 20:14:36.635906 progress 35 % (8 MB)
29 20:14:36.642732 progress 40 % (10 MB)
30 20:14:36.649588 progress 45 % (11 MB)
31 20:14:36.656544 progress 50 % (12 MB)
32 20:14:36.663459 progress 55 % (13 MB)
33 20:14:36.670241 progress 60 % (15 MB)
34 20:14:36.677216 progress 65 % (16 MB)
35 20:14:36.684140 progress 70 % (17 MB)
36 20:14:36.691167 progress 75 % (18 MB)
37 20:14:36.698067 progress 80 % (20 MB)
38 20:14:36.704987 progress 85 % (21 MB)
39 20:14:36.711654 progress 90 % (22 MB)
40 20:14:36.718308 progress 95 % (23 MB)
41 20:14:36.725049 progress 100 % (25 MB)
42 20:14:36.725310 25 MB downloaded in 0.14 s (180.29 MB/s)
43 20:14:36.725494 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:14:36.725734 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:14:36.725819 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:14:36.725900 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:14:36.726032 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:14:36.726099 saving as /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/kernel/Image
50 20:14:36.726158 total size: 51601920 (49 MB)
51 20:14:36.726221 No compression specified
52 20:14:36.727900 progress 0 % (0 MB)
53 20:14:36.741039 progress 5 % (2 MB)
54 20:14:36.754492 progress 10 % (4 MB)
55 20:14:36.768053 progress 15 % (7 MB)
56 20:14:36.781271 progress 20 % (9 MB)
57 20:14:36.794982 progress 25 % (12 MB)
58 20:14:36.808649 progress 30 % (14 MB)
59 20:14:36.822248 progress 35 % (17 MB)
60 20:14:36.835702 progress 40 % (19 MB)
61 20:14:36.849159 progress 45 % (22 MB)
62 20:14:36.862766 progress 50 % (24 MB)
63 20:14:36.876185 progress 55 % (27 MB)
64 20:14:36.889420 progress 60 % (29 MB)
65 20:14:36.903084 progress 65 % (32 MB)
66 20:14:36.916813 progress 70 % (34 MB)
67 20:14:36.930335 progress 75 % (36 MB)
68 20:14:36.943709 progress 80 % (39 MB)
69 20:14:36.957133 progress 85 % (41 MB)
70 20:14:36.970680 progress 90 % (44 MB)
71 20:14:36.983865 progress 95 % (46 MB)
72 20:14:36.996837 progress 100 % (49 MB)
73 20:14:36.997059 49 MB downloaded in 0.27 s (181.66 MB/s)
74 20:14:36.997209 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:14:36.997433 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:14:36.997524 start: 1.3 download-retry (timeout 00:10:00) [common]
78 20:14:36.997607 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 20:14:36.997747 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:14:36.997824 saving as /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/dtb/mt8192-asurada-spherion-r0.dtb
81 20:14:36.997885 total size: 47278 (0 MB)
82 20:14:36.997946 No compression specified
83 20:14:36.999329 progress 69 % (0 MB)
84 20:14:36.999671 progress 100 % (0 MB)
85 20:14:36.999856 0 MB downloaded in 0.00 s (22.90 MB/s)
86 20:14:37.000024 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:14:37.000372 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:14:37.000483 start: 1.4 download-retry (timeout 00:10:00) [common]
90 20:14:37.000593 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 20:14:37.000734 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:14:37.000827 saving as /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/modules/modules.tar
93 20:14:37.000914 total size: 8632284 (8 MB)
94 20:14:37.001002 Using unxz to decompress xz
95 20:14:37.005302 progress 0 % (0 MB)
96 20:14:37.026674 progress 5 % (0 MB)
97 20:14:37.061693 progress 10 % (0 MB)
98 20:14:37.095063 progress 15 % (1 MB)
99 20:14:37.119120 progress 20 % (1 MB)
100 20:14:37.143617 progress 25 % (2 MB)
101 20:14:37.169682 progress 30 % (2 MB)
102 20:14:37.196092 progress 35 % (2 MB)
103 20:14:37.220772 progress 40 % (3 MB)
104 20:14:37.245062 progress 45 % (3 MB)
105 20:14:37.269738 progress 50 % (4 MB)
106 20:14:37.294486 progress 55 % (4 MB)
107 20:14:37.319473 progress 60 % (4 MB)
108 20:14:37.343809 progress 65 % (5 MB)
109 20:14:37.368786 progress 70 % (5 MB)
110 20:14:37.393841 progress 75 % (6 MB)
111 20:14:37.420258 progress 80 % (6 MB)
112 20:14:37.444938 progress 85 % (7 MB)
113 20:14:37.471195 progress 90 % (7 MB)
114 20:14:37.500660 progress 95 % (7 MB)
115 20:14:37.529583 progress 100 % (8 MB)
116 20:14:37.534983 8 MB downloaded in 0.53 s (15.41 MB/s)
117 20:14:37.535250 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:14:37.535557 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:14:37.535651 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:14:37.535746 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:14:37.535823 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:14:37.535914 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:14:37.536139 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0
125 20:14:37.536273 makedir: /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin
126 20:14:37.536375 makedir: /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/tests
127 20:14:37.536475 makedir: /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/results
128 20:14:37.536592 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-add-keys
129 20:14:37.536736 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-add-sources
130 20:14:37.536865 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-background-process-start
131 20:14:37.536999 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-background-process-stop
132 20:14:37.537142 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-common-functions
133 20:14:37.537306 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-echo-ipv4
134 20:14:37.537436 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-install-packages
135 20:14:37.537561 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-installed-packages
136 20:14:37.537687 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-os-build
137 20:14:37.537811 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-probe-channel
138 20:14:37.537938 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-probe-ip
139 20:14:37.538061 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-target-ip
140 20:14:37.538184 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-target-mac
141 20:14:37.538306 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-target-storage
142 20:14:37.538435 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-case
143 20:14:37.538558 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-event
144 20:14:37.538682 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-feedback
145 20:14:37.538805 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-raise
146 20:14:37.538926 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-reference
147 20:14:37.539048 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-runner
148 20:14:37.539170 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-set
149 20:14:37.539296 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-test-shell
150 20:14:37.539464 Updating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-install-packages (oe)
151 20:14:37.539615 Updating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/bin/lava-installed-packages (oe)
152 20:14:37.539738 Creating /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/environment
153 20:14:37.539836 LAVA metadata
154 20:14:37.539910 - LAVA_JOB_ID=12928147
155 20:14:37.539974 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:14:37.540074 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:14:37.540141 skipped lava-vland-overlay
158 20:14:37.540212 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:14:37.540294 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:14:37.540355 skipped lava-multinode-overlay
161 20:14:37.540425 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:14:37.540507 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:14:37.540580 Loading test definitions
164 20:14:37.540683 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 20:14:37.540758 Using /lava-12928147 at stage 0
166 20:14:37.541075 uuid=12928147_1.5.2.3.1 testdef=None
167 20:14:37.541162 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 20:14:37.541244 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 20:14:37.541760 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 20:14:37.541978 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 20:14:37.542611 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 20:14:37.542842 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 20:14:37.543598 runner path: /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12928147_1.5.2.3.1
176 20:14:37.543758 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 20:14:37.543960 Creating lava-test-runner.conf files
179 20:14:37.544021 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928147/lava-overlay-svmvhot0/lava-12928147/0 for stage 0
180 20:14:37.544108 - 0_v4l2-compliance-mtk-vcodec-enc
181 20:14:37.544204 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 20:14:37.544285 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 20:14:37.551853 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 20:14:37.551967 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 20:14:37.552052 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 20:14:37.552135 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 20:14:37.552219 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 20:14:38.273344 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 20:14:38.273729 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 20:14:38.273843 extracting modules file /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928147/extract-overlay-ramdisk-6hkjqwsm/ramdisk
191 20:14:38.504949 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 20:14:38.505126 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 20:14:38.505225 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928147/compress-overlay-ufu_rn__/overlay-1.5.2.4.tar.gz to ramdisk
194 20:14:38.505303 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928147/compress-overlay-ufu_rn__/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928147/extract-overlay-ramdisk-6hkjqwsm/ramdisk
195 20:14:38.511884 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 20:14:38.511996 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 20:14:38.512088 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 20:14:38.512182 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 20:14:38.512258 Building ramdisk /var/lib/lava/dispatcher/tmp/12928147/extract-overlay-ramdisk-6hkjqwsm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928147/extract-overlay-ramdisk-6hkjqwsm/ramdisk
200 20:14:39.144561 >> 228484 blocks
201 20:14:43.055630 rename /var/lib/lava/dispatcher/tmp/12928147/extract-overlay-ramdisk-6hkjqwsm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/ramdisk/ramdisk.cpio.gz
202 20:14:43.056080 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 20:14:43.056200 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 20:14:43.056301 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 20:14:43.056405 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/kernel/Image'
206 20:14:55.739530 Returned 0 in 12 seconds
207 20:14:55.840160 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/kernel/image.itb
208 20:14:56.472271 output: FIT description: Kernel Image image with one or more FDT blobs
209 20:14:56.472638 output: Created: Sun Mar 3 20:14:56 2024
210 20:14:56.472718 output: Image 0 (kernel-1)
211 20:14:56.472786 output: Description:
212 20:14:56.472851 output: Created: Sun Mar 3 20:14:56 2024
213 20:14:56.472913 output: Type: Kernel Image
214 20:14:56.473005 output: Compression: lzma compressed
215 20:14:56.473067 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
216 20:14:56.473127 output: Architecture: AArch64
217 20:14:56.473185 output: OS: Linux
218 20:14:56.473240 output: Load Address: 0x00000000
219 20:14:56.473294 output: Entry Point: 0x00000000
220 20:14:56.473347 output: Hash algo: crc32
221 20:14:56.473400 output: Hash value: 91cb1a17
222 20:14:56.473454 output: Image 1 (fdt-1)
223 20:14:56.473509 output: Description: mt8192-asurada-spherion-r0
224 20:14:56.473563 output: Created: Sun Mar 3 20:14:56 2024
225 20:14:56.473617 output: Type: Flat Device Tree
226 20:14:56.473670 output: Compression: uncompressed
227 20:14:56.473723 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 20:14:56.473775 output: Architecture: AArch64
229 20:14:56.473827 output: Hash algo: crc32
230 20:14:56.473879 output: Hash value: cc4352de
231 20:14:56.473932 output: Image 2 (ramdisk-1)
232 20:14:56.473983 output: Description: unavailable
233 20:14:56.474036 output: Created: Sun Mar 3 20:14:56 2024
234 20:14:56.474088 output: Type: RAMDisk Image
235 20:14:56.474141 output: Compression: Unknown Compression
236 20:14:56.474193 output: Data Size: 39369254 Bytes = 38446.54 KiB = 37.55 MiB
237 20:14:56.474246 output: Architecture: AArch64
238 20:14:56.474298 output: OS: Linux
239 20:14:56.474350 output: Load Address: unavailable
240 20:14:56.474403 output: Entry Point: unavailable
241 20:14:56.474455 output: Hash algo: crc32
242 20:14:56.474507 output: Hash value: 5fcccfc0
243 20:14:56.474559 output: Default Configuration: 'conf-1'
244 20:14:56.474611 output: Configuration 0 (conf-1)
245 20:14:56.474663 output: Description: mt8192-asurada-spherion-r0
246 20:14:56.474715 output: Kernel: kernel-1
247 20:14:56.474788 output: Init Ramdisk: ramdisk-1
248 20:14:56.474845 output: FDT: fdt-1
249 20:14:56.474939 output: Loadables: kernel-1
250 20:14:56.474991 output:
251 20:14:56.475197 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 20:14:56.475315 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 20:14:56.475457 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 20:14:56.475602 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 20:14:56.475708 No LXC device requested
256 20:14:56.475793 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 20:14:56.475882 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 20:14:56.475961 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 20:14:56.476029 Checking files for TFTP limit of 4294967296 bytes.
260 20:14:56.476611 end: 1 tftp-deploy (duration 00:00:20) [common]
261 20:14:56.476717 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 20:14:56.476812 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 20:14:56.476971 substitutions:
264 20:14:56.477038 - {DTB}: 12928147/tftp-deploy-0_cc30s3/dtb/mt8192-asurada-spherion-r0.dtb
265 20:14:56.477103 - {INITRD}: 12928147/tftp-deploy-0_cc30s3/ramdisk/ramdisk.cpio.gz
266 20:14:56.477164 - {KERNEL}: 12928147/tftp-deploy-0_cc30s3/kernel/Image
267 20:14:56.477221 - {LAVA_MAC}: None
268 20:14:56.477326 - {PRESEED_CONFIG}: None
269 20:14:56.477396 - {PRESEED_LOCAL}: None
270 20:14:56.477450 - {RAMDISK}: 12928147/tftp-deploy-0_cc30s3/ramdisk/ramdisk.cpio.gz
271 20:14:56.477504 - {ROOT_PART}: None
272 20:14:56.477558 - {ROOT}: None
273 20:14:56.477611 - {SERVER_IP}: 192.168.201.1
274 20:14:56.477665 - {TEE}: None
275 20:14:56.477718 Parsed boot commands:
276 20:14:56.477772 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 20:14:56.477984 Parsed boot commands: tftpboot 192.168.201.1 12928147/tftp-deploy-0_cc30s3/kernel/image.itb 12928147/tftp-deploy-0_cc30s3/kernel/cmdline
278 20:14:56.478091 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 20:14:56.478177 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 20:14:56.478271 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 20:14:56.478355 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 20:14:56.478427 Not connected, no need to disconnect.
283 20:14:56.478500 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 20:14:56.478581 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 20:14:56.478647 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 20:14:56.482723 Setting prompt string to ['lava-test: # ']
287 20:14:56.483133 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 20:14:56.483239 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 20:14:56.483356 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 20:14:56.483493 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 20:14:56.483738 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 20:15:01.618572 >> Command sent successfully.
293 20:15:01.621492 Returned 0 in 5 seconds
294 20:15:01.721880 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 20:15:01.722249 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 20:15:01.722376 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 20:15:01.722543 Setting prompt string to 'Starting depthcharge on Spherion...'
299 20:15:01.722614 Changing prompt to 'Starting depthcharge on Spherion...'
300 20:15:01.722684 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 20:15:01.723000 [Enter `^Ec?' for help]
302 20:15:01.897037
303 20:15:01.897179
304 20:15:01.897249 F0: 102B 0000
305 20:15:01.897313
306 20:15:01.897371 F3: 1001 0000 [0200]
307 20:15:01.897430
308 20:15:01.900653 F3: 1001 0000
309 20:15:01.900737
310 20:15:01.900802 F7: 102D 0000
311 20:15:01.900864
312 20:15:01.903925 F1: 0000 0000
313 20:15:01.904049
314 20:15:01.904147 V0: 0000 0000 [0001]
315 20:15:01.904255
316 20:15:01.904340 00: 0007 8000
317 20:15:01.904435
318 20:15:01.907741 01: 0000 0000
319 20:15:01.907858
320 20:15:01.907947 BP: 0C00 0209 [0000]
321 20:15:01.908027
322 20:15:01.911249 G0: 1182 0000
323 20:15:01.911367
324 20:15:01.911472 EC: 0000 0021 [4000]
325 20:15:01.911553
326 20:15:01.915537 S7: 0000 0000 [0000]
327 20:15:01.915619
328 20:15:01.915684 CC: 0000 0000 [0001]
329 20:15:01.915745
330 20:15:01.918644 T0: 0000 0040 [010F]
331 20:15:01.918727
332 20:15:01.918793 Jump to BL
333 20:15:01.918854
334 20:15:01.943574
335 20:15:01.943673
336 20:15:01.943741
337 20:15:01.951202 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 20:15:01.955236 ARM64: Exception handlers installed.
339 20:15:01.958907 ARM64: Testing exception
340 20:15:01.962662 ARM64: Done test exception
341 20:15:01.969769 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 20:15:01.976434 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 20:15:01.983465 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 20:15:01.994602 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 20:15:02.001238 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 20:15:02.011480 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 20:15:02.021857 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 20:15:02.028164 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 20:15:02.046683 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 20:15:02.050261 WDT: Last reset was cold boot
351 20:15:02.053051 SPI1(PAD0) initialized at 2873684 Hz
352 20:15:02.056677 SPI5(PAD0) initialized at 992727 Hz
353 20:15:02.059909 VBOOT: Loading verstage.
354 20:15:02.066406 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 20:15:02.069880 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 20:15:02.073355 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 20:15:02.076302 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 20:15:02.083842 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 20:15:02.090702 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 20:15:02.101426 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 20:15:02.101512
362 20:15:02.101577
363 20:15:02.111252 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 20:15:02.114727 ARM64: Exception handlers installed.
365 20:15:02.118150 ARM64: Testing exception
366 20:15:02.118266 ARM64: Done test exception
367 20:15:02.125134 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 20:15:02.128244 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 20:15:02.142520 Probing TPM: . done!
370 20:15:02.142635 TPM ready after 0 ms
371 20:15:02.149785 Connected to device vid:did:rid of 1ae0:0028:00
372 20:15:02.156289 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 20:15:02.214257 Initialized TPM device CR50 revision 0
374 20:15:02.226555 tlcl_send_startup: Startup return code is 0
375 20:15:02.226662 TPM: setup succeeded
376 20:15:02.237996 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 20:15:02.246754 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 20:15:02.253288 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 20:15:02.267564 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 20:15:02.272101 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 20:15:02.278528 in-header: 03 07 00 00 08 00 00 00
382 20:15:02.282252 in-data: aa e4 47 04 13 02 00 00
383 20:15:02.285690 Chrome EC: UHEPI supported
384 20:15:02.292890 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 20:15:02.296823 in-header: 03 95 00 00 08 00 00 00
386 20:15:02.300330 in-data: 18 20 20 08 00 00 00 00
387 20:15:02.300413 Phase 1
388 20:15:02.303923 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 20:15:02.311242 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 20:15:02.314717 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 20:15:02.318083 Recovery requested (1009000e)
392 20:15:02.327452 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 20:15:02.332919 tlcl_extend: response is 0
394 20:15:02.342337 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 20:15:02.347693 tlcl_extend: response is 0
396 20:15:02.354786 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 20:15:02.374560 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 20:15:02.381295 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 20:15:02.381379
400 20:15:02.381444
401 20:15:02.391212 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 20:15:02.394499 ARM64: Exception handlers installed.
403 20:15:02.397492 ARM64: Testing exception
404 20:15:02.397576 ARM64: Done test exception
405 20:15:02.419822 pmic_efuse_setting: Set efuses in 11 msecs
406 20:15:02.423191 pmwrap_interface_init: Select PMIF_VLD_RDY
407 20:15:02.429808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 20:15:02.433199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 20:15:02.440553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 20:15:02.444252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 20:15:02.447637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 20:15:02.455974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 20:15:02.459161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 20:15:02.462768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 20:15:02.466405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 20:15:02.474144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 20:15:02.477704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 20:15:02.481782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 20:15:02.484959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 20:15:02.492107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 20:15:02.499292 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 20:15:02.502769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 20:15:02.510530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 20:15:02.514160 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 20:15:02.521277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 20:15:02.525461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 20:15:02.532403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 20:15:02.536517 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 20:15:02.543913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 20:15:02.547769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 20:15:02.555256 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 20:15:02.558652 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 20:15:02.565588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 20:15:02.569309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 20:15:02.573520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 20:15:02.580118 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 20:15:02.584930 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 20:15:02.587347 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 20:15:02.595042 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 20:15:02.598897 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 20:15:02.605472 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 20:15:02.609187 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 20:15:02.613211 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 20:15:02.620319 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 20:15:02.624290 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 20:15:02.628262 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 20:15:02.632140 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 20:15:02.635391 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 20:15:02.642516 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 20:15:02.645949 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 20:15:02.649792 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 20:15:02.653601 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 20:15:02.657166 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 20:15:02.664727 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 20:15:02.668424 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 20:15:02.671998 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 20:15:02.675510 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 20:15:02.683206 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 20:15:02.690852 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 20:15:02.697450 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 20:15:02.705319 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 20:15:02.712440 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 20:15:02.716307 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 20:15:02.719833 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 20:15:02.727208 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 20:15:02.734379 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
467 20:15:02.737769 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 20:15:02.744734 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 20:15:02.748267 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 20:15:02.757953 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 20:15:02.767217 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 20:15:02.776910 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 20:15:02.786732 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 20:15:02.795572 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 20:15:02.804907 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 20:15:02.814526 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 20:15:02.818040 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 20:15:02.825845 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 20:15:02.828977 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 20:15:02.832786 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 20:15:02.836181 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 20:15:02.840147 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 20:15:02.843931 ADC[4]: Raw value=904802 ID=7
484 20:15:02.847343 ADC[3]: Raw value=213546 ID=1
485 20:15:02.847494 RAM Code: 0x71
486 20:15:02.851484 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 20:15:02.858734 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 20:15:02.866442 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 20:15:02.873238 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 20:15:02.876984 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 20:15:02.880926 in-header: 03 07 00 00 08 00 00 00
492 20:15:02.884186 in-data: aa e4 47 04 13 02 00 00
493 20:15:02.884300 Chrome EC: UHEPI supported
494 20:15:02.891354 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 20:15:02.895575 in-header: 03 95 00 00 08 00 00 00
496 20:15:02.898811 in-data: 18 20 20 08 00 00 00 00
497 20:15:02.903079 MRC: failed to locate region type 0.
498 20:15:02.906649 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 20:15:02.910475 DRAM-K: Running full calibration
500 20:15:02.917635 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 20:15:02.917716 header.status = 0x0
502 20:15:02.921424 header.version = 0x6 (expected: 0x6)
503 20:15:02.925178 header.size = 0xd00 (expected: 0xd00)
504 20:15:02.928486 header.flags = 0x0
505 20:15:02.932407 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 20:15:02.952281 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 20:15:02.959221 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 20:15:02.963168 dram_init: ddr_geometry: 2
509 20:15:02.963251 [EMI] MDL number = 2
510 20:15:02.966795 [EMI] Get MDL freq = 0
511 20:15:02.966877 dram_init: ddr_type: 0
512 20:15:02.970239 is_discrete_lpddr4: 1
513 20:15:02.974190 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 20:15:02.974273
515 20:15:02.974337
516 20:15:02.974397 [Bian_co] ETT version 0.0.0.1
517 20:15:02.981188 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 20:15:02.981272
519 20:15:02.984562 dramc_set_vcore_voltage set vcore to 650000
520 20:15:02.987926 Read voltage for 800, 4
521 20:15:02.988007 Vio18 = 0
522 20:15:02.988072 Vcore = 650000
523 20:15:02.991185 Vdram = 0
524 20:15:02.991298 Vddq = 0
525 20:15:02.991421 Vmddr = 0
526 20:15:02.994624 dram_init: config_dvfs: 1
527 20:15:02.998017 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 20:15:03.005027 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 20:15:03.009181 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 20:15:03.013336 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 20:15:03.016349 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 20:15:03.019692 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 20:15:03.019775 MEM_TYPE=3, freq_sel=18
534 20:15:03.023112 sv_algorithm_assistance_LP4_1600
535 20:15:03.029630 ============ PULL DRAM RESETB DOWN ============
536 20:15:03.033258 ========== PULL DRAM RESETB DOWN end =========
537 20:15:03.036780 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 20:15:03.040481 ===================================
539 20:15:03.044293 LPDDR4 DRAM CONFIGURATION
540 20:15:03.047491 ===================================
541 20:15:03.047573 EX_ROW_EN[0] = 0x0
542 20:15:03.050651 EX_ROW_EN[1] = 0x0
543 20:15:03.050795 LP4Y_EN = 0x0
544 20:15:03.054035 WORK_FSP = 0x0
545 20:15:03.054142 WL = 0x2
546 20:15:03.057442 RL = 0x2
547 20:15:03.057549 BL = 0x2
548 20:15:03.060558 RPST = 0x0
549 20:15:03.060641 RD_PRE = 0x0
550 20:15:03.063891 WR_PRE = 0x1
551 20:15:03.067137 WR_PST = 0x0
552 20:15:03.067219 DBI_WR = 0x0
553 20:15:03.070618 DBI_RD = 0x0
554 20:15:03.070699 OTF = 0x1
555 20:15:03.073864 ===================================
556 20:15:03.076915 ===================================
557 20:15:03.076996 ANA top config
558 20:15:03.080524 ===================================
559 20:15:03.083845 DLL_ASYNC_EN = 0
560 20:15:03.086978 ALL_SLAVE_EN = 1
561 20:15:03.090465 NEW_RANK_MODE = 1
562 20:15:03.093699 DLL_IDLE_MODE = 1
563 20:15:03.093791 LP45_APHY_COMB_EN = 1
564 20:15:03.096934 TX_ODT_DIS = 1
565 20:15:03.100464 NEW_8X_MODE = 1
566 20:15:03.103874 ===================================
567 20:15:03.106926 ===================================
568 20:15:03.110363 data_rate = 1600
569 20:15:03.113656 CKR = 1
570 20:15:03.113738 DQ_P2S_RATIO = 8
571 20:15:03.116864 ===================================
572 20:15:03.120635 CA_P2S_RATIO = 8
573 20:15:03.124929 DQ_CA_OPEN = 0
574 20:15:03.127711 DQ_SEMI_OPEN = 0
575 20:15:03.130689 CA_SEMI_OPEN = 0
576 20:15:03.130799 CA_FULL_RATE = 0
577 20:15:03.134670 DQ_CKDIV4_EN = 1
578 20:15:03.138002 CA_CKDIV4_EN = 1
579 20:15:03.141342 CA_PREDIV_EN = 0
580 20:15:03.144545 PH8_DLY = 0
581 20:15:03.147697 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 20:15:03.147779 DQ_AAMCK_DIV = 4
583 20:15:03.151296 CA_AAMCK_DIV = 4
584 20:15:03.154532 CA_ADMCK_DIV = 4
585 20:15:03.157536 DQ_TRACK_CA_EN = 0
586 20:15:03.160884 CA_PICK = 800
587 20:15:03.164067 CA_MCKIO = 800
588 20:15:03.164148 MCKIO_SEMI = 0
589 20:15:03.168099 PLL_FREQ = 3068
590 20:15:03.171657 DQ_UI_PI_RATIO = 32
591 20:15:03.175185 CA_UI_PI_RATIO = 0
592 20:15:03.178683 ===================================
593 20:15:03.182532 ===================================
594 20:15:03.182614 memory_type:LPDDR4
595 20:15:03.186356 GP_NUM : 10
596 20:15:03.186469 SRAM_EN : 1
597 20:15:03.189923 MD32_EN : 0
598 20:15:03.193901 ===================================
599 20:15:03.193984 [ANA_INIT] >>>>>>>>>>>>>>
600 20:15:03.197111 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 20:15:03.201252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 20:15:03.204560 ===================================
603 20:15:03.207892 data_rate = 1600,PCW = 0X7600
604 20:15:03.211151 ===================================
605 20:15:03.214769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 20:15:03.221037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 20:15:03.224247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 20:15:03.231113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 20:15:03.234343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 20:15:03.237864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 20:15:03.237947 [ANA_INIT] flow start
612 20:15:03.241415 [ANA_INIT] PLL >>>>>>>>
613 20:15:03.244960 [ANA_INIT] PLL <<<<<<<<
614 20:15:03.245042 [ANA_INIT] MIDPI >>>>>>>>
615 20:15:03.248042 [ANA_INIT] MIDPI <<<<<<<<
616 20:15:03.251199 [ANA_INIT] DLL >>>>>>>>
617 20:15:03.251280 [ANA_INIT] flow end
618 20:15:03.257809 ============ LP4 DIFF to SE enter ============
619 20:15:03.260931 ============ LP4 DIFF to SE exit ============
620 20:15:03.264231 [ANA_INIT] <<<<<<<<<<<<<
621 20:15:03.268328 [Flow] Enable top DCM control >>>>>
622 20:15:03.270862 [Flow] Enable top DCM control <<<<<
623 20:15:03.270944 Enable DLL master slave shuffle
624 20:15:03.277685 ==============================================================
625 20:15:03.280676 Gating Mode config
626 20:15:03.283985 ==============================================================
627 20:15:03.287578 Config description:
628 20:15:03.297314 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 20:15:03.304196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 20:15:03.307274 SELPH_MODE 0: By rank 1: By Phase
631 20:15:03.314012 ==============================================================
632 20:15:03.317298 GAT_TRACK_EN = 1
633 20:15:03.320370 RX_GATING_MODE = 2
634 20:15:03.324088 RX_GATING_TRACK_MODE = 2
635 20:15:03.327725 SELPH_MODE = 1
636 20:15:03.327807 PICG_EARLY_EN = 1
637 20:15:03.330835 VALID_LAT_VALUE = 1
638 20:15:03.337223 ==============================================================
639 20:15:03.340734 Enter into Gating configuration >>>>
640 20:15:03.343935 Exit from Gating configuration <<<<
641 20:15:03.347238 Enter into DVFS_PRE_config >>>>>
642 20:15:03.360173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 20:15:03.360480 Exit from DVFS_PRE_config <<<<<
644 20:15:03.364044 Enter into PICG configuration >>>>
645 20:15:03.366757 Exit from PICG configuration <<<<
646 20:15:03.370093 [RX_INPUT] configuration >>>>>
647 20:15:03.373733 [RX_INPUT] configuration <<<<<
648 20:15:03.377299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 20:15:03.383489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 20:15:03.390279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 20:15:03.396984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 20:15:03.403276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 20:15:03.407305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 20:15:03.413713 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 20:15:03.416638 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 20:15:03.420207 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 20:15:03.423478 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 20:15:03.429739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 20:15:03.433183 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 20:15:03.436516 ===================================
661 20:15:03.440177 LPDDR4 DRAM CONFIGURATION
662 20:15:03.443483 ===================================
663 20:15:03.443592 EX_ROW_EN[0] = 0x0
664 20:15:03.446480 EX_ROW_EN[1] = 0x0
665 20:15:03.446562 LP4Y_EN = 0x0
666 20:15:03.450550 WORK_FSP = 0x0
667 20:15:03.450625 WL = 0x2
668 20:15:03.453704 RL = 0x2
669 20:15:03.453784 BL = 0x2
670 20:15:03.456493 RPST = 0x0
671 20:15:03.456568 RD_PRE = 0x0
672 20:15:03.460205 WR_PRE = 0x1
673 20:15:03.463503 WR_PST = 0x0
674 20:15:03.463586 DBI_WR = 0x0
675 20:15:03.466319 DBI_RD = 0x0
676 20:15:03.466402 OTF = 0x1
677 20:15:03.469629 ===================================
678 20:15:03.473373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 20:15:03.476392 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 20:15:03.482909 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 20:15:03.486481 ===================================
682 20:15:03.489840 LPDDR4 DRAM CONFIGURATION
683 20:15:03.493129 ===================================
684 20:15:03.493204 EX_ROW_EN[0] = 0x10
685 20:15:03.496192 EX_ROW_EN[1] = 0x0
686 20:15:03.496266 LP4Y_EN = 0x0
687 20:15:03.499630 WORK_FSP = 0x0
688 20:15:03.499706 WL = 0x2
689 20:15:03.503259 RL = 0x2
690 20:15:03.503366 BL = 0x2
691 20:15:03.506436 RPST = 0x0
692 20:15:03.506519 RD_PRE = 0x0
693 20:15:03.509664 WR_PRE = 0x1
694 20:15:03.509747 WR_PST = 0x0
695 20:15:03.513150 DBI_WR = 0x0
696 20:15:03.513227 DBI_RD = 0x0
697 20:15:03.516316 OTF = 0x1
698 20:15:03.520449 ===================================
699 20:15:03.526830 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 20:15:03.529568 nWR fixed to 40
701 20:15:03.533088 [ModeRegInit_LP4] CH0 RK0
702 20:15:03.533166 [ModeRegInit_LP4] CH0 RK1
703 20:15:03.535943 [ModeRegInit_LP4] CH1 RK0
704 20:15:03.539576 [ModeRegInit_LP4] CH1 RK1
705 20:15:03.539658 match AC timing 13
706 20:15:03.545989 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 20:15:03.549915 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 20:15:03.553364 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 20:15:03.559858 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 20:15:03.562708 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 20:15:03.566581 [EMI DOE] emi_dcm 0
712 20:15:03.569421 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 20:15:03.569502 ==
714 20:15:03.572527 Dram Type= 6, Freq= 0, CH_0, rank 0
715 20:15:03.575755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 20:15:03.575838 ==
717 20:15:03.582378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 20:15:03.589127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 20:15:03.597558 [CA 0] Center 38 (7~69) winsize 63
720 20:15:03.600318 [CA 1] Center 37 (6~68) winsize 63
721 20:15:03.603427 [CA 2] Center 34 (4~65) winsize 62
722 20:15:03.606789 [CA 3] Center 35 (4~66) winsize 63
723 20:15:03.610675 [CA 4] Center 33 (3~64) winsize 62
724 20:15:03.613684 [CA 5] Center 33 (3~64) winsize 62
725 20:15:03.613763
726 20:15:03.616854 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 20:15:03.616936
728 20:15:03.620311 [CATrainingPosCal] consider 1 rank data
729 20:15:03.623509 u2DelayCellTimex100 = 270/100 ps
730 20:15:03.626746 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 20:15:03.633409 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 20:15:03.636719 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 20:15:03.640629 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 20:15:03.643118 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 20:15:03.646457 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 20:15:03.646539
737 20:15:03.649780 CA PerBit enable=1, Macro0, CA PI delay=33
738 20:15:03.649861
739 20:15:03.653125 [CBTSetCACLKResult] CA Dly = 33
740 20:15:03.656726 CS Dly: 5 (0~36)
741 20:15:03.656808 ==
742 20:15:03.660155 Dram Type= 6, Freq= 0, CH_0, rank 1
743 20:15:03.663160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 20:15:03.663247 ==
745 20:15:03.670355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 20:15:03.673552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 20:15:03.683559 [CA 0] Center 38 (7~69) winsize 63
748 20:15:03.686676 [CA 1] Center 37 (7~68) winsize 62
749 20:15:03.690270 [CA 2] Center 35 (4~66) winsize 63
750 20:15:03.693264 [CA 3] Center 35 (4~66) winsize 63
751 20:15:03.697008 [CA 4] Center 34 (3~65) winsize 63
752 20:15:03.700385 [CA 5] Center 33 (3~64) winsize 62
753 20:15:03.700492
754 20:15:03.703246 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 20:15:03.703353
756 20:15:03.706608 [CATrainingPosCal] consider 2 rank data
757 20:15:03.709972 u2DelayCellTimex100 = 270/100 ps
758 20:15:03.714379 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
759 20:15:03.719940 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 20:15:03.723063 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 20:15:03.727019 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 20:15:03.729953 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 20:15:03.733158 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 20:15:03.733240
765 20:15:03.736686 CA PerBit enable=1, Macro0, CA PI delay=33
766 20:15:03.736768
767 20:15:03.740076 [CBTSetCACLKResult] CA Dly = 33
768 20:15:03.740157 CS Dly: 6 (0~38)
769 20:15:03.743299
770 20:15:03.746411 ----->DramcWriteLeveling(PI) begin...
771 20:15:03.746497 ==
772 20:15:03.750533 Dram Type= 6, Freq= 0, CH_0, rank 0
773 20:15:03.754071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 20:15:03.754153 ==
775 20:15:03.757597 Write leveling (Byte 0): 32 => 32
776 20:15:03.757680 Write leveling (Byte 1): 30 => 30
777 20:15:03.760934 DramcWriteLeveling(PI) end<-----
778 20:15:03.761017
779 20:15:03.761081 ==
780 20:15:03.764736 Dram Type= 6, Freq= 0, CH_0, rank 0
781 20:15:03.771509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 20:15:03.771592 ==
783 20:15:03.771657 [Gating] SW mode calibration
784 20:15:03.778266 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 20:15:03.785312 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 20:15:03.788433 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 20:15:03.795115 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 20:15:03.798476 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 20:15:03.801716 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 20:15:03.805353 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 20:15:03.812164 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 20:15:03.815130 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 20:15:03.818380 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 20:15:03.825074 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 20:15:03.828540 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 20:15:03.831574 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 20:15:03.838340 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 20:15:03.842019 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 20:15:03.844995 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 20:15:03.851479 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 20:15:03.854955 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 20:15:03.858457 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 20:15:03.865273 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 20:15:03.868361 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 20:15:03.872119 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 20:15:03.878908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 20:15:03.881772 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 20:15:03.885235 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 20:15:03.891479 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 20:15:03.894732 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 20:15:03.898458 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 20:15:03.904914 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
813 20:15:03.908066 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
814 20:15:03.911977 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 20:15:03.918183 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 20:15:03.921185 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 20:15:03.924591 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 20:15:03.931259 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 20:15:03.934351 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
820 20:15:03.937871 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
821 20:15:03.944862 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
822 20:15:03.947644 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 20:15:03.951325 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 20:15:03.957844 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 20:15:03.960970 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 20:15:03.964627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 20:15:03.970984 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
828 20:15:03.974446 0 11 8 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
829 20:15:03.977716 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
830 20:15:03.980803 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 20:15:03.988344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 20:15:03.990806 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 20:15:03.994798 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 20:15:04.000810 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 20:15:04.004270 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 20:15:04.007407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 20:15:04.014026 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 20:15:04.017647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 20:15:04.021310 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 20:15:04.028011 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 20:15:04.031075 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 20:15:04.034246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 20:15:04.040897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 20:15:04.044204 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 20:15:04.047233 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 20:15:04.053972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 20:15:04.057281 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 20:15:04.060528 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 20:15:04.067236 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 20:15:04.070758 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 20:15:04.073941 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 20:15:04.080498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 20:15:04.080581 Total UI for P1: 0, mck2ui 16
854 20:15:04.087016 best dqsien dly found for B0: ( 0, 14, 2)
855 20:15:04.090502 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 20:15:04.093875 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 20:15:04.097466 Total UI for P1: 0, mck2ui 16
858 20:15:04.100348 best dqsien dly found for B1: ( 0, 14, 10)
859 20:15:04.104416 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
860 20:15:04.106749 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 20:15:04.106831
862 20:15:04.113557 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
863 20:15:04.116782 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 20:15:04.116865 [Gating] SW calibration Done
865 20:15:04.121078 ==
866 20:15:04.121160 Dram Type= 6, Freq= 0, CH_0, rank 0
867 20:15:04.127528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 20:15:04.127611 ==
869 20:15:04.127677 RX Vref Scan: 0
870 20:15:04.127738
871 20:15:04.131233 RX Vref 0 -> 0, step: 1
872 20:15:04.131315
873 20:15:04.135073 RX Delay -130 -> 252, step: 16
874 20:15:04.137438 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 20:15:04.140865 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 20:15:04.144248 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 20:15:04.148069 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 20:15:04.154380 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 20:15:04.157472 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 20:15:04.160977 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 20:15:04.164620 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 20:15:04.168134 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 20:15:04.174148 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
884 20:15:04.177545 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 20:15:04.181514 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 20:15:04.184896 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 20:15:04.190998 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 20:15:04.193887 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 20:15:04.197523 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 20:15:04.197605 ==
891 20:15:04.201309 Dram Type= 6, Freq= 0, CH_0, rank 0
892 20:15:04.204015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 20:15:04.204097 ==
894 20:15:04.207280 DQS Delay:
895 20:15:04.207434 DQS0 = 0, DQS1 = 0
896 20:15:04.210978 DQM Delay:
897 20:15:04.211085 DQM0 = 88, DQM1 = 75
898 20:15:04.211178 DQ Delay:
899 20:15:04.214384 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 20:15:04.217286 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
901 20:15:04.220763 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
902 20:15:04.224682 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 20:15:04.224763
904 20:15:04.224828
905 20:15:04.228072 ==
906 20:15:04.228154 Dram Type= 6, Freq= 0, CH_0, rank 0
907 20:15:04.234147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 20:15:04.234229 ==
909 20:15:04.234293
910 20:15:04.234353
911 20:15:04.237547 TX Vref Scan disable
912 20:15:04.237629 == TX Byte 0 ==
913 20:15:04.240800 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 20:15:04.247592 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 20:15:04.247731 == TX Byte 1 ==
916 20:15:04.250501 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 20:15:04.257187 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 20:15:04.257288 ==
919 20:15:04.260462 Dram Type= 6, Freq= 0, CH_0, rank 0
920 20:15:04.263330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 20:15:04.263478 ==
922 20:15:04.277135 TX Vref=22, minBit 7, minWin=26, winSum=441
923 20:15:04.280490 TX Vref=24, minBit 1, minWin=27, winSum=445
924 20:15:04.283767 TX Vref=26, minBit 3, minWin=27, winSum=449
925 20:15:04.287649 TX Vref=28, minBit 0, minWin=28, winSum=454
926 20:15:04.290569 TX Vref=30, minBit 5, minWin=27, winSum=454
927 20:15:04.293968 TX Vref=32, minBit 1, minWin=27, winSum=451
928 20:15:04.300492 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
929 20:15:04.300575
930 20:15:04.304368 Final TX Range 1 Vref 28
931 20:15:04.304450
932 20:15:04.304516 ==
933 20:15:04.306901 Dram Type= 6, Freq= 0, CH_0, rank 0
934 20:15:04.310276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 20:15:04.310398 ==
936 20:15:04.313677
937 20:15:04.313758
938 20:15:04.313822 TX Vref Scan disable
939 20:15:04.317236 == TX Byte 0 ==
940 20:15:04.320462 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 20:15:04.326719 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 20:15:04.326808 == TX Byte 1 ==
943 20:15:04.330464 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 20:15:04.336756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 20:15:04.336837
946 20:15:04.336901 [DATLAT]
947 20:15:04.336961 Freq=800, CH0 RK0
948 20:15:04.337018
949 20:15:04.340074 DATLAT Default: 0xa
950 20:15:04.340156 0, 0xFFFF, sum = 0
951 20:15:04.343312 1, 0xFFFF, sum = 0
952 20:15:04.347059 2, 0xFFFF, sum = 0
953 20:15:04.347140 3, 0xFFFF, sum = 0
954 20:15:04.350153 4, 0xFFFF, sum = 0
955 20:15:04.350236 5, 0xFFFF, sum = 0
956 20:15:04.353590 6, 0xFFFF, sum = 0
957 20:15:04.353673 7, 0xFFFF, sum = 0
958 20:15:04.356784 8, 0xFFFF, sum = 0
959 20:15:04.356866 9, 0x0, sum = 1
960 20:15:04.359878 10, 0x0, sum = 2
961 20:15:04.359960 11, 0x0, sum = 3
962 20:15:04.360025 12, 0x0, sum = 4
963 20:15:04.363265 best_step = 10
964 20:15:04.363397
965 20:15:04.363478 ==
966 20:15:04.366705 Dram Type= 6, Freq= 0, CH_0, rank 0
967 20:15:04.370026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 20:15:04.370108 ==
969 20:15:04.373402 RX Vref Scan: 1
970 20:15:04.373483
971 20:15:04.376895 Set Vref Range= 32 -> 127
972 20:15:04.376976
973 20:15:04.377046 RX Vref 32 -> 127, step: 1
974 20:15:04.377106
975 20:15:04.380287 RX Delay -111 -> 252, step: 8
976 20:15:04.380395
977 20:15:04.383526 Set Vref, RX VrefLevel [Byte0]: 32
978 20:15:04.386517 [Byte1]: 32
979 20:15:04.389746
980 20:15:04.389827 Set Vref, RX VrefLevel [Byte0]: 33
981 20:15:04.392992 [Byte1]: 33
982 20:15:04.397310
983 20:15:04.397443 Set Vref, RX VrefLevel [Byte0]: 34
984 20:15:04.400895 [Byte1]: 34
985 20:15:04.405388
986 20:15:04.405499 Set Vref, RX VrefLevel [Byte0]: 35
987 20:15:04.408699 [Byte1]: 35
988 20:15:04.413624
989 20:15:04.413705 Set Vref, RX VrefLevel [Byte0]: 36
990 20:15:04.416940 [Byte1]: 36
991 20:15:04.421151
992 20:15:04.421232 Set Vref, RX VrefLevel [Byte0]: 37
993 20:15:04.424502 [Byte1]: 37
994 20:15:04.428448
995 20:15:04.428530 Set Vref, RX VrefLevel [Byte0]: 38
996 20:15:04.432324 [Byte1]: 38
997 20:15:04.435902
998 20:15:04.435983 Set Vref, RX VrefLevel [Byte0]: 39
999 20:15:04.439934 [Byte1]: 39
1000 20:15:04.444399
1001 20:15:04.444517 Set Vref, RX VrefLevel [Byte0]: 40
1002 20:15:04.447121 [Byte1]: 40
1003 20:15:04.451820
1004 20:15:04.451901 Set Vref, RX VrefLevel [Byte0]: 41
1005 20:15:04.455026 [Byte1]: 41
1006 20:15:04.458929
1007 20:15:04.459013 Set Vref, RX VrefLevel [Byte0]: 42
1008 20:15:04.462300 [Byte1]: 42
1009 20:15:04.466190
1010 20:15:04.466270 Set Vref, RX VrefLevel [Byte0]: 43
1011 20:15:04.469989 [Byte1]: 43
1012 20:15:04.474078
1013 20:15:04.474158 Set Vref, RX VrefLevel [Byte0]: 44
1014 20:15:04.477429 [Byte1]: 44
1015 20:15:04.481506
1016 20:15:04.481589 Set Vref, RX VrefLevel [Byte0]: 45
1017 20:15:04.485177 [Byte1]: 45
1018 20:15:04.489288
1019 20:15:04.489373 Set Vref, RX VrefLevel [Byte0]: 46
1020 20:15:04.492627 [Byte1]: 46
1021 20:15:04.497122
1022 20:15:04.497215 Set Vref, RX VrefLevel [Byte0]: 47
1023 20:15:04.500151 [Byte1]: 47
1024 20:15:04.504639
1025 20:15:04.504724 Set Vref, RX VrefLevel [Byte0]: 48
1026 20:15:04.507850 [Byte1]: 48
1027 20:15:04.512799
1028 20:15:04.512878 Set Vref, RX VrefLevel [Byte0]: 49
1029 20:15:04.515896 [Byte1]: 49
1030 20:15:04.519748
1031 20:15:04.519827 Set Vref, RX VrefLevel [Byte0]: 50
1032 20:15:04.523233 [Byte1]: 50
1033 20:15:04.528094
1034 20:15:04.528175 Set Vref, RX VrefLevel [Byte0]: 51
1035 20:15:04.531301 [Byte1]: 51
1036 20:15:04.535588
1037 20:15:04.535667 Set Vref, RX VrefLevel [Byte0]: 52
1038 20:15:04.538585 [Byte1]: 52
1039 20:15:04.542849
1040 20:15:04.542928 Set Vref, RX VrefLevel [Byte0]: 53
1041 20:15:04.545980 [Byte1]: 53
1042 20:15:04.550335
1043 20:15:04.550415 Set Vref, RX VrefLevel [Byte0]: 54
1044 20:15:04.553656 [Byte1]: 54
1045 20:15:04.558315
1046 20:15:04.558395 Set Vref, RX VrefLevel [Byte0]: 55
1047 20:15:04.561346 [Byte1]: 55
1048 20:15:04.565904
1049 20:15:04.565982 Set Vref, RX VrefLevel [Byte0]: 56
1050 20:15:04.569506 [Byte1]: 56
1051 20:15:04.573707
1052 20:15:04.573786 Set Vref, RX VrefLevel [Byte0]: 57
1053 20:15:04.576519 [Byte1]: 57
1054 20:15:04.580888
1055 20:15:04.580985 Set Vref, RX VrefLevel [Byte0]: 58
1056 20:15:04.584509 [Byte1]: 58
1057 20:15:04.588575
1058 20:15:04.588655 Set Vref, RX VrefLevel [Byte0]: 59
1059 20:15:04.592660 [Byte1]: 59
1060 20:15:04.596232
1061 20:15:04.596337 Set Vref, RX VrefLevel [Byte0]: 60
1062 20:15:04.599496 [Byte1]: 60
1063 20:15:04.603894
1064 20:15:04.604023 Set Vref, RX VrefLevel [Byte0]: 61
1065 20:15:04.607842 [Byte1]: 61
1066 20:15:04.612190
1067 20:15:04.612269 Set Vref, RX VrefLevel [Byte0]: 62
1068 20:15:04.614694 [Byte1]: 62
1069 20:15:04.619109
1070 20:15:04.619214 Set Vref, RX VrefLevel [Byte0]: 63
1071 20:15:04.622372 [Byte1]: 63
1072 20:15:04.626988
1073 20:15:04.627067 Set Vref, RX VrefLevel [Byte0]: 64
1074 20:15:04.630402 [Byte1]: 64
1075 20:15:04.634629
1076 20:15:04.634709 Set Vref, RX VrefLevel [Byte0]: 65
1077 20:15:04.638037 [Byte1]: 65
1078 20:15:04.642051
1079 20:15:04.642131 Set Vref, RX VrefLevel [Byte0]: 66
1080 20:15:04.645255 [Byte1]: 66
1081 20:15:04.649658
1082 20:15:04.649738 Set Vref, RX VrefLevel [Byte0]: 67
1083 20:15:04.652999 [Byte1]: 67
1084 20:15:04.657545
1085 20:15:04.657625 Set Vref, RX VrefLevel [Byte0]: 68
1086 20:15:04.661171 [Byte1]: 68
1087 20:15:04.665151
1088 20:15:04.665231 Set Vref, RX VrefLevel [Byte0]: 69
1089 20:15:04.668288 [Byte1]: 69
1090 20:15:04.672937
1091 20:15:04.673017 Set Vref, RX VrefLevel [Byte0]: 70
1092 20:15:04.676089 [Byte1]: 70
1093 20:15:04.680594
1094 20:15:04.680675 Set Vref, RX VrefLevel [Byte0]: 71
1095 20:15:04.683995 [Byte1]: 71
1096 20:15:04.687949
1097 20:15:04.688076 Set Vref, RX VrefLevel [Byte0]: 72
1098 20:15:04.691335 [Byte1]: 72
1099 20:15:04.695380
1100 20:15:04.695475 Set Vref, RX VrefLevel [Byte0]: 73
1101 20:15:04.698777 [Byte1]: 73
1102 20:15:04.703436
1103 20:15:04.703511 Final RX Vref Byte 0 = 58 to rank0
1104 20:15:04.706909 Final RX Vref Byte 1 = 60 to rank0
1105 20:15:04.710455 Final RX Vref Byte 0 = 58 to rank1
1106 20:15:04.713292 Final RX Vref Byte 1 = 60 to rank1==
1107 20:15:04.716849 Dram Type= 6, Freq= 0, CH_0, rank 0
1108 20:15:04.723204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1109 20:15:04.723311 ==
1110 20:15:04.723443 DQS Delay:
1111 20:15:04.723532 DQS0 = 0, DQS1 = 0
1112 20:15:04.726401 DQM Delay:
1113 20:15:04.726528 DQM0 = 88, DQM1 = 76
1114 20:15:04.729756 DQ Delay:
1115 20:15:04.733374 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1116 20:15:04.736347 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1117 20:15:04.739897 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1118 20:15:04.743289 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1119 20:15:04.743391
1120 20:15:04.743469
1121 20:15:04.749745 [DQSOSCAuto] RK0, (LSB)MR18= 0x312b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1122 20:15:04.754050 CH0 RK0: MR19=606, MR18=312B
1123 20:15:04.759803 CH0_RK0: MR19=0x606, MR18=0x312B, DQSOSC=397, MR23=63, INC=93, DEC=62
1124 20:15:04.759880
1125 20:15:04.763624 ----->DramcWriteLeveling(PI) begin...
1126 20:15:04.763706 ==
1127 20:15:04.766498 Dram Type= 6, Freq= 0, CH_0, rank 1
1128 20:15:04.769692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 20:15:04.769773 ==
1130 20:15:04.773495 Write leveling (Byte 0): 32 => 32
1131 20:15:04.776741 Write leveling (Byte 1): 27 => 27
1132 20:15:04.779805 DramcWriteLeveling(PI) end<-----
1133 20:15:04.779885
1134 20:15:04.779950 ==
1135 20:15:04.783338 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 20:15:04.786324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 20:15:04.786404 ==
1138 20:15:04.789490 [Gating] SW mode calibration
1139 20:15:04.796160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1140 20:15:04.803171 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1141 20:15:04.806726 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1142 20:15:04.809556 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1143 20:15:04.853331 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1144 20:15:04.853771 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1145 20:15:04.854134 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 20:15:04.854210 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 20:15:04.854274 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 20:15:04.854348 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 20:15:04.854436 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 20:15:04.855146 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 20:15:04.855498 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 20:15:04.855581 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 20:15:04.878993 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 20:15:04.879480 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 20:15:04.879792 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 20:15:04.879872 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 20:15:04.879936 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 20:15:04.882755 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1159 20:15:04.886908 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1160 20:15:04.889599 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 20:15:04.892780 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 20:15:04.899567 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 20:15:04.903123 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 20:15:04.905990 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 20:15:04.912811 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 20:15:04.916445 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 20:15:04.919635 0 9 8 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
1168 20:15:04.925959 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1169 20:15:04.929260 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 20:15:04.933151 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 20:15:04.939108 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 20:15:04.942574 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 20:15:04.946163 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 20:15:04.952623 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
1175 20:15:04.955876 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1176 20:15:04.959236 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1177 20:15:04.966270 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 20:15:04.968983 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 20:15:04.972440 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 20:15:04.979039 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 20:15:04.982724 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 20:15:04.985804 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1183 20:15:04.992485 0 11 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
1184 20:15:04.996882 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1185 20:15:04.999492 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 20:15:05.003263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 20:15:05.010227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 20:15:05.013674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 20:15:05.017980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 20:15:05.020339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1191 20:15:05.027869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1192 20:15:05.031164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 20:15:05.034081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 20:15:05.040596 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 20:15:05.044168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 20:15:05.047534 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 20:15:05.054043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 20:15:05.057462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 20:15:05.060717 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 20:15:05.067351 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 20:15:05.070556 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 20:15:05.073901 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 20:15:05.080784 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 20:15:05.083843 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 20:15:05.087342 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 20:15:05.094169 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1207 20:15:05.097498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1208 20:15:05.100678 Total UI for P1: 0, mck2ui 16
1209 20:15:05.103852 best dqsien dly found for B0: ( 0, 14, 4)
1210 20:15:05.107317 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 20:15:05.110540 Total UI for P1: 0, mck2ui 16
1212 20:15:05.113817 best dqsien dly found for B1: ( 0, 14, 6)
1213 20:15:05.116933 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1214 20:15:05.120240 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1215 20:15:05.120362
1216 20:15:05.123649 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1217 20:15:05.130306 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1218 20:15:05.130388 [Gating] SW calibration Done
1219 20:15:05.130452 ==
1220 20:15:05.133734 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 20:15:05.140098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 20:15:05.140180 ==
1223 20:15:05.140245 RX Vref Scan: 0
1224 20:15:05.140305
1225 20:15:05.143774 RX Vref 0 -> 0, step: 1
1226 20:15:05.143855
1227 20:15:05.147637 RX Delay -130 -> 252, step: 16
1228 20:15:05.150168 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1229 20:15:05.153815 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1230 20:15:05.156741 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1231 20:15:05.163537 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1232 20:15:05.166688 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1233 20:15:05.169931 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1234 20:15:05.173501 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1235 20:15:05.176726 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1236 20:15:05.184244 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1237 20:15:05.186789 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1238 20:15:05.189853 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1239 20:15:05.192919 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1240 20:15:05.196210 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1241 20:15:05.202938 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1242 20:15:05.206384 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1243 20:15:05.209683 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1244 20:15:05.209764 ==
1245 20:15:05.213005 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 20:15:05.216355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1247 20:15:05.216430 ==
1248 20:15:05.219652 DQS Delay:
1249 20:15:05.219729 DQS0 = 0, DQS1 = 0
1250 20:15:05.222944 DQM Delay:
1251 20:15:05.223026 DQM0 = 88, DQM1 = 79
1252 20:15:05.226042 DQ Delay:
1253 20:15:05.226117 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1254 20:15:05.229324 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1255 20:15:05.233598 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1256 20:15:05.236041 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1257 20:15:05.236123
1258 20:15:05.239679
1259 20:15:05.239762 ==
1260 20:15:05.242946 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 20:15:05.246333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 20:15:05.246414 ==
1263 20:15:05.246478
1264 20:15:05.246537
1265 20:15:05.249470 TX Vref Scan disable
1266 20:15:05.249551 == TX Byte 0 ==
1267 20:15:05.255883 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1268 20:15:05.259240 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1269 20:15:05.259321 == TX Byte 1 ==
1270 20:15:05.266012 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1271 20:15:05.269182 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1272 20:15:05.269263 ==
1273 20:15:05.272707 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 20:15:05.275940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 20:15:05.276025 ==
1276 20:15:05.289990 TX Vref=22, minBit 1, minWin=27, winSum=441
1277 20:15:05.293217 TX Vref=24, minBit 2, minWin=27, winSum=447
1278 20:15:05.296789 TX Vref=26, minBit 1, minWin=27, winSum=449
1279 20:15:05.300353 TX Vref=28, minBit 2, minWin=27, winSum=449
1280 20:15:05.303286 TX Vref=30, minBit 1, minWin=27, winSum=450
1281 20:15:05.310095 TX Vref=32, minBit 1, minWin=27, winSum=449
1282 20:15:05.313316 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1283 20:15:05.313398
1284 20:15:05.316398 Final TX Range 1 Vref 30
1285 20:15:05.316478
1286 20:15:05.316543 ==
1287 20:15:05.319890 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 20:15:05.323665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 20:15:05.326163 ==
1290 20:15:05.326243
1291 20:15:05.326306
1292 20:15:05.326366 TX Vref Scan disable
1293 20:15:05.329991 == TX Byte 0 ==
1294 20:15:05.333290 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1295 20:15:05.340048 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1296 20:15:05.340129 == TX Byte 1 ==
1297 20:15:05.343168 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1298 20:15:05.349966 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1299 20:15:05.350046
1300 20:15:05.350109 [DATLAT]
1301 20:15:05.350167 Freq=800, CH0 RK1
1302 20:15:05.350225
1303 20:15:05.353510 DATLAT Default: 0xa
1304 20:15:05.353590 0, 0xFFFF, sum = 0
1305 20:15:05.356713 1, 0xFFFF, sum = 0
1306 20:15:05.356800 2, 0xFFFF, sum = 0
1307 20:15:05.360036 3, 0xFFFF, sum = 0
1308 20:15:05.363315 4, 0xFFFF, sum = 0
1309 20:15:05.363432 5, 0xFFFF, sum = 0
1310 20:15:05.366306 6, 0xFFFF, sum = 0
1311 20:15:05.366386 7, 0xFFFF, sum = 0
1312 20:15:05.369588 8, 0xFFFF, sum = 0
1313 20:15:05.369669 9, 0x0, sum = 1
1314 20:15:05.373273 10, 0x0, sum = 2
1315 20:15:05.373353 11, 0x0, sum = 3
1316 20:15:05.373419 12, 0x0, sum = 4
1317 20:15:05.376239 best_step = 10
1318 20:15:05.376318
1319 20:15:05.376381 ==
1320 20:15:05.379591 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 20:15:05.383327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 20:15:05.383445 ==
1323 20:15:05.386110 RX Vref Scan: 0
1324 20:15:05.386189
1325 20:15:05.386252 RX Vref 0 -> 0, step: 1
1326 20:15:05.389551
1327 20:15:05.389631 RX Delay -95 -> 252, step: 8
1328 20:15:05.396563 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1329 20:15:05.400076 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1330 20:15:05.403541 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1331 20:15:05.406309 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1332 20:15:05.413333 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1333 20:15:05.416526 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1334 20:15:05.419708 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1335 20:15:05.423128 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1336 20:15:05.427268 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1337 20:15:05.433255 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1338 20:15:05.436025 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1339 20:15:05.439469 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1340 20:15:05.442848 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1341 20:15:05.446178 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1342 20:15:05.452841 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1343 20:15:05.456107 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1344 20:15:05.456187 ==
1345 20:15:05.459409 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 20:15:05.462625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 20:15:05.462705 ==
1348 20:15:05.465958 DQS Delay:
1349 20:15:05.466037 DQS0 = 0, DQS1 = 0
1350 20:15:05.466100 DQM Delay:
1351 20:15:05.469095 DQM0 = 86, DQM1 = 76
1352 20:15:05.469175 DQ Delay:
1353 20:15:05.472558 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1354 20:15:05.476024 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1355 20:15:05.479245 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1356 20:15:05.482666 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1357 20:15:05.482753
1358 20:15:05.482818
1359 20:15:05.492576 [DQSOSCAuto] RK1, (LSB)MR18= 0x231f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1360 20:15:05.495641 CH0 RK1: MR19=606, MR18=231F
1361 20:15:05.498927 CH0_RK1: MR19=0x606, MR18=0x231F, DQSOSC=401, MR23=63, INC=91, DEC=61
1362 20:15:05.502333 [RxdqsGatingPostProcess] freq 800
1363 20:15:05.509127 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1364 20:15:05.512079 Pre-setting of DQS Precalculation
1365 20:15:05.515867 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1366 20:15:05.515947 ==
1367 20:15:05.519476 Dram Type= 6, Freq= 0, CH_1, rank 0
1368 20:15:05.525646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 20:15:05.525727 ==
1370 20:15:05.528695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1371 20:15:05.535560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1372 20:15:05.545327 [CA 0] Center 37 (6~68) winsize 63
1373 20:15:05.548430 [CA 1] Center 37 (6~68) winsize 63
1374 20:15:05.551663 [CA 2] Center 35 (5~66) winsize 62
1375 20:15:05.554731 [CA 3] Center 34 (4~65) winsize 62
1376 20:15:05.558354 [CA 4] Center 35 (4~66) winsize 63
1377 20:15:05.561391 [CA 5] Center 34 (4~65) winsize 62
1378 20:15:05.561471
1379 20:15:05.565084 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1380 20:15:05.565165
1381 20:15:05.568304 [CATrainingPosCal] consider 1 rank data
1382 20:15:05.571315 u2DelayCellTimex100 = 270/100 ps
1383 20:15:05.574627 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1384 20:15:05.581252 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1385 20:15:05.584729 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1386 20:15:05.587880 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1387 20:15:05.591269 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1388 20:15:05.594893 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1389 20:15:05.594988
1390 20:15:05.597744 CA PerBit enable=1, Macro0, CA PI delay=34
1391 20:15:05.597824
1392 20:15:05.601191 [CBTSetCACLKResult] CA Dly = 34
1393 20:15:05.601279 CS Dly: 4 (0~35)
1394 20:15:05.604569 ==
1395 20:15:05.607953 Dram Type= 6, Freq= 0, CH_1, rank 1
1396 20:15:05.611304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 20:15:05.611421 ==
1398 20:15:05.614662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 20:15:05.621190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 20:15:05.631114 [CA 0] Center 36 (6~67) winsize 62
1401 20:15:05.634651 [CA 1] Center 36 (6~67) winsize 62
1402 20:15:05.638011 [CA 2] Center 35 (4~66) winsize 63
1403 20:15:05.641077 [CA 3] Center 34 (4~65) winsize 62
1404 20:15:05.644999 [CA 4] Center 34 (4~65) winsize 62
1405 20:15:05.647718 [CA 5] Center 34 (4~65) winsize 62
1406 20:15:05.647798
1407 20:15:05.650940 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1408 20:15:05.651020
1409 20:15:05.654426 [CATrainingPosCal] consider 2 rank data
1410 20:15:05.657450 u2DelayCellTimex100 = 270/100 ps
1411 20:15:05.660976 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 20:15:05.665024 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 20:15:05.668717 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1414 20:15:05.672183 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 20:15:05.675898 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 20:15:05.679146 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 20:15:05.679227
1418 20:15:05.682704 CA PerBit enable=1, Macro0, CA PI delay=34
1419 20:15:05.686147
1420 20:15:05.686227 [CBTSetCACLKResult] CA Dly = 34
1421 20:15:05.690292 CS Dly: 5 (0~38)
1422 20:15:05.690372
1423 20:15:05.693451 ----->DramcWriteLeveling(PI) begin...
1424 20:15:05.693533 ==
1425 20:15:05.697322 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 20:15:05.700933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 20:15:05.701014 ==
1428 20:15:05.704231 Write leveling (Byte 0): 26 => 26
1429 20:15:05.707287 Write leveling (Byte 1): 25 => 25
1430 20:15:05.711014 DramcWriteLeveling(PI) end<-----
1431 20:15:05.711094
1432 20:15:05.711157 ==
1433 20:15:05.713938 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 20:15:05.717297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 20:15:05.717378 ==
1436 20:15:05.721197 [Gating] SW mode calibration
1437 20:15:05.727535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1438 20:15:05.734017 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1439 20:15:05.737320 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1440 20:15:05.740747 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1441 20:15:05.747156 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 20:15:05.750411 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 20:15:05.753694 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 20:15:05.760597 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 20:15:05.763988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 20:15:05.767059 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 20:15:05.773737 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 20:15:05.777220 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 20:15:05.780520 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 20:15:05.783329 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 20:15:05.790493 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 20:15:05.793680 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 20:15:05.797177 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 20:15:05.803633 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 20:15:05.807254 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 20:15:05.810218 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1457 20:15:05.816624 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 20:15:05.820407 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 20:15:05.823480 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 20:15:05.829815 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 20:15:05.833338 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 20:15:05.836651 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 20:15:05.843203 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 20:15:05.846401 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 20:15:05.849736 0 9 8 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 1)
1466 20:15:05.856745 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 20:15:05.859681 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 20:15:05.863091 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 20:15:05.869692 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 20:15:05.873284 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 20:15:05.876456 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 20:15:05.882747 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
1473 20:15:05.887099 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1474 20:15:05.889451 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 20:15:05.896540 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 20:15:05.899491 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 20:15:05.902610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 20:15:05.909240 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 20:15:05.913282 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 20:15:05.916032 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1481 20:15:05.922892 0 11 8 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)
1482 20:15:05.926292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 20:15:05.929564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 20:15:05.936279 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 20:15:05.939897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 20:15:05.942359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 20:15:05.949300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 20:15:05.952844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1489 20:15:05.955655 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 20:15:05.962145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 20:15:05.965765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 20:15:05.968927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 20:15:05.975601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 20:15:05.978863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 20:15:05.982273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 20:15:05.989402 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 20:15:05.992218 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 20:15:05.995740 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 20:15:05.998935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 20:15:06.005612 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 20:15:06.009295 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 20:15:06.012144 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 20:15:06.018974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 20:15:06.022461 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1505 20:15:06.025247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 20:15:06.028825 Total UI for P1: 0, mck2ui 16
1507 20:15:06.032553 best dqsien dly found for B0: ( 0, 14, 4)
1508 20:15:06.035256 Total UI for P1: 0, mck2ui 16
1509 20:15:06.038676 best dqsien dly found for B1: ( 0, 14, 4)
1510 20:15:06.042086 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1511 20:15:06.045226 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1512 20:15:06.048424
1513 20:15:06.051870 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1514 20:15:06.055351 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1515 20:15:06.058797 [Gating] SW calibration Done
1516 20:15:06.058918 ==
1517 20:15:06.061839 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 20:15:06.064852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 20:15:06.064975 ==
1520 20:15:06.065085 RX Vref Scan: 0
1521 20:15:06.068077
1522 20:15:06.068199 RX Vref 0 -> 0, step: 1
1523 20:15:06.068307
1524 20:15:06.071576 RX Delay -130 -> 252, step: 16
1525 20:15:06.074784 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1526 20:15:06.078148 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1527 20:15:06.084875 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1528 20:15:06.088743 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1529 20:15:06.091655 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1530 20:15:06.094904 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1531 20:15:06.098013 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1532 20:15:06.104886 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1533 20:15:06.108094 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1534 20:15:06.111684 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1535 20:15:06.115150 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1536 20:15:06.117976 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1537 20:15:06.124606 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1538 20:15:06.128183 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1539 20:15:06.131117 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1540 20:15:06.134492 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1541 20:15:06.137762 ==
1542 20:15:06.137887 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 20:15:06.144582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 20:15:06.144708 ==
1545 20:15:06.144818 DQS Delay:
1546 20:15:06.147764 DQS0 = 0, DQS1 = 0
1547 20:15:06.147902 DQM Delay:
1548 20:15:06.151477 DQM0 = 88, DQM1 = 82
1549 20:15:06.151598 DQ Delay:
1550 20:15:06.154257 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1551 20:15:06.157488 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1552 20:15:06.161316 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1553 20:15:06.163935 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1554 20:15:06.164055
1555 20:15:06.164167
1556 20:15:06.164275 ==
1557 20:15:06.167321 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 20:15:06.170768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 20:15:06.170889 ==
1560 20:15:06.171000
1561 20:15:06.171108
1562 20:15:06.174281 TX Vref Scan disable
1563 20:15:06.177214 == TX Byte 0 ==
1564 20:15:06.180997 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1565 20:15:06.183809 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1566 20:15:06.187495 == TX Byte 1 ==
1567 20:15:06.190724 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1568 20:15:06.193793 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1569 20:15:06.193912 ==
1570 20:15:06.196930 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 20:15:06.203496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 20:15:06.203619 ==
1573 20:15:06.215386 TX Vref=22, minBit 2, minWin=26, winSum=437
1574 20:15:06.218753 TX Vref=24, minBit 6, minWin=26, winSum=446
1575 20:15:06.222167 TX Vref=26, minBit 1, minWin=27, winSum=448
1576 20:15:06.225644 TX Vref=28, minBit 2, minWin=27, winSum=452
1577 20:15:06.228779 TX Vref=30, minBit 0, minWin=27, winSum=452
1578 20:15:06.235168 TX Vref=32, minBit 1, minWin=27, winSum=451
1579 20:15:06.238574 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 28
1580 20:15:06.238698
1581 20:15:06.242304 Final TX Range 1 Vref 28
1582 20:15:06.242427
1583 20:15:06.242540 ==
1584 20:15:06.246193 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 20:15:06.249621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 20:15:06.249742 ==
1587 20:15:06.249856
1588 20:15:06.249964
1589 20:15:06.253007 TX Vref Scan disable
1590 20:15:06.256195 == TX Byte 0 ==
1591 20:15:06.259866 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1592 20:15:06.263025 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1593 20:15:06.266218 == TX Byte 1 ==
1594 20:15:06.269358 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1595 20:15:06.272944 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1596 20:15:06.273067
1597 20:15:06.276112 [DATLAT]
1598 20:15:06.276233 Freq=800, CH1 RK0
1599 20:15:06.276349
1600 20:15:06.279718 DATLAT Default: 0xa
1601 20:15:06.279839 0, 0xFFFF, sum = 0
1602 20:15:06.282624 1, 0xFFFF, sum = 0
1603 20:15:06.282748 2, 0xFFFF, sum = 0
1604 20:15:06.285976 3, 0xFFFF, sum = 0
1605 20:15:06.286099 4, 0xFFFF, sum = 0
1606 20:15:06.289753 5, 0xFFFF, sum = 0
1607 20:15:06.289837 6, 0xFFFF, sum = 0
1608 20:15:06.292339 7, 0xFFFF, sum = 0
1609 20:15:06.292422 8, 0xFFFF, sum = 0
1610 20:15:06.295862 9, 0x0, sum = 1
1611 20:15:06.295963 10, 0x0, sum = 2
1612 20:15:06.299248 11, 0x0, sum = 3
1613 20:15:06.299400 12, 0x0, sum = 4
1614 20:15:06.302149 best_step = 10
1615 20:15:06.302231
1616 20:15:06.302295 ==
1617 20:15:06.305608 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 20:15:06.308772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 20:15:06.308871 ==
1620 20:15:06.312016 RX Vref Scan: 1
1621 20:15:06.312097
1622 20:15:06.312162 Set Vref Range= 32 -> 127
1623 20:15:06.312222
1624 20:15:06.315789 RX Vref 32 -> 127, step: 1
1625 20:15:06.315913
1626 20:15:06.319145 RX Delay -95 -> 252, step: 8
1627 20:15:06.319263
1628 20:15:06.322079 Set Vref, RX VrefLevel [Byte0]: 32
1629 20:15:06.325576 [Byte1]: 32
1630 20:15:06.325696
1631 20:15:06.328782 Set Vref, RX VrefLevel [Byte0]: 33
1632 20:15:06.332274 [Byte1]: 33
1633 20:15:06.335999
1634 20:15:06.336120 Set Vref, RX VrefLevel [Byte0]: 34
1635 20:15:06.338985 [Byte1]: 34
1636 20:15:06.343934
1637 20:15:06.344057 Set Vref, RX VrefLevel [Byte0]: 35
1638 20:15:06.346710 [Byte1]: 35
1639 20:15:06.350720
1640 20:15:06.350838 Set Vref, RX VrefLevel [Byte0]: 36
1641 20:15:06.354391 [Byte1]: 36
1642 20:15:06.358525
1643 20:15:06.358639 Set Vref, RX VrefLevel [Byte0]: 37
1644 20:15:06.361711 [Byte1]: 37
1645 20:15:06.366128
1646 20:15:06.366249 Set Vref, RX VrefLevel [Byte0]: 38
1647 20:15:06.369568 [Byte1]: 38
1648 20:15:06.373664
1649 20:15:06.373786 Set Vref, RX VrefLevel [Byte0]: 39
1650 20:15:06.376853 [Byte1]: 39
1651 20:15:06.381441
1652 20:15:06.381563 Set Vref, RX VrefLevel [Byte0]: 40
1653 20:15:06.384345 [Byte1]: 40
1654 20:15:06.388980
1655 20:15:06.389102 Set Vref, RX VrefLevel [Byte0]: 41
1656 20:15:06.391970 [Byte1]: 41
1657 20:15:06.396611
1658 20:15:06.396720 Set Vref, RX VrefLevel [Byte0]: 42
1659 20:15:06.399347 [Byte1]: 42
1660 20:15:06.404114
1661 20:15:06.404209 Set Vref, RX VrefLevel [Byte0]: 43
1662 20:15:06.407326 [Byte1]: 43
1663 20:15:06.412147
1664 20:15:06.412228 Set Vref, RX VrefLevel [Byte0]: 44
1665 20:15:06.414796 [Byte1]: 44
1666 20:15:06.419470
1667 20:15:06.419550 Set Vref, RX VrefLevel [Byte0]: 45
1668 20:15:06.422680 [Byte1]: 45
1669 20:15:06.426849
1670 20:15:06.426960 Set Vref, RX VrefLevel [Byte0]: 46
1671 20:15:06.430004 [Byte1]: 46
1672 20:15:06.434315
1673 20:15:06.434395 Set Vref, RX VrefLevel [Byte0]: 47
1674 20:15:06.437612 [Byte1]: 47
1675 20:15:06.441873
1676 20:15:06.441953 Set Vref, RX VrefLevel [Byte0]: 48
1677 20:15:06.445178 [Byte1]: 48
1678 20:15:06.449750
1679 20:15:06.449830 Set Vref, RX VrefLevel [Byte0]: 49
1680 20:15:06.453255 [Byte1]: 49
1681 20:15:06.457087
1682 20:15:06.457167 Set Vref, RX VrefLevel [Byte0]: 50
1683 20:15:06.460671 [Byte1]: 50
1684 20:15:06.464911
1685 20:15:06.464991 Set Vref, RX VrefLevel [Byte0]: 51
1686 20:15:06.467864 [Byte1]: 51
1687 20:15:06.472647
1688 20:15:06.472728 Set Vref, RX VrefLevel [Byte0]: 52
1689 20:15:06.475582 [Byte1]: 52
1690 20:15:06.480181
1691 20:15:06.480311 Set Vref, RX VrefLevel [Byte0]: 53
1692 20:15:06.483510 [Byte1]: 53
1693 20:15:06.487465
1694 20:15:06.487546 Set Vref, RX VrefLevel [Byte0]: 54
1695 20:15:06.490774 [Byte1]: 54
1696 20:15:06.495085
1697 20:15:06.495166 Set Vref, RX VrefLevel [Byte0]: 55
1698 20:15:06.498344 [Byte1]: 55
1699 20:15:06.502721
1700 20:15:06.502802 Set Vref, RX VrefLevel [Byte0]: 56
1701 20:15:06.506059 [Byte1]: 56
1702 20:15:06.510557
1703 20:15:06.510637 Set Vref, RX VrefLevel [Byte0]: 57
1704 20:15:06.513444 [Byte1]: 57
1705 20:15:06.518028
1706 20:15:06.518108 Set Vref, RX VrefLevel [Byte0]: 58
1707 20:15:06.521312 [Byte1]: 58
1708 20:15:06.525416
1709 20:15:06.525512 Set Vref, RX VrefLevel [Byte0]: 59
1710 20:15:06.528791 [Byte1]: 59
1711 20:15:06.533415
1712 20:15:06.533527 Set Vref, RX VrefLevel [Byte0]: 60
1713 20:15:06.536534 [Byte1]: 60
1714 20:15:06.540493
1715 20:15:06.540587 Set Vref, RX VrefLevel [Byte0]: 61
1716 20:15:06.544084 [Byte1]: 61
1717 20:15:06.548585
1718 20:15:06.548666 Set Vref, RX VrefLevel [Byte0]: 62
1719 20:15:06.551696 [Byte1]: 62
1720 20:15:06.556261
1721 20:15:06.556342 Set Vref, RX VrefLevel [Byte0]: 63
1722 20:15:06.559211 [Byte1]: 63
1723 20:15:06.563489
1724 20:15:06.563571 Set Vref, RX VrefLevel [Byte0]: 64
1725 20:15:06.566696 [Byte1]: 64
1726 20:15:06.570855
1727 20:15:06.570937 Set Vref, RX VrefLevel [Byte0]: 65
1728 20:15:06.574543 [Byte1]: 65
1729 20:15:06.578921
1730 20:15:06.579020 Set Vref, RX VrefLevel [Byte0]: 66
1731 20:15:06.581823 [Byte1]: 66
1732 20:15:06.586180
1733 20:15:06.586277 Set Vref, RX VrefLevel [Byte0]: 67
1734 20:15:06.589363 [Byte1]: 67
1735 20:15:06.594139
1736 20:15:06.594233 Set Vref, RX VrefLevel [Byte0]: 68
1737 20:15:06.597173 [Byte1]: 68
1738 20:15:06.601634
1739 20:15:06.601715 Set Vref, RX VrefLevel [Byte0]: 69
1740 20:15:06.604587 [Byte1]: 69
1741 20:15:06.609368
1742 20:15:06.609489 Set Vref, RX VrefLevel [Byte0]: 70
1743 20:15:06.612722 [Byte1]: 70
1744 20:15:06.616666
1745 20:15:06.616790 Set Vref, RX VrefLevel [Byte0]: 71
1746 20:15:06.620485 [Byte1]: 71
1747 20:15:06.624938
1748 20:15:06.625046 Set Vref, RX VrefLevel [Byte0]: 72
1749 20:15:06.627772 [Byte1]: 72
1750 20:15:06.631888
1751 20:15:06.631977 Set Vref, RX VrefLevel [Byte0]: 73
1752 20:15:06.635344 [Byte1]: 73
1753 20:15:06.639413
1754 20:15:06.639511 Set Vref, RX VrefLevel [Byte0]: 74
1755 20:15:06.642860 [Byte1]: 74
1756 20:15:06.646864
1757 20:15:06.646944 Final RX Vref Byte 0 = 60 to rank0
1758 20:15:06.650524 Final RX Vref Byte 1 = 58 to rank0
1759 20:15:06.653927 Final RX Vref Byte 0 = 60 to rank1
1760 20:15:06.656971 Final RX Vref Byte 1 = 58 to rank1==
1761 20:15:06.660834 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 20:15:06.666988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 20:15:06.667069 ==
1764 20:15:06.667134 DQS Delay:
1765 20:15:06.667194 DQS0 = 0, DQS1 = 0
1766 20:15:06.671086 DQM Delay:
1767 20:15:06.671166 DQM0 = 87, DQM1 = 81
1768 20:15:06.674210 DQ Delay:
1769 20:15:06.676916 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1770 20:15:06.680703 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1771 20:15:06.683343 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1772 20:15:06.686708 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1773 20:15:06.686797
1774 20:15:06.686892
1775 20:15:06.693348 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
1776 20:15:06.696711 CH1 RK0: MR19=606, MR18=1B2F
1777 20:15:06.703290 CH1_RK0: MR19=0x606, MR18=0x1B2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1778 20:15:06.703424
1779 20:15:06.706891 ----->DramcWriteLeveling(PI) begin...
1780 20:15:06.706994 ==
1781 20:15:06.709932 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 20:15:06.713153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 20:15:06.713234 ==
1784 20:15:06.716529 Write leveling (Byte 0): 25 => 25
1785 20:15:06.719512 Write leveling (Byte 1): 30 => 30
1786 20:15:06.723066 DramcWriteLeveling(PI) end<-----
1787 20:15:06.723149
1788 20:15:06.723250 ==
1789 20:15:06.726324 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 20:15:06.729625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 20:15:06.733316 ==
1792 20:15:06.733397 [Gating] SW mode calibration
1793 20:15:06.739904 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 20:15:06.746417 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 20:15:06.749345 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1796 20:15:06.755919 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1797 20:15:06.759170 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1798 20:15:06.762666 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 20:15:06.769638 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 20:15:06.772634 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 20:15:06.775975 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 20:15:06.782722 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 20:15:06.785782 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 20:15:06.789205 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 20:15:06.796074 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 20:15:06.799115 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 20:15:06.802238 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 20:15:06.809470 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 20:15:06.812659 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 20:15:06.815894 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 20:15:06.822806 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1812 20:15:06.825639 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1813 20:15:06.829005 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1814 20:15:06.832267 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 20:15:06.839012 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 20:15:06.842776 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 20:15:06.845690 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 20:15:06.852266 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 20:15:06.855608 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 20:15:06.858585 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1821 20:15:06.865649 0 9 8 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
1822 20:15:06.868571 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 20:15:06.872073 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 20:15:06.878441 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 20:15:06.882410 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 20:15:06.885392 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 20:15:06.892237 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
1828 20:15:06.895241 0 10 4 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
1829 20:15:06.898348 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 20:15:06.904997 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 20:15:06.908488 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 20:15:06.911991 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 20:15:06.918349 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 20:15:06.922289 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 20:15:06.925253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 20:15:06.931733 0 11 4 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
1837 20:15:06.934905 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1838 20:15:06.938851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 20:15:06.944780 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 20:15:06.948179 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 20:15:06.951469 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 20:15:06.958586 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 20:15:06.961632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 20:15:06.964835 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1845 20:15:06.971434 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 20:15:06.974722 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 20:15:06.978101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 20:15:06.984704 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 20:15:06.988157 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 20:15:06.991226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 20:15:06.997974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 20:15:07.001313 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 20:15:07.004634 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 20:15:07.011162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 20:15:07.014727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 20:15:07.018127 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 20:15:07.024779 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 20:15:07.027941 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 20:15:07.031309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1860 20:15:07.034426 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1861 20:15:07.037923 Total UI for P1: 0, mck2ui 16
1862 20:15:07.041029 best dqsien dly found for B0: ( 0, 14, 0)
1863 20:15:07.047793 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1864 20:15:07.050922 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 20:15:07.054536 Total UI for P1: 0, mck2ui 16
1866 20:15:07.057918 best dqsien dly found for B1: ( 0, 14, 6)
1867 20:15:07.060923 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1868 20:15:07.064241 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1869 20:15:07.064323
1870 20:15:07.067925 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1871 20:15:07.071070 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1872 20:15:07.074516 [Gating] SW calibration Done
1873 20:15:07.074598 ==
1874 20:15:07.077633 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 20:15:07.084310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 20:15:07.084392 ==
1877 20:15:07.084457 RX Vref Scan: 0
1878 20:15:07.084517
1879 20:15:07.088080 RX Vref 0 -> 0, step: 1
1880 20:15:07.088161
1881 20:15:07.091241 RX Delay -130 -> 252, step: 16
1882 20:15:07.094360 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1883 20:15:07.097387 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1884 20:15:07.101006 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1885 20:15:07.104165 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1886 20:15:07.110603 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1887 20:15:07.113780 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1888 20:15:07.117384 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1889 20:15:07.120638 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1890 20:15:07.123766 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1891 20:15:07.130559 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1892 20:15:07.134166 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1893 20:15:07.137243 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1894 20:15:07.140654 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1895 20:15:07.147288 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1896 20:15:07.150749 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1897 20:15:07.153851 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1898 20:15:07.153932 ==
1899 20:15:07.157048 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 20:15:07.160519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 20:15:07.160601 ==
1902 20:15:07.164021 DQS Delay:
1903 20:15:07.164102 DQS0 = 0, DQS1 = 0
1904 20:15:07.167246 DQM Delay:
1905 20:15:07.167327 DQM0 = 85, DQM1 = 84
1906 20:15:07.167430 DQ Delay:
1907 20:15:07.170291 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1908 20:15:07.173923 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1909 20:15:07.176859 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1910 20:15:07.180035 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1911 20:15:07.180117
1912 20:15:07.183167
1913 20:15:07.183247 ==
1914 20:15:07.187354 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 20:15:07.190514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 20:15:07.190595 ==
1917 20:15:07.190659
1918 20:15:07.190719
1919 20:15:07.193694 TX Vref Scan disable
1920 20:15:07.193775 == TX Byte 0 ==
1921 20:15:07.200258 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1922 20:15:07.203541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1923 20:15:07.203623 == TX Byte 1 ==
1924 20:15:07.210180 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1925 20:15:07.213547 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1926 20:15:07.213628 ==
1927 20:15:07.216461 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 20:15:07.220174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 20:15:07.220299 ==
1930 20:15:07.234052 TX Vref=22, minBit 1, minWin=26, winSum=442
1931 20:15:07.237194 TX Vref=24, minBit 1, minWin=26, winSum=444
1932 20:15:07.240547 TX Vref=26, minBit 1, minWin=27, winSum=451
1933 20:15:07.244312 TX Vref=28, minBit 3, minWin=27, winSum=455
1934 20:15:07.247188 TX Vref=30, minBit 3, minWin=27, winSum=455
1935 20:15:07.253815 TX Vref=32, minBit 3, minWin=27, winSum=454
1936 20:15:07.257461 [TxChooseVref] Worse bit 3, Min win 27, Win sum 455, Final Vref 28
1937 20:15:07.257583
1938 20:15:07.260548 Final TX Range 1 Vref 28
1939 20:15:07.260631
1940 20:15:07.260695 ==
1941 20:15:07.263966 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 20:15:07.267211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 20:15:07.267317 ==
1944 20:15:07.270864
1945 20:15:07.270945
1946 20:15:07.271010 TX Vref Scan disable
1947 20:15:07.273924 == TX Byte 0 ==
1948 20:15:07.277178 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1949 20:15:07.280369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1950 20:15:07.284608 == TX Byte 1 ==
1951 20:15:07.287269 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1952 20:15:07.293880 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1953 20:15:07.293962
1954 20:15:07.294043 [DATLAT]
1955 20:15:07.294148 Freq=800, CH1 RK1
1956 20:15:07.294208
1957 20:15:07.296878 DATLAT Default: 0xa
1958 20:15:07.296959 0, 0xFFFF, sum = 0
1959 20:15:07.300324 1, 0xFFFF, sum = 0
1960 20:15:07.300430 2, 0xFFFF, sum = 0
1961 20:15:07.303554 3, 0xFFFF, sum = 0
1962 20:15:07.306837 4, 0xFFFF, sum = 0
1963 20:15:07.306920 5, 0xFFFF, sum = 0
1964 20:15:07.310223 6, 0xFFFF, sum = 0
1965 20:15:07.310306 7, 0xFFFF, sum = 0
1966 20:15:07.313728 8, 0xFFFF, sum = 0
1967 20:15:07.313811 9, 0x0, sum = 1
1968 20:15:07.317199 10, 0x0, sum = 2
1969 20:15:07.317282 11, 0x0, sum = 3
1970 20:15:07.317348 12, 0x0, sum = 4
1971 20:15:07.320496 best_step = 10
1972 20:15:07.320577
1973 20:15:07.320642 ==
1974 20:15:07.323842 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 20:15:07.327033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 20:15:07.327119 ==
1977 20:15:07.330306 RX Vref Scan: 0
1978 20:15:07.330387
1979 20:15:07.330452 RX Vref 0 -> 0, step: 1
1980 20:15:07.333522
1981 20:15:07.333603 RX Delay -95 -> 252, step: 8
1982 20:15:07.340554 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1983 20:15:07.344217 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1984 20:15:07.347284 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1985 20:15:07.350669 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1986 20:15:07.354375 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1987 20:15:07.360646 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1988 20:15:07.363794 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1989 20:15:07.367249 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1990 20:15:07.370723 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1991 20:15:07.373757 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1992 20:15:07.380412 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1993 20:15:07.383422 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1994 20:15:07.386985 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1995 20:15:07.390279 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1996 20:15:07.396696 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1997 20:15:07.400248 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1998 20:15:07.400369 ==
1999 20:15:07.403233 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 20:15:07.406505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 20:15:07.406625 ==
2002 20:15:07.409871 DQS Delay:
2003 20:15:07.409991 DQS0 = 0, DQS1 = 0
2004 20:15:07.410099 DQM Delay:
2005 20:15:07.413024 DQM0 = 87, DQM1 = 84
2006 20:15:07.413144 DQ Delay:
2007 20:15:07.416212 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2008 20:15:07.420129 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2009 20:15:07.423190 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
2010 20:15:07.426579 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =88
2011 20:15:07.426698
2012 20:15:07.426808
2013 20:15:07.436700 [DQSOSCAuto] RK1, (LSB)MR18= 0x1935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2014 20:15:07.436824 CH1 RK1: MR19=606, MR18=1935
2015 20:15:07.442948 CH1_RK1: MR19=0x606, MR18=0x1935, DQSOSC=396, MR23=63, INC=94, DEC=62
2016 20:15:07.446446 [RxdqsGatingPostProcess] freq 800
2017 20:15:07.453213 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 20:15:07.456864 Pre-setting of DQS Precalculation
2019 20:15:07.459583 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 20:15:07.469740 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 20:15:07.476117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 20:15:07.476200
2023 20:15:07.476265
2024 20:15:07.479497 [Calibration Summary] 1600 Mbps
2025 20:15:07.479578 CH 0, Rank 0
2026 20:15:07.483198 SW Impedance : PASS
2027 20:15:07.483297 DUTY Scan : NO K
2028 20:15:07.486154 ZQ Calibration : PASS
2029 20:15:07.489599 Jitter Meter : NO K
2030 20:15:07.489680 CBT Training : PASS
2031 20:15:07.493279 Write leveling : PASS
2032 20:15:07.496116 RX DQS gating : PASS
2033 20:15:07.496197 RX DQ/DQS(RDDQC) : PASS
2034 20:15:07.500007 TX DQ/DQS : PASS
2035 20:15:07.500089 RX DATLAT : PASS
2036 20:15:07.502941 RX DQ/DQS(Engine): PASS
2037 20:15:07.506079 TX OE : NO K
2038 20:15:07.506161 All Pass.
2039 20:15:07.506226
2040 20:15:07.506286 CH 0, Rank 1
2041 20:15:07.509541 SW Impedance : PASS
2042 20:15:07.512891 DUTY Scan : NO K
2043 20:15:07.512971 ZQ Calibration : PASS
2044 20:15:07.516335 Jitter Meter : NO K
2045 20:15:07.519308 CBT Training : PASS
2046 20:15:07.519423 Write leveling : PASS
2047 20:15:07.522852 RX DQS gating : PASS
2048 20:15:07.526142 RX DQ/DQS(RDDQC) : PASS
2049 20:15:07.526223 TX DQ/DQS : PASS
2050 20:15:07.529471 RX DATLAT : PASS
2051 20:15:07.532525 RX DQ/DQS(Engine): PASS
2052 20:15:07.532606 TX OE : NO K
2053 20:15:07.536110 All Pass.
2054 20:15:07.536191
2055 20:15:07.536256 CH 1, Rank 0
2056 20:15:07.539317 SW Impedance : PASS
2057 20:15:07.539451 DUTY Scan : NO K
2058 20:15:07.542675 ZQ Calibration : PASS
2059 20:15:07.545996 Jitter Meter : NO K
2060 20:15:07.546077 CBT Training : PASS
2061 20:15:07.549791 Write leveling : PASS
2062 20:15:07.549872 RX DQS gating : PASS
2063 20:15:07.552728 RX DQ/DQS(RDDQC) : PASS
2064 20:15:07.556176 TX DQ/DQS : PASS
2065 20:15:07.556257 RX DATLAT : PASS
2066 20:15:07.559407 RX DQ/DQS(Engine): PASS
2067 20:15:07.562740 TX OE : NO K
2068 20:15:07.562821 All Pass.
2069 20:15:07.562886
2070 20:15:07.562946 CH 1, Rank 1
2071 20:15:07.566247 SW Impedance : PASS
2072 20:15:07.569482 DUTY Scan : NO K
2073 20:15:07.569563 ZQ Calibration : PASS
2074 20:15:07.572891 Jitter Meter : NO K
2075 20:15:07.576271 CBT Training : PASS
2076 20:15:07.576352 Write leveling : PASS
2077 20:15:07.579275 RX DQS gating : PASS
2078 20:15:07.582955 RX DQ/DQS(RDDQC) : PASS
2079 20:15:07.583036 TX DQ/DQS : PASS
2080 20:15:07.586400 RX DATLAT : PASS
2081 20:15:07.589213 RX DQ/DQS(Engine): PASS
2082 20:15:07.589294 TX OE : NO K
2083 20:15:07.592442 All Pass.
2084 20:15:07.592522
2085 20:15:07.592587 DramC Write-DBI off
2086 20:15:07.596906 PER_BANK_REFRESH: Hybrid Mode
2087 20:15:07.596989 TX_TRACKING: ON
2088 20:15:07.599353 [GetDramInforAfterCalByMRR] Vendor 6.
2089 20:15:07.605842 [GetDramInforAfterCalByMRR] Revision 606.
2090 20:15:07.609021 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 20:15:07.609145 MR0 0x3b3b
2092 20:15:07.609252 MR8 0x5151
2093 20:15:07.612252 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 20:15:07.612371
2095 20:15:07.615423 MR0 0x3b3b
2096 20:15:07.615505 MR8 0x5151
2097 20:15:07.618845 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 20:15:07.618927
2099 20:15:07.628833 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 20:15:07.631930 [FAST_K] Save calibration result to emmc
2101 20:15:07.635581 [FAST_K] Save calibration result to emmc
2102 20:15:07.638908 dram_init: config_dvfs: 1
2103 20:15:07.641979 dramc_set_vcore_voltage set vcore to 662500
2104 20:15:07.645139 Read voltage for 1200, 2
2105 20:15:07.645220 Vio18 = 0
2106 20:15:07.645285 Vcore = 662500
2107 20:15:07.648741 Vdram = 0
2108 20:15:07.648821 Vddq = 0
2109 20:15:07.648886 Vmddr = 0
2110 20:15:07.655526 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 20:15:07.658619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 20:15:07.662034 MEM_TYPE=3, freq_sel=15
2113 20:15:07.665228 sv_algorithm_assistance_LP4_1600
2114 20:15:07.668829 ============ PULL DRAM RESETB DOWN ============
2115 20:15:07.671798 ========== PULL DRAM RESETB DOWN end =========
2116 20:15:07.678573 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 20:15:07.681673 ===================================
2118 20:15:07.684876 LPDDR4 DRAM CONFIGURATION
2119 20:15:07.688203 ===================================
2120 20:15:07.688329 EX_ROW_EN[0] = 0x0
2121 20:15:07.691390 EX_ROW_EN[1] = 0x0
2122 20:15:07.691488 LP4Y_EN = 0x0
2123 20:15:07.695181 WORK_FSP = 0x0
2124 20:15:07.695267 WL = 0x4
2125 20:15:07.697802 RL = 0x4
2126 20:15:07.697884 BL = 0x2
2127 20:15:07.701344 RPST = 0x0
2128 20:15:07.701426 RD_PRE = 0x0
2129 20:15:07.705455 WR_PRE = 0x1
2130 20:15:07.705537 WR_PST = 0x0
2131 20:15:07.708107 DBI_WR = 0x0
2132 20:15:07.708189 DBI_RD = 0x0
2133 20:15:07.711524 OTF = 0x1
2134 20:15:07.714455 ===================================
2135 20:15:07.718108 ===================================
2136 20:15:07.718191 ANA top config
2137 20:15:07.721564 ===================================
2138 20:15:07.724433 DLL_ASYNC_EN = 0
2139 20:15:07.727847 ALL_SLAVE_EN = 0
2140 20:15:07.731182 NEW_RANK_MODE = 1
2141 20:15:07.734407 DLL_IDLE_MODE = 1
2142 20:15:07.734490 LP45_APHY_COMB_EN = 1
2143 20:15:07.738003 TX_ODT_DIS = 1
2144 20:15:07.741026 NEW_8X_MODE = 1
2145 20:15:07.744453 ===================================
2146 20:15:07.747974 ===================================
2147 20:15:07.751089 data_rate = 2400
2148 20:15:07.754905 CKR = 1
2149 20:15:07.754988 DQ_P2S_RATIO = 8
2150 20:15:07.758029 ===================================
2151 20:15:07.761000 CA_P2S_RATIO = 8
2152 20:15:07.764296 DQ_CA_OPEN = 0
2153 20:15:07.767533 DQ_SEMI_OPEN = 0
2154 20:15:07.771230 CA_SEMI_OPEN = 0
2155 20:15:07.774276 CA_FULL_RATE = 0
2156 20:15:07.774358 DQ_CKDIV4_EN = 0
2157 20:15:07.777764 CA_CKDIV4_EN = 0
2158 20:15:07.781128 CA_PREDIV_EN = 0
2159 20:15:07.784238 PH8_DLY = 17
2160 20:15:07.787903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 20:15:07.791284 DQ_AAMCK_DIV = 4
2162 20:15:07.791388 CA_AAMCK_DIV = 4
2163 20:15:07.794391 CA_ADMCK_DIV = 4
2164 20:15:07.797730 DQ_TRACK_CA_EN = 0
2165 20:15:07.801055 CA_PICK = 1200
2166 20:15:07.804475 CA_MCKIO = 1200
2167 20:15:07.807704 MCKIO_SEMI = 0
2168 20:15:07.810808 PLL_FREQ = 2366
2169 20:15:07.810889 DQ_UI_PI_RATIO = 32
2170 20:15:07.814099 CA_UI_PI_RATIO = 0
2171 20:15:07.817640 ===================================
2172 20:15:07.821238 ===================================
2173 20:15:07.824513 memory_type:LPDDR4
2174 20:15:07.827795 GP_NUM : 10
2175 20:15:07.827876 SRAM_EN : 1
2176 20:15:07.830637 MD32_EN : 0
2177 20:15:07.834256 ===================================
2178 20:15:07.837610 [ANA_INIT] >>>>>>>>>>>>>>
2179 20:15:07.837692 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 20:15:07.840594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 20:15:07.843653 ===================================
2182 20:15:07.847187 data_rate = 2400,PCW = 0X5b00
2183 20:15:07.850792 ===================================
2184 20:15:07.853916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 20:15:07.860360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 20:15:07.866975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 20:15:07.870560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 20:15:07.873940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 20:15:07.876980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 20:15:07.880018 [ANA_INIT] flow start
2191 20:15:07.880099 [ANA_INIT] PLL >>>>>>>>
2192 20:15:07.883614 [ANA_INIT] PLL <<<<<<<<
2193 20:15:07.886658 [ANA_INIT] MIDPI >>>>>>>>
2194 20:15:07.890331 [ANA_INIT] MIDPI <<<<<<<<
2195 20:15:07.890412 [ANA_INIT] DLL >>>>>>>>
2196 20:15:07.893312 [ANA_INIT] DLL <<<<<<<<
2197 20:15:07.896556 [ANA_INIT] flow end
2198 20:15:07.900098 ============ LP4 DIFF to SE enter ============
2199 20:15:07.903515 ============ LP4 DIFF to SE exit ============
2200 20:15:07.906213 [ANA_INIT] <<<<<<<<<<<<<
2201 20:15:07.909925 [Flow] Enable top DCM control >>>>>
2202 20:15:07.912732 [Flow] Enable top DCM control <<<<<
2203 20:15:07.916167 Enable DLL master slave shuffle
2204 20:15:07.919473 ==============================================================
2205 20:15:07.922690 Gating Mode config
2206 20:15:07.929552 ==============================================================
2207 20:15:07.929634 Config description:
2208 20:15:07.939602 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 20:15:07.946030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 20:15:07.949632 SELPH_MODE 0: By rank 1: By Phase
2211 20:15:07.956347 ==============================================================
2212 20:15:07.959658 GAT_TRACK_EN = 1
2213 20:15:07.963372 RX_GATING_MODE = 2
2214 20:15:07.967000 RX_GATING_TRACK_MODE = 2
2215 20:15:07.969251 SELPH_MODE = 1
2216 20:15:07.972610 PICG_EARLY_EN = 1
2217 20:15:07.976162 VALID_LAT_VALUE = 1
2218 20:15:07.979253 ==============================================================
2219 20:15:07.982608 Enter into Gating configuration >>>>
2220 20:15:07.985971 Exit from Gating configuration <<<<
2221 20:15:07.989584 Enter into DVFS_PRE_config >>>>>
2222 20:15:08.002306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 20:15:08.002431 Exit from DVFS_PRE_config <<<<<
2224 20:15:08.005790 Enter into PICG configuration >>>>
2225 20:15:08.009043 Exit from PICG configuration <<<<
2226 20:15:08.012679 [RX_INPUT] configuration >>>>>
2227 20:15:08.015589 [RX_INPUT] configuration <<<<<
2228 20:15:08.022356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 20:15:08.025542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 20:15:08.032588 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 20:15:08.039542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 20:15:08.045528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 20:15:08.052306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 20:15:08.055691 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 20:15:08.058882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 20:15:08.062278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 20:15:08.068894 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 20:15:08.072359 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 20:15:08.075501 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 20:15:08.079199 ===================================
2241 20:15:08.082407 LPDDR4 DRAM CONFIGURATION
2242 20:15:08.085137 ===================================
2243 20:15:08.088814 EX_ROW_EN[0] = 0x0
2244 20:15:08.088897 EX_ROW_EN[1] = 0x0
2245 20:15:08.092058 LP4Y_EN = 0x0
2246 20:15:08.092137 WORK_FSP = 0x0
2247 20:15:08.095115 WL = 0x4
2248 20:15:08.095233 RL = 0x4
2249 20:15:08.098420 BL = 0x2
2250 20:15:08.098531 RPST = 0x0
2251 20:15:08.101893 RD_PRE = 0x0
2252 20:15:08.101970 WR_PRE = 0x1
2253 20:15:08.105302 WR_PST = 0x0
2254 20:15:08.105376 DBI_WR = 0x0
2255 20:15:08.108812 DBI_RD = 0x0
2256 20:15:08.108898 OTF = 0x1
2257 20:15:08.111974 ===================================
2258 20:15:08.115263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 20:15:08.121942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 20:15:08.125240 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 20:15:08.128427 ===================================
2262 20:15:08.131633 LPDDR4 DRAM CONFIGURATION
2263 20:15:08.135106 ===================================
2264 20:15:08.135187 EX_ROW_EN[0] = 0x10
2265 20:15:08.138392 EX_ROW_EN[1] = 0x0
2266 20:15:08.141922 LP4Y_EN = 0x0
2267 20:15:08.142005 WORK_FSP = 0x0
2268 20:15:08.144924 WL = 0x4
2269 20:15:08.145010 RL = 0x4
2270 20:15:08.148256 BL = 0x2
2271 20:15:08.148338 RPST = 0x0
2272 20:15:08.151702 RD_PRE = 0x0
2273 20:15:08.151784 WR_PRE = 0x1
2274 20:15:08.154976 WR_PST = 0x0
2275 20:15:08.155058 DBI_WR = 0x0
2276 20:15:08.158445 DBI_RD = 0x0
2277 20:15:08.158527 OTF = 0x1
2278 20:15:08.161499 ===================================
2279 20:15:08.168082 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 20:15:08.168165 ==
2281 20:15:08.171729 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 20:15:08.174602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 20:15:08.178048 ==
2284 20:15:08.178130 [Duty_Offset_Calibration]
2285 20:15:08.181150 B0:2 B1:0 CA:4
2286 20:15:08.181232
2287 20:15:08.184819 [DutyScan_Calibration_Flow] k_type=0
2288 20:15:08.192253
2289 20:15:08.192339 ==CLK 0==
2290 20:15:08.195983 Final CLK duty delay cell = -4
2291 20:15:08.199150 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2292 20:15:08.202245 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2293 20:15:08.205583 [-4] AVG Duty = 4937%(X100)
2294 20:15:08.205667
2295 20:15:08.208782 CH0 CLK Duty spec in!! Max-Min= 187%
2296 20:15:08.212647 [DutyScan_Calibration_Flow] ====Done====
2297 20:15:08.212729
2298 20:15:08.215763 [DutyScan_Calibration_Flow] k_type=1
2299 20:15:08.232102
2300 20:15:08.232185 ==DQS 0 ==
2301 20:15:08.235483 Final DQS duty delay cell = 0
2302 20:15:08.238668 [0] MAX Duty = 5156%(X100), DQS PI = 18
2303 20:15:08.242355 [0] MIN Duty = 5093%(X100), DQS PI = 2
2304 20:15:08.242436 [0] AVG Duty = 5124%(X100)
2305 20:15:08.245385
2306 20:15:08.245465 ==DQS 1 ==
2307 20:15:08.248884 Final DQS duty delay cell = 0
2308 20:15:08.252029 [0] MAX Duty = 5125%(X100), DQS PI = 4
2309 20:15:08.255206 [0] MIN Duty = 5000%(X100), DQS PI = 0
2310 20:15:08.255286 [0] AVG Duty = 5062%(X100)
2311 20:15:08.258469
2312 20:15:08.261884 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2313 20:15:08.261964
2314 20:15:08.265181 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2315 20:15:08.268490 [DutyScan_Calibration_Flow] ====Done====
2316 20:15:08.268570
2317 20:15:08.271825 [DutyScan_Calibration_Flow] k_type=3
2318 20:15:08.288104
2319 20:15:08.288185 ==DQM 0 ==
2320 20:15:08.291726 Final DQM duty delay cell = 0
2321 20:15:08.295050 [0] MAX Duty = 5125%(X100), DQS PI = 20
2322 20:15:08.298396 [0] MIN Duty = 4844%(X100), DQS PI = 50
2323 20:15:08.301296 [0] AVG Duty = 4984%(X100)
2324 20:15:08.301400
2325 20:15:08.301465 ==DQM 1 ==
2326 20:15:08.304657 Final DQM duty delay cell = 0
2327 20:15:08.307917 [0] MAX Duty = 4969%(X100), DQS PI = 2
2328 20:15:08.311535 [0] MIN Duty = 4875%(X100), DQS PI = 20
2329 20:15:08.315039 [0] AVG Duty = 4922%(X100)
2330 20:15:08.315115
2331 20:15:08.318372 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2332 20:15:08.318459
2333 20:15:08.321616 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2334 20:15:08.324573 [DutyScan_Calibration_Flow] ====Done====
2335 20:15:08.324657
2336 20:15:08.327553 [DutyScan_Calibration_Flow] k_type=2
2337 20:15:08.344458
2338 20:15:08.344536 ==DQ 0 ==
2339 20:15:08.347901 Final DQ duty delay cell = 0
2340 20:15:08.351728 [0] MAX Duty = 5125%(X100), DQS PI = 18
2341 20:15:08.354530 [0] MIN Duty = 5000%(X100), DQS PI = 8
2342 20:15:08.354605 [0] AVG Duty = 5062%(X100)
2343 20:15:08.354666
2344 20:15:08.359874 ==DQ 1 ==
2345 20:15:08.361930 Final DQ duty delay cell = 0
2346 20:15:08.364512 [0] MAX Duty = 5156%(X100), DQS PI = 6
2347 20:15:08.368211 [0] MIN Duty = 4938%(X100), DQS PI = 14
2348 20:15:08.368289 [0] AVG Duty = 5047%(X100)
2349 20:15:08.368352
2350 20:15:08.371237 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2351 20:15:08.371302
2352 20:15:08.378041 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2353 20:15:08.381487 [DutyScan_Calibration_Flow] ====Done====
2354 20:15:08.381571 ==
2355 20:15:08.384822 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 20:15:08.387837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 20:15:08.387921 ==
2358 20:15:08.391270 [Duty_Offset_Calibration]
2359 20:15:08.391349 B0:0 B1:-1 CA:3
2360 20:15:08.391438
2361 20:15:08.394611 [DutyScan_Calibration_Flow] k_type=0
2362 20:15:08.403656
2363 20:15:08.403734 ==CLK 0==
2364 20:15:08.407061 Final CLK duty delay cell = -4
2365 20:15:08.410544 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2366 20:15:08.413895 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2367 20:15:08.417157 [-4] AVG Duty = 4938%(X100)
2368 20:15:08.417232
2369 20:15:08.420356 CH1 CLK Duty spec in!! Max-Min= 124%
2370 20:15:08.423271 [DutyScan_Calibration_Flow] ====Done====
2371 20:15:08.423346
2372 20:15:08.426766 [DutyScan_Calibration_Flow] k_type=1
2373 20:15:08.442528
2374 20:15:08.442618 ==DQS 0 ==
2375 20:15:08.445640 Final DQS duty delay cell = 0
2376 20:15:08.450022 [0] MAX Duty = 5156%(X100), DQS PI = 28
2377 20:15:08.452299 [0] MIN Duty = 4907%(X100), DQS PI = 38
2378 20:15:08.455367 [0] AVG Duty = 5031%(X100)
2379 20:15:08.455450
2380 20:15:08.455512 ==DQS 1 ==
2381 20:15:08.459303 Final DQS duty delay cell = -4
2382 20:15:08.462467 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2383 20:15:08.465785 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2384 20:15:08.469287 [-4] AVG Duty = 4937%(X100)
2385 20:15:08.469360
2386 20:15:08.472519 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2387 20:15:08.472598
2388 20:15:08.475589 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2389 20:15:08.478620 [DutyScan_Calibration_Flow] ====Done====
2390 20:15:08.478713
2391 20:15:08.482198 [DutyScan_Calibration_Flow] k_type=3
2392 20:15:08.499202
2393 20:15:08.499299 ==DQM 0 ==
2394 20:15:08.502421 Final DQM duty delay cell = 0
2395 20:15:08.505820 [0] MAX Duty = 5031%(X100), DQS PI = 28
2396 20:15:08.509241 [0] MIN Duty = 4813%(X100), DQS PI = 38
2397 20:15:08.512542 [0] AVG Duty = 4922%(X100)
2398 20:15:08.512624
2399 20:15:08.512708 ==DQM 1 ==
2400 20:15:08.515807 Final DQM duty delay cell = 0
2401 20:15:08.519174 [0] MAX Duty = 5000%(X100), DQS PI = 34
2402 20:15:08.522672 [0] MIN Duty = 4844%(X100), DQS PI = 0
2403 20:15:08.525714 [0] AVG Duty = 4922%(X100)
2404 20:15:08.525793
2405 20:15:08.529034 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2406 20:15:08.529121
2407 20:15:08.532443 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 20:15:08.535776 [DutyScan_Calibration_Flow] ====Done====
2409 20:15:08.535855
2410 20:15:08.538905 [DutyScan_Calibration_Flow] k_type=2
2411 20:15:08.554956
2412 20:15:08.555042 ==DQ 0 ==
2413 20:15:08.558202 Final DQ duty delay cell = -4
2414 20:15:08.561641 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2415 20:15:08.565275 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2416 20:15:08.568789 [-4] AVG Duty = 4937%(X100)
2417 20:15:08.568865
2418 20:15:08.568946 ==DQ 1 ==
2419 20:15:08.571615 Final DQ duty delay cell = 0
2420 20:15:08.575343 [0] MAX Duty = 5031%(X100), DQS PI = 32
2421 20:15:08.578653 [0] MIN Duty = 4844%(X100), DQS PI = 62
2422 20:15:08.578736 [0] AVG Duty = 4937%(X100)
2423 20:15:08.581901
2424 20:15:08.585606 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2425 20:15:08.585686
2426 20:15:08.588400 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2427 20:15:08.591562 [DutyScan_Calibration_Flow] ====Done====
2428 20:15:08.594967 nWR fixed to 30
2429 20:15:08.595043 [ModeRegInit_LP4] CH0 RK0
2430 20:15:08.598275 [ModeRegInit_LP4] CH0 RK1
2431 20:15:08.601677 [ModeRegInit_LP4] CH1 RK0
2432 20:15:08.605555 [ModeRegInit_LP4] CH1 RK1
2433 20:15:08.605670 match AC timing 7
2434 20:15:08.611737 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 20:15:08.614677 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 20:15:08.618687 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 20:15:08.624848 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 20:15:08.627904 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 20:15:08.627989 ==
2440 20:15:08.631245 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 20:15:08.634914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 20:15:08.635013 ==
2443 20:15:08.641264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 20:15:08.648045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 20:15:08.655558 [CA 0] Center 39 (9~70) winsize 62
2446 20:15:08.658543 [CA 1] Center 39 (9~70) winsize 62
2447 20:15:08.661944 [CA 2] Center 35 (5~66) winsize 62
2448 20:15:08.665440 [CA 3] Center 35 (5~66) winsize 62
2449 20:15:08.668679 [CA 4] Center 33 (3~64) winsize 62
2450 20:15:08.671789 [CA 5] Center 33 (3~64) winsize 62
2451 20:15:08.671878
2452 20:15:08.675307 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2453 20:15:08.675425
2454 20:15:08.679164 [CATrainingPosCal] consider 1 rank data
2455 20:15:08.682142 u2DelayCellTimex100 = 270/100 ps
2456 20:15:08.685179 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2457 20:15:08.692307 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2458 20:15:08.695196 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 20:15:08.698687 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2460 20:15:08.701483 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2461 20:15:08.704824 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2462 20:15:08.704894
2463 20:15:08.708301 CA PerBit enable=1, Macro0, CA PI delay=33
2464 20:15:08.708373
2465 20:15:08.711829 [CBTSetCACLKResult] CA Dly = 33
2466 20:15:08.715111 CS Dly: 7 (0~38)
2467 20:15:08.715215 ==
2468 20:15:08.718404 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 20:15:08.721949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 20:15:08.722026 ==
2471 20:15:08.725117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 20:15:08.731831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 20:15:08.741207 [CA 0] Center 39 (9~70) winsize 62
2474 20:15:08.744677 [CA 1] Center 39 (9~70) winsize 62
2475 20:15:08.748149 [CA 2] Center 35 (5~66) winsize 62
2476 20:15:08.751158 [CA 3] Center 35 (5~66) winsize 62
2477 20:15:08.754381 [CA 4] Center 34 (4~65) winsize 62
2478 20:15:08.758738 [CA 5] Center 33 (3~63) winsize 61
2479 20:15:08.758810
2480 20:15:08.761294 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 20:15:08.761367
2482 20:15:08.764551 [CATrainingPosCal] consider 2 rank data
2483 20:15:08.768430 u2DelayCellTimex100 = 270/100 ps
2484 20:15:08.770944 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 20:15:08.774259 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 20:15:08.781058 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 20:15:08.784343 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 20:15:08.787791 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2489 20:15:08.790860 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 20:15:08.790962
2491 20:15:08.794583 CA PerBit enable=1, Macro0, CA PI delay=33
2492 20:15:08.794660
2493 20:15:08.798298 [CBTSetCACLKResult] CA Dly = 33
2494 20:15:08.798404 CS Dly: 8 (0~41)
2495 20:15:08.798494
2496 20:15:08.801099 ----->DramcWriteLeveling(PI) begin...
2497 20:15:08.804401 ==
2498 20:15:08.807481 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 20:15:08.810740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 20:15:08.810814 ==
2501 20:15:08.814280 Write leveling (Byte 0): 30 => 30
2502 20:15:08.817423 Write leveling (Byte 1): 27 => 27
2503 20:15:08.820753 DramcWriteLeveling(PI) end<-----
2504 20:15:08.820827
2505 20:15:08.820897 ==
2506 20:15:08.824135 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 20:15:08.827587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 20:15:08.827695 ==
2509 20:15:08.831099 [Gating] SW mode calibration
2510 20:15:08.837241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 20:15:08.843904 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 20:15:08.847294 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2513 20:15:08.850871 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2514 20:15:08.857139 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 20:15:08.860454 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 20:15:08.864170 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 20:15:08.870274 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 20:15:08.873792 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2519 20:15:08.876727 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2520 20:15:08.883630 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
2521 20:15:08.887310 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 20:15:08.890280 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 20:15:08.896955 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 20:15:08.899976 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 20:15:08.903615 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 20:15:08.910318 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2527 20:15:08.913615 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2528 20:15:08.916640 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2529 20:15:08.923381 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2530 20:15:08.926449 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 20:15:08.930077 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 20:15:08.933717 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 20:15:08.939805 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 20:15:08.942983 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 20:15:08.946626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 20:15:08.953141 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 20:15:08.956549 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 20:15:08.959678 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 20:15:08.966532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 20:15:08.969707 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 20:15:08.973039 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 20:15:08.979788 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 20:15:08.983169 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 20:15:08.986173 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 20:15:08.993469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 20:15:08.996488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 20:15:08.999472 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 20:15:09.006064 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 20:15:09.009349 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 20:15:09.012965 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 20:15:09.019502 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 20:15:09.022916 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 20:15:09.025968 Total UI for P1: 0, mck2ui 16
2554 20:15:09.029800 best dqsien dly found for B0: ( 1, 3, 28)
2555 20:15:09.032964 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 20:15:09.035954 Total UI for P1: 0, mck2ui 16
2557 20:15:09.039828 best dqsien dly found for B1: ( 1, 4, 0)
2558 20:15:09.042471 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2559 20:15:09.046251 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2560 20:15:09.046330
2561 20:15:09.052385 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2562 20:15:09.056372 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2563 20:15:09.056447 [Gating] SW calibration Done
2564 20:15:09.058990 ==
2565 20:15:09.062744 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 20:15:09.065613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 20:15:09.065715 ==
2568 20:15:09.065782 RX Vref Scan: 0
2569 20:15:09.065842
2570 20:15:09.068929 RX Vref 0 -> 0, step: 1
2571 20:15:09.069011
2572 20:15:09.072493 RX Delay -40 -> 252, step: 8
2573 20:15:09.075571 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2574 20:15:09.079200 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2575 20:15:09.085656 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 20:15:09.088815 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2577 20:15:09.092458 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 20:15:09.095915 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2579 20:15:09.099333 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 20:15:09.102384 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2581 20:15:09.109052 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2582 20:15:09.112225 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2583 20:15:09.115614 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2584 20:15:09.118693 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2585 20:15:09.122434 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2586 20:15:09.128732 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2587 20:15:09.132193 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2588 20:15:09.135605 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2589 20:15:09.135728 ==
2590 20:15:09.139090 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 20:15:09.142199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 20:15:09.145045 ==
2593 20:15:09.145166 DQS Delay:
2594 20:15:09.145279 DQS0 = 0, DQS1 = 0
2595 20:15:09.148486 DQM Delay:
2596 20:15:09.148608 DQM0 = 118, DQM1 = 107
2597 20:15:09.152197 DQ Delay:
2598 20:15:09.155101 DQ0 =115, DQ1 =115, DQ2 =119, DQ3 =111
2599 20:15:09.158402 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2600 20:15:09.161964 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2601 20:15:09.165331 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2602 20:15:09.165469
2603 20:15:09.165671
2604 20:15:09.165818 ==
2605 20:15:09.168705 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 20:15:09.172011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 20:15:09.172089 ==
2608 20:15:09.172163
2609 20:15:09.175019
2610 20:15:09.175159 TX Vref Scan disable
2611 20:15:09.178181 == TX Byte 0 ==
2612 20:15:09.181608 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2613 20:15:09.184864 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2614 20:15:09.188278 == TX Byte 1 ==
2615 20:15:09.191613 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2616 20:15:09.195022 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2617 20:15:09.195135 ==
2618 20:15:09.198545 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 20:15:09.204831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 20:15:09.204918 ==
2621 20:15:09.215812 TX Vref=22, minBit 5, minWin=24, winSum=405
2622 20:15:09.219113 TX Vref=24, minBit 4, minWin=25, winSum=415
2623 20:15:09.222187 TX Vref=26, minBit 3, minWin=25, winSum=418
2624 20:15:09.225653 TX Vref=28, minBit 0, minWin=26, winSum=424
2625 20:15:09.228854 TX Vref=30, minBit 5, minWin=25, winSum=426
2626 20:15:09.235682 TX Vref=32, minBit 0, minWin=26, winSum=426
2627 20:15:09.238718 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 32
2628 20:15:09.238807
2629 20:15:09.242458 Final TX Range 1 Vref 32
2630 20:15:09.242535
2631 20:15:09.242624 ==
2632 20:15:09.245478 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 20:15:09.248808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 20:15:09.248886 ==
2635 20:15:09.252247
2636 20:15:09.252334
2637 20:15:09.252396 TX Vref Scan disable
2638 20:15:09.255806 == TX Byte 0 ==
2639 20:15:09.258928 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2640 20:15:09.262333 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2641 20:15:09.265201 == TX Byte 1 ==
2642 20:15:09.268803 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 20:15:09.275760 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 20:15:09.275839
2645 20:15:09.275912 [DATLAT]
2646 20:15:09.275973 Freq=1200, CH0 RK0
2647 20:15:09.276032
2648 20:15:09.278716 DATLAT Default: 0xd
2649 20:15:09.278802 0, 0xFFFF, sum = 0
2650 20:15:09.281966 1, 0xFFFF, sum = 0
2651 20:15:09.285045 2, 0xFFFF, sum = 0
2652 20:15:09.285139 3, 0xFFFF, sum = 0
2653 20:15:09.289152 4, 0xFFFF, sum = 0
2654 20:15:09.289231 5, 0xFFFF, sum = 0
2655 20:15:09.291851 6, 0xFFFF, sum = 0
2656 20:15:09.291930 7, 0xFFFF, sum = 0
2657 20:15:09.295284 8, 0xFFFF, sum = 0
2658 20:15:09.295401 9, 0xFFFF, sum = 0
2659 20:15:09.298505 10, 0xFFFF, sum = 0
2660 20:15:09.298582 11, 0xFFFF, sum = 0
2661 20:15:09.301616 12, 0x0, sum = 1
2662 20:15:09.301694 13, 0x0, sum = 2
2663 20:15:09.305359 14, 0x0, sum = 3
2664 20:15:09.305438 15, 0x0, sum = 4
2665 20:15:09.305513 best_step = 13
2666 20:15:09.308691
2667 20:15:09.308769 ==
2668 20:15:09.311648 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 20:15:09.315103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 20:15:09.315187 ==
2671 20:15:09.315264 RX Vref Scan: 1
2672 20:15:09.315326
2673 20:15:09.318265 Set Vref Range= 32 -> 127
2674 20:15:09.318375
2675 20:15:09.321854 RX Vref 32 -> 127, step: 1
2676 20:15:09.321956
2677 20:15:09.324882 RX Delay -21 -> 252, step: 4
2678 20:15:09.324974
2679 20:15:09.328349 Set Vref, RX VrefLevel [Byte0]: 32
2680 20:15:09.331535 [Byte1]: 32
2681 20:15:09.331617
2682 20:15:09.334810 Set Vref, RX VrefLevel [Byte0]: 33
2683 20:15:09.338259 [Byte1]: 33
2684 20:15:09.341611
2685 20:15:09.341684 Set Vref, RX VrefLevel [Byte0]: 34
2686 20:15:09.345074 [Byte1]: 34
2687 20:15:09.349850
2688 20:15:09.349955 Set Vref, RX VrefLevel [Byte0]: 35
2689 20:15:09.353365 [Byte1]: 35
2690 20:15:09.357876
2691 20:15:09.357959 Set Vref, RX VrefLevel [Byte0]: 36
2692 20:15:09.361252 [Byte1]: 36
2693 20:15:09.365509
2694 20:15:09.365601 Set Vref, RX VrefLevel [Byte0]: 37
2695 20:15:09.369373 [Byte1]: 37
2696 20:15:09.373383
2697 20:15:09.373467 Set Vref, RX VrefLevel [Byte0]: 38
2698 20:15:09.377061 [Byte1]: 38
2699 20:15:09.381978
2700 20:15:09.382056 Set Vref, RX VrefLevel [Byte0]: 39
2701 20:15:09.384653 [Byte1]: 39
2702 20:15:09.389604
2703 20:15:09.389678 Set Vref, RX VrefLevel [Byte0]: 40
2704 20:15:09.392943 [Byte1]: 40
2705 20:15:09.397975
2706 20:15:09.398059 Set Vref, RX VrefLevel [Byte0]: 41
2707 20:15:09.400523 [Byte1]: 41
2708 20:15:09.405154
2709 20:15:09.405230 Set Vref, RX VrefLevel [Byte0]: 42
2710 20:15:09.408527 [Byte1]: 42
2711 20:15:09.413370
2712 20:15:09.416285 Set Vref, RX VrefLevel [Byte0]: 43
2713 20:15:09.419418 [Byte1]: 43
2714 20:15:09.419496
2715 20:15:09.423399 Set Vref, RX VrefLevel [Byte0]: 44
2716 20:15:09.426540 [Byte1]: 44
2717 20:15:09.426620
2718 20:15:09.429215 Set Vref, RX VrefLevel [Byte0]: 45
2719 20:15:09.432748 [Byte1]: 45
2720 20:15:09.437388
2721 20:15:09.437476 Set Vref, RX VrefLevel [Byte0]: 46
2722 20:15:09.440075 [Byte1]: 46
2723 20:15:09.444944
2724 20:15:09.445034 Set Vref, RX VrefLevel [Byte0]: 47
2725 20:15:09.447957 [Byte1]: 47
2726 20:15:09.452800
2727 20:15:09.452873 Set Vref, RX VrefLevel [Byte0]: 48
2728 20:15:09.455856 [Byte1]: 48
2729 20:15:09.460574
2730 20:15:09.460646 Set Vref, RX VrefLevel [Byte0]: 49
2731 20:15:09.464552 [Byte1]: 49
2732 20:15:09.468886
2733 20:15:09.468962 Set Vref, RX VrefLevel [Byte0]: 50
2734 20:15:09.472103 [Byte1]: 50
2735 20:15:09.476299
2736 20:15:09.476390 Set Vref, RX VrefLevel [Byte0]: 51
2737 20:15:09.480194 [Byte1]: 51
2738 20:15:09.484795
2739 20:15:09.484877 Set Vref, RX VrefLevel [Byte0]: 52
2740 20:15:09.488082 [Byte1]: 52
2741 20:15:09.492282
2742 20:15:09.492361 Set Vref, RX VrefLevel [Byte0]: 53
2743 20:15:09.495534 [Byte1]: 53
2744 20:15:09.500301
2745 20:15:09.500376 Set Vref, RX VrefLevel [Byte0]: 54
2746 20:15:09.503677 [Byte1]: 54
2747 20:15:09.508555
2748 20:15:09.508631 Set Vref, RX VrefLevel [Byte0]: 55
2749 20:15:09.514457 [Byte1]: 55
2750 20:15:09.514548
2751 20:15:09.518103 Set Vref, RX VrefLevel [Byte0]: 56
2752 20:15:09.521411 [Byte1]: 56
2753 20:15:09.521498
2754 20:15:09.524608 Set Vref, RX VrefLevel [Byte0]: 57
2755 20:15:09.527957 [Byte1]: 57
2756 20:15:09.532390
2757 20:15:09.532463 Set Vref, RX VrefLevel [Byte0]: 58
2758 20:15:09.535221 [Byte1]: 58
2759 20:15:09.539850
2760 20:15:09.539935 Set Vref, RX VrefLevel [Byte0]: 59
2761 20:15:09.543405 [Byte1]: 59
2762 20:15:09.548137
2763 20:15:09.548215 Set Vref, RX VrefLevel [Byte0]: 60
2764 20:15:09.552056 [Byte1]: 60
2765 20:15:09.555640
2766 20:15:09.555717 Set Vref, RX VrefLevel [Byte0]: 61
2767 20:15:09.559497 [Byte1]: 61
2768 20:15:09.563985
2769 20:15:09.564067 Set Vref, RX VrefLevel [Byte0]: 62
2770 20:15:09.567166 [Byte1]: 62
2771 20:15:09.571479
2772 20:15:09.571572 Set Vref, RX VrefLevel [Byte0]: 63
2773 20:15:09.574736 [Byte1]: 63
2774 20:15:09.579556
2775 20:15:09.579631 Set Vref, RX VrefLevel [Byte0]: 64
2776 20:15:09.582780 [Byte1]: 64
2777 20:15:09.587527
2778 20:15:09.587601 Set Vref, RX VrefLevel [Byte0]: 65
2779 20:15:09.590976 [Byte1]: 65
2780 20:15:09.595215
2781 20:15:09.595318 Set Vref, RX VrefLevel [Byte0]: 66
2782 20:15:09.598466 [Byte1]: 66
2783 20:15:09.603082
2784 20:15:09.603195 Set Vref, RX VrefLevel [Byte0]: 67
2785 20:15:09.606355 [Byte1]: 67
2786 20:15:09.610940
2787 20:15:09.611036 Set Vref, RX VrefLevel [Byte0]: 68
2788 20:15:09.614450 [Byte1]: 68
2789 20:15:09.619018
2790 20:15:09.619095 Set Vref, RX VrefLevel [Byte0]: 69
2791 20:15:09.622780 [Byte1]: 69
2792 20:15:09.626894
2793 20:15:09.626969 Set Vref, RX VrefLevel [Byte0]: 70
2794 20:15:09.630510 [Byte1]: 70
2795 20:15:09.634983
2796 20:15:09.635075 Final RX Vref Byte 0 = 52 to rank0
2797 20:15:09.638428 Final RX Vref Byte 1 = 59 to rank0
2798 20:15:09.641519 Final RX Vref Byte 0 = 52 to rank1
2799 20:15:09.645019 Final RX Vref Byte 1 = 59 to rank1==
2800 20:15:09.647941 Dram Type= 6, Freq= 0, CH_0, rank 0
2801 20:15:09.654709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2802 20:15:09.654793 ==
2803 20:15:09.654858 DQS Delay:
2804 20:15:09.657965 DQS0 = 0, DQS1 = 0
2805 20:15:09.658066 DQM Delay:
2806 20:15:09.658157 DQM0 = 117, DQM1 = 105
2807 20:15:09.661378 DQ Delay:
2808 20:15:09.664718 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2809 20:15:09.668040 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2810 20:15:09.671725 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2811 20:15:09.674687 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2812 20:15:09.674759
2813 20:15:09.674820
2814 20:15:09.681801 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2815 20:15:09.684856 CH0 RK0: MR19=403, MR18=1FC
2816 20:15:09.691396 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2817 20:15:09.691488
2818 20:15:09.695011 ----->DramcWriteLeveling(PI) begin...
2819 20:15:09.695103 ==
2820 20:15:09.697779 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 20:15:09.701132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 20:15:09.704878 ==
2823 20:15:09.704956 Write leveling (Byte 0): 30 => 30
2824 20:15:09.708083 Write leveling (Byte 1): 28 => 28
2825 20:15:09.711512 DramcWriteLeveling(PI) end<-----
2826 20:15:09.711589
2827 20:15:09.711652 ==
2828 20:15:09.714648 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 20:15:09.721223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 20:15:09.721300 ==
2831 20:15:09.724363 [Gating] SW mode calibration
2832 20:15:09.731179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2833 20:15:09.734291 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2834 20:15:09.741159 0 15 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
2835 20:15:09.744550 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2836 20:15:09.747903 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 20:15:09.751763 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 20:15:09.757859 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 20:15:09.761203 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 20:15:09.764493 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2841 20:15:09.770801 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
2842 20:15:09.774522 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
2843 20:15:09.777630 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 20:15:09.784239 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 20:15:09.787763 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 20:15:09.791088 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 20:15:09.797562 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 20:15:09.800650 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2849 20:15:09.804310 1 0 28 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
2850 20:15:09.811039 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2851 20:15:09.813793 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 20:15:09.817009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 20:15:09.824159 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 20:15:09.827066 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 20:15:09.830818 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 20:15:09.836940 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2857 20:15:09.840459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2858 20:15:09.843825 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2859 20:15:09.850426 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 20:15:09.853640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 20:15:09.856805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 20:15:09.863596 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 20:15:09.867380 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 20:15:09.870053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 20:15:09.877130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 20:15:09.880214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 20:15:09.883352 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 20:15:09.890686 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 20:15:09.893680 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 20:15:09.897044 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 20:15:09.903390 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 20:15:09.906954 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2873 20:15:09.910097 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2874 20:15:09.913562 Total UI for P1: 0, mck2ui 16
2875 20:15:09.916775 best dqsien dly found for B0: ( 1, 3, 24)
2876 20:15:09.920240 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2877 20:15:09.926932 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 20:15:09.930143 Total UI for P1: 0, mck2ui 16
2879 20:15:09.933320 best dqsien dly found for B1: ( 1, 4, 0)
2880 20:15:09.936930 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2881 20:15:09.940365 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2882 20:15:09.940442
2883 20:15:09.943668 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2884 20:15:09.947303 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2885 20:15:09.950235 [Gating] SW calibration Done
2886 20:15:09.950315 ==
2887 20:15:09.953236 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 20:15:09.956722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 20:15:09.956802 ==
2890 20:15:09.959809 RX Vref Scan: 0
2891 20:15:09.959884
2892 20:15:09.963909 RX Vref 0 -> 0, step: 1
2893 20:15:09.963982
2894 20:15:09.964044 RX Delay -40 -> 252, step: 8
2895 20:15:09.969792 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2896 20:15:09.973268 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2897 20:15:09.976846 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2898 20:15:09.979761 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2899 20:15:09.982850 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2900 20:15:09.989952 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2901 20:15:09.992974 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2902 20:15:09.996151 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2903 20:15:09.999266 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2904 20:15:10.002632 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2905 20:15:10.009732 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2906 20:15:10.012640 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2907 20:15:10.016842 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2908 20:15:10.019440 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2909 20:15:10.022664 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2910 20:15:10.029710 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2911 20:15:10.029790 ==
2912 20:15:10.033102 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 20:15:10.036460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 20:15:10.036546 ==
2915 20:15:10.036612 DQS Delay:
2916 20:15:10.039332 DQS0 = 0, DQS1 = 0
2917 20:15:10.039459 DQM Delay:
2918 20:15:10.042633 DQM0 = 115, DQM1 = 109
2919 20:15:10.042713 DQ Delay:
2920 20:15:10.046156 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2921 20:15:10.049292 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2922 20:15:10.052348 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2923 20:15:10.056012 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2924 20:15:10.056085
2925 20:15:10.059340
2926 20:15:10.059450 ==
2927 20:15:10.062839 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 20:15:10.066381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 20:15:10.066460 ==
2930 20:15:10.066528
2931 20:15:10.066590
2932 20:15:10.069195 TX Vref Scan disable
2933 20:15:10.069274 == TX Byte 0 ==
2934 20:15:10.075783 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2935 20:15:10.079032 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2936 20:15:10.079119 == TX Byte 1 ==
2937 20:15:10.085984 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2938 20:15:10.089292 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2939 20:15:10.089368 ==
2940 20:15:10.092585 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 20:15:10.095876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 20:15:10.095960 ==
2943 20:15:10.107869 TX Vref=22, minBit 3, minWin=25, winSum=411
2944 20:15:10.111588 TX Vref=24, minBit 10, minWin=25, winSum=419
2945 20:15:10.115551 TX Vref=26, minBit 0, minWin=26, winSum=420
2946 20:15:10.118165 TX Vref=28, minBit 12, minWin=25, winSum=421
2947 20:15:10.121380 TX Vref=30, minBit 12, minWin=25, winSum=424
2948 20:15:10.127763 TX Vref=32, minBit 5, minWin=25, winSum=424
2949 20:15:10.131588 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 26
2950 20:15:10.131667
2951 20:15:10.135019 Final TX Range 1 Vref 26
2952 20:15:10.135098
2953 20:15:10.135167 ==
2954 20:15:10.137773 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 20:15:10.141135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 20:15:10.144617 ==
2957 20:15:10.144689
2958 20:15:10.144750
2959 20:15:10.144808 TX Vref Scan disable
2960 20:15:10.147864 == TX Byte 0 ==
2961 20:15:10.151171 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2962 20:15:10.157885 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2963 20:15:10.158008 == TX Byte 1 ==
2964 20:15:10.161529 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2965 20:15:10.168217 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2966 20:15:10.168341
2967 20:15:10.168451 [DATLAT]
2968 20:15:10.168590 Freq=1200, CH0 RK1
2969 20:15:10.168698
2970 20:15:10.171351 DATLAT Default: 0xd
2971 20:15:10.171509 0, 0xFFFF, sum = 0
2972 20:15:10.174641 1, 0xFFFF, sum = 0
2973 20:15:10.174763 2, 0xFFFF, sum = 0
2974 20:15:10.178123 3, 0xFFFF, sum = 0
2975 20:15:10.181232 4, 0xFFFF, sum = 0
2976 20:15:10.181355 5, 0xFFFF, sum = 0
2977 20:15:10.184957 6, 0xFFFF, sum = 0
2978 20:15:10.185079 7, 0xFFFF, sum = 0
2979 20:15:10.188066 8, 0xFFFF, sum = 0
2980 20:15:10.188187 9, 0xFFFF, sum = 0
2981 20:15:10.191128 10, 0xFFFF, sum = 0
2982 20:15:10.191253 11, 0xFFFF, sum = 0
2983 20:15:10.194327 12, 0x0, sum = 1
2984 20:15:10.194450 13, 0x0, sum = 2
2985 20:15:10.197715 14, 0x0, sum = 3
2986 20:15:10.197831 15, 0x0, sum = 4
2987 20:15:10.201261 best_step = 13
2988 20:15:10.201376
2989 20:15:10.201486 ==
2990 20:15:10.204735 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 20:15:10.207827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 20:15:10.207948 ==
2993 20:15:10.208091 RX Vref Scan: 0
2994 20:15:10.208227
2995 20:15:10.211313 RX Vref 0 -> 0, step: 1
2996 20:15:10.211486
2997 20:15:10.214737 RX Delay -21 -> 252, step: 4
2998 20:15:10.217583 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2999 20:15:10.224339 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3000 20:15:10.227627 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3001 20:15:10.230864 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3002 20:15:10.234157 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3003 20:15:10.237825 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3004 20:15:10.244033 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3005 20:15:10.247145 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3006 20:15:10.250313 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3007 20:15:10.253824 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3008 20:15:10.257158 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3009 20:15:10.264067 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3010 20:15:10.267061 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3011 20:15:10.270333 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3012 20:15:10.273702 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3013 20:15:10.280789 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3014 20:15:10.280871 ==
3015 20:15:10.283567 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 20:15:10.286838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 20:15:10.286920 ==
3018 20:15:10.286984 DQS Delay:
3019 20:15:10.290344 DQS0 = 0, DQS1 = 0
3020 20:15:10.290426 DQM Delay:
3021 20:15:10.293462 DQM0 = 115, DQM1 = 106
3022 20:15:10.293549 DQ Delay:
3023 20:15:10.297173 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3024 20:15:10.300568 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3025 20:15:10.303525 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3026 20:15:10.306702 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3027 20:15:10.306784
3028 20:15:10.310432
3029 20:15:10.316469 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3030 20:15:10.319807 CH0 RK1: MR19=303, MR18=FEFC
3031 20:15:10.326454 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3032 20:15:10.330194 [RxdqsGatingPostProcess] freq 1200
3033 20:15:10.333472 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3034 20:15:10.336375 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 20:15:10.339583 best DQS1 dly(2T, 0.5T) = (0, 12)
3036 20:15:10.343289 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 20:15:10.347027 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3038 20:15:10.350258 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 20:15:10.353373 best DQS1 dly(2T, 0.5T) = (0, 12)
3040 20:15:10.356380 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 20:15:10.359455 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3042 20:15:10.363190 Pre-setting of DQS Precalculation
3043 20:15:10.366652 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3044 20:15:10.366728 ==
3045 20:15:10.369676 Dram Type= 6, Freq= 0, CH_1, rank 0
3046 20:15:10.373501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 20:15:10.376441 ==
3048 20:15:10.381000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3049 20:15:10.386029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3050 20:15:10.394591 [CA 0] Center 38 (8~68) winsize 61
3051 20:15:10.397604 [CA 1] Center 37 (7~68) winsize 62
3052 20:15:10.400834 [CA 2] Center 35 (6~65) winsize 60
3053 20:15:10.404479 [CA 3] Center 34 (4~64) winsize 61
3054 20:15:10.407493 [CA 4] Center 35 (5~65) winsize 61
3055 20:15:10.410853 [CA 5] Center 33 (3~64) winsize 62
3056 20:15:10.410933
3057 20:15:10.414236 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3058 20:15:10.414315
3059 20:15:10.417566 [CATrainingPosCal] consider 1 rank data
3060 20:15:10.421207 u2DelayCellTimex100 = 270/100 ps
3061 20:15:10.424074 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3062 20:15:10.430911 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 20:15:10.434334 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3064 20:15:10.437687 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 20:15:10.441014 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 20:15:10.444398 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3067 20:15:10.444514
3068 20:15:10.447437 CA PerBit enable=1, Macro0, CA PI delay=33
3069 20:15:10.447554
3070 20:15:10.450907 [CBTSetCACLKResult] CA Dly = 33
3071 20:15:10.451026 CS Dly: 4 (0~35)
3072 20:15:10.454033 ==
3073 20:15:10.457376 Dram Type= 6, Freq= 0, CH_1, rank 1
3074 20:15:10.461117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 20:15:10.461233 ==
3076 20:15:10.464039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 20:15:10.470505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 20:15:10.479932 [CA 0] Center 37 (7~68) winsize 62
3079 20:15:10.483524 [CA 1] Center 38 (8~68) winsize 61
3080 20:15:10.486403 [CA 2] Center 35 (5~65) winsize 61
3081 20:15:10.489751 [CA 3] Center 33 (3~64) winsize 62
3082 20:15:10.493186 [CA 4] Center 34 (4~64) winsize 61
3083 20:15:10.496384 [CA 5] Center 33 (3~64) winsize 62
3084 20:15:10.496506
3085 20:15:10.499794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3086 20:15:10.499914
3087 20:15:10.503496 [CATrainingPosCal] consider 2 rank data
3088 20:15:10.506220 u2DelayCellTimex100 = 270/100 ps
3089 20:15:10.509643 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3090 20:15:10.517005 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3091 20:15:10.519868 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3092 20:15:10.523889 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 20:15:10.526589 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3094 20:15:10.529625 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3095 20:15:10.529747
3096 20:15:10.533076 CA PerBit enable=1, Macro0, CA PI delay=33
3097 20:15:10.533196
3098 20:15:10.536407 [CBTSetCACLKResult] CA Dly = 33
3099 20:15:10.536527 CS Dly: 5 (0~38)
3100 20:15:10.536636
3101 20:15:10.543347 ----->DramcWriteLeveling(PI) begin...
3102 20:15:10.543453 ==
3103 20:15:10.546041 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 20:15:10.549758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 20:15:10.549839 ==
3106 20:15:10.552782 Write leveling (Byte 0): 24 => 24
3107 20:15:10.556036 Write leveling (Byte 1): 27 => 27
3108 20:15:10.559381 DramcWriteLeveling(PI) end<-----
3109 20:15:10.559489
3110 20:15:10.559583 ==
3111 20:15:10.562952 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 20:15:10.566030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 20:15:10.566110 ==
3114 20:15:10.569514 [Gating] SW mode calibration
3115 20:15:10.575855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3116 20:15:10.582610 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3117 20:15:10.586509 0 15 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
3118 20:15:10.589501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 20:15:10.596515 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 20:15:10.599235 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 20:15:10.602661 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 20:15:10.609546 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 20:15:10.612590 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 20:15:10.615828 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3125 20:15:10.622920 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 20:15:10.625774 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 20:15:10.629193 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 20:15:10.635934 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 20:15:10.639107 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 20:15:10.642471 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 20:15:10.648923 1 0 24 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
3132 20:15:10.652192 1 0 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3133 20:15:10.655435 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 20:15:10.658732 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 20:15:10.665482 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 20:15:10.668867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 20:15:10.672100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 20:15:10.678679 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 20:15:10.682070 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3140 20:15:10.685922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 20:15:10.692022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3142 20:15:10.695147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 20:15:10.698551 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 20:15:10.705236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 20:15:10.708346 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 20:15:10.711824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 20:15:10.718393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 20:15:10.721575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 20:15:10.725373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 20:15:10.731358 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 20:15:10.735226 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 20:15:10.738331 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 20:15:10.744980 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 20:15:10.748057 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 20:15:10.751258 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3156 20:15:10.758150 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3157 20:15:10.761535 Total UI for P1: 0, mck2ui 16
3158 20:15:10.764989 best dqsien dly found for B0: ( 1, 3, 24)
3159 20:15:10.768261 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 20:15:10.771304 Total UI for P1: 0, mck2ui 16
3161 20:15:10.774595 best dqsien dly found for B1: ( 1, 3, 28)
3162 20:15:10.777846 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3163 20:15:10.781426 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3164 20:15:10.781521
3165 20:15:10.785240 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3166 20:15:10.787937 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3167 20:15:10.791522 [Gating] SW calibration Done
3168 20:15:10.791601 ==
3169 20:15:10.794638 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 20:15:10.801060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 20:15:10.801140 ==
3172 20:15:10.801203 RX Vref Scan: 0
3173 20:15:10.801261
3174 20:15:10.804595 RX Vref 0 -> 0, step: 1
3175 20:15:10.804676
3176 20:15:10.808169 RX Delay -40 -> 252, step: 8
3177 20:15:10.811211 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3178 20:15:10.814444 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3179 20:15:10.818436 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3180 20:15:10.820989 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3181 20:15:10.828267 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3182 20:15:10.831036 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3183 20:15:10.834718 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3184 20:15:10.837801 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3185 20:15:10.841002 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3186 20:15:10.847480 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3187 20:15:10.851260 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3188 20:15:10.854559 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3189 20:15:10.857835 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3190 20:15:10.861497 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3191 20:15:10.868048 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3192 20:15:10.871073 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3193 20:15:10.871155 ==
3194 20:15:10.874438 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 20:15:10.877502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 20:15:10.877585 ==
3197 20:15:10.880648 DQS Delay:
3198 20:15:10.880729 DQS0 = 0, DQS1 = 0
3199 20:15:10.880796 DQM Delay:
3200 20:15:10.883855 DQM0 = 116, DQM1 = 113
3201 20:15:10.883938 DQ Delay:
3202 20:15:10.887276 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3203 20:15:10.890879 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3204 20:15:10.897255 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3205 20:15:10.900956 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3206 20:15:10.901038
3207 20:15:10.901103
3208 20:15:10.901162 ==
3209 20:15:10.904180 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 20:15:10.907464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 20:15:10.907550 ==
3212 20:15:10.907615
3213 20:15:10.907674
3214 20:15:10.911139 TX Vref Scan disable
3215 20:15:10.911220 == TX Byte 0 ==
3216 20:15:10.917272 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3217 20:15:10.920606 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3218 20:15:10.920719 == TX Byte 1 ==
3219 20:15:10.927274 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3220 20:15:10.930479 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3221 20:15:10.930561 ==
3222 20:15:10.933974 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 20:15:10.937033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 20:15:10.937115 ==
3225 20:15:10.950474 TX Vref=22, minBit 3, minWin=25, winSum=413
3226 20:15:10.953846 TX Vref=24, minBit 8, minWin=24, winSum=414
3227 20:15:10.956817 TX Vref=26, minBit 2, minWin=25, winSum=422
3228 20:15:10.960181 TX Vref=28, minBit 2, minWin=25, winSum=425
3229 20:15:10.963611 TX Vref=30, minBit 11, minWin=25, winSum=425
3230 20:15:10.969934 TX Vref=32, minBit 8, minWin=25, winSum=431
3231 20:15:10.973547 [TxChooseVref] Worse bit 8, Min win 25, Win sum 431, Final Vref 32
3232 20:15:10.973629
3233 20:15:10.976580 Final TX Range 1 Vref 32
3234 20:15:10.976662
3235 20:15:10.976726 ==
3236 20:15:10.980097 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 20:15:10.983337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 20:15:10.986549 ==
3239 20:15:10.986631
3240 20:15:10.986695
3241 20:15:10.986754 TX Vref Scan disable
3242 20:15:10.989787 == TX Byte 0 ==
3243 20:15:10.993482 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3244 20:15:11.000011 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3245 20:15:11.000095 == TX Byte 1 ==
3246 20:15:11.003319 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3247 20:15:11.009808 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3248 20:15:11.009891
3249 20:15:11.009956 [DATLAT]
3250 20:15:11.010016 Freq=1200, CH1 RK0
3251 20:15:11.010075
3252 20:15:11.013218 DATLAT Default: 0xd
3253 20:15:11.013286 0, 0xFFFF, sum = 0
3254 20:15:11.016489 1, 0xFFFF, sum = 0
3255 20:15:11.016600 2, 0xFFFF, sum = 0
3256 20:15:11.019706 3, 0xFFFF, sum = 0
3257 20:15:11.023229 4, 0xFFFF, sum = 0
3258 20:15:11.023340 5, 0xFFFF, sum = 0
3259 20:15:11.026972 6, 0xFFFF, sum = 0
3260 20:15:11.027054 7, 0xFFFF, sum = 0
3261 20:15:11.030085 8, 0xFFFF, sum = 0
3262 20:15:11.030168 9, 0xFFFF, sum = 0
3263 20:15:11.033079 10, 0xFFFF, sum = 0
3264 20:15:11.033192 11, 0xFFFF, sum = 0
3265 20:15:11.036419 12, 0x0, sum = 1
3266 20:15:11.036501 13, 0x0, sum = 2
3267 20:15:11.039769 14, 0x0, sum = 3
3268 20:15:11.039850 15, 0x0, sum = 4
3269 20:15:11.039914 best_step = 13
3270 20:15:11.043122
3271 20:15:11.043243 ==
3272 20:15:11.047129 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 20:15:11.049838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 20:15:11.049918 ==
3275 20:15:11.049981 RX Vref Scan: 1
3276 20:15:11.050039
3277 20:15:11.053157 Set Vref Range= 32 -> 127
3278 20:15:11.053236
3279 20:15:11.056112 RX Vref 32 -> 127, step: 1
3280 20:15:11.056192
3281 20:15:11.059535 RX Delay -13 -> 252, step: 4
3282 20:15:11.059614
3283 20:15:11.062767 Set Vref, RX VrefLevel [Byte0]: 32
3284 20:15:11.066436 [Byte1]: 32
3285 20:15:11.066518
3286 20:15:11.069657 Set Vref, RX VrefLevel [Byte0]: 33
3287 20:15:11.072679 [Byte1]: 33
3288 20:15:11.076995
3289 20:15:11.077075 Set Vref, RX VrefLevel [Byte0]: 34
3290 20:15:11.079616 [Byte1]: 34
3291 20:15:11.084304
3292 20:15:11.084399 Set Vref, RX VrefLevel [Byte0]: 35
3293 20:15:11.087722 [Byte1]: 35
3294 20:15:11.092208
3295 20:15:11.092288 Set Vref, RX VrefLevel [Byte0]: 36
3296 20:15:11.095705 [Byte1]: 36
3297 20:15:11.099864
3298 20:15:11.099944 Set Vref, RX VrefLevel [Byte0]: 37
3299 20:15:11.103617 [Byte1]: 37
3300 20:15:11.108039
3301 20:15:11.108118 Set Vref, RX VrefLevel [Byte0]: 38
3302 20:15:11.111041 [Byte1]: 38
3303 20:15:11.115883
3304 20:15:11.115963 Set Vref, RX VrefLevel [Byte0]: 39
3305 20:15:11.119146 [Byte1]: 39
3306 20:15:11.123667
3307 20:15:11.123746 Set Vref, RX VrefLevel [Byte0]: 40
3308 20:15:11.126844 [Byte1]: 40
3309 20:15:11.131606
3310 20:15:11.131685 Set Vref, RX VrefLevel [Byte0]: 41
3311 20:15:11.134865 [Byte1]: 41
3312 20:15:11.139250
3313 20:15:11.139333 Set Vref, RX VrefLevel [Byte0]: 42
3314 20:15:11.143078 [Byte1]: 42
3315 20:15:11.147229
3316 20:15:11.147311 Set Vref, RX VrefLevel [Byte0]: 43
3317 20:15:11.150524 [Byte1]: 43
3318 20:15:11.155544
3319 20:15:11.155619 Set Vref, RX VrefLevel [Byte0]: 44
3320 20:15:11.158472 [Byte1]: 44
3321 20:15:11.163234
3322 20:15:11.163342 Set Vref, RX VrefLevel [Byte0]: 45
3323 20:15:11.166487 [Byte1]: 45
3324 20:15:11.171107
3325 20:15:11.171188 Set Vref, RX VrefLevel [Byte0]: 46
3326 20:15:11.174082 [Byte1]: 46
3327 20:15:11.178689
3328 20:15:11.178769 Set Vref, RX VrefLevel [Byte0]: 47
3329 20:15:11.182161 [Byte1]: 47
3330 20:15:11.186668
3331 20:15:11.186748 Set Vref, RX VrefLevel [Byte0]: 48
3332 20:15:11.190111 [Byte1]: 48
3333 20:15:11.194641
3334 20:15:11.194720 Set Vref, RX VrefLevel [Byte0]: 49
3335 20:15:11.197804 [Byte1]: 49
3336 20:15:11.202501
3337 20:15:11.202580 Set Vref, RX VrefLevel [Byte0]: 50
3338 20:15:11.205648 [Byte1]: 50
3339 20:15:11.210696
3340 20:15:11.210781 Set Vref, RX VrefLevel [Byte0]: 51
3341 20:15:11.213615 [Byte1]: 51
3342 20:15:11.218157
3343 20:15:11.218270 Set Vref, RX VrefLevel [Byte0]: 52
3344 20:15:11.221516 [Byte1]: 52
3345 20:15:11.226342
3346 20:15:11.226425 Set Vref, RX VrefLevel [Byte0]: 53
3347 20:15:11.229347 [Byte1]: 53
3348 20:15:11.234188
3349 20:15:11.234266 Set Vref, RX VrefLevel [Byte0]: 54
3350 20:15:11.237877 [Byte1]: 54
3351 20:15:11.241696
3352 20:15:11.241775 Set Vref, RX VrefLevel [Byte0]: 55
3353 20:15:11.245482 [Byte1]: 55
3354 20:15:11.250089
3355 20:15:11.250168 Set Vref, RX VrefLevel [Byte0]: 56
3356 20:15:11.253214 [Byte1]: 56
3357 20:15:11.257462
3358 20:15:11.257611 Set Vref, RX VrefLevel [Byte0]: 57
3359 20:15:11.260807 [Byte1]: 57
3360 20:15:11.265484
3361 20:15:11.265562 Set Vref, RX VrefLevel [Byte0]: 58
3362 20:15:11.268756 [Byte1]: 58
3363 20:15:11.273500
3364 20:15:11.273578 Set Vref, RX VrefLevel [Byte0]: 59
3365 20:15:11.277040 [Byte1]: 59
3366 20:15:11.281690
3367 20:15:11.281775 Set Vref, RX VrefLevel [Byte0]: 60
3368 20:15:11.285020 [Byte1]: 60
3369 20:15:11.289365
3370 20:15:11.289490 Set Vref, RX VrefLevel [Byte0]: 61
3371 20:15:11.292698 [Byte1]: 61
3372 20:15:11.297463
3373 20:15:11.297618 Set Vref, RX VrefLevel [Byte0]: 62
3374 20:15:11.300579 [Byte1]: 62
3375 20:15:11.304868
3376 20:15:11.305024 Set Vref, RX VrefLevel [Byte0]: 63
3377 20:15:11.308413 [Byte1]: 63
3378 20:15:11.313220
3379 20:15:11.313343 Set Vref, RX VrefLevel [Byte0]: 64
3380 20:15:11.316043 [Byte1]: 64
3381 20:15:11.321458
3382 20:15:11.321580 Set Vref, RX VrefLevel [Byte0]: 65
3383 20:15:11.323893 [Byte1]: 65
3384 20:15:11.328885
3385 20:15:11.329007 Final RX Vref Byte 0 = 52 to rank0
3386 20:15:11.331845 Final RX Vref Byte 1 = 51 to rank0
3387 20:15:11.335086 Final RX Vref Byte 0 = 52 to rank1
3388 20:15:11.338658 Final RX Vref Byte 1 = 51 to rank1==
3389 20:15:11.341721 Dram Type= 6, Freq= 0, CH_1, rank 0
3390 20:15:11.348358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3391 20:15:11.348486 ==
3392 20:15:11.348599 DQS Delay:
3393 20:15:11.351935 DQS0 = 0, DQS1 = 0
3394 20:15:11.352057 DQM Delay:
3395 20:15:11.352168 DQM0 = 114, DQM1 = 112
3396 20:15:11.355203 DQ Delay:
3397 20:15:11.358654 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3398 20:15:11.362400 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3399 20:15:11.365120 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3400 20:15:11.368297 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =122
3401 20:15:11.368377
3402 20:15:11.368440
3403 20:15:11.378379 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3404 20:15:11.378506 CH1 RK0: MR19=303, MR18=F0FD
3405 20:15:11.385013 CH1_RK0: MR19=0x303, MR18=0xF0FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3406 20:15:11.385137
3407 20:15:11.388417 ----->DramcWriteLeveling(PI) begin...
3408 20:15:11.388540 ==
3409 20:15:11.391219 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 20:15:11.397883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 20:15:11.398024 ==
3412 20:15:11.401163 Write leveling (Byte 0): 24 => 24
3413 20:15:11.404557 Write leveling (Byte 1): 29 => 29
3414 20:15:11.404680 DramcWriteLeveling(PI) end<-----
3415 20:15:11.404791
3416 20:15:11.407775 ==
3417 20:15:11.411501 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 20:15:11.414657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 20:15:11.414778 ==
3420 20:15:11.417999 [Gating] SW mode calibration
3421 20:15:11.424395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3422 20:15:11.428092 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3423 20:15:11.434413 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3424 20:15:11.437759 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 20:15:11.440658 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 20:15:11.447570 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 20:15:11.450994 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 20:15:11.454006 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3429 20:15:11.460833 0 15 24 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
3430 20:15:11.464037 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
3431 20:15:11.467318 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 20:15:11.473688 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 20:15:11.477010 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 20:15:11.480576 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 20:15:11.487011 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 20:15:11.490283 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3437 20:15:11.493547 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3438 20:15:11.499946 1 0 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3439 20:15:11.503413 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 20:15:11.506446 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 20:15:11.513536 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 20:15:11.516808 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 20:15:11.519810 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 20:15:11.526164 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 20:15:11.529583 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3446 20:15:11.536297 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3447 20:15:11.539746 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 20:15:11.543177 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 20:15:11.549546 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 20:15:11.552561 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 20:15:11.555860 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 20:15:11.562574 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 20:15:11.565725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 20:15:11.569002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 20:15:11.575590 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 20:15:11.578952 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 20:15:11.582004 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 20:15:11.589330 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 20:15:11.591827 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 20:15:11.595805 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3461 20:15:11.601825 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3462 20:15:11.605089 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3463 20:15:11.608670 Total UI for P1: 0, mck2ui 16
3464 20:15:11.612008 best dqsien dly found for B0: ( 1, 3, 22)
3465 20:15:11.614963 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 20:15:11.618652 Total UI for P1: 0, mck2ui 16
3467 20:15:11.621675 best dqsien dly found for B1: ( 1, 3, 26)
3468 20:15:11.624781 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3469 20:15:11.628449 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3470 20:15:11.628532
3471 20:15:11.634709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3472 20:15:11.637834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3473 20:15:11.637917 [Gating] SW calibration Done
3474 20:15:11.641527 ==
3475 20:15:11.644510 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 20:15:11.648275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 20:15:11.648358 ==
3478 20:15:11.648423 RX Vref Scan: 0
3479 20:15:11.648484
3480 20:15:11.651498 RX Vref 0 -> 0, step: 1
3481 20:15:11.651580
3482 20:15:11.654563 RX Delay -40 -> 252, step: 8
3483 20:15:11.658533 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3484 20:15:11.661028 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3485 20:15:11.667734 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3486 20:15:11.671064 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3487 20:15:11.674116 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3488 20:15:11.677675 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3489 20:15:11.681232 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3490 20:15:11.687287 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3491 20:15:11.690727 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3492 20:15:11.694228 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3493 20:15:11.696976 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3494 20:15:11.700738 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3495 20:15:11.707347 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3496 20:15:11.710528 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3497 20:15:11.713655 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3498 20:15:11.717456 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3499 20:15:11.717538 ==
3500 20:15:11.720254 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 20:15:11.727240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 20:15:11.727351 ==
3503 20:15:11.727431 DQS Delay:
3504 20:15:11.730776 DQS0 = 0, DQS1 = 0
3505 20:15:11.730857 DQM Delay:
3506 20:15:11.733638 DQM0 = 115, DQM1 = 111
3507 20:15:11.733720 DQ Delay:
3508 20:15:11.737156 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3509 20:15:11.740152 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3510 20:15:11.743566 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3511 20:15:11.746457 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3512 20:15:11.746537
3513 20:15:11.746601
3514 20:15:11.746660 ==
3515 20:15:11.750071 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 20:15:11.756529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 20:15:11.756611 ==
3518 20:15:11.756675
3519 20:15:11.756734
3520 20:15:11.756790 TX Vref Scan disable
3521 20:15:11.759751 == TX Byte 0 ==
3522 20:15:11.763192 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3523 20:15:11.769894 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3524 20:15:11.769976 == TX Byte 1 ==
3525 20:15:11.773402 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3526 20:15:11.779297 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3527 20:15:11.779402 ==
3528 20:15:11.783094 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 20:15:11.785874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 20:15:11.786016 ==
3531 20:15:11.797990 TX Vref=22, minBit 1, minWin=25, winSum=417
3532 20:15:11.801227 TX Vref=24, minBit 9, minWin=25, winSum=422
3533 20:15:11.804435 TX Vref=26, minBit 0, minWin=26, winSum=429
3534 20:15:11.807980 TX Vref=28, minBit 1, minWin=26, winSum=430
3535 20:15:11.810940 TX Vref=30, minBit 7, minWin=26, winSum=432
3536 20:15:11.817675 TX Vref=32, minBit 2, minWin=26, winSum=434
3537 20:15:11.820995 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3538 20:15:11.821076
3539 20:15:11.823987 Final TX Range 1 Vref 32
3540 20:15:11.824068
3541 20:15:11.824131 ==
3542 20:15:11.827633 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 20:15:11.830883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 20:15:11.833976 ==
3545 20:15:11.834055
3546 20:15:11.834119
3547 20:15:11.834177 TX Vref Scan disable
3548 20:15:11.837912 == TX Byte 0 ==
3549 20:15:11.840944 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3550 20:15:11.847992 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3551 20:15:11.848075 == TX Byte 1 ==
3552 20:15:11.850773 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3553 20:15:11.857110 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3554 20:15:11.857204
3555 20:15:11.857268 [DATLAT]
3556 20:15:11.857327 Freq=1200, CH1 RK1
3557 20:15:11.857383
3558 20:15:11.860435 DATLAT Default: 0xd
3559 20:15:11.864384 0, 0xFFFF, sum = 0
3560 20:15:11.864465 1, 0xFFFF, sum = 0
3561 20:15:11.867507 2, 0xFFFF, sum = 0
3562 20:15:11.867588 3, 0xFFFF, sum = 0
3563 20:15:11.870634 4, 0xFFFF, sum = 0
3564 20:15:11.870715 5, 0xFFFF, sum = 0
3565 20:15:11.873848 6, 0xFFFF, sum = 0
3566 20:15:11.873946 7, 0xFFFF, sum = 0
3567 20:15:11.877008 8, 0xFFFF, sum = 0
3568 20:15:11.877118 9, 0xFFFF, sum = 0
3569 20:15:11.880112 10, 0xFFFF, sum = 0
3570 20:15:11.880210 11, 0xFFFF, sum = 0
3571 20:15:11.883375 12, 0x0, sum = 1
3572 20:15:11.883470 13, 0x0, sum = 2
3573 20:15:11.886955 14, 0x0, sum = 3
3574 20:15:11.887036 15, 0x0, sum = 4
3575 20:15:11.890244 best_step = 13
3576 20:15:11.890323
3577 20:15:11.890416 ==
3578 20:15:11.893738 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 20:15:11.896781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 20:15:11.896861 ==
3581 20:15:11.899888 RX Vref Scan: 0
3582 20:15:11.899983
3583 20:15:11.900060 RX Vref 0 -> 0, step: 1
3584 20:15:11.900148
3585 20:15:11.903586 RX Delay -13 -> 252, step: 4
3586 20:15:11.910248 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3587 20:15:11.913474 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3588 20:15:11.916306 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3589 20:15:11.919633 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3590 20:15:11.926143 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3591 20:15:11.929457 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3592 20:15:11.933084 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3593 20:15:11.936391 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3594 20:15:11.939693 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3595 20:15:11.946179 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3596 20:15:11.949754 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3597 20:15:11.952608 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3598 20:15:11.955837 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3599 20:15:11.959318 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3600 20:15:11.965587 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3601 20:15:11.969154 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3602 20:15:11.969235 ==
3603 20:15:11.972634 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 20:15:11.975593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 20:15:11.975700 ==
3606 20:15:11.978980 DQS Delay:
3607 20:15:11.979077 DQS0 = 0, DQS1 = 0
3608 20:15:11.982001 DQM Delay:
3609 20:15:11.982096 DQM0 = 115, DQM1 = 111
3610 20:15:11.982183 DQ Delay:
3611 20:15:11.988779 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3612 20:15:11.992159 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3613 20:15:11.995632 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3614 20:15:11.998432 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3615 20:15:11.998531
3616 20:15:11.998596
3617 20:15:12.005276 [DQSOSCAuto] RK1, (LSB)MR18= 0xf609, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3618 20:15:12.008422 CH1 RK1: MR19=304, MR18=F609
3619 20:15:12.015297 CH1_RK1: MR19=0x304, MR18=0xF609, DQSOSC=406, MR23=63, INC=39, DEC=26
3620 20:15:12.018103 [RxdqsGatingPostProcess] freq 1200
3621 20:15:12.024846 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3622 20:15:12.028746 best DQS0 dly(2T, 0.5T) = (0, 11)
3623 20:15:12.028827 best DQS1 dly(2T, 0.5T) = (0, 11)
3624 20:15:12.031605 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3625 20:15:12.034653 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3626 20:15:12.038029 best DQS0 dly(2T, 0.5T) = (0, 11)
3627 20:15:12.041376 best DQS1 dly(2T, 0.5T) = (0, 11)
3628 20:15:12.044572 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3629 20:15:12.047861 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3630 20:15:12.051095 Pre-setting of DQS Precalculation
3631 20:15:12.057988 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3632 20:15:12.064367 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3633 20:15:12.071169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3634 20:15:12.071283
3635 20:15:12.071348
3636 20:15:12.074522 [Calibration Summary] 2400 Mbps
3637 20:15:12.074602 CH 0, Rank 0
3638 20:15:12.077705 SW Impedance : PASS
3639 20:15:12.081094 DUTY Scan : NO K
3640 20:15:12.081174 ZQ Calibration : PASS
3641 20:15:12.084455 Jitter Meter : NO K
3642 20:15:12.087706 CBT Training : PASS
3643 20:15:12.087786 Write leveling : PASS
3644 20:15:12.091329 RX DQS gating : PASS
3645 20:15:12.094614 RX DQ/DQS(RDDQC) : PASS
3646 20:15:12.094695 TX DQ/DQS : PASS
3647 20:15:12.097891 RX DATLAT : PASS
3648 20:15:12.100546 RX DQ/DQS(Engine): PASS
3649 20:15:12.100626 TX OE : NO K
3650 20:15:12.104315 All Pass.
3651 20:15:12.104394
3652 20:15:12.104456 CH 0, Rank 1
3653 20:15:12.107205 SW Impedance : PASS
3654 20:15:12.107310 DUTY Scan : NO K
3655 20:15:12.110408 ZQ Calibration : PASS
3656 20:15:12.114037 Jitter Meter : NO K
3657 20:15:12.114172 CBT Training : PASS
3658 20:15:12.117007 Write leveling : PASS
3659 20:15:12.120252 RX DQS gating : PASS
3660 20:15:12.120348 RX DQ/DQS(RDDQC) : PASS
3661 20:15:12.123852 TX DQ/DQS : PASS
3662 20:15:12.127186 RX DATLAT : PASS
3663 20:15:12.127283 RX DQ/DQS(Engine): PASS
3664 20:15:12.130560 TX OE : NO K
3665 20:15:12.130640 All Pass.
3666 20:15:12.130703
3667 20:15:12.133818 CH 1, Rank 0
3668 20:15:12.133899 SW Impedance : PASS
3669 20:15:12.137033 DUTY Scan : NO K
3670 20:15:12.140135 ZQ Calibration : PASS
3671 20:15:12.140215 Jitter Meter : NO K
3672 20:15:12.143525 CBT Training : PASS
3673 20:15:12.143652 Write leveling : PASS
3674 20:15:12.146789 RX DQS gating : PASS
3675 20:15:12.149884 RX DQ/DQS(RDDQC) : PASS
3676 20:15:12.150006 TX DQ/DQS : PASS
3677 20:15:12.153517 RX DATLAT : PASS
3678 20:15:12.156593 RX DQ/DQS(Engine): PASS
3679 20:15:12.156712 TX OE : NO K
3680 20:15:12.159867 All Pass.
3681 20:15:12.159965
3682 20:15:12.160054 CH 1, Rank 1
3683 20:15:12.163250 SW Impedance : PASS
3684 20:15:12.163347 DUTY Scan : NO K
3685 20:15:12.166637 ZQ Calibration : PASS
3686 20:15:12.169863 Jitter Meter : NO K
3687 20:15:12.169944 CBT Training : PASS
3688 20:15:12.173643 Write leveling : PASS
3689 20:15:12.176444 RX DQS gating : PASS
3690 20:15:12.176520 RX DQ/DQS(RDDQC) : PASS
3691 20:15:12.180578 TX DQ/DQS : PASS
3692 20:15:12.183127 RX DATLAT : PASS
3693 20:15:12.183202 RX DQ/DQS(Engine): PASS
3694 20:15:12.186556 TX OE : NO K
3695 20:15:12.186638 All Pass.
3696 20:15:12.186702
3697 20:15:12.189457 DramC Write-DBI off
3698 20:15:12.192950 PER_BANK_REFRESH: Hybrid Mode
3699 20:15:12.193024 TX_TRACKING: ON
3700 20:15:12.203142 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3701 20:15:12.206209 [FAST_K] Save calibration result to emmc
3702 20:15:12.209526 dramc_set_vcore_voltage set vcore to 650000
3703 20:15:12.212664 Read voltage for 600, 5
3704 20:15:12.212744 Vio18 = 0
3705 20:15:12.212808 Vcore = 650000
3706 20:15:12.215985 Vdram = 0
3707 20:15:12.216132 Vddq = 0
3708 20:15:12.216197 Vmddr = 0
3709 20:15:12.222752 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3710 20:15:12.226284 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3711 20:15:12.229333 MEM_TYPE=3, freq_sel=19
3712 20:15:12.232778 sv_algorithm_assistance_LP4_1600
3713 20:15:12.235715 ============ PULL DRAM RESETB DOWN ============
3714 20:15:12.242302 ========== PULL DRAM RESETB DOWN end =========
3715 20:15:12.245544 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3716 20:15:12.249306 ===================================
3717 20:15:12.252077 LPDDR4 DRAM CONFIGURATION
3718 20:15:12.255349 ===================================
3719 20:15:12.255442 EX_ROW_EN[0] = 0x0
3720 20:15:12.258922 EX_ROW_EN[1] = 0x0
3721 20:15:12.259004 LP4Y_EN = 0x0
3722 20:15:12.261882 WORK_FSP = 0x0
3723 20:15:12.261983 WL = 0x2
3724 20:15:12.265859 RL = 0x2
3725 20:15:12.265952 BL = 0x2
3726 20:15:12.268437 RPST = 0x0
3727 20:15:12.271878 RD_PRE = 0x0
3728 20:15:12.271970 WR_PRE = 0x1
3729 20:15:12.275235 WR_PST = 0x0
3730 20:15:12.275345 DBI_WR = 0x0
3731 20:15:12.278684 DBI_RD = 0x0
3732 20:15:12.278783 OTF = 0x1
3733 20:15:12.281636 ===================================
3734 20:15:12.284985 ===================================
3735 20:15:12.288426 ANA top config
3736 20:15:12.291766 ===================================
3737 20:15:12.291863 DLL_ASYNC_EN = 0
3738 20:15:12.295127 ALL_SLAVE_EN = 1
3739 20:15:12.298180 NEW_RANK_MODE = 1
3740 20:15:12.301403 DLL_IDLE_MODE = 1
3741 20:15:12.301485 LP45_APHY_COMB_EN = 1
3742 20:15:12.304733 TX_ODT_DIS = 1
3743 20:15:12.307863 NEW_8X_MODE = 1
3744 20:15:12.311850 ===================================
3745 20:15:12.314710 ===================================
3746 20:15:12.318099 data_rate = 1200
3747 20:15:12.321450 CKR = 1
3748 20:15:12.324637 DQ_P2S_RATIO = 8
3749 20:15:12.327781 ===================================
3750 20:15:12.327863 CA_P2S_RATIO = 8
3751 20:15:12.331382 DQ_CA_OPEN = 0
3752 20:15:12.334334 DQ_SEMI_OPEN = 0
3753 20:15:12.337688 CA_SEMI_OPEN = 0
3754 20:15:12.341052 CA_FULL_RATE = 0
3755 20:15:12.344387 DQ_CKDIV4_EN = 1
3756 20:15:12.344493 CA_CKDIV4_EN = 1
3757 20:15:12.347804 CA_PREDIV_EN = 0
3758 20:15:12.351113 PH8_DLY = 0
3759 20:15:12.354324 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3760 20:15:12.357483 DQ_AAMCK_DIV = 4
3761 20:15:12.360628 CA_AAMCK_DIV = 4
3762 20:15:12.364030 CA_ADMCK_DIV = 4
3763 20:15:12.364111 DQ_TRACK_CA_EN = 0
3764 20:15:12.367271 CA_PICK = 600
3765 20:15:12.370592 CA_MCKIO = 600
3766 20:15:12.374466 MCKIO_SEMI = 0
3767 20:15:12.377467 PLL_FREQ = 2288
3768 20:15:12.380711 DQ_UI_PI_RATIO = 32
3769 20:15:12.383553 CA_UI_PI_RATIO = 0
3770 20:15:12.387045 ===================================
3771 20:15:12.390509 ===================================
3772 20:15:12.390591 memory_type:LPDDR4
3773 20:15:12.393461 GP_NUM : 10
3774 20:15:12.397401 SRAM_EN : 1
3775 20:15:12.397483 MD32_EN : 0
3776 20:15:12.400222 ===================================
3777 20:15:12.403485 [ANA_INIT] >>>>>>>>>>>>>>
3778 20:15:12.406867 <<<<<< [CONFIGURE PHASE]: ANA_TX
3779 20:15:12.410119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3780 20:15:12.413570 ===================================
3781 20:15:12.417130 data_rate = 1200,PCW = 0X5800
3782 20:15:12.420072 ===================================
3783 20:15:12.423672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3784 20:15:12.426692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3785 20:15:12.433604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3786 20:15:12.436988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3787 20:15:12.439953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3788 20:15:12.443386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3789 20:15:12.446894 [ANA_INIT] flow start
3790 20:15:12.450132 [ANA_INIT] PLL >>>>>>>>
3791 20:15:12.450214 [ANA_INIT] PLL <<<<<<<<
3792 20:15:12.453264 [ANA_INIT] MIDPI >>>>>>>>
3793 20:15:12.456543 [ANA_INIT] MIDPI <<<<<<<<
3794 20:15:12.459910 [ANA_INIT] DLL >>>>>>>>
3795 20:15:12.459991 [ANA_INIT] flow end
3796 20:15:12.463611 ============ LP4 DIFF to SE enter ============
3797 20:15:12.469750 ============ LP4 DIFF to SE exit ============
3798 20:15:12.469832 [ANA_INIT] <<<<<<<<<<<<<
3799 20:15:12.473134 [Flow] Enable top DCM control >>>>>
3800 20:15:12.476046 [Flow] Enable top DCM control <<<<<
3801 20:15:12.479692 Enable DLL master slave shuffle
3802 20:15:12.486122 ==============================================================
3803 20:15:12.486204 Gating Mode config
3804 20:15:12.492589 ==============================================================
3805 20:15:12.495706 Config description:
3806 20:15:12.505927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3807 20:15:12.512480 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3808 20:15:12.515574 SELPH_MODE 0: By rank 1: By Phase
3809 20:15:12.522464 ==============================================================
3810 20:15:12.525456 GAT_TRACK_EN = 1
3811 20:15:12.528971 RX_GATING_MODE = 2
3812 20:15:12.532128 RX_GATING_TRACK_MODE = 2
3813 20:15:12.535906 SELPH_MODE = 1
3814 20:15:12.535987 PICG_EARLY_EN = 1
3815 20:15:12.538963 VALID_LAT_VALUE = 1
3816 20:15:12.545611 ==============================================================
3817 20:15:12.548872 Enter into Gating configuration >>>>
3818 20:15:12.551981 Exit from Gating configuration <<<<
3819 20:15:12.555345 Enter into DVFS_PRE_config >>>>>
3820 20:15:12.565084 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3821 20:15:12.568133 Exit from DVFS_PRE_config <<<<<
3822 20:15:12.571658 Enter into PICG configuration >>>>
3823 20:15:12.574936 Exit from PICG configuration <<<<
3824 20:15:12.578813 [RX_INPUT] configuration >>>>>
3825 20:15:12.582004 [RX_INPUT] configuration <<<<<
3826 20:15:12.584712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3827 20:15:12.591314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3828 20:15:12.598118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3829 20:15:12.604325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3830 20:15:12.611155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3831 20:15:12.617879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3832 20:15:12.621059 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3833 20:15:12.624146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3834 20:15:12.627780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3835 20:15:12.634102 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3836 20:15:12.637710 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3837 20:15:12.640666 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3838 20:15:12.644259 ===================================
3839 20:15:12.647116 LPDDR4 DRAM CONFIGURATION
3840 20:15:12.650402 ===================================
3841 20:15:12.654069 EX_ROW_EN[0] = 0x0
3842 20:15:12.654150 EX_ROW_EN[1] = 0x0
3843 20:15:12.657233 LP4Y_EN = 0x0
3844 20:15:12.657348 WORK_FSP = 0x0
3845 20:15:12.660540 WL = 0x2
3846 20:15:12.660621 RL = 0x2
3847 20:15:12.663737 BL = 0x2
3848 20:15:12.663818 RPST = 0x0
3849 20:15:12.667214 RD_PRE = 0x0
3850 20:15:12.667321 WR_PRE = 0x1
3851 20:15:12.670074 WR_PST = 0x0
3852 20:15:12.670144 DBI_WR = 0x0
3853 20:15:12.673514 DBI_RD = 0x0
3854 20:15:12.673595 OTF = 0x1
3855 20:15:12.676871 ===================================
3856 20:15:12.683403 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3857 20:15:12.686693 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3858 20:15:12.690274 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 20:15:12.693079 ===================================
3860 20:15:12.696464 LPDDR4 DRAM CONFIGURATION
3861 20:15:12.699928 ===================================
3862 20:15:12.703061 EX_ROW_EN[0] = 0x10
3863 20:15:12.703142 EX_ROW_EN[1] = 0x0
3864 20:15:12.706324 LP4Y_EN = 0x0
3865 20:15:12.706406 WORK_FSP = 0x0
3866 20:15:12.709414 WL = 0x2
3867 20:15:12.709495 RL = 0x2
3868 20:15:12.712822 BL = 0x2
3869 20:15:12.712904 RPST = 0x0
3870 20:15:12.716542 RD_PRE = 0x0
3871 20:15:12.716623 WR_PRE = 0x1
3872 20:15:12.719663 WR_PST = 0x0
3873 20:15:12.719744 DBI_WR = 0x0
3874 20:15:12.723190 DBI_RD = 0x0
3875 20:15:12.723297 OTF = 0x1
3876 20:15:12.726091 ===================================
3877 20:15:12.733023 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3878 20:15:12.738340 nWR fixed to 30
3879 20:15:12.741116 [ModeRegInit_LP4] CH0 RK0
3880 20:15:12.741197 [ModeRegInit_LP4] CH0 RK1
3881 20:15:12.744662 [ModeRegInit_LP4] CH1 RK0
3882 20:15:12.747843 [ModeRegInit_LP4] CH1 RK1
3883 20:15:12.747924 match AC timing 17
3884 20:15:12.754421 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3885 20:15:12.757404 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3886 20:15:12.761282 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3887 20:15:12.767225 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3888 20:15:12.770549 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3889 20:15:12.770672 ==
3890 20:15:12.774557 Dram Type= 6, Freq= 0, CH_0, rank 0
3891 20:15:12.777006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3892 20:15:12.777109 ==
3893 20:15:12.783601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3894 20:15:12.790548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3895 20:15:12.794165 [CA 0] Center 36 (6~67) winsize 62
3896 20:15:12.796911 [CA 1] Center 36 (5~67) winsize 63
3897 20:15:12.800193 [CA 2] Center 34 (4~65) winsize 62
3898 20:15:12.803534 [CA 3] Center 34 (3~65) winsize 63
3899 20:15:12.806709 [CA 4] Center 33 (3~64) winsize 62
3900 20:15:12.810465 [CA 5] Center 33 (3~64) winsize 62
3901 20:15:12.810545
3902 20:15:12.813454 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3903 20:15:12.813534
3904 20:15:12.816908 [CATrainingPosCal] consider 1 rank data
3905 20:15:12.820248 u2DelayCellTimex100 = 270/100 ps
3906 20:15:12.823749 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3907 20:15:12.826558 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3908 20:15:12.829829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3909 20:15:12.836662 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3910 20:15:12.839474 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3911 20:15:12.843172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3912 20:15:12.843279
3913 20:15:12.846388 CA PerBit enable=1, Macro0, CA PI delay=33
3914 20:15:12.846470
3915 20:15:12.849427 [CBTSetCACLKResult] CA Dly = 33
3916 20:15:12.849508 CS Dly: 5 (0~36)
3917 20:15:12.852955 ==
3918 20:15:12.853037 Dram Type= 6, Freq= 0, CH_0, rank 1
3919 20:15:12.859578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 20:15:12.859660 ==
3921 20:15:12.862841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 20:15:12.869450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 20:15:12.873380 [CA 0] Center 36 (6~67) winsize 62
3924 20:15:12.876395 [CA 1] Center 36 (6~67) winsize 62
3925 20:15:12.879785 [CA 2] Center 34 (4~65) winsize 62
3926 20:15:12.882938 [CA 3] Center 34 (4~65) winsize 62
3927 20:15:12.886639 [CA 4] Center 34 (3~65) winsize 63
3928 20:15:12.889702 [CA 5] Center 33 (3~64) winsize 62
3929 20:15:12.889782
3930 20:15:12.892938 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 20:15:12.893045
3932 20:15:12.896481 [CATrainingPosCal] consider 2 rank data
3933 20:15:12.899588 u2DelayCellTimex100 = 270/100 ps
3934 20:15:12.902695 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 20:15:12.909405 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 20:15:12.912931 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 20:15:12.916155 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 20:15:12.919018 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 20:15:12.922902 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 20:15:12.923110
3941 20:15:12.925945 CA PerBit enable=1, Macro0, CA PI delay=33
3942 20:15:12.926042
3943 20:15:12.929144 [CBTSetCACLKResult] CA Dly = 33
3944 20:15:12.932483 CS Dly: 5 (0~36)
3945 20:15:12.932579
3946 20:15:12.935806 ----->DramcWriteLeveling(PI) begin...
3947 20:15:12.935887 ==
3948 20:15:12.939172 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 20:15:12.942088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 20:15:12.942168 ==
3951 20:15:12.945384 Write leveling (Byte 0): 32 => 32
3952 20:15:12.949007 Write leveling (Byte 1): 28 => 28
3953 20:15:12.952044 DramcWriteLeveling(PI) end<-----
3954 20:15:12.952123
3955 20:15:12.952186 ==
3956 20:15:12.955294 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 20:15:12.958480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 20:15:12.958560 ==
3959 20:15:12.961889 [Gating] SW mode calibration
3960 20:15:12.968633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3961 20:15:12.975221 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3962 20:15:12.978423 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 20:15:12.981634 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 20:15:12.988112 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 20:15:12.991638 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3966 20:15:12.998009 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 1) (0 0)
3967 20:15:13.001457 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 20:15:13.004846 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 20:15:13.011648 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 20:15:13.014561 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 20:15:13.018089 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 20:15:13.024782 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 20:15:13.027856 0 10 12 | B1->B0 | 2323 3131 | 1 0 | (0 0) (0 0)
3974 20:15:13.031286 0 10 16 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (1 1)
3975 20:15:13.037456 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 20:15:13.041109 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 20:15:13.044008 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 20:15:13.050988 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 20:15:13.053917 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 20:15:13.057344 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 20:15:13.063782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3982 20:15:13.067468 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3983 20:15:13.070690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 20:15:13.076858 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 20:15:13.080433 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 20:15:13.083357 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 20:15:13.090353 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 20:15:13.093348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 20:15:13.096631 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 20:15:13.103712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 20:15:13.106454 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 20:15:13.109763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 20:15:13.117087 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 20:15:13.119824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 20:15:13.122884 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 20:15:13.129763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 20:15:13.133211 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3998 20:15:13.136231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3999 20:15:13.142942 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 20:15:13.143023 Total UI for P1: 0, mck2ui 16
4001 20:15:13.146301 best dqsien dly found for B0: ( 0, 13, 14)
4002 20:15:13.149991 Total UI for P1: 0, mck2ui 16
4003 20:15:13.153165 best dqsien dly found for B1: ( 0, 13, 18)
4004 20:15:13.159683 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4005 20:15:13.162887 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4006 20:15:13.162968
4007 20:15:13.166201 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4008 20:15:13.169704 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4009 20:15:13.172681 [Gating] SW calibration Done
4010 20:15:13.172766 ==
4011 20:15:13.175881 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 20:15:13.179158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 20:15:13.179240 ==
4014 20:15:13.182200 RX Vref Scan: 0
4015 20:15:13.182282
4016 20:15:13.182347 RX Vref 0 -> 0, step: 1
4017 20:15:13.182407
4018 20:15:13.185683 RX Delay -230 -> 252, step: 16
4019 20:15:13.192186 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4020 20:15:13.195736 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4021 20:15:13.199300 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4022 20:15:13.202898 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4023 20:15:13.205862 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4024 20:15:13.212002 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4025 20:15:13.215726 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4026 20:15:13.218872 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4027 20:15:13.221865 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4028 20:15:13.228599 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4029 20:15:13.232425 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4030 20:15:13.235048 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4031 20:15:13.238456 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4032 20:15:13.245458 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4033 20:15:13.248386 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4034 20:15:13.251812 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4035 20:15:13.251897 ==
4036 20:15:13.254883 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 20:15:13.258491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 20:15:13.261679 ==
4039 20:15:13.261756 DQS Delay:
4040 20:15:13.261818 DQS0 = 0, DQS1 = 0
4041 20:15:13.264952 DQM Delay:
4042 20:15:13.265032 DQM0 = 42, DQM1 = 33
4043 20:15:13.268383 DQ Delay:
4044 20:15:13.271345 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4045 20:15:13.271450 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4046 20:15:13.274689 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4047 20:15:13.277947 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4048 20:15:13.281605
4049 20:15:13.281684
4050 20:15:13.281747 ==
4051 20:15:13.284874 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 20:15:13.287815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 20:15:13.287973 ==
4054 20:15:13.288041
4055 20:15:13.288101
4056 20:15:13.291600 TX Vref Scan disable
4057 20:15:13.291680 == TX Byte 0 ==
4058 20:15:13.297963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4059 20:15:13.301121 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4060 20:15:13.301202 == TX Byte 1 ==
4061 20:15:13.307747 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4062 20:15:13.310933 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4063 20:15:13.311016 ==
4064 20:15:13.314237 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 20:15:13.317554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 20:15:13.317635 ==
4067 20:15:13.321253
4068 20:15:13.321333
4069 20:15:13.321397 TX Vref Scan disable
4070 20:15:13.324956 == TX Byte 0 ==
4071 20:15:13.328006 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4072 20:15:13.334743 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4073 20:15:13.334823 == TX Byte 1 ==
4074 20:15:13.337844 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4075 20:15:13.344332 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4076 20:15:13.344413
4077 20:15:13.344478 [DATLAT]
4078 20:15:13.344537 Freq=600, CH0 RK0
4079 20:15:13.344594
4080 20:15:13.347534 DATLAT Default: 0x9
4081 20:15:13.347614 0, 0xFFFF, sum = 0
4082 20:15:13.350915 1, 0xFFFF, sum = 0
4083 20:15:13.354041 2, 0xFFFF, sum = 0
4084 20:15:13.354121 3, 0xFFFF, sum = 0
4085 20:15:13.357644 4, 0xFFFF, sum = 0
4086 20:15:13.357741 5, 0xFFFF, sum = 0
4087 20:15:13.362144 6, 0xFFFF, sum = 0
4088 20:15:13.362240 7, 0xFFFF, sum = 0
4089 20:15:13.364329 8, 0x0, sum = 1
4090 20:15:13.364412 9, 0x0, sum = 2
4091 20:15:13.367337 10, 0x0, sum = 3
4092 20:15:13.367449 11, 0x0, sum = 4
4093 20:15:13.367517 best_step = 9
4094 20:15:13.367576
4095 20:15:13.370634 ==
4096 20:15:13.370717 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 20:15:13.377518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 20:15:13.377627 ==
4099 20:15:13.377724 RX Vref Scan: 1
4100 20:15:13.377812
4101 20:15:13.380507 RX Vref 0 -> 0, step: 1
4102 20:15:13.380587
4103 20:15:13.383965 RX Delay -195 -> 252, step: 8
4104 20:15:13.384050
4105 20:15:13.387275 Set Vref, RX VrefLevel [Byte0]: 52
4106 20:15:13.390592 [Byte1]: 59
4107 20:15:13.390697
4108 20:15:13.393739 Final RX Vref Byte 0 = 52 to rank0
4109 20:15:13.397466 Final RX Vref Byte 1 = 59 to rank0
4110 20:15:13.400841 Final RX Vref Byte 0 = 52 to rank1
4111 20:15:13.403770 Final RX Vref Byte 1 = 59 to rank1==
4112 20:15:13.407410 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 20:15:13.410440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 20:15:13.413760 ==
4115 20:15:13.413841 DQS Delay:
4116 20:15:13.413904 DQS0 = 0, DQS1 = 0
4117 20:15:13.417101 DQM Delay:
4118 20:15:13.417181 DQM0 = 41, DQM1 = 32
4119 20:15:13.420085 DQ Delay:
4120 20:15:13.420165 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4121 20:15:13.423779 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4122 20:15:13.426923 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4123 20:15:13.430231 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4124 20:15:13.433377
4125 20:15:13.433456
4126 20:15:13.439956 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4127 20:15:13.443029 CH0 RK0: MR19=808, MR18=4D43
4128 20:15:13.450209 CH0_RK0: MR19=0x808, MR18=0x4D43, DQSOSC=395, MR23=63, INC=168, DEC=112
4129 20:15:13.450336
4130 20:15:13.453352 ----->DramcWriteLeveling(PI) begin...
4131 20:15:13.453478 ==
4132 20:15:13.456528 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 20:15:13.459864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 20:15:13.460014 ==
4135 20:15:13.463245 Write leveling (Byte 0): 35 => 35
4136 20:15:13.466530 Write leveling (Byte 1): 31 => 31
4137 20:15:13.470069 DramcWriteLeveling(PI) end<-----
4138 20:15:13.470185
4139 20:15:13.470292 ==
4140 20:15:13.473032 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 20:15:13.476894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 20:15:13.477015 ==
4143 20:15:13.479510 [Gating] SW mode calibration
4144 20:15:13.486261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4145 20:15:13.492751 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4146 20:15:13.496033 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 20:15:13.502985 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 20:15:13.506399 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 20:15:13.509592 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 1) (1 1)
4150 20:15:13.515848 0 9 16 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
4151 20:15:13.519173 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 20:15:13.522830 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 20:15:13.529704 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 20:15:13.532854 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 20:15:13.536406 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 20:15:13.542203 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 20:15:13.545578 0 10 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
4158 20:15:13.549117 0 10 16 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
4159 20:15:13.555547 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 20:15:13.558866 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 20:15:13.562274 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 20:15:13.568498 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 20:15:13.572114 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 20:15:13.574991 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 20:15:13.581364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 20:15:13.584939 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4167 20:15:13.588243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 20:15:13.595382 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 20:15:13.598147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 20:15:13.601305 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 20:15:13.608519 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 20:15:13.611237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 20:15:13.615131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 20:15:13.621267 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 20:15:13.624186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 20:15:13.627607 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 20:15:13.634489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 20:15:13.637614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 20:15:13.641012 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 20:15:13.647405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4181 20:15:13.650911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4182 20:15:13.654211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4183 20:15:13.657049 Total UI for P1: 0, mck2ui 16
4184 20:15:13.660367 best dqsien dly found for B0: ( 0, 13, 10)
4185 20:15:13.667144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 20:15:13.667270 Total UI for P1: 0, mck2ui 16
4187 20:15:13.673640 best dqsien dly found for B1: ( 0, 13, 14)
4188 20:15:13.676829 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4189 20:15:13.680473 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4190 20:15:13.680592
4191 20:15:13.683197 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4192 20:15:13.686613 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4193 20:15:13.689950 [Gating] SW calibration Done
4194 20:15:13.690070 ==
4195 20:15:13.693753 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 20:15:13.696427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 20:15:13.696548 ==
4198 20:15:13.700190 RX Vref Scan: 0
4199 20:15:13.700352
4200 20:15:13.703180 RX Vref 0 -> 0, step: 1
4201 20:15:13.703299
4202 20:15:13.703447 RX Delay -230 -> 252, step: 16
4203 20:15:13.710113 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4204 20:15:13.713271 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4205 20:15:13.716405 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4206 20:15:13.719713 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4207 20:15:13.726173 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4208 20:15:13.730207 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4209 20:15:13.732993 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4210 20:15:13.736329 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4211 20:15:13.742733 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4212 20:15:13.746018 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4213 20:15:13.749197 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4214 20:15:13.753207 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4215 20:15:13.759221 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4216 20:15:13.762685 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4217 20:15:13.765687 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4218 20:15:13.769777 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4219 20:15:13.769900 ==
4220 20:15:13.772448 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 20:15:13.778865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 20:15:13.778991 ==
4223 20:15:13.779104 DQS Delay:
4224 20:15:13.782044 DQS0 = 0, DQS1 = 0
4225 20:15:13.782163 DQM Delay:
4226 20:15:13.782274 DQM0 = 46, DQM1 = 35
4227 20:15:13.785401 DQ Delay:
4228 20:15:13.789075 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =49
4229 20:15:13.791961 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4230 20:15:13.795386 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4231 20:15:13.798508 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4232 20:15:13.798593
4233 20:15:13.798657
4234 20:15:13.798716 ==
4235 20:15:13.801832 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 20:15:13.805134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 20:15:13.805243 ==
4238 20:15:13.805361
4239 20:15:13.805486
4240 20:15:13.808558 TX Vref Scan disable
4241 20:15:13.812025 == TX Byte 0 ==
4242 20:15:13.815247 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4243 20:15:13.818719 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4244 20:15:13.821663 == TX Byte 1 ==
4245 20:15:13.824983 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4246 20:15:13.828417 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4247 20:15:13.828500 ==
4248 20:15:13.831645 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 20:15:13.838284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 20:15:13.838370 ==
4251 20:15:13.838437
4252 20:15:13.838498
4253 20:15:13.838557 TX Vref Scan disable
4254 20:15:13.842493 == TX Byte 0 ==
4255 20:15:13.845696 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4256 20:15:13.852401 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4257 20:15:13.852489 == TX Byte 1 ==
4258 20:15:13.855903 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4259 20:15:13.862290 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4260 20:15:13.862375
4261 20:15:13.862442 [DATLAT]
4262 20:15:13.862503 Freq=600, CH0 RK1
4263 20:15:13.862562
4264 20:15:13.866498 DATLAT Default: 0x9
4265 20:15:13.866581 0, 0xFFFF, sum = 0
4266 20:15:13.869025 1, 0xFFFF, sum = 0
4267 20:15:13.872215 2, 0xFFFF, sum = 0
4268 20:15:13.872299 3, 0xFFFF, sum = 0
4269 20:15:13.875843 4, 0xFFFF, sum = 0
4270 20:15:13.875927 5, 0xFFFF, sum = 0
4271 20:15:13.879172 6, 0xFFFF, sum = 0
4272 20:15:13.879256 7, 0xFFFF, sum = 0
4273 20:15:13.882277 8, 0x0, sum = 1
4274 20:15:13.882361 9, 0x0, sum = 2
4275 20:15:13.885111 10, 0x0, sum = 3
4276 20:15:13.885197 11, 0x0, sum = 4
4277 20:15:13.885264 best_step = 9
4278 20:15:13.885325
4279 20:15:13.888443 ==
4280 20:15:13.892260 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 20:15:13.895148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 20:15:13.895232 ==
4283 20:15:13.895299 RX Vref Scan: 0
4284 20:15:13.895364
4285 20:15:13.899232 RX Vref 0 -> 0, step: 1
4286 20:15:13.899315
4287 20:15:13.902303 RX Delay -179 -> 252, step: 8
4288 20:15:13.908575 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4289 20:15:13.911417 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4290 20:15:13.914946 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4291 20:15:13.917897 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4292 20:15:13.924383 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4293 20:15:13.928002 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4294 20:15:13.931193 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4295 20:15:13.934445 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4296 20:15:13.937522 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4297 20:15:13.944419 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4298 20:15:13.947349 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4299 20:15:13.950610 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4300 20:15:13.953949 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4301 20:15:13.960711 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4302 20:15:13.964205 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4303 20:15:13.967205 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4304 20:15:13.967314 ==
4305 20:15:13.970431 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 20:15:13.977287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 20:15:13.977371 ==
4308 20:15:13.977437 DQS Delay:
4309 20:15:13.981311 DQS0 = 0, DQS1 = 0
4310 20:15:13.981420 DQM Delay:
4311 20:15:13.981515 DQM0 = 40, DQM1 = 33
4312 20:15:13.984012 DQ Delay:
4313 20:15:13.987261 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4314 20:15:13.990468 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4315 20:15:13.993731 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4316 20:15:13.997565 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4317 20:15:13.997648
4318 20:15:13.997713
4319 20:15:14.003441 [DQSOSCAuto] RK1, (LSB)MR18= 0x4742, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4320 20:15:14.006875 CH0 RK1: MR19=808, MR18=4742
4321 20:15:14.013464 CH0_RK1: MR19=0x808, MR18=0x4742, DQSOSC=396, MR23=63, INC=167, DEC=111
4322 20:15:14.017107 [RxdqsGatingPostProcess] freq 600
4323 20:15:14.020022 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4324 20:15:14.023019 Pre-setting of DQS Precalculation
4325 20:15:14.029678 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4326 20:15:14.029781 ==
4327 20:15:14.032948 Dram Type= 6, Freq= 0, CH_1, rank 0
4328 20:15:14.036584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 20:15:14.036713 ==
4330 20:15:14.042970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4331 20:15:14.049446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4332 20:15:14.053564 [CA 0] Center 35 (5~66) winsize 62
4333 20:15:14.056029 [CA 1] Center 35 (5~66) winsize 62
4334 20:15:14.059687 [CA 2] Center 34 (4~65) winsize 62
4335 20:15:14.063152 [CA 3] Center 34 (3~65) winsize 63
4336 20:15:14.066212 [CA 4] Center 34 (4~65) winsize 62
4337 20:15:14.069248 [CA 5] Center 34 (3~65) winsize 63
4338 20:15:14.069367
4339 20:15:14.072633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4340 20:15:14.072751
4341 20:15:14.075947 [CATrainingPosCal] consider 1 rank data
4342 20:15:14.079606 u2DelayCellTimex100 = 270/100 ps
4343 20:15:14.082959 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4344 20:15:14.086576 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4345 20:15:14.089391 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4346 20:15:14.092814 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4347 20:15:14.095831 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4348 20:15:14.099457 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4349 20:15:14.099539
4350 20:15:14.105657 CA PerBit enable=1, Macro0, CA PI delay=34
4351 20:15:14.105740
4352 20:15:14.109221 [CBTSetCACLKResult] CA Dly = 34
4353 20:15:14.109303 CS Dly: 5 (0~36)
4354 20:15:14.109368 ==
4355 20:15:14.112308 Dram Type= 6, Freq= 0, CH_1, rank 1
4356 20:15:14.115348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 20:15:14.115492 ==
4358 20:15:14.122572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 20:15:14.128915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4360 20:15:14.132291 [CA 0] Center 35 (5~66) winsize 62
4361 20:15:14.135519 [CA 1] Center 35 (5~66) winsize 62
4362 20:15:14.138548 [CA 2] Center 34 (4~65) winsize 62
4363 20:15:14.141922 [CA 3] Center 34 (3~65) winsize 63
4364 20:15:14.145398 [CA 4] Center 34 (3~65) winsize 63
4365 20:15:14.148408 [CA 5] Center 34 (3~65) winsize 63
4366 20:15:14.148527
4367 20:15:14.151715 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4368 20:15:14.151837
4369 20:15:14.155466 [CATrainingPosCal] consider 2 rank data
4370 20:15:14.158071 u2DelayCellTimex100 = 270/100 ps
4371 20:15:14.161477 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4372 20:15:14.165205 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4373 20:15:14.168498 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4374 20:15:14.171523 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4375 20:15:14.178182 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4376 20:15:14.181248 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4377 20:15:14.181373
4378 20:15:14.184503 CA PerBit enable=1, Macro0, CA PI delay=34
4379 20:15:14.184627
4380 20:15:14.187813 [CBTSetCACLKResult] CA Dly = 34
4381 20:15:14.187936 CS Dly: 5 (0~36)
4382 20:15:14.188048
4383 20:15:14.191662 ----->DramcWriteLeveling(PI) begin...
4384 20:15:14.191786 ==
4385 20:15:14.195341 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 20:15:14.201384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 20:15:14.201510 ==
4388 20:15:14.204148 Write leveling (Byte 0): 28 => 28
4389 20:15:14.207464 Write leveling (Byte 1): 28 => 28
4390 20:15:14.210906 DramcWriteLeveling(PI) end<-----
4391 20:15:14.211029
4392 20:15:14.211135 ==
4393 20:15:14.214575 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 20:15:14.217392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 20:15:14.217513 ==
4396 20:15:14.220890 [Gating] SW mode calibration
4397 20:15:14.227949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4398 20:15:14.234227 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4399 20:15:14.236962 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 20:15:14.240752 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 20:15:14.246806 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 20:15:14.250344 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
4403 20:15:14.253800 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
4404 20:15:14.260238 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 20:15:14.263260 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 20:15:14.266710 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 20:15:14.273185 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 20:15:14.276599 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 20:15:14.280378 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4410 20:15:14.286585 0 10 12 | B1->B0 | 3131 3333 | 0 0 | (0 0) (1 1)
4411 20:15:14.290242 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 20:15:14.293402 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 20:15:14.299907 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 20:15:14.303082 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 20:15:14.306308 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 20:15:14.312660 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 20:15:14.316653 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 20:15:14.319211 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4419 20:15:14.326134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 20:15:14.329198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 20:15:14.332641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 20:15:14.338936 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 20:15:14.342336 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 20:15:14.345383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 20:15:14.353001 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 20:15:14.355284 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 20:15:14.358549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 20:15:14.365490 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 20:15:14.368562 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 20:15:14.371983 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 20:15:14.378694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 20:15:14.382723 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 20:15:14.385056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 20:15:14.391460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4435 20:15:14.394652 Total UI for P1: 0, mck2ui 16
4436 20:15:14.398035 best dqsien dly found for B0: ( 0, 13, 10)
4437 20:15:14.401470 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4438 20:15:14.404561 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 20:15:14.408461 Total UI for P1: 0, mck2ui 16
4440 20:15:14.411642 best dqsien dly found for B1: ( 0, 13, 14)
4441 20:15:14.414669 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4442 20:15:14.421725 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4443 20:15:14.421806
4444 20:15:14.424625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4445 20:15:14.427631 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4446 20:15:14.431017 [Gating] SW calibration Done
4447 20:15:14.431137 ==
4448 20:15:14.434321 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 20:15:14.437507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 20:15:14.437685 ==
4451 20:15:14.440799 RX Vref Scan: 0
4452 20:15:14.440907
4453 20:15:14.440973 RX Vref 0 -> 0, step: 1
4454 20:15:14.441067
4455 20:15:14.444594 RX Delay -230 -> 252, step: 16
4456 20:15:14.447423 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4457 20:15:14.454899 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4458 20:15:14.457909 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4459 20:15:14.461612 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4460 20:15:14.463909 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4461 20:15:14.470885 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4462 20:15:14.473952 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4463 20:15:14.477231 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4464 20:15:14.480276 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4465 20:15:14.483472 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4466 20:15:14.490593 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4467 20:15:14.494353 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4468 20:15:14.497314 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4469 20:15:14.500444 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4470 20:15:14.506839 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4471 20:15:14.510626 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4472 20:15:14.510707 ==
4473 20:15:14.513250 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 20:15:14.516687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 20:15:14.516768 ==
4476 20:15:14.520122 DQS Delay:
4477 20:15:14.520202 DQS0 = 0, DQS1 = 0
4478 20:15:14.523702 DQM Delay:
4479 20:15:14.523783 DQM0 = 43, DQM1 = 38
4480 20:15:14.526402 DQ Delay:
4481 20:15:14.526483 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4482 20:15:14.529961 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4483 20:15:14.532740 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4484 20:15:14.536519 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4485 20:15:14.539743
4486 20:15:14.539824
4487 20:15:14.539888 ==
4488 20:15:14.542752 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 20:15:14.546338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 20:15:14.546420 ==
4491 20:15:14.546484
4492 20:15:14.546543
4493 20:15:14.549517 TX Vref Scan disable
4494 20:15:14.549598 == TX Byte 0 ==
4495 20:15:14.555924 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4496 20:15:14.559550 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4497 20:15:14.559631 == TX Byte 1 ==
4498 20:15:14.566284 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 20:15:14.569845 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 20:15:14.569926 ==
4501 20:15:14.572621 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 20:15:14.576199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 20:15:14.576281 ==
4504 20:15:14.576345
4505 20:15:14.576403
4506 20:15:14.579117 TX Vref Scan disable
4507 20:15:14.582628 == TX Byte 0 ==
4508 20:15:14.585682 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4509 20:15:14.589782 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4510 20:15:14.592755 == TX Byte 1 ==
4511 20:15:14.595668 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 20:15:14.598934 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 20:15:14.603098
4514 20:15:14.603178 [DATLAT]
4515 20:15:14.603242 Freq=600, CH1 RK0
4516 20:15:14.603303
4517 20:15:14.605993 DATLAT Default: 0x9
4518 20:15:14.606074 0, 0xFFFF, sum = 0
4519 20:15:14.609180 1, 0xFFFF, sum = 0
4520 20:15:14.609262 2, 0xFFFF, sum = 0
4521 20:15:14.612522 3, 0xFFFF, sum = 0
4522 20:15:14.612604 4, 0xFFFF, sum = 0
4523 20:15:14.615663 5, 0xFFFF, sum = 0
4524 20:15:14.619049 6, 0xFFFF, sum = 0
4525 20:15:14.619132 7, 0xFFFF, sum = 0
4526 20:15:14.619198 8, 0x0, sum = 1
4527 20:15:14.622315 9, 0x0, sum = 2
4528 20:15:14.622397 10, 0x0, sum = 3
4529 20:15:14.625424 11, 0x0, sum = 4
4530 20:15:14.625506 best_step = 9
4531 20:15:14.625570
4532 20:15:14.625630 ==
4533 20:15:14.628740 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 20:15:14.635383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 20:15:14.635465 ==
4536 20:15:14.635530 RX Vref Scan: 1
4537 20:15:14.635590
4538 20:15:14.638458 RX Vref 0 -> 0, step: 1
4539 20:15:14.638539
4540 20:15:14.642257 RX Delay -179 -> 252, step: 8
4541 20:15:14.642338
4542 20:15:14.645669 Set Vref, RX VrefLevel [Byte0]: 52
4543 20:15:14.648323 [Byte1]: 51
4544 20:15:14.648404
4545 20:15:14.651674 Final RX Vref Byte 0 = 52 to rank0
4546 20:15:14.655833 Final RX Vref Byte 1 = 51 to rank0
4547 20:15:14.658390 Final RX Vref Byte 0 = 52 to rank1
4548 20:15:14.661433 Final RX Vref Byte 1 = 51 to rank1==
4549 20:15:14.664808 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 20:15:14.668171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 20:15:14.668256 ==
4552 20:15:14.672136 DQS Delay:
4553 20:15:14.672216 DQS0 = 0, DQS1 = 0
4554 20:15:14.674910 DQM Delay:
4555 20:15:14.674990 DQM0 = 41, DQM1 = 34
4556 20:15:14.678352 DQ Delay:
4557 20:15:14.678432 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4558 20:15:14.681346 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4559 20:15:14.684593 DQ8 =16, DQ9 =24, DQ10 =36, DQ11 =28
4560 20:15:14.688347 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4561 20:15:14.688445
4562 20:15:14.691203
4563 20:15:14.697909 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4564 20:15:14.701327 CH1 RK0: MR19=808, MR18=2B45
4565 20:15:14.707627 CH1_RK0: MR19=0x808, MR18=0x2B45, DQSOSC=396, MR23=63, INC=167, DEC=111
4566 20:15:14.707711
4567 20:15:14.711254 ----->DramcWriteLeveling(PI) begin...
4568 20:15:14.711336 ==
4569 20:15:14.714152 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 20:15:14.717837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 20:15:14.717918 ==
4572 20:15:14.720949 Write leveling (Byte 0): 29 => 29
4573 20:15:14.724407 Write leveling (Byte 1): 30 => 30
4574 20:15:14.727461 DramcWriteLeveling(PI) end<-----
4575 20:15:14.727543
4576 20:15:14.727607 ==
4577 20:15:14.730608 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 20:15:14.734129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 20:15:14.734211 ==
4580 20:15:14.737946 [Gating] SW mode calibration
4581 20:15:14.744356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4582 20:15:14.750557 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4583 20:15:14.753491 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 20:15:14.760187 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 20:15:14.763837 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4586 20:15:14.767177 0 9 12 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (1 1)
4587 20:15:14.773276 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 20:15:14.776509 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 20:15:14.779931 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 20:15:14.786308 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 20:15:14.789898 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 20:15:14.793241 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 20:15:14.800078 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4594 20:15:14.803062 0 10 12 | B1->B0 | 2e2e 4343 | 1 0 | (0 0) (0 0)
4595 20:15:14.806363 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 20:15:14.812833 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 20:15:14.816082 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 20:15:14.819721 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 20:15:14.826605 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 20:15:14.829273 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 20:15:14.832525 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4602 20:15:14.839242 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 20:15:14.842688 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4604 20:15:14.845779 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 20:15:14.852498 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 20:15:14.855792 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 20:15:14.859299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 20:15:14.865492 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 20:15:14.869150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 20:15:14.872485 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 20:15:14.878832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 20:15:14.881998 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 20:15:14.886414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 20:15:14.892027 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 20:15:14.895329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 20:15:14.898379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 20:15:14.904683 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4618 20:15:14.908097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4619 20:15:14.911541 Total UI for P1: 0, mck2ui 16
4620 20:15:14.914700 best dqsien dly found for B0: ( 0, 13, 8)
4621 20:15:14.918382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 20:15:14.921550 Total UI for P1: 0, mck2ui 16
4623 20:15:14.924977 best dqsien dly found for B1: ( 0, 13, 12)
4624 20:15:14.927818 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4625 20:15:14.931357 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4626 20:15:14.934504
4627 20:15:14.937859 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4628 20:15:14.941290 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4629 20:15:14.944532 [Gating] SW calibration Done
4630 20:15:14.944614 ==
4631 20:15:14.947665 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 20:15:14.950966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 20:15:14.951047 ==
4634 20:15:14.951112 RX Vref Scan: 0
4635 20:15:14.954169
4636 20:15:14.954250 RX Vref 0 -> 0, step: 1
4637 20:15:14.954314
4638 20:15:14.957555 RX Delay -230 -> 252, step: 16
4639 20:15:14.960959 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4640 20:15:14.967812 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4641 20:15:14.971205 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4642 20:15:14.974165 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4643 20:15:14.977765 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4644 20:15:14.980867 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4645 20:15:14.987932 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4646 20:15:14.990831 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4647 20:15:14.994466 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4648 20:15:14.997268 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4649 20:15:15.003557 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4650 20:15:15.006775 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4651 20:15:15.010490 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4652 20:15:15.013763 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4653 20:15:15.020149 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4654 20:15:15.023462 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4655 20:15:15.023568 ==
4656 20:15:15.026799 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 20:15:15.029992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 20:15:15.030074 ==
4659 20:15:15.033177 DQS Delay:
4660 20:15:15.033258 DQS0 = 0, DQS1 = 0
4661 20:15:15.037058 DQM Delay:
4662 20:15:15.037139 DQM0 = 39, DQM1 = 38
4663 20:15:15.037235 DQ Delay:
4664 20:15:15.040191 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4665 20:15:15.043203 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4666 20:15:15.046471 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4667 20:15:15.049946 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4668 20:15:15.050027
4669 20:15:15.050091
4670 20:15:15.050150 ==
4671 20:15:15.053200 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 20:15:15.059690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 20:15:15.059770 ==
4674 20:15:15.059901
4675 20:15:15.059980
4676 20:15:15.062877 TX Vref Scan disable
4677 20:15:15.062958 == TX Byte 0 ==
4678 20:15:15.066288 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4679 20:15:15.073113 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4680 20:15:15.073195 == TX Byte 1 ==
4681 20:15:15.079685 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4682 20:15:15.082934 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4683 20:15:15.083016 ==
4684 20:15:15.086129 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 20:15:15.089277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 20:15:15.089359 ==
4687 20:15:15.089424
4688 20:15:15.089484
4689 20:15:15.092856 TX Vref Scan disable
4690 20:15:15.095982 == TX Byte 0 ==
4691 20:15:15.099822 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4692 20:15:15.102653 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4693 20:15:15.106248 == TX Byte 1 ==
4694 20:15:15.109054 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4695 20:15:15.112444 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4696 20:15:15.112525
4697 20:15:15.115856 [DATLAT]
4698 20:15:15.115937 Freq=600, CH1 RK1
4699 20:15:15.116003
4700 20:15:15.118811 DATLAT Default: 0x9
4701 20:15:15.118891 0, 0xFFFF, sum = 0
4702 20:15:15.122149 1, 0xFFFF, sum = 0
4703 20:15:15.122231 2, 0xFFFF, sum = 0
4704 20:15:15.125700 3, 0xFFFF, sum = 0
4705 20:15:15.125782 4, 0xFFFF, sum = 0
4706 20:15:15.128960 5, 0xFFFF, sum = 0
4707 20:15:15.129042 6, 0xFFFF, sum = 0
4708 20:15:15.132369 7, 0xFFFF, sum = 0
4709 20:15:15.132452 8, 0x0, sum = 1
4710 20:15:15.135762 9, 0x0, sum = 2
4711 20:15:15.135844 10, 0x0, sum = 3
4712 20:15:15.138660 11, 0x0, sum = 4
4713 20:15:15.138742 best_step = 9
4714 20:15:15.138806
4715 20:15:15.138866 ==
4716 20:15:15.142363 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 20:15:15.148542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 20:15:15.148623 ==
4719 20:15:15.148688 RX Vref Scan: 0
4720 20:15:15.148747
4721 20:15:15.152001 RX Vref 0 -> 0, step: 1
4722 20:15:15.152085
4723 20:15:15.155524 RX Delay -179 -> 252, step: 8
4724 20:15:15.158559 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4725 20:15:15.165145 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4726 20:15:15.168515 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4727 20:15:15.172430 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4728 20:15:15.174978 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4729 20:15:15.181444 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4730 20:15:15.185279 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4731 20:15:15.187960 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4732 20:15:15.191610 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4733 20:15:15.194633 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4734 20:15:15.201070 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4735 20:15:15.204400 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4736 20:15:15.208395 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4737 20:15:15.214781 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4738 20:15:15.218166 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4739 20:15:15.221762 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4740 20:15:15.221844 ==
4741 20:15:15.224281 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 20:15:15.228052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 20:15:15.228133 ==
4744 20:15:15.230878 DQS Delay:
4745 20:15:15.230985 DQS0 = 0, DQS1 = 0
4746 20:15:15.234178 DQM Delay:
4747 20:15:15.234260 DQM0 = 38, DQM1 = 36
4748 20:15:15.234325 DQ Delay:
4749 20:15:15.237672 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4750 20:15:15.241031 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4751 20:15:15.244373 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4752 20:15:15.247649 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4753 20:15:15.247729
4754 20:15:15.251477
4755 20:15:15.257284 [DQSOSCAuto] RK1, (LSB)MR18= 0x375d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4756 20:15:15.260686 CH1 RK1: MR19=808, MR18=375D
4757 20:15:15.267700 CH1_RK1: MR19=0x808, MR18=0x375D, DQSOSC=392, MR23=63, INC=170, DEC=113
4758 20:15:15.270604 [RxdqsGatingPostProcess] freq 600
4759 20:15:15.274290 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4760 20:15:15.276860 Pre-setting of DQS Precalculation
4761 20:15:15.283574 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4762 20:15:15.290441 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4763 20:15:15.296701 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4764 20:15:15.296783
4765 20:15:15.296848
4766 20:15:15.300125 [Calibration Summary] 1200 Mbps
4767 20:15:15.300211 CH 0, Rank 0
4768 20:15:15.303341 SW Impedance : PASS
4769 20:15:15.306544 DUTY Scan : NO K
4770 20:15:15.306625 ZQ Calibration : PASS
4771 20:15:15.309970 Jitter Meter : NO K
4772 20:15:15.313261 CBT Training : PASS
4773 20:15:15.313343 Write leveling : PASS
4774 20:15:15.316598 RX DQS gating : PASS
4775 20:15:15.320028 RX DQ/DQS(RDDQC) : PASS
4776 20:15:15.320109 TX DQ/DQS : PASS
4777 20:15:15.323004 RX DATLAT : PASS
4778 20:15:15.326761 RX DQ/DQS(Engine): PASS
4779 20:15:15.326842 TX OE : NO K
4780 20:15:15.326907 All Pass.
4781 20:15:15.329742
4782 20:15:15.329823 CH 0, Rank 1
4783 20:15:15.333420 SW Impedance : PASS
4784 20:15:15.333501 DUTY Scan : NO K
4785 20:15:15.336416 ZQ Calibration : PASS
4786 20:15:15.336497 Jitter Meter : NO K
4787 20:15:15.339982 CBT Training : PASS
4788 20:15:15.342972 Write leveling : PASS
4789 20:15:15.343053 RX DQS gating : PASS
4790 20:15:15.346352 RX DQ/DQS(RDDQC) : PASS
4791 20:15:15.349405 TX DQ/DQS : PASS
4792 20:15:15.349487 RX DATLAT : PASS
4793 20:15:15.352618 RX DQ/DQS(Engine): PASS
4794 20:15:15.356102 TX OE : NO K
4795 20:15:15.356183 All Pass.
4796 20:15:15.356247
4797 20:15:15.356306 CH 1, Rank 0
4798 20:15:15.359438 SW Impedance : PASS
4799 20:15:15.362574 DUTY Scan : NO K
4800 20:15:15.362655 ZQ Calibration : PASS
4801 20:15:15.366189 Jitter Meter : NO K
4802 20:15:15.369232 CBT Training : PASS
4803 20:15:15.369320 Write leveling : PASS
4804 20:15:15.372860 RX DQS gating : PASS
4805 20:15:15.375978 RX DQ/DQS(RDDQC) : PASS
4806 20:15:15.376060 TX DQ/DQS : PASS
4807 20:15:15.379399 RX DATLAT : PASS
4808 20:15:15.382335 RX DQ/DQS(Engine): PASS
4809 20:15:15.382416 TX OE : NO K
4810 20:15:15.385586 All Pass.
4811 20:15:15.385667
4812 20:15:15.385731 CH 1, Rank 1
4813 20:15:15.388956 SW Impedance : PASS
4814 20:15:15.389036 DUTY Scan : NO K
4815 20:15:15.392529 ZQ Calibration : PASS
4816 20:15:15.395912 Jitter Meter : NO K
4817 20:15:15.395993 CBT Training : PASS
4818 20:15:15.399084 Write leveling : PASS
4819 20:15:15.402433 RX DQS gating : PASS
4820 20:15:15.402539 RX DQ/DQS(RDDQC) : PASS
4821 20:15:15.405178 TX DQ/DQS : PASS
4822 20:15:15.408676 RX DATLAT : PASS
4823 20:15:15.408757 RX DQ/DQS(Engine): PASS
4824 20:15:15.412029 TX OE : NO K
4825 20:15:15.412110 All Pass.
4826 20:15:15.412175
4827 20:15:15.415121 DramC Write-DBI off
4828 20:15:15.418929 PER_BANK_REFRESH: Hybrid Mode
4829 20:15:15.419036 TX_TRACKING: ON
4830 20:15:15.428810 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4831 20:15:15.432215 [FAST_K] Save calibration result to emmc
4832 20:15:15.435238 dramc_set_vcore_voltage set vcore to 662500
4833 20:15:15.438525 Read voltage for 933, 3
4834 20:15:15.438606 Vio18 = 0
4835 20:15:15.438670 Vcore = 662500
4836 20:15:15.441633 Vdram = 0
4837 20:15:15.441714 Vddq = 0
4838 20:15:15.441778 Vmddr = 0
4839 20:15:15.448441 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4840 20:15:15.451896 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4841 20:15:15.455318 MEM_TYPE=3, freq_sel=17
4842 20:15:15.458384 sv_algorithm_assistance_LP4_1600
4843 20:15:15.461484 ============ PULL DRAM RESETB DOWN ============
4844 20:15:15.464451 ========== PULL DRAM RESETB DOWN end =========
4845 20:15:15.471620 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4846 20:15:15.474574 ===================================
4847 20:15:15.478127 LPDDR4 DRAM CONFIGURATION
4848 20:15:15.481225 ===================================
4849 20:15:15.481306 EX_ROW_EN[0] = 0x0
4850 20:15:15.484290 EX_ROW_EN[1] = 0x0
4851 20:15:15.484397 LP4Y_EN = 0x0
4852 20:15:15.487692 WORK_FSP = 0x0
4853 20:15:15.487773 WL = 0x3
4854 20:15:15.491592 RL = 0x3
4855 20:15:15.491673 BL = 0x2
4856 20:15:15.494086 RPST = 0x0
4857 20:15:15.494167 RD_PRE = 0x0
4858 20:15:15.497590 WR_PRE = 0x1
4859 20:15:15.497671 WR_PST = 0x0
4860 20:15:15.500989 DBI_WR = 0x0
4861 20:15:15.501071 DBI_RD = 0x0
4862 20:15:15.504277 OTF = 0x1
4863 20:15:15.507777 ===================================
4864 20:15:15.511371 ===================================
4865 20:15:15.511461 ANA top config
4866 20:15:15.514290 ===================================
4867 20:15:15.517461 DLL_ASYNC_EN = 0
4868 20:15:15.520919 ALL_SLAVE_EN = 1
4869 20:15:15.524568 NEW_RANK_MODE = 1
4870 20:15:15.524650 DLL_IDLE_MODE = 1
4871 20:15:15.527630 LP45_APHY_COMB_EN = 1
4872 20:15:15.530725 TX_ODT_DIS = 1
4873 20:15:15.533982 NEW_8X_MODE = 1
4874 20:15:15.537270 ===================================
4875 20:15:15.540468 ===================================
4876 20:15:15.543583 data_rate = 1866
4877 20:15:15.547026 CKR = 1
4878 20:15:15.547103 DQ_P2S_RATIO = 8
4879 20:15:15.550314 ===================================
4880 20:15:15.553771 CA_P2S_RATIO = 8
4881 20:15:15.557373 DQ_CA_OPEN = 0
4882 20:15:15.561784 DQ_SEMI_OPEN = 0
4883 20:15:15.563525 CA_SEMI_OPEN = 0
4884 20:15:15.567043 CA_FULL_RATE = 0
4885 20:15:15.567124 DQ_CKDIV4_EN = 1
4886 20:15:15.570321 CA_CKDIV4_EN = 1
4887 20:15:15.573461 CA_PREDIV_EN = 0
4888 20:15:15.576859 PH8_DLY = 0
4889 20:15:15.580506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4890 20:15:15.583767 DQ_AAMCK_DIV = 4
4891 20:15:15.583870 CA_AAMCK_DIV = 4
4892 20:15:15.587022 CA_ADMCK_DIV = 4
4893 20:15:15.590439 DQ_TRACK_CA_EN = 0
4894 20:15:15.593381 CA_PICK = 933
4895 20:15:15.596744 CA_MCKIO = 933
4896 20:15:15.600102 MCKIO_SEMI = 0
4897 20:15:15.603145 PLL_FREQ = 3732
4898 20:15:15.606541 DQ_UI_PI_RATIO = 32
4899 20:15:15.606622 CA_UI_PI_RATIO = 0
4900 20:15:15.609891 ===================================
4901 20:15:15.612979 ===================================
4902 20:15:15.616423 memory_type:LPDDR4
4903 20:15:15.619670 GP_NUM : 10
4904 20:15:15.619751 SRAM_EN : 1
4905 20:15:15.623270 MD32_EN : 0
4906 20:15:15.626203 ===================================
4907 20:15:15.629707 [ANA_INIT] >>>>>>>>>>>>>>
4908 20:15:15.632878 <<<<<< [CONFIGURE PHASE]: ANA_TX
4909 20:15:15.636270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4910 20:15:15.639778 ===================================
4911 20:15:15.639860 data_rate = 1866,PCW = 0X8f00
4912 20:15:15.642913 ===================================
4913 20:15:15.649351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4914 20:15:15.652462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 20:15:15.658892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 20:15:15.661954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4917 20:15:15.665932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4918 20:15:15.668715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4919 20:15:15.671827 [ANA_INIT] flow start
4920 20:15:15.675224 [ANA_INIT] PLL >>>>>>>>
4921 20:15:15.675332 [ANA_INIT] PLL <<<<<<<<
4922 20:15:15.678661 [ANA_INIT] MIDPI >>>>>>>>
4923 20:15:15.681970 [ANA_INIT] MIDPI <<<<<<<<
4924 20:15:15.685195 [ANA_INIT] DLL >>>>>>>>
4925 20:15:15.685277 [ANA_INIT] flow end
4926 20:15:15.688665 ============ LP4 DIFF to SE enter ============
4927 20:15:15.695253 ============ LP4 DIFF to SE exit ============
4928 20:15:15.695370 [ANA_INIT] <<<<<<<<<<<<<
4929 20:15:15.698691 [Flow] Enable top DCM control >>>>>
4930 20:15:15.701727 [Flow] Enable top DCM control <<<<<
4931 20:15:15.704986 Enable DLL master slave shuffle
4932 20:15:15.711696 ==============================================================
4933 20:15:15.711778 Gating Mode config
4934 20:15:15.718343 ==============================================================
4935 20:15:15.721438 Config description:
4936 20:15:15.731494 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4937 20:15:15.738044 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4938 20:15:15.741095 SELPH_MODE 0: By rank 1: By Phase
4939 20:15:15.747784 ==============================================================
4940 20:15:15.751275 GAT_TRACK_EN = 1
4941 20:15:15.755294 RX_GATING_MODE = 2
4942 20:15:15.757448 RX_GATING_TRACK_MODE = 2
4943 20:15:15.757529 SELPH_MODE = 1
4944 20:15:15.761212 PICG_EARLY_EN = 1
4945 20:15:15.763926 VALID_LAT_VALUE = 1
4946 20:15:15.770596 ==============================================================
4947 20:15:15.774094 Enter into Gating configuration >>>>
4948 20:15:15.777242 Exit from Gating configuration <<<<
4949 20:15:15.780375 Enter into DVFS_PRE_config >>>>>
4950 20:15:15.790892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4951 20:15:15.793900 Exit from DVFS_PRE_config <<<<<
4952 20:15:15.797072 Enter into PICG configuration >>>>
4953 20:15:15.800509 Exit from PICG configuration <<<<
4954 20:15:15.804126 [RX_INPUT] configuration >>>>>
4955 20:15:15.806654 [RX_INPUT] configuration <<<<<
4956 20:15:15.810065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4957 20:15:15.816954 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4958 20:15:15.823647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4959 20:15:15.829863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4960 20:15:15.836509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 20:15:15.842989 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 20:15:15.846656 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4963 20:15:15.850036 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4964 20:15:15.853063 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4965 20:15:15.859265 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4966 20:15:15.862741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4967 20:15:15.865945 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4968 20:15:15.869090 ===================================
4969 20:15:15.872652 LPDDR4 DRAM CONFIGURATION
4970 20:15:15.876266 ===================================
4971 20:15:15.876347 EX_ROW_EN[0] = 0x0
4972 20:15:15.879484 EX_ROW_EN[1] = 0x0
4973 20:15:15.882552 LP4Y_EN = 0x0
4974 20:15:15.882633 WORK_FSP = 0x0
4975 20:15:15.885613 WL = 0x3
4976 20:15:15.885694 RL = 0x3
4977 20:15:15.889024 BL = 0x2
4978 20:15:15.889158 RPST = 0x0
4979 20:15:15.892414 RD_PRE = 0x0
4980 20:15:15.892487 WR_PRE = 0x1
4981 20:15:15.895753 WR_PST = 0x0
4982 20:15:15.895833 DBI_WR = 0x0
4983 20:15:15.899072 DBI_RD = 0x0
4984 20:15:15.899152 OTF = 0x1
4985 20:15:15.903244 ===================================
4986 20:15:15.909125 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4987 20:15:15.912170 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4988 20:15:15.915177 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 20:15:15.918465 ===================================
4990 20:15:15.921644 LPDDR4 DRAM CONFIGURATION
4991 20:15:15.925097 ===================================
4992 20:15:15.928563 EX_ROW_EN[0] = 0x10
4993 20:15:15.928643 EX_ROW_EN[1] = 0x0
4994 20:15:15.931976 LP4Y_EN = 0x0
4995 20:15:15.932056 WORK_FSP = 0x0
4996 20:15:15.935268 WL = 0x3
4997 20:15:15.935382 RL = 0x3
4998 20:15:15.938692 BL = 0x2
4999 20:15:15.938772 RPST = 0x0
5000 20:15:15.941433 RD_PRE = 0x0
5001 20:15:15.941513 WR_PRE = 0x1
5002 20:15:15.944719 WR_PST = 0x0
5003 20:15:15.944799 DBI_WR = 0x0
5004 20:15:15.948566 DBI_RD = 0x0
5005 20:15:15.948646 OTF = 0x1
5006 20:15:15.951284 ===================================
5007 20:15:15.957968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5008 20:15:15.962832 nWR fixed to 30
5009 20:15:15.966484 [ModeRegInit_LP4] CH0 RK0
5010 20:15:15.966564 [ModeRegInit_LP4] CH0 RK1
5011 20:15:15.969688 [ModeRegInit_LP4] CH1 RK0
5012 20:15:15.972730 [ModeRegInit_LP4] CH1 RK1
5013 20:15:15.972810 match AC timing 9
5014 20:15:15.979531 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5015 20:15:15.982790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5016 20:15:15.986474 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5017 20:15:15.993393 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5018 20:15:15.995913 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5019 20:15:15.995993 ==
5020 20:15:15.999048 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 20:15:16.002290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5022 20:15:16.005749 ==
5023 20:15:16.008907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5024 20:15:16.015787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5025 20:15:16.018968 [CA 0] Center 37 (7~68) winsize 62
5026 20:15:16.022260 [CA 1] Center 37 (7~68) winsize 62
5027 20:15:16.025594 [CA 2] Center 34 (4~64) winsize 61
5028 20:15:16.028876 [CA 3] Center 34 (4~65) winsize 62
5029 20:15:16.032059 [CA 4] Center 33 (3~63) winsize 61
5030 20:15:16.035349 [CA 5] Center 32 (2~63) winsize 62
5031 20:15:16.035454
5032 20:15:16.038407 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5033 20:15:16.038487
5034 20:15:16.041981 [CATrainingPosCal] consider 1 rank data
5035 20:15:16.045282 u2DelayCellTimex100 = 270/100 ps
5036 20:15:16.049737 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5037 20:15:16.051552 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5038 20:15:16.054962 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5039 20:15:16.061689 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5040 20:15:16.064576 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5041 20:15:16.068089 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5042 20:15:16.068171
5043 20:15:16.071654 CA PerBit enable=1, Macro0, CA PI delay=32
5044 20:15:16.071736
5045 20:15:16.074830 [CBTSetCACLKResult] CA Dly = 32
5046 20:15:16.074911 CS Dly: 5 (0~36)
5047 20:15:16.078315 ==
5048 20:15:16.081591 Dram Type= 6, Freq= 0, CH_0, rank 1
5049 20:15:16.084399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 20:15:16.084479 ==
5051 20:15:16.088117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 20:15:16.094530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 20:15:16.098887 [CA 0] Center 38 (7~69) winsize 63
5054 20:15:16.101230 [CA 1] Center 37 (7~68) winsize 62
5055 20:15:16.104818 [CA 2] Center 34 (4~65) winsize 62
5056 20:15:16.107776 [CA 3] Center 34 (4~65) winsize 62
5057 20:15:16.111393 [CA 4] Center 33 (3~64) winsize 62
5058 20:15:16.114634 [CA 5] Center 32 (2~63) winsize 62
5059 20:15:16.114714
5060 20:15:16.117780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 20:15:16.117860
5062 20:15:16.121288 [CATrainingPosCal] consider 2 rank data
5063 20:15:16.124474 u2DelayCellTimex100 = 270/100 ps
5064 20:15:16.127636 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 20:15:16.134352 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5066 20:15:16.137481 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5067 20:15:16.140795 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5068 20:15:16.144571 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5069 20:15:16.147279 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5070 20:15:16.147427
5071 20:15:16.150679 CA PerBit enable=1, Macro0, CA PI delay=32
5072 20:15:16.150760
5073 20:15:16.154035 [CBTSetCACLKResult] CA Dly = 32
5074 20:15:16.157559 CS Dly: 6 (0~39)
5075 20:15:16.157639
5076 20:15:16.160741 ----->DramcWriteLeveling(PI) begin...
5077 20:15:16.160823 ==
5078 20:15:16.163898 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 20:15:16.167176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 20:15:16.167257 ==
5081 20:15:16.170979 Write leveling (Byte 0): 30 => 30
5082 20:15:16.174188 Write leveling (Byte 1): 27 => 27
5083 20:15:16.177250 DramcWriteLeveling(PI) end<-----
5084 20:15:16.177331
5085 20:15:16.177395 ==
5086 20:15:16.180437 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 20:15:16.183947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 20:15:16.184030 ==
5089 20:15:16.186872 [Gating] SW mode calibration
5090 20:15:16.193690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5091 20:15:16.200229 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5092 20:15:16.203389 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5093 20:15:16.210053 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5094 20:15:16.213291 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 20:15:16.216834 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 20:15:16.223039 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 20:15:16.226655 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 20:15:16.229921 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5099 20:15:16.236253 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5100 20:15:16.239568 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5101 20:15:16.243235 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 20:15:16.249521 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 20:15:16.252714 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 20:15:16.256011 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 20:15:16.262320 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 20:15:16.265906 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5107 20:15:16.268993 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
5108 20:15:16.275549 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
5109 20:15:16.279118 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 20:15:16.282677 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 20:15:16.288827 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 20:15:16.292041 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 20:15:16.295471 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 20:15:16.301717 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 20:15:16.305393 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 20:15:16.308603 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5117 20:15:16.315503 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 20:15:16.318512 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 20:15:16.322049 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 20:15:16.327969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 20:15:16.332122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 20:15:16.334702 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 20:15:16.341435 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 20:15:16.344687 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 20:15:16.347896 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 20:15:16.354463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 20:15:16.357665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 20:15:16.360975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 20:15:16.367664 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 20:15:16.370735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 20:15:16.374150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 20:15:16.381326 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5133 20:15:16.384098 Total UI for P1: 0, mck2ui 16
5134 20:15:16.387733 best dqsien dly found for B0: ( 1, 2, 28)
5135 20:15:16.391107 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5136 20:15:16.394639 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 20:15:16.397363 Total UI for P1: 0, mck2ui 16
5138 20:15:16.400725 best dqsien dly found for B1: ( 1, 3, 2)
5139 20:15:16.404076 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5140 20:15:16.407350 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5141 20:15:16.407454
5142 20:15:16.413859 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5143 20:15:16.417051 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5144 20:15:16.420591 [Gating] SW calibration Done
5145 20:15:16.420673 ==
5146 20:15:16.423632 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 20:15:16.427159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 20:15:16.427241 ==
5149 20:15:16.427321 RX Vref Scan: 0
5150 20:15:16.427392
5151 20:15:16.430469 RX Vref 0 -> 0, step: 1
5152 20:15:16.430550
5153 20:15:16.433476 RX Delay -80 -> 252, step: 8
5154 20:15:16.436515 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5155 20:15:16.440292 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5156 20:15:16.447069 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5157 20:15:16.450039 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5158 20:15:16.453205 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5159 20:15:16.456841 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5160 20:15:16.459996 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5161 20:15:16.463052 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5162 20:15:16.469884 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5163 20:15:16.473206 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5164 20:15:16.476717 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5165 20:15:16.479406 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5166 20:15:16.483037 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5167 20:15:16.489566 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5168 20:15:16.492569 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5169 20:15:16.496571 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5170 20:15:16.496652 ==
5171 20:15:16.499152 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 20:15:16.502913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 20:15:16.503022 ==
5174 20:15:16.505773 DQS Delay:
5175 20:15:16.505883 DQS0 = 0, DQS1 = 0
5176 20:15:16.509080 DQM Delay:
5177 20:15:16.509161 DQM0 = 100, DQM1 = 89
5178 20:15:16.509226 DQ Delay:
5179 20:15:16.512161 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5180 20:15:16.516117 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5181 20:15:16.518785 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5182 20:15:16.522145 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5183 20:15:16.525762
5184 20:15:16.525843
5185 20:15:16.525906 ==
5186 20:15:16.528752 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 20:15:16.531982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 20:15:16.532064 ==
5189 20:15:16.532128
5190 20:15:16.532187
5191 20:15:16.535408 TX Vref Scan disable
5192 20:15:16.535490 == TX Byte 0 ==
5193 20:15:16.542255 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5194 20:15:16.545427 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5195 20:15:16.545508 == TX Byte 1 ==
5196 20:15:16.551969 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5197 20:15:16.555315 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5198 20:15:16.555448 ==
5199 20:15:16.558870 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 20:15:16.561930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 20:15:16.562013 ==
5202 20:15:16.562078
5203 20:15:16.562137
5204 20:15:16.565224 TX Vref Scan disable
5205 20:15:16.568164 == TX Byte 0 ==
5206 20:15:16.571564 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5207 20:15:16.575826 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5208 20:15:16.578193 == TX Byte 1 ==
5209 20:15:16.581373 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 20:15:16.584906 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 20:15:16.587908
5212 20:15:16.588015 [DATLAT]
5213 20:15:16.588132 Freq=933, CH0 RK0
5214 20:15:16.588193
5215 20:15:16.591728 DATLAT Default: 0xd
5216 20:15:16.591809 0, 0xFFFF, sum = 0
5217 20:15:16.594671 1, 0xFFFF, sum = 0
5218 20:15:16.594753 2, 0xFFFF, sum = 0
5219 20:15:16.597951 3, 0xFFFF, sum = 0
5220 20:15:16.601421 4, 0xFFFF, sum = 0
5221 20:15:16.601503 5, 0xFFFF, sum = 0
5222 20:15:16.605538 6, 0xFFFF, sum = 0
5223 20:15:16.605621 7, 0xFFFF, sum = 0
5224 20:15:16.607854 8, 0xFFFF, sum = 0
5225 20:15:16.607936 9, 0xFFFF, sum = 0
5226 20:15:16.611018 10, 0x0, sum = 1
5227 20:15:16.611099 11, 0x0, sum = 2
5228 20:15:16.614559 12, 0x0, sum = 3
5229 20:15:16.614645 13, 0x0, sum = 4
5230 20:15:16.614711 best_step = 11
5231 20:15:16.617620
5232 20:15:16.617701 ==
5233 20:15:16.620790 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 20:15:16.624200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 20:15:16.624281 ==
5236 20:15:16.624346 RX Vref Scan: 1
5237 20:15:16.624406
5238 20:15:16.627713 RX Vref 0 -> 0, step: 1
5239 20:15:16.627793
5240 20:15:16.630804 RX Delay -61 -> 252, step: 4
5241 20:15:16.630887
5242 20:15:16.634220 Set Vref, RX VrefLevel [Byte0]: 52
5243 20:15:16.637335 [Byte1]: 59
5244 20:15:16.641393
5245 20:15:16.641482 Final RX Vref Byte 0 = 52 to rank0
5246 20:15:16.643941 Final RX Vref Byte 1 = 59 to rank0
5247 20:15:16.647506 Final RX Vref Byte 0 = 52 to rank1
5248 20:15:16.650522 Final RX Vref Byte 1 = 59 to rank1==
5249 20:15:16.653678 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 20:15:16.660653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 20:15:16.660735 ==
5252 20:15:16.660799 DQS Delay:
5253 20:15:16.664322 DQS0 = 0, DQS1 = 0
5254 20:15:16.664403 DQM Delay:
5255 20:15:16.664467 DQM0 = 98, DQM1 = 88
5256 20:15:16.667625 DQ Delay:
5257 20:15:16.670278 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =94
5258 20:15:16.673454 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5259 20:15:16.677060 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5260 20:15:16.680156 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5261 20:15:16.680237
5262 20:15:16.680302
5263 20:15:16.686606 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5264 20:15:16.689868 CH0 RK0: MR19=505, MR18=150F
5265 20:15:16.696664 CH0_RK0: MR19=0x505, MR18=0x150F, DQSOSC=415, MR23=63, INC=62, DEC=41
5266 20:15:16.696746
5267 20:15:16.699822 ----->DramcWriteLeveling(PI) begin...
5268 20:15:16.699905 ==
5269 20:15:16.702795 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 20:15:16.706288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 20:15:16.709654 ==
5272 20:15:16.709754 Write leveling (Byte 0): 32 => 32
5273 20:15:16.712896 Write leveling (Byte 1): 31 => 31
5274 20:15:16.716407 DramcWriteLeveling(PI) end<-----
5275 20:15:16.716489
5276 20:15:16.716553 ==
5277 20:15:16.719253 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 20:15:16.725923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 20:15:16.726004 ==
5280 20:15:16.729131 [Gating] SW mode calibration
5281 20:15:16.735700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5282 20:15:16.739852 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5283 20:15:16.746698 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5284 20:15:16.748954 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 20:15:16.752233 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 20:15:16.759017 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 20:15:16.762158 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 20:15:16.765451 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 20:15:16.771962 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5290 20:15:16.775300 0 14 28 | B1->B0 | 3333 2828 | 0 0 | (0 0) (0 0)
5291 20:15:16.778862 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5292 20:15:16.784930 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5293 20:15:16.788611 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 20:15:16.792153 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 20:15:16.798315 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 20:15:16.801659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 20:15:16.804669 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5298 20:15:16.811878 0 15 28 | B1->B0 | 2626 4040 | 0 0 | (0 0) (0 0)
5299 20:15:16.814702 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5300 20:15:16.818575 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 20:15:16.824685 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 20:15:16.827874 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 20:15:16.830955 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 20:15:16.838222 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 20:15:16.841599 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5306 20:15:16.844238 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5307 20:15:16.850711 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5308 20:15:16.854304 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 20:15:16.857435 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 20:15:16.864195 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 20:15:16.867660 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 20:15:16.870403 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 20:15:16.876922 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 20:15:16.880391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 20:15:16.883881 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 20:15:16.890448 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 20:15:16.893778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 20:15:16.896688 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 20:15:16.903482 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 20:15:16.906679 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 20:15:16.910251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 20:15:16.917180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5323 20:15:16.919774 Total UI for P1: 0, mck2ui 16
5324 20:15:16.923520 best dqsien dly found for B0: ( 1, 2, 26)
5325 20:15:16.927802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 20:15:16.929501 Total UI for P1: 0, mck2ui 16
5327 20:15:16.932761 best dqsien dly found for B1: ( 1, 2, 30)
5328 20:15:16.936164 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5329 20:15:16.939681 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5330 20:15:16.939762
5331 20:15:16.942877 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5332 20:15:16.950062 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5333 20:15:16.950144 [Gating] SW calibration Done
5334 20:15:16.950208 ==
5335 20:15:16.952943 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 20:15:16.959356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 20:15:16.959490 ==
5338 20:15:16.959556 RX Vref Scan: 0
5339 20:15:16.959616
5340 20:15:16.962614 RX Vref 0 -> 0, step: 1
5341 20:15:16.962698
5342 20:15:16.965895 RX Delay -80 -> 252, step: 8
5343 20:15:16.969140 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5344 20:15:16.973075 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5345 20:15:16.975742 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5346 20:15:16.979132 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5347 20:15:16.985611 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5348 20:15:16.989110 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5349 20:15:16.992408 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5350 20:15:16.995857 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5351 20:15:16.998878 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5352 20:15:17.001924 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5353 20:15:17.009002 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5354 20:15:17.011861 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5355 20:15:17.015001 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5356 20:15:17.019060 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5357 20:15:17.021885 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5358 20:15:17.028469 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5359 20:15:17.028590 ==
5360 20:15:17.031503 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 20:15:17.034970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 20:15:17.035090 ==
5363 20:15:17.035195 DQS Delay:
5364 20:15:17.038193 DQS0 = 0, DQS1 = 0
5365 20:15:17.038313 DQM Delay:
5366 20:15:17.041740 DQM0 = 97, DQM1 = 91
5367 20:15:17.041821 DQ Delay:
5368 20:15:17.044641 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5369 20:15:17.048123 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5370 20:15:17.051201 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5371 20:15:17.054455 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5372 20:15:17.054536
5373 20:15:17.054600
5374 20:15:17.054659 ==
5375 20:15:17.057752 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 20:15:17.061323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 20:15:17.064858 ==
5378 20:15:17.064939
5379 20:15:17.065002
5380 20:15:17.065062 TX Vref Scan disable
5381 20:15:17.067629 == TX Byte 0 ==
5382 20:15:17.071561 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5383 20:15:17.074482 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5384 20:15:17.077959 == TX Byte 1 ==
5385 20:15:17.081088 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5386 20:15:17.084116 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5387 20:15:17.087693 ==
5388 20:15:17.091098 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 20:15:17.094025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 20:15:17.094107 ==
5391 20:15:17.094171
5392 20:15:17.094230
5393 20:15:17.097252 TX Vref Scan disable
5394 20:15:17.097333 == TX Byte 0 ==
5395 20:15:17.104216 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5396 20:15:17.107699 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5397 20:15:17.107781 == TX Byte 1 ==
5398 20:15:17.114117 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5399 20:15:17.117956 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5400 20:15:17.118037
5401 20:15:17.118102 [DATLAT]
5402 20:15:17.120543 Freq=933, CH0 RK1
5403 20:15:17.120671
5404 20:15:17.120782 DATLAT Default: 0xb
5405 20:15:17.123735 0, 0xFFFF, sum = 0
5406 20:15:17.123860 1, 0xFFFF, sum = 0
5407 20:15:17.127334 2, 0xFFFF, sum = 0
5408 20:15:17.127503 3, 0xFFFF, sum = 0
5409 20:15:17.130381 4, 0xFFFF, sum = 0
5410 20:15:17.134081 5, 0xFFFF, sum = 0
5411 20:15:17.134206 6, 0xFFFF, sum = 0
5412 20:15:17.137149 7, 0xFFFF, sum = 0
5413 20:15:17.137272 8, 0xFFFF, sum = 0
5414 20:15:17.140317 9, 0xFFFF, sum = 0
5415 20:15:17.140439 10, 0x0, sum = 1
5416 20:15:17.143514 11, 0x0, sum = 2
5417 20:15:17.143612 12, 0x0, sum = 3
5418 20:15:17.146931 13, 0x0, sum = 4
5419 20:15:17.147052 best_step = 11
5420 20:15:17.147165
5421 20:15:17.147273 ==
5422 20:15:17.150212 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 20:15:17.153218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 20:15:17.153339 ==
5425 20:15:17.156718 RX Vref Scan: 0
5426 20:15:17.156832
5427 20:15:17.160290 RX Vref 0 -> 0, step: 1
5428 20:15:17.160411
5429 20:15:17.160523 RX Delay -53 -> 252, step: 4
5430 20:15:17.167744 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5431 20:15:17.171141 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5432 20:15:17.174526 iDelay=195, Bit 2, Center 94 (7 ~ 182) 176
5433 20:15:17.177938 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5434 20:15:17.181653 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5435 20:15:17.184375 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5436 20:15:17.191567 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5437 20:15:17.194487 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5438 20:15:17.197799 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5439 20:15:17.200722 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5440 20:15:17.204275 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5441 20:15:17.211637 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5442 20:15:17.213819 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5443 20:15:17.217492 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5444 20:15:17.220576 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5445 20:15:17.223635 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5446 20:15:17.223756 ==
5447 20:15:17.226831 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 20:15:17.233648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 20:15:17.233774 ==
5450 20:15:17.233881 DQS Delay:
5451 20:15:17.236920 DQS0 = 0, DQS1 = 0
5452 20:15:17.237038 DQM Delay:
5453 20:15:17.240457 DQM0 = 97, DQM1 = 89
5454 20:15:17.240575 DQ Delay:
5455 20:15:17.243740 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =96
5456 20:15:17.247087 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5457 20:15:17.249994 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5458 20:15:17.253263 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =94
5459 20:15:17.253381
5460 20:15:17.253494
5461 20:15:17.259951 [DQSOSCAuto] RK1, (LSB)MR18= 0x120f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5462 20:15:17.263705 CH0 RK1: MR19=505, MR18=120F
5463 20:15:17.269723 CH0_RK1: MR19=0x505, MR18=0x120F, DQSOSC=416, MR23=63, INC=62, DEC=41
5464 20:15:17.272813 [RxdqsGatingPostProcess] freq 933
5465 20:15:17.279631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5466 20:15:17.282900 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 20:15:17.286360 best DQS1 dly(2T, 0.5T) = (0, 11)
5468 20:15:17.289407 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 20:15:17.289511 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5470 20:15:17.293073 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 20:15:17.295923 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 20:15:17.299544 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 20:15:17.302499 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 20:15:17.306034 Pre-setting of DQS Precalculation
5475 20:15:17.312697 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5476 20:15:17.312780 ==
5477 20:15:17.315892 Dram Type= 6, Freq= 0, CH_1, rank 0
5478 20:15:17.319129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 20:15:17.319209 ==
5480 20:15:17.325821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5481 20:15:17.332285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5482 20:15:17.336714 [CA 0] Center 36 (6~67) winsize 62
5483 20:15:17.338798 [CA 1] Center 36 (6~67) winsize 62
5484 20:15:17.342084 [CA 2] Center 34 (4~65) winsize 62
5485 20:15:17.345716 [CA 3] Center 34 (4~64) winsize 61
5486 20:15:17.349230 [CA 4] Center 34 (4~64) winsize 61
5487 20:15:17.352003 [CA 5] Center 33 (3~64) winsize 62
5488 20:15:17.352087
5489 20:15:17.355294 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5490 20:15:17.355428
5491 20:15:17.358499 [CATrainingPosCal] consider 1 rank data
5492 20:15:17.361936 u2DelayCellTimex100 = 270/100 ps
5493 20:15:17.365068 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 20:15:17.368328 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5495 20:15:17.371709 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5496 20:15:17.375756 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5497 20:15:17.378329 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5498 20:15:17.381702 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5499 20:15:17.385238
5500 20:15:17.388248 CA PerBit enable=1, Macro0, CA PI delay=33
5501 20:15:17.388329
5502 20:15:17.391283 [CBTSetCACLKResult] CA Dly = 33
5503 20:15:17.391387 CS Dly: 5 (0~36)
5504 20:15:17.391468 ==
5505 20:15:17.394557 Dram Type= 6, Freq= 0, CH_1, rank 1
5506 20:15:17.398457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 20:15:17.398538 ==
5508 20:15:17.404771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 20:15:17.411260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5510 20:15:17.414473 [CA 0] Center 36 (6~66) winsize 61
5511 20:15:17.417434 [CA 1] Center 36 (6~67) winsize 62
5512 20:15:17.421180 [CA 2] Center 34 (4~65) winsize 62
5513 20:15:17.424471 [CA 3] Center 33 (3~64) winsize 62
5514 20:15:17.427384 [CA 4] Center 33 (3~64) winsize 62
5515 20:15:17.430990 [CA 5] Center 33 (3~64) winsize 62
5516 20:15:17.431095
5517 20:15:17.434350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5518 20:15:17.434455
5519 20:15:17.437871 [CATrainingPosCal] consider 2 rank data
5520 20:15:17.440664 u2DelayCellTimex100 = 270/100 ps
5521 20:15:17.444319 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5522 20:15:17.447270 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 20:15:17.450544 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5524 20:15:17.457363 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 20:15:17.460306 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5526 20:15:17.463586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 20:15:17.463666
5528 20:15:17.466898 CA PerBit enable=1, Macro0, CA PI delay=33
5529 20:15:17.466977
5530 20:15:17.470155 [CBTSetCACLKResult] CA Dly = 33
5531 20:15:17.470235 CS Dly: 6 (0~38)
5532 20:15:17.470298
5533 20:15:17.473482 ----->DramcWriteLeveling(PI) begin...
5534 20:15:17.476840 ==
5535 20:15:17.480501 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 20:15:17.483296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 20:15:17.483401 ==
5538 20:15:17.486651 Write leveling (Byte 0): 26 => 26
5539 20:15:17.490113 Write leveling (Byte 1): 28 => 28
5540 20:15:17.493204 DramcWriteLeveling(PI) end<-----
5541 20:15:17.493284
5542 20:15:17.493347 ==
5543 20:15:17.497157 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 20:15:17.499783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 20:15:17.499863 ==
5546 20:15:17.503118 [Gating] SW mode calibration
5547 20:15:17.509804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 20:15:17.516069 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5549 20:15:17.519855 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 20:15:17.522691 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 20:15:17.529312 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 20:15:17.532664 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 20:15:17.535815 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 20:15:17.542541 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 20:15:17.545908 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
5556 20:15:17.548989 0 14 28 | B1->B0 | 2b2b 2424 | 1 0 | (1 1) (1 1)
5557 20:15:17.555622 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5558 20:15:17.559293 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 20:15:17.562700 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 20:15:17.569158 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 20:15:17.572176 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 20:15:17.575560 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 20:15:17.582466 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5564 20:15:17.585220 0 15 28 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
5565 20:15:17.588399 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 20:15:17.595631 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 20:15:17.598327 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 20:15:17.601997 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 20:15:17.608519 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 20:15:17.611872 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 20:15:17.614877 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5572 20:15:17.621464 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5573 20:15:17.624833 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 20:15:17.628081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 20:15:17.634722 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 20:15:17.638374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 20:15:17.641280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 20:15:17.648250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 20:15:17.651141 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 20:15:17.654349 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 20:15:17.661098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 20:15:17.664252 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 20:15:17.667456 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 20:15:17.674525 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 20:15:17.677671 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 20:15:17.680725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 20:15:17.687342 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5588 20:15:17.690582 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5589 20:15:17.694243 Total UI for P1: 0, mck2ui 16
5590 20:15:17.697025 best dqsien dly found for B1: ( 1, 2, 26)
5591 20:15:17.700685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5592 20:15:17.703799 Total UI for P1: 0, mck2ui 16
5593 20:15:17.707307 best dqsien dly found for B0: ( 1, 2, 26)
5594 20:15:17.710200 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5595 20:15:17.713566 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5596 20:15:17.716803
5597 20:15:17.720241 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5598 20:15:17.723754 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5599 20:15:17.726816 [Gating] SW calibration Done
5600 20:15:17.726897 ==
5601 20:15:17.730091 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 20:15:17.733258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 20:15:17.733365 ==
5604 20:15:17.736641 RX Vref Scan: 0
5605 20:15:17.736739
5606 20:15:17.736828 RX Vref 0 -> 0, step: 1
5607 20:15:17.736914
5608 20:15:17.739784 RX Delay -80 -> 252, step: 8
5609 20:15:17.742882 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5610 20:15:17.746688 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5611 20:15:17.752919 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5612 20:15:17.756495 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5613 20:15:17.759706 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5614 20:15:17.763661 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5615 20:15:17.766275 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5616 20:15:17.769832 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5617 20:15:17.776365 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5618 20:15:17.779534 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5619 20:15:17.782999 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5620 20:15:17.786100 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5621 20:15:17.789206 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5622 20:15:17.795907 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5623 20:15:17.799248 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5624 20:15:17.802941 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5625 20:15:17.803022 ==
5626 20:15:17.805544 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 20:15:17.809058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 20:15:17.812214 ==
5629 20:15:17.812298 DQS Delay:
5630 20:15:17.812362 DQS0 = 0, DQS1 = 0
5631 20:15:17.815541 DQM Delay:
5632 20:15:17.815623 DQM0 = 100, DQM1 = 95
5633 20:15:17.818560 DQ Delay:
5634 20:15:17.822306 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5635 20:15:17.825624 DQ4 =99, DQ5 =107, DQ6 =111, DQ7 =99
5636 20:15:17.825709 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5637 20:15:17.832132 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5638 20:15:17.832213
5639 20:15:17.832276
5640 20:15:17.832335 ==
5641 20:15:17.835530 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 20:15:17.838470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 20:15:17.838563 ==
5644 20:15:17.838627
5645 20:15:17.838685
5646 20:15:17.842323 TX Vref Scan disable
5647 20:15:17.842431 == TX Byte 0 ==
5648 20:15:17.849056 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5649 20:15:17.851867 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5650 20:15:17.851948 == TX Byte 1 ==
5651 20:15:17.858549 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5652 20:15:17.861929 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5653 20:15:17.862009 ==
5654 20:15:17.865366 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 20:15:17.868451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 20:15:17.868532 ==
5657 20:15:17.868595
5658 20:15:17.871682
5659 20:15:17.871762 TX Vref Scan disable
5660 20:15:17.875069 == TX Byte 0 ==
5661 20:15:17.878514 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5662 20:15:17.885004 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5663 20:15:17.885084 == TX Byte 1 ==
5664 20:15:17.888276 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5665 20:15:17.894727 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5666 20:15:17.894807
5667 20:15:17.894899 [DATLAT]
5668 20:15:17.894958 Freq=933, CH1 RK0
5669 20:15:17.895016
5670 20:15:17.898206 DATLAT Default: 0xd
5671 20:15:17.898287 0, 0xFFFF, sum = 0
5672 20:15:17.901538 1, 0xFFFF, sum = 0
5673 20:15:17.904581 2, 0xFFFF, sum = 0
5674 20:15:17.904662 3, 0xFFFF, sum = 0
5675 20:15:17.908390 4, 0xFFFF, sum = 0
5676 20:15:17.908475 5, 0xFFFF, sum = 0
5677 20:15:17.911816 6, 0xFFFF, sum = 0
5678 20:15:17.911898 7, 0xFFFF, sum = 0
5679 20:15:17.915089 8, 0xFFFF, sum = 0
5680 20:15:17.915170 9, 0xFFFF, sum = 0
5681 20:15:17.918071 10, 0x0, sum = 1
5682 20:15:17.918155 11, 0x0, sum = 2
5683 20:15:17.921047 12, 0x0, sum = 3
5684 20:15:17.921131 13, 0x0, sum = 4
5685 20:15:17.924680 best_step = 11
5686 20:15:17.924760
5687 20:15:17.924867 ==
5688 20:15:17.927710 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 20:15:17.931031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 20:15:17.931113 ==
5691 20:15:17.931177 RX Vref Scan: 1
5692 20:15:17.931262
5693 20:15:17.934624 RX Vref 0 -> 0, step: 1
5694 20:15:17.934704
5695 20:15:17.937693 RX Delay -53 -> 252, step: 4
5696 20:15:17.937773
5697 20:15:17.941068 Set Vref, RX VrefLevel [Byte0]: 52
5698 20:15:17.944097 [Byte1]: 51
5699 20:15:17.947604
5700 20:15:17.947684 Final RX Vref Byte 0 = 52 to rank0
5701 20:15:17.950826 Final RX Vref Byte 1 = 51 to rank0
5702 20:15:17.954174 Final RX Vref Byte 0 = 52 to rank1
5703 20:15:17.957361 Final RX Vref Byte 1 = 51 to rank1==
5704 20:15:17.960977 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 20:15:17.967582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 20:15:17.967663 ==
5707 20:15:17.967727 DQS Delay:
5708 20:15:17.971028 DQS0 = 0, DQS1 = 0
5709 20:15:17.971107 DQM Delay:
5710 20:15:17.971179 DQM0 = 98, DQM1 = 94
5711 20:15:17.974388 DQ Delay:
5712 20:15:17.977131 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =100
5713 20:15:17.980828 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5714 20:15:17.983705 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5715 20:15:17.987639 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5716 20:15:17.987723
5717 20:15:17.987786
5718 20:15:17.993911 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5719 20:15:17.997056 CH1 RK0: MR19=505, MR18=B1A
5720 20:15:18.003928 CH1_RK0: MR19=0x505, MR18=0xB1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5721 20:15:18.004010
5722 20:15:18.007047 ----->DramcWriteLeveling(PI) begin...
5723 20:15:18.007129 ==
5724 20:15:18.009966 Dram Type= 6, Freq= 0, CH_1, rank 1
5725 20:15:18.013406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 20:15:18.013488 ==
5727 20:15:18.017281 Write leveling (Byte 0): 28 => 28
5728 20:15:18.019983 Write leveling (Byte 1): 28 => 28
5729 20:15:18.023451 DramcWriteLeveling(PI) end<-----
5730 20:15:18.023582
5731 20:15:18.023701 ==
5732 20:15:18.026587 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 20:15:18.032978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 20:15:18.033101 ==
5735 20:15:18.036801 [Gating] SW mode calibration
5736 20:15:18.043012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5737 20:15:18.046260 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5738 20:15:18.053093 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5739 20:15:18.055981 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 20:15:18.059468 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 20:15:18.065683 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 20:15:18.069231 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 20:15:18.072473 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 20:15:18.079080 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
5745 20:15:18.082250 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5746 20:15:18.085458 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 20:15:18.092278 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 20:15:18.095826 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 20:15:18.098731 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 20:15:18.105492 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 20:15:18.108396 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 20:15:18.111602 0 15 24 | B1->B0 | 2525 3737 | 0 1 | (0 0) (0 0)
5753 20:15:18.118369 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5754 20:15:18.121594 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 20:15:18.124716 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 20:15:18.131413 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 20:15:18.135153 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 20:15:18.137807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 20:15:18.144550 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5760 20:15:18.148159 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5761 20:15:18.151110 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5762 20:15:18.158096 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5763 20:15:18.160917 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 20:15:18.164043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 20:15:18.170743 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 20:15:18.174375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 20:15:18.177976 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 20:15:18.183985 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 20:15:18.187735 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 20:15:18.190630 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 20:15:18.197521 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 20:15:18.200230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 20:15:18.203817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 20:15:18.210694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 20:15:18.214047 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 20:15:18.217154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 20:15:18.224099 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5778 20:15:18.226708 Total UI for P1: 0, mck2ui 16
5779 20:15:18.230460 best dqsien dly found for B0: ( 1, 2, 26)
5780 20:15:18.233373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 20:15:18.236363 Total UI for P1: 0, mck2ui 16
5782 20:15:18.240057 best dqsien dly found for B1: ( 1, 2, 28)
5783 20:15:18.243130 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5784 20:15:18.246396 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5785 20:15:18.246506
5786 20:15:18.250637 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5787 20:15:18.256341 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5788 20:15:18.256440 [Gating] SW calibration Done
5789 20:15:18.256518 ==
5790 20:15:18.259534 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 20:15:18.266149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 20:15:18.266231 ==
5793 20:15:18.266295 RX Vref Scan: 0
5794 20:15:18.266355
5795 20:15:18.269519 RX Vref 0 -> 0, step: 1
5796 20:15:18.269601
5797 20:15:18.272856 RX Delay -80 -> 252, step: 8
5798 20:15:18.276050 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5799 20:15:18.279381 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5800 20:15:18.282525 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5801 20:15:18.289069 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5802 20:15:18.292451 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5803 20:15:18.295700 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5804 20:15:18.299348 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5805 20:15:18.302219 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5806 20:15:18.305761 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5807 20:15:18.312674 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5808 20:15:18.315453 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5809 20:15:18.319034 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5810 20:15:18.322630 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5811 20:15:18.325253 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5812 20:15:18.332160 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5813 20:15:18.335258 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5814 20:15:18.335347 ==
5815 20:15:18.339068 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 20:15:18.341883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 20:15:18.341964 ==
5818 20:15:18.342029 DQS Delay:
5819 20:15:18.345306 DQS0 = 0, DQS1 = 0
5820 20:15:18.345389 DQM Delay:
5821 20:15:18.348380 DQM0 = 97, DQM1 = 93
5822 20:15:18.348504 DQ Delay:
5823 20:15:18.351673 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5824 20:15:18.354681 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5825 20:15:18.358031 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5826 20:15:18.361253 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5827 20:15:18.361383
5828 20:15:18.361494
5829 20:15:18.361612 ==
5830 20:15:18.365225 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 20:15:18.371338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 20:15:18.371498 ==
5833 20:15:18.371610
5834 20:15:18.371717
5835 20:15:18.374618 TX Vref Scan disable
5836 20:15:18.374737 == TX Byte 0 ==
5837 20:15:18.377642 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5838 20:15:18.384173 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5839 20:15:18.384297 == TX Byte 1 ==
5840 20:15:18.387781 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5841 20:15:18.394340 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5842 20:15:18.394471 ==
5843 20:15:18.398065 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 20:15:18.401078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 20:15:18.401208 ==
5846 20:15:18.401319
5847 20:15:18.401440
5848 20:15:18.404405 TX Vref Scan disable
5849 20:15:18.407770 == TX Byte 0 ==
5850 20:15:18.410509 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5851 20:15:18.414187 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5852 20:15:18.417098 == TX Byte 1 ==
5853 20:15:18.420629 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5854 20:15:18.424025 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5855 20:15:18.424145
5856 20:15:18.427607 [DATLAT]
5857 20:15:18.427732 Freq=933, CH1 RK1
5858 20:15:18.427846
5859 20:15:18.430469 DATLAT Default: 0xb
5860 20:15:18.430597 0, 0xFFFF, sum = 0
5861 20:15:18.433913 1, 0xFFFF, sum = 0
5862 20:15:18.434034 2, 0xFFFF, sum = 0
5863 20:15:18.436784 3, 0xFFFF, sum = 0
5864 20:15:18.436907 4, 0xFFFF, sum = 0
5865 20:15:18.440503 5, 0xFFFF, sum = 0
5866 20:15:18.440636 6, 0xFFFF, sum = 0
5867 20:15:18.443647 7, 0xFFFF, sum = 0
5868 20:15:18.443770 8, 0xFFFF, sum = 0
5869 20:15:18.446879 9, 0xFFFF, sum = 0
5870 20:15:18.446999 10, 0x0, sum = 1
5871 20:15:18.450234 11, 0x0, sum = 2
5872 20:15:18.450358 12, 0x0, sum = 3
5873 20:15:18.453424 13, 0x0, sum = 4
5874 20:15:18.453544 best_step = 11
5875 20:15:18.453652
5876 20:15:18.453760 ==
5877 20:15:18.457314 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 20:15:18.463251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 20:15:18.463410 ==
5880 20:15:18.463522 RX Vref Scan: 0
5881 20:15:18.463628
5882 20:15:18.467124 RX Vref 0 -> 0, step: 1
5883 20:15:18.467244
5884 20:15:18.469693 RX Delay -53 -> 252, step: 4
5885 20:15:18.473368 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5886 20:15:18.479542 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5887 20:15:18.483023 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5888 20:15:18.486319 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5889 20:15:18.489587 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5890 20:15:18.492744 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5891 20:15:18.499100 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5892 20:15:18.502706 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5893 20:15:18.505954 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5894 20:15:18.509096 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5895 20:15:18.512567 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5896 20:15:18.515930 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5897 20:15:18.522700 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5898 20:15:18.525965 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5899 20:15:18.529268 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5900 20:15:18.532508 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5901 20:15:18.532592 ==
5902 20:15:18.535670 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 20:15:18.542158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 20:15:18.542243 ==
5905 20:15:18.542329 DQS Delay:
5906 20:15:18.545535 DQS0 = 0, DQS1 = 0
5907 20:15:18.545623 DQM Delay:
5908 20:15:18.545709 DQM0 = 97, DQM1 = 92
5909 20:15:18.548853 DQ Delay:
5910 20:15:18.552309 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5911 20:15:18.555716 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =92
5912 20:15:18.558859 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5913 20:15:18.561926 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5914 20:15:18.562009
5915 20:15:18.562094
5916 20:15:18.568500 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5917 20:15:18.571958 CH1 RK1: MR19=505, MR18=E25
5918 20:15:18.579150 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
5919 20:15:18.581838 [RxdqsGatingPostProcess] freq 933
5920 20:15:18.585003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5921 20:15:18.588571 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 20:15:18.591648 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 20:15:18.594964 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 20:15:18.598576 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 20:15:18.601386 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 20:15:18.605281 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 20:15:18.608592 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 20:15:18.611435 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 20:15:18.614638 Pre-setting of DQS Precalculation
5930 20:15:18.621231 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5931 20:15:18.627773 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5932 20:15:18.634913 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5933 20:15:18.635022
5934 20:15:18.635123
5935 20:15:18.637708 [Calibration Summary] 1866 Mbps
5936 20:15:18.637808 CH 0, Rank 0
5937 20:15:18.641061 SW Impedance : PASS
5938 20:15:18.644317 DUTY Scan : NO K
5939 20:15:18.644401 ZQ Calibration : PASS
5940 20:15:18.647390 Jitter Meter : NO K
5941 20:15:18.651912 CBT Training : PASS
5942 20:15:18.651997 Write leveling : PASS
5943 20:15:18.654565 RX DQS gating : PASS
5944 20:15:18.657779 RX DQ/DQS(RDDQC) : PASS
5945 20:15:18.657863 TX DQ/DQS : PASS
5946 20:15:18.660746 RX DATLAT : PASS
5947 20:15:18.663831 RX DQ/DQS(Engine): PASS
5948 20:15:18.663916 TX OE : NO K
5949 20:15:18.664003 All Pass.
5950 20:15:18.667273
5951 20:15:18.667356 CH 0, Rank 1
5952 20:15:18.670499 SW Impedance : PASS
5953 20:15:18.670635 DUTY Scan : NO K
5954 20:15:18.674093 ZQ Calibration : PASS
5955 20:15:18.677376 Jitter Meter : NO K
5956 20:15:18.677496 CBT Training : PASS
5957 20:15:18.680408 Write leveling : PASS
5958 20:15:18.680532 RX DQS gating : PASS
5959 20:15:18.683738 RX DQ/DQS(RDDQC) : PASS
5960 20:15:18.686940 TX DQ/DQS : PASS
5961 20:15:18.687063 RX DATLAT : PASS
5962 20:15:18.690549 RX DQ/DQS(Engine): PASS
5963 20:15:18.693719 TX OE : NO K
5964 20:15:18.693840 All Pass.
5965 20:15:18.693963
5966 20:15:18.694078 CH 1, Rank 0
5967 20:15:18.697142 SW Impedance : PASS
5968 20:15:18.700068 DUTY Scan : NO K
5969 20:15:18.700191 ZQ Calibration : PASS
5970 20:15:18.703306 Jitter Meter : NO K
5971 20:15:18.706807 CBT Training : PASS
5972 20:15:18.706937 Write leveling : PASS
5973 20:15:18.710117 RX DQS gating : PASS
5974 20:15:18.713735 RX DQ/DQS(RDDQC) : PASS
5975 20:15:18.713816 TX DQ/DQS : PASS
5976 20:15:18.716814 RX DATLAT : PASS
5977 20:15:18.719923 RX DQ/DQS(Engine): PASS
5978 20:15:18.720004 TX OE : NO K
5979 20:15:18.723318 All Pass.
5980 20:15:18.723448
5981 20:15:18.723513 CH 1, Rank 1
5982 20:15:18.726740 SW Impedance : PASS
5983 20:15:18.726821 DUTY Scan : NO K
5984 20:15:18.729875 ZQ Calibration : PASS
5985 20:15:18.733056 Jitter Meter : NO K
5986 20:15:18.733137 CBT Training : PASS
5987 20:15:18.736273 Write leveling : PASS
5988 20:15:18.739689 RX DQS gating : PASS
5989 20:15:18.739770 RX DQ/DQS(RDDQC) : PASS
5990 20:15:18.743103 TX DQ/DQS : PASS
5991 20:15:18.746251 RX DATLAT : PASS
5992 20:15:18.746332 RX DQ/DQS(Engine): PASS
5993 20:15:18.749501 TX OE : NO K
5994 20:15:18.749582 All Pass.
5995 20:15:18.749646
5996 20:15:18.752812 DramC Write-DBI off
5997 20:15:18.755799 PER_BANK_REFRESH: Hybrid Mode
5998 20:15:18.755881 TX_TRACKING: ON
5999 20:15:18.765696 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6000 20:15:18.768930 [FAST_K] Save calibration result to emmc
6001 20:15:18.772179 dramc_set_vcore_voltage set vcore to 650000
6002 20:15:18.775634 Read voltage for 400, 6
6003 20:15:18.775715 Vio18 = 0
6004 20:15:18.775779 Vcore = 650000
6005 20:15:18.778884 Vdram = 0
6006 20:15:18.778965 Vddq = 0
6007 20:15:18.779029 Vmddr = 0
6008 20:15:18.785961 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6009 20:15:18.788584 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6010 20:15:18.792223 MEM_TYPE=3, freq_sel=20
6011 20:15:18.795143 sv_algorithm_assistance_LP4_800
6012 20:15:18.798771 ============ PULL DRAM RESETB DOWN ============
6013 20:15:18.804962 ========== PULL DRAM RESETB DOWN end =========
6014 20:15:18.808406 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6015 20:15:18.811743 ===================================
6016 20:15:18.815273 LPDDR4 DRAM CONFIGURATION
6017 20:15:18.818180 ===================================
6018 20:15:18.818265 EX_ROW_EN[0] = 0x0
6019 20:15:18.821522 EX_ROW_EN[1] = 0x0
6020 20:15:18.821645 LP4Y_EN = 0x0
6021 20:15:18.824885 WORK_FSP = 0x0
6022 20:15:18.825014 WL = 0x2
6023 20:15:18.828153 RL = 0x2
6024 20:15:18.831240 BL = 0x2
6025 20:15:18.831374 RPST = 0x0
6026 20:15:18.834803 RD_PRE = 0x0
6027 20:15:18.834928 WR_PRE = 0x1
6028 20:15:18.837917 WR_PST = 0x0
6029 20:15:18.838043 DBI_WR = 0x0
6030 20:15:18.841819 DBI_RD = 0x0
6031 20:15:18.841952 OTF = 0x1
6032 20:15:18.844231 ===================================
6033 20:15:18.847513 ===================================
6034 20:15:18.851048 ANA top config
6035 20:15:18.854422 ===================================
6036 20:15:18.854546 DLL_ASYNC_EN = 0
6037 20:15:18.857787 ALL_SLAVE_EN = 1
6038 20:15:18.860827 NEW_RANK_MODE = 1
6039 20:15:18.864128 DLL_IDLE_MODE = 1
6040 20:15:18.867509 LP45_APHY_COMB_EN = 1
6041 20:15:18.867630 TX_ODT_DIS = 1
6042 20:15:18.870947 NEW_8X_MODE = 1
6043 20:15:18.874487 ===================================
6044 20:15:18.878007 ===================================
6045 20:15:18.880627 data_rate = 800
6046 20:15:18.884076 CKR = 1
6047 20:15:18.887014 DQ_P2S_RATIO = 4
6048 20:15:18.890459 ===================================
6049 20:15:18.894405 CA_P2S_RATIO = 4
6050 20:15:18.894528 DQ_CA_OPEN = 0
6051 20:15:18.896919 DQ_SEMI_OPEN = 1
6052 20:15:18.900496 CA_SEMI_OPEN = 1
6053 20:15:18.903715 CA_FULL_RATE = 0
6054 20:15:18.907042 DQ_CKDIV4_EN = 0
6055 20:15:18.910815 CA_CKDIV4_EN = 1
6056 20:15:18.910970 CA_PREDIV_EN = 0
6057 20:15:18.913394 PH8_DLY = 0
6058 20:15:18.916926 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6059 20:15:18.920159 DQ_AAMCK_DIV = 0
6060 20:15:18.923172 CA_AAMCK_DIV = 0
6061 20:15:18.926853 CA_ADMCK_DIV = 4
6062 20:15:18.926932 DQ_TRACK_CA_EN = 0
6063 20:15:18.930230 CA_PICK = 800
6064 20:15:18.933036 CA_MCKIO = 400
6065 20:15:18.936313 MCKIO_SEMI = 400
6066 20:15:18.940357 PLL_FREQ = 3016
6067 20:15:18.942924 DQ_UI_PI_RATIO = 32
6068 20:15:18.946462 CA_UI_PI_RATIO = 32
6069 20:15:18.949534 ===================================
6070 20:15:18.953334 ===================================
6071 20:15:18.956319 memory_type:LPDDR4
6072 20:15:18.956403 GP_NUM : 10
6073 20:15:18.960016 SRAM_EN : 1
6074 20:15:18.960096 MD32_EN : 0
6075 20:15:18.963230 ===================================
6076 20:15:18.966125 [ANA_INIT] >>>>>>>>>>>>>>
6077 20:15:18.969537 <<<<<< [CONFIGURE PHASE]: ANA_TX
6078 20:15:18.972472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6079 20:15:18.976188 ===================================
6080 20:15:18.979055 data_rate = 800,PCW = 0X7400
6081 20:15:18.982770 ===================================
6082 20:15:18.985672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6083 20:15:18.992437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 20:15:19.002192 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6085 20:15:19.005409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6086 20:15:19.008842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6087 20:15:19.012408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6088 20:15:19.015785 [ANA_INIT] flow start
6089 20:15:19.018738 [ANA_INIT] PLL >>>>>>>>
6090 20:15:19.018818 [ANA_INIT] PLL <<<<<<<<
6091 20:15:19.022133 [ANA_INIT] MIDPI >>>>>>>>
6092 20:15:19.025549 [ANA_INIT] MIDPI <<<<<<<<
6093 20:15:19.028610 [ANA_INIT] DLL >>>>>>>>
6094 20:15:19.028721 [ANA_INIT] flow end
6095 20:15:19.031792 ============ LP4 DIFF to SE enter ============
6096 20:15:19.038716 ============ LP4 DIFF to SE exit ============
6097 20:15:19.038915 [ANA_INIT] <<<<<<<<<<<<<
6098 20:15:19.041713 [Flow] Enable top DCM control >>>>>
6099 20:15:19.044929 [Flow] Enable top DCM control <<<<<
6100 20:15:19.048402 Enable DLL master slave shuffle
6101 20:15:19.055238 ==============================================================
6102 20:15:19.058115 Gating Mode config
6103 20:15:19.061211 ==============================================================
6104 20:15:19.064730 Config description:
6105 20:15:19.075245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6106 20:15:19.081341 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6107 20:15:19.084533 SELPH_MODE 0: By rank 1: By Phase
6108 20:15:19.090820 ==============================================================
6109 20:15:19.094534 GAT_TRACK_EN = 0
6110 20:15:19.097544 RX_GATING_MODE = 2
6111 20:15:19.100912 RX_GATING_TRACK_MODE = 2
6112 20:15:19.104100 SELPH_MODE = 1
6113 20:15:19.104222 PICG_EARLY_EN = 1
6114 20:15:19.107461 VALID_LAT_VALUE = 1
6115 20:15:19.113765 ==============================================================
6116 20:15:19.117252 Enter into Gating configuration >>>>
6117 20:15:19.120559 Exit from Gating configuration <<<<
6118 20:15:19.123939 Enter into DVFS_PRE_config >>>>>
6119 20:15:19.133683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6120 20:15:19.137116 Exit from DVFS_PRE_config <<<<<
6121 20:15:19.140406 Enter into PICG configuration >>>>
6122 20:15:19.143542 Exit from PICG configuration <<<<
6123 20:15:19.146588 [RX_INPUT] configuration >>>>>
6124 20:15:19.149868 [RX_INPUT] configuration <<<<<
6125 20:15:19.156946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6126 20:15:19.159948 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6127 20:15:19.166469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6128 20:15:19.173638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6129 20:15:19.179880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 20:15:19.186609 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 20:15:19.189740 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6132 20:15:19.193213 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6133 20:15:19.196593 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6134 20:15:19.203013 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6135 20:15:19.206390 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6136 20:15:19.210226 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6137 20:15:19.213027 ===================================
6138 20:15:19.216934 LPDDR4 DRAM CONFIGURATION
6139 20:15:19.220195 ===================================
6140 20:15:19.220317 EX_ROW_EN[0] = 0x0
6141 20:15:19.222882 EX_ROW_EN[1] = 0x0
6142 20:15:19.226391 LP4Y_EN = 0x0
6143 20:15:19.226521 WORK_FSP = 0x0
6144 20:15:19.229500 WL = 0x2
6145 20:15:19.229636 RL = 0x2
6146 20:15:19.233364 BL = 0x2
6147 20:15:19.233491 RPST = 0x0
6148 20:15:19.236056 RD_PRE = 0x0
6149 20:15:19.236186 WR_PRE = 0x1
6150 20:15:19.239210 WR_PST = 0x0
6151 20:15:19.239330 DBI_WR = 0x0
6152 20:15:19.242822 DBI_RD = 0x0
6153 20:15:19.242944 OTF = 0x1
6154 20:15:19.246112 ===================================
6155 20:15:19.252179 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6156 20:15:19.255333 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6157 20:15:19.258786 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 20:15:19.261958 ===================================
6159 20:15:19.266073 LPDDR4 DRAM CONFIGURATION
6160 20:15:19.268869 ===================================
6161 20:15:19.272240 EX_ROW_EN[0] = 0x10
6162 20:15:19.272329 EX_ROW_EN[1] = 0x0
6163 20:15:19.275617 LP4Y_EN = 0x0
6164 20:15:19.275700 WORK_FSP = 0x0
6165 20:15:19.278404 WL = 0x2
6166 20:15:19.278477 RL = 0x2
6167 20:15:19.282245 BL = 0x2
6168 20:15:19.282325 RPST = 0x0
6169 20:15:19.285032 RD_PRE = 0x0
6170 20:15:19.285113 WR_PRE = 0x1
6171 20:15:19.288833 WR_PST = 0x0
6172 20:15:19.288914 DBI_WR = 0x0
6173 20:15:19.292105 DBI_RD = 0x0
6174 20:15:19.292177 OTF = 0x1
6175 20:15:19.294971 ===================================
6176 20:15:19.301909 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6177 20:15:19.306894 nWR fixed to 30
6178 20:15:19.310326 [ModeRegInit_LP4] CH0 RK0
6179 20:15:19.310400 [ModeRegInit_LP4] CH0 RK1
6180 20:15:19.313399 [ModeRegInit_LP4] CH1 RK0
6181 20:15:19.317022 [ModeRegInit_LP4] CH1 RK1
6182 20:15:19.317101 match AC timing 19
6183 20:15:19.322939 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6184 20:15:19.326373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6185 20:15:19.329592 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6186 20:15:19.336151 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6187 20:15:19.339928 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6188 20:15:19.340009 ==
6189 20:15:19.342714 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 20:15:19.346305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6191 20:15:19.346383 ==
6192 20:15:19.353495 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6193 20:15:19.359297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6194 20:15:19.363308 [CA 0] Center 36 (8~64) winsize 57
6195 20:15:19.366677 [CA 1] Center 36 (8~64) winsize 57
6196 20:15:19.369168 [CA 2] Center 36 (8~64) winsize 57
6197 20:15:19.372550 [CA 3] Center 36 (8~64) winsize 57
6198 20:15:19.375793 [CA 4] Center 36 (8~64) winsize 57
6199 20:15:19.379163 [CA 5] Center 36 (8~64) winsize 57
6200 20:15:19.379239
6201 20:15:19.382637 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6202 20:15:19.382718
6203 20:15:19.385967 [CATrainingPosCal] consider 1 rank data
6204 20:15:19.389080 u2DelayCellTimex100 = 270/100 ps
6205 20:15:19.392745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 20:15:19.395778 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 20:15:19.398890 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 20:15:19.402057 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 20:15:19.405241 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 20:15:19.408858 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 20:15:19.408982
6212 20:15:19.415034 CA PerBit enable=1, Macro0, CA PI delay=36
6213 20:15:19.415156
6214 20:15:19.415267 [CBTSetCACLKResult] CA Dly = 36
6215 20:15:19.418559 CS Dly: 1 (0~32)
6216 20:15:19.418683 ==
6217 20:15:19.422027 Dram Type= 6, Freq= 0, CH_0, rank 1
6218 20:15:19.425391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6219 20:15:19.425524 ==
6220 20:15:19.431686 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6221 20:15:19.438513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6222 20:15:19.442647 [CA 0] Center 36 (8~64) winsize 57
6223 20:15:19.444989 [CA 1] Center 36 (8~64) winsize 57
6224 20:15:19.448422 [CA 2] Center 36 (8~64) winsize 57
6225 20:15:19.451396 [CA 3] Center 36 (8~64) winsize 57
6226 20:15:19.455043 [CA 4] Center 36 (8~64) winsize 57
6227 20:15:19.455172 [CA 5] Center 36 (8~64) winsize 57
6228 20:15:19.455281
6229 20:15:19.461553 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6230 20:15:19.461676
6231 20:15:19.464559 [CATrainingPosCal] consider 2 rank data
6232 20:15:19.467890 u2DelayCellTimex100 = 270/100 ps
6233 20:15:19.471054 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 20:15:19.474586 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 20:15:19.477783 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 20:15:19.481518 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 20:15:19.484686 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 20:15:19.487845 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 20:15:19.487975
6240 20:15:19.491407 CA PerBit enable=1, Macro0, CA PI delay=36
6241 20:15:19.491539
6242 20:15:19.494325 [CBTSetCACLKResult] CA Dly = 36
6243 20:15:19.497487 CS Dly: 1 (0~32)
6244 20:15:19.497604
6245 20:15:19.501052 ----->DramcWriteLeveling(PI) begin...
6246 20:15:19.501171 ==
6247 20:15:19.504712 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 20:15:19.508440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 20:15:19.508566 ==
6250 20:15:19.511112 Write leveling (Byte 0): 40 => 8
6251 20:15:19.514229 Write leveling (Byte 1): 40 => 8
6252 20:15:19.517848 DramcWriteLeveling(PI) end<-----
6253 20:15:19.517928
6254 20:15:19.517991 ==
6255 20:15:19.520781 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 20:15:19.524188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 20:15:19.524269 ==
6258 20:15:19.527505 [Gating] SW mode calibration
6259 20:15:19.533856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6260 20:15:19.540881 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6261 20:15:19.543751 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 20:15:19.550476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 20:15:19.553454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 20:15:19.557002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 20:15:19.563500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 20:15:19.566527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 20:15:19.570210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 20:15:19.576616 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 20:15:19.579819 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 20:15:19.583029 Total UI for P1: 0, mck2ui 16
6271 20:15:19.586463 best dqsien dly found for B0: ( 0, 14, 24)
6272 20:15:19.589926 Total UI for P1: 0, mck2ui 16
6273 20:15:19.592768 best dqsien dly found for B1: ( 0, 14, 24)
6274 20:15:19.595995 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6275 20:15:19.600526 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6276 20:15:19.600647
6277 20:15:19.603087 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 20:15:19.609663 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6279 20:15:19.609794 [Gating] SW calibration Done
6280 20:15:19.609905 ==
6281 20:15:19.612985 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 20:15:19.619135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 20:15:19.619256 ==
6284 20:15:19.619375 RX Vref Scan: 0
6285 20:15:19.619509
6286 20:15:19.622711 RX Vref 0 -> 0, step: 1
6287 20:15:19.622829
6288 20:15:19.625753 RX Delay -410 -> 252, step: 16
6289 20:15:19.629239 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6290 20:15:19.632278 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6291 20:15:19.639281 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6292 20:15:19.642415 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6293 20:15:19.645510 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6294 20:15:19.648571 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6295 20:15:19.655331 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6296 20:15:19.658717 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6297 20:15:19.662089 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6298 20:15:19.669435 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6299 20:15:19.671838 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6300 20:15:19.674929 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6301 20:15:19.678260 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6302 20:15:19.684719 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6303 20:15:19.688339 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6304 20:15:19.691621 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6305 20:15:19.691745 ==
6306 20:15:19.694993 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 20:15:19.701626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 20:15:19.701750 ==
6309 20:15:19.701863 DQS Delay:
6310 20:15:19.704481 DQS0 = 35, DQS1 = 59
6311 20:15:19.704617 DQM Delay:
6312 20:15:19.704737 DQM0 = 4, DQM1 = 17
6313 20:15:19.709142 DQ Delay:
6314 20:15:19.711513 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6315 20:15:19.711634 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6316 20:15:19.714924 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6317 20:15:19.717730 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6318 20:15:19.717850
6319 20:15:19.721408
6320 20:15:19.721527 ==
6321 20:15:19.724309 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 20:15:19.727664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 20:15:19.727785 ==
6324 20:15:19.727893
6325 20:15:19.727997
6326 20:15:19.730960 TX Vref Scan disable
6327 20:15:19.731082 == TX Byte 0 ==
6328 20:15:19.734347 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 20:15:19.740710 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 20:15:19.740832 == TX Byte 1 ==
6331 20:15:19.744322 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 20:15:19.750803 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 20:15:19.750925 ==
6334 20:15:19.754077 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 20:15:19.757277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 20:15:19.757402 ==
6337 20:15:19.757528
6338 20:15:19.757638
6339 20:15:19.760430 TX Vref Scan disable
6340 20:15:19.760552 == TX Byte 0 ==
6341 20:15:19.767076 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 20:15:19.770508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 20:15:19.770630 == TX Byte 1 ==
6344 20:15:19.777007 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 20:15:19.780438 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 20:15:19.780572
6347 20:15:19.780690 [DATLAT]
6348 20:15:19.783460 Freq=400, CH0 RK0
6349 20:15:19.783581
6350 20:15:19.783692 DATLAT Default: 0xf
6351 20:15:19.786752 0, 0xFFFF, sum = 0
6352 20:15:19.786874 1, 0xFFFF, sum = 0
6353 20:15:19.790319 2, 0xFFFF, sum = 0
6354 20:15:19.790450 3, 0xFFFF, sum = 0
6355 20:15:19.793414 4, 0xFFFF, sum = 0
6356 20:15:19.793537 5, 0xFFFF, sum = 0
6357 20:15:19.797316 6, 0xFFFF, sum = 0
6358 20:15:19.797450 7, 0xFFFF, sum = 0
6359 20:15:19.800193 8, 0xFFFF, sum = 0
6360 20:15:19.800316 9, 0xFFFF, sum = 0
6361 20:15:19.803806 10, 0xFFFF, sum = 0
6362 20:15:19.807098 11, 0xFFFF, sum = 0
6363 20:15:19.807225 12, 0xFFFF, sum = 0
6364 20:15:19.810115 13, 0x0, sum = 1
6365 20:15:19.810240 14, 0x0, sum = 2
6366 20:15:19.810355 15, 0x0, sum = 3
6367 20:15:19.813586 16, 0x0, sum = 4
6368 20:15:19.813717 best_step = 14
6369 20:15:19.813827
6370 20:15:19.816577 ==
6371 20:15:19.819923 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 20:15:19.823252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 20:15:19.823381 ==
6374 20:15:19.823492 RX Vref Scan: 1
6375 20:15:19.823602
6376 20:15:19.826474 RX Vref 0 -> 0, step: 1
6377 20:15:19.826592
6378 20:15:19.829833 RX Delay -359 -> 252, step: 8
6379 20:15:19.829958
6380 20:15:19.832700 Set Vref, RX VrefLevel [Byte0]: 52
6381 20:15:19.836424 [Byte1]: 59
6382 20:15:19.840532
6383 20:15:19.840638 Final RX Vref Byte 0 = 52 to rank0
6384 20:15:19.843214 Final RX Vref Byte 1 = 59 to rank0
6385 20:15:19.846616 Final RX Vref Byte 0 = 52 to rank1
6386 20:15:19.850630 Final RX Vref Byte 1 = 59 to rank1==
6387 20:15:19.853521 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 20:15:19.859810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 20:15:19.859891 ==
6390 20:15:19.859956 DQS Delay:
6391 20:15:19.863789 DQS0 = 44, DQS1 = 60
6392 20:15:19.863871 DQM Delay:
6393 20:15:19.863935 DQM0 = 10, DQM1 = 17
6394 20:15:19.866173 DQ Delay:
6395 20:15:19.869903 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6396 20:15:19.873093 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6397 20:15:19.876030 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6398 20:15:19.879814 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6399 20:15:19.879893
6400 20:15:19.879955
6401 20:15:19.886261 [DQSOSCAuto] RK0, (LSB)MR18= 0x9588, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6402 20:15:19.889088 CH0 RK0: MR19=C0C, MR18=9588
6403 20:15:19.895670 CH0_RK0: MR19=0xC0C, MR18=0x9588, DQSOSC=391, MR23=63, INC=386, DEC=257
6404 20:15:19.895751 ==
6405 20:15:19.899505 Dram Type= 6, Freq= 0, CH_0, rank 1
6406 20:15:19.902541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 20:15:19.902622 ==
6408 20:15:19.905994 [Gating] SW mode calibration
6409 20:15:19.912301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6410 20:15:19.918890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6411 20:15:19.922595 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 20:15:19.928809 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6413 20:15:19.932259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 20:15:19.935898 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 20:15:19.938529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 20:15:19.945371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 20:15:19.948763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 20:15:19.952236 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 20:15:19.959300 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 20:15:19.961695 Total UI for P1: 0, mck2ui 16
6421 20:15:19.965491 best dqsien dly found for B0: ( 0, 14, 24)
6422 20:15:19.968694 Total UI for P1: 0, mck2ui 16
6423 20:15:19.971863 best dqsien dly found for B1: ( 0, 14, 24)
6424 20:15:19.974856 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6425 20:15:19.978264 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6426 20:15:19.978348
6427 20:15:19.981481 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 20:15:19.984991 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6429 20:15:19.988110 [Gating] SW calibration Done
6430 20:15:19.988206 ==
6431 20:15:19.991181 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 20:15:19.994849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 20:15:19.998014 ==
6434 20:15:19.998108 RX Vref Scan: 0
6435 20:15:19.998172
6436 20:15:20.001502 RX Vref 0 -> 0, step: 1
6437 20:15:20.001585
6438 20:15:20.004552 RX Delay -410 -> 252, step: 16
6439 20:15:20.007890 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6440 20:15:20.011200 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6441 20:15:20.014246 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6442 20:15:20.021152 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6443 20:15:20.024214 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6444 20:15:20.027349 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6445 20:15:20.031048 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6446 20:15:20.037417 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6447 20:15:20.040990 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6448 20:15:20.044107 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6449 20:15:20.051194 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6450 20:15:20.054198 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6451 20:15:20.057392 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6452 20:15:20.060821 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6453 20:15:20.067244 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6454 20:15:20.070544 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6455 20:15:20.070629 ==
6456 20:15:20.073555 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 20:15:20.077104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 20:15:20.077190 ==
6459 20:15:20.080153 DQS Delay:
6460 20:15:20.080246 DQS0 = 35, DQS1 = 51
6461 20:15:20.084421 DQM Delay:
6462 20:15:20.084506 DQM0 = 6, DQM1 = 9
6463 20:15:20.084610 DQ Delay:
6464 20:15:20.086963 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6465 20:15:20.090965 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6466 20:15:20.093424 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6467 20:15:20.096706 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6468 20:15:20.096790
6469 20:15:20.096892
6470 20:15:20.096991 ==
6471 20:15:20.100371 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 20:15:20.103166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 20:15:20.106362 ==
6474 20:15:20.106445
6475 20:15:20.106530
6476 20:15:20.106611 TX Vref Scan disable
6477 20:15:20.109793 == TX Byte 0 ==
6478 20:15:20.113151 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6479 20:15:20.116371 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6480 20:15:20.119924 == TX Byte 1 ==
6481 20:15:20.123089 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6482 20:15:20.126431 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6483 20:15:20.126515 ==
6484 20:15:20.129873 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 20:15:20.136605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 20:15:20.136690 ==
6487 20:15:20.136776
6488 20:15:20.136856
6489 20:15:20.136934 TX Vref Scan disable
6490 20:15:20.139762 == TX Byte 0 ==
6491 20:15:20.142815 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6492 20:15:20.146107 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6493 20:15:20.149458 == TX Byte 1 ==
6494 20:15:20.153494 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6495 20:15:20.156189 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6496 20:15:20.156297
6497 20:15:20.159287 [DATLAT]
6498 20:15:20.159432 Freq=400, CH0 RK1
6499 20:15:20.159500
6500 20:15:20.162388 DATLAT Default: 0xe
6501 20:15:20.162469 0, 0xFFFF, sum = 0
6502 20:15:20.165903 1, 0xFFFF, sum = 0
6503 20:15:20.165986 2, 0xFFFF, sum = 0
6504 20:15:20.169106 3, 0xFFFF, sum = 0
6505 20:15:20.169189 4, 0xFFFF, sum = 0
6506 20:15:20.172388 5, 0xFFFF, sum = 0
6507 20:15:20.172471 6, 0xFFFF, sum = 0
6508 20:15:20.175965 7, 0xFFFF, sum = 0
6509 20:15:20.176048 8, 0xFFFF, sum = 0
6510 20:15:20.179240 9, 0xFFFF, sum = 0
6511 20:15:20.182143 10, 0xFFFF, sum = 0
6512 20:15:20.182226 11, 0xFFFF, sum = 0
6513 20:15:20.185569 12, 0xFFFF, sum = 0
6514 20:15:20.185652 13, 0x0, sum = 1
6515 20:15:20.189029 14, 0x0, sum = 2
6516 20:15:20.189111 15, 0x0, sum = 3
6517 20:15:20.191950 16, 0x0, sum = 4
6518 20:15:20.192062 best_step = 14
6519 20:15:20.192127
6520 20:15:20.192187 ==
6521 20:15:20.196199 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 20:15:20.198462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 20:15:20.198544 ==
6524 20:15:20.201719 RX Vref Scan: 0
6525 20:15:20.201801
6526 20:15:20.205462 RX Vref 0 -> 0, step: 1
6527 20:15:20.205547
6528 20:15:20.205612 RX Delay -343 -> 252, step: 8
6529 20:15:20.214535 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6530 20:15:20.217209 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6531 20:15:20.221079 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6532 20:15:20.227713 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6533 20:15:20.230965 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6534 20:15:20.233790 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6535 20:15:20.237093 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6536 20:15:20.240595 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6537 20:15:20.247248 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6538 20:15:20.250748 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6539 20:15:20.253596 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6540 20:15:20.260393 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6541 20:15:20.263562 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6542 20:15:20.267033 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6543 20:15:20.270318 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6544 20:15:20.276848 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6545 20:15:20.276930 ==
6546 20:15:20.279852 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 20:15:20.283284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 20:15:20.283433 ==
6549 20:15:20.283522 DQS Delay:
6550 20:15:20.287113 DQS0 = 44, DQS1 = 60
6551 20:15:20.287213 DQM Delay:
6552 20:15:20.290022 DQM0 = 9, DQM1 = 16
6553 20:15:20.290121 DQ Delay:
6554 20:15:20.293491 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6555 20:15:20.296511 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6556 20:15:20.299557 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6557 20:15:20.302888 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6558 20:15:20.302972
6559 20:15:20.303073
6560 20:15:20.312792 [DQSOSCAuto] RK1, (LSB)MR18= 0x8b82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6561 20:15:20.312878 CH0 RK1: MR19=C0C, MR18=8B82
6562 20:15:20.319432 CH0_RK1: MR19=0xC0C, MR18=0x8B82, DQSOSC=392, MR23=63, INC=384, DEC=256
6563 20:15:20.322949 [RxdqsGatingPostProcess] freq 400
6564 20:15:20.329381 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6565 20:15:20.332990 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 20:15:20.335855 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 20:15:20.339272 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 20:15:20.342251 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 20:15:20.345883 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 20:15:20.345968 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 20:15:20.349376 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 20:15:20.352638 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 20:15:20.355575 Pre-setting of DQS Precalculation
6574 20:15:20.363064 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6575 20:15:20.363171 ==
6576 20:15:20.365918 Dram Type= 6, Freq= 0, CH_1, rank 0
6577 20:15:20.368750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 20:15:20.368830 ==
6579 20:15:20.375883 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6580 20:15:20.382355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6581 20:15:20.385318 [CA 0] Center 36 (8~64) winsize 57
6582 20:15:20.388983 [CA 1] Center 36 (8~64) winsize 57
6583 20:15:20.391840 [CA 2] Center 36 (8~64) winsize 57
6584 20:15:20.395128 [CA 3] Center 36 (8~64) winsize 57
6585 20:15:20.395215 [CA 4] Center 36 (8~64) winsize 57
6586 20:15:20.398567 [CA 5] Center 36 (8~64) winsize 57
6587 20:15:20.398648
6588 20:15:20.405375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6589 20:15:20.405465
6590 20:15:20.408544 [CATrainingPosCal] consider 1 rank data
6591 20:15:20.411946 u2DelayCellTimex100 = 270/100 ps
6592 20:15:20.415097 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 20:15:20.418152 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 20:15:20.421644 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 20:15:20.425022 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 20:15:20.427949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 20:15:20.431384 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 20:15:20.431478
6599 20:15:20.434755 CA PerBit enable=1, Macro0, CA PI delay=36
6600 20:15:20.434835
6601 20:15:20.438009 [CBTSetCACLKResult] CA Dly = 36
6602 20:15:20.441338 CS Dly: 1 (0~32)
6603 20:15:20.441418 ==
6604 20:15:20.444472 Dram Type= 6, Freq= 0, CH_1, rank 1
6605 20:15:20.447843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 20:15:20.447923 ==
6607 20:15:20.454483 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6608 20:15:20.460754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6609 20:15:20.463969 [CA 0] Center 36 (8~64) winsize 57
6610 20:15:20.467328 [CA 1] Center 36 (8~64) winsize 57
6611 20:15:20.470751 [CA 2] Center 36 (8~64) winsize 57
6612 20:15:20.474251 [CA 3] Center 36 (8~64) winsize 57
6613 20:15:20.474331 [CA 4] Center 36 (8~64) winsize 57
6614 20:15:20.477357 [CA 5] Center 36 (8~64) winsize 57
6615 20:15:20.477436
6616 20:15:20.484176 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6617 20:15:20.484282
6618 20:15:20.487233 [CATrainingPosCal] consider 2 rank data
6619 20:15:20.490516 u2DelayCellTimex100 = 270/100 ps
6620 20:15:20.493833 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 20:15:20.497292 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 20:15:20.500605 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 20:15:20.503594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 20:15:20.506888 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 20:15:20.510201 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 20:15:20.510281
6627 20:15:20.513527 CA PerBit enable=1, Macro0, CA PI delay=36
6628 20:15:20.513607
6629 20:15:20.517398 [CBTSetCACLKResult] CA Dly = 36
6630 20:15:20.521373 CS Dly: 1 (0~32)
6631 20:15:20.521453
6632 20:15:20.523566 ----->DramcWriteLeveling(PI) begin...
6633 20:15:20.523650 ==
6634 20:15:20.526671 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 20:15:20.530583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 20:15:20.530664 ==
6637 20:15:20.534761 Write leveling (Byte 0): 40 => 8
6638 20:15:20.536443 Write leveling (Byte 1): 40 => 8
6639 20:15:20.539704 DramcWriteLeveling(PI) end<-----
6640 20:15:20.539784
6641 20:15:20.539848 ==
6642 20:15:20.543225 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 20:15:20.546393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 20:15:20.546504 ==
6645 20:15:20.549706 [Gating] SW mode calibration
6646 20:15:20.556315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6647 20:15:20.563189 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6648 20:15:20.566626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 20:15:20.573151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 20:15:20.576129 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 20:15:20.579680 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 20:15:20.586471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 20:15:20.589163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 20:15:20.592738 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 20:15:20.599596 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 20:15:20.602651 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 20:15:20.605500 Total UI for P1: 0, mck2ui 16
6658 20:15:20.608692 best dqsien dly found for B0: ( 0, 14, 24)
6659 20:15:20.612173 Total UI for P1: 0, mck2ui 16
6660 20:15:20.615602 best dqsien dly found for B1: ( 0, 14, 24)
6661 20:15:20.618846 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6662 20:15:20.622092 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6663 20:15:20.622172
6664 20:15:20.625318 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 20:15:20.628681 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6666 20:15:20.632232 [Gating] SW calibration Done
6667 20:15:20.632338 ==
6668 20:15:20.635960 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 20:15:20.641816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 20:15:20.641896 ==
6671 20:15:20.641960 RX Vref Scan: 0
6672 20:15:20.642020
6673 20:15:20.645232 RX Vref 0 -> 0, step: 1
6674 20:15:20.645312
6675 20:15:20.648727 RX Delay -410 -> 252, step: 16
6676 20:15:20.651921 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6677 20:15:20.655064 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6678 20:15:20.661463 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6679 20:15:20.665955 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6680 20:15:20.667994 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6681 20:15:20.671200 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6682 20:15:20.678572 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6683 20:15:20.681079 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6684 20:15:20.684716 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6685 20:15:20.688045 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6686 20:15:20.694547 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6687 20:15:20.697919 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6688 20:15:20.700963 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6689 20:15:20.707321 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6690 20:15:20.710752 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6691 20:15:20.714235 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6692 20:15:20.714316 ==
6693 20:15:20.717690 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 20:15:20.720648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 20:15:20.723789 ==
6696 20:15:20.723869 DQS Delay:
6697 20:15:20.723933 DQS0 = 35, DQS1 = 51
6698 20:15:20.727546 DQM Delay:
6699 20:15:20.727625 DQM0 = 6, DQM1 = 13
6700 20:15:20.731000 DQ Delay:
6701 20:15:20.733671 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6702 20:15:20.733751 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6703 20:15:20.736929 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6704 20:15:20.740361 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6705 20:15:20.740443
6706 20:15:20.740507
6707 20:15:20.743649 ==
6708 20:15:20.747280 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 20:15:20.750059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 20:15:20.750140 ==
6711 20:15:20.750204
6712 20:15:20.750264
6713 20:15:20.753264 TX Vref Scan disable
6714 20:15:20.753345 == TX Byte 0 ==
6715 20:15:20.756913 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 20:15:20.763091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 20:15:20.763177 == TX Byte 1 ==
6718 20:15:20.766494 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 20:15:20.773015 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 20:15:20.773096 ==
6721 20:15:20.777133 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 20:15:20.780055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 20:15:20.780139 ==
6724 20:15:20.780203
6725 20:15:20.780262
6726 20:15:20.782739 TX Vref Scan disable
6727 20:15:20.782807 == TX Byte 0 ==
6728 20:15:20.789596 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 20:15:20.793534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 20:15:20.793615 == TX Byte 1 ==
6731 20:15:20.796247 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 20:15:20.803347 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 20:15:20.803472
6734 20:15:20.803536 [DATLAT]
6735 20:15:20.806097 Freq=400, CH1 RK0
6736 20:15:20.806172
6737 20:15:20.806233 DATLAT Default: 0xf
6738 20:15:20.810509 0, 0xFFFF, sum = 0
6739 20:15:20.810590 1, 0xFFFF, sum = 0
6740 20:15:20.813300 2, 0xFFFF, sum = 0
6741 20:15:20.813398 3, 0xFFFF, sum = 0
6742 20:15:20.815988 4, 0xFFFF, sum = 0
6743 20:15:20.816071 5, 0xFFFF, sum = 0
6744 20:15:20.818947 6, 0xFFFF, sum = 0
6745 20:15:20.819023 7, 0xFFFF, sum = 0
6746 20:15:20.822924 8, 0xFFFF, sum = 0
6747 20:15:20.823034 9, 0xFFFF, sum = 0
6748 20:15:20.825745 10, 0xFFFF, sum = 0
6749 20:15:20.829135 11, 0xFFFF, sum = 0
6750 20:15:20.829219 12, 0xFFFF, sum = 0
6751 20:15:20.832598 13, 0x0, sum = 1
6752 20:15:20.832681 14, 0x0, sum = 2
6753 20:15:20.832752 15, 0x0, sum = 3
6754 20:15:20.836003 16, 0x0, sum = 4
6755 20:15:20.836085 best_step = 14
6756 20:15:20.836149
6757 20:15:20.839475 ==
6758 20:15:20.839556 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 20:15:20.845400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 20:15:20.845484 ==
6761 20:15:20.845552 RX Vref Scan: 1
6762 20:15:20.845612
6763 20:15:20.849137 RX Vref 0 -> 0, step: 1
6764 20:15:20.849218
6765 20:15:20.852029 RX Delay -343 -> 252, step: 8
6766 20:15:20.852110
6767 20:15:20.855328 Set Vref, RX VrefLevel [Byte0]: 52
6768 20:15:20.858530 [Byte1]: 51
6769 20:15:20.862594
6770 20:15:20.862679 Final RX Vref Byte 0 = 52 to rank0
6771 20:15:20.865662 Final RX Vref Byte 1 = 51 to rank0
6772 20:15:20.869381 Final RX Vref Byte 0 = 52 to rank1
6773 20:15:20.872451 Final RX Vref Byte 1 = 51 to rank1==
6774 20:15:20.876299 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 20:15:20.882205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 20:15:20.882286 ==
6777 20:15:20.882351 DQS Delay:
6778 20:15:20.885304 DQS0 = 44, DQS1 = 52
6779 20:15:20.885386 DQM Delay:
6780 20:15:20.885450 DQM0 = 11, DQM1 = 10
6781 20:15:20.889461 DQ Delay:
6782 20:15:20.892133 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6783 20:15:20.894881 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6784 20:15:20.894965 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6785 20:15:20.901623 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6786 20:15:20.901708
6787 20:15:20.901793
6788 20:15:20.908370 [DQSOSCAuto] RK0, (LSB)MR18= 0x678e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6789 20:15:20.911503 CH1 RK0: MR19=C0C, MR18=678E
6790 20:15:20.918092 CH1_RK0: MR19=0xC0C, MR18=0x678E, DQSOSC=392, MR23=63, INC=384, DEC=256
6791 20:15:20.918182 ==
6792 20:15:20.921507 Dram Type= 6, Freq= 0, CH_1, rank 1
6793 20:15:20.924395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 20:15:20.924480 ==
6795 20:15:20.927954 [Gating] SW mode calibration
6796 20:15:20.934917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6797 20:15:20.940806 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6798 20:15:20.944130 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 20:15:20.947375 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6800 20:15:20.954174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 20:15:20.957388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 20:15:20.960870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 20:15:20.967342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 20:15:20.970311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 20:15:20.976925 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 20:15:20.980543 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 20:15:20.983574 Total UI for P1: 0, mck2ui 16
6808 20:15:20.987131 best dqsien dly found for B0: ( 0, 14, 24)
6809 20:15:20.990179 Total UI for P1: 0, mck2ui 16
6810 20:15:20.993758 best dqsien dly found for B1: ( 0, 14, 24)
6811 20:15:20.996823 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6812 20:15:20.999894 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6813 20:15:20.999976
6814 20:15:21.003480 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 20:15:21.006875 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6816 20:15:21.010527 [Gating] SW calibration Done
6817 20:15:21.010608 ==
6818 20:15:21.013365 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 20:15:21.016426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 20:15:21.020467 ==
6821 20:15:21.020548 RX Vref Scan: 0
6822 20:15:21.020652
6823 20:15:21.023136 RX Vref 0 -> 0, step: 1
6824 20:15:21.023217
6825 20:15:21.026468 RX Delay -410 -> 252, step: 16
6826 20:15:21.029703 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6827 20:15:21.033571 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6828 20:15:21.036179 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6829 20:15:21.043239 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6830 20:15:21.046441 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6831 20:15:21.049431 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6832 20:15:21.053010 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6833 20:15:21.059245 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6834 20:15:21.062897 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6835 20:15:21.065820 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6836 20:15:21.072304 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6837 20:15:21.075584 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6838 20:15:21.079168 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6839 20:15:21.082821 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6840 20:15:21.088723 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6841 20:15:21.092063 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6842 20:15:21.092158 ==
6843 20:15:21.096835 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 20:15:21.098825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 20:15:21.098905 ==
6846 20:15:21.102304 DQS Delay:
6847 20:15:21.102397 DQS0 = 43, DQS1 = 51
6848 20:15:21.105412 DQM Delay:
6849 20:15:21.105492 DQM0 = 10, DQM1 = 14
6850 20:15:21.105555 DQ Delay:
6851 20:15:21.108781 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6852 20:15:21.111887 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6853 20:15:21.115240 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6854 20:15:21.118380 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6855 20:15:21.118460
6856 20:15:21.118524
6857 20:15:21.118582 ==
6858 20:15:21.121750 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 20:15:21.128406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 20:15:21.128489 ==
6861 20:15:21.128554
6862 20:15:21.128612
6863 20:15:21.128669 TX Vref Scan disable
6864 20:15:21.131524 == TX Byte 0 ==
6865 20:15:21.134973 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6866 20:15:21.138182 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6867 20:15:21.141335 == TX Byte 1 ==
6868 20:15:21.144786 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6869 20:15:21.148342 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6870 20:15:21.151387 ==
6871 20:15:21.155062 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 20:15:21.157737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 20:15:21.157819 ==
6874 20:15:21.157883
6875 20:15:21.157942
6876 20:15:21.161465 TX Vref Scan disable
6877 20:15:21.161547 == TX Byte 0 ==
6878 20:15:21.164449 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6879 20:15:21.171257 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6880 20:15:21.171341 == TX Byte 1 ==
6881 20:15:21.174168 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6882 20:15:21.180938 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6883 20:15:21.181064
6884 20:15:21.181167 [DATLAT]
6885 20:15:21.181283 Freq=400, CH1 RK1
6886 20:15:21.181409
6887 20:15:21.184203 DATLAT Default: 0xe
6888 20:15:21.187526 0, 0xFFFF, sum = 0
6889 20:15:21.187608 1, 0xFFFF, sum = 0
6890 20:15:21.190897 2, 0xFFFF, sum = 0
6891 20:15:21.190978 3, 0xFFFF, sum = 0
6892 20:15:21.194423 4, 0xFFFF, sum = 0
6893 20:15:21.194505 5, 0xFFFF, sum = 0
6894 20:15:21.197503 6, 0xFFFF, sum = 0
6895 20:15:21.197602 7, 0xFFFF, sum = 0
6896 20:15:21.200563 8, 0xFFFF, sum = 0
6897 20:15:21.200647 9, 0xFFFF, sum = 0
6898 20:15:21.204360 10, 0xFFFF, sum = 0
6899 20:15:21.204443 11, 0xFFFF, sum = 0
6900 20:15:21.207341 12, 0xFFFF, sum = 0
6901 20:15:21.207433 13, 0x0, sum = 1
6902 20:15:21.210726 14, 0x0, sum = 2
6903 20:15:21.210836 15, 0x0, sum = 3
6904 20:15:21.213945 16, 0x0, sum = 4
6905 20:15:21.214028 best_step = 14
6906 20:15:21.214094
6907 20:15:21.214155 ==
6908 20:15:21.217287 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 20:15:21.223309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 20:15:21.223418 ==
6911 20:15:21.223491 RX Vref Scan: 0
6912 20:15:21.223555
6913 20:15:21.226712 RX Vref 0 -> 0, step: 1
6914 20:15:21.226821
6915 20:15:21.230238 RX Delay -343 -> 252, step: 8
6916 20:15:21.237266 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6917 20:15:21.240021 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6918 20:15:21.243229 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6919 20:15:21.247256 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6920 20:15:21.253175 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6921 20:15:21.256675 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6922 20:15:21.260318 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6923 20:15:21.263499 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6924 20:15:21.269734 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6925 20:15:21.273512 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6926 20:15:21.276298 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6927 20:15:21.283083 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6928 20:15:21.286000 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6929 20:15:21.289773 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6930 20:15:21.292661 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6931 20:15:21.299249 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6932 20:15:21.299330 ==
6933 20:15:21.302706 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 20:15:21.305709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 20:15:21.305791 ==
6936 20:15:21.305857 DQS Delay:
6937 20:15:21.309107 DQS0 = 48, DQS1 = 52
6938 20:15:21.309188 DQM Delay:
6939 20:15:21.312480 DQM0 = 11, DQM1 = 10
6940 20:15:21.312597 DQ Delay:
6941 20:15:21.315642 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6942 20:15:21.318940 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6943 20:15:21.322062 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6944 20:15:21.325603 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6945 20:15:21.325684
6946 20:15:21.325748
6947 20:15:21.335919 [DQSOSCAuto] RK1, (LSB)MR18= 0x72a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6948 20:15:21.336002 CH1 RK1: MR19=C0C, MR18=72A9
6949 20:15:21.342017 CH1_RK1: MR19=0xC0C, MR18=0x72A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6950 20:15:21.345235 [RxdqsGatingPostProcess] freq 400
6951 20:15:21.351815 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6952 20:15:21.355121 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 20:15:21.358467 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 20:15:21.361717 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 20:15:21.365119 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 20:15:21.368236 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 20:15:21.371525 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 20:15:21.374976 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 20:15:21.378030 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 20:15:21.378110 Pre-setting of DQS Precalculation
6961 20:15:21.384487 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6962 20:15:21.390978 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6963 20:15:21.397647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6964 20:15:21.397729
6965 20:15:21.397792
6966 20:15:21.400994 [Calibration Summary] 800 Mbps
6967 20:15:21.404396 CH 0, Rank 0
6968 20:15:21.404483 SW Impedance : PASS
6969 20:15:21.407682 DUTY Scan : NO K
6970 20:15:21.410746 ZQ Calibration : PASS
6971 20:15:21.410827 Jitter Meter : NO K
6972 20:15:21.413968 CBT Training : PASS
6973 20:15:21.417542 Write leveling : PASS
6974 20:15:21.417623 RX DQS gating : PASS
6975 20:15:21.420940 RX DQ/DQS(RDDQC) : PASS
6976 20:15:21.424020 TX DQ/DQS : PASS
6977 20:15:21.424101 RX DATLAT : PASS
6978 20:15:21.427717 RX DQ/DQS(Engine): PASS
6979 20:15:21.430767 TX OE : NO K
6980 20:15:21.430847 All Pass.
6981 20:15:21.430911
6982 20:15:21.430970 CH 0, Rank 1
6983 20:15:21.433917 SW Impedance : PASS
6984 20:15:21.437072 DUTY Scan : NO K
6985 20:15:21.437152 ZQ Calibration : PASS
6986 20:15:21.440855 Jitter Meter : NO K
6987 20:15:21.440935 CBT Training : PASS
6988 20:15:21.443756 Write leveling : NO K
6989 20:15:21.447075 RX DQS gating : PASS
6990 20:15:21.447155 RX DQ/DQS(RDDQC) : PASS
6991 20:15:21.450700 TX DQ/DQS : PASS
6992 20:15:21.454057 RX DATLAT : PASS
6993 20:15:21.454138 RX DQ/DQS(Engine): PASS
6994 20:15:21.456880 TX OE : NO K
6995 20:15:21.456964 All Pass.
6996 20:15:21.457029
6997 20:15:21.460184 CH 1, Rank 0
6998 20:15:21.460264 SW Impedance : PASS
6999 20:15:21.464241 DUTY Scan : NO K
7000 20:15:21.467230 ZQ Calibration : PASS
7001 20:15:21.467353 Jitter Meter : NO K
7002 20:15:21.470507 CBT Training : PASS
7003 20:15:21.473532 Write leveling : PASS
7004 20:15:21.473612 RX DQS gating : PASS
7005 20:15:21.476887 RX DQ/DQS(RDDQC) : PASS
7006 20:15:21.480513 TX DQ/DQS : PASS
7007 20:15:21.480594 RX DATLAT : PASS
7008 20:15:21.483210 RX DQ/DQS(Engine): PASS
7009 20:15:21.486534 TX OE : NO K
7010 20:15:21.486615 All Pass.
7011 20:15:21.486679
7012 20:15:21.486738 CH 1, Rank 1
7013 20:15:21.489970 SW Impedance : PASS
7014 20:15:21.493302 DUTY Scan : NO K
7015 20:15:21.493382 ZQ Calibration : PASS
7016 20:15:21.496660 Jitter Meter : NO K
7017 20:15:21.499860 CBT Training : PASS
7018 20:15:21.499940 Write leveling : NO K
7019 20:15:21.503254 RX DQS gating : PASS
7020 20:15:21.506486 RX DQ/DQS(RDDQC) : PASS
7021 20:15:21.506569 TX DQ/DQS : PASS
7022 20:15:21.509515 RX DATLAT : PASS
7023 20:15:21.513021 RX DQ/DQS(Engine): PASS
7024 20:15:21.513101 TX OE : NO K
7025 20:15:21.516324 All Pass.
7026 20:15:21.516405
7027 20:15:21.516469 DramC Write-DBI off
7028 20:15:21.519889 PER_BANK_REFRESH: Hybrid Mode
7029 20:15:21.520028 TX_TRACKING: ON
7030 20:15:21.529476 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7031 20:15:21.532593 [FAST_K] Save calibration result to emmc
7032 20:15:21.535795 dramc_set_vcore_voltage set vcore to 725000
7033 20:15:21.539289 Read voltage for 1600, 0
7034 20:15:21.539435 Vio18 = 0
7035 20:15:21.542513 Vcore = 725000
7036 20:15:21.542592 Vdram = 0
7037 20:15:21.542657 Vddq = 0
7038 20:15:21.546387 Vmddr = 0
7039 20:15:21.548955 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7040 20:15:21.555506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7041 20:15:21.555586 MEM_TYPE=3, freq_sel=13
7042 20:15:21.559109 sv_algorithm_assistance_LP4_3733
7043 20:15:21.566158 ============ PULL DRAM RESETB DOWN ============
7044 20:15:21.568900 ========== PULL DRAM RESETB DOWN end =========
7045 20:15:21.572550 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7046 20:15:21.575411 ===================================
7047 20:15:21.578706 LPDDR4 DRAM CONFIGURATION
7048 20:15:21.582114 ===================================
7049 20:15:21.585145 EX_ROW_EN[0] = 0x0
7050 20:15:21.585226 EX_ROW_EN[1] = 0x0
7051 20:15:21.588256 LP4Y_EN = 0x0
7052 20:15:21.588336 WORK_FSP = 0x1
7053 20:15:21.591606 WL = 0x5
7054 20:15:21.591691 RL = 0x5
7055 20:15:21.594980 BL = 0x2
7056 20:15:21.595060 RPST = 0x0
7057 20:15:21.598417 RD_PRE = 0x0
7058 20:15:21.598497 WR_PRE = 0x1
7059 20:15:21.602412 WR_PST = 0x1
7060 20:15:21.602493 DBI_WR = 0x0
7061 20:15:21.605082 DBI_RD = 0x0
7062 20:15:21.605162 OTF = 0x1
7063 20:15:21.608458 ===================================
7064 20:15:21.611494 ===================================
7065 20:15:21.614821 ANA top config
7066 20:15:21.617984 ===================================
7067 20:15:21.621266 DLL_ASYNC_EN = 0
7068 20:15:21.621347 ALL_SLAVE_EN = 0
7069 20:15:21.625725 NEW_RANK_MODE = 1
7070 20:15:21.627726 DLL_IDLE_MODE = 1
7071 20:15:21.631016 LP45_APHY_COMB_EN = 1
7072 20:15:21.634899 TX_ODT_DIS = 0
7073 20:15:21.634980 NEW_8X_MODE = 1
7074 20:15:21.637961 ===================================
7075 20:15:21.641130 ===================================
7076 20:15:21.644382 data_rate = 3200
7077 20:15:21.647601 CKR = 1
7078 20:15:21.651072 DQ_P2S_RATIO = 8
7079 20:15:21.654809 ===================================
7080 20:15:21.657664 CA_P2S_RATIO = 8
7081 20:15:21.661334 DQ_CA_OPEN = 0
7082 20:15:21.661415 DQ_SEMI_OPEN = 0
7083 20:15:21.663917 CA_SEMI_OPEN = 0
7084 20:15:21.667519 CA_FULL_RATE = 0
7085 20:15:21.670672 DQ_CKDIV4_EN = 0
7086 20:15:21.674072 CA_CKDIV4_EN = 0
7087 20:15:21.677536 CA_PREDIV_EN = 0
7088 20:15:21.680417 PH8_DLY = 12
7089 20:15:21.680498 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7090 20:15:21.684506 DQ_AAMCK_DIV = 4
7091 20:15:21.687166 CA_AAMCK_DIV = 4
7092 20:15:21.690985 CA_ADMCK_DIV = 4
7093 20:15:21.694059 DQ_TRACK_CA_EN = 0
7094 20:15:21.697243 CA_PICK = 1600
7095 20:15:21.700250 CA_MCKIO = 1600
7096 20:15:21.700330 MCKIO_SEMI = 0
7097 20:15:21.703779 PLL_FREQ = 3068
7098 20:15:21.706775 DQ_UI_PI_RATIO = 32
7099 20:15:21.710313 CA_UI_PI_RATIO = 0
7100 20:15:21.713815 ===================================
7101 20:15:21.716773 ===================================
7102 20:15:21.720030 memory_type:LPDDR4
7103 20:15:21.720110 GP_NUM : 10
7104 20:15:21.723572 SRAM_EN : 1
7105 20:15:21.726389 MD32_EN : 0
7106 20:15:21.729946 ===================================
7107 20:15:21.730026 [ANA_INIT] >>>>>>>>>>>>>>
7108 20:15:21.733150 <<<<<< [CONFIGURE PHASE]: ANA_TX
7109 20:15:21.736515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7110 20:15:21.739639 ===================================
7111 20:15:21.743499 data_rate = 3200,PCW = 0X7600
7112 20:15:21.746663 ===================================
7113 20:15:21.749664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7114 20:15:21.756334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 20:15:21.759313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7116 20:15:21.766034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7117 20:15:21.769365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7118 20:15:21.772712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7119 20:15:21.776064 [ANA_INIT] flow start
7120 20:15:21.776146 [ANA_INIT] PLL >>>>>>>>
7121 20:15:21.779350 [ANA_INIT] PLL <<<<<<<<
7122 20:15:21.782575 [ANA_INIT] MIDPI >>>>>>>>
7123 20:15:21.782656 [ANA_INIT] MIDPI <<<<<<<<
7124 20:15:21.785858 [ANA_INIT] DLL >>>>>>>>
7125 20:15:21.788968 [ANA_INIT] DLL <<<<<<<<
7126 20:15:21.789048 [ANA_INIT] flow end
7127 20:15:21.795609 ============ LP4 DIFF to SE enter ============
7128 20:15:21.799130 ============ LP4 DIFF to SE exit ============
7129 20:15:21.802426 [ANA_INIT] <<<<<<<<<<<<<
7130 20:15:21.805458 [Flow] Enable top DCM control >>>>>
7131 20:15:21.808954 [Flow] Enable top DCM control <<<<<
7132 20:15:21.809035 Enable DLL master slave shuffle
7133 20:15:21.815607 ==============================================================
7134 20:15:21.818784 Gating Mode config
7135 20:15:21.822110 ==============================================================
7136 20:15:21.825680 Config description:
7137 20:15:21.835082 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7138 20:15:21.841781 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7139 20:15:21.845842 SELPH_MODE 0: By rank 1: By Phase
7140 20:15:21.851702 ==============================================================
7141 20:15:21.854658 GAT_TRACK_EN = 1
7142 20:15:21.858330 RX_GATING_MODE = 2
7143 20:15:21.861383 RX_GATING_TRACK_MODE = 2
7144 20:15:21.864580 SELPH_MODE = 1
7145 20:15:21.867798 PICG_EARLY_EN = 1
7146 20:15:21.871327 VALID_LAT_VALUE = 1
7147 20:15:21.874629 ==============================================================
7148 20:15:21.877904 Enter into Gating configuration >>>>
7149 20:15:21.881113 Exit from Gating configuration <<<<
7150 20:15:21.884816 Enter into DVFS_PRE_config >>>>>
7151 20:15:21.897836 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7152 20:15:21.900707 Exit from DVFS_PRE_config <<<<<
7153 20:15:21.903908 Enter into PICG configuration >>>>
7154 20:15:21.903989 Exit from PICG configuration <<<<
7155 20:15:21.907158 [RX_INPUT] configuration >>>>>
7156 20:15:21.910719 [RX_INPUT] configuration <<<<<
7157 20:15:21.917095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7158 20:15:21.920435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7159 20:15:21.927037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7160 20:15:21.933515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7161 20:15:21.940043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 20:15:21.946821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 20:15:21.950396 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7164 20:15:21.953464 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7165 20:15:21.960410 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7166 20:15:21.963665 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7167 20:15:21.966582 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7168 20:15:21.970239 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7169 20:15:21.973018 ===================================
7170 20:15:21.976236 LPDDR4 DRAM CONFIGURATION
7171 20:15:21.979910 ===================================
7172 20:15:21.982764 EX_ROW_EN[0] = 0x0
7173 20:15:21.982845 EX_ROW_EN[1] = 0x0
7174 20:15:21.986249 LP4Y_EN = 0x0
7175 20:15:21.986329 WORK_FSP = 0x1
7176 20:15:21.989391 WL = 0x5
7177 20:15:21.989471 RL = 0x5
7178 20:15:21.992830 BL = 0x2
7179 20:15:21.995925 RPST = 0x0
7180 20:15:21.996005 RD_PRE = 0x0
7181 20:15:21.999738 WR_PRE = 0x1
7182 20:15:21.999834 WR_PST = 0x1
7183 20:15:22.002947 DBI_WR = 0x0
7184 20:15:22.003030 DBI_RD = 0x0
7185 20:15:22.006204 OTF = 0x1
7186 20:15:22.009567 ===================================
7187 20:15:22.012502 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7188 20:15:22.015631 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7189 20:15:22.022352 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 20:15:22.025752 ===================================
7191 20:15:22.025833 LPDDR4 DRAM CONFIGURATION
7192 20:15:22.029497 ===================================
7193 20:15:22.032596 EX_ROW_EN[0] = 0x10
7194 20:15:22.032676 EX_ROW_EN[1] = 0x0
7195 20:15:22.035606 LP4Y_EN = 0x0
7196 20:15:22.035690 WORK_FSP = 0x1
7197 20:15:22.038969 WL = 0x5
7198 20:15:22.042112 RL = 0x5
7199 20:15:22.042218 BL = 0x2
7200 20:15:22.045844 RPST = 0x0
7201 20:15:22.045924 RD_PRE = 0x0
7202 20:15:22.048616 WR_PRE = 0x1
7203 20:15:22.048709 WR_PST = 0x1
7204 20:15:22.052284 DBI_WR = 0x0
7205 20:15:22.052365 DBI_RD = 0x0
7206 20:15:22.055196 OTF = 0x1
7207 20:15:22.058569 ===================================
7208 20:15:22.065360 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7209 20:15:22.065442 ==
7210 20:15:22.068740 Dram Type= 6, Freq= 0, CH_0, rank 0
7211 20:15:22.071593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7212 20:15:22.071674 ==
7213 20:15:22.075125 [Duty_Offset_Calibration]
7214 20:15:22.075206 B0:2 B1:0 CA:4
7215 20:15:22.075270
7216 20:15:22.078868 [DutyScan_Calibration_Flow] k_type=0
7217 20:15:22.087842
7218 20:15:22.087922 ==CLK 0==
7219 20:15:22.091485 Final CLK duty delay cell = -4
7220 20:15:22.095005 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7221 20:15:22.097995 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7222 20:15:22.101285 [-4] AVG Duty = 4937%(X100)
7223 20:15:22.101366
7224 20:15:22.104481 CH0 CLK Duty spec in!! Max-Min= 187%
7225 20:15:22.108072 [DutyScan_Calibration_Flow] ====Done====
7226 20:15:22.108153
7227 20:15:22.111111 [DutyScan_Calibration_Flow] k_type=1
7228 20:15:22.128608
7229 20:15:22.128694 ==DQS 0 ==
7230 20:15:22.131418 Final DQS duty delay cell = 0
7231 20:15:22.134925 [0] MAX Duty = 5249%(X100), DQS PI = 38
7232 20:15:22.138304 [0] MIN Duty = 5093%(X100), DQS PI = 4
7233 20:15:22.141313 [0] AVG Duty = 5171%(X100)
7234 20:15:22.141394
7235 20:15:22.141490 ==DQS 1 ==
7236 20:15:22.144772 Final DQS duty delay cell = 0
7237 20:15:22.147816 [0] MAX Duty = 5156%(X100), DQS PI = 2
7238 20:15:22.151167 [0] MIN Duty = 4969%(X100), DQS PI = 10
7239 20:15:22.154585 [0] AVG Duty = 5062%(X100)
7240 20:15:22.154668
7241 20:15:22.158137 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7242 20:15:22.158218
7243 20:15:22.161055 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7244 20:15:22.164479 [DutyScan_Calibration_Flow] ====Done====
7245 20:15:22.164560
7246 20:15:22.167690 [DutyScan_Calibration_Flow] k_type=3
7247 20:15:22.185280
7248 20:15:22.185361 ==DQM 0 ==
7249 20:15:22.188873 Final DQM duty delay cell = 0
7250 20:15:22.191818 [0] MAX Duty = 5124%(X100), DQS PI = 22
7251 20:15:22.195133 [0] MIN Duty = 4875%(X100), DQS PI = 54
7252 20:15:22.198977 [0] AVG Duty = 4999%(X100)
7253 20:15:22.199058
7254 20:15:22.199122 ==DQM 1 ==
7255 20:15:22.202050 Final DQM duty delay cell = 0
7256 20:15:22.205661 [0] MAX Duty = 5000%(X100), DQS PI = 2
7257 20:15:22.208334 [0] MIN Duty = 4844%(X100), DQS PI = 16
7258 20:15:22.211594 [0] AVG Duty = 4922%(X100)
7259 20:15:22.211675
7260 20:15:22.215642 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7261 20:15:22.215755
7262 20:15:22.218571 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7263 20:15:22.221376 [DutyScan_Calibration_Flow] ====Done====
7264 20:15:22.221457
7265 20:15:22.225158 [DutyScan_Calibration_Flow] k_type=2
7266 20:15:22.242198
7267 20:15:22.242282 ==DQ 0 ==
7268 20:15:22.247183 Final DQ duty delay cell = 0
7269 20:15:22.249074 [0] MAX Duty = 5124%(X100), DQS PI = 20
7270 20:15:22.252115 [0] MIN Duty = 4938%(X100), DQS PI = 12
7271 20:15:22.255644 [0] AVG Duty = 5031%(X100)
7272 20:15:22.255724
7273 20:15:22.255827 ==DQ 1 ==
7274 20:15:22.259047 Final DQ duty delay cell = 0
7275 20:15:22.261924 [0] MAX Duty = 5187%(X100), DQS PI = 2
7276 20:15:22.265745 [0] MIN Duty = 4938%(X100), DQS PI = 12
7277 20:15:22.265846 [0] AVG Duty = 5062%(X100)
7278 20:15:22.268658
7279 20:15:22.272508 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7280 20:15:22.272589
7281 20:15:22.275485 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7282 20:15:22.278621 [DutyScan_Calibration_Flow] ====Done====
7283 20:15:22.278722 ==
7284 20:15:22.281766 Dram Type= 6, Freq= 0, CH_1, rank 0
7285 20:15:22.284935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 20:15:22.285020 ==
7287 20:15:22.288147 [Duty_Offset_Calibration]
7288 20:15:22.288227 B0:0 B1:-1 CA:3
7289 20:15:22.288292
7290 20:15:22.291623 [DutyScan_Calibration_Flow] k_type=0
7291 20:15:22.301924
7292 20:15:22.302004 ==CLK 0==
7293 20:15:22.305172 Final CLK duty delay cell = -4
7294 20:15:22.308434 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7295 20:15:22.311776 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7296 20:15:22.314831 [-4] AVG Duty = 4922%(X100)
7297 20:15:22.314937
7298 20:15:22.318834 CH1 CLK Duty spec in!! Max-Min= 156%
7299 20:15:22.321839 [DutyScan_Calibration_Flow] ====Done====
7300 20:15:22.321919
7301 20:15:22.325050 [DutyScan_Calibration_Flow] k_type=1
7302 20:15:22.341153
7303 20:15:22.341291 ==DQS 0 ==
7304 20:15:22.344376 Final DQS duty delay cell = 0
7305 20:15:22.348310 [0] MAX Duty = 5218%(X100), DQS PI = 30
7306 20:15:22.350894 [0] MIN Duty = 4907%(X100), DQS PI = 58
7307 20:15:22.354311 [0] AVG Duty = 5062%(X100)
7308 20:15:22.354391
7309 20:15:22.354464 ==DQS 1 ==
7310 20:15:22.357618 Final DQS duty delay cell = -4
7311 20:15:22.360931 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7312 20:15:22.364627 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7313 20:15:22.367580 [-4] AVG Duty = 4922%(X100)
7314 20:15:22.367659
7315 20:15:22.370751 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7316 20:15:22.370831
7317 20:15:22.374315 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7318 20:15:22.377076 [DutyScan_Calibration_Flow] ====Done====
7319 20:15:22.377155
7320 20:15:22.380940 [DutyScan_Calibration_Flow] k_type=3
7321 20:15:22.398234
7322 20:15:22.398314 ==DQM 0 ==
7323 20:15:22.401543 Final DQM duty delay cell = 0
7324 20:15:22.404634 [0] MAX Duty = 5062%(X100), DQS PI = 32
7325 20:15:22.408117 [0] MIN Duty = 4750%(X100), DQS PI = 40
7326 20:15:22.411350 [0] AVG Duty = 4906%(X100)
7327 20:15:22.411473
7328 20:15:22.411537 ==DQM 1 ==
7329 20:15:22.414603 Final DQM duty delay cell = 0
7330 20:15:22.417897 [0] MAX Duty = 5000%(X100), DQS PI = 30
7331 20:15:22.421423 [0] MIN Duty = 4813%(X100), DQS PI = 0
7332 20:15:22.424844 [0] AVG Duty = 4906%(X100)
7333 20:15:22.424929
7334 20:15:22.427676 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7335 20:15:22.427756
7336 20:15:22.431028 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7337 20:15:22.434382 [DutyScan_Calibration_Flow] ====Done====
7338 20:15:22.434461
7339 20:15:22.437444 [DutyScan_Calibration_Flow] k_type=2
7340 20:15:22.454698
7341 20:15:22.454782 ==DQ 0 ==
7342 20:15:22.457657 Final DQ duty delay cell = -4
7343 20:15:22.461148 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7344 20:15:22.464490 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7345 20:15:22.467799 [-4] AVG Duty = 4891%(X100)
7346 20:15:22.467873
7347 20:15:22.467935 ==DQ 1 ==
7348 20:15:22.470863 Final DQ duty delay cell = 0
7349 20:15:22.474733 [0] MAX Duty = 5031%(X100), DQS PI = 30
7350 20:15:22.477895 [0] MIN Duty = 4844%(X100), DQS PI = 60
7351 20:15:22.481008 [0] AVG Duty = 4937%(X100)
7352 20:15:22.481089
7353 20:15:22.484807 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7354 20:15:22.484894
7355 20:15:22.487257 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7356 20:15:22.490995 [DutyScan_Calibration_Flow] ====Done====
7357 20:15:22.493926 nWR fixed to 30
7358 20:15:22.497640 [ModeRegInit_LP4] CH0 RK0
7359 20:15:22.497722 [ModeRegInit_LP4] CH0 RK1
7360 20:15:22.500420 [ModeRegInit_LP4] CH1 RK0
7361 20:15:22.503677 [ModeRegInit_LP4] CH1 RK1
7362 20:15:22.503775 match AC timing 5
7363 20:15:22.510545 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7364 20:15:22.513748 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7365 20:15:22.517251 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7366 20:15:22.523508 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7367 20:15:22.526685 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7368 20:15:22.526766 [MiockJmeterHQA]
7369 20:15:22.530445
7370 20:15:22.530526 [DramcMiockJmeter] u1RxGatingPI = 0
7371 20:15:22.533412 0 : 4253, 4026
7372 20:15:22.533495 4 : 4253, 4027
7373 20:15:22.536739 8 : 4258, 4030
7374 20:15:22.536822 12 : 4253, 4026
7375 20:15:22.540004 16 : 4252, 4027
7376 20:15:22.540086 20 : 4252, 4027
7377 20:15:22.543505 24 : 4253, 4026
7378 20:15:22.543588 28 : 4363, 4138
7379 20:15:22.543654 32 : 4252, 4027
7380 20:15:22.547066 36 : 4252, 4027
7381 20:15:22.547189 40 : 4253, 4027
7382 20:15:22.549923 44 : 4257, 4032
7383 20:15:22.550052 48 : 4252, 4027
7384 20:15:22.553513 52 : 4363, 4137
7385 20:15:22.553637 56 : 4363, 4137
7386 20:15:22.556846 60 : 4253, 4027
7387 20:15:22.556970 64 : 4252, 4027
7388 20:15:22.557081 68 : 4252, 4027
7389 20:15:22.559707 72 : 4250, 4026
7390 20:15:22.559830 76 : 4250, 4026
7391 20:15:22.563627 80 : 4360, 4137
7392 20:15:22.563751 84 : 4250, 4027
7393 20:15:22.566467 88 : 4250, 4027
7394 20:15:22.566586 92 : 4250, 4026
7395 20:15:22.569765 96 : 4250, 2962
7396 20:15:22.569885 100 : 4250, 0
7397 20:15:22.569999 104 : 4250, 0
7398 20:15:22.572876 108 : 4366, 0
7399 20:15:22.572999 112 : 4360, 0
7400 20:15:22.573111 116 : 4361, 0
7401 20:15:22.576766 120 : 4250, 0
7402 20:15:22.576888 124 : 4361, 0
7403 20:15:22.580224 128 : 4250, 0
7404 20:15:22.580347 132 : 4250, 0
7405 20:15:22.580459 136 : 4250, 0
7406 20:15:22.582814 140 : 4253, 0
7407 20:15:22.582935 144 : 4250, 0
7408 20:15:22.586301 148 : 4250, 0
7409 20:15:22.586423 152 : 4250, 0
7410 20:15:22.586536 156 : 4250, 0
7411 20:15:22.589644 160 : 4361, 0
7412 20:15:22.589770 164 : 4360, 0
7413 20:15:22.592851 168 : 4361, 0
7414 20:15:22.592975 172 : 4250, 0
7415 20:15:22.593088 176 : 4253, 0
7416 20:15:22.595879 180 : 4250, 0
7417 20:15:22.596003 184 : 4250, 0
7418 20:15:22.599420 188 : 4250, 0
7419 20:15:22.599543 192 : 4250, 0
7420 20:15:22.599654 196 : 4252, 0
7421 20:15:22.602490 200 : 4250, 0
7422 20:15:22.602614 204 : 4250, 0
7423 20:15:22.605957 208 : 4252, 0
7424 20:15:22.606084 212 : 4361, 0
7425 20:15:22.606195 216 : 4250, 0
7426 20:15:22.609690 220 : 4250, 794
7427 20:15:22.609811 224 : 4250, 4007
7428 20:15:22.612899 228 : 4360, 4138
7429 20:15:22.613021 232 : 4249, 4027
7430 20:15:22.615466 236 : 4250, 4027
7431 20:15:22.615588 240 : 4360, 4137
7432 20:15:22.619055 244 : 4250, 4027
7433 20:15:22.619179 248 : 4250, 4027
7434 20:15:22.622827 252 : 4361, 4137
7435 20:15:22.622951 256 : 4250, 4027
7436 20:15:22.623061 260 : 4250, 4026
7437 20:15:22.625601 264 : 4250, 4027
7438 20:15:22.625724 268 : 4250, 4026
7439 20:15:22.628761 272 : 4250, 4027
7440 20:15:22.628886 276 : 4253, 4026
7441 20:15:22.632521 280 : 4361, 4137
7442 20:15:22.632632 284 : 4250, 4027
7443 20:15:22.635689 288 : 4250, 4027
7444 20:15:22.635799 292 : 4360, 4138
7445 20:15:22.638527 296 : 4250, 4026
7446 20:15:22.638617 300 : 4250, 4027
7447 20:15:22.642118 304 : 4361, 4137
7448 20:15:22.642200 308 : 4250, 4027
7449 20:15:22.645485 312 : 4250, 4027
7450 20:15:22.645569 316 : 4250, 4027
7451 20:15:22.648855 320 : 4250, 4026
7452 20:15:22.648940 324 : 4250, 4027
7453 20:15:22.652523 328 : 4250, 4026
7454 20:15:22.652605 332 : 4361, 3920
7455 20:15:22.652671 336 : 4250, 1316
7456 20:15:22.655554
7457 20:15:22.655683 MIOCK jitter meter ch=0
7458 20:15:22.655793
7459 20:15:22.658858 1T = (336-100) = 236 dly cells
7460 20:15:22.665018 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7461 20:15:22.665100 ==
7462 20:15:22.668650 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 20:15:22.671514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7464 20:15:22.671595 ==
7465 20:15:22.678149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7466 20:15:22.681497 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7467 20:15:22.684936 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7468 20:15:22.691582 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7469 20:15:22.701467 [CA 0] Center 43 (13~74) winsize 62
7470 20:15:22.704229 [CA 1] Center 42 (12~73) winsize 62
7471 20:15:22.707494 [CA 2] Center 37 (8~67) winsize 60
7472 20:15:22.710551 [CA 3] Center 37 (7~67) winsize 61
7473 20:15:22.714239 [CA 4] Center 36 (6~66) winsize 61
7474 20:15:22.717801 [CA 5] Center 35 (5~66) winsize 62
7475 20:15:22.717882
7476 20:15:22.720636 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7477 20:15:22.720717
7478 20:15:22.727757 [CATrainingPosCal] consider 1 rank data
7479 20:15:22.727839 u2DelayCellTimex100 = 275/100 ps
7480 20:15:22.733817 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7481 20:15:22.737255 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7482 20:15:22.740317 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7483 20:15:22.743653 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7484 20:15:22.746725 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7485 20:15:22.750330 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7486 20:15:22.750411
7487 20:15:22.753588 CA PerBit enable=1, Macro0, CA PI delay=35
7488 20:15:22.753686
7489 20:15:22.756628 [CBTSetCACLKResult] CA Dly = 35
7490 20:15:22.760382 CS Dly: 11 (0~42)
7491 20:15:22.763353 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7492 20:15:22.766440 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7493 20:15:22.766520 ==
7494 20:15:22.769890 Dram Type= 6, Freq= 0, CH_0, rank 1
7495 20:15:22.776575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 20:15:22.776657 ==
7497 20:15:22.779981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 20:15:22.786291 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 20:15:22.789651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 20:15:22.796436 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 20:15:22.804745 [CA 0] Center 43 (13~74) winsize 62
7502 20:15:22.808115 [CA 1] Center 43 (13~73) winsize 61
7503 20:15:22.810803 [CA 2] Center 38 (9~68) winsize 60
7504 20:15:22.814160 [CA 3] Center 38 (9~68) winsize 60
7505 20:15:22.817945 [CA 4] Center 37 (7~67) winsize 61
7506 20:15:22.820946 [CA 5] Center 36 (6~66) winsize 61
7507 20:15:22.821067
7508 20:15:22.825118 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7509 20:15:22.825237
7510 20:15:22.827292 [CATrainingPosCal] consider 2 rank data
7511 20:15:22.830755 u2DelayCellTimex100 = 275/100 ps
7512 20:15:22.837813 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7513 20:15:22.840852 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7514 20:15:22.843998 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7515 20:15:22.847654 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7516 20:15:22.850989 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 20:15:22.853784 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7518 20:15:22.853905
7519 20:15:22.856958 CA PerBit enable=1, Macro0, CA PI delay=36
7520 20:15:22.857078
7521 20:15:22.860307 [CBTSetCACLKResult] CA Dly = 36
7522 20:15:22.864004 CS Dly: 11 (0~43)
7523 20:15:22.866959 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 20:15:22.870606 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 20:15:22.870708
7526 20:15:22.873558 ----->DramcWriteLeveling(PI) begin...
7527 20:15:22.873671 ==
7528 20:15:22.877394 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 20:15:22.883482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 20:15:22.883564 ==
7531 20:15:22.886818 Write leveling (Byte 0): 33 => 33
7532 20:15:22.889834 Write leveling (Byte 1): 23 => 23
7533 20:15:22.889915 DramcWriteLeveling(PI) end<-----
7534 20:15:22.893504
7535 20:15:22.893584 ==
7536 20:15:22.897078 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 20:15:22.900076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 20:15:22.900157 ==
7539 20:15:22.903599 [Gating] SW mode calibration
7540 20:15:22.909608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7541 20:15:22.916331 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7542 20:15:22.919935 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 20:15:22.923245 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 20:15:22.929389 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 20:15:22.932973 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7546 20:15:22.935825 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7547 20:15:22.942522 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7548 20:15:22.945659 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 20:15:22.949294 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 20:15:22.956602 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 20:15:22.958738 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 20:15:22.962175 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7553 20:15:22.969190 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7554 20:15:22.972059 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7555 20:15:22.975199 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
7556 20:15:22.981938 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7557 20:15:22.985116 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 20:15:22.988649 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 20:15:22.995213 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 20:15:22.998387 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7561 20:15:23.001487 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7562 20:15:23.008488 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 20:15:23.011540 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7564 20:15:23.014978 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 20:15:23.021190 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 20:15:23.024783 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 20:15:23.028002 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 20:15:23.035148 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 20:15:23.037814 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7570 20:15:23.041640 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 20:15:23.047514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 20:15:23.050841 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 20:15:23.054100 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 20:15:23.060839 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 20:15:23.064180 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 20:15:23.067616 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 20:15:23.073994 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 20:15:23.077143 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 20:15:23.080921 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 20:15:23.087267 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 20:15:23.090870 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 20:15:23.093678 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 20:15:23.100380 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 20:15:23.103886 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 20:15:23.106772 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7586 20:15:23.110812 Total UI for P1: 0, mck2ui 16
7587 20:15:23.113793 best dqsien dly found for B0: ( 1, 9, 10)
7588 20:15:23.119791 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7589 20:15:23.123528 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 20:15:23.126630 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 20:15:23.133089 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 20:15:23.133168 Total UI for P1: 0, mck2ui 16
7593 20:15:23.139609 best dqsien dly found for B1: ( 1, 9, 22)
7594 20:15:23.143304 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7595 20:15:23.146396 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7596 20:15:23.146467
7597 20:15:23.149514 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7598 20:15:23.153397 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7599 20:15:23.156158 [Gating] SW calibration Done
7600 20:15:23.156278 ==
7601 20:15:23.159262 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 20:15:23.162683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 20:15:23.162801 ==
7604 20:15:23.166243 RX Vref Scan: 0
7605 20:15:23.166362
7606 20:15:23.169662 RX Vref 0 -> 0, step: 1
7607 20:15:23.169816
7608 20:15:23.169925 RX Delay 0 -> 252, step: 8
7609 20:15:23.176011 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7610 20:15:23.179304 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7611 20:15:23.183165 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7612 20:15:23.186420 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7613 20:15:23.189536 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7614 20:15:23.196062 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7615 20:15:23.198951 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7616 20:15:23.202803 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7617 20:15:23.206202 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7618 20:15:23.209442 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7619 20:15:23.215560 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7620 20:15:23.219465 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7621 20:15:23.222411 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7622 20:15:23.225338 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7623 20:15:23.228679 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7624 20:15:23.235405 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7625 20:15:23.235500 ==
7626 20:15:23.239015 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 20:15:23.242889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 20:15:23.242970 ==
7629 20:15:23.243035 DQS Delay:
7630 20:15:23.245308 DQS0 = 0, DQS1 = 0
7631 20:15:23.245390 DQM Delay:
7632 20:15:23.248803 DQM0 = 132, DQM1 = 127
7633 20:15:23.248888 DQ Delay:
7634 20:15:23.251640 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
7635 20:15:23.255030 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7636 20:15:23.258382 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7637 20:15:23.265248 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7638 20:15:23.265329
7639 20:15:23.265393
7640 20:15:23.265453 ==
7641 20:15:23.268203 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 20:15:23.271960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 20:15:23.272042 ==
7644 20:15:23.272107
7645 20:15:23.272168
7646 20:15:23.275010 TX Vref Scan disable
7647 20:15:23.275091 == TX Byte 0 ==
7648 20:15:23.281455 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7649 20:15:23.284991 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7650 20:15:23.285086 == TX Byte 1 ==
7651 20:15:23.291699 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7652 20:15:23.294480 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7653 20:15:23.294561 ==
7654 20:15:23.298058 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 20:15:23.300877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 20:15:23.304464 ==
7657 20:15:23.317216
7658 20:15:23.320665 TX Vref early break, caculate TX vref
7659 20:15:23.323879 TX Vref=16, minBit 4, minWin=22, winSum=369
7660 20:15:23.327983 TX Vref=18, minBit 8, minWin=22, winSum=381
7661 20:15:23.330809 TX Vref=20, minBit 1, minWin=23, winSum=384
7662 20:15:23.334033 TX Vref=22, minBit 8, minWin=23, winSum=398
7663 20:15:23.337175 TX Vref=24, minBit 7, minWin=24, winSum=405
7664 20:15:23.343889 TX Vref=26, minBit 8, minWin=24, winSum=417
7665 20:15:23.347157 TX Vref=28, minBit 0, minWin=26, winSum=419
7666 20:15:23.350375 TX Vref=30, minBit 4, minWin=24, winSum=410
7667 20:15:23.353881 TX Vref=32, minBit 0, minWin=25, winSum=409
7668 20:15:23.357418 TX Vref=34, minBit 1, minWin=24, winSum=401
7669 20:15:23.363694 TX Vref=36, minBit 6, minWin=23, winSum=386
7670 20:15:23.367010 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 28
7671 20:15:23.367173
7672 20:15:23.370156 Final TX Range 0 Vref 28
7673 20:15:23.370261
7674 20:15:23.370381 ==
7675 20:15:23.373254 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 20:15:23.377034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 20:15:23.380116 ==
7678 20:15:23.380223
7679 20:15:23.380316
7680 20:15:23.380404 TX Vref Scan disable
7681 20:15:23.386424 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7682 20:15:23.386558 == TX Byte 0 ==
7683 20:15:23.390532 u2DelayCellOfst[0]=14 cells (4 PI)
7684 20:15:23.393368 u2DelayCellOfst[1]=17 cells (5 PI)
7685 20:15:23.396691 u2DelayCellOfst[2]=10 cells (3 PI)
7686 20:15:23.399906 u2DelayCellOfst[3]=14 cells (4 PI)
7687 20:15:23.403732 u2DelayCellOfst[4]=10 cells (3 PI)
7688 20:15:23.406366 u2DelayCellOfst[5]=0 cells (0 PI)
7689 20:15:23.409549 u2DelayCellOfst[6]=17 cells (5 PI)
7690 20:15:23.412904 u2DelayCellOfst[7]=17 cells (5 PI)
7691 20:15:23.416247 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7692 20:15:23.422879 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7693 20:15:23.422961 == TX Byte 1 ==
7694 20:15:23.426380 u2DelayCellOfst[8]=3 cells (1 PI)
7695 20:15:23.429803 u2DelayCellOfst[9]=0 cells (0 PI)
7696 20:15:23.433116 u2DelayCellOfst[10]=7 cells (2 PI)
7697 20:15:23.435900 u2DelayCellOfst[11]=3 cells (1 PI)
7698 20:15:23.439450 u2DelayCellOfst[12]=10 cells (3 PI)
7699 20:15:23.443752 u2DelayCellOfst[13]=10 cells (3 PI)
7700 20:15:23.446124 u2DelayCellOfst[14]=14 cells (4 PI)
7701 20:15:23.449544 u2DelayCellOfst[15]=10 cells (3 PI)
7702 20:15:23.453452 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7703 20:15:23.456253 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7704 20:15:23.459779 DramC Write-DBI on
7705 20:15:23.459861 ==
7706 20:15:23.463087 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 20:15:23.466247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 20:15:23.466329 ==
7709 20:15:23.466394
7710 20:15:23.466453
7711 20:15:23.469404 TX Vref Scan disable
7712 20:15:23.472514 == TX Byte 0 ==
7713 20:15:23.475796 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7714 20:15:23.475878 == TX Byte 1 ==
7715 20:15:23.482410 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7716 20:15:23.482491 DramC Write-DBI off
7717 20:15:23.482557
7718 20:15:23.482616 [DATLAT]
7719 20:15:23.485909 Freq=1600, CH0 RK0
7720 20:15:23.485990
7721 20:15:23.489269 DATLAT Default: 0xf
7722 20:15:23.489351 0, 0xFFFF, sum = 0
7723 20:15:23.492227 1, 0xFFFF, sum = 0
7724 20:15:23.492309 2, 0xFFFF, sum = 0
7725 20:15:23.495831 3, 0xFFFF, sum = 0
7726 20:15:23.495913 4, 0xFFFF, sum = 0
7727 20:15:23.499181 5, 0xFFFF, sum = 0
7728 20:15:23.499263 6, 0xFFFF, sum = 0
7729 20:15:23.502115 7, 0xFFFF, sum = 0
7730 20:15:23.502237 8, 0xFFFF, sum = 0
7731 20:15:23.505337 9, 0xFFFF, sum = 0
7732 20:15:23.505419 10, 0xFFFF, sum = 0
7733 20:15:23.508657 11, 0xFFFF, sum = 0
7734 20:15:23.508740 12, 0xFFFF, sum = 0
7735 20:15:23.512039 13, 0xFFFF, sum = 0
7736 20:15:23.512121 14, 0x0, sum = 1
7737 20:15:23.515251 15, 0x0, sum = 2
7738 20:15:23.515370 16, 0x0, sum = 3
7739 20:15:23.518468 17, 0x0, sum = 4
7740 20:15:23.518552 best_step = 15
7741 20:15:23.518617
7742 20:15:23.518676 ==
7743 20:15:23.522120 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 20:15:23.528461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 20:15:23.528545 ==
7746 20:15:23.528632 RX Vref Scan: 1
7747 20:15:23.528741
7748 20:15:23.531710 Set Vref Range= 24 -> 127
7749 20:15:23.531791
7750 20:15:23.535082 RX Vref 24 -> 127, step: 1
7751 20:15:23.535163
7752 20:15:23.538219 RX Delay 19 -> 252, step: 4
7753 20:15:23.538329
7754 20:15:23.541657 Set Vref, RX VrefLevel [Byte0]: 24
7755 20:15:23.545097 [Byte1]: 24
7756 20:15:23.545179
7757 20:15:23.548337 Set Vref, RX VrefLevel [Byte0]: 25
7758 20:15:23.551733 [Byte1]: 25
7759 20:15:23.551819
7760 20:15:23.554937 Set Vref, RX VrefLevel [Byte0]: 26
7761 20:15:23.557888 [Byte1]: 26
7762 20:15:23.561463
7763 20:15:23.561548 Set Vref, RX VrefLevel [Byte0]: 27
7764 20:15:23.564924 [Byte1]: 27
7765 20:15:23.568678
7766 20:15:23.568783 Set Vref, RX VrefLevel [Byte0]: 28
7767 20:15:23.572131 [Byte1]: 28
7768 20:15:23.576434
7769 20:15:23.576518 Set Vref, RX VrefLevel [Byte0]: 29
7770 20:15:23.579693 [Byte1]: 29
7771 20:15:23.584259
7772 20:15:23.584340 Set Vref, RX VrefLevel [Byte0]: 30
7773 20:15:23.587265 [Byte1]: 30
7774 20:15:23.591832
7775 20:15:23.591941 Set Vref, RX VrefLevel [Byte0]: 31
7776 20:15:23.595038 [Byte1]: 31
7777 20:15:23.600548
7778 20:15:23.600629 Set Vref, RX VrefLevel [Byte0]: 32
7779 20:15:23.602456 [Byte1]: 32
7780 20:15:23.606602
7781 20:15:23.606687 Set Vref, RX VrefLevel [Byte0]: 33
7782 20:15:23.609902 [Byte1]: 33
7783 20:15:23.614516
7784 20:15:23.614612 Set Vref, RX VrefLevel [Byte0]: 34
7785 20:15:23.617505 [Byte1]: 34
7786 20:15:23.621955
7787 20:15:23.622036 Set Vref, RX VrefLevel [Byte0]: 35
7788 20:15:23.625053 [Byte1]: 35
7789 20:15:23.629626
7790 20:15:23.629707 Set Vref, RX VrefLevel [Byte0]: 36
7791 20:15:23.632777 [Byte1]: 36
7792 20:15:23.637602
7793 20:15:23.637683 Set Vref, RX VrefLevel [Byte0]: 37
7794 20:15:23.640239 [Byte1]: 37
7795 20:15:23.644834
7796 20:15:23.644915 Set Vref, RX VrefLevel [Byte0]: 38
7797 20:15:23.647825 [Byte1]: 38
7798 20:15:23.652242
7799 20:15:23.652323 Set Vref, RX VrefLevel [Byte0]: 39
7800 20:15:23.655246 [Byte1]: 39
7801 20:15:23.660851
7802 20:15:23.660958 Set Vref, RX VrefLevel [Byte0]: 40
7803 20:15:23.663350 [Byte1]: 40
7804 20:15:23.668669
7805 20:15:23.668749 Set Vref, RX VrefLevel [Byte0]: 41
7806 20:15:23.670829 [Byte1]: 41
7807 20:15:23.674950
7808 20:15:23.675076 Set Vref, RX VrefLevel [Byte0]: 42
7809 20:15:23.678102 [Byte1]: 42
7810 20:15:23.682741
7811 20:15:23.682836 Set Vref, RX VrefLevel [Byte0]: 43
7812 20:15:23.685833 [Byte1]: 43
7813 20:15:23.690003
7814 20:15:23.690088 Set Vref, RX VrefLevel [Byte0]: 44
7815 20:15:23.693374 [Byte1]: 44
7816 20:15:23.697706
7817 20:15:23.697802 Set Vref, RX VrefLevel [Byte0]: 45
7818 20:15:23.700927 [Byte1]: 45
7819 20:15:23.705175
7820 20:15:23.705255 Set Vref, RX VrefLevel [Byte0]: 46
7821 20:15:23.708494 [Byte1]: 46
7822 20:15:23.712960
7823 20:15:23.713067 Set Vref, RX VrefLevel [Byte0]: 47
7824 20:15:23.716005 [Byte1]: 47
7825 20:15:23.720275
7826 20:15:23.720356 Set Vref, RX VrefLevel [Byte0]: 48
7827 20:15:23.723939 [Byte1]: 48
7828 20:15:23.728071
7829 20:15:23.728153 Set Vref, RX VrefLevel [Byte0]: 49
7830 20:15:23.731250 [Byte1]: 49
7831 20:15:23.736076
7832 20:15:23.736184 Set Vref, RX VrefLevel [Byte0]: 50
7833 20:15:23.738858 [Byte1]: 50
7834 20:15:23.742977
7835 20:15:23.743058 Set Vref, RX VrefLevel [Byte0]: 51
7836 20:15:23.746341 [Byte1]: 51
7837 20:15:23.751085
7838 20:15:23.751209 Set Vref, RX VrefLevel [Byte0]: 52
7839 20:15:23.753930 [Byte1]: 52
7840 20:15:23.758113
7841 20:15:23.758194 Set Vref, RX VrefLevel [Byte0]: 53
7842 20:15:23.761581 [Byte1]: 53
7843 20:15:23.765931
7844 20:15:23.766012 Set Vref, RX VrefLevel [Byte0]: 54
7845 20:15:23.768915 [Byte1]: 54
7846 20:15:23.773418
7847 20:15:23.773505 Set Vref, RX VrefLevel [Byte0]: 55
7848 20:15:23.776419 [Byte1]: 55
7849 20:15:23.780856
7850 20:15:23.780937 Set Vref, RX VrefLevel [Byte0]: 56
7851 20:15:23.784281 [Byte1]: 56
7852 20:15:23.788603
7853 20:15:23.788683 Set Vref, RX VrefLevel [Byte0]: 57
7854 20:15:23.791663 [Byte1]: 57
7855 20:15:23.795884
7856 20:15:23.795965 Set Vref, RX VrefLevel [Byte0]: 58
7857 20:15:23.799330 [Byte1]: 58
7858 20:15:23.803946
7859 20:15:23.804027 Set Vref, RX VrefLevel [Byte0]: 59
7860 20:15:23.807131 [Byte1]: 59
7861 20:15:23.811292
7862 20:15:23.811383 Set Vref, RX VrefLevel [Byte0]: 60
7863 20:15:23.814633 [Byte1]: 60
7864 20:15:23.819007
7865 20:15:23.819088 Set Vref, RX VrefLevel [Byte0]: 61
7866 20:15:23.822034 [Byte1]: 61
7867 20:15:23.826342
7868 20:15:23.826423 Set Vref, RX VrefLevel [Byte0]: 62
7869 20:15:23.829813 [Byte1]: 62
7870 20:15:23.834302
7871 20:15:23.834383 Set Vref, RX VrefLevel [Byte0]: 63
7872 20:15:23.837070 [Byte1]: 63
7873 20:15:23.841465
7874 20:15:23.841545 Set Vref, RX VrefLevel [Byte0]: 64
7875 20:15:23.844499 [Byte1]: 64
7876 20:15:23.849110
7877 20:15:23.849191 Set Vref, RX VrefLevel [Byte0]: 65
7878 20:15:23.852297 [Byte1]: 65
7879 20:15:23.856470
7880 20:15:23.856551 Set Vref, RX VrefLevel [Byte0]: 66
7881 20:15:23.859788 [Byte1]: 66
7882 20:15:23.864221
7883 20:15:23.864302 Set Vref, RX VrefLevel [Byte0]: 67
7884 20:15:23.867546 [Byte1]: 67
7885 20:15:23.871819
7886 20:15:23.871900 Set Vref, RX VrefLevel [Byte0]: 68
7887 20:15:23.875346 [Byte1]: 68
7888 20:15:23.879132
7889 20:15:23.879237 Set Vref, RX VrefLevel [Byte0]: 69
7890 20:15:23.882940 [Byte1]: 69
7891 20:15:23.886720
7892 20:15:23.886806 Set Vref, RX VrefLevel [Byte0]: 70
7893 20:15:23.890462 [Byte1]: 70
7894 20:15:23.894660
7895 20:15:23.894767 Set Vref, RX VrefLevel [Byte0]: 71
7896 20:15:23.898534 [Byte1]: 71
7897 20:15:23.902106
7898 20:15:23.902192 Set Vref, RX VrefLevel [Byte0]: 72
7899 20:15:23.905366 [Byte1]: 72
7900 20:15:23.909685
7901 20:15:23.909780 Set Vref, RX VrefLevel [Byte0]: 73
7902 20:15:23.912938 [Byte1]: 73
7903 20:15:23.917128
7904 20:15:23.917209 Set Vref, RX VrefLevel [Byte0]: 74
7905 20:15:23.920377 [Byte1]: 74
7906 20:15:23.925153
7907 20:15:23.925234 Set Vref, RX VrefLevel [Byte0]: 75
7908 20:15:23.928112 [Byte1]: 75
7909 20:15:23.932961
7910 20:15:23.933042 Set Vref, RX VrefLevel [Byte0]: 76
7911 20:15:23.935652 [Byte1]: 76
7912 20:15:23.939837
7913 20:15:23.939917 Set Vref, RX VrefLevel [Byte0]: 77
7914 20:15:23.943710 [Byte1]: 77
7915 20:15:23.947529
7916 20:15:23.947610 Final RX Vref Byte 0 = 57 to rank0
7917 20:15:23.950954 Final RX Vref Byte 1 = 61 to rank0
7918 20:15:23.954021 Final RX Vref Byte 0 = 57 to rank1
7919 20:15:23.957179 Final RX Vref Byte 1 = 61 to rank1==
7920 20:15:23.960821 Dram Type= 6, Freq= 0, CH_0, rank 0
7921 20:15:23.967687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7922 20:15:23.967769 ==
7923 20:15:23.967834 DQS Delay:
7924 20:15:23.970261 DQS0 = 0, DQS1 = 0
7925 20:15:23.970342 DQM Delay:
7926 20:15:23.973519 DQM0 = 129, DQM1 = 123
7927 20:15:23.973600 DQ Delay:
7928 20:15:23.977066 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7929 20:15:23.980339 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
7930 20:15:23.983630 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7931 20:15:23.986618 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7932 20:15:23.986699
7933 20:15:23.986767
7934 20:15:23.986828
7935 20:15:23.989998 [DramC_TX_OE_Calibration] TA2
7936 20:15:23.993301 Original DQ_B0 (3 6) =30, OEN = 27
7937 20:15:23.996463 Original DQ_B1 (3 6) =30, OEN = 27
7938 20:15:23.999727 24, 0x0, End_B0=24 End_B1=24
7939 20:15:24.002944 25, 0x0, End_B0=25 End_B1=25
7940 20:15:24.003027 26, 0x0, End_B0=26 End_B1=26
7941 20:15:24.006476 27, 0x0, End_B0=27 End_B1=27
7942 20:15:24.009899 28, 0x0, End_B0=28 End_B1=28
7943 20:15:24.013269 29, 0x0, End_B0=29 End_B1=29
7944 20:15:24.016514 30, 0x0, End_B0=30 End_B1=30
7945 20:15:24.016597 31, 0x4141, End_B0=30 End_B1=30
7946 20:15:24.019733 Byte0 end_step=30 best_step=27
7947 20:15:24.022578 Byte1 end_step=30 best_step=27
7948 20:15:24.026097 Byte0 TX OE(2T, 0.5T) = (3, 3)
7949 20:15:24.029378 Byte1 TX OE(2T, 0.5T) = (3, 3)
7950 20:15:24.029460
7951 20:15:24.029525
7952 20:15:24.035642 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7953 20:15:24.038956 CH0 RK0: MR19=303, MR18=1815
7954 20:15:24.045544 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7955 20:15:24.045627
7956 20:15:24.049435 ----->DramcWriteLeveling(PI) begin...
7957 20:15:24.049543 ==
7958 20:15:24.052430 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 20:15:24.055574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 20:15:24.059006 ==
7961 20:15:24.059156 Write leveling (Byte 0): 36 => 36
7962 20:15:24.062070 Write leveling (Byte 1): 24 => 24
7963 20:15:24.065677 DramcWriteLeveling(PI) end<-----
7964 20:15:24.065762
7965 20:15:24.065827 ==
7966 20:15:24.068958 Dram Type= 6, Freq= 0, CH_0, rank 1
7967 20:15:24.075498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 20:15:24.075580 ==
7969 20:15:24.079298 [Gating] SW mode calibration
7970 20:15:24.085242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7971 20:15:24.088534 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7972 20:15:24.095583 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 20:15:24.098353 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 20:15:24.101921 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7975 20:15:24.108088 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7976 20:15:24.111652 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7977 20:15:24.114660 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7978 20:15:24.121408 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 20:15:24.125024 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 20:15:24.128156 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7981 20:15:24.134875 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 20:15:24.138494 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7983 20:15:24.141195 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7984 20:15:24.147919 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7985 20:15:24.151167 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7986 20:15:24.154405 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 20:15:24.161230 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 20:15:24.164394 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 20:15:24.167528 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7990 20:15:24.174140 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7991 20:15:24.177483 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7992 20:15:24.180962 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7993 20:15:24.187126 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7994 20:15:24.190584 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 20:15:24.193927 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 20:15:24.200550 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 20:15:24.203488 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 20:15:24.207335 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7999 20:15:24.213461 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8000 20:15:24.216721 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8001 20:15:24.219886 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8002 20:15:24.227008 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 20:15:24.230283 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 20:15:24.233744 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 20:15:24.239764 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 20:15:24.243164 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 20:15:24.246540 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 20:15:24.252834 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 20:15:24.256357 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 20:15:24.259909 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 20:15:24.266304 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 20:15:24.269138 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 20:15:24.272622 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 20:15:24.279168 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8015 20:15:24.282909 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8016 20:15:24.286464 Total UI for P1: 0, mck2ui 16
8017 20:15:24.289072 best dqsien dly found for B0: ( 1, 9, 8)
8018 20:15:24.292872 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8019 20:15:24.299166 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8020 20:15:24.302047 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 20:15:24.305843 Total UI for P1: 0, mck2ui 16
8022 20:15:24.309028 best dqsien dly found for B1: ( 1, 9, 18)
8023 20:15:24.311942 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8024 20:15:24.315693 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8025 20:15:24.315774
8026 20:15:24.318863 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8027 20:15:24.325306 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8028 20:15:24.325388 [Gating] SW calibration Done
8029 20:15:24.325453 ==
8030 20:15:24.328696 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 20:15:24.335432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 20:15:24.335514 ==
8033 20:15:24.335597 RX Vref Scan: 0
8034 20:15:24.335660
8035 20:15:24.338343 RX Vref 0 -> 0, step: 1
8036 20:15:24.338460
8037 20:15:24.342170 RX Delay 0 -> 252, step: 8
8038 20:15:24.345083 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8039 20:15:24.348385 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8040 20:15:24.351644 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8041 20:15:24.358880 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8042 20:15:24.362022 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8043 20:15:24.364821 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8044 20:15:24.368324 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8045 20:15:24.371534 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8046 20:15:24.377884 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8047 20:15:24.381617 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8048 20:15:24.384575 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8049 20:15:24.388003 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8050 20:15:24.391091 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8051 20:15:24.397696 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8052 20:15:24.401050 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8053 20:15:24.404383 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8054 20:15:24.404465 ==
8055 20:15:24.407413 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 20:15:24.413913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 20:15:24.414038 ==
8058 20:15:24.414150 DQS Delay:
8059 20:15:24.414259 DQS0 = 0, DQS1 = 0
8060 20:15:24.417771 DQM Delay:
8061 20:15:24.417892 DQM0 = 132, DQM1 = 127
8062 20:15:24.420663 DQ Delay:
8063 20:15:24.425100 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8064 20:15:24.427482 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8065 20:15:24.431052 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8066 20:15:24.433690 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8067 20:15:24.433813
8068 20:15:24.433922
8069 20:15:24.434032 ==
8070 20:15:24.437281 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 20:15:24.440760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 20:15:24.443559 ==
8073 20:15:24.443680
8074 20:15:24.443788
8075 20:15:24.443896 TX Vref Scan disable
8076 20:15:24.447041 == TX Byte 0 ==
8077 20:15:24.450733 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8078 20:15:24.456593 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8079 20:15:24.456676 == TX Byte 1 ==
8080 20:15:24.460126 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8081 20:15:24.468286 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8082 20:15:24.468409 ==
8083 20:15:24.470113 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 20:15:24.473286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 20:15:24.473368 ==
8086 20:15:24.487301
8087 20:15:24.490446 TX Vref early break, caculate TX vref
8088 20:15:24.493773 TX Vref=16, minBit 1, minWin=23, winSum=378
8089 20:15:24.497148 TX Vref=18, minBit 8, minWin=23, winSum=387
8090 20:15:24.500445 TX Vref=20, minBit 2, minWin=24, winSum=396
8091 20:15:24.503346 TX Vref=22, minBit 1, minWin=25, winSum=405
8092 20:15:24.506581 TX Vref=24, minBit 1, minWin=25, winSum=408
8093 20:15:24.513310 TX Vref=26, minBit 4, minWin=25, winSum=416
8094 20:15:24.516517 TX Vref=28, minBit 4, minWin=25, winSum=417
8095 20:15:24.519843 TX Vref=30, minBit 2, minWin=25, winSum=411
8096 20:15:24.523582 TX Vref=32, minBit 8, minWin=24, winSum=401
8097 20:15:24.526249 TX Vref=34, minBit 1, minWin=24, winSum=390
8098 20:15:24.533020 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
8099 20:15:24.533144
8100 20:15:24.536531 Final TX Range 0 Vref 28
8101 20:15:24.536653
8102 20:15:24.536763 ==
8103 20:15:24.539716 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 20:15:24.542873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 20:15:24.542994 ==
8106 20:15:24.543107
8107 20:15:24.546436
8108 20:15:24.546556 TX Vref Scan disable
8109 20:15:24.552659 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8110 20:15:24.552779 == TX Byte 0 ==
8111 20:15:24.556495 u2DelayCellOfst[0]=10 cells (3 PI)
8112 20:15:24.559669 u2DelayCellOfst[1]=14 cells (4 PI)
8113 20:15:24.562590 u2DelayCellOfst[2]=7 cells (2 PI)
8114 20:15:24.565759 u2DelayCellOfst[3]=10 cells (3 PI)
8115 20:15:24.569279 u2DelayCellOfst[4]=7 cells (2 PI)
8116 20:15:24.572755 u2DelayCellOfst[5]=0 cells (0 PI)
8117 20:15:24.575503 u2DelayCellOfst[6]=14 cells (4 PI)
8118 20:15:24.579130 u2DelayCellOfst[7]=14 cells (4 PI)
8119 20:15:24.582629 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8120 20:15:24.585852 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8121 20:15:24.588981 == TX Byte 1 ==
8122 20:15:24.592166 u2DelayCellOfst[8]=0 cells (0 PI)
8123 20:15:24.595452 u2DelayCellOfst[9]=0 cells (0 PI)
8124 20:15:24.598828 u2DelayCellOfst[10]=3 cells (1 PI)
8125 20:15:24.601910 u2DelayCellOfst[11]=0 cells (0 PI)
8126 20:15:24.605304 u2DelayCellOfst[12]=7 cells (2 PI)
8127 20:15:24.609374 u2DelayCellOfst[13]=10 cells (3 PI)
8128 20:15:24.609492 u2DelayCellOfst[14]=10 cells (3 PI)
8129 20:15:24.611788 u2DelayCellOfst[15]=10 cells (3 PI)
8130 20:15:24.618742 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8131 20:15:24.621722 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8132 20:15:24.625163 DramC Write-DBI on
8133 20:15:24.625244 ==
8134 20:15:24.628185 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 20:15:24.631505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 20:15:24.631609 ==
8137 20:15:24.631734
8138 20:15:24.631808
8139 20:15:24.635249 TX Vref Scan disable
8140 20:15:24.635356 == TX Byte 0 ==
8141 20:15:24.641969 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8142 20:15:24.642051 == TX Byte 1 ==
8143 20:15:24.645055 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8144 20:15:24.648954 DramC Write-DBI off
8145 20:15:24.649077
8146 20:15:24.649185 [DATLAT]
8147 20:15:24.651687 Freq=1600, CH0 RK1
8148 20:15:24.651808
8149 20:15:24.651920 DATLAT Default: 0xf
8150 20:15:24.654778 0, 0xFFFF, sum = 0
8151 20:15:24.658123 1, 0xFFFF, sum = 0
8152 20:15:24.658246 2, 0xFFFF, sum = 0
8153 20:15:24.661354 3, 0xFFFF, sum = 0
8154 20:15:24.661474 4, 0xFFFF, sum = 0
8155 20:15:24.664665 5, 0xFFFF, sum = 0
8156 20:15:24.664788 6, 0xFFFF, sum = 0
8157 20:15:24.668075 7, 0xFFFF, sum = 0
8158 20:15:24.668195 8, 0xFFFF, sum = 0
8159 20:15:24.671251 9, 0xFFFF, sum = 0
8160 20:15:24.671396 10, 0xFFFF, sum = 0
8161 20:15:24.674474 11, 0xFFFF, sum = 0
8162 20:15:24.674594 12, 0xFFFF, sum = 0
8163 20:15:24.678091 13, 0xFFFF, sum = 0
8164 20:15:24.678196 14, 0x0, sum = 1
8165 20:15:24.681226 15, 0x0, sum = 2
8166 20:15:24.681339 16, 0x0, sum = 3
8167 20:15:24.684508 17, 0x0, sum = 4
8168 20:15:24.684589 best_step = 15
8169 20:15:24.684654
8170 20:15:24.684714 ==
8171 20:15:24.687867 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 20:15:24.694357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 20:15:24.694438 ==
8174 20:15:24.694502 RX Vref Scan: 0
8175 20:15:24.694562
8176 20:15:24.697806 RX Vref 0 -> 0, step: 1
8177 20:15:24.697930
8178 20:15:24.700866 RX Delay 19 -> 252, step: 4
8179 20:15:24.704702 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8180 20:15:24.708026 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8181 20:15:24.711061 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8182 20:15:24.717771 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8183 20:15:24.721220 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8184 20:15:24.724599 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8185 20:15:24.727676 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8186 20:15:24.730714 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8187 20:15:24.737344 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8188 20:15:24.740469 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8189 20:15:24.743998 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8190 20:15:24.746989 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8191 20:15:24.753596 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8192 20:15:24.756815 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8193 20:15:24.760650 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8194 20:15:24.763623 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8195 20:15:24.763742 ==
8196 20:15:24.766762 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 20:15:24.773499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 20:15:24.773620 ==
8199 20:15:24.773733 DQS Delay:
8200 20:15:24.776551 DQS0 = 0, DQS1 = 0
8201 20:15:24.776671 DQM Delay:
8202 20:15:24.776781 DQM0 = 129, DQM1 = 123
8203 20:15:24.780012 DQ Delay:
8204 20:15:24.783541 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8205 20:15:24.786444 DQ4 =132, DQ5 =118, DQ6 =140, DQ7 =134
8206 20:15:24.790301 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8207 20:15:24.793108 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8208 20:15:24.793229
8209 20:15:24.793341
8210 20:15:24.793447
8211 20:15:24.796494 [DramC_TX_OE_Calibration] TA2
8212 20:15:24.799812 Original DQ_B0 (3 6) =30, OEN = 27
8213 20:15:24.803249 Original DQ_B1 (3 6) =30, OEN = 27
8214 20:15:24.806491 24, 0x0, End_B0=24 End_B1=24
8215 20:15:24.809583 25, 0x0, End_B0=25 End_B1=25
8216 20:15:24.809706 26, 0x0, End_B0=26 End_B1=26
8217 20:15:24.812837 27, 0x0, End_B0=27 End_B1=27
8218 20:15:24.816503 28, 0x0, End_B0=28 End_B1=28
8219 20:15:24.819470 29, 0x0, End_B0=29 End_B1=29
8220 20:15:24.819595 30, 0x0, End_B0=30 End_B1=30
8221 20:15:24.822590 31, 0x4141, End_B0=30 End_B1=30
8222 20:15:24.826704 Byte0 end_step=30 best_step=27
8223 20:15:24.829764 Byte1 end_step=30 best_step=27
8224 20:15:24.832573 Byte0 TX OE(2T, 0.5T) = (3, 3)
8225 20:15:24.836065 Byte1 TX OE(2T, 0.5T) = (3, 3)
8226 20:15:24.836183
8227 20:15:24.836295
8228 20:15:24.842550 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8229 20:15:24.845685 CH0 RK1: MR19=303, MR18=1513
8230 20:15:24.852719 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8231 20:15:24.855801 [RxdqsGatingPostProcess] freq 1600
8232 20:15:24.862910 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8233 20:15:24.863033 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 20:15:24.865697 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 20:15:24.868884 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 20:15:24.872560 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 20:15:24.875445 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 20:15:24.878487 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 20:15:24.881881 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 20:15:24.885060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 20:15:24.888785 Pre-setting of DQS Precalculation
8242 20:15:24.891686 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8243 20:15:24.895055 ==
8244 20:15:24.898539 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 20:15:24.901591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 20:15:24.901713 ==
8247 20:15:24.905220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8248 20:15:24.912164 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8249 20:15:24.914612 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8250 20:15:24.921215 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8251 20:15:24.929697 [CA 0] Center 42 (12~72) winsize 61
8252 20:15:24.933095 [CA 1] Center 42 (12~72) winsize 61
8253 20:15:24.936263 [CA 2] Center 38 (9~67) winsize 59
8254 20:15:24.939378 [CA 3] Center 37 (8~66) winsize 59
8255 20:15:24.943123 [CA 4] Center 38 (8~68) winsize 61
8256 20:15:24.946205 [CA 5] Center 37 (8~66) winsize 59
8257 20:15:24.946325
8258 20:15:24.949474 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8259 20:15:24.949596
8260 20:15:24.956200 [CATrainingPosCal] consider 1 rank data
8261 20:15:24.956321 u2DelayCellTimex100 = 275/100 ps
8262 20:15:24.962608 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8263 20:15:24.965889 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8264 20:15:24.969071 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8265 20:15:24.972153 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8266 20:15:24.975680 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8267 20:15:24.979008 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8268 20:15:24.979129
8269 20:15:24.982567 CA PerBit enable=1, Macro0, CA PI delay=37
8270 20:15:24.982686
8271 20:15:24.985580 [CBTSetCACLKResult] CA Dly = 37
8272 20:15:24.989036 CS Dly: 8 (0~39)
8273 20:15:24.992443 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8274 20:15:24.995264 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8275 20:15:24.995415 ==
8276 20:15:24.998446 Dram Type= 6, Freq= 0, CH_1, rank 1
8277 20:15:25.005591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 20:15:25.005675 ==
8279 20:15:25.008504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 20:15:25.015161 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 20:15:25.018793 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 20:15:25.025137 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 20:15:25.032849 [CA 0] Center 42 (12~72) winsize 61
8284 20:15:25.036085 [CA 1] Center 42 (12~72) winsize 61
8285 20:15:25.039326 [CA 2] Center 38 (8~68) winsize 61
8286 20:15:25.043085 [CA 3] Center 37 (7~67) winsize 61
8287 20:15:25.045824 [CA 4] Center 37 (8~67) winsize 60
8288 20:15:25.048997 [CA 5] Center 37 (7~67) winsize 61
8289 20:15:25.049078
8290 20:15:25.052623 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 20:15:25.052704
8292 20:15:25.059237 [CATrainingPosCal] consider 2 rank data
8293 20:15:25.059319 u2DelayCellTimex100 = 275/100 ps
8294 20:15:25.065565 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8295 20:15:25.069090 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8296 20:15:25.072340 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8297 20:15:25.075307 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 20:15:25.078652 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8299 20:15:25.081957 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8300 20:15:25.082038
8301 20:15:25.085316 CA PerBit enable=1, Macro0, CA PI delay=37
8302 20:15:25.085397
8303 20:15:25.088459 [CBTSetCACLKResult] CA Dly = 37
8304 20:15:25.092142 CS Dly: 9 (0~42)
8305 20:15:25.095528 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 20:15:25.098772 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 20:15:25.098853
8308 20:15:25.102209 ----->DramcWriteLeveling(PI) begin...
8309 20:15:25.102290 ==
8310 20:15:25.104803 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 20:15:25.111671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 20:15:25.111752 ==
8313 20:15:25.114871 Write leveling (Byte 0): 25 => 25
8314 20:15:25.118690 Write leveling (Byte 1): 28 => 28
8315 20:15:25.121282 DramcWriteLeveling(PI) end<-----
8316 20:15:25.121362
8317 20:15:25.121426 ==
8318 20:15:25.124617 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 20:15:25.127826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 20:15:25.127906 ==
8321 20:15:25.131160 [Gating] SW mode calibration
8322 20:15:25.137749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8323 20:15:25.144284 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8324 20:15:25.147658 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 20:15:25.151051 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 20:15:25.157603 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 20:15:25.161039 1 4 12 | B1->B0 | 2626 3434 | 1 0 | (0 0) (0 0)
8328 20:15:25.164452 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 20:15:25.171275 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 20:15:25.174192 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 20:15:25.177368 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 20:15:25.184132 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 20:15:25.187374 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 20:15:25.190520 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8335 20:15:25.197422 1 5 12 | B1->B0 | 3030 2525 | 1 1 | (1 0) (1 0)
8336 20:15:25.200396 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8337 20:15:25.203867 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 20:15:25.210714 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 20:15:25.214232 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 20:15:25.216842 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 20:15:25.224420 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 20:15:25.227052 1 6 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
8343 20:15:25.229879 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8344 20:15:25.236925 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 20:15:25.240038 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 20:15:25.243118 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 20:15:25.249637 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 20:15:25.253013 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 20:15:25.256640 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 20:15:25.263022 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8351 20:15:25.266175 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8352 20:15:25.269444 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 20:15:25.276674 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 20:15:25.279449 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 20:15:25.282741 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 20:15:25.289350 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 20:15:25.292512 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 20:15:25.296477 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 20:15:25.302537 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 20:15:25.305424 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 20:15:25.309155 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 20:15:25.315298 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 20:15:25.318612 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 20:15:25.321807 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 20:15:25.328444 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 20:15:25.331786 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 20:15:25.335044 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 20:15:25.341728 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8369 20:15:25.345426 Total UI for P1: 0, mck2ui 16
8370 20:15:25.348088 best dqsien dly found for B0: ( 1, 9, 12)
8371 20:15:25.351561 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 20:15:25.354887 Total UI for P1: 0, mck2ui 16
8373 20:15:25.358349 best dqsien dly found for B1: ( 1, 9, 14)
8374 20:15:25.361447 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8375 20:15:25.365614 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8376 20:15:25.365695
8377 20:15:25.368267 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8378 20:15:25.371325 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8379 20:15:25.374661 [Gating] SW calibration Done
8380 20:15:25.374741 ==
8381 20:15:25.378275 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 20:15:25.384622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 20:15:25.384702 ==
8384 20:15:25.384766 RX Vref Scan: 0
8385 20:15:25.384825
8386 20:15:25.388084 RX Vref 0 -> 0, step: 1
8387 20:15:25.388164
8388 20:15:25.390924 RX Delay 0 -> 252, step: 8
8389 20:15:25.394657 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8390 20:15:25.397658 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 20:15:25.400974 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8392 20:15:25.407876 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 20:15:25.410775 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 20:15:25.414342 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8395 20:15:25.417536 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8396 20:15:25.420893 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8397 20:15:25.428294 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8398 20:15:25.431056 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8399 20:15:25.433873 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 20:15:25.437288 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8401 20:15:25.440626 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 20:15:25.446870 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8403 20:15:25.450398 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 20:15:25.453576 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8405 20:15:25.453657 ==
8406 20:15:25.457342 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 20:15:25.460108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 20:15:25.463454 ==
8409 20:15:25.463535 DQS Delay:
8410 20:15:25.463600 DQS0 = 0, DQS1 = 0
8411 20:15:25.467309 DQM Delay:
8412 20:15:25.467385 DQM0 = 134, DQM1 = 131
8413 20:15:25.470059 DQ Delay:
8414 20:15:25.473265 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8415 20:15:25.476610 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8416 20:15:25.480262 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8417 20:15:25.483182 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8418 20:15:25.483265
8419 20:15:25.483332
8420 20:15:25.483405 ==
8421 20:15:25.486835 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 20:15:25.492868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 20:15:25.492951 ==
8424 20:15:25.493015
8425 20:15:25.493075
8426 20:15:25.493133 TX Vref Scan disable
8427 20:15:25.496728 == TX Byte 0 ==
8428 20:15:25.499542 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 20:15:25.503033 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 20:15:25.506156 == TX Byte 1 ==
8431 20:15:25.509488 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8432 20:15:25.512666 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8433 20:15:25.516107 ==
8434 20:15:25.519393 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 20:15:25.523300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 20:15:25.523405 ==
8437 20:15:25.534837
8438 20:15:25.539199 TX Vref early break, caculate TX vref
8439 20:15:25.541690 TX Vref=16, minBit 8, minWin=22, winSum=375
8440 20:15:25.544871 TX Vref=18, minBit 8, minWin=22, winSum=377
8441 20:15:25.547974 TX Vref=20, minBit 9, minWin=23, winSum=390
8442 20:15:25.551372 TX Vref=22, minBit 8, minWin=23, winSum=400
8443 20:15:25.554728 TX Vref=24, minBit 9, minWin=24, winSum=405
8444 20:15:25.560949 TX Vref=26, minBit 3, minWin=25, winSum=416
8445 20:15:25.564348 TX Vref=28, minBit 0, minWin=26, winSum=423
8446 20:15:25.568024 TX Vref=30, minBit 0, minWin=25, winSum=416
8447 20:15:25.571126 TX Vref=32, minBit 0, minWin=24, winSum=410
8448 20:15:25.574211 TX Vref=34, minBit 9, minWin=23, winSum=395
8449 20:15:25.580740 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8450 20:15:25.580823
8451 20:15:25.583948 Final TX Range 0 Vref 28
8452 20:15:25.584030
8453 20:15:25.584094 ==
8454 20:15:25.587202 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 20:15:25.590648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 20:15:25.590730 ==
8457 20:15:25.590794
8458 20:15:25.593913
8459 20:15:25.593993 TX Vref Scan disable
8460 20:15:25.600694 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8461 20:15:25.600775 == TX Byte 0 ==
8462 20:15:25.603921 u2DelayCellOfst[0]=14 cells (4 PI)
8463 20:15:25.607335 u2DelayCellOfst[1]=10 cells (3 PI)
8464 20:15:25.610529 u2DelayCellOfst[2]=0 cells (0 PI)
8465 20:15:25.613846 u2DelayCellOfst[3]=7 cells (2 PI)
8466 20:15:25.617573 u2DelayCellOfst[4]=7 cells (2 PI)
8467 20:15:25.620641 u2DelayCellOfst[5]=17 cells (5 PI)
8468 20:15:25.623824 u2DelayCellOfst[6]=14 cells (4 PI)
8469 20:15:25.627197 u2DelayCellOfst[7]=3 cells (1 PI)
8470 20:15:25.630281 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8471 20:15:25.633401 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8472 20:15:25.636801 == TX Byte 1 ==
8473 20:15:25.640653 u2DelayCellOfst[8]=0 cells (0 PI)
8474 20:15:25.643534 u2DelayCellOfst[9]=3 cells (1 PI)
8475 20:15:25.647682 u2DelayCellOfst[10]=14 cells (4 PI)
8476 20:15:25.647802 u2DelayCellOfst[11]=3 cells (1 PI)
8477 20:15:25.650333 u2DelayCellOfst[12]=14 cells (4 PI)
8478 20:15:25.653734 u2DelayCellOfst[13]=14 cells (4 PI)
8479 20:15:25.656442 u2DelayCellOfst[14]=21 cells (6 PI)
8480 20:15:25.660146 u2DelayCellOfst[15]=17 cells (5 PI)
8481 20:15:25.666716 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8482 20:15:25.670025 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8483 20:15:25.670145 DramC Write-DBI on
8484 20:15:25.672925 ==
8485 20:15:25.676287 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 20:15:25.679986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 20:15:25.680069 ==
8488 20:15:25.680134
8489 20:15:25.680194
8490 20:15:25.682896 TX Vref Scan disable
8491 20:15:25.682977 == TX Byte 0 ==
8492 20:15:25.689515 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8493 20:15:25.689596 == TX Byte 1 ==
8494 20:15:25.693314 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8495 20:15:25.696293 DramC Write-DBI off
8496 20:15:25.696374
8497 20:15:25.696438 [DATLAT]
8498 20:15:25.699537 Freq=1600, CH1 RK0
8499 20:15:25.699666
8500 20:15:25.699730 DATLAT Default: 0xf
8501 20:15:25.702646 0, 0xFFFF, sum = 0
8502 20:15:25.702728 1, 0xFFFF, sum = 0
8503 20:15:25.706170 2, 0xFFFF, sum = 0
8504 20:15:25.706252 3, 0xFFFF, sum = 0
8505 20:15:25.709531 4, 0xFFFF, sum = 0
8506 20:15:25.712426 5, 0xFFFF, sum = 0
8507 20:15:25.712509 6, 0xFFFF, sum = 0
8508 20:15:25.715732 7, 0xFFFF, sum = 0
8509 20:15:25.715846 8, 0xFFFF, sum = 0
8510 20:15:25.720235 9, 0xFFFF, sum = 0
8511 20:15:25.720318 10, 0xFFFF, sum = 0
8512 20:15:25.722534 11, 0xFFFF, sum = 0
8513 20:15:25.722617 12, 0xFFFF, sum = 0
8514 20:15:25.725527 13, 0xFFFF, sum = 0
8515 20:15:25.725649 14, 0x0, sum = 1
8516 20:15:25.729209 15, 0x0, sum = 2
8517 20:15:25.729332 16, 0x0, sum = 3
8518 20:15:25.732278 17, 0x0, sum = 4
8519 20:15:25.732400 best_step = 15
8520 20:15:25.732511
8521 20:15:25.732618 ==
8522 20:15:25.735495 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 20:15:25.742233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 20:15:25.742356 ==
8525 20:15:25.742471 RX Vref Scan: 1
8526 20:15:25.742581
8527 20:15:25.746101 Set Vref Range= 24 -> 127
8528 20:15:25.746220
8529 20:15:25.748731 RX Vref 24 -> 127, step: 1
8530 20:15:25.748852
8531 20:15:25.748962 RX Delay 19 -> 252, step: 4
8532 20:15:25.749070
8533 20:15:25.752263 Set Vref, RX VrefLevel [Byte0]: 24
8534 20:15:25.755296 [Byte1]: 24
8535 20:15:25.759608
8536 20:15:25.759730 Set Vref, RX VrefLevel [Byte0]: 25
8537 20:15:25.762693 [Byte1]: 25
8538 20:15:25.766750
8539 20:15:25.766870 Set Vref, RX VrefLevel [Byte0]: 26
8540 20:15:25.770355 [Byte1]: 26
8541 20:15:25.774375
8542 20:15:25.774497 Set Vref, RX VrefLevel [Byte0]: 27
8543 20:15:25.778024 [Byte1]: 27
8544 20:15:25.781910
8545 20:15:25.782031 Set Vref, RX VrefLevel [Byte0]: 28
8546 20:15:25.785216 [Byte1]: 28
8547 20:15:25.789764
8548 20:15:25.789885 Set Vref, RX VrefLevel [Byte0]: 29
8549 20:15:25.792720 [Byte1]: 29
8550 20:15:25.797241
8551 20:15:25.797322 Set Vref, RX VrefLevel [Byte0]: 30
8552 20:15:25.800382 [Byte1]: 30
8553 20:15:25.804582
8554 20:15:25.804705 Set Vref, RX VrefLevel [Byte0]: 31
8555 20:15:25.808136 [Byte1]: 31
8556 20:15:25.812290
8557 20:15:25.812411 Set Vref, RX VrefLevel [Byte0]: 32
8558 20:15:25.816297 [Byte1]: 32
8559 20:15:25.819902
8560 20:15:25.820023 Set Vref, RX VrefLevel [Byte0]: 33
8561 20:15:25.823116 [Byte1]: 33
8562 20:15:25.827661
8563 20:15:25.827782 Set Vref, RX VrefLevel [Byte0]: 34
8564 20:15:25.830672 [Byte1]: 34
8565 20:15:25.834973
8566 20:15:25.835095 Set Vref, RX VrefLevel [Byte0]: 35
8567 20:15:25.838508 [Byte1]: 35
8568 20:15:25.842864
8569 20:15:25.842987 Set Vref, RX VrefLevel [Byte0]: 36
8570 20:15:25.845882 [Byte1]: 36
8571 20:15:25.850490
8572 20:15:25.850609 Set Vref, RX VrefLevel [Byte0]: 37
8573 20:15:25.853516 [Byte1]: 37
8574 20:15:25.857995
8575 20:15:25.858117 Set Vref, RX VrefLevel [Byte0]: 38
8576 20:15:25.861054 [Byte1]: 38
8577 20:15:25.865514
8578 20:15:25.865636 Set Vref, RX VrefLevel [Byte0]: 39
8579 20:15:25.868757 [Byte1]: 39
8580 20:15:25.873083
8581 20:15:25.873204 Set Vref, RX VrefLevel [Byte0]: 40
8582 20:15:25.876188 [Byte1]: 40
8583 20:15:25.880541
8584 20:15:25.880661 Set Vref, RX VrefLevel [Byte0]: 41
8585 20:15:25.884228 [Byte1]: 41
8586 20:15:25.888634
8587 20:15:25.888756 Set Vref, RX VrefLevel [Byte0]: 42
8588 20:15:25.891457 [Byte1]: 42
8589 20:15:25.895578
8590 20:15:25.895742 Set Vref, RX VrefLevel [Byte0]: 43
8591 20:15:25.899255 [Byte1]: 43
8592 20:15:25.903730
8593 20:15:25.903850 Set Vref, RX VrefLevel [Byte0]: 44
8594 20:15:25.906540 [Byte1]: 44
8595 20:15:25.910998
8596 20:15:25.911119 Set Vref, RX VrefLevel [Byte0]: 45
8597 20:15:25.914129 [Byte1]: 45
8598 20:15:25.918297
8599 20:15:25.918420 Set Vref, RX VrefLevel [Byte0]: 46
8600 20:15:25.921548 [Byte1]: 46
8601 20:15:25.926501
8602 20:15:25.926623 Set Vref, RX VrefLevel [Byte0]: 47
8603 20:15:25.929280 [Byte1]: 47
8604 20:15:25.933552
8605 20:15:25.933673 Set Vref, RX VrefLevel [Byte0]: 48
8606 20:15:25.936827 [Byte1]: 48
8607 20:15:25.941119
8608 20:15:25.941241 Set Vref, RX VrefLevel [Byte0]: 49
8609 20:15:25.944699 [Byte1]: 49
8610 20:15:25.948732
8611 20:15:25.948853 Set Vref, RX VrefLevel [Byte0]: 50
8612 20:15:25.952125 [Byte1]: 50
8613 20:15:25.956585
8614 20:15:25.956706 Set Vref, RX VrefLevel [Byte0]: 51
8615 20:15:25.959375 [Byte1]: 51
8616 20:15:25.963761
8617 20:15:25.963882 Set Vref, RX VrefLevel [Byte0]: 52
8618 20:15:25.966957 [Byte1]: 52
8619 20:15:25.971606
8620 20:15:25.971727 Set Vref, RX VrefLevel [Byte0]: 53
8621 20:15:25.974886 [Byte1]: 53
8622 20:15:25.979101
8623 20:15:25.979222 Set Vref, RX VrefLevel [Byte0]: 54
8624 20:15:25.982545 [Byte1]: 54
8625 20:15:25.986838
8626 20:15:25.986959 Set Vref, RX VrefLevel [Byte0]: 55
8627 20:15:25.990057 [Byte1]: 55
8628 20:15:25.994154
8629 20:15:25.994276 Set Vref, RX VrefLevel [Byte0]: 56
8630 20:15:25.997386 [Byte1]: 56
8631 20:15:26.001491
8632 20:15:26.001610 Set Vref, RX VrefLevel [Byte0]: 57
8633 20:15:26.005611 [Byte1]: 57
8634 20:15:26.009613
8635 20:15:26.009733 Set Vref, RX VrefLevel [Byte0]: 58
8636 20:15:26.012339 [Byte1]: 58
8637 20:15:26.016924
8638 20:15:26.017046 Set Vref, RX VrefLevel [Byte0]: 59
8639 20:15:26.020040 [Byte1]: 59
8640 20:15:26.024432
8641 20:15:26.024553 Set Vref, RX VrefLevel [Byte0]: 60
8642 20:15:26.027576 [Byte1]: 60
8643 20:15:26.032539
8644 20:15:26.032658 Set Vref, RX VrefLevel [Byte0]: 61
8645 20:15:26.035054 [Byte1]: 61
8646 20:15:26.039601
8647 20:15:26.039722 Set Vref, RX VrefLevel [Byte0]: 62
8648 20:15:26.043332 [Byte1]: 62
8649 20:15:26.046988
8650 20:15:26.047109 Set Vref, RX VrefLevel [Byte0]: 63
8651 20:15:26.050320 [Byte1]: 63
8652 20:15:26.054549
8653 20:15:26.054677 Set Vref, RX VrefLevel [Byte0]: 64
8654 20:15:26.057888 [Byte1]: 64
8655 20:15:26.062287
8656 20:15:26.062409 Set Vref, RX VrefLevel [Byte0]: 65
8657 20:15:26.065533 [Byte1]: 65
8658 20:15:26.069869
8659 20:15:26.069991 Set Vref, RX VrefLevel [Byte0]: 66
8660 20:15:26.073281 [Byte1]: 66
8661 20:15:26.077629
8662 20:15:26.077752 Set Vref, RX VrefLevel [Byte0]: 67
8663 20:15:26.080732 [Byte1]: 67
8664 20:15:26.085906
8665 20:15:26.086027 Set Vref, RX VrefLevel [Byte0]: 68
8666 20:15:26.088207 [Byte1]: 68
8667 20:15:26.092516
8668 20:15:26.092639 Set Vref, RX VrefLevel [Byte0]: 69
8669 20:15:26.096192 [Byte1]: 69
8670 20:15:26.100078
8671 20:15:26.100199 Set Vref, RX VrefLevel [Byte0]: 70
8672 20:15:26.103596 [Byte1]: 70
8673 20:15:26.107979
8674 20:15:26.108100 Final RX Vref Byte 0 = 56 to rank0
8675 20:15:26.111216 Final RX Vref Byte 1 = 62 to rank0
8676 20:15:26.114451 Final RX Vref Byte 0 = 56 to rank1
8677 20:15:26.117579 Final RX Vref Byte 1 = 62 to rank1==
8678 20:15:26.121398 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 20:15:26.127624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 20:15:26.127732 ==
8681 20:15:26.127824 DQS Delay:
8682 20:15:26.130833 DQS0 = 0, DQS1 = 0
8683 20:15:26.130939 DQM Delay:
8684 20:15:26.131035 DQM0 = 131, DQM1 = 130
8685 20:15:26.134543 DQ Delay:
8686 20:15:26.137207 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =130
8687 20:15:26.140682 DQ4 =126, DQ5 =140, DQ6 =144, DQ7 =126
8688 20:15:26.144363 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8689 20:15:26.147070 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8690 20:15:26.147152
8691 20:15:26.147217
8692 20:15:26.147276
8693 20:15:26.150689 [DramC_TX_OE_Calibration] TA2
8694 20:15:26.154446 Original DQ_B0 (3 6) =30, OEN = 27
8695 20:15:26.156949 Original DQ_B1 (3 6) =30, OEN = 27
8696 20:15:26.160181 24, 0x0, End_B0=24 End_B1=24
8697 20:15:26.163705 25, 0x0, End_B0=25 End_B1=25
8698 20:15:26.163788 26, 0x0, End_B0=26 End_B1=26
8699 20:15:26.166770 27, 0x0, End_B0=27 End_B1=27
8700 20:15:26.170329 28, 0x0, End_B0=28 End_B1=28
8701 20:15:26.173544 29, 0x0, End_B0=29 End_B1=29
8702 20:15:26.173627 30, 0x0, End_B0=30 End_B1=30
8703 20:15:26.176588 31, 0x4141, End_B0=30 End_B1=30
8704 20:15:26.180327 Byte0 end_step=30 best_step=27
8705 20:15:26.183313 Byte1 end_step=30 best_step=27
8706 20:15:26.186817 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 20:15:26.189907 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 20:15:26.190014
8709 20:15:26.190105
8710 20:15:26.196292 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8711 20:15:26.199694 CH1 RK0: MR19=303, MR18=913
8712 20:15:26.206349 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8713 20:15:26.206430
8714 20:15:26.210129 ----->DramcWriteLeveling(PI) begin...
8715 20:15:26.210212 ==
8716 20:15:26.212999 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 20:15:26.216036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 20:15:26.216118 ==
8719 20:15:26.219805 Write leveling (Byte 0): 22 => 22
8720 20:15:26.222621 Write leveling (Byte 1): 27 => 27
8721 20:15:26.226220 DramcWriteLeveling(PI) end<-----
8722 20:15:26.226302
8723 20:15:26.226366 ==
8724 20:15:26.229764 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 20:15:26.232489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 20:15:26.236133 ==
8727 20:15:26.236242 [Gating] SW mode calibration
8728 20:15:26.245608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 20:15:26.249649 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 20:15:26.252658 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 20:15:26.259047 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 20:15:26.262650 1 4 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8733 20:15:26.265929 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8734 20:15:26.272105 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 20:15:26.275647 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 20:15:26.278835 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 20:15:26.285523 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 20:15:26.288949 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 20:15:26.291761 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 20:15:26.298830 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8741 20:15:26.301745 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8742 20:15:26.305231 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8743 20:15:26.312022 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 20:15:26.314982 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 20:15:26.318225 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 20:15:26.325003 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 20:15:26.328407 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8748 20:15:26.331625 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8749 20:15:26.338098 1 6 12 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8750 20:15:26.341524 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 20:15:26.344649 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 20:15:26.351279 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 20:15:26.355057 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 20:15:26.358111 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 20:15:26.364395 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 20:15:26.367688 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8757 20:15:26.371335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8758 20:15:26.377842 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8759 20:15:26.380723 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 20:15:26.384050 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 20:15:26.390742 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 20:15:26.394099 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 20:15:26.397639 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 20:15:26.403759 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 20:15:26.407431 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 20:15:26.410351 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 20:15:26.417348 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 20:15:26.420670 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 20:15:26.427274 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 20:15:26.430236 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 20:15:26.433545 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 20:15:26.437134 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8773 20:15:26.443869 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8774 20:15:26.446735 Total UI for P1: 0, mck2ui 16
8775 20:15:26.450386 best dqsien dly found for B0: ( 1, 9, 8)
8776 20:15:26.453524 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 20:15:26.456785 Total UI for P1: 0, mck2ui 16
8778 20:15:26.459817 best dqsien dly found for B1: ( 1, 9, 10)
8779 20:15:26.463046 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8780 20:15:26.466416 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8781 20:15:26.466498
8782 20:15:26.469813 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8783 20:15:26.476658 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8784 20:15:26.476740 [Gating] SW calibration Done
8785 20:15:26.476821 ==
8786 20:15:26.479625 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 20:15:26.487248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 20:15:26.487345 ==
8789 20:15:26.487434 RX Vref Scan: 0
8790 20:15:26.487495
8791 20:15:26.489480 RX Vref 0 -> 0, step: 1
8792 20:15:26.489562
8793 20:15:26.493030 RX Delay 0 -> 252, step: 8
8794 20:15:26.496077 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8795 20:15:26.499259 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8796 20:15:26.502703 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8797 20:15:26.509465 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8798 20:15:26.512428 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8799 20:15:26.515755 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8800 20:15:26.519279 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8801 20:15:26.522659 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8802 20:15:26.528930 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8803 20:15:26.532197 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8804 20:15:26.535520 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8805 20:15:26.539216 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8806 20:15:26.542248 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8807 20:15:26.549454 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8808 20:15:26.552285 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8809 20:15:26.555530 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8810 20:15:26.555612 ==
8811 20:15:26.558692 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 20:15:26.565444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 20:15:26.565526 ==
8814 20:15:26.565591 DQS Delay:
8815 20:15:26.565652 DQS0 = 0, DQS1 = 0
8816 20:15:26.568621 DQM Delay:
8817 20:15:26.568702 DQM0 = 136, DQM1 = 130
8818 20:15:26.572401 DQ Delay:
8819 20:15:26.575226 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8820 20:15:26.578490 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8821 20:15:26.581506 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8822 20:15:26.584757 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8823 20:15:26.584838
8824 20:15:26.584902
8825 20:15:26.584961 ==
8826 20:15:26.588757 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 20:15:26.594980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 20:15:26.595063 ==
8829 20:15:26.595152
8830 20:15:26.595214
8831 20:15:26.595272 TX Vref Scan disable
8832 20:15:26.598061 == TX Byte 0 ==
8833 20:15:26.601234 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8834 20:15:26.608175 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8835 20:15:26.608331 == TX Byte 1 ==
8836 20:15:26.611599 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8837 20:15:26.618047 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8838 20:15:26.618136 ==
8839 20:15:26.620837 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 20:15:26.624626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 20:15:26.624713 ==
8842 20:15:26.638492
8843 20:15:26.641560 TX Vref early break, caculate TX vref
8844 20:15:26.645049 TX Vref=16, minBit 9, minWin=21, winSum=376
8845 20:15:26.649360 TX Vref=18, minBit 9, minWin=22, winSum=385
8846 20:15:26.651744 TX Vref=20, minBit 9, minWin=22, winSum=391
8847 20:15:26.655270 TX Vref=22, minBit 9, minWin=23, winSum=403
8848 20:15:26.657869 TX Vref=24, minBit 9, minWin=23, winSum=408
8849 20:15:26.664742 TX Vref=26, minBit 9, minWin=24, winSum=417
8850 20:15:26.667650 TX Vref=28, minBit 9, minWin=25, winSum=420
8851 20:15:26.671133 TX Vref=30, minBit 9, minWin=24, winSum=418
8852 20:15:26.675185 TX Vref=32, minBit 8, minWin=24, winSum=412
8853 20:15:26.677740 TX Vref=34, minBit 0, minWin=24, winSum=401
8854 20:15:26.684245 TX Vref=36, minBit 0, minWin=23, winSum=395
8855 20:15:26.687678 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8856 20:15:26.687760
8857 20:15:26.690916 Final TX Range 0 Vref 28
8858 20:15:26.690998
8859 20:15:26.691063 ==
8860 20:15:26.694200 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 20:15:26.697503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 20:15:26.700677 ==
8863 20:15:26.700758
8864 20:15:26.700822
8865 20:15:26.700882 TX Vref Scan disable
8866 20:15:26.708117 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8867 20:15:26.708198 == TX Byte 0 ==
8868 20:15:26.710854 u2DelayCellOfst[0]=14 cells (4 PI)
8869 20:15:26.714235 u2DelayCellOfst[1]=10 cells (3 PI)
8870 20:15:26.717289 u2DelayCellOfst[2]=0 cells (0 PI)
8871 20:15:26.720843 u2DelayCellOfst[3]=7 cells (2 PI)
8872 20:15:26.724240 u2DelayCellOfst[4]=10 cells (3 PI)
8873 20:15:26.727403 u2DelayCellOfst[5]=14 cells (4 PI)
8874 20:15:26.730469 u2DelayCellOfst[6]=14 cells (4 PI)
8875 20:15:26.734433 u2DelayCellOfst[7]=7 cells (2 PI)
8876 20:15:26.737335 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8877 20:15:26.740567 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8878 20:15:26.743670 == TX Byte 1 ==
8879 20:15:26.746798 u2DelayCellOfst[8]=0 cells (0 PI)
8880 20:15:26.750106 u2DelayCellOfst[9]=3 cells (1 PI)
8881 20:15:26.753622 u2DelayCellOfst[10]=10 cells (3 PI)
8882 20:15:26.757500 u2DelayCellOfst[11]=3 cells (1 PI)
8883 20:15:26.760022 u2DelayCellOfst[12]=14 cells (4 PI)
8884 20:15:26.763327 u2DelayCellOfst[13]=14 cells (4 PI)
8885 20:15:26.766743 u2DelayCellOfst[14]=17 cells (5 PI)
8886 20:15:26.769910 u2DelayCellOfst[15]=17 cells (5 PI)
8887 20:15:26.773586 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8888 20:15:26.776656 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8889 20:15:26.780101 DramC Write-DBI on
8890 20:15:26.780182 ==
8891 20:15:26.783186 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 20:15:26.786441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 20:15:26.786523 ==
8894 20:15:26.786588
8895 20:15:26.786647
8896 20:15:26.789798 TX Vref Scan disable
8897 20:15:26.793216 == TX Byte 0 ==
8898 20:15:26.796318 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8899 20:15:26.796400 == TX Byte 1 ==
8900 20:15:26.803287 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8901 20:15:26.803379 DramC Write-DBI off
8902 20:15:26.803459
8903 20:15:26.803525 [DATLAT]
8904 20:15:26.806249 Freq=1600, CH1 RK1
8905 20:15:26.806330
8906 20:15:26.809787 DATLAT Default: 0xf
8907 20:15:26.809868 0, 0xFFFF, sum = 0
8908 20:15:26.812769 1, 0xFFFF, sum = 0
8909 20:15:26.812857 2, 0xFFFF, sum = 0
8910 20:15:26.816185 3, 0xFFFF, sum = 0
8911 20:15:26.816294 4, 0xFFFF, sum = 0
8912 20:15:26.819602 5, 0xFFFF, sum = 0
8913 20:15:26.819684 6, 0xFFFF, sum = 0
8914 20:15:26.822644 7, 0xFFFF, sum = 0
8915 20:15:26.822726 8, 0xFFFF, sum = 0
8916 20:15:26.825908 9, 0xFFFF, sum = 0
8917 20:15:26.825992 10, 0xFFFF, sum = 0
8918 20:15:26.829550 11, 0xFFFF, sum = 0
8919 20:15:26.829639 12, 0xFFFF, sum = 0
8920 20:15:26.832364 13, 0xFFFF, sum = 0
8921 20:15:26.832446 14, 0x0, sum = 1
8922 20:15:26.835798 15, 0x0, sum = 2
8923 20:15:26.835882 16, 0x0, sum = 3
8924 20:15:26.839667 17, 0x0, sum = 4
8925 20:15:26.839749 best_step = 15
8926 20:15:26.839813
8927 20:15:26.839872 ==
8928 20:15:26.842887 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 20:15:26.849417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 20:15:26.849499 ==
8931 20:15:26.849564 RX Vref Scan: 0
8932 20:15:26.849622
8933 20:15:26.852652 RX Vref 0 -> 0, step: 1
8934 20:15:26.852733
8935 20:15:26.856114 RX Delay 19 -> 252, step: 4
8936 20:15:26.858858 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8937 20:15:26.862062 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8938 20:15:26.868642 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8939 20:15:26.871902 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8940 20:15:26.875358 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8941 20:15:26.878570 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8942 20:15:26.881854 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8943 20:15:26.888348 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8944 20:15:26.891648 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8945 20:15:26.895338 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8946 20:15:26.898331 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8947 20:15:26.901884 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8948 20:15:26.908360 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8949 20:15:26.911251 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8950 20:15:26.914667 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8951 20:15:26.918020 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8952 20:15:26.921128 ==
8953 20:15:26.921209 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 20:15:26.927691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 20:15:26.927773 ==
8956 20:15:26.927837 DQS Delay:
8957 20:15:26.931041 DQS0 = 0, DQS1 = 0
8958 20:15:26.931122 DQM Delay:
8959 20:15:26.934524 DQM0 = 133, DQM1 = 128
8960 20:15:26.934605 DQ Delay:
8961 20:15:26.937488 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8962 20:15:26.940918 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8963 20:15:26.944818 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8964 20:15:26.948604 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8965 20:15:26.948685
8966 20:15:26.948755
8967 20:15:26.948814
8968 20:15:26.951330 [DramC_TX_OE_Calibration] TA2
8969 20:15:26.954379 Original DQ_B0 (3 6) =30, OEN = 27
8970 20:15:26.957338 Original DQ_B1 (3 6) =30, OEN = 27
8971 20:15:26.961143 24, 0x0, End_B0=24 End_B1=24
8972 20:15:26.963901 25, 0x0, End_B0=25 End_B1=25
8973 20:15:26.963984 26, 0x0, End_B0=26 End_B1=26
8974 20:15:26.967475 27, 0x0, End_B0=27 End_B1=27
8975 20:15:26.970775 28, 0x0, End_B0=28 End_B1=28
8976 20:15:26.973848 29, 0x0, End_B0=29 End_B1=29
8977 20:15:26.977244 30, 0x0, End_B0=30 End_B1=30
8978 20:15:26.980189 31, 0x4141, End_B0=30 End_B1=30
8979 20:15:26.980272 Byte0 end_step=30 best_step=27
8980 20:15:26.983610 Byte1 end_step=30 best_step=27
8981 20:15:26.986767 Byte0 TX OE(2T, 0.5T) = (3, 3)
8982 20:15:26.990186 Byte1 TX OE(2T, 0.5T) = (3, 3)
8983 20:15:26.990267
8984 20:15:26.990331
8985 20:15:26.996857 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8986 20:15:26.999969 CH1 RK1: MR19=303, MR18=D1B
8987 20:15:27.006492 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8988 20:15:27.009889 [RxdqsGatingPostProcess] freq 1600
8989 20:15:27.017070 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8990 20:15:27.020267 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 20:15:27.020349 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 20:15:27.023411 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 20:15:27.026740 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 20:15:27.029844 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 20:15:27.033277 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 20:15:27.036827 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 20:15:27.039816 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 20:15:27.042989 Pre-setting of DQS Precalculation
8999 20:15:27.049455 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9000 20:15:27.056093 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9001 20:15:27.062963 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9002 20:15:27.063074
9003 20:15:27.063166
9004 20:15:27.066142 [Calibration Summary] 3200 Mbps
9005 20:15:27.066224 CH 0, Rank 0
9006 20:15:27.069697 SW Impedance : PASS
9007 20:15:27.073179 DUTY Scan : NO K
9008 20:15:27.073261 ZQ Calibration : PASS
9009 20:15:27.075889 Jitter Meter : NO K
9010 20:15:27.079084 CBT Training : PASS
9011 20:15:27.079191 Write leveling : PASS
9012 20:15:27.082651 RX DQS gating : PASS
9013 20:15:27.085842 RX DQ/DQS(RDDQC) : PASS
9014 20:15:27.085923 TX DQ/DQS : PASS
9015 20:15:27.088852 RX DATLAT : PASS
9016 20:15:27.092144 RX DQ/DQS(Engine): PASS
9017 20:15:27.092225 TX OE : PASS
9018 20:15:27.092290 All Pass.
9019 20:15:27.095740
9020 20:15:27.095821 CH 0, Rank 1
9021 20:15:27.098699 SW Impedance : PASS
9022 20:15:27.098781 DUTY Scan : NO K
9023 20:15:27.102347 ZQ Calibration : PASS
9024 20:15:27.102428 Jitter Meter : NO K
9025 20:15:27.105394 CBT Training : PASS
9026 20:15:27.108752 Write leveling : PASS
9027 20:15:27.108859 RX DQS gating : PASS
9028 20:15:27.112288 RX DQ/DQS(RDDQC) : PASS
9029 20:15:27.115267 TX DQ/DQS : PASS
9030 20:15:27.115400 RX DATLAT : PASS
9031 20:15:27.118723 RX DQ/DQS(Engine): PASS
9032 20:15:27.122019 TX OE : PASS
9033 20:15:27.122103 All Pass.
9034 20:15:27.122168
9035 20:15:27.122227 CH 1, Rank 0
9036 20:15:27.125079 SW Impedance : PASS
9037 20:15:27.128933 DUTY Scan : NO K
9038 20:15:27.129014 ZQ Calibration : PASS
9039 20:15:27.132014 Jitter Meter : NO K
9040 20:15:27.135115 CBT Training : PASS
9041 20:15:27.135222 Write leveling : PASS
9042 20:15:27.138554 RX DQS gating : PASS
9043 20:15:27.141950 RX DQ/DQS(RDDQC) : PASS
9044 20:15:27.142031 TX DQ/DQS : PASS
9045 20:15:27.145251 RX DATLAT : PASS
9046 20:15:27.148575 RX DQ/DQS(Engine): PASS
9047 20:15:27.148656 TX OE : PASS
9048 20:15:27.151432 All Pass.
9049 20:15:27.151513
9050 20:15:27.151577 CH 1, Rank 1
9051 20:15:27.154809 SW Impedance : PASS
9052 20:15:27.154891 DUTY Scan : NO K
9053 20:15:27.158953 ZQ Calibration : PASS
9054 20:15:27.161791 Jitter Meter : NO K
9055 20:15:27.161878 CBT Training : PASS
9056 20:15:27.164925 Write leveling : PASS
9057 20:15:27.168776 RX DQS gating : PASS
9058 20:15:27.168857 RX DQ/DQS(RDDQC) : PASS
9059 20:15:27.171409 TX DQ/DQS : PASS
9060 20:15:27.171523 RX DATLAT : PASS
9061 20:15:27.174756 RX DQ/DQS(Engine): PASS
9062 20:15:27.178614 TX OE : PASS
9063 20:15:27.178696 All Pass.
9064 20:15:27.178760
9065 20:15:27.181798 DramC Write-DBI on
9066 20:15:27.181902 PER_BANK_REFRESH: Hybrid Mode
9067 20:15:27.184647 TX_TRACKING: ON
9068 20:15:27.194348 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9069 20:15:27.200930 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9070 20:15:27.207652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 20:15:27.210853 [FAST_K] Save calibration result to emmc
9072 20:15:27.214547 sync common calibartion params.
9073 20:15:27.217338 sync cbt_mode0:1, 1:1
9074 20:15:27.220788 dram_init: ddr_geometry: 2
9075 20:15:27.220863 dram_init: ddr_geometry: 2
9076 20:15:27.224070 dram_init: ddr_geometry: 2
9077 20:15:27.227337 0:dram_rank_size:100000000
9078 20:15:27.227481 1:dram_rank_size:100000000
9079 20:15:27.233742 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9080 20:15:27.237116 DFS_SHUFFLE_HW_MODE: ON
9081 20:15:27.241011 dramc_set_vcore_voltage set vcore to 725000
9082 20:15:27.243631 Read voltage for 1600, 0
9083 20:15:27.243712 Vio18 = 0
9084 20:15:27.243780 Vcore = 725000
9085 20:15:27.247060 Vdram = 0
9086 20:15:27.247141 Vddq = 0
9087 20:15:27.247205 Vmddr = 0
9088 20:15:27.250277 switch to 3200 Mbps bootup
9089 20:15:27.253896 [DramcRunTimeConfig]
9090 20:15:27.253994 PHYPLL
9091 20:15:27.254091 DPM_CONTROL_AFTERK: ON
9092 20:15:27.257063 PER_BANK_REFRESH: ON
9093 20:15:27.260251 REFRESH_OVERHEAD_REDUCTION: ON
9094 20:15:27.260332 CMD_PICG_NEW_MODE: OFF
9095 20:15:27.263597 XRTWTW_NEW_MODE: ON
9096 20:15:27.266836 XRTRTR_NEW_MODE: ON
9097 20:15:27.266916 TX_TRACKING: ON
9098 20:15:27.271205 RDSEL_TRACKING: OFF
9099 20:15:27.271286 DQS Precalculation for DVFS: ON
9100 20:15:27.273340 RX_TRACKING: OFF
9101 20:15:27.273421 HW_GATING DBG: ON
9102 20:15:27.276592 ZQCS_ENABLE_LP4: ON
9103 20:15:27.279925 RX_PICG_NEW_MODE: ON
9104 20:15:27.280006 TX_PICG_NEW_MODE: ON
9105 20:15:27.283309 ENABLE_RX_DCM_DPHY: ON
9106 20:15:27.286478 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9107 20:15:27.286559 DUMMY_READ_FOR_TRACKING: OFF
9108 20:15:27.290014 !!! SPM_CONTROL_AFTERK: OFF
9109 20:15:27.293015 !!! SPM could not control APHY
9110 20:15:27.296431 IMPEDANCE_TRACKING: ON
9111 20:15:27.296511 TEMP_SENSOR: ON
9112 20:15:27.299613 HW_SAVE_FOR_SR: OFF
9113 20:15:27.302923 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9114 20:15:27.306463 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9115 20:15:27.306544 Read ODT Tracking: ON
9116 20:15:27.309637 Refresh Rate DeBounce: ON
9117 20:15:27.312913 DFS_NO_QUEUE_FLUSH: ON
9118 20:15:27.316206 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9119 20:15:27.316287 ENABLE_DFS_RUNTIME_MRW: OFF
9120 20:15:27.320026 DDR_RESERVE_NEW_MODE: ON
9121 20:15:27.322641 MR_CBT_SWITCH_FREQ: ON
9122 20:15:27.322722 =========================
9123 20:15:27.343229 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9124 20:15:27.346096 dram_init: ddr_geometry: 2
9125 20:15:27.364861 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9126 20:15:27.367654 dram_init: dram init end (result: 0)
9127 20:15:27.374135 DRAM-K: Full calibration passed in 24451 msecs
9128 20:15:27.377407 MRC: failed to locate region type 0.
9129 20:15:27.377489 DRAM rank0 size:0x100000000,
9130 20:15:27.381038 DRAM rank1 size=0x100000000
9131 20:15:27.390860 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9132 20:15:27.397203 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9133 20:15:27.407045 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9134 20:15:27.413302 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9135 20:15:27.413384 DRAM rank0 size:0x100000000,
9136 20:15:27.417032 DRAM rank1 size=0x100000000
9137 20:15:27.417113 CBMEM:
9138 20:15:27.420056 IMD: root @ 0xfffff000 254 entries.
9139 20:15:27.423322 IMD: root @ 0xffffec00 62 entries.
9140 20:15:27.429783 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9141 20:15:27.433486 WARNING: RO_VPD is uninitialized or empty.
9142 20:15:27.436521 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9143 20:15:27.444233 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9144 20:15:27.457356 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9145 20:15:27.468462 BS: romstage times (exec / console): total (unknown) / 23979 ms
9146 20:15:27.468545
9147 20:15:27.468609
9148 20:15:27.478782 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9149 20:15:27.481667 ARM64: Exception handlers installed.
9150 20:15:27.484970 ARM64: Testing exception
9151 20:15:27.488453 ARM64: Done test exception
9152 20:15:27.488534 Enumerating buses...
9153 20:15:27.491640 Show all devs... Before device enumeration.
9154 20:15:27.494807 Root Device: enabled 1
9155 20:15:27.498175 CPU_CLUSTER: 0: enabled 1
9156 20:15:27.498256 CPU: 00: enabled 1
9157 20:15:27.501560 Compare with tree...
9158 20:15:27.501640 Root Device: enabled 1
9159 20:15:27.505008 CPU_CLUSTER: 0: enabled 1
9160 20:15:27.508373 CPU: 00: enabled 1
9161 20:15:27.508454 Root Device scanning...
9162 20:15:27.511509 scan_static_bus for Root Device
9163 20:15:27.514540 CPU_CLUSTER: 0 enabled
9164 20:15:27.517754 scan_static_bus for Root Device done
9165 20:15:27.521081 scan_bus: bus Root Device finished in 8 msecs
9166 20:15:27.521188 done
9167 20:15:27.528103 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9168 20:15:27.531333 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9169 20:15:27.537668 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9170 20:15:27.544229 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9171 20:15:27.544311 Allocating resources...
9172 20:15:27.547353 Reading resources...
9173 20:15:27.551050 Root Device read_resources bus 0 link: 0
9174 20:15:27.554042 DRAM rank0 size:0x100000000,
9175 20:15:27.554124 DRAM rank1 size=0x100000000
9176 20:15:27.560666 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9177 20:15:27.560748 CPU: 00 missing read_resources
9178 20:15:27.567642 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9179 20:15:27.570558 Root Device read_resources bus 0 link: 0 done
9180 20:15:27.573863 Done reading resources.
9181 20:15:27.577620 Show resources in subtree (Root Device)...After reading.
9182 20:15:27.580566 Root Device child on link 0 CPU_CLUSTER: 0
9183 20:15:27.583551 CPU_CLUSTER: 0 child on link 0 CPU: 00
9184 20:15:27.593370 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9185 20:15:27.593452 CPU: 00
9186 20:15:27.600241 Root Device assign_resources, bus 0 link: 0
9187 20:15:27.603619 CPU_CLUSTER: 0 missing set_resources
9188 20:15:27.606880 Root Device assign_resources, bus 0 link: 0 done
9189 20:15:27.609998 Done setting resources.
9190 20:15:27.612970 Show resources in subtree (Root Device)...After assigning values.
9191 20:15:27.616336 Root Device child on link 0 CPU_CLUSTER: 0
9192 20:15:27.622959 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 20:15:27.629832 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 20:15:27.633406 CPU: 00
9195 20:15:27.633508 Done allocating resources.
9196 20:15:27.639861 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9197 20:15:27.639943 Enabling resources...
9198 20:15:27.642829 done.
9199 20:15:27.645942 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9200 20:15:27.649621 Initializing devices...
9201 20:15:27.649703 Root Device init
9202 20:15:27.652606 init hardware done!
9203 20:15:27.652688 0x00000018: ctrlr->caps
9204 20:15:27.655926 52.000 MHz: ctrlr->f_max
9205 20:15:27.659813 0.400 MHz: ctrlr->f_min
9206 20:15:27.663075 0x40ff8080: ctrlr->voltages
9207 20:15:27.663158 sclk: 390625
9208 20:15:27.663224 Bus Width = 1
9209 20:15:27.666221 sclk: 390625
9210 20:15:27.666302 Bus Width = 1
9211 20:15:27.669372 Early init status = 3
9212 20:15:27.672594 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9213 20:15:27.676331 in-header: 03 fc 00 00 01 00 00 00
9214 20:15:27.679231 in-data: 00
9215 20:15:27.682837 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9216 20:15:27.687201 in-header: 03 fd 00 00 00 00 00 00
9217 20:15:27.691182 in-data:
9218 20:15:27.694344 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9219 20:15:27.697732 in-header: 03 fc 00 00 01 00 00 00
9220 20:15:27.700513 in-data: 00
9221 20:15:27.703672 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9222 20:15:27.708526 in-header: 03 fd 00 00 00 00 00 00
9223 20:15:27.712064 in-data:
9224 20:15:27.715528 [SSUSB] Setting up USB HOST controller...
9225 20:15:27.718829 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9226 20:15:27.721452 [SSUSB] phy power-on done.
9227 20:15:27.724787 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9228 20:15:27.731324 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9229 20:15:27.735223 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9230 20:15:27.741867 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9231 20:15:27.748060 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9232 20:15:27.754571 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9233 20:15:27.761250 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9234 20:15:27.767831 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9235 20:15:27.770973 SPM: binary array size = 0x9dc
9236 20:15:27.774218 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9237 20:15:27.780722 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9238 20:15:27.787657 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9239 20:15:27.794055 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9240 20:15:27.797197 configure_display: Starting display init
9241 20:15:27.831826 anx7625_power_on_init: Init interface.
9242 20:15:27.835449 anx7625_disable_pd_protocol: Disabled PD feature.
9243 20:15:27.838364 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9244 20:15:27.866495 anx7625_start_dp_work: Secure OCM version=00
9245 20:15:27.869354 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9246 20:15:27.884376 sp_tx_get_edid_block: EDID Block = 1
9247 20:15:27.987009 Extracted contents:
9248 20:15:27.990478 header: 00 ff ff ff ff ff ff 00
9249 20:15:27.993508 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9250 20:15:27.996725 version: 01 04
9251 20:15:27.999859 basic params: 95 1f 11 78 0a
9252 20:15:28.003756 chroma info: 76 90 94 55 54 90 27 21 50 54
9253 20:15:28.006709 established: 00 00 00
9254 20:15:28.013195 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9255 20:15:28.019529 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9256 20:15:28.022808 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9257 20:15:28.029490 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9258 20:15:28.036197 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9259 20:15:28.039637 extensions: 00
9260 20:15:28.039718 checksum: fb
9261 20:15:28.039783
9262 20:15:28.046520 Manufacturer: IVO Model 57d Serial Number 0
9263 20:15:28.046601 Made week 0 of 2020
9264 20:15:28.049857 EDID version: 1.4
9265 20:15:28.049939 Digital display
9266 20:15:28.052681 6 bits per primary color channel
9267 20:15:28.055690 DisplayPort interface
9268 20:15:28.055771 Maximum image size: 31 cm x 17 cm
9269 20:15:28.058963 Gamma: 220%
9270 20:15:28.059044 Check DPMS levels
9271 20:15:28.065748 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9272 20:15:28.069299 First detailed timing is preferred timing
9273 20:15:28.072218 Established timings supported:
9274 20:15:28.072299 Standard timings supported:
9275 20:15:28.075344 Detailed timings
9276 20:15:28.078888 Hex of detail: 383680a07038204018303c0035ae10000019
9277 20:15:28.085327 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9278 20:15:28.088854 0780 0798 07c8 0820 hborder 0
9279 20:15:28.091815 0438 043b 0447 0458 vborder 0
9280 20:15:28.095335 -hsync -vsync
9281 20:15:28.095439 Did detailed timing
9282 20:15:28.101728 Hex of detail: 000000000000000000000000000000000000
9283 20:15:28.105159 Manufacturer-specified data, tag 0
9284 20:15:28.108813 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9285 20:15:28.111407 ASCII string: InfoVision
9286 20:15:28.115222 Hex of detail: 000000fe00523134304e574635205248200a
9287 20:15:28.118102 ASCII string: R140NWF5 RH
9288 20:15:28.118184 Checksum
9289 20:15:28.121890 Checksum: 0xfb (valid)
9290 20:15:28.124990 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9291 20:15:28.127863 DSI data_rate: 832800000 bps
9292 20:15:28.134369 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9293 20:15:28.137747 anx7625_parse_edid: pixelclock(138800).
9294 20:15:28.142132 hactive(1920), hsync(48), hfp(24), hbp(88)
9295 20:15:28.144497 vactive(1080), vsync(12), vfp(3), vbp(17)
9296 20:15:28.147859 anx7625_dsi_config: config dsi.
9297 20:15:28.154734 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9298 20:15:28.168766 anx7625_dsi_config: success to config DSI
9299 20:15:28.172393 anx7625_dp_start: MIPI phy setup OK.
9300 20:15:28.175401 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9301 20:15:28.178890 mtk_ddp_mode_set invalid vrefresh 60
9302 20:15:28.182846 main_disp_path_setup
9303 20:15:28.182926 ovl_layer_smi_id_en
9304 20:15:28.185150 ovl_layer_smi_id_en
9305 20:15:28.185230 ccorr_config
9306 20:15:28.185294 aal_config
9307 20:15:28.188559 gamma_config
9308 20:15:28.188640 postmask_config
9309 20:15:28.192043 dither_config
9310 20:15:28.195019 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9311 20:15:28.202172 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9312 20:15:28.205735 Root Device init finished in 551 msecs
9313 20:15:28.208315 CPU_CLUSTER: 0 init
9314 20:15:28.215066 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9315 20:15:28.221495 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9316 20:15:28.221576 APU_MBOX 0x190000b0 = 0x10001
9317 20:15:28.225013 APU_MBOX 0x190001b0 = 0x10001
9318 20:15:28.228036 APU_MBOX 0x190005b0 = 0x10001
9319 20:15:28.231343 APU_MBOX 0x190006b0 = 0x10001
9320 20:15:28.237843 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9321 20:15:28.247753 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9322 20:15:28.259977 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9323 20:15:28.266748 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9324 20:15:28.278774 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9325 20:15:28.287669 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9326 20:15:28.291107 CPU_CLUSTER: 0 init finished in 81 msecs
9327 20:15:28.294125 Devices initialized
9328 20:15:28.297555 Show all devs... After init.
9329 20:15:28.297637 Root Device: enabled 1
9330 20:15:28.300929 CPU_CLUSTER: 0: enabled 1
9331 20:15:28.304360 CPU: 00: enabled 1
9332 20:15:28.307168 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9333 20:15:28.310618 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9334 20:15:28.314044 ELOG: NV offset 0x57f000 size 0x1000
9335 20:15:28.321723 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9336 20:15:28.327158 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9337 20:15:28.330656 ELOG: Event(17) added with size 13 at 2024-03-03 20:15:28 UTC
9338 20:15:28.337021 out: cmd=0x121: 03 db 21 01 00 00 00 00
9339 20:15:28.340505 in-header: 03 12 00 00 2c 00 00 00
9340 20:15:28.350302 in-data: 4d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 20:15:28.356777 ELOG: Event(A1) added with size 10 at 2024-03-03 20:15:28 UTC
9342 20:15:28.363496 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9343 20:15:28.370046 ELOG: Event(A0) added with size 9 at 2024-03-03 20:15:28 UTC
9344 20:15:28.373678 elog_add_boot_reason: Logged dev mode boot
9345 20:15:28.380406 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9346 20:15:28.380489 Finalize devices...
9347 20:15:28.383306 Devices finalized
9348 20:15:28.387236 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9349 20:15:28.389913 Writing coreboot table at 0xffe64000
9350 20:15:28.393417 0. 000000000010a000-0000000000113fff: RAMSTAGE
9351 20:15:28.400089 1. 0000000040000000-00000000400fffff: RAM
9352 20:15:28.402932 2. 0000000040100000-000000004032afff: RAMSTAGE
9353 20:15:28.406362 3. 000000004032b000-00000000545fffff: RAM
9354 20:15:28.409720 4. 0000000054600000-000000005465ffff: BL31
9355 20:15:28.412885 5. 0000000054660000-00000000ffe63fff: RAM
9356 20:15:28.419714 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9357 20:15:28.423026 7. 0000000100000000-000000023fffffff: RAM
9358 20:15:28.426450 Passing 5 GPIOs to payload:
9359 20:15:28.429485 NAME | PORT | POLARITY | VALUE
9360 20:15:28.435804 EC in RW | 0x000000aa | low | undefined
9361 20:15:28.439629 EC interrupt | 0x00000005 | low | undefined
9362 20:15:28.445539 TPM interrupt | 0x000000ab | high | undefined
9363 20:15:28.449004 SD card detect | 0x00000011 | high | undefined
9364 20:15:28.452204 speaker enable | 0x00000093 | high | undefined
9365 20:15:28.455755 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9366 20:15:28.460020 in-header: 03 f9 00 00 02 00 00 00
9367 20:15:28.463274 in-data: 02 00
9368 20:15:28.466647 ADC[4]: Raw value=901477 ID=7
9369 20:15:28.469792 ADC[3]: Raw value=213546 ID=1
9370 20:15:28.469873 RAM Code: 0x71
9371 20:15:28.473843 ADC[6]: Raw value=75000 ID=0
9372 20:15:28.477498 ADC[5]: Raw value=213546 ID=1
9373 20:15:28.477579 SKU Code: 0x1
9374 20:15:28.483158 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 74a3
9375 20:15:28.483241 coreboot table: 964 bytes.
9376 20:15:28.486952 IMD ROOT 0. 0xfffff000 0x00001000
9377 20:15:28.489804 IMD SMALL 1. 0xffffe000 0x00001000
9378 20:15:28.493368 RO MCACHE 2. 0xffffc000 0x00001104
9379 20:15:28.496216 CONSOLE 3. 0xfff7c000 0x00080000
9380 20:15:28.500035 FMAP 4. 0xfff7b000 0x00000452
9381 20:15:28.502847 TIME STAMP 5. 0xfff7a000 0x00000910
9382 20:15:28.506145 VBOOT WORK 6. 0xfff66000 0x00014000
9383 20:15:28.509687 RAMOOPS 7. 0xffe66000 0x00100000
9384 20:15:28.512815 COREBOOT 8. 0xffe64000 0x00002000
9385 20:15:28.516548 IMD small region:
9386 20:15:28.519307 IMD ROOT 0. 0xffffec00 0x00000400
9387 20:15:28.522604 VPD 1. 0xffffeb80 0x0000006c
9388 20:15:28.526021 MMC STATUS 2. 0xffffeb60 0x00000004
9389 20:15:28.532626 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9390 20:15:28.532708 Probing TPM: done!
9391 20:15:28.539872 Connected to device vid:did:rid of 1ae0:0028:00
9392 20:15:28.546424 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9393 20:15:28.549918 Initialized TPM device CR50 revision 0
9394 20:15:28.552983 Checking cr50 for pending updates
9395 20:15:28.558130 Reading cr50 TPM mode
9396 20:15:28.566674 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9397 20:15:28.573335 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9398 20:15:28.613770 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9399 20:15:28.616881 Checking segment from ROM address 0x40100000
9400 20:15:28.620543 Checking segment from ROM address 0x4010001c
9401 20:15:28.627688 Loading segment from ROM address 0x40100000
9402 20:15:28.627770 code (compression=0)
9403 20:15:28.636759 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9404 20:15:28.643476 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9405 20:15:28.643559 it's not compressed!
9406 20:15:28.650074 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9407 20:15:28.657138 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9408 20:15:28.674171 Loading segment from ROM address 0x4010001c
9409 20:15:28.674253 Entry Point 0x80000000
9410 20:15:28.677103 Loaded segments
9411 20:15:28.680670 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9412 20:15:28.687265 Jumping to boot code at 0x80000000(0xffe64000)
9413 20:15:28.694140 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9414 20:15:28.700269 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9415 20:15:28.708533 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9416 20:15:28.711667 Checking segment from ROM address 0x40100000
9417 20:15:28.715008 Checking segment from ROM address 0x4010001c
9418 20:15:28.721686 Loading segment from ROM address 0x40100000
9419 20:15:28.721800 code (compression=1)
9420 20:15:28.728589 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9421 20:15:28.738237 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9422 20:15:28.738320 using LZMA
9423 20:15:28.746647 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9424 20:15:28.753641 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9425 20:15:28.756569 Loading segment from ROM address 0x4010001c
9426 20:15:28.756650 Entry Point 0x54601000
9427 20:15:28.759873 Loaded segments
9428 20:15:28.763155 NOTICE: MT8192 bl31_setup
9429 20:15:28.771116 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9430 20:15:28.773977 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9431 20:15:28.777289 WARNING: region 0:
9432 20:15:28.780785 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 20:15:28.780867 WARNING: region 1:
9434 20:15:28.786953 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9435 20:15:28.790574 WARNING: region 2:
9436 20:15:28.793806 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9437 20:15:28.796923 WARNING: region 3:
9438 20:15:28.800217 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9439 20:15:28.803810 WARNING: region 4:
9440 20:15:28.810506 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 20:15:28.810630 WARNING: region 5:
9442 20:15:28.813169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 20:15:28.816802 WARNING: region 6:
9444 20:15:28.820370 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 20:15:28.823284 WARNING: region 7:
9446 20:15:28.826604 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 20:15:28.833253 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9448 20:15:28.836767 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9449 20:15:28.843234 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9450 20:15:28.846441 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9451 20:15:28.849881 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9452 20:15:28.856568 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9453 20:15:28.859524 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9454 20:15:28.863177 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9455 20:15:28.870003 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9456 20:15:28.873160 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9457 20:15:28.876287 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9458 20:15:28.882912 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9459 20:15:28.886299 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9460 20:15:28.893275 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9461 20:15:28.896705 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9462 20:15:28.900079 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9463 20:15:28.906314 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9464 20:15:28.909436 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9465 20:15:28.912808 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9466 20:15:28.919765 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9467 20:15:28.922907 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9468 20:15:28.929411 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9469 20:15:28.932704 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9470 20:15:28.936630 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9471 20:15:28.942894 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9472 20:15:28.945980 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9473 20:15:28.952628 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9474 20:15:28.955971 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9475 20:15:28.959660 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9476 20:15:28.966016 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9477 20:15:28.969596 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9478 20:15:28.976561 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9479 20:15:28.979013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9480 20:15:28.982833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9481 20:15:28.986035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9482 20:15:28.992227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9483 20:15:28.995786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9484 20:15:28.999057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9485 20:15:29.002623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9486 20:15:29.009136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9487 20:15:29.012524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9488 20:15:29.016289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9489 20:15:29.019406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9490 20:15:29.025563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9491 20:15:29.029282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9492 20:15:29.032286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9493 20:15:29.035303 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9494 20:15:29.041916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9495 20:15:29.046237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9496 20:15:29.052128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9497 20:15:29.055675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9498 20:15:29.058709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9499 20:15:29.065302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9500 20:15:29.068694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9501 20:15:29.075521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9502 20:15:29.078434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9503 20:15:29.085733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9504 20:15:29.088352 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9505 20:15:29.095254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9506 20:15:29.098312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9507 20:15:29.102224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9508 20:15:29.109104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9509 20:15:29.111868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9510 20:15:29.118576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9511 20:15:29.121960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9512 20:15:29.128576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9513 20:15:29.131497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9514 20:15:29.135207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9515 20:15:29.141690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9516 20:15:29.144992 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9517 20:15:29.151537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9518 20:15:29.155313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9519 20:15:29.161847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9520 20:15:29.165100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9521 20:15:29.171542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9522 20:15:29.175222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9523 20:15:29.178161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9524 20:15:29.184559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9525 20:15:29.188278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9526 20:15:29.195112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9527 20:15:29.198301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9528 20:15:29.204545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9529 20:15:29.208214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9530 20:15:29.214625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9531 20:15:29.217942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9532 20:15:29.221340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9533 20:15:29.227840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9534 20:15:29.231061 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9535 20:15:29.237668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9536 20:15:29.241488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9537 20:15:29.247520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9538 20:15:29.251304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9539 20:15:29.254930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9540 20:15:29.261235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9541 20:15:29.264862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9542 20:15:29.271242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9543 20:15:29.274422 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9544 20:15:29.277859 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9545 20:15:29.284370 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9546 20:15:29.287828 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9547 20:15:29.290859 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9548 20:15:29.294254 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9549 20:15:29.301535 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9550 20:15:29.304328 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9551 20:15:29.310912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9552 20:15:29.314318 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9553 20:15:29.318018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9554 20:15:29.324483 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9555 20:15:29.327609 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9556 20:15:29.333721 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9557 20:15:29.337452 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9558 20:15:29.344162 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9559 20:15:29.347068 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9560 20:15:29.350638 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9561 20:15:29.357083 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9562 20:15:29.360422 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9563 20:15:29.363921 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9564 20:15:29.370422 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9565 20:15:29.373749 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9566 20:15:29.377203 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9567 20:15:29.383913 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9568 20:15:29.387247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9569 20:15:29.390249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9570 20:15:29.394015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9571 20:15:29.400168 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9572 20:15:29.403632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9573 20:15:29.409986 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9574 20:15:29.414003 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9575 20:15:29.416650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9576 20:15:29.423894 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9577 20:15:29.426658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9578 20:15:29.430458 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9579 20:15:29.437274 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9580 20:15:29.440391 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9581 20:15:29.447593 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9582 20:15:29.450511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9583 20:15:29.453150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9584 20:15:29.460009 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9585 20:15:29.463098 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9586 20:15:29.469962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9587 20:15:29.473447 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9588 20:15:29.476464 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9589 20:15:29.483605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9590 20:15:29.486694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9591 20:15:29.493159 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9592 20:15:29.496325 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9593 20:15:29.499385 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9594 20:15:29.506056 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9595 20:15:29.509369 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9596 20:15:29.516173 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9597 20:15:29.519354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9598 20:15:29.522961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9599 20:15:29.529723 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9600 20:15:29.532794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9601 20:15:29.539562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9602 20:15:29.542692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9603 20:15:29.546003 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9604 20:15:29.552745 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9605 20:15:29.557017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9606 20:15:29.559358 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9607 20:15:29.565654 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9608 20:15:29.569398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9609 20:15:29.575645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9610 20:15:29.578800 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9611 20:15:29.585477 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9612 20:15:29.588664 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9613 20:15:29.592175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9614 20:15:29.598830 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9615 20:15:29.601952 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9616 20:15:29.608488 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9617 20:15:29.611655 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9618 20:15:29.615016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9619 20:15:29.621786 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9620 20:15:29.624928 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9621 20:15:29.631621 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9622 20:15:29.634838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9623 20:15:29.638329 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9624 20:15:29.644834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9625 20:15:29.648064 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9626 20:15:29.654839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9627 20:15:29.657925 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9628 20:15:29.661475 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9629 20:15:29.667560 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9630 20:15:29.670824 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9631 20:15:29.677788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9632 20:15:29.680639 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9633 20:15:29.683875 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9634 20:15:29.690449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9635 20:15:29.693868 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9636 20:15:29.700726 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9637 20:15:29.704392 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9638 20:15:29.710889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9639 20:15:29.713424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9640 20:15:29.716919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9641 20:15:29.723301 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9642 20:15:29.726465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9643 20:15:29.733444 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9644 20:15:29.736362 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9645 20:15:29.742956 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9646 20:15:29.746311 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9647 20:15:29.749638 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9648 20:15:29.756496 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9649 20:15:29.759438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9650 20:15:29.766386 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9651 20:15:29.770260 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9652 20:15:29.776088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9653 20:15:29.779397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9654 20:15:29.782494 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9655 20:15:29.789199 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9656 20:15:29.792455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9657 20:15:29.799230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9658 20:15:29.802232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9659 20:15:29.809704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9660 20:15:29.812513 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9661 20:15:29.816260 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9662 20:15:29.822269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9663 20:15:29.825698 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9664 20:15:29.832504 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9665 20:15:29.835687 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9666 20:15:29.842525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9667 20:15:29.845175 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9668 20:15:29.848730 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9669 20:15:29.855330 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9670 20:15:29.858276 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9671 20:15:29.865175 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9672 20:15:29.868143 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9673 20:15:29.875075 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9674 20:15:29.877904 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9675 20:15:29.881829 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9676 20:15:29.887965 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9677 20:15:29.891055 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9678 20:15:29.894322 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9679 20:15:29.897967 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9680 20:15:29.904604 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9681 20:15:29.908071 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9682 20:15:29.911501 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9683 20:15:29.917607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9684 20:15:29.921017 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9685 20:15:29.924278 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9686 20:15:29.930864 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9687 20:15:29.934006 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9688 20:15:29.940773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9689 20:15:29.943886 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9690 20:15:29.947488 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9691 20:15:29.954054 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9692 20:15:29.957707 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9693 20:15:29.964180 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9694 20:15:29.966835 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9695 20:15:29.970173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9696 20:15:29.976865 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9697 20:15:29.980024 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9698 20:15:29.983387 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9699 20:15:29.990045 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9700 20:15:29.993514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9701 20:15:29.996745 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9702 20:15:30.003606 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9703 20:15:30.006550 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9704 20:15:30.013558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9705 20:15:30.016517 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9706 20:15:30.020094 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9707 20:15:30.026714 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9708 20:15:30.029668 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9709 20:15:30.036149 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9710 20:15:30.039763 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9711 20:15:30.042662 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9712 20:15:30.049505 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9713 20:15:30.052600 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9714 20:15:30.059843 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9715 20:15:30.062792 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9716 20:15:30.065775 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9717 20:15:30.069388 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9718 20:15:30.072373 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9719 20:15:30.079256 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9720 20:15:30.082334 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9721 20:15:30.085446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9722 20:15:30.088885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9723 20:15:30.095586 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9724 20:15:30.098824 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9725 20:15:30.101983 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9726 20:15:30.105429 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9727 20:15:30.112038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9728 20:15:30.115760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9729 20:15:30.119049 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9730 20:15:30.125656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9731 20:15:30.128578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9732 20:15:30.135089 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9733 20:15:30.138490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9734 20:15:30.144851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9735 20:15:30.148897 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9736 20:15:30.151514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9737 20:15:30.158090 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9738 20:15:30.161169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9739 20:15:30.167936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9740 20:15:30.171492 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9741 20:15:30.177927 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9742 20:15:30.181293 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9743 20:15:30.188040 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9744 20:15:30.190794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9745 20:15:30.194465 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9746 20:15:30.200734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9747 20:15:30.204239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9748 20:15:30.210376 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9749 20:15:30.214106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9750 20:15:30.217234 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9751 20:15:30.223683 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9752 20:15:30.226807 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9753 20:15:30.233498 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9754 20:15:30.236774 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9755 20:15:30.243521 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9756 20:15:30.246799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9757 20:15:30.250078 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9758 20:15:30.256590 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9759 20:15:30.259988 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9760 20:15:30.266404 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9761 20:15:30.269636 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9762 20:15:30.276939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9763 20:15:30.279329 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9764 20:15:30.282994 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9765 20:15:30.289636 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9766 20:15:30.293023 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9767 20:15:30.299596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9768 20:15:30.302653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9769 20:15:30.305692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9770 20:15:30.312666 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9771 20:15:30.315608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9772 20:15:30.322228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9773 20:15:30.325439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9774 20:15:30.332238 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9775 20:15:30.335590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9776 20:15:30.338623 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9777 20:15:30.345071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9778 20:15:30.348697 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9779 20:15:30.355064 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9780 20:15:30.358224 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9781 20:15:30.364804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9782 20:15:30.368328 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9783 20:15:30.371881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9784 20:15:30.378127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9785 20:15:30.381211 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9786 20:15:30.388029 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9787 20:15:30.391450 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9788 20:15:30.397644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9789 20:15:30.401086 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9790 20:15:30.405015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9791 20:15:30.411071 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9792 20:15:30.414413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9793 20:15:30.421053 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9794 20:15:30.424109 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9795 20:15:30.427606 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9796 20:15:30.434038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9797 20:15:30.437336 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9798 20:15:30.444040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9799 20:15:30.447560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9800 20:15:30.450439 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9801 20:15:30.457149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9802 20:15:30.460420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9803 20:15:30.467138 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9804 20:15:30.470435 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9805 20:15:30.476981 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9806 20:15:30.480774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9807 20:15:30.486652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9808 20:15:30.490573 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9809 20:15:30.496331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9810 20:15:30.500222 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9811 20:15:30.503040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9812 20:15:30.510224 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9813 20:15:30.513143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9814 20:15:30.519619 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9815 20:15:30.522796 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9816 20:15:30.529485 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9817 20:15:30.532639 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9818 20:15:30.539273 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9819 20:15:30.543037 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9820 20:15:30.546143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9821 20:15:30.552647 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9822 20:15:30.555770 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9823 20:15:30.562744 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9824 20:15:30.566359 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9825 20:15:30.572437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9826 20:15:30.575577 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9827 20:15:30.582521 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9828 20:15:30.585741 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9829 20:15:30.589347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9830 20:15:30.595395 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9831 20:15:30.598915 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9832 20:15:30.605142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9833 20:15:30.608798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9834 20:15:30.615224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9835 20:15:30.618333 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9836 20:15:30.624939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9837 20:15:30.628648 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9838 20:15:30.631614 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9839 20:15:30.638526 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9840 20:15:30.641406 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9841 20:15:30.648092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9842 20:15:30.651675 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9843 20:15:30.658013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9844 20:15:30.661584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9845 20:15:30.667790 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9846 20:15:30.671565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9847 20:15:30.677658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9848 20:15:30.680936 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9849 20:15:30.684263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9850 20:15:30.691040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9851 20:15:30.694465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9852 20:15:30.700785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9853 20:15:30.704177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9854 20:15:30.710940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9855 20:15:30.714182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9856 20:15:30.720844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9857 20:15:30.724354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9858 20:15:30.730325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9859 20:15:30.734427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9860 20:15:30.740334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9861 20:15:30.743516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9862 20:15:30.747399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9863 20:15:30.753727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9864 20:15:30.756894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9865 20:15:30.763239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9866 20:15:30.767141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9867 20:15:30.773421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9868 20:15:30.776712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9869 20:15:30.783267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9870 20:15:30.786528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9871 20:15:30.793132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9872 20:15:30.796813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9873 20:15:30.802833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9874 20:15:30.809728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9875 20:15:30.813010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9876 20:15:30.819255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9877 20:15:30.823115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9878 20:15:30.829110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9879 20:15:30.832786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9880 20:15:30.839401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9881 20:15:30.842580 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9882 20:15:30.846368 INFO: [APUAPC] vio 0
9883 20:15:30.848896 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9884 20:15:30.853179 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9885 20:15:30.855482 INFO: [APUAPC] D0_APC_0: 0x400510
9886 20:15:30.858764 INFO: [APUAPC] D0_APC_1: 0x0
9887 20:15:30.862378 INFO: [APUAPC] D0_APC_2: 0x1540
9888 20:15:30.865540 INFO: [APUAPC] D0_APC_3: 0x0
9889 20:15:30.868614 INFO: [APUAPC] D1_APC_0: 0xffffffff
9890 20:15:30.872173 INFO: [APUAPC] D1_APC_1: 0xffffffff
9891 20:15:30.875291 INFO: [APUAPC] D1_APC_2: 0x3fffff
9892 20:15:30.878423 INFO: [APUAPC] D1_APC_3: 0x0
9893 20:15:30.882229 INFO: [APUAPC] D2_APC_0: 0xffffffff
9894 20:15:30.885304 INFO: [APUAPC] D2_APC_1: 0xffffffff
9895 20:15:30.888778 INFO: [APUAPC] D2_APC_2: 0x3fffff
9896 20:15:30.891925 INFO: [APUAPC] D2_APC_3: 0x0
9897 20:15:30.894924 INFO: [APUAPC] D3_APC_0: 0xffffffff
9898 20:15:30.898414 INFO: [APUAPC] D3_APC_1: 0xffffffff
9899 20:15:30.901467 INFO: [APUAPC] D3_APC_2: 0x3fffff
9900 20:15:30.905539 INFO: [APUAPC] D3_APC_3: 0x0
9901 20:15:30.908105 INFO: [APUAPC] D4_APC_0: 0xffffffff
9902 20:15:30.911636 INFO: [APUAPC] D4_APC_1: 0xffffffff
9903 20:15:30.915175 INFO: [APUAPC] D4_APC_2: 0x3fffff
9904 20:15:30.917981 INFO: [APUAPC] D4_APC_3: 0x0
9905 20:15:30.921239 INFO: [APUAPC] D5_APC_0: 0xffffffff
9906 20:15:30.924370 INFO: [APUAPC] D5_APC_1: 0xffffffff
9907 20:15:30.927901 INFO: [APUAPC] D5_APC_2: 0x3fffff
9908 20:15:30.931622 INFO: [APUAPC] D5_APC_3: 0x0
9909 20:15:30.934491 INFO: [APUAPC] D6_APC_0: 0xffffffff
9910 20:15:30.937784 INFO: [APUAPC] D6_APC_1: 0xffffffff
9911 20:15:30.941576 INFO: [APUAPC] D6_APC_2: 0x3fffff
9912 20:15:30.944743 INFO: [APUAPC] D6_APC_3: 0x0
9913 20:15:30.947594 INFO: [APUAPC] D7_APC_0: 0xffffffff
9914 20:15:30.951145 INFO: [APUAPC] D7_APC_1: 0xffffffff
9915 20:15:30.954322 INFO: [APUAPC] D7_APC_2: 0x3fffff
9916 20:15:30.957359 INFO: [APUAPC] D7_APC_3: 0x0
9917 20:15:30.960510 INFO: [APUAPC] D8_APC_0: 0xffffffff
9918 20:15:30.963950 INFO: [APUAPC] D8_APC_1: 0xffffffff
9919 20:15:30.967311 INFO: [APUAPC] D8_APC_2: 0x3fffff
9920 20:15:30.970756 INFO: [APUAPC] D8_APC_3: 0x0
9921 20:15:30.974015 INFO: [APUAPC] D9_APC_0: 0xffffffff
9922 20:15:30.977274 INFO: [APUAPC] D9_APC_1: 0xffffffff
9923 20:15:30.980358 INFO: [APUAPC] D9_APC_2: 0x3fffff
9924 20:15:30.984155 INFO: [APUAPC] D9_APC_3: 0x0
9925 20:15:30.987042 INFO: [APUAPC] D10_APC_0: 0xffffffff
9926 20:15:30.990470 INFO: [APUAPC] D10_APC_1: 0xffffffff
9927 20:15:30.993655 INFO: [APUAPC] D10_APC_2: 0x3fffff
9928 20:15:30.996892 INFO: [APUAPC] D10_APC_3: 0x0
9929 20:15:31.000099 INFO: [APUAPC] D11_APC_0: 0xffffffff
9930 20:15:31.003712 INFO: [APUAPC] D11_APC_1: 0xffffffff
9931 20:15:31.007032 INFO: [APUAPC] D11_APC_2: 0x3fffff
9932 20:15:31.010588 INFO: [APUAPC] D11_APC_3: 0x0
9933 20:15:31.013644 INFO: [APUAPC] D12_APC_0: 0xffffffff
9934 20:15:31.017846 INFO: [APUAPC] D12_APC_1: 0xffffffff
9935 20:15:31.020383 INFO: [APUAPC] D12_APC_2: 0x3fffff
9936 20:15:31.023336 INFO: [APUAPC] D12_APC_3: 0x0
9937 20:15:31.026636 INFO: [APUAPC] D13_APC_0: 0xffffffff
9938 20:15:31.029956 INFO: [APUAPC] D13_APC_1: 0xffffffff
9939 20:15:31.033670 INFO: [APUAPC] D13_APC_2: 0x3fffff
9940 20:15:31.036516 INFO: [APUAPC] D13_APC_3: 0x0
9941 20:15:31.040477 INFO: [APUAPC] D14_APC_0: 0xffffffff
9942 20:15:31.043065 INFO: [APUAPC] D14_APC_1: 0xffffffff
9943 20:15:31.046537 INFO: [APUAPC] D14_APC_2: 0x3fffff
9944 20:15:31.049945 INFO: [APUAPC] D14_APC_3: 0x0
9945 20:15:31.053152 INFO: [APUAPC] D15_APC_0: 0xffffffff
9946 20:15:31.057192 INFO: [APUAPC] D15_APC_1: 0xffffffff
9947 20:15:31.060040 INFO: [APUAPC] D15_APC_2: 0x3fffff
9948 20:15:31.062813 INFO: [APUAPC] D15_APC_3: 0x0
9949 20:15:31.066165 INFO: [APUAPC] APC_CON: 0x4
9950 20:15:31.069264 INFO: [NOCDAPC] D0_APC_0: 0x0
9951 20:15:31.072936 INFO: [NOCDAPC] D0_APC_1: 0x0
9952 20:15:31.075869 INFO: [NOCDAPC] D1_APC_0: 0x0
9953 20:15:31.079344 INFO: [NOCDAPC] D1_APC_1: 0xfff
9954 20:15:31.079466 INFO: [NOCDAPC] D2_APC_0: 0x0
9955 20:15:31.083084 INFO: [NOCDAPC] D2_APC_1: 0xfff
9956 20:15:31.086570 INFO: [NOCDAPC] D3_APC_0: 0x0
9957 20:15:31.089042 INFO: [NOCDAPC] D3_APC_1: 0xfff
9958 20:15:31.092660 INFO: [NOCDAPC] D4_APC_0: 0x0
9959 20:15:31.095902 INFO: [NOCDAPC] D4_APC_1: 0xfff
9960 20:15:31.099092 INFO: [NOCDAPC] D5_APC_0: 0x0
9961 20:15:31.102483 INFO: [NOCDAPC] D5_APC_1: 0xfff
9962 20:15:31.105937 INFO: [NOCDAPC] D6_APC_0: 0x0
9963 20:15:31.109669 INFO: [NOCDAPC] D6_APC_1: 0xfff
9964 20:15:31.112359 INFO: [NOCDAPC] D7_APC_0: 0x0
9965 20:15:31.115218 INFO: [NOCDAPC] D7_APC_1: 0xfff
9966 20:15:31.115320 INFO: [NOCDAPC] D8_APC_0: 0x0
9967 20:15:31.119210 INFO: [NOCDAPC] D8_APC_1: 0xfff
9968 20:15:31.121954 INFO: [NOCDAPC] D9_APC_0: 0x0
9969 20:15:31.125167 INFO: [NOCDAPC] D9_APC_1: 0xfff
9970 20:15:31.128585 INFO: [NOCDAPC] D10_APC_0: 0x0
9971 20:15:31.132373 INFO: [NOCDAPC] D10_APC_1: 0xfff
9972 20:15:31.134980 INFO: [NOCDAPC] D11_APC_0: 0x0
9973 20:15:31.138452 INFO: [NOCDAPC] D11_APC_1: 0xfff
9974 20:15:31.141880 INFO: [NOCDAPC] D12_APC_0: 0x0
9975 20:15:31.144991 INFO: [NOCDAPC] D12_APC_1: 0xfff
9976 20:15:31.148485 INFO: [NOCDAPC] D13_APC_0: 0x0
9977 20:15:31.151710 INFO: [NOCDAPC] D13_APC_1: 0xfff
9978 20:15:31.155099 INFO: [NOCDAPC] D14_APC_0: 0x0
9979 20:15:31.158285 INFO: [NOCDAPC] D14_APC_1: 0xfff
9980 20:15:31.161199 INFO: [NOCDAPC] D15_APC_0: 0x0
9981 20:15:31.164926 INFO: [NOCDAPC] D15_APC_1: 0xfff
9982 20:15:31.165053 INFO: [NOCDAPC] APC_CON: 0x4
9983 20:15:31.168313 INFO: [APUAPC] set_apusys_apc done
9984 20:15:31.171314 INFO: [DEVAPC] devapc_init done
9985 20:15:31.177994 INFO: GICv3 without legacy support detected.
9986 20:15:31.181425 INFO: ARM GICv3 driver initialized in EL3
9987 20:15:31.184621 INFO: Maximum SPI INTID supported: 639
9988 20:15:31.187925 INFO: BL31: Initializing runtime services
9989 20:15:31.194075 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9990 20:15:31.197898 INFO: SPM: enable CPC mode
9991 20:15:31.200983 INFO: mcdi ready for mcusys-off-idle and system suspend
9992 20:15:31.208144 INFO: BL31: Preparing for EL3 exit to normal world
9993 20:15:31.210891 INFO: Entry point address = 0x80000000
9994 20:15:31.213877 INFO: SPSR = 0x8
9995 20:15:31.218384
9996 20:15:31.218487
9997 20:15:31.218578
9998 20:15:31.221562 Starting depthcharge on Spherion...
9999 20:15:31.221640
10000 20:15:31.221704 Wipe memory regions:
10001 20:15:31.221783
10002 20:15:31.222584 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10003 20:15:31.222711 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10004 20:15:31.222795 Setting prompt string to ['asurada:']
10005 20:15:31.222878 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10006 20:15:31.224946 [0x00000040000000, 0x00000054600000)
10007 20:15:31.347494
10008 20:15:31.347642 [0x00000054660000, 0x00000080000000)
10009 20:15:31.608479
10010 20:15:31.608660 [0x000000821a7280, 0x000000ffe64000)
10011 20:15:32.352592
10012 20:15:32.355498 [0x00000100000000, 0x00000240000000)
10013 20:15:34.243439
10014 20:15:34.245999 Initializing XHCI USB controller at 0x11200000.
10015 20:15:35.284951
10016 20:15:35.288715 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10017 20:15:35.288797
10018 20:15:35.288861
10019 20:15:35.288919
10020 20:15:35.289195 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10022 20:15:35.389528 asurada: tftpboot 192.168.201.1 12928147/tftp-deploy-0_cc30s3/kernel/image.itb 12928147/tftp-deploy-0_cc30s3/kernel/cmdline
10023 20:15:35.389682 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 20:15:35.389803 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10025 20:15:35.394519 tftpboot 192.168.201.1 12928147/tftp-deploy-0_cc30s3/kernel/image.itp-deploy-0_cc30s3/kernel/cmdline
10026 20:15:35.394604
10027 20:15:35.394668 Waiting for link
10028 20:15:35.554788
10029 20:15:35.554916 R8152: Initializing
10030 20:15:35.554984
10031 20:15:35.557466 Version 6 (ocp_data = 5c30)
10032 20:15:35.557547
10033 20:15:35.560958 R8152: Done initializing
10034 20:15:35.561038
10035 20:15:35.561103 Adding net device
10036 20:15:37.494517
10037 20:15:37.494668 done.
10038 20:15:37.494735
10039 20:15:37.494795 MAC: 00:24:32:30:7c:7b
10040 20:15:37.494853
10041 20:15:37.497901 Sending DHCP discover... done.
10042 20:15:37.497984
10043 20:15:37.500979 Waiting for reply... done.
10044 20:15:37.501059
10045 20:15:37.505321 Sending DHCP request... done.
10046 20:15:37.505406
10047 20:15:37.519993 Waiting for reply... done.
10048 20:15:37.520078
10049 20:15:37.520142 My ip is 192.168.201.14
10050 20:15:37.520202
10051 20:15:37.523319 The DHCP server ip is 192.168.201.1
10052 20:15:37.523407
10053 20:15:37.529675 TFTP server IP predefined by user: 192.168.201.1
10054 20:15:37.529757
10055 20:15:37.536554 Bootfile predefined by user: 12928147/tftp-deploy-0_cc30s3/kernel/image.itb
10056 20:15:37.536635
10057 20:15:37.539577 Sending tftp read request... done.
10058 20:15:37.539665
10059 20:15:37.543796 Waiting for the transfer...
10060 20:15:37.543877
10061 20:15:38.094570 00000000 ################################################################
10062 20:15:38.094716
10063 20:15:38.628573 00080000 ################################################################
10064 20:15:38.628717
10065 20:15:39.174086 00100000 ################################################################
10066 20:15:39.174232
10067 20:15:39.731044 00180000 ################################################################
10068 20:15:39.731251
10069 20:15:40.258154 00200000 ################################################################
10070 20:15:40.258366
10071 20:15:40.797727 00280000 ################################################################
10072 20:15:40.797932
10073 20:15:41.340280 00300000 ################################################################
10074 20:15:41.340425
10075 20:15:41.895573 00380000 ################################################################
10076 20:15:41.895760
10077 20:15:42.435036 00400000 ################################################################
10078 20:15:42.435182
10079 20:15:42.967212 00480000 ################################################################
10080 20:15:42.967402
10081 20:15:43.528947 00500000 ################################################################
10082 20:15:43.529116
10083 20:15:44.094812 00580000 ################################################################
10084 20:15:44.094953
10085 20:15:44.643459 00600000 ################################################################
10086 20:15:44.643631
10087 20:15:45.171028 00680000 ################################################################
10088 20:15:45.171192
10089 20:15:45.698919 00700000 ################################################################
10090 20:15:45.699101
10091 20:15:46.227774 00780000 ################################################################
10092 20:15:46.227978
10093 20:15:46.782971 00800000 ################################################################
10094 20:15:46.783115
10095 20:15:47.344417 00880000 ################################################################
10096 20:15:47.344559
10097 20:15:47.903032 00900000 ################################################################
10098 20:15:47.903176
10099 20:15:48.445031 00980000 ################################################################
10100 20:15:48.445171
10101 20:15:49.002418 00a00000 ################################################################
10102 20:15:49.002560
10103 20:15:49.557096 00a80000 ################################################################
10104 20:15:49.557241
10105 20:15:50.116946 00b00000 ################################################################
10106 20:15:50.117091
10107 20:15:50.666645 00b80000 ################################################################
10108 20:15:50.666785
10109 20:15:51.206766 00c00000 ################################################################
10110 20:15:51.206972
10111 20:15:51.749750 00c80000 ################################################################
10112 20:15:51.749941
10113 20:15:52.294370 00d00000 ################################################################
10114 20:15:52.294576
10115 20:15:52.826370 00d80000 ################################################################
10116 20:15:52.826573
10117 20:15:53.368700 00e00000 ################################################################
10118 20:15:53.368848
10119 20:15:53.924720 00e80000 ################################################################
10120 20:15:53.924860
10121 20:15:54.497152 00f00000 ################################################################
10122 20:15:54.497354
10123 20:15:55.057466 00f80000 ################################################################
10124 20:15:55.057605
10125 20:15:55.606864 01000000 ################################################################
10126 20:15:55.607004
10127 20:15:56.132781 01080000 ################################################################
10128 20:15:56.132922
10129 20:15:56.683230 01100000 ################################################################
10130 20:15:56.683444
10131 20:15:57.219730 01180000 ################################################################
10132 20:15:57.219931
10133 20:15:57.771111 01200000 ################################################################
10134 20:15:57.771319
10135 20:15:58.300702 01280000 ################################################################
10136 20:15:58.300909
10137 20:15:58.844035 01300000 ################################################################
10138 20:15:58.844243
10139 20:15:59.372130 01380000 ################################################################
10140 20:15:59.372330
10141 20:15:59.900499 01400000 ################################################################
10142 20:15:59.900642
10143 20:16:00.441353 01480000 ################################################################
10144 20:16:00.441494
10145 20:16:00.970708 01500000 ################################################################
10146 20:16:00.970910
10147 20:16:01.494455 01580000 ################################################################
10148 20:16:01.494662
10149 20:16:02.048063 01600000 ################################################################
10150 20:16:02.048276
10151 20:16:02.625613 01680000 ################################################################
10152 20:16:02.625755
10153 20:16:03.190869 01700000 ################################################################
10154 20:16:03.191078
10155 20:16:03.739079 01780000 ################################################################
10156 20:16:03.739279
10157 20:16:04.280216 01800000 ################################################################
10158 20:16:04.280362
10159 20:16:04.822998 01880000 ################################################################
10160 20:16:04.823138
10161 20:16:05.385218 01900000 ################################################################
10162 20:16:05.385364
10163 20:16:05.967252 01980000 ################################################################
10164 20:16:05.967451
10165 20:16:06.534683 01a00000 ################################################################
10166 20:16:06.534825
10167 20:16:07.074724 01a80000 ################################################################
10168 20:16:07.074868
10169 20:16:07.601472 01b00000 ################################################################
10170 20:16:07.601616
10171 20:16:08.123196 01b80000 ################################################################
10172 20:16:08.123339
10173 20:16:08.670624 01c00000 ################################################################
10174 20:16:08.670767
10175 20:16:09.231289 01c80000 ################################################################
10176 20:16:09.231471
10177 20:16:09.804843 01d00000 ################################################################
10178 20:16:09.804987
10179 20:16:10.378635 01d80000 ################################################################
10180 20:16:10.378779
10181 20:16:10.938859 01e00000 ################################################################
10182 20:16:10.939027
10183 20:16:11.523242 01e80000 ################################################################
10184 20:16:11.523430
10185 20:16:12.065382 01f00000 ################################################################
10186 20:16:12.065528
10187 20:16:12.606968 01f80000 ################################################################
10188 20:16:12.607171
10189 20:16:13.178426 02000000 ################################################################
10190 20:16:13.178566
10191 20:16:13.742240 02080000 ################################################################
10192 20:16:13.742379
10193 20:16:14.294766 02100000 ################################################################
10194 20:16:14.294910
10195 20:16:14.834578 02180000 ################################################################
10196 20:16:14.834718
10197 20:16:15.398823 02200000 ################################################################
10198 20:16:15.398965
10199 20:16:15.954114 02280000 ################################################################
10200 20:16:15.954262
10201 20:16:16.491672 02300000 ################################################################
10202 20:16:16.491877
10203 20:16:17.043385 02380000 ################################################################
10204 20:16:17.043583
10205 20:16:17.591495 02400000 ################################################################
10206 20:16:17.591699
10207 20:16:18.143009 02480000 ################################################################
10208 20:16:18.143155
10209 20:16:18.693834 02500000 ################################################################
10210 20:16:18.694040
10211 20:16:19.258976 02580000 ################################################################
10212 20:16:19.259183
10213 20:16:19.810992 02600000 ################################################################
10214 20:16:19.811153
10215 20:16:20.378061 02680000 ################################################################
10216 20:16:20.378204
10217 20:16:20.934337 02700000 ################################################################
10218 20:16:20.934484
10219 20:16:21.504449 02780000 ################################################################
10220 20:16:21.504592
10221 20:16:22.031042 02800000 ################################################################
10222 20:16:22.031189
10223 20:16:22.574689 02880000 ################################################################
10224 20:16:22.574836
10225 20:16:23.116550 02900000 ################################################################
10226 20:16:23.116694
10227 20:16:23.648192 02980000 ################################################################
10228 20:16:23.648337
10229 20:16:24.208841 02a00000 ################################################################
10230 20:16:24.209012
10231 20:16:24.784232 02a80000 ################################################################
10232 20:16:24.784373
10233 20:16:25.355116 02b00000 ################################################################
10234 20:16:25.355291
10235 20:16:25.891241 02b80000 ################################################################
10236 20:16:25.891418
10237 20:16:26.440955 02c00000 ################################################################
10238 20:16:26.441097
10239 20:16:26.986940 02c80000 ################################################################
10240 20:16:26.987092
10241 20:16:27.568715 02d00000 ################################################################
10242 20:16:27.568864
10243 20:16:28.143113 02d80000 ################################################################
10244 20:16:28.143261
10245 20:16:28.704223 02e00000 ################################################################
10246 20:16:28.704370
10247 20:16:29.263064 02e80000 ################################################################
10248 20:16:29.263213
10249 20:16:29.809790 02f00000 ################################################################
10250 20:16:29.809949
10251 20:16:30.367691 02f80000 ################################################################
10252 20:16:30.367836
10253 20:16:30.910054 03000000 ################################################################
10254 20:16:30.910199
10255 20:16:31.464235 03080000 ################################################################
10256 20:16:31.464384
10257 20:16:31.572477 03100000 ############# done.
10258 20:16:31.572586
10259 20:16:31.575721 The bootfile was 51478606 bytes long.
10260 20:16:31.575808
10261 20:16:31.578726 Sending tftp read request... done.
10262 20:16:31.578807
10263 20:16:31.578872 Waiting for the transfer...
10264 20:16:31.578934
10265 20:16:31.582121 00000000 # done.
10266 20:16:31.582204
10267 20:16:31.589018 Command line loaded dynamically from TFTP file: 12928147/tftp-deploy-0_cc30s3/kernel/cmdline
10268 20:16:31.589103
10269 20:16:31.601837 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10270 20:16:31.605072
10271 20:16:31.605156 Loading FIT.
10272 20:16:31.605241
10273 20:16:31.608093 Image ramdisk-1 has 39369254 bytes.
10274 20:16:31.608177
10275 20:16:31.611534 Image fdt-1 has 47278 bytes.
10276 20:16:31.611617
10277 20:16:31.614982 Image kernel-1 has 12060038 bytes.
10278 20:16:31.615066
10279 20:16:31.621453 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10280 20:16:31.621537
10281 20:16:31.641377 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10282 20:16:31.641466
10283 20:16:31.644186 Choosing best match conf-1 for compat google,spherion-rev2.
10284 20:16:31.649341
10285 20:16:31.654494 Connected to device vid:did:rid of 1ae0:0028:00
10286 20:16:31.661964
10287 20:16:31.664275 tpm_get_response: command 0x17b, return code 0x0
10288 20:16:31.664359
10289 20:16:31.667346 ec_init: CrosEC protocol v3 supported (256, 248)
10290 20:16:31.671315
10291 20:16:31.674941 tpm_cleanup: add release locality here.
10292 20:16:31.675025
10293 20:16:31.675109 Shutting down all USB controllers.
10294 20:16:31.678053
10295 20:16:31.678136 Removing current net device
10296 20:16:31.678221
10297 20:16:31.684835 Exiting depthcharge with code 4 at timestamp: 89737391
10298 20:16:31.684919
10299 20:16:31.688039 LZMA decompressing kernel-1 to 0x821a6718
10300 20:16:31.688123
10301 20:16:31.691498 LZMA decompressing kernel-1 to 0x40000000
10302 20:16:33.192065
10303 20:16:33.192281 jumping to kernel
10304 20:16:33.193128 end: 2.2.4 bootloader-commands (duration 00:01:02) [common]
10305 20:16:33.193286 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10306 20:16:33.193412 Setting prompt string to ['Linux version [0-9]']
10307 20:16:33.193533 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10308 20:16:33.193653 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10309 20:16:33.272704
10310 20:16:33.276289 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10311 20:16:33.279808 start: 2.2.5.1 login-action (timeout 00:03:23) [common]
10312 20:16:33.279900 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10313 20:16:33.279971 Setting prompt string to []
10314 20:16:33.280051 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10315 20:16:33.280126 Using line separator: #'\n'#
10316 20:16:33.280186 No login prompt set.
10317 20:16:33.280246 Parsing kernel messages
10318 20:16:33.280302 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10319 20:16:33.280401 [login-action] Waiting for messages, (timeout 00:03:23)
10320 20:16:33.280465 Waiting using forced prompt support (timeout 00:01:42)
10321 20:16:33.299009 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10322 20:16:33.302349 [ 0.000000] random: crng init done
10323 20:16:33.309418 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10324 20:16:33.312521 [ 0.000000] efi: UEFI not found.
10325 20:16:33.319106 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10326 20:16:33.328944 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10327 20:16:33.338550 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10328 20:16:33.345174 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10329 20:16:33.351964 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10330 20:16:33.358959 [ 0.000000] printk: bootconsole [mtk8250] enabled
10331 20:16:33.364789 [ 0.000000] NUMA: No NUMA configuration found
10332 20:16:33.371915 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10333 20:16:33.378172 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10334 20:16:33.378255 [ 0.000000] Zone ranges:
10335 20:16:33.385568 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10336 20:16:33.388191 [ 0.000000] DMA32 empty
10337 20:16:33.394369 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10338 20:16:33.397753 [ 0.000000] Movable zone start for each node
10339 20:16:33.401603 [ 0.000000] Early memory node ranges
10340 20:16:33.407997 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10341 20:16:33.414717 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10342 20:16:33.420674 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10343 20:16:33.427766 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10344 20:16:33.434071 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10345 20:16:33.441009 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10346 20:16:33.497708 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10347 20:16:33.503946 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10348 20:16:33.511290 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10349 20:16:33.514095 [ 0.000000] psci: probing for conduit method from DT.
10350 20:16:33.520543 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10351 20:16:33.523999 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10352 20:16:33.530835 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10353 20:16:33.534054 [ 0.000000] psci: SMC Calling Convention v1.2
10354 20:16:33.540596 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10355 20:16:33.543662 [ 0.000000] Detected VIPT I-cache on CPU0
10356 20:16:33.550172 [ 0.000000] CPU features: detected: GIC system register CPU interface
10357 20:16:33.556691 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10358 20:16:33.563686 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10359 20:16:33.569875 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10360 20:16:33.580285 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10361 20:16:33.586769 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10362 20:16:33.590029 [ 0.000000] alternatives: applying boot alternatives
10363 20:16:33.596932 [ 0.000000] Fallback order for Node 0: 0
10364 20:16:33.603078 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10365 20:16:33.606700 [ 0.000000] Policy zone: Normal
10366 20:16:33.620317 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10367 20:16:33.629402 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10368 20:16:33.640909 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10369 20:16:33.651077 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10370 20:16:33.658381 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10371 20:16:33.660869 <6>[ 0.000000] software IO TLB: area num 8.
10372 20:16:33.717572 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10373 20:16:33.867123 <6>[ 0.000000] Memory: 7928752K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 424016K reserved, 32768K cma-reserved)
10374 20:16:33.873284 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10375 20:16:33.879945 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10376 20:16:33.883040 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10377 20:16:33.890101 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10378 20:16:33.896165 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10379 20:16:33.899324 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10380 20:16:33.909516 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10381 20:16:33.916043 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10382 20:16:33.922607 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10383 20:16:33.929167 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10384 20:16:33.932516 <6>[ 0.000000] GICv3: 608 SPIs implemented
10385 20:16:33.935617 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10386 20:16:33.942562 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10387 20:16:33.946374 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10388 20:16:33.952379 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10389 20:16:33.965237 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10390 20:16:33.978425 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10391 20:16:33.985171 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10392 20:16:33.993189 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10393 20:16:34.006433 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10394 20:16:34.012864 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10395 20:16:34.019350 <6>[ 0.009179] Console: colour dummy device 80x25
10396 20:16:34.029582 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10397 20:16:34.035930 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10398 20:16:34.039234 <6>[ 0.029217] LSM: Security Framework initializing
10399 20:16:34.045956 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 20:16:34.056105 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10401 20:16:34.065752 <6>[ 0.051476] cblist_init_generic: Setting adjustable number of callback queues.
10402 20:16:34.069182 <6>[ 0.058964] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 20:16:34.079146 <6>[ 0.065342] cblist_init_generic: Setting adjustable number of callback queues.
10404 20:16:34.086171 <6>[ 0.072769] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 20:16:34.089037 <6>[ 0.079200] rcu: Hierarchical SRCU implementation.
10406 20:16:34.095698 <6>[ 0.079202] rcu: Max phase no-delay instances is 1000.
10407 20:16:34.102035 <6>[ 0.079226] printk: bootconsole [mtk8250] printing thread started
10408 20:16:34.108818 <6>[ 0.097567] EFI services will not be available.
10409 20:16:34.112149 <6>[ 0.097773] smp: Bringing up secondary CPUs ...
10410 20:16:34.118816 <6>[ 0.098083] Detected VIPT I-cache on CPU1
10411 20:16:34.125390 <6>[ 0.098152] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10412 20:16:34.131376 <6>[ 0.098184] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10413 20:16:34.141623 <6>[ 0.126060] Detected VIPT I-cache on CPU2
10414 20:16:34.151557 <6>[ 0.126106] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10415 20:16:34.157992 <6>[ 0.126122] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10416 20:16:34.161087 <6>[ 0.126381] Detected VIPT I-cache on CPU3
10417 20:16:34.168083 <6>[ 0.126428] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10418 20:16:34.174709 <6>[ 0.126441] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10419 20:16:34.180753 <6>[ 0.126754] CPU features: detected: Spectre-v4
10420 20:16:34.184435 <6>[ 0.126760] CPU features: detected: Spectre-BHB
10421 20:16:34.187249 <6>[ 0.126765] Detected PIPT I-cache on CPU4
10422 20:16:34.193943 <6>[ 0.126824] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10423 20:16:34.205161 <6>[ 0.126841] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10424 20:16:34.207006 <6>[ 0.127138] Detected PIPT I-cache on CPU5
10425 20:16:34.213907 <6>[ 0.127197] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10426 20:16:34.220121 <6>[ 0.127213] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10427 20:16:34.223624 <6>[ 0.127493] Detected PIPT I-cache on CPU6
10428 20:16:34.233275 <6>[ 0.127558] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10429 20:16:34.240514 <6>[ 0.127574] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10430 20:16:34.243192 <6>[ 0.127866] Detected PIPT I-cache on CPU7
10431 20:16:34.249742 <6>[ 0.127929] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10432 20:16:34.256267 <6>[ 0.127945] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10433 20:16:34.263174 <6>[ 0.127991] smp: Brought up 1 node, 8 CPUs
10434 20:16:34.266465 <6>[ 0.127996] SMP: Total of 8 processors activated.
10435 20:16:34.272877 <6>[ 0.127999] CPU features: detected: 32-bit EL0 Support
10436 20:16:34.279313 <6>[ 0.128001] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10437 20:16:34.286276 <6>[ 0.128003] CPU features: detected: Common not Private translations
10438 20:16:34.292679 <6>[ 0.128005] CPU features: detected: CRC32 instructions
10439 20:16:34.299645 <6>[ 0.128008] CPU features: detected: RCpc load-acquire (LDAPR)
10440 20:16:34.306073 <6>[ 0.128009] CPU features: detected: LSE atomic instructions
10441 20:16:34.309074 <6>[ 0.128011] CPU features: detected: Privileged Access Never
10442 20:16:34.315611 <6>[ 0.128012] CPU features: detected: RAS Extension Support
10443 20:16:34.322570 <6>[ 0.128015] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10444 20:16:34.325759 <6>[ 0.128082] CPU: All CPU(s) started at EL2
10445 20:16:34.349125 �íͽ�ɍ��
10446 20:16:34.356197 ɍ�}���}��չѕ�5R�<6>[ 0.344<429] printk: console [ttyS0] printing thread started
10447 20:16:34.358801 5>[<6>[ 0.344458] printk: console [ttyS0] enabled
10448 20:16:34.365367 0.225585] VFS: Disk quotas dquot_6.6.0
10449 20:16:34.372548 <6>[ 0.344462] printk: bootconsole [mtk8250] disabled
10450 20:16:34.378573 <6>[ 0.358882] printk: bootconsole [mtk8250] printing thread stopped
10451 20:16:34.382225 <6>[ 0.359890] SuperH (H)SCI(F) driver initialized
10452 20:16:34.388380 <6>[ 0.360358] msm_serial: driver initialized
10453 20:16:34.395155 <6>[ 0.364838] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10454 20:16:34.405136 <6>[ 0.364865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10455 20:16:34.411679 <6>[ 0.364894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10456 20:16:34.421282 <6>[ 0.364923] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10457 20:16:34.431194 <6>[ 0.364944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10458 20:16:34.445266 <6>[ 0.364970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10459 20:16:34.456759 <6>[ 0.364998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10460 20:16:34.464498 <6>[ 0.365107] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10461 20:16:34.468948 <6>[ 0.365136] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10462 20:16:34.474346 <6>[ 0.376366] loop: module loaded
10463 20:16:34.478154 <6>[ 0.378848] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10464 20:16:34.481654 <4>[ 0.395513] mtk-pmic-keys: Failed to locate of_node [id: -1]
10465 20:16:34.484872 <6>[ 0.396303] megasas: 07.719.03.00-rc1
10466 20:16:34.491393 <6>[ 0.408885] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10467 20:16:34.494643 <6>[ 0.409047] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10468 20:16:34.501594 <6>[ 0.420902] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10469 20:16:34.514417 <6>[ 0.472752] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10470 20:16:35.847628 <6>[ 1.835473] Freeing initrd memory: 38440K
10471 20:16:35.854346 <6>[ 1.841451] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10472 20:16:35.857419 <6>[ 1.846315] tun: Universal TUN/TAP device driver, 1.6
10473 20:16:35.861294 <6>[ 1.847073] thunder_xcv, ver 1.0
10474 20:16:35.864091 <6>[ 1.847090] thunder_bgx, ver 1.0
10475 20:16:35.867326 <6>[ 1.847107] nicpf, ver 1.0
10476 20:16:35.877388 <6>[ 1.848154] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10477 20:16:35.880882 <6>[ 1.848157] hns3: Copyright (c) 2017 Huawei Corporation.
10478 20:16:35.884044 <6>[ 1.848182] hclge is initializing
10479 20:16:35.891274 <6>[ 1.848198] e1000: Intel(R) PRO/1000 Network Driver
10480 20:16:35.897530 <6>[ 1.848200] e1000: Copyright (c) 1999-2006 Intel Corporation.
10481 20:16:35.900859 <6>[ 1.848220] e1000e: Intel(R) PRO/1000 Network Driver
10482 20:16:35.907587 <6>[ 1.848222] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10483 20:16:35.914577 <6>[ 1.848236] igb: Intel(R) Gigabit Ethernet Network Driver
10484 20:16:35.918646 <6>[ 1.848238] igb: Copyright (c) 2007-2014 Intel Corporation.
10485 20:16:35.925319 <6>[ 1.848252] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10486 20:16:35.932067 <6>[ 1.848255] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10487 20:16:35.935104 <6>[ 1.848545] sky2: driver version 1.30
10488 20:16:35.942300 <6>[ 1.849629] VFIO - User Level meta-driver version: 0.3
10489 20:16:35.948493 <6>[ 1.852459] usbcore: registered new interface driver usb-storage
10490 20:16:35.952022 <6>[ 1.852640] usbcore: registered new device driver onboard-usb-hub
10491 20:16:35.958639 <6>[ 1.855377] mt6397-rtc mt6359-rtc: registered as rtc0
10492 20:16:35.968404 <6>[ 1.855529] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:16:35 UTC (1709496995)
10493 20:16:35.971565 <6>[ 1.856131] i2c_dev: i2c /dev entries driver
10494 20:16:35.981863 <6>[ 1.863274] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10495 20:16:35.985031 <6>[ 1.879249] cpu cpu0: EM: created perf domain
10496 20:16:35.988423 <6>[ 1.879575] cpu cpu4: EM: created perf domain
10497 20:16:35.995434 <6>[ 1.885103] sdhci: Secure Digital Host Controller Interface driver
10498 20:16:36.001366 <6>[ 1.885104] sdhci: Copyright(c) Pierre Ossman
10499 20:16:36.008230 <6>[ 1.885453] Synopsys Designware Multimedia Card Interface Driver
10500 20:16:36.011213 <6>[ 1.885829] sdhci-pltfm: SDHCI platform and OF driver helper
10501 20:16:36.017865 <6>[ 1.891455] mmc0: CQHCI version 5.10
10502 20:16:36.021474 <6>[ 1.896256] ledtrig-cpu: registered to indicate activity on CPUs
10503 20:16:36.031131 <6>[ 1.897163] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10504 20:16:36.034939 <6>[ 1.897436] usbcore: registered new interface driver usbhid
10505 20:16:36.041381 <6>[ 1.897437] usbhid: USB HID core driver
10506 20:16:36.047487 <6>[ 1.897592] spi_master spi0: will run message pump with realtime priority
10507 20:16:36.057552 <6>[ 1.927721] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10508 20:16:36.074292 <6>[ 1.929972] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10509 20:16:36.077530 <6>[ 1.930970] cros-ec-spi spi0.0: Chrome EC device registered
10510 20:16:36.087537 <6>[ 1.944035] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10511 20:16:36.094074 <6>[ 1.944991] NET: Registered PF_PACKET protocol family
10512 20:16:36.097331 <6>[ 1.945063] 9pnet: Installing 9P2000 support
10513 20:16:36.100531 <5>[ 1.945096] Key type dns_resolver registered
10514 20:16:36.107147 <6>[ 1.945380] registered taskstats version 1
10515 20:16:36.110736 <5>[ 1.945393] Loading compiled-in X.509 certificates
10516 20:16:36.120216 <4>[ 1.961283] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 20:16:36.134305 <4>[ 1.961441] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 20:16:36.140375 <3>[ 1.961456] debugfs: File 'uA_load' in directory '/' already present!
10519 20:16:36.146727 <3>[ 1.961474] debugfs: File 'min_uV' in directory '/' already present!
10520 20:16:36.153062 <3>[ 1.961480] debugfs: File 'max_uV' in directory '/' already present!
10521 20:16:36.160330 <3>[ 1.961483] debugfs: File 'constraint_flags' in directory '/' already present!
10522 20:16:36.170027 <3>[ 1.963696] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10523 20:16:36.173423 <6>[ 1.971412] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10524 20:16:36.180199 <6>[ 1.972079] xhci-mtk 11200000.usb: xHCI Host Controller
10525 20:16:36.186534 <6>[ 1.972099] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10526 20:16:36.195995 <6>[ 1.972366] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10527 20:16:36.202994 <6>[ 1.972413] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10528 20:16:36.209521 <6>[ 1.972496] xhci-mtk 11200000.usb: xHCI Host Controller
10529 20:16:36.215731 <6>[ 1.972504] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10530 20:16:36.223036 <6>[ 1.972512] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10531 20:16:36.225709 <6>[ 1.972892] hub 1-0:1.0: USB hub found
10532 20:16:36.232461 <6>[ 1.972910] hub 1-0:1.0: 1 port detected
10533 20:16:36.238971 <6>[ 1.973079] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10534 20:16:36.242187 <6>[ 1.973291] hub 2-0:1.0: USB hub found
10535 20:16:36.248855 <6>[ 1.973306] hub 2-0:1.0: 1 port detected
10536 20:16:36.253131 <6>[ 1.976406] mtk-msdc 11f70000.mmc: Got CD GPIO
10537 20:16:36.262257 <6>[ 1.990346] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10538 20:16:36.269001 <6>[ 1.990355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10539 20:16:36.279029 <4>[ 1.990518] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10540 20:16:36.281720 <6>[ 1.990925] mmc0: Command Queue Engine enabled
10541 20:16:36.288423 <6>[ 1.990935] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10542 20:16:36.298205 <6>[ 1.991148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10543 20:16:36.305048 <6>[ 1.991153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10544 20:16:36.311601 <6>[ 1.991287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10545 20:16:36.321705 <6>[ 1.991301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10546 20:16:36.328104 <6>[ 1.991307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10547 20:16:36.338442 <6>[ 1.991319] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10548 20:16:36.341542 <6>[ 1.991475] mmcblk0: mmc0:0001 DA4128 116 GiB
10549 20:16:36.351490 <6>[ 1.993112] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10550 20:16:36.357843 <6>[ 1.993131] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10551 20:16:36.368192 <6>[ 1.993137] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10552 20:16:36.374478 <6>[ 1.993142] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10553 20:16:36.384382 <6>[ 1.993147] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10554 20:16:36.391123 <6>[ 1.993153] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10555 20:16:36.400928 <6>[ 1.993158] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10556 20:16:36.407223 <6>[ 1.993164] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10557 20:16:36.417256 <6>[ 1.993169] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10558 20:16:36.427071 <6>[ 1.993174] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10559 20:16:36.433621 <6>[ 1.993179] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10560 20:16:36.443460 <6>[ 1.993184] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10561 20:16:36.449971 <6>[ 1.993189] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10562 20:16:36.459946 <6>[ 1.993194] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10563 20:16:36.466469 <6>[ 1.993200] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10564 20:16:36.473033 <6>[ 1.993809] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10565 20:16:36.479698 <6>[ 1.994707] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10566 20:16:36.486621 <6>[ 1.995237] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10567 20:16:36.493135 <6>[ 1.995275] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10568 20:16:36.499697 <6>[ 1.995912] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10569 20:16:36.506098 <6>[ 1.996363] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10570 20:16:36.512583 <6>[ 1.996580] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10571 20:16:36.519329 <6>[ 1.996795] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10572 20:16:36.529330 <6>[ 1.996814] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10573 20:16:36.538992 <6>[ 1.996819] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10574 20:16:36.548830 <6>[ 1.996826] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10575 20:16:36.559234 <6>[ 1.996832] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10576 20:16:36.565341 <6>[ 1.996838] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10577 20:16:36.575317 <6>[ 1.996844] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10578 20:16:36.584910 <6>[ 1.996849] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10579 20:16:36.595030 <6>[ 1.996855] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10580 20:16:36.604930 <6>[ 1.996866] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10581 20:16:36.615213 <6>[ 1.996870] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10582 20:16:36.621259 <6>[ 1.997140] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10583 20:16:36.627696 <6>[ 1.997434] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10584 20:16:36.634703 <6>[ 1.998144] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10585 20:16:36.641382 <6>[ 2.329822] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10586 20:16:36.644444 <6>[ 2.356538] hub 2-1:1.0: USB hub found
10587 20:16:36.650898 <6>[ 2.356888] hub 2-1:1.0: 3 ports detected
10588 20:16:36.654193 <6>[ 2.359633] hub 2-1:1.0: USB hub found
10589 20:16:36.657702 <6>[ 2.359995] hub 2-1:1.0: 3 ports detected
10590 20:16:36.664040 <6>[ 2.481556] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10591 20:16:36.667855 <6>[ 2.633752] hub 1-1:1.0: USB hub found
10592 20:16:36.674666 <6>[ 2.634096] hub 1-1:1.0: 4 ports detected
10593 20:16:36.677336 <6>[ 2.637170] hub 1-1:1.0: USB hub found
10594 20:16:36.683188 <6>[ 2.637432] hub 1-1:1.0: 4 ports detected
10595 20:16:36.730675 <6>[ 2.713924] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10596 20:16:36.966848 <6>[ 2.949755] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10597 20:16:37.092090 <6>[ 3.077667] hub 1-1.4:1.0: USB hub found
10598 20:16:37.095024 <6>[ 3.078129] hub 1-1.4:1.0: 2 ports detected
10599 20:16:37.098193 <6>[ 3.082275] hub 1-1.4:1.0: USB hub found
10600 20:16:37.104629 <6>[ 3.082635] hub 1-1.4:1.0: 2 ports detected
10601 20:16:37.386554 <6>[ 3.369755] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10602 20:16:37.570968 <6>[ 3.553758] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10603 20:16:48.315310 <6>[ 14.307108] ALSA device list:
10604 20:16:48.322671 <6>[ 14.307132] No soundcards found.
10605 20:16:48.326440 <6>[ 14.311101] Freeing unused kernel memory: 8448K
10606 20:16:48.328624 <6>[ 14.311194] Run /init as init process
10607 20:16:48.346620 <6>[ 14.334490] NET: Registered PF_INET6 protocol family
10608 20:16:48.350078 <6>[ 14.335661] Segment Routing with IPv6
10609 20:16:48.353874
10610 20:16:48.359517 Welcome to [1mDebian GNU/Linu<6>[ 14.335672] In-situ OAM (IOAM) with IPv6
10611 20:16:48.382961 <30>[ 14.346989] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10612 20:16:48.386453 <30>[ 14.347390] systemd[1]: Detected architecture arm64.
10613 20:16:48.389237 x 11 (bullseye)[0m!
10614 20:16:48.389361
10615 20:16:48.406464 <30>[ 14.393691] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10616 20:16:48.529533 <30>[ 14.517141] systemd[1]: Queued start job for default target Graphical Interface.
10617 20:16:48.563141 [[0;32m OK [0m] Created slic<30>[ 14.550844] systemd[1]: Created slice system-getty.slice.
10618 20:16:48.566283 e [0;1;39msystem-getty.slice[0m.
10619 20:16:48.589470 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.574195] systemd[1]: Created slice system-modprobe.slice.
10620 20:16:48.589600 m-modprobe.slice[0m.
10621 20:16:48.611885 [[0;32m OK [0m] Created slic<30>[ 14.599546] systemd[1]: Created slice system-serial\x2dgetty.slice.
10622 20:16:48.618352 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10623 20:16:48.635592 [[0;32m OK [0m] Created slic<30>[ 14.623361] systemd[1]: Created slice User and Session Slice.
10624 20:16:48.638800 e [0;1;39mUser and Session Slice[0m.
10625 20:16:48.661895 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.646346] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10626 20:16:48.666086 ssword …ts to Console Directory Watch[0m.
10627 20:16:48.690373 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.674405] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10628 20:16:48.693737 sword R…uests to Wall Directory Watch[0m.
10629 20:16:48.721279 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.702201] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10630 20:16:48.731017 l Encrypted Volu<30>[ 14.702441] systemd[1]: Reached target Local Encrypted Volumes.
10631 20:16:48.731099 mes[0m.
10632 20:16:48.750506 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.738308] systemd[1]: Reached target Paths.
10633 20:16:48.750590 s[0m.
10634 20:16:48.772997 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.757753] systemd[1]: Reached target Remote File Systems.
10635 20:16:48.773124 te File Systems[0m.
10636 20:16:48.794243 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.782151] systemd[1]: Reached target Slices.
10637 20:16:48.794369 es[0m.
10638 20:16:48.813561 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.801761] systemd[1]: Reached target Swap.
10639 20:16:48.813686 [0m.
10640 20:16:48.838037 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.822243] systemd[1]: Listening on initctl Compatibility Named Pipe.
10641 20:16:48.841521 l Compatibility Named Pipe[0m.
10642 20:16:48.847724 [[0;32m OK [<30>[ 14.837349] systemd[1]: Listening on Journal Audit Socket.
10643 20:16:48.854561 0m] Listening on [0;1;39mJournal Audit Socket[0m.
10644 20:16:48.874322 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.858245] systemd[1]: Listening on Journal Socket (/dev/log).
10645 20:16:48.874404 l Socket (/dev/log)[0m.
10646 20:16:48.895332 [[0;32m OK [0m] Listening on<30>[ 14.882995] systemd[1]: Listening on Journal Socket.
10647 20:16:48.898911 [0;1;39mJournal Socket[0m.
10648 20:16:48.918011 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.902434] systemd[1]: Listening on Network Service Netlink Socket.
10649 20:16:48.921540 k Service Netlink Socket[0m.
10650 20:16:48.938505 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.926319] systemd[1]: Listening on udev Control Socket.
10651 20:16:48.941923 ontrol Socket[0m.
10652 20:16:48.963605 [[0;32m OK [0m] Listening on<30>[ 14.950831] systemd[1]: Listening on udev Kernel Socket.
10653 20:16:48.966522 [0;1;39mudev Kernel Socket[0m.
10654 20:16:49.013408 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.997944] systemd[1]: Mounting Huge Pages File System...
10655 20:16:49.013499 m[0m...
10656 20:16:49.031769 Mounting [0;1;39mPOSIX<30>[ 15.019525] systemd[1]: Mounting POSIX Message Queue File System...
10657 20:16:49.034895 Message Queue File System[0m...
10658 20:16:49.055859 Mounting [0;1;39mKerne<30>[ 15.043855] systemd[1]: Mounting Kernel Debug File System...
10659 20:16:49.059324 l Debug File System[0m...
10660 20:16:49.084757 Startin<30>[ 15.065990] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10661 20:16:49.094708 g [0;1;39mCreat<30>[ 15.069312] systemd[1]: Starting Create list of static device nodes for the current kernel...
10662 20:16:49.098168 e list of st…odes for the current kernel[0m...
10663 20:16:49.122049 Startin<30>[ 15.108853] systemd[1]: Starting Load Kernel Module configfs...
10664 20:16:49.124210 g [0;1;39mLoad Kernel Module configfs[0m...
10665 20:16:49.146268 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.133817] systemd[1]: Starting Load Kernel Module drm...
10666 20:16:49.149363 m[0m...
10667 20:16:49.170157 <30>[ 15.154031] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10668 20:16:49.182356 Starting [0;1;39mJournal Service[0m..<30>[ 15.170144] systemd[1]: Starting Journal Service...
10669 20:16:49.182438 .
10670 20:16:49.204919 Startin<30>[ 15.192471] systemd[1]: Starting Load Kernel Modules...
10671 20:16:49.208415 g [0;1;39mLoad Kernel Modules[0m...
10672 20:16:49.231628 Starting [0;1;39mRemou<30>[ 15.218955] systemd[1]: Starting Remount Root and Kernel File Systems...
10673 20:16:49.238062 nt Root and Kernel File Systems[0m...
10674 20:16:49.261782 Starting [0;1;39mColdplug All udev Dev<30>[ 15.246100] systemd[1]: Starting Coldplug All udev Devices...
10675 20:16:49.261866 ices[0m...
10676 20:16:49.278423 <30>[ 15.269387] systemd[1]: Started Journal Service.
10677 20:16:49.284868 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10678 20:16:49.300883 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10679 20:16:49.319407 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10680 20:16:49.335354 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10681 20:16:49.359947 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10682 20:16:49.375783 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10683 20:16:49.391656 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10684 20:16:49.411716 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10685 20:16:49.436518 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10686 20:16:49.454646 See 'systemctl status systemd-remount-fs.service' for details.
10687 20:16:49.511065 Mounting [0;1;39mKernel Configuration File System[0m...
10688 20:16:49.531552 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10689 20:16:49.545538 <46>[ 15.532821] systemd-journald[193]: Received client request to flush runtime journal.
10690 20:16:49.555921 Starting [0;1;39mLoad/Save Random Seed[0m...
10691 20:16:49.575541 Starting [0;1;39mApply Kernel Variables[0m...
10692 20:16:49.595540 Starting [0;1;39mCreate System Users[0m...
10693 20:16:49.615504 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10694 20:16:49.631957 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10695 20:16:49.651429 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10696 20:16:49.664724 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10697 20:16:49.680304 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10698 20:16:49.695835 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10699 20:16:49.742947 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10700 20:16:49.766809 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10701 20:16:49.783186 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10702 20:16:49.798402 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10703 20:16:49.843002 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10704 20:16:49.871176 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10705 20:16:49.899617 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10706 20:16:49.921077 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10707 20:16:49.968107 Starting [0;1;39mNetwork Service[0m...
10708 20:16:49.994827 Starting [0;1;39mNetwork Time Synchronization[0m...
10709 20:16:50.019269 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10710 20:16:50.036490 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10711 20:16:50.073651 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10712 20:16:50.089502 <6>[ 16.075870] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10713 20:16:50.095959 <6>[ 16.075993] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10714 20:16:50.105819 <6>[ 16.076010] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10715 20:16:50.112318 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10716 20:16:50.118979 <4>[ 16.107127] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10717 20:16:50.133548 <4>[ 16.118678] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10718 20:16:50.146707 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10719 20:16:50.158502 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10720 20:16:50.169277 <3>[ 16.156031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 20:16:50.175925 <3>[ 16.156058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 20:16:50.185724 <3>[ 16.156063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 20:16:50.192799 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10724 20:16:50.199013 <6>[ 16.186008] usbcore: registered new device driver r8152-cfgselector
10725 20:16:50.209162 <3>[ 16.186286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 20:16:50.215613 <3>[ 16.186307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 20:16:50.225283 <3>[ 16.186316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 20:16:50.232293 <3>[ 16.186325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 20:16:50.238606 <3>[ 16.186334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 20:16:50.245477 <6>[ 16.187650] mc: Linux media interface: v0.10
10731 20:16:50.251890 <3>[ 16.193831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 20:16:50.261988 <3>[ 16.199960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 20:16:50.268871 <3>[ 16.199978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 20:16:50.278550 <3>[ 16.199985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 20:16:50.285039 <6>[ 16.200068] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10736 20:16:50.288326 <6>[ 16.200076] pci_bus 0000:00: root bus resource [bus 00-ff]
10737 20:16:50.295478 <6>[ 16.200082] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10738 20:16:50.305031 <6>[ 16.200087] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10739 20:16:50.311569 <6>[ 16.200128] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 20:16:50.321403 <6>[ 16.200148] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10741 20:16:50.324589 <6>[ 16.200228] pci 0000:00:00.0: supports D1 D2
10742 20:16:50.331341 <6>[ 16.200231] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 20:16:50.344871 Starting [0;1;39mLoad/<3>[ 16.202043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 20:16:50.351207 <3>[ 16.202057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 20:16:50.357968 <3>[ 16.202065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 20:16:50.367635 Save Screen …o<3>[ 16.202075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 20:16:50.377928 <3>[ 16.202083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 20:16:50.385254 <3>[ 16.202135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 20:16:50.394832 f leds:white:kbd<6>[ 16.215650] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10750 20:16:50.402222 <6>[ 16.217505] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10751 20:16:50.408764 <6>[ 16.217536] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10752 20:16:50.415283 <6>[ 16.217556] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10753 20:16:50.425011 _backlight[0m..<6>[ 16.217571] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10754 20:16:50.425140 .
10755 20:16:50.428904 <6>[ 16.217684] pci 0000:01:00.0: supports D1 D2
10756 20:16:50.435174 <6>[ 16.217686] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10757 20:16:50.441618 <6>[ 16.239229] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10758 20:16:50.452579 <6>[ 16.239295] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10759 20:16:50.458246 <6>[ 16.239298] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10760 20:16:50.468039 <6>[ 16.239307] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10761 20:16:50.477950 Startin<6>[ 16.239320] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10762 20:16:50.488212 g [0;1;39mNetwo<6>[ 16.239333] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10763 20:16:50.492157 <6>[ 16.239365] pci 0000:00:00.0: PCI bridge to [bus 01]
10764 20:16:50.502347 rk Name Resoluti<6>[ 16.239370] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10765 20:16:50.508738 <6>[ 16.241554] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10766 20:16:50.512007 <6>[ 16.247743] videodev: Linux video capture interface: v2.00
10767 20:16:50.515131 on[0m...
10768 20:16:50.525509 <6>[ 16.251193] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10769 20:16:50.532591 <6>[ 16.265904] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10770 20:16:50.541935 <6>[ 16.266708] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10771 20:16:50.549464 <6>[ 16.304135] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10772 20:16:50.552443 <6>[ 16.311324] Bluetooth: Core ver 2.22
10773 20:16:50.559009 <6>[ 16.311611] NET: Registered PF_BLUETOOTH protocol family
10774 20:16:50.565429 <6>[ 16.311618] Bluetooth: HCI device and connection manager initialized
10775 20:16:50.572079 <6>[ 16.311699] Bluetooth: HCI socket layer initialized
10776 20:16:50.575222 <6>[ 16.311741] Bluetooth: L2CAP socket layer initialized
10777 20:16:50.582135 <6>[ 16.311802] Bluetooth: SCO socket layer initialized
10778 20:16:50.591702 [[0;32m OK [<6>[ 16.314719] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10779 20:16:50.598811 0m] Finished [0<6>[ 16.331332] remoteproc remoteproc0: scp is available
10780 20:16:50.602337 <6>[ 16.331510] remoteproc remoteproc0: powering up scp
10781 20:16:50.609572 <6>[ 16.331516] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10782 20:16:50.616436 <6>[ 16.331535] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10783 20:16:50.623122 <6>[ 16.343680] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10784 20:16:50.629964 ;1;39mUpdate UTM<6>[ 16.360854] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10785 20:16:50.640220 P about System B<4>[ 16.361744] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10786 20:16:50.643770 <4>[ 16.361744] Fallback method does not support PEC.
10787 20:16:50.653782 oot/Shutdown[0m<6>[ 16.363528] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10788 20:16:50.653866 .
10789 20:16:50.664654 <3>[ 16.377621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 20:16:50.671570 <4>[ 16.396048] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10791 20:16:50.680640 <4>[ 16.396065] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10792 20:16:50.687874 [[0;32m OK [<6>[ 16.397724] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10793 20:16:50.701506 0m] Finished [0<3>[ 16.401731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 20:16:50.711735 <6>[ 16.449155] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10795 20:16:50.717664 ;1;39mLoad/Save <6>[ 16.457117] r8152 2-1.3:1.0 eth0: v1.12.13
10796 20:16:50.725539 Screen …s of l<6>[ 16.457206] usbcore: registered new interface driver r8152
10797 20:16:50.735921 eds:white:kbd_ba<6>[ 16.457257] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10798 20:16:50.736003 cklight[0m.
10799 20:16:50.742444 <6>[ 16.457257] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10800 20:16:50.749968 <6>[ 16.457268] remoteproc remoteproc0: remote processor scp is now up
10801 20:16:50.759348 <4>[ 16.457596] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10802 20:16:50.766428 [[0;32m OK [<3>[ 16.457609] Bluetooth: hci0: Failed to load firmware file (-2)
10803 20:16:50.772490 <3>[ 16.457615] Bluetooth: hci0: Failed to set up firmware (-2)
10804 20:16:50.782289 <4>[ 16.457619] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10805 20:16:50.789101 <6>[ 16.457912] usbcore: registered new interface driver uvcvideo
10806 20:16:50.795627 <6>[ 16.465416] usbcore: registered new interface driver btusb
10807 20:16:50.802030 <6>[ 16.478657] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10808 20:16:50.811964 <3>[ 16.488283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10809 20:16:50.818327 <3>[ 16.523882] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 20:16:50.825761 <6>[ 16.531972] usbcore: registered new interface driver cdc_ether
10811 20:16:50.835172 0m] Started [0;<3>[ 16.547849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10812 20:16:50.841499 <6>[ 16.548206] usbcore: registered new interface driver r8153_ecm
10813 20:16:50.848626 <6>[ 16.589690] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10814 20:16:50.857990 <6>[ 16.593676] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10815 20:16:50.864699 <5>[ 16.595342] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10816 20:16:50.871723 <6>[ 16.603445] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10817 20:16:50.878170 <5>[ 16.607639] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10818 20:16:50.887602 <5>[ 16.607873] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10819 20:16:50.894330 <3>[ 16.611066] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10820 20:16:50.904627 <3>[ 16.611888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10821 20:16:50.914957 <3>[ 16.612693] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 20:16:50.921276 <3>[ 16.637844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 20:16:50.930596 <3>[ 16.660015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10824 20:16:50.941397 <4>[ 16.722470] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10825 20:16:50.943779 <6>[ 16.722502] cfg80211: failed to load regulatory.db
10826 20:16:50.954285 <6>[ 16.806828] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 20:16:50.957241 <6>[ 16.806933] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 20:16:50.963701 <6>[ 16.832298] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 20:16:50.973670 <6>[ 16.928522] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10830 20:16:50.973750 <6>[ 16.928522]
10831 20:16:50.976876 1;39mNetwork Name Resolution[0m.
10832 20:16:51.064978 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10833 20:16:51.078191 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10834 20:16:51.097263 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10835 20:16:51.110765 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10836 20:16:51.134104 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10837 20:16:51.149571 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10838 20:16:51.162063 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10839 20:16:51.182387 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10840 20:16:51.195156 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10841 20:16:51.205336 <6>[ 17.190411] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10842 20:16:51.212486 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10843 20:16:51.231018 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10844 20:16:51.266774 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10845 20:16:51.297617 Starting [0;1;39mUser Login Management[0m...
10846 20:16:51.314647 Starting [0;1;39mPermit User Sessions[0m...
10847 20:16:51.334400 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10848 20:16:51.375267 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10849 20:16:51.395245 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10850 20:16:51.410892 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10851 20:16:51.431242 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10852 20:16:51.447966 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10853 20:16:51.463380 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10854 20:16:51.480617 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10855 20:16:51.499599 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10856 20:16:51.558660 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10857 20:16:51.593985 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10858 20:16:51.639849
10859 20:16:51.639933
10860 20:16:51.642703 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10861 20:16:51.642784
10862 20:16:51.646129 debian-bullseye-arm64 login: root (automatic login)
10863 20:16:51.646209
10864 20:16:51.646274
10865 20:16:51.662668 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10866 20:16:51.662749
10867 20:16:51.669666 The programs included with the Debian GNU/Linux system are free software;
10868 20:16:51.675935 the exact distribution terms for each program are described in the
10869 20:16:51.679179 individual files in /usr/share/doc/*/copyright.
10870 20:16:51.679259
10871 20:16:51.686189 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10872 20:16:51.689186 permitted by applicable law.
10873 20:16:51.689553 Matched prompt #10: / #
10875 20:16:51.689754 Setting prompt string to ['/ #']
10876 20:16:51.689844 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10878 20:16:51.690034 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10879 20:16:51.690117 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
10880 20:16:51.690185 Setting prompt string to ['/ #']
10881 20:16:51.690243 Forcing a shell prompt, looking for ['/ #']
10883 20:16:51.740452 / #
10884 20:16:51.740548 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10885 20:16:51.740650 Waiting using forced prompt support (timeout 00:02:30)
10886 20:16:51.745391
10887 20:16:51.745660 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10888 20:16:51.745754 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
10889 20:16:51.745848 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10890 20:16:51.745931 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
10891 20:16:51.746012 end: 2 depthcharge-action (duration 00:01:55) [common]
10892 20:16:51.746099 start: 3 lava-test-retry (timeout 00:07:45) [common]
10893 20:16:51.746180 start: 3.1 lava-test-shell (timeout 00:07:45) [common]
10894 20:16:51.746254 Using namespace: common
10896 20:16:51.846566 / # #
10897 20:16:51.846684 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10898 20:16:51.851773 #
10899 20:16:51.852036 Using /lava-12928147
10901 20:16:51.952364 / # export SHELL=/bin/sh
10902 20:16:51.957721 export SHELL=/bin/sh
10904 20:16:52.058234 / # . /lava-12928147/environment
10905 20:16:52.058381 . /lava-12928147/environment<6>[ 18.024048] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
10906 20:16:52.058465 <6>[ 18.024656] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10907 20:16:52.061065 <6>[ 18.035561] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10908 20:16:52.061147
10910 20:16:52.203979 / # /lava-12928147/bin/lava-test-runner /lava-12928147/0
10911 20:16:52.204098 Test shell timeout: 10s (minimum of the action and connection timeout)
10912 20:16:52.208943 /lava-12928147/bin/lava-test-runner /lava-12928147/0
10913 20:16:52.232653 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10914 20:16:52.239547 + cd /lava-12928147/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10915 20:16:52.239663 + cat uuid
10916 20:16:52.242574 + UUID=12928147_1.5.2.3.1
10917 20:16:52.242661 + set +x
10918 20:16:52.248843 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12928147_1.5.2.3.1>
10919 20:16:52.249115 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12928147_1.5.2.3.1
10920 20:16:52.249207 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12928147_1.5.2.3.1)
10921 20:16:52.249303 Skipping test definition patterns.
10922 20:16:52.252301 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10923 20:16:52.259157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10924 20:16:52.259482 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10926 20:16:52.265642 d<4>[ 18.252298] use of bytesused == 0 is deprecated and will be removed in the future,
10927 20:16:52.272027 evice: /dev/vide<4>[ 18.252305] use the actual size instead.
10928 20:16:52.272109 o2
10929 20:16:52.275273 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10930 20:16:52.288113 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10931 20:16:52.294367
10932 20:16:52.305994 Compliance test for mtk-vcodec-enc device /dev/video2:
10933 20:16:52.314067
10934 20:16:52.324641 Driver Info:
10935 20:16:52.335554 Driver name : mtk-vcodec-enc
10936 20:16:52.348722 Card type : MT8192 video encoder
10937 20:16:52.360200 Bus info : platform:17020000.vcodec
10938 20:16:52.367040 Driver version : 6.1.80
10939 20:16:52.376757 Capabilities : 0x84204000
10940 20:16:52.388094 Video Memory-to-Memory Multiplanar
10941 20:16:52.399571 Streaming
10942 20:16:52.415469 Extended Pix Format
10943 20:16:52.427120 Device Capabilities
10944 20:16:52.436685 Device Caps : 0x04204000
10945 20:16:52.448153 Video Memory-to-Memory Multiplanar
10946 20:16:52.460744 Streaming
10947 20:16:52.474540 Extended Pix Format
10948 20:16:52.485107 Detected Stateful Encoder
10949 20:16:52.495912
10950 20:16:52.508749 Required ioctls:
10951 20:16:52.524238 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10952 20:16:52.524320 test VIDIOC_QUERYCAP: OK
10953 20:16:52.524561 Received signal: <TESTSET> START Required-ioctls
10954 20:16:52.524634 Starting test_set Required-ioctls
10955 20:16:52.552854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10956 20:16:52.553108 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10958 20:16:52.555821 test invalid ioctls: OK
10959 20:16:52.578225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10960 20:16:52.578308
10961 20:16:52.578542 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10963 20:16:52.588784 Allow for multiple opens:
10964 20:16:52.597952 <LAVA_SIGNAL_TESTSET STOP>
10965 20:16:52.598203 Received signal: <TESTSET> STOP
10966 20:16:52.598276 Closing test_set Required-ioctls
10967 20:16:52.608941 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10968 20:16:52.609192 Received signal: <TESTSET> START Allow-for-multiple-opens
10969 20:16:52.609262 Starting test_set Allow-for-multiple-opens
10970 20:16:52.612708 test second /dev/video2 open: OK
10971 20:16:52.632852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10972 20:16:52.633105 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10974 20:16:52.635936 test VIDIOC_QUERYCAP: OK
10975 20:16:52.657262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10976 20:16:52.657514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10978 20:16:52.660557 test VIDIOC_G/S_PRIORITY: OK
10979 20:16:52.680514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10980 20:16:52.680771 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10982 20:16:52.683667 test for unlimited opens: OK
10983 20:16:52.706151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10984 20:16:52.706233
10985 20:16:52.706468 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10987 20:16:52.716651 Debug ioctls:
10988 20:16:52.725860 <LAVA_SIGNAL_TESTSET STOP>
10989 20:16:52.726110 Received signal: <TESTSET> STOP
10990 20:16:52.726178 Closing test_set Allow-for-multiple-opens
10991 20:16:52.736546 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10992 20:16:52.736814 Received signal: <TESTSET> START Debug-ioctls
10993 20:16:52.736883 Starting test_set Debug-ioctls
10994 20:16:52.740157 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10995 20:16:52.762541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10996 20:16:52.762818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10998 20:16:52.769655 test VIDIOC_LOG_STATUS: OK (Not Supported)
10999 20:16:52.788910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11000 20:16:52.789021
11001 20:16:52.789267 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11003 20:16:52.799493 Input ioctls:
11004 20:16:52.809030 <LAVA_SIGNAL_TESTSET STOP>
11005 20:16:52.809349 Received signal: <TESTSET> STOP
11006 20:16:52.809426 Closing test_set Debug-ioctls
11007 20:16:52.820177 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11008 20:16:52.820434 Received signal: <TESTSET> START Input-ioctls
11009 20:16:52.820504 Starting test_set Input-ioctls
11010 20:16:52.823348 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11011 20:16:52.847834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11012 20:16:52.848116 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11014 20:16:52.851069 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11015 20:16:52.871119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11016 20:16:52.871418 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11018 20:16:52.877326 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11019 20:16:52.894753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11020 20:16:52.895052 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11022 20:16:52.901117 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11023 20:16:52.919561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11024 20:16:52.919852 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11026 20:16:52.922941 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11027 20:16:52.949605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11028 20:16:52.949910 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11030 20:16:52.953016 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11031 20:16:52.973792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11032 20:16:52.974100 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11034 20:16:52.977599 Inputs: 0 Audio Inputs: 0 Tuners: 0
11035 20:16:52.985125
11036 20:16:53.007981 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11037 20:16:53.030491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11038 20:16:53.030801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11040 20:16:53.038025 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11041 20:16:53.056431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11042 20:16:53.056741 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11044 20:16:53.063223 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11045 20:16:53.085547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11046 20:16:53.085856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11048 20:16:53.091805 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11049 20:16:53.112271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11050 20:16:53.112580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11052 20:16:53.118836 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11053 20:16:53.152429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11054 20:16:53.152752 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11056 20:16:53.155607
11057 20:16:53.173070 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11058 20:16:53.195478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11059 20:16:53.195793 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11061 20:16:53.201913 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11062 20:16:53.222908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11063 20:16:53.223235 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11065 20:16:53.226308 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11066 20:16:53.243445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11067 20:16:53.243759 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11069 20:16:53.250093 test VIDIOC_G/S_EDID: OK (Not Supported)
11070 20:16:53.271830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11071 20:16:53.271976
11072 20:16:53.272221 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11074 20:16:53.282976 Control ioctls:
11075 20:16:53.289307 <LAVA_SIGNAL_TESTSET STOP>
11076 20:16:53.289596 Received signal: <TESTSET> STOP
11077 20:16:53.289671 Closing test_set Input-ioctls
11078 20:16:53.298213 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11079 20:16:53.298486 Received signal: <TESTSET> START Control-ioctls
11080 20:16:53.298559 Starting test_set Control-ioctls
11081 20:16:53.301653 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11082 20:16:53.327304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11083 20:16:53.327484 test VIDIOC_QUERYCTRL: OK
11084 20:16:53.327731 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11086 20:16:53.347157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11087 20:16:53.347533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11089 20:16:53.350915 test VIDIOC_G/S_CTRL: OK
11090 20:16:53.376292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11091 20:16:53.376623 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11093 20:16:53.379331 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11094 20:16:53.401994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11095 20:16:53.402326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11097 20:16:53.411962 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11098 20:16:53.418962 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11099 20:16:53.445671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11100 20:16:53.446001 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11102 20:16:53.448934 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11103 20:16:53.467768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11104 20:16:53.468084 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11106 20:16:53.471033 Standard Controls: 16 Private Controls: 0
11107 20:16:53.478776
11108 20:16:53.492610 Format ioctls:
11109 20:16:53.500814 <LAVA_SIGNAL_TESTSET STOP>
11110 20:16:53.501127 Received signal: <TESTSET> STOP
11111 20:16:53.501200 Closing test_set Control-ioctls
11112 20:16:53.510551 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11113 20:16:53.510836 Received signal: <TESTSET> START Format-ioctls
11114 20:16:53.510908 Starting test_set Format-ioctls
11115 20:16:53.513779 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11116 20:16:53.560009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11117 20:16:53.560331 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11119 20:16:53.562856 test VIDIOC_G/S_PARM: OK
11120 20:16:53.584854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11121 20:16:53.585174 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11123 20:16:53.587961 test VIDIOC_G_FBUF: OK (Not Supported)
11124 20:16:53.615567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11125 20:16:53.615889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11127 20:16:53.618947 test VIDIOC_G_FMT: OK
11128 20:16:53.647817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11129 20:16:53.648175 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11131 20:16:53.651182 test VIDIOC_TRY_FMT: OK
11132 20:16:53.678869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11133 20:16:53.679196 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11135 20:16:53.688847 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11136 20:16:53.693618 test VIDIOC_S_FMT: FAIL
11137 20:16:53.719424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11138 20:16:53.719747 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11140 20:16:53.722472 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11141 20:16:53.744288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11142 20:16:53.744620 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11144 20:16:53.747765 test Cropping: OK
11145 20:16:53.774057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11146 20:16:53.774383 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11148 20:16:53.777578 test Composing: OK (Not Supported)
11149 20:16:53.804258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11150 20:16:53.804582 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11152 20:16:53.807437 test Scaling: OK (Not Supported)
11153 20:16:53.831271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11154 20:16:53.831427
11155 20:16:53.831674 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11157 20:16:53.841558 Codec ioctls:
11158 20:16:53.850805 <LAVA_SIGNAL_TESTSET STOP>
11159 20:16:53.851118 Received signal: <TESTSET> STOP
11160 20:16:53.851190 Closing test_set Format-ioctls
11161 20:16:53.861098 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11162 20:16:53.861394 Received signal: <TESTSET> START Codec-ioctls
11163 20:16:53.861469 Starting test_set Codec-ioctls
11164 20:16:53.864686 test VIDIOC_(TRY_)ENCODER_CMD: OK
11165 20:16:53.886325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11166 20:16:53.886649 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11168 20:16:53.893019 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11169 20:16:53.911727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11170 20:16:53.912049 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11172 20:16:53.918998 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11173 20:16:53.936555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11174 20:16:53.936702
11175 20:16:53.936945 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11177 20:16:53.945235 Buffer ioctls:
11178 20:16:53.951941 <LAVA_SIGNAL_TESTSET STOP>
11179 20:16:53.952269 Received signal: <TESTSET> STOP
11180 20:16:53.952347 Closing test_set Codec-ioctls
11181 20:16:53.961805 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11182 20:16:53.962100 Received signal: <TESTSET> START Buffer-ioctls
11183 20:16:53.962177 Starting test_set Buffer-ioctls
11184 20:16:53.964976 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11185 20:16:53.990918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11186 20:16:53.991078 test VIDIOC_EXPBUF: OK
11187 20:16:53.991325 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11189 20:16:54.011638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11190 20:16:54.011968 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11192 20:16:54.014038 test Requests: OK (Not Supported)
11193 20:16:54.035927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11194 20:16:54.036075
11195 20:16:54.036318 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11197 20:16:54.051604 Test input 0:
11198 20:16:54.061886
11199 20:16:54.077700 Streaming ioctls:
11200 20:16:54.084557 <LAVA_SIGNAL_TESTSET STOP>
11201 20:16:54.084855 Received signal: <TESTSET> STOP
11202 20:16:54.084933 Closing test_set Buffer-ioctls
11203 20:16:54.093994 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11204 20:16:54.094287 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11205 20:16:54.094363 Starting test_set Streaming-ioctls_Test-input-0
11206 20:16:54.097110 test read/write: OK (Not Supported)
11207 20:16:54.120894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11208 20:16:54.121221 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11210 20:16:54.126947 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11211 20:16:54.138625 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11212 20:16:54.143139 test blocking wait: FAIL
11213 20:16:54.168445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11214 20:16:54.168772 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11216 20:16:54.178566 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11217 20:16:54.181807 test MMAP (select): FAIL
11218 20:16:54.206526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11219 20:16:54.206855 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11221 20:16:54.213210 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11222 20:16:54.216650 test MMAP (epoll): FAIL
11223 20:16:54.247508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11224 20:16:54.247836 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11226 20:16:54.256878 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11227 20:16:54.263034 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11228 20:16:54.267050 test USERPTR (select): FAIL
11229 20:16:54.292590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11230 20:16:54.292919 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11232 20:16:54.299108 test DMABUF: Cannot test, specify --expbuf-device
11233 20:16:54.304320
11234 20:16:54.322833 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11235 20:16:54.328781 <LAVA_TEST_RUNNER EXIT>
11236 20:16:54.329076 ok: lava_test_shell seems to have completed
11237 20:16:54.329163 Marking unfinished test run as failed
11239 20:16:54.330048 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11240 20:16:54.330170 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11241 20:16:54.330256 end: 3 lava-test-retry (duration 00:00:03) [common]
11242 20:16:54.330343 start: 4 finalize (timeout 00:07:42) [common]
11243 20:16:54.330436 start: 4.1 power-off (timeout 00:00:30) [common]
11244 20:16:54.330629 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11245 20:16:54.407370 >> Command sent successfully.
11246 20:16:54.410970 Returned 0 in 0 seconds
11247 20:16:54.511462 end: 4.1 power-off (duration 00:00:00) [common]
11249 20:16:54.511796 start: 4.2 read-feedback (timeout 00:07:42) [common]
11250 20:16:54.512098 Listened to connection for namespace 'common' for up to 1s
11251 20:16:55.512997 Finalising connection for namespace 'common'
11252 20:16:55.513186 Disconnecting from shell: Finalise
11253 20:16:55.513266 / #
11254 20:16:55.613618 end: 4.2 read-feedback (duration 00:00:01) [common]
11255 20:16:55.613799 end: 4 finalize (duration 00:00:01) [common]
11256 20:16:55.613917 Cleaning after the job
11257 20:16:55.614021 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/ramdisk
11258 20:16:55.619698 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/kernel
11259 20:16:55.628726 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/dtb
11260 20:16:55.628958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928147/tftp-deploy-0_cc30s3/modules
11261 20:16:55.636466 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928147
11262 20:16:55.705136 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928147
11263 20:16:55.705320 Job finished correctly