Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 27
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 13
1 20:10:49.020909 lava-dispatcher, installed at version: 2024.01
2 20:10:49.021130 start: 0 validate
3 20:10:49.021261 Start time: 2024-03-03 20:10:49.021253+00:00 (UTC)
4 20:10:49.021393 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:10:49.021563 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 20:10:49.291492 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:10:49.292161 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:11:10.580271 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:11:10.580539 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:11:10.841061 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:11:10.841833 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:11:18.610922 validate duration: 29.59
14 20:11:18.611204 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:11:18.611303 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:11:18.611389 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:11:18.611521 Not decompressing ramdisk as can be used compressed.
18 20:11:18.611605 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 20:11:18.611668 saving as /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/ramdisk/rootfs.cpio.gz
20 20:11:18.611732 total size: 8181372 (7 MB)
21 20:11:18.878761 progress 0 % (0 MB)
22 20:11:18.881175 progress 5 % (0 MB)
23 20:11:18.883386 progress 10 % (0 MB)
24 20:11:18.885714 progress 15 % (1 MB)
25 20:11:18.887837 progress 20 % (1 MB)
26 20:11:18.890155 progress 25 % (1 MB)
27 20:11:18.892261 progress 30 % (2 MB)
28 20:11:18.894770 progress 35 % (2 MB)
29 20:11:18.897018 progress 40 % (3 MB)
30 20:11:18.899324 progress 45 % (3 MB)
31 20:11:18.901425 progress 50 % (3 MB)
32 20:11:18.903669 progress 55 % (4 MB)
33 20:11:18.905732 progress 60 % (4 MB)
34 20:11:18.907974 progress 65 % (5 MB)
35 20:11:18.910038 progress 70 % (5 MB)
36 20:11:18.912252 progress 75 % (5 MB)
37 20:11:18.914324 progress 80 % (6 MB)
38 20:11:18.916547 progress 85 % (6 MB)
39 20:11:18.918826 progress 90 % (7 MB)
40 20:11:18.921060 progress 95 % (7 MB)
41 20:11:18.923180 progress 100 % (7 MB)
42 20:11:18.923386 7 MB downloaded in 0.31 s (25.04 MB/s)
43 20:11:18.923543 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:11:18.923786 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:11:18.923875 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:11:18.923964 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:11:18.924106 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:11:18.924176 saving as /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/kernel/Image
50 20:11:18.924238 total size: 51601920 (49 MB)
51 20:11:18.924301 No compression specified
52 20:11:18.925426 progress 0 % (0 MB)
53 20:11:18.939048 progress 5 % (2 MB)
54 20:11:18.952633 progress 10 % (4 MB)
55 20:11:18.966072 progress 15 % (7 MB)
56 20:11:18.979457 progress 20 % (9 MB)
57 20:11:18.992980 progress 25 % (12 MB)
58 20:11:19.006713 progress 30 % (14 MB)
59 20:11:19.020401 progress 35 % (17 MB)
60 20:11:19.033816 progress 40 % (19 MB)
61 20:11:19.047465 progress 45 % (22 MB)
62 20:11:19.061071 progress 50 % (24 MB)
63 20:11:19.074543 progress 55 % (27 MB)
64 20:11:19.087871 progress 60 % (29 MB)
65 20:11:19.101572 progress 65 % (32 MB)
66 20:11:19.115099 progress 70 % (34 MB)
67 20:11:19.128728 progress 75 % (36 MB)
68 20:11:19.145607 progress 80 % (39 MB)
69 20:11:19.159152 progress 85 % (41 MB)
70 20:11:19.172760 progress 90 % (44 MB)
71 20:11:19.186135 progress 95 % (46 MB)
72 20:11:19.199361 progress 100 % (49 MB)
73 20:11:19.199626 49 MB downloaded in 0.28 s (178.70 MB/s)
74 20:11:19.199783 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:11:19.200025 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:11:19.200114 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:11:19.200201 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:11:19.200346 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:11:19.200421 saving as /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/dtb/mt8192-asurada-spherion-r0.dtb
81 20:11:19.200483 total size: 47278 (0 MB)
82 20:11:19.200544 No compression specified
83 20:11:19.201682 progress 69 % (0 MB)
84 20:11:19.201964 progress 100 % (0 MB)
85 20:11:19.202122 0 MB downloaded in 0.00 s (27.54 MB/s)
86 20:11:19.202247 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:11:19.202470 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:11:19.202557 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:11:19.202640 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:11:19.202754 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:11:19.202823 saving as /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/modules/modules.tar
93 20:11:19.202884 total size: 8632284 (8 MB)
94 20:11:19.202946 Using unxz to decompress xz
95 20:11:19.207211 progress 0 % (0 MB)
96 20:11:19.227509 progress 5 % (0 MB)
97 20:11:19.251720 progress 10 % (0 MB)
98 20:11:19.277149 progress 15 % (1 MB)
99 20:11:19.301230 progress 20 % (1 MB)
100 20:11:19.325869 progress 25 % (2 MB)
101 20:11:19.352417 progress 30 % (2 MB)
102 20:11:19.378745 progress 35 % (2 MB)
103 20:11:19.404461 progress 40 % (3 MB)
104 20:11:19.428914 progress 45 % (3 MB)
105 20:11:19.453822 progress 50 % (4 MB)
106 20:11:19.478607 progress 55 % (4 MB)
107 20:11:19.503995 progress 60 % (4 MB)
108 20:11:19.528825 progress 65 % (5 MB)
109 20:11:19.553885 progress 70 % (5 MB)
110 20:11:19.579283 progress 75 % (6 MB)
111 20:11:19.605999 progress 80 % (6 MB)
112 20:11:19.631185 progress 85 % (7 MB)
113 20:11:19.658052 progress 90 % (7 MB)
114 20:11:19.687303 progress 95 % (7 MB)
115 20:11:19.716372 progress 100 % (8 MB)
116 20:11:19.721825 8 MB downloaded in 0.52 s (15.86 MB/s)
117 20:11:19.722101 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:11:19.722376 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:11:19.722484 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:11:19.722595 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:11:19.722680 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:11:19.722781 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:11:19.723013 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w
125 20:11:19.723149 makedir: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin
126 20:11:19.723251 makedir: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/tests
127 20:11:19.723350 makedir: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/results
128 20:11:19.723467 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-add-keys
129 20:11:19.723621 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-add-sources
130 20:11:19.723753 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-background-process-start
131 20:11:19.723884 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-background-process-stop
132 20:11:19.724015 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-common-functions
133 20:11:19.724141 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-echo-ipv4
134 20:11:19.724269 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-install-packages
135 20:11:19.724397 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-installed-packages
136 20:11:19.724525 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-os-build
137 20:11:19.724652 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-probe-channel
138 20:11:19.724780 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-probe-ip
139 20:11:19.724906 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-target-ip
140 20:11:19.725032 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-target-mac
141 20:11:19.725158 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-target-storage
142 20:11:19.725290 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-case
143 20:11:19.725418 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-event
144 20:11:19.725588 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-feedback
145 20:11:19.725714 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-raise
146 20:11:19.725840 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-reference
147 20:11:19.725966 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-runner
148 20:11:19.726091 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-set
149 20:11:19.726218 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-test-shell
150 20:11:19.726347 Updating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-install-packages (oe)
151 20:11:19.726502 Updating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/bin/lava-installed-packages (oe)
152 20:11:19.726628 Creating /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/environment
153 20:11:19.726728 LAVA metadata
154 20:11:19.726803 - LAVA_JOB_ID=12928138
155 20:11:19.726868 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:11:19.726975 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:11:19.727043 skipped lava-vland-overlay
158 20:11:19.727118 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:11:19.727199 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:11:19.727261 skipped lava-multinode-overlay
161 20:11:19.727336 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:11:19.727416 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:11:19.727492 Loading test definitions
164 20:11:19.727586 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 20:11:19.727661 Using /lava-12928138 at stage 0
166 20:11:19.727983 uuid=12928138_1.5.2.3.1 testdef=None
167 20:11:19.728071 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 20:11:19.728157 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 20:11:19.728747 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 20:11:19.728968 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 20:11:19.729662 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 20:11:19.729894 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 20:11:19.730547 runner path: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/0/tests/0_dmesg test_uuid 12928138_1.5.2.3.1
176 20:11:19.730709 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 20:11:19.730933 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 20:11:19.731004 Using /lava-12928138 at stage 1
180 20:11:19.731306 uuid=12928138_1.5.2.3.5 testdef=None
181 20:11:19.731394 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 20:11:19.731478 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 20:11:19.731954 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 20:11:19.732170 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 20:11:19.732855 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 20:11:19.733084 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 20:11:19.733834 runner path: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/1/tests/1_bootrr test_uuid 12928138_1.5.2.3.5
190 20:11:19.733987 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 20:11:19.734191 Creating lava-test-runner.conf files
193 20:11:19.734255 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/0 for stage 0
194 20:11:19.734346 - 0_dmesg
195 20:11:19.734473 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928138/lava-overlay-g33f7_6w/lava-12928138/1 for stage 1
196 20:11:19.734599 - 1_bootrr
197 20:11:19.734694 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 20:11:19.734780 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 20:11:19.743063 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 20:11:19.743188 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 20:11:19.743279 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 20:11:19.743366 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 20:11:19.743454 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 20:11:19.996077 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 20:11:19.996528 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 20:11:19.996648 extracting modules file /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928138/extract-overlay-ramdisk-z9v83989/ramdisk
207 20:11:20.217207 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 20:11:20.217380 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 20:11:20.217479 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928138/compress-overlay-ki4dx2y9/overlay-1.5.2.4.tar.gz to ramdisk
210 20:11:20.217584 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928138/compress-overlay-ki4dx2y9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928138/extract-overlay-ramdisk-z9v83989/ramdisk
211 20:11:20.225880 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 20:11:20.226006 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 20:11:20.226099 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 20:11:20.226191 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 20:11:20.226272 Building ramdisk /var/lib/lava/dispatcher/tmp/12928138/extract-overlay-ramdisk-z9v83989/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928138/extract-overlay-ramdisk-z9v83989/ramdisk
216 20:11:20.635276 >> 145368 blocks
217 20:11:22.963441 rename /var/lib/lava/dispatcher/tmp/12928138/extract-overlay-ramdisk-z9v83989/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/ramdisk/ramdisk.cpio.gz
218 20:11:22.963903 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 20:11:22.964028 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 20:11:22.964129 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 20:11:22.964245 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/kernel/Image'
222 20:11:36.030533 Returned 0 in 13 seconds
223 20:11:36.131202 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/kernel/image.itb
224 20:11:36.549601 output: FIT description: Kernel Image image with one or more FDT blobs
225 20:11:36.549980 output: Created: Sun Mar 3 20:11:36 2024
226 20:11:36.550055 output: Image 0 (kernel-1)
227 20:11:36.550121 output: Description:
228 20:11:36.550245 output: Created: Sun Mar 3 20:11:36 2024
229 20:11:36.550394 output: Type: Kernel Image
230 20:11:36.550480 output: Compression: lzma compressed
231 20:11:36.550544 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
232 20:11:36.550607 output: Architecture: AArch64
233 20:11:36.550669 output: OS: Linux
234 20:11:36.550726 output: Load Address: 0x00000000
235 20:11:36.550788 output: Entry Point: 0x00000000
236 20:11:36.550849 output: Hash algo: crc32
237 20:11:36.550912 output: Hash value: 91cb1a17
238 20:11:36.550968 output: Image 1 (fdt-1)
239 20:11:36.551026 output: Description: mt8192-asurada-spherion-r0
240 20:11:36.551084 output: Created: Sun Mar 3 20:11:36 2024
241 20:11:36.551139 output: Type: Flat Device Tree
242 20:11:36.551193 output: Compression: uncompressed
243 20:11:36.551247 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 20:11:36.551301 output: Architecture: AArch64
245 20:11:36.551355 output: Hash algo: crc32
246 20:11:36.551408 output: Hash value: cc4352de
247 20:11:36.551462 output: Image 2 (ramdisk-1)
248 20:11:36.551515 output: Description: unavailable
249 20:11:36.551568 output: Created: Sun Mar 3 20:11:36 2024
250 20:11:36.551622 output: Type: RAMDisk Image
251 20:11:36.551675 output: Compression: Unknown Compression
252 20:11:36.551729 output: Data Size: 21401675 Bytes = 20900.07 KiB = 20.41 MiB
253 20:11:36.551783 output: Architecture: AArch64
254 20:11:36.551836 output: OS: Linux
255 20:11:36.551889 output: Load Address: unavailable
256 20:11:36.551942 output: Entry Point: unavailable
257 20:11:36.551995 output: Hash algo: crc32
258 20:11:36.552049 output: Hash value: d54f3693
259 20:11:36.552103 output: Default Configuration: 'conf-1'
260 20:11:36.552156 output: Configuration 0 (conf-1)
261 20:11:36.552209 output: Description: mt8192-asurada-spherion-r0
262 20:11:36.552262 output: Kernel: kernel-1
263 20:11:36.552316 output: Init Ramdisk: ramdisk-1
264 20:11:36.552369 output: FDT: fdt-1
265 20:11:36.552423 output: Loadables: kernel-1
266 20:11:36.552475 output:
267 20:11:36.552684 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 20:11:36.552787 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 20:11:36.552892 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 20:11:36.552994 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 20:11:36.553078 No LXC device requested
272 20:11:36.553160 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 20:11:36.553244 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 20:11:36.553324 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 20:11:36.553398 Checking files for TFTP limit of 4294967296 bytes.
276 20:11:36.554073 end: 1 tftp-deploy (duration 00:00:18) [common]
277 20:11:36.554215 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 20:11:36.554391 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 20:11:36.554525 substitutions:
280 20:11:36.554595 - {DTB}: 12928138/tftp-deploy-9cf_hi8c/dtb/mt8192-asurada-spherion-r0.dtb
281 20:11:36.554660 - {INITRD}: 12928138/tftp-deploy-9cf_hi8c/ramdisk/ramdisk.cpio.gz
282 20:11:36.554721 - {KERNEL}: 12928138/tftp-deploy-9cf_hi8c/kernel/Image
283 20:11:36.554780 - {LAVA_MAC}: None
284 20:11:36.554837 - {PRESEED_CONFIG}: None
285 20:11:36.554895 - {PRESEED_LOCAL}: None
286 20:11:36.554951 - {RAMDISK}: 12928138/tftp-deploy-9cf_hi8c/ramdisk/ramdisk.cpio.gz
287 20:11:36.555006 - {ROOT_PART}: None
288 20:11:36.555061 - {ROOT}: None
289 20:11:36.555116 - {SERVER_IP}: 192.168.201.1
290 20:11:36.555171 - {TEE}: None
291 20:11:36.555224 Parsed boot commands:
292 20:11:36.555278 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 20:11:36.555465 Parsed boot commands: tftpboot 192.168.201.1 12928138/tftp-deploy-9cf_hi8c/kernel/image.itb 12928138/tftp-deploy-9cf_hi8c/kernel/cmdline
294 20:11:36.555556 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 20:11:36.555644 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 20:11:36.555739 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 20:11:36.555825 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 20:11:36.555896 Not connected, no need to disconnect.
299 20:11:36.555970 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 20:11:36.556054 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 20:11:36.556125 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
302 20:11:36.560294 Setting prompt string to ['lava-test: # ']
303 20:11:36.560732 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 20:11:36.560848 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 20:11:36.560968 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 20:11:36.561093 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 20:11:36.561546 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
308 20:11:41.696250 >> Command sent successfully.
309 20:11:41.698726 Returned 0 in 5 seconds
310 20:11:41.799150 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 20:11:41.799485 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 20:11:41.799586 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 20:11:41.799677 Setting prompt string to 'Starting depthcharge on Spherion...'
315 20:11:41.799746 Changing prompt to 'Starting depthcharge on Spherion...'
316 20:11:41.799816 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 20:11:41.800102 [Enter `^Ec?' for help]
318 20:11:41.971013
319 20:11:41.971174
320 20:11:41.971248 F0: 102B 0000
321 20:11:41.971316
322 20:11:41.971381 F3: 1001 0000 [0200]
323 20:11:41.971442
324 20:11:41.974599 F3: 1001 0000
325 20:11:41.974688
326 20:11:41.974755 F7: 102D 0000
327 20:11:41.974819
328 20:11:41.974879 F1: 0000 0000
329 20:11:41.978238
330 20:11:41.978323 V0: 0000 0000 [0001]
331 20:11:41.978394
332 20:11:41.978457 00: 0007 8000
333 20:11:41.978521
334 20:11:41.982208 01: 0000 0000
335 20:11:41.982295
336 20:11:41.982362 BP: 0C00 0209 [0000]
337 20:11:41.982425
338 20:11:41.985703 G0: 1182 0000
339 20:11:41.985788
340 20:11:41.985859 EC: 0000 0021 [4000]
341 20:11:41.985922
342 20:11:41.989241 S7: 0000 0000 [0000]
343 20:11:41.989325
344 20:11:41.989393 CC: 0000 0000 [0001]
345 20:11:41.989456
346 20:11:41.992480 T0: 0000 0040 [010F]
347 20:11:41.992584
348 20:11:41.992701 Jump to BL
349 20:11:41.992778
350 20:11:42.017847
351 20:11:42.017999
352 20:11:42.018068
353 20:11:42.025461 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 20:11:42.029467 ARM64: Exception handlers installed.
355 20:11:42.032868 ARM64: Testing exception
356 20:11:42.036285 ARM64: Done test exception
357 20:11:42.043532 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 20:11:42.050690 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 20:11:42.057902 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 20:11:42.068715 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 20:11:42.075056 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 20:11:42.085719 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 20:11:42.096553 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 20:11:42.102795 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 20:11:42.120703 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 20:11:42.124074 WDT: Last reset was cold boot
367 20:11:42.127412 SPI1(PAD0) initialized at 2873684 Hz
368 20:11:42.130576 SPI5(PAD0) initialized at 992727 Hz
369 20:11:42.134136 VBOOT: Loading verstage.
370 20:11:42.140717 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 20:11:42.144140 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 20:11:42.147570 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 20:11:42.150714 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 20:11:42.158119 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 20:11:42.164740 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 20:11:42.175835 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
377 20:11:42.175925
378 20:11:42.175993
379 20:11:42.185796 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 20:11:42.188869 ARM64: Exception handlers installed.
381 20:11:42.192372 ARM64: Testing exception
382 20:11:42.192456 ARM64: Done test exception
383 20:11:42.199131 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 20:11:42.202296 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 20:11:42.216657 Probing TPM: . done!
386 20:11:42.216744 TPM ready after 0 ms
387 20:11:42.223519 Connected to device vid:did:rid of 1ae0:0028:00
388 20:11:42.230441 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 20:11:42.271653 Initialized TPM device CR50 revision 0
390 20:11:42.283342 tlcl_send_startup: Startup return code is 0
391 20:11:42.283438 TPM: setup succeeded
392 20:11:42.294652 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 20:11:42.303783 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 20:11:42.315473 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 20:11:42.324750 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 20:11:42.328328 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 20:11:42.332900 in-header: 03 07 00 00 08 00 00 00
398 20:11:42.336709 in-data: aa e4 47 04 13 02 00 00
399 20:11:42.340288 Chrome EC: UHEPI supported
400 20:11:42.347330 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 20:11:42.351030 in-header: 03 9d 00 00 08 00 00 00
402 20:11:42.354744 in-data: 10 20 20 08 00 00 00 00
403 20:11:42.354834 Phase 1
404 20:11:42.358378 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 20:11:42.365712 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 20:11:42.372812 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 20:11:42.372903 Recovery requested (1009000e)
408 20:11:42.381246 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 20:11:42.386707 tlcl_extend: response is 0
410 20:11:42.394843 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 20:11:42.400243 tlcl_extend: response is 0
412 20:11:42.407085 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 20:11:42.428039 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
414 20:11:42.435234 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 20:11:42.435325
416 20:11:42.435414
417 20:11:42.442534 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 20:11:42.446385 ARM64: Exception handlers installed.
419 20:11:42.450011 ARM64: Testing exception
420 20:11:42.453351 ARM64: Done test exception
421 20:11:42.473095 pmic_efuse_setting: Set efuses in 11 msecs
422 20:11:42.476709 pmwrap_interface_init: Select PMIF_VLD_RDY
423 20:11:42.484106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 20:11:42.487694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 20:11:42.491307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 20:11:42.495133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 20:11:42.502363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 20:11:42.506084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 20:11:42.509766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 20:11:42.516899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 20:11:42.520149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 20:11:42.523314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 20:11:42.529998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 20:11:42.533408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 20:11:42.540119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 20:11:42.543540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 20:11:42.550061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 20:11:42.556777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 20:11:42.563687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 20:11:42.566986 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 20:11:42.573789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 20:11:42.581094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 20:11:42.584417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 20:11:42.591574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 20:11:42.594823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 20:11:42.601991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 20:11:42.605741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 20:11:42.612079 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 20:11:42.618865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 20:11:42.622272 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 20:11:42.625449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 20:11:42.633450 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 20:11:42.637057 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 20:11:42.640935 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 20:11:42.648571 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 20:11:42.652068 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 20:11:42.655712 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 20:11:42.663183 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 20:11:42.666363 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 20:11:42.673232 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 20:11:42.676559 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 20:11:42.679722 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 20:11:42.686296 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 20:11:42.689676 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 20:11:42.692915 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 20:11:42.699623 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 20:11:42.702929 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 20:11:42.705987 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 20:11:42.709650 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 20:11:42.716354 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 20:11:42.719607 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 20:11:42.722951 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 20:11:42.726342 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 20:11:42.736490 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 20:11:42.743055 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 20:11:42.749374 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 20:11:42.756463 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 20:11:42.766315 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 20:11:42.769786 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 20:11:42.772712 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 20:11:42.779433 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 20:11:42.786168 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xe
483 20:11:42.792992 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 20:11:42.796326 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 20:11:42.799563 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 20:11:42.810087 [RTC]rtc_get_frequency_meter,154: input=15, output=794
487 20:11:42.813174 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
488 20:11:42.820105 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
489 20:11:42.823126 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
490 20:11:42.826562 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
491 20:11:42.829792 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
492 20:11:42.833248 ADC[4]: Raw value=898150 ID=7
493 20:11:42.836816 ADC[3]: Raw value=212700 ID=1
494 20:11:42.836926 RAM Code: 0x71
495 20:11:42.843286 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
496 20:11:42.846763 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
497 20:11:42.857299 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
498 20:11:42.863857 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
499 20:11:42.867075 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
500 20:11:42.870581 in-header: 03 07 00 00 08 00 00 00
501 20:11:42.873775 in-data: aa e4 47 04 13 02 00 00
502 20:11:42.877190 Chrome EC: UHEPI supported
503 20:11:42.880804 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
504 20:11:42.885173 in-header: 03 d5 00 00 08 00 00 00
505 20:11:42.889097 in-data: 98 20 60 08 00 00 00 00
506 20:11:42.892634 MRC: failed to locate region type 0.
507 20:11:42.899196 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
508 20:11:42.902759 DRAM-K: Running full calibration
509 20:11:42.909355 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
510 20:11:42.909499 header.status = 0x0
511 20:11:42.912538 header.version = 0x6 (expected: 0x6)
512 20:11:42.915828 header.size = 0xd00 (expected: 0xd00)
513 20:11:42.919456 header.flags = 0x0
514 20:11:42.926585 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
515 20:11:42.942467 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
516 20:11:42.949221 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
517 20:11:42.952304 dram_init: ddr_geometry: 2
518 20:11:42.955683 [EMI] MDL number = 2
519 20:11:42.955796 [EMI] Get MDL freq = 0
520 20:11:42.959250 dram_init: ddr_type: 0
521 20:11:42.959360 is_discrete_lpddr4: 1
522 20:11:42.962429 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
523 20:11:42.962539
524 20:11:42.962634
525 20:11:42.965806 [Bian_co] ETT version 0.0.0.1
526 20:11:42.972374 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
527 20:11:42.972490
528 20:11:42.975573 dramc_set_vcore_voltage set vcore to 650000
529 20:11:42.978930 Read voltage for 800, 4
530 20:11:42.979041 Vio18 = 0
531 20:11:42.979139 Vcore = 650000
532 20:11:42.982281 Vdram = 0
533 20:11:42.982391 Vddq = 0
534 20:11:42.982487 Vmddr = 0
535 20:11:42.985830 dram_init: config_dvfs: 1
536 20:11:42.988955 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
537 20:11:42.995821 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
538 20:11:42.999140 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
539 20:11:43.002357 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
540 20:11:43.005820 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
541 20:11:43.008825 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
542 20:11:43.012233 MEM_TYPE=3, freq_sel=18
543 20:11:43.015705 sv_algorithm_assistance_LP4_1600
544 20:11:43.019228 ============ PULL DRAM RESETB DOWN ============
545 20:11:43.022481 ========== PULL DRAM RESETB DOWN end =========
546 20:11:43.029278 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
547 20:11:43.032445 ===================================
548 20:11:43.035885 LPDDR4 DRAM CONFIGURATION
549 20:11:43.036001 ===================================
550 20:11:43.039263 EX_ROW_EN[0] = 0x0
551 20:11:43.042580 EX_ROW_EN[1] = 0x0
552 20:11:43.042693 LP4Y_EN = 0x0
553 20:11:43.045726 WORK_FSP = 0x0
554 20:11:43.045839 WL = 0x2
555 20:11:43.049430 RL = 0x2
556 20:11:43.049546 BL = 0x2
557 20:11:43.052607 RPST = 0x0
558 20:11:43.052716 RD_PRE = 0x0
559 20:11:43.055962 WR_PRE = 0x1
560 20:11:43.056071 WR_PST = 0x0
561 20:11:43.059445 DBI_WR = 0x0
562 20:11:43.059549 DBI_RD = 0x0
563 20:11:43.062464 OTF = 0x1
564 20:11:43.065828 ===================================
565 20:11:43.069149 ===================================
566 20:11:43.069261 ANA top config
567 20:11:43.072623 ===================================
568 20:11:43.075826 DLL_ASYNC_EN = 0
569 20:11:43.079053 ALL_SLAVE_EN = 1
570 20:11:43.082478 NEW_RANK_MODE = 1
571 20:11:43.082592 DLL_IDLE_MODE = 1
572 20:11:43.085724 LP45_APHY_COMB_EN = 1
573 20:11:43.088897 TX_ODT_DIS = 1
574 20:11:43.092243 NEW_8X_MODE = 1
575 20:11:43.095530 ===================================
576 20:11:43.099037 ===================================
577 20:11:43.102071 data_rate = 1600
578 20:11:43.102182 CKR = 1
579 20:11:43.105353 DQ_P2S_RATIO = 8
580 20:11:43.108950 ===================================
581 20:11:43.112257 CA_P2S_RATIO = 8
582 20:11:43.115496 DQ_CA_OPEN = 0
583 20:11:43.118623 DQ_SEMI_OPEN = 0
584 20:11:43.122265 CA_SEMI_OPEN = 0
585 20:11:43.122376 CA_FULL_RATE = 0
586 20:11:43.125639 DQ_CKDIV4_EN = 1
587 20:11:43.128685 CA_CKDIV4_EN = 1
588 20:11:43.132309 CA_PREDIV_EN = 0
589 20:11:43.135516 PH8_DLY = 0
590 20:11:43.138861 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
591 20:11:43.138970 DQ_AAMCK_DIV = 4
592 20:11:43.142109 CA_AAMCK_DIV = 4
593 20:11:43.145344 CA_ADMCK_DIV = 4
594 20:11:43.148981 DQ_TRACK_CA_EN = 0
595 20:11:43.152331 CA_PICK = 800
596 20:11:43.155644 CA_MCKIO = 800
597 20:11:43.155753 MCKIO_SEMI = 0
598 20:11:43.159075 PLL_FREQ = 3068
599 20:11:43.163244 DQ_UI_PI_RATIO = 32
600 20:11:43.166608 CA_UI_PI_RATIO = 0
601 20:11:43.170374 ===================================
602 20:11:43.174099 ===================================
603 20:11:43.174211 memory_type:LPDDR4
604 20:11:43.178333 GP_NUM : 10
605 20:11:43.178442 SRAM_EN : 1
606 20:11:43.181968 MD32_EN : 0
607 20:11:43.185500 ===================================
608 20:11:43.185623 [ANA_INIT] >>>>>>>>>>>>>>
609 20:11:43.189444 <<<<<< [CONFIGURE PHASE]: ANA_TX
610 20:11:43.193242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
611 20:11:43.196407 ===================================
612 20:11:43.200057 data_rate = 1600,PCW = 0X7600
613 20:11:43.204019 ===================================
614 20:11:43.204136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
615 20:11:43.211097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
616 20:11:43.214898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
617 20:11:43.221924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
618 20:11:43.225925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
619 20:11:43.229659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
620 20:11:43.229775 [ANA_INIT] flow start
621 20:11:43.233046 [ANA_INIT] PLL >>>>>>>>
622 20:11:43.233156 [ANA_INIT] PLL <<<<<<<<
623 20:11:43.236807 [ANA_INIT] MIDPI >>>>>>>>
624 20:11:43.240281 [ANA_INIT] MIDPI <<<<<<<<
625 20:11:43.240392 [ANA_INIT] DLL >>>>>>>>
626 20:11:43.243718 [ANA_INIT] flow end
627 20:11:43.247528 ============ LP4 DIFF to SE enter ============
628 20:11:43.251257 ============ LP4 DIFF to SE exit ============
629 20:11:43.255206 [ANA_INIT] <<<<<<<<<<<<<
630 20:11:43.258856 [Flow] Enable top DCM control >>>>>
631 20:11:43.262481 [Flow] Enable top DCM control <<<<<
632 20:11:43.262591 Enable DLL master slave shuffle
633 20:11:43.269738 ==============================================================
634 20:11:43.269859 Gating Mode config
635 20:11:43.277268 ==============================================================
636 20:11:43.277386 Config description:
637 20:11:43.288291 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
638 20:11:43.295220 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
639 20:11:43.298547 SELPH_MODE 0: By rank 1: By Phase
640 20:11:43.305014 ==============================================================
641 20:11:43.308299 GAT_TRACK_EN = 1
642 20:11:43.312019 RX_GATING_MODE = 2
643 20:11:43.315044 RX_GATING_TRACK_MODE = 2
644 20:11:43.318436 SELPH_MODE = 1
645 20:11:43.318546 PICG_EARLY_EN = 1
646 20:11:43.321694 VALID_LAT_VALUE = 1
647 20:11:43.328369 ==============================================================
648 20:11:43.331861 Enter into Gating configuration >>>>
649 20:11:43.335003 Exit from Gating configuration <<<<
650 20:11:43.338430 Enter into DVFS_PRE_config >>>>>
651 20:11:43.348341 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
652 20:11:43.351698 Exit from DVFS_PRE_config <<<<<
653 20:11:43.355112 Enter into PICG configuration >>>>
654 20:11:43.358180 Exit from PICG configuration <<<<
655 20:11:43.361424 [RX_INPUT] configuration >>>>>
656 20:11:43.364998 [RX_INPUT] configuration <<<<<
657 20:11:43.368171 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
658 20:11:43.374751 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
659 20:11:43.381465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
660 20:11:43.388217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
661 20:11:43.394837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
662 20:11:43.397994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
663 20:11:43.404828 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
664 20:11:43.408006 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
665 20:11:43.411132 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
666 20:11:43.414427 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
667 20:11:43.421530 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
668 20:11:43.424457 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
669 20:11:43.427836 ===================================
670 20:11:43.431426 LPDDR4 DRAM CONFIGURATION
671 20:11:43.434645 ===================================
672 20:11:43.434729 EX_ROW_EN[0] = 0x0
673 20:11:43.437882 EX_ROW_EN[1] = 0x0
674 20:11:43.437966 LP4Y_EN = 0x0
675 20:11:43.441228 WORK_FSP = 0x0
676 20:11:43.441311 WL = 0x2
677 20:11:43.444622 RL = 0x2
678 20:11:43.444706 BL = 0x2
679 20:11:43.448004 RPST = 0x0
680 20:11:43.448088 RD_PRE = 0x0
681 20:11:43.451024 WR_PRE = 0x1
682 20:11:43.451107 WR_PST = 0x0
683 20:11:43.454704 DBI_WR = 0x0
684 20:11:43.454788 DBI_RD = 0x0
685 20:11:43.457819 OTF = 0x1
686 20:11:43.461437 ===================================
687 20:11:43.464640 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
688 20:11:43.467827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
689 20:11:43.474857 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 20:11:43.478018 ===================================
691 20:11:43.478136 LPDDR4 DRAM CONFIGURATION
692 20:11:43.481269 ===================================
693 20:11:43.484579 EX_ROW_EN[0] = 0x10
694 20:11:43.487925 EX_ROW_EN[1] = 0x0
695 20:11:43.488018 LP4Y_EN = 0x0
696 20:11:43.491288 WORK_FSP = 0x0
697 20:11:43.491376 WL = 0x2
698 20:11:43.494657 RL = 0x2
699 20:11:43.494746 BL = 0x2
700 20:11:43.498170 RPST = 0x0
701 20:11:43.498270 RD_PRE = 0x0
702 20:11:43.501252 WR_PRE = 0x1
703 20:11:43.501359 WR_PST = 0x0
704 20:11:43.504680 DBI_WR = 0x0
705 20:11:43.504764 DBI_RD = 0x0
706 20:11:43.507980 OTF = 0x1
707 20:11:43.511400 ===================================
708 20:11:43.517872 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
709 20:11:43.521430 nWR fixed to 40
710 20:11:43.524403 [ModeRegInit_LP4] CH0 RK0
711 20:11:43.524487 [ModeRegInit_LP4] CH0 RK1
712 20:11:43.527922 [ModeRegInit_LP4] CH1 RK0
713 20:11:43.531141 [ModeRegInit_LP4] CH1 RK1
714 20:11:43.531226 match AC timing 13
715 20:11:43.537963 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
716 20:11:43.541163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
717 20:11:43.544451 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
718 20:11:43.551355 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
719 20:11:43.554446 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
720 20:11:43.554530 [EMI DOE] emi_dcm 0
721 20:11:43.561252 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
722 20:11:43.561336 ==
723 20:11:43.564656 Dram Type= 6, Freq= 0, CH_0, rank 0
724 20:11:43.567940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
725 20:11:43.568070 ==
726 20:11:43.574804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
727 20:11:43.578009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
728 20:11:43.588373 [CA 0] Center 38 (7~69) winsize 63
729 20:11:43.591847 [CA 1] Center 37 (7~68) winsize 62
730 20:11:43.595049 [CA 2] Center 35 (5~66) winsize 62
731 20:11:43.598248 [CA 3] Center 35 (5~66) winsize 62
732 20:11:43.601429 [CA 4] Center 34 (4~65) winsize 62
733 20:11:43.605068 [CA 5] Center 34 (3~65) winsize 63
734 20:11:43.605152
735 20:11:43.608414 [CmdBusTrainingLP45] Vref(ca) range 1: 34
736 20:11:43.608498
737 20:11:43.611624 [CATrainingPosCal] consider 1 rank data
738 20:11:43.614889 u2DelayCellTimex100 = 270/100 ps
739 20:11:43.618423 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
740 20:11:43.621959 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
741 20:11:43.628407 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
742 20:11:43.631672 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
743 20:11:43.634905 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
744 20:11:43.638276 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
745 20:11:43.638360
746 20:11:43.641754 CA PerBit enable=1, Macro0, CA PI delay=34
747 20:11:43.641838
748 20:11:43.644904 [CBTSetCACLKResult] CA Dly = 34
749 20:11:43.644986 CS Dly: 6 (0~37)
750 20:11:43.648257 ==
751 20:11:43.648341 Dram Type= 6, Freq= 0, CH_0, rank 1
752 20:11:43.654782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 20:11:43.654866 ==
754 20:11:43.658283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 20:11:43.664948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 20:11:43.674753 [CA 0] Center 38 (7~69) winsize 63
757 20:11:43.677966 [CA 1] Center 37 (7~68) winsize 62
758 20:11:43.681366 [CA 2] Center 35 (5~66) winsize 62
759 20:11:43.684593 [CA 3] Center 35 (5~66) winsize 62
760 20:11:43.687945 [CA 4] Center 34 (4~65) winsize 62
761 20:11:43.691439 [CA 5] Center 34 (4~65) winsize 62
762 20:11:43.691523
763 20:11:43.694838 [CmdBusTrainingLP45] Vref(ca) range 1: 30
764 20:11:43.694922
765 20:11:43.698554 [CATrainingPosCal] consider 2 rank data
766 20:11:43.702117 u2DelayCellTimex100 = 270/100 ps
767 20:11:43.705645 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
768 20:11:43.709372 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
769 20:11:43.712943 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
770 20:11:43.716500 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
771 20:11:43.720457 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
772 20:11:43.723882 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
773 20:11:43.723966
774 20:11:43.727565 CA PerBit enable=1, Macro0, CA PI delay=34
775 20:11:43.727650
776 20:11:43.731363 [CBTSetCACLKResult] CA Dly = 34
777 20:11:43.731447 CS Dly: 6 (0~38)
778 20:11:43.731513
779 20:11:43.734751 ----->DramcWriteLeveling(PI) begin...
780 20:11:43.734878 ==
781 20:11:43.738451 Dram Type= 6, Freq= 0, CH_0, rank 0
782 20:11:43.742309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 20:11:43.745749 ==
784 20:11:43.745884 Write leveling (Byte 0): 32 => 32
785 20:11:43.749756 Write leveling (Byte 1): 31 => 31
786 20:11:43.753435 DramcWriteLeveling(PI) end<-----
787 20:11:43.753529
788 20:11:43.753597 ==
789 20:11:43.757148 Dram Type= 6, Freq= 0, CH_0, rank 0
790 20:11:43.760687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
791 20:11:43.760772 ==
792 20:11:43.764469 [Gating] SW mode calibration
793 20:11:43.771731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
794 20:11:43.775435 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
795 20:11:43.779017 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
796 20:11:43.786605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
797 20:11:43.790106 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
798 20:11:43.793714 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 20:11:43.797421 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 20:11:43.801219 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 20:11:43.808988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 20:11:43.812142 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 20:11:43.816254 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 20:11:43.819523 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 20:11:43.823608 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 20:11:43.830939 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 20:11:43.834613 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 20:11:43.838229 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 20:11:43.841549 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 20:11:43.845429 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 20:11:43.852791 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 20:11:43.856525 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 20:11:43.860032 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
814 20:11:43.863771 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
815 20:11:43.867543 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 20:11:43.874822 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 20:11:43.878589 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 20:11:43.881842 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 20:11:43.885878 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 20:11:43.889351 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 20:11:43.896482 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 20:11:43.900534 0 9 12 | B1->B0 | 2727 3333 | 1 0 | (0 0) (1 1)
823 20:11:43.904024 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 20:11:43.907666 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 20:11:43.911241 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 20:11:43.918712 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
827 20:11:43.922333 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 20:11:43.925872 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 20:11:43.929642 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
830 20:11:43.933470 0 10 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
831 20:11:43.936970 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 20:11:43.944513 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 20:11:43.948097 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 20:11:43.951997 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 20:11:43.955453 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 20:11:43.959139 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 20:11:43.966404 0 11 8 | B1->B0 | 2424 2525 | 1 0 | (0 0) (0 0)
838 20:11:43.970389 0 11 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
839 20:11:43.974005 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 20:11:43.977534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 20:11:43.981254 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 20:11:43.988610 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
843 20:11:43.992395 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 20:11:43.996192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 20:11:43.999897 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
846 20:11:44.003561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
847 20:11:44.007407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 20:11:44.014730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 20:11:44.018442 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 20:11:44.022036 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 20:11:44.025339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 20:11:44.032132 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 20:11:44.035510 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 20:11:44.038778 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 20:11:44.045327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 20:11:44.048727 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 20:11:44.051958 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 20:11:44.058558 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 20:11:44.062125 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 20:11:44.065390 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 20:11:44.068942 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
862 20:11:44.075499 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 20:11:44.078953 Total UI for P1: 0, mck2ui 16
864 20:11:44.082211 best dqsien dly found for B0: ( 0, 14, 8)
865 20:11:44.085616 Total UI for P1: 0, mck2ui 16
866 20:11:44.089046 best dqsien dly found for B1: ( 0, 14, 10)
867 20:11:44.092305 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
868 20:11:44.095688 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
869 20:11:44.095772
870 20:11:44.099080 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
871 20:11:44.102354 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
872 20:11:44.105793 [Gating] SW calibration Done
873 20:11:44.105877 ==
874 20:11:44.108984 Dram Type= 6, Freq= 0, CH_0, rank 0
875 20:11:44.112147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
876 20:11:44.112232 ==
877 20:11:44.115455 RX Vref Scan: 0
878 20:11:44.115539
879 20:11:44.115605 RX Vref 0 -> 0, step: 1
880 20:11:44.115667
881 20:11:44.119041 RX Delay -130 -> 252, step: 16
882 20:11:44.125289 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
883 20:11:44.128621 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
884 20:11:44.132023 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
885 20:11:44.135450 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
886 20:11:44.138862 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
887 20:11:44.142216 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
888 20:11:44.148546 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
889 20:11:44.151949 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
890 20:11:44.155371 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
891 20:11:44.158667 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
892 20:11:44.164951 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
893 20:11:44.168459 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
894 20:11:44.171770 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
895 20:11:44.175186 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
896 20:11:44.178454 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
897 20:11:44.185164 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
898 20:11:44.185375 ==
899 20:11:44.188546 Dram Type= 6, Freq= 0, CH_0, rank 0
900 20:11:44.191819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 20:11:44.191905 ==
902 20:11:44.191972 DQS Delay:
903 20:11:44.195591 DQS0 = 0, DQS1 = 0
904 20:11:44.195676 DQM Delay:
905 20:11:44.198350 DQM0 = 81, DQM1 = 70
906 20:11:44.198434 DQ Delay:
907 20:11:44.201650 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
908 20:11:44.204966 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
909 20:11:44.208189 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
910 20:11:44.211447 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
911 20:11:44.211532
912 20:11:44.211599
913 20:11:44.211661 ==
914 20:11:44.215021 Dram Type= 6, Freq= 0, CH_0, rank 0
915 20:11:44.218305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 20:11:44.218394 ==
917 20:11:44.222020
918 20:11:44.222104
919 20:11:44.222170 TX Vref Scan disable
920 20:11:44.225732 == TX Byte 0 ==
921 20:11:44.229289 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
922 20:11:44.232544 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
923 20:11:44.235703 == TX Byte 1 ==
924 20:11:44.239117 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
925 20:11:44.242464 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
926 20:11:44.242549 ==
927 20:11:44.245699 Dram Type= 6, Freq= 0, CH_0, rank 0
928 20:11:44.249042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 20:11:44.249126 ==
930 20:11:44.263223 TX Vref=22, minBit 12, minWin=26, winSum=432
931 20:11:44.266539 TX Vref=24, minBit 9, minWin=26, winSum=435
932 20:11:44.269905 TX Vref=26, minBit 5, minWin=27, winSum=442
933 20:11:44.273329 TX Vref=28, minBit 2, minWin=27, winSum=441
934 20:11:44.276742 TX Vref=30, minBit 1, minWin=27, winSum=440
935 20:11:44.283392 TX Vref=32, minBit 2, minWin=27, winSum=440
936 20:11:44.286854 [TxChooseVref] Worse bit 5, Min win 27, Win sum 442, Final Vref 26
937 20:11:44.286938
938 20:11:44.289957 Final TX Range 1 Vref 26
939 20:11:44.290041
940 20:11:44.290107 ==
941 20:11:44.293360 Dram Type= 6, Freq= 0, CH_0, rank 0
942 20:11:44.296931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 20:11:44.297015 ==
944 20:11:44.297082
945 20:11:44.300250
946 20:11:44.300333 TX Vref Scan disable
947 20:11:44.303347 == TX Byte 0 ==
948 20:11:44.306551 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
949 20:11:44.310096 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
950 20:11:44.313435 == TX Byte 1 ==
951 20:11:44.316523 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
952 20:11:44.323473 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
953 20:11:44.323556
954 20:11:44.323622 [DATLAT]
955 20:11:44.323684 Freq=800, CH0 RK0
956 20:11:44.323744
957 20:11:44.326775 DATLAT Default: 0xa
958 20:11:44.326858 0, 0xFFFF, sum = 0
959 20:11:44.330075 1, 0xFFFF, sum = 0
960 20:11:44.330162 2, 0xFFFF, sum = 0
961 20:11:44.333378 3, 0xFFFF, sum = 0
962 20:11:44.333462 4, 0xFFFF, sum = 0
963 20:11:44.336727 5, 0xFFFF, sum = 0
964 20:11:44.336811 6, 0xFFFF, sum = 0
965 20:11:44.340088 7, 0xFFFF, sum = 0
966 20:11:44.343359 8, 0xFFFF, sum = 0
967 20:11:44.343455 9, 0x0, sum = 1
968 20:11:44.343524 10, 0x0, sum = 2
969 20:11:44.346907 11, 0x0, sum = 3
970 20:11:44.346991 12, 0x0, sum = 4
971 20:11:44.350201 best_step = 10
972 20:11:44.350285
973 20:11:44.350351 ==
974 20:11:44.353423 Dram Type= 6, Freq= 0, CH_0, rank 0
975 20:11:44.356802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
976 20:11:44.356887 ==
977 20:11:44.360202 RX Vref Scan: 1
978 20:11:44.360285
979 20:11:44.360351 Set Vref Range= 32 -> 127
980 20:11:44.360414
981 20:11:44.363251 RX Vref 32 -> 127, step: 1
982 20:11:44.363334
983 20:11:44.366537 RX Delay -111 -> 252, step: 8
984 20:11:44.366622
985 20:11:44.369887 Set Vref, RX VrefLevel [Byte0]: 32
986 20:11:44.373230 [Byte1]: 32
987 20:11:44.373316
988 20:11:44.376605 Set Vref, RX VrefLevel [Byte0]: 33
989 20:11:44.380021 [Byte1]: 33
990 20:11:44.383733
991 20:11:44.383819 Set Vref, RX VrefLevel [Byte0]: 34
992 20:11:44.387181 [Byte1]: 34
993 20:11:44.391438
994 20:11:44.391526 Set Vref, RX VrefLevel [Byte0]: 35
995 20:11:44.394617 [Byte1]: 35
996 20:11:44.399157
997 20:11:44.399242 Set Vref, RX VrefLevel [Byte0]: 36
998 20:11:44.402346 [Byte1]: 36
999 20:11:44.406848
1000 20:11:44.406932 Set Vref, RX VrefLevel [Byte0]: 37
1001 20:11:44.410065 [Byte1]: 37
1002 20:11:44.414505
1003 20:11:44.414589 Set Vref, RX VrefLevel [Byte0]: 38
1004 20:11:44.417847 [Byte1]: 38
1005 20:11:44.421944
1006 20:11:44.422028 Set Vref, RX VrefLevel [Byte0]: 39
1007 20:11:44.425202 [Byte1]: 39
1008 20:11:44.429658
1009 20:11:44.429745 Set Vref, RX VrefLevel [Byte0]: 40
1010 20:11:44.432982 [Byte1]: 40
1011 20:11:44.437414
1012 20:11:44.437508 Set Vref, RX VrefLevel [Byte0]: 41
1013 20:11:44.440867 [Byte1]: 41
1014 20:11:44.445023
1015 20:11:44.445108 Set Vref, RX VrefLevel [Byte0]: 42
1016 20:11:44.448227 [Byte1]: 42
1017 20:11:44.452744
1018 20:11:44.452829 Set Vref, RX VrefLevel [Byte0]: 43
1019 20:11:44.455988 [Byte1]: 43
1020 20:11:44.460118
1021 20:11:44.460204 Set Vref, RX VrefLevel [Byte0]: 44
1022 20:11:44.463494 [Byte1]: 44
1023 20:11:44.467896
1024 20:11:44.467979 Set Vref, RX VrefLevel [Byte0]: 45
1025 20:11:44.471333 [Byte1]: 45
1026 20:11:44.475864
1027 20:11:44.475946 Set Vref, RX VrefLevel [Byte0]: 46
1028 20:11:44.479243 [Byte1]: 46
1029 20:11:44.483350
1030 20:11:44.483433 Set Vref, RX VrefLevel [Byte0]: 47
1031 20:11:44.487074 [Byte1]: 47
1032 20:11:44.491131
1033 20:11:44.491212 Set Vref, RX VrefLevel [Byte0]: 48
1034 20:11:44.494626 [Byte1]: 48
1035 20:11:44.499065
1036 20:11:44.499147 Set Vref, RX VrefLevel [Byte0]: 49
1037 20:11:44.502633 [Byte1]: 49
1038 20:11:44.506584
1039 20:11:44.506665 Set Vref, RX VrefLevel [Byte0]: 50
1040 20:11:44.510107 [Byte1]: 50
1041 20:11:44.513719
1042 20:11:44.513823 Set Vref, RX VrefLevel [Byte0]: 51
1043 20:11:44.516954 [Byte1]: 51
1044 20:11:44.521582
1045 20:11:44.521666 Set Vref, RX VrefLevel [Byte0]: 52
1046 20:11:44.524963 [Byte1]: 52
1047 20:11:44.529078
1048 20:11:44.529159 Set Vref, RX VrefLevel [Byte0]: 53
1049 20:11:44.532648 [Byte1]: 53
1050 20:11:44.536905
1051 20:11:44.536986 Set Vref, RX VrefLevel [Byte0]: 54
1052 20:11:44.539988 [Byte1]: 54
1053 20:11:44.544374
1054 20:11:44.544455 Set Vref, RX VrefLevel [Byte0]: 55
1055 20:11:44.547917 [Byte1]: 55
1056 20:11:44.551978
1057 20:11:44.552059 Set Vref, RX VrefLevel [Byte0]: 56
1058 20:11:44.558525 [Byte1]: 56
1059 20:11:44.558607
1060 20:11:44.561825 Set Vref, RX VrefLevel [Byte0]: 57
1061 20:11:44.565307 [Byte1]: 57
1062 20:11:44.565388
1063 20:11:44.568586 Set Vref, RX VrefLevel [Byte0]: 58
1064 20:11:44.572120 [Byte1]: 58
1065 20:11:44.572203
1066 20:11:44.575395 Set Vref, RX VrefLevel [Byte0]: 59
1067 20:11:44.578393 [Byte1]: 59
1068 20:11:44.582944
1069 20:11:44.583025 Set Vref, RX VrefLevel [Byte0]: 60
1070 20:11:44.585955 [Byte1]: 60
1071 20:11:44.590373
1072 20:11:44.590454 Set Vref, RX VrefLevel [Byte0]: 61
1073 20:11:44.593767 [Byte1]: 61
1074 20:11:44.597806
1075 20:11:44.597887 Set Vref, RX VrefLevel [Byte0]: 62
1076 20:11:44.601452 [Byte1]: 62
1077 20:11:44.605406
1078 20:11:44.605515 Set Vref, RX VrefLevel [Byte0]: 63
1079 20:11:44.609021 [Byte1]: 63
1080 20:11:44.613339
1081 20:11:44.613420 Set Vref, RX VrefLevel [Byte0]: 64
1082 20:11:44.616342 [Byte1]: 64
1083 20:11:44.620806
1084 20:11:44.620886 Set Vref, RX VrefLevel [Byte0]: 65
1085 20:11:44.624055 [Byte1]: 65
1086 20:11:44.628527
1087 20:11:44.628608 Set Vref, RX VrefLevel [Byte0]: 66
1088 20:11:44.631851 [Byte1]: 66
1089 20:11:44.636090
1090 20:11:44.636170 Set Vref, RX VrefLevel [Byte0]: 67
1091 20:11:44.639274 [Byte1]: 67
1092 20:11:44.643539
1093 20:11:44.643619 Set Vref, RX VrefLevel [Byte0]: 68
1094 20:11:44.646969 [Byte1]: 68
1095 20:11:44.651273
1096 20:11:44.651353 Set Vref, RX VrefLevel [Byte0]: 69
1097 20:11:44.654721 [Byte1]: 69
1098 20:11:44.659219
1099 20:11:44.659299 Set Vref, RX VrefLevel [Byte0]: 70
1100 20:11:44.662270 [Byte1]: 70
1101 20:11:44.666696
1102 20:11:44.666775 Set Vref, RX VrefLevel [Byte0]: 71
1103 20:11:44.669966 [Byte1]: 71
1104 20:11:44.674642
1105 20:11:44.674722 Set Vref, RX VrefLevel [Byte0]: 72
1106 20:11:44.677825 [Byte1]: 72
1107 20:11:44.681897
1108 20:11:44.681977 Set Vref, RX VrefLevel [Byte0]: 73
1109 20:11:44.685238 [Byte1]: 73
1110 20:11:44.689680
1111 20:11:44.689763 Set Vref, RX VrefLevel [Byte0]: 74
1112 20:11:44.693020 [Byte1]: 74
1113 20:11:44.697581
1114 20:11:44.697661 Set Vref, RX VrefLevel [Byte0]: 75
1115 20:11:44.700679 [Byte1]: 75
1116 20:11:44.705151
1117 20:11:44.705231 Set Vref, RX VrefLevel [Byte0]: 76
1118 20:11:44.708309 [Byte1]: 76
1119 20:11:44.712489
1120 20:11:44.712569 Set Vref, RX VrefLevel [Byte0]: 77
1121 20:11:44.716016 [Byte1]: 77
1122 20:11:44.720216
1123 20:11:44.723562 Set Vref, RX VrefLevel [Byte0]: 78
1124 20:11:44.723643 [Byte1]: 78
1125 20:11:44.727815
1126 20:11:44.727895 Set Vref, RX VrefLevel [Byte0]: 79
1127 20:11:44.731272 [Byte1]: 79
1128 20:11:44.735475
1129 20:11:44.735557 Final RX Vref Byte 0 = 60 to rank0
1130 20:11:44.738740 Final RX Vref Byte 1 = 58 to rank0
1131 20:11:44.742108 Final RX Vref Byte 0 = 60 to rank1
1132 20:11:44.745463 Final RX Vref Byte 1 = 58 to rank1==
1133 20:11:44.748984 Dram Type= 6, Freq= 0, CH_0, rank 0
1134 20:11:44.755703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 20:11:44.755805 ==
1136 20:11:44.755872 DQS Delay:
1137 20:11:44.755933 DQS0 = 0, DQS1 = 0
1138 20:11:44.758874 DQM Delay:
1139 20:11:44.758956 DQM0 = 81, DQM1 = 68
1140 20:11:44.762406 DQ Delay:
1141 20:11:44.765682 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1142 20:11:44.765763 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1143 20:11:44.768985 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1144 20:11:44.772255 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1145 20:11:44.775572
1146 20:11:44.775654
1147 20:11:44.782328 [DQSOSCAuto] RK0, (LSB)MR18= 0x2625, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1148 20:11:44.785382 CH0 RK0: MR19=606, MR18=2625
1149 20:11:44.792466 CH0_RK0: MR19=0x606, MR18=0x2625, DQSOSC=400, MR23=63, INC=92, DEC=61
1150 20:11:44.792548
1151 20:11:44.795756 ----->DramcWriteLeveling(PI) begin...
1152 20:11:44.795839 ==
1153 20:11:44.799075 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 20:11:44.802550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 20:11:44.802633 ==
1156 20:11:44.805390 Write leveling (Byte 0): 30 => 30
1157 20:11:44.808822 Write leveling (Byte 1): 29 => 29
1158 20:11:44.812355 DramcWriteLeveling(PI) end<-----
1159 20:11:44.812436
1160 20:11:44.812501 ==
1161 20:11:44.815554 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 20:11:44.819242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 20:11:44.819324 ==
1164 20:11:44.822581 [Gating] SW mode calibration
1165 20:11:44.829218 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1166 20:11:44.835625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1167 20:11:44.839300 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1168 20:11:44.842544 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 20:11:44.849021 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1170 20:11:44.852394 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 20:11:44.855786 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 20:11:44.862521 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 20:11:44.865682 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 20:11:44.869048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 20:11:44.872426 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 20:11:44.879169 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 20:11:44.882358 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 20:11:44.885918 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 20:11:44.892244 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 20:11:44.936587 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 20:11:44.937047 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 20:11:44.937142 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 20:11:44.937215 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 20:11:44.937322 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 20:11:44.937383 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1186 20:11:44.937496 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 20:11:44.937587 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 20:11:44.937673 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 20:11:44.937759 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 20:11:44.942905 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 20:11:44.945864 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 20:11:44.949173 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 20:11:44.952736 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1194 20:11:44.955769 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1195 20:11:44.962397 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 20:11:44.965942 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 20:11:44.969298 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 20:11:44.975669 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 20:11:44.979460 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 20:11:44.982508 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1201 20:11:44.989163 0 10 8 | B1->B0 | 2f2f 2323 | 1 1 | (1 1) (1 0)
1202 20:11:44.992505 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1203 20:11:44.995731 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 20:11:45.002525 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 20:11:45.005931 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 20:11:45.009252 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 20:11:45.015887 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 20:11:45.019256 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1209 20:11:45.022501 0 11 8 | B1->B0 | 2f2f 3d3d | 1 0 | (0 0) (0 0)
1210 20:11:45.029044 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1211 20:11:45.032399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 20:11:45.035739 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 20:11:45.042643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 20:11:45.045665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 20:11:45.049142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 20:11:45.053014 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1217 20:11:45.060252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1218 20:11:45.063806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 20:11:45.067352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 20:11:45.070755 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 20:11:45.077358 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 20:11:45.080671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 20:11:45.084750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 20:11:45.088375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 20:11:45.094675 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 20:11:45.098251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 20:11:45.101574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 20:11:45.108104 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 20:11:45.111443 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 20:11:45.114672 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 20:11:45.121433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 20:11:45.124578 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1233 20:11:45.128183 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1234 20:11:45.134768 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 20:11:45.134856 Total UI for P1: 0, mck2ui 16
1236 20:11:45.138245 best dqsien dly found for B0: ( 0, 14, 6)
1237 20:11:45.141420 Total UI for P1: 0, mck2ui 16
1238 20:11:45.144913 best dqsien dly found for B1: ( 0, 14, 8)
1239 20:11:45.148323 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1240 20:11:45.154680 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1241 20:11:45.154762
1242 20:11:45.158055 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1243 20:11:45.161354 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1244 20:11:45.164770 [Gating] SW calibration Done
1245 20:11:45.164853 ==
1246 20:11:45.168059 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 20:11:45.171598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 20:11:45.171682 ==
1249 20:11:45.171748 RX Vref Scan: 0
1250 20:11:45.171809
1251 20:11:45.174801 RX Vref 0 -> 0, step: 1
1252 20:11:45.174883
1253 20:11:45.177985 RX Delay -130 -> 252, step: 16
1254 20:11:45.181408 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1255 20:11:45.184889 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1256 20:11:45.191524 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1257 20:11:45.194991 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1258 20:11:45.198278 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1259 20:11:45.201290 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1260 20:11:45.204641 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1261 20:11:45.211693 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1262 20:11:45.214812 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1263 20:11:45.218080 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1264 20:11:45.221776 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1265 20:11:45.225000 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1266 20:11:45.231324 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1267 20:11:45.234826 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1268 20:11:45.238195 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1269 20:11:45.241536 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1270 20:11:45.241618 ==
1271 20:11:45.244983 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 20:11:45.248541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 20:11:45.251372 ==
1274 20:11:45.251454 DQS Delay:
1275 20:11:45.251519 DQS0 = 0, DQS1 = 0
1276 20:11:45.254840 DQM Delay:
1277 20:11:45.254922 DQM0 = 80, DQM1 = 73
1278 20:11:45.258013 DQ Delay:
1279 20:11:45.261471 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1280 20:11:45.261559 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1281 20:11:45.264770 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1282 20:11:45.268261 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1283 20:11:45.271419
1284 20:11:45.271500
1285 20:11:45.271566 ==
1286 20:11:45.275036 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 20:11:45.277960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 20:11:45.278043 ==
1289 20:11:45.278107
1290 20:11:45.278167
1291 20:11:45.281670 TX Vref Scan disable
1292 20:11:45.281752 == TX Byte 0 ==
1293 20:11:45.288371 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 20:11:45.291568 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 20:11:45.291651 == TX Byte 1 ==
1296 20:11:45.298062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1297 20:11:45.301292 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1298 20:11:45.301375 ==
1299 20:11:45.304866 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 20:11:45.308038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 20:11:45.308121 ==
1302 20:11:45.321637 TX Vref=22, minBit 9, minWin=26, winSum=434
1303 20:11:45.324918 TX Vref=24, minBit 1, minWin=27, winSum=440
1304 20:11:45.328327 TX Vref=26, minBit 1, minWin=27, winSum=442
1305 20:11:45.331479 TX Vref=28, minBit 1, minWin=27, winSum=443
1306 20:11:45.335208 TX Vref=30, minBit 1, minWin=27, winSum=446
1307 20:11:45.338274 TX Vref=32, minBit 2, minWin=27, winSum=442
1308 20:11:45.345283 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 30
1309 20:11:45.345371
1310 20:11:45.348298 Final TX Range 1 Vref 30
1311 20:11:45.348378
1312 20:11:45.348442 ==
1313 20:11:45.351921 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 20:11:45.355346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 20:11:45.355427 ==
1316 20:11:45.355490
1317 20:11:45.358453
1318 20:11:45.358533 TX Vref Scan disable
1319 20:11:45.361953 == TX Byte 0 ==
1320 20:11:45.364892 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1321 20:11:45.368197 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1322 20:11:45.371490 == TX Byte 1 ==
1323 20:11:45.375235 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1324 20:11:45.378590 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1325 20:11:45.381430
1326 20:11:45.381561 [DATLAT]
1327 20:11:45.381627 Freq=800, CH0 RK1
1328 20:11:45.381689
1329 20:11:45.385166 DATLAT Default: 0xa
1330 20:11:45.385246 0, 0xFFFF, sum = 0
1331 20:11:45.388237 1, 0xFFFF, sum = 0
1332 20:11:45.388319 2, 0xFFFF, sum = 0
1333 20:11:45.391753 3, 0xFFFF, sum = 0
1334 20:11:45.391837 4, 0xFFFF, sum = 0
1335 20:11:45.395004 5, 0xFFFF, sum = 0
1336 20:11:45.395086 6, 0xFFFF, sum = 0
1337 20:11:45.398399 7, 0xFFFF, sum = 0
1338 20:11:45.401620 8, 0xFFFF, sum = 0
1339 20:11:45.401704 9, 0x0, sum = 1
1340 20:11:45.401769 10, 0x0, sum = 2
1341 20:11:45.404829 11, 0x0, sum = 3
1342 20:11:45.404925 12, 0x0, sum = 4
1343 20:11:45.408231 best_step = 10
1344 20:11:45.408311
1345 20:11:45.408374 ==
1346 20:11:45.411523 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 20:11:45.414895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 20:11:45.414976 ==
1349 20:11:45.418089 RX Vref Scan: 0
1350 20:11:45.418169
1351 20:11:45.418232 RX Vref 0 -> 0, step: 1
1352 20:11:45.418292
1353 20:11:45.421361 RX Delay -111 -> 252, step: 8
1354 20:11:45.428357 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1355 20:11:45.431363 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1356 20:11:45.435133 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1357 20:11:45.438338 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1358 20:11:45.441669 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1359 20:11:45.448202 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1360 20:11:45.451514 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1361 20:11:45.454932 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1362 20:11:45.458286 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1363 20:11:45.461428 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1364 20:11:45.468319 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1365 20:11:45.471734 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1366 20:11:45.474599 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1367 20:11:45.478055 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1368 20:11:45.481456 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1369 20:11:45.488035 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1370 20:11:45.488122 ==
1371 20:11:45.491412 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 20:11:45.494768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 20:11:45.494851 ==
1374 20:11:45.494915 DQS Delay:
1375 20:11:45.498325 DQS0 = 0, DQS1 = 0
1376 20:11:45.498407 DQM Delay:
1377 20:11:45.501289 DQM0 = 79, DQM1 = 70
1378 20:11:45.501371 DQ Delay:
1379 20:11:45.504593 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1380 20:11:45.508003 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1381 20:11:45.511420 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1382 20:11:45.514565 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1383 20:11:45.514647
1384 20:11:45.514711
1385 20:11:45.524823 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1386 20:11:45.524932 CH0 RK1: MR19=606, MR18=4B26
1387 20:11:45.531642 CH0_RK1: MR19=0x606, MR18=0x4B26, DQSOSC=391, MR23=63, INC=96, DEC=64
1388 20:11:45.534656 [RxdqsGatingPostProcess] freq 800
1389 20:11:45.541406 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1390 20:11:45.544731 Pre-setting of DQS Precalculation
1391 20:11:45.548064 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1392 20:11:45.548147 ==
1393 20:11:45.551444 Dram Type= 6, Freq= 0, CH_1, rank 0
1394 20:11:45.554672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 20:11:45.554755 ==
1396 20:11:45.561365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 20:11:45.567994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 20:11:45.576760 [CA 0] Center 36 (6~66) winsize 61
1399 20:11:45.580163 [CA 1] Center 36 (6~67) winsize 62
1400 20:11:45.583229 [CA 2] Center 34 (5~64) winsize 60
1401 20:11:45.586736 [CA 3] Center 34 (4~64) winsize 61
1402 20:11:45.589838 [CA 4] Center 35 (5~65) winsize 61
1403 20:11:45.593184 [CA 5] Center 34 (4~64) winsize 61
1404 20:11:45.593268
1405 20:11:45.596375 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 20:11:45.596459
1407 20:11:45.599962 [CATrainingPosCal] consider 1 rank data
1408 20:11:45.603093 u2DelayCellTimex100 = 270/100 ps
1409 20:11:45.606344 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1410 20:11:45.609663 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 20:11:45.616422 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1412 20:11:45.619792 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1413 20:11:45.623270 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1414 20:11:45.626367 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1415 20:11:45.626452
1416 20:11:45.629697 CA PerBit enable=1, Macro0, CA PI delay=34
1417 20:11:45.629782
1418 20:11:45.633061 [CBTSetCACLKResult] CA Dly = 34
1419 20:11:45.633157 CS Dly: 5 (0~36)
1420 20:11:45.636431 ==
1421 20:11:45.636516 Dram Type= 6, Freq= 0, CH_1, rank 1
1422 20:11:45.643233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 20:11:45.643317 ==
1424 20:11:45.646597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 20:11:45.653174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 20:11:45.662738 [CA 0] Center 37 (7~67) winsize 61
1427 20:11:45.666026 [CA 1] Center 36 (6~67) winsize 62
1428 20:11:45.669282 [CA 2] Center 35 (5~65) winsize 61
1429 20:11:45.672580 [CA 3] Center 34 (4~64) winsize 61
1430 20:11:45.676038 [CA 4] Center 34 (4~65) winsize 62
1431 20:11:45.679239 [CA 5] Center 33 (3~64) winsize 62
1432 20:11:45.679323
1433 20:11:45.682712 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 20:11:45.682795
1435 20:11:45.686119 [CATrainingPosCal] consider 2 rank data
1436 20:11:45.689327 u2DelayCellTimex100 = 270/100 ps
1437 20:11:45.692718 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1438 20:11:45.695972 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 20:11:45.702721 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1440 20:11:45.706093 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1441 20:11:45.709346 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 20:11:45.713016 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1443 20:11:45.713354
1444 20:11:45.716750 CA PerBit enable=1, Macro0, CA PI delay=34
1445 20:11:45.717090
1446 20:11:45.720233 [CBTSetCACLKResult] CA Dly = 34
1447 20:11:45.720562 CS Dly: 5 (0~37)
1448 20:11:45.720822
1449 20:11:45.724241 ----->DramcWriteLeveling(PI) begin...
1450 20:11:45.724574 ==
1451 20:11:45.727879 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 20:11:45.731692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 20:11:45.732035 ==
1454 20:11:45.734770 Write leveling (Byte 0): 28 => 28
1455 20:11:45.738531 Write leveling (Byte 1): 29 => 29
1456 20:11:45.742157 DramcWriteLeveling(PI) end<-----
1457 20:11:45.742242
1458 20:11:45.742329 ==
1459 20:11:45.745946 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 20:11:45.749679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 20:11:45.749763 ==
1462 20:11:45.752964 [Gating] SW mode calibration
1463 20:11:45.759779 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1464 20:11:45.763241 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1465 20:11:45.769977 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1466 20:11:45.773245 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1467 20:11:45.776542 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 20:11:45.783162 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 20:11:45.786700 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 20:11:45.790121 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 20:11:45.793403 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 20:11:45.800067 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 20:11:45.803343 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 20:11:45.806604 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 20:11:45.813325 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 20:11:45.816827 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 20:11:45.820233 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 20:11:45.826450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 20:11:45.830014 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 20:11:45.833097 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 20:11:45.839781 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 20:11:45.843130 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1483 20:11:45.846494 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1484 20:11:45.853387 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 20:11:45.856430 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 20:11:45.859999 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 20:11:45.866490 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 20:11:45.869697 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 20:11:45.873312 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 20:11:45.880023 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1491 20:11:45.883276 0 9 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1492 20:11:45.886572 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 20:11:45.893201 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 20:11:45.896342 0 9 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
1495 20:11:45.899849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 20:11:45.906320 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 20:11:45.909655 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 20:11:45.913099 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1499 20:11:45.916140 0 10 8 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
1500 20:11:45.923152 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1501 20:11:45.926465 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 20:11:45.929903 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 20:11:45.936416 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 20:11:45.939385 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 20:11:45.942728 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 20:11:45.949652 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1507 20:11:45.952847 0 11 8 | B1->B0 | 3838 3939 | 0 0 | (0 0) (0 0)
1508 20:11:45.956191 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 20:11:45.962823 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 20:11:45.966309 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 20:11:45.969614 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 20:11:45.976029 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 20:11:45.979635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 20:11:45.982713 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1515 20:11:45.990193 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1516 20:11:45.992883 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 20:11:45.996070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 20:11:46.002717 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 20:11:46.006282 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 20:11:46.009628 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 20:11:46.016170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 20:11:46.019464 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 20:11:46.022669 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 20:11:46.026128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 20:11:46.032688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 20:11:46.036090 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 20:11:46.039330 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 20:11:46.046196 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 20:11:46.049459 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 20:11:46.052768 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1531 20:11:46.059461 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1532 20:11:46.062822 Total UI for P1: 0, mck2ui 16
1533 20:11:46.066021 best dqsien dly found for B0: ( 0, 14, 4)
1534 20:11:46.069365 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 20:11:46.072494 Total UI for P1: 0, mck2ui 16
1536 20:11:46.075947 best dqsien dly found for B1: ( 0, 14, 8)
1537 20:11:46.079410 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1538 20:11:46.082935 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1539 20:11:46.083042
1540 20:11:46.086015 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 20:11:46.089543 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1542 20:11:46.092934 [Gating] SW calibration Done
1543 20:11:46.093015 ==
1544 20:11:46.095950 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 20:11:46.099319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 20:11:46.102756 ==
1547 20:11:46.102837 RX Vref Scan: 0
1548 20:11:46.102901
1549 20:11:46.106033 RX Vref 0 -> 0, step: 1
1550 20:11:46.106114
1551 20:11:46.109329 RX Delay -130 -> 252, step: 16
1552 20:11:46.112957 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1553 20:11:46.116088 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1554 20:11:46.119372 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1555 20:11:46.123029 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1556 20:11:46.126348 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1557 20:11:46.132832 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1558 20:11:46.136285 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1559 20:11:46.139371 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1560 20:11:46.142705 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1561 20:11:46.146069 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1562 20:11:46.152821 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1563 20:11:46.156041 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1564 20:11:46.159374 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1565 20:11:46.162693 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1566 20:11:46.169442 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1567 20:11:46.172815 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1568 20:11:46.172914 ==
1569 20:11:46.176016 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 20:11:46.179339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 20:11:46.179424 ==
1572 20:11:46.179510 DQS Delay:
1573 20:11:46.182717 DQS0 = 0, DQS1 = 0
1574 20:11:46.182801 DQM Delay:
1575 20:11:46.185941 DQM0 = 81, DQM1 = 71
1576 20:11:46.186025 DQ Delay:
1577 20:11:46.189387 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1578 20:11:46.192573 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1579 20:11:46.196039 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1580 20:11:46.199504 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1581 20:11:46.199588
1582 20:11:46.199674
1583 20:11:46.199755 ==
1584 20:11:46.202605 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 20:11:46.206291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 20:11:46.209182 ==
1587 20:11:46.209291
1588 20:11:46.209396
1589 20:11:46.209532 TX Vref Scan disable
1590 20:11:46.212658 == TX Byte 0 ==
1591 20:11:46.215920 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1592 20:11:46.219475 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1593 20:11:46.222852 == TX Byte 1 ==
1594 20:11:46.226322 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1595 20:11:46.229417 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1596 20:11:46.229540 ==
1597 20:11:46.232514 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 20:11:46.239195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 20:11:46.239280 ==
1600 20:11:46.251239 TX Vref=22, minBit 1, minWin=27, winSum=440
1601 20:11:46.254710 TX Vref=24, minBit 5, minWin=26, winSum=441
1602 20:11:46.257963 TX Vref=26, minBit 1, minWin=27, winSum=445
1603 20:11:46.261004 TX Vref=28, minBit 1, minWin=27, winSum=446
1604 20:11:46.264269 TX Vref=30, minBit 0, minWin=27, winSum=448
1605 20:11:46.271004 TX Vref=32, minBit 0, minWin=27, winSum=443
1606 20:11:46.274527 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 30
1607 20:11:46.274613
1608 20:11:46.277782 Final TX Range 1 Vref 30
1609 20:11:46.277866
1610 20:11:46.277952 ==
1611 20:11:46.281355 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 20:11:46.284626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 20:11:46.284711 ==
1614 20:11:46.284797
1615 20:11:46.287989
1616 20:11:46.288073 TX Vref Scan disable
1617 20:11:46.291074 == TX Byte 0 ==
1618 20:11:46.294801 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1619 20:11:46.298434 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1620 20:11:46.301872 == TX Byte 1 ==
1621 20:11:46.305402 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1622 20:11:46.308356 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1623 20:11:46.308440
1624 20:11:46.311803 [DATLAT]
1625 20:11:46.311897 Freq=800, CH1 RK0
1626 20:11:46.311982
1627 20:11:46.315443 DATLAT Default: 0xa
1628 20:11:46.315527 0, 0xFFFF, sum = 0
1629 20:11:46.318703 1, 0xFFFF, sum = 0
1630 20:11:46.318788 2, 0xFFFF, sum = 0
1631 20:11:46.321869 3, 0xFFFF, sum = 0
1632 20:11:46.321954 4, 0xFFFF, sum = 0
1633 20:11:46.325036 5, 0xFFFF, sum = 0
1634 20:11:46.325121 6, 0xFFFF, sum = 0
1635 20:11:46.328705 7, 0xFFFF, sum = 0
1636 20:11:46.328790 8, 0xFFFF, sum = 0
1637 20:11:46.331714 9, 0x0, sum = 1
1638 20:11:46.331810 10, 0x0, sum = 2
1639 20:11:46.335021 11, 0x0, sum = 3
1640 20:11:46.335106 12, 0x0, sum = 4
1641 20:11:46.338606 best_step = 10
1642 20:11:46.338689
1643 20:11:46.338775 ==
1644 20:11:46.341720 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 20:11:46.345272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 20:11:46.345382 ==
1647 20:11:46.345468 RX Vref Scan: 1
1648 20:11:46.348429
1649 20:11:46.348512 Set Vref Range= 32 -> 127
1650 20:11:46.348599
1651 20:11:46.351692 RX Vref 32 -> 127, step: 1
1652 20:11:46.351792
1653 20:11:46.354987 RX Delay -111 -> 252, step: 8
1654 20:11:46.355072
1655 20:11:46.358295 Set Vref, RX VrefLevel [Byte0]: 32
1656 20:11:46.361864 [Byte1]: 32
1657 20:11:46.361948
1658 20:11:46.365425 Set Vref, RX VrefLevel [Byte0]: 33
1659 20:11:46.368709 [Byte1]: 33
1660 20:11:46.368794
1661 20:11:46.371964 Set Vref, RX VrefLevel [Byte0]: 34
1662 20:11:46.375026 [Byte1]: 34
1663 20:11:46.379411
1664 20:11:46.379495 Set Vref, RX VrefLevel [Byte0]: 35
1665 20:11:46.382584 [Byte1]: 35
1666 20:11:46.387097
1667 20:11:46.387181 Set Vref, RX VrefLevel [Byte0]: 36
1668 20:11:46.390049 [Byte1]: 36
1669 20:11:46.394700
1670 20:11:46.394785 Set Vref, RX VrefLevel [Byte0]: 37
1671 20:11:46.397748 [Byte1]: 37
1672 20:11:46.402165
1673 20:11:46.402248 Set Vref, RX VrefLevel [Byte0]: 38
1674 20:11:46.405444 [Byte1]: 38
1675 20:11:46.409740
1676 20:11:46.409824 Set Vref, RX VrefLevel [Byte0]: 39
1677 20:11:46.413015 [Byte1]: 39
1678 20:11:46.417606
1679 20:11:46.417690 Set Vref, RX VrefLevel [Byte0]: 40
1680 20:11:46.420952 [Byte1]: 40
1681 20:11:46.425123
1682 20:11:46.425206 Set Vref, RX VrefLevel [Byte0]: 41
1683 20:11:46.431557 [Byte1]: 41
1684 20:11:46.431642
1685 20:11:46.435013 Set Vref, RX VrefLevel [Byte0]: 42
1686 20:11:46.438327 [Byte1]: 42
1687 20:11:46.438412
1688 20:11:46.441922 Set Vref, RX VrefLevel [Byte0]: 43
1689 20:11:46.444980 [Byte1]: 43
1690 20:11:46.445061
1691 20:11:46.448267 Set Vref, RX VrefLevel [Byte0]: 44
1692 20:11:46.451814 [Byte1]: 44
1693 20:11:46.455738
1694 20:11:46.455819 Set Vref, RX VrefLevel [Byte0]: 45
1695 20:11:46.459142 [Byte1]: 45
1696 20:11:46.463318
1697 20:11:46.463400 Set Vref, RX VrefLevel [Byte0]: 46
1698 20:11:46.466611 [Byte1]: 46
1699 20:11:46.470852
1700 20:11:46.470933 Set Vref, RX VrefLevel [Byte0]: 47
1701 20:11:46.474134 [Byte1]: 47
1702 20:11:46.479039
1703 20:11:46.479120 Set Vref, RX VrefLevel [Byte0]: 48
1704 20:11:46.481846 [Byte1]: 48
1705 20:11:46.486163
1706 20:11:46.486244 Set Vref, RX VrefLevel [Byte0]: 49
1707 20:11:46.489381 [Byte1]: 49
1708 20:11:46.493956
1709 20:11:46.494037 Set Vref, RX VrefLevel [Byte0]: 50
1710 20:11:46.497262 [Byte1]: 50
1711 20:11:46.501674
1712 20:11:46.501754 Set Vref, RX VrefLevel [Byte0]: 51
1713 20:11:46.505028 [Byte1]: 51
1714 20:11:46.509373
1715 20:11:46.509454 Set Vref, RX VrefLevel [Byte0]: 52
1716 20:11:46.512590 [Byte1]: 52
1717 20:11:46.516934
1718 20:11:46.517015 Set Vref, RX VrefLevel [Byte0]: 53
1719 20:11:46.520238 [Byte1]: 53
1720 20:11:46.524634
1721 20:11:46.524715 Set Vref, RX VrefLevel [Byte0]: 54
1722 20:11:46.527710 [Byte1]: 54
1723 20:11:46.532109
1724 20:11:46.532190 Set Vref, RX VrefLevel [Byte0]: 55
1725 20:11:46.535391 [Byte1]: 55
1726 20:11:46.540009
1727 20:11:46.540090 Set Vref, RX VrefLevel [Byte0]: 56
1728 20:11:46.543137 [Byte1]: 56
1729 20:11:46.547326
1730 20:11:46.547407 Set Vref, RX VrefLevel [Byte0]: 57
1731 20:11:46.550931 [Byte1]: 57
1732 20:11:46.555330
1733 20:11:46.555410 Set Vref, RX VrefLevel [Byte0]: 58
1734 20:11:46.558413 [Byte1]: 58
1735 20:11:46.562757
1736 20:11:46.562838 Set Vref, RX VrefLevel [Byte0]: 59
1737 20:11:46.566102 [Byte1]: 59
1738 20:11:46.570257
1739 20:11:46.570338 Set Vref, RX VrefLevel [Byte0]: 60
1740 20:11:46.573797 [Byte1]: 60
1741 20:11:46.578190
1742 20:11:46.578297 Set Vref, RX VrefLevel [Byte0]: 61
1743 20:11:46.581505 [Byte1]: 61
1744 20:11:46.585758
1745 20:11:46.585839 Set Vref, RX VrefLevel [Byte0]: 62
1746 20:11:46.589116 [Byte1]: 62
1747 20:11:46.593060
1748 20:11:46.596414 Set Vref, RX VrefLevel [Byte0]: 63
1749 20:11:46.596495 [Byte1]: 63
1750 20:11:46.601102
1751 20:11:46.601183 Set Vref, RX VrefLevel [Byte0]: 64
1752 20:11:46.604368 [Byte1]: 64
1753 20:11:46.608721
1754 20:11:46.608802 Set Vref, RX VrefLevel [Byte0]: 65
1755 20:11:46.612283 [Byte1]: 65
1756 20:11:46.616491
1757 20:11:46.616572 Set Vref, RX VrefLevel [Byte0]: 66
1758 20:11:46.619439 [Byte1]: 66
1759 20:11:46.624188
1760 20:11:46.624269 Set Vref, RX VrefLevel [Byte0]: 67
1761 20:11:46.627459 [Byte1]: 67
1762 20:11:46.631498
1763 20:11:46.631578 Set Vref, RX VrefLevel [Byte0]: 68
1764 20:11:46.634911 [Byte1]: 68
1765 20:11:46.639264
1766 20:11:46.639343 Set Vref, RX VrefLevel [Byte0]: 69
1767 20:11:46.642504 [Byte1]: 69
1768 20:11:46.646802
1769 20:11:46.646882 Set Vref, RX VrefLevel [Byte0]: 70
1770 20:11:46.650161 [Byte1]: 70
1771 20:11:46.654704
1772 20:11:46.654783 Set Vref, RX VrefLevel [Byte0]: 71
1773 20:11:46.657946 [Byte1]: 71
1774 20:11:46.662173
1775 20:11:46.662252 Set Vref, RX VrefLevel [Byte0]: 72
1776 20:11:46.665412 [Byte1]: 72
1777 20:11:46.669880
1778 20:11:46.669960 Set Vref, RX VrefLevel [Byte0]: 73
1779 20:11:46.673061 [Byte1]: 73
1780 20:11:46.677379
1781 20:11:46.677461 Set Vref, RX VrefLevel [Byte0]: 74
1782 20:11:46.680789 [Byte1]: 74
1783 20:11:46.685065
1784 20:11:46.685144 Final RX Vref Byte 0 = 64 to rank0
1785 20:11:46.688570 Final RX Vref Byte 1 = 56 to rank0
1786 20:11:46.691873 Final RX Vref Byte 0 = 64 to rank1
1787 20:11:46.695038 Final RX Vref Byte 1 = 56 to rank1==
1788 20:11:46.698487 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 20:11:46.705170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 20:11:46.705253 ==
1791 20:11:46.705352 DQS Delay:
1792 20:11:46.705450 DQS0 = 0, DQS1 = 0
1793 20:11:46.708351 DQM Delay:
1794 20:11:46.708433 DQM0 = 79, DQM1 = 71
1795 20:11:46.711620 DQ Delay:
1796 20:11:46.715117 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1797 20:11:46.718561 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1798 20:11:46.718644 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1799 20:11:46.724993 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1800 20:11:46.725076
1801 20:11:46.725161
1802 20:11:46.731619 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1803 20:11:46.735102 CH1 RK0: MR19=606, MR18=E18
1804 20:11:46.741866 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1805 20:11:46.741950
1806 20:11:46.744977 ----->DramcWriteLeveling(PI) begin...
1807 20:11:46.745061 ==
1808 20:11:46.748320 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 20:11:46.751617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 20:11:46.751701 ==
1811 20:11:46.754964 Write leveling (Byte 0): 28 => 28
1812 20:11:46.758134 Write leveling (Byte 1): 29 => 29
1813 20:11:46.761442 DramcWriteLeveling(PI) end<-----
1814 20:11:46.761576
1815 20:11:46.761660 ==
1816 20:11:46.764844 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 20:11:46.768179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 20:11:46.768263 ==
1819 20:11:46.771528 [Gating] SW mode calibration
1820 20:11:46.778090 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 20:11:46.784763 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 20:11:46.788076 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1823 20:11:46.791295 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1824 20:11:46.798065 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 20:11:46.801345 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 20:11:46.804694 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 20:11:46.811496 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 20:11:46.814879 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 20:11:46.818088 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 20:11:46.824779 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 20:11:46.828024 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 20:11:46.831653 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 20:11:46.838437 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 20:11:46.841282 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 20:11:46.844793 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 20:11:46.847964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 20:11:46.854865 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 20:11:46.858124 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 20:11:46.861342 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1840 20:11:46.868098 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 20:11:46.871369 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 20:11:46.874911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 20:11:46.881292 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 20:11:46.884672 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 20:11:46.888085 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 20:11:46.894592 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 20:11:46.898308 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1848 20:11:46.901331 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1849 20:11:46.908030 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 20:11:46.911341 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 20:11:46.914771 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 20:11:46.921472 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 20:11:46.924862 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 20:11:46.928072 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 20:11:46.934664 0 10 4 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 1)
1856 20:11:46.938201 0 10 8 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
1857 20:11:46.941794 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 20:11:46.944780 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 20:11:46.951333 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 20:11:46.954582 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 20:11:46.958085 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 20:11:46.964628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 20:11:46.968241 0 11 4 | B1->B0 | 2b2b 3a3a | 0 1 | (0 0) (0 0)
1864 20:11:46.971435 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1865 20:11:46.978178 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 20:11:46.981380 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 20:11:46.984673 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 20:11:46.991256 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 20:11:46.994728 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 20:11:46.998143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 20:11:47.004686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1872 20:11:47.008218 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 20:11:47.011402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 20:11:47.018005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 20:11:47.021225 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 20:11:47.024684 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 20:11:47.031668 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 20:11:47.034789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 20:11:47.038035 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 20:11:47.044811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 20:11:47.048125 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 20:11:47.051393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 20:11:47.054762 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 20:11:47.061377 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 20:11:47.064925 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 20:11:47.068230 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 20:11:47.074763 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 20:11:47.078429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 20:11:47.081435 Total UI for P1: 0, mck2ui 16
1890 20:11:47.084768 best dqsien dly found for B0: ( 0, 14, 2)
1891 20:11:47.088140 Total UI for P1: 0, mck2ui 16
1892 20:11:47.091525 best dqsien dly found for B1: ( 0, 14, 4)
1893 20:11:47.094803 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1894 20:11:47.097975 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 20:11:47.098058
1896 20:11:47.101365 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1897 20:11:47.104610 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 20:11:47.107668 [Gating] SW calibration Done
1899 20:11:47.107750 ==
1900 20:11:47.111484 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 20:11:47.114673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 20:11:47.117793 ==
1903 20:11:47.117875 RX Vref Scan: 0
1904 20:11:47.117960
1905 20:11:47.121066 RX Vref 0 -> 0, step: 1
1906 20:11:47.121208
1907 20:11:47.124090 RX Delay -130 -> 252, step: 16
1908 20:11:47.127696 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 20:11:47.131015 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1910 20:11:47.134456 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 20:11:47.137595 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1912 20:11:47.144345 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1913 20:11:47.147315 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1914 20:11:47.150934 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1915 20:11:47.153961 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1916 20:11:47.157451 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1917 20:11:47.163992 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1918 20:11:47.167249 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1919 20:11:47.170548 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1920 20:11:47.174037 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1921 20:11:47.177446 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1922 20:11:47.183984 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1923 20:11:47.187282 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1924 20:11:47.187367 ==
1925 20:11:47.190568 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 20:11:47.193938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 20:11:47.194023 ==
1928 20:11:47.197222 DQS Delay:
1929 20:11:47.197306 DQS0 = 0, DQS1 = 0
1930 20:11:47.200725 DQM Delay:
1931 20:11:47.200809 DQM0 = 76, DQM1 = 71
1932 20:11:47.200897 DQ Delay:
1933 20:11:47.204081 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1934 20:11:47.207207 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1935 20:11:47.210595 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1936 20:11:47.213795 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1937 20:11:47.213879
1938 20:11:47.213965
1939 20:11:47.214047 ==
1940 20:11:47.217095 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 20:11:47.223674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 20:11:47.223759 ==
1943 20:11:47.223845
1944 20:11:47.223925
1945 20:11:47.224004 TX Vref Scan disable
1946 20:11:47.227436 == TX Byte 0 ==
1947 20:11:47.230841 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1948 20:11:47.234287 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1949 20:11:47.237410 == TX Byte 1 ==
1950 20:11:47.241238 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 20:11:47.247645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 20:11:47.247726 ==
1953 20:11:47.250816 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 20:11:47.254240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 20:11:47.254321 ==
1956 20:11:47.266500 TX Vref=22, minBit 3, minWin=27, winSum=449
1957 20:11:47.269824 TX Vref=24, minBit 0, minWin=27, winSum=451
1958 20:11:47.273026 TX Vref=26, minBit 0, minWin=28, winSum=455
1959 20:11:47.276619 TX Vref=28, minBit 0, minWin=28, winSum=458
1960 20:11:47.280147 TX Vref=30, minBit 1, minWin=27, winSum=460
1961 20:11:47.283475 TX Vref=32, minBit 1, minWin=27, winSum=459
1962 20:11:47.289804 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1963 20:11:47.289888
1964 20:11:47.292940 Final TX Range 1 Vref 28
1965 20:11:47.293025
1966 20:11:47.293111 ==
1967 20:11:47.296151 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 20:11:47.299798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 20:11:47.299883 ==
1970 20:11:47.302844
1971 20:11:47.302927
1972 20:11:47.303012 TX Vref Scan disable
1973 20:11:47.306576 == TX Byte 0 ==
1974 20:11:47.309938 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1975 20:11:47.316525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1976 20:11:47.316610 == TX Byte 1 ==
1977 20:11:47.319979 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 20:11:47.323284 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 20:11:47.326400
1980 20:11:47.326483 [DATLAT]
1981 20:11:47.326569 Freq=800, CH1 RK1
1982 20:11:47.326651
1983 20:11:47.330054 DATLAT Default: 0xa
1984 20:11:47.330138 0, 0xFFFF, sum = 0
1985 20:11:47.333144 1, 0xFFFF, sum = 0
1986 20:11:47.333226 2, 0xFFFF, sum = 0
1987 20:11:47.336487 3, 0xFFFF, sum = 0
1988 20:11:47.336570 4, 0xFFFF, sum = 0
1989 20:11:47.339918 5, 0xFFFF, sum = 0
1990 20:11:47.340001 6, 0xFFFF, sum = 0
1991 20:11:47.343269 7, 0xFFFF, sum = 0
1992 20:11:47.346598 8, 0xFFFF, sum = 0
1993 20:11:47.346681 9, 0x0, sum = 1
1994 20:11:47.346748 10, 0x0, sum = 2
1995 20:11:47.350004 11, 0x0, sum = 3
1996 20:11:47.350087 12, 0x0, sum = 4
1997 20:11:47.353063 best_step = 10
1998 20:11:47.353144
1999 20:11:47.353208 ==
2000 20:11:47.356339 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 20:11:47.359760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 20:11:47.359842 ==
2003 20:11:47.363358 RX Vref Scan: 0
2004 20:11:47.363439
2005 20:11:47.363503 RX Vref 0 -> 0, step: 1
2006 20:11:47.363564
2007 20:11:47.366535 RX Delay -111 -> 252, step: 8
2008 20:11:47.373238 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2009 20:11:47.376579 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2010 20:11:47.379814 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2011 20:11:47.383517 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2012 20:11:47.386722 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2013 20:11:47.393184 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2014 20:11:47.396767 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2015 20:11:47.399979 iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240
2016 20:11:47.403217 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2017 20:11:47.406602 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2018 20:11:47.413252 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2019 20:11:47.416507 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2020 20:11:47.419869 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2021 20:11:47.423235 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2022 20:11:47.429829 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2023 20:11:47.433085 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2024 20:11:47.433166 ==
2025 20:11:47.436320 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 20:11:47.439591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 20:11:47.439672 ==
2028 20:11:47.439735 DQS Delay:
2029 20:11:47.443168 DQS0 = 0, DQS1 = 0
2030 20:11:47.443248 DQM Delay:
2031 20:11:47.446436 DQM0 = 76, DQM1 = 73
2032 20:11:47.446516 DQ Delay:
2033 20:11:47.449801 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2034 20:11:47.452989 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =72
2035 20:11:47.456151 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2036 20:11:47.459671 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2037 20:11:47.459806
2038 20:11:47.459911
2039 20:11:47.469767 [DQSOSCAuto] RK1, (LSB)MR18= 0x213a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2040 20:11:47.469895 CH1 RK1: MR19=606, MR18=213A
2041 20:11:47.476399 CH1_RK1: MR19=0x606, MR18=0x213A, DQSOSC=395, MR23=63, INC=94, DEC=63
2042 20:11:47.479739 [RxdqsGatingPostProcess] freq 800
2043 20:11:47.486482 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 20:11:47.489876 Pre-setting of DQS Precalculation
2045 20:11:47.493240 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 20:11:47.499769 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 20:11:47.506352 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 20:11:47.506432
2049 20:11:47.509866
2050 20:11:47.509946 [Calibration Summary] 1600 Mbps
2051 20:11:47.513367 CH 0, Rank 0
2052 20:11:47.513447 SW Impedance : PASS
2053 20:11:47.516369 DUTY Scan : NO K
2054 20:11:47.520062 ZQ Calibration : PASS
2055 20:11:47.520142 Jitter Meter : NO K
2056 20:11:47.523047 CBT Training : PASS
2057 20:11:47.526454 Write leveling : PASS
2058 20:11:47.526534 RX DQS gating : PASS
2059 20:11:47.529905 RX DQ/DQS(RDDQC) : PASS
2060 20:11:47.533130 TX DQ/DQS : PASS
2061 20:11:47.533212 RX DATLAT : PASS
2062 20:11:47.536404 RX DQ/DQS(Engine): PASS
2063 20:11:47.536485 TX OE : NO K
2064 20:11:47.539737 All Pass.
2065 20:11:47.539818
2066 20:11:47.539882 CH 0, Rank 1
2067 20:11:47.543347 SW Impedance : PASS
2068 20:11:47.543429 DUTY Scan : NO K
2069 20:11:47.546790 ZQ Calibration : PASS
2070 20:11:47.549842 Jitter Meter : NO K
2071 20:11:47.549924 CBT Training : PASS
2072 20:11:47.553412 Write leveling : PASS
2073 20:11:47.556593 RX DQS gating : PASS
2074 20:11:47.556674 RX DQ/DQS(RDDQC) : PASS
2075 20:11:47.559837 TX DQ/DQS : PASS
2076 20:11:47.563164 RX DATLAT : PASS
2077 20:11:47.563246 RX DQ/DQS(Engine): PASS
2078 20:11:47.566392 TX OE : NO K
2079 20:11:47.566473 All Pass.
2080 20:11:47.566538
2081 20:11:47.570043 CH 1, Rank 0
2082 20:11:47.570125 SW Impedance : PASS
2083 20:11:47.573099 DUTY Scan : NO K
2084 20:11:47.576714 ZQ Calibration : PASS
2085 20:11:47.576795 Jitter Meter : NO K
2086 20:11:47.579891 CBT Training : PASS
2087 20:11:47.579973 Write leveling : PASS
2088 20:11:47.582922 RX DQS gating : PASS
2089 20:11:47.586560 RX DQ/DQS(RDDQC) : PASS
2090 20:11:47.586641 TX DQ/DQS : PASS
2091 20:11:47.589696 RX DATLAT : PASS
2092 20:11:47.593143 RX DQ/DQS(Engine): PASS
2093 20:11:47.593224 TX OE : NO K
2094 20:11:47.596498 All Pass.
2095 20:11:47.596583
2096 20:11:47.596648 CH 1, Rank 1
2097 20:11:47.599974 SW Impedance : PASS
2098 20:11:47.600055 DUTY Scan : NO K
2099 20:11:47.603355 ZQ Calibration : PASS
2100 20:11:47.606572 Jitter Meter : NO K
2101 20:11:47.606654 CBT Training : PASS
2102 20:11:47.609670 Write leveling : PASS
2103 20:11:47.613138 RX DQS gating : PASS
2104 20:11:47.613219 RX DQ/DQS(RDDQC) : PASS
2105 20:11:47.616467 TX DQ/DQS : PASS
2106 20:11:47.619586 RX DATLAT : PASS
2107 20:11:47.619689 RX DQ/DQS(Engine): PASS
2108 20:11:47.623307 TX OE : NO K
2109 20:11:47.623392 All Pass.
2110 20:11:47.623479
2111 20:11:47.626234 DramC Write-DBI off
2112 20:11:47.629633 PER_BANK_REFRESH: Hybrid Mode
2113 20:11:47.629727 TX_TRACKING: ON
2114 20:11:47.632968 [GetDramInforAfterCalByMRR] Vendor 6.
2115 20:11:47.636277 [GetDramInforAfterCalByMRR] Revision 606.
2116 20:11:47.639806 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 20:11:47.642858 MR0 0x3b3b
2118 20:11:47.642951 MR8 0x5151
2119 20:11:47.646505 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 20:11:47.646591
2121 20:11:47.646679 MR0 0x3b3b
2122 20:11:47.649648 MR8 0x5151
2123 20:11:47.652980 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 20:11:47.653065
2125 20:11:47.659866 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 20:11:47.666360 [FAST_K] Save calibration result to emmc
2127 20:11:47.669599 [FAST_K] Save calibration result to emmc
2128 20:11:47.669684 dram_init: config_dvfs: 1
2129 20:11:47.672981 dramc_set_vcore_voltage set vcore to 662500
2130 20:11:47.676316 Read voltage for 1200, 2
2131 20:11:47.676403 Vio18 = 0
2132 20:11:47.679477 Vcore = 662500
2133 20:11:47.679562 Vdram = 0
2134 20:11:47.679648 Vddq = 0
2135 20:11:47.682853 Vmddr = 0
2136 20:11:47.686263 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 20:11:47.692756 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 20:11:47.692851 MEM_TYPE=3, freq_sel=15
2139 20:11:47.696281 sv_algorithm_assistance_LP4_1600
2140 20:11:47.702607 ============ PULL DRAM RESETB DOWN ============
2141 20:11:47.706246 ========== PULL DRAM RESETB DOWN end =========
2142 20:11:47.709341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 20:11:47.712831 ===================================
2144 20:11:47.716096 LPDDR4 DRAM CONFIGURATION
2145 20:11:47.719410 ===================================
2146 20:11:47.722553 EX_ROW_EN[0] = 0x0
2147 20:11:47.722639 EX_ROW_EN[1] = 0x0
2148 20:11:47.725904 LP4Y_EN = 0x0
2149 20:11:47.725992 WORK_FSP = 0x0
2150 20:11:47.729213 WL = 0x4
2151 20:11:47.729298 RL = 0x4
2152 20:11:47.732634 BL = 0x2
2153 20:11:47.732719 RPST = 0x0
2154 20:11:47.735964 RD_PRE = 0x0
2155 20:11:47.736048 WR_PRE = 0x1
2156 20:11:47.739288 WR_PST = 0x0
2157 20:11:47.739373 DBI_WR = 0x0
2158 20:11:47.742412 DBI_RD = 0x0
2159 20:11:47.742496 OTF = 0x1
2160 20:11:47.745831 ===================================
2161 20:11:47.749416 ===================================
2162 20:11:47.752562 ANA top config
2163 20:11:47.756149 ===================================
2164 20:11:47.759384 DLL_ASYNC_EN = 0
2165 20:11:47.759470 ALL_SLAVE_EN = 0
2166 20:11:47.762593 NEW_RANK_MODE = 1
2167 20:11:47.765862 DLL_IDLE_MODE = 1
2168 20:11:47.769237 LP45_APHY_COMB_EN = 1
2169 20:11:47.769322 TX_ODT_DIS = 1
2170 20:11:47.772512 NEW_8X_MODE = 1
2171 20:11:47.775926 ===================================
2172 20:11:47.779185 ===================================
2173 20:11:47.782408 data_rate = 2400
2174 20:11:47.786040 CKR = 1
2175 20:11:47.789219 DQ_P2S_RATIO = 8
2176 20:11:47.792263 ===================================
2177 20:11:47.795752 CA_P2S_RATIO = 8
2178 20:11:47.795835 DQ_CA_OPEN = 0
2179 20:11:47.798836 DQ_SEMI_OPEN = 0
2180 20:11:47.802235 CA_SEMI_OPEN = 0
2181 20:11:47.805891 CA_FULL_RATE = 0
2182 20:11:47.808947 DQ_CKDIV4_EN = 0
2183 20:11:47.812264 CA_CKDIV4_EN = 0
2184 20:11:47.812347 CA_PREDIV_EN = 0
2185 20:11:47.815716 PH8_DLY = 17
2186 20:11:47.819009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 20:11:47.822420 DQ_AAMCK_DIV = 4
2188 20:11:47.825585 CA_AAMCK_DIV = 4
2189 20:11:47.829012 CA_ADMCK_DIV = 4
2190 20:11:47.829095 DQ_TRACK_CA_EN = 0
2191 20:11:47.832427 CA_PICK = 1200
2192 20:11:47.835571 CA_MCKIO = 1200
2193 20:11:47.839021 MCKIO_SEMI = 0
2194 20:11:47.842295 PLL_FREQ = 2366
2195 20:11:47.845832 DQ_UI_PI_RATIO = 32
2196 20:11:47.849361 CA_UI_PI_RATIO = 0
2197 20:11:47.852595 ===================================
2198 20:11:47.855940 ===================================
2199 20:11:47.856025 memory_type:LPDDR4
2200 20:11:47.859397 GP_NUM : 10
2201 20:11:47.862440 SRAM_EN : 1
2202 20:11:47.862523 MD32_EN : 0
2203 20:11:47.865793 ===================================
2204 20:11:47.868987 [ANA_INIT] >>>>>>>>>>>>>>
2205 20:11:47.872414 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 20:11:47.875625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 20:11:47.879020 ===================================
2208 20:11:47.882359 data_rate = 2400,PCW = 0X5b00
2209 20:11:47.885874 ===================================
2210 20:11:47.888877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 20:11:47.892003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 20:11:47.898701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 20:11:47.902447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 20:11:47.905588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 20:11:47.908763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 20:11:47.912291 [ANA_INIT] flow start
2217 20:11:47.915483 [ANA_INIT] PLL >>>>>>>>
2218 20:11:47.915567 [ANA_INIT] PLL <<<<<<<<
2219 20:11:47.918808 [ANA_INIT] MIDPI >>>>>>>>
2220 20:11:47.922291 [ANA_INIT] MIDPI <<<<<<<<
2221 20:11:47.922374 [ANA_INIT] DLL >>>>>>>>
2222 20:11:47.925436 [ANA_INIT] DLL <<<<<<<<
2223 20:11:47.928847 [ANA_INIT] flow end
2224 20:11:47.932399 ============ LP4 DIFF to SE enter ============
2225 20:11:47.935441 ============ LP4 DIFF to SE exit ============
2226 20:11:47.938871 [ANA_INIT] <<<<<<<<<<<<<
2227 20:11:47.942126 [Flow] Enable top DCM control >>>>>
2228 20:11:47.945583 [Flow] Enable top DCM control <<<<<
2229 20:11:47.948763 Enable DLL master slave shuffle
2230 20:11:47.952207 ==============================================================
2231 20:11:47.955462 Gating Mode config
2232 20:11:47.962201 ==============================================================
2233 20:11:47.962294 Config description:
2234 20:11:47.972160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 20:11:47.978636 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 20:11:47.982288 SELPH_MODE 0: By rank 1: By Phase
2237 20:11:47.988927 ==============================================================
2238 20:11:47.992301 GAT_TRACK_EN = 1
2239 20:11:47.995324 RX_GATING_MODE = 2
2240 20:11:47.998920 RX_GATING_TRACK_MODE = 2
2241 20:11:48.002196 SELPH_MODE = 1
2242 20:11:48.005457 PICG_EARLY_EN = 1
2243 20:11:48.008634 VALID_LAT_VALUE = 1
2244 20:11:48.012188 ==============================================================
2245 20:11:48.015416 Enter into Gating configuration >>>>
2246 20:11:48.018708 Exit from Gating configuration <<<<
2247 20:11:48.022191 Enter into DVFS_PRE_config >>>>>
2248 20:11:48.032164 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 20:11:48.035690 Exit from DVFS_PRE_config <<<<<
2250 20:11:48.038636 Enter into PICG configuration >>>>
2251 20:11:48.042310 Exit from PICG configuration <<<<
2252 20:11:48.045368 [RX_INPUT] configuration >>>>>
2253 20:11:48.048716 [RX_INPUT] configuration <<<<<
2254 20:11:48.055317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 20:11:48.058865 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 20:11:48.065202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 20:11:48.071927 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 20:11:48.078589 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 20:11:48.085238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 20:11:48.088616 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 20:11:48.091817 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 20:11:48.095240 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 20:11:48.101728 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 20:11:48.105100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 20:11:48.108461 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 20:11:48.111676 ===================================
2267 20:11:48.114740 LPDDR4 DRAM CONFIGURATION
2268 20:11:48.118323 ===================================
2269 20:11:48.118410 EX_ROW_EN[0] = 0x0
2270 20:11:48.121675 EX_ROW_EN[1] = 0x0
2271 20:11:48.125027 LP4Y_EN = 0x0
2272 20:11:48.125113 WORK_FSP = 0x0
2273 20:11:48.128178 WL = 0x4
2274 20:11:48.128262 RL = 0x4
2275 20:11:48.131532 BL = 0x2
2276 20:11:48.131618 RPST = 0x0
2277 20:11:48.134841 RD_PRE = 0x0
2278 20:11:48.134924 WR_PRE = 0x1
2279 20:11:48.138400 WR_PST = 0x0
2280 20:11:48.138484 DBI_WR = 0x0
2281 20:11:48.141453 DBI_RD = 0x0
2282 20:11:48.141545 OTF = 0x1
2283 20:11:48.144778 ===================================
2284 20:11:48.147736 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 20:11:48.154411 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 20:11:48.157728 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 20:11:48.161070 ===================================
2288 20:11:48.164421 LPDDR4 DRAM CONFIGURATION
2289 20:11:48.168100 ===================================
2290 20:11:48.168187 EX_ROW_EN[0] = 0x10
2291 20:11:48.171362 EX_ROW_EN[1] = 0x0
2292 20:11:48.174491 LP4Y_EN = 0x0
2293 20:11:48.174574 WORK_FSP = 0x0
2294 20:11:48.177886 WL = 0x4
2295 20:11:48.177973 RL = 0x4
2296 20:11:48.181246 BL = 0x2
2297 20:11:48.181330 RPST = 0x0
2298 20:11:48.184469 RD_PRE = 0x0
2299 20:11:48.184551 WR_PRE = 0x1
2300 20:11:48.188129 WR_PST = 0x0
2301 20:11:48.188213 DBI_WR = 0x0
2302 20:11:48.191143 DBI_RD = 0x0
2303 20:11:48.191228 OTF = 0x1
2304 20:11:48.194564 ===================================
2305 20:11:48.201288 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 20:11:48.201379 ==
2307 20:11:48.204659 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 20:11:48.207687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 20:11:48.207775 ==
2310 20:11:48.211289 [Duty_Offset_Calibration]
2311 20:11:48.214679 B0:2 B1:0 CA:3
2312 20:11:48.214765
2313 20:11:48.217585 [DutyScan_Calibration_Flow] k_type=0
2314 20:11:48.226284
2315 20:11:48.226387 ==CLK 0==
2316 20:11:48.229158 Final CLK duty delay cell = 0
2317 20:11:48.232709 [0] MAX Duty = 5031%(X100), DQS PI = 12
2318 20:11:48.235952 [0] MIN Duty = 4906%(X100), DQS PI = 54
2319 20:11:48.236048 [0] AVG Duty = 4968%(X100)
2320 20:11:48.239284
2321 20:11:48.242824 CH0 CLK Duty spec in!! Max-Min= 125%
2322 20:11:48.245680 [DutyScan_Calibration_Flow] ====Done====
2323 20:11:48.245757
2324 20:11:48.249019 [DutyScan_Calibration_Flow] k_type=1
2325 20:11:48.264415
2326 20:11:48.264540 ==DQS 0 ==
2327 20:11:48.267718 Final DQS duty delay cell = 0
2328 20:11:48.271208 [0] MAX Duty = 5062%(X100), DQS PI = 14
2329 20:11:48.274609 [0] MIN Duty = 4907%(X100), DQS PI = 2
2330 20:11:48.274694 [0] AVG Duty = 4984%(X100)
2331 20:11:48.278042
2332 20:11:48.278129 ==DQS 1 ==
2333 20:11:48.281090 Final DQS duty delay cell = -4
2334 20:11:48.284637 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2335 20:11:48.287959 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2336 20:11:48.291161 [-4] AVG Duty = 4922%(X100)
2337 20:11:48.291261
2338 20:11:48.294417 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2339 20:11:48.294501
2340 20:11:48.297601 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2341 20:11:48.301335 [DutyScan_Calibration_Flow] ====Done====
2342 20:11:48.301419
2343 20:11:48.304289 [DutyScan_Calibration_Flow] k_type=3
2344 20:11:48.322052
2345 20:11:48.322204 ==DQM 0 ==
2346 20:11:48.325226 Final DQM duty delay cell = 0
2347 20:11:48.328551 [0] MAX Duty = 5124%(X100), DQS PI = 28
2348 20:11:48.331833 [0] MIN Duty = 4876%(X100), DQS PI = 0
2349 20:11:48.331923 [0] AVG Duty = 5000%(X100)
2350 20:11:48.335066
2351 20:11:48.335148 ==DQM 1 ==
2352 20:11:48.338532 Final DQM duty delay cell = 4
2353 20:11:48.341961 [4] MAX Duty = 5124%(X100), DQS PI = 50
2354 20:11:48.345207 [4] MIN Duty = 5000%(X100), DQS PI = 32
2355 20:11:48.348411 [4] AVG Duty = 5062%(X100)
2356 20:11:48.348496
2357 20:11:48.351761 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2358 20:11:48.351844
2359 20:11:48.355046 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2360 20:11:48.358452 [DutyScan_Calibration_Flow] ====Done====
2361 20:11:48.358536
2362 20:11:48.361677 [DutyScan_Calibration_Flow] k_type=2
2363 20:11:48.376877
2364 20:11:48.377021 ==DQ 0 ==
2365 20:11:48.380101 Final DQ duty delay cell = -4
2366 20:11:48.383554 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2367 20:11:48.386736 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2368 20:11:48.389956 [-4] AVG Duty = 4969%(X100)
2369 20:11:48.390045
2370 20:11:48.390110 ==DQ 1 ==
2371 20:11:48.393378 Final DQ duty delay cell = -4
2372 20:11:48.396696 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2373 20:11:48.399947 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2374 20:11:48.403258 [-4] AVG Duty = 4938%(X100)
2375 20:11:48.403342
2376 20:11:48.406966 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2377 20:11:48.407050
2378 20:11:48.410096 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 20:11:48.413223 [DutyScan_Calibration_Flow] ====Done====
2380 20:11:48.413306 ==
2381 20:11:48.416628 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 20:11:48.420226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 20:11:48.420310 ==
2384 20:11:48.423210 [Duty_Offset_Calibration]
2385 20:11:48.423297 B0:1 B1:-2 CA:0
2386 20:11:48.423361
2387 20:11:48.426527 [DutyScan_Calibration_Flow] k_type=0
2388 20:11:48.437223
2389 20:11:48.437347 ==CLK 0==
2390 20:11:48.441062 Final CLK duty delay cell = 0
2391 20:11:48.444336 [0] MAX Duty = 5031%(X100), DQS PI = 16
2392 20:11:48.447594 [0] MIN Duty = 4875%(X100), DQS PI = 58
2393 20:11:48.447678 [0] AVG Duty = 4953%(X100)
2394 20:11:48.450781
2395 20:11:48.450863 CH1 CLK Duty spec in!! Max-Min= 156%
2396 20:11:48.457705 [DutyScan_Calibration_Flow] ====Done====
2397 20:11:48.457801
2398 20:11:48.460981 [DutyScan_Calibration_Flow] k_type=1
2399 20:11:48.476158
2400 20:11:48.476294 ==DQS 0 ==
2401 20:11:48.479268 Final DQS duty delay cell = -4
2402 20:11:48.482629 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2403 20:11:48.485985 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2404 20:11:48.489339 [-4] AVG Duty = 4938%(X100)
2405 20:11:48.489429
2406 20:11:48.489538 ==DQS 1 ==
2407 20:11:48.492937 Final DQS duty delay cell = 0
2408 20:11:48.495858 [0] MAX Duty = 5093%(X100), DQS PI = 0
2409 20:11:48.499479 [0] MIN Duty = 4875%(X100), DQS PI = 26
2410 20:11:48.502740 [0] AVG Duty = 4984%(X100)
2411 20:11:48.502825
2412 20:11:48.505981 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2413 20:11:48.506064
2414 20:11:48.509230 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2415 20:11:48.512729 [DutyScan_Calibration_Flow] ====Done====
2416 20:11:48.512848
2417 20:11:48.515696 [DutyScan_Calibration_Flow] k_type=3
2418 20:11:48.532831
2419 20:11:48.532975 ==DQM 0 ==
2420 20:11:48.536106 Final DQM duty delay cell = 0
2421 20:11:48.539433 [0] MAX Duty = 5000%(X100), DQS PI = 22
2422 20:11:48.542812 [0] MIN Duty = 4844%(X100), DQS PI = 54
2423 20:11:48.542897 [0] AVG Duty = 4922%(X100)
2424 20:11:48.546232
2425 20:11:48.546314 ==DQM 1 ==
2426 20:11:48.549593 Final DQM duty delay cell = 0
2427 20:11:48.553080 [0] MAX Duty = 5031%(X100), DQS PI = 36
2428 20:11:48.555993 [0] MIN Duty = 4907%(X100), DQS PI = 4
2429 20:11:48.556078 [0] AVG Duty = 4969%(X100)
2430 20:11:48.559530
2431 20:11:48.562749 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2432 20:11:48.562835
2433 20:11:48.566098 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2434 20:11:48.569302 [DutyScan_Calibration_Flow] ====Done====
2435 20:11:48.569421
2436 20:11:48.572795 [DutyScan_Calibration_Flow] k_type=2
2437 20:11:48.589071
2438 20:11:48.589257 ==DQ 0 ==
2439 20:11:48.592280 Final DQ duty delay cell = 0
2440 20:11:48.595791 [0] MAX Duty = 5062%(X100), DQS PI = 18
2441 20:11:48.599188 [0] MIN Duty = 4938%(X100), DQS PI = 56
2442 20:11:48.599280 [0] AVG Duty = 5000%(X100)
2443 20:11:48.602619
2444 20:11:48.602698 ==DQ 1 ==
2445 20:11:48.605957 Final DQ duty delay cell = 0
2446 20:11:48.609134 [0] MAX Duty = 5093%(X100), DQS PI = 18
2447 20:11:48.612393 [0] MIN Duty = 4969%(X100), DQS PI = 26
2448 20:11:48.612474 [0] AVG Duty = 5031%(X100)
2449 20:11:48.612538
2450 20:11:48.615857 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2451 20:11:48.618904
2452 20:11:48.622215 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2453 20:11:48.625708 [DutyScan_Calibration_Flow] ====Done====
2454 20:11:48.629018 nWR fixed to 30
2455 20:11:48.629098 [ModeRegInit_LP4] CH0 RK0
2456 20:11:48.632333 [ModeRegInit_LP4] CH0 RK1
2457 20:11:48.635779 [ModeRegInit_LP4] CH1 RK0
2458 20:11:48.635867 [ModeRegInit_LP4] CH1 RK1
2459 20:11:48.638905 match AC timing 7
2460 20:11:48.642294 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 20:11:48.645765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 20:11:48.652472 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 20:11:48.655846 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 20:11:48.662366 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 20:11:48.662465 ==
2466 20:11:48.665733 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 20:11:48.669163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 20:11:48.669254 ==
2469 20:11:48.675739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 20:11:48.679315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 20:11:48.689076 [CA 0] Center 40 (10~71) winsize 62
2472 20:11:48.692585 [CA 1] Center 39 (9~70) winsize 62
2473 20:11:48.695759 [CA 2] Center 36 (6~66) winsize 61
2474 20:11:48.699029 [CA 3] Center 35 (5~66) winsize 62
2475 20:11:48.702332 [CA 4] Center 34 (4~65) winsize 62
2476 20:11:48.705722 [CA 5] Center 33 (3~64) winsize 62
2477 20:11:48.705814
2478 20:11:48.709046 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2479 20:11:48.709129
2480 20:11:48.712419 [CATrainingPosCal] consider 1 rank data
2481 20:11:48.715764 u2DelayCellTimex100 = 270/100 ps
2482 20:11:48.719104 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2483 20:11:48.725452 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 20:11:48.729173 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2485 20:11:48.732235 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 20:11:48.735582 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2487 20:11:48.739028 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2488 20:11:48.739115
2489 20:11:48.742368 CA PerBit enable=1, Macro0, CA PI delay=33
2490 20:11:48.742452
2491 20:11:48.745858 [CBTSetCACLKResult] CA Dly = 33
2492 20:11:48.749150 CS Dly: 7 (0~38)
2493 20:11:48.749234 ==
2494 20:11:48.752457 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 20:11:48.755564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 20:11:48.755650 ==
2497 20:11:48.758903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 20:11:48.765750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2499 20:11:48.775355 [CA 0] Center 40 (10~71) winsize 62
2500 20:11:48.778781 [CA 1] Center 40 (10~70) winsize 61
2501 20:11:48.781825 [CA 2] Center 35 (5~66) winsize 62
2502 20:11:48.785260 [CA 3] Center 35 (5~66) winsize 62
2503 20:11:48.788793 [CA 4] Center 34 (4~65) winsize 62
2504 20:11:48.792187 [CA 5] Center 33 (3~63) winsize 61
2505 20:11:48.792277
2506 20:11:48.795147 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2507 20:11:48.795232
2508 20:11:48.798627 [CATrainingPosCal] consider 2 rank data
2509 20:11:48.801906 u2DelayCellTimex100 = 270/100 ps
2510 20:11:48.805058 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2511 20:11:48.811867 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2512 20:11:48.815132 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2513 20:11:48.818668 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 20:11:48.821834 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2515 20:11:48.825101 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2516 20:11:48.825222
2517 20:11:48.828396 CA PerBit enable=1, Macro0, CA PI delay=33
2518 20:11:48.828485
2519 20:11:48.831931 [CBTSetCACLKResult] CA Dly = 33
2520 20:11:48.834929 CS Dly: 8 (0~40)
2521 20:11:48.835054
2522 20:11:48.838344 ----->DramcWriteLeveling(PI) begin...
2523 20:11:48.838430 ==
2524 20:11:48.841869 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 20:11:48.845205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 20:11:48.845291 ==
2527 20:11:48.848516 Write leveling (Byte 0): 34 => 34
2528 20:11:48.851897 Write leveling (Byte 1): 30 => 30
2529 20:11:48.855275 DramcWriteLeveling(PI) end<-----
2530 20:11:48.855360
2531 20:11:48.855424 ==
2532 20:11:48.858335 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 20:11:48.861778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 20:11:48.861874 ==
2535 20:11:48.865223 [Gating] SW mode calibration
2536 20:11:48.871774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 20:11:48.878267 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 20:11:48.881666 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2539 20:11:48.885237 0 15 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2540 20:11:48.891611 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 20:11:48.895413 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 20:11:48.898511 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 20:11:48.904932 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 20:11:48.908287 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 20:11:48.911766 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2546 20:11:48.915114 1 0 0 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
2547 20:11:48.921596 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2548 20:11:48.924901 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 20:11:48.928288 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 20:11:48.934822 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 20:11:48.938392 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 20:11:48.941800 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 20:11:48.948232 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2554 20:11:48.951581 1 1 0 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
2555 20:11:48.954978 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2556 20:11:48.961801 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 20:11:48.965216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 20:11:48.968361 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 20:11:48.974914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 20:11:48.978185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 20:11:48.981932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 20:11:48.988283 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 20:11:48.991636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 20:11:48.995155 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 20:11:49.001727 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 20:11:49.005066 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 20:11:49.008180 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 20:11:49.011667 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 20:11:49.018346 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 20:11:49.021379 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 20:11:49.024734 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 20:11:49.031688 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 20:11:49.034908 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 20:11:49.038481 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 20:11:49.044933 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 20:11:49.048204 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 20:11:49.051709 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 20:11:49.058123 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 20:11:49.061585 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 20:11:49.065155 Total UI for P1: 0, mck2ui 16
2581 20:11:49.068251 best dqsien dly found for B0: ( 1, 3, 30)
2582 20:11:49.071503 Total UI for P1: 0, mck2ui 16
2583 20:11:49.074952 best dqsien dly found for B1: ( 1, 4, 2)
2584 20:11:49.078352 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2585 20:11:49.081383 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2586 20:11:49.081535
2587 20:11:49.084761 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2588 20:11:49.088117 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2589 20:11:49.091511 [Gating] SW calibration Done
2590 20:11:49.091595 ==
2591 20:11:49.094824 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 20:11:49.098398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 20:11:49.098510 ==
2594 20:11:49.101234 RX Vref Scan: 0
2595 20:11:49.101341
2596 20:11:49.104802 RX Vref 0 -> 0, step: 1
2597 20:11:49.104910
2598 20:11:49.105005 RX Delay -40 -> 252, step: 8
2599 20:11:49.111588 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2600 20:11:49.114770 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2601 20:11:49.118069 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2602 20:11:49.121406 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2603 20:11:49.124905 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2604 20:11:49.131289 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2605 20:11:49.134880 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2606 20:11:49.138240 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2607 20:11:49.141304 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2608 20:11:49.144810 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2609 20:11:49.148228 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2610 20:11:49.154678 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2611 20:11:49.158062 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2612 20:11:49.161482 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2613 20:11:49.164913 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2614 20:11:49.171562 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2615 20:11:49.171666 ==
2616 20:11:49.175014 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 20:11:49.177937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 20:11:49.178058 ==
2619 20:11:49.178157 DQS Delay:
2620 20:11:49.181416 DQS0 = 0, DQS1 = 0
2621 20:11:49.181539 DQM Delay:
2622 20:11:49.184679 DQM0 = 112, DQM1 = 102
2623 20:11:49.184763 DQ Delay:
2624 20:11:49.188209 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2625 20:11:49.191379 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2626 20:11:49.194798 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2627 20:11:49.198185 DQ12 =103, DQ13 =111, DQ14 =115, DQ15 =111
2628 20:11:49.198272
2629 20:11:49.198338
2630 20:11:49.198399 ==
2631 20:11:49.201686 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 20:11:49.208206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 20:11:49.208307 ==
2634 20:11:49.208374
2635 20:11:49.208436
2636 20:11:49.208499 TX Vref Scan disable
2637 20:11:49.211425 == TX Byte 0 ==
2638 20:11:49.214864 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2639 20:11:49.221757 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2640 20:11:49.221860 == TX Byte 1 ==
2641 20:11:49.224969 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2642 20:11:49.231643 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2643 20:11:49.231742 ==
2644 20:11:49.235018 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 20:11:49.238209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 20:11:49.238298 ==
2647 20:11:49.249792 TX Vref=22, minBit 0, minWin=25, winSum=412
2648 20:11:49.253030 TX Vref=24, minBit 0, minWin=26, winSum=420
2649 20:11:49.256562 TX Vref=26, minBit 4, minWin=26, winSum=428
2650 20:11:49.259855 TX Vref=28, minBit 8, minWin=26, winSum=430
2651 20:11:49.263080 TX Vref=30, minBit 7, minWin=26, winSum=430
2652 20:11:49.269615 TX Vref=32, minBit 1, minWin=26, winSum=425
2653 20:11:49.273056 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 28
2654 20:11:49.273148
2655 20:11:49.276357 Final TX Range 1 Vref 28
2656 20:11:49.276441
2657 20:11:49.276506 ==
2658 20:11:49.279673 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 20:11:49.282912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 20:11:49.283000 ==
2661 20:11:49.286574
2662 20:11:49.286657
2663 20:11:49.286721 TX Vref Scan disable
2664 20:11:49.289806 == TX Byte 0 ==
2665 20:11:49.292841 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2666 20:11:49.296522 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2667 20:11:49.299762 == TX Byte 1 ==
2668 20:11:49.302858 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2669 20:11:49.306433 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2670 20:11:49.309905
2671 20:11:49.309991 [DATLAT]
2672 20:11:49.310057 Freq=1200, CH0 RK0
2673 20:11:49.310117
2674 20:11:49.312827 DATLAT Default: 0xd
2675 20:11:49.312913 0, 0xFFFF, sum = 0
2676 20:11:49.316339 1, 0xFFFF, sum = 0
2677 20:11:49.316440 2, 0xFFFF, sum = 0
2678 20:11:49.319397 3, 0xFFFF, sum = 0
2679 20:11:49.322749 4, 0xFFFF, sum = 0
2680 20:11:49.322861 5, 0xFFFF, sum = 0
2681 20:11:49.326089 6, 0xFFFF, sum = 0
2682 20:11:49.326167 7, 0xFFFF, sum = 0
2683 20:11:49.329334 8, 0xFFFF, sum = 0
2684 20:11:49.329439 9, 0xFFFF, sum = 0
2685 20:11:49.332778 10, 0xFFFF, sum = 0
2686 20:11:49.332918 11, 0xFFFF, sum = 0
2687 20:11:49.336133 12, 0x0, sum = 1
2688 20:11:49.336236 13, 0x0, sum = 2
2689 20:11:49.339498 14, 0x0, sum = 3
2690 20:11:49.339621 15, 0x0, sum = 4
2691 20:11:49.339728 best_step = 13
2692 20:11:49.342918
2693 20:11:49.343011 ==
2694 20:11:49.346244 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 20:11:49.349270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 20:11:49.349362 ==
2697 20:11:49.349450 RX Vref Scan: 1
2698 20:11:49.349535
2699 20:11:49.352938 Set Vref Range= 32 -> 127
2700 20:11:49.353039
2701 20:11:49.356186 RX Vref 32 -> 127, step: 1
2702 20:11:49.356271
2703 20:11:49.359522 RX Delay -37 -> 252, step: 4
2704 20:11:49.359608
2705 20:11:49.362743 Set Vref, RX VrefLevel [Byte0]: 32
2706 20:11:49.366113 [Byte1]: 32
2707 20:11:49.366237
2708 20:11:49.369456 Set Vref, RX VrefLevel [Byte0]: 33
2709 20:11:49.372872 [Byte1]: 33
2710 20:11:49.376113
2711 20:11:49.376200 Set Vref, RX VrefLevel [Byte0]: 34
2712 20:11:49.379520 [Byte1]: 34
2713 20:11:49.384061
2714 20:11:49.384180 Set Vref, RX VrefLevel [Byte0]: 35
2715 20:11:49.387570 [Byte1]: 35
2716 20:11:49.392108
2717 20:11:49.392233 Set Vref, RX VrefLevel [Byte0]: 36
2718 20:11:49.395322 [Byte1]: 36
2719 20:11:49.399999
2720 20:11:49.400121 Set Vref, RX VrefLevel [Byte0]: 37
2721 20:11:49.403419 [Byte1]: 37
2722 20:11:49.408264
2723 20:11:49.408384 Set Vref, RX VrefLevel [Byte0]: 38
2724 20:11:49.411595 [Byte1]: 38
2725 20:11:49.416320
2726 20:11:49.416413 Set Vref, RX VrefLevel [Byte0]: 39
2727 20:11:49.419692 [Byte1]: 39
2728 20:11:49.424080
2729 20:11:49.424164 Set Vref, RX VrefLevel [Byte0]: 40
2730 20:11:49.427342 [Byte1]: 40
2731 20:11:49.432378
2732 20:11:49.432470 Set Vref, RX VrefLevel [Byte0]: 41
2733 20:11:49.435452 [Byte1]: 41
2734 20:11:49.440352
2735 20:11:49.440483 Set Vref, RX VrefLevel [Byte0]: 42
2736 20:11:49.443385 [Byte1]: 42
2737 20:11:49.448436
2738 20:11:49.448538 Set Vref, RX VrefLevel [Byte0]: 43
2739 20:11:49.451288 [Byte1]: 43
2740 20:11:49.456146
2741 20:11:49.456237 Set Vref, RX VrefLevel [Byte0]: 44
2742 20:11:49.459612 [Byte1]: 44
2743 20:11:49.464169
2744 20:11:49.464263 Set Vref, RX VrefLevel [Byte0]: 45
2745 20:11:49.467399 [Byte1]: 45
2746 20:11:49.472286
2747 20:11:49.472407 Set Vref, RX VrefLevel [Byte0]: 46
2748 20:11:49.475604 [Byte1]: 46
2749 20:11:49.480256
2750 20:11:49.480351 Set Vref, RX VrefLevel [Byte0]: 47
2751 20:11:49.483450 [Byte1]: 47
2752 20:11:49.488209
2753 20:11:49.488298 Set Vref, RX VrefLevel [Byte0]: 48
2754 20:11:49.491579 [Byte1]: 48
2755 20:11:49.496274
2756 20:11:49.496358 Set Vref, RX VrefLevel [Byte0]: 49
2757 20:11:49.499746 [Byte1]: 49
2758 20:11:49.504198
2759 20:11:49.504314 Set Vref, RX VrefLevel [Byte0]: 50
2760 20:11:49.507684 [Byte1]: 50
2761 20:11:49.512425
2762 20:11:49.512513 Set Vref, RX VrefLevel [Byte0]: 51
2763 20:11:49.515496 [Byte1]: 51
2764 20:11:49.519986
2765 20:11:49.520076 Set Vref, RX VrefLevel [Byte0]: 52
2766 20:11:49.523584 [Byte1]: 52
2767 20:11:49.527999
2768 20:11:49.528108 Set Vref, RX VrefLevel [Byte0]: 53
2769 20:11:49.531451 [Byte1]: 53
2770 20:11:49.536252
2771 20:11:49.536368 Set Vref, RX VrefLevel [Byte0]: 54
2772 20:11:49.539372 [Byte1]: 54
2773 20:11:49.544258
2774 20:11:49.544361 Set Vref, RX VrefLevel [Byte0]: 55
2775 20:11:49.547506 [Byte1]: 55
2776 20:11:49.552111
2777 20:11:49.552208 Set Vref, RX VrefLevel [Byte0]: 56
2778 20:11:49.555164 [Byte1]: 56
2779 20:11:49.560058
2780 20:11:49.560193 Set Vref, RX VrefLevel [Byte0]: 57
2781 20:11:49.566371 [Byte1]: 57
2782 20:11:49.566483
2783 20:11:49.569809 Set Vref, RX VrefLevel [Byte0]: 58
2784 20:11:49.573285 [Byte1]: 58
2785 20:11:49.573388
2786 20:11:49.576555 Set Vref, RX VrefLevel [Byte0]: 59
2787 20:11:49.579938 [Byte1]: 59
2788 20:11:49.584010
2789 20:11:49.584129 Set Vref, RX VrefLevel [Byte0]: 60
2790 20:11:49.587234 [Byte1]: 60
2791 20:11:49.592133
2792 20:11:49.592239 Set Vref, RX VrefLevel [Byte0]: 61
2793 20:11:49.595543 [Byte1]: 61
2794 20:11:49.600135
2795 20:11:49.600250 Set Vref, RX VrefLevel [Byte0]: 62
2796 20:11:49.603520 [Byte1]: 62
2797 20:11:49.608205
2798 20:11:49.608290 Set Vref, RX VrefLevel [Byte0]: 63
2799 20:11:49.611209 [Byte1]: 63
2800 20:11:49.616008
2801 20:11:49.616101 Set Vref, RX VrefLevel [Byte0]: 64
2802 20:11:49.619599 [Byte1]: 64
2803 20:11:49.623974
2804 20:11:49.624056 Set Vref, RX VrefLevel [Byte0]: 65
2805 20:11:49.627268 [Byte1]: 65
2806 20:11:49.632467
2807 20:11:49.632578 Set Vref, RX VrefLevel [Byte0]: 66
2808 20:11:49.635341 [Byte1]: 66
2809 20:11:49.639933
2810 20:11:49.640022 Set Vref, RX VrefLevel [Byte0]: 67
2811 20:11:49.643635 [Byte1]: 67
2812 20:11:49.648020
2813 20:11:49.648108 Set Vref, RX VrefLevel [Byte0]: 68
2814 20:11:49.651331 [Byte1]: 68
2815 20:11:49.656428
2816 20:11:49.656517 Set Vref, RX VrefLevel [Byte0]: 69
2817 20:11:49.659275 [Byte1]: 69
2818 20:11:49.664260
2819 20:11:49.664350 Set Vref, RX VrefLevel [Byte0]: 70
2820 20:11:49.667264 [Byte1]: 70
2821 20:11:49.672019
2822 20:11:49.672109 Set Vref, RX VrefLevel [Byte0]: 71
2823 20:11:49.675403 [Byte1]: 71
2824 20:11:49.680302
2825 20:11:49.680397 Set Vref, RX VrefLevel [Byte0]: 72
2826 20:11:49.683428 [Byte1]: 72
2827 20:11:49.688171
2828 20:11:49.688263 Set Vref, RX VrefLevel [Byte0]: 73
2829 20:11:49.691461 [Byte1]: 73
2830 20:11:49.696254
2831 20:11:49.696345 Set Vref, RX VrefLevel [Byte0]: 74
2832 20:11:49.699486 [Byte1]: 74
2833 20:11:49.704162
2834 20:11:49.704255 Set Vref, RX VrefLevel [Byte0]: 75
2835 20:11:49.707304 [Byte1]: 75
2836 20:11:49.712224
2837 20:11:49.712316 Final RX Vref Byte 0 = 60 to rank0
2838 20:11:49.715291 Final RX Vref Byte 1 = 45 to rank0
2839 20:11:49.718788 Final RX Vref Byte 0 = 60 to rank1
2840 20:11:49.721954 Final RX Vref Byte 1 = 45 to rank1==
2841 20:11:49.725457 Dram Type= 6, Freq= 0, CH_0, rank 0
2842 20:11:49.731924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 20:11:49.732023 ==
2844 20:11:49.732091 DQS Delay:
2845 20:11:49.735433 DQS0 = 0, DQS1 = 0
2846 20:11:49.735524 DQM Delay:
2847 20:11:49.735630 DQM0 = 111, DQM1 = 98
2848 20:11:49.738709 DQ Delay:
2849 20:11:49.742287 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2850 20:11:49.745416 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2851 20:11:49.748544 DQ8 =90, DQ9 =82, DQ10 =98, DQ11 =90
2852 20:11:49.751994 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2853 20:11:49.752080
2854 20:11:49.752163
2855 20:11:49.758686 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2856 20:11:49.761919 CH0 RK0: MR19=303, MR18=FEFD
2857 20:11:49.768636 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2858 20:11:49.768741
2859 20:11:49.772126 ----->DramcWriteLeveling(PI) begin...
2860 20:11:49.772213 ==
2861 20:11:49.775446 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 20:11:49.778581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 20:11:49.778670 ==
2864 20:11:49.782098 Write leveling (Byte 0): 33 => 33
2865 20:11:49.785261 Write leveling (Byte 1): 31 => 31
2866 20:11:49.788755 DramcWriteLeveling(PI) end<-----
2867 20:11:49.788845
2868 20:11:49.788910 ==
2869 20:11:49.791857 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 20:11:49.798751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 20:11:49.798848 ==
2872 20:11:49.798915 [Gating] SW mode calibration
2873 20:11:49.808342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2874 20:11:49.811823 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2875 20:11:49.815335 0 15 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2876 20:11:49.821933 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 20:11:49.825098 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 20:11:49.828669 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 20:11:49.835067 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 20:11:49.838500 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 20:11:49.841741 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 20:11:49.848492 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2883 20:11:49.851572 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2884 20:11:49.854949 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 20:11:49.861827 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 20:11:49.864872 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 20:11:49.868409 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 20:11:49.875135 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 20:11:49.878368 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2890 20:11:49.881813 1 0 28 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
2891 20:11:49.888473 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2892 20:11:49.891801 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 20:11:49.895065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 20:11:49.901400 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 20:11:49.904865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 20:11:49.908256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 20:11:49.915148 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 20:11:49.918237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2899 20:11:49.921408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2900 20:11:49.924818 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 20:11:49.931569 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 20:11:49.934899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 20:11:49.938223 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 20:11:49.944790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 20:11:49.948278 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 20:11:49.951462 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 20:11:49.958083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 20:11:49.961223 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 20:11:49.964982 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 20:11:49.971569 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 20:11:49.974871 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 20:11:49.977943 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 20:11:49.984611 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 20:11:49.987816 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2915 20:11:49.991145 Total UI for P1: 0, mck2ui 16
2916 20:11:49.994926 best dqsien dly found for B0: ( 1, 3, 26)
2917 20:11:49.998113 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2918 20:11:50.004786 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 20:11:50.004931 Total UI for P1: 0, mck2ui 16
2920 20:11:50.011531 best dqsien dly found for B1: ( 1, 4, 0)
2921 20:11:50.014952 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2922 20:11:50.018338 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2923 20:11:50.018459
2924 20:11:50.021593 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2925 20:11:50.024899 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2926 20:11:50.028208 [Gating] SW calibration Done
2927 20:11:50.028317 ==
2928 20:11:50.031296 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 20:11:50.034730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 20:11:50.034857 ==
2931 20:11:50.038119 RX Vref Scan: 0
2932 20:11:50.038225
2933 20:11:50.038319 RX Vref 0 -> 0, step: 1
2934 20:11:50.038412
2935 20:11:50.041487 RX Delay -40 -> 252, step: 8
2936 20:11:50.044868 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2937 20:11:50.048162 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2938 20:11:50.054675 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2939 20:11:50.058007 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2940 20:11:50.061271 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2941 20:11:50.064574 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2942 20:11:50.067852 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2943 20:11:50.074575 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2944 20:11:50.078006 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2945 20:11:50.081304 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2946 20:11:50.084494 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2947 20:11:50.087930 iDelay=200, Bit 11, Center 87 (16 ~ 159) 144
2948 20:11:50.094720 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2949 20:11:50.098133 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
2950 20:11:50.101444 iDelay=200, Bit 14, Center 107 (32 ~ 183) 152
2951 20:11:50.104696 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2952 20:11:50.104778 ==
2953 20:11:50.108147 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 20:11:50.111383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 20:11:50.114750 ==
2956 20:11:50.114871 DQS Delay:
2957 20:11:50.114970 DQS0 = 0, DQS1 = 0
2958 20:11:50.118156 DQM Delay:
2959 20:11:50.118275 DQM0 = 112, DQM1 = 99
2960 20:11:50.121678 DQ Delay:
2961 20:11:50.124425 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2962 20:11:50.127735 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2963 20:11:50.131286 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =87
2964 20:11:50.134602 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =111
2965 20:11:50.134703
2966 20:11:50.134768
2967 20:11:50.134830 ==
2968 20:11:50.137838 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 20:11:50.141143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 20:11:50.141234 ==
2971 20:11:50.141302
2972 20:11:50.141363
2973 20:11:50.144466 TX Vref Scan disable
2974 20:11:50.147652 == TX Byte 0 ==
2975 20:11:50.150989 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2976 20:11:50.154764 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2977 20:11:50.157561 == TX Byte 1 ==
2978 20:11:50.160943 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2979 20:11:50.164266 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2980 20:11:50.164388 ==
2981 20:11:50.167669 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 20:11:50.174226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 20:11:50.174387 ==
2984 20:11:50.184766 TX Vref=22, minBit 1, minWin=26, winSum=424
2985 20:11:50.188322 TX Vref=24, minBit 0, minWin=26, winSum=431
2986 20:11:50.191634 TX Vref=26, minBit 1, minWin=26, winSum=435
2987 20:11:50.194937 TX Vref=28, minBit 3, minWin=26, winSum=440
2988 20:11:50.198112 TX Vref=30, minBit 8, minWin=27, winSum=445
2989 20:11:50.201559 TX Vref=32, minBit 8, minWin=26, winSum=439
2990 20:11:50.208338 [TxChooseVref] Worse bit 8, Min win 27, Win sum 445, Final Vref 30
2991 20:11:50.208469
2992 20:11:50.211605 Final TX Range 1 Vref 30
2993 20:11:50.211719
2994 20:11:50.211817 ==
2995 20:11:50.214988 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 20:11:50.218221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 20:11:50.218327 ==
2998 20:11:50.218420
2999 20:11:50.218510
3000 20:11:50.221496 TX Vref Scan disable
3001 20:11:50.224945 == TX Byte 0 ==
3002 20:11:50.228193 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3003 20:11:50.231584 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3004 20:11:50.235125 == TX Byte 1 ==
3005 20:11:50.238374 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3006 20:11:50.241695 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3007 20:11:50.241856
3008 20:11:50.244877 [DATLAT]
3009 20:11:50.245012 Freq=1200, CH0 RK1
3010 20:11:50.245133
3011 20:11:50.248092 DATLAT Default: 0xd
3012 20:11:50.248200 0, 0xFFFF, sum = 0
3013 20:11:50.251562 1, 0xFFFF, sum = 0
3014 20:11:50.251678 2, 0xFFFF, sum = 0
3015 20:11:50.255054 3, 0xFFFF, sum = 0
3016 20:11:50.255190 4, 0xFFFF, sum = 0
3017 20:11:50.258167 5, 0xFFFF, sum = 0
3018 20:11:50.258300 6, 0xFFFF, sum = 0
3019 20:11:50.261759 7, 0xFFFF, sum = 0
3020 20:11:50.261898 8, 0xFFFF, sum = 0
3021 20:11:50.265121 9, 0xFFFF, sum = 0
3022 20:11:50.268303 10, 0xFFFF, sum = 0
3023 20:11:50.268418 11, 0xFFFF, sum = 0
3024 20:11:50.271510 12, 0x0, sum = 1
3025 20:11:50.271624 13, 0x0, sum = 2
3026 20:11:50.274761 14, 0x0, sum = 3
3027 20:11:50.274867 15, 0x0, sum = 4
3028 20:11:50.274961 best_step = 13
3029 20:11:50.275049
3030 20:11:50.278144 ==
3031 20:11:50.281719 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 20:11:50.284895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 20:11:50.285017 ==
3034 20:11:50.285115 RX Vref Scan: 0
3035 20:11:50.285213
3036 20:11:50.288180 RX Vref 0 -> 0, step: 1
3037 20:11:50.288287
3038 20:11:50.291299 RX Delay -37 -> 252, step: 4
3039 20:11:50.294708 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3040 20:11:50.301100 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3041 20:11:50.304697 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3042 20:11:50.307886 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3043 20:11:50.311311 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3044 20:11:50.314696 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3045 20:11:50.321363 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3046 20:11:50.324629 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3047 20:11:50.328038 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3048 20:11:50.331379 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3049 20:11:50.334664 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3050 20:11:50.338375 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3051 20:11:50.344614 iDelay=195, Bit 12, Center 106 (35 ~ 178) 144
3052 20:11:50.348021 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3053 20:11:50.351398 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3054 20:11:50.354695 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3055 20:11:50.354838 ==
3056 20:11:50.358022 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 20:11:50.364905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 20:11:50.365053 ==
3059 20:11:50.365122 DQS Delay:
3060 20:11:50.365183 DQS0 = 0, DQS1 = 0
3061 20:11:50.368207 DQM Delay:
3062 20:11:50.368302 DQM0 = 110, DQM1 = 98
3063 20:11:50.371599 DQ Delay:
3064 20:11:50.374650 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3065 20:11:50.378066 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3066 20:11:50.381617 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3067 20:11:50.384823 DQ12 =106, DQ13 =106, DQ14 =110, DQ15 =108
3068 20:11:50.384910
3069 20:11:50.384974
3070 20:11:50.391236 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3071 20:11:50.394984 CH0 RK1: MR19=403, MR18=11F9
3072 20:11:50.401497 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3073 20:11:50.404554 [RxdqsGatingPostProcess] freq 1200
3074 20:11:50.411281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3075 20:11:50.414861 best DQS0 dly(2T, 0.5T) = (0, 11)
3076 20:11:50.414985 best DQS1 dly(2T, 0.5T) = (0, 12)
3077 20:11:50.417887 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3078 20:11:50.421208 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3079 20:11:50.424863 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 20:11:50.427895 best DQS1 dly(2T, 0.5T) = (0, 12)
3081 20:11:50.431229 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 20:11:50.434629 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3083 20:11:50.437973 Pre-setting of DQS Precalculation
3084 20:11:50.444700 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3085 20:11:50.444810 ==
3086 20:11:50.448080 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 20:11:50.451299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 20:11:50.451389 ==
3089 20:11:50.458190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 20:11:50.461787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 20:11:50.470666 [CA 0] Center 37 (7~67) winsize 61
3092 20:11:50.474036 [CA 1] Center 38 (8~68) winsize 61
3093 20:11:50.477677 [CA 2] Center 34 (4~64) winsize 61
3094 20:11:50.480860 [CA 3] Center 33 (3~64) winsize 62
3095 20:11:50.484370 [CA 4] Center 34 (4~64) winsize 61
3096 20:11:50.487369 [CA 5] Center 33 (3~63) winsize 61
3097 20:11:50.487465
3098 20:11:50.490759 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3099 20:11:50.490845
3100 20:11:50.494176 [CATrainingPosCal] consider 1 rank data
3101 20:11:50.497311 u2DelayCellTimex100 = 270/100 ps
3102 20:11:50.500753 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3103 20:11:50.504264 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3104 20:11:50.510652 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 20:11:50.513965 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3106 20:11:50.517261 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 20:11:50.520612 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3108 20:11:50.520708
3109 20:11:50.523976 CA PerBit enable=1, Macro0, CA PI delay=33
3110 20:11:50.524083
3111 20:11:50.527515 [CBTSetCACLKResult] CA Dly = 33
3112 20:11:50.527655 CS Dly: 6 (0~37)
3113 20:11:50.527752 ==
3114 20:11:50.530833 Dram Type= 6, Freq= 0, CH_1, rank 1
3115 20:11:50.537471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 20:11:50.537631 ==
3117 20:11:50.540693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 20:11:50.547317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 20:11:50.556196 [CA 0] Center 37 (7~67) winsize 61
3120 20:11:50.559676 [CA 1] Center 37 (7~68) winsize 62
3121 20:11:50.562859 [CA 2] Center 34 (4~65) winsize 62
3122 20:11:50.566346 [CA 3] Center 33 (3~64) winsize 62
3123 20:11:50.569622 [CA 4] Center 34 (4~64) winsize 61
3124 20:11:50.573104 [CA 5] Center 33 (3~63) winsize 61
3125 20:11:50.573214
3126 20:11:50.576581 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3127 20:11:50.576680
3128 20:11:50.579453 [CATrainingPosCal] consider 2 rank data
3129 20:11:50.583124 u2DelayCellTimex100 = 270/100 ps
3130 20:11:50.586277 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3131 20:11:50.589429 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3132 20:11:50.596118 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 20:11:50.599453 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 20:11:50.602997 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 20:11:50.606389 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 20:11:50.606506
3137 20:11:50.609774 CA PerBit enable=1, Macro0, CA PI delay=33
3138 20:11:50.609885
3139 20:11:50.613030 [CBTSetCACLKResult] CA Dly = 33
3140 20:11:50.613115 CS Dly: 7 (0~39)
3141 20:11:50.613212
3142 20:11:50.616278 ----->DramcWriteLeveling(PI) begin...
3143 20:11:50.619641 ==
3144 20:11:50.619753 Dram Type= 6, Freq= 0, CH_1, rank 0
3145 20:11:50.626511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 20:11:50.626612 ==
3147 20:11:50.629634 Write leveling (Byte 0): 25 => 25
3148 20:11:50.632946 Write leveling (Byte 1): 28 => 28
3149 20:11:50.636231 DramcWriteLeveling(PI) end<-----
3150 20:11:50.636325
3151 20:11:50.636393 ==
3152 20:11:50.639521 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 20:11:50.643015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 20:11:50.643103 ==
3155 20:11:50.646330 [Gating] SW mode calibration
3156 20:11:50.652841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3157 20:11:50.659563 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3158 20:11:50.662793 0 15 0 | B1->B0 | 2f2f 302f | 1 1 | (1 1) (0 0)
3159 20:11:50.666307 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 20:11:50.669647 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 20:11:50.676373 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 20:11:50.679769 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 20:11:50.682962 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 20:11:50.689743 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 20:11:50.693044 0 15 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
3166 20:11:50.696325 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3167 20:11:50.703077 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 20:11:50.706178 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 20:11:50.709912 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 20:11:50.716123 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 20:11:50.719584 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 20:11:50.722891 1 0 24 | B1->B0 | 2626 2423 | 0 1 | (0 0) (0 0)
3173 20:11:50.729381 1 0 28 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
3174 20:11:50.732819 1 1 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
3175 20:11:50.736361 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 20:11:50.742971 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 20:11:50.746157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 20:11:50.749835 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 20:11:50.756056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 20:11:50.759521 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 20:11:50.762635 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 20:11:50.766009 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3183 20:11:50.772636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 20:11:50.775849 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 20:11:50.779368 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 20:11:50.785997 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 20:11:50.789456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 20:11:50.792736 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 20:11:50.799349 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 20:11:50.802793 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 20:11:50.806131 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 20:11:50.812662 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 20:11:50.815859 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 20:11:50.819623 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 20:11:50.826031 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 20:11:50.829450 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3197 20:11:50.832771 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3198 20:11:50.839307 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3199 20:11:50.839421 Total UI for P1: 0, mck2ui 16
3200 20:11:50.846017 best dqsien dly found for B1: ( 1, 3, 26)
3201 20:11:50.849198 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 20:11:50.852582 Total UI for P1: 0, mck2ui 16
3203 20:11:50.855937 best dqsien dly found for B0: ( 1, 3, 30)
3204 20:11:50.859267 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3205 20:11:50.862492 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3206 20:11:50.862581
3207 20:11:50.865922 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3208 20:11:50.869218 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3209 20:11:50.872559 [Gating] SW calibration Done
3210 20:11:50.872649 ==
3211 20:11:50.875904 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 20:11:50.879356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 20:11:50.879441 ==
3214 20:11:50.882758 RX Vref Scan: 0
3215 20:11:50.882845
3216 20:11:50.885983 RX Vref 0 -> 0, step: 1
3217 20:11:50.886066
3218 20:11:50.886129 RX Delay -40 -> 252, step: 8
3219 20:11:50.892559 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3220 20:11:50.896208 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3221 20:11:50.899281 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3222 20:11:50.902694 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3223 20:11:50.905904 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3224 20:11:50.912670 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3225 20:11:50.915977 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3226 20:11:50.919208 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3227 20:11:50.922385 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3228 20:11:50.925944 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3229 20:11:50.932515 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3230 20:11:50.936305 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3231 20:11:50.939192 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3232 20:11:50.942503 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3233 20:11:50.945974 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3234 20:11:50.952676 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3235 20:11:50.952783 ==
3236 20:11:50.956141 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 20:11:50.959329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 20:11:50.959417 ==
3239 20:11:50.959483 DQS Delay:
3240 20:11:50.962706 DQS0 = 0, DQS1 = 0
3241 20:11:50.962789 DQM Delay:
3242 20:11:50.965802 DQM0 = 114, DQM1 = 107
3243 20:11:50.965885 DQ Delay:
3244 20:11:50.969138 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115
3245 20:11:50.972580 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3246 20:11:50.976009 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3247 20:11:50.979412 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3248 20:11:50.979500
3249 20:11:50.979565
3250 20:11:50.979625 ==
3251 20:11:50.982599 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 20:11:50.989141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 20:11:50.989246 ==
3254 20:11:50.989312
3255 20:11:50.989371
3256 20:11:50.992530 TX Vref Scan disable
3257 20:11:50.992611 == TX Byte 0 ==
3258 20:11:50.995861 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 20:11:51.002540 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 20:11:51.002639 == TX Byte 1 ==
3261 20:11:51.005851 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 20:11:51.012463 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 20:11:51.012559 ==
3264 20:11:51.015802 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 20:11:51.019226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 20:11:51.019309 ==
3267 20:11:51.031048 TX Vref=22, minBit 10, minWin=24, winSum=408
3268 20:11:51.034432 TX Vref=24, minBit 8, minWin=25, winSum=413
3269 20:11:51.037732 TX Vref=26, minBit 8, minWin=25, winSum=415
3270 20:11:51.040879 TX Vref=28, minBit 9, minWin=25, winSum=423
3271 20:11:51.044354 TX Vref=30, minBit 9, minWin=24, winSum=422
3272 20:11:51.047918 TX Vref=32, minBit 9, minWin=24, winSum=421
3273 20:11:51.054355 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
3274 20:11:51.054455
3275 20:11:51.057484 Final TX Range 1 Vref 28
3276 20:11:51.057568
3277 20:11:51.057634 ==
3278 20:11:51.060787 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 20:11:51.064455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 20:11:51.064540 ==
3281 20:11:51.064606
3282 20:11:51.067436
3283 20:11:51.067522 TX Vref Scan disable
3284 20:11:51.070984 == TX Byte 0 ==
3285 20:11:51.074320 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 20:11:51.077772 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 20:11:51.080857 == TX Byte 1 ==
3288 20:11:51.084283 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 20:11:51.087719 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 20:11:51.087806
3291 20:11:51.091014 [DATLAT]
3292 20:11:51.091096 Freq=1200, CH1 RK0
3293 20:11:51.091160
3294 20:11:51.094649 DATLAT Default: 0xd
3295 20:11:51.094733 0, 0xFFFF, sum = 0
3296 20:11:51.097614 1, 0xFFFF, sum = 0
3297 20:11:51.097698 2, 0xFFFF, sum = 0
3298 20:11:51.101277 3, 0xFFFF, sum = 0
3299 20:11:51.101387 4, 0xFFFF, sum = 0
3300 20:11:51.104602 5, 0xFFFF, sum = 0
3301 20:11:51.104685 6, 0xFFFF, sum = 0
3302 20:11:51.107869 7, 0xFFFF, sum = 0
3303 20:11:51.107953 8, 0xFFFF, sum = 0
3304 20:11:51.111172 9, 0xFFFF, sum = 0
3305 20:11:51.114212 10, 0xFFFF, sum = 0
3306 20:11:51.114297 11, 0xFFFF, sum = 0
3307 20:11:51.117672 12, 0x0, sum = 1
3308 20:11:51.117755 13, 0x0, sum = 2
3309 20:11:51.117820 14, 0x0, sum = 3
3310 20:11:51.120995 15, 0x0, sum = 4
3311 20:11:51.121077 best_step = 13
3312 20:11:51.121141
3313 20:11:51.124299 ==
3314 20:11:51.124382 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 20:11:51.131074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 20:11:51.131166 ==
3317 20:11:51.131231 RX Vref Scan: 1
3318 20:11:51.131291
3319 20:11:51.134422 Set Vref Range= 32 -> 127
3320 20:11:51.134503
3321 20:11:51.137466 RX Vref 32 -> 127, step: 1
3322 20:11:51.137559
3323 20:11:51.140865 RX Delay -21 -> 252, step: 4
3324 20:11:51.140955
3325 20:11:51.144080 Set Vref, RX VrefLevel [Byte0]: 32
3326 20:11:51.147519 [Byte1]: 32
3327 20:11:51.147605
3328 20:11:51.150887 Set Vref, RX VrefLevel [Byte0]: 33
3329 20:11:51.154556 [Byte1]: 33
3330 20:11:51.154643
3331 20:11:51.157597 Set Vref, RX VrefLevel [Byte0]: 34
3332 20:11:51.161071 [Byte1]: 34
3333 20:11:51.165025
3334 20:11:51.165111 Set Vref, RX VrefLevel [Byte0]: 35
3335 20:11:51.168151 [Byte1]: 35
3336 20:11:51.172765
3337 20:11:51.172852 Set Vref, RX VrefLevel [Byte0]: 36
3338 20:11:51.176246 [Byte1]: 36
3339 20:11:51.180787
3340 20:11:51.184031 Set Vref, RX VrefLevel [Byte0]: 37
3341 20:11:51.184123 [Byte1]: 37
3342 20:11:51.189031
3343 20:11:51.189116 Set Vref, RX VrefLevel [Byte0]: 38
3344 20:11:51.192080 [Byte1]: 38
3345 20:11:51.196740
3346 20:11:51.196824 Set Vref, RX VrefLevel [Byte0]: 39
3347 20:11:51.200118 [Byte1]: 39
3348 20:11:51.204799
3349 20:11:51.204884 Set Vref, RX VrefLevel [Byte0]: 40
3350 20:11:51.208088 [Byte1]: 40
3351 20:11:51.212590
3352 20:11:51.212673 Set Vref, RX VrefLevel [Byte0]: 41
3353 20:11:51.216037 [Byte1]: 41
3354 20:11:51.220604
3355 20:11:51.220690 Set Vref, RX VrefLevel [Byte0]: 42
3356 20:11:51.223833 [Byte1]: 42
3357 20:11:51.228532
3358 20:11:51.228619 Set Vref, RX VrefLevel [Byte0]: 43
3359 20:11:51.231986 [Byte1]: 43
3360 20:11:51.236194
3361 20:11:51.236282 Set Vref, RX VrefLevel [Byte0]: 44
3362 20:11:51.239510 [Byte1]: 44
3363 20:11:51.244422
3364 20:11:51.244508 Set Vref, RX VrefLevel [Byte0]: 45
3365 20:11:51.247526 [Byte1]: 45
3366 20:11:51.252317
3367 20:11:51.252401 Set Vref, RX VrefLevel [Byte0]: 46
3368 20:11:51.255350 [Byte1]: 46
3369 20:11:51.260229
3370 20:11:51.260313 Set Vref, RX VrefLevel [Byte0]: 47
3371 20:11:51.266790 [Byte1]: 47
3372 20:11:51.266881
3373 20:11:51.269808 Set Vref, RX VrefLevel [Byte0]: 48
3374 20:11:51.273220 [Byte1]: 48
3375 20:11:51.273303
3376 20:11:51.276536 Set Vref, RX VrefLevel [Byte0]: 49
3377 20:11:51.279934 [Byte1]: 49
3378 20:11:51.283957
3379 20:11:51.284050 Set Vref, RX VrefLevel [Byte0]: 50
3380 20:11:51.286987 [Byte1]: 50
3381 20:11:51.291724
3382 20:11:51.291813 Set Vref, RX VrefLevel [Byte0]: 51
3383 20:11:51.295146 [Byte1]: 51
3384 20:11:51.299775
3385 20:11:51.299862 Set Vref, RX VrefLevel [Byte0]: 52
3386 20:11:51.302919 [Byte1]: 52
3387 20:11:51.307706
3388 20:11:51.307797 Set Vref, RX VrefLevel [Byte0]: 53
3389 20:11:51.310784 [Byte1]: 53
3390 20:11:51.315626
3391 20:11:51.315712 Set Vref, RX VrefLevel [Byte0]: 54
3392 20:11:51.318769 [Byte1]: 54
3393 20:11:51.323467
3394 20:11:51.323551 Set Vref, RX VrefLevel [Byte0]: 55
3395 20:11:51.326701 [Byte1]: 55
3396 20:11:51.331271
3397 20:11:51.331361 Set Vref, RX VrefLevel [Byte0]: 56
3398 20:11:51.334571 [Byte1]: 56
3399 20:11:51.339400
3400 20:11:51.339490 Set Vref, RX VrefLevel [Byte0]: 57
3401 20:11:51.342672 [Byte1]: 57
3402 20:11:51.347127
3403 20:11:51.347211 Set Vref, RX VrefLevel [Byte0]: 58
3404 20:11:51.350551 [Byte1]: 58
3405 20:11:51.355313
3406 20:11:51.355398 Set Vref, RX VrefLevel [Byte0]: 59
3407 20:11:51.358364 [Byte1]: 59
3408 20:11:51.363038
3409 20:11:51.363122 Set Vref, RX VrefLevel [Byte0]: 60
3410 20:11:51.366428 [Byte1]: 60
3411 20:11:51.370841
3412 20:11:51.370925 Set Vref, RX VrefLevel [Byte0]: 61
3413 20:11:51.374315 [Byte1]: 61
3414 20:11:51.378829
3415 20:11:51.378913 Set Vref, RX VrefLevel [Byte0]: 62
3416 20:11:51.382143 [Byte1]: 62
3417 20:11:51.386855
3418 20:11:51.386956 Set Vref, RX VrefLevel [Byte0]: 63
3419 20:11:51.390105 [Byte1]: 63
3420 20:11:51.394815
3421 20:11:51.394902 Set Vref, RX VrefLevel [Byte0]: 64
3422 20:11:51.398200 [Byte1]: 64
3423 20:11:51.402653
3424 20:11:51.402740 Set Vref, RX VrefLevel [Byte0]: 65
3425 20:11:51.405717 [Byte1]: 65
3426 20:11:51.410553
3427 20:11:51.410641 Set Vref, RX VrefLevel [Byte0]: 66
3428 20:11:51.413708 [Byte1]: 66
3429 20:11:51.418588
3430 20:11:51.418675 Final RX Vref Byte 0 = 58 to rank0
3431 20:11:51.421827 Final RX Vref Byte 1 = 49 to rank0
3432 20:11:51.425190 Final RX Vref Byte 0 = 58 to rank1
3433 20:11:51.428480 Final RX Vref Byte 1 = 49 to rank1==
3434 20:11:51.431947 Dram Type= 6, Freq= 0, CH_1, rank 0
3435 20:11:51.438656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 20:11:51.438768 ==
3437 20:11:51.438834 DQS Delay:
3438 20:11:51.438894 DQS0 = 0, DQS1 = 0
3439 20:11:51.441797 DQM Delay:
3440 20:11:51.441880 DQM0 = 114, DQM1 = 105
3441 20:11:51.445152 DQ Delay:
3442 20:11:51.448378 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3443 20:11:51.451739 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3444 20:11:51.454992 DQ8 =92, DQ9 =100, DQ10 =106, DQ11 =100
3445 20:11:51.458384 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110
3446 20:11:51.458468
3447 20:11:51.458533
3448 20:11:51.464938 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3449 20:11:51.468388 CH1 RK0: MR19=303, MR18=ECF3
3450 20:11:51.475016 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3451 20:11:51.475115
3452 20:11:51.478403 ----->DramcWriteLeveling(PI) begin...
3453 20:11:51.478487 ==
3454 20:11:51.481786 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 20:11:51.485164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 20:11:51.488471 ==
3457 20:11:51.488558 Write leveling (Byte 0): 27 => 27
3458 20:11:51.491613 Write leveling (Byte 1): 27 => 27
3459 20:11:51.495250 DramcWriteLeveling(PI) end<-----
3460 20:11:51.495336
3461 20:11:51.495401 ==
3462 20:11:51.498293 Dram Type= 6, Freq= 0, CH_1, rank 1
3463 20:11:51.505192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 20:11:51.505286 ==
3465 20:11:51.505353 [Gating] SW mode calibration
3466 20:11:51.515028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3467 20:11:51.518231 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3468 20:11:51.524943 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 20:11:51.528205 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 20:11:51.531617 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 20:11:51.534859 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 20:11:51.541599 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 20:11:51.544966 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 20:11:51.548251 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
3475 20:11:51.554928 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3476 20:11:51.558501 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 20:11:51.561801 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 20:11:51.568491 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 20:11:51.571627 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 20:11:51.575106 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 20:11:51.581733 1 0 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3482 20:11:51.585034 1 0 24 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
3483 20:11:51.588300 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3484 20:11:51.595162 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 20:11:51.598372 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 20:11:51.601375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 20:11:51.608295 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 20:11:51.611648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 20:11:51.614573 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3490 20:11:51.621206 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3491 20:11:51.624575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3492 20:11:51.627873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 20:11:51.634756 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 20:11:51.638091 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 20:11:51.641123 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 20:11:51.647785 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 20:11:51.651054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 20:11:51.654227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 20:11:51.661253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 20:11:51.664395 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 20:11:51.667670 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 20:11:51.674372 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 20:11:51.677513 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 20:11:51.680728 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 20:11:51.687463 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 20:11:51.690810 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3507 20:11:51.694362 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 20:11:51.697535 Total UI for P1: 0, mck2ui 16
3509 20:11:51.700830 best dqsien dly found for B0: ( 1, 3, 24)
3510 20:11:51.704246 Total UI for P1: 0, mck2ui 16
3511 20:11:51.707239 best dqsien dly found for B1: ( 1, 3, 24)
3512 20:11:51.710699 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3513 20:11:51.714339 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3514 20:11:51.714428
3515 20:11:51.717522 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3516 20:11:51.723985 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3517 20:11:51.724081 [Gating] SW calibration Done
3518 20:11:51.724146 ==
3519 20:11:51.727390 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 20:11:51.733925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 20:11:51.734021 ==
3522 20:11:51.734087 RX Vref Scan: 0
3523 20:11:51.734146
3524 20:11:51.737246 RX Vref 0 -> 0, step: 1
3525 20:11:51.737329
3526 20:11:51.740535 RX Delay -40 -> 252, step: 8
3527 20:11:51.743766 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3528 20:11:51.747267 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3529 20:11:51.750445 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3530 20:11:51.757236 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3531 20:11:51.760311 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3532 20:11:51.764017 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3533 20:11:51.767016 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3534 20:11:51.770373 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3535 20:11:51.776978 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3536 20:11:51.780437 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3537 20:11:51.783376 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3538 20:11:51.786827 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3539 20:11:51.790433 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3540 20:11:51.796877 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3541 20:11:51.800351 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3542 20:11:51.803828 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3543 20:11:51.803914 ==
3544 20:11:51.807041 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 20:11:51.810015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 20:11:51.810098 ==
3547 20:11:51.813435 DQS Delay:
3548 20:11:51.813549 DQS0 = 0, DQS1 = 0
3549 20:11:51.816683 DQM Delay:
3550 20:11:51.816780 DQM0 = 110, DQM1 = 107
3551 20:11:51.816857 DQ Delay:
3552 20:11:51.819986 DQ0 =111, DQ1 =107, DQ2 =99, DQ3 =107
3553 20:11:51.826771 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3554 20:11:51.830227 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3555 20:11:51.833236 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3556 20:11:51.833324
3557 20:11:51.833389
3558 20:11:51.833449 ==
3559 20:11:51.836586 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 20:11:51.839989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 20:11:51.840076 ==
3562 20:11:51.840141
3563 20:11:51.840202
3564 20:11:51.843022 TX Vref Scan disable
3565 20:11:51.846562 == TX Byte 0 ==
3566 20:11:51.849846 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3567 20:11:51.853292 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3568 20:11:51.856623 == TX Byte 1 ==
3569 20:11:51.859626 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3570 20:11:51.863009 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3571 20:11:51.863094 ==
3572 20:11:51.866280 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 20:11:51.869748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 20:11:51.872763 ==
3575 20:11:51.882813 TX Vref=22, minBit 9, minWin=25, winSum=417
3576 20:11:51.886255 TX Vref=24, minBit 9, minWin=25, winSum=424
3577 20:11:51.889676 TX Vref=26, minBit 1, minWin=26, winSum=424
3578 20:11:51.892733 TX Vref=28, minBit 1, minWin=26, winSum=432
3579 20:11:51.895978 TX Vref=30, minBit 3, minWin=26, winSum=429
3580 20:11:51.902826 TX Vref=32, minBit 1, minWin=25, winSum=431
3581 20:11:51.906188 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
3582 20:11:51.906279
3583 20:11:51.909166 Final TX Range 1 Vref 28
3584 20:11:51.909251
3585 20:11:51.909316 ==
3586 20:11:51.912835 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 20:11:51.915906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 20:11:51.915993 ==
3589 20:11:51.919321
3590 20:11:51.919404
3591 20:11:51.919468 TX Vref Scan disable
3592 20:11:51.922659 == TX Byte 0 ==
3593 20:11:51.925981 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3594 20:11:51.929439 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3595 20:11:51.932757 == TX Byte 1 ==
3596 20:11:51.935791 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 20:11:51.942461 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 20:11:51.942562
3599 20:11:51.942628 [DATLAT]
3600 20:11:51.942690 Freq=1200, CH1 RK1
3601 20:11:51.942749
3602 20:11:51.945852 DATLAT Default: 0xd
3603 20:11:51.945934 0, 0xFFFF, sum = 0
3604 20:11:51.949027 1, 0xFFFF, sum = 0
3605 20:11:51.949110 2, 0xFFFF, sum = 0
3606 20:11:51.952511 3, 0xFFFF, sum = 0
3607 20:11:51.956034 4, 0xFFFF, sum = 0
3608 20:11:51.956122 5, 0xFFFF, sum = 0
3609 20:11:51.958982 6, 0xFFFF, sum = 0
3610 20:11:51.959066 7, 0xFFFF, sum = 0
3611 20:11:51.962479 8, 0xFFFF, sum = 0
3612 20:11:51.962564 9, 0xFFFF, sum = 0
3613 20:11:51.965591 10, 0xFFFF, sum = 0
3614 20:11:51.965675 11, 0xFFFF, sum = 0
3615 20:11:51.968786 12, 0x0, sum = 1
3616 20:11:51.968870 13, 0x0, sum = 2
3617 20:11:51.972202 14, 0x0, sum = 3
3618 20:11:51.972289 15, 0x0, sum = 4
3619 20:11:51.975547 best_step = 13
3620 20:11:51.975630
3621 20:11:51.975694 ==
3622 20:11:51.978773 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 20:11:51.982018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 20:11:51.982102 ==
3625 20:11:51.982167 RX Vref Scan: 0
3626 20:11:51.985333
3627 20:11:51.985419 RX Vref 0 -> 0, step: 1
3628 20:11:51.985513
3629 20:11:51.988650 RX Delay -21 -> 252, step: 4
3630 20:11:51.995566 iDelay=195, Bit 0, Center 116 (43 ~ 190) 148
3631 20:11:51.998579 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3632 20:11:52.001978 iDelay=195, Bit 2, Center 102 (31 ~ 174) 144
3633 20:11:52.005331 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3634 20:11:52.008446 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3635 20:11:52.015189 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3636 20:11:52.018752 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3637 20:11:52.021680 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3638 20:11:52.025307 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3639 20:11:52.028403 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3640 20:11:52.034936 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3641 20:11:52.038247 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3642 20:11:52.041579 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3643 20:11:52.044841 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3644 20:11:52.048194 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3645 20:11:52.054717 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3646 20:11:52.054813 ==
3647 20:11:52.058196 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 20:11:52.061360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 20:11:52.061448 ==
3650 20:11:52.061522 DQS Delay:
3651 20:11:52.064786 DQS0 = 0, DQS1 = 0
3652 20:11:52.064871 DQM Delay:
3653 20:11:52.067983 DQM0 = 112, DQM1 = 109
3654 20:11:52.068066 DQ Delay:
3655 20:11:52.071520 DQ0 =116, DQ1 =110, DQ2 =102, DQ3 =108
3656 20:11:52.074894 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3657 20:11:52.078233 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3658 20:11:52.081238 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3659 20:11:52.081323
3660 20:11:52.084648
3661 20:11:52.091268 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3662 20:11:52.094860 CH1 RK1: MR19=304, MR18=FC0C
3663 20:11:52.101304 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3664 20:11:52.104648 [RxdqsGatingPostProcess] freq 1200
3665 20:11:52.108108 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 20:11:52.111324 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 20:11:52.114710 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 20:11:52.118056 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 20:11:52.121305 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 20:11:52.124641 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 20:11:52.127975 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 20:11:52.131179 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 20:11:52.134395 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 20:11:52.138094 Pre-setting of DQS Precalculation
3675 20:11:52.141500 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 20:11:52.147770 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 20:11:52.157775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 20:11:52.157893
3679 20:11:52.157960
3680 20:11:52.158020 [Calibration Summary] 2400 Mbps
3681 20:11:52.161001 CH 0, Rank 0
3682 20:11:52.161083 SW Impedance : PASS
3683 20:11:52.164490 DUTY Scan : NO K
3684 20:11:52.167807 ZQ Calibration : PASS
3685 20:11:52.167894 Jitter Meter : NO K
3686 20:11:52.171212 CBT Training : PASS
3687 20:11:52.174414 Write leveling : PASS
3688 20:11:52.174498 RX DQS gating : PASS
3689 20:11:52.177687 RX DQ/DQS(RDDQC) : PASS
3690 20:11:52.180976 TX DQ/DQS : PASS
3691 20:11:52.181062 RX DATLAT : PASS
3692 20:11:52.184384 RX DQ/DQS(Engine): PASS
3693 20:11:52.187704 TX OE : NO K
3694 20:11:52.187799 All Pass.
3695 20:11:52.187865
3696 20:11:52.187926 CH 0, Rank 1
3697 20:11:52.190970 SW Impedance : PASS
3698 20:11:52.194546 DUTY Scan : NO K
3699 20:11:52.194631 ZQ Calibration : PASS
3700 20:11:52.197415 Jitter Meter : NO K
3701 20:11:52.200818 CBT Training : PASS
3702 20:11:52.200903 Write leveling : PASS
3703 20:11:52.204194 RX DQS gating : PASS
3704 20:11:52.207199 RX DQ/DQS(RDDQC) : PASS
3705 20:11:52.207283 TX DQ/DQS : PASS
3706 20:11:52.210491 RX DATLAT : PASS
3707 20:11:52.213958 RX DQ/DQS(Engine): PASS
3708 20:11:52.214045 TX OE : NO K
3709 20:11:52.214111 All Pass.
3710 20:11:52.217315
3711 20:11:52.217444 CH 1, Rank 0
3712 20:11:52.220546 SW Impedance : PASS
3713 20:11:52.220632 DUTY Scan : NO K
3714 20:11:52.223722 ZQ Calibration : PASS
3715 20:11:52.227028 Jitter Meter : NO K
3716 20:11:52.227114 CBT Training : PASS
3717 20:11:52.230427 Write leveling : PASS
3718 20:11:52.230511 RX DQS gating : PASS
3719 20:11:52.233943 RX DQ/DQS(RDDQC) : PASS
3720 20:11:52.237119 TX DQ/DQS : PASS
3721 20:11:52.237211 RX DATLAT : PASS
3722 20:11:52.240430 RX DQ/DQS(Engine): PASS
3723 20:11:52.243742 TX OE : NO K
3724 20:11:52.243828 All Pass.
3725 20:11:52.243893
3726 20:11:52.243954 CH 1, Rank 1
3727 20:11:52.247107 SW Impedance : PASS
3728 20:11:52.250408 DUTY Scan : NO K
3729 20:11:52.250492 ZQ Calibration : PASS
3730 20:11:52.253847 Jitter Meter : NO K
3731 20:11:52.256990 CBT Training : PASS
3732 20:11:52.257075 Write leveling : PASS
3733 20:11:52.260352 RX DQS gating : PASS
3734 20:11:52.263483 RX DQ/DQS(RDDQC) : PASS
3735 20:11:52.263568 TX DQ/DQS : PASS
3736 20:11:52.266843 RX DATLAT : PASS
3737 20:11:52.270350 RX DQ/DQS(Engine): PASS
3738 20:11:52.270437 TX OE : NO K
3739 20:11:52.273514 All Pass.
3740 20:11:52.273598
3741 20:11:52.273663 DramC Write-DBI off
3742 20:11:52.276927 PER_BANK_REFRESH: Hybrid Mode
3743 20:11:52.277015 TX_TRACKING: ON
3744 20:11:52.286746 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 20:11:52.290266 [FAST_K] Save calibration result to emmc
3746 20:11:52.293450 dramc_set_vcore_voltage set vcore to 650000
3747 20:11:52.296877 Read voltage for 600, 5
3748 20:11:52.296964 Vio18 = 0
3749 20:11:52.299814 Vcore = 650000
3750 20:11:52.299896 Vdram = 0
3751 20:11:52.299961 Vddq = 0
3752 20:11:52.303190 Vmddr = 0
3753 20:11:52.306509 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 20:11:52.313242 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 20:11:52.313343 MEM_TYPE=3, freq_sel=19
3756 20:11:52.316407 sv_algorithm_assistance_LP4_1600
3757 20:11:52.319870 ============ PULL DRAM RESETB DOWN ============
3758 20:11:52.326513 ========== PULL DRAM RESETB DOWN end =========
3759 20:11:52.329916 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 20:11:52.333294 ===================================
3761 20:11:52.336414 LPDDR4 DRAM CONFIGURATION
3762 20:11:52.339576 ===================================
3763 20:11:52.339744 EX_ROW_EN[0] = 0x0
3764 20:11:52.342825 EX_ROW_EN[1] = 0x0
3765 20:11:52.346070 LP4Y_EN = 0x0
3766 20:11:52.346155 WORK_FSP = 0x0
3767 20:11:52.349706 WL = 0x2
3768 20:11:52.349790 RL = 0x2
3769 20:11:52.352697 BL = 0x2
3770 20:11:52.352780 RPST = 0x0
3771 20:11:52.356238 RD_PRE = 0x0
3772 20:11:52.356322 WR_PRE = 0x1
3773 20:11:52.359275 WR_PST = 0x0
3774 20:11:52.359356 DBI_WR = 0x0
3775 20:11:52.363022 DBI_RD = 0x0
3776 20:11:52.363104 OTF = 0x1
3777 20:11:52.365898 ===================================
3778 20:11:52.369368 ===================================
3779 20:11:52.372783 ANA top config
3780 20:11:52.375985 ===================================
3781 20:11:52.376081 DLL_ASYNC_EN = 0
3782 20:11:52.379458 ALL_SLAVE_EN = 1
3783 20:11:52.382806 NEW_RANK_MODE = 1
3784 20:11:52.386151 DLL_IDLE_MODE = 1
3785 20:11:52.389363 LP45_APHY_COMB_EN = 1
3786 20:11:52.389452 TX_ODT_DIS = 1
3787 20:11:52.392434 NEW_8X_MODE = 1
3788 20:11:52.396015 ===================================
3789 20:11:52.399301 ===================================
3790 20:11:52.402476 data_rate = 1200
3791 20:11:52.405873 CKR = 1
3792 20:11:52.409024 DQ_P2S_RATIO = 8
3793 20:11:52.412509 ===================================
3794 20:11:52.415506 CA_P2S_RATIO = 8
3795 20:11:52.415593 DQ_CA_OPEN = 0
3796 20:11:52.418717 DQ_SEMI_OPEN = 0
3797 20:11:52.422006 CA_SEMI_OPEN = 0
3798 20:11:52.425402 CA_FULL_RATE = 0
3799 20:11:52.428646 DQ_CKDIV4_EN = 1
3800 20:11:52.432118 CA_CKDIV4_EN = 1
3801 20:11:52.432204 CA_PREDIV_EN = 0
3802 20:11:52.435228 PH8_DLY = 0
3803 20:11:52.438704 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 20:11:52.441979 DQ_AAMCK_DIV = 4
3805 20:11:52.445142 CA_AAMCK_DIV = 4
3806 20:11:52.448476 CA_ADMCK_DIV = 4
3807 20:11:52.448566 DQ_TRACK_CA_EN = 0
3808 20:11:52.451811 CA_PICK = 600
3809 20:11:52.455241 CA_MCKIO = 600
3810 20:11:52.458311 MCKIO_SEMI = 0
3811 20:11:52.461698 PLL_FREQ = 2288
3812 20:11:52.465021 DQ_UI_PI_RATIO = 32
3813 20:11:52.468425 CA_UI_PI_RATIO = 0
3814 20:11:52.471647 ===================================
3815 20:11:52.475206 ===================================
3816 20:11:52.475292 memory_type:LPDDR4
3817 20:11:52.478205 GP_NUM : 10
3818 20:11:52.481419 SRAM_EN : 1
3819 20:11:52.481591 MD32_EN : 0
3820 20:11:52.484831 ===================================
3821 20:11:52.487917 [ANA_INIT] >>>>>>>>>>>>>>
3822 20:11:52.491376 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 20:11:52.494535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 20:11:52.498003 ===================================
3825 20:11:52.501258 data_rate = 1200,PCW = 0X5800
3826 20:11:52.504619 ===================================
3827 20:11:52.508111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 20:11:52.511316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 20:11:52.518023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 20:11:52.520995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 20:11:52.527820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 20:11:52.530999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 20:11:52.531091 [ANA_INIT] flow start
3834 20:11:52.534364 [ANA_INIT] PLL >>>>>>>>
3835 20:11:52.537645 [ANA_INIT] PLL <<<<<<<<
3836 20:11:52.537735 [ANA_INIT] MIDPI >>>>>>>>
3837 20:11:52.541216 [ANA_INIT] MIDPI <<<<<<<<
3838 20:11:52.544445 [ANA_INIT] DLL >>>>>>>>
3839 20:11:52.544531 [ANA_INIT] flow end
3840 20:11:52.547725 ============ LP4 DIFF to SE enter ============
3841 20:11:52.554316 ============ LP4 DIFF to SE exit ============
3842 20:11:52.554413 [ANA_INIT] <<<<<<<<<<<<<
3843 20:11:52.557700 [Flow] Enable top DCM control >>>>>
3844 20:11:52.560872 [Flow] Enable top DCM control <<<<<
3845 20:11:52.564076 Enable DLL master slave shuffle
3846 20:11:52.570839 ==============================================================
3847 20:11:52.574248 Gating Mode config
3848 20:11:52.577353 ==============================================================
3849 20:11:52.580866 Config description:
3850 20:11:52.590788 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 20:11:52.597290 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 20:11:52.600486 SELPH_MODE 0: By rank 1: By Phase
3853 20:11:52.607273 ==============================================================
3854 20:11:52.610623 GAT_TRACK_EN = 1
3855 20:11:52.613938 RX_GATING_MODE = 2
3856 20:11:52.617184 RX_GATING_TRACK_MODE = 2
3857 20:11:52.617271 SELPH_MODE = 1
3858 20:11:52.620582 PICG_EARLY_EN = 1
3859 20:11:52.624019 VALID_LAT_VALUE = 1
3860 20:11:52.630367 ==============================================================
3861 20:11:52.633672 Enter into Gating configuration >>>>
3862 20:11:52.637001 Exit from Gating configuration <<<<
3863 20:11:52.640385 Enter into DVFS_PRE_config >>>>>
3864 20:11:52.650149 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 20:11:52.653590 Exit from DVFS_PRE_config <<<<<
3866 20:11:52.656876 Enter into PICG configuration >>>>
3867 20:11:52.660353 Exit from PICG configuration <<<<
3868 20:11:52.663612 [RX_INPUT] configuration >>>>>
3869 20:11:52.666859 [RX_INPUT] configuration <<<<<
3870 20:11:52.670282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 20:11:52.676924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 20:11:52.683398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 20:11:52.690185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 20:11:52.696742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 20:11:52.699730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 20:11:52.706757 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 20:11:52.709913 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 20:11:52.713192 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 20:11:52.716439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 20:11:52.723141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 20:11:52.726557 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 20:11:52.729595 ===================================
3883 20:11:52.732850 LPDDR4 DRAM CONFIGURATION
3884 20:11:52.736293 ===================================
3885 20:11:52.736380 EX_ROW_EN[0] = 0x0
3886 20:11:52.739603 EX_ROW_EN[1] = 0x0
3887 20:11:52.739688 LP4Y_EN = 0x0
3888 20:11:52.743032 WORK_FSP = 0x0
3889 20:11:52.743115 WL = 0x2
3890 20:11:52.746139 RL = 0x2
3891 20:11:52.746222 BL = 0x2
3892 20:11:52.749337 RPST = 0x0
3893 20:11:52.749420 RD_PRE = 0x0
3894 20:11:52.752767 WR_PRE = 0x1
3895 20:11:52.755977 WR_PST = 0x0
3896 20:11:52.756061 DBI_WR = 0x0
3897 20:11:52.759417 DBI_RD = 0x0
3898 20:11:52.759500 OTF = 0x1
3899 20:11:52.762593 ===================================
3900 20:11:52.766036 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 20:11:52.772493 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 20:11:52.776076 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 20:11:52.778952 ===================================
3904 20:11:52.782401 LPDDR4 DRAM CONFIGURATION
3905 20:11:52.785599 ===================================
3906 20:11:52.785685 EX_ROW_EN[0] = 0x10
3907 20:11:52.789138 EX_ROW_EN[1] = 0x0
3908 20:11:52.789227 LP4Y_EN = 0x0
3909 20:11:52.792209 WORK_FSP = 0x0
3910 20:11:52.792297 WL = 0x2
3911 20:11:52.795714 RL = 0x2
3912 20:11:52.795796 BL = 0x2
3913 20:11:52.799040 RPST = 0x0
3914 20:11:52.799122 RD_PRE = 0x0
3915 20:11:52.802234 WR_PRE = 0x1
3916 20:11:52.805403 WR_PST = 0x0
3917 20:11:52.805534 DBI_WR = 0x0
3918 20:11:52.808777 DBI_RD = 0x0
3919 20:11:52.808859 OTF = 0x1
3920 20:11:52.812126 ===================================
3921 20:11:52.818658 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 20:11:52.822403 nWR fixed to 30
3923 20:11:52.825762 [ModeRegInit_LP4] CH0 RK0
3924 20:11:52.825847 [ModeRegInit_LP4] CH0 RK1
3925 20:11:52.829010 [ModeRegInit_LP4] CH1 RK0
3926 20:11:52.832380 [ModeRegInit_LP4] CH1 RK1
3927 20:11:52.832467 match AC timing 17
3928 20:11:52.838808 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 20:11:52.842409 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 20:11:52.845741 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 20:11:52.852141 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 20:11:52.855417 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 20:11:52.855510 ==
3934 20:11:52.858737 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 20:11:52.862016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 20:11:52.862101 ==
3937 20:11:52.868916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 20:11:52.875289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3939 20:11:52.878627 [CA 0] Center 37 (7~67) winsize 61
3940 20:11:52.881986 [CA 1] Center 36 (6~67) winsize 62
3941 20:11:52.885496 [CA 2] Center 35 (5~65) winsize 61
3942 20:11:52.888833 [CA 3] Center 35 (5~65) winsize 61
3943 20:11:52.892247 [CA 4] Center 34 (4~64) winsize 61
3944 20:11:52.895336 [CA 5] Center 33 (3~64) winsize 62
3945 20:11:52.895422
3946 20:11:52.898552 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3947 20:11:52.898635
3948 20:11:52.901932 [CATrainingPosCal] consider 1 rank data
3949 20:11:52.905050 u2DelayCellTimex100 = 270/100 ps
3950 20:11:52.908398 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3951 20:11:52.911886 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3952 20:11:52.915283 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3953 20:11:52.918505 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3954 20:11:52.925240 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3955 20:11:52.928530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 20:11:52.928619
3957 20:11:52.931821 CA PerBit enable=1, Macro0, CA PI delay=33
3958 20:11:52.931904
3959 20:11:52.935100 [CBTSetCACLKResult] CA Dly = 33
3960 20:11:52.935181 CS Dly: 5 (0~36)
3961 20:11:52.935245 ==
3962 20:11:52.938292 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 20:11:52.944964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 20:11:52.945065 ==
3965 20:11:52.948206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 20:11:52.954839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3967 20:11:52.958178 [CA 0] Center 37 (7~67) winsize 61
3968 20:11:52.961599 [CA 1] Center 36 (6~67) winsize 62
3969 20:11:52.964673 [CA 2] Center 35 (5~65) winsize 61
3970 20:11:52.967948 [CA 3] Center 35 (5~65) winsize 61
3971 20:11:52.971460 [CA 4] Center 34 (3~65) winsize 63
3972 20:11:52.974676 [CA 5] Center 33 (3~64) winsize 62
3973 20:11:52.974759
3974 20:11:52.977908 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3975 20:11:52.977989
3976 20:11:52.981279 [CATrainingPosCal] consider 2 rank data
3977 20:11:52.984686 u2DelayCellTimex100 = 270/100 ps
3978 20:11:52.987993 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3979 20:11:52.991443 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3980 20:11:52.998081 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3981 20:11:53.001285 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3982 20:11:53.004392 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3983 20:11:53.007839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 20:11:53.007924
3985 20:11:53.011153 CA PerBit enable=1, Macro0, CA PI delay=33
3986 20:11:53.011234
3987 20:11:53.014561 [CBTSetCACLKResult] CA Dly = 33
3988 20:11:53.014667 CS Dly: 6 (0~38)
3989 20:11:53.017874
3990 20:11:53.020961 ----->DramcWriteLeveling(PI) begin...
3991 20:11:53.021048 ==
3992 20:11:53.024333 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 20:11:53.027712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 20:11:53.027796 ==
3995 20:11:53.030970 Write leveling (Byte 0): 33 => 33
3996 20:11:53.034433 Write leveling (Byte 1): 31 => 31
3997 20:11:53.037713 DramcWriteLeveling(PI) end<-----
3998 20:11:53.037816
3999 20:11:53.037881 ==
4000 20:11:53.041037 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 20:11:53.044237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 20:11:53.044320 ==
4003 20:11:53.047314 [Gating] SW mode calibration
4004 20:11:53.053948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 20:11:53.060617 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 20:11:53.064163 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 20:11:53.067566 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 20:11:53.073959 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 20:11:53.077397 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4010 20:11:53.080695 0 9 16 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (1 1)
4011 20:11:53.087387 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 20:11:53.090625 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 20:11:53.093728 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 20:11:53.100287 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 20:11:53.103642 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 20:11:53.107328 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 20:11:53.113806 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
4018 20:11:53.117311 0 10 16 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
4019 20:11:53.120734 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4020 20:11:53.127136 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 20:11:53.130401 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 20:11:53.133737 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 20:11:53.140450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 20:11:53.143785 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 20:11:53.146839 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4026 20:11:53.150418 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 20:11:53.156919 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 20:11:53.160348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 20:11:53.163558 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 20:11:53.170303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 20:11:53.173860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 20:11:53.177199 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 20:11:53.183620 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 20:11:53.187034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 20:11:53.190099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 20:11:53.196953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 20:11:53.200122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 20:11:53.203648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 20:11:53.210185 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 20:11:53.213286 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 20:11:53.216950 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4042 20:11:53.223392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 20:11:53.223494 Total UI for P1: 0, mck2ui 16
4044 20:11:53.230237 best dqsien dly found for B0: ( 0, 13, 12)
4045 20:11:53.230329 Total UI for P1: 0, mck2ui 16
4046 20:11:53.233564 best dqsien dly found for B1: ( 0, 13, 14)
4047 20:11:53.240039 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4048 20:11:53.243467 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4049 20:11:53.243561
4050 20:11:53.246714 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4051 20:11:53.250107 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4052 20:11:53.253471 [Gating] SW calibration Done
4053 20:11:53.253564 ==
4054 20:11:53.256882 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 20:11:53.260262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 20:11:53.260348 ==
4057 20:11:53.263365 RX Vref Scan: 0
4058 20:11:53.263448
4059 20:11:53.263513 RX Vref 0 -> 0, step: 1
4060 20:11:53.263573
4061 20:11:53.266668 RX Delay -230 -> 252, step: 16
4062 20:11:53.273385 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4063 20:11:53.276454 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4064 20:11:53.280070 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4065 20:11:53.283431 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4066 20:11:53.286610 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4067 20:11:53.293265 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4068 20:11:53.296344 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4069 20:11:53.299736 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4070 20:11:53.303025 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4071 20:11:53.309498 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4072 20:11:53.312846 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4073 20:11:53.316399 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4074 20:11:53.319586 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4075 20:11:53.326334 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4076 20:11:53.329289 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4077 20:11:53.332565 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4078 20:11:53.332652 ==
4079 20:11:53.335923 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 20:11:53.339324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 20:11:53.339416 ==
4082 20:11:53.342720 DQS Delay:
4083 20:11:53.342805 DQS0 = 0, DQS1 = 0
4084 20:11:53.346095 DQM Delay:
4085 20:11:53.346178 DQM0 = 38, DQM1 = 29
4086 20:11:53.346243 DQ Delay:
4087 20:11:53.349385 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4088 20:11:53.352859 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4089 20:11:53.355935 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4090 20:11:53.359143 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4091 20:11:53.359229
4092 20:11:53.362479
4093 20:11:53.362561 ==
4094 20:11:53.365882 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 20:11:53.369346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 20:11:53.369431 ==
4097 20:11:53.369503
4098 20:11:53.369564
4099 20:11:53.372285 TX Vref Scan disable
4100 20:11:53.372367 == TX Byte 0 ==
4101 20:11:53.379142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4102 20:11:53.382271 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4103 20:11:53.382356 == TX Byte 1 ==
4104 20:11:53.388963 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4105 20:11:53.392296 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4106 20:11:53.392390 ==
4107 20:11:53.395617 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 20:11:53.399117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 20:11:53.399202 ==
4110 20:11:53.399267
4111 20:11:53.399326
4112 20:11:53.402340 TX Vref Scan disable
4113 20:11:53.405755 == TX Byte 0 ==
4114 20:11:53.408829 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4115 20:11:53.412330 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4116 20:11:53.415883 == TX Byte 1 ==
4117 20:11:53.419377 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4118 20:11:53.422348 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4119 20:11:53.422434
4120 20:11:53.425350 [DATLAT]
4121 20:11:53.425432 Freq=600, CH0 RK0
4122 20:11:53.425507
4123 20:11:53.428756 DATLAT Default: 0x9
4124 20:11:53.428838 0, 0xFFFF, sum = 0
4125 20:11:53.431838 1, 0xFFFF, sum = 0
4126 20:11:53.431950 2, 0xFFFF, sum = 0
4127 20:11:53.435198 3, 0xFFFF, sum = 0
4128 20:11:53.435309 4, 0xFFFF, sum = 0
4129 20:11:53.438528 5, 0xFFFF, sum = 0
4130 20:11:53.438617 6, 0xFFFF, sum = 0
4131 20:11:53.442056 7, 0xFFFF, sum = 0
4132 20:11:53.442141 8, 0x0, sum = 1
4133 20:11:53.445420 9, 0x0, sum = 2
4134 20:11:53.445511 10, 0x0, sum = 3
4135 20:11:53.448633 11, 0x0, sum = 4
4136 20:11:53.448716 best_step = 9
4137 20:11:53.448780
4138 20:11:53.448840 ==
4139 20:11:53.451823 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 20:11:53.458420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 20:11:53.458517 ==
4142 20:11:53.458582 RX Vref Scan: 1
4143 20:11:53.458642
4144 20:11:53.461758 RX Vref 0 -> 0, step: 1
4145 20:11:53.461841
4146 20:11:53.465072 RX Delay -195 -> 252, step: 8
4147 20:11:53.465156
4148 20:11:53.468544 Set Vref, RX VrefLevel [Byte0]: 60
4149 20:11:53.471770 [Byte1]: 45
4150 20:11:53.471853
4151 20:11:53.475253 Final RX Vref Byte 0 = 60 to rank0
4152 20:11:53.478195 Final RX Vref Byte 1 = 45 to rank0
4153 20:11:53.481996 Final RX Vref Byte 0 = 60 to rank1
4154 20:11:53.485080 Final RX Vref Byte 1 = 45 to rank1==
4155 20:11:53.488190 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 20:11:53.491606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 20:11:53.491695 ==
4158 20:11:53.494791 DQS Delay:
4159 20:11:53.494873 DQS0 = 0, DQS1 = 0
4160 20:11:53.497972 DQM Delay:
4161 20:11:53.498070 DQM0 = 34, DQM1 = 28
4162 20:11:53.498135 DQ Delay:
4163 20:11:53.501408 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4164 20:11:53.504858 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4165 20:11:53.507998 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4166 20:11:53.511306 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4167 20:11:53.511391
4168 20:11:53.511456
4169 20:11:53.521374 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4170 20:11:53.524706 CH0 RK0: MR19=808, MR18=3C3B
4171 20:11:53.528076 CH0_RK0: MR19=0x808, MR18=0x3C3B, DQSOSC=398, MR23=63, INC=165, DEC=110
4172 20:11:53.531461
4173 20:11:53.534649 ----->DramcWriteLeveling(PI) begin...
4174 20:11:53.534737 ==
4175 20:11:53.538522 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 20:11:53.541685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 20:11:53.541775 ==
4178 20:11:53.544667 Write leveling (Byte 0): 33 => 33
4179 20:11:53.547889 Write leveling (Byte 1): 33 => 33
4180 20:11:53.551234 DramcWriteLeveling(PI) end<-----
4181 20:11:53.551320
4182 20:11:53.551385 ==
4183 20:11:53.554580 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 20:11:53.557766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 20:11:53.557853 ==
4186 20:11:53.561286 [Gating] SW mode calibration
4187 20:11:53.567935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4188 20:11:53.574368 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4189 20:11:53.577811 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 20:11:53.581186 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 20:11:53.587710 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 20:11:53.591061 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4193 20:11:53.594478 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4194 20:11:53.600721 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 20:11:53.604053 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 20:11:53.607588 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 20:11:53.614030 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 20:11:53.617264 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 20:11:53.620678 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 20:11:53.627403 0 10 12 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
4201 20:11:53.630623 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4202 20:11:53.634137 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 20:11:53.637440 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 20:11:53.644115 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 20:11:53.647523 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 20:11:53.650764 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 20:11:53.657427 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 20:11:53.660767 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 20:11:53.663870 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4210 20:11:53.670545 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 20:11:53.674110 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 20:11:53.676982 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 20:11:53.683705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 20:11:53.687287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 20:11:53.690412 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 20:11:53.696895 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 20:11:53.700589 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 20:11:53.703661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 20:11:53.710407 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 20:11:53.713801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 20:11:53.717093 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 20:11:53.723547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 20:11:53.726776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 20:11:53.730292 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4225 20:11:53.736781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4226 20:11:53.740044 Total UI for P1: 0, mck2ui 16
4227 20:11:53.743515 best dqsien dly found for B0: ( 0, 13, 12)
4228 20:11:53.746794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 20:11:53.750063 Total UI for P1: 0, mck2ui 16
4230 20:11:53.753465 best dqsien dly found for B1: ( 0, 13, 14)
4231 20:11:53.756805 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4232 20:11:53.760088 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4233 20:11:53.760174
4234 20:11:53.763340 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4235 20:11:53.766647 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4236 20:11:53.769842 [Gating] SW calibration Done
4237 20:11:53.769927 ==
4238 20:11:53.773061 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 20:11:53.779924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 20:11:53.780020 ==
4241 20:11:53.780087 RX Vref Scan: 0
4242 20:11:53.780147
4243 20:11:53.783186 RX Vref 0 -> 0, step: 1
4244 20:11:53.783269
4245 20:11:53.786384 RX Delay -230 -> 252, step: 16
4246 20:11:53.789963 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4247 20:11:53.793062 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4248 20:11:53.796347 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4249 20:11:53.802914 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4250 20:11:53.806945 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4251 20:11:53.809746 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4252 20:11:53.813002 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4253 20:11:53.816315 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4254 20:11:53.822810 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4255 20:11:53.826274 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4256 20:11:53.829573 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4257 20:11:53.832975 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4258 20:11:53.839512 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4259 20:11:53.842995 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4260 20:11:53.846347 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4261 20:11:53.849412 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4262 20:11:53.852682 ==
4263 20:11:53.852775 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 20:11:53.859437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 20:11:53.859532 ==
4266 20:11:53.859620 DQS Delay:
4267 20:11:53.862742 DQS0 = 0, DQS1 = 0
4268 20:11:53.862828 DQM Delay:
4269 20:11:53.866121 DQM0 = 35, DQM1 = 29
4270 20:11:53.866207 DQ Delay:
4271 20:11:53.869223 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4272 20:11:53.872798 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4273 20:11:53.875840 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4274 20:11:53.879380 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4275 20:11:53.879469
4276 20:11:53.879555
4277 20:11:53.879636 ==
4278 20:11:53.882598 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 20:11:53.886082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 20:11:53.886170 ==
4281 20:11:53.886257
4282 20:11:53.886338
4283 20:11:53.889172 TX Vref Scan disable
4284 20:11:53.892444 == TX Byte 0 ==
4285 20:11:53.895847 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4286 20:11:53.899307 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4287 20:11:53.902587 == TX Byte 1 ==
4288 20:11:53.905981 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4289 20:11:53.909318 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4290 20:11:53.909408 ==
4291 20:11:53.912701 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 20:11:53.915911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 20:11:53.918957 ==
4294 20:11:53.919047
4295 20:11:53.919134
4296 20:11:53.919215 TX Vref Scan disable
4297 20:11:53.922945 == TX Byte 0 ==
4298 20:11:53.926043 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4299 20:11:53.932798 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4300 20:11:53.932901 == TX Byte 1 ==
4301 20:11:53.936173 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4302 20:11:53.942756 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4303 20:11:53.942864
4304 20:11:53.942953 [DATLAT]
4305 20:11:53.943034 Freq=600, CH0 RK1
4306 20:11:53.943113
4307 20:11:53.946320 DATLAT Default: 0x9
4308 20:11:53.946405 0, 0xFFFF, sum = 0
4309 20:11:53.949256 1, 0xFFFF, sum = 0
4310 20:11:53.952839 2, 0xFFFF, sum = 0
4311 20:11:53.952935 3, 0xFFFF, sum = 0
4312 20:11:53.955792 4, 0xFFFF, sum = 0
4313 20:11:53.955875 5, 0xFFFF, sum = 0
4314 20:11:53.959125 6, 0xFFFF, sum = 0
4315 20:11:53.959207 7, 0xFFFF, sum = 0
4316 20:11:53.962510 8, 0x0, sum = 1
4317 20:11:53.962591 9, 0x0, sum = 2
4318 20:11:53.962655 10, 0x0, sum = 3
4319 20:11:53.965887 11, 0x0, sum = 4
4320 20:11:53.965969 best_step = 9
4321 20:11:53.966031
4322 20:11:53.966089 ==
4323 20:11:53.969274 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 20:11:53.975715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 20:11:53.975810 ==
4326 20:11:53.975874 RX Vref Scan: 0
4327 20:11:53.975933
4328 20:11:53.979302 RX Vref 0 -> 0, step: 1
4329 20:11:53.979384
4330 20:11:53.982194 RX Delay -195 -> 252, step: 8
4331 20:11:53.985974 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4332 20:11:53.992260 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4333 20:11:53.995754 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4334 20:11:53.999036 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4335 20:11:54.002454 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4336 20:11:54.009116 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4337 20:11:54.012127 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4338 20:11:54.015417 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4339 20:11:54.018763 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4340 20:11:54.022303 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4341 20:11:54.028738 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4342 20:11:54.032105 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4343 20:11:54.035412 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4344 20:11:54.038806 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4345 20:11:54.045298 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4346 20:11:54.048550 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4347 20:11:54.048653 ==
4348 20:11:54.052185 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 20:11:54.055269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 20:11:54.055355 ==
4351 20:11:54.058565 DQS Delay:
4352 20:11:54.058647 DQS0 = 0, DQS1 = 0
4353 20:11:54.062064 DQM Delay:
4354 20:11:54.062145 DQM0 = 33, DQM1 = 28
4355 20:11:54.062208 DQ Delay:
4356 20:11:54.065458 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4357 20:11:54.068704 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4358 20:11:54.071925 DQ8 =24, DQ9 =12, DQ10 =32, DQ11 =20
4359 20:11:54.075144 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4360 20:11:54.075229
4361 20:11:54.075293
4362 20:11:54.085087 [DQSOSCAuto] RK1, (LSB)MR18= 0x6938, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4363 20:11:54.088531 CH0 RK1: MR19=808, MR18=6938
4364 20:11:54.095332 CH0_RK1: MR19=0x808, MR18=0x6938, DQSOSC=390, MR23=63, INC=172, DEC=114
4365 20:11:54.095451 [RxdqsGatingPostProcess] freq 600
4366 20:11:54.101722 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4367 20:11:54.104914 Pre-setting of DQS Precalculation
4368 20:11:54.108256 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4369 20:11:54.108343 ==
4370 20:11:54.111662 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 20:11:54.118318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 20:11:54.118416 ==
4373 20:11:54.121618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 20:11:54.128171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4375 20:11:54.131827 [CA 0] Center 36 (6~66) winsize 61
4376 20:11:54.135166 [CA 1] Center 36 (6~66) winsize 61
4377 20:11:54.138369 [CA 2] Center 34 (4~65) winsize 62
4378 20:11:54.141638 [CA 3] Center 34 (4~65) winsize 62
4379 20:11:54.145117 [CA 4] Center 34 (4~65) winsize 62
4380 20:11:54.148274 [CA 5] Center 33 (3~64) winsize 62
4381 20:11:54.148359
4382 20:11:54.151632 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4383 20:11:54.151715
4384 20:11:54.154769 [CATrainingPosCal] consider 1 rank data
4385 20:11:54.158060 u2DelayCellTimex100 = 270/100 ps
4386 20:11:54.161439 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4387 20:11:54.168046 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4388 20:11:54.171361 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 20:11:54.174617 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 20:11:54.177995 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 20:11:54.181421 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 20:11:54.181564
4393 20:11:54.184727 CA PerBit enable=1, Macro0, CA PI delay=33
4394 20:11:54.184808
4395 20:11:54.187881 [CBTSetCACLKResult] CA Dly = 33
4396 20:11:54.191318 CS Dly: 5 (0~36)
4397 20:11:54.191409 ==
4398 20:11:54.194482 Dram Type= 6, Freq= 0, CH_1, rank 1
4399 20:11:54.197785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 20:11:54.197869 ==
4401 20:11:54.204460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 20:11:54.207728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4403 20:11:54.212177 [CA 0] Center 36 (6~66) winsize 61
4404 20:11:54.215437 [CA 1] Center 36 (5~67) winsize 63
4405 20:11:54.218431 [CA 2] Center 34 (4~65) winsize 62
4406 20:11:54.221811 [CA 3] Center 34 (3~65) winsize 63
4407 20:11:54.225262 [CA 4] Center 34 (4~65) winsize 62
4408 20:11:54.228508 [CA 5] Center 33 (3~64) winsize 62
4409 20:11:54.228592
4410 20:11:54.231628 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4411 20:11:54.231712
4412 20:11:54.235048 [CATrainingPosCal] consider 2 rank data
4413 20:11:54.238519 u2DelayCellTimex100 = 270/100 ps
4414 20:11:54.241643 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4415 20:11:54.248580 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4416 20:11:54.251950 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 20:11:54.255198 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 20:11:54.258338 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 20:11:54.261730 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 20:11:54.261817
4421 20:11:54.264913 CA PerBit enable=1, Macro0, CA PI delay=33
4422 20:11:54.264995
4423 20:11:54.268368 [CBTSetCACLKResult] CA Dly = 33
4424 20:11:54.268459 CS Dly: 5 (0~36)
4425 20:11:54.271531
4426 20:11:54.275277 ----->DramcWriteLeveling(PI) begin...
4427 20:11:54.275365 ==
4428 20:11:54.278351 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 20:11:54.281700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 20:11:54.281784 ==
4431 20:11:54.284747 Write leveling (Byte 0): 30 => 30
4432 20:11:54.288253 Write leveling (Byte 1): 30 => 30
4433 20:11:54.291618 DramcWriteLeveling(PI) end<-----
4434 20:11:54.291707
4435 20:11:54.291772 ==
4436 20:11:54.294857 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 20:11:54.298040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 20:11:54.298126 ==
4439 20:11:54.301278 [Gating] SW mode calibration
4440 20:11:54.307791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4441 20:11:54.314445 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4442 20:11:54.317936 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 20:11:54.321123 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 20:11:54.327936 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 20:11:54.331330 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
4446 20:11:54.334645 0 9 16 | B1->B0 | 2b2b 2727 | 0 0 | (1 0) (1 1)
4447 20:11:54.341114 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 20:11:54.344743 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 20:11:54.347967 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 20:11:54.354356 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 20:11:54.358045 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 20:11:54.361072 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 20:11:54.367696 0 10 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4454 20:11:54.371135 0 10 16 | B1->B0 | 4545 4242 | 0 0 | (0 0) (1 1)
4455 20:11:54.374350 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 20:11:54.377687 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 20:11:54.384407 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 20:11:54.387679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 20:11:54.391086 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 20:11:54.397799 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 20:11:54.401250 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4462 20:11:54.404522 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 20:11:54.411051 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 20:11:54.414218 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 20:11:54.417520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 20:11:54.424096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 20:11:54.427457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 20:11:54.430746 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 20:11:54.437359 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 20:11:54.440587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 20:11:54.443941 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 20:11:54.450461 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 20:11:54.453838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 20:11:54.457213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 20:11:54.463925 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 20:11:54.466982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 20:11:54.470308 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 20:11:54.477032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4479 20:11:54.480310 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 20:11:54.483476 Total UI for P1: 0, mck2ui 16
4481 20:11:54.486941 best dqsien dly found for B0: ( 0, 13, 16)
4482 20:11:54.490170 Total UI for P1: 0, mck2ui 16
4483 20:11:54.493370 best dqsien dly found for B1: ( 0, 13, 16)
4484 20:11:54.496678 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4485 20:11:54.500125 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4486 20:11:54.500213
4487 20:11:54.503509 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4488 20:11:54.506727 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4489 20:11:54.509869 [Gating] SW calibration Done
4490 20:11:54.509955 ==
4491 20:11:54.513320 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 20:11:54.519882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 20:11:54.519973 ==
4494 20:11:54.520038 RX Vref Scan: 0
4495 20:11:54.520099
4496 20:11:54.523212 RX Vref 0 -> 0, step: 1
4497 20:11:54.523292
4498 20:11:54.526710 RX Delay -230 -> 252, step: 16
4499 20:11:54.530198 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4500 20:11:54.533115 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4501 20:11:54.536735 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4502 20:11:54.543017 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4503 20:11:54.546442 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4504 20:11:54.549732 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4505 20:11:54.553090 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4506 20:11:54.559817 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4507 20:11:54.562995 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4508 20:11:54.566361 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4509 20:11:54.569759 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 20:11:54.572831 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4511 20:11:54.579580 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4512 20:11:54.582843 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4513 20:11:54.586226 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4514 20:11:54.589461 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4515 20:11:54.592664 ==
4516 20:11:54.596141 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 20:11:54.599500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 20:11:54.599582 ==
4519 20:11:54.599646 DQS Delay:
4520 20:11:54.602568 DQS0 = 0, DQS1 = 0
4521 20:11:54.602649 DQM Delay:
4522 20:11:54.606021 DQM0 = 39, DQM1 = 28
4523 20:11:54.606101 DQ Delay:
4524 20:11:54.609397 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4525 20:11:54.612687 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4526 20:11:54.616357 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4527 20:11:54.619262 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4528 20:11:54.619343
4529 20:11:54.619408
4530 20:11:54.619467 ==
4531 20:11:54.622558 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 20:11:54.626006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 20:11:54.626087 ==
4534 20:11:54.626151
4535 20:11:54.626210
4536 20:11:54.629617 TX Vref Scan disable
4537 20:11:54.632521 == TX Byte 0 ==
4538 20:11:54.635965 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 20:11:54.639216 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 20:11:54.642504 == TX Byte 1 ==
4541 20:11:54.645835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 20:11:54.649259 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 20:11:54.649339 ==
4544 20:11:54.652591 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 20:11:54.658947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 20:11:54.659029 ==
4547 20:11:54.659094
4548 20:11:54.659153
4549 20:11:54.659211 TX Vref Scan disable
4550 20:11:54.663496 == TX Byte 0 ==
4551 20:11:54.666843 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 20:11:54.673421 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 20:11:54.673538 == TX Byte 1 ==
4554 20:11:54.676483 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 20:11:54.683139 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 20:11:54.683220
4557 20:11:54.683284 [DATLAT]
4558 20:11:54.683343 Freq=600, CH1 RK0
4559 20:11:54.683402
4560 20:11:54.686611 DATLAT Default: 0x9
4561 20:11:54.686692 0, 0xFFFF, sum = 0
4562 20:11:54.689760 1, 0xFFFF, sum = 0
4563 20:11:54.689842 2, 0xFFFF, sum = 0
4564 20:11:54.693248 3, 0xFFFF, sum = 0
4565 20:11:54.696225 4, 0xFFFF, sum = 0
4566 20:11:54.696307 5, 0xFFFF, sum = 0
4567 20:11:54.699735 6, 0xFFFF, sum = 0
4568 20:11:54.699817 7, 0xFFFF, sum = 0
4569 20:11:54.703154 8, 0x0, sum = 1
4570 20:11:54.703236 9, 0x0, sum = 2
4571 20:11:54.703302 10, 0x0, sum = 3
4572 20:11:54.706804 11, 0x0, sum = 4
4573 20:11:54.706886 best_step = 9
4574 20:11:54.706949
4575 20:11:54.707008 ==
4576 20:11:54.709728 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 20:11:54.716223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 20:11:54.716309 ==
4579 20:11:54.716373 RX Vref Scan: 1
4580 20:11:54.716433
4581 20:11:54.719677 RX Vref 0 -> 0, step: 1
4582 20:11:54.719758
4583 20:11:54.722975 RX Delay -195 -> 252, step: 8
4584 20:11:54.723056
4585 20:11:54.726258 Set Vref, RX VrefLevel [Byte0]: 58
4586 20:11:54.729767 [Byte1]: 49
4587 20:11:54.729874
4588 20:11:54.732916 Final RX Vref Byte 0 = 58 to rank0
4589 20:11:54.736346 Final RX Vref Byte 1 = 49 to rank0
4590 20:11:54.739518 Final RX Vref Byte 0 = 58 to rank1
4591 20:11:54.742863 Final RX Vref Byte 1 = 49 to rank1==
4592 20:11:54.746320 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 20:11:54.749686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 20:11:54.749769 ==
4595 20:11:54.752677 DQS Delay:
4596 20:11:54.752758 DQS0 = 0, DQS1 = 0
4597 20:11:54.756011 DQM Delay:
4598 20:11:54.756092 DQM0 = 38, DQM1 = 29
4599 20:11:54.756158 DQ Delay:
4600 20:11:54.759428 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4601 20:11:54.762621 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4602 20:11:54.766100 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4603 20:11:54.769163 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4604 20:11:54.769245
4605 20:11:54.769310
4606 20:11:54.779398 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4607 20:11:54.782579 CH1 RK0: MR19=808, MR18=202D
4608 20:11:54.789318 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4609 20:11:54.789401
4610 20:11:54.792543 ----->DramcWriteLeveling(PI) begin...
4611 20:11:54.792629 ==
4612 20:11:54.795870 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 20:11:54.799001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 20:11:54.799083 ==
4615 20:11:54.802558 Write leveling (Byte 0): 31 => 31
4616 20:11:54.805950 Write leveling (Byte 1): 31 => 31
4617 20:11:54.808991 DramcWriteLeveling(PI) end<-----
4618 20:11:54.809072
4619 20:11:54.809137 ==
4620 20:11:54.812429 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 20:11:54.815875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 20:11:54.815958 ==
4623 20:11:54.819293 [Gating] SW mode calibration
4624 20:11:54.825748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 20:11:54.832250 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 20:11:54.835620 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 20:11:54.839052 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 20:11:54.845834 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4629 20:11:54.848889 0 9 12 | B1->B0 | 3131 2c2c | 1 0 | (0 0) (1 1)
4630 20:11:54.852138 0 9 16 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
4631 20:11:54.858957 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 20:11:54.862268 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 20:11:54.865425 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 20:11:54.872010 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 20:11:54.875408 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 20:11:54.878820 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4637 20:11:54.885394 0 10 12 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
4638 20:11:54.888780 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4639 20:11:54.891965 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 20:11:54.898599 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 20:11:54.901879 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 20:11:54.904970 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 20:11:54.911834 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 20:11:54.915125 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 20:11:54.918414 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4646 20:11:54.924824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 20:11:54.928150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 20:11:54.931527 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 20:11:54.938168 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 20:11:54.941629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 20:11:54.944906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 20:11:54.951291 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 20:11:54.954741 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 20:11:54.957956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 20:11:54.964412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 20:11:54.967998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 20:11:54.971232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 20:11:54.977727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 20:11:54.981814 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 20:11:54.984616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 20:11:54.987956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4662 20:11:54.994397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 20:11:54.997627 Total UI for P1: 0, mck2ui 16
4664 20:11:55.000815 best dqsien dly found for B0: ( 0, 13, 14)
4665 20:11:55.004145 Total UI for P1: 0, mck2ui 16
4666 20:11:55.007751 best dqsien dly found for B1: ( 0, 13, 12)
4667 20:11:55.011048 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4668 20:11:55.014343 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4669 20:11:55.014425
4670 20:11:55.017741 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4671 20:11:55.020767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4672 20:11:55.024175 [Gating] SW calibration Done
4673 20:11:55.024257 ==
4674 20:11:55.027499 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 20:11:55.030898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 20:11:55.030981 ==
4677 20:11:55.034195 RX Vref Scan: 0
4678 20:11:55.034277
4679 20:11:55.037224 RX Vref 0 -> 0, step: 1
4680 20:11:55.037305
4681 20:11:55.037369 RX Delay -230 -> 252, step: 16
4682 20:11:55.043951 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4683 20:11:55.047321 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4684 20:11:55.050700 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4685 20:11:55.053980 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4686 20:11:55.060807 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4687 20:11:55.063847 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4688 20:11:55.067337 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4689 20:11:55.070808 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4690 20:11:55.077175 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4691 20:11:55.080550 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4692 20:11:55.083753 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4693 20:11:55.087233 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4694 20:11:55.093810 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4695 20:11:55.097032 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4696 20:11:55.100618 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4697 20:11:55.103545 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4698 20:11:55.103630 ==
4699 20:11:55.107058 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 20:11:55.113495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 20:11:55.113595 ==
4702 20:11:55.113661 DQS Delay:
4703 20:11:55.113722 DQS0 = 0, DQS1 = 0
4704 20:11:55.116945 DQM Delay:
4705 20:11:55.117026 DQM0 = 36, DQM1 = 29
4706 20:11:55.120453 DQ Delay:
4707 20:11:55.123727 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4708 20:11:55.127184 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4709 20:11:55.127265 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4710 20:11:55.133479 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4711 20:11:55.133594
4712 20:11:55.133658
4713 20:11:55.133717 ==
4714 20:11:55.136828 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 20:11:55.140229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 20:11:55.140357 ==
4717 20:11:55.140469
4718 20:11:55.140565
4719 20:11:55.143528 TX Vref Scan disable
4720 20:11:55.143609 == TX Byte 0 ==
4721 20:11:55.150374 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4722 20:11:55.153610 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4723 20:11:55.153693 == TX Byte 1 ==
4724 20:11:55.160318 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 20:11:55.163712 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 20:11:55.163794 ==
4727 20:11:55.166863 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 20:11:55.170194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 20:11:55.170276 ==
4730 20:11:55.170341
4731 20:11:55.170401
4732 20:11:55.173385 TX Vref Scan disable
4733 20:11:55.176894 == TX Byte 0 ==
4734 20:11:55.179934 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4735 20:11:55.186579 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4736 20:11:55.186663 == TX Byte 1 ==
4737 20:11:55.189942 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 20:11:55.196505 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 20:11:55.196593
4740 20:11:55.196659 [DATLAT]
4741 20:11:55.196719 Freq=600, CH1 RK1
4742 20:11:55.196779
4743 20:11:55.199808 DATLAT Default: 0x9
4744 20:11:55.199890 0, 0xFFFF, sum = 0
4745 20:11:55.203270 1, 0xFFFF, sum = 0
4746 20:11:55.206177 2, 0xFFFF, sum = 0
4747 20:11:55.206259 3, 0xFFFF, sum = 0
4748 20:11:55.209782 4, 0xFFFF, sum = 0
4749 20:11:55.209865 5, 0xFFFF, sum = 0
4750 20:11:55.213150 6, 0xFFFF, sum = 0
4751 20:11:55.213232 7, 0xFFFF, sum = 0
4752 20:11:55.216091 8, 0x0, sum = 1
4753 20:11:55.216173 9, 0x0, sum = 2
4754 20:11:55.219428 10, 0x0, sum = 3
4755 20:11:55.219511 11, 0x0, sum = 4
4756 20:11:55.219577 best_step = 9
4757 20:11:55.219636
4758 20:11:55.222836 ==
4759 20:11:55.222917 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 20:11:55.229447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 20:11:55.229575 ==
4762 20:11:55.229641 RX Vref Scan: 0
4763 20:11:55.229701
4764 20:11:55.232881 RX Vref 0 -> 0, step: 1
4765 20:11:55.232962
4766 20:11:55.235943 RX Delay -195 -> 252, step: 8
4767 20:11:55.242919 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4768 20:11:55.246258 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4769 20:11:55.249189 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4770 20:11:55.252475 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4771 20:11:55.256029 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4772 20:11:55.262512 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4773 20:11:55.265787 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4774 20:11:55.269109 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4775 20:11:55.272499 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4776 20:11:55.279279 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4777 20:11:55.282575 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4778 20:11:55.285631 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4779 20:11:55.289255 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4780 20:11:55.295582 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4781 20:11:55.298991 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4782 20:11:55.302443 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4783 20:11:55.302528 ==
4784 20:11:55.305427 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 20:11:55.308764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 20:11:55.308847 ==
4787 20:11:55.312168 DQS Delay:
4788 20:11:55.312250 DQS0 = 0, DQS1 = 0
4789 20:11:55.315569 DQM Delay:
4790 20:11:55.315650 DQM0 = 36, DQM1 = 29
4791 20:11:55.315714 DQ Delay:
4792 20:11:55.318640 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4793 20:11:55.322107 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4794 20:11:55.325369 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4795 20:11:55.328757 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4796 20:11:55.328841
4797 20:11:55.332199
4798 20:11:55.338618 [DQSOSCAuto] RK1, (LSB)MR18= 0x3454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4799 20:11:55.341932 CH1 RK1: MR19=808, MR18=3454
4800 20:11:55.348380 CH1_RK1: MR19=0x808, MR18=0x3454, DQSOSC=393, MR23=63, INC=169, DEC=113
4801 20:11:55.351577 [RxdqsGatingPostProcess] freq 600
4802 20:11:55.355031 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 20:11:55.358174 Pre-setting of DQS Precalculation
4804 20:11:55.364996 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 20:11:55.371432 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 20:11:55.378163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 20:11:55.378251
4808 20:11:55.378317
4809 20:11:55.381626 [Calibration Summary] 1200 Mbps
4810 20:11:55.381711 CH 0, Rank 0
4811 20:11:55.384755 SW Impedance : PASS
4812 20:11:55.387849 DUTY Scan : NO K
4813 20:11:55.387936 ZQ Calibration : PASS
4814 20:11:55.391362 Jitter Meter : NO K
4815 20:11:55.394577 CBT Training : PASS
4816 20:11:55.394680 Write leveling : PASS
4817 20:11:55.398084 RX DQS gating : PASS
4818 20:11:55.398174 RX DQ/DQS(RDDQC) : PASS
4819 20:11:55.401185 TX DQ/DQS : PASS
4820 20:11:55.404405 RX DATLAT : PASS
4821 20:11:55.404493 RX DQ/DQS(Engine): PASS
4822 20:11:55.407840 TX OE : NO K
4823 20:11:55.407925 All Pass.
4824 20:11:55.407990
4825 20:11:55.411214 CH 0, Rank 1
4826 20:11:55.411301 SW Impedance : PASS
4827 20:11:55.414441 DUTY Scan : NO K
4828 20:11:55.417838 ZQ Calibration : PASS
4829 20:11:55.417928 Jitter Meter : NO K
4830 20:11:55.421180 CBT Training : PASS
4831 20:11:55.424554 Write leveling : PASS
4832 20:11:55.424642 RX DQS gating : PASS
4833 20:11:55.427744 RX DQ/DQS(RDDQC) : PASS
4834 20:11:55.431025 TX DQ/DQS : PASS
4835 20:11:55.431114 RX DATLAT : PASS
4836 20:11:55.434397 RX DQ/DQS(Engine): PASS
4837 20:11:55.437782 TX OE : NO K
4838 20:11:55.437873 All Pass.
4839 20:11:55.437938
4840 20:11:55.437999 CH 1, Rank 0
4841 20:11:55.440687 SW Impedance : PASS
4842 20:11:55.443924 DUTY Scan : NO K
4843 20:11:55.444013 ZQ Calibration : PASS
4844 20:11:55.447418 Jitter Meter : NO K
4845 20:11:55.450928 CBT Training : PASS
4846 20:11:55.451023 Write leveling : PASS
4847 20:11:55.454171 RX DQS gating : PASS
4848 20:11:55.457195 RX DQ/DQS(RDDQC) : PASS
4849 20:11:55.457292 TX DQ/DQS : PASS
4850 20:11:55.460549 RX DATLAT : PASS
4851 20:11:55.463877 RX DQ/DQS(Engine): PASS
4852 20:11:55.463964 TX OE : NO K
4853 20:11:55.464029 All Pass.
4854 20:11:55.467401
4855 20:11:55.467484 CH 1, Rank 1
4856 20:11:55.470543 SW Impedance : PASS
4857 20:11:55.470625 DUTY Scan : NO K
4858 20:11:55.474009 ZQ Calibration : PASS
4859 20:11:55.474090 Jitter Meter : NO K
4860 20:11:55.477148 CBT Training : PASS
4861 20:11:55.480592 Write leveling : PASS
4862 20:11:55.480673 RX DQS gating : PASS
4863 20:11:55.484088 RX DQ/DQS(RDDQC) : PASS
4864 20:11:55.487262 TX DQ/DQS : PASS
4865 20:11:55.487344 RX DATLAT : PASS
4866 20:11:55.490647 RX DQ/DQS(Engine): PASS
4867 20:11:55.493660 TX OE : NO K
4868 20:11:55.493745 All Pass.
4869 20:11:55.493809
4870 20:11:55.496942 DramC Write-DBI off
4871 20:11:55.497023 PER_BANK_REFRESH: Hybrid Mode
4872 20:11:55.500494 TX_TRACKING: ON
4873 20:11:55.510374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 20:11:55.513413 [FAST_K] Save calibration result to emmc
4875 20:11:55.516642 dramc_set_vcore_voltage set vcore to 662500
4876 20:11:55.516724 Read voltage for 933, 3
4877 20:11:55.520057 Vio18 = 0
4878 20:11:55.520138 Vcore = 662500
4879 20:11:55.520202 Vdram = 0
4880 20:11:55.523310 Vddq = 0
4881 20:11:55.523390 Vmddr = 0
4882 20:11:55.526636 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 20:11:55.533405 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 20:11:55.536379 MEM_TYPE=3, freq_sel=17
4885 20:11:55.540019 sv_algorithm_assistance_LP4_1600
4886 20:11:55.543399 ============ PULL DRAM RESETB DOWN ============
4887 20:11:55.546522 ========== PULL DRAM RESETB DOWN end =========
4888 20:11:55.552856 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 20:11:55.556319 ===================================
4890 20:11:55.556432 LPDDR4 DRAM CONFIGURATION
4891 20:11:55.559670 ===================================
4892 20:11:55.563012 EX_ROW_EN[0] = 0x0
4893 20:11:55.566320 EX_ROW_EN[1] = 0x0
4894 20:11:55.566427 LP4Y_EN = 0x0
4895 20:11:55.569646 WORK_FSP = 0x0
4896 20:11:55.569753 WL = 0x3
4897 20:11:55.572943 RL = 0x3
4898 20:11:55.573043 BL = 0x2
4899 20:11:55.576168 RPST = 0x0
4900 20:11:55.576274 RD_PRE = 0x0
4901 20:11:55.579731 WR_PRE = 0x1
4902 20:11:55.579839 WR_PST = 0x0
4903 20:11:55.582980 DBI_WR = 0x0
4904 20:11:55.583085 DBI_RD = 0x0
4905 20:11:55.586268 OTF = 0x1
4906 20:11:55.589662 ===================================
4907 20:11:55.592999 ===================================
4908 20:11:55.593119 ANA top config
4909 20:11:55.596258 ===================================
4910 20:11:55.599296 DLL_ASYNC_EN = 0
4911 20:11:55.602662 ALL_SLAVE_EN = 1
4912 20:11:55.606005 NEW_RANK_MODE = 1
4913 20:11:55.606090 DLL_IDLE_MODE = 1
4914 20:11:55.609081 LP45_APHY_COMB_EN = 1
4915 20:11:55.612449 TX_ODT_DIS = 1
4916 20:11:55.615716 NEW_8X_MODE = 1
4917 20:11:55.619160 ===================================
4918 20:11:55.622390 ===================================
4919 20:11:55.625660 data_rate = 1866
4920 20:11:55.625753 CKR = 1
4921 20:11:55.628893 DQ_P2S_RATIO = 8
4922 20:11:55.632340 ===================================
4923 20:11:55.635653 CA_P2S_RATIO = 8
4924 20:11:55.638916 DQ_CA_OPEN = 0
4925 20:11:55.642378 DQ_SEMI_OPEN = 0
4926 20:11:55.645589 CA_SEMI_OPEN = 0
4927 20:11:55.645675 CA_FULL_RATE = 0
4928 20:11:55.648877 DQ_CKDIV4_EN = 1
4929 20:11:55.652203 CA_CKDIV4_EN = 1
4930 20:11:55.655243 CA_PREDIV_EN = 0
4931 20:11:55.658733 PH8_DLY = 0
4932 20:11:55.661860 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 20:11:55.661942 DQ_AAMCK_DIV = 4
4934 20:11:55.665089 CA_AAMCK_DIV = 4
4935 20:11:55.668804 CA_ADMCK_DIV = 4
4936 20:11:55.672223 DQ_TRACK_CA_EN = 0
4937 20:11:55.675172 CA_PICK = 933
4938 20:11:55.678491 CA_MCKIO = 933
4939 20:11:55.678573 MCKIO_SEMI = 0
4940 20:11:55.681922 PLL_FREQ = 3732
4941 20:11:55.685365 DQ_UI_PI_RATIO = 32
4942 20:11:55.688535 CA_UI_PI_RATIO = 0
4943 20:11:55.691921 ===================================
4944 20:11:55.695270 ===================================
4945 20:11:55.698551 memory_type:LPDDR4
4946 20:11:55.698634 GP_NUM : 10
4947 20:11:55.701432 SRAM_EN : 1
4948 20:11:55.704970 MD32_EN : 0
4949 20:11:55.708321 ===================================
4950 20:11:55.708407 [ANA_INIT] >>>>>>>>>>>>>>
4951 20:11:55.711667 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 20:11:55.715068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 20:11:55.718471 ===================================
4954 20:11:55.721312 data_rate = 1866,PCW = 0X8f00
4955 20:11:55.724889 ===================================
4956 20:11:55.728123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 20:11:55.734932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 20:11:55.738056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 20:11:55.744641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 20:11:55.747964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 20:11:55.751280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 20:11:55.754774 [ANA_INIT] flow start
4963 20:11:55.754857 [ANA_INIT] PLL >>>>>>>>
4964 20:11:55.758104 [ANA_INIT] PLL <<<<<<<<
4965 20:11:55.761354 [ANA_INIT] MIDPI >>>>>>>>
4966 20:11:55.761435 [ANA_INIT] MIDPI <<<<<<<<
4967 20:11:55.764532 [ANA_INIT] DLL >>>>>>>>
4968 20:11:55.767767 [ANA_INIT] flow end
4969 20:11:55.771195 ============ LP4 DIFF to SE enter ============
4970 20:11:55.774428 ============ LP4 DIFF to SE exit ============
4971 20:11:55.777833 [ANA_INIT] <<<<<<<<<<<<<
4972 20:11:55.781280 [Flow] Enable top DCM control >>>>>
4973 20:11:55.784342 [Flow] Enable top DCM control <<<<<
4974 20:11:55.787653 Enable DLL master slave shuffle
4975 20:11:55.790962 ==============================================================
4976 20:11:55.794499 Gating Mode config
4977 20:11:55.801077 ==============================================================
4978 20:11:55.801166 Config description:
4979 20:11:55.811126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 20:11:55.817437 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 20:11:55.824131 SELPH_MODE 0: By rank 1: By Phase
4982 20:11:55.827199 ==============================================================
4983 20:11:55.830713 GAT_TRACK_EN = 1
4984 20:11:55.833989 RX_GATING_MODE = 2
4985 20:11:55.837296 RX_GATING_TRACK_MODE = 2
4986 20:11:55.840397 SELPH_MODE = 1
4987 20:11:55.843718 PICG_EARLY_EN = 1
4988 20:11:55.847121 VALID_LAT_VALUE = 1
4989 20:11:55.850463 ==============================================================
4990 20:11:55.853678 Enter into Gating configuration >>>>
4991 20:11:55.857281 Exit from Gating configuration <<<<
4992 20:11:55.860717 Enter into DVFS_PRE_config >>>>>
4993 20:11:55.873424 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 20:11:55.876754 Exit from DVFS_PRE_config <<<<<
4995 20:11:55.880161 Enter into PICG configuration >>>>
4996 20:11:55.883446 Exit from PICG configuration <<<<
4997 20:11:55.883531 [RX_INPUT] configuration >>>>>
4998 20:11:55.886534 [RX_INPUT] configuration <<<<<
4999 20:11:55.893293 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 20:11:55.896477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 20:11:55.903008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 20:11:55.909699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 20:11:55.916192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 20:11:55.923150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 20:11:55.926238 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 20:11:55.929635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 20:11:55.936095 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 20:11:55.939742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 20:11:55.942866 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 20:11:55.946177 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 20:11:55.949308 ===================================
5012 20:11:55.952631 LPDDR4 DRAM CONFIGURATION
5013 20:11:55.956322 ===================================
5014 20:11:55.959516 EX_ROW_EN[0] = 0x0
5015 20:11:55.959651 EX_ROW_EN[1] = 0x0
5016 20:11:55.962669 LP4Y_EN = 0x0
5017 20:11:55.962750 WORK_FSP = 0x0
5018 20:11:55.965787 WL = 0x3
5019 20:11:55.965869 RL = 0x3
5020 20:11:55.969216 BL = 0x2
5021 20:11:55.972911 RPST = 0x0
5022 20:11:55.972993 RD_PRE = 0x0
5023 20:11:55.975971 WR_PRE = 0x1
5024 20:11:55.976052 WR_PST = 0x0
5025 20:11:55.979114 DBI_WR = 0x0
5026 20:11:55.979194 DBI_RD = 0x0
5027 20:11:55.982527 OTF = 0x1
5028 20:11:55.985996 ===================================
5029 20:11:55.989270 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 20:11:55.992536 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 20:11:55.995950 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 20:11:55.999090 ===================================
5033 20:11:56.002386 LPDDR4 DRAM CONFIGURATION
5034 20:11:56.005655 ===================================
5035 20:11:56.009133 EX_ROW_EN[0] = 0x10
5036 20:11:56.009214 EX_ROW_EN[1] = 0x0
5037 20:11:56.012461 LP4Y_EN = 0x0
5038 20:11:56.012542 WORK_FSP = 0x0
5039 20:11:56.015821 WL = 0x3
5040 20:11:56.015903 RL = 0x3
5041 20:11:56.018791 BL = 0x2
5042 20:11:56.018872 RPST = 0x0
5043 20:11:56.022145 RD_PRE = 0x0
5044 20:11:56.025458 WR_PRE = 0x1
5045 20:11:56.025578 WR_PST = 0x0
5046 20:11:56.028642 DBI_WR = 0x0
5047 20:11:56.028722 DBI_RD = 0x0
5048 20:11:56.032159 OTF = 0x1
5049 20:11:56.035376 ===================================
5050 20:11:56.041678 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 20:11:56.045001 nWR fixed to 30
5052 20:11:56.045084 [ModeRegInit_LP4] CH0 RK0
5053 20:11:56.048614 [ModeRegInit_LP4] CH0 RK1
5054 20:11:56.051788 [ModeRegInit_LP4] CH1 RK0
5055 20:11:56.051870 [ModeRegInit_LP4] CH1 RK1
5056 20:11:56.055017 match AC timing 9
5057 20:11:56.058509 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 20:11:56.061754 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 20:11:56.068279 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 20:11:56.071421 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 20:11:56.078286 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 20:11:56.078368 ==
5063 20:11:56.081666 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 20:11:56.084853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 20:11:56.084935 ==
5066 20:11:56.091198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 20:11:56.097864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5068 20:11:56.101190 [CA 0] Center 38 (7~69) winsize 63
5069 20:11:56.104405 [CA 1] Center 38 (7~69) winsize 63
5070 20:11:56.107749 [CA 2] Center 35 (5~65) winsize 61
5071 20:11:56.111040 [CA 3] Center 34 (4~65) winsize 62
5072 20:11:56.114302 [CA 4] Center 34 (4~64) winsize 61
5073 20:11:56.117666 [CA 5] Center 34 (4~64) winsize 61
5074 20:11:56.117748
5075 20:11:56.121101 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5076 20:11:56.121186
5077 20:11:56.124424 [CATrainingPosCal] consider 1 rank data
5078 20:11:56.127446 u2DelayCellTimex100 = 270/100 ps
5079 20:11:56.130899 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5080 20:11:56.134434 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5081 20:11:56.137755 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5082 20:11:56.141053 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 20:11:56.144363 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 20:11:56.147519 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 20:11:56.147600
5086 20:11:56.151052 CA PerBit enable=1, Macro0, CA PI delay=34
5087 20:11:56.154118
5088 20:11:56.154199 [CBTSetCACLKResult] CA Dly = 34
5089 20:11:56.157568 CS Dly: 7 (0~38)
5090 20:11:56.157650 ==
5091 20:11:56.161127 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 20:11:56.164093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 20:11:56.164176 ==
5094 20:11:56.170719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 20:11:56.177380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5096 20:11:56.180699 [CA 0] Center 38 (8~69) winsize 62
5097 20:11:56.184045 [CA 1] Center 38 (7~69) winsize 63
5098 20:11:56.187435 [CA 2] Center 35 (5~66) winsize 62
5099 20:11:56.190454 [CA 3] Center 35 (5~66) winsize 62
5100 20:11:56.193789 [CA 4] Center 34 (4~65) winsize 62
5101 20:11:56.197180 [CA 5] Center 33 (3~64) winsize 62
5102 20:11:56.197287
5103 20:11:56.200420 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5104 20:11:56.200502
5105 20:11:56.203734 [CATrainingPosCal] consider 2 rank data
5106 20:11:56.207261 u2DelayCellTimex100 = 270/100 ps
5107 20:11:56.210385 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5108 20:11:56.213883 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5109 20:11:56.217287 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5110 20:11:56.220413 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5111 20:11:56.223852 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5112 20:11:56.227271 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5113 20:11:56.227354
5114 20:11:56.233803 CA PerBit enable=1, Macro0, CA PI delay=34
5115 20:11:56.233886
5116 20:11:56.237027 [CBTSetCACLKResult] CA Dly = 34
5117 20:11:56.237109 CS Dly: 7 (0~39)
5118 20:11:56.237175
5119 20:11:56.240312 ----->DramcWriteLeveling(PI) begin...
5120 20:11:56.240397 ==
5121 20:11:56.243560 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 20:11:56.247050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 20:11:56.250468 ==
5124 20:11:56.250551 Write leveling (Byte 0): 30 => 30
5125 20:11:56.253797 Write leveling (Byte 1): 28 => 28
5126 20:11:56.257023 DramcWriteLeveling(PI) end<-----
5127 20:11:56.257105
5128 20:11:56.257170 ==
5129 20:11:56.260268 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 20:11:56.266673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 20:11:56.266762 ==
5132 20:11:56.270073 [Gating] SW mode calibration
5133 20:11:56.276520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 20:11:56.279971 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 20:11:56.286370 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
5136 20:11:56.289942 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 20:11:56.293375 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 20:11:56.299773 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 20:11:56.302956 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 20:11:56.306447 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 20:11:56.312945 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 20:11:56.316300 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5143 20:11:56.319437 0 15 0 | B1->B0 | 3131 2a2a | 0 1 | (0 0) (1 0)
5144 20:11:56.325951 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 20:11:56.329413 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 20:11:56.332799 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 20:11:56.339202 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 20:11:56.342453 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 20:11:56.345754 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 20:11:56.352637 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5151 20:11:56.355902 1 0 0 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (1 1)
5152 20:11:56.358950 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5153 20:11:56.365879 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 20:11:56.369251 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 20:11:56.372384 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 20:11:56.379018 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 20:11:56.382390 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 20:11:56.385416 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5159 20:11:56.388947 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 20:11:56.395296 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5161 20:11:56.398541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 20:11:56.405366 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 20:11:56.408472 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 20:11:56.411876 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 20:11:56.415401 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 20:11:56.421694 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 20:11:56.425217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 20:11:56.428516 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 20:11:56.435021 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 20:11:56.438476 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 20:11:56.441465 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 20:11:56.448304 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 20:11:56.451662 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 20:11:56.455075 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 20:11:56.461449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5176 20:11:56.464749 Total UI for P1: 0, mck2ui 16
5177 20:11:56.468170 best dqsien dly found for B0: ( 1, 2, 30)
5178 20:11:56.471405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5179 20:11:56.474582 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 20:11:56.478081 Total UI for P1: 0, mck2ui 16
5181 20:11:56.481390 best dqsien dly found for B1: ( 1, 3, 2)
5182 20:11:56.484687 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5183 20:11:56.488051 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5184 20:11:56.491496
5185 20:11:56.494402 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5186 20:11:56.497830 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5187 20:11:56.501168 [Gating] SW calibration Done
5188 20:11:56.501251 ==
5189 20:11:56.504545 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 20:11:56.507901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 20:11:56.507985 ==
5192 20:11:56.508051 RX Vref Scan: 0
5193 20:11:56.508113
5194 20:11:56.511163 RX Vref 0 -> 0, step: 1
5195 20:11:56.511245
5196 20:11:56.514479 RX Delay -80 -> 252, step: 8
5197 20:11:56.517591 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5198 20:11:56.520903 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5199 20:11:56.527708 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5200 20:11:56.530844 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5201 20:11:56.534301 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5202 20:11:56.537801 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5203 20:11:56.541031 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5204 20:11:56.544152 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5205 20:11:56.550937 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5206 20:11:56.554456 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5207 20:11:56.557386 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5208 20:11:56.560905 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5209 20:11:56.564263 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5210 20:11:56.570767 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5211 20:11:56.573949 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5212 20:11:56.577359 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5213 20:11:56.577466 ==
5214 20:11:56.580740 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 20:11:56.584164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 20:11:56.584246 ==
5217 20:11:56.587202 DQS Delay:
5218 20:11:56.587283 DQS0 = 0, DQS1 = 0
5219 20:11:56.590440 DQM Delay:
5220 20:11:56.590520 DQM0 = 93, DQM1 = 82
5221 20:11:56.590583 DQ Delay:
5222 20:11:56.593898 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5223 20:11:56.597164 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5224 20:11:56.600450 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5225 20:11:56.603718 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5226 20:11:56.603798
5227 20:11:56.607073
5228 20:11:56.607154 ==
5229 20:11:56.610325 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 20:11:56.613809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 20:11:56.613891 ==
5232 20:11:56.613955
5233 20:11:56.614015
5234 20:11:56.617304 TX Vref Scan disable
5235 20:11:56.617409 == TX Byte 0 ==
5236 20:11:56.623697 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5237 20:11:56.626949 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5238 20:11:56.627032 == TX Byte 1 ==
5239 20:11:56.633370 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5240 20:11:56.636702 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5241 20:11:56.636785 ==
5242 20:11:56.640093 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 20:11:56.643375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 20:11:56.643460 ==
5245 20:11:56.643525
5246 20:11:56.643584
5247 20:11:56.646725 TX Vref Scan disable
5248 20:11:56.650190 == TX Byte 0 ==
5249 20:11:56.653308 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5250 20:11:56.656670 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5251 20:11:56.659636 == TX Byte 1 ==
5252 20:11:56.663475 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5253 20:11:56.666334 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5254 20:11:56.666416
5255 20:11:56.669642 [DATLAT]
5256 20:11:56.669723 Freq=933, CH0 RK0
5257 20:11:56.669788
5258 20:11:56.673375 DATLAT Default: 0xd
5259 20:11:56.673489 0, 0xFFFF, sum = 0
5260 20:11:56.676247 1, 0xFFFF, sum = 0
5261 20:11:56.676364 2, 0xFFFF, sum = 0
5262 20:11:56.679523 3, 0xFFFF, sum = 0
5263 20:11:56.679606 4, 0xFFFF, sum = 0
5264 20:11:56.682893 5, 0xFFFF, sum = 0
5265 20:11:56.682976 6, 0xFFFF, sum = 0
5266 20:11:56.686365 7, 0xFFFF, sum = 0
5267 20:11:56.689657 8, 0xFFFF, sum = 0
5268 20:11:56.689740 9, 0xFFFF, sum = 0
5269 20:11:56.689806 10, 0x0, sum = 1
5270 20:11:56.693227 11, 0x0, sum = 2
5271 20:11:56.693310 12, 0x0, sum = 3
5272 20:11:56.696296 13, 0x0, sum = 4
5273 20:11:56.696379 best_step = 11
5274 20:11:56.696443
5275 20:11:56.696503 ==
5276 20:11:56.699883 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 20:11:56.706225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 20:11:56.706308 ==
5279 20:11:56.706374 RX Vref Scan: 1
5280 20:11:56.706434
5281 20:11:56.709756 RX Vref 0 -> 0, step: 1
5282 20:11:56.709837
5283 20:11:56.713175 RX Delay -77 -> 252, step: 4
5284 20:11:56.713256
5285 20:11:56.716308 Set Vref, RX VrefLevel [Byte0]: 60
5286 20:11:56.719550 [Byte1]: 45
5287 20:11:56.719632
5288 20:11:56.722922 Final RX Vref Byte 0 = 60 to rank0
5289 20:11:56.726343 Final RX Vref Byte 1 = 45 to rank0
5290 20:11:56.729448 Final RX Vref Byte 0 = 60 to rank1
5291 20:11:56.732837 Final RX Vref Byte 1 = 45 to rank1==
5292 20:11:56.735871 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 20:11:56.739372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 20:11:56.739455 ==
5295 20:11:56.742384 DQS Delay:
5296 20:11:56.742496 DQS0 = 0, DQS1 = 0
5297 20:11:56.745969 DQM Delay:
5298 20:11:56.746051 DQM0 = 95, DQM1 = 83
5299 20:11:56.746117 DQ Delay:
5300 20:11:56.749420 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5301 20:11:56.752343 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5302 20:11:56.755744 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =78
5303 20:11:56.759116 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5304 20:11:56.762344
5305 20:11:56.762426
5306 20:11:56.769053 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5307 20:11:56.772540 CH0 RK0: MR19=505, MR18=100F
5308 20:11:56.779238 CH0_RK0: MR19=0x505, MR18=0x100F, DQSOSC=416, MR23=63, INC=62, DEC=41
5309 20:11:56.779328
5310 20:11:56.782431 ----->DramcWriteLeveling(PI) begin...
5311 20:11:56.782513 ==
5312 20:11:56.785882 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 20:11:56.789155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 20:11:56.789238 ==
5315 20:11:56.792291 Write leveling (Byte 0): 33 => 33
5316 20:11:56.795714 Write leveling (Byte 1): 32 => 32
5317 20:11:56.799048 DramcWriteLeveling(PI) end<-----
5318 20:11:56.799130
5319 20:11:56.799194 ==
5320 20:11:56.802272 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 20:11:56.805639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 20:11:56.805721 ==
5323 20:11:56.808767 [Gating] SW mode calibration
5324 20:11:56.815442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 20:11:56.822401 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 20:11:56.825412 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5327 20:11:56.828942 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 20:11:56.835362 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 20:11:56.838801 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 20:11:56.841969 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 20:11:56.848703 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 20:11:56.851950 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 20:11:56.855437 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
5334 20:11:56.862019 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5335 20:11:56.865318 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 20:11:56.868594 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 20:11:56.875173 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 20:11:56.878537 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 20:11:56.882028 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 20:11:56.888336 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5341 20:11:56.891578 0 15 28 | B1->B0 | 2524 3434 | 1 1 | (0 0) (0 0)
5342 20:11:56.895083 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5343 20:11:56.901439 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 20:11:56.905030 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 20:11:56.908230 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 20:11:56.915170 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 20:11:56.918550 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 20:11:56.921445 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 20:11:56.928221 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5350 20:11:56.931342 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 20:11:56.934752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 20:11:56.941423 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 20:11:56.944506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 20:11:56.948001 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 20:11:56.954763 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 20:11:56.957873 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 20:11:56.961158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 20:11:56.967832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 20:11:56.971270 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 20:11:56.974553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 20:11:56.981247 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 20:11:56.984493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 20:11:56.987550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 20:11:56.994304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 20:11:56.997676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5366 20:11:57.000659 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5367 20:11:57.003934 Total UI for P1: 0, mck2ui 16
5368 20:11:57.007379 best dqsien dly found for B0: ( 1, 2, 28)
5369 20:11:57.014100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 20:11:57.014205 Total UI for P1: 0, mck2ui 16
5371 20:11:57.017327 best dqsien dly found for B1: ( 1, 3, 0)
5372 20:11:57.024092 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5373 20:11:57.027408 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5374 20:11:57.027492
5375 20:11:57.030465 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5376 20:11:57.033727 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5377 20:11:57.037175 [Gating] SW calibration Done
5378 20:11:57.037257 ==
5379 20:11:57.040506 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 20:11:57.043920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 20:11:57.044005 ==
5382 20:11:57.047359 RX Vref Scan: 0
5383 20:11:57.047440
5384 20:11:57.047506 RX Vref 0 -> 0, step: 1
5385 20:11:57.047567
5386 20:11:57.050691 RX Delay -80 -> 252, step: 8
5387 20:11:57.053609 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5388 20:11:57.060423 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5389 20:11:57.063692 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5390 20:11:57.066899 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5391 20:11:57.070261 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5392 20:11:57.073313 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5393 20:11:57.076760 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5394 20:11:57.083478 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5395 20:11:57.086804 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5396 20:11:57.090268 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5397 20:11:57.093688 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5398 20:11:57.096724 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5399 20:11:57.103649 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5400 20:11:57.106645 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5401 20:11:57.110094 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5402 20:11:57.113578 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5403 20:11:57.113662 ==
5404 20:11:57.116684 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 20:11:57.119940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 20:11:57.123234 ==
5407 20:11:57.123317 DQS Delay:
5408 20:11:57.123448 DQS0 = 0, DQS1 = 0
5409 20:11:57.126643 DQM Delay:
5410 20:11:57.126727 DQM0 = 91, DQM1 = 81
5411 20:11:57.130127 DQ Delay:
5412 20:11:57.133216 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5413 20:11:57.136816 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5414 20:11:57.136900 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5415 20:11:57.143138 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5416 20:11:57.143227
5417 20:11:57.143293
5418 20:11:57.143354 ==
5419 20:11:57.146641 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 20:11:57.149869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 20:11:57.149952 ==
5422 20:11:57.150019
5423 20:11:57.150080
5424 20:11:57.153420 TX Vref Scan disable
5425 20:11:57.153510 == TX Byte 0 ==
5426 20:11:57.160110 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5427 20:11:57.162990 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5428 20:11:57.163074 == TX Byte 1 ==
5429 20:11:57.169710 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5430 20:11:57.173055 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5431 20:11:57.173139 ==
5432 20:11:57.176192 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 20:11:57.179557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 20:11:57.179642 ==
5435 20:11:57.179707
5436 20:11:57.179767
5437 20:11:57.182876 TX Vref Scan disable
5438 20:11:57.186224 == TX Byte 0 ==
5439 20:11:57.189420 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5440 20:11:57.192723 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5441 20:11:57.196138 == TX Byte 1 ==
5442 20:11:57.199641 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5443 20:11:57.202796 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5444 20:11:57.202881
5445 20:11:57.205968 [DATLAT]
5446 20:11:57.206051 Freq=933, CH0 RK1
5447 20:11:57.206117
5448 20:11:57.209251 DATLAT Default: 0xb
5449 20:11:57.209379 0, 0xFFFF, sum = 0
5450 20:11:57.212659 1, 0xFFFF, sum = 0
5451 20:11:57.212742 2, 0xFFFF, sum = 0
5452 20:11:57.216135 3, 0xFFFF, sum = 0
5453 20:11:57.216219 4, 0xFFFF, sum = 0
5454 20:11:57.219496 5, 0xFFFF, sum = 0
5455 20:11:57.219578 6, 0xFFFF, sum = 0
5456 20:11:57.222772 7, 0xFFFF, sum = 0
5457 20:11:57.225968 8, 0xFFFF, sum = 0
5458 20:11:57.226054 9, 0xFFFF, sum = 0
5459 20:11:57.229457 10, 0x0, sum = 1
5460 20:11:57.229560 11, 0x0, sum = 2
5461 20:11:57.229627 12, 0x0, sum = 3
5462 20:11:57.232697 13, 0x0, sum = 4
5463 20:11:57.232781 best_step = 11
5464 20:11:57.232845
5465 20:11:57.232906 ==
5466 20:11:57.236023 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 20:11:57.242447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 20:11:57.242540 ==
5469 20:11:57.242607 RX Vref Scan: 0
5470 20:11:57.242671
5471 20:11:57.245777 RX Vref 0 -> 0, step: 1
5472 20:11:57.245863
5473 20:11:57.249128 RX Delay -77 -> 252, step: 4
5474 20:11:57.252587 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5475 20:11:57.259189 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5476 20:11:57.262560 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5477 20:11:57.265462 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5478 20:11:57.268946 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5479 20:11:57.272387 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5480 20:11:57.275670 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5481 20:11:57.282494 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5482 20:11:57.285703 iDelay=199, Bit 8, Center 72 (-17 ~ 162) 180
5483 20:11:57.288848 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5484 20:11:57.292393 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5485 20:11:57.295579 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5486 20:11:57.302399 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5487 20:11:57.305391 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5488 20:11:57.308679 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5489 20:11:57.312073 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5490 20:11:57.312159 ==
5491 20:11:57.315486 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 20:11:57.321757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 20:11:57.321848 ==
5494 20:11:57.321915 DQS Delay:
5495 20:11:57.325060 DQS0 = 0, DQS1 = 0
5496 20:11:57.325143 DQM Delay:
5497 20:11:57.325208 DQM0 = 92, DQM1 = 83
5498 20:11:57.328344 DQ Delay:
5499 20:11:57.331705 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =86
5500 20:11:57.335086 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5501 20:11:57.338348 DQ8 =72, DQ9 =68, DQ10 =86, DQ11 =76
5502 20:11:57.341840 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =90
5503 20:11:57.341927
5504 20:11:57.341993
5505 20:11:57.348364 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5506 20:11:57.351571 CH0 RK1: MR19=505, MR18=2F11
5507 20:11:57.358386 CH0_RK1: MR19=0x505, MR18=0x2F11, DQSOSC=407, MR23=63, INC=65, DEC=43
5508 20:11:57.361377 [RxdqsGatingPostProcess] freq 933
5509 20:11:57.364982 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 20:11:57.368322 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 20:11:57.371355 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 20:11:57.375012 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 20:11:57.378425 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 20:11:57.381343 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 20:11:57.384566 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 20:11:57.388245 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 20:11:57.391624 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 20:11:57.395048 Pre-setting of DQS Precalculation
5519 20:11:57.398025 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 20:11:57.401333 ==
5521 20:11:57.401417 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 20:11:57.408205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 20:11:57.408290 ==
5524 20:11:57.411194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 20:11:57.418090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5526 20:11:57.421388 [CA 0] Center 37 (7~67) winsize 61
5527 20:11:57.424667 [CA 1] Center 37 (7~68) winsize 62
5528 20:11:57.428034 [CA 2] Center 34 (5~64) winsize 60
5529 20:11:57.431318 [CA 3] Center 34 (5~64) winsize 60
5530 20:11:57.434793 [CA 4] Center 35 (5~65) winsize 61
5531 20:11:57.437914 [CA 5] Center 34 (4~64) winsize 61
5532 20:11:57.437997
5533 20:11:57.441271 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5534 20:11:57.441354
5535 20:11:57.444648 [CATrainingPosCal] consider 1 rank data
5536 20:11:57.447934 u2DelayCellTimex100 = 270/100 ps
5537 20:11:57.451257 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5538 20:11:57.457840 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5539 20:11:57.461121 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5540 20:11:57.464464 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5541 20:11:57.467710 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5542 20:11:57.471322 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5543 20:11:57.471406
5544 20:11:57.474244 CA PerBit enable=1, Macro0, CA PI delay=34
5545 20:11:57.474326
5546 20:11:57.477682 [CBTSetCACLKResult] CA Dly = 34
5547 20:11:57.477765 CS Dly: 6 (0~37)
5548 20:11:57.480920 ==
5549 20:11:57.484252 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 20:11:57.487728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 20:11:57.487810 ==
5552 20:11:57.491032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 20:11:57.497425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5554 20:11:57.501544 [CA 0] Center 37 (8~67) winsize 60
5555 20:11:57.504641 [CA 1] Center 37 (7~68) winsize 62
5556 20:11:57.508003 [CA 2] Center 35 (5~65) winsize 61
5557 20:11:57.511433 [CA 3] Center 34 (4~64) winsize 61
5558 20:11:57.514748 [CA 4] Center 34 (4~65) winsize 62
5559 20:11:57.518152 [CA 5] Center 34 (4~64) winsize 61
5560 20:11:57.518235
5561 20:11:57.521222 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5562 20:11:57.521304
5563 20:11:57.524453 [CATrainingPosCal] consider 2 rank data
5564 20:11:57.527842 u2DelayCellTimex100 = 270/100 ps
5565 20:11:57.531194 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5566 20:11:57.537642 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5567 20:11:57.541033 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5568 20:11:57.544139 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5569 20:11:57.547729 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5570 20:11:57.550950 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5571 20:11:57.551033
5572 20:11:57.554386 CA PerBit enable=1, Macro0, CA PI delay=34
5573 20:11:57.554469
5574 20:11:57.557794 [CBTSetCACLKResult] CA Dly = 34
5575 20:11:57.560738 CS Dly: 7 (0~39)
5576 20:11:57.560819
5577 20:11:57.564175 ----->DramcWriteLeveling(PI) begin...
5578 20:11:57.564258 ==
5579 20:11:57.567714 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 20:11:57.570759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 20:11:57.570843 ==
5582 20:11:57.574004 Write leveling (Byte 0): 28 => 28
5583 20:11:57.577470 Write leveling (Byte 1): 29 => 29
5584 20:11:57.580728 DramcWriteLeveling(PI) end<-----
5585 20:11:57.580810
5586 20:11:57.580874 ==
5587 20:11:57.583837 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 20:11:57.587287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 20:11:57.587370 ==
5590 20:11:57.590383 [Gating] SW mode calibration
5591 20:11:57.597160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 20:11:57.603670 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 20:11:57.606889 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5594 20:11:57.610363 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 20:11:57.616958 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 20:11:57.620135 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 20:11:57.623509 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 20:11:57.630258 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 20:11:57.633809 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 20:11:57.636743 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5601 20:11:57.643683 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5602 20:11:57.646647 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 20:11:57.649858 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 20:11:57.656557 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 20:11:57.659950 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 20:11:57.663043 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 20:11:57.669920 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 20:11:57.673141 0 15 28 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
5609 20:11:57.676497 1 0 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
5610 20:11:57.682793 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 20:11:57.686172 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 20:11:57.689694 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 20:11:57.696040 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 20:11:57.699388 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 20:11:57.702544 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 20:11:57.709413 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5617 20:11:57.712343 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 20:11:57.715968 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 20:11:57.722479 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 20:11:57.725715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 20:11:57.729248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 20:11:57.735675 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 20:11:57.738997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 20:11:57.742398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 20:11:57.748939 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 20:11:57.752120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 20:11:57.755461 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 20:11:57.762175 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 20:11:57.765409 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 20:11:57.768726 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 20:11:57.775368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 20:11:57.778649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5633 20:11:57.781952 Total UI for P1: 0, mck2ui 16
5634 20:11:57.785381 best dqsien dly found for B1: ( 1, 2, 26)
5635 20:11:57.788785 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 20:11:57.791982 Total UI for P1: 0, mck2ui 16
5637 20:11:57.795353 best dqsien dly found for B0: ( 1, 2, 28)
5638 20:11:57.798730 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5639 20:11:57.802064 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5640 20:11:57.802145
5641 20:11:57.808592 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5642 20:11:57.812279 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5643 20:11:57.812360 [Gating] SW calibration Done
5644 20:11:57.815149 ==
5645 20:11:57.818393 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 20:11:57.821838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 20:11:57.821919 ==
5648 20:11:57.821983 RX Vref Scan: 0
5649 20:11:57.822043
5650 20:11:57.824890 RX Vref 0 -> 0, step: 1
5651 20:11:57.824969
5652 20:11:57.828273 RX Delay -80 -> 252, step: 8
5653 20:11:57.831636 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5654 20:11:57.835036 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5655 20:11:57.838412 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5656 20:11:57.845127 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5657 20:11:57.848065 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5658 20:11:57.851284 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5659 20:11:57.854739 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5660 20:11:57.858020 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 20:11:57.864793 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5662 20:11:57.868096 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5663 20:11:57.871389 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5664 20:11:57.874515 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5665 20:11:57.877965 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5666 20:11:57.884471 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5667 20:11:57.888060 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5668 20:11:57.891092 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5669 20:11:57.891174 ==
5670 20:11:57.894598 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 20:11:57.897471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 20:11:57.897594 ==
5673 20:11:57.901028 DQS Delay:
5674 20:11:57.901109 DQS0 = 0, DQS1 = 0
5675 20:11:57.904209 DQM Delay:
5676 20:11:57.904290 DQM0 = 94, DQM1 = 85
5677 20:11:57.904356 DQ Delay:
5678 20:11:57.907639 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5679 20:11:57.910987 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5680 20:11:57.914097 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5681 20:11:57.917508 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5682 20:11:57.917603
5683 20:11:57.920731
5684 20:11:57.920811 ==
5685 20:11:57.924132 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 20:11:57.927385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 20:11:57.927468 ==
5688 20:11:57.927532
5689 20:11:57.927592
5690 20:11:57.930546 TX Vref Scan disable
5691 20:11:57.930628 == TX Byte 0 ==
5692 20:11:57.937164 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5693 20:11:57.940421 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5694 20:11:57.940503 == TX Byte 1 ==
5695 20:11:57.947077 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 20:11:57.950726 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 20:11:57.950813 ==
5698 20:11:57.953756 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 20:11:57.956939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 20:11:57.957022 ==
5701 20:11:57.957087
5702 20:11:57.957146
5703 20:11:57.960514 TX Vref Scan disable
5704 20:11:57.963841 == TX Byte 0 ==
5705 20:11:57.966924 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 20:11:57.970432 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 20:11:57.973694 == TX Byte 1 ==
5708 20:11:57.977012 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5709 20:11:57.980044 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5710 20:11:57.980126
5711 20:11:57.983416 [DATLAT]
5712 20:11:57.983497 Freq=933, CH1 RK0
5713 20:11:57.983563
5714 20:11:57.986763 DATLAT Default: 0xd
5715 20:11:57.986845 0, 0xFFFF, sum = 0
5716 20:11:57.990181 1, 0xFFFF, sum = 0
5717 20:11:57.990264 2, 0xFFFF, sum = 0
5718 20:11:57.993502 3, 0xFFFF, sum = 0
5719 20:11:57.993584 4, 0xFFFF, sum = 0
5720 20:11:57.996518 5, 0xFFFF, sum = 0
5721 20:11:57.996603 6, 0xFFFF, sum = 0
5722 20:11:57.999803 7, 0xFFFF, sum = 0
5723 20:11:57.999911 8, 0xFFFF, sum = 0
5724 20:11:58.003332 9, 0xFFFF, sum = 0
5725 20:11:58.003417 10, 0x0, sum = 1
5726 20:11:58.006710 11, 0x0, sum = 2
5727 20:11:58.006795 12, 0x0, sum = 3
5728 20:11:58.009917 13, 0x0, sum = 4
5729 20:11:58.010002 best_step = 11
5730 20:11:58.010087
5731 20:11:58.010166 ==
5732 20:11:58.013162 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 20:11:58.019983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 20:11:58.020068 ==
5735 20:11:58.020154 RX Vref Scan: 1
5736 20:11:58.020235
5737 20:11:58.023171 RX Vref 0 -> 0, step: 1
5738 20:11:58.023255
5739 20:11:58.026474 RX Delay -69 -> 252, step: 4
5740 20:11:58.026558
5741 20:11:58.029700 Set Vref, RX VrefLevel [Byte0]: 58
5742 20:11:58.033014 [Byte1]: 49
5743 20:11:58.033098
5744 20:11:58.036358 Final RX Vref Byte 0 = 58 to rank0
5745 20:11:58.039682 Final RX Vref Byte 1 = 49 to rank0
5746 20:11:58.043222 Final RX Vref Byte 0 = 58 to rank1
5747 20:11:58.046284 Final RX Vref Byte 1 = 49 to rank1==
5748 20:11:58.049728 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 20:11:58.052962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 20:11:58.053047 ==
5751 20:11:58.056397 DQS Delay:
5752 20:11:58.056481 DQS0 = 0, DQS1 = 0
5753 20:11:58.059573 DQM Delay:
5754 20:11:58.059657 DQM0 = 96, DQM1 = 88
5755 20:11:58.059743 DQ Delay:
5756 20:11:58.062761 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =92
5757 20:11:58.065910 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5758 20:11:58.069436 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5759 20:11:58.072613 DQ12 =98, DQ13 =94, DQ14 =94, DQ15 =96
5760 20:11:58.072697
5761 20:11:58.076024
5762 20:11:58.082380 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5763 20:11:58.085696 CH1 RK0: MR19=505, MR18=10A
5764 20:11:58.092490 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5765 20:11:58.092575
5766 20:11:58.095599 ----->DramcWriteLeveling(PI) begin...
5767 20:11:58.095688 ==
5768 20:11:58.098901 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 20:11:58.102527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 20:11:58.102612 ==
5771 20:11:58.105842 Write leveling (Byte 0): 24 => 24
5772 20:11:58.108972 Write leveling (Byte 1): 29 => 29
5773 20:11:58.112287 DramcWriteLeveling(PI) end<-----
5774 20:11:58.112371
5775 20:11:58.112472 ==
5776 20:11:58.115561 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 20:11:58.118713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 20:11:58.118799 ==
5779 20:11:58.122324 [Gating] SW mode calibration
5780 20:11:58.128812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 20:11:58.135210 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 20:11:58.138850 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 20:11:58.142283 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 20:11:58.148594 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 20:11:58.152072 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 20:11:58.154941 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 20:11:58.161793 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 20:11:58.165127 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5789 20:11:58.168292 0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
5790 20:11:58.174894 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5791 20:11:58.178282 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 20:11:58.181488 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 20:11:58.188143 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 20:11:58.191367 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 20:11:58.194694 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 20:11:58.201400 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5797 20:11:58.204826 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5798 20:11:58.207830 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5799 20:11:58.214768 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 20:11:58.217941 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 20:11:58.221298 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 20:11:58.227890 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 20:11:58.231242 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 20:11:58.234590 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5805 20:11:58.241170 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5806 20:11:58.244486 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 20:11:58.247770 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 20:11:58.254247 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 20:11:58.257607 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 20:11:58.260958 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 20:11:58.267765 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 20:11:58.271079 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 20:11:58.274404 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 20:11:58.281023 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 20:11:58.284336 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 20:11:58.287729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 20:11:58.294216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 20:11:58.297261 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 20:11:58.300649 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 20:11:58.307324 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5821 20:11:58.310845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5822 20:11:58.313876 Total UI for P1: 0, mck2ui 16
5823 20:11:58.317290 best dqsien dly found for B0: ( 1, 2, 24)
5824 20:11:58.320735 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 20:11:58.323965 Total UI for P1: 0, mck2ui 16
5826 20:11:58.327313 best dqsien dly found for B1: ( 1, 2, 26)
5827 20:11:58.330755 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5828 20:11:58.334252 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5829 20:11:58.334332
5830 20:11:58.337430 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5831 20:11:58.343942 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5832 20:11:58.344023 [Gating] SW calibration Done
5833 20:11:58.344087 ==
5834 20:11:58.347367 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 20:11:58.354044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 20:11:58.354130 ==
5837 20:11:58.354216 RX Vref Scan: 0
5838 20:11:58.354297
5839 20:11:58.357187 RX Vref 0 -> 0, step: 1
5840 20:11:58.357272
5841 20:11:58.360565 RX Delay -80 -> 252, step: 8
5842 20:11:58.363738 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5843 20:11:58.367019 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5844 20:11:58.370538 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5845 20:11:58.373770 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5846 20:11:58.380445 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5847 20:11:58.383581 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5848 20:11:58.387010 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5849 20:11:58.390384 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5850 20:11:58.393661 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5851 20:11:58.400325 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5852 20:11:58.403466 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5853 20:11:58.406920 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5854 20:11:58.410132 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5855 20:11:58.413327 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5856 20:11:58.420156 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5857 20:11:58.423638 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5858 20:11:58.423719 ==
5859 20:11:58.426920 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 20:11:58.430155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 20:11:58.430237 ==
5862 20:11:58.430301 DQS Delay:
5863 20:11:58.433435 DQS0 = 0, DQS1 = 0
5864 20:11:58.433522 DQM Delay:
5865 20:11:58.436692 DQM0 = 94, DQM1 = 89
5866 20:11:58.436772 DQ Delay:
5867 20:11:58.440010 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5868 20:11:58.443318 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5869 20:11:58.446662 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5870 20:11:58.449869 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5871 20:11:58.449950
5872 20:11:58.450014
5873 20:11:58.450073 ==
5874 20:11:58.453143 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 20:11:58.456430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 20:11:58.459637 ==
5877 20:11:58.459717
5878 20:11:58.459780
5879 20:11:58.459839 TX Vref Scan disable
5880 20:11:58.462920 == TX Byte 0 ==
5881 20:11:58.466435 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5882 20:11:58.469777 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5883 20:11:58.473126 == TX Byte 1 ==
5884 20:11:58.476158 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 20:11:58.479552 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 20:11:58.482793 ==
5887 20:11:58.486159 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 20:11:58.489542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 20:11:58.489622 ==
5890 20:11:58.489686
5891 20:11:58.489745
5892 20:11:58.492777 TX Vref Scan disable
5893 20:11:58.492857 == TX Byte 0 ==
5894 20:11:58.499593 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5895 20:11:58.502841 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5896 20:11:58.502922 == TX Byte 1 ==
5897 20:11:58.509433 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5898 20:11:58.512707 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5899 20:11:58.512789
5900 20:11:58.512852 [DATLAT]
5901 20:11:58.516253 Freq=933, CH1 RK1
5902 20:11:58.516334
5903 20:11:58.516398 DATLAT Default: 0xb
5904 20:11:58.519221 0, 0xFFFF, sum = 0
5905 20:11:58.519303 1, 0xFFFF, sum = 0
5906 20:11:58.522660 2, 0xFFFF, sum = 0
5907 20:11:58.522742 3, 0xFFFF, sum = 0
5908 20:11:58.525913 4, 0xFFFF, sum = 0
5909 20:11:58.529167 5, 0xFFFF, sum = 0
5910 20:11:58.529249 6, 0xFFFF, sum = 0
5911 20:11:58.532512 7, 0xFFFF, sum = 0
5912 20:11:58.532594 8, 0xFFFF, sum = 0
5913 20:11:58.535809 9, 0xFFFF, sum = 0
5914 20:11:58.535892 10, 0x0, sum = 1
5915 20:11:58.539091 11, 0x0, sum = 2
5916 20:11:58.539173 12, 0x0, sum = 3
5917 20:11:58.542337 13, 0x0, sum = 4
5918 20:11:58.542419 best_step = 11
5919 20:11:58.542483
5920 20:11:58.542543 ==
5921 20:11:58.545587 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 20:11:58.549122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 20:11:58.549203 ==
5924 20:11:58.552343 RX Vref Scan: 0
5925 20:11:58.552423
5926 20:11:58.555738 RX Vref 0 -> 0, step: 1
5927 20:11:58.555822
5928 20:11:58.555907 RX Delay -69 -> 252, step: 4
5929 20:11:58.563281 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5930 20:11:58.566637 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5931 20:11:58.570137 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5932 20:11:58.573426 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5933 20:11:58.576796 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5934 20:11:58.583341 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5935 20:11:58.586522 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5936 20:11:58.589915 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5937 20:11:58.593190 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5938 20:11:58.596620 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5939 20:11:58.600010 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5940 20:11:58.606339 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5941 20:11:58.609824 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5942 20:11:58.613207 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5943 20:11:58.616494 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5944 20:11:58.619800 iDelay=203, Bit 15, Center 100 (11 ~ 190) 180
5945 20:11:58.623103 ==
5946 20:11:58.626300 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 20:11:58.629450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 20:11:58.629560 ==
5949 20:11:58.629624 DQS Delay:
5950 20:11:58.633055 DQS0 = 0, DQS1 = 0
5951 20:11:58.633135 DQM Delay:
5952 20:11:58.636459 DQM0 = 91, DQM1 = 91
5953 20:11:58.636539 DQ Delay:
5954 20:11:58.639592 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5955 20:11:58.642853 DQ4 =88, DQ5 =100, DQ6 =106, DQ7 =88
5956 20:11:58.646338 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5957 20:11:58.649585 DQ12 =100, DQ13 =100, DQ14 =94, DQ15 =100
5958 20:11:58.649667
5959 20:11:58.649731
5960 20:11:58.656300 [DQSOSCAuto] RK1, (LSB)MR18= 0xb20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5961 20:11:58.659547 CH1 RK1: MR19=505, MR18=B20
5962 20:11:58.666234 CH1_RK1: MR19=0x505, MR18=0xB20, DQSOSC=411, MR23=63, INC=64, DEC=42
5963 20:11:58.669484 [RxdqsGatingPostProcess] freq 933
5964 20:11:58.676397 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5965 20:11:58.676481 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 20:11:58.679726 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 20:11:58.683122 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 20:11:58.686395 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 20:11:58.689608 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 20:11:58.692875 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 20:11:58.696383 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 20:11:58.699783 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 20:11:58.702965 Pre-setting of DQS Precalculation
5974 20:11:58.709631 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5975 20:11:58.716088 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5976 20:11:58.722748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5977 20:11:58.722830
5978 20:11:58.722893
5979 20:11:58.726175 [Calibration Summary] 1866 Mbps
5980 20:11:58.726256 CH 0, Rank 0
5981 20:11:58.729466 SW Impedance : PASS
5982 20:11:58.732783 DUTY Scan : NO K
5983 20:11:58.732865 ZQ Calibration : PASS
5984 20:11:58.736044 Jitter Meter : NO K
5985 20:11:58.739317 CBT Training : PASS
5986 20:11:58.739399 Write leveling : PASS
5987 20:11:58.742396 RX DQS gating : PASS
5988 20:11:58.742478 RX DQ/DQS(RDDQC) : PASS
5989 20:11:58.745718 TX DQ/DQS : PASS
5990 20:11:58.749009 RX DATLAT : PASS
5991 20:11:58.749091 RX DQ/DQS(Engine): PASS
5992 20:11:58.752464 TX OE : NO K
5993 20:11:58.752546 All Pass.
5994 20:11:58.752612
5995 20:11:58.755709 CH 0, Rank 1
5996 20:11:58.755790 SW Impedance : PASS
5997 20:11:58.759175 DUTY Scan : NO K
5998 20:11:58.762419 ZQ Calibration : PASS
5999 20:11:58.762500 Jitter Meter : NO K
6000 20:11:58.765754 CBT Training : PASS
6001 20:11:58.769002 Write leveling : PASS
6002 20:11:58.769084 RX DQS gating : PASS
6003 20:11:58.772378 RX DQ/DQS(RDDQC) : PASS
6004 20:11:58.775528 TX DQ/DQS : PASS
6005 20:11:58.775628 RX DATLAT : PASS
6006 20:11:58.778801 RX DQ/DQS(Engine): PASS
6007 20:11:58.782411 TX OE : NO K
6008 20:11:58.782493 All Pass.
6009 20:11:58.782559
6010 20:11:58.782620 CH 1, Rank 0
6011 20:11:58.785741 SW Impedance : PASS
6012 20:11:58.788743 DUTY Scan : NO K
6013 20:11:58.788825 ZQ Calibration : PASS
6014 20:11:58.791961 Jitter Meter : NO K
6015 20:11:58.795458 CBT Training : PASS
6016 20:11:58.795540 Write leveling : PASS
6017 20:11:58.798908 RX DQS gating : PASS
6018 20:11:58.798994 RX DQ/DQS(RDDQC) : PASS
6019 20:11:58.802196 TX DQ/DQS : PASS
6020 20:11:58.805598 RX DATLAT : PASS
6021 20:11:58.805681 RX DQ/DQS(Engine): PASS
6022 20:11:58.808670 TX OE : NO K
6023 20:11:58.808752 All Pass.
6024 20:11:58.808817
6025 20:11:58.811916 CH 1, Rank 1
6026 20:11:58.811999 SW Impedance : PASS
6027 20:11:58.815188 DUTY Scan : NO K
6028 20:11:58.818460 ZQ Calibration : PASS
6029 20:11:58.818542 Jitter Meter : NO K
6030 20:11:58.822181 CBT Training : PASS
6031 20:11:58.825222 Write leveling : PASS
6032 20:11:58.825304 RX DQS gating : PASS
6033 20:11:58.828765 RX DQ/DQS(RDDQC) : PASS
6034 20:11:58.832042 TX DQ/DQS : PASS
6035 20:11:58.832124 RX DATLAT : PASS
6036 20:11:58.835450 RX DQ/DQS(Engine): PASS
6037 20:11:58.838512 TX OE : NO K
6038 20:11:58.838594 All Pass.
6039 20:11:58.838659
6040 20:11:58.838720 DramC Write-DBI off
6041 20:11:58.841894 PER_BANK_REFRESH: Hybrid Mode
6042 20:11:58.845221 TX_TRACKING: ON
6043 20:11:58.851881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6044 20:11:58.855148 [FAST_K] Save calibration result to emmc
6045 20:11:58.861885 dramc_set_vcore_voltage set vcore to 650000
6046 20:11:58.861995 Read voltage for 400, 6
6047 20:11:58.865395 Vio18 = 0
6048 20:11:58.865509 Vcore = 650000
6049 20:11:58.865605 Vdram = 0
6050 20:11:58.868374 Vddq = 0
6051 20:11:58.868478 Vmddr = 0
6052 20:11:58.871691 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6053 20:11:58.878630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6054 20:11:58.881657 MEM_TYPE=3, freq_sel=20
6055 20:11:58.884900 sv_algorithm_assistance_LP4_800
6056 20:11:58.888175 ============ PULL DRAM RESETB DOWN ============
6057 20:11:58.891776 ========== PULL DRAM RESETB DOWN end =========
6058 20:11:58.895009 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6059 20:11:58.898188 ===================================
6060 20:11:58.901452 LPDDR4 DRAM CONFIGURATION
6061 20:11:58.904700 ===================================
6062 20:11:58.908365 EX_ROW_EN[0] = 0x0
6063 20:11:58.908446 EX_ROW_EN[1] = 0x0
6064 20:11:58.911454 LP4Y_EN = 0x0
6065 20:11:58.911535 WORK_FSP = 0x0
6066 20:11:58.914782 WL = 0x2
6067 20:11:58.914863 RL = 0x2
6068 20:11:58.918196 BL = 0x2
6069 20:11:58.918277 RPST = 0x0
6070 20:11:58.921396 RD_PRE = 0x0
6071 20:11:58.921485 WR_PRE = 0x1
6072 20:11:58.924741 WR_PST = 0x0
6073 20:11:58.927887 DBI_WR = 0x0
6074 20:11:58.927967 DBI_RD = 0x0
6075 20:11:58.931215 OTF = 0x1
6076 20:11:58.934578 ===================================
6077 20:11:58.937876 ===================================
6078 20:11:58.937957 ANA top config
6079 20:11:58.941103 ===================================
6080 20:11:58.944445 DLL_ASYNC_EN = 0
6081 20:11:58.947740 ALL_SLAVE_EN = 1
6082 20:11:58.947822 NEW_RANK_MODE = 1
6083 20:11:58.951192 DLL_IDLE_MODE = 1
6084 20:11:58.954518 LP45_APHY_COMB_EN = 1
6085 20:11:58.957822 TX_ODT_DIS = 1
6086 20:11:58.957904 NEW_8X_MODE = 1
6087 20:11:58.961274 ===================================
6088 20:11:58.964084 ===================================
6089 20:11:58.967610 data_rate = 800
6090 20:11:58.970890 CKR = 1
6091 20:11:58.974281 DQ_P2S_RATIO = 4
6092 20:11:58.977614 ===================================
6093 20:11:58.980936 CA_P2S_RATIO = 4
6094 20:11:58.984384 DQ_CA_OPEN = 0
6095 20:11:58.984466 DQ_SEMI_OPEN = 1
6096 20:11:58.987670 CA_SEMI_OPEN = 1
6097 20:11:58.991003 CA_FULL_RATE = 0
6098 20:11:58.994449 DQ_CKDIV4_EN = 0
6099 20:11:58.997815 CA_CKDIV4_EN = 1
6100 20:11:59.001036 CA_PREDIV_EN = 0
6101 20:11:59.001121 PH8_DLY = 0
6102 20:11:59.004005 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6103 20:11:59.007332 DQ_AAMCK_DIV = 0
6104 20:11:59.010761 CA_AAMCK_DIV = 0
6105 20:11:59.013911 CA_ADMCK_DIV = 4
6106 20:11:59.017452 DQ_TRACK_CA_EN = 0
6107 20:11:59.020527 CA_PICK = 800
6108 20:11:59.020610 CA_MCKIO = 400
6109 20:11:59.024084 MCKIO_SEMI = 400
6110 20:11:59.027174 PLL_FREQ = 3016
6111 20:11:59.030427 DQ_UI_PI_RATIO = 32
6112 20:11:59.034156 CA_UI_PI_RATIO = 32
6113 20:11:59.037032 ===================================
6114 20:11:59.040509 ===================================
6115 20:11:59.043791 memory_type:LPDDR4
6116 20:11:59.043877 GP_NUM : 10
6117 20:11:59.047147 SRAM_EN : 1
6118 20:11:59.047232 MD32_EN : 0
6119 20:11:59.050418 ===================================
6120 20:11:59.053800 [ANA_INIT] >>>>>>>>>>>>>>
6121 20:11:59.057111 <<<<<< [CONFIGURE PHASE]: ANA_TX
6122 20:11:59.060396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6123 20:11:59.063606 ===================================
6124 20:11:59.066951 data_rate = 800,PCW = 0X7400
6125 20:11:59.070314 ===================================
6126 20:11:59.073465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6127 20:11:59.079991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 20:11:59.089935 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 20:11:59.093403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6130 20:11:59.099903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6131 20:11:59.103167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6132 20:11:59.103246 [ANA_INIT] flow start
6133 20:11:59.106553 [ANA_INIT] PLL >>>>>>>>
6134 20:11:59.109739 [ANA_INIT] PLL <<<<<<<<
6135 20:11:59.109821 [ANA_INIT] MIDPI >>>>>>>>
6136 20:11:59.112983 [ANA_INIT] MIDPI <<<<<<<<
6137 20:11:59.116594 [ANA_INIT] DLL >>>>>>>>
6138 20:11:59.116676 [ANA_INIT] flow end
6139 20:11:59.119845 ============ LP4 DIFF to SE enter ============
6140 20:11:59.126505 ============ LP4 DIFF to SE exit ============
6141 20:11:59.126587 [ANA_INIT] <<<<<<<<<<<<<
6142 20:11:59.129772 [Flow] Enable top DCM control >>>>>
6143 20:11:59.132834 [Flow] Enable top DCM control <<<<<
6144 20:11:59.136163 Enable DLL master slave shuffle
6145 20:11:59.142725 ==============================================================
6146 20:11:59.146159 Gating Mode config
6147 20:11:59.149750 ==============================================================
6148 20:11:59.152648 Config description:
6149 20:11:59.162804 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6150 20:11:59.169629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6151 20:11:59.172485 SELPH_MODE 0: By rank 1: By Phase
6152 20:11:59.179275 ==============================================================
6153 20:11:59.182435 GAT_TRACK_EN = 0
6154 20:11:59.185974 RX_GATING_MODE = 2
6155 20:11:59.189148 RX_GATING_TRACK_MODE = 2
6156 20:11:59.189230 SELPH_MODE = 1
6157 20:11:59.192682 PICG_EARLY_EN = 1
6158 20:11:59.195915 VALID_LAT_VALUE = 1
6159 20:11:59.202612 ==============================================================
6160 20:11:59.206123 Enter into Gating configuration >>>>
6161 20:11:59.209169 Exit from Gating configuration <<<<
6162 20:11:59.212642 Enter into DVFS_PRE_config >>>>>
6163 20:11:59.222159 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6164 20:11:59.225593 Exit from DVFS_PRE_config <<<<<
6165 20:11:59.228830 Enter into PICG configuration >>>>
6166 20:11:59.232301 Exit from PICG configuration <<<<
6167 20:11:59.235514 [RX_INPUT] configuration >>>>>
6168 20:11:59.238954 [RX_INPUT] configuration <<<<<
6169 20:11:59.242344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6170 20:11:59.248726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6171 20:11:59.255528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 20:11:59.262175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 20:11:59.268625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 20:11:59.271956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 20:11:59.278716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6176 20:11:59.282259 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6177 20:11:59.285396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6178 20:11:59.288754 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6179 20:11:59.295267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6180 20:11:59.298416 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 20:11:59.301987 ===================================
6182 20:11:59.305445 LPDDR4 DRAM CONFIGURATION
6183 20:11:59.308578 ===================================
6184 20:11:59.308660 EX_ROW_EN[0] = 0x0
6185 20:11:59.311831 EX_ROW_EN[1] = 0x0
6186 20:11:59.311912 LP4Y_EN = 0x0
6187 20:11:59.315018 WORK_FSP = 0x0
6188 20:11:59.315099 WL = 0x2
6189 20:11:59.318495 RL = 0x2
6190 20:11:59.318607 BL = 0x2
6191 20:11:59.321789 RPST = 0x0
6192 20:11:59.321871 RD_PRE = 0x0
6193 20:11:59.325147 WR_PRE = 0x1
6194 20:11:59.325228 WR_PST = 0x0
6195 20:11:59.328344 DBI_WR = 0x0
6196 20:11:59.331622 DBI_RD = 0x0
6197 20:11:59.331704 OTF = 0x1
6198 20:11:59.335331 ===================================
6199 20:11:59.338275 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6200 20:11:59.341722 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6201 20:11:59.348339 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 20:11:59.351512 ===================================
6203 20:11:59.354940 LPDDR4 DRAM CONFIGURATION
6204 20:11:59.358423 ===================================
6205 20:11:59.358505 EX_ROW_EN[0] = 0x10
6206 20:11:59.361605 EX_ROW_EN[1] = 0x0
6207 20:11:59.361686 LP4Y_EN = 0x0
6208 20:11:59.364869 WORK_FSP = 0x0
6209 20:11:59.364950 WL = 0x2
6210 20:11:59.368535 RL = 0x2
6211 20:11:59.368616 BL = 0x2
6212 20:11:59.371783 RPST = 0x0
6213 20:11:59.371864 RD_PRE = 0x0
6214 20:11:59.374710 WR_PRE = 0x1
6215 20:11:59.374791 WR_PST = 0x0
6216 20:11:59.378275 DBI_WR = 0x0
6217 20:11:59.378356 DBI_RD = 0x0
6218 20:11:59.381303 OTF = 0x1
6219 20:11:59.384676 ===================================
6220 20:11:59.391328 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6221 20:11:59.394682 nWR fixed to 30
6222 20:11:59.398131 [ModeRegInit_LP4] CH0 RK0
6223 20:11:59.398211 [ModeRegInit_LP4] CH0 RK1
6224 20:11:59.401401 [ModeRegInit_LP4] CH1 RK0
6225 20:11:59.404646 [ModeRegInit_LP4] CH1 RK1
6226 20:11:59.404727 match AC timing 19
6227 20:11:59.411051 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6228 20:11:59.414432 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6229 20:11:59.417766 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6230 20:11:59.424506 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6231 20:11:59.427652 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6232 20:11:59.427732 ==
6233 20:11:59.431210 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 20:11:59.434253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 20:11:59.434335 ==
6236 20:11:59.441118 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 20:11:59.447729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6238 20:11:59.451232 [CA 0] Center 36 (8~64) winsize 57
6239 20:11:59.454282 [CA 1] Center 36 (8~64) winsize 57
6240 20:11:59.457584 [CA 2] Center 36 (8~64) winsize 57
6241 20:11:59.460828 [CA 3] Center 36 (8~64) winsize 57
6242 20:11:59.464147 [CA 4] Center 36 (8~64) winsize 57
6243 20:11:59.464228 [CA 5] Center 36 (8~64) winsize 57
6244 20:11:59.467500
6245 20:11:59.470555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6246 20:11:59.470635
6247 20:11:59.473929 [CATrainingPosCal] consider 1 rank data
6248 20:11:59.477425 u2DelayCellTimex100 = 270/100 ps
6249 20:11:59.480876 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 20:11:59.484014 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 20:11:59.487557 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 20:11:59.490646 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 20:11:59.493763 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 20:11:59.497424 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 20:11:59.497559
6256 20:11:59.500821 CA PerBit enable=1, Macro0, CA PI delay=36
6257 20:11:59.500903
6258 20:11:59.504155 [CBTSetCACLKResult] CA Dly = 36
6259 20:11:59.507210 CS Dly: 1 (0~32)
6260 20:11:59.507290 ==
6261 20:11:59.510523 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 20:11:59.514039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 20:11:59.514120 ==
6264 20:11:59.520261 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 20:11:59.527182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6266 20:11:59.530335 [CA 0] Center 36 (8~64) winsize 57
6267 20:11:59.530416 [CA 1] Center 36 (8~64) winsize 57
6268 20:11:59.533626 [CA 2] Center 36 (8~64) winsize 57
6269 20:11:59.537018 [CA 3] Center 36 (8~64) winsize 57
6270 20:11:59.540442 [CA 4] Center 36 (8~64) winsize 57
6271 20:11:59.543522 [CA 5] Center 36 (8~64) winsize 57
6272 20:11:59.543603
6273 20:11:59.547106 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6274 20:11:59.547188
6275 20:11:59.553641 [CATrainingPosCal] consider 2 rank data
6276 20:11:59.553723 u2DelayCellTimex100 = 270/100 ps
6277 20:11:59.557074 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 20:11:59.563565 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 20:11:59.566961 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 20:11:59.570199 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 20:11:59.573633 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 20:11:59.576621 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 20:11:59.576702
6284 20:11:59.580095 CA PerBit enable=1, Macro0, CA PI delay=36
6285 20:11:59.580176
6286 20:11:59.583355 [CBTSetCACLKResult] CA Dly = 36
6287 20:11:59.586636 CS Dly: 1 (0~32)
6288 20:11:59.586717
6289 20:11:59.589943 ----->DramcWriteLeveling(PI) begin...
6290 20:11:59.590025 ==
6291 20:11:59.593313 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 20:11:59.596638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 20:11:59.596719 ==
6294 20:11:59.599873 Write leveling (Byte 0): 40 => 8
6295 20:11:59.603431 Write leveling (Byte 1): 40 => 8
6296 20:11:59.606656 DramcWriteLeveling(PI) end<-----
6297 20:11:59.606737
6298 20:11:59.606802 ==
6299 20:11:59.609784 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 20:11:59.613089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 20:11:59.613169 ==
6302 20:11:59.616566 [Gating] SW mode calibration
6303 20:11:59.623180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6304 20:11:59.629702 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6305 20:11:59.632759 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 20:11:59.636264 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 20:11:59.642734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 20:11:59.645887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 20:11:59.649501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 20:11:59.656083 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 20:11:59.659204 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 20:11:59.662496 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 20:11:59.669407 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 20:11:59.669530 Total UI for P1: 0, mck2ui 16
6315 20:11:59.675928 best dqsien dly found for B0: ( 0, 14, 24)
6316 20:11:59.676012 Total UI for P1: 0, mck2ui 16
6317 20:11:59.682325 best dqsien dly found for B1: ( 0, 14, 24)
6318 20:11:59.685911 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6319 20:11:59.688909 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6320 20:11:59.688989
6321 20:11:59.692242 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 20:11:59.695541 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 20:11:59.698902 [Gating] SW calibration Done
6324 20:11:59.698981 ==
6325 20:11:59.702258 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 20:11:59.705397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 20:11:59.705537 ==
6328 20:11:59.708871 RX Vref Scan: 0
6329 20:11:59.708950
6330 20:11:59.712089 RX Vref 0 -> 0, step: 1
6331 20:11:59.712169
6332 20:11:59.712232 RX Delay -410 -> 252, step: 16
6333 20:11:59.718527 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6334 20:11:59.721891 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6335 20:11:59.725350 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6336 20:11:59.728607 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6337 20:11:59.735184 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6338 20:11:59.738792 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6339 20:11:59.742068 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6340 20:11:59.745365 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6341 20:11:59.751823 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6342 20:11:59.755073 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6343 20:11:59.758462 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6344 20:11:59.762042 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6345 20:11:59.768635 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6346 20:11:59.772038 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6347 20:11:59.775352 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6348 20:11:59.781857 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6349 20:11:59.781945 ==
6350 20:11:59.785186 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 20:11:59.788676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 20:11:59.788757 ==
6353 20:11:59.788820 DQS Delay:
6354 20:11:59.792012 DQS0 = 59, DQS1 = 59
6355 20:11:59.792092 DQM Delay:
6356 20:11:59.794990 DQM0 = 18, DQM1 = 10
6357 20:11:59.795069 DQ Delay:
6358 20:11:59.798388 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6359 20:11:59.801685 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6360 20:11:59.805048 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6361 20:11:59.808099 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6362 20:11:59.808180
6363 20:11:59.808243
6364 20:11:59.808303 ==
6365 20:11:59.811512 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 20:11:59.814953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 20:11:59.815035 ==
6368 20:11:59.815099
6369 20:11:59.815160
6370 20:11:59.818199 TX Vref Scan disable
6371 20:11:59.821453 == TX Byte 0 ==
6372 20:11:59.825160 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 20:11:59.827984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 20:11:59.831328 == TX Byte 1 ==
6375 20:11:59.834528 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 20:11:59.837830 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 20:11:59.837911 ==
6378 20:11:59.841314 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 20:11:59.844674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 20:11:59.844782 ==
6381 20:11:59.844874
6382 20:11:59.848030
6383 20:11:59.848112 TX Vref Scan disable
6384 20:11:59.851130 == TX Byte 0 ==
6385 20:11:59.854697 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 20:11:59.857964 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 20:11:59.861239 == TX Byte 1 ==
6388 20:11:59.864492 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 20:11:59.867775 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 20:11:59.867857
6391 20:11:59.867921 [DATLAT]
6392 20:11:59.870877 Freq=400, CH0 RK0
6393 20:11:59.870957
6394 20:11:59.874386 DATLAT Default: 0xf
6395 20:11:59.874467 0, 0xFFFF, sum = 0
6396 20:11:59.877680 1, 0xFFFF, sum = 0
6397 20:11:59.877762 2, 0xFFFF, sum = 0
6398 20:11:59.880804 3, 0xFFFF, sum = 0
6399 20:11:59.880887 4, 0xFFFF, sum = 0
6400 20:11:59.884464 5, 0xFFFF, sum = 0
6401 20:11:59.884546 6, 0xFFFF, sum = 0
6402 20:11:59.887618 7, 0xFFFF, sum = 0
6403 20:11:59.887700 8, 0xFFFF, sum = 0
6404 20:11:59.891004 9, 0xFFFF, sum = 0
6405 20:11:59.891086 10, 0xFFFF, sum = 0
6406 20:11:59.893980 11, 0xFFFF, sum = 0
6407 20:11:59.894063 12, 0xFFFF, sum = 0
6408 20:11:59.897553 13, 0x0, sum = 1
6409 20:11:59.897635 14, 0x0, sum = 2
6410 20:11:59.900933 15, 0x0, sum = 3
6411 20:11:59.901015 16, 0x0, sum = 4
6412 20:11:59.903948 best_step = 14
6413 20:11:59.904030
6414 20:11:59.904094 ==
6415 20:11:59.907342 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 20:11:59.910564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 20:11:59.910646 ==
6418 20:11:59.914010 RX Vref Scan: 1
6419 20:11:59.914091
6420 20:11:59.914154 RX Vref 0 -> 0, step: 1
6421 20:11:59.914214
6422 20:11:59.917469 RX Delay -359 -> 252, step: 8
6423 20:11:59.917595
6424 20:11:59.920689 Set Vref, RX VrefLevel [Byte0]: 60
6425 20:11:59.924020 [Byte1]: 45
6426 20:11:59.928372
6427 20:11:59.928479 Final RX Vref Byte 0 = 60 to rank0
6428 20:11:59.931937 Final RX Vref Byte 1 = 45 to rank0
6429 20:11:59.935146 Final RX Vref Byte 0 = 60 to rank1
6430 20:11:59.938232 Final RX Vref Byte 1 = 45 to rank1==
6431 20:11:59.941452 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 20:11:59.948047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 20:11:59.948132 ==
6434 20:11:59.948195 DQS Delay:
6435 20:11:59.951634 DQS0 = 60, DQS1 = 68
6436 20:11:59.951713 DQM Delay:
6437 20:11:59.951777 DQM0 = 14, DQM1 = 13
6438 20:11:59.954848 DQ Delay:
6439 20:11:59.958148 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6440 20:11:59.961374 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6441 20:11:59.964901 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6442 20:11:59.968132 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6443 20:11:59.968212
6444 20:11:59.968275
6445 20:11:59.974478 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b88, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6446 20:11:59.978101 CH0 RK0: MR19=C0C, MR18=8B88
6447 20:11:59.984743 CH0_RK0: MR19=0xC0C, MR18=0x8B88, DQSOSC=392, MR23=63, INC=384, DEC=256
6448 20:11:59.984823 ==
6449 20:11:59.988128 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 20:11:59.991307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 20:11:59.991419 ==
6452 20:11:59.994556 [Gating] SW mode calibration
6453 20:12:00.001180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6454 20:12:00.008013 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6455 20:12:00.011108 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 20:12:00.014345 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 20:12:00.021133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 20:12:00.024505 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 20:12:00.027722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 20:12:00.034550 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 20:12:00.037443 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 20:12:00.040969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 20:12:00.047765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 20:12:00.047845 Total UI for P1: 0, mck2ui 16
6465 20:12:00.054218 best dqsien dly found for B0: ( 0, 14, 24)
6466 20:12:00.054301 Total UI for P1: 0, mck2ui 16
6467 20:12:00.060767 best dqsien dly found for B1: ( 0, 14, 24)
6468 20:12:00.064278 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6469 20:12:00.067469 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6470 20:12:00.067548
6471 20:12:00.070953 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 20:12:00.074079 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 20:12:00.077294 [Gating] SW calibration Done
6474 20:12:00.077373 ==
6475 20:12:00.080652 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 20:12:00.084079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 20:12:00.084159 ==
6478 20:12:00.087361 RX Vref Scan: 0
6479 20:12:00.087440
6480 20:12:00.087502 RX Vref 0 -> 0, step: 1
6481 20:12:00.087560
6482 20:12:00.090606 RX Delay -410 -> 252, step: 16
6483 20:12:00.097347 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6484 20:12:00.100724 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6485 20:12:00.104006 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6486 20:12:00.107388 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6487 20:12:00.114052 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6488 20:12:00.116981 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6489 20:12:00.120350 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6490 20:12:00.123774 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6491 20:12:00.130533 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6492 20:12:00.133867 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6493 20:12:00.136925 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6494 20:12:00.140175 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6495 20:12:00.146833 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6496 20:12:00.150270 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6497 20:12:00.153484 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6498 20:12:00.156735 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6499 20:12:00.160254 ==
6500 20:12:00.163574 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 20:12:00.166683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 20:12:00.166763 ==
6503 20:12:00.166826 DQS Delay:
6504 20:12:00.170189 DQS0 = 59, DQS1 = 67
6505 20:12:00.170268 DQM Delay:
6506 20:12:00.173700 DQM0 = 17, DQM1 = 17
6507 20:12:00.173780 DQ Delay:
6508 20:12:00.176878 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6509 20:12:00.180424 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6510 20:12:00.183425 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6511 20:12:00.186707 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6512 20:12:00.186786
6513 20:12:00.186848
6514 20:12:00.186906 ==
6515 20:12:00.190126 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 20:12:00.193443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 20:12:00.193584 ==
6518 20:12:00.193648
6519 20:12:00.193707
6520 20:12:00.196661 TX Vref Scan disable
6521 20:12:00.196740 == TX Byte 0 ==
6522 20:12:00.203211 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6523 20:12:00.206523 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6524 20:12:00.206603 == TX Byte 1 ==
6525 20:12:00.213146 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6526 20:12:00.216662 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6527 20:12:00.216742 ==
6528 20:12:00.219645 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 20:12:00.222966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 20:12:00.223046 ==
6531 20:12:00.223109
6532 20:12:00.223167
6533 20:12:00.226418 TX Vref Scan disable
6534 20:12:00.229671 == TX Byte 0 ==
6535 20:12:00.232978 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6536 20:12:00.236014 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6537 20:12:00.239372 == TX Byte 1 ==
6538 20:12:00.242815 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 20:12:00.246069 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 20:12:00.246150
6541 20:12:00.246214 [DATLAT]
6542 20:12:00.249388 Freq=400, CH0 RK1
6543 20:12:00.249469
6544 20:12:00.249542 DATLAT Default: 0xe
6545 20:12:00.252487 0, 0xFFFF, sum = 0
6546 20:12:00.255760 1, 0xFFFF, sum = 0
6547 20:12:00.255842 2, 0xFFFF, sum = 0
6548 20:12:00.259407 3, 0xFFFF, sum = 0
6549 20:12:00.259489 4, 0xFFFF, sum = 0
6550 20:12:00.262815 5, 0xFFFF, sum = 0
6551 20:12:00.262897 6, 0xFFFF, sum = 0
6552 20:12:00.266058 7, 0xFFFF, sum = 0
6553 20:12:00.266142 8, 0xFFFF, sum = 0
6554 20:12:00.269299 9, 0xFFFF, sum = 0
6555 20:12:00.269381 10, 0xFFFF, sum = 0
6556 20:12:00.272377 11, 0xFFFF, sum = 0
6557 20:12:00.272459 12, 0xFFFF, sum = 0
6558 20:12:00.275926 13, 0x0, sum = 1
6559 20:12:00.276007 14, 0x0, sum = 2
6560 20:12:00.279244 15, 0x0, sum = 3
6561 20:12:00.279325 16, 0x0, sum = 4
6562 20:12:00.282302 best_step = 14
6563 20:12:00.282381
6564 20:12:00.282445 ==
6565 20:12:00.285644 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 20:12:00.289232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 20:12:00.289314 ==
6568 20:12:00.292478 RX Vref Scan: 0
6569 20:12:00.292563
6570 20:12:00.292631 RX Vref 0 -> 0, step: 1
6571 20:12:00.292690
6572 20:12:00.295774 RX Delay -359 -> 252, step: 8
6573 20:12:00.303242 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6574 20:12:00.306700 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6575 20:12:00.310038 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6576 20:12:00.313225 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6577 20:12:00.319951 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6578 20:12:00.323373 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6579 20:12:00.326509 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6580 20:12:00.329869 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6581 20:12:00.336440 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6582 20:12:00.339866 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6583 20:12:00.343225 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6584 20:12:00.349888 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6585 20:12:00.353210 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6586 20:12:00.356130 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6587 20:12:00.359603 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6588 20:12:00.366472 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6589 20:12:00.366557 ==
6590 20:12:00.369399 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 20:12:00.372970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 20:12:00.373055 ==
6593 20:12:00.373139 DQS Delay:
6594 20:12:00.376399 DQS0 = 60, DQS1 = 72
6595 20:12:00.376561 DQM Delay:
6596 20:12:00.379892 DQM0 = 11, DQM1 = 16
6597 20:12:00.380053 DQ Delay:
6598 20:12:00.382867 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6599 20:12:00.386557 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6600 20:12:00.389714 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6601 20:12:00.393114 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6602 20:12:00.393276
6603 20:12:00.393382
6604 20:12:00.399932 [DQSOSCAuto] RK1, (LSB)MR18= 0xc378, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6605 20:12:00.403132 CH0 RK1: MR19=C0C, MR18=C378
6606 20:12:00.409748 CH0_RK1: MR19=0xC0C, MR18=0xC378, DQSOSC=385, MR23=63, INC=398, DEC=265
6607 20:12:00.412916 [RxdqsGatingPostProcess] freq 400
6608 20:12:00.419495 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6609 20:12:00.423006 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 20:12:00.423189 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 20:12:00.426065 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 20:12:00.429437 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 20:12:00.432640 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 20:12:00.435857 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 20:12:00.439542 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 20:12:00.442689 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 20:12:00.445927 Pre-setting of DQS Precalculation
6618 20:12:00.452568 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6619 20:12:00.452861 ==
6620 20:12:00.455892 Dram Type= 6, Freq= 0, CH_1, rank 0
6621 20:12:00.459536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 20:12:00.459783 ==
6623 20:12:00.465991 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 20:12:00.469606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6625 20:12:00.473054 [CA 0] Center 36 (8~64) winsize 57
6626 20:12:00.476188 [CA 1] Center 36 (8~64) winsize 57
6627 20:12:00.479242 [CA 2] Center 36 (8~64) winsize 57
6628 20:12:00.482160 [CA 3] Center 36 (8~64) winsize 57
6629 20:12:00.485458 [CA 4] Center 36 (8~64) winsize 57
6630 20:12:00.488899 [CA 5] Center 36 (8~64) winsize 57
6631 20:12:00.489050
6632 20:12:00.492198 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6633 20:12:00.492290
6634 20:12:00.495284 [CATrainingPosCal] consider 1 rank data
6635 20:12:00.499018 u2DelayCellTimex100 = 270/100 ps
6636 20:12:00.501967 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 20:12:00.505392 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 20:12:00.511924 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 20:12:00.515253 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 20:12:00.518359 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 20:12:00.521763 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 20:12:00.521854
6643 20:12:00.524949 CA PerBit enable=1, Macro0, CA PI delay=36
6644 20:12:00.525037
6645 20:12:00.528520 [CBTSetCACLKResult] CA Dly = 36
6646 20:12:00.528611 CS Dly: 1 (0~32)
6647 20:12:00.531918 ==
6648 20:12:00.532008 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 20:12:00.538364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 20:12:00.538452 ==
6651 20:12:00.541741 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 20:12:00.548495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6653 20:12:00.551943 [CA 0] Center 36 (8~64) winsize 57
6654 20:12:00.555268 [CA 1] Center 36 (8~64) winsize 57
6655 20:12:00.558401 [CA 2] Center 36 (8~64) winsize 57
6656 20:12:00.561827 [CA 3] Center 36 (8~64) winsize 57
6657 20:12:00.565372 [CA 4] Center 36 (8~64) winsize 57
6658 20:12:00.568430 [CA 5] Center 36 (8~64) winsize 57
6659 20:12:00.568581
6660 20:12:00.572042 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6661 20:12:00.572207
6662 20:12:00.575320 [CATrainingPosCal] consider 2 rank data
6663 20:12:00.578717 u2DelayCellTimex100 = 270/100 ps
6664 20:12:00.581688 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 20:12:00.585222 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 20:12:00.588646 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 20:12:00.591717 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 20:12:00.595056 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 20:12:00.601693 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 20:12:00.601820
6671 20:12:00.604963 CA PerBit enable=1, Macro0, CA PI delay=36
6672 20:12:00.605142
6673 20:12:00.608086 [CBTSetCACLKResult] CA Dly = 36
6674 20:12:00.608215 CS Dly: 1 (0~32)
6675 20:12:00.608346
6676 20:12:00.611726 ----->DramcWriteLeveling(PI) begin...
6677 20:12:00.611857 ==
6678 20:12:00.614963 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 20:12:00.618299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 20:12:00.621436 ==
6681 20:12:00.621569 Write leveling (Byte 0): 40 => 8
6682 20:12:00.624916 Write leveling (Byte 1): 40 => 8
6683 20:12:00.628154 DramcWriteLeveling(PI) end<-----
6684 20:12:00.628245
6685 20:12:00.628337 ==
6686 20:12:00.631253 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 20:12:00.638150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 20:12:00.638235 ==
6689 20:12:00.641403 [Gating] SW mode calibration
6690 20:12:00.647897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6691 20:12:00.651399 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6692 20:12:00.657862 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 20:12:00.661302 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 20:12:00.664151 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 20:12:00.671035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 20:12:00.674258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 20:12:00.677787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 20:12:00.684206 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 20:12:00.687483 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 20:12:00.691150 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 20:12:00.693984 Total UI for P1: 0, mck2ui 16
6702 20:12:00.697388 best dqsien dly found for B0: ( 0, 14, 24)
6703 20:12:00.700860 Total UI for P1: 0, mck2ui 16
6704 20:12:00.704228 best dqsien dly found for B1: ( 0, 14, 24)
6705 20:12:00.707262 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6706 20:12:00.710740 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6707 20:12:00.710823
6708 20:12:00.713927 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 20:12:00.720739 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 20:12:00.720825 [Gating] SW calibration Done
6711 20:12:00.724006 ==
6712 20:12:00.724090 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 20:12:00.730809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 20:12:00.730893 ==
6715 20:12:00.730993 RX Vref Scan: 0
6716 20:12:00.731092
6717 20:12:00.733901 RX Vref 0 -> 0, step: 1
6718 20:12:00.733983
6719 20:12:00.737229 RX Delay -410 -> 252, step: 16
6720 20:12:00.740565 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6721 20:12:00.743874 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6722 20:12:00.750368 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6723 20:12:00.753613 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6724 20:12:00.757057 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6725 20:12:00.760424 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6726 20:12:00.767155 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6727 20:12:00.770152 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6728 20:12:00.773455 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6729 20:12:00.776622 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6730 20:12:00.783360 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6731 20:12:00.786685 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6732 20:12:00.790135 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6733 20:12:00.796854 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6734 20:12:00.799906 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6735 20:12:00.803265 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6736 20:12:00.803345 ==
6737 20:12:00.806737 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 20:12:00.809819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 20:12:00.813003 ==
6740 20:12:00.813109 DQS Delay:
6741 20:12:00.813200 DQS0 = 51, DQS1 = 67
6742 20:12:00.816377 DQM Delay:
6743 20:12:00.816457 DQM0 = 12, DQM1 = 19
6744 20:12:00.819780 DQ Delay:
6745 20:12:00.819860 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6746 20:12:00.822943 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6747 20:12:00.826387 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6748 20:12:00.829670 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6749 20:12:00.829757
6750 20:12:00.829823
6751 20:12:00.832910 ==
6752 20:12:00.836177 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 20:12:00.839638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 20:12:00.839719 ==
6755 20:12:00.839788
6756 20:12:00.839851
6757 20:12:00.842808 TX Vref Scan disable
6758 20:12:00.842887 == TX Byte 0 ==
6759 20:12:00.846352 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 20:12:00.852964 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 20:12:00.853044 == TX Byte 1 ==
6762 20:12:00.856368 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 20:12:00.862783 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 20:12:00.862874 ==
6765 20:12:00.865981 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 20:12:00.869362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 20:12:00.869459 ==
6768 20:12:00.869544
6769 20:12:00.869603
6770 20:12:00.872683 TX Vref Scan disable
6771 20:12:00.872762 == TX Byte 0 ==
6772 20:12:00.876054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 20:12:00.882877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 20:12:00.882957 == TX Byte 1 ==
6775 20:12:00.886142 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 20:12:00.892777 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 20:12:00.892860
6778 20:12:00.892923 [DATLAT]
6779 20:12:00.892982 Freq=400, CH1 RK0
6780 20:12:00.893040
6781 20:12:00.895826 DATLAT Default: 0xf
6782 20:12:00.899114 0, 0xFFFF, sum = 0
6783 20:12:00.899210 1, 0xFFFF, sum = 0
6784 20:12:00.902373 2, 0xFFFF, sum = 0
6785 20:12:00.902468 3, 0xFFFF, sum = 0
6786 20:12:00.905776 4, 0xFFFF, sum = 0
6787 20:12:00.905884 5, 0xFFFF, sum = 0
6788 20:12:00.909192 6, 0xFFFF, sum = 0
6789 20:12:00.909328 7, 0xFFFF, sum = 0
6790 20:12:00.912407 8, 0xFFFF, sum = 0
6791 20:12:00.912515 9, 0xFFFF, sum = 0
6792 20:12:00.915825 10, 0xFFFF, sum = 0
6793 20:12:00.915916 11, 0xFFFF, sum = 0
6794 20:12:00.919181 12, 0xFFFF, sum = 0
6795 20:12:00.919264 13, 0x0, sum = 1
6796 20:12:00.922600 14, 0x0, sum = 2
6797 20:12:00.922683 15, 0x0, sum = 3
6798 20:12:00.925641 16, 0x0, sum = 4
6799 20:12:00.925722 best_step = 14
6800 20:12:00.925787
6801 20:12:00.925845 ==
6802 20:12:00.929007 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 20:12:00.932330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 20:12:00.935816 ==
6805 20:12:00.935896 RX Vref Scan: 1
6806 20:12:00.935961
6807 20:12:00.939030 RX Vref 0 -> 0, step: 1
6808 20:12:00.939182
6809 20:12:00.942399 RX Delay -375 -> 252, step: 8
6810 20:12:00.942533
6811 20:12:00.945833 Set Vref, RX VrefLevel [Byte0]: 58
6812 20:12:00.949357 [Byte1]: 49
6813 20:12:00.949561
6814 20:12:00.952748 Final RX Vref Byte 0 = 58 to rank0
6815 20:12:00.955895 Final RX Vref Byte 1 = 49 to rank0
6816 20:12:00.959346 Final RX Vref Byte 0 = 58 to rank1
6817 20:12:00.962585 Final RX Vref Byte 1 = 49 to rank1==
6818 20:12:00.965855 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 20:12:00.969062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 20:12:00.972615 ==
6821 20:12:00.972830 DQS Delay:
6822 20:12:00.972952 DQS0 = 56, DQS1 = 68
6823 20:12:00.975975 DQM Delay:
6824 20:12:00.976252 DQM0 = 13, DQM1 = 14
6825 20:12:00.978777 DQ Delay:
6826 20:12:00.979027 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6827 20:12:00.982086 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6828 20:12:00.985784 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6829 20:12:00.989029 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6830 20:12:00.989324
6831 20:12:00.989533
6832 20:12:00.999508 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6833 20:12:01.002269 CH1 RK0: MR19=C0C, MR18=5A6D
6834 20:12:01.009533 CH1_RK0: MR19=0xC0C, MR18=0x5A6D, DQSOSC=396, MR23=63, INC=376, DEC=251
6835 20:12:01.010057 ==
6836 20:12:01.012595 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 20:12:01.015854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 20:12:01.016367 ==
6839 20:12:01.018928 [Gating] SW mode calibration
6840 20:12:01.025436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6841 20:12:01.028810 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6842 20:12:01.035738 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 20:12:01.039316 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6844 20:12:01.042359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 20:12:01.049171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 20:12:01.051927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 20:12:01.055338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 20:12:01.062170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 20:12:01.065456 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 20:12:01.068864 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 20:12:01.071925 Total UI for P1: 0, mck2ui 16
6852 20:12:01.075612 best dqsien dly found for B0: ( 0, 14, 24)
6853 20:12:01.078583 Total UI for P1: 0, mck2ui 16
6854 20:12:01.082384 best dqsien dly found for B1: ( 0, 14, 24)
6855 20:12:01.085420 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6856 20:12:01.089009 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6857 20:12:01.089573
6858 20:12:01.095367 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 20:12:01.098762 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 20:12:01.102074 [Gating] SW calibration Done
6861 20:12:01.102613 ==
6862 20:12:01.105647 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 20:12:01.108650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 20:12:01.109176 ==
6865 20:12:01.109562 RX Vref Scan: 0
6866 20:12:01.109887
6867 20:12:01.112167 RX Vref 0 -> 0, step: 1
6868 20:12:01.112691
6869 20:12:01.115281 RX Delay -410 -> 252, step: 16
6870 20:12:01.118503 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6871 20:12:01.125295 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6872 20:12:01.128565 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6873 20:12:01.131717 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6874 20:12:01.135311 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6875 20:12:01.142001 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6876 20:12:01.145128 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6877 20:12:01.148161 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6878 20:12:01.151675 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6879 20:12:01.158068 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6880 20:12:01.161414 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6881 20:12:01.164653 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6882 20:12:01.168250 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6883 20:12:01.174643 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6884 20:12:01.177913 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6885 20:12:01.180895 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6886 20:12:01.181308 ==
6887 20:12:01.184763 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 20:12:01.190893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 20:12:01.191578 ==
6890 20:12:01.192184 DQS Delay:
6891 20:12:01.194202 DQS0 = 59, DQS1 = 59
6892 20:12:01.194648 DQM Delay:
6893 20:12:01.197632 DQM0 = 19, DQM1 = 12
6894 20:12:01.198047 DQ Delay:
6895 20:12:01.200598 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6896 20:12:01.204027 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6897 20:12:01.207553 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6898 20:12:01.211062 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6899 20:12:01.211477
6900 20:12:01.211808
6901 20:12:01.212109 ==
6902 20:12:01.214255 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 20:12:01.217464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 20:12:01.217936 ==
6905 20:12:01.218264
6906 20:12:01.218568
6907 20:12:01.220756 TX Vref Scan disable
6908 20:12:01.221165 == TX Byte 0 ==
6909 20:12:01.227389 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6910 20:12:01.230847 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6911 20:12:01.231227 == TX Byte 1 ==
6912 20:12:01.234159 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6913 20:12:01.240463 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6914 20:12:01.240841 ==
6915 20:12:01.243799 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 20:12:01.247404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 20:12:01.247908 ==
6918 20:12:01.248250
6919 20:12:01.248576
6920 20:12:01.250350 TX Vref Scan disable
6921 20:12:01.250897 == TX Byte 0 ==
6922 20:12:01.257217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6923 20:12:01.260646 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6924 20:12:01.261060 == TX Byte 1 ==
6925 20:12:01.267308 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 20:12:01.270344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 20:12:01.270997
6928 20:12:01.271600 [DATLAT]
6929 20:12:01.273631 Freq=400, CH1 RK1
6930 20:12:01.274261
6931 20:12:01.274858 DATLAT Default: 0xe
6932 20:12:01.276834 0, 0xFFFF, sum = 0
6933 20:12:01.277513 1, 0xFFFF, sum = 0
6934 20:12:01.280605 2, 0xFFFF, sum = 0
6935 20:12:01.281022 3, 0xFFFF, sum = 0
6936 20:12:01.283630 4, 0xFFFF, sum = 0
6937 20:12:01.284217 5, 0xFFFF, sum = 0
6938 20:12:01.287133 6, 0xFFFF, sum = 0
6939 20:12:01.287655 7, 0xFFFF, sum = 0
6940 20:12:01.290270 8, 0xFFFF, sum = 0
6941 20:12:01.290880 9, 0xFFFF, sum = 0
6942 20:12:01.293702 10, 0xFFFF, sum = 0
6943 20:12:01.294120 11, 0xFFFF, sum = 0
6944 20:12:01.297217 12, 0xFFFF, sum = 0
6945 20:12:01.297851 13, 0x0, sum = 1
6946 20:12:01.300439 14, 0x0, sum = 2
6947 20:12:01.300954 15, 0x0, sum = 3
6948 20:12:01.303563 16, 0x0, sum = 4
6949 20:12:01.304133 best_step = 14
6950 20:12:01.304602
6951 20:12:01.305051 ==
6952 20:12:01.307037 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 20:12:01.353634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 20:12:01.354487 ==
6955 20:12:01.355190 RX Vref Scan: 0
6956 20:12:01.355819
6957 20:12:01.356378 RX Vref 0 -> 0, step: 1
6958 20:12:01.356932
6959 20:12:01.357524 RX Delay -359 -> 252, step: 8
6960 20:12:01.358102 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6961 20:12:01.358673 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6962 20:12:01.359239 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6963 20:12:01.359805 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6964 20:12:01.360372 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6965 20:12:01.361198 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6966 20:12:01.361958 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6967 20:12:01.362532 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6968 20:12:01.363479 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6969 20:12:01.364149 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
6970 20:12:01.366637 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6971 20:12:01.369960 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6972 20:12:01.376698 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6973 20:12:01.379756 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6974 20:12:01.382801 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6975 20:12:01.389599 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6976 20:12:01.389820 ==
6977 20:12:01.392931 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 20:12:01.396183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 20:12:01.396326 ==
6980 20:12:01.396455 DQS Delay:
6981 20:12:01.399496 DQS0 = 60, DQS1 = 64
6982 20:12:01.399635 DQM Delay:
6983 20:12:01.402665 DQM0 = 13, DQM1 = 11
6984 20:12:01.402815 DQ Delay:
6985 20:12:01.406109 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6986 20:12:01.409461 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6987 20:12:01.412747 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6988 20:12:01.415743 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6989 20:12:01.415854
6990 20:12:01.415967
6991 20:12:01.422736 [DQSOSCAuto] RK1, (LSB)MR18= 0x80af, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
6992 20:12:01.425745 CH1 RK1: MR19=C0C, MR18=80AF
6993 20:12:01.432348 CH1_RK1: MR19=0xC0C, MR18=0x80AF, DQSOSC=388, MR23=63, INC=392, DEC=261
6994 20:12:01.435832 [RxdqsGatingPostProcess] freq 400
6995 20:12:01.442541 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6996 20:12:01.445463 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 20:12:01.448916 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 20:12:01.452371 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 20:12:01.455483 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 20:12:01.455575 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 20:12:01.458747 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 20:12:01.462249 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 20:12:01.465298 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 20:12:01.468602 Pre-setting of DQS Precalculation
7005 20:12:01.475464 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7006 20:12:01.481792 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7007 20:12:01.488599 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7008 20:12:01.488698
7009 20:12:01.488763
7010 20:12:01.491670 [Calibration Summary] 800 Mbps
7011 20:12:01.491767 CH 0, Rank 0
7012 20:12:01.495143 SW Impedance : PASS
7013 20:12:01.498250 DUTY Scan : NO K
7014 20:12:01.498332 ZQ Calibration : PASS
7015 20:12:01.501707 Jitter Meter : NO K
7016 20:12:01.504864 CBT Training : PASS
7017 20:12:01.504990 Write leveling : PASS
7018 20:12:01.508393 RX DQS gating : PASS
7019 20:12:01.511350 RX DQ/DQS(RDDQC) : PASS
7020 20:12:01.511455 TX DQ/DQS : PASS
7021 20:12:01.514821 RX DATLAT : PASS
7022 20:12:01.518040 RX DQ/DQS(Engine): PASS
7023 20:12:01.518115 TX OE : NO K
7024 20:12:01.521446 All Pass.
7025 20:12:01.521569
7026 20:12:01.521650 CH 0, Rank 1
7027 20:12:01.524859 SW Impedance : PASS
7028 20:12:01.524961 DUTY Scan : NO K
7029 20:12:01.527900 ZQ Calibration : PASS
7030 20:12:01.531347 Jitter Meter : NO K
7031 20:12:01.531451 CBT Training : PASS
7032 20:12:01.534584 Write leveling : NO K
7033 20:12:01.537884 RX DQS gating : PASS
7034 20:12:01.537968 RX DQ/DQS(RDDQC) : PASS
7035 20:12:01.541425 TX DQ/DQS : PASS
7036 20:12:01.541586 RX DATLAT : PASS
7037 20:12:01.544758 RX DQ/DQS(Engine): PASS
7038 20:12:01.547794 TX OE : NO K
7039 20:12:01.547897 All Pass.
7040 20:12:01.547992
7041 20:12:01.548079 CH 1, Rank 0
7042 20:12:01.551206 SW Impedance : PASS
7043 20:12:01.554674 DUTY Scan : NO K
7044 20:12:01.554748 ZQ Calibration : PASS
7045 20:12:01.557917 Jitter Meter : NO K
7046 20:12:01.561214 CBT Training : PASS
7047 20:12:01.561313 Write leveling : PASS
7048 20:12:01.564533 RX DQS gating : PASS
7049 20:12:01.567892 RX DQ/DQS(RDDQC) : PASS
7050 20:12:01.567968 TX DQ/DQS : PASS
7051 20:12:01.571013 RX DATLAT : PASS
7052 20:12:01.574513 RX DQ/DQS(Engine): PASS
7053 20:12:01.574586 TX OE : NO K
7054 20:12:01.577718 All Pass.
7055 20:12:01.577795
7056 20:12:01.577857 CH 1, Rank 1
7057 20:12:01.581146 SW Impedance : PASS
7058 20:12:01.581218 DUTY Scan : NO K
7059 20:12:01.584255 ZQ Calibration : PASS
7060 20:12:01.587867 Jitter Meter : NO K
7061 20:12:01.587939 CBT Training : PASS
7062 20:12:01.590920 Write leveling : NO K
7063 20:12:01.594196 RX DQS gating : PASS
7064 20:12:01.594268 RX DQ/DQS(RDDQC) : PASS
7065 20:12:01.597885 TX DQ/DQS : PASS
7066 20:12:01.597956 RX DATLAT : PASS
7067 20:12:01.601105 RX DQ/DQS(Engine): PASS
7068 20:12:01.604094 TX OE : NO K
7069 20:12:01.604162 All Pass.
7070 20:12:01.604223
7071 20:12:01.607625 DramC Write-DBI off
7072 20:12:01.607701 PER_BANK_REFRESH: Hybrid Mode
7073 20:12:01.610975 TX_TRACKING: ON
7074 20:12:01.620691 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7075 20:12:01.624091 [FAST_K] Save calibration result to emmc
7076 20:12:01.627634 dramc_set_vcore_voltage set vcore to 725000
7077 20:12:01.627709 Read voltage for 1600, 0
7078 20:12:01.630948 Vio18 = 0
7079 20:12:01.631021 Vcore = 725000
7080 20:12:01.631082 Vdram = 0
7081 20:12:01.634673 Vddq = 0
7082 20:12:01.634744 Vmddr = 0
7083 20:12:01.640897 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7084 20:12:01.644055 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7085 20:12:01.647518 MEM_TYPE=3, freq_sel=13
7086 20:12:01.650529 sv_algorithm_assistance_LP4_3733
7087 20:12:01.654073 ============ PULL DRAM RESETB DOWN ============
7088 20:12:01.657250 ========== PULL DRAM RESETB DOWN end =========
7089 20:12:01.663778 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7090 20:12:01.667292 ===================================
7091 20:12:01.667370 LPDDR4 DRAM CONFIGURATION
7092 20:12:01.670365 ===================================
7093 20:12:01.673633 EX_ROW_EN[0] = 0x0
7094 20:12:01.676696 EX_ROW_EN[1] = 0x0
7095 20:12:01.676777 LP4Y_EN = 0x0
7096 20:12:01.680406 WORK_FSP = 0x1
7097 20:12:01.680480 WL = 0x5
7098 20:12:01.683394 RL = 0x5
7099 20:12:01.683467 BL = 0x2
7100 20:12:01.686939 RPST = 0x0
7101 20:12:01.687010 RD_PRE = 0x0
7102 20:12:01.690209 WR_PRE = 0x1
7103 20:12:01.690284 WR_PST = 0x1
7104 20:12:01.693460 DBI_WR = 0x0
7105 20:12:01.693570 DBI_RD = 0x0
7106 20:12:01.696556 OTF = 0x1
7107 20:12:01.699901 ===================================
7108 20:12:01.703140 ===================================
7109 20:12:01.703216 ANA top config
7110 20:12:01.706797 ===================================
7111 20:12:01.709734 DLL_ASYNC_EN = 0
7112 20:12:01.713217 ALL_SLAVE_EN = 0
7113 20:12:01.716283 NEW_RANK_MODE = 1
7114 20:12:01.716356 DLL_IDLE_MODE = 1
7115 20:12:01.719646 LP45_APHY_COMB_EN = 1
7116 20:12:01.723376 TX_ODT_DIS = 0
7117 20:12:01.726422 NEW_8X_MODE = 1
7118 20:12:01.729532 ===================================
7119 20:12:01.732968 ===================================
7120 20:12:01.736488 data_rate = 3200
7121 20:12:01.736564 CKR = 1
7122 20:12:01.739798 DQ_P2S_RATIO = 8
7123 20:12:01.743126 ===================================
7124 20:12:01.746444 CA_P2S_RATIO = 8
7125 20:12:01.749620 DQ_CA_OPEN = 0
7126 20:12:01.752896 DQ_SEMI_OPEN = 0
7127 20:12:01.756091 CA_SEMI_OPEN = 0
7128 20:12:01.756171 CA_FULL_RATE = 0
7129 20:12:01.759710 DQ_CKDIV4_EN = 0
7130 20:12:01.762809 CA_CKDIV4_EN = 0
7131 20:12:01.766107 CA_PREDIV_EN = 0
7132 20:12:01.769460 PH8_DLY = 12
7133 20:12:01.772575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7134 20:12:01.772648 DQ_AAMCK_DIV = 4
7135 20:12:01.775871 CA_AAMCK_DIV = 4
7136 20:12:01.779336 CA_ADMCK_DIV = 4
7137 20:12:01.782813 DQ_TRACK_CA_EN = 0
7138 20:12:01.785939 CA_PICK = 1600
7139 20:12:01.789578 CA_MCKIO = 1600
7140 20:12:01.792730 MCKIO_SEMI = 0
7141 20:12:01.795793 PLL_FREQ = 3068
7142 20:12:01.795869 DQ_UI_PI_RATIO = 32
7143 20:12:01.799512 CA_UI_PI_RATIO = 0
7144 20:12:01.802700 ===================================
7145 20:12:01.805791 ===================================
7146 20:12:01.809343 memory_type:LPDDR4
7147 20:12:01.812453 GP_NUM : 10
7148 20:12:01.812527 SRAM_EN : 1
7149 20:12:01.815867 MD32_EN : 0
7150 20:12:01.819201 ===================================
7151 20:12:01.822774 [ANA_INIT] >>>>>>>>>>>>>>
7152 20:12:01.822845 <<<<<< [CONFIGURE PHASE]: ANA_TX
7153 20:12:01.825666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7154 20:12:01.829210 ===================================
7155 20:12:01.832531 data_rate = 3200,PCW = 0X7600
7156 20:12:01.835798 ===================================
7157 20:12:01.839144 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7158 20:12:01.845415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 20:12:01.852231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 20:12:01.855262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7161 20:12:01.858673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7162 20:12:01.862185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7163 20:12:01.865293 [ANA_INIT] flow start
7164 20:12:01.865404 [ANA_INIT] PLL >>>>>>>>
7165 20:12:01.868696 [ANA_INIT] PLL <<<<<<<<
7166 20:12:01.871998 [ANA_INIT] MIDPI >>>>>>>>
7167 20:12:01.875116 [ANA_INIT] MIDPI <<<<<<<<
7168 20:12:01.875199 [ANA_INIT] DLL >>>>>>>>
7169 20:12:01.878538 [ANA_INIT] DLL <<<<<<<<
7170 20:12:01.878610 [ANA_INIT] flow end
7171 20:12:01.885270 ============ LP4 DIFF to SE enter ============
7172 20:12:01.888386 ============ LP4 DIFF to SE exit ============
7173 20:12:01.892033 [ANA_INIT] <<<<<<<<<<<<<
7174 20:12:01.895346 [Flow] Enable top DCM control >>>>>
7175 20:12:01.898354 [Flow] Enable top DCM control <<<<<
7176 20:12:01.901650 Enable DLL master slave shuffle
7177 20:12:01.905115 ==============================================================
7178 20:12:01.908180 Gating Mode config
7179 20:12:01.911622 ==============================================================
7180 20:12:01.914872 Config description:
7181 20:12:01.924712 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7182 20:12:01.931406 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7183 20:12:01.934854 SELPH_MODE 0: By rank 1: By Phase
7184 20:12:01.941651 ==============================================================
7185 20:12:01.944901 GAT_TRACK_EN = 1
7186 20:12:01.948092 RX_GATING_MODE = 2
7187 20:12:01.951492 RX_GATING_TRACK_MODE = 2
7188 20:12:01.954893 SELPH_MODE = 1
7189 20:12:01.957906 PICG_EARLY_EN = 1
7190 20:12:01.957978 VALID_LAT_VALUE = 1
7191 20:12:01.964701 ==============================================================
7192 20:12:01.967891 Enter into Gating configuration >>>>
7193 20:12:01.971228 Exit from Gating configuration <<<<
7194 20:12:01.974793 Enter into DVFS_PRE_config >>>>>
7195 20:12:01.984533 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7196 20:12:01.987932 Exit from DVFS_PRE_config <<<<<
7197 20:12:01.991234 Enter into PICG configuration >>>>
7198 20:12:01.994502 Exit from PICG configuration <<<<
7199 20:12:01.998173 [RX_INPUT] configuration >>>>>
7200 20:12:02.000983 [RX_INPUT] configuration <<<<<
7201 20:12:02.007769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7202 20:12:02.011068 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7203 20:12:02.017676 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 20:12:02.024444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 20:12:02.030970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 20:12:02.037393 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 20:12:02.040840 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7208 20:12:02.044136 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7209 20:12:02.047492 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7210 20:12:02.053906 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7211 20:12:02.057306 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7212 20:12:02.060819 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 20:12:02.064012 ===================================
7214 20:12:02.067270 LPDDR4 DRAM CONFIGURATION
7215 20:12:02.070627 ===================================
7216 20:12:02.070711 EX_ROW_EN[0] = 0x0
7217 20:12:02.073887 EX_ROW_EN[1] = 0x0
7218 20:12:02.077251 LP4Y_EN = 0x0
7219 20:12:02.077327 WORK_FSP = 0x1
7220 20:12:02.080620 WL = 0x5
7221 20:12:02.080691 RL = 0x5
7222 20:12:02.084027 BL = 0x2
7223 20:12:02.084103 RPST = 0x0
7224 20:12:02.087342 RD_PRE = 0x0
7225 20:12:02.087415 WR_PRE = 0x1
7226 20:12:02.090811 WR_PST = 0x1
7227 20:12:02.090884 DBI_WR = 0x0
7228 20:12:02.093739 DBI_RD = 0x0
7229 20:12:02.093809 OTF = 0x1
7230 20:12:02.097288 ===================================
7231 20:12:02.100411 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7232 20:12:02.107286 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7233 20:12:02.110527 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 20:12:02.113710 ===================================
7235 20:12:02.117299 LPDDR4 DRAM CONFIGURATION
7236 20:12:02.120554 ===================================
7237 20:12:02.120637 EX_ROW_EN[0] = 0x10
7238 20:12:02.124047 EX_ROW_EN[1] = 0x0
7239 20:12:02.124129 LP4Y_EN = 0x0
7240 20:12:02.127266 WORK_FSP = 0x1
7241 20:12:02.130312 WL = 0x5
7242 20:12:02.130393 RL = 0x5
7243 20:12:02.133682 BL = 0x2
7244 20:12:02.133763 RPST = 0x0
7245 20:12:02.137124 RD_PRE = 0x0
7246 20:12:02.137205 WR_PRE = 0x1
7247 20:12:02.140146 WR_PST = 0x1
7248 20:12:02.140227 DBI_WR = 0x0
7249 20:12:02.143646 DBI_RD = 0x0
7250 20:12:02.143728 OTF = 0x1
7251 20:12:02.146948 ===================================
7252 20:12:02.153268 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7253 20:12:02.153352 ==
7254 20:12:02.156665 Dram Type= 6, Freq= 0, CH_0, rank 0
7255 20:12:02.160067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7256 20:12:02.163434 ==
7257 20:12:02.163516 [Duty_Offset_Calibration]
7258 20:12:02.166709 B0:2 B1:0 CA:3
7259 20:12:02.166790
7260 20:12:02.169781 [DutyScan_Calibration_Flow] k_type=0
7261 20:12:02.178418
7262 20:12:02.178499 ==CLK 0==
7263 20:12:02.182017 Final CLK duty delay cell = 0
7264 20:12:02.185357 [0] MAX Duty = 5031%(X100), DQS PI = 12
7265 20:12:02.188527 [0] MIN Duty = 4907%(X100), DQS PI = 4
7266 20:12:02.188609 [0] AVG Duty = 4969%(X100)
7267 20:12:02.191798
7268 20:12:02.194969 CH0 CLK Duty spec in!! Max-Min= 124%
7269 20:12:02.198668 [DutyScan_Calibration_Flow] ====Done====
7270 20:12:02.198750
7271 20:12:02.201533 [DutyScan_Calibration_Flow] k_type=1
7272 20:12:02.218429
7273 20:12:02.218512 ==DQS 0 ==
7274 20:12:02.221599 Final DQS duty delay cell = 0
7275 20:12:02.224793 [0] MAX Duty = 5094%(X100), DQS PI = 12
7276 20:12:02.228495 [0] MIN Duty = 4875%(X100), DQS PI = 48
7277 20:12:02.231781 [0] AVG Duty = 4984%(X100)
7278 20:12:02.231863
7279 20:12:02.231927 ==DQS 1 ==
7280 20:12:02.234805 Final DQS duty delay cell = 0
7281 20:12:02.237766 [0] MAX Duty = 5156%(X100), DQS PI = 32
7282 20:12:02.241273 [0] MIN Duty = 5031%(X100), DQS PI = 14
7283 20:12:02.244325 [0] AVG Duty = 5093%(X100)
7284 20:12:02.244432
7285 20:12:02.247753 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7286 20:12:02.247835
7287 20:12:02.251094 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7288 20:12:02.254420 [DutyScan_Calibration_Flow] ====Done====
7289 20:12:02.254524
7290 20:12:02.257817 [DutyScan_Calibration_Flow] k_type=3
7291 20:12:02.276015
7292 20:12:02.276150 ==DQM 0 ==
7293 20:12:02.279584 Final DQM duty delay cell = 0
7294 20:12:02.282624 [0] MAX Duty = 5187%(X100), DQS PI = 30
7295 20:12:02.286172 [0] MIN Duty = 4844%(X100), DQS PI = 48
7296 20:12:02.289295 [0] AVG Duty = 5015%(X100)
7297 20:12:02.289401
7298 20:12:02.289517 ==DQM 1 ==
7299 20:12:02.292627 Final DQM duty delay cell = 4
7300 20:12:02.296128 [4] MAX Duty = 5187%(X100), DQS PI = 62
7301 20:12:02.299200 [4] MIN Duty = 5000%(X100), DQS PI = 12
7302 20:12:02.302507 [4] AVG Duty = 5093%(X100)
7303 20:12:02.302589
7304 20:12:02.306035 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7305 20:12:02.306117
7306 20:12:02.309226 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7307 20:12:02.312529 [DutyScan_Calibration_Flow] ====Done====
7308 20:12:02.312615
7309 20:12:02.315775 [DutyScan_Calibration_Flow] k_type=2
7310 20:12:02.332565
7311 20:12:02.332774 ==DQ 0 ==
7312 20:12:02.335535 Final DQ duty delay cell = -4
7313 20:12:02.339050 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7314 20:12:02.342357 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7315 20:12:02.345640 [-4] AVG Duty = 4938%(X100)
7316 20:12:02.345767
7317 20:12:02.345886 ==DQ 1 ==
7318 20:12:02.348979 Final DQ duty delay cell = 0
7319 20:12:02.352328 [0] MAX Duty = 5156%(X100), DQS PI = 58
7320 20:12:02.355463 [0] MIN Duty = 4969%(X100), DQS PI = 20
7321 20:12:02.359006 [0] AVG Duty = 5062%(X100)
7322 20:12:02.359106
7323 20:12:02.362317 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7324 20:12:02.362396
7325 20:12:02.365752 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7326 20:12:02.368789 [DutyScan_Calibration_Flow] ====Done====
7327 20:12:02.368894 ==
7328 20:12:02.372268 Dram Type= 6, Freq= 0, CH_1, rank 0
7329 20:12:02.375562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7330 20:12:02.375642 ==
7331 20:12:02.379088 [Duty_Offset_Calibration]
7332 20:12:02.379167 B0:1 B1:-2 CA:0
7333 20:12:02.379230
7334 20:12:02.382118 [DutyScan_Calibration_Flow] k_type=0
7335 20:12:02.393063
7336 20:12:02.393136 ==CLK 0==
7337 20:12:02.396495 Final CLK duty delay cell = 0
7338 20:12:02.399532 [0] MAX Duty = 5062%(X100), DQS PI = 20
7339 20:12:02.402866 [0] MIN Duty = 4844%(X100), DQS PI = 2
7340 20:12:02.402943 [0] AVG Duty = 4953%(X100)
7341 20:12:02.406105
7342 20:12:02.409428 CH1 CLK Duty spec in!! Max-Min= 218%
7343 20:12:02.412909 [DutyScan_Calibration_Flow] ====Done====
7344 20:12:02.412999
7345 20:12:02.416040 [DutyScan_Calibration_Flow] k_type=1
7346 20:12:02.432351
7347 20:12:02.432462 ==DQS 0 ==
7348 20:12:02.435635 Final DQS duty delay cell = 0
7349 20:12:02.438883 [0] MAX Duty = 5187%(X100), DQS PI = 22
7350 20:12:02.442367 [0] MIN Duty = 5031%(X100), DQS PI = 54
7351 20:12:02.445464 [0] AVG Duty = 5109%(X100)
7352 20:12:02.445607
7353 20:12:02.445698 ==DQS 1 ==
7354 20:12:02.449088 Final DQS duty delay cell = 0
7355 20:12:02.452312 [0] MAX Duty = 5093%(X100), DQS PI = 0
7356 20:12:02.455577 [0] MIN Duty = 4844%(X100), DQS PI = 24
7357 20:12:02.458945 [0] AVG Duty = 4968%(X100)
7358 20:12:02.459027
7359 20:12:02.461950 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7360 20:12:02.462022
7361 20:12:02.465488 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7362 20:12:02.468879 [DutyScan_Calibration_Flow] ====Done====
7363 20:12:02.468978
7364 20:12:02.471919 [DutyScan_Calibration_Flow] k_type=3
7365 20:12:02.489272
7366 20:12:02.489372 ==DQM 0 ==
7367 20:12:02.492393 Final DQM duty delay cell = 0
7368 20:12:02.495844 [0] MAX Duty = 5031%(X100), DQS PI = 24
7369 20:12:02.498978 [0] MIN Duty = 4813%(X100), DQS PI = 56
7370 20:12:02.502378 [0] AVG Duty = 4922%(X100)
7371 20:12:02.502475
7372 20:12:02.502573 ==DQM 1 ==
7373 20:12:02.505616 Final DQM duty delay cell = 0
7374 20:12:02.508901 [0] MAX Duty = 5094%(X100), DQS PI = 36
7375 20:12:02.512271 [0] MIN Duty = 4875%(X100), DQS PI = 26
7376 20:12:02.515466 [0] AVG Duty = 4984%(X100)
7377 20:12:02.515541
7378 20:12:02.519131 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7379 20:12:02.519208
7380 20:12:02.522010 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7381 20:12:02.525675 [DutyScan_Calibration_Flow] ====Done====
7382 20:12:02.525743
7383 20:12:02.528699 [DutyScan_Calibration_Flow] k_type=2
7384 20:12:02.546056
7385 20:12:02.546141 ==DQ 0 ==
7386 20:12:02.549207 Final DQ duty delay cell = 0
7387 20:12:02.553386 [0] MAX Duty = 5093%(X100), DQS PI = 22
7388 20:12:02.556637 [0] MIN Duty = 4907%(X100), DQS PI = 62
7389 20:12:02.557118 [0] AVG Duty = 5000%(X100)
7390 20:12:02.557528
7391 20:12:02.559812 ==DQ 1 ==
7392 20:12:02.563042 Final DQ duty delay cell = 0
7393 20:12:02.566518 [0] MAX Duty = 5125%(X100), DQS PI = 34
7394 20:12:02.569898 [0] MIN Duty = 4938%(X100), DQS PI = 24
7395 20:12:02.570384 [0] AVG Duty = 5031%(X100)
7396 20:12:02.570746
7397 20:12:02.573119 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7398 20:12:02.576524
7399 20:12:02.579645 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7400 20:12:02.582802 [DutyScan_Calibration_Flow] ====Done====
7401 20:12:02.586290 nWR fixed to 30
7402 20:12:02.586735 [ModeRegInit_LP4] CH0 RK0
7403 20:12:02.589615 [ModeRegInit_LP4] CH0 RK1
7404 20:12:02.592803 [ModeRegInit_LP4] CH1 RK0
7405 20:12:02.595994 [ModeRegInit_LP4] CH1 RK1
7406 20:12:02.596440 match AC timing 5
7407 20:12:02.599375 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7408 20:12:02.606346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7409 20:12:02.609537 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7410 20:12:02.616205 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7411 20:12:02.619136 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7412 20:12:02.619581 [MiockJmeterHQA]
7413 20:12:02.619936
7414 20:12:02.622668 [DramcMiockJmeter] u1RxGatingPI = 0
7415 20:12:02.625808 0 : 4260, 4032
7416 20:12:02.626259 4 : 4257, 4032
7417 20:12:02.629623 8 : 4255, 4029
7418 20:12:02.630073 12 : 4255, 4029
7419 20:12:02.630441 16 : 4370, 4142
7420 20:12:02.632569 20 : 4365, 4140
7421 20:12:02.633029 24 : 4255, 4030
7422 20:12:02.635961 28 : 4363, 4140
7423 20:12:02.636405 32 : 4255, 4029
7424 20:12:02.639231 36 : 4252, 4030
7425 20:12:02.639685 40 : 4252, 4029
7426 20:12:02.642306 44 : 4366, 4139
7427 20:12:02.642762 48 : 4363, 4140
7428 20:12:02.643130 52 : 4255, 4029
7429 20:12:02.645589 56 : 4255, 4030
7430 20:12:02.646040 60 : 4363, 4140
7431 20:12:02.649003 64 : 4365, 4140
7432 20:12:02.649452 68 : 4253, 4027
7433 20:12:02.652674 72 : 4253, 4029
7434 20:12:02.653124 76 : 4252, 4029
7435 20:12:02.653525 80 : 4363, 4140
7436 20:12:02.655626 84 : 4253, 4030
7437 20:12:02.656113 88 : 4252, 4030
7438 20:12:02.659203 92 : 4365, 4140
7439 20:12:02.659652 96 : 4253, 4029
7440 20:12:02.662361 100 : 4363, 4140
7441 20:12:02.662819 104 : 4361, 3772
7442 20:12:02.665523 108 : 4250, 0
7443 20:12:02.665974 112 : 4252, 0
7444 20:12:02.666340 116 : 4255, 0
7445 20:12:02.668937 120 : 4363, 0
7446 20:12:02.669381 124 : 4366, 0
7447 20:12:02.672216 128 : 4366, 0
7448 20:12:02.672671 132 : 4253, 0
7449 20:12:02.673038 136 : 4253, 0
7450 20:12:02.675498 140 : 4368, 0
7451 20:12:02.676047 144 : 4252, 0
7452 20:12:02.679077 148 : 4252, 0
7453 20:12:02.679505 152 : 4363, 0
7454 20:12:02.679842 156 : 4252, 0
7455 20:12:02.682111 160 : 4363, 0
7456 20:12:02.682533 164 : 4252, 0
7457 20:12:02.682872 168 : 4363, 0
7458 20:12:02.685376 172 : 4253, 0
7459 20:12:02.685970 176 : 4252, 0
7460 20:12:02.688785 180 : 4365, 0
7461 20:12:02.689206 184 : 4254, 0
7462 20:12:02.689574 188 : 4252, 0
7463 20:12:02.692035 192 : 4252, 0
7464 20:12:02.692473 196 : 4252, 0
7465 20:12:02.695564 200 : 4252, 0
7466 20:12:02.695985 204 : 4363, 0
7467 20:12:02.696323 208 : 4253, 0
7468 20:12:02.698756 212 : 4363, 0
7469 20:12:02.698838 216 : 4363, 0
7470 20:12:02.701860 220 : 4250, 0
7471 20:12:02.701942 224 : 4253, 0
7472 20:12:02.702008 228 : 4366, 0
7473 20:12:02.705290 232 : 4252, 0
7474 20:12:02.705373 236 : 4363, 1153
7475 20:12:02.708295 240 : 4252, 4030
7476 20:12:02.708383 244 : 4363, 4140
7477 20:12:02.711749 248 : 4252, 4029
7478 20:12:02.711844 252 : 4363, 4140
7479 20:12:02.714895 256 : 4252, 4029
7480 20:12:02.714991 260 : 4250, 4027
7481 20:12:02.715066 264 : 4252, 4029
7482 20:12:02.718272 268 : 4363, 4139
7483 20:12:02.718375 272 : 4253, 4029
7484 20:12:02.721722 276 : 4252, 4030
7485 20:12:02.721835 280 : 4363, 4140
7486 20:12:02.724845 284 : 4252, 4029
7487 20:12:02.724957 288 : 4255, 4029
7488 20:12:02.728405 292 : 4258, 4032
7489 20:12:02.728529 296 : 4253, 4029
7490 20:12:02.731831 300 : 4253, 4030
7491 20:12:02.731967 304 : 4253, 4029
7492 20:12:02.735089 308 : 4257, 4032
7493 20:12:02.735225 312 : 4253, 4029
7494 20:12:02.738202 316 : 4365, 4140
7495 20:12:02.738356 320 : 4252, 4030
7496 20:12:02.738479 324 : 4250, 4027
7497 20:12:02.741431 328 : 4254, 4030
7498 20:12:02.741620 332 : 4252, 4029
7499 20:12:02.744793 336 : 4364, 4140
7500 20:12:02.744991 340 : 4253, 4029
7501 20:12:02.748331 344 : 4363, 4140
7502 20:12:02.748536 348 : 4255, 4029
7503 20:12:02.751618 352 : 4363, 4128
7504 20:12:02.751864 356 : 4252, 2650
7505 20:12:02.755115 360 : 4255, 3
7506 20:12:02.755359
7507 20:12:02.755552 MIOCK jitter meter ch=0
7508 20:12:02.755732
7509 20:12:02.758565 1T = (360-108) = 252 dly cells
7510 20:12:02.765543 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7511 20:12:02.765933 ==
7512 20:12:02.768637 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 20:12:02.772039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 20:12:02.772464 ==
7515 20:12:02.778594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 20:12:02.781891 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 20:12:02.785088 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 20:12:02.791857 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 20:12:02.801520 [CA 0] Center 44 (14~75) winsize 62
7520 20:12:02.804659 [CA 1] Center 43 (13~74) winsize 62
7521 20:12:02.808121 [CA 2] Center 39 (11~68) winsize 58
7522 20:12:02.811086 [CA 3] Center 39 (10~68) winsize 59
7523 20:12:02.814652 [CA 4] Center 37 (7~67) winsize 61
7524 20:12:02.818029 [CA 5] Center 36 (7~66) winsize 60
7525 20:12:02.818453
7526 20:12:02.821000 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 20:12:02.821423
7528 20:12:02.827658 [CATrainingPosCal] consider 1 rank data
7529 20:12:02.828082 u2DelayCellTimex100 = 258/100 ps
7530 20:12:02.834541 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7531 20:12:02.837870 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7532 20:12:02.841205 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7533 20:12:02.844657 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7534 20:12:02.847753 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7535 20:12:02.851094 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7536 20:12:02.851641
7537 20:12:02.854521 CA PerBit enable=1, Macro0, CA PI delay=36
7538 20:12:02.854939
7539 20:12:02.858010 [CBTSetCACLKResult] CA Dly = 36
7540 20:12:02.861042 CS Dly: 11 (0~42)
7541 20:12:02.864390 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 20:12:02.867573 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 20:12:02.867992 ==
7544 20:12:02.870951 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 20:12:02.877721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 20:12:02.878139 ==
7547 20:12:02.880924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 20:12:02.887400 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 20:12:02.890871 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 20:12:02.897325 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 20:12:02.905307 [CA 0] Center 43 (13~74) winsize 62
7552 20:12:02.908531 [CA 1] Center 43 (13~74) winsize 62
7553 20:12:02.911649 [CA 2] Center 39 (10~68) winsize 59
7554 20:12:02.915255 [CA 3] Center 39 (10~68) winsize 59
7555 20:12:02.918268 [CA 4] Center 36 (6~66) winsize 61
7556 20:12:02.922008 [CA 5] Center 36 (6~66) winsize 61
7557 20:12:02.922434
7558 20:12:02.925037 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 20:12:02.925628
7560 20:12:02.931620 [CATrainingPosCal] consider 2 rank data
7561 20:12:02.932044 u2DelayCellTimex100 = 258/100 ps
7562 20:12:02.938509 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7563 20:12:02.941712 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7564 20:12:02.945179 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7565 20:12:02.948313 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7566 20:12:02.951744 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7567 20:12:02.955059 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7568 20:12:02.955478
7569 20:12:02.958154 CA PerBit enable=1, Macro0, CA PI delay=36
7570 20:12:02.958722
7571 20:12:02.961786 [CBTSetCACLKResult] CA Dly = 36
7572 20:12:02.964763 CS Dly: 11 (0~43)
7573 20:12:02.968292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 20:12:02.971601 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 20:12:02.972023
7576 20:12:02.974751 ----->DramcWriteLeveling(PI) begin...
7577 20:12:02.975178 ==
7578 20:12:02.978267 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 20:12:02.984652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 20:12:02.985076 ==
7581 20:12:02.988184 Write leveling (Byte 0): 35 => 35
7582 20:12:02.991284 Write leveling (Byte 1): 27 => 27
7583 20:12:02.994950 DramcWriteLeveling(PI) end<-----
7584 20:12:02.995475
7585 20:12:02.995813 ==
7586 20:12:02.998200 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 20:12:03.001294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 20:12:03.001758 ==
7589 20:12:03.004781 [Gating] SW mode calibration
7590 20:12:03.011334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 20:12:03.014633 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 20:12:03.021361 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 20:12:03.024506 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 20:12:03.027578 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 20:12:03.034562 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 20:12:03.037801 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7597 20:12:03.040880 1 4 20 | B1->B0 | 2524 3434 | 1 1 | (1 1) (1 1)
7598 20:12:03.047674 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7599 20:12:03.051259 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 20:12:03.054581 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 20:12:03.061090 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 20:12:03.064280 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 20:12:03.067681 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 20:12:03.074025 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7605 20:12:03.077553 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7606 20:12:03.080548 1 5 24 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
7607 20:12:03.087211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 20:12:03.090511 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 20:12:03.093638 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 20:12:03.100609 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 20:12:03.103902 1 6 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7612 20:12:03.107166 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
7613 20:12:03.113590 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7614 20:12:03.117032 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7615 20:12:03.120516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 20:12:03.127043 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 20:12:03.130613 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 20:12:03.133794 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 20:12:03.140158 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 20:12:03.143622 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7621 20:12:03.146879 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 20:12:03.153426 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7623 20:12:03.156725 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 20:12:03.160030 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 20:12:03.166565 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 20:12:03.170090 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 20:12:03.173446 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 20:12:03.179919 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 20:12:03.183402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 20:12:03.186839 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 20:12:03.193279 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 20:12:03.196493 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 20:12:03.199883 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 20:12:03.206463 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 20:12:03.209903 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 20:12:03.213315 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7637 20:12:03.220000 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 20:12:03.220418 Total UI for P1: 0, mck2ui 16
7639 20:12:03.223125 best dqsien dly found for B0: ( 1, 9, 16)
7640 20:12:03.229586 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 20:12:03.233128 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 20:12:03.236564 Total UI for P1: 0, mck2ui 16
7643 20:12:03.239648 best dqsien dly found for B1: ( 1, 9, 22)
7644 20:12:03.243092 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7645 20:12:03.246504 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7646 20:12:03.246921
7647 20:12:03.249510 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7648 20:12:03.256341 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7649 20:12:03.256764 [Gating] SW calibration Done
7650 20:12:03.258982 ==
7651 20:12:03.262308 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 20:12:03.265772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 20:12:03.265854 ==
7654 20:12:03.265918 RX Vref Scan: 0
7655 20:12:03.265980
7656 20:12:03.269098 RX Vref 0 -> 0, step: 1
7657 20:12:03.269179
7658 20:12:03.272193 RX Delay 0 -> 252, step: 8
7659 20:12:03.275651 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7660 20:12:03.279065 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7661 20:12:03.282114 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7662 20:12:03.289102 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7663 20:12:03.292185 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7664 20:12:03.295439 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7665 20:12:03.298798 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7666 20:12:03.302192 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7667 20:12:03.308590 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7668 20:12:03.311907 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7669 20:12:03.315394 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7670 20:12:03.318563 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7671 20:12:03.321896 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7672 20:12:03.328600 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7673 20:12:03.331864 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7674 20:12:03.335206 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7675 20:12:03.335288 ==
7676 20:12:03.338245 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 20:12:03.341731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 20:12:03.344989 ==
7679 20:12:03.345070 DQS Delay:
7680 20:12:03.345134 DQS0 = 0, DQS1 = 0
7681 20:12:03.348421 DQM Delay:
7682 20:12:03.348502 DQM0 = 127, DQM1 = 124
7683 20:12:03.351729 DQ Delay:
7684 20:12:03.354856 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7685 20:12:03.358614 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7686 20:12:03.361635 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7687 20:12:03.364913 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7688 20:12:03.365014
7689 20:12:03.365094
7690 20:12:03.365169 ==
7691 20:12:03.368207 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 20:12:03.371795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 20:12:03.371917 ==
7694 20:12:03.374720
7695 20:12:03.374841
7696 20:12:03.374937 TX Vref Scan disable
7697 20:12:03.378459 == TX Byte 0 ==
7698 20:12:03.381667 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7699 20:12:03.384969 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7700 20:12:03.388495 == TX Byte 1 ==
7701 20:12:03.391670 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7702 20:12:03.395222 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7703 20:12:03.395422 ==
7704 20:12:03.398365 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 20:12:03.405188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 20:12:03.405501 ==
7707 20:12:03.417726
7708 20:12:03.421045 TX Vref early break, caculate TX vref
7709 20:12:03.424133 TX Vref=16, minBit 8, minWin=21, winSum=357
7710 20:12:03.427652 TX Vref=18, minBit 11, minWin=21, winSum=367
7711 20:12:03.430813 TX Vref=20, minBit 8, minWin=22, winSum=379
7712 20:12:03.434042 TX Vref=22, minBit 0, minWin=24, winSum=390
7713 20:12:03.437234 TX Vref=24, minBit 4, minWin=24, winSum=396
7714 20:12:03.443837 TX Vref=26, minBit 8, minWin=24, winSum=404
7715 20:12:03.447423 TX Vref=28, minBit 8, minWin=24, winSum=403
7716 20:12:03.450837 TX Vref=30, minBit 8, minWin=23, winSum=395
7717 20:12:03.453920 TX Vref=32, minBit 8, minWin=23, winSum=388
7718 20:12:03.457528 TX Vref=34, minBit 8, minWin=22, winSum=379
7719 20:12:03.464046 [TxChooseVref] Worse bit 8, Min win 24, Win sum 404, Final Vref 26
7720 20:12:03.464466
7721 20:12:03.467362 Final TX Range 0 Vref 26
7722 20:12:03.467781
7723 20:12:03.468116 ==
7724 20:12:03.470638 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 20:12:03.473760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 20:12:03.474180 ==
7727 20:12:03.474517
7728 20:12:03.474828
7729 20:12:03.477058 TX Vref Scan disable
7730 20:12:03.483554 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7731 20:12:03.483972 == TX Byte 0 ==
7732 20:12:03.486785 u2DelayCellOfst[0]=11 cells (3 PI)
7733 20:12:03.490166 u2DelayCellOfst[1]=15 cells (4 PI)
7734 20:12:03.493611 u2DelayCellOfst[2]=11 cells (3 PI)
7735 20:12:03.496884 u2DelayCellOfst[3]=11 cells (3 PI)
7736 20:12:03.500153 u2DelayCellOfst[4]=7 cells (2 PI)
7737 20:12:03.503532 u2DelayCellOfst[5]=0 cells (0 PI)
7738 20:12:03.507040 u2DelayCellOfst[6]=18 cells (5 PI)
7739 20:12:03.510339 u2DelayCellOfst[7]=15 cells (4 PI)
7740 20:12:03.513631 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7741 20:12:03.516860 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7742 20:12:03.520101 == TX Byte 1 ==
7743 20:12:03.523638 u2DelayCellOfst[8]=0 cells (0 PI)
7744 20:12:03.527023 u2DelayCellOfst[9]=0 cells (0 PI)
7745 20:12:03.527501 u2DelayCellOfst[10]=7 cells (2 PI)
7746 20:12:03.530005 u2DelayCellOfst[11]=3 cells (1 PI)
7747 20:12:03.533694 u2DelayCellOfst[12]=11 cells (3 PI)
7748 20:12:03.536971 u2DelayCellOfst[13]=11 cells (3 PI)
7749 20:12:03.540124 u2DelayCellOfst[14]=15 cells (4 PI)
7750 20:12:03.543711 u2DelayCellOfst[15]=11 cells (3 PI)
7751 20:12:03.546832 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7752 20:12:03.553422 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7753 20:12:03.554026 DramC Write-DBI on
7754 20:12:03.554475 ==
7755 20:12:03.556965 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 20:12:03.563358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 20:12:03.563785 ==
7758 20:12:03.564123
7759 20:12:03.564441
7760 20:12:03.564770 TX Vref Scan disable
7761 20:12:03.567344 == TX Byte 0 ==
7762 20:12:03.570605 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7763 20:12:03.574175 == TX Byte 1 ==
7764 20:12:03.577211 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7765 20:12:03.580660 DramC Write-DBI off
7766 20:12:03.581077
7767 20:12:03.581415 [DATLAT]
7768 20:12:03.581790 Freq=1600, CH0 RK0
7769 20:12:03.582106
7770 20:12:03.584053 DATLAT Default: 0xf
7771 20:12:03.584469 0, 0xFFFF, sum = 0
7772 20:12:03.587459 1, 0xFFFF, sum = 0
7773 20:12:03.590705 2, 0xFFFF, sum = 0
7774 20:12:03.591129 3, 0xFFFF, sum = 0
7775 20:12:03.593736 4, 0xFFFF, sum = 0
7776 20:12:03.594159 5, 0xFFFF, sum = 0
7777 20:12:03.597068 6, 0xFFFF, sum = 0
7778 20:12:03.597527 7, 0xFFFF, sum = 0
7779 20:12:03.600506 8, 0xFFFF, sum = 0
7780 20:12:03.600929 9, 0xFFFF, sum = 0
7781 20:12:03.604027 10, 0xFFFF, sum = 0
7782 20:12:03.604453 11, 0xFFFF, sum = 0
7783 20:12:03.606953 12, 0xFFFF, sum = 0
7784 20:12:03.607379 13, 0xCFFF, sum = 0
7785 20:12:03.610442 14, 0x0, sum = 1
7786 20:12:03.611072 15, 0x0, sum = 2
7787 20:12:03.613594 16, 0x0, sum = 3
7788 20:12:03.614265 17, 0x0, sum = 4
7789 20:12:03.617107 best_step = 15
7790 20:12:03.617568
7791 20:12:03.617914 ==
7792 20:12:03.620280 Dram Type= 6, Freq= 0, CH_0, rank 0
7793 20:12:03.623511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7794 20:12:03.623934 ==
7795 20:12:03.626812 RX Vref Scan: 1
7796 20:12:03.627394
7797 20:12:03.627754 Set Vref Range= 24 -> 127
7798 20:12:03.628077
7799 20:12:03.629951 RX Vref 24 -> 127, step: 1
7800 20:12:03.630370
7801 20:12:03.633403 RX Delay 11 -> 252, step: 4
7802 20:12:03.633863
7803 20:12:03.636763 Set Vref, RX VrefLevel [Byte0]: 24
7804 20:12:03.639844 [Byte1]: 24
7805 20:12:03.640271
7806 20:12:03.643605 Set Vref, RX VrefLevel [Byte0]: 25
7807 20:12:03.646603 [Byte1]: 25
7808 20:12:03.649954
7809 20:12:03.650541 Set Vref, RX VrefLevel [Byte0]: 26
7810 20:12:03.653454 [Byte1]: 26
7811 20:12:03.657722
7812 20:12:03.658311 Set Vref, RX VrefLevel [Byte0]: 27
7813 20:12:03.661007 [Byte1]: 27
7814 20:12:03.665270
7815 20:12:03.665750 Set Vref, RX VrefLevel [Byte0]: 28
7816 20:12:03.668468 [Byte1]: 28
7817 20:12:03.673074
7818 20:12:03.673539 Set Vref, RX VrefLevel [Byte0]: 29
7819 20:12:03.676397 [Byte1]: 29
7820 20:12:03.680520
7821 20:12:03.680935 Set Vref, RX VrefLevel [Byte0]: 30
7822 20:12:03.683701 [Byte1]: 30
7823 20:12:03.688510
7824 20:12:03.688926 Set Vref, RX VrefLevel [Byte0]: 31
7825 20:12:03.691638 [Byte1]: 31
7826 20:12:03.696116
7827 20:12:03.696534 Set Vref, RX VrefLevel [Byte0]: 32
7828 20:12:03.699015 [Byte1]: 32
7829 20:12:03.703536
7830 20:12:03.703949 Set Vref, RX VrefLevel [Byte0]: 33
7831 20:12:03.706697 [Byte1]: 33
7832 20:12:03.711156
7833 20:12:03.711570 Set Vref, RX VrefLevel [Byte0]: 34
7834 20:12:03.714270 [Byte1]: 34
7835 20:12:03.718624
7836 20:12:03.719127 Set Vref, RX VrefLevel [Byte0]: 35
7837 20:12:03.722142 [Byte1]: 35
7838 20:12:03.726368
7839 20:12:03.726964 Set Vref, RX VrefLevel [Byte0]: 36
7840 20:12:03.730182 [Byte1]: 36
7841 20:12:03.733928
7842 20:12:03.734514 Set Vref, RX VrefLevel [Byte0]: 37
7843 20:12:03.737194 [Byte1]: 37
7844 20:12:03.741746
7845 20:12:03.742163 Set Vref, RX VrefLevel [Byte0]: 38
7846 20:12:03.744899 [Byte1]: 38
7847 20:12:03.749197
7848 20:12:03.749658 Set Vref, RX VrefLevel [Byte0]: 39
7849 20:12:03.752407 [Byte1]: 39
7850 20:12:03.756574
7851 20:12:03.756989 Set Vref, RX VrefLevel [Byte0]: 40
7852 20:12:03.760016 [Byte1]: 40
7853 20:12:03.764192
7854 20:12:03.764606 Set Vref, RX VrefLevel [Byte0]: 41
7855 20:12:03.767663 [Byte1]: 41
7856 20:12:03.771577
7857 20:12:03.771658 Set Vref, RX VrefLevel [Byte0]: 42
7858 20:12:03.774902 [Byte1]: 42
7859 20:12:03.779229
7860 20:12:03.779310 Set Vref, RX VrefLevel [Byte0]: 43
7861 20:12:03.782273 [Byte1]: 43
7862 20:12:03.786897
7863 20:12:03.786977 Set Vref, RX VrefLevel [Byte0]: 44
7864 20:12:03.790427 [Byte1]: 44
7865 20:12:03.794283
7866 20:12:03.794363 Set Vref, RX VrefLevel [Byte0]: 45
7867 20:12:03.797728 [Byte1]: 45
7868 20:12:03.802131
7869 20:12:03.802212 Set Vref, RX VrefLevel [Byte0]: 46
7870 20:12:03.805270 [Byte1]: 46
7871 20:12:03.809811
7872 20:12:03.809892 Set Vref, RX VrefLevel [Byte0]: 47
7873 20:12:03.812799 [Byte1]: 47
7874 20:12:03.817302
7875 20:12:03.817383 Set Vref, RX VrefLevel [Byte0]: 48
7876 20:12:03.823707 [Byte1]: 48
7877 20:12:03.823788
7878 20:12:03.826938 Set Vref, RX VrefLevel [Byte0]: 49
7879 20:12:03.830406 [Byte1]: 49
7880 20:12:03.830487
7881 20:12:03.833603 Set Vref, RX VrefLevel [Byte0]: 50
7882 20:12:03.836975 [Byte1]: 50
7883 20:12:03.840275
7884 20:12:03.840356 Set Vref, RX VrefLevel [Byte0]: 51
7885 20:12:03.843451 [Byte1]: 51
7886 20:12:03.847673
7887 20:12:03.847754 Set Vref, RX VrefLevel [Byte0]: 52
7888 20:12:03.850997 [Byte1]: 52
7889 20:12:03.855357
7890 20:12:03.855438 Set Vref, RX VrefLevel [Byte0]: 53
7891 20:12:03.858409 [Byte1]: 53
7892 20:12:03.862819
7893 20:12:03.862900 Set Vref, RX VrefLevel [Byte0]: 54
7894 20:12:03.866325 [Byte1]: 54
7895 20:12:03.870605
7896 20:12:03.870685 Set Vref, RX VrefLevel [Byte0]: 55
7897 20:12:03.873682 [Byte1]: 55
7898 20:12:03.878183
7899 20:12:03.878263 Set Vref, RX VrefLevel [Byte0]: 56
7900 20:12:03.881393 [Byte1]: 56
7901 20:12:03.885789
7902 20:12:03.885870 Set Vref, RX VrefLevel [Byte0]: 57
7903 20:12:03.889098 [Byte1]: 57
7904 20:12:03.893373
7905 20:12:03.893454 Set Vref, RX VrefLevel [Byte0]: 58
7906 20:12:03.896440 [Byte1]: 58
7907 20:12:03.900816
7908 20:12:03.900897 Set Vref, RX VrefLevel [Byte0]: 59
7909 20:12:03.904333 [Byte1]: 59
7910 20:12:03.908577
7911 20:12:03.908657 Set Vref, RX VrefLevel [Byte0]: 60
7912 20:12:03.911731 [Byte1]: 60
7913 20:12:03.916262
7914 20:12:03.916342 Set Vref, RX VrefLevel [Byte0]: 61
7915 20:12:03.919616 [Byte1]: 61
7916 20:12:03.923672
7917 20:12:03.923753 Set Vref, RX VrefLevel [Byte0]: 62
7918 20:12:03.927291 [Byte1]: 62
7919 20:12:03.931204
7920 20:12:03.931285 Set Vref, RX VrefLevel [Byte0]: 63
7921 20:12:03.934824 [Byte1]: 63
7922 20:12:03.938987
7923 20:12:03.939067 Set Vref, RX VrefLevel [Byte0]: 64
7924 20:12:03.942247 [Byte1]: 64
7925 20:12:03.946702
7926 20:12:03.946782 Set Vref, RX VrefLevel [Byte0]: 65
7927 20:12:03.950011 [Byte1]: 65
7928 20:12:03.954239
7929 20:12:03.954320 Set Vref, RX VrefLevel [Byte0]: 66
7930 20:12:03.957399 [Byte1]: 66
7931 20:12:03.962125
7932 20:12:03.962205 Set Vref, RX VrefLevel [Byte0]: 67
7933 20:12:03.965140 [Byte1]: 67
7934 20:12:03.969461
7935 20:12:03.969552 Set Vref, RX VrefLevel [Byte0]: 68
7936 20:12:03.972807 [Byte1]: 68
7937 20:12:03.977148
7938 20:12:03.977229 Set Vref, RX VrefLevel [Byte0]: 69
7939 20:12:03.980535 [Byte1]: 69
7940 20:12:03.984693
7941 20:12:03.984773 Set Vref, RX VrefLevel [Byte0]: 70
7942 20:12:03.987940 [Byte1]: 70
7943 20:12:03.992143
7944 20:12:03.992223 Set Vref, RX VrefLevel [Byte0]: 71
7945 20:12:03.995619 [Byte1]: 71
7946 20:12:03.999915
7947 20:12:03.999995 Set Vref, RX VrefLevel [Byte0]: 72
7948 20:12:04.003148 [Byte1]: 72
7949 20:12:04.007767
7950 20:12:04.007847 Set Vref, RX VrefLevel [Byte0]: 73
7951 20:12:04.010897 [Byte1]: 73
7952 20:12:04.015235
7953 20:12:04.015329 Set Vref, RX VrefLevel [Byte0]: 74
7954 20:12:04.021671 [Byte1]: 74
7955 20:12:04.021752
7956 20:12:04.025080 Set Vref, RX VrefLevel [Byte0]: 75
7957 20:12:04.028175 [Byte1]: 75
7958 20:12:04.028256
7959 20:12:04.031551 Final RX Vref Byte 0 = 65 to rank0
7960 20:12:04.035180 Final RX Vref Byte 1 = 57 to rank0
7961 20:12:04.038091 Final RX Vref Byte 0 = 65 to rank1
7962 20:12:04.041673 Final RX Vref Byte 1 = 57 to rank1==
7963 20:12:04.045017 Dram Type= 6, Freq= 0, CH_0, rank 0
7964 20:12:04.048313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 20:12:04.048395 ==
7966 20:12:04.051605 DQS Delay:
7967 20:12:04.051686 DQS0 = 0, DQS1 = 0
7968 20:12:04.051751 DQM Delay:
7969 20:12:04.054654 DQM0 = 126, DQM1 = 119
7970 20:12:04.054734 DQ Delay:
7971 20:12:04.058385 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7972 20:12:04.061549 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7973 20:12:04.067910 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =112
7974 20:12:04.071463 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7975 20:12:04.071544
7976 20:12:04.071609
7977 20:12:04.071668
7978 20:12:04.074656 [DramC_TX_OE_Calibration] TA2
7979 20:12:04.077866 Original DQ_B0 (3 6) =30, OEN = 27
7980 20:12:04.081269 Original DQ_B1 (3 6) =30, OEN = 27
7981 20:12:04.081351 24, 0x0, End_B0=24 End_B1=24
7982 20:12:04.084619 25, 0x0, End_B0=25 End_B1=25
7983 20:12:04.087709 26, 0x0, End_B0=26 End_B1=26
7984 20:12:04.091274 27, 0x0, End_B0=27 End_B1=27
7985 20:12:04.091357 28, 0x0, End_B0=28 End_B1=28
7986 20:12:04.094330 29, 0x0, End_B0=29 End_B1=29
7987 20:12:04.097646 30, 0x0, End_B0=30 End_B1=30
7988 20:12:04.100846 31, 0x4545, End_B0=30 End_B1=30
7989 20:12:04.104305 Byte0 end_step=30 best_step=27
7990 20:12:04.107482 Byte1 end_step=30 best_step=27
7991 20:12:04.107563 Byte0 TX OE(2T, 0.5T) = (3, 3)
7992 20:12:04.110854 Byte1 TX OE(2T, 0.5T) = (3, 3)
7993 20:12:04.110935
7994 20:12:04.110999
7995 20:12:04.120917 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7996 20:12:04.123976 CH0 RK0: MR19=303, MR18=1615
7997 20:12:04.127559 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
7998 20:12:04.130554
7999 20:12:04.133972 ----->DramcWriteLeveling(PI) begin...
8000 20:12:04.134055 ==
8001 20:12:04.137409 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 20:12:04.140481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 20:12:04.140562 ==
8004 20:12:04.143858 Write leveling (Byte 0): 34 => 34
8005 20:12:04.147161 Write leveling (Byte 1): 26 => 26
8006 20:12:04.150609 DramcWriteLeveling(PI) end<-----
8007 20:12:04.150689
8008 20:12:04.150753 ==
8009 20:12:04.153612 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 20:12:04.157184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 20:12:04.157265 ==
8012 20:12:04.160428 [Gating] SW mode calibration
8013 20:12:04.167236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8014 20:12:04.173756 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8015 20:12:04.177361 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 20:12:04.180238 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 20:12:04.186993 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 20:12:04.190466 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8019 20:12:04.193720 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8020 20:12:04.200554 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 20:12:04.203568 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 20:12:04.207167 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 20:12:04.213638 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 20:12:04.216862 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 20:12:04.220208 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8026 20:12:04.223619 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8027 20:12:04.230165 1 5 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8028 20:12:04.233633 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8029 20:12:04.240169 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 20:12:04.243250 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 20:12:04.246677 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 20:12:04.249824 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 20:12:04.256454 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8034 20:12:04.259999 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8035 20:12:04.263173 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8036 20:12:04.269786 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 20:12:04.273378 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 20:12:04.276233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 20:12:04.283123 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 20:12:04.286168 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 20:12:04.289828 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 20:12:04.296515 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8043 20:12:04.299676 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 20:12:04.302801 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 20:12:04.309466 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8046 20:12:04.313128 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 20:12:04.316209 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 20:12:04.322849 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 20:12:04.326191 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 20:12:04.329510 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 20:12:04.336181 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 20:12:04.339204 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 20:12:04.342833 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 20:12:04.349457 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 20:12:04.352683 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 20:12:04.355963 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 20:12:04.362443 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 20:12:04.365750 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8059 20:12:04.369104 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 20:12:04.372507 Total UI for P1: 0, mck2ui 16
8061 20:12:04.375997 best dqsien dly found for B0: ( 1, 9, 12)
8062 20:12:04.382404 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8063 20:12:04.385905 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 20:12:04.388949 Total UI for P1: 0, mck2ui 16
8065 20:12:04.392301 best dqsien dly found for B1: ( 1, 9, 18)
8066 20:12:04.395641 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8067 20:12:04.399148 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8068 20:12:04.399229
8069 20:12:04.402363 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8070 20:12:04.405859 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8071 20:12:04.408979 [Gating] SW calibration Done
8072 20:12:04.409060 ==
8073 20:12:04.412199 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 20:12:04.415789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 20:12:04.419152 ==
8076 20:12:04.419233 RX Vref Scan: 0
8077 20:12:04.419297
8078 20:12:04.422252 RX Vref 0 -> 0, step: 1
8079 20:12:04.422332
8080 20:12:04.422396 RX Delay 0 -> 252, step: 8
8081 20:12:04.429177 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8082 20:12:04.432379 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8083 20:12:04.435474 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8084 20:12:04.438884 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8085 20:12:04.442165 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8086 20:12:04.448841 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8087 20:12:04.452267 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8088 20:12:04.455563 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8089 20:12:04.458852 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8090 20:12:04.462282 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8091 20:12:04.468859 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8092 20:12:04.472120 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8093 20:12:04.475450 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8094 20:12:04.478591 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8095 20:12:04.485382 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8096 20:12:04.488618 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8097 20:12:04.488699 ==
8098 20:12:04.492089 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 20:12:04.495332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 20:12:04.495414 ==
8101 20:12:04.498308 DQS Delay:
8102 20:12:04.498389 DQS0 = 0, DQS1 = 0
8103 20:12:04.498453 DQM Delay:
8104 20:12:04.501915 DQM0 = 127, DQM1 = 121
8105 20:12:04.501996 DQ Delay:
8106 20:12:04.505165 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8107 20:12:04.508487 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8108 20:12:04.511881 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8109 20:12:04.518529 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8110 20:12:04.518611
8111 20:12:04.518676
8112 20:12:04.518736 ==
8113 20:12:04.522068 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 20:12:04.525049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 20:12:04.525131 ==
8116 20:12:04.525195
8117 20:12:04.525256
8118 20:12:04.528494 TX Vref Scan disable
8119 20:12:04.528575 == TX Byte 0 ==
8120 20:12:04.535126 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8121 20:12:04.538504 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8122 20:12:04.538585 == TX Byte 1 ==
8123 20:12:04.545138 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8124 20:12:04.548182 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8125 20:12:04.548264 ==
8126 20:12:04.551464 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 20:12:04.554861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 20:12:04.554942 ==
8129 20:12:04.569803
8130 20:12:04.573062 TX Vref early break, caculate TX vref
8131 20:12:04.576177 TX Vref=16, minBit 0, minWin=22, winSum=367
8132 20:12:04.579522 TX Vref=18, minBit 11, minWin=22, winSum=376
8133 20:12:04.582858 TX Vref=20, minBit 1, minWin=23, winSum=382
8134 20:12:04.586297 TX Vref=22, minBit 8, minWin=22, winSum=389
8135 20:12:04.589488 TX Vref=24, minBit 8, minWin=24, winSum=400
8136 20:12:04.596321 TX Vref=26, minBit 9, minWin=24, winSum=406
8137 20:12:04.599603 TX Vref=28, minBit 1, minWin=25, winSum=414
8138 20:12:04.602584 TX Vref=30, minBit 8, minWin=24, winSum=410
8139 20:12:04.606115 TX Vref=32, minBit 8, minWin=23, winSum=394
8140 20:12:04.609337 TX Vref=34, minBit 8, minWin=23, winSum=389
8141 20:12:04.616332 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
8142 20:12:04.616419
8143 20:12:04.619561 Final TX Range 0 Vref 28
8144 20:12:04.619643
8145 20:12:04.619708 ==
8146 20:12:04.622589 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 20:12:04.626029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 20:12:04.626110 ==
8149 20:12:04.626174
8150 20:12:04.626234
8151 20:12:04.629631 TX Vref Scan disable
8152 20:12:04.636192 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8153 20:12:04.636273 == TX Byte 0 ==
8154 20:12:04.639420 u2DelayCellOfst[0]=11 cells (3 PI)
8155 20:12:04.642832 u2DelayCellOfst[1]=15 cells (4 PI)
8156 20:12:04.645917 u2DelayCellOfst[2]=7 cells (2 PI)
8157 20:12:04.649461 u2DelayCellOfst[3]=11 cells (3 PI)
8158 20:12:04.652519 u2DelayCellOfst[4]=7 cells (2 PI)
8159 20:12:04.655901 u2DelayCellOfst[5]=0 cells (0 PI)
8160 20:12:04.659391 u2DelayCellOfst[6]=18 cells (5 PI)
8161 20:12:04.662439 u2DelayCellOfst[7]=15 cells (4 PI)
8162 20:12:04.665912 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8163 20:12:04.669293 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8164 20:12:04.672579 == TX Byte 1 ==
8165 20:12:04.672659 u2DelayCellOfst[8]=0 cells (0 PI)
8166 20:12:04.675812 u2DelayCellOfst[9]=0 cells (0 PI)
8167 20:12:04.679098 u2DelayCellOfst[10]=7 cells (2 PI)
8168 20:12:04.682541 u2DelayCellOfst[11]=7 cells (2 PI)
8169 20:12:04.685783 u2DelayCellOfst[12]=11 cells (3 PI)
8170 20:12:04.689161 u2DelayCellOfst[13]=11 cells (3 PI)
8171 20:12:04.692372 u2DelayCellOfst[14]=15 cells (4 PI)
8172 20:12:04.695475 u2DelayCellOfst[15]=11 cells (3 PI)
8173 20:12:04.698954 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8174 20:12:04.705544 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8175 20:12:04.705619 DramC Write-DBI on
8176 20:12:04.705687 ==
8177 20:12:04.708958 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 20:12:04.715488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 20:12:04.715570 ==
8180 20:12:04.715635
8181 20:12:04.715694
8182 20:12:04.715751 TX Vref Scan disable
8183 20:12:04.719332 == TX Byte 0 ==
8184 20:12:04.722625 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8185 20:12:04.725891 == TX Byte 1 ==
8186 20:12:04.729357 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8187 20:12:04.732479 DramC Write-DBI off
8188 20:12:04.732561
8189 20:12:04.732625 [DATLAT]
8190 20:12:04.732686 Freq=1600, CH0 RK1
8191 20:12:04.732745
8192 20:12:04.736009 DATLAT Default: 0xf
8193 20:12:04.736089 0, 0xFFFF, sum = 0
8194 20:12:04.739096 1, 0xFFFF, sum = 0
8195 20:12:04.742442 2, 0xFFFF, sum = 0
8196 20:12:04.742524 3, 0xFFFF, sum = 0
8197 20:12:04.745716 4, 0xFFFF, sum = 0
8198 20:12:04.745799 5, 0xFFFF, sum = 0
8199 20:12:04.749256 6, 0xFFFF, sum = 0
8200 20:12:04.749338 7, 0xFFFF, sum = 0
8201 20:12:04.752132 8, 0xFFFF, sum = 0
8202 20:12:04.752214 9, 0xFFFF, sum = 0
8203 20:12:04.755611 10, 0xFFFF, sum = 0
8204 20:12:04.755694 11, 0xFFFF, sum = 0
8205 20:12:04.758791 12, 0xFFFF, sum = 0
8206 20:12:04.758873 13, 0xCFFF, sum = 0
8207 20:12:04.762181 14, 0x0, sum = 1
8208 20:12:04.762263 15, 0x0, sum = 2
8209 20:12:04.765606 16, 0x0, sum = 3
8210 20:12:04.765688 17, 0x0, sum = 4
8211 20:12:04.768771 best_step = 15
8212 20:12:04.768851
8213 20:12:04.768915 ==
8214 20:12:04.772216 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 20:12:04.775280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 20:12:04.775362 ==
8217 20:12:04.778745 RX Vref Scan: 0
8218 20:12:04.778826
8219 20:12:04.778890 RX Vref 0 -> 0, step: 1
8220 20:12:04.778952
8221 20:12:04.781903 RX Delay 3 -> 252, step: 4
8222 20:12:04.788785 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8223 20:12:04.792091 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8224 20:12:04.795150 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8225 20:12:04.798580 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8226 20:12:04.801838 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8227 20:12:04.805131 iDelay=195, Bit 5, Center 112 (59 ~ 166) 108
8228 20:12:04.811852 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8229 20:12:04.815141 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8230 20:12:04.818822 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8231 20:12:04.821763 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8232 20:12:04.825181 iDelay=195, Bit 10, Center 120 (63 ~ 178) 116
8233 20:12:04.831868 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8234 20:12:04.834987 iDelay=195, Bit 12, Center 124 (67 ~ 182) 116
8235 20:12:04.838434 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
8236 20:12:04.841732 iDelay=195, Bit 14, Center 128 (71 ~ 186) 116
8237 20:12:04.848490 iDelay=195, Bit 15, Center 124 (67 ~ 182) 116
8238 20:12:04.848571 ==
8239 20:12:04.851762 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 20:12:04.854980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 20:12:04.855061 ==
8242 20:12:04.855126 DQS Delay:
8243 20:12:04.858359 DQS0 = 0, DQS1 = 0
8244 20:12:04.858440 DQM Delay:
8245 20:12:04.861715 DQM0 = 125, DQM1 = 118
8246 20:12:04.861795 DQ Delay:
8247 20:12:04.864937 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8248 20:12:04.868175 DQ4 =124, DQ5 =112, DQ6 =136, DQ7 =136
8249 20:12:04.871310 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
8250 20:12:04.874746 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8251 20:12:04.874827
8252 20:12:04.878337
8253 20:12:04.878417
8254 20:12:04.878482 [DramC_TX_OE_Calibration] TA2
8255 20:12:04.881364 Original DQ_B0 (3 6) =30, OEN = 27
8256 20:12:04.884804 Original DQ_B1 (3 6) =30, OEN = 27
8257 20:12:04.888199 24, 0x0, End_B0=24 End_B1=24
8258 20:12:04.891487 25, 0x0, End_B0=25 End_B1=25
8259 20:12:04.894512 26, 0x0, End_B0=26 End_B1=26
8260 20:12:04.894594 27, 0x0, End_B0=27 End_B1=27
8261 20:12:04.898111 28, 0x0, End_B0=28 End_B1=28
8262 20:12:04.901169 29, 0x0, End_B0=29 End_B1=29
8263 20:12:04.904540 30, 0x0, End_B0=30 End_B1=30
8264 20:12:04.908072 31, 0x4141, End_B0=30 End_B1=30
8265 20:12:04.908154 Byte0 end_step=30 best_step=27
8266 20:12:04.911494 Byte1 end_step=30 best_step=27
8267 20:12:04.914504 Byte0 TX OE(2T, 0.5T) = (3, 3)
8268 20:12:04.917769 Byte1 TX OE(2T, 0.5T) = (3, 3)
8269 20:12:04.917850
8270 20:12:04.917914
8271 20:12:04.924386 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8272 20:12:04.927752 CH0 RK1: MR19=303, MR18=2613
8273 20:12:04.934423 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8274 20:12:04.937699 [RxdqsGatingPostProcess] freq 1600
8275 20:12:04.944612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8276 20:12:04.947810 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 20:12:04.947895 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 20:12:04.950865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 20:12:04.954249 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 20:12:04.957564 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 20:12:04.960815 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 20:12:04.964516 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 20:12:04.967695 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 20:12:04.971122 Pre-setting of DQS Precalculation
8285 20:12:04.974409 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8286 20:12:04.977952 ==
8287 20:12:04.978034 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 20:12:04.984432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 20:12:04.984513 ==
8290 20:12:04.987599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8291 20:12:04.994061 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8292 20:12:04.997442 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8293 20:12:05.004237 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8294 20:12:05.012208 [CA 0] Center 42 (13~71) winsize 59
8295 20:12:05.015650 [CA 1] Center 42 (12~72) winsize 61
8296 20:12:05.019168 [CA 2] Center 38 (9~67) winsize 59
8297 20:12:05.022201 [CA 3] Center 37 (8~66) winsize 59
8298 20:12:05.025543 [CA 4] Center 37 (8~67) winsize 60
8299 20:12:05.028967 [CA 5] Center 36 (7~66) winsize 60
8300 20:12:05.029049
8301 20:12:05.032010 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8302 20:12:05.032091
8303 20:12:05.035593 [CATrainingPosCal] consider 1 rank data
8304 20:12:05.038583 u2DelayCellTimex100 = 258/100 ps
8305 20:12:05.042158 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8306 20:12:05.048605 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8307 20:12:05.051864 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8308 20:12:05.055517 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8309 20:12:05.058523 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8310 20:12:05.061959 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8311 20:12:05.062039
8312 20:12:05.065323 CA PerBit enable=1, Macro0, CA PI delay=36
8313 20:12:05.065402
8314 20:12:05.068762 [CBTSetCACLKResult] CA Dly = 36
8315 20:12:05.072023 CS Dly: 9 (0~40)
8316 20:12:05.075254 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8317 20:12:05.078511 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8318 20:12:05.078591 ==
8319 20:12:05.081813 Dram Type= 6, Freq= 0, CH_1, rank 1
8320 20:12:05.085155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 20:12:05.088748 ==
8322 20:12:05.091676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 20:12:05.095204 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 20:12:05.101809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 20:12:05.108130 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 20:12:05.115550 [CA 0] Center 42 (12~72) winsize 61
8327 20:12:05.118910 [CA 1] Center 43 (13~73) winsize 61
8328 20:12:05.121891 [CA 2] Center 38 (9~67) winsize 59
8329 20:12:05.125256 [CA 3] Center 37 (8~66) winsize 59
8330 20:12:05.128771 [CA 4] Center 38 (8~68) winsize 61
8331 20:12:05.132064 [CA 5] Center 37 (7~67) winsize 61
8332 20:12:05.132144
8333 20:12:05.135370 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8334 20:12:05.135450
8335 20:12:05.138468 [CATrainingPosCal] consider 2 rank data
8336 20:12:05.141913 u2DelayCellTimex100 = 258/100 ps
8337 20:12:05.148605 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8338 20:12:05.151922 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8339 20:12:05.155167 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8340 20:12:05.158396 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8341 20:12:05.161699 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8342 20:12:05.165112 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8343 20:12:05.165192
8344 20:12:05.168267 CA PerBit enable=1, Macro0, CA PI delay=36
8345 20:12:05.168347
8346 20:12:05.171832 [CBTSetCACLKResult] CA Dly = 36
8347 20:12:05.174855 CS Dly: 10 (0~43)
8348 20:12:05.178230 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 20:12:05.181515 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 20:12:05.181608
8351 20:12:05.184717 ----->DramcWriteLeveling(PI) begin...
8352 20:12:05.184799 ==
8353 20:12:05.188083 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 20:12:05.194739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 20:12:05.194820 ==
8356 20:12:05.198376 Write leveling (Byte 0): 24 => 24
8357 20:12:05.198456 Write leveling (Byte 1): 29 => 29
8358 20:12:05.201600 DramcWriteLeveling(PI) end<-----
8359 20:12:05.201680
8360 20:12:05.204853 ==
8361 20:12:05.204932 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 20:12:05.211427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 20:12:05.211508 ==
8364 20:12:05.214869 [Gating] SW mode calibration
8365 20:12:05.221197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8366 20:12:05.224652 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8367 20:12:05.231214 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 20:12:05.234605 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 20:12:05.237944 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 20:12:05.244646 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 20:12:05.247851 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 20:12:05.251160 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 20:12:05.257888 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8374 20:12:05.261054 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 20:12:05.264379 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 20:12:05.271062 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 20:12:05.274320 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 20:12:05.277586 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8379 20:12:05.284368 1 5 16 | B1->B0 | 2525 2525 | 0 0 | (0 1) (1 0)
8380 20:12:05.287424 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 20:12:05.290949 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 20:12:05.297685 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 20:12:05.300634 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 20:12:05.303793 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 20:12:05.310533 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 20:12:05.314045 1 6 12 | B1->B0 | 2929 2424 | 1 0 | (0 0) (0 0)
8387 20:12:05.317153 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8388 20:12:05.323942 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 20:12:05.327215 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 20:12:05.330477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 20:12:05.336950 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 20:12:05.340300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 20:12:05.343675 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 20:12:05.350268 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 20:12:05.353665 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 20:12:05.356848 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8397 20:12:05.363359 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 20:12:05.366889 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 20:12:05.370065 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 20:12:05.376571 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 20:12:05.379646 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 20:12:05.383126 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 20:12:05.389869 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 20:12:05.393169 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 20:12:05.396498 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 20:12:05.402814 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 20:12:05.406160 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 20:12:05.409456 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 20:12:05.416066 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 20:12:05.419476 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 20:12:05.422587 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 20:12:05.429411 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 20:12:05.429538 Total UI for P1: 0, mck2ui 16
8414 20:12:05.435846 best dqsien dly found for B0: ( 1, 9, 16)
8415 20:12:05.435928 Total UI for P1: 0, mck2ui 16
8416 20:12:05.439127 best dqsien dly found for B1: ( 1, 9, 16)
8417 20:12:05.446195 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8418 20:12:05.449127 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8419 20:12:05.449208
8420 20:12:05.452600 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8421 20:12:05.455761 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8422 20:12:05.459081 [Gating] SW calibration Done
8423 20:12:05.459162 ==
8424 20:12:05.462323 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 20:12:05.465591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 20:12:05.465673 ==
8427 20:12:05.468740 RX Vref Scan: 0
8428 20:12:05.468820
8429 20:12:05.468885 RX Vref 0 -> 0, step: 1
8430 20:12:05.468946
8431 20:12:05.472189 RX Delay 0 -> 252, step: 8
8432 20:12:05.475610 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8433 20:12:05.482195 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8434 20:12:05.485339 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8435 20:12:05.488799 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8436 20:12:05.492109 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8437 20:12:05.495364 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8438 20:12:05.501776 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8439 20:12:05.505229 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8440 20:12:05.508721 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8441 20:12:05.511802 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8442 20:12:05.515097 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8443 20:12:05.521810 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8444 20:12:05.525225 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8445 20:12:05.528260 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8446 20:12:05.531786 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8447 20:12:05.538033 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8448 20:12:05.538115 ==
8449 20:12:05.541481 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 20:12:05.544859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 20:12:05.544941 ==
8452 20:12:05.545006 DQS Delay:
8453 20:12:05.548208 DQS0 = 0, DQS1 = 0
8454 20:12:05.548289 DQM Delay:
8455 20:12:05.551335 DQM0 = 131, DQM1 = 125
8456 20:12:05.551415 DQ Delay:
8457 20:12:05.554732 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8458 20:12:05.558129 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8459 20:12:05.561354 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8460 20:12:05.564726 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8461 20:12:05.564807
8462 20:12:05.564872
8463 20:12:05.568040 ==
8464 20:12:05.571147 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 20:12:05.574722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 20:12:05.574804 ==
8467 20:12:05.574869
8468 20:12:05.574929
8469 20:12:05.577818 TX Vref Scan disable
8470 20:12:05.577900 == TX Byte 0 ==
8471 20:12:05.584495 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8472 20:12:05.587994 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8473 20:12:05.588076 == TX Byte 1 ==
8474 20:12:05.594572 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8475 20:12:05.597841 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8476 20:12:05.597922 ==
8477 20:12:05.601025 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 20:12:05.604267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 20:12:05.604348 ==
8480 20:12:05.617807
8481 20:12:05.621143 TX Vref early break, caculate TX vref
8482 20:12:05.624480 TX Vref=16, minBit 8, minWin=21, winSum=360
8483 20:12:05.627809 TX Vref=18, minBit 10, minWin=21, winSum=373
8484 20:12:05.631378 TX Vref=20, minBit 10, minWin=22, winSum=380
8485 20:12:05.634587 TX Vref=22, minBit 9, minWin=23, winSum=391
8486 20:12:05.640878 TX Vref=24, minBit 12, minWin=24, winSum=403
8487 20:12:05.644159 TX Vref=26, minBit 12, minWin=24, winSum=410
8488 20:12:05.647546 TX Vref=28, minBit 1, minWin=25, winSum=416
8489 20:12:05.650765 TX Vref=30, minBit 9, minWin=24, winSum=413
8490 20:12:05.654263 TX Vref=32, minBit 1, minWin=25, winSum=407
8491 20:12:05.657257 TX Vref=34, minBit 6, minWin=23, winSum=393
8492 20:12:05.664170 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
8493 20:12:05.664252
8494 20:12:05.667271 Final TX Range 0 Vref 28
8495 20:12:05.667360
8496 20:12:05.667431 ==
8497 20:12:05.670649 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 20:12:05.673871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 20:12:05.673978 ==
8500 20:12:05.674071
8501 20:12:05.677143
8502 20:12:05.677238 TX Vref Scan disable
8503 20:12:05.683645 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8504 20:12:05.683726 == TX Byte 0 ==
8505 20:12:05.687193 u2DelayCellOfst[0]=18 cells (5 PI)
8506 20:12:05.690460 u2DelayCellOfst[1]=15 cells (4 PI)
8507 20:12:05.693538 u2DelayCellOfst[2]=0 cells (0 PI)
8508 20:12:05.696735 u2DelayCellOfst[3]=7 cells (2 PI)
8509 20:12:05.700338 u2DelayCellOfst[4]=7 cells (2 PI)
8510 20:12:05.703329 u2DelayCellOfst[5]=22 cells (6 PI)
8511 20:12:05.706843 u2DelayCellOfst[6]=22 cells (6 PI)
8512 20:12:05.710042 u2DelayCellOfst[7]=3 cells (1 PI)
8513 20:12:05.713510 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8514 20:12:05.716561 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8515 20:12:05.719923 == TX Byte 1 ==
8516 20:12:05.723463 u2DelayCellOfst[8]=0 cells (0 PI)
8517 20:12:05.726736 u2DelayCellOfst[9]=7 cells (2 PI)
8518 20:12:05.730133 u2DelayCellOfst[10]=18 cells (5 PI)
8519 20:12:05.733165 u2DelayCellOfst[11]=11 cells (3 PI)
8520 20:12:05.733247 u2DelayCellOfst[12]=18 cells (5 PI)
8521 20:12:05.736601 u2DelayCellOfst[13]=26 cells (7 PI)
8522 20:12:05.739914 u2DelayCellOfst[14]=22 cells (6 PI)
8523 20:12:05.743276 u2DelayCellOfst[15]=22 cells (6 PI)
8524 20:12:05.750119 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8525 20:12:05.753145 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8526 20:12:05.753226 DramC Write-DBI on
8527 20:12:05.756704 ==
8528 20:12:05.756785 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 20:12:05.763139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 20:12:05.763221 ==
8531 20:12:05.763285
8532 20:12:05.763345
8533 20:12:05.766262 TX Vref Scan disable
8534 20:12:05.766343 == TX Byte 0 ==
8535 20:12:05.772785 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8536 20:12:05.772866 == TX Byte 1 ==
8537 20:12:05.776129 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8538 20:12:05.779617 DramC Write-DBI off
8539 20:12:05.779698
8540 20:12:05.779762 [DATLAT]
8541 20:12:05.782742 Freq=1600, CH1 RK0
8542 20:12:05.782823
8543 20:12:05.782887 DATLAT Default: 0xf
8544 20:12:05.786193 0, 0xFFFF, sum = 0
8545 20:12:05.786276 1, 0xFFFF, sum = 0
8546 20:12:05.789547 2, 0xFFFF, sum = 0
8547 20:12:05.789630 3, 0xFFFF, sum = 0
8548 20:12:05.792830 4, 0xFFFF, sum = 0
8549 20:12:05.792911 5, 0xFFFF, sum = 0
8550 20:12:05.796175 6, 0xFFFF, sum = 0
8551 20:12:05.796257 7, 0xFFFF, sum = 0
8552 20:12:05.799611 8, 0xFFFF, sum = 0
8553 20:12:05.802789 9, 0xFFFF, sum = 0
8554 20:12:05.802871 10, 0xFFFF, sum = 0
8555 20:12:05.806132 11, 0xFFFF, sum = 0
8556 20:12:05.806214 12, 0xFFFF, sum = 0
8557 20:12:05.809167 13, 0x8FFF, sum = 0
8558 20:12:05.809249 14, 0x0, sum = 1
8559 20:12:05.812886 15, 0x0, sum = 2
8560 20:12:05.812968 16, 0x0, sum = 3
8561 20:12:05.816084 17, 0x0, sum = 4
8562 20:12:05.816166 best_step = 15
8563 20:12:05.816230
8564 20:12:05.816290 ==
8565 20:12:05.819376 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 20:12:05.822499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 20:12:05.822581 ==
8568 20:12:05.826103 RX Vref Scan: 1
8569 20:12:05.826184
8570 20:12:05.829261 Set Vref Range= 24 -> 127
8571 20:12:05.829341
8572 20:12:05.829405 RX Vref 24 -> 127, step: 1
8573 20:12:05.829488
8574 20:12:05.832535 RX Delay 11 -> 252, step: 4
8575 20:12:05.832615
8576 20:12:05.835628 Set Vref, RX VrefLevel [Byte0]: 24
8577 20:12:05.839104 [Byte1]: 24
8578 20:12:05.842605
8579 20:12:05.842685 Set Vref, RX VrefLevel [Byte0]: 25
8580 20:12:05.846056 [Byte1]: 25
8581 20:12:05.850225
8582 20:12:05.850306 Set Vref, RX VrefLevel [Byte0]: 26
8583 20:12:05.853625 [Byte1]: 26
8584 20:12:05.858343
8585 20:12:05.858423 Set Vref, RX VrefLevel [Byte0]: 27
8586 20:12:05.861161 [Byte1]: 27
8587 20:12:05.865664
8588 20:12:05.865745 Set Vref, RX VrefLevel [Byte0]: 28
8589 20:12:05.868866 [Byte1]: 28
8590 20:12:05.872913
8591 20:12:05.872994 Set Vref, RX VrefLevel [Byte0]: 29
8592 20:12:05.876245 [Byte1]: 29
8593 20:12:05.880598
8594 20:12:05.880679 Set Vref, RX VrefLevel [Byte0]: 30
8595 20:12:05.883874 [Byte1]: 30
8596 20:12:05.888374
8597 20:12:05.888455 Set Vref, RX VrefLevel [Byte0]: 31
8598 20:12:05.891469 [Byte1]: 31
8599 20:12:05.895789
8600 20:12:05.895870 Set Vref, RX VrefLevel [Byte0]: 32
8601 20:12:05.899314 [Byte1]: 32
8602 20:12:05.903472
8603 20:12:05.903553 Set Vref, RX VrefLevel [Byte0]: 33
8604 20:12:05.907022 [Byte1]: 33
8605 20:12:05.911436
8606 20:12:05.911516 Set Vref, RX VrefLevel [Byte0]: 34
8607 20:12:05.914449 [Byte1]: 34
8608 20:12:05.918952
8609 20:12:05.919033 Set Vref, RX VrefLevel [Byte0]: 35
8610 20:12:05.921840 [Byte1]: 35
8611 20:12:05.926456
8612 20:12:05.926536 Set Vref, RX VrefLevel [Byte0]: 36
8613 20:12:05.929659 [Byte1]: 36
8614 20:12:05.933908
8615 20:12:05.933989 Set Vref, RX VrefLevel [Byte0]: 37
8616 20:12:05.937319 [Byte1]: 37
8617 20:12:05.941445
8618 20:12:05.941546 Set Vref, RX VrefLevel [Byte0]: 38
8619 20:12:05.944933 [Byte1]: 38
8620 20:12:05.949168
8621 20:12:05.949280 Set Vref, RX VrefLevel [Byte0]: 39
8622 20:12:05.952702 [Byte1]: 39
8623 20:12:05.956615
8624 20:12:05.956727 Set Vref, RX VrefLevel [Byte0]: 40
8625 20:12:05.960072 [Byte1]: 40
8626 20:12:05.964498
8627 20:12:05.964579 Set Vref, RX VrefLevel [Byte0]: 41
8628 20:12:05.967814 [Byte1]: 41
8629 20:12:05.972070
8630 20:12:05.972192 Set Vref, RX VrefLevel [Byte0]: 42
8631 20:12:05.975382 [Byte1]: 42
8632 20:12:05.979658
8633 20:12:05.979731 Set Vref, RX VrefLevel [Byte0]: 43
8634 20:12:05.982725 [Byte1]: 43
8635 20:12:05.987461
8636 20:12:05.987562 Set Vref, RX VrefLevel [Byte0]: 44
8637 20:12:05.990719 [Byte1]: 44
8638 20:12:05.995008
8639 20:12:05.995090 Set Vref, RX VrefLevel [Byte0]: 45
8640 20:12:05.998159 [Byte1]: 45
8641 20:12:06.002584
8642 20:12:06.002656 Set Vref, RX VrefLevel [Byte0]: 46
8643 20:12:06.005768 [Byte1]: 46
8644 20:12:06.010112
8645 20:12:06.010220 Set Vref, RX VrefLevel [Byte0]: 47
8646 20:12:06.013446 [Byte1]: 47
8647 20:12:06.017916
8648 20:12:06.018038 Set Vref, RX VrefLevel [Byte0]: 48
8649 20:12:06.021156 [Byte1]: 48
8650 20:12:06.025228
8651 20:12:06.025332 Set Vref, RX VrefLevel [Byte0]: 49
8652 20:12:06.028715 [Byte1]: 49
8653 20:12:06.032760
8654 20:12:06.032870 Set Vref, RX VrefLevel [Byte0]: 50
8655 20:12:06.036143 [Byte1]: 50
8656 20:12:06.040421
8657 20:12:06.040524 Set Vref, RX VrefLevel [Byte0]: 51
8658 20:12:06.043841 [Byte1]: 51
8659 20:12:06.048186
8660 20:12:06.048268 Set Vref, RX VrefLevel [Byte0]: 52
8661 20:12:06.051195 [Byte1]: 52
8662 20:12:06.055813
8663 20:12:06.055929 Set Vref, RX VrefLevel [Byte0]: 53
8664 20:12:06.058938 [Byte1]: 53
8665 20:12:06.063462
8666 20:12:06.063568 Set Vref, RX VrefLevel [Byte0]: 54
8667 20:12:06.066626 [Byte1]: 54
8668 20:12:06.070791
8669 20:12:06.070896 Set Vref, RX VrefLevel [Byte0]: 55
8670 20:12:06.074119 [Byte1]: 55
8671 20:12:06.078760
8672 20:12:06.078843 Set Vref, RX VrefLevel [Byte0]: 56
8673 20:12:06.081910 [Byte1]: 56
8674 20:12:06.086265
8675 20:12:06.086370 Set Vref, RX VrefLevel [Byte0]: 57
8676 20:12:06.089594 [Byte1]: 57
8677 20:12:06.093760
8678 20:12:06.093843 Set Vref, RX VrefLevel [Byte0]: 58
8679 20:12:06.097246 [Byte1]: 58
8680 20:12:06.101524
8681 20:12:06.101637 Set Vref, RX VrefLevel [Byte0]: 59
8682 20:12:06.104947 [Byte1]: 59
8683 20:12:06.109122
8684 20:12:06.109205 Set Vref, RX VrefLevel [Byte0]: 60
8685 20:12:06.112365 [Byte1]: 60
8686 20:12:06.116791
8687 20:12:06.116873 Set Vref, RX VrefLevel [Byte0]: 61
8688 20:12:06.119923 [Byte1]: 61
8689 20:12:06.124227
8690 20:12:06.124309 Set Vref, RX VrefLevel [Byte0]: 62
8691 20:12:06.127741 [Byte1]: 62
8692 20:12:06.131761
8693 20:12:06.131845 Set Vref, RX VrefLevel [Byte0]: 63
8694 20:12:06.135118 [Byte1]: 63
8695 20:12:06.139381
8696 20:12:06.139463 Set Vref, RX VrefLevel [Byte0]: 64
8697 20:12:06.142767 [Byte1]: 64
8698 20:12:06.147185
8699 20:12:06.147267 Set Vref, RX VrefLevel [Byte0]: 65
8700 20:12:06.150386 [Byte1]: 65
8701 20:12:06.154758
8702 20:12:06.154867 Set Vref, RX VrefLevel [Byte0]: 66
8703 20:12:06.157975 [Byte1]: 66
8704 20:12:06.162679
8705 20:12:06.162761 Set Vref, RX VrefLevel [Byte0]: 67
8706 20:12:06.165612 [Byte1]: 67
8707 20:12:06.170093
8708 20:12:06.170175 Set Vref, RX VrefLevel [Byte0]: 68
8709 20:12:06.173247 [Byte1]: 68
8710 20:12:06.177448
8711 20:12:06.177535 Set Vref, RX VrefLevel [Byte0]: 69
8712 20:12:06.180672 [Byte1]: 69
8713 20:12:06.185175
8714 20:12:06.185254 Set Vref, RX VrefLevel [Byte0]: 70
8715 20:12:06.188279 [Byte1]: 70
8716 20:12:06.192728
8717 20:12:06.192810 Set Vref, RX VrefLevel [Byte0]: 71
8718 20:12:06.196180 [Byte1]: 71
8719 20:12:06.200413
8720 20:12:06.200485 Final RX Vref Byte 0 = 58 to rank0
8721 20:12:06.203796 Final RX Vref Byte 1 = 53 to rank0
8722 20:12:06.207084 Final RX Vref Byte 0 = 58 to rank1
8723 20:12:06.210147 Final RX Vref Byte 1 = 53 to rank1==
8724 20:12:06.213617 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 20:12:06.220230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 20:12:06.220315 ==
8727 20:12:06.220383 DQS Delay:
8728 20:12:06.220444 DQS0 = 0, DQS1 = 0
8729 20:12:06.223614 DQM Delay:
8730 20:12:06.223696 DQM0 = 131, DQM1 = 123
8731 20:12:06.227020 DQ Delay:
8732 20:12:06.230361 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8733 20:12:06.233675 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8734 20:12:06.237044 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8735 20:12:06.240211 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8736 20:12:06.240292
8737 20:12:06.240357
8738 20:12:06.240417
8739 20:12:06.243512 [DramC_TX_OE_Calibration] TA2
8740 20:12:06.246595 Original DQ_B0 (3 6) =30, OEN = 27
8741 20:12:06.250213 Original DQ_B1 (3 6) =30, OEN = 27
8742 20:12:06.253412 24, 0x0, End_B0=24 End_B1=24
8743 20:12:06.253535 25, 0x0, End_B0=25 End_B1=25
8744 20:12:06.256858 26, 0x0, End_B0=26 End_B1=26
8745 20:12:06.259906 27, 0x0, End_B0=27 End_B1=27
8746 20:12:06.263223 28, 0x0, End_B0=28 End_B1=28
8747 20:12:06.266651 29, 0x0, End_B0=29 End_B1=29
8748 20:12:06.266734 30, 0x0, End_B0=30 End_B1=30
8749 20:12:06.270067 31, 0x4141, End_B0=30 End_B1=30
8750 20:12:06.273283 Byte0 end_step=30 best_step=27
8751 20:12:06.276602 Byte1 end_step=30 best_step=27
8752 20:12:06.279807 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 20:12:06.283076 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 20:12:06.283163
8755 20:12:06.283229
8756 20:12:06.289917 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8757 20:12:06.293056 CH1 RK0: MR19=303, MR18=A0E
8758 20:12:06.299636 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8759 20:12:06.299718
8760 20:12:06.302939 ----->DramcWriteLeveling(PI) begin...
8761 20:12:06.303037 ==
8762 20:12:06.306464 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 20:12:06.309682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 20:12:06.309764 ==
8765 20:12:06.313114 Write leveling (Byte 0): 25 => 25
8766 20:12:06.316173 Write leveling (Byte 1): 30 => 30
8767 20:12:06.319713 DramcWriteLeveling(PI) end<-----
8768 20:12:06.319793
8769 20:12:06.319859 ==
8770 20:12:06.323109 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 20:12:06.326054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 20:12:06.326136 ==
8773 20:12:06.329407 [Gating] SW mode calibration
8774 20:12:06.336207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 20:12:06.342541 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 20:12:06.345830 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 20:12:06.358427 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 20:12:06.358510 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8779 20:12:06.359097 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
8780 20:12:06.365960 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 20:12:06.368999 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 20:12:06.372510 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 20:12:06.378945 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 20:12:06.382271 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 20:12:06.385697 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 20:12:06.389125 1 5 8 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8787 20:12:06.395597 1 5 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
8788 20:12:06.399044 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 20:12:06.402275 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 20:12:06.408825 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 20:12:06.412210 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 20:12:06.415689 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 20:12:06.422087 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 20:12:06.425394 1 6 8 | B1->B0 | 2f2f 4545 | 1 1 | (0 0) (0 0)
8795 20:12:06.428579 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8796 20:12:06.435179 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 20:12:06.438873 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 20:12:06.441908 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 20:12:06.448701 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 20:12:06.451875 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 20:12:06.455341 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 20:12:06.461940 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 20:12:06.465472 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 20:12:06.468495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 20:12:06.475326 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 20:12:06.478730 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 20:12:06.482153 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 20:12:06.488540 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 20:12:06.491982 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 20:12:06.495113 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 20:12:06.501711 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 20:12:06.505164 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 20:12:06.508485 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 20:12:06.514979 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 20:12:06.518109 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 20:12:06.521791 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 20:12:06.528086 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 20:12:06.531534 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 20:12:06.534961 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 20:12:06.537965 Total UI for P1: 0, mck2ui 16
8821 20:12:06.541246 best dqsien dly found for B0: ( 1, 9, 8)
8822 20:12:06.548161 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 20:12:06.548243 Total UI for P1: 0, mck2ui 16
8824 20:12:06.551292 best dqsien dly found for B1: ( 1, 9, 12)
8825 20:12:06.558018 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8826 20:12:06.561232 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8827 20:12:06.561333
8828 20:12:06.564411 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8829 20:12:06.567795 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8830 20:12:06.570877 [Gating] SW calibration Done
8831 20:12:06.570958 ==
8832 20:12:06.574317 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 20:12:06.577616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 20:12:06.577699 ==
8835 20:12:06.580984 RX Vref Scan: 0
8836 20:12:06.581091
8837 20:12:06.581187 RX Vref 0 -> 0, step: 1
8838 20:12:06.581276
8839 20:12:06.584262 RX Delay 0 -> 252, step: 8
8840 20:12:06.587480 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8841 20:12:06.594216 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 20:12:06.597128 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8843 20:12:06.600660 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8844 20:12:06.604030 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8845 20:12:06.607253 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8846 20:12:06.614044 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8847 20:12:06.616992 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8848 20:12:06.620519 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8849 20:12:06.623750 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 20:12:06.626875 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 20:12:06.633590 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8852 20:12:06.637036 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8853 20:12:06.640308 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8854 20:12:06.643419 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8855 20:12:06.650404 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8856 20:12:06.650487 ==
8857 20:12:06.653602 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 20:12:06.656891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 20:12:06.656977 ==
8860 20:12:06.657044 DQS Delay:
8861 20:12:06.659891 DQS0 = 0, DQS1 = 0
8862 20:12:06.660000 DQM Delay:
8863 20:12:06.663468 DQM0 = 129, DQM1 = 128
8864 20:12:06.663551 DQ Delay:
8865 20:12:06.666575 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8866 20:12:06.669927 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8867 20:12:06.673328 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8868 20:12:06.676456 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8869 20:12:06.676565
8870 20:12:06.676660
8871 20:12:06.679806 ==
8872 20:12:06.682960 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 20:12:06.686479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 20:12:06.686591 ==
8875 20:12:06.686691
8876 20:12:06.686758
8877 20:12:06.689875 TX Vref Scan disable
8878 20:12:06.689983 == TX Byte 0 ==
8879 20:12:06.696514 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8880 20:12:06.699591 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8881 20:12:06.699677 == TX Byte 1 ==
8882 20:12:06.706305 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8883 20:12:06.709598 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8884 20:12:06.709683 ==
8885 20:12:06.713015 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 20:12:06.716274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 20:12:06.716360 ==
8888 20:12:06.729821
8889 20:12:06.733369 TX Vref early break, caculate TX vref
8890 20:12:06.736401 TX Vref=16, minBit 0, minWin=22, winSum=378
8891 20:12:06.739967 TX Vref=18, minBit 11, minWin=22, winSum=386
8892 20:12:06.743361 TX Vref=20, minBit 8, minWin=23, winSum=394
8893 20:12:06.746317 TX Vref=22, minBit 8, minWin=23, winSum=402
8894 20:12:06.749887 TX Vref=24, minBit 8, minWin=24, winSum=410
8895 20:12:06.756426 TX Vref=26, minBit 8, minWin=24, winSum=416
8896 20:12:06.759454 TX Vref=28, minBit 0, minWin=25, winSum=420
8897 20:12:06.762826 TX Vref=30, minBit 8, minWin=24, winSum=416
8898 20:12:06.766476 TX Vref=32, minBit 8, minWin=23, winSum=405
8899 20:12:06.769645 TX Vref=34, minBit 1, minWin=23, winSum=397
8900 20:12:06.776243 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8901 20:12:06.776327
8902 20:12:06.779473 Final TX Range 0 Vref 28
8903 20:12:06.779556
8904 20:12:06.779621 ==
8905 20:12:06.782774 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 20:12:06.786043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 20:12:06.786127 ==
8908 20:12:06.786193
8909 20:12:06.786253
8910 20:12:06.789377 TX Vref Scan disable
8911 20:12:06.796116 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8912 20:12:06.796199 == TX Byte 0 ==
8913 20:12:06.799383 u2DelayCellOfst[0]=18 cells (5 PI)
8914 20:12:06.802705 u2DelayCellOfst[1]=15 cells (4 PI)
8915 20:12:06.805839 u2DelayCellOfst[2]=0 cells (0 PI)
8916 20:12:06.809169 u2DelayCellOfst[3]=7 cells (2 PI)
8917 20:12:06.812539 u2DelayCellOfst[4]=7 cells (2 PI)
8918 20:12:06.815892 u2DelayCellOfst[5]=18 cells (5 PI)
8919 20:12:06.819295 u2DelayCellOfst[6]=18 cells (5 PI)
8920 20:12:06.822367 u2DelayCellOfst[7]=3 cells (1 PI)
8921 20:12:06.825766 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8922 20:12:06.829225 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8923 20:12:06.832274 == TX Byte 1 ==
8924 20:12:06.835735 u2DelayCellOfst[8]=0 cells (0 PI)
8925 20:12:06.835816 u2DelayCellOfst[9]=7 cells (2 PI)
8926 20:12:06.839021 u2DelayCellOfst[10]=11 cells (3 PI)
8927 20:12:06.842260 u2DelayCellOfst[11]=3 cells (1 PI)
8928 20:12:06.845662 u2DelayCellOfst[12]=15 cells (4 PI)
8929 20:12:06.848720 u2DelayCellOfst[13]=15 cells (4 PI)
8930 20:12:06.852239 u2DelayCellOfst[14]=15 cells (4 PI)
8931 20:12:06.855622 u2DelayCellOfst[15]=18 cells (5 PI)
8932 20:12:06.859107 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8933 20:12:06.865619 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8934 20:12:06.865743 DramC Write-DBI on
8935 20:12:06.865836 ==
8936 20:12:06.869003 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 20:12:06.875468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 20:12:06.875550 ==
8939 20:12:06.875638
8940 20:12:06.875734
8941 20:12:06.875794 TX Vref Scan disable
8942 20:12:06.879415 == TX Byte 0 ==
8943 20:12:06.882454 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8944 20:12:06.885893 == TX Byte 1 ==
8945 20:12:06.889340 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8946 20:12:06.892593 DramC Write-DBI off
8947 20:12:06.892673
8948 20:12:06.892738 [DATLAT]
8949 20:12:06.892799 Freq=1600, CH1 RK1
8950 20:12:06.892858
8951 20:12:06.895968 DATLAT Default: 0xf
8952 20:12:06.896049 0, 0xFFFF, sum = 0
8953 20:12:06.899540 1, 0xFFFF, sum = 0
8954 20:12:06.899621 2, 0xFFFF, sum = 0
8955 20:12:06.902535 3, 0xFFFF, sum = 0
8956 20:12:06.905855 4, 0xFFFF, sum = 0
8957 20:12:06.905941 5, 0xFFFF, sum = 0
8958 20:12:06.909582 6, 0xFFFF, sum = 0
8959 20:12:06.909665 7, 0xFFFF, sum = 0
8960 20:12:06.912772 8, 0xFFFF, sum = 0
8961 20:12:06.912862 9, 0xFFFF, sum = 0
8962 20:12:06.915946 10, 0xFFFF, sum = 0
8963 20:12:06.916028 11, 0xFFFF, sum = 0
8964 20:12:06.919485 12, 0xFFFF, sum = 0
8965 20:12:06.919596 13, 0x8FFF, sum = 0
8966 20:12:06.922474 14, 0x0, sum = 1
8967 20:12:06.922557 15, 0x0, sum = 2
8968 20:12:06.925697 16, 0x0, sum = 3
8969 20:12:06.925779 17, 0x0, sum = 4
8970 20:12:06.929091 best_step = 15
8971 20:12:06.929172
8972 20:12:06.929258 ==
8973 20:12:06.932498 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 20:12:06.935843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 20:12:06.935926 ==
8976 20:12:06.935991 RX Vref Scan: 0
8977 20:12:06.939239
8978 20:12:06.939319 RX Vref 0 -> 0, step: 1
8979 20:12:06.939383
8980 20:12:06.942196 RX Delay 11 -> 252, step: 4
8981 20:12:06.945624 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8982 20:12:06.952168 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8983 20:12:06.955558 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8984 20:12:06.958964 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8985 20:12:06.962287 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8986 20:12:06.965585 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8987 20:12:06.972166 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8988 20:12:06.975588 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8989 20:12:06.979188 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8990 20:12:06.982170 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8991 20:12:06.985733 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8992 20:12:06.992383 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8993 20:12:06.995753 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8994 20:12:06.998697 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8995 20:12:07.002214 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8996 20:12:07.008692 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8997 20:12:07.008817 ==
8998 20:12:07.012037 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 20:12:07.015472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 20:12:07.015607 ==
9001 20:12:07.015714 DQS Delay:
9002 20:12:07.018771 DQS0 = 0, DQS1 = 0
9003 20:12:07.018921 DQM Delay:
9004 20:12:07.022090 DQM0 = 128, DQM1 = 125
9005 20:12:07.022261 DQ Delay:
9006 20:12:07.025237 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
9007 20:12:07.028769 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9008 20:12:07.031777 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9009 20:12:07.035291 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9010 20:12:07.035531
9011 20:12:07.035719
9012 20:12:07.038905
9013 20:12:07.039200 [DramC_TX_OE_Calibration] TA2
9014 20:12:07.041973 Original DQ_B0 (3 6) =30, OEN = 27
9015 20:12:07.045602 Original DQ_B1 (3 6) =30, OEN = 27
9016 20:12:07.048676 24, 0x0, End_B0=24 End_B1=24
9017 20:12:07.052085 25, 0x0, End_B0=25 End_B1=25
9018 20:12:07.055548 26, 0x0, End_B0=26 End_B1=26
9019 20:12:07.056039 27, 0x0, End_B0=27 End_B1=27
9020 20:12:07.058661 28, 0x0, End_B0=28 End_B1=28
9021 20:12:07.062127 29, 0x0, End_B0=29 End_B1=29
9022 20:12:07.065184 30, 0x0, End_B0=30 End_B1=30
9023 20:12:07.068917 31, 0x4141, End_B0=30 End_B1=30
9024 20:12:07.069341 Byte0 end_step=30 best_step=27
9025 20:12:07.071995 Byte1 end_step=30 best_step=27
9026 20:12:07.075254 Byte0 TX OE(2T, 0.5T) = (3, 3)
9027 20:12:07.078514 Byte1 TX OE(2T, 0.5T) = (3, 3)
9028 20:12:07.079031
9029 20:12:07.079403
9030 20:12:07.085022 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9031 20:12:07.088358 CH1 RK1: MR19=303, MR18=101D
9032 20:12:07.094984 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
9033 20:12:07.098626 [RxdqsGatingPostProcess] freq 1600
9034 20:12:07.104956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9035 20:12:07.108510 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 20:12:07.108929 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 20:12:07.111611 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 20:12:07.115227 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 20:12:07.118309 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 20:12:07.121974 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 20:12:07.124895 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 20:12:07.127970 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 20:12:07.131347 Pre-setting of DQS Precalculation
9044 20:12:07.134819 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9045 20:12:07.144651 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9046 20:12:07.151378 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9047 20:12:07.151922
9048 20:12:07.152366
9049 20:12:07.154464 [Calibration Summary] 3200 Mbps
9050 20:12:07.155022 CH 0, Rank 0
9051 20:12:07.157792 SW Impedance : PASS
9052 20:12:07.161405 DUTY Scan : NO K
9053 20:12:07.161648 ZQ Calibration : PASS
9054 20:12:07.164200 Jitter Meter : NO K
9055 20:12:07.164382 CBT Training : PASS
9056 20:12:07.167687 Write leveling : PASS
9057 20:12:07.170770 RX DQS gating : PASS
9058 20:12:07.170890 RX DQ/DQS(RDDQC) : PASS
9059 20:12:07.174233 TX DQ/DQS : PASS
9060 20:12:07.177370 RX DATLAT : PASS
9061 20:12:07.177451 RX DQ/DQS(Engine): PASS
9062 20:12:07.180929 TX OE : PASS
9063 20:12:07.181010 All Pass.
9064 20:12:07.181077
9065 20:12:07.184069 CH 0, Rank 1
9066 20:12:07.184151 SW Impedance : PASS
9067 20:12:07.187590 DUTY Scan : NO K
9068 20:12:07.190799 ZQ Calibration : PASS
9069 20:12:07.190880 Jitter Meter : NO K
9070 20:12:07.193946 CBT Training : PASS
9071 20:12:07.197446 Write leveling : PASS
9072 20:12:07.197581 RX DQS gating : PASS
9073 20:12:07.200527 RX DQ/DQS(RDDQC) : PASS
9074 20:12:07.204025 TX DQ/DQS : PASS
9075 20:12:07.204108 RX DATLAT : PASS
9076 20:12:07.207300 RX DQ/DQS(Engine): PASS
9077 20:12:07.210735 TX OE : PASS
9078 20:12:07.210818 All Pass.
9079 20:12:07.210883
9080 20:12:07.210944 CH 1, Rank 0
9081 20:12:07.213995 SW Impedance : PASS
9082 20:12:07.217315 DUTY Scan : NO K
9083 20:12:07.217395 ZQ Calibration : PASS
9084 20:12:07.220504 Jitter Meter : NO K
9085 20:12:07.220639 CBT Training : PASS
9086 20:12:07.224018 Write leveling : PASS
9087 20:12:07.227167 RX DQS gating : PASS
9088 20:12:07.227264 RX DQ/DQS(RDDQC) : PASS
9089 20:12:07.230677 TX DQ/DQS : PASS
9090 20:12:07.233661 RX DATLAT : PASS
9091 20:12:07.233756 RX DQ/DQS(Engine): PASS
9092 20:12:07.237108 TX OE : PASS
9093 20:12:07.237207 All Pass.
9094 20:12:07.237273
9095 20:12:07.240295 CH 1, Rank 1
9096 20:12:07.240378 SW Impedance : PASS
9097 20:12:07.243491 DUTY Scan : NO K
9098 20:12:07.246828 ZQ Calibration : PASS
9099 20:12:07.246902 Jitter Meter : NO K
9100 20:12:07.250362 CBT Training : PASS
9101 20:12:07.253661 Write leveling : PASS
9102 20:12:07.253735 RX DQS gating : PASS
9103 20:12:07.256649 RX DQ/DQS(RDDQC) : PASS
9104 20:12:07.260054 TX DQ/DQS : PASS
9105 20:12:07.260128 RX DATLAT : PASS
9106 20:12:07.263683 RX DQ/DQS(Engine): PASS
9107 20:12:07.266928 TX OE : PASS
9108 20:12:07.267044 All Pass.
9109 20:12:07.267138
9110 20:12:07.267226 DramC Write-DBI on
9111 20:12:07.270187 PER_BANK_REFRESH: Hybrid Mode
9112 20:12:07.273559 TX_TRACKING: ON
9113 20:12:07.280083 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9114 20:12:07.290181 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9115 20:12:07.296862 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9116 20:12:07.300083 [FAST_K] Save calibration result to emmc
9117 20:12:07.303375 sync common calibartion params.
9118 20:12:07.306537 sync cbt_mode0:1, 1:1
9119 20:12:07.306618 dram_init: ddr_geometry: 2
9120 20:12:07.309822 dram_init: ddr_geometry: 2
9121 20:12:07.313106 dram_init: ddr_geometry: 2
9122 20:12:07.313188 0:dram_rank_size:100000000
9123 20:12:07.316260 1:dram_rank_size:100000000
9124 20:12:07.323111 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9125 20:12:07.326265 DFS_SHUFFLE_HW_MODE: ON
9126 20:12:07.329688 dramc_set_vcore_voltage set vcore to 725000
9127 20:12:07.329795 Read voltage for 1600, 0
9128 20:12:07.333086 Vio18 = 0
9129 20:12:07.333195 Vcore = 725000
9130 20:12:07.333296 Vdram = 0
9131 20:12:07.336083 Vddq = 0
9132 20:12:07.336183 Vmddr = 0
9133 20:12:07.339577 switch to 3200 Mbps bootup
9134 20:12:07.339677 [DramcRunTimeConfig]
9135 20:12:07.339744 PHYPLL
9136 20:12:07.342962 DPM_CONTROL_AFTERK: ON
9137 20:12:07.346289 PER_BANK_REFRESH: ON
9138 20:12:07.346371 REFRESH_OVERHEAD_REDUCTION: ON
9139 20:12:07.349522 CMD_PICG_NEW_MODE: OFF
9140 20:12:07.353034 XRTWTW_NEW_MODE: ON
9141 20:12:07.353114 XRTRTR_NEW_MODE: ON
9142 20:12:07.356203 TX_TRACKING: ON
9143 20:12:07.356313 RDSEL_TRACKING: OFF
9144 20:12:07.359532 DQS Precalculation for DVFS: ON
9145 20:12:07.359614 RX_TRACKING: OFF
9146 20:12:07.363048 HW_GATING DBG: ON
9147 20:12:07.366040 ZQCS_ENABLE_LP4: ON
9148 20:12:07.366114 RX_PICG_NEW_MODE: ON
9149 20:12:07.369500 TX_PICG_NEW_MODE: ON
9150 20:12:07.369574 ENABLE_RX_DCM_DPHY: ON
9151 20:12:07.372722 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9152 20:12:07.376216 DUMMY_READ_FOR_TRACKING: OFF
9153 20:12:07.379418 !!! SPM_CONTROL_AFTERK: OFF
9154 20:12:07.382632 !!! SPM could not control APHY
9155 20:12:07.382734 IMPEDANCE_TRACKING: ON
9156 20:12:07.386346 TEMP_SENSOR: ON
9157 20:12:07.386424 HW_SAVE_FOR_SR: OFF
9158 20:12:07.389354 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9159 20:12:07.392710 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9160 20:12:07.395941 Read ODT Tracking: ON
9161 20:12:07.399321 Refresh Rate DeBounce: ON
9162 20:12:07.399450 DFS_NO_QUEUE_FLUSH: ON
9163 20:12:07.402578 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9164 20:12:07.405892 ENABLE_DFS_RUNTIME_MRW: OFF
9165 20:12:07.409306 DDR_RESERVE_NEW_MODE: ON
9166 20:12:07.409389 MR_CBT_SWITCH_FREQ: ON
9167 20:12:07.412544 =========================
9168 20:12:07.430855 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9169 20:12:07.434387 dram_init: ddr_geometry: 2
9170 20:12:07.452680 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9171 20:12:07.455902 dram_init: dram init end (result: 0)
9172 20:12:07.462209 DRAM-K: Full calibration passed in 24548 msecs
9173 20:12:07.465418 MRC: failed to locate region type 0.
9174 20:12:07.465540 DRAM rank0 size:0x100000000,
9175 20:12:07.468896 DRAM rank1 size=0x100000000
9176 20:12:07.478687 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9177 20:12:07.485345 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9178 20:12:07.492215 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9179 20:12:07.498689 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9180 20:12:07.502206 DRAM rank0 size:0x100000000,
9181 20:12:07.505384 DRAM rank1 size=0x100000000
9182 20:12:07.505464 CBMEM:
9183 20:12:07.508750 IMD: root @ 0xfffff000 254 entries.
9184 20:12:07.512054 IMD: root @ 0xffffec00 62 entries.
9185 20:12:07.515226 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9186 20:12:07.522139 WARNING: RO_VPD is uninitialized or empty.
9187 20:12:07.525189 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9188 20:12:07.532706 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9189 20:12:07.545245 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9190 20:12:07.556751 BS: romstage times (exec / console): total (unknown) / 24016 ms
9191 20:12:07.556888
9192 20:12:07.556995
9193 20:12:07.566941 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9194 20:12:07.570229 ARM64: Exception handlers installed.
9195 20:12:07.573258 ARM64: Testing exception
9196 20:12:07.576784 ARM64: Done test exception
9197 20:12:07.577026 Enumerating buses...
9198 20:12:07.580478 Show all devs... Before device enumeration.
9199 20:12:07.583646 Root Device: enabled 1
9200 20:12:07.587054 CPU_CLUSTER: 0: enabled 1
9201 20:12:07.587439 CPU: 00: enabled 1
9202 20:12:07.590297 Compare with tree...
9203 20:12:07.590679 Root Device: enabled 1
9204 20:12:07.593926 CPU_CLUSTER: 0: enabled 1
9205 20:12:07.596894 CPU: 00: enabled 1
9206 20:12:07.597317 Root Device scanning...
9207 20:12:07.600071 scan_static_bus for Root Device
9208 20:12:07.603241 CPU_CLUSTER: 0 enabled
9209 20:12:07.606936 scan_static_bus for Root Device done
9210 20:12:07.610136 scan_bus: bus Root Device finished in 8 msecs
9211 20:12:07.610571 done
9212 20:12:07.616634 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9213 20:12:07.620006 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9214 20:12:07.626776 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9215 20:12:07.630092 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9216 20:12:07.633181 Allocating resources...
9217 20:12:07.636415 Reading resources...
9218 20:12:07.639796 Root Device read_resources bus 0 link: 0
9219 20:12:07.639948 DRAM rank0 size:0x100000000,
9220 20:12:07.643294 DRAM rank1 size=0x100000000
9221 20:12:07.646546 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9222 20:12:07.649577 CPU: 00 missing read_resources
9223 20:12:07.653035 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9224 20:12:07.659807 Root Device read_resources bus 0 link: 0 done
9225 20:12:07.659902 Done reading resources.
9226 20:12:07.666229 Show resources in subtree (Root Device)...After reading.
9227 20:12:07.669542 Root Device child on link 0 CPU_CLUSTER: 0
9228 20:12:07.672718 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 20:12:07.682636 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 20:12:07.682715 CPU: 00
9231 20:12:07.685870 Root Device assign_resources, bus 0 link: 0
9232 20:12:07.689469 CPU_CLUSTER: 0 missing set_resources
9233 20:12:07.696126 Root Device assign_resources, bus 0 link: 0 done
9234 20:12:07.696208 Done setting resources.
9235 20:12:07.702672 Show resources in subtree (Root Device)...After assigning values.
9236 20:12:07.706087 Root Device child on link 0 CPU_CLUSTER: 0
9237 20:12:07.709251 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 20:12:07.719170 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 20:12:07.719306 CPU: 00
9240 20:12:07.722675 Done allocating resources.
9241 20:12:07.726071 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9242 20:12:07.729176 Enabling resources...
9243 20:12:07.729352 done.
9244 20:12:07.736038 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9245 20:12:07.736213 Initializing devices...
9246 20:12:07.739448 Root Device init
9247 20:12:07.739646 init hardware done!
9248 20:12:07.742502 0x00000018: ctrlr->caps
9249 20:12:07.746129 52.000 MHz: ctrlr->f_max
9250 20:12:07.746374 0.400 MHz: ctrlr->f_min
9251 20:12:07.749133 0x40ff8080: ctrlr->voltages
9252 20:12:07.749499 sclk: 390625
9253 20:12:07.752620 Bus Width = 1
9254 20:12:07.753086 sclk: 390625
9255 20:12:07.756042 Bus Width = 1
9256 20:12:07.756423 Early init status = 3
9257 20:12:07.762521 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9258 20:12:07.766230 in-header: 03 fc 00 00 01 00 00 00
9259 20:12:07.766648 in-data: 00
9260 20:12:07.772467 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9261 20:12:07.776059 in-header: 03 fd 00 00 00 00 00 00
9262 20:12:07.779714 in-data:
9263 20:12:07.782853 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9264 20:12:07.787207 in-header: 03 fc 00 00 01 00 00 00
9265 20:12:07.790602 in-data: 00
9266 20:12:07.793587 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9267 20:12:07.799516 in-header: 03 fd 00 00 00 00 00 00
9268 20:12:07.802653 in-data:
9269 20:12:07.806035 [SSUSB] Setting up USB HOST controller...
9270 20:12:07.809211 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9271 20:12:07.812842 [SSUSB] phy power-on done.
9272 20:12:07.816030 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9273 20:12:07.822399 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9274 20:12:07.825294 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9275 20:12:07.832010 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9276 20:12:07.838796 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9277 20:12:07.845217 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9278 20:12:07.852010 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9279 20:12:07.858588 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9280 20:12:07.861813 SPM: binary array size = 0x9dc
9281 20:12:07.865214 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9282 20:12:07.871910 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9283 20:12:07.878491 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9284 20:12:07.881832 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9285 20:12:07.888406 configure_display: Starting display init
9286 20:12:07.922391 anx7625_power_on_init: Init interface.
9287 20:12:07.925271 anx7625_disable_pd_protocol: Disabled PD feature.
9288 20:12:07.928688 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9289 20:12:07.956695 anx7625_start_dp_work: Secure OCM version=00
9290 20:12:07.959787 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9291 20:12:07.974462 sp_tx_get_edid_block: EDID Block = 1
9292 20:12:08.077168 Extracted contents:
9293 20:12:08.080506 header: 00 ff ff ff ff ff ff 00
9294 20:12:08.083967 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9295 20:12:08.087162 version: 01 04
9296 20:12:08.090525 basic params: 95 1f 11 78 0a
9297 20:12:08.093599 chroma info: 76 90 94 55 54 90 27 21 50 54
9298 20:12:08.097038 established: 00 00 00
9299 20:12:08.103489 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9300 20:12:08.110348 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9301 20:12:08.113410 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9302 20:12:08.120292 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9303 20:12:08.126972 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9304 20:12:08.129925 extensions: 00
9305 20:12:08.130016 checksum: fb
9306 20:12:08.130081
9307 20:12:08.133447 Manufacturer: IVO Model 57d Serial Number 0
9308 20:12:08.136529 Made week 0 of 2020
9309 20:12:08.139904 EDID version: 1.4
9310 20:12:08.140003 Digital display
9311 20:12:08.143136 6 bits per primary color channel
9312 20:12:08.143213 DisplayPort interface
9313 20:12:08.146565 Maximum image size: 31 cm x 17 cm
9314 20:12:08.149920 Gamma: 220%
9315 20:12:08.150001 Check DPMS levels
9316 20:12:08.153039 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9317 20:12:08.160173 First detailed timing is preferred timing
9318 20:12:08.160257 Established timings supported:
9319 20:12:08.163278 Standard timings supported:
9320 20:12:08.166582 Detailed timings
9321 20:12:08.169742 Hex of detail: 383680a07038204018303c0035ae10000019
9322 20:12:08.176313 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9323 20:12:08.179694 0780 0798 07c8 0820 hborder 0
9324 20:12:08.182881 0438 043b 0447 0458 vborder 0
9325 20:12:08.186439 -hsync -vsync
9326 20:12:08.186509 Did detailed timing
9327 20:12:08.192891 Hex of detail: 000000000000000000000000000000000000
9328 20:12:08.196561 Manufacturer-specified data, tag 0
9329 20:12:08.199674 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9330 20:12:08.203241 ASCII string: InfoVision
9331 20:12:08.206402 Hex of detail: 000000fe00523134304e574635205248200a
9332 20:12:08.209840 ASCII string: R140NWF5 RH
9333 20:12:08.209923 Checksum
9334 20:12:08.212977 Checksum: 0xfb (valid)
9335 20:12:08.216243 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9336 20:12:08.219702 DSI data_rate: 832800000 bps
9337 20:12:08.226416 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9338 20:12:08.229436 anx7625_parse_edid: pixelclock(138800).
9339 20:12:08.232900 hactive(1920), hsync(48), hfp(24), hbp(88)
9340 20:12:08.236307 vactive(1080), vsync(12), vfp(3), vbp(17)
9341 20:12:08.239436 anx7625_dsi_config: config dsi.
9342 20:12:08.245869 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9343 20:12:08.259333 anx7625_dsi_config: success to config DSI
9344 20:12:08.262583 anx7625_dp_start: MIPI phy setup OK.
9345 20:12:08.265869 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9346 20:12:08.269039 mtk_ddp_mode_set invalid vrefresh 60
9347 20:12:08.272585 main_disp_path_setup
9348 20:12:08.272665 ovl_layer_smi_id_en
9349 20:12:08.275863 ovl_layer_smi_id_en
9350 20:12:08.275945 ccorr_config
9351 20:12:08.276025 aal_config
9352 20:12:08.279157 gamma_config
9353 20:12:08.279239 postmask_config
9354 20:12:08.282274 dither_config
9355 20:12:08.285650 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9356 20:12:08.292193 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9357 20:12:08.295849 Root Device init finished in 553 msecs
9358 20:12:08.299140 CPU_CLUSTER: 0 init
9359 20:12:08.305407 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9360 20:12:08.312230 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9361 20:12:08.312311 APU_MBOX 0x190000b0 = 0x10001
9362 20:12:08.315385 APU_MBOX 0x190001b0 = 0x10001
9363 20:12:08.318712 APU_MBOX 0x190005b0 = 0x10001
9364 20:12:08.322160 APU_MBOX 0x190006b0 = 0x10001
9365 20:12:08.328755 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9366 20:12:08.338355 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9367 20:12:08.350560 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9368 20:12:08.357190 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9369 20:12:08.368896 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9370 20:12:08.378088 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9371 20:12:08.381515 CPU_CLUSTER: 0 init finished in 81 msecs
9372 20:12:08.384904 Devices initialized
9373 20:12:08.387995 Show all devs... After init.
9374 20:12:08.388076 Root Device: enabled 1
9375 20:12:08.391616 CPU_CLUSTER: 0: enabled 1
9376 20:12:08.394676 CPU: 00: enabled 1
9377 20:12:08.398012 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9378 20:12:08.401291 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9379 20:12:08.404548 ELOG: NV offset 0x57f000 size 0x1000
9380 20:12:08.411166 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9381 20:12:08.417773 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9382 20:12:08.421309 ELOG: Event(17) added with size 13 at 2024-03-03 20:12:09 UTC
9383 20:12:08.427798 out: cmd=0x121: 03 db 21 01 00 00 00 00
9384 20:12:08.431054 in-header: 03 74 00 00 2c 00 00 00
9385 20:12:08.440895 in-data: eb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9386 20:12:08.447696 ELOG: Event(A1) added with size 10 at 2024-03-03 20:12:09 UTC
9387 20:12:08.454350 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9388 20:12:08.460905 ELOG: Event(A0) added with size 9 at 2024-03-03 20:12:09 UTC
9389 20:12:08.464148 elog_add_boot_reason: Logged dev mode boot
9390 20:12:08.470806 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9391 20:12:08.470887 Finalize devices...
9392 20:12:08.474388 Devices finalized
9393 20:12:08.477309 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9394 20:12:08.480537 Writing coreboot table at 0xffe64000
9395 20:12:08.484153 0. 000000000010a000-0000000000113fff: RAMSTAGE
9396 20:12:08.487172 1. 0000000040000000-00000000400fffff: RAM
9397 20:12:08.494127 2. 0000000040100000-000000004032afff: RAMSTAGE
9398 20:12:08.497490 3. 000000004032b000-00000000545fffff: RAM
9399 20:12:08.500704 4. 0000000054600000-000000005465ffff: BL31
9400 20:12:08.503909 5. 0000000054660000-00000000ffe63fff: RAM
9401 20:12:08.510688 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9402 20:12:08.513827 7. 0000000100000000-000000023fffffff: RAM
9403 20:12:08.517243 Passing 5 GPIOs to payload:
9404 20:12:08.520862 NAME | PORT | POLARITY | VALUE
9405 20:12:08.523789 EC in RW | 0x000000aa | low | undefined
9406 20:12:08.530489 EC interrupt | 0x00000005 | low | undefined
9407 20:12:08.533826 TPM interrupt | 0x000000ab | high | undefined
9408 20:12:08.540367 SD card detect | 0x00000011 | high | undefined
9409 20:12:08.543924 speaker enable | 0x00000093 | high | undefined
9410 20:12:08.547414 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9411 20:12:08.550532 in-header: 03 f9 00 00 02 00 00 00
9412 20:12:08.553702 in-data: 02 00
9413 20:12:08.553783 ADC[4]: Raw value=896670 ID=7
9414 20:12:08.557193 ADC[3]: Raw value=213440 ID=1
9415 20:12:08.560607 RAM Code: 0x71
9416 20:12:08.560689 ADC[6]: Raw value=74352 ID=0
9417 20:12:08.563597 ADC[5]: Raw value=211590 ID=1
9418 20:12:08.566805 SKU Code: 0x1
9419 20:12:08.570311 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 18ab
9420 20:12:08.573703 coreboot table: 964 bytes.
9421 20:12:08.576864 IMD ROOT 0. 0xfffff000 0x00001000
9422 20:12:08.580204 IMD SMALL 1. 0xffffe000 0x00001000
9423 20:12:08.583757 RO MCACHE 2. 0xffffc000 0x00001104
9424 20:12:08.587066 CONSOLE 3. 0xfff7c000 0x00080000
9425 20:12:08.590293 FMAP 4. 0xfff7b000 0x00000452
9426 20:12:08.593371 TIME STAMP 5. 0xfff7a000 0x00000910
9427 20:12:08.596721 VBOOT WORK 6. 0xfff66000 0x00014000
9428 20:12:08.599948 RAMOOPS 7. 0xffe66000 0x00100000
9429 20:12:08.603315 COREBOOT 8. 0xffe64000 0x00002000
9430 20:12:08.606812 IMD small region:
9431 20:12:08.609863 IMD ROOT 0. 0xffffec00 0x00000400
9432 20:12:08.613355 VPD 1. 0xffffeb80 0x0000006c
9433 20:12:08.616833 MMC STATUS 2. 0xffffeb60 0x00000004
9434 20:12:08.619845 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9435 20:12:08.623326 Probing TPM: done!
9436 20:12:08.627095 Connected to device vid:did:rid of 1ae0:0028:00
9437 20:12:08.637096 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9438 20:12:08.640521 Initialized TPM device CR50 revision 0
9439 20:12:08.643983 Checking cr50 for pending updates
9440 20:12:08.647829 Reading cr50 TPM mode
9441 20:12:08.656810 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9442 20:12:08.663044 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9443 20:12:08.703500 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9444 20:12:08.706751 Checking segment from ROM address 0x40100000
9445 20:12:08.709980 Checking segment from ROM address 0x4010001c
9446 20:12:08.716488 Loading segment from ROM address 0x40100000
9447 20:12:08.716924 code (compression=0)
9448 20:12:08.726922 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9449 20:12:08.733588 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9450 20:12:08.734025 it's not compressed!
9451 20:12:08.740206 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9452 20:12:08.743397 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9453 20:12:08.764014 Loading segment from ROM address 0x4010001c
9454 20:12:08.764450 Entry Point 0x80000000
9455 20:12:08.767537 Loaded segments
9456 20:12:08.770624 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9457 20:12:08.777222 Jumping to boot code at 0x80000000(0xffe64000)
9458 20:12:08.784270 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9459 20:12:08.790697 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9460 20:12:08.798488 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9461 20:12:08.801889 Checking segment from ROM address 0x40100000
9462 20:12:08.805311 Checking segment from ROM address 0x4010001c
9463 20:12:08.811943 Loading segment from ROM address 0x40100000
9464 20:12:08.812362 code (compression=1)
9465 20:12:08.818457 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9466 20:12:08.828549 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9467 20:12:08.828974 using LZMA
9468 20:12:08.836847 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9469 20:12:08.843831 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9470 20:12:08.846991 Loading segment from ROM address 0x4010001c
9471 20:12:08.847408 Entry Point 0x54601000
9472 20:12:08.850191 Loaded segments
9473 20:12:08.853435 NOTICE: MT8192 bl31_setup
9474 20:12:08.860310 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9475 20:12:08.863869 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9476 20:12:08.866857 WARNING: region 0:
9477 20:12:08.870272 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 20:12:08.870727 WARNING: region 1:
9479 20:12:08.876914 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9480 20:12:08.880473 WARNING: region 2:
9481 20:12:08.883538 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9482 20:12:08.887002 WARNING: region 3:
9483 20:12:08.890451 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9484 20:12:08.893534 WARNING: region 4:
9485 20:12:08.900196 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9486 20:12:08.900614 WARNING: region 5:
9487 20:12:08.903477 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 20:12:08.906882 WARNING: region 6:
9489 20:12:08.910230 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 20:12:08.913523 WARNING: region 7:
9491 20:12:08.916989 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 20:12:08.923556 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9493 20:12:08.927286 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9494 20:12:08.930763 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9495 20:12:08.937184 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9496 20:12:08.940359 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9497 20:12:08.943738 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9498 20:12:08.950443 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9499 20:12:08.953636 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9500 20:12:08.957242 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9501 20:12:08.963722 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9502 20:12:08.967278 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9503 20:12:08.973926 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9504 20:12:08.976976 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9505 20:12:08.980355 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9506 20:12:08.986910 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9507 20:12:08.990628 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9508 20:12:08.993951 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9509 20:12:09.000698 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9510 20:12:09.003784 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9511 20:12:09.010306 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9512 20:12:09.013950 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9513 20:12:09.016955 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9514 20:12:09.023763 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9515 20:12:09.027212 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9516 20:12:09.033892 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9517 20:12:09.037103 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9518 20:12:09.040494 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9519 20:12:09.047016 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9520 20:12:09.050549 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9521 20:12:09.054061 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9522 20:12:09.060384 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9523 20:12:09.063637 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9524 20:12:09.070561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9525 20:12:09.073862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9526 20:12:09.077089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9527 20:12:09.080740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9528 20:12:09.083622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9529 20:12:09.090492 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9530 20:12:09.093249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9531 20:12:09.096861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9532 20:12:09.100147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9533 20:12:09.106769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9534 20:12:09.110225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9535 20:12:09.113662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9536 20:12:09.116596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9537 20:12:09.123411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9538 20:12:09.126906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9539 20:12:09.129806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9540 20:12:09.136401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9541 20:12:09.139868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9542 20:12:09.146555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9543 20:12:09.150064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9544 20:12:09.153414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9545 20:12:09.159902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9546 20:12:09.163283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9547 20:12:09.169918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9548 20:12:09.173062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9549 20:12:09.179918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9550 20:12:09.183076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9551 20:12:09.186422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9552 20:12:09.193294 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9553 20:12:09.196720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9554 20:12:09.203390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9555 20:12:09.206593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9556 20:12:09.213130 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9557 20:12:09.216726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9558 20:12:09.219899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9559 20:12:09.226868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9560 20:12:09.230056 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9561 20:12:09.236748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9562 20:12:09.239948 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9563 20:12:09.246573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9564 20:12:09.250111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9565 20:12:09.253157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9566 20:12:09.260106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9567 20:12:09.263466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9568 20:12:09.270018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9569 20:12:09.273546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9570 20:12:09.280095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9571 20:12:09.283549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9572 20:12:09.290150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9573 20:12:09.293322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9574 20:12:09.296798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9575 20:12:09.303396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9576 20:12:09.306732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9577 20:12:09.313266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9578 20:12:09.316690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9579 20:12:09.320084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9580 20:12:09.326858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9581 20:12:09.330065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9582 20:12:09.336646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9583 20:12:09.340302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9584 20:12:09.346925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9585 20:12:09.350137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9586 20:12:09.356940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9587 20:12:09.360235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9588 20:12:09.363545 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9589 20:12:09.366651 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9590 20:12:09.373295 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9591 20:12:09.376564 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9592 20:12:09.380303 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9593 20:12:09.386927 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9594 20:12:09.389928 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9595 20:12:09.393317 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9596 20:12:09.399905 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9597 20:12:09.403387 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9598 20:12:09.409909 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9599 20:12:09.413150 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9600 20:12:09.416668 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9601 20:12:09.423115 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9602 20:12:09.426435 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9603 20:12:09.433235 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9604 20:12:09.436338 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9605 20:12:09.439956 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9606 20:12:09.446492 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9607 20:12:09.449928 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9608 20:12:09.453055 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9609 20:12:09.459935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9610 20:12:09.463145 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9611 20:12:09.466820 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9612 20:12:09.473722 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9613 20:12:09.476618 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9614 20:12:09.479746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9615 20:12:09.483200 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9616 20:12:09.489877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9617 20:12:09.492971 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9618 20:12:09.499580 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9619 20:12:09.503093 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9620 20:12:09.506244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9621 20:12:09.512934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9622 20:12:09.516461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9623 20:12:09.519732 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9624 20:12:09.526368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9625 20:12:09.529752 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9626 20:12:09.536300 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9627 20:12:09.539597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9628 20:12:09.543071 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9629 20:12:09.549612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9630 20:12:09.552970 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9631 20:12:09.559663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9632 20:12:09.562892 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9633 20:12:09.566418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9634 20:12:09.573057 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9635 20:12:09.576063 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9636 20:12:09.582881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9637 20:12:09.586374 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9638 20:12:09.589563 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9639 20:12:09.596157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9640 20:12:09.599422 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9641 20:12:09.602821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9642 20:12:09.609397 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9643 20:12:09.612709 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9644 20:12:09.619390 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9645 20:12:09.622660 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9646 20:12:09.626089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9647 20:12:09.632879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9648 20:12:09.636171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9649 20:12:09.642644 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9650 20:12:09.645856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9651 20:12:09.649417 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9652 20:12:09.655985 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9653 20:12:09.659457 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9654 20:12:09.666083 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9655 20:12:09.669420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9656 20:12:09.672710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9657 20:12:09.679460 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9658 20:12:09.682675 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9659 20:12:09.685998 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9660 20:12:09.692467 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9661 20:12:09.696143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9662 20:12:09.702535 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9663 20:12:09.705798 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9664 20:12:09.709247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9665 20:12:09.715925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9666 20:12:09.719346 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9667 20:12:09.725822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9668 20:12:09.729245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9669 20:12:09.732453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9670 20:12:09.738946 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9671 20:12:09.742593 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9672 20:12:09.745654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9673 20:12:09.752296 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9674 20:12:09.755765 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9675 20:12:09.762438 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9676 20:12:09.765612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9677 20:12:09.768785 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9678 20:12:09.775652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9679 20:12:09.779106 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9680 20:12:09.785622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9681 20:12:09.789027 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9682 20:12:09.795507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9683 20:12:09.798770 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9684 20:12:09.802194 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9685 20:12:09.808885 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9686 20:12:09.811983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9687 20:12:09.818688 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9688 20:12:09.822109 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9689 20:12:09.828739 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9690 20:12:09.831840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9691 20:12:09.835176 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9692 20:12:09.841820 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9693 20:12:09.845090 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9694 20:12:09.851561 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9695 20:12:09.855192 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9696 20:12:09.858311 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9697 20:12:09.865151 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9698 20:12:09.868263 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9699 20:12:09.874954 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9700 20:12:09.878215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9701 20:12:09.884926 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9702 20:12:09.888299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9703 20:12:09.891715 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9704 20:12:09.898250 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9705 20:12:09.901211 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9706 20:12:09.907843 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9707 20:12:09.911437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9708 20:12:09.914598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9709 20:12:09.921067 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9710 20:12:09.924350 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9711 20:12:09.930923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9712 20:12:09.934292 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9713 20:12:09.941280 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9714 20:12:09.944311 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9715 20:12:09.947484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9716 20:12:09.954203 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9717 20:12:09.957700 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9718 20:12:09.963987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9719 20:12:09.967465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9720 20:12:09.973945 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9721 20:12:09.977254 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9722 20:12:09.980752 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9723 20:12:09.983896 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9724 20:12:09.987262 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9725 20:12:09.993906 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9726 20:12:09.997180 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9727 20:12:10.000411 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9728 20:12:10.007024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9729 20:12:10.010600 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9730 20:12:10.013942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9731 20:12:10.020544 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9732 20:12:10.024051 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9733 20:12:10.030469 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9734 20:12:10.033951 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9735 20:12:10.037300 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9736 20:12:10.043963 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9737 20:12:10.047177 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9738 20:12:10.050629 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9739 20:12:10.057128 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9740 20:12:10.060216 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9741 20:12:10.063923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9742 20:12:10.070488 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9743 20:12:10.073664 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9744 20:12:10.080400 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9745 20:12:10.083456 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9746 20:12:10.086977 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9747 20:12:10.093585 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9748 20:12:10.097015 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9749 20:12:10.103727 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9750 20:12:10.106870 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9751 20:12:10.110026 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9752 20:12:10.116856 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9753 20:12:10.119817 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9754 20:12:10.123318 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9755 20:12:10.129864 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9756 20:12:10.133407 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9757 20:12:10.136482 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9758 20:12:10.143073 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9759 20:12:10.146453 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9760 20:12:10.149770 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9761 20:12:10.156139 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9762 20:12:10.159450 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9763 20:12:10.163021 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9764 20:12:10.166032 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9765 20:12:10.169641 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9766 20:12:10.176194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9767 20:12:10.179619 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9768 20:12:10.182965 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9769 20:12:10.189446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9770 20:12:10.192827 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9771 20:12:10.196131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9772 20:12:10.199435 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9773 20:12:10.205929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9774 20:12:10.209397 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9775 20:12:10.216105 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9776 20:12:10.219175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9777 20:12:10.222402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9778 20:12:10.229095 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9779 20:12:10.232529 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9780 20:12:10.239382 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9781 20:12:10.242529 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9782 20:12:10.249099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9783 20:12:10.252117 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9784 20:12:10.255692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9785 20:12:10.262397 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9786 20:12:10.265351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9787 20:12:10.271965 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9788 20:12:10.275407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9789 20:12:10.278832 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9790 20:12:10.285395 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9791 20:12:10.288608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9792 20:12:10.295317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9793 20:12:10.298481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9794 20:12:10.305120 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9795 20:12:10.308562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9796 20:12:10.311690 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9797 20:12:10.318197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9798 20:12:10.321590 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9799 20:12:10.328087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9800 20:12:10.331472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9801 20:12:10.334831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9802 20:12:10.341562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9803 20:12:10.344637 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9804 20:12:10.351070 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9805 20:12:10.354505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9806 20:12:10.361076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9807 20:12:10.364719 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9808 20:12:10.367626 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9809 20:12:10.374554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9810 20:12:10.377642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9811 20:12:10.384362 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9812 20:12:10.387685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9813 20:12:10.390755 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9814 20:12:10.397550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9815 20:12:10.400952 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9816 20:12:10.407315 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9817 20:12:10.410541 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9818 20:12:10.417394 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9819 20:12:10.420660 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9820 20:12:10.424122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9821 20:12:10.430623 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9822 20:12:10.434036 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9823 20:12:10.440619 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9824 20:12:10.443623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9825 20:12:10.447228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9826 20:12:10.453907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9827 20:12:10.456782 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9828 20:12:10.463534 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9829 20:12:10.466849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9830 20:12:10.470102 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9831 20:12:10.476756 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9832 20:12:10.479966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9833 20:12:10.486534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9834 20:12:10.490046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9835 20:12:10.496928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9836 20:12:10.500089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9837 20:12:10.503302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9838 20:12:10.509942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9839 20:12:10.513305 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9840 20:12:10.520177 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9841 20:12:10.523330 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9842 20:12:10.526658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9843 20:12:10.533143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9844 20:12:10.536606 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9845 20:12:10.543147 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9846 20:12:10.546622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9847 20:12:10.549665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9848 20:12:10.556257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9849 20:12:10.559688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9850 20:12:10.566307 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9851 20:12:10.569893 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9852 20:12:10.576444 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9853 20:12:10.579827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9854 20:12:10.583079 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9855 20:12:10.589611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9856 20:12:10.592889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9857 20:12:10.599443 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9858 20:12:10.602898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9859 20:12:10.609618 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9860 20:12:10.612672 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9861 20:12:10.619488 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9862 20:12:10.622808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9863 20:12:10.625925 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9864 20:12:10.632595 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9865 20:12:10.636078 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9866 20:12:10.642632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9867 20:12:10.645768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9868 20:12:10.652705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9869 20:12:10.656018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9870 20:12:10.662429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9871 20:12:10.666011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9872 20:12:10.669049 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9873 20:12:10.675723 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9874 20:12:10.679169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9875 20:12:10.685756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9876 20:12:10.689024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9877 20:12:10.692785 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9878 20:12:10.699226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9879 20:12:10.702401 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9880 20:12:10.709009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9881 20:12:10.712500 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9882 20:12:10.718879 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9883 20:12:10.722335 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9884 20:12:10.728996 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9885 20:12:10.732149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9886 20:12:10.735762 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9887 20:12:10.742324 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9888 20:12:10.745541 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9889 20:12:10.752314 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9890 20:12:10.755461 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9891 20:12:10.762210 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9892 20:12:10.765234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9893 20:12:10.768746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9894 20:12:10.775386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9895 20:12:10.778504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9896 20:12:10.785149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9897 20:12:10.788648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9898 20:12:10.795458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9899 20:12:10.798389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9900 20:12:10.804993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9901 20:12:10.808451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9902 20:12:10.815121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9903 20:12:10.818424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9904 20:12:10.825307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9905 20:12:10.828598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9906 20:12:10.835176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9907 20:12:10.838553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9908 20:12:10.841779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9909 20:12:10.848393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9910 20:12:10.851749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9911 20:12:10.858407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9912 20:12:10.861756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9913 20:12:10.868177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9914 20:12:10.871624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9915 20:12:10.878103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9916 20:12:10.881640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9917 20:12:10.888041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9918 20:12:10.891615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9919 20:12:10.898182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9920 20:12:10.901633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9921 20:12:10.908244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9922 20:12:10.911600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9923 20:12:10.918132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9924 20:12:10.921275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9925 20:12:10.928086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9926 20:12:10.931470 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9927 20:12:10.934502 INFO: [APUAPC] vio 0
9928 20:12:10.938024 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9929 20:12:10.944453 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9930 20:12:10.948018 INFO: [APUAPC] D0_APC_0: 0x400510
9931 20:12:10.951129 INFO: [APUAPC] D0_APC_1: 0x0
9932 20:12:10.954523 INFO: [APUAPC] D0_APC_2: 0x1540
9933 20:12:10.954620 INFO: [APUAPC] D0_APC_3: 0x0
9934 20:12:10.957801 INFO: [APUAPC] D1_APC_0: 0xffffffff
9935 20:12:10.961019 INFO: [APUAPC] D1_APC_1: 0xffffffff
9936 20:12:10.964399 INFO: [APUAPC] D1_APC_2: 0x3fffff
9937 20:12:10.967987 INFO: [APUAPC] D1_APC_3: 0x0
9938 20:12:10.971026 INFO: [APUAPC] D2_APC_0: 0xffffffff
9939 20:12:10.974355 INFO: [APUAPC] D2_APC_1: 0xffffffff
9940 20:12:10.977697 INFO: [APUAPC] D2_APC_2: 0x3fffff
9941 20:12:10.981045 INFO: [APUAPC] D2_APC_3: 0x0
9942 20:12:10.984377 INFO: [APUAPC] D3_APC_0: 0xffffffff
9943 20:12:10.987501 INFO: [APUAPC] D3_APC_1: 0xffffffff
9944 20:12:10.991027 INFO: [APUAPC] D3_APC_2: 0x3fffff
9945 20:12:10.994441 INFO: [APUAPC] D3_APC_3: 0x0
9946 20:12:10.997627 INFO: [APUAPC] D4_APC_0: 0xffffffff
9947 20:12:11.000774 INFO: [APUAPC] D4_APC_1: 0xffffffff
9948 20:12:11.004222 INFO: [APUAPC] D4_APC_2: 0x3fffff
9949 20:12:11.007581 INFO: [APUAPC] D4_APC_3: 0x0
9950 20:12:11.010682 INFO: [APUAPC] D5_APC_0: 0xffffffff
9951 20:12:11.014135 INFO: [APUAPC] D5_APC_1: 0xffffffff
9952 20:12:11.017799 INFO: [APUAPC] D5_APC_2: 0x3fffff
9953 20:12:11.020714 INFO: [APUAPC] D5_APC_3: 0x0
9954 20:12:11.024272 INFO: [APUAPC] D6_APC_0: 0xffffffff
9955 20:12:11.027280 INFO: [APUAPC] D6_APC_1: 0xffffffff
9956 20:12:11.030860 INFO: [APUAPC] D6_APC_2: 0x3fffff
9957 20:12:11.034175 INFO: [APUAPC] D6_APC_3: 0x0
9958 20:12:11.037403 INFO: [APUAPC] D7_APC_0: 0xffffffff
9959 20:12:11.040536 INFO: [APUAPC] D7_APC_1: 0xffffffff
9960 20:12:11.043659 INFO: [APUAPC] D7_APC_2: 0x3fffff
9961 20:12:11.047302 INFO: [APUAPC] D7_APC_3: 0x0
9962 20:12:11.050547 INFO: [APUAPC] D8_APC_0: 0xffffffff
9963 20:12:11.053754 INFO: [APUAPC] D8_APC_1: 0xffffffff
9964 20:12:11.056897 INFO: [APUAPC] D8_APC_2: 0x3fffff
9965 20:12:11.060559 INFO: [APUAPC] D8_APC_3: 0x0
9966 20:12:11.063632 INFO: [APUAPC] D9_APC_0: 0xffffffff
9967 20:12:11.067189 INFO: [APUAPC] D9_APC_1: 0xffffffff
9968 20:12:11.070187 INFO: [APUAPC] D9_APC_2: 0x3fffff
9969 20:12:11.073725 INFO: [APUAPC] D9_APC_3: 0x0
9970 20:12:11.077047 INFO: [APUAPC] D10_APC_0: 0xffffffff
9971 20:12:11.080204 INFO: [APUAPC] D10_APC_1: 0xffffffff
9972 20:12:11.083675 INFO: [APUAPC] D10_APC_2: 0x3fffff
9973 20:12:11.086929 INFO: [APUAPC] D10_APC_3: 0x0
9974 20:12:11.090056 INFO: [APUAPC] D11_APC_0: 0xffffffff
9975 20:12:11.093353 INFO: [APUAPC] D11_APC_1: 0xffffffff
9976 20:12:11.096970 INFO: [APUAPC] D11_APC_2: 0x3fffff
9977 20:12:11.099943 INFO: [APUAPC] D11_APC_3: 0x0
9978 20:12:11.103315 INFO: [APUAPC] D12_APC_0: 0xffffffff
9979 20:12:11.106469 INFO: [APUAPC] D12_APC_1: 0xffffffff
9980 20:12:11.109896 INFO: [APUAPC] D12_APC_2: 0x3fffff
9981 20:12:11.113217 INFO: [APUAPC] D12_APC_3: 0x0
9982 20:12:11.116358 INFO: [APUAPC] D13_APC_0: 0xffffffff
9983 20:12:11.119871 INFO: [APUAPC] D13_APC_1: 0xffffffff
9984 20:12:11.123119 INFO: [APUAPC] D13_APC_2: 0x3fffff
9985 20:12:11.126528 INFO: [APUAPC] D13_APC_3: 0x0
9986 20:12:11.129644 INFO: [APUAPC] D14_APC_0: 0xffffffff
9987 20:12:11.133025 INFO: [APUAPC] D14_APC_1: 0xffffffff
9988 20:12:11.136168 INFO: [APUAPC] D14_APC_2: 0x3fffff
9989 20:12:11.139357 INFO: [APUAPC] D14_APC_3: 0x0
9990 20:12:11.142960 INFO: [APUAPC] D15_APC_0: 0xffffffff
9991 20:12:11.145924 INFO: [APUAPC] D15_APC_1: 0xffffffff
9992 20:12:11.149414 INFO: [APUAPC] D15_APC_2: 0x3fffff
9993 20:12:11.152587 INFO: [APUAPC] D15_APC_3: 0x0
9994 20:12:11.156075 INFO: [APUAPC] APC_CON: 0x4
9995 20:12:11.159313 INFO: [NOCDAPC] D0_APC_0: 0x0
9996 20:12:11.162489 INFO: [NOCDAPC] D0_APC_1: 0x0
9997 20:12:11.165887 INFO: [NOCDAPC] D1_APC_0: 0x0
9998 20:12:11.169270 INFO: [NOCDAPC] D1_APC_1: 0xfff
9999 20:12:11.169354 INFO: [NOCDAPC] D2_APC_0: 0x0
10000 20:12:11.172414 INFO: [NOCDAPC] D2_APC_1: 0xfff
10001 20:12:11.175816 INFO: [NOCDAPC] D3_APC_0: 0x0
10002 20:12:11.179442 INFO: [NOCDAPC] D3_APC_1: 0xfff
10003 20:12:11.182457 INFO: [NOCDAPC] D4_APC_0: 0x0
10004 20:12:11.185773 INFO: [NOCDAPC] D4_APC_1: 0xfff
10005 20:12:11.189023 INFO: [NOCDAPC] D5_APC_0: 0x0
10006 20:12:11.192190 INFO: [NOCDAPC] D5_APC_1: 0xfff
10007 20:12:11.195695 INFO: [NOCDAPC] D6_APC_0: 0x0
10008 20:12:11.199038 INFO: [NOCDAPC] D6_APC_1: 0xfff
10009 20:12:11.202413 INFO: [NOCDAPC] D7_APC_0: 0x0
10010 20:12:11.202496 INFO: [NOCDAPC] D7_APC_1: 0xfff
10011 20:12:11.205832 INFO: [NOCDAPC] D8_APC_0: 0x0
10012 20:12:11.209011 INFO: [NOCDAPC] D8_APC_1: 0xfff
10013 20:12:11.212257 INFO: [NOCDAPC] D9_APC_0: 0x0
10014 20:12:11.215418 INFO: [NOCDAPC] D9_APC_1: 0xfff
10015 20:12:11.218888 INFO: [NOCDAPC] D10_APC_0: 0x0
10016 20:12:11.222040 INFO: [NOCDAPC] D10_APC_1: 0xfff
10017 20:12:11.225289 INFO: [NOCDAPC] D11_APC_0: 0x0
10018 20:12:11.228811 INFO: [NOCDAPC] D11_APC_1: 0xfff
10019 20:12:11.232088 INFO: [NOCDAPC] D12_APC_0: 0x0
10020 20:12:11.235478 INFO: [NOCDAPC] D12_APC_1: 0xfff
10021 20:12:11.238649 INFO: [NOCDAPC] D13_APC_0: 0x0
10022 20:12:11.242246 INFO: [NOCDAPC] D13_APC_1: 0xfff
10023 20:12:11.245234 INFO: [NOCDAPC] D14_APC_0: 0x0
10024 20:12:11.245322 INFO: [NOCDAPC] D14_APC_1: 0xfff
10025 20:12:11.248609 INFO: [NOCDAPC] D15_APC_0: 0x0
10026 20:12:11.252050 INFO: [NOCDAPC] D15_APC_1: 0xfff
10027 20:12:11.255452 INFO: [NOCDAPC] APC_CON: 0x4
10028 20:12:11.258562 INFO: [APUAPC] set_apusys_apc done
10029 20:12:11.262097 INFO: [DEVAPC] devapc_init done
10030 20:12:11.265025 INFO: GICv3 without legacy support detected.
10031 20:12:11.271646 INFO: ARM GICv3 driver initialized in EL3
10032 20:12:11.275065 INFO: Maximum SPI INTID supported: 639
10033 20:12:11.278386 INFO: BL31: Initializing runtime services
10034 20:12:11.285089 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10035 20:12:11.288334 INFO: SPM: enable CPC mode
10036 20:12:11.291916 INFO: mcdi ready for mcusys-off-idle and system suspend
10037 20:12:11.298423 INFO: BL31: Preparing for EL3 exit to normal world
10038 20:12:11.301665 INFO: Entry point address = 0x80000000
10039 20:12:11.301772 INFO: SPSR = 0x8
10040 20:12:11.307930
10041 20:12:11.308011
10042 20:12:11.308075
10043 20:12:11.311339 Starting depthcharge on Spherion...
10044 20:12:11.311420
10045 20:12:11.311485 Wipe memory regions:
10046 20:12:11.311545
10047 20:12:11.312264 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10048 20:12:11.312369 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10049 20:12:11.312455 Setting prompt string to ['asurada:']
10050 20:12:11.312536 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10051 20:12:11.314580 [0x00000040000000, 0x00000054600000)
10052 20:12:11.437097
10053 20:12:11.437224 [0x00000054660000, 0x00000080000000)
10054 20:12:11.697724
10055 20:12:11.697858 [0x000000821a7280, 0x000000ffe64000)
10056 20:12:12.442522
10057 20:12:12.442656 [0x00000100000000, 0x00000240000000)
10058 20:12:14.333159
10059 20:12:14.336141 Initializing XHCI USB controller at 0x11200000.
10060 20:12:15.374873
10061 20:12:15.377873 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10062 20:12:15.377992
10063 20:12:15.378056
10064 20:12:15.378117
10065 20:12:15.378399 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 20:12:15.478766 asurada: tftpboot 192.168.201.1 12928138/tftp-deploy-9cf_hi8c/kernel/image.itb 12928138/tftp-deploy-9cf_hi8c/kernel/cmdline
10068 20:12:15.478936 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 20:12:15.479025 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10070 20:12:15.482831 tftpboot 192.168.201.1 12928138/tftp-deploy-9cf_hi8c/kernel/image.itp-deploy-9cf_hi8c/kernel/cmdline
10071 20:12:15.482916
10072 20:12:15.482985 Waiting for link
10073 20:12:15.643522
10074 20:12:15.643654 R8152: Initializing
10075 20:12:15.643722
10076 20:12:15.646580 Version 6 (ocp_data = 5c30)
10077 20:12:15.646662
10078 20:12:15.649734 R8152: Done initializing
10079 20:12:15.649816
10080 20:12:15.649881 Adding net device
10081 20:12:17.679525
10082 20:12:17.679676 done.
10083 20:12:17.679745
10084 20:12:17.679806 MAC: 00:24:32:30:78:ff
10085 20:12:17.679866
10086 20:12:17.682810 Sending DHCP discover... done.
10087 20:12:17.682893
10088 20:12:17.686362 Waiting for reply... done.
10089 20:12:17.686444
10090 20:12:17.689581 Sending DHCP request... done.
10091 20:12:17.689689
10092 20:12:17.693172 Waiting for reply... done.
10093 20:12:17.693253
10094 20:12:17.693335 My ip is 192.168.201.21
10095 20:12:17.693452
10096 20:12:17.696701 The DHCP server ip is 192.168.201.1
10097 20:12:17.696783
10098 20:12:17.703262 TFTP server IP predefined by user: 192.168.201.1
10099 20:12:17.703344
10100 20:12:17.709826 Bootfile predefined by user: 12928138/tftp-deploy-9cf_hi8c/kernel/image.itb
10101 20:12:17.709908
10102 20:12:17.713251 Sending tftp read request... done.
10103 20:12:17.713333
10104 20:12:17.716902 Waiting for the transfer...
10105 20:12:17.716983
10106 20:12:18.238287 00000000 ################################################################
10107 20:12:18.238443
10108 20:12:18.763802 00080000 ################################################################
10109 20:12:18.763938
10110 20:12:19.281672 00100000 ################################################################
10111 20:12:19.281850
10112 20:12:19.803185 00180000 ################################################################
10113 20:12:19.803317
10114 20:12:20.326447 00200000 ################################################################
10115 20:12:20.326584
10116 20:12:20.858456 00280000 ################################################################
10117 20:12:20.858603
10118 20:12:21.376887 00300000 ################################################################
10119 20:12:21.377030
10120 20:12:21.904115 00380000 ################################################################
10121 20:12:21.904285
10122 20:12:22.425645 00400000 ################################################################
10123 20:12:22.425799
10124 20:12:22.961111 00480000 ################################################################
10125 20:12:22.961259
10126 20:12:23.496960 00500000 ################################################################
10127 20:12:23.497106
10128 20:12:24.020305 00580000 ################################################################
10129 20:12:24.020471
10130 20:12:24.550379 00600000 ################################################################
10131 20:12:24.550528
10132 20:12:25.097531 00680000 ################################################################
10133 20:12:25.097670
10134 20:12:25.632416 00700000 ################################################################
10135 20:12:25.632573
10136 20:12:26.181681 00780000 ################################################################
10137 20:12:26.181822
10138 20:12:26.749228 00800000 ################################################################
10139 20:12:26.749411
10140 20:12:27.282218 00880000 ################################################################
10141 20:12:27.282352
10142 20:12:27.819156 00900000 ################################################################
10143 20:12:27.819365
10144 20:12:28.344208 00980000 ################################################################
10145 20:12:28.344346
10146 20:12:28.873735 00a00000 ################################################################
10147 20:12:28.873878
10148 20:12:29.393922 00a80000 ################################################################
10149 20:12:29.394052
10150 20:12:29.950576 00b00000 ################################################################
10151 20:12:29.950717
10152 20:12:30.488678 00b80000 ################################################################
10153 20:12:30.488810
10154 20:12:31.041010 00c00000 ################################################################
10155 20:12:31.041157
10156 20:12:31.602779 00c80000 ################################################################
10157 20:12:31.602931
10158 20:12:32.145140 00d00000 ################################################################
10159 20:12:32.145290
10160 20:12:32.684521 00d80000 ################################################################
10161 20:12:32.684673
10162 20:12:33.240050 00e00000 ################################################################
10163 20:12:33.240194
10164 20:12:33.788451 00e80000 ################################################################
10165 20:12:33.788598
10166 20:12:34.341055 00f00000 ################################################################
10167 20:12:34.341190
10168 20:12:34.880955 00f80000 ################################################################
10169 20:12:34.881097
10170 20:12:35.425726 01000000 ################################################################
10171 20:12:35.425869
10172 20:12:36.005954 01080000 ################################################################
10173 20:12:36.006092
10174 20:12:36.569007 01100000 ################################################################
10175 20:12:36.569161
10176 20:12:37.141323 01180000 ################################################################
10177 20:12:37.141471
10178 20:12:37.718415 01200000 ################################################################
10179 20:12:37.718561
10180 20:12:38.284018 01280000 ################################################################
10181 20:12:38.284164
10182 20:12:38.841933 01300000 ################################################################
10183 20:12:38.842083
10184 20:12:39.417191 01380000 ################################################################
10185 20:12:39.417337
10186 20:12:39.976263 01400000 ################################################################
10187 20:12:39.976412
10188 20:12:40.506403 01480000 ################################################################
10189 20:12:40.506545
10190 20:12:41.042462 01500000 ################################################################
10191 20:12:41.042610
10192 20:12:41.591639 01580000 ################################################################
10193 20:12:41.591778
10194 20:12:42.152500 01600000 ################################################################
10195 20:12:42.152684
10196 20:12:42.706650 01680000 ################################################################
10197 20:12:42.706781
10198 20:12:43.252322 01700000 ################################################################
10199 20:12:43.252485
10200 20:12:43.809400 01780000 ################################################################
10201 20:12:43.809599
10202 20:12:44.358866 01800000 ################################################################
10203 20:12:44.359017
10204 20:12:44.901393 01880000 ################################################################
10205 20:12:44.901558
10206 20:12:45.458342 01900000 ################################################################
10207 20:12:45.458487
10208 20:12:46.023312 01980000 ################################################################
10209 20:12:46.023454
10210 20:12:46.582269 01a00000 ################################################################
10211 20:12:46.582406
10212 20:12:47.122510 01a80000 ################################################################
10213 20:12:47.122656
10214 20:12:47.666317 01b00000 ################################################################
10215 20:12:47.666456
10216 20:12:48.208266 01b80000 ################################################################
10217 20:12:48.208418
10218 20:12:48.758520 01c00000 ################################################################
10219 20:12:48.758662
10220 20:12:49.425749 01c80000 ################################################################
10221 20:12:49.426384
10222 20:12:50.079776 01d00000 ################################################################
10223 20:12:50.079920
10224 20:12:50.657851 01d80000 ################################################################
10225 20:12:50.658002
10226 20:12:51.222638 01e00000 ################################################################
10227 20:12:51.222776
10228 20:12:51.788280 01e80000 ################################################################
10229 20:12:51.788461
10230 20:12:52.317714 01f00000 ################################################################
10231 20:12:52.317853
10232 20:12:52.821492 01f80000 ########################################################### done.
10233 20:12:52.821639
10234 20:12:52.825033 The bootfile was 33511026 bytes long.
10235 20:12:52.825147
10236 20:12:52.828113 Sending tftp read request... done.
10237 20:12:52.828223
10238 20:12:52.828317 Waiting for the transfer...
10239 20:12:52.828413
10240 20:12:52.831536 00000000 # done.
10241 20:12:52.831666
10242 20:12:52.837863 Command line loaded dynamically from TFTP file: 12928138/tftp-deploy-9cf_hi8c/kernel/cmdline
10243 20:12:52.837946
10244 20:12:52.851326 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10245 20:12:52.851408
10246 20:12:52.854701 Loading FIT.
10247 20:12:52.854783
10248 20:12:52.858182 Image ramdisk-1 has 21401675 bytes.
10249 20:12:52.858264
10250 20:12:52.861375 Image fdt-1 has 47278 bytes.
10251 20:12:52.861459
10252 20:12:52.861551 Image kernel-1 has 12060038 bytes.
10253 20:12:52.864444
10254 20:12:52.871127 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10255 20:12:52.871209
10256 20:12:52.890752 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10257 20:12:52.890869
10258 20:12:52.894474 Choosing best match conf-1 for compat google,spherion-rev2.
10259 20:12:52.899035
10260 20:12:52.926242 Connected to device vid:did:rid of 1ae0:0028:00
10261 20:12:52.941550
10262 20:12:52.944964 tpm_get_response: command 0x17b, return code 0x0
10263 20:12:52.945429
10264 20:12:52.947959 ec_init: CrosEC protocol v3 supported (256, 248)
10265 20:12:52.952123
10266 20:12:52.955499 tpm_cleanup: add release locality here.
10267 20:12:52.955963
10268 20:12:52.956330 Shutting down all USB controllers.
10269 20:12:52.958524
10270 20:12:52.958944 Removing current net device
10271 20:12:52.959278
10272 20:12:52.965539 Exiting depthcharge with code 4 at timestamp: 70943331
10273 20:12:52.965962
10274 20:12:52.968849 LZMA decompressing kernel-1 to 0x821a6718
10275 20:12:52.969270
10276 20:12:52.972022 LZMA decompressing kernel-1 to 0x40000000
10277 20:12:54.470946
10278 20:12:54.471093 jumping to kernel
10279 20:12:54.471573 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10280 20:12:54.471675 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10281 20:12:54.471756 Setting prompt string to ['Linux version [0-9]']
10282 20:12:54.471836 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10283 20:12:54.471905 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10284 20:12:54.552894
10285 20:12:54.556215 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10286 20:12:54.559704 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10287 20:12:54.559829 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10288 20:12:54.559934 Setting prompt string to []
10289 20:12:54.560049 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10290 20:12:54.560161 Using line separator: #'\n'#
10291 20:12:54.560249 No login prompt set.
10292 20:12:54.560314 Parsing kernel messages
10293 20:12:54.560375 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10294 20:12:54.560549 [login-action] Waiting for messages, (timeout 00:03:42)
10295 20:12:54.560645 Waiting using forced prompt support (timeout 00:01:51)
10296 20:12:54.579261 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10297 20:12:54.582780 [ 0.000000] random: crng init done
10298 20:12:54.589446 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10299 20:12:54.592676 [ 0.000000] efi: UEFI not found.
10300 20:12:54.599177 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10301 20:12:54.609297 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10302 20:12:54.619187 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10303 20:12:54.625818 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10304 20:12:54.632273 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10305 20:12:54.638992 [ 0.000000] printk: bootconsole [mtk8250] enabled
10306 20:12:54.645473 [ 0.000000] NUMA: No NUMA configuration found
10307 20:12:54.652320 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10308 20:12:54.655382 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10309 20:12:54.658949 [ 0.000000] Zone ranges:
10310 20:12:54.665374 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10311 20:12:54.668879 [ 0.000000] DMA32 empty
10312 20:12:54.675551 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10313 20:12:54.678737 [ 0.000000] Movable zone start for each node
10314 20:12:54.682194 [ 0.000000] Early memory node ranges
10315 20:12:54.688639 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10316 20:12:54.695210 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10317 20:12:54.702225 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10318 20:12:54.708942 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10319 20:12:54.715359 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10320 20:12:54.721597 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10321 20:12:54.777952 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10322 20:12:54.784698 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10323 20:12:54.791235 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10324 20:12:54.794601 [ 0.000000] psci: probing for conduit method from DT.
10325 20:12:54.800983 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10326 20:12:54.804307 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10327 20:12:54.811024 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10328 20:12:54.814166 [ 0.000000] psci: SMC Calling Convention v1.2
10329 20:12:54.820741 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10330 20:12:54.824184 [ 0.000000] Detected VIPT I-cache on CPU0
10331 20:12:54.831279 [ 0.000000] CPU features: detected: GIC system register CPU interface
10332 20:12:54.837510 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10333 20:12:54.844140 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10334 20:12:54.850757 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10335 20:12:54.857262 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10336 20:12:54.867233 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10337 20:12:54.870526 [ 0.000000] alternatives: applying boot alternatives
10338 20:12:54.877060 [ 0.000000] Fallback order for Node 0: 0
10339 20:12:54.883775 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10340 20:12:54.887259 [ 0.000000] Policy zone: Normal
10341 20:12:54.900462 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10342 20:12:54.910436 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10343 20:12:54.922373 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10344 20:12:54.932138 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10345 20:12:54.938805 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10346 20:12:54.941911 <6>[ 0.000000] software IO TLB: area num 8.
10347 20:12:54.998601 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10348 20:12:55.148359 <6>[ 0.000000] Memory: 7946296K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 406472K reserved, 32768K cma-reserved)
10349 20:12:55.154774 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10350 20:12:55.161584 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10351 20:12:55.164572 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10352 20:12:55.171448 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10353 20:12:55.177932 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10354 20:12:55.181342 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10355 20:12:55.191181 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10356 20:12:55.197967 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10357 20:12:55.204225 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10358 20:12:55.210956 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10359 20:12:55.214369 <6>[ 0.000000] GICv3: 608 SPIs implemented
10360 20:12:55.217825 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10361 20:12:55.224350 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10362 20:12:55.227848 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10363 20:12:55.234283 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10364 20:12:55.247627 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10365 20:12:55.257443 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10366 20:12:55.267280 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10367 20:12:55.274506 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10368 20:12:55.287881 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10369 20:12:55.294582 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10370 20:12:55.301102 <6>[ 0.009182] Console: colour dummy device 80x25
10371 20:12:55.311084 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10372 20:12:55.317664 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10373 20:12:55.320829 <6>[ 0.029227] LSM: Security Framework initializing
10374 20:12:55.327868 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10375 20:12:55.337462 <6>[ 0.041980] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10376 20:12:55.344118 <6>[ 0.051444] cblist_init_generic: Setting adjustable number of callback queues.
10377 20:12:55.350926 <6>[ 0.058932] cblist_init_generic: Setting shift to 3 and lim to 1.
10378 20:12:55.360833 <6>[ 0.065270] cblist_init_generic: Setting adjustable number of callback queues.
10379 20:12:55.367232 <6>[ 0.072744] cblist_init_generic: Setting shift to 3 and lim to 1.
10380 20:12:55.370795 <6>[ 0.079223] rcu: Hierarchical SRCU implementation.
10381 20:12:55.377357 <6>[ 0.079225] rcu: Max phase no-delay instances is 1000.
10382 20:12:55.383879 <6>[ 0.079249] printk: bootconsole [mtk8250] printing thread started
10383 20:12:55.390464 <6>[ 0.097574] EFI services will not be available.
10384 20:12:55.394032 <6>[ 0.097776] smp: Bringing up secondary CPUs ...
10385 20:12:55.397059 <6>[ 0.098083] Detected VIPT I-cache on CPU1
10386 20:12:55.406976 <6>[ 0.098149] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10387 20:12:55.413377 <6>[ 0.098180] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10388 20:12:55.422968 <6>[ 0.126082] Detected VIPT I-cache on CPU2
10389 20:12:55.432891 <6>[ 0.126129] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10390 20:12:55.439242 <6>[ 0.126143] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10391 20:12:55.442589 <6>[ 0.126400] Detected VIPT I-cache on CPU3
10392 20:12:55.449216 <6>[ 0.126447] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10393 20:12:55.456009 <6>[ 0.126460] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10394 20:12:55.459276 <6>[ 0.126771] CPU features: detected: Spectre-v4
10395 20:12:55.465759 <6>[ 0.126777] CPU features: detected: Spectre-BHB
10396 20:12:55.469226 <6>[ 0.126782] Detected PIPT I-cache on CPU4
10397 20:12:55.475624 <6>[ 0.126839] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10398 20:12:55.482335 <6>[ 0.126856] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10399 20:12:55.488851 <6>[ 0.127150] Detected PIPT I-cache on CPU5
10400 20:12:55.495406 <6>[ 0.127211] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10401 20:12:55.502061 <6>[ 0.127226] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10402 20:12:55.505304 <6>[ 0.127503] Detected PIPT I-cache on CPU6
10403 20:12:55.515287 <6>[ 0.127567] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10404 20:12:55.522011 <6>[ 0.127583] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10405 20:12:55.525073 <6>[ 0.127878] Detected PIPT I-cache on CPU7
10406 20:12:55.531798 <6>[ 0.127941] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10407 20:12:55.538286 <6>[ 0.127957] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10408 20:12:55.541668 <6>[ 0.128004] smp: Brought up 1 node, 8 CPUs
10409 20:12:55.548127 <6>[ 0.128009] SMP: Total of 8 processors activated.
10410 20:12:55.554997 <6>[ 0.128012] CPU features: detected: 32-bit EL0 Support
10411 20:12:55.561404 <6>[ 0.128013] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10412 20:12:55.568043 <6>[ 0.128016] CPU features: detected: Common not Private translations
10413 20:12:55.574651 <6>[ 0.128018] CPU features: detected: CRC32 instructions
10414 20:12:55.581566 <6>[ 0.128021] CPU features: detected: RCpc load-acquire (LDAPR)
10415 20:12:55.584561 <6>[ 0.128022] CPU features: detected: LSE atomic instructions
10416 20:12:55.591287 <6>[ 0.128024] CPU features: detected: Privileged Access Never
10417 20:12:55.597885 <6>[ 0.128025] CPU features: detected: RAS Extension Support
10418 20:12:55.604535 <6>[ 0.128028] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10419 20:12:55.607952 <6>[ 0.128097] CPU: All CPU(s) started at EL2
10420 20:12:55.630466 �xͽ�ɍ��
10421 20:12:55.637072 ɍ�}���}��չѕ�5R�<6>[ 0.344<432] printk: console [ttyS0] printing thread started
10422 20:12:55.640417 5<6>[ 0.344464] printk: console [ttyS0] enabled
10423 20:12:55.647050 >[ 0.225608] VFS: Disk quotas dquot_6.6.0
10424 20:12:55.653543 <6>[ 0.344468] printk: bootconsole [mtk8250] disabled
10425 20:12:55.660685 <6>[ 0.358882] printk: bootconsole [mtk8250] printing thread stopped
10426 20:12:55.663653 <6>[ 0.360135] SuperH (H)SCI(F) driver initialized
10427 20:12:55.670212 <6>[ 0.360614] msm_serial: driver initialized
10428 20:12:55.676847 <6>[ 0.365210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10429 20:12:55.686990 <6>[ 0.365239] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10430 20:12:55.693365 <6>[ 0.365268] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10431 20:12:55.705839 <6>[ 0.365296] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10432 20:12:55.720606 <6>[ 0.365317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10433 20:12:55.736549 <6>[ 0.365344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10434 20:12:55.736893 <6>[ 0.365372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10435 20:12:55.742113 <6>[ 0.365494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10436 20:12:55.750766 <6>[ 0.365523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10437 20:12:55.750849 <6>[ 0.376587] loop: module loaded
10438 20:12:55.755688 <6>[ 0.379210] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10439 20:12:55.762680 <4>[ 0.396044] mtk-pmic-keys: Failed to locate of_node [id: -1]
10440 20:12:55.766010 <6>[ 0.396941] megasas: 07.719.03.00-rc1
10441 20:12:55.772403 <6>[ 0.408912] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10442 20:12:55.775917 <6>[ 0.409036] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10443 20:12:55.782717 <6>[ 0.420705] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10444 20:12:55.795940 <6>[ 0.473302] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10445 20:12:56.425269 <6>[ 1.132575] Freeing initrd memory: 20896K
10446 20:12:56.437338 <6>[ 1.144125] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10447 20:12:56.443824 <6>[ 1.148722] tun: Universal TUN/TAP device driver, 1.6
10448 20:12:56.447242 <6>[ 1.149453] thunder_xcv, ver 1.0
10449 20:12:56.450345 <6>[ 1.149471] thunder_bgx, ver 1.0
10450 20:12:56.453916 <6>[ 1.149495] nicpf, ver 1.0
10451 20:12:56.460439 <6>[ 1.150526] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10452 20:12:56.466981 <6>[ 1.150529] hns3: Copyright (c) 2017 Huawei Corporation.
10453 20:12:56.470294 <6>[ 1.150556] hclge is initializing
10454 20:12:56.476889 <6>[ 1.150570] e1000: Intel(R) PRO/1000 Network Driver
10455 20:12:56.480892 <6>[ 1.150572] e1000: Copyright (c) 1999-2006 Intel Corporation.
10456 20:12:56.488336 <6>[ 1.150588] e1000e: Intel(R) PRO/1000 Network Driver
10457 20:12:56.491613 <6>[ 1.150590] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10458 20:12:56.498321 <6>[ 1.150605] igb: Intel(R) Gigabit Ethernet Network Driver
10459 20:12:56.504968 <6>[ 1.150608] igb: Copyright (c) 2007-2014 Intel Corporation.
10460 20:12:56.511743 <6>[ 1.150621] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10461 20:12:56.515437 <6>[ 1.150623] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10462 20:12:56.522057 <6>[ 1.150915] sky2: driver version 1.30
10463 20:12:56.525413 <6>[ 1.151972] VFIO - User Level meta-driver version: 0.3
10464 20:12:56.532018 <6>[ 1.154779] usbcore: registered new interface driver usb-storage
10465 20:12:56.538701 <6>[ 1.154958] usbcore: registered new device driver onboard-usb-hub
10466 20:12:56.545172 <6>[ 1.157702] mt6397-rtc mt6359-rtc: registered as rtc0
10467 20:12:56.551667 <6>[ 1.157854] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:12:57 UTC (1709496777)
10468 20:12:56.558392 <6>[ 1.158459] i2c_dev: i2c /dev entries driver
10469 20:12:56.565014 <6>[ 1.165457] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10470 20:12:56.571809 <6>[ 1.180432] cpu cpu0: EM: created perf domain
10471 20:12:56.574807 <6>[ 1.180754] cpu cpu4: EM: created perf domain
10472 20:12:56.581499 <6>[ 1.183693] sdhci: Secure Digital Host Controller Interface driver
10473 20:12:56.585043 <6>[ 1.183694] sdhci: Copyright(c) Pierre Ossman
10474 20:12:56.591623 <6>[ 1.184052] Synopsys Designware Multimedia Card Interface Driver
10475 20:12:56.598284 <6>[ 1.184430] sdhci-pltfm: SDHCI platform and OF driver helper
10476 20:12:56.604947 <6>[ 1.188698] ledtrig-cpu: registered to indicate activity on CPUs
10477 20:12:56.608104 <6>[ 1.189378] mmc0: CQHCI version 5.10
10478 20:12:56.614863 <6>[ 1.189463] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10479 20:12:56.621459 <6>[ 1.189741] usbcore: registered new interface driver usbhid
10480 20:12:56.624935 <6>[ 1.189743] usbhid: USB HID core driver
10481 20:12:56.631307 <6>[ 1.189863] spi_master spi0: will run message pump with realtime priority
10482 20:12:56.644843 <6>[ 1.221572] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10483 20:12:56.658119 <6>[ 1.223584] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10484 20:12:56.664934 <6>[ 1.224570] cros-ec-spi spi0.0: Chrome EC device registered
10485 20:12:56.671310 <6>[ 1.242527] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10486 20:12:56.677933 <6>[ 1.245431] NET: Registered PF_PACKET protocol family
10487 20:12:56.681424 <6>[ 1.245557] 9pnet: Installing 9P2000 support
10488 20:12:56.687813 <5>[ 1.245627] Key type dns_resolver registered
10489 20:12:56.691272 <6>[ 1.245987] registered taskstats version 1
10490 20:12:56.697991 <5>[ 1.246014] Loading compiled-in X.509 certificates
10491 20:12:56.707934 <4>[ 1.263457] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10492 20:12:56.718217 <4>[ 1.263649] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10493 20:12:56.724836 <3>[ 1.263662] debugfs: File 'uA_load' in directory '/' already present!
10494 20:12:56.731426 <3>[ 1.263672] debugfs: File 'min_uV' in directory '/' already present!
10495 20:12:56.737852 <3>[ 1.263676] debugfs: File 'max_uV' in directory '/' already present!
10496 20:12:56.744611 <3>[ 1.263681] debugfs: File 'constraint_flags' in directory '/' already present!
10497 20:12:56.754287 <3>[ 1.266186] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10498 20:12:56.761006 <6>[ 1.277292] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10499 20:12:56.764503 <6>[ 1.278101] xhci-mtk 11200000.usb: xHCI Host Controller
10500 20:12:56.774457 <6>[ 1.278131] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10501 20:12:56.780793 <6>[ 1.278384] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10502 20:12:56.787578 <6>[ 1.278446] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10503 20:12:56.793899 <6>[ 1.278602] xhci-mtk 11200000.usb: xHCI Host Controller
10504 20:12:56.800716 <6>[ 1.278618] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10505 20:12:56.807133 <6>[ 1.278639] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10506 20:12:56.813542 <6>[ 1.279393] hub 1-0:1.0: USB hub found
10507 20:12:56.816870 <6>[ 1.279429] hub 1-0:1.0: 1 port detected
10508 20:12:56.823386 <6>[ 1.279853] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10509 20:12:56.829958 <6>[ 1.280772] hub 2-0:1.0: USB hub found
10510 20:12:56.833271 <6>[ 1.280804] hub 2-0:1.0: 1 port detected
10511 20:12:56.836719 <6>[ 1.283697] mmc0: Command Queue Engine enabled
10512 20:12:56.843229 <6>[ 1.283713] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10513 20:12:56.850203 <6>[ 1.284404] mmcblk0: mmc0:0001 DA4128 116 GiB
10514 20:12:56.853244 <6>[ 1.285589] mtk-msdc 11f70000.mmc: Got CD GPIO
10515 20:12:56.859786 <6>[ 1.288264] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10516 20:12:56.866319 <6>[ 1.289794] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10517 20:12:56.869882 <6>[ 1.290698] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10518 20:12:56.876278 <6>[ 1.291728] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10519 20:12:56.886462 <6>[ 1.300882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10520 20:12:56.892968 <6>[ 1.300889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10521 20:12:56.902770 <4>[ 1.301038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10522 20:12:56.909287 <6>[ 1.301685] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10523 20:12:56.919220 <6>[ 1.301689] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10524 20:12:56.925811 <6>[ 1.301810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10525 20:12:56.932322 <6>[ 1.301821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10526 20:12:56.942481 <6>[ 1.301826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10527 20:12:56.948959 <6>[ 1.301831] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10528 20:12:56.958971 <6>[ 1.303289] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10529 20:12:56.965362 <6>[ 1.303307] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10530 20:12:56.975256 <6>[ 1.303312] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10531 20:12:56.982023 <6>[ 1.303318] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10532 20:12:56.991942 <6>[ 1.303323] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10533 20:12:57.001764 <6>[ 1.303328] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10534 20:12:57.008190 <6>[ 1.303334] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10535 20:12:57.018318 <6>[ 1.303339] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10536 20:12:57.024967 <6>[ 1.303345] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10537 20:12:57.034845 <6>[ 1.303353] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10538 20:12:57.041453 <6>[ 1.303359] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10539 20:12:57.051098 <6>[ 1.303364] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10540 20:12:57.057999 <6>[ 1.303369] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10541 20:12:57.067704 <6>[ 1.303374] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10542 20:12:57.074407 <6>[ 1.303379] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10543 20:12:57.081044 <6>[ 1.303864] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10544 20:12:57.087647 <6>[ 1.304703] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10545 20:12:57.094389 <6>[ 1.305243] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10546 20:12:57.100999 <6>[ 1.305893] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10547 20:12:57.107617 <6>[ 1.306554] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10548 20:12:57.117573 <6>[ 1.306758] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10549 20:12:57.127455 <6>[ 1.306775] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10550 20:12:57.137499 <6>[ 1.306780] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10551 20:12:57.143974 <6>[ 1.306792] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10552 20:12:57.153998 <6>[ 1.306798] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10553 20:12:57.163690 <6>[ 1.306804] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10554 20:12:57.173471 <6>[ 1.306810] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10555 20:12:57.183727 <6>[ 1.306816] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10556 20:12:57.189996 <6>[ 1.306821] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10557 20:12:57.203204 <6>[ 1.306828] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10558 20:12:57.213332 <6>[ 1.306833] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10559 20:12:57.219996 <6>[ 1.307893] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10560 20:12:57.226531 <6>[ 1.705599] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10561 20:12:57.229891 <6>[ 1.866103] hub 1-1:1.0: USB hub found
10562 20:12:57.236449 <6>[ 1.866464] hub 1-1:1.0: 4 ports detected
10563 20:12:57.239642 <6>[ 1.869750] hub 1-1:1.0: USB hub found
10564 20:12:57.242859 <6>[ 1.870025] hub 1-1:1.0: 4 ports detected
10565 20:12:57.292605 <6>[ 1.993828] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10566 20:12:57.313577 <6>[ 2.017806] hub 2-1:1.0: USB hub found
10567 20:12:57.316597 <6>[ 2.018177] hub 2-1:1.0: 3 ports detected
10568 20:12:57.319884 <6>[ 2.020909] hub 2-1:1.0: USB hub found
10569 20:12:57.323372 <6>[ 2.021227] hub 2-1:1.0: 3 ports detected
10570 20:12:57.480858 <6>[ 2.181742] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10571 20:12:57.601320 <6>[ 2.309215] hub 1-1.4:1.0: USB hub found
10572 20:12:57.604389 <6>[ 2.309651] hub 1-1.4:1.0: 2 ports detected
10573 20:12:57.607865 <6>[ 2.312658] hub 1-1.4:1.0: USB hub found
10574 20:12:57.614421 <6>[ 2.312948] hub 1-1.4:1.0: 2 ports detected
10575 20:12:57.688315 <6>[ 2.389821] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10576 20:12:57.900564 <6>[ 2.601777] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10577 20:12:58.084378 <6>[ 2.785835] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10578 20:13:08.893109 <6>[ 13.603164] ALSA device list:
10579 20:13:08.899341 <6>[ 13.603187] No soundcards found.
10580 20:13:08.902971 <6>[ 13.607564] Freeing unused kernel memory: 8448K
10581 20:13:08.906135 <6>[ 13.607738] Run /init as init process
10582 20:13:08.930580 Starting syslogd: OK
10583 20:13:08.934997 Starting klogd: OK
10584 20:13:08.941424 Running sysctl: OK
10585 20:13:08.952133 Populating /dev using udev: <30>[ 13.660028] udevd[200]: starting version 3.2.9
10586 20:13:08.958605 <27>[ 13.663522] udevd[200]: specified user 'tss' unknown
10587 20:13:08.961893 <27>[ 13.663569] udevd[200]: specified group 'tss' unknown
10588 20:13:08.968675 <30>[ 13.664502] udevd[201]: starting eudev-3.2.9
10589 20:13:08.992287 <27>[ 13.700581] udevd[201]: specified user 'tss' unknown
10590 20:13:08.998924 <27>[ 13.700684] udevd[201]: specified group 'tss' unknown
10591 20:13:09.132001 <3>[ 13.833830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10592 20:13:09.138199 <3>[ 13.833906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10593 20:13:09.148778 <3>[ 13.833919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10594 20:13:09.158004 <3>[ 13.834308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10595 20:13:09.168016 <3>[ 13.834321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10596 20:13:09.174600 <3>[ 13.834331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10597 20:13:09.181176 <3>[ 13.834362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10598 20:13:09.191732 <3>[ 13.834375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 20:13:09.198044 <3>[ 13.834505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 20:13:09.208010 <3>[ 13.834622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10601 20:13:09.214552 <3>[ 13.834632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10602 20:13:09.224769 <3>[ 13.834643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10603 20:13:09.230970 <3>[ 13.834771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10604 20:13:09.241169 <3>[ 13.834784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10605 20:13:09.247910 <3>[ 13.834795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10606 20:13:09.258086 <3>[ 13.834806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10607 20:13:09.264758 <3>[ 13.834815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 20:13:09.274327 <3>[ 13.834882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 20:13:09.281367 <6>[ 13.847064] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10610 20:13:09.291213 <6>[ 13.847097] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10611 20:13:09.297993 <6>[ 13.847102] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10612 20:13:09.304984 <6>[ 13.863157] usbcore: registered new device driver r8152-cfgselector
10613 20:13:09.314626 <6>[ 13.863759] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10614 20:13:09.321954 <6>[ 13.864209] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10615 20:13:09.325607 <6>[ 13.883035] remoteproc remoteproc0: scp is available
10616 20:13:09.332246 <6>[ 13.883222] remoteproc remoteproc0: powering up scp
10617 20:13:09.338851 <6>[ 13.883236] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10618 20:13:09.345779 <6>[ 13.883298] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10619 20:13:09.349060 <6>[ 13.901787] mc: Linux media interface: v0.10
10620 20:13:09.355440 <6>[ 13.906347] videodev: Linux video capture interface: v2.00
10621 20:13:09.362245 <4>[ 13.931542] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10622 20:13:09.372374 <4>[ 13.931746] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10623 20:13:09.378572 <6>[ 13.971096] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10624 20:13:09.382073 <6>[ 13.971110] pci_bus 0000:00: root bus resource [bus 00-ff]
10625 20:13:09.388607 <6>[ 13.971117] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10626 20:13:09.398420 <6>[ 13.971121] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10627 20:13:09.404865 <6>[ 13.971168] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10628 20:13:09.415049 <6>[ 13.971188] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10629 20:13:09.417979 <6>[ 13.971276] pci 0000:00:00.0: supports D1 D2
10630 20:13:09.424754 <6>[ 13.971281] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10631 20:13:09.434421 <6>[ 13.972682] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10632 20:13:09.437983 <6>[ 13.974412] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10633 20:13:09.447737 <6>[ 13.974448] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10634 20:13:09.454567 <6>[ 13.974469] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10635 20:13:09.461390 <6>[ 13.974484] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10636 20:13:09.467812 <6>[ 13.974611] pci 0000:01:00.0: supports D1 D2
10637 20:13:09.474442 <6>[ 13.974620] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10638 20:13:09.481042 <6>[ 13.985648] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10639 20:13:09.487323 <6>[ 13.985689] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10640 20:13:09.497380 <6>[ 13.985692] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10641 20:13:09.503928 <6>[ 13.985700] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10642 20:13:09.510493 <6>[ 13.985713] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10643 20:13:09.520635 <6>[ 13.985725] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10644 20:13:09.524064 <6>[ 13.985737] pci 0000:00:00.0: PCI bridge to [bus 01]
10645 20:13:09.533809 <6>[ 13.985742] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10646 20:13:09.540066 <6>[ 13.987333] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10647 20:13:09.547185 <6>[ 13.988516] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10648 20:13:09.550216 <6>[ 13.989685] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10649 20:13:09.560387 <6>[ 13.990640] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10650 20:13:09.570096 <4>[ 13.996551] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10651 20:13:09.573847 <4>[ 13.996551] Fallback method does not support PEC.
10652 20:13:09.583435 <6>[ 14.009887] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10653 20:13:09.590175 <6>[ 14.009904] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10654 20:13:09.596675 <6>[ 14.009912] remoteproc remoteproc0: remote processor scp is now up
10655 20:13:09.603356 <4>[ 14.014067] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10656 20:13:09.613305 <4>[ 14.014083] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10657 20:13:09.622861 <3>[ 14.016668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 20:13:09.632552 <6>[ 14.035958] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10659 20:13:09.639186 <6>[ 14.036323] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10660 20:13:09.649541 <6>[ 14.036549] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10661 20:13:09.655878 <6>[ 14.037561] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10662 20:13:09.665920 <3>[ 14.040328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 20:13:09.675798 <6>[ 14.045375] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10664 20:13:09.678959 <6>[ 14.064951] Bluetooth: Core ver 2.22
10665 20:13:09.685854 <6>[ 14.065165] NET: Registered PF_BLUETOOTH protocol family
10666 20:13:09.692497 <6>[ 14.065182] Bluetooth: HCI device and connection manager initialized
10667 20:13:09.695909 <6>[ 14.065273] Bluetooth: HCI socket layer initialized
10668 20:13:09.702640 <6>[ 14.065302] Bluetooth: L2CAP socket layer initialized
10669 20:13:09.705342 <6>[ 14.065337] Bluetooth: SCO socket layer initialized
10670 20:13:09.712461 <6>[ 14.069618] r8152 2-1.3:1.0 eth0: v1.12.13
10671 20:13:09.715720 <6>[ 14.069701] usbcore: registered new interface driver r8152
10672 20:13:09.725188 <5>[ 14.071973] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10673 20:13:09.731889 <6>[ 14.078513] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10674 20:13:09.745567 <6>[ 14.079756] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10675 20:13:09.751867 <6>[ 14.079851] usbcore: registered new interface driver uvcvideo
10676 20:13:09.758109 <5>[ 14.095742] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10677 20:13:09.764707 <5>[ 14.096196] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10678 20:13:09.774958 <4>[ 14.096270] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10679 20:13:09.778264 <6>[ 14.096279] cfg80211: failed to load regulatory.db
10680 20:13:09.785026 <6>[ 14.097298] usbcore: registered new interface driver cdc_ether
10681 20:13:09.791236 <6>[ 14.104791] usbcore: registered new interface driver r8153_ecm
10682 20:13:09.798018 <6>[ 14.122061] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10683 20:13:09.804639 <6>[ 14.133469] usbcore: registered new interface driver btusb
10684 20:13:09.814551 <4>[ 14.134514] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10685 20:13:09.821177 <3>[ 14.134529] Bluetooth: hci0: Failed to load firmware file (-2)
10686 20:13:09.827484 <3>[ 14.134533] Bluetooth: hci0: Failed to set up firmware (-2)
10687 20:13:09.837338 <4>[ 14.134536] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10688 20:13:09.844270 <6>[ 14.202789] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10689 20:13:09.850949 <6>[ 14.202889] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10690 20:13:09.857394 <6>[ 14.221602] mt7921e 0000:01:00.0: ASIC revision: 79610010
10691 20:13:09.863871 <6>[ 14.316550] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10692 20:13:09.867265 <6>[ 14.316550]
10693 20:13:09.873593 <6>[ 14.574141] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10694 20:13:09.918207 done
10695 20:13:09.929004 Saving random seed: OK
10696 20:13:09.944597 Starting network: OK
10697 20:13:09.980506 Starting dropbear sshd: <6>[ 14.687661] NET: Registered PF_INET6 protocol family
10698 20:13:09.984105 <6>[ 14.688871] Segment Routing with IPv6
10699 20:13:09.990406 <6>[ 14.688881] In-situ OAM (IOAM) with IPv6
10700 20:13:09.990939 OK
10701 20:13:10.000378 /bin/sh: can't access tty; job control turned off
10702 20:13:10.001628 Matched prompt #10: / #
10704 20:13:10.002651 Setting prompt string to ['/ #']
10705 20:13:10.003080 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10707 20:13:10.004045 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10708 20:13:10.004485 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10709 20:13:10.004852 Setting prompt string to ['/ #']
10710 20:13:10.005161 Forcing a shell prompt, looking for ['/ #']
10712 20:13:10.056138 / #
10713 20:13:10.056767 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10714 20:13:10.057189 Waiting using forced prompt support (timeout 00:02:30)
10715 20:13:10.062540
10716 20:13:10.063596 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10717 20:13:10.064095 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10718 20:13:10.064565 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10719 20:13:10.065084 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10720 20:13:10.065557 end: 2 depthcharge-action (duration 00:01:34) [common]
10721 20:13:10.066026 start: 3 lava-test-retry (timeout 00:01:00) [common]
10722 20:13:10.066462 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10723 20:13:10.066831 Using namespace: common
10725 20:13:10.167993 / # #
10726 20:13:10.168598 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10727 20:13:10.174345 #
10728 20:13:10.175172 Using /lava-12928138
10730 20:13:10.276450 / # export SHELL=/bin/sh
10731 20:13:10.282711 export SHELL=/bin/sh
10733 20:13:10.384349 / # . /lava-12928138/environment
10734 20:13:10.390743 . /lava-12928138/environment
10736 20:13:10.492443 / # /lava-12928138/bin/lava-test-runner /lava-12928138/0
10737 20:13:10.493045 Test shell timeout: 10s (minimum of the action and connection timeout)
10738 20:13:10.499010 /lava-12928138/bin/lava-test-runner /lava-12928138/0
10739 20:13:10.518808 + export 'TESTRUN_ID=0_dmesg'
10740 20:13:10.525319 +<8>[ 15.233133] <LAVA_SIGNAL_STARTRUN 0_dmesg 12928138_1.5.2.3.1>
10741 20:13:10.526168 Received signal: <STARTRUN> 0_dmesg 12928138_1.5.2.3.1
10742 20:13:10.526557 Starting test lava.0_dmesg (12928138_1.5.2.3.1)
10743 20:13:10.526973 Skipping test definition patterns.
10744 20:13:10.528623 cd /lava-12928138/0/tests/0_dmesg
10745 20:13:10.529136 + cat uuid
10746 20:13:10.531940 + UUID=12928138_1.5.2.3.1
10747 20:13:10.542005 + set<8>[ 15.243903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10748 20:13:10.542534 +x
10749 20:13:10.543149 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10751 20:13:10.551894 + KERNELCI_LAVA=y /bin/sh /<8>[ 15.256328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10752 20:13:10.552706 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10754 20:13:10.561538 opt/kernelci/dme<8>[ 15.266177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10755 20:13:10.562321 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10757 20:13:10.565450 sg.sh
10758 20:13:10.568588 + <8>[ 15.277187] <LAVA_SIGNAL_ENDRUN 0_dmesg 12928138_1.5.2.3.1>
10759 20:13:10.569392 Received signal: <ENDRUN> 0_dmesg 12928138_1.5.2.3.1
10760 20:13:10.569840 Ending use of test pattern.
10761 20:13:10.570167 Ending test lava.0_dmesg (12928138_1.5.2.3.1), duration 0.04
10763 20:13:10.571688 set +x
10764 20:13:10.572038 <LAVA_TEST_RUNNER EXIT>
10765 20:13:10.572616 ok: lava_test_shell seems to have completed
10766 20:13:10.573117 alert: pass
crit: pass
emerg: pass
10767 20:13:10.573549 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10768 20:13:10.573972 end: 3 lava-test-retry (duration 00:00:01) [common]
10769 20:13:10.574397 start: 4 lava-test-retry (timeout 00:01:00) [common]
10770 20:13:10.574810 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10771 20:13:10.575138 Using namespace: common
10773 20:13:10.676437 / # #
10774 20:13:10.677049 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10775 20:13:10.677627 Using /lava-12928138
10777 20:13:10.778836 export SHELL=/bin/sh
10778 20:13:10.779597 #
10779 20:13:10.779990 / # <6>[ 15.420035] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10781 20:13:10.881574 export SHELL=/bin/sh. /lava-12928138/environment
10782 20:13:10.882312
10784 20:13:10.983991 / # . /lava-12928138/environment/lava-12928138/bin/lava-test-runner /lava-12928138/1
10785 20:13:10.984571 Test shell timeout: 10s (minimum of the action and connection timeout)
10786 20:13:10.985089
10787 20:13:10.990282 / # /lava-12928138/bin/lava-test-runner /lava-12928138/1
10788 20:13:11.010044 + export 'TESTRUN_ID=1_bootrr'
10789 20:13:11.016449 <8>[ 15.724890] <LAVA_SIGNAL_STARTRUN 1_bootrr 12928138_1.5.2.3.5>
10790 20:13:11.016810 Received signal: <STARTRUN> 1_bootrr 12928138_1.5.2.3.5
10791 20:13:11.016909 Starting test lava.1_bootrr (12928138_1.5.2.3.5)
10792 20:13:11.017031 Skipping test definition patterns.
10793 20:13:11.020021 + cd /lava-12928138/1/tests/1_bootrr
10794 20:13:11.023566 + cat uuid
10795 20:13:11.023768 + UUID=12928138_1.5.2.3.5
10796 20:13:11.023877 + set +x
10797 20:13:11.036523 + export 'PATH=/opt/bootrr/libexec/bootrr<8>[ 15.737983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10798 20:13:11.036963 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10800 20:13:11.046962 /helpers:/lava-12928138/1/../bin:/sbin:/usr/sbin<8>[ 15.753287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10801 20:13:11.047507 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10803 20:13:11.049599 :/bin:/usr/bin'
10804 20:13:11.053006 + cd /opt/bootrr/libexec/bootrr
10805 20:13:11.053285 + sh helpers/bootrr-auto
10806 20:13:11.056551 /lava-12928138/1/../bin/lava-test-case
10807 20:13:11.067470 /lava-12928138/1/../bin/lava-test-case
10808 20:13:11.067994 /usr/bin/tpm2_getcap
10809 20:13:11.083926 /lava-12928138/1/../bin/lava-test-case
10810 20:13:11.090074 <8>[ 15.796579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10811 20:13:11.090764 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10813 20:13:11.097617 /lava-12928138/1/../bin/lava-test-case
10814 20:13:11.107707 <8>[ 15.810357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10815 20:13:11.108476 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10817 20:13:11.110821 /lava-12928138/1/../bin/lava-test-case
10818 20:13:11.121244 <8>[ 15.824936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10819 20:13:11.122088 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10821 20:13:11.124157 /lava-12928138/1/../bin/lava-test-case
10822 20:13:11.131163 <8>[ 15.837100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10823 20:13:11.131969 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10825 20:13:11.134067 /lava-12928138/1/../bin/lava-test-case
10826 20:13:11.144103 <8>[ 15.848740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10827 20:13:11.144896 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10829 20:13:11.147711 /lava-12928138/1/../bin/lava-test-case
10830 20:13:11.160094 /lava-12928138/1<8>[ 15.862246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10831 20:13:11.160913 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10833 20:13:11.169650 /../bin/lava-tes<8>[ 15.868341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10834 20:13:11.170420 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10836 20:13:11.173223 t-case
10837 20:13:11.179865 /lava-12<8>[ 15.878129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10838 20:13:11.180662 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10840 20:13:11.189694 928138/1/../bin/<8>[ 15.888282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10841 20:13:11.190502 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10843 20:13:11.192994 lava-test-case
10844 20:13:11.196575 /lava-12928138/1/../bin/lava-test-case
10845 20:13:11.206446 /lava-12<8>[ 15.907542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10846 20:13:11.207241 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10848 20:13:11.209518 928138/1/../bin/lava-test-case
10849 20:13:11.212927 /lava-12928138/1/../bin/lava-test-case
10850 20:13:11.219516 <8>[ 15.923523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10851 20:13:11.220325 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10853 20:13:11.222894 /lava-12928138/1/../bin/lava-test-case
10854 20:13:11.235775 <8>[ 15.938146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10855 20:13:11.236554 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10857 20:13:11.239463 /lava-12928138/1/../bin/lava-test-case
10858 20:13:11.251524 <8>[ 15.954012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10859 20:13:11.252353 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10861 20:13:11.254744 /lava-12928138/1/../bin/lava-test-case
10862 20:13:11.267811 <8>[ 15.969599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10863 20:13:11.268611 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10865 20:13:11.271196 /lava-12928138/1/../bin/lava-test-case
10866 20:13:11.284258 <8>[ 15.986658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10867 20:13:11.285069 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10869 20:13:11.287039 /lava-12928138/1/../bin/lava-test-case
10870 20:13:11.297369 <8>[ 16.000444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10871 20:13:11.298204 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10873 20:13:11.300641 /lava-12928138/1/../bin/lava-test-case
10874 20:13:11.307509 <8>[ 16.013423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10875 20:13:11.308304 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10877 20:13:11.310587 /lava-12928138/1/../bin/lava-test-case
10878 20:13:11.320553 <8>[ 16.023965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10879 20:13:11.321347 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10881 20:13:11.323715 /lava-12928138/1/../bin/lava-test-case
10882 20:13:11.335649 <8>[ 16.039062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10883 20:13:11.336434 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10885 20:13:11.339227 /lava-12928138/1/../bin/lava-test-case
10886 20:13:11.351649 <8>[ 16.055800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10887 20:13:11.352419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10889 20:13:11.355417 /lava-12928138/1/../bin/lava-test-case
10890 20:13:11.367803 <8>[ 16.070629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10891 20:13:11.368602 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10893 20:13:11.371132 /lava-12928138/1/../bin/lava-test-case
10894 20:13:11.384009 <8>[ 16.088404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10895 20:13:11.384806 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10897 20:13:11.386668 /lava-12928138/1/../bin/lava-test-case
10898 20:13:11.399778 <8>[ 16.102728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10899 20:13:11.400568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10901 20:13:11.403116 /lava-12928138/1/../bin/lava-test-case
10902 20:13:11.416053 <8>[ 16.118473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10903 20:13:11.416841 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10905 20:13:11.419249 /lava-12928138/1/../bin/lava-test-case
10906 20:13:11.432161 <8>[ 16.134198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10907 20:13:11.432949 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10909 20:13:11.435171 /lava-12928138/1/../bin/lava-test-case
10910 20:13:11.447773 <8>[ 16.150852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10911 20:13:11.448563 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10913 20:13:11.451070 /lava-12928138/1/../bin/lava-test-case
10914 20:13:11.460992 <8>[ 16.164951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10915 20:13:11.461819 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10917 20:13:11.464282 /lava-12928138/1/../bin/lava-test-case
10918 20:13:11.475794 <8>[ 16.178952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10919 20:13:11.476595 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10921 20:13:11.479146 /lava-12928138/1/../bin/lava-test-case
10922 20:13:11.486253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10924 20:13:11.488982 <8>[ 16.192891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10925 20:13:11.492570 /lava-12928138/1/../bin/lava-test-case
10926 20:13:11.499402 <8>[ 16.205286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10927 20:13:11.500203 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10929 20:13:11.502345 /lava-12928138/1/../bin/lava-test-case
10930 20:13:11.515777 <8>[ 16.219165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10931 20:13:11.516574 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10933 20:13:11.519271 /lava-12928138/1/../bin/lava-test-case
10934 20:13:11.529457 <8>[ 16.232721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10935 20:13:11.530309 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10937 20:13:11.532060 /lava-12928138/1/../bin/lava-test-case
10938 20:13:11.543781 <8>[ 16.246651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10939 20:13:11.544674 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10941 20:13:11.546904 /lava-12928138/1/../bin/lava-test-case
10942 20:13:11.553566 <8>[ 16.260487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10943 20:13:11.554238 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10945 20:13:11.560003 /lava-12928138/1/../bin/lava-test-case
10946 20:13:11.571758 <8>[ 16.273507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10947 20:13:11.572564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10949 20:13:11.574870 /lava-12928138/1/../bin/lava-test-case
10950 20:13:11.588185 <8>[ 16.290645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10951 20:13:11.588979 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10953 20:13:11.590928 /lava-12928138/1/../bin/lava-test-case
10954 20:13:11.601262 <8>[ 16.304906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10955 20:13:11.602100 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10957 20:13:11.604270 /lava-12928138/1/../bin/lava-test-case
10958 20:13:11.615725 <8>[ 16.320207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10959 20:13:11.616492 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10961 20:13:11.619186 /lava-12928138/1/../bin/lava-test-case
10962 20:13:11.629037 <8>[ 16.332630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10963 20:13:11.629872 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10965 20:13:11.631949 /lava-12928138/1/../bin/lava-test-case
10966 20:13:11.643865 <8>[ 16.345501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10967 20:13:11.644705 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10969 20:13:11.646809 /lava-12928138/1/../bin/lava-test-case
10970 20:13:11.657400 <8>[ 16.360364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10971 20:13:11.658276 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10973 20:13:11.660571 /lava-12928138/1/../bin/lava-test-case
10974 20:13:11.671881 <8>[ 16.374498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10975 20:13:11.672675 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10977 20:13:11.675275 /lava-12928138/1/../bin/lava-test-case
10978 20:13:11.685082 <8>[ 16.388693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10979 20:13:11.685937 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10981 20:13:11.688329 /lava-12928138/1/../bin/lava-test-case
10982 20:13:11.700079 <8>[ 16.402468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10983 20:13:11.700879 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10985 20:13:11.703254 /lava-12928138/1/../bin/lava-test-case
10986 20:13:11.709862 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10988 20:13:11.713231 <8>[ 16.416209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10989 20:13:11.716636 /lava-12928138/1/../bin/lava-test-case
10990 20:13:11.723174 <8>[ 16.429156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10991 20:13:11.723983 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10993 20:13:11.726293 /lava-12928138/1/../bin/lava-test-case
10994 20:13:11.736163 <8>[ 16.440524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10995 20:13:11.736962 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10997 20:13:11.739427 /lava-12928138/1/../bin/lava-test-case
10998 20:13:11.751662 <8>[ 16.453900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10999 20:13:11.752361 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11001 20:13:11.755218 /lava-12928138/1/../bin/lava-test-case
11002 20:13:11.768155 <8>[ 16.470401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11003 20:13:11.768963 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11005 20:13:11.770792 /lava-12928138/1/../bin/lava-test-case
11006 20:13:11.781241 <8>[ 16.484475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11007 20:13:11.782073 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11009 20:13:11.783943 /lava-12928138/1/../bin/lava-test-case
11010 20:13:11.790798 <8>[ 16.496765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11011 20:13:11.791597 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11013 20:13:11.794164 /lava-12928138/1/../bin/lava-test-case
11014 20:13:11.804127 <8>[ 16.508902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11015 20:13:11.804933 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11017 20:13:11.807586 /lava-12928138/1/../bin/lava-test-case
11018 20:13:11.813944 <8>[ 16.521159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11019 20:13:11.814747 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11021 20:13:11.817362 /lava-12928138/1/../bin/lava-test-case
11022 20:13:11.832026 <8>[ 16.534543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11023 20:13:11.832837 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11025 20:13:11.834713 /lava-12928138/1/../bin/lava-test-case
11026 20:13:11.847201 <8>[ 16.552475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11027 20:13:11.847976 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11029 20:13:11.850652 /lava-12928138/1/../bin/lava-test-case
11030 20:13:11.863819 <8>[ 16.566055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11031 20:13:11.864613 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11033 20:13:11.867442 /lava-12928138/1/../bin/lava-test-case
11034 20:13:11.873811 <8>[ 16.581200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11035 20:13:11.874604 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11037 20:13:11.877173 /lava-12928138/1/../bin/lava-test-case
11038 20:13:11.892075 <8>[ 16.593689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11039 20:13:11.892867 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11041 20:13:11.895289 /lava-12928138/1/../bin/lava-test-case
11042 20:13:11.901850 <8>[ 16.609196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11043 20:13:11.902583 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11045 20:13:11.910354 /lava-12928138/1/../bin/lava-test-case
11046 20:13:11.917378 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11048 20:13:11.920362 <8>[ 16.623139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11049 20:13:11.923852 /lava-12928138/1/../bin/lava-test-case
11050 20:13:11.930416 <8>[ 16.636672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11051 20:13:11.931225 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11053 20:13:11.933726 /lava-12928138/1/../bin/lava-test-case
11054 20:13:11.947683 <8>[ 16.650410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11055 20:13:11.948451 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11057 20:13:11.950666 /lava-12928138/1/../bin/lava-test-case
11058 20:13:11.963785 <8>[ 16.665654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11059 20:13:11.964583 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11061 20:13:11.966870 /lava-12928138/1/../bin/lava-test-case
11062 20:13:11.979585 <8>[ 16.682635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11063 20:13:11.980382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11065 20:13:11.983087 /lava-12928138/1/../bin/lava-test-case
11066 20:13:11.995470 <8>[ 16.699746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11067 20:13:11.996260 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11069 20:13:11.999170 /lava-12928138/1/../bin/lava-test-case
11070 20:13:12.011994 <8>[ 16.714351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11071 20:13:12.012942 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11073 20:13:12.015546 /lava-12928138/1/../bin/lava-test-case
11074 20:13:12.027862 <8>[ 16.730189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11075 20:13:12.028653 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11077 20:13:12.030776 /lava-12928138/1/../bin/lava-test-case
11078 20:13:12.043805 <8>[ 16.746054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11079 20:13:12.044570 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11081 20:13:12.046873 /lava-12928138/1/../bin/lava-test-case
11082 20:13:12.059391 <8>[ 16.762310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11083 20:13:12.060185 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11085 20:13:12.062924 /lava-12928138/1/../bin/lava-test-case
11086 20:13:12.069689 <8>[ 16.777081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11087 20:13:12.070488 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11089 20:13:12.072969 /lava-12928138/1/../bin/lava-test-case
11090 20:13:12.087929 <8>[ 16.790013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11091 20:13:12.088723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11093 20:13:12.091338 /lava-12928138/1/../bin/lava-test-case
11094 20:13:12.097918 <8>[ 16.805107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11095 20:13:12.098713 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11097 20:13:12.100769 /lava-12928138/1/../bin/lava-test-case
11098 20:13:12.115685 <8>[ 16.818872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11099 20:13:12.116492 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11101 20:13:12.119004 /lava-12928138/1/../bin/lava-test-case
11102 20:13:12.131818 <8>[ 16.834294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11103 20:13:12.132649 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11105 20:13:12.134644 /lava-12928138/1/../bin/lava-test-case
11106 20:13:12.147618 <8>[ 16.849885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11107 20:13:12.148374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11109 20:13:12.150971 /lava-12928138/1/../bin/lava-test-case
11110 20:13:12.163521 <8>[ 16.868330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11111 20:13:12.164205 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11113 20:13:12.166758 /lava-12928138/1/../bin/lava-test-case
11114 20:13:12.173369 <8>[ 16.880921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11115 20:13:12.174088 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11117 20:13:12.176716 /lava-12928138/1/../bin/lava-test-case
11118 20:13:12.191600 <8>[ 16.893869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11119 20:13:12.192282 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11121 20:13:12.194843 /lava-12928138/1/../bin/lava-test-case
11122 20:13:12.201687 <8>[ 16.908887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11123 20:13:12.202484 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11125 20:13:12.208365 /lava-12928138/1/../bin/lava-test-case
11126 20:13:12.214521 <8>[ 16.920921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11127 20:13:12.215324 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11129 20:13:12.217779 /lava-12928138/1/../bin/lava-test-case
11130 20:13:12.231874 <8>[ 16.934079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11131 20:13:12.232667 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11133 20:13:12.234798 /lava-12928138/1/../bin/lava-test-case
11134 20:13:12.241833 <8>[ 16.948543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11135 20:13:12.242662 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11137 20:13:12.245106 /lava-12928138/1/../bin/lava-test-case
11138 20:13:12.255532 <8>[ 16.960387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11139 20:13:12.256400 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11141 20:13:12.258697 /lava-12928138/1/../bin/lava-test-case
11142 20:13:12.265702 <8>[ 16.973133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11143 20:13:12.266499 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11145 20:13:12.268949 /lava-12928138/1/../bin/lava-test-case
11146 20:13:12.279890 <8>[ 16.984596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11147 20:13:12.280729 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11149 20:13:12.282687 /lava-12928138/1/../bin/lava-test-case
11150 20:13:12.295629 <8>[ 16.998267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11151 20:13:12.296450 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11153 20:13:12.298897 /lava-12928138/1/../bin/lava-test-case
11154 20:13:12.309110 <8>[ 17.012562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11155 20:13:12.309994 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11157 20:13:12.312044 /lava-12928138/1/../bin/lava-test-case
11158 20:13:12.324082 <8>[ 17.025659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11159 20:13:12.324910 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11161 20:13:12.326936 /lava-12928138/1/../bin/lava-test-case
11162 20:13:12.334206 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11164 20:13:12.336822 <8>[ 17.040858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11165 20:13:12.340385 /lava-12928138/1/../bin/lava-test-case
11166 20:13:12.351582 <8>[ 17.053777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11167 20:13:12.352272 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11169 20:13:12.354553 /lava-12928138/1/../bin/lava-test-case
11170 20:13:12.367450 <8>[ 17.069803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11171 20:13:12.368130 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11173 20:13:12.370729 /lava-12928138/1/../bin/lava-test-case
11174 20:13:12.383280 <8>[ 17.087011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11175 20:13:12.383954 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11177 20:13:12.386682 /lava-12928138/1/../bin/lava-test-case
11178 20:13:12.399510 <8>[ 17.102369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11179 20:13:12.400361 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11181 20:13:12.402682 /lava-12928138/1/../bin/lava-test-case
11182 20:13:12.412516 <8>[ 17.117379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11183 20:13:12.413236 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11185 20:13:12.415925 /lava-12928138/1/../bin/lava-test-case
11186 20:13:12.427629 <8>[ 17.131815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11187 20:13:12.428352 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11189 20:13:12.430837 /lava-12928138/1/../bin/lava-test-case
11190 20:13:12.443366 <8>[ 17.145890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11191 20:13:12.444038 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11193 20:13:12.446497 /lava-12928138/1/../bin/lava-test-case
11194 20:13:12.459312 <8>[ 17.161957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11195 20:13:12.460174 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11197 20:13:12.462343 /lava-12928138/1/../bin/lava-test-case
11198 20:13:12.475147 <8>[ 17.177508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11199 20:13:12.475607 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11201 20:13:13.478991 /lava-12928138/1/../bin/lava-test-case
11202 20:13:13.485729 <8>[ 18.192629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11203 20:13:13.486008 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11205 20:13:13.488797 /lava-12928138/1/../bin/lava-test-case
11206 20:13:13.498947 <8>[ 18.204266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11207 20:13:13.499225 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11209 20:13:14.503977 /lava-12928138/1/../bin/lava-test-case
11210 20:13:14.515398 <8>[ 19.218397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11211 20:13:14.516077 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11213 20:13:14.518739 /lava-12928138/1/../bin/lava-test-case
11214 20:13:14.528755 <8>[ 19.232034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11215 20:13:14.529580 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11217 20:13:15.530559 /lava-12928138/1/../bin/lava-test-case
11218 20:13:15.543264 <8>[ 20.245524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11219 20:13:15.544141 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11221 20:13:15.546522 /lava-12928138/1/../bin/lava-test-case
11222 20:13:15.553387 <8>[ 20.260491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11223 20:13:15.554343 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11225 20:13:16.558876 /lava-12928138/1/../bin/lava-test-case
11226 20:13:16.571026 <8>[ 21.274254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11227 20:13:16.571756 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11229 20:13:16.574377 /lava-12928138/1/../bin/lava-test-case
11230 20:13:16.586947 <8>[ 21.289676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11231 20:13:16.587741 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11233 20:13:17.590132 /lava-12928138/1/../bin/lava-test-case
11234 20:13:17.596891 <8>[ 22.303868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11235 20:13:17.597812 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11237 20:13:17.600306 /lava-12928138/1/../bin/lava-test-case
11238 20:13:17.614857 <8>[ 22.317909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11239 20:13:17.615664 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11241 20:13:18.615657 /lava-12928138/1/../bin/lava-test-case
11242 20:13:18.622240 <8>[ 23.329438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11243 20:13:18.622931 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11245 20:13:18.625590 /lava-12928138/1/../bin/lava-test-case
11246 20:13:18.638380 <8>[ 23.344290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11247 20:13:18.639075 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11249 20:13:19.645538 /lava-12928138/1/../bin/lava-test-case
11250 20:13:19.651989 <8>[ 24.361346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11251 20:13:19.652737 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11253 20:13:19.659066 /lava-12928138/1/../bin/lava-test-case
11254 20:13:19.665314 <8>[ 24.372163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11255 20:13:19.666188 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11257 20:13:19.668822 /lava-12928138/1/../bin/lava-test-case
11258 20:13:19.678761 <8>[ 24.385391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11259 20:13:19.679555 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11261 20:13:20.683663 /lava-12928138/1/../bin/lava-test-case
11262 20:13:20.694542 <8>[ 25.398285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11263 20:13:20.695228 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11265 20:13:20.697920 /lava-12928138/1/../bin/lava-test-case
11266 20:13:20.710703 <8>[ 25.415387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11267 20:13:20.711379 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11269 20:13:20.713698 /lava-12928138/1/../bin/lava-test-case
11270 20:13:20.726524 <8>[ 25.430678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11271 20:13:20.727199 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11273 20:13:20.729644 /lava-12928138/1/../bin/lava-test-case
11274 20:13:20.739541 <8>[ 25.444510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11275 20:13:20.740215 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11277 20:13:20.742978 /lava-12928138/1/../bin/lava-test-case
11278 20:13:20.749917 <8>[ 25.457187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11279 20:13:20.750593 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11281 20:13:20.752754 /lava-12928138/1/../bin/lava-test-case
11282 20:13:20.766749 <8>[ 25.471702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11283 20:13:20.767475 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11285 20:13:20.770416 /lava-12928138/1/../bin/lava-test-case
11286 20:13:20.782807 <8>[ 25.486698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11287 20:13:20.783596 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11289 20:13:20.786192 /lava-12928138/1/../bin/lava-test-case
11290 20:13:20.798962 <8>[ 25.501672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11291 20:13:20.799755 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11293 20:13:20.802005 /lava-12928138/1/../bin/lava-test-case
11294 20:13:20.815184 <8>[ 25.519218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11295 20:13:20.815977 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11297 20:13:20.818270 /lava-12928138/1/../bin/lava-test-case
11298 20:13:20.825406 <8>[ 25.533176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11299 20:13:20.826236 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11301 20:13:20.831588 /lava-12928138/1/../bin/lava-test-case
11302 20:13:20.842718 <8>[ 25.546277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11303 20:13:20.843619 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11305 20:13:20.846446 /lava-12928138/1/../bin/lava-test-case
11306 20:13:20.858518 <8>[ 25.562678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11307 20:13:20.859206 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11309 20:13:20.861774 /lava-12928138/1/../bin/lava-test-case
11310 20:13:20.874404 <8>[ 25.578520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11311 20:13:20.875154 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11313 20:13:20.877925 /lava-12928138/1/../bin/lava-test-case
11314 20:13:20.890580 <8>[ 25.594213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11315 20:13:20.891298 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11317 20:13:20.893964 /lava-12928138/1/../bin/lava-test-case
11318 20:13:20.906727 <8>[ 25.610437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11319 20:13:20.907622 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11321 20:13:20.909710 /lava-12928138/1/../bin/lava-test-case
11322 20:13:20.922570 <8>[ 25.627103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11323 20:13:20.923441 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11325 20:13:20.925780 /lava-12928138/1/../bin/lava-test-case
11326 20:13:20.938592 <8>[ 25.642138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11327 20:13:20.939296 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11329 20:13:20.941799 /lava-12928138/1/../bin/lava-test-case
11330 20:13:20.954325 <8>[ 25.657510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11331 20:13:20.954720 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11333 20:13:20.957974 /lava-12928138/1/../bin/lava-test-case
11334 20:13:20.967588 <8>[ 25.672907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11335 20:13:20.967970 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11337 20:13:20.970689 /lava-12928138/1/../bin/lava-test-case
11338 20:13:20.977701 <8>[ 25.684941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11339 20:13:20.978019 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11341 20:13:20.980891 /lava-12928138/1/../bin/lava-test-case
11342 20:13:20.990590 <8>[ 25.696912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11343 20:13:20.990942 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11345 20:13:21.994613 /lava-12928138/1/../bin/lava-test-case
11346 20:13:22.000856 <8>[ 26.708406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11347 20:13:22.001580 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11349 20:13:23.008171 /lava-12928138/1/../bin/lava-test-case
11350 20:13:23.018733 <8>[ 27.723532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11351 20:13:23.019526 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11353 20:13:23.021584 /lava-12928138/1/../bin/lava-test-case
11354 20:13:23.031829 <8>[ 27.735861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11355 20:13:23.032625 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11357 20:13:23.035044 /lava-12928138/1/../bin/lava-test-case
11358 20:13:23.041644 <8>[ 27.748952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11359 20:13:23.042436 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11361 20:13:23.045279 /lava-12928138/1/../bin/lava-test-case
11362 20:13:23.054878 <8>[ 27.760071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11363 20:13:23.055693 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11365 20:13:23.058132 /lava-12928138/1/../bin/lava-test-case
11366 20:13:23.064930 <8>[ 27.772920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11367 20:13:23.065715 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11369 20:13:23.068129 /lava-12928138/1/../bin/lava-test-case
11370 20:13:23.078444 <8>[ 27.784327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11371 20:13:23.079250 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11373 20:13:23.082044 /lava-12928138/1/../bin/lava-test-case
11374 20:13:23.094727 <8>[ 27.798958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11375 20:13:23.095515 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11377 20:13:23.098295 /lava-12928138/1/../bin/lava-test-case
11378 20:13:23.104939 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11380 20:13:23.107983 <8>[ 27.812655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11381 20:13:23.111303 /lava-12928138/1/../bin/lava-test-case
11382 20:13:23.117772 <8>[ 27.825346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11383 20:13:23.118557 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11385 20:13:23.121286 /lava-12928138/1/../bin/lava-test-case
11386 20:13:23.134479 <8>[ 27.838188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11387 20:13:23.135249 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11389 20:13:23.137642 /lava-12928138/1/../bin/lava-test-case
11390 20:13:23.145012 <8>[ 27.852967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11391 20:13:23.145843 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11393 20:13:23.147799 /lava-12928138/1/../bin/lava-test-case
11394 20:13:23.162317 <8>[ 27.865475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11395 20:13:23.163095 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11397 20:13:23.166054 /lava-12928138/1/../bin/lava-test-case
11398 20:13:23.172375 <8>[ 27.880952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11399 20:13:23.173061 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11401 20:13:23.175918 /lava-12928138/1/../bin/lava-test-case
11402 20:13:23.186631 <8>[ 27.893223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11403 20:13:23.187435 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11405 20:13:23.189740 /lava-12928138/1/../bin/lava-test-case
11406 20:13:23.196357 <8>[ 27.904711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11407 20:13:23.197058 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11409 20:13:23.199478 /lava-12928138/1/../bin/lava-test-case
11410 20:13:23.210372 <8>[ 27.915752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11411 20:13:23.211068 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11413 20:13:23.213686 /lava-12928138/1/../bin/lava-test-case
11414 20:13:23.226735 <8>[ 27.929803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11415 20:13:23.227535 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11417 20:13:23.229964 /lava-12928138/1/../bin/lava-test-case
11418 20:13:23.236555 <8>[ 27.945416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11419 20:13:23.237358 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11421 20:13:23.243623 /lava-12928138/1/../bin/lava-test-case
11422 20:13:23.249941 <8>[ 27.957307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11423 20:13:23.250757 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11425 20:13:23.253103 /lava-12928138/1/../bin/lava-test-case
11426 20:13:23.263478 <8>[ 27.968664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11427 20:13:23.264298 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11429 20:13:23.266370 /lava-12928138/1/../bin/lava-test-case
11430 20:13:23.272957 <8>[ 27.981077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11431 20:13:23.273650 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11433 20:13:24.277321 /lava-12928138/1/../bin/lava-test-case
11434 20:13:24.287480 <8>[ 28.992477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11435 20:13:24.288298 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11437 20:13:25.287803 /lava-12928138/1/../bin/lava-test-case
11438 20:13:25.298270 <8>[ 30.002059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11439 20:13:25.298581 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11440 20:13:25.298702 Bad test result: blocked
11441 20:13:25.301905 /lava-12928138/1/../bin/lava-test-case
11442 20:13:25.313720 <8>[ 30.018969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11443 20:13:25.314109 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11445 20:13:26.316682 /lava-12928138/1/../bin/lava-test-case
11446 20:13:26.323433 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11448 20:13:26.326277 <8>[ 31.031862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11449 20:13:26.329529 /lava-12928138/1/../bin/lava-test-case
11450 20:13:26.336073 <8>[ 31.045253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11451 20:13:26.336886 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11453 20:13:26.347491 /lava-12928138/1/../bin/lava-test-case
11454 20:13:26.357843 <8>[ 31.062836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11455 20:13:26.358629 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11457 20:13:26.361096 /lava-12928138/1/../bin/lava-test-case
11458 20:13:26.374106 <8>[ 31.079729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11459 20:13:26.374776 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11461 20:13:26.377413 /lava-12928138/1/../bin/lava-test-case
11462 20:13:26.387400 <8>[ 31.091892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11463 20:13:26.388205 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11465 20:13:26.390608 /lava-12928138/1/../bin/lava-test-case
11466 20:13:26.397006 <8>[ 31.104873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11467 20:13:26.397709 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11469 20:13:26.400575 /lava-12928138/1/../bin/lava-test-case
11470 20:13:26.410262 <8>[ 31.116634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11471 20:13:26.411040 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11473 20:13:27.413584 /lava-12928138/1/../bin/lava-test-case
11474 20:13:27.426414 <8>[ 32.130087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11475 20:13:27.427421 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11477 20:13:27.428965 /lava-12928138/1/../bin/lava-test-case
11478 20:13:27.441807 <8>[ 32.146804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11479 20:13:27.442586 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11481 20:13:28.447872 /lava-12928138/1/../bin/lava-test-case
11482 20:13:28.455072 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11484 20:13:28.457907 <8>[ 33.164270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11485 20:13:28.461275 /lava-12928138/1/../bin/lava-test-case
11486 20:13:28.467921 <8>[ 33.175340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11487 20:13:28.468715 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11489 20:13:29.475281 /lava-12928138/1/../bin/lava-test-case
11490 20:13:29.485689 <8>[ 34.191941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11491 20:13:29.486483 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11493 20:13:29.489188 /lava-12928138/1/../bin/lava-test-case
11494 20:13:29.498505 <8>[ 34.203558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11495 20:13:29.499465 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11497 20:13:30.503411 /lava-12928138/1/../bin/lava-test-case
11498 20:13:30.513724 <8>[ 35.219873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11499 20:13:30.514609 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11501 20:13:30.516443 /lava-12928138/1/../bin/lava-test-case
11502 20:13:30.523753 <8>[ 35.232118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11503 20:13:30.524544 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11505 20:13:30.530061 /lava-12928138/1/../bin/lava-test-case
11506 20:13:30.536904 <8>[ 35.244390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11507 20:13:30.537708 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11509 20:13:30.539849 /lava-12928138/1/../bin/lava-test-case
11510 20:13:30.547156 <8>[ 35.257289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11511 20:13:30.547974 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11513 20:13:30.556931 /lava-12928138/1/../bin/lava-test-case
11514 20:13:30.563513 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11516 20:13:30.566299 <8>[ 35.272444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11517 20:13:30.570058 /lava-12928138/1/../bin/lava-test-case
11518 20:13:30.576643 <8>[ 35.284360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11519 20:13:30.577440 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11521 20:13:30.579964 /lava-12928138/1/../bin/lava-test-case
11522 20:13:30.589286 <8>[ 35.297271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11523 20:13:30.590229 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11525 20:13:30.598959 /lava-12928138/1/../bin/lava-test-case
11526 20:13:30.609554 <8>[ 35.315415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11527 20:13:30.610456 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11529 20:13:30.612775 /lava-12928138/1/../bin/lava-test-case
11530 20:13:30.626077 <8>[ 35.329845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11531 20:13:30.626878 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11533 20:13:30.628624 /lava-12928138/1/../bin/lava-test-case
11534 20:13:30.633848 + set +x
11535 20:13:30.640962 <8>[ 35.346721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11536 20:13:30.641818 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11538 20:13:30.647388 <8>[ 35.348990] <LAVA_SIGNAL_ENDRUN 1_bootrr 12928138_1.5.2.3.5>
11539 20:13:30.648185 Received signal: <ENDRUN> 1_bootrr 12928138_1.5.2.3.5
11540 20:13:30.648581 Ending use of test pattern.
11541 20:13:30.648907 Ending test lava.1_bootrr (12928138_1.5.2.3.5), duration 19.63
11543 20:13:30.650558 ok: lava_test_shell seems to have completed
11544 20:13:30.655553 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11545 20:13:30.656257 end: 4.1 lava-test-shell (duration 00:00:20) [common]
11546 20:13:30.656695 end: 4 lava-test-retry (duration 00:00:20) [common]
11547 20:13:30.657147 start: 5 finalize (timeout 00:07:48) [common]
11548 20:13:30.657646 start: 5.1 power-off (timeout 00:00:30) [common]
11549 20:13:30.658516 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11550 20:13:30.742909 >> Command sent successfully.
11551 20:13:30.747236 Returned 0 in 0 seconds
11552 20:13:30.848176 end: 5.1 power-off (duration 00:00:00) [common]
11554 20:13:30.849641 start: 5.2 read-feedback (timeout 00:07:48) [common]
11556 20:13:30.852073 Listened to connection for namespace 'common' for up to 1s
11557 20:13:31.851727 Finalising connection for namespace 'common'
11558 20:13:31.852503 Disconnecting from shell: Finalise
11559 20:13:31.852907 / #
11560 20:13:31.953868 end: 5.2 read-feedback (duration 00:00:01) [common]
11561 20:13:31.954496 end: 5 finalize (duration 00:00:01) [common]
11562 20:13:31.955043 Cleaning after the job
11563 20:13:31.955511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/ramdisk
11564 20:13:31.969128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/kernel
11565 20:13:31.997763 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/dtb
11566 20:13:31.998123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928138/tftp-deploy-9cf_hi8c/modules
11567 20:13:32.009744 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928138
11568 20:13:32.057611 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928138
11569 20:13:32.057785 Job finished correctly