Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 29
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 10
1 20:14:35.910918 lava-dispatcher, installed at version: 2024.01
2 20:14:35.911144 start: 0 validate
3 20:14:35.911291 Start time: 2024-03-03 20:14:35.911280+00:00 (UTC)
4 20:14:35.911421 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:14:35.911574 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 20:14:36.180499 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:14:36.180683 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:14:36.445219 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:14:36.445402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:14:36.710497 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:14:36.710678 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:14:36.976583 validate duration: 1.07
14 20:14:36.977102 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:14:36.977214 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:14:36.977318 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:14:36.977439 Not decompressing ramdisk as can be used compressed.
18 20:14:36.977530 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 20:14:36.977601 saving as /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/ramdisk/rootfs.cpio.gz
20 20:14:36.977665 total size: 34390042 (32 MB)
21 20:14:36.978834 progress 0 % (0 MB)
22 20:14:36.988142 progress 5 % (1 MB)
23 20:14:36.997245 progress 10 % (3 MB)
24 20:14:37.006615 progress 15 % (4 MB)
25 20:14:37.015706 progress 20 % (6 MB)
26 20:14:37.024885 progress 25 % (8 MB)
27 20:14:37.033995 progress 30 % (9 MB)
28 20:14:37.043192 progress 35 % (11 MB)
29 20:14:37.052366 progress 40 % (13 MB)
30 20:14:37.061570 progress 45 % (14 MB)
31 20:14:37.070720 progress 50 % (16 MB)
32 20:14:37.080075 progress 55 % (18 MB)
33 20:14:37.089152 progress 60 % (19 MB)
34 20:14:37.098405 progress 65 % (21 MB)
35 20:14:37.107407 progress 70 % (22 MB)
36 20:14:37.116679 progress 75 % (24 MB)
37 20:14:37.125724 progress 80 % (26 MB)
38 20:14:37.135033 progress 85 % (27 MB)
39 20:14:37.143982 progress 90 % (29 MB)
40 20:14:37.153135 progress 95 % (31 MB)
41 20:14:37.162279 progress 100 % (32 MB)
42 20:14:37.162466 32 MB downloaded in 0.18 s (177.47 MB/s)
43 20:14:37.162627 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:14:37.162882 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:14:37.162992 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:14:37.163084 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:14:37.163222 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:14:37.163296 saving as /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/kernel/Image
50 20:14:37.163359 total size: 51601920 (49 MB)
51 20:14:37.163421 No compression specified
52 20:14:37.164630 progress 0 % (0 MB)
53 20:14:37.178372 progress 5 % (2 MB)
54 20:14:37.191949 progress 10 % (4 MB)
55 20:14:37.205484 progress 15 % (7 MB)
56 20:14:37.219047 progress 20 % (9 MB)
57 20:14:37.232803 progress 25 % (12 MB)
58 20:14:37.246586 progress 30 % (14 MB)
59 20:14:37.260278 progress 35 % (17 MB)
60 20:14:37.273836 progress 40 % (19 MB)
61 20:14:37.287521 progress 45 % (22 MB)
62 20:14:37.301094 progress 50 % (24 MB)
63 20:14:37.314627 progress 55 % (27 MB)
64 20:14:37.328263 progress 60 % (29 MB)
65 20:14:37.342158 progress 65 % (32 MB)
66 20:14:37.356017 progress 70 % (34 MB)
67 20:14:37.369689 progress 75 % (36 MB)
68 20:14:37.383098 progress 80 % (39 MB)
69 20:14:37.396735 progress 85 % (41 MB)
70 20:14:37.410291 progress 90 % (44 MB)
71 20:14:37.423567 progress 95 % (46 MB)
72 20:14:37.436998 progress 100 % (49 MB)
73 20:14:37.437236 49 MB downloaded in 0.27 s (179.69 MB/s)
74 20:14:37.437396 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:14:37.437636 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:14:37.437731 start: 1.3 download-retry (timeout 00:10:00) [common]
78 20:14:37.437826 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 20:14:37.438013 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:14:37.438090 saving as /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/dtb/mt8192-asurada-spherion-r0.dtb
81 20:14:37.438151 total size: 47278 (0 MB)
82 20:14:37.438212 No compression specified
83 20:14:37.439336 progress 69 % (0 MB)
84 20:14:37.439614 progress 100 % (0 MB)
85 20:14:37.439776 0 MB downloaded in 0.00 s (27.77 MB/s)
86 20:14:37.439901 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:14:37.440135 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:14:37.440314 start: 1.4 download-retry (timeout 00:10:00) [common]
90 20:14:37.440399 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 20:14:37.440515 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:14:37.440583 saving as /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/modules/modules.tar
93 20:14:37.440643 total size: 8632284 (8 MB)
94 20:14:37.440711 Using unxz to decompress xz
95 20:14:37.444490 progress 0 % (0 MB)
96 20:14:37.465191 progress 5 % (0 MB)
97 20:14:37.489707 progress 10 % (0 MB)
98 20:14:37.514229 progress 15 % (1 MB)
99 20:14:37.537382 progress 20 % (1 MB)
100 20:14:37.563156 progress 25 % (2 MB)
101 20:14:37.589496 progress 30 % (2 MB)
102 20:14:37.615932 progress 35 % (2 MB)
103 20:14:37.641470 progress 40 % (3 MB)
104 20:14:37.666197 progress 45 % (3 MB)
105 20:14:37.691138 progress 50 % (4 MB)
106 20:14:37.716086 progress 55 % (4 MB)
107 20:14:37.742156 progress 60 % (4 MB)
108 20:14:37.767471 progress 65 % (5 MB)
109 20:14:37.793089 progress 70 % (5 MB)
110 20:14:37.818406 progress 75 % (6 MB)
111 20:14:37.844881 progress 80 % (6 MB)
112 20:14:37.871089 progress 85 % (7 MB)
113 20:14:37.898212 progress 90 % (7 MB)
114 20:14:37.927224 progress 95 % (7 MB)
115 20:14:37.956047 progress 100 % (8 MB)
116 20:14:37.961526 8 MB downloaded in 0.52 s (15.80 MB/s)
117 20:14:37.961777 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:14:37.962089 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:14:37.962183 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:14:37.962310 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:14:37.962409 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:14:37.962512 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:14:37.962771 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_
125 20:14:37.962909 makedir: /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin
126 20:14:37.963012 makedir: /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/tests
127 20:14:37.963116 makedir: /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/results
128 20:14:37.963267 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-add-keys
129 20:14:37.963484 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-add-sources
130 20:14:37.963656 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-background-process-start
131 20:14:37.963850 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-background-process-stop
132 20:14:37.963981 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-common-functions
133 20:14:37.964113 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-echo-ipv4
134 20:14:37.964235 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-install-packages
135 20:14:37.964404 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-installed-packages
136 20:14:37.964526 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-os-build
137 20:14:37.964689 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-probe-channel
138 20:14:37.964811 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-probe-ip
139 20:14:37.964954 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-target-ip
140 20:14:37.965094 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-target-mac
141 20:14:37.965220 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-target-storage
142 20:14:37.965350 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-case
143 20:14:37.965479 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-event
144 20:14:37.965603 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-feedback
145 20:14:37.965743 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-raise
146 20:14:37.965893 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-reference
147 20:14:37.966051 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-runner
148 20:14:37.966174 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-set
149 20:14:37.966302 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-test-shell
150 20:14:37.966430 Updating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-install-packages (oe)
151 20:14:37.966586 Updating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/bin/lava-installed-packages (oe)
152 20:14:37.966715 Creating /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/environment
153 20:14:37.966819 LAVA metadata
154 20:14:37.966897 - LAVA_JOB_ID=12928131
155 20:14:37.966964 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:14:37.967124 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:14:37.967211 skipped lava-vland-overlay
158 20:14:37.967286 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:14:37.967376 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:14:37.967489 skipped lava-multinode-overlay
161 20:14:37.967625 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:14:37.967729 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:14:37.967806 Loading test definitions
164 20:14:37.967950 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 20:14:37.968077 Using /lava-12928131 at stage 0
166 20:14:37.968521 uuid=12928131_1.5.2.3.1 testdef=None
167 20:14:37.968611 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 20:14:37.968710 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 20:14:37.969250 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 20:14:37.969482 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 20:14:37.970190 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 20:14:37.970455 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 20:14:37.971117 runner path: /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/0/tests/0_cros-ec test_uuid 12928131_1.5.2.3.1
176 20:14:37.971274 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 20:14:37.971525 Creating lava-test-runner.conf files
179 20:14:37.971634 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928131/lava-overlay-ewu9ytz_/lava-12928131/0 for stage 0
180 20:14:37.971723 - 0_cros-ec
181 20:14:37.971840 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 20:14:37.971961 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 20:14:37.979515 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 20:14:37.979629 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 20:14:37.979747 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 20:14:37.979835 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 20:14:37.979921 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 20:14:38.920395 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 20:14:38.920769 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 20:14:38.920888 extracting modules file /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928131/extract-overlay-ramdisk-n74zdqz5/ramdisk
191 20:14:39.141213 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 20:14:39.141393 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 20:14:39.141487 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928131/compress-overlay-a1pcdikm/overlay-1.5.2.4.tar.gz to ramdisk
194 20:14:39.141567 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928131/compress-overlay-a1pcdikm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928131/extract-overlay-ramdisk-n74zdqz5/ramdisk
195 20:14:39.148171 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 20:14:39.148289 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 20:14:39.148388 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 20:14:39.148481 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 20:14:39.148560 Building ramdisk /var/lib/lava/dispatcher/tmp/12928131/extract-overlay-ramdisk-n74zdqz5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928131/extract-overlay-ramdisk-n74zdqz5/ramdisk
200 20:14:39.778483 >> 271124 blocks
201 20:14:44.490256 rename /var/lib/lava/dispatcher/tmp/12928131/extract-overlay-ramdisk-n74zdqz5/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/ramdisk/ramdisk.cpio.gz
202 20:14:44.490684 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 20:14:44.490810 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 20:14:44.490926 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 20:14:44.491035 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/kernel/Image'
206 20:14:56.962703 Returned 0 in 12 seconds
207 20:14:57.063806 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/kernel/image.itb
208 20:14:57.797833 output: FIT description: Kernel Image image with one or more FDT blobs
209 20:14:57.798231 output: Created: Sun Mar 3 20:14:57 2024
210 20:14:57.798305 output: Image 0 (kernel-1)
211 20:14:57.798367 output: Description:
212 20:14:57.798426 output: Created: Sun Mar 3 20:14:57 2024
213 20:14:57.798486 output: Type: Kernel Image
214 20:14:57.798546 output: Compression: lzma compressed
215 20:14:57.798604 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
216 20:14:57.798664 output: Architecture: AArch64
217 20:14:57.798722 output: OS: Linux
218 20:14:57.798777 output: Load Address: 0x00000000
219 20:14:57.798833 output: Entry Point: 0x00000000
220 20:14:57.798893 output: Hash algo: crc32
221 20:14:57.798949 output: Hash value: 91cb1a17
222 20:14:57.799006 output: Image 1 (fdt-1)
223 20:14:57.799071 output: Description: mt8192-asurada-spherion-r0
224 20:14:57.799128 output: Created: Sun Mar 3 20:14:57 2024
225 20:14:57.799180 output: Type: Flat Device Tree
226 20:14:57.799233 output: Compression: uncompressed
227 20:14:57.799285 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 20:14:57.799338 output: Architecture: AArch64
229 20:14:57.799390 output: Hash algo: crc32
230 20:14:57.799442 output: Hash value: cc4352de
231 20:14:57.799494 output: Image 2 (ramdisk-1)
232 20:14:57.799546 output: Description: unavailable
233 20:14:57.799598 output: Created: Sun Mar 3 20:14:57 2024
234 20:14:57.799650 output: Type: RAMDisk Image
235 20:14:57.799702 output: Compression: Unknown Compression
236 20:14:57.799754 output: Data Size: 47545634 Bytes = 46431.28 KiB = 45.34 MiB
237 20:14:57.799807 output: Architecture: AArch64
238 20:14:57.799859 output: OS: Linux
239 20:14:57.799910 output: Load Address: unavailable
240 20:14:57.799962 output: Entry Point: unavailable
241 20:14:57.800014 output: Hash algo: crc32
242 20:14:57.800065 output: Hash value: 99d91071
243 20:14:57.800116 output: Default Configuration: 'conf-1'
244 20:14:57.800168 output: Configuration 0 (conf-1)
245 20:14:57.800219 output: Description: mt8192-asurada-spherion-r0
246 20:14:57.800271 output: Kernel: kernel-1
247 20:14:57.800322 output: Init Ramdisk: ramdisk-1
248 20:14:57.800374 output: FDT: fdt-1
249 20:14:57.800426 output: Loadables: kernel-1
250 20:14:57.800477 output:
251 20:14:57.800663 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 20:14:57.800760 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 20:14:57.800858 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 20:14:57.800950 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 20:14:57.801034 No LXC device requested
256 20:14:57.801164 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 20:14:57.801265 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 20:14:57.801343 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 20:14:57.801410 Checking files for TFTP limit of 4294967296 bytes.
260 20:14:57.801883 end: 1 tftp-deploy (duration 00:00:21) [common]
261 20:14:57.802056 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 20:14:57.802151 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 20:14:57.802277 substitutions:
264 20:14:57.802345 - {DTB}: 12928131/tftp-deploy-47lgp2yt/dtb/mt8192-asurada-spherion-r0.dtb
265 20:14:57.802409 - {INITRD}: 12928131/tftp-deploy-47lgp2yt/ramdisk/ramdisk.cpio.gz
266 20:14:57.802467 - {KERNEL}: 12928131/tftp-deploy-47lgp2yt/kernel/Image
267 20:14:57.802523 - {LAVA_MAC}: None
268 20:14:57.802578 - {PRESEED_CONFIG}: None
269 20:14:57.802634 - {PRESEED_LOCAL}: None
270 20:14:57.802688 - {RAMDISK}: 12928131/tftp-deploy-47lgp2yt/ramdisk/ramdisk.cpio.gz
271 20:14:57.802742 - {ROOT_PART}: None
272 20:14:57.802795 - {ROOT}: None
273 20:14:57.802848 - {SERVER_IP}: 192.168.201.1
274 20:14:57.802901 - {TEE}: None
275 20:14:57.802955 Parsed boot commands:
276 20:14:57.803010 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 20:14:57.803181 Parsed boot commands: tftpboot 192.168.201.1 12928131/tftp-deploy-47lgp2yt/kernel/image.itb 12928131/tftp-deploy-47lgp2yt/kernel/cmdline
278 20:14:57.803321 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 20:14:57.803407 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 20:14:57.803493 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 20:14:57.803576 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 20:14:57.803645 Not connected, no need to disconnect.
283 20:14:57.803717 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 20:14:57.803797 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 20:14:57.803861 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 20:14:57.807232 Setting prompt string to ['lava-test: # ']
287 20:14:57.807623 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 20:14:57.807732 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 20:14:57.807845 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 20:14:57.807963 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 20:14:57.808199 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 20:15:02.952002 >> Command sent successfully.
293 20:15:02.962127 Returned 0 in 5 seconds
294 20:15:03.063253 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 20:15:03.064567 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 20:15:03.065058 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 20:15:03.065490 Setting prompt string to 'Starting depthcharge on Spherion...'
299 20:15:03.065834 Changing prompt to 'Starting depthcharge on Spherion...'
300 20:15:03.066236 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 20:15:03.067406 [Enter `^Ec?' for help]
302 20:15:03.228672
303 20:15:03.229220
304 20:15:03.229588 F0: 102B 0000
305 20:15:03.229988
306 20:15:03.230327 F3: 1001 0000 [0200]
307 20:15:03.230656
308 20:15:03.231890 F3: 1001 0000
309 20:15:03.232318
310 20:15:03.232658 F7: 102D 0000
311 20:15:03.232978
312 20:15:03.234943 F1: 0000 0000
313 20:15:03.235372
314 20:15:03.235725 V0: 0000 0000 [0001]
315 20:15:03.236046
316 20:15:03.236352 00: 0007 8000
317 20:15:03.238242
318 20:15:03.238667 01: 0000 0000
319 20:15:03.239018
320 20:15:03.239334 BP: 0C00 0209 [0000]
321 20:15:03.239639
322 20:15:03.241617 G0: 1182 0000
323 20:15:03.242082
324 20:15:03.242431 EC: 0000 0021 [4000]
325 20:15:03.242750
326 20:15:03.245112 S7: 0000 0000 [0000]
327 20:15:03.245543
328 20:15:03.248672 CC: 0000 0000 [0001]
329 20:15:03.249145
330 20:15:03.249509 T0: 0000 0040 [010F]
331 20:15:03.249838
332 20:15:03.250197 Jump to BL
333 20:15:03.250512
334 20:15:03.275133
335 20:15:03.275566
336 20:15:03.276002
337 20:15:03.282943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 20:15:03.286386 ARM64: Exception handlers installed.
339 20:15:03.290029 ARM64: Testing exception
340 20:15:03.290724 ARM64: Done test exception
341 20:15:03.300509 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 20:15:03.310784 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 20:15:03.317625 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 20:15:03.327359 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 20:15:03.334198 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 20:15:03.340876 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 20:15:03.351161 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 20:15:03.358083 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 20:15:03.377737 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 20:15:03.380800 WDT: Last reset was cold boot
351 20:15:03.384215 SPI1(PAD0) initialized at 2873684 Hz
352 20:15:03.387557 SPI5(PAD0) initialized at 992727 Hz
353 20:15:03.391008 VBOOT: Loading verstage.
354 20:15:03.397781 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 20:15:03.400697 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 20:15:03.404057 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 20:15:03.407453 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 20:15:03.414922 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 20:15:03.421681 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 20:15:03.432512 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 20:15:03.433055
362 20:15:03.433520
363 20:15:03.442409 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 20:15:03.446004 ARM64: Exception handlers installed.
365 20:15:03.449742 ARM64: Testing exception
366 20:15:03.450238 ARM64: Done test exception
367 20:15:03.456034 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 20:15:03.459578 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 20:15:03.473573 Probing TPM: . done!
370 20:15:03.474157 TPM ready after 0 ms
371 20:15:03.480615 Connected to device vid:did:rid of 1ae0:0028:00
372 20:15:03.487273 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 20:15:03.543624 Initialized TPM device CR50 revision 0
374 20:15:03.555418 tlcl_send_startup: Startup return code is 0
375 20:15:03.555820 TPM: setup succeeded
376 20:15:03.567126 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 20:15:03.575669 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 20:15:03.585902 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 20:15:03.595007 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 20:15:03.597968 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 20:15:03.608269 in-header: 03 07 00 00 08 00 00 00
382 20:15:03.611723 in-data: aa e4 47 04 13 02 00 00
383 20:15:03.615366 Chrome EC: UHEPI supported
384 20:15:03.622312 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 20:15:03.626688 in-header: 03 ad 00 00 08 00 00 00
386 20:15:03.629634 in-data: 00 20 20 08 00 00 00 00
387 20:15:03.630107 Phase 1
388 20:15:03.633393 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 20:15:03.640646 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 20:15:03.644677 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 20:15:03.648630 Recovery requested (1009000e)
392 20:15:03.656963 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 20:15:03.662638 tlcl_extend: response is 0
394 20:15:03.672074 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 20:15:03.677952 tlcl_extend: response is 0
396 20:15:03.685057 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 20:15:03.704842 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 20:15:03.711956 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 20:15:03.712446
400 20:15:03.712912
401 20:15:03.721967 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 20:15:03.725119 ARM64: Exception handlers installed.
403 20:15:03.725560 ARM64: Testing exception
404 20:15:03.728611 ARM64: Done test exception
405 20:15:03.750244 pmic_efuse_setting: Set efuses in 11 msecs
406 20:15:03.753778 pmwrap_interface_init: Select PMIF_VLD_RDY
407 20:15:03.760619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 20:15:03.764145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 20:15:03.767486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 20:15:03.774008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 20:15:03.777646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 20:15:03.785392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 20:15:03.789181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 20:15:03.792873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 20:15:03.796160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 20:15:03.803725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 20:15:03.807517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 20:15:03.811491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 20:15:03.814905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 20:15:03.821586 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 20:15:03.828311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 20:15:03.835077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 20:15:03.838808 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 20:15:03.846288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 20:15:03.849972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 20:15:03.856642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 20:15:03.860279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 20:15:03.867301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 20:15:03.873758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 20:15:03.877067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 20:15:03.884133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 20:15:03.890715 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 20:15:03.894227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 20:15:03.900655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 20:15:03.904247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 20:15:03.907502 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 20:15:03.914608 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 20:15:03.917815 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 20:15:03.924100 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 20:15:03.927958 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 20:15:03.934341 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 20:15:03.937411 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 20:15:03.944149 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 20:15:03.947616 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 20:15:03.954277 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 20:15:03.957310 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 20:15:03.961102 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 20:15:03.968432 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 20:15:03.971604 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 20:15:03.974891 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 20:15:03.978179 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 20:15:03.985281 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 20:15:03.988249 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 20:15:03.991638 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 20:15:03.995288 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 20:15:04.001832 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 20:15:04.005739 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 20:15:04.012815 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 20:15:04.020232 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 20:15:04.027980 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 20:15:04.034956 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 20:15:04.042899 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 20:15:04.046011 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 20:15:04.049715 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 20:15:04.057388 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 20:15:04.064808 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
467 20:15:04.067988 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 20:15:04.074572 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 20:15:04.078393 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 20:15:04.087227 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 20:15:04.096276 [RTC]rtc_get_frequency_meter,154: input=23, output=956
472 20:15:04.105637 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 20:15:04.115099 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 20:15:04.125530 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 20:15:04.129269 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 20:15:04.132458 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 20:15:04.136373 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
478 20:15:04.143928 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 20:15:04.147574 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
480 20:15:04.151068 ADC[4]: Raw value=902876 ID=7
481 20:15:04.151229 ADC[3]: Raw value=213179 ID=1
482 20:15:04.153868 RAM Code: 0x71
483 20:15:04.157325 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 20:15:04.164002 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 20:15:04.171079 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 20:15:04.178045 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 20:15:04.180777 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 20:15:04.184416 in-header: 03 07 00 00 08 00 00 00
489 20:15:04.187770 in-data: aa e4 47 04 13 02 00 00
490 20:15:04.190901 Chrome EC: UHEPI supported
491 20:15:04.198175 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 20:15:04.201456 in-header: 03 ed 00 00 08 00 00 00
493 20:15:04.204794 in-data: 80 20 60 08 00 00 00 00
494 20:15:04.207869 MRC: failed to locate region type 0.
495 20:15:04.214293 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 20:15:04.217891 DRAM-K: Running full calibration
497 20:15:04.224374 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 20:15:04.225004 header.status = 0x0
499 20:15:04.227682 header.version = 0x6 (expected: 0x6)
500 20:15:04.231176 header.size = 0xd00 (expected: 0xd00)
501 20:15:04.234387 header.flags = 0x0
502 20:15:04.238125 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 20:15:04.257209 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 20:15:04.263862 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 20:15:04.267296 dram_init: ddr_geometry: 2
506 20:15:04.270744 [EMI] MDL number = 2
507 20:15:04.271252 [EMI] Get MDL freq = 0
508 20:15:04.273695 dram_init: ddr_type: 0
509 20:15:04.274210 is_discrete_lpddr4: 1
510 20:15:04.276899 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 20:15:04.277438
512 20:15:04.277826
513 20:15:04.280694 [Bian_co] ETT version 0.0.0.1
514 20:15:04.287357 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 20:15:04.287947
516 20:15:04.290451 dramc_set_vcore_voltage set vcore to 650000
517 20:15:04.290990 Read voltage for 800, 4
518 20:15:04.293689 Vio18 = 0
519 20:15:04.294204 Vcore = 650000
520 20:15:04.294591 Vdram = 0
521 20:15:04.297158 Vddq = 0
522 20:15:04.297658 Vmddr = 0
523 20:15:04.300312 dram_init: config_dvfs: 1
524 20:15:04.304172 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 20:15:04.310330 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 20:15:04.313486 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
527 20:15:04.316817 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
528 20:15:04.320025 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 20:15:04.327696 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 20:15:04.328183 MEM_TYPE=3, freq_sel=18
531 20:15:04.330942 sv_algorithm_assistance_LP4_1600
532 20:15:04.334476 ============ PULL DRAM RESETB DOWN ============
533 20:15:04.338211 ========== PULL DRAM RESETB DOWN end =========
534 20:15:04.345203 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 20:15:04.348736 ===================================
536 20:15:04.349171 LPDDR4 DRAM CONFIGURATION
537 20:15:04.352408 ===================================
538 20:15:04.355736 EX_ROW_EN[0] = 0x0
539 20:15:04.356190 EX_ROW_EN[1] = 0x0
540 20:15:04.359147 LP4Y_EN = 0x0
541 20:15:04.359785 WORK_FSP = 0x0
542 20:15:04.362901 WL = 0x2
543 20:15:04.363549 RL = 0x2
544 20:15:04.366489 BL = 0x2
545 20:15:04.367133 RPST = 0x0
546 20:15:04.367551 RD_PRE = 0x0
547 20:15:04.370374 WR_PRE = 0x1
548 20:15:04.370918 WR_PST = 0x0
549 20:15:04.374075 DBI_WR = 0x0
550 20:15:04.374543 DBI_RD = 0x0
551 20:15:04.377313 OTF = 0x1
552 20:15:04.381218 ===================================
553 20:15:04.384856 ===================================
554 20:15:04.385587 ANA top config
555 20:15:04.388428 ===================================
556 20:15:04.392036 DLL_ASYNC_EN = 0
557 20:15:04.392613 ALL_SLAVE_EN = 1
558 20:15:04.396116 NEW_RANK_MODE = 1
559 20:15:04.399943 DLL_IDLE_MODE = 1
560 20:15:04.400730 LP45_APHY_COMB_EN = 1
561 20:15:04.403636 TX_ODT_DIS = 1
562 20:15:04.407215 NEW_8X_MODE = 1
563 20:15:04.410699 ===================================
564 20:15:04.414371 ===================================
565 20:15:04.414888 data_rate = 1600
566 20:15:04.418262 CKR = 1
567 20:15:04.422295 DQ_P2S_RATIO = 8
568 20:15:04.425909 ===================================
569 20:15:04.426428 CA_P2S_RATIO = 8
570 20:15:04.429436 DQ_CA_OPEN = 0
571 20:15:04.433078 DQ_SEMI_OPEN = 0
572 20:15:04.436757 CA_SEMI_OPEN = 0
573 20:15:04.437231 CA_FULL_RATE = 0
574 20:15:04.440553 DQ_CKDIV4_EN = 1
575 20:15:04.444355 CA_CKDIV4_EN = 1
576 20:15:04.448205 CA_PREDIV_EN = 0
577 20:15:04.448684 PH8_DLY = 0
578 20:15:04.452112 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 20:15:04.455260 DQ_AAMCK_DIV = 4
580 20:15:04.459572 CA_AAMCK_DIV = 4
581 20:15:04.460091 CA_ADMCK_DIV = 4
582 20:15:04.462491 DQ_TRACK_CA_EN = 0
583 20:15:04.466738 CA_PICK = 800
584 20:15:04.470548 CA_MCKIO = 800
585 20:15:04.471035 MCKIO_SEMI = 0
586 20:15:04.473999 PLL_FREQ = 3068
587 20:15:04.478169 DQ_UI_PI_RATIO = 32
588 20:15:04.481929 CA_UI_PI_RATIO = 0
589 20:15:04.485239 ===================================
590 20:15:04.485779 ===================================
591 20:15:04.489048 memory_type:LPDDR4
592 20:15:04.493145 GP_NUM : 10
593 20:15:04.493734 SRAM_EN : 1
594 20:15:04.496749 MD32_EN : 0
595 20:15:04.500164 ===================================
596 20:15:04.500751 [ANA_INIT] >>>>>>>>>>>>>>
597 20:15:04.504116 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 20:15:04.508043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 20:15:04.511573 ===================================
600 20:15:04.515592 data_rate = 1600,PCW = 0X7600
601 20:15:04.516030 ===================================
602 20:15:04.519163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 20:15:04.526239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 20:15:04.530024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 20:15:04.537191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 20:15:04.541015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 20:15:04.544808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 20:15:04.545436 [ANA_INIT] flow start
609 20:15:04.548491 [ANA_INIT] PLL >>>>>>>>
610 20:15:04.548970 [ANA_INIT] PLL <<<<<<<<
611 20:15:04.552113 [ANA_INIT] MIDPI >>>>>>>>
612 20:15:04.555958 [ANA_INIT] MIDPI <<<<<<<<
613 20:15:04.556393 [ANA_INIT] DLL >>>>>>>>
614 20:15:04.559299 [ANA_INIT] flow end
615 20:15:04.563037 ============ LP4 DIFF to SE enter ============
616 20:15:04.567259 ============ LP4 DIFF to SE exit ============
617 20:15:04.570765 [ANA_INIT] <<<<<<<<<<<<<
618 20:15:04.571250 [Flow] Enable top DCM control >>>>>
619 20:15:04.574423 [Flow] Enable top DCM control <<<<<
620 20:15:04.578137 Enable DLL master slave shuffle
621 20:15:04.585996 ==============================================================
622 20:15:04.586439 Gating Mode config
623 20:15:04.593367 ==============================================================
624 20:15:04.594000 Config description:
625 20:15:04.604176 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 20:15:04.607683 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 20:15:04.615250 SELPH_MODE 0: By rank 1: By Phase
628 20:15:04.619387 ==============================================================
629 20:15:04.623071 GAT_TRACK_EN = 1
630 20:15:04.626403 RX_GATING_MODE = 2
631 20:15:04.630038 RX_GATING_TRACK_MODE = 2
632 20:15:04.630520 SELPH_MODE = 1
633 20:15:04.633905 PICG_EARLY_EN = 1
634 20:15:04.637447 VALID_LAT_VALUE = 1
635 20:15:04.645590 ==============================================================
636 20:15:04.646204 Enter into Gating configuration >>>>
637 20:15:04.648795 Exit from Gating configuration <<<<
638 20:15:04.652614 Enter into DVFS_PRE_config >>>>>
639 20:15:04.662522 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 20:15:04.666176 Exit from DVFS_PRE_config <<<<<
641 20:15:04.669301 Enter into PICG configuration >>>>
642 20:15:04.672294 Exit from PICG configuration <<<<
643 20:15:04.676095 [RX_INPUT] configuration >>>>>
644 20:15:04.679136 [RX_INPUT] configuration <<<<<
645 20:15:04.686143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 20:15:04.689370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 20:15:04.696040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 20:15:04.702630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 20:15:04.709436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 20:15:04.716104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 20:15:04.719332 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 20:15:04.722607 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 20:15:04.725985 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 20:15:04.729924 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 20:15:04.733165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 20:15:04.740115 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 20:15:04.743264 ===================================
658 20:15:04.743778 LPDDR4 DRAM CONFIGURATION
659 20:15:04.746657 ===================================
660 20:15:04.750122 EX_ROW_EN[0] = 0x0
661 20:15:04.753870 EX_ROW_EN[1] = 0x0
662 20:15:04.754403 LP4Y_EN = 0x0
663 20:15:04.757192 WORK_FSP = 0x0
664 20:15:04.757779 WL = 0x2
665 20:15:04.760352 RL = 0x2
666 20:15:04.760835 BL = 0x2
667 20:15:04.763506 RPST = 0x0
668 20:15:04.763990 RD_PRE = 0x0
669 20:15:04.767411 WR_PRE = 0x1
670 20:15:04.768004 WR_PST = 0x0
671 20:15:04.770453 DBI_WR = 0x0
672 20:15:04.770937 DBI_RD = 0x0
673 20:15:04.773499 OTF = 0x1
674 20:15:04.777215 ===================================
675 20:15:04.780373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 20:15:04.783904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 20:15:04.790558 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 20:15:04.793650 ===================================
679 20:15:04.794159 LPDDR4 DRAM CONFIGURATION
680 20:15:04.797071 ===================================
681 20:15:04.800486 EX_ROW_EN[0] = 0x10
682 20:15:04.801064 EX_ROW_EN[1] = 0x0
683 20:15:04.803813 LP4Y_EN = 0x0
684 20:15:04.804396 WORK_FSP = 0x0
685 20:15:04.807494 WL = 0x2
686 20:15:04.808078 RL = 0x2
687 20:15:04.810536 BL = 0x2
688 20:15:04.811014 RPST = 0x0
689 20:15:04.813713 RD_PRE = 0x0
690 20:15:04.814268 WR_PRE = 0x1
691 20:15:04.817068 WR_PST = 0x0
692 20:15:04.820267 DBI_WR = 0x0
693 20:15:04.820745 DBI_RD = 0x0
694 20:15:04.823864 OTF = 0x1
695 20:15:04.827345 ===================================
696 20:15:04.830469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 20:15:04.835493 nWR fixed to 40
698 20:15:04.839108 [ModeRegInit_LP4] CH0 RK0
699 20:15:04.839586 [ModeRegInit_LP4] CH0 RK1
700 20:15:04.842615 [ModeRegInit_LP4] CH1 RK0
701 20:15:04.845758 [ModeRegInit_LP4] CH1 RK1
702 20:15:04.846310 match AC timing 13
703 20:15:04.852604 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 20:15:04.855921 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 20:15:04.859283 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 20:15:04.865854 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 20:15:04.868936 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 20:15:04.869447 [EMI DOE] emi_dcm 0
709 20:15:04.876002 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 20:15:04.876585 ==
711 20:15:04.878853 Dram Type= 6, Freq= 0, CH_0, rank 0
712 20:15:04.882379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 20:15:04.882870 ==
714 20:15:04.889038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 20:15:04.895820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 20:15:04.903053 [CA 0] Center 38 (7~69) winsize 63
717 20:15:04.906607 [CA 1] Center 38 (7~69) winsize 63
718 20:15:04.909843 [CA 2] Center 35 (5~66) winsize 62
719 20:15:04.913029 [CA 3] Center 35 (5~66) winsize 62
720 20:15:04.916763 [CA 4] Center 34 (4~65) winsize 62
721 20:15:04.919869 [CA 5] Center 34 (4~64) winsize 61
722 20:15:04.920417
723 20:15:04.922816 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 20:15:04.923395
725 20:15:04.926165 [CATrainingPosCal] consider 1 rank data
726 20:15:04.929691 u2DelayCellTimex100 = 270/100 ps
727 20:15:04.932879 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 20:15:04.936463 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 20:15:04.943163 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 20:15:04.946219 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 20:15:04.949779 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 20:15:04.953201 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
733 20:15:04.953672
734 20:15:04.956186 CA PerBit enable=1, Macro0, CA PI delay=34
735 20:15:04.956611
736 20:15:04.959814 [CBTSetCACLKResult] CA Dly = 34
737 20:15:04.960239 CS Dly: 6 (0~37)
738 20:15:04.960586 ==
739 20:15:04.963189 Dram Type= 6, Freq= 0, CH_0, rank 1
740 20:15:04.969641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 20:15:04.970111 ==
742 20:15:04.973049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 20:15:04.979560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 20:15:04.989501 [CA 0] Center 38 (7~69) winsize 63
745 20:15:04.992783 [CA 1] Center 38 (8~69) winsize 62
746 20:15:04.996087 [CA 2] Center 36 (6~67) winsize 62
747 20:15:04.999659 [CA 3] Center 36 (5~67) winsize 63
748 20:15:05.003004 [CA 4] Center 35 (4~66) winsize 63
749 20:15:05.006186 [CA 5] Center 34 (4~65) winsize 62
750 20:15:05.006643
751 20:15:05.009345 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 20:15:05.009678
753 20:15:05.013248 [CATrainingPosCal] consider 2 rank data
754 20:15:05.015986 u2DelayCellTimex100 = 270/100 ps
755 20:15:05.019220 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 20:15:05.023360 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 20:15:05.029729 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 20:15:05.032877 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 20:15:05.036045 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 20:15:05.039280 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 20:15:05.039515
762 20:15:05.042727 CA PerBit enable=1, Macro0, CA PI delay=34
763 20:15:05.042962
764 20:15:05.045937 [CBTSetCACLKResult] CA Dly = 34
765 20:15:05.046226 CS Dly: 6 (0~38)
766 20:15:05.046420
767 20:15:05.049849 ----->DramcWriteLeveling(PI) begin...
768 20:15:05.052583 ==
769 20:15:05.052816 Dram Type= 6, Freq= 0, CH_0, rank 0
770 20:15:05.059114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 20:15:05.059200 ==
772 20:15:05.062704 Write leveling (Byte 0): 33 => 33
773 20:15:05.066295 Write leveling (Byte 1): 27 => 27
774 20:15:05.069207 DramcWriteLeveling(PI) end<-----
775 20:15:05.069305
776 20:15:05.069399 ==
777 20:15:05.072689 Dram Type= 6, Freq= 0, CH_0, rank 0
778 20:15:05.075892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 20:15:05.076020 ==
780 20:15:05.079326 [Gating] SW mode calibration
781 20:15:05.086380 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 20:15:05.090145 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 20:15:05.093716 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 20:15:05.100721 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 20:15:05.104359 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 20:15:05.107600 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 20:15:05.111228 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 20:15:05.118564 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 20:15:05.121876 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 20:15:05.124976 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 20:15:05.132029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 20:15:05.135176 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 20:15:05.138642 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 20:15:05.142043 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 20:15:05.148438 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 20:15:05.151626 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 20:15:05.155075 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 20:15:05.161954 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 20:15:05.165009 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 20:15:05.168398 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
801 20:15:05.175422 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 20:15:05.178543 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 20:15:05.181789 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 20:15:05.188679 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 20:15:05.191861 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 20:15:05.195136 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 20:15:05.202263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 20:15:05.205173 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
809 20:15:05.209173 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 20:15:05.212313 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
811 20:15:05.219009 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 20:15:05.222269 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 20:15:05.225741 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 20:15:05.232281 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 20:15:05.235485 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 20:15:05.238693 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
817 20:15:05.245681 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
818 20:15:05.249084 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
819 20:15:05.251982 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 20:15:05.258779 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 20:15:05.262080 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 20:15:05.265240 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 20:15:05.271963 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 20:15:05.275458 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
825 20:15:05.278726 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
826 20:15:05.285434 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
827 20:15:05.288637 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 20:15:05.291689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 20:15:05.298641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 20:15:05.302085 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 20:15:05.305472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 20:15:05.312265 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 20:15:05.315408 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 20:15:05.318589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 20:15:05.321982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 20:15:05.328796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 20:15:05.332721 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 20:15:05.336195 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 20:15:05.342142 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 20:15:05.345824 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 20:15:05.349349 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 20:15:05.355842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 20:15:05.359162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 20:15:05.362156 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 20:15:05.369133 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 20:15:05.372724 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 20:15:05.375686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 20:15:05.382384 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 20:15:05.383161 Total UI for P1: 0, mck2ui 16
850 20:15:05.389119 best dqsien dly found for B0: ( 0, 14, 2)
851 20:15:05.392254 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 20:15:05.395672 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 20:15:05.399191 Total UI for P1: 0, mck2ui 16
854 20:15:05.402615 best dqsien dly found for B1: ( 0, 14, 6)
855 20:15:05.405615 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 20:15:05.409278 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 20:15:05.409793
858 20:15:05.412647 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 20:15:05.415756 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 20:15:05.418926 [Gating] SW calibration Done
861 20:15:05.419444 ==
862 20:15:05.422311 Dram Type= 6, Freq= 0, CH_0, rank 0
863 20:15:05.429173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 20:15:05.429606 ==
865 20:15:05.429978 RX Vref Scan: 0
866 20:15:05.430309
867 20:15:05.432284 RX Vref 0 -> 0, step: 1
868 20:15:05.432714
869 20:15:05.435814 RX Delay -130 -> 252, step: 16
870 20:15:05.438893 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 20:15:05.442499 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
872 20:15:05.445852 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 20:15:05.448898 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 20:15:05.455718 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 20:15:05.459228 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 20:15:05.462660 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 20:15:05.465902 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 20:15:05.469230 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 20:15:05.475929 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 20:15:05.479332 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 20:15:05.482531 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 20:15:05.485419 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 20:15:05.488852 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
884 20:15:05.495714 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 20:15:05.499564 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
886 20:15:05.500120 ==
887 20:15:05.502540 Dram Type= 6, Freq= 0, CH_0, rank 0
888 20:15:05.506379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 20:15:05.506941 ==
890 20:15:05.508888 DQS Delay:
891 20:15:05.509340 DQS0 = 0, DQS1 = 0
892 20:15:05.509787 DQM Delay:
893 20:15:05.512546 DQM0 = 88, DQM1 = 77
894 20:15:05.512995 DQ Delay:
895 20:15:05.515578 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
896 20:15:05.519170 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 20:15:05.522442 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 20:15:05.526105 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
899 20:15:05.526533
900 20:15:05.526917
901 20:15:05.527258 ==
902 20:15:05.529099 Dram Type= 6, Freq= 0, CH_0, rank 0
903 20:15:05.535853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 20:15:05.536282 ==
905 20:15:05.536623
906 20:15:05.536940
907 20:15:05.537243 TX Vref Scan disable
908 20:15:05.539690 == TX Byte 0 ==
909 20:15:05.542971 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
910 20:15:05.545901 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
911 20:15:05.549549 == TX Byte 1 ==
912 20:15:05.552797 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
913 20:15:05.556433 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
914 20:15:05.559590 ==
915 20:15:05.560014 Dram Type= 6, Freq= 0, CH_0, rank 0
916 20:15:05.566183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 20:15:05.566644 ==
918 20:15:05.579352 TX Vref=22, minBit 8, minWin=26, winSum=440
919 20:15:05.582434 TX Vref=24, minBit 8, minWin=27, winSum=446
920 20:15:05.585710 TX Vref=26, minBit 8, minWin=27, winSum=449
921 20:15:05.589506 TX Vref=28, minBit 13, minWin=27, winSum=456
922 20:15:05.592605 TX Vref=30, minBit 5, minWin=28, winSum=459
923 20:15:05.598869 TX Vref=32, minBit 3, minWin=28, winSum=457
924 20:15:05.602562 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
925 20:15:05.603082
926 20:15:05.605753 Final TX Range 1 Vref 30
927 20:15:05.606294
928 20:15:05.606646 ==
929 20:15:05.608836 Dram Type= 6, Freq= 0, CH_0, rank 0
930 20:15:05.612407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 20:15:05.612973 ==
932 20:15:05.615568
933 20:15:05.615991
934 20:15:05.616418 TX Vref Scan disable
935 20:15:05.619213 == TX Byte 0 ==
936 20:15:05.622651 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
937 20:15:05.626296 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
938 20:15:05.629516 == TX Byte 1 ==
939 20:15:05.632946 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
940 20:15:05.636501 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
941 20:15:05.637041
942 20:15:05.639604 [DATLAT]
943 20:15:05.640154 Freq=800, CH0 RK0
944 20:15:05.640502
945 20:15:05.643072 DATLAT Default: 0xa
946 20:15:05.643610 0, 0xFFFF, sum = 0
947 20:15:05.646090 1, 0xFFFF, sum = 0
948 20:15:05.646561 2, 0xFFFF, sum = 0
949 20:15:05.649489 3, 0xFFFF, sum = 0
950 20:15:05.649987 4, 0xFFFF, sum = 0
951 20:15:05.652820 5, 0xFFFF, sum = 0
952 20:15:05.653256 6, 0xFFFF, sum = 0
953 20:15:05.656378 7, 0xFFFF, sum = 0
954 20:15:05.656879 8, 0xFFFF, sum = 0
955 20:15:05.659606 9, 0x0, sum = 1
956 20:15:05.660045 10, 0x0, sum = 2
957 20:15:05.663028 11, 0x0, sum = 3
958 20:15:05.663576 12, 0x0, sum = 4
959 20:15:05.666819 best_step = 10
960 20:15:05.667367
961 20:15:05.667718 ==
962 20:15:05.669691 Dram Type= 6, Freq= 0, CH_0, rank 0
963 20:15:05.673238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 20:15:05.673701 ==
965 20:15:05.676334 RX Vref Scan: 1
966 20:15:05.676803
967 20:15:05.677187 Set Vref Range= 32 -> 127
968 20:15:05.677523
969 20:15:05.679425 RX Vref 32 -> 127, step: 1
970 20:15:05.679855
971 20:15:05.683132 RX Delay -95 -> 252, step: 8
972 20:15:05.683215
973 20:15:05.685797 Set Vref, RX VrefLevel [Byte0]: 32
974 20:15:05.689967 [Byte1]: 32
975 20:15:05.690423
976 20:15:05.693247 Set Vref, RX VrefLevel [Byte0]: 33
977 20:15:05.696239 [Byte1]: 33
978 20:15:05.700032
979 20:15:05.700545 Set Vref, RX VrefLevel [Byte0]: 34
980 20:15:05.702990 [Byte1]: 34
981 20:15:05.707380
982 20:15:05.707847 Set Vref, RX VrefLevel [Byte0]: 35
983 20:15:05.710372 [Byte1]: 35
984 20:15:05.714660
985 20:15:05.715136 Set Vref, RX VrefLevel [Byte0]: 36
986 20:15:05.718109 [Byte1]: 36
987 20:15:05.722182
988 20:15:05.722665 Set Vref, RX VrefLevel [Byte0]: 37
989 20:15:05.725856 [Byte1]: 37
990 20:15:05.730459
991 20:15:05.731022 Set Vref, RX VrefLevel [Byte0]: 38
992 20:15:05.734068 [Byte1]: 38
993 20:15:05.737453
994 20:15:05.737902 Set Vref, RX VrefLevel [Byte0]: 39
995 20:15:05.741040 [Byte1]: 39
996 20:15:05.745049
997 20:15:05.745616 Set Vref, RX VrefLevel [Byte0]: 40
998 20:15:05.748732 [Byte1]: 40
999 20:15:05.753147
1000 20:15:05.753755 Set Vref, RX VrefLevel [Byte0]: 41
1001 20:15:05.756251 [Byte1]: 41
1002 20:15:05.760746
1003 20:15:05.761369 Set Vref, RX VrefLevel [Byte0]: 42
1004 20:15:05.763875 [Byte1]: 42
1005 20:15:05.768302
1006 20:15:05.768866 Set Vref, RX VrefLevel [Byte0]: 43
1007 20:15:05.771776 [Byte1]: 43
1008 20:15:05.775582
1009 20:15:05.776008 Set Vref, RX VrefLevel [Byte0]: 44
1010 20:15:05.779247 [Byte1]: 44
1011 20:15:05.783777
1012 20:15:05.784208 Set Vref, RX VrefLevel [Byte0]: 45
1013 20:15:05.786892 [Byte1]: 45
1014 20:15:05.790957
1015 20:15:05.791476 Set Vref, RX VrefLevel [Byte0]: 46
1016 20:15:05.794115 [Byte1]: 46
1017 20:15:05.798418
1018 20:15:05.799011 Set Vref, RX VrefLevel [Byte0]: 47
1019 20:15:05.801346 [Byte1]: 47
1020 20:15:05.806238
1021 20:15:05.806739 Set Vref, RX VrefLevel [Byte0]: 48
1022 20:15:05.809115 [Byte1]: 48
1023 20:15:05.813636
1024 20:15:05.814119 Set Vref, RX VrefLevel [Byte0]: 49
1025 20:15:05.817087 [Byte1]: 49
1026 20:15:05.820575
1027 20:15:05.820657 Set Vref, RX VrefLevel [Byte0]: 50
1028 20:15:05.824000 [Byte1]: 50
1029 20:15:05.828562
1030 20:15:05.828645 Set Vref, RX VrefLevel [Byte0]: 51
1031 20:15:05.831844 [Byte1]: 51
1032 20:15:05.835900
1033 20:15:05.835983 Set Vref, RX VrefLevel [Byte0]: 52
1034 20:15:05.839186 [Byte1]: 52
1035 20:15:05.843623
1036 20:15:05.843708 Set Vref, RX VrefLevel [Byte0]: 53
1037 20:15:05.847308 [Byte1]: 53
1038 20:15:05.851238
1039 20:15:05.851315 Set Vref, RX VrefLevel [Byte0]: 54
1040 20:15:05.854499 [Byte1]: 54
1041 20:15:05.858718
1042 20:15:05.858790 Set Vref, RX VrefLevel [Byte0]: 55
1043 20:15:05.862281 [Byte1]: 55
1044 20:15:05.866390
1045 20:15:05.866479 Set Vref, RX VrefLevel [Byte0]: 56
1046 20:15:05.869775 [Byte1]: 56
1047 20:15:05.874421
1048 20:15:05.874525 Set Vref, RX VrefLevel [Byte0]: 57
1049 20:15:05.877547 [Byte1]: 57
1050 20:15:05.881666
1051 20:15:05.881829 Set Vref, RX VrefLevel [Byte0]: 58
1052 20:15:05.884830 [Byte1]: 58
1053 20:15:05.889422
1054 20:15:05.889511 Set Vref, RX VrefLevel [Byte0]: 59
1055 20:15:05.892873 [Byte1]: 59
1056 20:15:05.896882
1057 20:15:05.896976 Set Vref, RX VrefLevel [Byte0]: 60
1058 20:15:05.900103 [Byte1]: 60
1059 20:15:05.904322
1060 20:15:05.904435 Set Vref, RX VrefLevel [Byte0]: 61
1061 20:15:05.907956 [Byte1]: 61
1062 20:15:05.912198
1063 20:15:05.912327 Set Vref, RX VrefLevel [Byte0]: 62
1064 20:15:05.915435 [Byte1]: 62
1065 20:15:05.919867
1066 20:15:05.920084 Set Vref, RX VrefLevel [Byte0]: 63
1067 20:15:05.922755 [Byte1]: 63
1068 20:15:05.927340
1069 20:15:05.927515 Set Vref, RX VrefLevel [Byte0]: 64
1070 20:15:05.931257 [Byte1]: 64
1071 20:15:05.935523
1072 20:15:05.935831 Set Vref, RX VrefLevel [Byte0]: 65
1073 20:15:05.938737 [Byte1]: 65
1074 20:15:05.942669
1075 20:15:05.943000 Set Vref, RX VrefLevel [Byte0]: 66
1076 20:15:05.946199 [Byte1]: 66
1077 20:15:05.950214
1078 20:15:05.950603 Set Vref, RX VrefLevel [Byte0]: 67
1079 20:15:05.954250 [Byte1]: 67
1080 20:15:05.958242
1081 20:15:05.958915 Set Vref, RX VrefLevel [Byte0]: 68
1082 20:15:05.961370 [Byte1]: 68
1083 20:15:05.965487
1084 20:15:05.965926 Set Vref, RX VrefLevel [Byte0]: 69
1085 20:15:05.968819 [Byte1]: 69
1086 20:15:05.973263
1087 20:15:05.974025 Set Vref, RX VrefLevel [Byte0]: 70
1088 20:15:05.976155 [Byte1]: 70
1089 20:15:05.980790
1090 20:15:05.981257 Set Vref, RX VrefLevel [Byte0]: 71
1091 20:15:05.984551 [Byte1]: 71
1092 20:15:05.988597
1093 20:15:05.989162 Set Vref, RX VrefLevel [Byte0]: 72
1094 20:15:05.991960 [Byte1]: 72
1095 20:15:05.996398
1096 20:15:05.996966 Set Vref, RX VrefLevel [Byte0]: 73
1097 20:15:05.999024 [Byte1]: 73
1098 20:15:06.004291
1099 20:15:06.004855 Set Vref, RX VrefLevel [Byte0]: 74
1100 20:15:06.007252 [Byte1]: 74
1101 20:15:06.011245
1102 20:15:06.011864 Set Vref, RX VrefLevel [Byte0]: 75
1103 20:15:06.014799 [Byte1]: 75
1104 20:15:06.018593
1105 20:15:06.019061 Set Vref, RX VrefLevel [Byte0]: 76
1106 20:15:06.022287 [Byte1]: 76
1107 20:15:06.026310
1108 20:15:06.026814 Set Vref, RX VrefLevel [Byte0]: 77
1109 20:15:06.030008 [Byte1]: 77
1110 20:15:06.034028
1111 20:15:06.034591 Set Vref, RX VrefLevel [Byte0]: 78
1112 20:15:06.037369 [Byte1]: 78
1113 20:15:06.041297
1114 20:15:06.041980 Final RX Vref Byte 0 = 63 to rank0
1115 20:15:06.044843 Final RX Vref Byte 1 = 62 to rank0
1116 20:15:06.048361 Final RX Vref Byte 0 = 63 to rank1
1117 20:15:06.051689 Final RX Vref Byte 1 = 62 to rank1==
1118 20:15:06.054960 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 20:15:06.058371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 20:15:06.061806 ==
1121 20:15:06.062393 DQS Delay:
1122 20:15:06.062804 DQS0 = 0, DQS1 = 0
1123 20:15:06.065037 DQM Delay:
1124 20:15:06.065500 DQM0 = 93, DQM1 = 82
1125 20:15:06.068534 DQ Delay:
1126 20:15:06.071978 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1127 20:15:06.072445 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1128 20:15:06.075045 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1129 20:15:06.078771 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1130 20:15:06.082035
1131 20:15:06.082598
1132 20:15:06.089039 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1133 20:15:06.092005 CH0 RK0: MR19=606, MR18=3833
1134 20:15:06.098857 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1135 20:15:06.099431
1136 20:15:06.101791 ----->DramcWriteLeveling(PI) begin...
1137 20:15:06.102303 ==
1138 20:15:06.105110 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 20:15:06.108259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 20:15:06.108732 ==
1141 20:15:06.111634 Write leveling (Byte 0): 31 => 31
1142 20:15:06.115248 Write leveling (Byte 1): 31 => 31
1143 20:15:06.118454 DramcWriteLeveling(PI) end<-----
1144 20:15:06.118918
1145 20:15:06.119290 ==
1146 20:15:06.121758 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 20:15:06.125181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 20:15:06.125765 ==
1149 20:15:06.128338 [Gating] SW mode calibration
1150 20:15:06.135247 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 20:15:06.142229 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 20:15:06.145381 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 20:15:06.148904 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 20:15:06.195769 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 20:15:06.195860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 20:15:06.196182 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 20:15:06.196449 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 20:15:06.196563 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 20:15:06.197028 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 20:15:06.197127 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 20:15:06.197405 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 20:15:06.197503 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 20:15:06.197909 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 20:15:06.198028 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 20:15:06.230612 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 20:15:06.230953 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 20:15:06.231089 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 20:15:06.231209 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 20:15:06.231289 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1170 20:15:06.231380 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 20:15:06.232106 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 20:15:06.234789 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 20:15:06.238233 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 20:15:06.241594 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 20:15:06.244801 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 20:15:06.251684 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 20:15:06.254649 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1178 20:15:06.258236 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1179 20:15:06.265088 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 20:15:06.268150 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 20:15:06.271691 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 20:15:06.278321 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 20:15:06.281703 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 20:15:06.285114 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 20:15:06.288284 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1186 20:15:06.295007 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (0 0)
1187 20:15:06.298458 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 20:15:06.301810 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 20:15:06.308358 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 20:15:06.311597 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 20:15:06.315005 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 20:15:06.321105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 20:15:06.324740 0 11 4 | B1->B0 | 2626 3131 | 0 1 | (0 0) (0 0)
1194 20:15:06.327951 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1195 20:15:06.335516 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 20:15:06.339385 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 20:15:06.343032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 20:15:06.346808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 20:15:06.350362 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 20:15:06.356825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 20:15:06.360675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 20:15:06.364290 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 20:15:06.367580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 20:15:06.374339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 20:15:06.377519 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 20:15:06.381078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 20:15:06.387839 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 20:15:06.391120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 20:15:06.394262 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 20:15:06.401145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 20:15:06.404428 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 20:15:06.407967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 20:15:06.411166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 20:15:06.417700 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 20:15:06.421302 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 20:15:06.424468 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 20:15:06.431052 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1218 20:15:06.434546 Total UI for P1: 0, mck2ui 16
1219 20:15:06.437971 best dqsien dly found for B1: ( 0, 14, 2)
1220 20:15:06.441335 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 20:15:06.444251 Total UI for P1: 0, mck2ui 16
1222 20:15:06.447879 best dqsien dly found for B0: ( 0, 14, 4)
1223 20:15:06.451067 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1224 20:15:06.454628 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1225 20:15:06.454712
1226 20:15:06.458026 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 20:15:06.461105 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1228 20:15:06.464345 [Gating] SW calibration Done
1229 20:15:06.464431 ==
1230 20:15:06.467869 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 20:15:06.471015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 20:15:06.471099 ==
1233 20:15:06.474372 RX Vref Scan: 0
1234 20:15:06.474454
1235 20:15:06.477802 RX Vref 0 -> 0, step: 1
1236 20:15:06.477911
1237 20:15:06.481545 RX Delay -130 -> 252, step: 16
1238 20:15:06.484547 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1239 20:15:06.487830 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1240 20:15:06.491129 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1241 20:15:06.494453 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1242 20:15:06.500939 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1243 20:15:06.504554 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1244 20:15:06.508087 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1245 20:15:06.510978 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1246 20:15:06.514438 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1247 20:15:06.517665 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1248 20:15:06.524315 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1249 20:15:06.527901 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1250 20:15:06.531265 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1251 20:15:06.534385 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1252 20:15:06.541349 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1253 20:15:06.544624 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1254 20:15:06.544708 ==
1255 20:15:06.547671 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 20:15:06.551053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 20:15:06.551137 ==
1258 20:15:06.551205 DQS Delay:
1259 20:15:06.554500 DQS0 = 0, DQS1 = 0
1260 20:15:06.554583 DQM Delay:
1261 20:15:06.557779 DQM0 = 92, DQM1 = 80
1262 20:15:06.557887 DQ Delay:
1263 20:15:06.561199 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1264 20:15:06.564627 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1265 20:15:06.567947 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1266 20:15:06.571168 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =85
1267 20:15:06.571251
1268 20:15:06.571317
1269 20:15:06.571378 ==
1270 20:15:06.574397 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 20:15:06.578153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 20:15:06.581132 ==
1273 20:15:06.581215
1274 20:15:06.581281
1275 20:15:06.581344 TX Vref Scan disable
1276 20:15:06.584515 == TX Byte 0 ==
1277 20:15:06.587894 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 20:15:06.591094 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 20:15:06.594312 == TX Byte 1 ==
1280 20:15:06.597915 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1281 20:15:06.601067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1282 20:15:06.604441 ==
1283 20:15:06.604524 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 20:15:06.611282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 20:15:06.611366 ==
1286 20:15:06.623628 TX Vref=22, minBit 3, minWin=27, winSum=445
1287 20:15:06.626875 TX Vref=24, minBit 8, minWin=27, winSum=446
1288 20:15:06.629888 TX Vref=26, minBit 8, minWin=27, winSum=450
1289 20:15:06.633462 TX Vref=28, minBit 8, minWin=27, winSum=453
1290 20:15:06.637226 TX Vref=30, minBit 8, minWin=27, winSum=455
1291 20:15:06.640089 TX Vref=32, minBit 8, minWin=27, winSum=454
1292 20:15:06.647077 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
1293 20:15:06.647161
1294 20:15:06.650022 Final TX Range 1 Vref 30
1295 20:15:06.650105
1296 20:15:06.650170 ==
1297 20:15:06.653544 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 20:15:06.656787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 20:15:06.656869 ==
1300 20:15:06.656934
1301 20:15:06.656995
1302 20:15:06.660674 TX Vref Scan disable
1303 20:15:06.663671 == TX Byte 0 ==
1304 20:15:06.667013 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1305 20:15:06.670280 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1306 20:15:06.673709 == TX Byte 1 ==
1307 20:15:06.677028 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1308 20:15:06.680899 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1309 20:15:06.680981
1310 20:15:06.683480 [DATLAT]
1311 20:15:06.683561 Freq=800, CH0 RK1
1312 20:15:06.683627
1313 20:15:06.686833 DATLAT Default: 0xa
1314 20:15:06.686914 0, 0xFFFF, sum = 0
1315 20:15:06.690448 1, 0xFFFF, sum = 0
1316 20:15:06.690530 2, 0xFFFF, sum = 0
1317 20:15:06.693861 3, 0xFFFF, sum = 0
1318 20:15:06.693973 4, 0xFFFF, sum = 0
1319 20:15:06.697226 5, 0xFFFF, sum = 0
1320 20:15:06.697309 6, 0xFFFF, sum = 0
1321 20:15:06.700081 7, 0xFFFF, sum = 0
1322 20:15:06.700165 8, 0xFFFF, sum = 0
1323 20:15:06.703354 9, 0x0, sum = 1
1324 20:15:06.703437 10, 0x0, sum = 2
1325 20:15:06.707490 11, 0x0, sum = 3
1326 20:15:06.707573 12, 0x0, sum = 4
1327 20:15:06.710269 best_step = 10
1328 20:15:06.710350
1329 20:15:06.710415 ==
1330 20:15:06.713519 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 20:15:06.716796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 20:15:06.716883 ==
1333 20:15:06.720239 RX Vref Scan: 0
1334 20:15:06.720320
1335 20:15:06.720388 RX Vref 0 -> 0, step: 1
1336 20:15:06.720450
1337 20:15:06.723467 RX Delay -79 -> 252, step: 8
1338 20:15:06.730104 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1339 20:15:06.733623 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1340 20:15:06.736893 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1341 20:15:06.739944 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1342 20:15:06.743774 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1343 20:15:06.750481 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1344 20:15:06.753371 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1345 20:15:06.757084 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1346 20:15:06.760104 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1347 20:15:06.763339 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1348 20:15:06.770256 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1349 20:15:06.773608 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1350 20:15:06.777134 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1351 20:15:06.780270 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1352 20:15:06.783439 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1353 20:15:06.790335 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1354 20:15:06.790418 ==
1355 20:15:06.793670 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 20:15:06.797192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 20:15:06.797275 ==
1358 20:15:06.797340 DQS Delay:
1359 20:15:06.800269 DQS0 = 0, DQS1 = 0
1360 20:15:06.800351 DQM Delay:
1361 20:15:06.803614 DQM0 = 90, DQM1 = 80
1362 20:15:06.803695 DQ Delay:
1363 20:15:06.806998 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1364 20:15:06.810314 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1365 20:15:06.813460 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1366 20:15:06.816705 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1367 20:15:06.816786
1368 20:15:06.816850
1369 20:15:06.823676 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
1370 20:15:06.827272 CH0 RK1: MR19=606, MR18=3D17
1371 20:15:06.833605 CH0_RK1: MR19=0x606, MR18=0x3D17, DQSOSC=394, MR23=63, INC=95, DEC=63
1372 20:15:06.836808 [RxdqsGatingPostProcess] freq 800
1373 20:15:06.843810 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 20:15:06.843922 Pre-setting of DQS Precalculation
1375 20:15:06.850285 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 20:15:06.850368 ==
1377 20:15:06.853558 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 20:15:06.857457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 20:15:06.857539 ==
1380 20:15:06.863879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 20:15:06.870244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 20:15:06.878488 [CA 0] Center 36 (6~67) winsize 62
1383 20:15:06.882242 [CA 1] Center 36 (6~67) winsize 62
1384 20:15:06.885175 [CA 2] Center 34 (4~65) winsize 62
1385 20:15:06.888509 [CA 3] Center 34 (4~65) winsize 62
1386 20:15:06.891800 [CA 4] Center 34 (4~65) winsize 62
1387 20:15:06.894853 [CA 5] Center 33 (3~64) winsize 62
1388 20:15:06.894935
1389 20:15:06.898332 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1390 20:15:06.898414
1391 20:15:06.901484 [CATrainingPosCal] consider 1 rank data
1392 20:15:06.905152 u2DelayCellTimex100 = 270/100 ps
1393 20:15:06.908293 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 20:15:06.911607 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 20:15:06.918487 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 20:15:06.921822 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 20:15:06.924897 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 20:15:06.928559 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 20:15:06.928643
1400 20:15:06.931894 CA PerBit enable=1, Macro0, CA PI delay=33
1401 20:15:06.932003
1402 20:15:06.935136 [CBTSetCACLKResult] CA Dly = 33
1403 20:15:06.935219 CS Dly: 5 (0~36)
1404 20:15:06.935286 ==
1405 20:15:06.938388 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 20:15:06.945180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 20:15:06.945264 ==
1408 20:15:06.948478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 20:15:06.955199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 20:15:06.964343 [CA 0] Center 36 (6~67) winsize 62
1411 20:15:06.967841 [CA 1] Center 37 (6~68) winsize 63
1412 20:15:06.970993 [CA 2] Center 35 (5~66) winsize 62
1413 20:15:06.974297 [CA 3] Center 34 (4~65) winsize 62
1414 20:15:06.977719 [CA 4] Center 34 (4~65) winsize 62
1415 20:15:06.981129 [CA 5] Center 34 (4~65) winsize 62
1416 20:15:06.981215
1417 20:15:06.984331 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 20:15:06.984410
1419 20:15:06.987931 [CATrainingPosCal] consider 2 rank data
1420 20:15:06.991045 u2DelayCellTimex100 = 270/100 ps
1421 20:15:06.994367 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 20:15:06.998063 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 20:15:07.004888 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1424 20:15:07.008487 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 20:15:07.008665 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 20:15:07.012749 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 20:15:07.012940
1428 20:15:07.019916 CA PerBit enable=1, Macro0, CA PI delay=34
1429 20:15:07.020141
1430 20:15:07.020342 [CBTSetCACLKResult] CA Dly = 34
1431 20:15:07.023479 CS Dly: 6 (0~38)
1432 20:15:07.023734
1433 20:15:07.027105 ----->DramcWriteLeveling(PI) begin...
1434 20:15:07.027368 ==
1435 20:15:07.030890 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 20:15:07.035001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 20:15:07.035518 ==
1438 20:15:07.038665 Write leveling (Byte 0): 28 => 28
1439 20:15:07.039284 Write leveling (Byte 1): 29 => 29
1440 20:15:07.041790 DramcWriteLeveling(PI) end<-----
1441 20:15:07.042441
1442 20:15:07.045050 ==
1443 20:15:07.045536 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 20:15:07.052270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 20:15:07.052688 ==
1446 20:15:07.055457 [Gating] SW mode calibration
1447 20:15:07.061646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 20:15:07.065172 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 20:15:07.071656 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 20:15:07.075145 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 20:15:07.078203 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 20:15:07.085045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 20:15:07.088181 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 20:15:07.091580 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 20:15:07.094903 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 20:15:07.101521 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 20:15:07.105020 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 20:15:07.108422 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 20:15:07.115100 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 20:15:07.118233 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 20:15:07.121816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 20:15:07.128393 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 20:15:07.132119 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 20:15:07.134868 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 20:15:07.141643 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 20:15:07.144836 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1467 20:15:07.148429 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 20:15:07.154815 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 20:15:07.158443 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 20:15:07.161577 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 20:15:07.168524 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 20:15:07.171676 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 20:15:07.174868 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 20:15:07.182113 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1475 20:15:07.185158 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 20:15:07.188652 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 20:15:07.191902 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 20:15:07.198277 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 20:15:07.201771 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 20:15:07.205162 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 20:15:07.211931 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1482 20:15:07.215190 0 10 4 | B1->B0 | 2f2f 2b2b | 0 0 | (1 0) (0 0)
1483 20:15:07.218422 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 20:15:07.225383 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 20:15:07.228554 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 20:15:07.231863 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 20:15:07.239051 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 20:15:07.242107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 20:15:07.245410 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 20:15:07.248730 0 11 4 | B1->B0 | 3131 3838 | 0 1 | (0 0) (1 1)
1491 20:15:07.255292 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1492 20:15:07.258809 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 20:15:07.262050 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 20:15:07.268839 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 20:15:07.272092 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 20:15:07.275352 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 20:15:07.282459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 20:15:07.285603 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1499 20:15:07.289139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 20:15:07.295688 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 20:15:07.299021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 20:15:07.302400 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 20:15:07.308947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 20:15:07.312392 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 20:15:07.315830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 20:15:07.322724 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 20:15:07.326236 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 20:15:07.329507 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 20:15:07.332961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 20:15:07.339327 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 20:15:07.342825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 20:15:07.346105 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 20:15:07.352474 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 20:15:07.356194 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 20:15:07.359431 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 20:15:07.362538 Total UI for P1: 0, mck2ui 16
1517 20:15:07.365902 best dqsien dly found for B0: ( 0, 14, 4)
1518 20:15:07.369221 Total UI for P1: 0, mck2ui 16
1519 20:15:07.372640 best dqsien dly found for B1: ( 0, 14, 4)
1520 20:15:07.376053 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1521 20:15:07.379720 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1522 20:15:07.380185
1523 20:15:07.386058 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 20:15:07.389311 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 20:15:07.389923 [Gating] SW calibration Done
1526 20:15:07.392412 ==
1527 20:15:07.393050 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 20:15:07.399479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 20:15:07.400071 ==
1530 20:15:07.400602 RX Vref Scan: 0
1531 20:15:07.401103
1532 20:15:07.402621 RX Vref 0 -> 0, step: 1
1533 20:15:07.403401
1534 20:15:07.406012 RX Delay -130 -> 252, step: 16
1535 20:15:07.409045 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1536 20:15:07.412554 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1537 20:15:07.415841 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1538 20:15:07.422435 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1539 20:15:07.426014 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1540 20:15:07.429276 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1541 20:15:07.432763 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1542 20:15:07.435749 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1543 20:15:07.442710 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1544 20:15:07.445899 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1545 20:15:07.449189 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1546 20:15:07.452614 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1547 20:15:07.456441 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1548 20:15:07.462597 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1549 20:15:07.466352 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1550 20:15:07.469524 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1551 20:15:07.470175 ==
1552 20:15:07.472850 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 20:15:07.476174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 20:15:07.476744 ==
1555 20:15:07.479662 DQS Delay:
1556 20:15:07.480073 DQS0 = 0, DQS1 = 0
1557 20:15:07.482965 DQM Delay:
1558 20:15:07.483379 DQM0 = 87, DQM1 = 80
1559 20:15:07.483709 DQ Delay:
1560 20:15:07.486234 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1561 20:15:07.489927 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1562 20:15:07.492814 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1563 20:15:07.496417 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 20:15:07.496833
1565 20:15:07.497162
1566 20:15:07.499963 ==
1567 20:15:07.500377 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 20:15:07.506272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 20:15:07.506504 ==
1570 20:15:07.506568
1571 20:15:07.506627
1572 20:15:07.509191 TX Vref Scan disable
1573 20:15:07.509272 == TX Byte 0 ==
1574 20:15:07.512727 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 20:15:07.519425 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 20:15:07.519511 == TX Byte 1 ==
1577 20:15:07.522666 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 20:15:07.529198 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 20:15:07.529281 ==
1580 20:15:07.532610 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 20:15:07.535675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 20:15:07.535760 ==
1583 20:15:07.548758 TX Vref=22, minBit 8, minWin=27, winSum=448
1584 20:15:07.552139 TX Vref=24, minBit 15, minWin=27, winSum=455
1585 20:15:07.555468 TX Vref=26, minBit 10, minWin=27, winSum=455
1586 20:15:07.559069 TX Vref=28, minBit 15, minWin=27, winSum=456
1587 20:15:07.562234 TX Vref=30, minBit 15, minWin=27, winSum=458
1588 20:15:07.568915 TX Vref=32, minBit 15, minWin=27, winSum=458
1589 20:15:07.571807 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 30
1590 20:15:07.571889
1591 20:15:07.575706 Final TX Range 1 Vref 30
1592 20:15:07.575787
1593 20:15:07.575852 ==
1594 20:15:07.578736 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 20:15:07.582408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 20:15:07.582490 ==
1597 20:15:07.582600
1598 20:15:07.585685
1599 20:15:07.585792 TX Vref Scan disable
1600 20:15:07.589178 == TX Byte 0 ==
1601 20:15:07.592612 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 20:15:07.596133 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 20:15:07.599293 == TX Byte 1 ==
1604 20:15:07.602703 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1605 20:15:07.605739 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1606 20:15:07.609236
1607 20:15:07.609317 [DATLAT]
1608 20:15:07.609382 Freq=800, CH1 RK0
1609 20:15:07.609442
1610 20:15:07.612369 DATLAT Default: 0xa
1611 20:15:07.612452 0, 0xFFFF, sum = 0
1612 20:15:07.615749 1, 0xFFFF, sum = 0
1613 20:15:07.615831 2, 0xFFFF, sum = 0
1614 20:15:07.619332 3, 0xFFFF, sum = 0
1615 20:15:07.619416 4, 0xFFFF, sum = 0
1616 20:15:07.622612 5, 0xFFFF, sum = 0
1617 20:15:07.622695 6, 0xFFFF, sum = 0
1618 20:15:07.626027 7, 0xFFFF, sum = 0
1619 20:15:07.629009 8, 0xFFFF, sum = 0
1620 20:15:07.629092 9, 0x0, sum = 1
1621 20:15:07.629158 10, 0x0, sum = 2
1622 20:15:07.632253 11, 0x0, sum = 3
1623 20:15:07.632335 12, 0x0, sum = 4
1624 20:15:07.635733 best_step = 10
1625 20:15:07.635814
1626 20:15:07.635878 ==
1627 20:15:07.639174 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 20:15:07.642327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 20:15:07.642409 ==
1630 20:15:07.646210 RX Vref Scan: 1
1631 20:15:07.646652
1632 20:15:07.647008 Set Vref Range= 32 -> 127
1633 20:15:07.647342
1634 20:15:07.649416 RX Vref 32 -> 127, step: 1
1635 20:15:07.650011
1636 20:15:07.652803 RX Delay -95 -> 252, step: 8
1637 20:15:07.653254
1638 20:15:07.656082 Set Vref, RX VrefLevel [Byte0]: 32
1639 20:15:07.659609 [Byte1]: 32
1640 20:15:07.660068
1641 20:15:07.662920 Set Vref, RX VrefLevel [Byte0]: 33
1642 20:15:07.666058 [Byte1]: 33
1643 20:15:07.669615
1644 20:15:07.670126 Set Vref, RX VrefLevel [Byte0]: 34
1645 20:15:07.672930 [Byte1]: 34
1646 20:15:07.676983
1647 20:15:07.677463 Set Vref, RX VrefLevel [Byte0]: 35
1648 20:15:07.680440 [Byte1]: 35
1649 20:15:07.684541
1650 20:15:07.688294 Set Vref, RX VrefLevel [Byte0]: 36
1651 20:15:07.691268 [Byte1]: 36
1652 20:15:07.691510
1653 20:15:07.694498 Set Vref, RX VrefLevel [Byte0]: 37
1654 20:15:07.697989 [Byte1]: 37
1655 20:15:07.698184
1656 20:15:07.701384 Set Vref, RX VrefLevel [Byte0]: 38
1657 20:15:07.704407 [Byte1]: 38
1658 20:15:07.704545
1659 20:15:07.707703 Set Vref, RX VrefLevel [Byte0]: 39
1660 20:15:07.711391 [Byte1]: 39
1661 20:15:07.714977
1662 20:15:07.715114 Set Vref, RX VrefLevel [Byte0]: 40
1663 20:15:07.718355 [Byte1]: 40
1664 20:15:07.722598
1665 20:15:07.722734 Set Vref, RX VrefLevel [Byte0]: 41
1666 20:15:07.726105 [Byte1]: 41
1667 20:15:07.730202
1668 20:15:07.730338 Set Vref, RX VrefLevel [Byte0]: 42
1669 20:15:07.733591 [Byte1]: 42
1670 20:15:07.738244
1671 20:15:07.738507 Set Vref, RX VrefLevel [Byte0]: 43
1672 20:15:07.741230 [Byte1]: 43
1673 20:15:07.745503
1674 20:15:07.745790 Set Vref, RX VrefLevel [Byte0]: 44
1675 20:15:07.748862 [Byte1]: 44
1676 20:15:07.753230
1677 20:15:07.753607 Set Vref, RX VrefLevel [Byte0]: 45
1678 20:15:07.756303 [Byte1]: 45
1679 20:15:07.760619
1680 20:15:07.760714 Set Vref, RX VrefLevel [Byte0]: 46
1681 20:15:07.763869 [Byte1]: 46
1682 20:15:07.768177
1683 20:15:07.768364 Set Vref, RX VrefLevel [Byte0]: 47
1684 20:15:07.771366 [Byte1]: 47
1685 20:15:07.775551
1686 20:15:07.775741 Set Vref, RX VrefLevel [Byte0]: 48
1687 20:15:07.779305 [Byte1]: 48
1688 20:15:07.783553
1689 20:15:07.783717 Set Vref, RX VrefLevel [Byte0]: 49
1690 20:15:07.786800 [Byte1]: 49
1691 20:15:07.790840
1692 20:15:07.790993 Set Vref, RX VrefLevel [Byte0]: 50
1693 20:15:07.794261 [Byte1]: 50
1694 20:15:07.798496
1695 20:15:07.798778 Set Vref, RX VrefLevel [Byte0]: 51
1696 20:15:07.802000 [Byte1]: 51
1697 20:15:07.806362
1698 20:15:07.806704 Set Vref, RX VrefLevel [Byte0]: 52
1699 20:15:07.809540 [Byte1]: 52
1700 20:15:07.814210
1701 20:15:07.814689 Set Vref, RX VrefLevel [Byte0]: 53
1702 20:15:07.817136 [Byte1]: 53
1703 20:15:07.821707
1704 20:15:07.822240 Set Vref, RX VrefLevel [Byte0]: 54
1705 20:15:07.824661 [Byte1]: 54
1706 20:15:07.829026
1707 20:15:07.829529 Set Vref, RX VrefLevel [Byte0]: 55
1708 20:15:07.832599 [Byte1]: 55
1709 20:15:07.836973
1710 20:15:07.837489 Set Vref, RX VrefLevel [Byte0]: 56
1711 20:15:07.840313 [Byte1]: 56
1712 20:15:07.844551
1713 20:15:07.844968 Set Vref, RX VrefLevel [Byte0]: 57
1714 20:15:07.847658 [Byte1]: 57
1715 20:15:07.851845
1716 20:15:07.852261 Set Vref, RX VrefLevel [Byte0]: 58
1717 20:15:07.855297 [Byte1]: 58
1718 20:15:07.859705
1719 20:15:07.860233 Set Vref, RX VrefLevel [Byte0]: 59
1720 20:15:07.862915 [Byte1]: 59
1721 20:15:07.867411
1722 20:15:07.867931 Set Vref, RX VrefLevel [Byte0]: 60
1723 20:15:07.870433 [Byte1]: 60
1724 20:15:07.874704
1725 20:15:07.875423 Set Vref, RX VrefLevel [Byte0]: 61
1726 20:15:07.878028 [Byte1]: 61
1727 20:15:07.882094
1728 20:15:07.882512 Set Vref, RX VrefLevel [Byte0]: 62
1729 20:15:07.885505 [Byte1]: 62
1730 20:15:07.889937
1731 20:15:07.890378 Set Vref, RX VrefLevel [Byte0]: 63
1732 20:15:07.893407 [Byte1]: 63
1733 20:15:07.897476
1734 20:15:07.898006 Set Vref, RX VrefLevel [Byte0]: 64
1735 20:15:07.900821 [Byte1]: 64
1736 20:15:07.905222
1737 20:15:07.905745 Set Vref, RX VrefLevel [Byte0]: 65
1738 20:15:07.908745 [Byte1]: 65
1739 20:15:07.913164
1740 20:15:07.913726 Set Vref, RX VrefLevel [Byte0]: 66
1741 20:15:07.919546 [Byte1]: 66
1742 20:15:07.920119
1743 20:15:07.922737 Set Vref, RX VrefLevel [Byte0]: 67
1744 20:15:07.926332 [Byte1]: 67
1745 20:15:07.926885
1746 20:15:07.929231 Set Vref, RX VrefLevel [Byte0]: 68
1747 20:15:07.932263 [Byte1]: 68
1748 20:15:07.932736
1749 20:15:07.936192 Set Vref, RX VrefLevel [Byte0]: 69
1750 20:15:07.939051 [Byte1]: 69
1751 20:15:07.943069
1752 20:15:07.943531 Set Vref, RX VrefLevel [Byte0]: 70
1753 20:15:07.946504 [Byte1]: 70
1754 20:15:07.950735
1755 20:15:07.951196 Set Vref, RX VrefLevel [Byte0]: 71
1756 20:15:07.953978 [Byte1]: 71
1757 20:15:07.958185
1758 20:15:07.958890 Set Vref, RX VrefLevel [Byte0]: 72
1759 20:15:07.961829 [Byte1]: 72
1760 20:15:07.966066
1761 20:15:07.966799 Set Vref, RX VrefLevel [Byte0]: 73
1762 20:15:07.969305 [Byte1]: 73
1763 20:15:07.973480
1764 20:15:07.974197 Set Vref, RX VrefLevel [Byte0]: 74
1765 20:15:07.976825 [Byte1]: 74
1766 20:15:07.980983
1767 20:15:07.981627 Set Vref, RX VrefLevel [Byte0]: 75
1768 20:15:07.984460 [Byte1]: 75
1769 20:15:07.988710
1770 20:15:07.989281 Set Vref, RX VrefLevel [Byte0]: 76
1771 20:15:07.992080 [Byte1]: 76
1772 20:15:07.996211
1773 20:15:07.996791 Set Vref, RX VrefLevel [Byte0]: 77
1774 20:15:07.999513 [Byte1]: 77
1775 20:15:08.003692
1776 20:15:08.004250 Set Vref, RX VrefLevel [Byte0]: 78
1777 20:15:08.007158 [Byte1]: 78
1778 20:15:08.011227
1779 20:15:08.011312 Final RX Vref Byte 0 = 54 to rank0
1780 20:15:08.014725 Final RX Vref Byte 1 = 59 to rank0
1781 20:15:08.018037 Final RX Vref Byte 0 = 54 to rank1
1782 20:15:08.021254 Final RX Vref Byte 1 = 59 to rank1==
1783 20:15:08.025008 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 20:15:08.028181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 20:15:08.031352 ==
1786 20:15:08.031440 DQS Delay:
1787 20:15:08.031510 DQS0 = 0, DQS1 = 0
1788 20:15:08.034854 DQM Delay:
1789 20:15:08.034948 DQM0 = 92, DQM1 = 81
1790 20:15:08.037833 DQ Delay:
1791 20:15:08.037962 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1792 20:15:08.041562 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =84
1793 20:15:08.044659 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1794 20:15:08.051064 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1795 20:15:08.051211
1796 20:15:08.051344
1797 20:15:08.057891 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1798 20:15:08.061166 CH1 RK0: MR19=606, MR18=314E
1799 20:15:08.068033 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1800 20:15:08.068243
1801 20:15:08.071284 ----->DramcWriteLeveling(PI) begin...
1802 20:15:08.071462 ==
1803 20:15:08.074909 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 20:15:08.078060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 20:15:08.078323 ==
1806 20:15:08.081540 Write leveling (Byte 0): 25 => 25
1807 20:15:08.084929 Write leveling (Byte 1): 30 => 30
1808 20:15:08.088090 DramcWriteLeveling(PI) end<-----
1809 20:15:08.088450
1810 20:15:08.088866 ==
1811 20:15:08.091427 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 20:15:08.094908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 20:15:08.095345 ==
1814 20:15:08.097991 [Gating] SW mode calibration
1815 20:15:08.104996 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 20:15:08.111251 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 20:15:08.114163 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 20:15:08.117693 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1819 20:15:08.124423 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 20:15:08.127722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 20:15:08.131489 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 20:15:08.137920 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 20:15:08.141193 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 20:15:08.144482 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 20:15:08.151227 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 20:15:08.154312 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 20:15:08.158008 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 20:15:08.164615 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 20:15:08.168016 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 20:15:08.171145 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 20:15:08.178342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 20:15:08.180972 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 20:15:08.184290 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 20:15:08.187810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1835 20:15:08.194436 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 20:15:08.197703 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 20:15:08.201128 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 20:15:08.208205 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 20:15:08.211519 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 20:15:08.214809 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 20:15:08.221626 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 20:15:08.224504 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 20:15:08.228019 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1844 20:15:08.234518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 20:15:08.238298 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 20:15:08.241370 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 20:15:08.248093 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 20:15:08.251213 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 20:15:08.254583 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
1850 20:15:08.258211 0 10 4 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (1 0)
1851 20:15:08.264909 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 20:15:08.268464 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 20:15:08.271113 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 20:15:08.278281 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 20:15:08.281438 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 20:15:08.284972 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 20:15:08.291262 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 20:15:08.294538 0 11 4 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
1859 20:15:08.297909 0 11 8 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
1860 20:15:08.304674 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 20:15:08.308109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 20:15:08.311796 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 20:15:08.318234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 20:15:08.321294 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 20:15:08.324790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 20:15:08.331645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1867 20:15:08.334911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1868 20:15:08.338723 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 20:15:08.345248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 20:15:08.348661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 20:15:08.352006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 20:15:08.355284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 20:15:08.362056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 20:15:08.365530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 20:15:08.368624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 20:15:08.375451 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 20:15:08.378754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 20:15:08.382011 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 20:15:08.388646 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 20:15:08.392416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 20:15:08.395736 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1882 20:15:08.402061 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 20:15:08.402647 Total UI for P1: 0, mck2ui 16
1884 20:15:08.405894 best dqsien dly found for B0: ( 0, 14, 2)
1885 20:15:08.408913 Total UI for P1: 0, mck2ui 16
1886 20:15:08.412347 best dqsien dly found for B1: ( 0, 14, 0)
1887 20:15:08.415539 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1888 20:15:08.422207 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1889 20:15:08.422630
1890 20:15:08.425596 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1891 20:15:08.428882 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1892 20:15:08.432312 [Gating] SW calibration Done
1893 20:15:08.432734 ==
1894 20:15:08.435718 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 20:15:08.438936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 20:15:08.439424 ==
1897 20:15:08.439772 RX Vref Scan: 0
1898 20:15:08.440091
1899 20:15:08.442325 RX Vref 0 -> 0, step: 1
1900 20:15:08.442749
1901 20:15:08.445572 RX Delay -130 -> 252, step: 16
1902 20:15:08.448753 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1903 20:15:08.452343 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1904 20:15:08.459008 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1905 20:15:08.462062 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1906 20:15:08.466041 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1907 20:15:08.469126 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1908 20:15:08.472255 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1909 20:15:08.478861 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1910 20:15:08.482171 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1911 20:15:08.485307 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1912 20:15:08.488693 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1913 20:15:08.492414 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1914 20:15:08.498861 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1915 20:15:08.502180 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1916 20:15:08.505355 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1917 20:15:08.508836 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1918 20:15:08.509261 ==
1919 20:15:08.512354 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 20:15:08.515630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 20:15:08.519086 ==
1922 20:15:08.519591 DQS Delay:
1923 20:15:08.520106 DQS0 = 0, DQS1 = 0
1924 20:15:08.522160 DQM Delay:
1925 20:15:08.522663 DQM0 = 89, DQM1 = 84
1926 20:15:08.525689 DQ Delay:
1927 20:15:08.526197 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1928 20:15:08.529012 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1929 20:15:08.532431 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1930 20:15:08.535746 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1931 20:15:08.536166
1932 20:15:08.539308
1933 20:15:08.539775 ==
1934 20:15:08.542200 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 20:15:08.545865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 20:15:08.546367 ==
1937 20:15:08.546782
1938 20:15:08.547127
1939 20:15:08.548769 TX Vref Scan disable
1940 20:15:08.549187 == TX Byte 0 ==
1941 20:15:08.555593 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1942 20:15:08.558799 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1943 20:15:08.559262 == TX Byte 1 ==
1944 20:15:08.565831 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1945 20:15:08.568757 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1946 20:15:08.569226 ==
1947 20:15:08.572532 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 20:15:08.575411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 20:15:08.575986 ==
1950 20:15:08.589204 TX Vref=22, minBit 12, minWin=27, winSum=451
1951 20:15:08.592920 TX Vref=24, minBit 15, minWin=27, winSum=455
1952 20:15:08.596004 TX Vref=26, minBit 13, minWin=27, winSum=454
1953 20:15:08.599666 TX Vref=28, minBit 13, minWin=27, winSum=455
1954 20:15:08.602989 TX Vref=30, minBit 8, minWin=28, winSum=459
1955 20:15:08.609303 TX Vref=32, minBit 8, minWin=28, winSum=459
1956 20:15:08.612667 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1957 20:15:08.613245
1958 20:15:08.615911 Final TX Range 1 Vref 30
1959 20:15:08.616579
1960 20:15:08.617161 ==
1961 20:15:08.619476 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 20:15:08.622530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 20:15:08.625760 ==
1964 20:15:08.625867
1965 20:15:08.626000
1966 20:15:08.626066 TX Vref Scan disable
1967 20:15:08.629481 == TX Byte 0 ==
1968 20:15:08.632808 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1969 20:15:08.636212 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1970 20:15:08.639586 == TX Byte 1 ==
1971 20:15:08.642830 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1972 20:15:08.646183 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1973 20:15:08.649648
1974 20:15:08.649771 [DATLAT]
1975 20:15:08.649878 Freq=800, CH1 RK1
1976 20:15:08.649980
1977 20:15:08.653113 DATLAT Default: 0xa
1978 20:15:08.653206 0, 0xFFFF, sum = 0
1979 20:15:08.656198 1, 0xFFFF, sum = 0
1980 20:15:08.656301 2, 0xFFFF, sum = 0
1981 20:15:08.659199 3, 0xFFFF, sum = 0
1982 20:15:08.659321 4, 0xFFFF, sum = 0
1983 20:15:08.662820 5, 0xFFFF, sum = 0
1984 20:15:08.662933 6, 0xFFFF, sum = 0
1985 20:15:08.666226 7, 0xFFFF, sum = 0
1986 20:15:08.669406 8, 0xFFFF, sum = 0
1987 20:15:08.669544 9, 0x0, sum = 1
1988 20:15:08.669654 10, 0x0, sum = 2
1989 20:15:08.673295 11, 0x0, sum = 3
1990 20:15:08.673549 12, 0x0, sum = 4
1991 20:15:08.676578 best_step = 10
1992 20:15:08.676774
1993 20:15:08.676909 ==
1994 20:15:08.679372 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 20:15:08.682941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 20:15:08.683153 ==
1997 20:15:08.686674 RX Vref Scan: 0
1998 20:15:08.686911
1999 20:15:08.687075 RX Vref 0 -> 0, step: 1
2000 20:15:08.687257
2001 20:15:08.689804 RX Delay -79 -> 252, step: 8
2002 20:15:08.696210 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2003 20:15:08.699416 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2004 20:15:08.702948 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2005 20:15:08.706353 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2006 20:15:08.709561 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2007 20:15:08.716263 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2008 20:15:08.719474 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
2009 20:15:08.722956 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2010 20:15:08.726267 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2011 20:15:08.729455 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2012 20:15:08.732802 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2013 20:15:08.739536 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2014 20:15:08.742698 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2015 20:15:08.746240 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2016 20:15:08.749768 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2017 20:15:08.756178 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2018 20:15:08.756255 ==
2019 20:15:08.759790 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 20:15:08.762953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 20:15:08.763026 ==
2022 20:15:08.763088 DQS Delay:
2023 20:15:08.765925 DQS0 = 0, DQS1 = 0
2024 20:15:08.766041 DQM Delay:
2025 20:15:08.769745 DQM0 = 92, DQM1 = 83
2026 20:15:08.769813 DQ Delay:
2027 20:15:08.772841 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2028 20:15:08.776341 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
2029 20:15:08.779460 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2030 20:15:08.783174 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2031 20:15:08.783248
2032 20:15:08.783309
2033 20:15:08.789328 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2034 20:15:08.792740 CH1 RK1: MR19=606, MR18=350A
2035 20:15:08.799720 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2036 20:15:08.802867 [RxdqsGatingPostProcess] freq 800
2037 20:15:08.809371 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 20:15:08.809471 Pre-setting of DQS Precalculation
2039 20:15:08.816332 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 20:15:08.823128 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 20:15:08.829703 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 20:15:08.829904
2043 20:15:08.830078
2044 20:15:08.832868 [Calibration Summary] 1600 Mbps
2045 20:15:08.836310 CH 0, Rank 0
2046 20:15:08.836465 SW Impedance : PASS
2047 20:15:08.839838 DUTY Scan : NO K
2048 20:15:08.843240 ZQ Calibration : PASS
2049 20:15:08.843453 Jitter Meter : NO K
2050 20:15:08.846335 CBT Training : PASS
2051 20:15:08.846547 Write leveling : PASS
2052 20:15:08.849716 RX DQS gating : PASS
2053 20:15:08.853119 RX DQ/DQS(RDDQC) : PASS
2054 20:15:08.853383 TX DQ/DQS : PASS
2055 20:15:08.856635 RX DATLAT : PASS
2056 20:15:08.859742 RX DQ/DQS(Engine): PASS
2057 20:15:08.860217 TX OE : NO K
2058 20:15:08.863384 All Pass.
2059 20:15:08.863960
2060 20:15:08.864483 CH 0, Rank 1
2061 20:15:08.866795 SW Impedance : PASS
2062 20:15:08.867263 DUTY Scan : NO K
2063 20:15:08.869865 ZQ Calibration : PASS
2064 20:15:08.873331 Jitter Meter : NO K
2065 20:15:08.873848 CBT Training : PASS
2066 20:15:08.876760 Write leveling : PASS
2067 20:15:08.880337 RX DQS gating : PASS
2068 20:15:08.880919 RX DQ/DQS(RDDQC) : PASS
2069 20:15:08.883400 TX DQ/DQS : PASS
2070 20:15:08.883990 RX DATLAT : PASS
2071 20:15:08.886746 RX DQ/DQS(Engine): PASS
2072 20:15:08.890002 TX OE : NO K
2073 20:15:08.890454 All Pass.
2074 20:15:08.890820
2075 20:15:08.891177 CH 1, Rank 0
2076 20:15:08.893605 SW Impedance : PASS
2077 20:15:08.896826 DUTY Scan : NO K
2078 20:15:08.897301 ZQ Calibration : PASS
2079 20:15:08.900451 Jitter Meter : NO K
2080 20:15:08.903694 CBT Training : PASS
2081 20:15:08.904170 Write leveling : PASS
2082 20:15:08.906728 RX DQS gating : PASS
2083 20:15:08.910128 RX DQ/DQS(RDDQC) : PASS
2084 20:15:08.910620 TX DQ/DQS : PASS
2085 20:15:08.913249 RX DATLAT : PASS
2086 20:15:08.916333 RX DQ/DQS(Engine): PASS
2087 20:15:08.916775 TX OE : NO K
2088 20:15:08.919991 All Pass.
2089 20:15:08.920453
2090 20:15:08.920824 CH 1, Rank 1
2091 20:15:08.922932 SW Impedance : PASS
2092 20:15:08.923398 DUTY Scan : NO K
2093 20:15:08.926594 ZQ Calibration : PASS
2094 20:15:08.930051 Jitter Meter : NO K
2095 20:15:08.930489 CBT Training : PASS
2096 20:15:08.933515 Write leveling : PASS
2097 20:15:08.934091 RX DQS gating : PASS
2098 20:15:08.936826 RX DQ/DQS(RDDQC) : PASS
2099 20:15:08.939921 TX DQ/DQS : PASS
2100 20:15:08.940336 RX DATLAT : PASS
2101 20:15:08.943145 RX DQ/DQS(Engine): PASS
2102 20:15:08.946488 TX OE : NO K
2103 20:15:08.946909 All Pass.
2104 20:15:08.947242
2105 20:15:08.949698 DramC Write-DBI off
2106 20:15:08.950157 PER_BANK_REFRESH: Hybrid Mode
2107 20:15:08.953564 TX_TRACKING: ON
2108 20:15:08.956798 [GetDramInforAfterCalByMRR] Vendor 6.
2109 20:15:08.960277 [GetDramInforAfterCalByMRR] Revision 606.
2110 20:15:08.963763 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 20:15:08.964193 MR0 0x3b3b
2112 20:15:08.966850 MR8 0x5151
2113 20:15:08.969857 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 20:15:08.970338
2115 20:15:08.970816 MR0 0x3b3b
2116 20:15:08.973167 MR8 0x5151
2117 20:15:08.976886 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 20:15:08.977318
2119 20:15:08.983309 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 20:15:08.986750 [FAST_K] Save calibration result to emmc
2121 20:15:08.990241 [FAST_K] Save calibration result to emmc
2122 20:15:08.993505 dram_init: config_dvfs: 1
2123 20:15:08.996878 dramc_set_vcore_voltage set vcore to 662500
2124 20:15:08.999869 Read voltage for 1200, 2
2125 20:15:09.000440 Vio18 = 0
2126 20:15:09.003426 Vcore = 662500
2127 20:15:09.003896 Vdram = 0
2128 20:15:09.004399 Vddq = 0
2129 20:15:09.006833 Vmddr = 0
2130 20:15:09.009752 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 20:15:09.016697 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 20:15:09.017230 MEM_TYPE=3, freq_sel=15
2133 20:15:09.019867 sv_algorithm_assistance_LP4_1600
2134 20:15:09.023070 ============ PULL DRAM RESETB DOWN ============
2135 20:15:09.030073 ========== PULL DRAM RESETB DOWN end =========
2136 20:15:09.033109 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 20:15:09.036564 ===================================
2138 20:15:09.040131 LPDDR4 DRAM CONFIGURATION
2139 20:15:09.043233 ===================================
2140 20:15:09.043668 EX_ROW_EN[0] = 0x0
2141 20:15:09.046705 EX_ROW_EN[1] = 0x0
2142 20:15:09.047144 LP4Y_EN = 0x0
2143 20:15:09.050035 WORK_FSP = 0x0
2144 20:15:09.050456 WL = 0x4
2145 20:15:09.053406 RL = 0x4
2146 20:15:09.056684 BL = 0x2
2147 20:15:09.057294 RPST = 0x0
2148 20:15:09.060292 RD_PRE = 0x0
2149 20:15:09.060857 WR_PRE = 0x1
2150 20:15:09.063410 WR_PST = 0x0
2151 20:15:09.063831 DBI_WR = 0x0
2152 20:15:09.066926 DBI_RD = 0x0
2153 20:15:09.067348 OTF = 0x1
2154 20:15:09.069832 ===================================
2155 20:15:09.073596 ===================================
2156 20:15:09.074068 ANA top config
2157 20:15:09.076869 ===================================
2158 20:15:09.080096 DLL_ASYNC_EN = 0
2159 20:15:09.083275 ALL_SLAVE_EN = 0
2160 20:15:09.086536 NEW_RANK_MODE = 1
2161 20:15:09.090034 DLL_IDLE_MODE = 1
2162 20:15:09.090464 LP45_APHY_COMB_EN = 1
2163 20:15:09.093216 TX_ODT_DIS = 1
2164 20:15:09.096748 NEW_8X_MODE = 1
2165 20:15:09.099879 ===================================
2166 20:15:09.103558 ===================================
2167 20:15:09.106631 data_rate = 2400
2168 20:15:09.109778 CKR = 1
2169 20:15:09.110217 DQ_P2S_RATIO = 8
2170 20:15:09.113234 ===================================
2171 20:15:09.116776 CA_P2S_RATIO = 8
2172 20:15:09.120277 DQ_CA_OPEN = 0
2173 20:15:09.123344 DQ_SEMI_OPEN = 0
2174 20:15:09.126699 CA_SEMI_OPEN = 0
2175 20:15:09.129695 CA_FULL_RATE = 0
2176 20:15:09.130160 DQ_CKDIV4_EN = 0
2177 20:15:09.133425 CA_CKDIV4_EN = 0
2178 20:15:09.136963 CA_PREDIV_EN = 0
2179 20:15:09.140034 PH8_DLY = 17
2180 20:15:09.143247 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 20:15:09.146687 DQ_AAMCK_DIV = 4
2182 20:15:09.147121 CA_AAMCK_DIV = 4
2183 20:15:09.149884 CA_ADMCK_DIV = 4
2184 20:15:09.153522 DQ_TRACK_CA_EN = 0
2185 20:15:09.156436 CA_PICK = 1200
2186 20:15:09.160133 CA_MCKIO = 1200
2187 20:15:09.163859 MCKIO_SEMI = 0
2188 20:15:09.167100 PLL_FREQ = 2366
2189 20:15:09.167632 DQ_UI_PI_RATIO = 32
2190 20:15:09.170091 CA_UI_PI_RATIO = 0
2191 20:15:09.173431 ===================================
2192 20:15:09.176539 ===================================
2193 20:15:09.180126 memory_type:LPDDR4
2194 20:15:09.183409 GP_NUM : 10
2195 20:15:09.183926 SRAM_EN : 1
2196 20:15:09.186611 MD32_EN : 0
2197 20:15:09.190061 ===================================
2198 20:15:09.190481 [ANA_INIT] >>>>>>>>>>>>>>
2199 20:15:09.194013 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 20:15:09.197331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 20:15:09.200380 ===================================
2202 20:15:09.203433 data_rate = 2400,PCW = 0X5b00
2203 20:15:09.207098 ===================================
2204 20:15:09.209861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 20:15:09.216628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 20:15:09.219920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 20:15:09.227010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 20:15:09.230404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 20:15:09.233935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 20:15:09.237080 [ANA_INIT] flow start
2211 20:15:09.237576 [ANA_INIT] PLL >>>>>>>>
2212 20:15:09.240391 [ANA_INIT] PLL <<<<<<<<
2213 20:15:09.243373 [ANA_INIT] MIDPI >>>>>>>>
2214 20:15:09.243924 [ANA_INIT] MIDPI <<<<<<<<
2215 20:15:09.246646 [ANA_INIT] DLL >>>>>>>>
2216 20:15:09.250037 [ANA_INIT] DLL <<<<<<<<
2217 20:15:09.250451 [ANA_INIT] flow end
2218 20:15:09.253445 ============ LP4 DIFF to SE enter ============
2219 20:15:09.260423 ============ LP4 DIFF to SE exit ============
2220 20:15:09.260841 [ANA_INIT] <<<<<<<<<<<<<
2221 20:15:09.263540 [Flow] Enable top DCM control >>>>>
2222 20:15:09.266814 [Flow] Enable top DCM control <<<<<
2223 20:15:09.270081 Enable DLL master slave shuffle
2224 20:15:09.276859 ==============================================================
2225 20:15:09.277274 Gating Mode config
2226 20:15:09.283354 ==============================================================
2227 20:15:09.286947 Config description:
2228 20:15:09.296432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 20:15:09.303598 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 20:15:09.306760 SELPH_MODE 0: By rank 1: By Phase
2231 20:15:09.313543 ==============================================================
2232 20:15:09.316720 GAT_TRACK_EN = 1
2233 20:15:09.317177 RX_GATING_MODE = 2
2234 20:15:09.320258 RX_GATING_TRACK_MODE = 2
2235 20:15:09.323312 SELPH_MODE = 1
2236 20:15:09.326812 PICG_EARLY_EN = 1
2237 20:15:09.330530 VALID_LAT_VALUE = 1
2238 20:15:09.336905 ==============================================================
2239 20:15:09.340011 Enter into Gating configuration >>>>
2240 20:15:09.343731 Exit from Gating configuration <<<<
2241 20:15:09.346813 Enter into DVFS_PRE_config >>>>>
2242 20:15:09.356904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 20:15:09.360399 Exit from DVFS_PRE_config <<<<<
2244 20:15:09.363682 Enter into PICG configuration >>>>
2245 20:15:09.367085 Exit from PICG configuration <<<<
2246 20:15:09.370282 [RX_INPUT] configuration >>>>>
2247 20:15:09.370744 [RX_INPUT] configuration <<<<<
2248 20:15:09.377280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 20:15:09.383799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 20:15:09.387073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 20:15:09.393748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 20:15:09.400755 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 20:15:09.406922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 20:15:09.410651 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 20:15:09.413889 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 20:15:09.420564 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 20:15:09.423722 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 20:15:09.426769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 20:15:09.433270 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 20:15:09.436736 ===================================
2261 20:15:09.437150 LPDDR4 DRAM CONFIGURATION
2262 20:15:09.440050 ===================================
2263 20:15:09.443459 EX_ROW_EN[0] = 0x0
2264 20:15:09.443871 EX_ROW_EN[1] = 0x0
2265 20:15:09.447266 LP4Y_EN = 0x0
2266 20:15:09.447744 WORK_FSP = 0x0
2267 20:15:09.450182 WL = 0x4
2268 20:15:09.450655 RL = 0x4
2269 20:15:09.453585 BL = 0x2
2270 20:15:09.454036 RPST = 0x0
2271 20:15:09.456847 RD_PRE = 0x0
2272 20:15:09.457268 WR_PRE = 0x1
2273 20:15:09.460239 WR_PST = 0x0
2274 20:15:09.463477 DBI_WR = 0x0
2275 20:15:09.463979 DBI_RD = 0x0
2276 20:15:09.466928 OTF = 0x1
2277 20:15:09.470171 ===================================
2278 20:15:09.473641 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 20:15:09.476732 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 20:15:09.480099 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 20:15:09.483572 ===================================
2282 20:15:09.486714 LPDDR4 DRAM CONFIGURATION
2283 20:15:09.490269 ===================================
2284 20:15:09.493395 EX_ROW_EN[0] = 0x10
2285 20:15:09.493823 EX_ROW_EN[1] = 0x0
2286 20:15:09.496914 LP4Y_EN = 0x0
2287 20:15:09.497336 WORK_FSP = 0x0
2288 20:15:09.500051 WL = 0x4
2289 20:15:09.500475 RL = 0x4
2290 20:15:09.503582 BL = 0x2
2291 20:15:09.504005 RPST = 0x0
2292 20:15:09.507133 RD_PRE = 0x0
2293 20:15:09.507542 WR_PRE = 0x1
2294 20:15:09.510513 WR_PST = 0x0
2295 20:15:09.510924 DBI_WR = 0x0
2296 20:15:09.513392 DBI_RD = 0x0
2297 20:15:09.513801 OTF = 0x1
2298 20:15:09.516797 ===================================
2299 20:15:09.523674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 20:15:09.524087 ==
2301 20:15:09.526899 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 20:15:09.533913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 20:15:09.534441 ==
2304 20:15:09.534941 [Duty_Offset_Calibration]
2305 20:15:09.537193 B0:2 B1:0 CA:1
2306 20:15:09.537603
2307 20:15:09.540450 [DutyScan_Calibration_Flow] k_type=0
2308 20:15:09.548591
2309 20:15:09.549165 ==CLK 0==
2310 20:15:09.551733 Final CLK duty delay cell = -4
2311 20:15:09.554912 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2312 20:15:09.558613 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2313 20:15:09.561547 [-4] AVG Duty = 4953%(X100)
2314 20:15:09.562123
2315 20:15:09.565042 CH0 CLK Duty spec in!! Max-Min= 156%
2316 20:15:09.568286 [DutyScan_Calibration_Flow] ====Done====
2317 20:15:09.568701
2318 20:15:09.571694 [DutyScan_Calibration_Flow] k_type=1
2319 20:15:09.587149
2320 20:15:09.587566 ==DQS 0 ==
2321 20:15:09.590409 Final DQS duty delay cell = 0
2322 20:15:09.594029 [0] MAX Duty = 5187%(X100), DQS PI = 32
2323 20:15:09.597084 [0] MIN Duty = 4938%(X100), DQS PI = 0
2324 20:15:09.597462 [0] AVG Duty = 5062%(X100)
2325 20:15:09.600331
2326 20:15:09.600739 ==DQS 1 ==
2327 20:15:09.603645 Final DQS duty delay cell = -4
2328 20:15:09.607279 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2329 20:15:09.610731 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2330 20:15:09.614085 [-4] AVG Duty = 5015%(X100)
2331 20:15:09.614517
2332 20:15:09.617081 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2333 20:15:09.617500
2334 20:15:09.620514 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2335 20:15:09.623756 [DutyScan_Calibration_Flow] ====Done====
2336 20:15:09.624172
2337 20:15:09.627163 [DutyScan_Calibration_Flow] k_type=3
2338 20:15:09.643857
2339 20:15:09.644295 ==DQM 0 ==
2340 20:15:09.647451 Final DQM duty delay cell = 0
2341 20:15:09.651118 [0] MAX Duty = 5062%(X100), DQS PI = 24
2342 20:15:09.653812 [0] MIN Duty = 4813%(X100), DQS PI = 2
2343 20:15:09.654329 [0] AVG Duty = 4937%(X100)
2344 20:15:09.657257
2345 20:15:09.657885 ==DQM 1 ==
2346 20:15:09.660689 Final DQM duty delay cell = 0
2347 20:15:09.663944 [0] MAX Duty = 5187%(X100), DQS PI = 46
2348 20:15:09.667452 [0] MIN Duty = 5000%(X100), DQS PI = 22
2349 20:15:09.667920 [0] AVG Duty = 5093%(X100)
2350 20:15:09.670752
2351 20:15:09.673801 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2352 20:15:09.674311
2353 20:15:09.677156 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2354 20:15:09.680573 [DutyScan_Calibration_Flow] ====Done====
2355 20:15:09.681183
2356 20:15:09.683840 [DutyScan_Calibration_Flow] k_type=2
2357 20:15:09.700512
2358 20:15:09.700964 ==DQ 0 ==
2359 20:15:09.703903 Final DQ duty delay cell = -4
2360 20:15:09.707149 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2361 20:15:09.710578 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2362 20:15:09.713542 [-4] AVG Duty = 4968%(X100)
2363 20:15:09.714134
2364 20:15:09.714693 ==DQ 1 ==
2365 20:15:09.716984 Final DQ duty delay cell = 4
2366 20:15:09.720681 [4] MAX Duty = 5093%(X100), DQS PI = 6
2367 20:15:09.723999 [4] MIN Duty = 5031%(X100), DQS PI = 0
2368 20:15:09.724568 [4] AVG Duty = 5062%(X100)
2369 20:15:09.725106
2370 20:15:09.726963 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2371 20:15:09.730544
2372 20:15:09.733399 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2373 20:15:09.737383 [DutyScan_Calibration_Flow] ====Done====
2374 20:15:09.737831 ==
2375 20:15:09.740661 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 20:15:09.743638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 20:15:09.744067 ==
2378 20:15:09.747210 [Duty_Offset_Calibration]
2379 20:15:09.747662 B0:0 B1:-1 CA:2
2380 20:15:09.748049
2381 20:15:09.750604 [DutyScan_Calibration_Flow] k_type=0
2382 20:15:09.760926
2383 20:15:09.761375 ==CLK 0==
2384 20:15:09.763979 Final CLK duty delay cell = 0
2385 20:15:09.767260 [0] MAX Duty = 5156%(X100), DQS PI = 16
2386 20:15:09.770466 [0] MIN Duty = 4938%(X100), DQS PI = 44
2387 20:15:09.770928 [0] AVG Duty = 5047%(X100)
2388 20:15:09.773931
2389 20:15:09.777088 CH1 CLK Duty spec in!! Max-Min= 218%
2390 20:15:09.780495 [DutyScan_Calibration_Flow] ====Done====
2391 20:15:09.781027
2392 20:15:09.783631 [DutyScan_Calibration_Flow] k_type=1
2393 20:15:09.800558
2394 20:15:09.801085 ==DQS 0 ==
2395 20:15:09.803374 Final DQS duty delay cell = 0
2396 20:15:09.807021 [0] MAX Duty = 5093%(X100), DQS PI = 22
2397 20:15:09.810263 [0] MIN Duty = 4969%(X100), DQS PI = 0
2398 20:15:09.810684 [0] AVG Duty = 5031%(X100)
2399 20:15:09.813870
2400 20:15:09.814341 ==DQS 1 ==
2401 20:15:09.817021 Final DQS duty delay cell = 0
2402 20:15:09.820185 [0] MAX Duty = 5156%(X100), DQS PI = 0
2403 20:15:09.823306 [0] MIN Duty = 4813%(X100), DQS PI = 36
2404 20:15:09.823774 [0] AVG Duty = 4984%(X100)
2405 20:15:09.824141
2406 20:15:09.830361 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2407 20:15:09.830797
2408 20:15:09.833513 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2409 20:15:09.836913 [DutyScan_Calibration_Flow] ====Done====
2410 20:15:09.837338
2411 20:15:09.840288 [DutyScan_Calibration_Flow] k_type=3
2412 20:15:09.857689
2413 20:15:09.858130 ==DQM 0 ==
2414 20:15:09.860674 Final DQM duty delay cell = 4
2415 20:15:09.863832 [4] MAX Duty = 5093%(X100), DQS PI = 6
2416 20:15:09.867056 [4] MIN Duty = 4969%(X100), DQS PI = 28
2417 20:15:09.867527 [4] AVG Duty = 5031%(X100)
2418 20:15:09.870591
2419 20:15:09.871143 ==DQM 1 ==
2420 20:15:09.873911 Final DQM duty delay cell = 0
2421 20:15:09.877635 [0] MAX Duty = 5280%(X100), DQS PI = 62
2422 20:15:09.880819 [0] MIN Duty = 4875%(X100), DQS PI = 36
2423 20:15:09.881412 [0] AVG Duty = 5077%(X100)
2424 20:15:09.881810
2425 20:15:09.887280 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2426 20:15:09.887747
2427 20:15:09.890726 CH1 DQM 1 Duty spec in!! Max-Min= 405%
2428 20:15:09.893968 [DutyScan_Calibration_Flow] ====Done====
2429 20:15:09.894617
2430 20:15:09.897067 [DutyScan_Calibration_Flow] k_type=2
2431 20:15:09.913899
2432 20:15:09.914349 ==DQ 0 ==
2433 20:15:09.917247 Final DQ duty delay cell = 0
2434 20:15:09.920369 [0] MAX Duty = 5062%(X100), DQS PI = 20
2435 20:15:09.923840 [0] MIN Duty = 4938%(X100), DQS PI = 30
2436 20:15:09.924306 [0] AVG Duty = 5000%(X100)
2437 20:15:09.927029
2438 20:15:09.927493 ==DQ 1 ==
2439 20:15:09.930136 Final DQ duty delay cell = 0
2440 20:15:09.933711 [0] MAX Duty = 5031%(X100), DQS PI = 0
2441 20:15:09.936805 [0] MIN Duty = 4813%(X100), DQS PI = 34
2442 20:15:09.937414 [0] AVG Duty = 4922%(X100)
2443 20:15:09.938034
2444 20:15:09.940363 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2445 20:15:09.943341
2446 20:15:09.946907 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2447 20:15:09.950452 [DutyScan_Calibration_Flow] ====Done====
2448 20:15:09.953617 nWR fixed to 30
2449 20:15:09.954141 [ModeRegInit_LP4] CH0 RK0
2450 20:15:09.956869 [ModeRegInit_LP4] CH0 RK1
2451 20:15:09.960477 [ModeRegInit_LP4] CH1 RK0
2452 20:15:09.960937 [ModeRegInit_LP4] CH1 RK1
2453 20:15:09.963581 match AC timing 7
2454 20:15:09.966783 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 20:15:09.970058 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 20:15:09.977088 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 20:15:09.980340 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 20:15:09.987078 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 20:15:09.987522 ==
2460 20:15:09.990239 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 20:15:09.993770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 20:15:09.994296 ==
2463 20:15:10.000361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 20:15:10.003802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2465 20:15:10.013810 [CA 0] Center 38 (8~69) winsize 62
2466 20:15:10.017047 [CA 1] Center 38 (7~69) winsize 63
2467 20:15:10.020417 [CA 2] Center 35 (5~66) winsize 62
2468 20:15:10.023409 [CA 3] Center 35 (5~66) winsize 62
2469 20:15:10.026918 [CA 4] Center 34 (4~65) winsize 62
2470 20:15:10.030449 [CA 5] Center 33 (3~63) winsize 61
2471 20:15:10.031005
2472 20:15:10.033584 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2473 20:15:10.034055
2474 20:15:10.036970 [CATrainingPosCal] consider 1 rank data
2475 20:15:10.040547 u2DelayCellTimex100 = 270/100 ps
2476 20:15:10.043620 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2477 20:15:10.047322 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2478 20:15:10.053606 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2479 20:15:10.057433 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 20:15:10.060441 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2481 20:15:10.063949 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2482 20:15:10.064377
2483 20:15:10.067040 CA PerBit enable=1, Macro0, CA PI delay=33
2484 20:15:10.067464
2485 20:15:10.070627 [CBTSetCACLKResult] CA Dly = 33
2486 20:15:10.071054 CS Dly: 6 (0~37)
2487 20:15:10.071478 ==
2488 20:15:10.073642 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 20:15:10.080566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 20:15:10.080994 ==
2491 20:15:10.084038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 20:15:10.090552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 20:15:10.099269 [CA 0] Center 39 (8~70) winsize 63
2494 20:15:10.102886 [CA 1] Center 38 (8~69) winsize 62
2495 20:15:10.106051 [CA 2] Center 35 (5~66) winsize 62
2496 20:15:10.109148 [CA 3] Center 35 (5~66) winsize 62
2497 20:15:10.112287 [CA 4] Center 34 (4~65) winsize 62
2498 20:15:10.115717 [CA 5] Center 34 (4~64) winsize 61
2499 20:15:10.116135
2500 20:15:10.118555 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2501 20:15:10.118635
2502 20:15:10.122107 [CATrainingPosCal] consider 2 rank data
2503 20:15:10.125420 u2DelayCellTimex100 = 270/100 ps
2504 20:15:10.129129 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2505 20:15:10.132151 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2506 20:15:10.138976 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 20:15:10.142463 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 20:15:10.145479 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2509 20:15:10.149078 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2510 20:15:10.149178
2511 20:15:10.152322 CA PerBit enable=1, Macro0, CA PI delay=33
2512 20:15:10.152422
2513 20:15:10.155583 [CBTSetCACLKResult] CA Dly = 33
2514 20:15:10.155693 CS Dly: 7 (0~39)
2515 20:15:10.155781
2516 20:15:10.158763 ----->DramcWriteLeveling(PI) begin...
2517 20:15:10.162685 ==
2518 20:15:10.165394 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 20:15:10.169021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 20:15:10.169208 ==
2521 20:15:10.172397 Write leveling (Byte 0): 34 => 34
2522 20:15:10.175915 Write leveling (Byte 1): 32 => 32
2523 20:15:10.179101 DramcWriteLeveling(PI) end<-----
2524 20:15:10.179390
2525 20:15:10.179564 ==
2526 20:15:10.182093 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 20:15:10.185474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 20:15:10.185715 ==
2529 20:15:10.188868 [Gating] SW mode calibration
2530 20:15:10.195874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 20:15:10.202044 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 20:15:10.205744 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2533 20:15:10.209194 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2534 20:15:10.212273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 20:15:10.219325 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 20:15:10.222859 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 20:15:10.225901 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 20:15:10.232615 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2539 20:15:10.235801 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
2540 20:15:10.239244 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2541 20:15:10.245460 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 20:15:10.249121 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 20:15:10.252564 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 20:15:10.259317 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 20:15:10.262499 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 20:15:10.265572 1 0 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2547 20:15:10.272660 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2548 20:15:10.275949 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
2549 20:15:10.278760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 20:15:10.285530 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 20:15:10.289093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 20:15:10.292480 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 20:15:10.299113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 20:15:10.302583 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 20:15:10.305899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 20:15:10.309310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 20:15:10.316309 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 20:15:10.319188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 20:15:10.322330 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 20:15:10.329153 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 20:15:10.332482 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 20:15:10.335987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 20:15:10.342759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 20:15:10.345922 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 20:15:10.349410 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 20:15:10.356124 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 20:15:10.359058 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 20:15:10.362411 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 20:15:10.368737 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 20:15:10.372296 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 20:15:10.375550 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 20:15:10.382450 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 20:15:10.382810 Total UI for P1: 0, mck2ui 16
2574 20:15:10.385436 best dqsien dly found for B0: ( 1, 3, 28)
2575 20:15:10.392051 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 20:15:10.395242 Total UI for P1: 0, mck2ui 16
2577 20:15:10.398651 best dqsien dly found for B1: ( 1, 4, 0)
2578 20:15:10.402016 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2579 20:15:10.405355 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2580 20:15:10.405506
2581 20:15:10.408626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2582 20:15:10.411878 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 20:15:10.415169 [Gating] SW calibration Done
2584 20:15:10.415320 ==
2585 20:15:10.418699 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 20:15:10.422024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 20:15:10.422178 ==
2588 20:15:10.425510 RX Vref Scan: 0
2589 20:15:10.425657
2590 20:15:10.425792 RX Vref 0 -> 0, step: 1
2591 20:15:10.428902
2592 20:15:10.429046 RX Delay -40 -> 252, step: 8
2593 20:15:10.435229 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2594 20:15:10.438802 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2595 20:15:10.442340 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2596 20:15:10.445176 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2597 20:15:10.448647 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2598 20:15:10.452044 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2599 20:15:10.458847 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2600 20:15:10.462210 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2601 20:15:10.465922 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2602 20:15:10.468716 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2603 20:15:10.472506 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2604 20:15:10.479002 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2605 20:15:10.482165 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2606 20:15:10.485522 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2607 20:15:10.489244 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2608 20:15:10.492338 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2609 20:15:10.496017 ==
2610 20:15:10.496161 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 20:15:10.502080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 20:15:10.502164 ==
2613 20:15:10.502239 DQS Delay:
2614 20:15:10.505576 DQS0 = 0, DQS1 = 0
2615 20:15:10.505650 DQM Delay:
2616 20:15:10.508906 DQM0 = 123, DQM1 = 110
2617 20:15:10.509002 DQ Delay:
2618 20:15:10.511952 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2619 20:15:10.515474 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2620 20:15:10.519116 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2621 20:15:10.522226 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2622 20:15:10.522329
2623 20:15:10.522409
2624 20:15:10.522484 ==
2625 20:15:10.525488 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 20:15:10.532565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 20:15:10.532768 ==
2628 20:15:10.532879
2629 20:15:10.532979
2630 20:15:10.533071 TX Vref Scan disable
2631 20:15:10.535486 == TX Byte 0 ==
2632 20:15:10.538956 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2633 20:15:10.545264 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2634 20:15:10.545448 == TX Byte 1 ==
2635 20:15:10.548845 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2636 20:15:10.555468 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2637 20:15:10.555711 ==
2638 20:15:10.559021 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 20:15:10.562119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 20:15:10.562432 ==
2641 20:15:10.573463 TX Vref=22, minBit 4, minWin=22, winSum=397
2642 20:15:10.576727 TX Vref=24, minBit 4, minWin=23, winSum=403
2643 20:15:10.580104 TX Vref=26, minBit 7, minWin=24, winSum=413
2644 20:15:10.583393 TX Vref=28, minBit 0, minWin=24, winSum=414
2645 20:15:10.586898 TX Vref=30, minBit 7, minWin=24, winSum=412
2646 20:15:10.590198 TX Vref=32, minBit 1, minWin=25, winSum=412
2647 20:15:10.596672 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 32
2648 20:15:10.597181
2649 20:15:10.600130 Final TX Range 1 Vref 32
2650 20:15:10.600600
2651 20:15:10.600971 ==
2652 20:15:10.603879 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 20:15:10.606759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 20:15:10.607238 ==
2655 20:15:10.607444
2656 20:15:10.609748
2657 20:15:10.609836 TX Vref Scan disable
2658 20:15:10.613271 == TX Byte 0 ==
2659 20:15:10.616494 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2660 20:15:10.619895 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2661 20:15:10.623244 == TX Byte 1 ==
2662 20:15:10.626618 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2663 20:15:10.629659 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2664 20:15:10.629738
2665 20:15:10.633237 [DATLAT]
2666 20:15:10.633307 Freq=1200, CH0 RK0
2667 20:15:10.633377
2668 20:15:10.636303 DATLAT Default: 0xd
2669 20:15:10.636375 0, 0xFFFF, sum = 0
2670 20:15:10.640123 1, 0xFFFF, sum = 0
2671 20:15:10.640195 2, 0xFFFF, sum = 0
2672 20:15:10.643415 3, 0xFFFF, sum = 0
2673 20:15:10.643486 4, 0xFFFF, sum = 0
2674 20:15:10.646256 5, 0xFFFF, sum = 0
2675 20:15:10.646341 6, 0xFFFF, sum = 0
2676 20:15:10.650066 7, 0xFFFF, sum = 0
2677 20:15:10.650142 8, 0xFFFF, sum = 0
2678 20:15:10.653413 9, 0xFFFF, sum = 0
2679 20:15:10.656786 10, 0xFFFF, sum = 0
2680 20:15:10.656863 11, 0xFFFF, sum = 0
2681 20:15:10.659998 12, 0x0, sum = 1
2682 20:15:10.660068 13, 0x0, sum = 2
2683 20:15:10.660131 14, 0x0, sum = 3
2684 20:15:10.663258 15, 0x0, sum = 4
2685 20:15:10.663333 best_step = 13
2686 20:15:10.663394
2687 20:15:10.663452 ==
2688 20:15:10.666748 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 20:15:10.673458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 20:15:10.673533 ==
2691 20:15:10.673596 RX Vref Scan: 1
2692 20:15:10.673666
2693 20:15:10.676684 Set Vref Range= 32 -> 127
2694 20:15:10.676752
2695 20:15:10.680001 RX Vref 32 -> 127, step: 1
2696 20:15:10.680072
2697 20:15:10.683169 RX Delay -13 -> 252, step: 4
2698 20:15:10.683241
2699 20:15:10.686579 Set Vref, RX VrefLevel [Byte0]: 32
2700 20:15:10.690183 [Byte1]: 32
2701 20:15:10.690252
2702 20:15:10.693486 Set Vref, RX VrefLevel [Byte0]: 33
2703 20:15:10.696769 [Byte1]: 33
2704 20:15:10.696839
2705 20:15:10.700146 Set Vref, RX VrefLevel [Byte0]: 34
2706 20:15:10.703200 [Byte1]: 34
2707 20:15:10.706980
2708 20:15:10.707051 Set Vref, RX VrefLevel [Byte0]: 35
2709 20:15:10.710438 [Byte1]: 35
2710 20:15:10.715299
2711 20:15:10.715374 Set Vref, RX VrefLevel [Byte0]: 36
2712 20:15:10.718279 [Byte1]: 36
2713 20:15:10.722794
2714 20:15:10.722872 Set Vref, RX VrefLevel [Byte0]: 37
2715 20:15:10.726402 [Byte1]: 37
2716 20:15:10.730795
2717 20:15:10.730865 Set Vref, RX VrefLevel [Byte0]: 38
2718 20:15:10.733944 [Byte1]: 38
2719 20:15:10.738572
2720 20:15:10.738643 Set Vref, RX VrefLevel [Byte0]: 39
2721 20:15:10.742093 [Byte1]: 39
2722 20:15:10.746620
2723 20:15:10.746697 Set Vref, RX VrefLevel [Byte0]: 40
2724 20:15:10.750104 [Byte1]: 40
2725 20:15:10.754636
2726 20:15:10.754707 Set Vref, RX VrefLevel [Byte0]: 41
2727 20:15:10.757713 [Byte1]: 41
2728 20:15:10.762489
2729 20:15:10.762562 Set Vref, RX VrefLevel [Byte0]: 42
2730 20:15:10.765624 [Byte1]: 42
2731 20:15:10.770047
2732 20:15:10.770115 Set Vref, RX VrefLevel [Byte0]: 43
2733 20:15:10.773533 [Byte1]: 43
2734 20:15:10.778569
2735 20:15:10.778639 Set Vref, RX VrefLevel [Byte0]: 44
2736 20:15:10.781250 [Byte1]: 44
2737 20:15:10.785947
2738 20:15:10.786024 Set Vref, RX VrefLevel [Byte0]: 45
2739 20:15:10.789236 [Byte1]: 45
2740 20:15:10.793974
2741 20:15:10.794053 Set Vref, RX VrefLevel [Byte0]: 46
2742 20:15:10.797216 [Byte1]: 46
2743 20:15:10.802035
2744 20:15:10.802106 Set Vref, RX VrefLevel [Byte0]: 47
2745 20:15:10.805196 [Byte1]: 47
2746 20:15:10.809867
2747 20:15:10.809943 Set Vref, RX VrefLevel [Byte0]: 48
2748 20:15:10.813012 [Byte1]: 48
2749 20:15:10.817801
2750 20:15:10.817884 Set Vref, RX VrefLevel [Byte0]: 49
2751 20:15:10.820997 [Byte1]: 49
2752 20:15:10.825858
2753 20:15:10.825928 Set Vref, RX VrefLevel [Byte0]: 50
2754 20:15:10.828903 [Byte1]: 50
2755 20:15:10.833291
2756 20:15:10.833369 Set Vref, RX VrefLevel [Byte0]: 51
2757 20:15:10.836832 [Byte1]: 51
2758 20:15:10.841448
2759 20:15:10.841523 Set Vref, RX VrefLevel [Byte0]: 52
2760 20:15:10.844406 [Byte1]: 52
2761 20:15:10.849414
2762 20:15:10.849485 Set Vref, RX VrefLevel [Byte0]: 53
2763 20:15:10.852495 [Byte1]: 53
2764 20:15:10.857490
2765 20:15:10.857560 Set Vref, RX VrefLevel [Byte0]: 54
2766 20:15:10.860396 [Byte1]: 54
2767 20:15:10.864904
2768 20:15:10.864973 Set Vref, RX VrefLevel [Byte0]: 55
2769 20:15:10.868354 [Byte1]: 55
2770 20:15:10.872859
2771 20:15:10.872944 Set Vref, RX VrefLevel [Byte0]: 56
2772 20:15:10.875940 [Byte1]: 56
2773 20:15:10.880928
2774 20:15:10.881033 Set Vref, RX VrefLevel [Byte0]: 57
2775 20:15:10.884146 [Byte1]: 57
2776 20:15:10.888533
2777 20:15:10.888635 Set Vref, RX VrefLevel [Byte0]: 58
2778 20:15:10.891678 [Byte1]: 58
2779 20:15:10.896392
2780 20:15:10.896502 Set Vref, RX VrefLevel [Byte0]: 59
2781 20:15:10.899993 [Byte1]: 59
2782 20:15:10.904515
2783 20:15:10.904649 Set Vref, RX VrefLevel [Byte0]: 60
2784 20:15:10.908127 [Byte1]: 60
2785 20:15:10.912389
2786 20:15:10.912528 Set Vref, RX VrefLevel [Byte0]: 61
2787 20:15:10.915602 [Byte1]: 61
2788 20:15:10.920011
2789 20:15:10.920092 Set Vref, RX VrefLevel [Byte0]: 62
2790 20:15:10.923443 [Byte1]: 62
2791 20:15:10.927982
2792 20:15:10.928055 Set Vref, RX VrefLevel [Byte0]: 63
2793 20:15:10.931376 [Byte1]: 63
2794 20:15:10.936210
2795 20:15:10.936286 Set Vref, RX VrefLevel [Byte0]: 64
2796 20:15:10.939357 [Byte1]: 64
2797 20:15:10.944132
2798 20:15:10.944217 Set Vref, RX VrefLevel [Byte0]: 65
2799 20:15:10.947351 [Byte1]: 65
2800 20:15:10.951886
2801 20:15:10.951962 Set Vref, RX VrefLevel [Byte0]: 66
2802 20:15:10.954861 [Byte1]: 66
2803 20:15:10.959574
2804 20:15:10.959647 Set Vref, RX VrefLevel [Byte0]: 67
2805 20:15:10.962585 [Byte1]: 67
2806 20:15:10.967351
2807 20:15:10.967460 Set Vref, RX VrefLevel [Byte0]: 68
2808 20:15:10.970890 [Byte1]: 68
2809 20:15:10.975173
2810 20:15:10.975249 Set Vref, RX VrefLevel [Byte0]: 69
2811 20:15:10.978645 [Byte1]: 69
2812 20:15:10.983330
2813 20:15:10.983407 Set Vref, RX VrefLevel [Byte0]: 70
2814 20:15:10.986698 [Byte1]: 70
2815 20:15:10.991043
2816 20:15:10.991124 Set Vref, RX VrefLevel [Byte0]: 71
2817 20:15:10.994419 [Byte1]: 71
2818 20:15:10.999262
2819 20:15:10.999343 Final RX Vref Byte 0 = 58 to rank0
2820 20:15:11.002424 Final RX Vref Byte 1 = 48 to rank0
2821 20:15:11.005610 Final RX Vref Byte 0 = 58 to rank1
2822 20:15:11.009365 Final RX Vref Byte 1 = 48 to rank1==
2823 20:15:11.012530 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 20:15:11.019103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 20:15:11.019186 ==
2826 20:15:11.019253 DQS Delay:
2827 20:15:11.019314 DQS0 = 0, DQS1 = 0
2828 20:15:11.022624 DQM Delay:
2829 20:15:11.022706 DQM0 = 123, DQM1 = 109
2830 20:15:11.025930 DQ Delay:
2831 20:15:11.029039 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2832 20:15:11.032651 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2833 20:15:11.035699 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2834 20:15:11.039090 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2835 20:15:11.039172
2836 20:15:11.039237
2837 20:15:11.046024 [DQSOSCAuto] RK0, (LSB)MR18= 0x704, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2838 20:15:11.049008 CH0 RK0: MR19=404, MR18=704
2839 20:15:11.055873 CH0_RK0: MR19=0x404, MR18=0x704, DQSOSC=407, MR23=63, INC=39, DEC=26
2840 20:15:11.055955
2841 20:15:11.059182 ----->DramcWriteLeveling(PI) begin...
2842 20:15:11.059264 ==
2843 20:15:11.062526 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 20:15:11.065687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 20:15:11.065769 ==
2846 20:15:11.069063 Write leveling (Byte 0): 34 => 34
2847 20:15:11.072570 Write leveling (Byte 1): 29 => 29
2848 20:15:11.076048 DramcWriteLeveling(PI) end<-----
2849 20:15:11.076129
2850 20:15:11.076194 ==
2851 20:15:11.079620 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 20:15:11.082624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 20:15:11.086143 ==
2854 20:15:11.086224 [Gating] SW mode calibration
2855 20:15:11.092513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 20:15:11.099202 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 20:15:11.102477 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2858 20:15:11.109400 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 20:15:11.112869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 20:15:11.116303 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 20:15:11.122900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 20:15:11.126170 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 20:15:11.129418 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 20:15:11.136068 0 15 28 | B1->B0 | 3030 2b2b | 0 0 | (1 0) (0 0)
2865 20:15:11.139174 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 20:15:11.142857 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 20:15:11.145880 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 20:15:11.152731 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 20:15:11.156181 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 20:15:11.159612 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 20:15:11.165880 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2872 20:15:11.169697 1 0 28 | B1->B0 | 3434 3e3e | 1 1 | (0 0) (0 0)
2873 20:15:11.173651 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 20:15:11.179942 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 20:15:11.182970 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 20:15:11.186798 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 20:15:11.193386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 20:15:11.196470 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 20:15:11.200105 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 20:15:11.206803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2881 20:15:11.209812 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 20:15:11.213164 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 20:15:11.220031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 20:15:11.223666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 20:15:11.226720 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 20:15:11.229842 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 20:15:11.236574 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 20:15:11.239964 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 20:15:11.243196 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 20:15:11.250072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 20:15:11.253652 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 20:15:11.256795 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 20:15:11.263278 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 20:15:11.266614 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 20:15:11.270289 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 20:15:11.277052 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 20:15:11.279984 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 20:15:11.283386 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 20:15:11.286501 Total UI for P1: 0, mck2ui 16
2900 20:15:11.290222 best dqsien dly found for B0: ( 1, 3, 30)
2901 20:15:11.293310 Total UI for P1: 0, mck2ui 16
2902 20:15:11.296840 best dqsien dly found for B1: ( 1, 4, 0)
2903 20:15:11.299978 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2904 20:15:11.303269 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2905 20:15:11.303690
2906 20:15:11.306872 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2907 20:15:11.310019 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2908 20:15:11.313625 [Gating] SW calibration Done
2909 20:15:11.314070 ==
2910 20:15:11.316759 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 20:15:11.323203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 20:15:11.323286 ==
2913 20:15:11.323351 RX Vref Scan: 0
2914 20:15:11.323412
2915 20:15:11.326871 RX Vref 0 -> 0, step: 1
2916 20:15:11.326953
2917 20:15:11.329767 RX Delay -40 -> 252, step: 8
2918 20:15:11.333099 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 20:15:11.336564 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 20:15:11.339912 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 20:15:11.343382 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2922 20:15:11.350156 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 20:15:11.353403 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 20:15:11.356630 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 20:15:11.360309 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 20:15:11.363393 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 20:15:11.366834 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 20:15:11.373298 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 20:15:11.376802 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 20:15:11.380005 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 20:15:11.383421 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 20:15:11.390278 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 20:15:11.393195 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2934 20:15:11.393277 ==
2935 20:15:11.396644 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 20:15:11.400250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 20:15:11.400333 ==
2938 20:15:11.400400 DQS Delay:
2939 20:15:11.403458 DQS0 = 0, DQS1 = 0
2940 20:15:11.403547 DQM Delay:
2941 20:15:11.406976 DQM0 = 120, DQM1 = 108
2942 20:15:11.407064 DQ Delay:
2943 20:15:11.410384 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2944 20:15:11.413706 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2945 20:15:11.416913 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2946 20:15:11.420086 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2947 20:15:11.420170
2948 20:15:11.423657
2949 20:15:11.423739 ==
2950 20:15:11.427055 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 20:15:11.430202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 20:15:11.430285 ==
2953 20:15:11.430351
2954 20:15:11.430413
2955 20:15:11.433483 TX Vref Scan disable
2956 20:15:11.433565 == TX Byte 0 ==
2957 20:15:11.439912 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2958 20:15:11.443393 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2959 20:15:11.443477 == TX Byte 1 ==
2960 20:15:11.446899 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2961 20:15:11.453795 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2962 20:15:11.453878 ==
2963 20:15:11.456645 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 20:15:11.459999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 20:15:11.460082 ==
2966 20:15:11.472555 TX Vref=22, minBit 1, minWin=24, winSum=407
2967 20:15:11.475975 TX Vref=24, minBit 7, minWin=24, winSum=414
2968 20:15:11.478984 TX Vref=26, minBit 7, minWin=24, winSum=414
2969 20:15:11.482473 TX Vref=28, minBit 2, minWin=25, winSum=420
2970 20:15:11.485900 TX Vref=30, minBit 1, minWin=25, winSum=425
2971 20:15:11.489005 TX Vref=32, minBit 2, minWin=25, winSum=422
2972 20:15:11.496238 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 30
2973 20:15:11.496322
2974 20:15:11.499422 Final TX Range 1 Vref 30
2975 20:15:11.499505
2976 20:15:11.499572 ==
2977 20:15:11.502627 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 20:15:11.505875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 20:15:11.505964 ==
2980 20:15:11.506031
2981 20:15:11.506093
2982 20:15:11.509245 TX Vref Scan disable
2983 20:15:11.512726 == TX Byte 0 ==
2984 20:15:11.515821 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2985 20:15:11.519267 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2986 20:15:11.522417 == TX Byte 1 ==
2987 20:15:11.526088 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2988 20:15:11.529410 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2989 20:15:11.529492
2990 20:15:11.532652 [DATLAT]
2991 20:15:11.532735 Freq=1200, CH0 RK1
2992 20:15:11.532801
2993 20:15:11.536207 DATLAT Default: 0xd
2994 20:15:11.536289 0, 0xFFFF, sum = 0
2995 20:15:11.539443 1, 0xFFFF, sum = 0
2996 20:15:11.539531 2, 0xFFFF, sum = 0
2997 20:15:11.542723 3, 0xFFFF, sum = 0
2998 20:15:11.542813 4, 0xFFFF, sum = 0
2999 20:15:11.546201 5, 0xFFFF, sum = 0
3000 20:15:11.546283 6, 0xFFFF, sum = 0
3001 20:15:11.549246 7, 0xFFFF, sum = 0
3002 20:15:11.549327 8, 0xFFFF, sum = 0
3003 20:15:11.552649 9, 0xFFFF, sum = 0
3004 20:15:11.552732 10, 0xFFFF, sum = 0
3005 20:15:11.556267 11, 0xFFFF, sum = 0
3006 20:15:11.559567 12, 0x0, sum = 1
3007 20:15:11.559650 13, 0x0, sum = 2
3008 20:15:11.559716 14, 0x0, sum = 3
3009 20:15:11.563086 15, 0x0, sum = 4
3010 20:15:11.563169 best_step = 13
3011 20:15:11.563234
3012 20:15:11.563294 ==
3013 20:15:11.566436 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 20:15:11.573069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 20:15:11.573156 ==
3016 20:15:11.573224 RX Vref Scan: 0
3017 20:15:11.573287
3018 20:15:11.576208 RX Vref 0 -> 0, step: 1
3019 20:15:11.576289
3020 20:15:11.579391 RX Delay -21 -> 252, step: 4
3021 20:15:11.583027 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 20:15:11.585889 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 20:15:11.593086 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3024 20:15:11.596320 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3025 20:15:11.599517 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3026 20:15:11.603397 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3027 20:15:11.606475 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3028 20:15:11.609931 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3029 20:15:11.616374 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3030 20:15:11.619646 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3031 20:15:11.623512 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3032 20:15:11.626368 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3033 20:15:11.629872 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3034 20:15:11.636669 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3035 20:15:11.640087 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 20:15:11.643277 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3037 20:15:11.643723 ==
3038 20:15:11.646566 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 20:15:11.649831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 20:15:11.649960 ==
3041 20:15:11.653379 DQS Delay:
3042 20:15:11.653468 DQS0 = 0, DQS1 = 0
3043 20:15:11.656446 DQM Delay:
3044 20:15:11.656535 DQM0 = 119, DQM1 = 107
3045 20:15:11.656624 DQ Delay:
3046 20:15:11.663286 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3047 20:15:11.666545 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3048 20:15:11.669891 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3049 20:15:11.673425 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3050 20:15:11.673549
3051 20:15:11.673699
3052 20:15:11.679707 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3053 20:15:11.683370 CH0 RK1: MR19=403, MR18=FF6
3054 20:15:11.689850 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3055 20:15:11.692899 [RxdqsGatingPostProcess] freq 1200
3056 20:15:11.696749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 20:15:11.699815 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 20:15:11.703028 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 20:15:11.706988 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 20:15:11.709827 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 20:15:11.713853 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 20:15:11.716859 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 20:15:11.720322 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 20:15:11.723676 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 20:15:11.726777 Pre-setting of DQS Precalculation
3066 20:15:11.730082 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 20:15:11.730546 ==
3068 20:15:11.733618 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 20:15:11.739778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 20:15:11.740243 ==
3071 20:15:11.743709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 20:15:11.749792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3073 20:15:11.758867 [CA 0] Center 37 (7~68) winsize 62
3074 20:15:11.761969 [CA 1] Center 37 (7~68) winsize 62
3075 20:15:11.765452 [CA 2] Center 35 (5~65) winsize 61
3076 20:15:11.768839 [CA 3] Center 34 (4~65) winsize 62
3077 20:15:11.772045 [CA 4] Center 34 (4~65) winsize 62
3078 20:15:11.775561 [CA 5] Center 33 (3~64) winsize 62
3079 20:15:11.776021
3080 20:15:11.778956 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 20:15:11.779411
3082 20:15:11.782393 [CATrainingPosCal] consider 1 rank data
3083 20:15:11.785373 u2DelayCellTimex100 = 270/100 ps
3084 20:15:11.788974 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 20:15:11.792416 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 20:15:11.795662 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 20:15:11.802247 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 20:15:11.805961 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3089 20:15:11.808946 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 20:15:11.809405
3091 20:15:11.812108 CA PerBit enable=1, Macro0, CA PI delay=33
3092 20:15:11.812522
3093 20:15:11.815592 [CBTSetCACLKResult] CA Dly = 33
3094 20:15:11.816008 CS Dly: 5 (0~36)
3095 20:15:11.816338 ==
3096 20:15:11.819255 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 20:15:11.825518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 20:15:11.826008 ==
3099 20:15:11.828942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 20:15:11.835794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3101 20:15:11.844439 [CA 0] Center 38 (8~68) winsize 61
3102 20:15:11.847997 [CA 1] Center 38 (7~69) winsize 63
3103 20:15:11.850848 [CA 2] Center 35 (5~66) winsize 62
3104 20:15:11.854440 [CA 3] Center 35 (5~65) winsize 61
3105 20:15:11.857613 [CA 4] Center 35 (5~65) winsize 61
3106 20:15:11.860966 [CA 5] Center 34 (4~64) winsize 61
3107 20:15:11.861384
3108 20:15:11.864486 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 20:15:11.864905
3110 20:15:11.867797 [CATrainingPosCal] consider 2 rank data
3111 20:15:11.870916 u2DelayCellTimex100 = 270/100 ps
3112 20:15:11.874629 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3113 20:15:11.877996 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3114 20:15:11.881478 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 20:15:11.888231 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3116 20:15:11.891321 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 20:15:11.894664 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 20:15:11.895261
3119 20:15:11.897991 CA PerBit enable=1, Macro0, CA PI delay=34
3120 20:15:11.898416
3121 20:15:11.901204 [CBTSetCACLKResult] CA Dly = 34
3122 20:15:11.901649 CS Dly: 6 (0~39)
3123 20:15:11.902223
3124 20:15:11.904982 ----->DramcWriteLeveling(PI) begin...
3125 20:15:11.905407 ==
3126 20:15:11.908255 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 20:15:11.914594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 20:15:11.915096 ==
3129 20:15:11.917900 Write leveling (Byte 0): 25 => 25
3130 20:15:11.921084 Write leveling (Byte 1): 28 => 28
3131 20:15:11.921518 DramcWriteLeveling(PI) end<-----
3132 20:15:11.921898
3133 20:15:11.924512 ==
3134 20:15:11.928083 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 20:15:11.931298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 20:15:11.931784 ==
3137 20:15:11.934565 [Gating] SW mode calibration
3138 20:15:11.941169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 20:15:11.944870 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 20:15:11.951148 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 20:15:11.954580 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 20:15:11.957775 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 20:15:11.964632 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 20:15:11.967763 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 20:15:11.971194 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3146 20:15:11.977869 0 15 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
3147 20:15:11.981523 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3148 20:15:11.984537 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 20:15:11.991568 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 20:15:11.994975 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 20:15:11.997611 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 20:15:12.001282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 20:15:12.007864 1 0 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3154 20:15:12.011006 1 0 24 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
3155 20:15:12.014150 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 20:15:12.021024 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 20:15:12.024111 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 20:15:12.027657 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 20:15:12.034531 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 20:15:12.037642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 20:15:12.041107 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3162 20:15:12.047488 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 20:15:12.050993 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 20:15:12.055114 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 20:15:12.061317 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 20:15:12.064745 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 20:15:12.068129 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 20:15:12.074674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 20:15:12.077711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 20:15:12.081385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 20:15:12.088130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 20:15:12.091167 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 20:15:12.094850 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 20:15:12.097788 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 20:15:12.104418 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 20:15:12.108076 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 20:15:12.111306 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 20:15:12.117976 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3179 20:15:12.121268 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 20:15:12.124425 Total UI for P1: 0, mck2ui 16
3181 20:15:12.127588 best dqsien dly found for B0: ( 1, 3, 22)
3182 20:15:12.131160 Total UI for P1: 0, mck2ui 16
3183 20:15:12.134377 best dqsien dly found for B1: ( 1, 3, 26)
3184 20:15:12.137913 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3185 20:15:12.140918 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3186 20:15:12.141320
3187 20:15:12.144899 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3188 20:15:12.147822 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3189 20:15:12.151019 [Gating] SW calibration Done
3190 20:15:12.151322 ==
3191 20:15:12.155042 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 20:15:12.157734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 20:15:12.161469 ==
3194 20:15:12.161749 RX Vref Scan: 0
3195 20:15:12.162011
3196 20:15:12.164501 RX Vref 0 -> 0, step: 1
3197 20:15:12.164830
3198 20:15:12.167953 RX Delay -40 -> 252, step: 8
3199 20:15:12.171132 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3200 20:15:12.174728 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3201 20:15:12.177797 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3202 20:15:12.181245 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3203 20:15:12.184831 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3204 20:15:12.191140 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3205 20:15:12.194376 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3206 20:15:12.197719 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3207 20:15:12.200982 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 20:15:12.204273 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3209 20:15:12.210689 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3210 20:15:12.214610 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 20:15:12.217591 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3212 20:15:12.221009 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3213 20:15:12.224144 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3214 20:15:12.230819 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3215 20:15:12.230921 ==
3216 20:15:12.234254 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 20:15:12.237435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 20:15:12.237532 ==
3219 20:15:12.237620 DQS Delay:
3220 20:15:12.241116 DQS0 = 0, DQS1 = 0
3221 20:15:12.241223 DQM Delay:
3222 20:15:12.244210 DQM0 = 119, DQM1 = 112
3223 20:15:12.244325 DQ Delay:
3224 20:15:12.247821 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3225 20:15:12.251025 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3226 20:15:12.254741 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3227 20:15:12.258201 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3228 20:15:12.258279
3229 20:15:12.258383
3230 20:15:12.261179 ==
3231 20:15:12.264511 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 20:15:12.268337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 20:15:12.268411 ==
3234 20:15:12.268489
3235 20:15:12.268564
3236 20:15:12.271179 TX Vref Scan disable
3237 20:15:12.271251 == TX Byte 0 ==
3238 20:15:12.274623 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3239 20:15:12.281088 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3240 20:15:12.281192 == TX Byte 1 ==
3241 20:15:12.284340 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3242 20:15:12.291305 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3243 20:15:12.291382 ==
3244 20:15:12.294442 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 20:15:12.297827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 20:15:12.297929 ==
3247 20:15:12.309633 TX Vref=22, minBit 1, minWin=24, winSum=403
3248 20:15:12.312788 TX Vref=24, minBit 1, minWin=24, winSum=404
3249 20:15:12.316227 TX Vref=26, minBit 8, minWin=25, winSum=414
3250 20:15:12.319443 TX Vref=28, minBit 10, minWin=25, winSum=421
3251 20:15:12.322713 TX Vref=30, minBit 11, minWin=25, winSum=422
3252 20:15:12.329932 TX Vref=32, minBit 9, minWin=25, winSum=421
3253 20:15:12.332840 [TxChooseVref] Worse bit 11, Min win 25, Win sum 422, Final Vref 30
3254 20:15:12.333434
3255 20:15:12.336322 Final TX Range 1 Vref 30
3256 20:15:12.336837
3257 20:15:12.337333 ==
3258 20:15:12.339941 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 20:15:12.343120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 20:15:12.343605 ==
3261 20:15:12.346315
3262 20:15:12.346768
3263 20:15:12.347102 TX Vref Scan disable
3264 20:15:12.349610 == TX Byte 0 ==
3265 20:15:12.353268 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3266 20:15:12.360101 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3267 20:15:12.360536 == TX Byte 1 ==
3268 20:15:12.363035 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 20:15:12.366455 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 20:15:12.369735
3271 20:15:12.370168 [DATLAT]
3272 20:15:12.370499 Freq=1200, CH1 RK0
3273 20:15:12.370812
3274 20:15:12.373115 DATLAT Default: 0xd
3275 20:15:12.373463 0, 0xFFFF, sum = 0
3276 20:15:12.376353 1, 0xFFFF, sum = 0
3277 20:15:12.376783 2, 0xFFFF, sum = 0
3278 20:15:12.379732 3, 0xFFFF, sum = 0
3279 20:15:12.380356 4, 0xFFFF, sum = 0
3280 20:15:12.383090 5, 0xFFFF, sum = 0
3281 20:15:12.386222 6, 0xFFFF, sum = 0
3282 20:15:12.386673 7, 0xFFFF, sum = 0
3283 20:15:12.389799 8, 0xFFFF, sum = 0
3284 20:15:12.390310 9, 0xFFFF, sum = 0
3285 20:15:12.392887 10, 0xFFFF, sum = 0
3286 20:15:12.393344 11, 0xFFFF, sum = 0
3287 20:15:12.396180 12, 0x0, sum = 1
3288 20:15:12.396739 13, 0x0, sum = 2
3289 20:15:12.399643 14, 0x0, sum = 3
3290 20:15:12.400071 15, 0x0, sum = 4
3291 20:15:12.400415 best_step = 13
3292 20:15:12.400730
3293 20:15:12.403062 ==
3294 20:15:12.406707 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 20:15:12.410180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 20:15:12.410602 ==
3297 20:15:12.410950 RX Vref Scan: 1
3298 20:15:12.411283
3299 20:15:12.413014 Set Vref Range= 32 -> 127
3300 20:15:12.413444
3301 20:15:12.416216 RX Vref 32 -> 127, step: 1
3302 20:15:12.416619
3303 20:15:12.419869 RX Delay -13 -> 252, step: 4
3304 20:15:12.420295
3305 20:15:12.422986 Set Vref, RX VrefLevel [Byte0]: 32
3306 20:15:12.426176 [Byte1]: 32
3307 20:15:12.426473
3308 20:15:12.429605 Set Vref, RX VrefLevel [Byte0]: 33
3309 20:15:12.432909 [Byte1]: 33
3310 20:15:12.433141
3311 20:15:12.436233 Set Vref, RX VrefLevel [Byte0]: 34
3312 20:15:12.439526 [Byte1]: 34
3313 20:15:12.444128
3314 20:15:12.444350 Set Vref, RX VrefLevel [Byte0]: 35
3315 20:15:12.447235 [Byte1]: 35
3316 20:15:12.451539
3317 20:15:12.451760 Set Vref, RX VrefLevel [Byte0]: 36
3318 20:15:12.454814 [Byte1]: 36
3319 20:15:12.459783
3320 20:15:12.459863 Set Vref, RX VrefLevel [Byte0]: 37
3321 20:15:12.462945 [Byte1]: 37
3322 20:15:12.467311
3323 20:15:12.467391 Set Vref, RX VrefLevel [Byte0]: 38
3324 20:15:12.470868 [Byte1]: 38
3325 20:15:12.475625
3326 20:15:12.475737 Set Vref, RX VrefLevel [Byte0]: 39
3327 20:15:12.478882 [Byte1]: 39
3328 20:15:12.483100
3329 20:15:12.483208 Set Vref, RX VrefLevel [Byte0]: 40
3330 20:15:12.486411 [Byte1]: 40
3331 20:15:12.491046
3332 20:15:12.491155 Set Vref, RX VrefLevel [Byte0]: 41
3333 20:15:12.494533 [Byte1]: 41
3334 20:15:12.498831
3335 20:15:12.498944 Set Vref, RX VrefLevel [Byte0]: 42
3336 20:15:12.502301 [Byte1]: 42
3337 20:15:12.506836
3338 20:15:12.506910 Set Vref, RX VrefLevel [Byte0]: 43
3339 20:15:12.510317 [Byte1]: 43
3340 20:15:12.514568
3341 20:15:12.514634 Set Vref, RX VrefLevel [Byte0]: 44
3342 20:15:12.517819 [Byte1]: 44
3343 20:15:12.522419
3344 20:15:12.522497 Set Vref, RX VrefLevel [Byte0]: 45
3345 20:15:12.525887 [Byte1]: 45
3346 20:15:12.530485
3347 20:15:12.530563 Set Vref, RX VrefLevel [Byte0]: 46
3348 20:15:12.533613 [Byte1]: 46
3349 20:15:12.538321
3350 20:15:12.538401 Set Vref, RX VrefLevel [Byte0]: 47
3351 20:15:12.541795 [Byte1]: 47
3352 20:15:12.546166
3353 20:15:12.546245 Set Vref, RX VrefLevel [Byte0]: 48
3354 20:15:12.549342 [Byte1]: 48
3355 20:15:12.554196
3356 20:15:12.554301 Set Vref, RX VrefLevel [Byte0]: 49
3357 20:15:12.557555 [Byte1]: 49
3358 20:15:12.562031
3359 20:15:12.562109 Set Vref, RX VrefLevel [Byte0]: 50
3360 20:15:12.565509 [Byte1]: 50
3361 20:15:12.569689
3362 20:15:12.569768 Set Vref, RX VrefLevel [Byte0]: 51
3363 20:15:12.573147 [Byte1]: 51
3364 20:15:12.577763
3365 20:15:12.577841 Set Vref, RX VrefLevel [Byte0]: 52
3366 20:15:12.581360 [Byte1]: 52
3367 20:15:12.585934
3368 20:15:12.586049 Set Vref, RX VrefLevel [Byte0]: 53
3369 20:15:12.588947 [Byte1]: 53
3370 20:15:12.593754
3371 20:15:12.593832 Set Vref, RX VrefLevel [Byte0]: 54
3372 20:15:12.597199 [Byte1]: 54
3373 20:15:12.601519
3374 20:15:12.601598 Set Vref, RX VrefLevel [Byte0]: 55
3375 20:15:12.604767 [Byte1]: 55
3376 20:15:12.609284
3377 20:15:12.609364 Set Vref, RX VrefLevel [Byte0]: 56
3378 20:15:12.612589 [Byte1]: 56
3379 20:15:12.617165
3380 20:15:12.617246 Set Vref, RX VrefLevel [Byte0]: 57
3381 20:15:12.620519 [Byte1]: 57
3382 20:15:12.625141
3383 20:15:12.625221 Set Vref, RX VrefLevel [Byte0]: 58
3384 20:15:12.628420 [Byte1]: 58
3385 20:15:12.633134
3386 20:15:12.633212 Set Vref, RX VrefLevel [Byte0]: 59
3387 20:15:12.636287 [Byte1]: 59
3388 20:15:12.641013
3389 20:15:12.641093 Set Vref, RX VrefLevel [Byte0]: 60
3390 20:15:12.644130 [Byte1]: 60
3391 20:15:12.649410
3392 20:15:12.649493 Set Vref, RX VrefLevel [Byte0]: 61
3393 20:15:12.652241 [Byte1]: 61
3394 20:15:12.656567
3395 20:15:12.656640 Set Vref, RX VrefLevel [Byte0]: 62
3396 20:15:12.660163 [Byte1]: 62
3397 20:15:12.664483
3398 20:15:12.664558 Set Vref, RX VrefLevel [Byte0]: 63
3399 20:15:12.667927 [Byte1]: 63
3400 20:15:12.672489
3401 20:15:12.672573 Set Vref, RX VrefLevel [Byte0]: 64
3402 20:15:12.675658 [Byte1]: 64
3403 20:15:12.680556
3404 20:15:12.680625 Set Vref, RX VrefLevel [Byte0]: 65
3405 20:15:12.683907 [Byte1]: 65
3406 20:15:12.688271
3407 20:15:12.688364 Set Vref, RX VrefLevel [Byte0]: 66
3408 20:15:12.691512 [Byte1]: 66
3409 20:15:12.696015
3410 20:15:12.696087 Set Vref, RX VrefLevel [Byte0]: 67
3411 20:15:12.699326 [Byte1]: 67
3412 20:15:12.704140
3413 20:15:12.704215 Final RX Vref Byte 0 = 51 to rank0
3414 20:15:12.707603 Final RX Vref Byte 1 = 52 to rank0
3415 20:15:12.710907 Final RX Vref Byte 0 = 51 to rank1
3416 20:15:12.714198 Final RX Vref Byte 1 = 52 to rank1==
3417 20:15:12.717298 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 20:15:12.724350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 20:15:12.724936 ==
3420 20:15:12.725416 DQS Delay:
3421 20:15:12.725890 DQS0 = 0, DQS1 = 0
3422 20:15:12.727912 DQM Delay:
3423 20:15:12.728407 DQM0 = 119, DQM1 = 112
3424 20:15:12.731153 DQ Delay:
3425 20:15:12.734454 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3426 20:15:12.738151 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3427 20:15:12.741197 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3428 20:15:12.744595 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3429 20:15:12.745057
3430 20:15:12.745427
3431 20:15:12.751241 [DQSOSCAuto] RK0, (LSB)MR18= 0x317, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3432 20:15:12.754672 CH1 RK0: MR19=404, MR18=317
3433 20:15:12.761209 CH1_RK0: MR19=0x404, MR18=0x317, DQSOSC=401, MR23=63, INC=40, DEC=27
3434 20:15:12.761628
3435 20:15:12.764329 ----->DramcWriteLeveling(PI) begin...
3436 20:15:12.764799 ==
3437 20:15:12.767669 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 20:15:12.770877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 20:15:12.771302 ==
3440 20:15:12.774477 Write leveling (Byte 0): 24 => 24
3441 20:15:12.777902 Write leveling (Byte 1): 29 => 29
3442 20:15:12.780839 DramcWriteLeveling(PI) end<-----
3443 20:15:12.780922
3444 20:15:12.780987 ==
3445 20:15:12.783844 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 20:15:12.787576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 20:15:12.790622 ==
3448 20:15:12.790735 [Gating] SW mode calibration
3449 20:15:12.800858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 20:15:12.803985 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 20:15:12.807385 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 20:15:12.814208 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 20:15:12.817338 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 20:15:12.820868 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 20:15:12.827415 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 20:15:12.830895 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 20:15:12.834535 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (0 0) (1 0)
3458 20:15:12.840951 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (0 0)
3459 20:15:12.844421 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 20:15:12.847714 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 20:15:12.851023 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 20:15:12.857571 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 20:15:12.861266 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 20:15:12.864344 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 20:15:12.871260 1 0 24 | B1->B0 | 3737 2929 | 0 0 | (0 0) (0 0)
3466 20:15:12.874438 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3467 20:15:12.877676 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 20:15:12.884177 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 20:15:12.887562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 20:15:12.890583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 20:15:12.898308 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 20:15:12.900914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 20:15:12.904107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 20:15:12.910532 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3475 20:15:12.914240 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 20:15:12.917370 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 20:15:12.924070 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 20:15:12.927696 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 20:15:12.930465 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 20:15:12.936900 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 20:15:12.940366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 20:15:12.943925 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 20:15:12.950434 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 20:15:12.953731 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 20:15:12.957088 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 20:15:12.963654 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 20:15:12.967228 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 20:15:12.970330 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 20:15:12.977183 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 20:15:12.980225 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3491 20:15:12.983710 Total UI for P1: 0, mck2ui 16
3492 20:15:12.987053 best dqsien dly found for B1: ( 1, 3, 24)
3493 20:15:12.990342 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 20:15:12.993617 Total UI for P1: 0, mck2ui 16
3495 20:15:12.997209 best dqsien dly found for B0: ( 1, 3, 26)
3496 20:15:13.000282 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3497 20:15:13.003531 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3498 20:15:13.003611
3499 20:15:13.007008 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 20:15:13.013701 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3501 20:15:13.013804 [Gating] SW calibration Done
3502 20:15:13.013906 ==
3503 20:15:13.016967 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 20:15:13.023575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 20:15:13.023683 ==
3506 20:15:13.023767 RX Vref Scan: 0
3507 20:15:13.023853
3508 20:15:13.026908 RX Vref 0 -> 0, step: 1
3509 20:15:13.027016
3510 20:15:13.030200 RX Delay -40 -> 252, step: 8
3511 20:15:13.033379 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3512 20:15:13.036876 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3513 20:15:13.040133 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3514 20:15:13.046948 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3515 20:15:13.050287 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3516 20:15:13.053263 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 20:15:13.056743 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3518 20:15:13.060422 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3519 20:15:13.066946 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3520 20:15:13.069933 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3521 20:15:13.073206 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 20:15:13.076457 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3523 20:15:13.079827 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3524 20:15:13.086550 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3525 20:15:13.089691 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3526 20:15:13.092974 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3527 20:15:13.093081 ==
3528 20:15:13.096263 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 20:15:13.099833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 20:15:13.099937 ==
3531 20:15:13.103196 DQS Delay:
3532 20:15:13.103278 DQS0 = 0, DQS1 = 0
3533 20:15:13.106348 DQM Delay:
3534 20:15:13.106460 DQM0 = 119, DQM1 = 113
3535 20:15:13.109971 DQ Delay:
3536 20:15:13.112939 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3537 20:15:13.116432 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3538 20:15:13.119712 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3539 20:15:13.123113 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3540 20:15:13.123227
3541 20:15:13.123342
3542 20:15:13.123438 ==
3543 20:15:13.126196 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 20:15:13.129794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 20:15:13.129905 ==
3546 20:15:13.129993
3547 20:15:13.130056
3548 20:15:13.132840 TX Vref Scan disable
3549 20:15:13.136106 == TX Byte 0 ==
3550 20:15:13.139629 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3551 20:15:13.142966 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3552 20:15:13.146435 == TX Byte 1 ==
3553 20:15:13.149669 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3554 20:15:13.152866 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3555 20:15:13.152969 ==
3556 20:15:13.156342 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 20:15:13.159508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 20:15:13.162622 ==
3559 20:15:13.173136 TX Vref=22, minBit 1, minWin=25, winSum=416
3560 20:15:13.176395 TX Vref=24, minBit 1, minWin=25, winSum=421
3561 20:15:13.179717 TX Vref=26, minBit 1, minWin=26, winSum=426
3562 20:15:13.183046 TX Vref=28, minBit 0, minWin=26, winSum=425
3563 20:15:13.186421 TX Vref=30, minBit 1, minWin=26, winSum=430
3564 20:15:13.193010 TX Vref=32, minBit 1, minWin=26, winSum=429
3565 20:15:13.196996 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3566 20:15:13.197073
3567 20:15:13.199946 Final TX Range 1 Vref 30
3568 20:15:13.200049
3569 20:15:13.200141 ==
3570 20:15:13.202883 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 20:15:13.206389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 20:15:13.206468 ==
3573 20:15:13.206532
3574 20:15:13.209738
3575 20:15:13.209840 TX Vref Scan disable
3576 20:15:13.213276 == TX Byte 0 ==
3577 20:15:13.216574 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 20:15:13.219947 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 20:15:13.223167 == TX Byte 1 ==
3580 20:15:13.226148 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 20:15:13.229617 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 20:15:13.233436
3583 20:15:13.233519 [DATLAT]
3584 20:15:13.233586 Freq=1200, CH1 RK1
3585 20:15:13.233651
3586 20:15:13.236689 DATLAT Default: 0xd
3587 20:15:13.236773 0, 0xFFFF, sum = 0
3588 20:15:13.239835 1, 0xFFFF, sum = 0
3589 20:15:13.239948 2, 0xFFFF, sum = 0
3590 20:15:13.243009 3, 0xFFFF, sum = 0
3591 20:15:13.243094 4, 0xFFFF, sum = 0
3592 20:15:13.246383 5, 0xFFFF, sum = 0
3593 20:15:13.249873 6, 0xFFFF, sum = 0
3594 20:15:13.249986 7, 0xFFFF, sum = 0
3595 20:15:13.253162 8, 0xFFFF, sum = 0
3596 20:15:13.253247 9, 0xFFFF, sum = 0
3597 20:15:13.256619 10, 0xFFFF, sum = 0
3598 20:15:13.256704 11, 0xFFFF, sum = 0
3599 20:15:13.259816 12, 0x0, sum = 1
3600 20:15:13.259901 13, 0x0, sum = 2
3601 20:15:13.263278 14, 0x0, sum = 3
3602 20:15:13.263363 15, 0x0, sum = 4
3603 20:15:13.263431 best_step = 13
3604 20:15:13.263491
3605 20:15:13.266648 ==
3606 20:15:13.269692 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 20:15:13.273092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 20:15:13.273176 ==
3609 20:15:13.273243 RX Vref Scan: 0
3610 20:15:13.273304
3611 20:15:13.276560 RX Vref 0 -> 0, step: 1
3612 20:15:13.276644
3613 20:15:13.279827 RX Delay -13 -> 252, step: 4
3614 20:15:13.282996 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3615 20:15:13.289549 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3616 20:15:13.292805 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3617 20:15:13.296293 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3618 20:15:13.299574 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3619 20:15:13.302697 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 20:15:13.309495 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3621 20:15:13.312979 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3622 20:15:13.316022 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3623 20:15:13.319581 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3624 20:15:13.322700 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3625 20:15:13.329429 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3626 20:15:13.333048 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3627 20:15:13.336006 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3628 20:15:13.339503 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3629 20:15:13.342585 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3630 20:15:13.346075 ==
3631 20:15:13.346164 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 20:15:13.352579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 20:15:13.352661 ==
3634 20:15:13.352726 DQS Delay:
3635 20:15:13.356214 DQS0 = 0, DQS1 = 0
3636 20:15:13.356295 DQM Delay:
3637 20:15:13.359546 DQM0 = 119, DQM1 = 113
3638 20:15:13.359628 DQ Delay:
3639 20:15:13.362949 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3640 20:15:13.365776 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3641 20:15:13.369424 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3642 20:15:13.372864 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3643 20:15:13.372940
3644 20:15:13.373003
3645 20:15:13.382375 [DQSOSCAuto] RK1, (LSB)MR18= 0xbef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3646 20:15:13.382464 CH1 RK1: MR19=403, MR18=BEF
3647 20:15:13.389170 CH1_RK1: MR19=0x403, MR18=0xBEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3648 20:15:13.392423 [RxdqsGatingPostProcess] freq 1200
3649 20:15:13.399332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 20:15:13.402206 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 20:15:13.405826 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 20:15:13.409032 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 20:15:13.412547 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 20:15:13.415877 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 20:15:13.418982 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 20:15:13.422217 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 20:15:13.425388 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 20:15:13.425469 Pre-setting of DQS Precalculation
3659 20:15:13.431925 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 20:15:13.438657 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 20:15:13.445139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 20:15:13.445222
3663 20:15:13.448504
3664 20:15:13.448585 [Calibration Summary] 2400 Mbps
3665 20:15:13.451808 CH 0, Rank 0
3666 20:15:13.451890 SW Impedance : PASS
3667 20:15:13.455040 DUTY Scan : NO K
3668 20:15:13.458520 ZQ Calibration : PASS
3669 20:15:13.458601 Jitter Meter : NO K
3670 20:15:13.461687 CBT Training : PASS
3671 20:15:13.464876 Write leveling : PASS
3672 20:15:13.464957 RX DQS gating : PASS
3673 20:15:13.468593 RX DQ/DQS(RDDQC) : PASS
3674 20:15:13.471636 TX DQ/DQS : PASS
3675 20:15:13.471717 RX DATLAT : PASS
3676 20:15:13.475030 RX DQ/DQS(Engine): PASS
3677 20:15:13.478032 TX OE : NO K
3678 20:15:13.478114 All Pass.
3679 20:15:13.478178
3680 20:15:13.478237 CH 0, Rank 1
3681 20:15:13.481546 SW Impedance : PASS
3682 20:15:13.484700 DUTY Scan : NO K
3683 20:15:13.484780 ZQ Calibration : PASS
3684 20:15:13.488318 Jitter Meter : NO K
3685 20:15:13.491528 CBT Training : PASS
3686 20:15:13.491609 Write leveling : PASS
3687 20:15:13.494821 RX DQS gating : PASS
3688 20:15:13.494902 RX DQ/DQS(RDDQC) : PASS
3689 20:15:13.497812 TX DQ/DQS : PASS
3690 20:15:13.501302 RX DATLAT : PASS
3691 20:15:13.501414 RX DQ/DQS(Engine): PASS
3692 20:15:13.504531 TX OE : NO K
3693 20:15:13.504614 All Pass.
3694 20:15:13.504680
3695 20:15:13.507721 CH 1, Rank 0
3696 20:15:13.507805 SW Impedance : PASS
3697 20:15:13.511384 DUTY Scan : NO K
3698 20:15:13.514291 ZQ Calibration : PASS
3699 20:15:13.514367 Jitter Meter : NO K
3700 20:15:13.517961 CBT Training : PASS
3701 20:15:13.521111 Write leveling : PASS
3702 20:15:13.521197 RX DQS gating : PASS
3703 20:15:13.524792 RX DQ/DQS(RDDQC) : PASS
3704 20:15:13.527723 TX DQ/DQS : PASS
3705 20:15:13.527812 RX DATLAT : PASS
3706 20:15:13.531197 RX DQ/DQS(Engine): PASS
3707 20:15:13.534481 TX OE : NO K
3708 20:15:13.534599 All Pass.
3709 20:15:13.534682
3710 20:15:13.534759 CH 1, Rank 1
3711 20:15:13.537423 SW Impedance : PASS
3712 20:15:13.540974 DUTY Scan : NO K
3713 20:15:13.541079 ZQ Calibration : PASS
3714 20:15:13.544194 Jitter Meter : NO K
3715 20:15:13.547513 CBT Training : PASS
3716 20:15:13.547590 Write leveling : PASS
3717 20:15:13.551145 RX DQS gating : PASS
3718 20:15:13.554231 RX DQ/DQS(RDDQC) : PASS
3719 20:15:13.554315 TX DQ/DQS : PASS
3720 20:15:13.557753 RX DATLAT : PASS
3721 20:15:13.557861 RX DQ/DQS(Engine): PASS
3722 20:15:13.560963 TX OE : NO K
3723 20:15:13.561052 All Pass.
3724 20:15:13.561123
3725 20:15:13.564422 DramC Write-DBI off
3726 20:15:13.567469 PER_BANK_REFRESH: Hybrid Mode
3727 20:15:13.567565 TX_TRACKING: ON
3728 20:15:13.577277 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 20:15:13.580744 [FAST_K] Save calibration result to emmc
3730 20:15:13.584018 dramc_set_vcore_voltage set vcore to 650000
3731 20:15:13.587405 Read voltage for 600, 5
3732 20:15:13.587542 Vio18 = 0
3733 20:15:13.590681 Vcore = 650000
3734 20:15:13.590834 Vdram = 0
3735 20:15:13.590957 Vddq = 0
3736 20:15:13.591070 Vmddr = 0
3737 20:15:13.597505 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 20:15:13.604059 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 20:15:13.604347 MEM_TYPE=3, freq_sel=19
3740 20:15:13.607529 sv_algorithm_assistance_LP4_1600
3741 20:15:13.610857 ============ PULL DRAM RESETB DOWN ============
3742 20:15:13.617647 ========== PULL DRAM RESETB DOWN end =========
3743 20:15:13.621228 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 20:15:13.624289 ===================================
3745 20:15:13.627422 LPDDR4 DRAM CONFIGURATION
3746 20:15:13.631042 ===================================
3747 20:15:13.631496 EX_ROW_EN[0] = 0x0
3748 20:15:13.634269 EX_ROW_EN[1] = 0x0
3749 20:15:13.634752 LP4Y_EN = 0x0
3750 20:15:13.637625 WORK_FSP = 0x0
3751 20:15:13.638052 WL = 0x2
3752 20:15:13.640637 RL = 0x2
3753 20:15:13.641101 BL = 0x2
3754 20:15:13.644049 RPST = 0x0
3755 20:15:13.647362 RD_PRE = 0x0
3756 20:15:13.647850 WR_PRE = 0x1
3757 20:15:13.650635 WR_PST = 0x0
3758 20:15:13.651088 DBI_WR = 0x0
3759 20:15:13.654004 DBI_RD = 0x0
3760 20:15:13.654461 OTF = 0x1
3761 20:15:13.657268 ===================================
3762 20:15:13.660854 ===================================
3763 20:15:13.661315 ANA top config
3764 20:15:13.664030 ===================================
3765 20:15:13.667519 DLL_ASYNC_EN = 0
3766 20:15:13.670856 ALL_SLAVE_EN = 1
3767 20:15:13.673932 NEW_RANK_MODE = 1
3768 20:15:13.677568 DLL_IDLE_MODE = 1
3769 20:15:13.678026 LP45_APHY_COMB_EN = 1
3770 20:15:13.680424 TX_ODT_DIS = 1
3771 20:15:13.684295 NEW_8X_MODE = 1
3772 20:15:13.687596 ===================================
3773 20:15:13.690308 ===================================
3774 20:15:13.693934 data_rate = 1200
3775 20:15:13.697405 CKR = 1
3776 20:15:13.697993 DQ_P2S_RATIO = 8
3777 20:15:13.700691 ===================================
3778 20:15:13.704030 CA_P2S_RATIO = 8
3779 20:15:13.707098 DQ_CA_OPEN = 0
3780 20:15:13.710752 DQ_SEMI_OPEN = 0
3781 20:15:13.713691 CA_SEMI_OPEN = 0
3782 20:15:13.717512 CA_FULL_RATE = 0
3783 20:15:13.717929 DQ_CKDIV4_EN = 1
3784 20:15:13.720546 CA_CKDIV4_EN = 1
3785 20:15:13.723858 CA_PREDIV_EN = 0
3786 20:15:13.727507 PH8_DLY = 0
3787 20:15:13.730734 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 20:15:13.734197 DQ_AAMCK_DIV = 4
3789 20:15:13.734615 CA_AAMCK_DIV = 4
3790 20:15:13.737347 CA_ADMCK_DIV = 4
3791 20:15:13.740679 DQ_TRACK_CA_EN = 0
3792 20:15:13.743973 CA_PICK = 600
3793 20:15:13.747187 CA_MCKIO = 600
3794 20:15:13.750712 MCKIO_SEMI = 0
3795 20:15:13.753998 PLL_FREQ = 2288
3796 20:15:13.754433 DQ_UI_PI_RATIO = 32
3797 20:15:13.757262 CA_UI_PI_RATIO = 0
3798 20:15:13.760664 ===================================
3799 20:15:13.764059 ===================================
3800 20:15:13.767292 memory_type:LPDDR4
3801 20:15:13.770263 GP_NUM : 10
3802 20:15:13.770676 SRAM_EN : 1
3803 20:15:13.773654 MD32_EN : 0
3804 20:15:13.776975 ===================================
3805 20:15:13.777443 [ANA_INIT] >>>>>>>>>>>>>>
3806 20:15:13.780297 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 20:15:13.784098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 20:15:13.787036 ===================================
3809 20:15:13.790227 data_rate = 1200,PCW = 0X5800
3810 20:15:13.793890 ===================================
3811 20:15:13.797159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 20:15:13.803965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 20:15:13.807295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 20:15:13.814004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 20:15:13.817299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 20:15:13.820493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 20:15:13.823849 [ANA_INIT] flow start
3818 20:15:13.824419 [ANA_INIT] PLL >>>>>>>>
3819 20:15:13.827055 [ANA_INIT] PLL <<<<<<<<
3820 20:15:13.830415 [ANA_INIT] MIDPI >>>>>>>>
3821 20:15:13.830849 [ANA_INIT] MIDPI <<<<<<<<
3822 20:15:13.833708 [ANA_INIT] DLL >>>>>>>>
3823 20:15:13.836972 [ANA_INIT] flow end
3824 20:15:13.840509 ============ LP4 DIFF to SE enter ============
3825 20:15:13.843823 ============ LP4 DIFF to SE exit ============
3826 20:15:13.846805 [ANA_INIT] <<<<<<<<<<<<<
3827 20:15:13.850103 [Flow] Enable top DCM control >>>>>
3828 20:15:13.853662 [Flow] Enable top DCM control <<<<<
3829 20:15:13.856770 Enable DLL master slave shuffle
3830 20:15:13.860443 ==============================================================
3831 20:15:13.863436 Gating Mode config
3832 20:15:13.870287 ==============================================================
3833 20:15:13.870841 Config description:
3834 20:15:13.879914 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 20:15:13.886597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 20:15:13.890223 SELPH_MODE 0: By rank 1: By Phase
3837 20:15:13.896578 ==============================================================
3838 20:15:13.899704 GAT_TRACK_EN = 1
3839 20:15:13.903201 RX_GATING_MODE = 2
3840 20:15:13.906578 RX_GATING_TRACK_MODE = 2
3841 20:15:13.910040 SELPH_MODE = 1
3842 20:15:13.913452 PICG_EARLY_EN = 1
3843 20:15:13.916569 VALID_LAT_VALUE = 1
3844 20:15:13.920060 ==============================================================
3845 20:15:13.923146 Enter into Gating configuration >>>>
3846 20:15:13.926581 Exit from Gating configuration <<<<
3847 20:15:13.929735 Enter into DVFS_PRE_config >>>>>
3848 20:15:13.942880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 20:15:13.943325 Exit from DVFS_PRE_config <<<<<
3850 20:15:13.946190 Enter into PICG configuration >>>>
3851 20:15:13.949706 Exit from PICG configuration <<<<
3852 20:15:13.953444 [RX_INPUT] configuration >>>>>
3853 20:15:13.957132 [RX_INPUT] configuration <<<<<
3854 20:15:13.962788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 20:15:13.966325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 20:15:13.972925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 20:15:13.979329 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 20:15:13.986000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 20:15:13.992768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 20:15:13.996013 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 20:15:13.999447 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 20:15:14.002627 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 20:15:14.009411 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 20:15:14.012483 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 20:15:14.015808 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 20:15:14.018944 ===================================
3867 20:15:14.022365 LPDDR4 DRAM CONFIGURATION
3868 20:15:14.025893 ===================================
3869 20:15:14.029177 EX_ROW_EN[0] = 0x0
3870 20:15:14.029599 EX_ROW_EN[1] = 0x0
3871 20:15:14.032521 LP4Y_EN = 0x0
3872 20:15:14.033031 WORK_FSP = 0x0
3873 20:15:14.035993 WL = 0x2
3874 20:15:14.036502 RL = 0x2
3875 20:15:14.038921 BL = 0x2
3876 20:15:14.039366 RPST = 0x0
3877 20:15:14.042730 RD_PRE = 0x0
3878 20:15:14.043155 WR_PRE = 0x1
3879 20:15:14.045894 WR_PST = 0x0
3880 20:15:14.046587 DBI_WR = 0x0
3881 20:15:14.049067 DBI_RD = 0x0
3882 20:15:14.049502 OTF = 0x1
3883 20:15:14.052440 ===================================
3884 20:15:14.055647 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 20:15:14.062647 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 20:15:14.065659 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 20:15:14.069206 ===================================
3888 20:15:14.072550 LPDDR4 DRAM CONFIGURATION
3889 20:15:14.075964 ===================================
3890 20:15:14.076413 EX_ROW_EN[0] = 0x10
3891 20:15:14.079292 EX_ROW_EN[1] = 0x0
3892 20:15:14.082276 LP4Y_EN = 0x0
3893 20:15:14.082711 WORK_FSP = 0x0
3894 20:15:14.085794 WL = 0x2
3895 20:15:14.086260 RL = 0x2
3896 20:15:14.088916 BL = 0x2
3897 20:15:14.089508 RPST = 0x0
3898 20:15:14.092308 RD_PRE = 0x0
3899 20:15:14.092866 WR_PRE = 0x1
3900 20:15:14.095625 WR_PST = 0x0
3901 20:15:14.096249 DBI_WR = 0x0
3902 20:15:14.098767 DBI_RD = 0x0
3903 20:15:14.099411 OTF = 0x1
3904 20:15:14.102055 ===================================
3905 20:15:14.109103 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 20:15:14.113224 nWR fixed to 30
3907 20:15:14.116483 [ModeRegInit_LP4] CH0 RK0
3908 20:15:14.116900 [ModeRegInit_LP4] CH0 RK1
3909 20:15:14.119925 [ModeRegInit_LP4] CH1 RK0
3910 20:15:14.123332 [ModeRegInit_LP4] CH1 RK1
3911 20:15:14.123779 match AC timing 17
3912 20:15:14.129735 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 20:15:14.133113 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 20:15:14.136244 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 20:15:14.143048 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 20:15:14.146098 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 20:15:14.146699 ==
3918 20:15:14.149786 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 20:15:14.152676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 20:15:14.153100 ==
3921 20:15:14.159436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 20:15:14.166011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3923 20:15:14.169085 [CA 0] Center 36 (5~67) winsize 63
3924 20:15:14.172390 [CA 1] Center 36 (6~67) winsize 62
3925 20:15:14.175769 [CA 2] Center 34 (4~65) winsize 62
3926 20:15:14.179020 [CA 3] Center 34 (3~65) winsize 63
3927 20:15:14.182410 [CA 4] Center 34 (3~65) winsize 63
3928 20:15:14.185819 [CA 5] Center 33 (2~64) winsize 63
3929 20:15:14.186389
3930 20:15:14.189612 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3931 20:15:14.190297
3932 20:15:14.192650 [CATrainingPosCal] consider 1 rank data
3933 20:15:14.195979 u2DelayCellTimex100 = 270/100 ps
3934 20:15:14.199145 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3935 20:15:14.202371 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 20:15:14.205853 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 20:15:14.209076 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3938 20:15:14.215384 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3939 20:15:14.218772 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3940 20:15:14.219103
3941 20:15:14.222081 CA PerBit enable=1, Macro0, CA PI delay=33
3942 20:15:14.222386
3943 20:15:14.225273 [CBTSetCACLKResult] CA Dly = 33
3944 20:15:14.225520 CS Dly: 5 (0~36)
3945 20:15:14.225766 ==
3946 20:15:14.228684 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 20:15:14.232215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 20:15:14.235137 ==
3949 20:15:14.239057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 20:15:14.245308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 20:15:14.248822 [CA 0] Center 36 (6~67) winsize 62
3952 20:15:14.252019 [CA 1] Center 36 (6~67) winsize 62
3953 20:15:14.255315 [CA 2] Center 34 (4~65) winsize 62
3954 20:15:14.259091 [CA 3] Center 34 (4~65) winsize 62
3955 20:15:14.262068 [CA 4] Center 34 (3~65) winsize 63
3956 20:15:14.265654 [CA 5] Center 33 (3~64) winsize 62
3957 20:15:14.265882
3958 20:15:14.268572 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 20:15:14.268802
3960 20:15:14.272223 [CATrainingPosCal] consider 2 rank data
3961 20:15:14.275178 u2DelayCellTimex100 = 270/100 ps
3962 20:15:14.278634 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 20:15:14.281845 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 20:15:14.285277 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 20:15:14.291677 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 20:15:14.295323 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3967 20:15:14.298752 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 20:15:14.298937
3969 20:15:14.301616 CA PerBit enable=1, Macro0, CA PI delay=33
3970 20:15:14.301800
3971 20:15:14.304897 [CBTSetCACLKResult] CA Dly = 33
3972 20:15:14.304980 CS Dly: 5 (0~37)
3973 20:15:14.305064
3974 20:15:14.308264 ----->DramcWriteLeveling(PI) begin...
3975 20:15:14.308349 ==
3976 20:15:14.311908 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 20:15:14.318373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 20:15:14.318458 ==
3979 20:15:14.321614 Write leveling (Byte 0): 32 => 32
3980 20:15:14.324954 Write leveling (Byte 1): 30 => 30
3981 20:15:14.325038 DramcWriteLeveling(PI) end<-----
3982 20:15:14.328437
3983 20:15:14.328545 ==
3984 20:15:14.331539 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 20:15:14.334789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 20:15:14.334892 ==
3987 20:15:14.338359 [Gating] SW mode calibration
3988 20:15:14.345054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 20:15:14.347969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 20:15:14.354788 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 20:15:14.358022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 20:15:14.361380 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3993 20:15:14.368257 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3994 20:15:14.371381 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
3995 20:15:14.374622 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 20:15:14.381510 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 20:15:14.385032 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 20:15:14.388349 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 20:15:14.394688 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 20:15:14.398156 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4001 20:15:14.401406 0 10 12 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
4002 20:15:14.408243 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
4003 20:15:14.411458 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 20:15:14.414722 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 20:15:14.421377 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 20:15:14.424623 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 20:15:14.428122 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 20:15:14.434614 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 20:15:14.438099 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 20:15:14.441497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4011 20:15:14.447857 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 20:15:14.451272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 20:15:14.454491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 20:15:14.457911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 20:15:14.464216 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 20:15:14.467593 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 20:15:14.471165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 20:15:14.477488 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 20:15:14.480994 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 20:15:14.484503 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 20:15:14.491002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 20:15:14.494407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 20:15:14.497825 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 20:15:14.504070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 20:15:14.507306 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4026 20:15:14.510992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 20:15:14.513848 Total UI for P1: 0, mck2ui 16
4028 20:15:14.517751 best dqsien dly found for B0: ( 0, 13, 12)
4029 20:15:14.520530 Total UI for P1: 0, mck2ui 16
4030 20:15:14.523769 best dqsien dly found for B1: ( 0, 13, 14)
4031 20:15:14.527177 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4032 20:15:14.534016 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4033 20:15:14.534099
4034 20:15:14.537274 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4035 20:15:14.540785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 20:15:14.543782 [Gating] SW calibration Done
4037 20:15:14.543865 ==
4038 20:15:14.547135 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 20:15:14.550841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 20:15:14.550926 ==
4041 20:15:14.550990 RX Vref Scan: 0
4042 20:15:14.551052
4043 20:15:14.554007 RX Vref 0 -> 0, step: 1
4044 20:15:14.554088
4045 20:15:14.557505 RX Delay -230 -> 252, step: 16
4046 20:15:14.560765 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4047 20:15:14.567122 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4048 20:15:14.570317 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4049 20:15:14.574000 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4050 20:15:14.577115 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4051 20:15:14.580555 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4052 20:15:14.587160 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4053 20:15:14.590346 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4054 20:15:14.593635 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4055 20:15:14.597175 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4056 20:15:14.600318 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4057 20:15:14.607068 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4058 20:15:14.610499 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4059 20:15:14.613730 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4060 20:15:14.617305 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4061 20:15:14.623878 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4062 20:15:14.623961 ==
4063 20:15:14.627227 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 20:15:14.630500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 20:15:14.630584 ==
4066 20:15:14.630650 DQS Delay:
4067 20:15:14.633729 DQS0 = 0, DQS1 = 0
4068 20:15:14.633811 DQM Delay:
4069 20:15:14.636984 DQM0 = 51, DQM1 = 40
4070 20:15:14.637067 DQ Delay:
4071 20:15:14.640553 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4072 20:15:14.643779 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4073 20:15:14.647168 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4074 20:15:14.650159 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4075 20:15:14.650244
4076 20:15:14.650310
4077 20:15:14.650370 ==
4078 20:15:14.653875 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 20:15:14.657213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 20:15:14.660146 ==
4081 20:15:14.660230
4082 20:15:14.660296
4083 20:15:14.660356 TX Vref Scan disable
4084 20:15:14.663378 == TX Byte 0 ==
4085 20:15:14.667167 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4086 20:15:14.670224 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4087 20:15:14.673408 == TX Byte 1 ==
4088 20:15:14.676801 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4089 20:15:14.680322 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4090 20:15:14.683586 ==
4091 20:15:14.687127 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 20:15:14.690369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 20:15:14.690454 ==
4094 20:15:14.690520
4095 20:15:14.690583
4096 20:15:14.693598 TX Vref Scan disable
4097 20:15:14.693681 == TX Byte 0 ==
4098 20:15:14.700221 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4099 20:15:14.703569 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4100 20:15:14.703653 == TX Byte 1 ==
4101 20:15:14.710226 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4102 20:15:14.713346 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4103 20:15:14.713430
4104 20:15:14.713496 [DATLAT]
4105 20:15:14.717184 Freq=600, CH0 RK0
4106 20:15:14.717267
4107 20:15:14.717334 DATLAT Default: 0x9
4108 20:15:14.720111 0, 0xFFFF, sum = 0
4109 20:15:14.720195 1, 0xFFFF, sum = 0
4110 20:15:14.723216 2, 0xFFFF, sum = 0
4111 20:15:14.723300 3, 0xFFFF, sum = 0
4112 20:15:14.726567 4, 0xFFFF, sum = 0
4113 20:15:14.730163 5, 0xFFFF, sum = 0
4114 20:15:14.730248 6, 0xFFFF, sum = 0
4115 20:15:14.733260 7, 0xFFFF, sum = 0
4116 20:15:14.733345 8, 0x0, sum = 1
4117 20:15:14.733412 9, 0x0, sum = 2
4118 20:15:14.736482 10, 0x0, sum = 3
4119 20:15:14.736593 11, 0x0, sum = 4
4120 20:15:14.740358 best_step = 9
4121 20:15:14.740441
4122 20:15:14.740506 ==
4123 20:15:14.743495 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 20:15:14.746410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 20:15:14.746500 ==
4126 20:15:14.749836 RX Vref Scan: 1
4127 20:15:14.749967
4128 20:15:14.750053 RX Vref 0 -> 0, step: 1
4129 20:15:14.750116
4130 20:15:14.753401 RX Delay -179 -> 252, step: 8
4131 20:15:14.753484
4132 20:15:14.756696 Set Vref, RX VrefLevel [Byte0]: 58
4133 20:15:14.759903 [Byte1]: 48
4134 20:15:14.764153
4135 20:15:14.764257 Final RX Vref Byte 0 = 58 to rank0
4136 20:15:14.767314 Final RX Vref Byte 1 = 48 to rank0
4137 20:15:14.770681 Final RX Vref Byte 0 = 58 to rank1
4138 20:15:14.773775 Final RX Vref Byte 1 = 48 to rank1==
4139 20:15:14.777141 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 20:15:14.783790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 20:15:14.783874 ==
4142 20:15:14.783940 DQS Delay:
4143 20:15:14.784004 DQS0 = 0, DQS1 = 0
4144 20:15:14.786981 DQM Delay:
4145 20:15:14.787065 DQM0 = 50, DQM1 = 37
4146 20:15:14.790325 DQ Delay:
4147 20:15:14.793577 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4148 20:15:14.797305 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4149 20:15:14.797388 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4150 20:15:14.803936 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4151 20:15:14.804019
4152 20:15:14.804085
4153 20:15:14.810633 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4154 20:15:14.813592 CH0 RK0: MR19=808, MR18=5751
4155 20:15:14.820391 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4156 20:15:14.820474
4157 20:15:14.823629 ----->DramcWriteLeveling(PI) begin...
4158 20:15:14.823714 ==
4159 20:15:14.827029 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 20:15:14.830227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 20:15:14.830304 ==
4162 20:15:14.833490 Write leveling (Byte 0): 33 => 33
4163 20:15:14.836777 Write leveling (Byte 1): 31 => 31
4164 20:15:14.840257 DramcWriteLeveling(PI) end<-----
4165 20:15:14.840368
4166 20:15:14.840471 ==
4167 20:15:14.843828 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 20:15:14.847185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 20:15:14.847303 ==
4170 20:15:14.850352 [Gating] SW mode calibration
4171 20:15:14.856584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 20:15:14.863384 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 20:15:14.866592 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 20:15:14.873087 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 20:15:14.876489 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 20:15:14.880243 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 0)
4177 20:15:14.883448 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4178 20:15:14.889936 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 20:15:14.893139 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 20:15:14.896766 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 20:15:14.903050 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 20:15:14.906296 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 20:15:14.909781 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 20:15:14.916631 0 10 12 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
4185 20:15:14.919924 0 10 16 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
4186 20:15:14.923091 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 20:15:14.929429 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 20:15:14.932852 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 20:15:14.936120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 20:15:14.943030 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 20:15:14.946169 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 20:15:14.949656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 20:15:14.956198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 20:15:14.959552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 20:15:14.962775 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 20:15:14.969298 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 20:15:14.972976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 20:15:14.976114 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 20:15:14.982757 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 20:15:14.985817 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 20:15:14.989866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 20:15:14.995863 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 20:15:14.999193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 20:15:15.002773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 20:15:15.009110 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 20:15:15.012665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 20:15:15.015990 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 20:15:15.022802 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4209 20:15:15.025970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 20:15:15.029173 Total UI for P1: 0, mck2ui 16
4211 20:15:15.032516 best dqsien dly found for B0: ( 0, 13, 14)
4212 20:15:15.035783 Total UI for P1: 0, mck2ui 16
4213 20:15:15.039437 best dqsien dly found for B1: ( 0, 13, 12)
4214 20:15:15.042462 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4215 20:15:15.046030 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4216 20:15:15.046139
4217 20:15:15.049275 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4218 20:15:15.052223 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4219 20:15:15.055542 [Gating] SW calibration Done
4220 20:15:15.055624 ==
4221 20:15:15.058968 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 20:15:15.062441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 20:15:15.062523 ==
4224 20:15:15.065762 RX Vref Scan: 0
4225 20:15:15.065844
4226 20:15:15.069172 RX Vref 0 -> 0, step: 1
4227 20:15:15.069277
4228 20:15:15.072234 RX Delay -230 -> 252, step: 16
4229 20:15:15.075987 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4230 20:15:15.079006 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4231 20:15:15.082481 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4232 20:15:15.088848 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4233 20:15:15.092163 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4234 20:15:15.095454 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4235 20:15:15.098813 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4236 20:15:15.102219 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4237 20:15:15.108913 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4238 20:15:15.112174 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4239 20:15:15.115583 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4240 20:15:15.119137 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4241 20:15:15.122427 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4242 20:15:15.128974 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4243 20:15:15.132431 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4244 20:15:15.135289 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4245 20:15:15.135371 ==
4246 20:15:15.138724 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 20:15:15.145318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 20:15:15.145400 ==
4249 20:15:15.145466 DQS Delay:
4250 20:15:15.148524 DQS0 = 0, DQS1 = 0
4251 20:15:15.148606 DQM Delay:
4252 20:15:15.148671 DQM0 = 51, DQM1 = 43
4253 20:15:15.152116 DQ Delay:
4254 20:15:15.155457 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4255 20:15:15.158777 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4256 20:15:15.162132 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4257 20:15:15.165553 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4258 20:15:15.165636
4259 20:15:15.165702
4260 20:15:15.165763 ==
4261 20:15:15.168488 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 20:15:15.171731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 20:15:15.171814 ==
4264 20:15:15.171879
4265 20:15:15.171939
4266 20:15:15.175192 TX Vref Scan disable
4267 20:15:15.175274 == TX Byte 0 ==
4268 20:15:15.181831 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4269 20:15:15.185209 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4270 20:15:15.185291 == TX Byte 1 ==
4271 20:15:15.191940 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4272 20:15:15.195160 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4273 20:15:15.195242 ==
4274 20:15:15.198366 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 20:15:15.201801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 20:15:15.201884 ==
4277 20:15:15.204766
4278 20:15:15.204848
4279 20:15:15.204914 TX Vref Scan disable
4280 20:15:15.208659 == TX Byte 0 ==
4281 20:15:15.212241 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4282 20:15:15.218459 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4283 20:15:15.218542 == TX Byte 1 ==
4284 20:15:15.222227 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4285 20:15:15.228354 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4286 20:15:15.228469
4287 20:15:15.228573 [DATLAT]
4288 20:15:15.228675 Freq=600, CH0 RK1
4289 20:15:15.228778
4290 20:15:15.232025 DATLAT Default: 0x9
4291 20:15:15.232132 0, 0xFFFF, sum = 0
4292 20:15:15.235137 1, 0xFFFF, sum = 0
4293 20:15:15.235238 2, 0xFFFF, sum = 0
4294 20:15:15.238253 3, 0xFFFF, sum = 0
4295 20:15:15.241922 4, 0xFFFF, sum = 0
4296 20:15:15.242057 5, 0xFFFF, sum = 0
4297 20:15:15.244919 6, 0xFFFF, sum = 0
4298 20:15:15.245018 7, 0xFFFF, sum = 0
4299 20:15:15.248506 8, 0x0, sum = 1
4300 20:15:15.248609 9, 0x0, sum = 2
4301 20:15:15.248709 10, 0x0, sum = 3
4302 20:15:15.251607 11, 0x0, sum = 4
4303 20:15:15.251715 best_step = 9
4304 20:15:15.251831
4305 20:15:15.251924 ==
4306 20:15:15.254893 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 20:15:15.261660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 20:15:15.261771 ==
4309 20:15:15.261879 RX Vref Scan: 0
4310 20:15:15.262018
4311 20:15:15.264979 RX Vref 0 -> 0, step: 1
4312 20:15:15.265087
4313 20:15:15.268317 RX Delay -179 -> 252, step: 8
4314 20:15:15.271570 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4315 20:15:15.278301 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4316 20:15:15.281567 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4317 20:15:15.284614 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4318 20:15:15.288190 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4319 20:15:15.291235 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4320 20:15:15.297858 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4321 20:15:15.301108 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4322 20:15:15.304655 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4323 20:15:15.308099 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4324 20:15:15.314703 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4325 20:15:15.317790 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4326 20:15:15.321360 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4327 20:15:15.324643 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4328 20:15:15.327716 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4329 20:15:15.334490 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4330 20:15:15.334587 ==
4331 20:15:15.337999 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 20:15:15.341807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 20:15:15.341902 ==
4334 20:15:15.342031 DQS Delay:
4335 20:15:15.344346 DQS0 = 0, DQS1 = 0
4336 20:15:15.344447 DQM Delay:
4337 20:15:15.348061 DQM0 = 47, DQM1 = 40
4338 20:15:15.348142 DQ Delay:
4339 20:15:15.351022 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4340 20:15:15.354436 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4341 20:15:15.357698 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4342 20:15:15.361260 DQ12 =44, DQ13 =48, DQ14 =52, DQ15 =48
4343 20:15:15.361328
4344 20:15:15.361417
4345 20:15:15.367787 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4346 20:15:15.371281 CH0 RK1: MR19=808, MR18=5D2B
4347 20:15:15.377929 CH0_RK1: MR19=0x808, MR18=0x5D2B, DQSOSC=392, MR23=63, INC=170, DEC=113
4348 20:15:15.381057 [RxdqsGatingPostProcess] freq 600
4349 20:15:15.387664 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 20:15:15.391131 Pre-setting of DQS Precalculation
4351 20:15:15.394684 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 20:15:15.394788 ==
4353 20:15:15.397713 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 20:15:15.401040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 20:15:15.401144 ==
4356 20:15:15.407573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 20:15:15.414414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 20:15:15.417780 [CA 0] Center 35 (5~66) winsize 62
4359 20:15:15.421012 [CA 1] Center 35 (5~66) winsize 62
4360 20:15:15.424484 [CA 2] Center 34 (4~65) winsize 62
4361 20:15:15.427626 [CA 3] Center 34 (3~65) winsize 63
4362 20:15:15.431054 [CA 4] Center 34 (3~65) winsize 63
4363 20:15:15.434153 [CA 5] Center 33 (3~64) winsize 62
4364 20:15:15.434252
4365 20:15:15.437754 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 20:15:15.437857
4367 20:15:15.440810 [CATrainingPosCal] consider 1 rank data
4368 20:15:15.444169 u2DelayCellTimex100 = 270/100 ps
4369 20:15:15.447617 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 20:15:15.450734 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 20:15:15.454156 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 20:15:15.457870 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 20:15:15.461140 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4374 20:15:15.467304 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 20:15:15.467412
4376 20:15:15.470847 CA PerBit enable=1, Macro0, CA PI delay=33
4377 20:15:15.470948
4378 20:15:15.474182 [CBTSetCACLKResult] CA Dly = 33
4379 20:15:15.474290 CS Dly: 5 (0~36)
4380 20:15:15.474382 ==
4381 20:15:15.477244 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 20:15:15.480784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 20:15:15.483977 ==
4384 20:15:15.487236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 20:15:15.493839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 20:15:15.497272 [CA 0] Center 35 (5~66) winsize 62
4387 20:15:15.500516 [CA 1] Center 35 (5~66) winsize 62
4388 20:15:15.503662 [CA 2] Center 34 (4~65) winsize 62
4389 20:15:15.507205 [CA 3] Center 34 (4~65) winsize 62
4390 20:15:15.510463 [CA 4] Center 34 (4~65) winsize 62
4391 20:15:15.514072 [CA 5] Center 34 (4~65) winsize 62
4392 20:15:15.514187
4393 20:15:15.517249 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 20:15:15.517352
4395 20:15:15.520661 [CATrainingPosCal] consider 2 rank data
4396 20:15:15.523641 u2DelayCellTimex100 = 270/100 ps
4397 20:15:15.527107 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4398 20:15:15.530306 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4399 20:15:15.533916 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4400 20:15:15.536905 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4401 20:15:15.543544 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 20:15:15.547300 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4403 20:15:15.547408
4404 20:15:15.550581 CA PerBit enable=1, Macro0, CA PI delay=34
4405 20:15:15.550667
4406 20:15:15.553399 [CBTSetCACLKResult] CA Dly = 34
4407 20:15:15.553469 CS Dly: 5 (0~37)
4408 20:15:15.553552
4409 20:15:15.557186 ----->DramcWriteLeveling(PI) begin...
4410 20:15:15.557266 ==
4411 20:15:15.560582 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 20:15:15.566950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 20:15:15.567062 ==
4414 20:15:15.570275 Write leveling (Byte 0): 29 => 29
4415 20:15:15.570357 Write leveling (Byte 1): 29 => 29
4416 20:15:15.573501 DramcWriteLeveling(PI) end<-----
4417 20:15:15.573610
4418 20:15:15.576951 ==
4419 20:15:15.577040 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 20:15:15.583471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 20:15:15.583584 ==
4422 20:15:15.587085 [Gating] SW mode calibration
4423 20:15:15.593751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 20:15:15.596699 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 20:15:15.603400 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 20:15:15.607031 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 20:15:15.610475 0 9 8 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 1)
4428 20:15:15.617286 0 9 12 | B1->B0 | 2c2c 2b2b | 1 0 | (1 0) (1 1)
4429 20:15:15.620271 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 20:15:15.623651 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 20:15:15.630102 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 20:15:15.633522 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 20:15:15.636819 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 20:15:15.643150 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 20:15:15.646485 0 10 8 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
4436 20:15:15.650149 0 10 12 | B1->B0 | 3d3d 3e3e | 0 0 | (1 1) (0 0)
4437 20:15:15.656725 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 20:15:15.660144 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 20:15:15.663299 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 20:15:15.666508 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 20:15:15.673172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 20:15:15.676505 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 20:15:15.679836 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 20:15:15.686340 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4445 20:15:15.689850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 20:15:15.693125 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 20:15:15.699581 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 20:15:15.702842 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 20:15:15.706335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 20:15:15.712593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 20:15:15.716141 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 20:15:15.719306 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 20:15:15.726230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 20:15:15.729487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 20:15:15.732604 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 20:15:15.739274 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 20:15:15.742654 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 20:15:15.745827 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 20:15:15.752876 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 20:15:15.755948 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4461 20:15:15.759246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 20:15:15.762577 Total UI for P1: 0, mck2ui 16
4463 20:15:15.765785 best dqsien dly found for B0: ( 0, 13, 12)
4464 20:15:15.769166 Total UI for P1: 0, mck2ui 16
4465 20:15:15.772154 best dqsien dly found for B1: ( 0, 13, 12)
4466 20:15:15.776130 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4467 20:15:15.778846 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4468 20:15:15.782495
4469 20:15:15.785569 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4470 20:15:15.788834 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4471 20:15:15.792454 [Gating] SW calibration Done
4472 20:15:15.792536 ==
4473 20:15:15.795356 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 20:15:15.798723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 20:15:15.798809 ==
4476 20:15:15.798874 RX Vref Scan: 0
4477 20:15:15.802100
4478 20:15:15.802185 RX Vref 0 -> 0, step: 1
4479 20:15:15.802283
4480 20:15:15.805322 RX Delay -230 -> 252, step: 16
4481 20:15:15.808751 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4482 20:15:15.815538 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4483 20:15:15.818632 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4484 20:15:15.821832 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4485 20:15:15.825518 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4486 20:15:15.828745 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4487 20:15:15.835100 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4488 20:15:15.838445 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4489 20:15:15.841848 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4490 20:15:15.845292 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4491 20:15:15.851964 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4492 20:15:15.855420 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4493 20:15:15.858794 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4494 20:15:15.861991 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4495 20:15:15.868469 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4496 20:15:15.871883 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4497 20:15:15.871966 ==
4498 20:15:15.875419 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 20:15:15.878628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 20:15:15.878712 ==
4501 20:15:15.878779 DQS Delay:
4502 20:15:15.882210 DQS0 = 0, DQS1 = 0
4503 20:15:15.882293 DQM Delay:
4504 20:15:15.885407 DQM0 = 45, DQM1 = 43
4505 20:15:15.885490 DQ Delay:
4506 20:15:15.888741 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4507 20:15:15.891906 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4508 20:15:15.895299 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4509 20:15:15.898661 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4510 20:15:15.898788
4511 20:15:15.898856
4512 20:15:15.898919 ==
4513 20:15:15.901890 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 20:15:15.905239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 20:15:15.908638 ==
4516 20:15:15.908721
4517 20:15:15.908787
4518 20:15:15.908849 TX Vref Scan disable
4519 20:15:15.911627 == TX Byte 0 ==
4520 20:15:15.915104 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 20:15:15.918267 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 20:15:15.921873 == TX Byte 1 ==
4523 20:15:15.925123 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 20:15:15.928257 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 20:15:15.931745 ==
4526 20:15:15.935258 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 20:15:15.938272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 20:15:15.938343 ==
4529 20:15:15.938413
4530 20:15:15.938475
4531 20:15:15.941991 TX Vref Scan disable
4532 20:15:15.942060 == TX Byte 0 ==
4533 20:15:15.948417 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4534 20:15:15.951506 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4535 20:15:15.951613 == TX Byte 1 ==
4536 20:15:15.958235 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4537 20:15:15.961437 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4538 20:15:15.961550
4539 20:15:15.961641 [DATLAT]
4540 20:15:15.964718 Freq=600, CH1 RK0
4541 20:15:15.964828
4542 20:15:15.964920 DATLAT Default: 0x9
4543 20:15:15.968328 0, 0xFFFF, sum = 0
4544 20:15:15.968449 1, 0xFFFF, sum = 0
4545 20:15:15.971849 2, 0xFFFF, sum = 0
4546 20:15:15.971958 3, 0xFFFF, sum = 0
4547 20:15:15.975088 4, 0xFFFF, sum = 0
4548 20:15:15.975200 5, 0xFFFF, sum = 0
4549 20:15:15.978397 6, 0xFFFF, sum = 0
4550 20:15:15.981830 7, 0xFFFF, sum = 0
4551 20:15:15.981940 8, 0x0, sum = 1
4552 20:15:15.982075 9, 0x0, sum = 2
4553 20:15:15.984732 10, 0x0, sum = 3
4554 20:15:15.984832 11, 0x0, sum = 4
4555 20:15:15.988381 best_step = 9
4556 20:15:15.988490
4557 20:15:15.988597 ==
4558 20:15:15.991439 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 20:15:15.995106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 20:15:15.995208 ==
4561 20:15:15.998314 RX Vref Scan: 1
4562 20:15:15.998421
4563 20:15:15.998529 RX Vref 0 -> 0, step: 1
4564 20:15:15.998617
4565 20:15:16.001461 RX Delay -179 -> 252, step: 8
4566 20:15:16.001576
4567 20:15:16.005026 Set Vref, RX VrefLevel [Byte0]: 51
4568 20:15:16.008046 [Byte1]: 52
4569 20:15:16.011832
4570 20:15:16.011953 Final RX Vref Byte 0 = 51 to rank0
4571 20:15:16.015239 Final RX Vref Byte 1 = 52 to rank0
4572 20:15:16.018505 Final RX Vref Byte 0 = 51 to rank1
4573 20:15:16.022097 Final RX Vref Byte 1 = 52 to rank1==
4574 20:15:16.025474 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 20:15:16.031957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 20:15:16.032040 ==
4577 20:15:16.032105 DQS Delay:
4578 20:15:16.035375 DQS0 = 0, DQS1 = 0
4579 20:15:16.035457 DQM Delay:
4580 20:15:16.035522 DQM0 = 45, DQM1 = 38
4581 20:15:16.038436 DQ Delay:
4582 20:15:16.041602 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =40
4583 20:15:16.044944 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =40
4584 20:15:16.048514 DQ8 =24, DQ9 =24, DQ10 =44, DQ11 =32
4585 20:15:16.051532 DQ12 =52, DQ13 =44, DQ14 =44, DQ15 =44
4586 20:15:16.051616
4587 20:15:16.051682
4588 20:15:16.058276 [DQSOSCAuto] RK0, (LSB)MR18= 0x5076, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4589 20:15:16.062132 CH1 RK0: MR19=808, MR18=5076
4590 20:15:16.068346 CH1_RK0: MR19=0x808, MR18=0x5076, DQSOSC=387, MR23=63, INC=175, DEC=116
4591 20:15:16.068466
4592 20:15:16.071986 ----->DramcWriteLeveling(PI) begin...
4593 20:15:16.072100 ==
4594 20:15:16.075148 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 20:15:16.078336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 20:15:16.078424 ==
4597 20:15:16.081753 Write leveling (Byte 0): 29 => 29
4598 20:15:16.084816 Write leveling (Byte 1): 29 => 29
4599 20:15:16.088539 DramcWriteLeveling(PI) end<-----
4600 20:15:16.088666
4601 20:15:16.088759 ==
4602 20:15:16.091748 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 20:15:16.095095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 20:15:16.095176 ==
4605 20:15:16.098142 [Gating] SW mode calibration
4606 20:15:16.104836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 20:15:16.111375 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 20:15:16.115042 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 20:15:16.121337 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 20:15:16.124962 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 20:15:16.128096 0 9 12 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 1)
4612 20:15:16.134995 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 20:15:16.138067 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 20:15:16.141281 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 20:15:16.144664 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 20:15:16.151309 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 20:15:16.154756 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 20:15:16.157870 0 10 8 | B1->B0 | 2929 2424 | 1 0 | (0 0) (0 0)
4619 20:15:16.164417 0 10 12 | B1->B0 | 4646 3434 | 0 0 | (0 0) (0 0)
4620 20:15:16.167886 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 20:15:16.170973 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 20:15:16.178064 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 20:15:16.181178 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 20:15:16.184329 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 20:15:16.191076 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 20:15:16.194385 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 20:15:16.197672 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 20:15:16.204386 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 20:15:16.207822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 20:15:16.210987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 20:15:16.217459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 20:15:16.220873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 20:15:16.224512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 20:15:16.230745 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 20:15:16.234378 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 20:15:16.237590 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 20:15:16.244825 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 20:15:16.247405 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 20:15:16.250973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 20:15:16.257537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 20:15:16.260969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 20:15:16.264023 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 20:15:16.270622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4644 20:15:16.273743 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 20:15:16.277361 Total UI for P1: 0, mck2ui 16
4646 20:15:16.280562 best dqsien dly found for B0: ( 0, 13, 14)
4647 20:15:16.284103 Total UI for P1: 0, mck2ui 16
4648 20:15:16.287065 best dqsien dly found for B1: ( 0, 13, 12)
4649 20:15:16.290431 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4650 20:15:16.293696 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4651 20:15:16.293768
4652 20:15:16.296929 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4653 20:15:16.300075 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 20:15:16.303723 [Gating] SW calibration Done
4655 20:15:16.303794 ==
4656 20:15:16.307040 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 20:15:16.310391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 20:15:16.313652 ==
4659 20:15:16.313721 RX Vref Scan: 0
4660 20:15:16.313783
4661 20:15:16.316865 RX Vref 0 -> 0, step: 1
4662 20:15:16.316934
4663 20:15:16.320123 RX Delay -230 -> 252, step: 16
4664 20:15:16.323611 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4665 20:15:16.326856 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4666 20:15:16.330333 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4667 20:15:16.336881 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4668 20:15:16.339850 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4669 20:15:16.343435 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4670 20:15:16.346664 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4671 20:15:16.350097 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4672 20:15:16.356650 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4673 20:15:16.359934 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4674 20:15:16.363432 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4675 20:15:16.366441 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4676 20:15:16.373137 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4677 20:15:16.376584 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4678 20:15:16.379669 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4679 20:15:16.383547 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4680 20:15:16.383634 ==
4681 20:15:16.386459 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 20:15:16.393116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 20:15:16.393193 ==
4684 20:15:16.393256 DQS Delay:
4685 20:15:16.396584 DQS0 = 0, DQS1 = 0
4686 20:15:16.396655 DQM Delay:
4687 20:15:16.399702 DQM0 = 47, DQM1 = 45
4688 20:15:16.399772 DQ Delay:
4689 20:15:16.402954 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =41
4690 20:15:16.406216 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4691 20:15:16.409541 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4692 20:15:16.413065 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4693 20:15:16.413133
4694 20:15:16.413193
4695 20:15:16.413258 ==
4696 20:15:16.416399 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 20:15:16.419773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 20:15:16.419841 ==
4699 20:15:16.419902
4700 20:15:16.419960
4701 20:15:16.423258 TX Vref Scan disable
4702 20:15:16.426563 == TX Byte 0 ==
4703 20:15:16.429778 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 20:15:16.432813 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 20:15:16.436533 == TX Byte 1 ==
4706 20:15:16.439634 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4707 20:15:16.442816 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4708 20:15:16.442886 ==
4709 20:15:16.446201 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 20:15:16.449695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 20:15:16.452977 ==
4712 20:15:16.453072
4713 20:15:16.453137
4714 20:15:16.453211 TX Vref Scan disable
4715 20:15:16.456558 == TX Byte 0 ==
4716 20:15:16.460136 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4717 20:15:16.466639 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4718 20:15:16.466712 == TX Byte 1 ==
4719 20:15:16.469728 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4720 20:15:16.476617 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4721 20:15:16.476690
4722 20:15:16.476753 [DATLAT]
4723 20:15:16.476821 Freq=600, CH1 RK1
4724 20:15:16.476917
4725 20:15:16.480022 DATLAT Default: 0x9
4726 20:15:16.480099 0, 0xFFFF, sum = 0
4727 20:15:16.483480 1, 0xFFFF, sum = 0
4728 20:15:16.483557 2, 0xFFFF, sum = 0
4729 20:15:16.486663 3, 0xFFFF, sum = 0
4730 20:15:16.490066 4, 0xFFFF, sum = 0
4731 20:15:16.490143 5, 0xFFFF, sum = 0
4732 20:15:16.493410 6, 0xFFFF, sum = 0
4733 20:15:16.493479 7, 0xFFFF, sum = 0
4734 20:15:16.493551 8, 0x0, sum = 1
4735 20:15:16.496412 9, 0x0, sum = 2
4736 20:15:16.496481 10, 0x0, sum = 3
4737 20:15:16.499820 11, 0x0, sum = 4
4738 20:15:16.499896 best_step = 9
4739 20:15:16.499957
4740 20:15:16.500023 ==
4741 20:15:16.503341 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 20:15:16.509733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 20:15:16.509814 ==
4744 20:15:16.509878 RX Vref Scan: 0
4745 20:15:16.509942
4746 20:15:16.513099 RX Vref 0 -> 0, step: 1
4747 20:15:16.513164
4748 20:15:16.516334 RX Delay -179 -> 252, step: 8
4749 20:15:16.519754 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4750 20:15:16.526172 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4751 20:15:16.529590 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4752 20:15:16.532714 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4753 20:15:16.536096 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4754 20:15:16.539562 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4755 20:15:16.545952 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4756 20:15:16.549510 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4757 20:15:16.552991 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4758 20:15:16.556090 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4759 20:15:16.559727 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4760 20:15:16.565833 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4761 20:15:16.569250 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4762 20:15:16.572698 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4763 20:15:16.576185 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4764 20:15:16.582773 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4765 20:15:16.582857 ==
4766 20:15:16.586078 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 20:15:16.589486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 20:15:16.589566 ==
4769 20:15:16.589629 DQS Delay:
4770 20:15:16.592760 DQS0 = 0, DQS1 = 0
4771 20:15:16.592842 DQM Delay:
4772 20:15:16.596090 DQM0 = 46, DQM1 = 40
4773 20:15:16.596164 DQ Delay:
4774 20:15:16.599243 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4775 20:15:16.602891 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4776 20:15:16.606124 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =32
4777 20:15:16.609414 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =52
4778 20:15:16.609489
4779 20:15:16.609552
4780 20:15:16.615653 [DQSOSCAuto] RK1, (LSB)MR18= 0x531a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4781 20:15:16.619005 CH1 RK1: MR19=808, MR18=531A
4782 20:15:16.625791 CH1_RK1: MR19=0x808, MR18=0x531A, DQSOSC=394, MR23=63, INC=168, DEC=112
4783 20:15:16.629375 [RxdqsGatingPostProcess] freq 600
4784 20:15:16.635742 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 20:15:16.639073 Pre-setting of DQS Precalculation
4786 20:15:16.642229 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 20:15:16.649196 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 20:15:16.655877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 20:15:16.655966
4790 20:15:16.659045
4791 20:15:16.659126 [Calibration Summary] 1200 Mbps
4792 20:15:16.662249 CH 0, Rank 0
4793 20:15:16.662331 SW Impedance : PASS
4794 20:15:16.665593 DUTY Scan : NO K
4795 20:15:16.669158 ZQ Calibration : PASS
4796 20:15:16.669239 Jitter Meter : NO K
4797 20:15:16.672191 CBT Training : PASS
4798 20:15:16.675930 Write leveling : PASS
4799 20:15:16.676011 RX DQS gating : PASS
4800 20:15:16.678863 RX DQ/DQS(RDDQC) : PASS
4801 20:15:16.682315 TX DQ/DQS : PASS
4802 20:15:16.682397 RX DATLAT : PASS
4803 20:15:16.685481 RX DQ/DQS(Engine): PASS
4804 20:15:16.689154 TX OE : NO K
4805 20:15:16.689238 All Pass.
4806 20:15:16.689324
4807 20:15:16.689422 CH 0, Rank 1
4808 20:15:16.692211 SW Impedance : PASS
4809 20:15:16.695534 DUTY Scan : NO K
4810 20:15:16.695618 ZQ Calibration : PASS
4811 20:15:16.698761 Jitter Meter : NO K
4812 20:15:16.698844 CBT Training : PASS
4813 20:15:16.702254 Write leveling : PASS
4814 20:15:16.705460 RX DQS gating : PASS
4815 20:15:16.705543 RX DQ/DQS(RDDQC) : PASS
4816 20:15:16.708578 TX DQ/DQS : PASS
4817 20:15:16.712142 RX DATLAT : PASS
4818 20:15:16.712225 RX DQ/DQS(Engine): PASS
4819 20:15:16.715695 TX OE : NO K
4820 20:15:16.715778 All Pass.
4821 20:15:16.715862
4822 20:15:16.718945 CH 1, Rank 0
4823 20:15:16.719028 SW Impedance : PASS
4824 20:15:16.721886 DUTY Scan : NO K
4825 20:15:16.725258 ZQ Calibration : PASS
4826 20:15:16.725342 Jitter Meter : NO K
4827 20:15:16.728639 CBT Training : PASS
4828 20:15:16.731924 Write leveling : PASS
4829 20:15:16.732012 RX DQS gating : PASS
4830 20:15:16.735407 RX DQ/DQS(RDDQC) : PASS
4831 20:15:16.738761 TX DQ/DQS : PASS
4832 20:15:16.738845 RX DATLAT : PASS
4833 20:15:16.741839 RX DQ/DQS(Engine): PASS
4834 20:15:16.741968 TX OE : NO K
4835 20:15:16.745561 All Pass.
4836 20:15:16.745644
4837 20:15:16.745727 CH 1, Rank 1
4838 20:15:16.749121 SW Impedance : PASS
4839 20:15:16.749205 DUTY Scan : NO K
4840 20:15:16.752281 ZQ Calibration : PASS
4841 20:15:16.755475 Jitter Meter : NO K
4842 20:15:16.755558 CBT Training : PASS
4843 20:15:16.758758 Write leveling : PASS
4844 20:15:16.762203 RX DQS gating : PASS
4845 20:15:16.762286 RX DQ/DQS(RDDQC) : PASS
4846 20:15:16.765273 TX DQ/DQS : PASS
4847 20:15:16.768972 RX DATLAT : PASS
4848 20:15:16.769056 RX DQ/DQS(Engine): PASS
4849 20:15:16.772494 TX OE : NO K
4850 20:15:16.772578 All Pass.
4851 20:15:16.772661
4852 20:15:16.775333 DramC Write-DBI off
4853 20:15:16.778853 PER_BANK_REFRESH: Hybrid Mode
4854 20:15:16.778936 TX_TRACKING: ON
4855 20:15:16.788949 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 20:15:16.792178 [FAST_K] Save calibration result to emmc
4857 20:15:16.795158 dramc_set_vcore_voltage set vcore to 662500
4858 20:15:16.798848 Read voltage for 933, 3
4859 20:15:16.798930 Vio18 = 0
4860 20:15:16.798995 Vcore = 662500
4861 20:15:16.802228 Vdram = 0
4862 20:15:16.802309 Vddq = 0
4863 20:15:16.802374 Vmddr = 0
4864 20:15:16.808815 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 20:15:16.811848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 20:15:16.815320 MEM_TYPE=3, freq_sel=17
4867 20:15:16.818506 sv_algorithm_assistance_LP4_1600
4868 20:15:16.822123 ============ PULL DRAM RESETB DOWN ============
4869 20:15:16.825181 ========== PULL DRAM RESETB DOWN end =========
4870 20:15:16.831513 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 20:15:16.834953 ===================================
4872 20:15:16.835035 LPDDR4 DRAM CONFIGURATION
4873 20:15:16.838579 ===================================
4874 20:15:16.841718 EX_ROW_EN[0] = 0x0
4875 20:15:16.845014 EX_ROW_EN[1] = 0x0
4876 20:15:16.845095 LP4Y_EN = 0x0
4877 20:15:16.848558 WORK_FSP = 0x0
4878 20:15:16.848640 WL = 0x3
4879 20:15:16.851630 RL = 0x3
4880 20:15:16.851763 BL = 0x2
4881 20:15:16.854784 RPST = 0x0
4882 20:15:16.854867 RD_PRE = 0x0
4883 20:15:16.858078 WR_PRE = 0x1
4884 20:15:16.858161 WR_PST = 0x0
4885 20:15:16.861610 DBI_WR = 0x0
4886 20:15:16.861693 DBI_RD = 0x0
4887 20:15:16.864770 OTF = 0x1
4888 20:15:16.868040 ===================================
4889 20:15:16.871398 ===================================
4890 20:15:16.871481 ANA top config
4891 20:15:16.874716 ===================================
4892 20:15:16.878118 DLL_ASYNC_EN = 0
4893 20:15:16.881249 ALL_SLAVE_EN = 1
4894 20:15:16.884774 NEW_RANK_MODE = 1
4895 20:15:16.884859 DLL_IDLE_MODE = 1
4896 20:15:16.888184 LP45_APHY_COMB_EN = 1
4897 20:15:16.891214 TX_ODT_DIS = 1
4898 20:15:16.894708 NEW_8X_MODE = 1
4899 20:15:16.897798 ===================================
4900 20:15:16.901207 ===================================
4901 20:15:16.904794 data_rate = 1866
4902 20:15:16.904877 CKR = 1
4903 20:15:16.907749 DQ_P2S_RATIO = 8
4904 20:15:16.911221 ===================================
4905 20:15:16.914671 CA_P2S_RATIO = 8
4906 20:15:16.917730 DQ_CA_OPEN = 0
4907 20:15:16.920876 DQ_SEMI_OPEN = 0
4908 20:15:16.924532 CA_SEMI_OPEN = 0
4909 20:15:16.924615 CA_FULL_RATE = 0
4910 20:15:16.927924 DQ_CKDIV4_EN = 1
4911 20:15:16.931134 CA_CKDIV4_EN = 1
4912 20:15:16.934379 CA_PREDIV_EN = 0
4913 20:15:16.937733 PH8_DLY = 0
4914 20:15:16.941277 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 20:15:16.941360 DQ_AAMCK_DIV = 4
4916 20:15:16.944551 CA_AAMCK_DIV = 4
4917 20:15:16.947805 CA_ADMCK_DIV = 4
4918 20:15:16.951003 DQ_TRACK_CA_EN = 0
4919 20:15:16.954195 CA_PICK = 933
4920 20:15:16.957778 CA_MCKIO = 933
4921 20:15:16.961146 MCKIO_SEMI = 0
4922 20:15:16.961244 PLL_FREQ = 3732
4923 20:15:16.964217 DQ_UI_PI_RATIO = 32
4924 20:15:16.967306 CA_UI_PI_RATIO = 0
4925 20:15:16.971111 ===================================
4926 20:15:16.974284 ===================================
4927 20:15:16.977580 memory_type:LPDDR4
4928 20:15:16.977664 GP_NUM : 10
4929 20:15:16.980941 SRAM_EN : 1
4930 20:15:16.984128 MD32_EN : 0
4931 20:15:16.987297 ===================================
4932 20:15:16.987380 [ANA_INIT] >>>>>>>>>>>>>>
4933 20:15:16.990712 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 20:15:16.994007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 20:15:16.997356 ===================================
4936 20:15:17.000783 data_rate = 1866,PCW = 0X8f00
4937 20:15:17.003966 ===================================
4938 20:15:17.007388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 20:15:17.013770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 20:15:17.017432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 20:15:17.023955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 20:15:17.027044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 20:15:17.030571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 20:15:17.033705 [ANA_INIT] flow start
4945 20:15:17.033797 [ANA_INIT] PLL >>>>>>>>
4946 20:15:17.036892 [ANA_INIT] PLL <<<<<<<<
4947 20:15:17.040416 [ANA_INIT] MIDPI >>>>>>>>
4948 20:15:17.040489 [ANA_INIT] MIDPI <<<<<<<<
4949 20:15:17.043617 [ANA_INIT] DLL >>>>>>>>
4950 20:15:17.046944 [ANA_INIT] flow end
4951 20:15:17.050238 ============ LP4 DIFF to SE enter ============
4952 20:15:17.053655 ============ LP4 DIFF to SE exit ============
4953 20:15:17.056825 [ANA_INIT] <<<<<<<<<<<<<
4954 20:15:17.060519 [Flow] Enable top DCM control >>>>>
4955 20:15:17.063690 [Flow] Enable top DCM control <<<<<
4956 20:15:17.067039 Enable DLL master slave shuffle
4957 20:15:17.070170 ==============================================================
4958 20:15:17.073879 Gating Mode config
4959 20:15:17.080284 ==============================================================
4960 20:15:17.080364 Config description:
4961 20:15:17.090111 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 20:15:17.096657 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 20:15:17.099889 SELPH_MODE 0: By rank 1: By Phase
4964 20:15:17.106858 ==============================================================
4965 20:15:17.109882 GAT_TRACK_EN = 1
4966 20:15:17.113146 RX_GATING_MODE = 2
4967 20:15:17.116872 RX_GATING_TRACK_MODE = 2
4968 20:15:17.119608 SELPH_MODE = 1
4969 20:15:17.123196 PICG_EARLY_EN = 1
4970 20:15:17.126381 VALID_LAT_VALUE = 1
4971 20:15:17.130114 ==============================================================
4972 20:15:17.133253 Enter into Gating configuration >>>>
4973 20:15:17.136752 Exit from Gating configuration <<<<
4974 20:15:17.139789 Enter into DVFS_PRE_config >>>>>
4975 20:15:17.153085 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 20:15:17.153177 Exit from DVFS_PRE_config <<<<<
4977 20:15:17.156431 Enter into PICG configuration >>>>
4978 20:15:17.159874 Exit from PICG configuration <<<<
4979 20:15:17.162929 [RX_INPUT] configuration >>>>>
4980 20:15:17.166270 [RX_INPUT] configuration <<<<<
4981 20:15:17.173162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 20:15:17.176324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 20:15:17.182798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 20:15:17.189568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 20:15:17.196177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 20:15:17.202548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 20:15:17.206176 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 20:15:17.209384 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 20:15:17.212810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 20:15:17.219505 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 20:15:17.222562 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 20:15:17.225858 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 20:15:17.229139 ===================================
4994 20:15:17.232673 LPDDR4 DRAM CONFIGURATION
4995 20:15:17.235753 ===================================
4996 20:15:17.239252 EX_ROW_EN[0] = 0x0
4997 20:15:17.239325 EX_ROW_EN[1] = 0x0
4998 20:15:17.242571 LP4Y_EN = 0x0
4999 20:15:17.242642 WORK_FSP = 0x0
5000 20:15:17.245815 WL = 0x3
5001 20:15:17.245883 RL = 0x3
5002 20:15:17.248990 BL = 0x2
5003 20:15:17.249069 RPST = 0x0
5004 20:15:17.252587 RD_PRE = 0x0
5005 20:15:17.252674 WR_PRE = 0x1
5006 20:15:17.255859 WR_PST = 0x0
5007 20:15:17.255947 DBI_WR = 0x0
5008 20:15:17.259107 DBI_RD = 0x0
5009 20:15:17.259192 OTF = 0x1
5010 20:15:17.262445 ===================================
5011 20:15:17.269204 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 20:15:17.272324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 20:15:17.275819 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 20:15:17.278935 ===================================
5015 20:15:17.282358 LPDDR4 DRAM CONFIGURATION
5016 20:15:17.285819 ===================================
5017 20:15:17.285925 EX_ROW_EN[0] = 0x10
5018 20:15:17.289005 EX_ROW_EN[1] = 0x0
5019 20:15:17.292366 LP4Y_EN = 0x0
5020 20:15:17.292450 WORK_FSP = 0x0
5021 20:15:17.295606 WL = 0x3
5022 20:15:17.295688 RL = 0x3
5023 20:15:17.298832 BL = 0x2
5024 20:15:17.298903 RPST = 0x0
5025 20:15:17.302065 RD_PRE = 0x0
5026 20:15:17.302135 WR_PRE = 0x1
5027 20:15:17.305857 WR_PST = 0x0
5028 20:15:17.305928 DBI_WR = 0x0
5029 20:15:17.308801 DBI_RD = 0x0
5030 20:15:17.308872 OTF = 0x1
5031 20:15:17.312136 ===================================
5032 20:15:17.318937 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 20:15:17.323059 nWR fixed to 30
5034 20:15:17.326523 [ModeRegInit_LP4] CH0 RK0
5035 20:15:17.326597 [ModeRegInit_LP4] CH0 RK1
5036 20:15:17.329642 [ModeRegInit_LP4] CH1 RK0
5037 20:15:17.333217 [ModeRegInit_LP4] CH1 RK1
5038 20:15:17.333297 match AC timing 9
5039 20:15:17.339908 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 20:15:17.343351 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 20:15:17.346470 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 20:15:17.352959 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 20:15:17.356683 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 20:15:17.356765 ==
5045 20:15:17.359991 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 20:15:17.362986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 20:15:17.363069 ==
5048 20:15:17.369501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 20:15:17.376488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5050 20:15:17.379625 [CA 0] Center 38 (7~69) winsize 63
5051 20:15:17.383056 [CA 1] Center 38 (8~69) winsize 62
5052 20:15:17.386278 [CA 2] Center 35 (5~66) winsize 62
5053 20:15:17.389767 [CA 3] Center 35 (5~66) winsize 62
5054 20:15:17.392924 [CA 4] Center 34 (4~65) winsize 62
5055 20:15:17.396074 [CA 5] Center 33 (3~64) winsize 62
5056 20:15:17.396164
5057 20:15:17.399559 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5058 20:15:17.399633
5059 20:15:17.403075 [CATrainingPosCal] consider 1 rank data
5060 20:15:17.406329 u2DelayCellTimex100 = 270/100 ps
5061 20:15:17.409504 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5062 20:15:17.413041 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5063 20:15:17.416451 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5064 20:15:17.419581 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5065 20:15:17.422705 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5066 20:15:17.429433 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5067 20:15:17.429511
5068 20:15:17.432943 CA PerBit enable=1, Macro0, CA PI delay=33
5069 20:15:17.433022
5070 20:15:17.435986 [CBTSetCACLKResult] CA Dly = 33
5071 20:15:17.436064 CS Dly: 7 (0~38)
5072 20:15:17.436135 ==
5073 20:15:17.439600 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 20:15:17.442750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 20:15:17.445664 ==
5076 20:15:17.449319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 20:15:17.455850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5078 20:15:17.459114 [CA 0] Center 38 (8~69) winsize 62
5079 20:15:17.462425 [CA 1] Center 38 (8~69) winsize 62
5080 20:15:17.465903 [CA 2] Center 36 (6~66) winsize 61
5081 20:15:17.468998 [CA 3] Center 35 (5~66) winsize 62
5082 20:15:17.472305 [CA 4] Center 34 (4~65) winsize 62
5083 20:15:17.475941 [CA 5] Center 34 (4~65) winsize 62
5084 20:15:17.476014
5085 20:15:17.479056 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5086 20:15:17.479134
5087 20:15:17.482141 [CATrainingPosCal] consider 2 rank data
5088 20:15:17.485852 u2DelayCellTimex100 = 270/100 ps
5089 20:15:17.489176 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 20:15:17.492486 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5091 20:15:17.495802 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5092 20:15:17.498855 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5093 20:15:17.505595 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5094 20:15:17.509084 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5095 20:15:17.509165
5096 20:15:17.512293 CA PerBit enable=1, Macro0, CA PI delay=34
5097 20:15:17.512375
5098 20:15:17.515481 [CBTSetCACLKResult] CA Dly = 34
5099 20:15:17.515563 CS Dly: 8 (0~40)
5100 20:15:17.515627
5101 20:15:17.519014 ----->DramcWriteLeveling(PI) begin...
5102 20:15:17.519096 ==
5103 20:15:17.522178 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 20:15:17.529013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 20:15:17.529156 ==
5106 20:15:17.532384 Write leveling (Byte 0): 34 => 34
5107 20:15:17.535689 Write leveling (Byte 1): 28 => 28
5108 20:15:17.535770 DramcWriteLeveling(PI) end<-----
5109 20:15:17.535834
5110 20:15:17.538926 ==
5111 20:15:17.542190 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 20:15:17.545442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 20:15:17.545511 ==
5114 20:15:17.549080 [Gating] SW mode calibration
5115 20:15:17.555475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 20:15:17.558871 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 20:15:17.565187 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5118 20:15:17.568795 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 20:15:17.572231 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 20:15:17.578578 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 20:15:17.582105 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 20:15:17.585102 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5123 20:15:17.592019 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5124 20:15:17.595258 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5125 20:15:17.598702 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5126 20:15:17.605137 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 20:15:17.608605 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 20:15:17.611716 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 20:15:17.618594 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 20:15:17.621825 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 20:15:17.625463 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
5132 20:15:17.628880 0 15 28 | B1->B0 | 2929 4444 | 1 0 | (0 0) (0 0)
5133 20:15:17.635183 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5134 20:15:17.638620 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 20:15:17.641812 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 20:15:17.648701 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 20:15:17.651933 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 20:15:17.655448 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 20:15:17.662197 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5140 20:15:17.665144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 20:15:17.668787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 20:15:17.675414 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 20:15:17.678390 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 20:15:17.681813 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 20:15:17.688471 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 20:15:17.691567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 20:15:17.695239 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 20:15:17.701790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 20:15:17.704969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 20:15:17.708124 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 20:15:17.714826 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 20:15:17.718091 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 20:15:17.721669 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 20:15:17.728424 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 20:15:17.731442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5156 20:15:17.735147 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5157 20:15:17.738460 Total UI for P1: 0, mck2ui 16
5158 20:15:17.741564 best dqsien dly found for B0: ( 1, 2, 24)
5159 20:15:17.748135 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 20:15:17.748218 Total UI for P1: 0, mck2ui 16
5161 20:15:17.751632 best dqsien dly found for B1: ( 1, 2, 28)
5162 20:15:17.758227 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5163 20:15:17.761290 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5164 20:15:17.761373
5165 20:15:17.764732 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5166 20:15:17.768482 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5167 20:15:17.771483 [Gating] SW calibration Done
5168 20:15:17.771565 ==
5169 20:15:17.774853 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 20:15:17.778115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 20:15:17.778198 ==
5172 20:15:17.781165 RX Vref Scan: 0
5173 20:15:17.781247
5174 20:15:17.781312 RX Vref 0 -> 0, step: 1
5175 20:15:17.781372
5176 20:15:17.784696 RX Delay -80 -> 252, step: 8
5177 20:15:17.787887 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5178 20:15:17.794648 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5179 20:15:17.797729 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5180 20:15:17.801243 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5181 20:15:17.804746 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5182 20:15:17.807843 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5183 20:15:17.814524 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5184 20:15:17.817889 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5185 20:15:17.821425 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5186 20:15:17.824611 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5187 20:15:17.827586 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5188 20:15:17.831154 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5189 20:15:17.837710 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5190 20:15:17.841288 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5191 20:15:17.844227 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5192 20:15:17.847512 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5193 20:15:17.847595 ==
5194 20:15:17.850914 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 20:15:17.857519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 20:15:17.857603 ==
5197 20:15:17.857669 DQS Delay:
5198 20:15:17.857731 DQS0 = 0, DQS1 = 0
5199 20:15:17.861036 DQM Delay:
5200 20:15:17.861118 DQM0 = 107, DQM1 = 91
5201 20:15:17.864349 DQ Delay:
5202 20:15:17.867673 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5203 20:15:17.871143 DQ4 =107, DQ5 =103, DQ6 =115, DQ7 =115
5204 20:15:17.874581 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5205 20:15:17.877468 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =103
5206 20:15:17.877550
5207 20:15:17.877615
5208 20:15:17.877675 ==
5209 20:15:17.880946 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 20:15:17.884476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 20:15:17.884562 ==
5212 20:15:17.884627
5213 20:15:17.884687
5214 20:15:17.887721 TX Vref Scan disable
5215 20:15:17.890911 == TX Byte 0 ==
5216 20:15:17.894573 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5217 20:15:17.897774 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5218 20:15:17.900963 == TX Byte 1 ==
5219 20:15:17.904095 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5220 20:15:17.907747 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5221 20:15:17.907830 ==
5222 20:15:17.911080 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 20:15:17.914519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 20:15:17.917642 ==
5225 20:15:17.917724
5226 20:15:17.917789
5227 20:15:17.917851 TX Vref Scan disable
5228 20:15:17.921347 == TX Byte 0 ==
5229 20:15:17.924259 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5230 20:15:17.931112 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5231 20:15:17.931194 == TX Byte 1 ==
5232 20:15:17.934574 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5233 20:15:17.937849 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5234 20:15:17.941220
5235 20:15:17.941302 [DATLAT]
5236 20:15:17.941368 Freq=933, CH0 RK0
5237 20:15:17.941430
5238 20:15:17.944369 DATLAT Default: 0xd
5239 20:15:17.944451 0, 0xFFFF, sum = 0
5240 20:15:17.947710 1, 0xFFFF, sum = 0
5241 20:15:17.947793 2, 0xFFFF, sum = 0
5242 20:15:17.951353 3, 0xFFFF, sum = 0
5243 20:15:17.951436 4, 0xFFFF, sum = 0
5244 20:15:17.954754 5, 0xFFFF, sum = 0
5245 20:15:17.958079 6, 0xFFFF, sum = 0
5246 20:15:17.958162 7, 0xFFFF, sum = 0
5247 20:15:17.960995 8, 0xFFFF, sum = 0
5248 20:15:17.961078 9, 0xFFFF, sum = 0
5249 20:15:17.964898 10, 0x0, sum = 1
5250 20:15:17.964981 11, 0x0, sum = 2
5251 20:15:17.965048 12, 0x0, sum = 3
5252 20:15:17.967975 13, 0x0, sum = 4
5253 20:15:17.968058 best_step = 11
5254 20:15:17.968123
5255 20:15:17.971360 ==
5256 20:15:17.971442 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 20:15:17.977970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 20:15:17.978067 ==
5259 20:15:17.978133 RX Vref Scan: 1
5260 20:15:17.978193
5261 20:15:17.981155 RX Vref 0 -> 0, step: 1
5262 20:15:17.981237
5263 20:15:17.984251 RX Delay -53 -> 252, step: 4
5264 20:15:17.984333
5265 20:15:17.987797 Set Vref, RX VrefLevel [Byte0]: 58
5266 20:15:17.991251 [Byte1]: 48
5267 20:15:17.991396
5268 20:15:17.994374 Final RX Vref Byte 0 = 58 to rank0
5269 20:15:17.997684 Final RX Vref Byte 1 = 48 to rank0
5270 20:15:18.000795 Final RX Vref Byte 0 = 58 to rank1
5271 20:15:18.004454 Final RX Vref Byte 1 = 48 to rank1==
5272 20:15:18.007504 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 20:15:18.011176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 20:15:18.011259 ==
5275 20:15:18.014265 DQS Delay:
5276 20:15:18.014347 DQS0 = 0, DQS1 = 0
5277 20:15:18.017649 DQM Delay:
5278 20:15:18.017731 DQM0 = 107, DQM1 = 91
5279 20:15:18.017797 DQ Delay:
5280 20:15:18.024184 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5281 20:15:18.027414 DQ4 =110, DQ5 =98, DQ6 =118, DQ7 =114
5282 20:15:18.030873 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =90
5283 20:15:18.034435 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =100
5284 20:15:18.034518
5285 20:15:18.034584
5286 20:15:18.040540 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5287 20:15:18.044270 CH0 RK0: MR19=505, MR18=2420
5288 20:15:18.050741 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5289 20:15:18.050826
5290 20:15:18.054236 ----->DramcWriteLeveling(PI) begin...
5291 20:15:18.054321 ==
5292 20:15:18.057772 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 20:15:18.060862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 20:15:18.060944 ==
5295 20:15:18.064136 Write leveling (Byte 0): 32 => 32
5296 20:15:18.067453 Write leveling (Byte 1): 29 => 29
5297 20:15:18.070803 DramcWriteLeveling(PI) end<-----
5298 20:15:18.070884
5299 20:15:18.070948 ==
5300 20:15:18.073911 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 20:15:18.077410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 20:15:18.077494 ==
5303 20:15:18.080866 [Gating] SW mode calibration
5304 20:15:18.087386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 20:15:18.093946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 20:15:18.097490 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 20:15:18.100560 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 20:15:18.107405 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 20:15:18.110998 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 20:15:18.113993 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 20:15:18.120648 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 20:15:18.124095 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (0 0) (0 1)
5313 20:15:18.127222 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 1) (1 0)
5314 20:15:18.134073 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 20:15:18.137219 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 20:15:18.140441 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 20:15:18.147081 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 20:15:18.150305 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 20:15:18.153553 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 20:15:18.160371 0 15 24 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
5321 20:15:18.163675 0 15 28 | B1->B0 | 3838 4242 | 0 0 | (1 1) (0 0)
5322 20:15:18.167228 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 20:15:18.173735 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 20:15:18.177137 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 20:15:18.180267 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 20:15:18.186979 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 20:15:18.190121 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 20:15:18.193816 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5329 20:15:18.200407 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5330 20:15:18.203642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 20:15:18.206928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 20:15:18.213651 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 20:15:18.216651 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 20:15:18.219951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 20:15:18.226804 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 20:15:18.230273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 20:15:18.233312 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 20:15:18.240340 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 20:15:18.243161 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 20:15:18.246653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 20:15:18.253158 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 20:15:18.256882 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 20:15:18.259902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 20:15:18.263244 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 20:15:18.270121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5346 20:15:18.273355 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 20:15:18.276656 Total UI for P1: 0, mck2ui 16
5348 20:15:18.280011 best dqsien dly found for B0: ( 1, 2, 28)
5349 20:15:18.283460 Total UI for P1: 0, mck2ui 16
5350 20:15:18.286807 best dqsien dly found for B1: ( 1, 2, 28)
5351 20:15:18.290259 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5352 20:15:18.293735 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5353 20:15:18.293814
5354 20:15:18.296689 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5355 20:15:18.300400 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5356 20:15:18.303219 [Gating] SW calibration Done
5357 20:15:18.303298 ==
5358 20:15:18.306813 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 20:15:18.312962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 20:15:18.313044 ==
5361 20:15:18.313109 RX Vref Scan: 0
5362 20:15:18.313170
5363 20:15:18.316393 RX Vref 0 -> 0, step: 1
5364 20:15:18.316474
5365 20:15:18.319892 RX Delay -80 -> 252, step: 8
5366 20:15:18.323368 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5367 20:15:18.326415 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5368 20:15:18.329595 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5369 20:15:18.333162 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5370 20:15:18.339668 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5371 20:15:18.342988 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5372 20:15:18.346286 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5373 20:15:18.349776 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5374 20:15:18.353260 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5375 20:15:18.356353 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5376 20:15:18.363047 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5377 20:15:18.366348 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5378 20:15:18.369727 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5379 20:15:18.372767 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5380 20:15:18.376371 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5381 20:15:18.379779 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5382 20:15:18.379860 ==
5383 20:15:18.383105 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 20:15:18.389619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 20:15:18.389701 ==
5386 20:15:18.389766 DQS Delay:
5387 20:15:18.393238 DQS0 = 0, DQS1 = 0
5388 20:15:18.393320 DQM Delay:
5389 20:15:18.396728 DQM0 = 104, DQM1 = 90
5390 20:15:18.396810 DQ Delay:
5391 20:15:18.399720 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5392 20:15:18.403223 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5393 20:15:18.406440 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5394 20:15:18.409661 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5395 20:15:18.409742
5396 20:15:18.409806
5397 20:15:18.409866 ==
5398 20:15:18.412767 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 20:15:18.416152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 20:15:18.416234 ==
5401 20:15:18.416299
5402 20:15:18.416357
5403 20:15:18.419373 TX Vref Scan disable
5404 20:15:18.422906 == TX Byte 0 ==
5405 20:15:18.426115 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5406 20:15:18.429288 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5407 20:15:18.432901 == TX Byte 1 ==
5408 20:15:18.436190 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5409 20:15:18.439309 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5410 20:15:18.439390 ==
5411 20:15:18.442874 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 20:15:18.449172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 20:15:18.449267 ==
5414 20:15:18.449368
5415 20:15:18.449459
5416 20:15:18.449547 TX Vref Scan disable
5417 20:15:18.453164 == TX Byte 0 ==
5418 20:15:18.456668 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5419 20:15:18.463416 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5420 20:15:18.463497 == TX Byte 1 ==
5421 20:15:18.466449 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5422 20:15:18.473415 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5423 20:15:18.473499
5424 20:15:18.473563 [DATLAT]
5425 20:15:18.473622 Freq=933, CH0 RK1
5426 20:15:18.473681
5427 20:15:18.476669 DATLAT Default: 0xb
5428 20:15:18.476774 0, 0xFFFF, sum = 0
5429 20:15:18.480024 1, 0xFFFF, sum = 0
5430 20:15:18.480107 2, 0xFFFF, sum = 0
5431 20:15:18.483034 3, 0xFFFF, sum = 0
5432 20:15:18.486773 4, 0xFFFF, sum = 0
5433 20:15:18.486856 5, 0xFFFF, sum = 0
5434 20:15:18.490310 6, 0xFFFF, sum = 0
5435 20:15:18.490392 7, 0xFFFF, sum = 0
5436 20:15:18.493247 8, 0xFFFF, sum = 0
5437 20:15:18.493329 9, 0xFFFF, sum = 0
5438 20:15:18.496827 10, 0x0, sum = 1
5439 20:15:18.496909 11, 0x0, sum = 2
5440 20:15:18.496975 12, 0x0, sum = 3
5441 20:15:18.500016 13, 0x0, sum = 4
5442 20:15:18.500099 best_step = 11
5443 20:15:18.500163
5444 20:15:18.503055 ==
5445 20:15:18.503136 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 20:15:18.509612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 20:15:18.509720 ==
5448 20:15:18.509813 RX Vref Scan: 0
5449 20:15:18.509905
5450 20:15:18.512949 RX Vref 0 -> 0, step: 1
5451 20:15:18.513029
5452 20:15:18.516427 RX Delay -53 -> 252, step: 4
5453 20:15:18.520018 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5454 20:15:18.526205 iDelay=199, Bit 1, Center 104 (15 ~ 194) 180
5455 20:15:18.529414 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5456 20:15:18.533028 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5457 20:15:18.536135 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5458 20:15:18.539811 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5459 20:15:18.546392 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5460 20:15:18.549810 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5461 20:15:18.552911 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5462 20:15:18.556139 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5463 20:15:18.559836 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5464 20:15:18.562895 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5465 20:15:18.569276 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5466 20:15:18.572741 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5467 20:15:18.576172 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5468 20:15:18.579331 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5469 20:15:18.579412 ==
5470 20:15:18.582782 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 20:15:18.589347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 20:15:18.589429 ==
5473 20:15:18.589494 DQS Delay:
5474 20:15:18.589553 DQS0 = 0, DQS1 = 0
5475 20:15:18.592725 DQM Delay:
5476 20:15:18.592805 DQM0 = 103, DQM1 = 91
5477 20:15:18.596053 DQ Delay:
5478 20:15:18.599746 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =98
5479 20:15:18.602711 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5480 20:15:18.605946 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =90
5481 20:15:18.609715 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5482 20:15:18.609796
5483 20:15:18.609860
5484 20:15:18.615905 [DQSOSCAuto] RK1, (LSB)MR18= 0x2506, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5485 20:15:18.619310 CH0 RK1: MR19=505, MR18=2506
5486 20:15:18.625936 CH0_RK1: MR19=0x505, MR18=0x2506, DQSOSC=410, MR23=63, INC=64, DEC=42
5487 20:15:18.629338 [RxdqsGatingPostProcess] freq 933
5488 20:15:18.632833 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 20:15:18.636205 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 20:15:18.639339 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 20:15:18.642350 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 20:15:18.646078 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 20:15:18.648981 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 20:15:18.652647 best DQS1 dly(2T, 0.5T) = (0, 10)
5495 20:15:18.655817 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 20:15:18.659027 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5497 20:15:18.662550 Pre-setting of DQS Precalculation
5498 20:15:18.665914 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 20:15:18.669191 ==
5500 20:15:18.669272 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 20:15:18.675571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 20:15:18.675652 ==
5503 20:15:18.679136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 20:15:18.685767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5505 20:15:18.689305 [CA 0] Center 37 (7~68) winsize 62
5506 20:15:18.692396 [CA 1] Center 37 (7~68) winsize 62
5507 20:15:18.695789 [CA 2] Center 35 (5~66) winsize 62
5508 20:15:18.699261 [CA 3] Center 34 (4~65) winsize 62
5509 20:15:18.702323 [CA 4] Center 35 (5~66) winsize 62
5510 20:15:18.705825 [CA 5] Center 34 (4~65) winsize 62
5511 20:15:18.705906
5512 20:15:18.708923 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5513 20:15:18.709010
5514 20:15:18.712451 [CATrainingPosCal] consider 1 rank data
5515 20:15:18.715775 u2DelayCellTimex100 = 270/100 ps
5516 20:15:18.718798 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5517 20:15:18.725353 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5518 20:15:18.728885 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5519 20:15:18.732464 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5520 20:15:18.735328 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5521 20:15:18.738710 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5522 20:15:18.738793
5523 20:15:18.742310 CA PerBit enable=1, Macro0, CA PI delay=34
5524 20:15:18.742393
5525 20:15:18.745601 [CBTSetCACLKResult] CA Dly = 34
5526 20:15:18.745683 CS Dly: 7 (0~38)
5527 20:15:18.749151 ==
5528 20:15:18.749234 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 20:15:18.755604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 20:15:18.755712 ==
5531 20:15:18.758858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 20:15:18.765504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5533 20:15:18.769384 [CA 0] Center 38 (8~69) winsize 62
5534 20:15:18.772699 [CA 1] Center 38 (7~69) winsize 63
5535 20:15:18.775877 [CA 2] Center 35 (5~66) winsize 62
5536 20:15:18.779279 [CA 3] Center 35 (5~65) winsize 61
5537 20:15:18.783008 [CA 4] Center 35 (5~66) winsize 62
5538 20:15:18.785830 [CA 5] Center 35 (5~65) winsize 61
5539 20:15:18.785984
5540 20:15:18.789139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5541 20:15:18.789268
5542 20:15:18.792608 [CATrainingPosCal] consider 2 rank data
5543 20:15:18.795883 u2DelayCellTimex100 = 270/100 ps
5544 20:15:18.799140 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5545 20:15:18.802720 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5546 20:15:18.809601 CA2 delay=35 (5~66),Diff = 0 PI (0 cell)
5547 20:15:18.812753 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5548 20:15:18.815948 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5549 20:15:18.819834 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5550 20:15:18.820133
5551 20:15:18.822655 CA PerBit enable=1, Macro0, CA PI delay=35
5552 20:15:18.822954
5553 20:15:18.826149 [CBTSetCACLKResult] CA Dly = 35
5554 20:15:18.826534 CS Dly: 7 (0~39)
5555 20:15:18.826842
5556 20:15:18.829514 ----->DramcWriteLeveling(PI) begin...
5557 20:15:18.832790 ==
5558 20:15:18.836324 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 20:15:18.839479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 20:15:18.839946 ==
5561 20:15:18.842534 Write leveling (Byte 0): 26 => 26
5562 20:15:18.846321 Write leveling (Byte 1): 29 => 29
5563 20:15:18.849363 DramcWriteLeveling(PI) end<-----
5564 20:15:18.849994
5565 20:15:18.850380 ==
5566 20:15:18.852840 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 20:15:18.856412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 20:15:18.857052 ==
5569 20:15:18.859414 [Gating] SW mode calibration
5570 20:15:18.866083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 20:15:18.869471 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 20:15:18.876124 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 20:15:18.879340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 20:15:18.882447 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 20:15:18.889427 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 20:15:18.892653 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 20:15:18.896057 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5578 20:15:18.902725 0 14 24 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 0)
5579 20:15:18.905980 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 20:15:18.909369 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 20:15:18.916408 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 20:15:18.919305 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 20:15:18.922421 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 20:15:18.929415 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 20:15:18.932225 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 20:15:18.935716 0 15 24 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
5587 20:15:18.942789 0 15 28 | B1->B0 | 3b3b 4141 | 0 1 | (1 1) (1 1)
5588 20:15:18.946043 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 20:15:18.948870 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 20:15:18.955437 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 20:15:18.958942 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 20:15:18.962319 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 20:15:18.969101 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 20:15:18.972227 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 20:15:18.975858 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 20:15:18.982733 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 20:15:18.985485 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 20:15:18.989366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 20:15:18.995800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 20:15:18.999171 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 20:15:19.002379 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 20:15:19.008720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 20:15:19.012203 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 20:15:19.015526 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 20:15:19.021970 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 20:15:19.025382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 20:15:19.028524 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 20:15:19.031978 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 20:15:19.038550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5610 20:15:19.041830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 20:15:19.045356 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 20:15:19.048524 Total UI for P1: 0, mck2ui 16
5613 20:15:19.051730 best dqsien dly found for B0: ( 1, 2, 22)
5614 20:15:19.055645 Total UI for P1: 0, mck2ui 16
5615 20:15:19.058534 best dqsien dly found for B1: ( 1, 2, 24)
5616 20:15:19.061988 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5617 20:15:19.065206 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5618 20:15:19.068647
5619 20:15:19.071854 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5620 20:15:19.075267 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 20:15:19.078479 [Gating] SW calibration Done
5622 20:15:19.078958 ==
5623 20:15:19.081695 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 20:15:19.084907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 20:15:19.085372 ==
5626 20:15:19.085865 RX Vref Scan: 0
5627 20:15:19.086277
5628 20:15:19.088394 RX Vref 0 -> 0, step: 1
5629 20:15:19.088855
5630 20:15:19.091710 RX Delay -80 -> 252, step: 8
5631 20:15:19.095183 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5632 20:15:19.098671 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5633 20:15:19.105055 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5634 20:15:19.108324 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5635 20:15:19.111580 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5636 20:15:19.114942 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5637 20:15:19.118443 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5638 20:15:19.122005 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5639 20:15:19.128637 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5640 20:15:19.131652 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5641 20:15:19.135125 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5642 20:15:19.138711 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5643 20:15:19.142082 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5644 20:15:19.145315 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5645 20:15:19.152037 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5646 20:15:19.155113 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5647 20:15:19.155585 ==
5648 20:15:19.158388 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 20:15:19.162022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 20:15:19.162582 ==
5651 20:15:19.162962 DQS Delay:
5652 20:15:19.165038 DQS0 = 0, DQS1 = 0
5653 20:15:19.165500 DQM Delay:
5654 20:15:19.168755 DQM0 = 102, DQM1 = 95
5655 20:15:19.169314 DQ Delay:
5656 20:15:19.171533 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5657 20:15:19.174701 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5658 20:15:19.178485 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5659 20:15:19.181430 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5660 20:15:19.181909
5661 20:15:19.182326
5662 20:15:19.182676 ==
5663 20:15:19.184722 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 20:15:19.191735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 20:15:19.192326 ==
5666 20:15:19.192708
5667 20:15:19.193296
5668 20:15:19.193692 TX Vref Scan disable
5669 20:15:19.194719 == TX Byte 0 ==
5670 20:15:19.198244 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5671 20:15:19.204748 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5672 20:15:19.205294 == TX Byte 1 ==
5673 20:15:19.208075 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 20:15:19.214455 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 20:15:19.215079 ==
5676 20:15:19.217868 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 20:15:19.221517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 20:15:19.222022 ==
5679 20:15:19.222433
5680 20:15:19.222781
5681 20:15:19.224721 TX Vref Scan disable
5682 20:15:19.225204 == TX Byte 0 ==
5683 20:15:19.231410 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 20:15:19.234541 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 20:15:19.235005 == TX Byte 1 ==
5686 20:15:19.241604 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 20:15:19.244897 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 20:15:19.245362
5689 20:15:19.245729 [DATLAT]
5690 20:15:19.248122 Freq=933, CH1 RK0
5691 20:15:19.248584
5692 20:15:19.248955 DATLAT Default: 0xd
5693 20:15:19.251015 0, 0xFFFF, sum = 0
5694 20:15:19.251489 1, 0xFFFF, sum = 0
5695 20:15:19.254776 2, 0xFFFF, sum = 0
5696 20:15:19.255247 3, 0xFFFF, sum = 0
5697 20:15:19.257736 4, 0xFFFF, sum = 0
5698 20:15:19.261082 5, 0xFFFF, sum = 0
5699 20:15:19.261556 6, 0xFFFF, sum = 0
5700 20:15:19.264842 7, 0xFFFF, sum = 0
5701 20:15:19.265315 8, 0xFFFF, sum = 0
5702 20:15:19.267719 9, 0xFFFF, sum = 0
5703 20:15:19.268194 10, 0x0, sum = 1
5704 20:15:19.271335 11, 0x0, sum = 2
5705 20:15:19.271811 12, 0x0, sum = 3
5706 20:15:19.272188 13, 0x0, sum = 4
5707 20:15:19.274396 best_step = 11
5708 20:15:19.274821
5709 20:15:19.275158 ==
5710 20:15:19.277908 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 20:15:19.281112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 20:15:19.281590 ==
5713 20:15:19.284193 RX Vref Scan: 1
5714 20:15:19.284615
5715 20:15:19.284960 RX Vref 0 -> 0, step: 1
5716 20:15:19.287648
5717 20:15:19.288070 RX Delay -53 -> 252, step: 4
5718 20:15:19.288410
5719 20:15:19.291293 Set Vref, RX VrefLevel [Byte0]: 51
5720 20:15:19.294234 [Byte1]: 52
5721 20:15:19.299105
5722 20:15:19.299525 Final RX Vref Byte 0 = 51 to rank0
5723 20:15:19.302154 Final RX Vref Byte 1 = 52 to rank0
5724 20:15:19.305101 Final RX Vref Byte 0 = 51 to rank1
5725 20:15:19.308553 Final RX Vref Byte 1 = 52 to rank1==
5726 20:15:19.311514 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 20:15:19.318354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 20:15:19.318774 ==
5729 20:15:19.319107 DQS Delay:
5730 20:15:19.321740 DQS0 = 0, DQS1 = 0
5731 20:15:19.322180 DQM Delay:
5732 20:15:19.322513 DQM0 = 104, DQM1 = 96
5733 20:15:19.325237 DQ Delay:
5734 20:15:19.328157 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =104
5735 20:15:19.331424 DQ4 =104, DQ5 =110, DQ6 =114, DQ7 =100
5736 20:15:19.334966 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =92
5737 20:15:19.338151 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =102
5738 20:15:19.338568
5739 20:15:19.338897
5740 20:15:19.348369 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5741 20:15:19.348920 CH1 RK0: MR19=505, MR18=1932
5742 20:15:19.354703 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5743 20:15:19.355261
5744 20:15:19.358009 ----->DramcWriteLeveling(PI) begin...
5745 20:15:19.358481 ==
5746 20:15:19.361627 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 20:15:19.368136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 20:15:19.368605 ==
5749 20:15:19.371603 Write leveling (Byte 0): 25 => 25
5750 20:15:19.372068 Write leveling (Byte 1): 26 => 26
5751 20:15:19.374640 DramcWriteLeveling(PI) end<-----
5752 20:15:19.375059
5753 20:15:19.375392 ==
5754 20:15:19.378060 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 20:15:19.384719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 20:15:19.385139 ==
5757 20:15:19.387900 [Gating] SW mode calibration
5758 20:15:19.394806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 20:15:19.398027 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 20:15:19.404719 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5761 20:15:19.407745 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 20:15:19.411346 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 20:15:19.417740 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 20:15:19.421097 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 20:15:19.424664 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 20:15:19.431172 0 14 24 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
5767 20:15:19.434173 0 14 28 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
5768 20:15:19.437539 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 20:15:19.444200 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 20:15:19.447440 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 20:15:19.450773 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 20:15:19.457565 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 20:15:19.460739 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 20:15:19.464256 0 15 24 | B1->B0 | 2d2d 2424 | 1 0 | (0 0) (0 0)
5775 20:15:19.467686 0 15 28 | B1->B0 | 4545 3939 | 0 0 | (0 0) (0 0)
5776 20:15:19.473903 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 20:15:19.477392 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 20:15:19.480595 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 20:15:19.487319 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 20:15:19.490800 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 20:15:19.494376 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 20:15:19.500717 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5783 20:15:19.504175 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5784 20:15:19.507347 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 20:15:19.513916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 20:15:19.517172 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 20:15:19.520561 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 20:15:19.526861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 20:15:19.530256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 20:15:19.533445 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 20:15:19.540202 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 20:15:19.543547 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 20:15:19.546777 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 20:15:19.553537 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 20:15:19.556982 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 20:15:19.560535 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 20:15:19.566811 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5798 20:15:19.570532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5799 20:15:19.573548 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 20:15:19.577298 Total UI for P1: 0, mck2ui 16
5801 20:15:19.580110 best dqsien dly found for B0: ( 1, 2, 26)
5802 20:15:19.583575 Total UI for P1: 0, mck2ui 16
5803 20:15:19.587034 best dqsien dly found for B1: ( 1, 2, 22)
5804 20:15:19.589926 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5805 20:15:19.593439 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5806 20:15:19.593977
5807 20:15:19.596880 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5808 20:15:19.603671 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5809 20:15:19.604090 [Gating] SW calibration Done
5810 20:15:19.606715 ==
5811 20:15:19.607141 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 20:15:19.613291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 20:15:19.613708 ==
5814 20:15:19.614089 RX Vref Scan: 0
5815 20:15:19.614410
5816 20:15:19.616860 RX Vref 0 -> 0, step: 1
5817 20:15:19.617273
5818 20:15:19.620200 RX Delay -80 -> 252, step: 8
5819 20:15:19.623554 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5820 20:15:19.626779 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5821 20:15:19.630256 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5822 20:15:19.637204 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5823 20:15:19.640098 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5824 20:15:19.643050 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5825 20:15:19.646597 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5826 20:15:19.650039 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5827 20:15:19.653312 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5828 20:15:19.659878 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5829 20:15:19.663190 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5830 20:15:19.666362 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5831 20:15:19.669903 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5832 20:15:19.673160 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5833 20:15:19.676546 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5834 20:15:19.683309 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5835 20:15:19.683744 ==
5836 20:15:19.686373 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 20:15:19.690008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 20:15:19.690447 ==
5839 20:15:19.690878 DQS Delay:
5840 20:15:19.693193 DQS0 = 0, DQS1 = 0
5841 20:15:19.693622 DQM Delay:
5842 20:15:19.696516 DQM0 = 102, DQM1 = 96
5843 20:15:19.697043 DQ Delay:
5844 20:15:19.700058 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5845 20:15:19.703332 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5846 20:15:19.706479 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5847 20:15:19.709845 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5848 20:15:19.710308
5849 20:15:19.710687
5850 20:15:19.711109 ==
5851 20:15:19.712885 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 20:15:19.719937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 20:15:19.720374 ==
5854 20:15:19.720808
5855 20:15:19.721214
5856 20:15:19.721611 TX Vref Scan disable
5857 20:15:19.723556 == TX Byte 0 ==
5858 20:15:19.726822 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5859 20:15:19.733250 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5860 20:15:19.733689 == TX Byte 1 ==
5861 20:15:19.736174 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5862 20:15:19.742884 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5863 20:15:19.743328 ==
5864 20:15:19.746407 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 20:15:19.749635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 20:15:19.750099 ==
5867 20:15:19.750530
5868 20:15:19.750934
5869 20:15:19.753242 TX Vref Scan disable
5870 20:15:19.753673 == TX Byte 0 ==
5871 20:15:19.759640 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5872 20:15:19.763037 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5873 20:15:19.763459 == TX Byte 1 ==
5874 20:15:19.769810 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5875 20:15:19.772978 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5876 20:15:19.773482
5877 20:15:19.773972 [DATLAT]
5878 20:15:19.776261 Freq=933, CH1 RK1
5879 20:15:19.776683
5880 20:15:19.777019 DATLAT Default: 0xb
5881 20:15:19.779632 0, 0xFFFF, sum = 0
5882 20:15:19.780060 1, 0xFFFF, sum = 0
5883 20:15:19.782998 2, 0xFFFF, sum = 0
5884 20:15:19.783439 3, 0xFFFF, sum = 0
5885 20:15:19.786385 4, 0xFFFF, sum = 0
5886 20:15:19.786808 5, 0xFFFF, sum = 0
5887 20:15:19.789581 6, 0xFFFF, sum = 0
5888 20:15:19.793101 7, 0xFFFF, sum = 0
5889 20:15:19.793625 8, 0xFFFF, sum = 0
5890 20:15:19.796151 9, 0xFFFF, sum = 0
5891 20:15:19.796573 10, 0x0, sum = 1
5892 20:15:19.799780 11, 0x0, sum = 2
5893 20:15:19.800229 12, 0x0, sum = 3
5894 20:15:19.800575 13, 0x0, sum = 4
5895 20:15:19.802716 best_step = 11
5896 20:15:19.803137
5897 20:15:19.803473 ==
5898 20:15:19.806168 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 20:15:19.809553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 20:15:19.810007 ==
5901 20:15:19.813024 RX Vref Scan: 0
5902 20:15:19.813443
5903 20:15:19.813927 RX Vref 0 -> 0, step: 1
5904 20:15:19.816127
5905 20:15:19.816543 RX Delay -53 -> 252, step: 4
5906 20:15:19.823619 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5907 20:15:19.827147 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5908 20:15:19.830447 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5909 20:15:19.833674 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5910 20:15:19.840402 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5911 20:15:19.843351 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5912 20:15:19.846825 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5913 20:15:19.850073 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5914 20:15:19.853526 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5915 20:15:19.857262 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5916 20:15:19.863193 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5917 20:15:19.866883 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5918 20:15:19.869704 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5919 20:15:19.873167 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5920 20:15:19.876906 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5921 20:15:19.883524 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5922 20:15:19.884084 ==
5923 20:15:19.886734 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 20:15:19.889788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 20:15:19.890333 ==
5926 20:15:19.890732 DQS Delay:
5927 20:15:19.893562 DQS0 = 0, DQS1 = 0
5928 20:15:19.894196 DQM Delay:
5929 20:15:19.896608 DQM0 = 105, DQM1 = 97
5930 20:15:19.897279 DQ Delay:
5931 20:15:19.899782 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5932 20:15:19.903418 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =100
5933 20:15:19.906298 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5934 20:15:19.909900 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5935 20:15:19.910403
5936 20:15:19.910771
5937 20:15:19.919633 [DQSOSCAuto] RK1, (LSB)MR18= 0x1efc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5938 20:15:19.923245 CH1 RK1: MR19=504, MR18=1EFC
5939 20:15:19.926668 CH1_RK1: MR19=0x504, MR18=0x1EFC, DQSOSC=412, MR23=63, INC=63, DEC=42
5940 20:15:19.929869 [RxdqsGatingPostProcess] freq 933
5941 20:15:19.936374 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5942 20:15:19.940140 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 20:15:19.942888 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 20:15:19.946460 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 20:15:19.949668 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 20:15:19.953126 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 20:15:19.956309 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 20:15:19.959451 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 20:15:19.962855 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 20:15:19.963321 Pre-setting of DQS Precalculation
5951 20:15:19.969286 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5952 20:15:19.976196 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5953 20:15:19.982813 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5954 20:15:19.983367
5955 20:15:19.983736
5956 20:15:19.986040 [Calibration Summary] 1866 Mbps
5957 20:15:19.989398 CH 0, Rank 0
5958 20:15:19.989859 SW Impedance : PASS
5959 20:15:19.992699 DUTY Scan : NO K
5960 20:15:19.996063 ZQ Calibration : PASS
5961 20:15:19.996600 Jitter Meter : NO K
5962 20:15:19.999509 CBT Training : PASS
5963 20:15:20.002589 Write leveling : PASS
5964 20:15:20.003121 RX DQS gating : PASS
5965 20:15:20.005919 RX DQ/DQS(RDDQC) : PASS
5966 20:15:20.006479 TX DQ/DQS : PASS
5967 20:15:20.009215 RX DATLAT : PASS
5968 20:15:20.012707 RX DQ/DQS(Engine): PASS
5969 20:15:20.013171 TX OE : NO K
5970 20:15:20.015915 All Pass.
5971 20:15:20.016444
5972 20:15:20.016995 CH 0, Rank 1
5973 20:15:20.019232 SW Impedance : PASS
5974 20:15:20.019839 DUTY Scan : NO K
5975 20:15:20.022803 ZQ Calibration : PASS
5976 20:15:20.025436 Jitter Meter : NO K
5977 20:15:20.025547 CBT Training : PASS
5978 20:15:20.029101 Write leveling : PASS
5979 20:15:20.032345 RX DQS gating : PASS
5980 20:15:20.032453 RX DQ/DQS(RDDQC) : PASS
5981 20:15:20.035735 TX DQ/DQS : PASS
5982 20:15:20.038980 RX DATLAT : PASS
5983 20:15:20.039061 RX DQ/DQS(Engine): PASS
5984 20:15:20.042192 TX OE : NO K
5985 20:15:20.042274 All Pass.
5986 20:15:20.042340
5987 20:15:20.045332 CH 1, Rank 0
5988 20:15:20.045420 SW Impedance : PASS
5989 20:15:20.048514 DUTY Scan : NO K
5990 20:15:20.051701 ZQ Calibration : PASS
5991 20:15:20.051795 Jitter Meter : NO K
5992 20:15:20.055133 CBT Training : PASS
5993 20:15:20.058375 Write leveling : PASS
5994 20:15:20.058477 RX DQS gating : PASS
5995 20:15:20.061965 RX DQ/DQS(RDDQC) : PASS
5996 20:15:20.065593 TX DQ/DQS : PASS
5997 20:15:20.066052 RX DATLAT : PASS
5998 20:15:20.068923 RX DQ/DQS(Engine): PASS
5999 20:15:20.069339 TX OE : NO K
6000 20:15:20.072634 All Pass.
6001 20:15:20.073156
6002 20:15:20.073496 CH 1, Rank 1
6003 20:15:20.075678 SW Impedance : PASS
6004 20:15:20.076245 DUTY Scan : NO K
6005 20:15:20.079216 ZQ Calibration : PASS
6006 20:15:20.082401 Jitter Meter : NO K
6007 20:15:20.082864 CBT Training : PASS
6008 20:15:20.085749 Write leveling : PASS
6009 20:15:20.089086 RX DQS gating : PASS
6010 20:15:20.089647 RX DQ/DQS(RDDQC) : PASS
6011 20:15:20.092407 TX DQ/DQS : PASS
6012 20:15:20.095431 RX DATLAT : PASS
6013 20:15:20.095896 RX DQ/DQS(Engine): PASS
6014 20:15:20.099230 TX OE : NO K
6015 20:15:20.099695 All Pass.
6016 20:15:20.100066
6017 20:15:20.102194 DramC Write-DBI off
6018 20:15:20.105973 PER_BANK_REFRESH: Hybrid Mode
6019 20:15:20.106549 TX_TRACKING: ON
6020 20:15:20.115802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6021 20:15:20.118629 [FAST_K] Save calibration result to emmc
6022 20:15:20.122015 dramc_set_vcore_voltage set vcore to 650000
6023 20:15:20.126046 Read voltage for 400, 6
6024 20:15:20.126617 Vio18 = 0
6025 20:15:20.126993 Vcore = 650000
6026 20:15:20.128776 Vdram = 0
6027 20:15:20.129240 Vddq = 0
6028 20:15:20.129612 Vmddr = 0
6029 20:15:20.135405 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6030 20:15:20.138663 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6031 20:15:20.142344 MEM_TYPE=3, freq_sel=20
6032 20:15:20.145333 sv_algorithm_assistance_LP4_800
6033 20:15:20.148682 ============ PULL DRAM RESETB DOWN ============
6034 20:15:20.152104 ========== PULL DRAM RESETB DOWN end =========
6035 20:15:20.158609 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6036 20:15:20.162117 ===================================
6037 20:15:20.162783 LPDDR4 DRAM CONFIGURATION
6038 20:15:20.164976 ===================================
6039 20:15:20.168565 EX_ROW_EN[0] = 0x0
6040 20:15:20.171939 EX_ROW_EN[1] = 0x0
6041 20:15:20.172395 LP4Y_EN = 0x0
6042 20:15:20.175183 WORK_FSP = 0x0
6043 20:15:20.175637 WL = 0x2
6044 20:15:20.178289 RL = 0x2
6045 20:15:20.178747 BL = 0x2
6046 20:15:20.182010 RPST = 0x0
6047 20:15:20.182469 RD_PRE = 0x0
6048 20:15:20.185147 WR_PRE = 0x1
6049 20:15:20.185603 WR_PST = 0x0
6050 20:15:20.188601 DBI_WR = 0x0
6051 20:15:20.189075 DBI_RD = 0x0
6052 20:15:20.191818 OTF = 0x1
6053 20:15:20.195101 ===================================
6054 20:15:20.198165 ===================================
6055 20:15:20.198682 ANA top config
6056 20:15:20.201796 ===================================
6057 20:15:20.205570 DLL_ASYNC_EN = 0
6058 20:15:20.208493 ALL_SLAVE_EN = 1
6059 20:15:20.211841 NEW_RANK_MODE = 1
6060 20:15:20.212305 DLL_IDLE_MODE = 1
6061 20:15:20.215733 LP45_APHY_COMB_EN = 1
6062 20:15:20.218523 TX_ODT_DIS = 1
6063 20:15:20.222016 NEW_8X_MODE = 1
6064 20:15:20.225178 ===================================
6065 20:15:20.228608 ===================================
6066 20:15:20.229026 data_rate = 800
6067 20:15:20.231742 CKR = 1
6068 20:15:20.235089 DQ_P2S_RATIO = 4
6069 20:15:20.238384 ===================================
6070 20:15:20.241256 CA_P2S_RATIO = 4
6071 20:15:20.244982 DQ_CA_OPEN = 0
6072 20:15:20.248053 DQ_SEMI_OPEN = 1
6073 20:15:20.248134 CA_SEMI_OPEN = 1
6074 20:15:20.251438 CA_FULL_RATE = 0
6075 20:15:20.254635 DQ_CKDIV4_EN = 0
6076 20:15:20.258163 CA_CKDIV4_EN = 1
6077 20:15:20.261689 CA_PREDIV_EN = 0
6078 20:15:20.265356 PH8_DLY = 0
6079 20:15:20.265772 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6080 20:15:20.268321 DQ_AAMCK_DIV = 0
6081 20:15:20.271764 CA_AAMCK_DIV = 0
6082 20:15:20.275063 CA_ADMCK_DIV = 4
6083 20:15:20.278473 DQ_TRACK_CA_EN = 0
6084 20:15:20.282118 CA_PICK = 800
6085 20:15:20.282535 CA_MCKIO = 400
6086 20:15:20.285357 MCKIO_SEMI = 400
6087 20:15:20.288862 PLL_FREQ = 3016
6088 20:15:20.291778 DQ_UI_PI_RATIO = 32
6089 20:15:20.295249 CA_UI_PI_RATIO = 32
6090 20:15:20.298761 ===================================
6091 20:15:20.301773 ===================================
6092 20:15:20.305354 memory_type:LPDDR4
6093 20:15:20.305814 GP_NUM : 10
6094 20:15:20.308652 SRAM_EN : 1
6095 20:15:20.312052 MD32_EN : 0
6096 20:15:20.314908 ===================================
6097 20:15:20.315476 [ANA_INIT] >>>>>>>>>>>>>>
6098 20:15:20.318112 <<<<<< [CONFIGURE PHASE]: ANA_TX
6099 20:15:20.321490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6100 20:15:20.324624 ===================================
6101 20:15:20.328418 data_rate = 800,PCW = 0X7400
6102 20:15:20.331229 ===================================
6103 20:15:20.334852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6104 20:15:20.341714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6105 20:15:20.351682 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 20:15:20.357977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6107 20:15:20.361456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6108 20:15:20.364967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6109 20:15:20.365474 [ANA_INIT] flow start
6110 20:15:20.367886 [ANA_INIT] PLL >>>>>>>>
6111 20:15:20.371648 [ANA_INIT] PLL <<<<<<<<
6112 20:15:20.372219 [ANA_INIT] MIDPI >>>>>>>>
6113 20:15:20.374853 [ANA_INIT] MIDPI <<<<<<<<
6114 20:15:20.378077 [ANA_INIT] DLL >>>>>>>>
6115 20:15:20.378595 [ANA_INIT] flow end
6116 20:15:20.381327 ============ LP4 DIFF to SE enter ============
6117 20:15:20.388091 ============ LP4 DIFF to SE exit ============
6118 20:15:20.388658 [ANA_INIT] <<<<<<<<<<<<<
6119 20:15:20.391585 [Flow] Enable top DCM control >>>>>
6120 20:15:20.394362 [Flow] Enable top DCM control <<<<<
6121 20:15:20.397908 Enable DLL master slave shuffle
6122 20:15:20.404655 ==============================================================
6123 20:15:20.405219 Gating Mode config
6124 20:15:20.411843 ==============================================================
6125 20:15:20.414703 Config description:
6126 20:15:20.424752 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6127 20:15:20.431026 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6128 20:15:20.434409 SELPH_MODE 0: By rank 1: By Phase
6129 20:15:20.441476 ==============================================================
6130 20:15:20.444448 GAT_TRACK_EN = 0
6131 20:15:20.447997 RX_GATING_MODE = 2
6132 20:15:20.448559 RX_GATING_TRACK_MODE = 2
6133 20:15:20.451343 SELPH_MODE = 1
6134 20:15:20.454663 PICG_EARLY_EN = 1
6135 20:15:20.457739 VALID_LAT_VALUE = 1
6136 20:15:20.464183 ==============================================================
6137 20:15:20.467596 Enter into Gating configuration >>>>
6138 20:15:20.471102 Exit from Gating configuration <<<<
6139 20:15:20.474239 Enter into DVFS_PRE_config >>>>>
6140 20:15:20.484511 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6141 20:15:20.487539 Exit from DVFS_PRE_config <<<<<
6142 20:15:20.490604 Enter into PICG configuration >>>>
6143 20:15:20.494250 Exit from PICG configuration <<<<
6144 20:15:20.497337 [RX_INPUT] configuration >>>>>
6145 20:15:20.500811 [RX_INPUT] configuration <<<<<
6146 20:15:20.504301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6147 20:15:20.510819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6148 20:15:20.517441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 20:15:20.524641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 20:15:20.527405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 20:15:20.534152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 20:15:20.537470 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6153 20:15:20.543566 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6154 20:15:20.546863 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6155 20:15:20.549904 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6156 20:15:20.553277 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6157 20:15:20.560266 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 20:15:20.563414 ===================================
6159 20:15:20.566945 LPDDR4 DRAM CONFIGURATION
6160 20:15:20.570178 ===================================
6161 20:15:20.570334 EX_ROW_EN[0] = 0x0
6162 20:15:20.573439 EX_ROW_EN[1] = 0x0
6163 20:15:20.573627 LP4Y_EN = 0x0
6164 20:15:20.577028 WORK_FSP = 0x0
6165 20:15:20.577228 WL = 0x2
6166 20:15:20.579844 RL = 0x2
6167 20:15:20.580030 BL = 0x2
6168 20:15:20.583211 RPST = 0x0
6169 20:15:20.583416 RD_PRE = 0x0
6170 20:15:20.586592 WR_PRE = 0x1
6171 20:15:20.586825 WR_PST = 0x0
6172 20:15:20.590235 DBI_WR = 0x0
6173 20:15:20.590464 DBI_RD = 0x0
6174 20:15:20.593174 OTF = 0x1
6175 20:15:20.596953 ===================================
6176 20:15:20.600222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6177 20:15:20.603877 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6178 20:15:20.610693 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 20:15:20.613823 ===================================
6180 20:15:20.614364 LPDDR4 DRAM CONFIGURATION
6181 20:15:20.617136 ===================================
6182 20:15:20.620099 EX_ROW_EN[0] = 0x10
6183 20:15:20.624042 EX_ROW_EN[1] = 0x0
6184 20:15:20.624603 LP4Y_EN = 0x0
6185 20:15:20.627271 WORK_FSP = 0x0
6186 20:15:20.627866 WL = 0x2
6187 20:15:20.630197 RL = 0x2
6188 20:15:20.630674 BL = 0x2
6189 20:15:20.633585 RPST = 0x0
6190 20:15:20.634116 RD_PRE = 0x0
6191 20:15:20.636665 WR_PRE = 0x1
6192 20:15:20.637131 WR_PST = 0x0
6193 20:15:20.640001 DBI_WR = 0x0
6194 20:15:20.640577 DBI_RD = 0x0
6195 20:15:20.643265 OTF = 0x1
6196 20:15:20.646637 ===================================
6197 20:15:20.653402 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6198 20:15:20.656971 nWR fixed to 30
6199 20:15:20.657450 [ModeRegInit_LP4] CH0 RK0
6200 20:15:20.660024 [ModeRegInit_LP4] CH0 RK1
6201 20:15:20.663311 [ModeRegInit_LP4] CH1 RK0
6202 20:15:20.666508 [ModeRegInit_LP4] CH1 RK1
6203 20:15:20.667090 match AC timing 19
6204 20:15:20.673171 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6205 20:15:20.676633 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6206 20:15:20.679932 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6207 20:15:20.686515 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6208 20:15:20.689693 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6209 20:15:20.690472 ==
6210 20:15:20.693147 Dram Type= 6, Freq= 0, CH_0, rank 0
6211 20:15:20.696234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6212 20:15:20.696621 ==
6213 20:15:20.702745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6214 20:15:20.709683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6215 20:15:20.712374 [CA 0] Center 36 (8~64) winsize 57
6216 20:15:20.715924 [CA 1] Center 36 (8~64) winsize 57
6217 20:15:20.716007 [CA 2] Center 36 (8~64) winsize 57
6218 20:15:20.719395 [CA 3] Center 36 (8~64) winsize 57
6219 20:15:20.722456 [CA 4] Center 36 (8~64) winsize 57
6220 20:15:20.725545 [CA 5] Center 36 (8~64) winsize 57
6221 20:15:20.725628
6222 20:15:20.729139 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6223 20:15:20.732760
6224 20:15:20.735684 [CATrainingPosCal] consider 1 rank data
6225 20:15:20.735769 u2DelayCellTimex100 = 270/100 ps
6226 20:15:20.742248 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 20:15:20.745493 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 20:15:20.749022 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 20:15:20.752305 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 20:15:20.755748 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 20:15:20.759318 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 20:15:20.759401
6233 20:15:20.762222 CA PerBit enable=1, Macro0, CA PI delay=36
6234 20:15:20.762305
6235 20:15:20.765450 [CBTSetCACLKResult] CA Dly = 36
6236 20:15:20.769243 CS Dly: 1 (0~32)
6237 20:15:20.769326 ==
6238 20:15:20.771937 Dram Type= 6, Freq= 0, CH_0, rank 1
6239 20:15:20.775344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 20:15:20.775429 ==
6241 20:15:20.782239 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6242 20:15:20.785132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6243 20:15:20.788567 [CA 0] Center 36 (8~64) winsize 57
6244 20:15:20.791975 [CA 1] Center 36 (8~64) winsize 57
6245 20:15:20.795139 [CA 2] Center 36 (8~64) winsize 57
6246 20:15:20.798701 [CA 3] Center 36 (8~64) winsize 57
6247 20:15:20.802387 [CA 4] Center 36 (8~64) winsize 57
6248 20:15:20.805379 [CA 5] Center 36 (8~64) winsize 57
6249 20:15:20.805457
6250 20:15:20.808568 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6251 20:15:20.808667
6252 20:15:20.811645 [CATrainingPosCal] consider 2 rank data
6253 20:15:20.815279 u2DelayCellTimex100 = 270/100 ps
6254 20:15:20.818670 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 20:15:20.821649 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 20:15:20.825472 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 20:15:20.831618 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 20:15:20.835290 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 20:15:20.838437 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 20:15:20.838511
6261 20:15:20.841719 CA PerBit enable=1, Macro0, CA PI delay=36
6262 20:15:20.841793
6263 20:15:20.845052 [CBTSetCACLKResult] CA Dly = 36
6264 20:15:20.845118 CS Dly: 1 (0~32)
6265 20:15:20.845182
6266 20:15:20.848475 ----->DramcWriteLeveling(PI) begin...
6267 20:15:20.851711 ==
6268 20:15:20.851808 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 20:15:20.858522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 20:15:20.858625 ==
6271 20:15:20.861574 Write leveling (Byte 0): 40 => 8
6272 20:15:20.864745 Write leveling (Byte 1): 32 => 0
6273 20:15:20.864821 DramcWriteLeveling(PI) end<-----
6274 20:15:20.868406
6275 20:15:20.868478 ==
6276 20:15:20.871577 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 20:15:20.875091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 20:15:20.875195 ==
6279 20:15:20.878202 [Gating] SW mode calibration
6280 20:15:20.884795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6281 20:15:20.888369 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6282 20:15:20.894681 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6283 20:15:20.897966 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 20:15:20.901142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 20:15:20.908087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 20:15:20.911153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 20:15:20.914699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 20:15:20.921410 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 20:15:20.924424 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 20:15:20.928099 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 20:15:20.931334 Total UI for P1: 0, mck2ui 16
6292 20:15:20.934646 best dqsien dly found for B0: ( 0, 14, 24)
6293 20:15:20.938367 Total UI for P1: 0, mck2ui 16
6294 20:15:20.941381 best dqsien dly found for B1: ( 0, 14, 24)
6295 20:15:20.944486 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6296 20:15:20.948157 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6297 20:15:20.948261
6298 20:15:20.954443 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6299 20:15:20.957776 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 20:15:20.961075 [Gating] SW calibration Done
6301 20:15:20.961169 ==
6302 20:15:20.964607 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 20:15:20.967994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 20:15:20.968106 ==
6305 20:15:20.968196 RX Vref Scan: 0
6306 20:15:20.968297
6307 20:15:20.971234 RX Vref 0 -> 0, step: 1
6308 20:15:20.971338
6309 20:15:20.974662 RX Delay -410 -> 252, step: 16
6310 20:15:20.978204 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6311 20:15:20.984396 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6312 20:15:20.987560 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6313 20:15:20.991167 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6314 20:15:20.994563 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6315 20:15:20.997662 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6316 20:15:21.004572 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6317 20:15:21.008155 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6318 20:15:21.011188 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6319 20:15:21.014417 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6320 20:15:21.021159 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6321 20:15:21.024226 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6322 20:15:21.027504 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6323 20:15:21.034196 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6324 20:15:21.037415 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6325 20:15:21.041410 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6326 20:15:21.041509 ==
6327 20:15:21.044296 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 20:15:21.047879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 20:15:21.047989 ==
6330 20:15:21.051104 DQS Delay:
6331 20:15:21.051214 DQS0 = 27, DQS1 = 43
6332 20:15:21.054495 DQM Delay:
6333 20:15:21.054591 DQM0 = 12, DQM1 = 12
6334 20:15:21.057424 DQ Delay:
6335 20:15:21.057509 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6336 20:15:21.060723 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6337 20:15:21.064218 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6338 20:15:21.067536 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6339 20:15:21.067611
6340 20:15:21.067673
6341 20:15:21.067731 ==
6342 20:15:21.070706 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 20:15:21.077405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 20:15:21.077484 ==
6345 20:15:21.077548
6346 20:15:21.077606
6347 20:15:21.080672 TX Vref Scan disable
6348 20:15:21.080751 == TX Byte 0 ==
6349 20:15:21.083857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 20:15:21.090826 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 20:15:21.090905 == TX Byte 1 ==
6352 20:15:21.094105 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6353 20:15:21.097308 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6354 20:15:21.100800 ==
6355 20:15:21.103883 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 20:15:21.107438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 20:15:21.107517 ==
6358 20:15:21.107580
6359 20:15:21.107638
6360 20:15:21.110651 TX Vref Scan disable
6361 20:15:21.110730 == TX Byte 0 ==
6362 20:15:21.113867 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 20:15:21.120765 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 20:15:21.120844 == TX Byte 1 ==
6365 20:15:21.123972 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 20:15:21.130609 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 20:15:21.130688
6368 20:15:21.130750 [DATLAT]
6369 20:15:21.130808 Freq=400, CH0 RK0
6370 20:15:21.130865
6371 20:15:21.133849 DATLAT Default: 0xf
6372 20:15:21.136985 0, 0xFFFF, sum = 0
6373 20:15:21.137065 1, 0xFFFF, sum = 0
6374 20:15:21.140520 2, 0xFFFF, sum = 0
6375 20:15:21.140599 3, 0xFFFF, sum = 0
6376 20:15:21.143976 4, 0xFFFF, sum = 0
6377 20:15:21.144056 5, 0xFFFF, sum = 0
6378 20:15:21.147054 6, 0xFFFF, sum = 0
6379 20:15:21.147134 7, 0xFFFF, sum = 0
6380 20:15:21.150218 8, 0xFFFF, sum = 0
6381 20:15:21.150298 9, 0xFFFF, sum = 0
6382 20:15:21.153807 10, 0xFFFF, sum = 0
6383 20:15:21.153887 11, 0xFFFF, sum = 0
6384 20:15:21.157074 12, 0xFFFF, sum = 0
6385 20:15:21.157162 13, 0x0, sum = 1
6386 20:15:21.160212 14, 0x0, sum = 2
6387 20:15:21.160292 15, 0x0, sum = 3
6388 20:15:21.163853 16, 0x0, sum = 4
6389 20:15:21.163960 best_step = 14
6390 20:15:21.164024
6391 20:15:21.164120 ==
6392 20:15:21.166893 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 20:15:21.173375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 20:15:21.173457 ==
6395 20:15:21.173568 RX Vref Scan: 1
6396 20:15:21.173661
6397 20:15:21.177203 RX Vref 0 -> 0, step: 1
6398 20:15:21.177302
6399 20:15:21.180309 RX Delay -327 -> 252, step: 8
6400 20:15:21.180388
6401 20:15:21.183669 Set Vref, RX VrefLevel [Byte0]: 58
6402 20:15:21.186919 [Byte1]: 48
6403 20:15:21.186998
6404 20:15:21.190065 Final RX Vref Byte 0 = 58 to rank0
6405 20:15:21.193746 Final RX Vref Byte 1 = 48 to rank0
6406 20:15:21.196867 Final RX Vref Byte 0 = 58 to rank1
6407 20:15:21.199898 Final RX Vref Byte 1 = 48 to rank1==
6408 20:15:21.203185 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 20:15:21.206632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 20:15:21.206714 ==
6411 20:15:21.210206 DQS Delay:
6412 20:15:21.210299 DQS0 = 28, DQS1 = 48
6413 20:15:21.213373 DQM Delay:
6414 20:15:21.213455 DQM0 = 11, DQM1 = 15
6415 20:15:21.216787 DQ Delay:
6416 20:15:21.216868 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6417 20:15:21.219999 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6418 20:15:21.223161 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6419 20:15:21.226390 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6420 20:15:21.226497
6421 20:15:21.226591
6422 20:15:21.236820 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6423 20:15:21.239994 CH0 RK0: MR19=C0C, MR18=AAA2
6424 20:15:21.243109 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6425 20:15:21.246923 ==
6426 20:15:21.249831 Dram Type= 6, Freq= 0, CH_0, rank 1
6427 20:15:21.253443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 20:15:21.253525 ==
6429 20:15:21.256427 [Gating] SW mode calibration
6430 20:15:21.263372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6431 20:15:21.266786 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6432 20:15:21.273376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6433 20:15:21.276192 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 20:15:21.279836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 20:15:21.286437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 20:15:21.289694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 20:15:21.292870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 20:15:21.299548 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 20:15:21.303098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 20:15:21.306188 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 20:15:21.309646 Total UI for P1: 0, mck2ui 16
6442 20:15:21.313267 best dqsien dly found for B0: ( 0, 14, 24)
6443 20:15:21.316266 Total UI for P1: 0, mck2ui 16
6444 20:15:21.319746 best dqsien dly found for B1: ( 0, 14, 24)
6445 20:15:21.323042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6446 20:15:21.326188 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6447 20:15:21.326271
6448 20:15:21.332858 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6449 20:15:21.335984 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 20:15:21.336101 [Gating] SW calibration Done
6451 20:15:21.339708 ==
6452 20:15:21.342632 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 20:15:21.346272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 20:15:21.346355 ==
6455 20:15:21.346421 RX Vref Scan: 0
6456 20:15:21.346482
6457 20:15:21.349389 RX Vref 0 -> 0, step: 1
6458 20:15:21.349471
6459 20:15:21.352645 RX Delay -410 -> 252, step: 16
6460 20:15:21.356143 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6461 20:15:21.359368 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6462 20:15:21.366166 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6463 20:15:21.370081 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6464 20:15:21.372476 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6465 20:15:21.375921 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6466 20:15:21.382979 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6467 20:15:21.386140 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6468 20:15:21.389594 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6469 20:15:21.392639 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6470 20:15:21.399099 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6471 20:15:21.402371 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6472 20:15:21.406002 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6473 20:15:21.412447 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6474 20:15:21.415758 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6475 20:15:21.419152 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6476 20:15:21.419235 ==
6477 20:15:21.422271 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 20:15:21.425808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 20:15:21.429045 ==
6480 20:15:21.429127 DQS Delay:
6481 20:15:21.429194 DQS0 = 27, DQS1 = 43
6482 20:15:21.432360 DQM Delay:
6483 20:15:21.432443 DQM0 = 9, DQM1 = 15
6484 20:15:21.435479 DQ Delay:
6485 20:15:21.435562 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6486 20:15:21.438710 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6487 20:15:21.442619 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6488 20:15:21.445570 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6489 20:15:21.445653
6490 20:15:21.445720
6491 20:15:21.445781 ==
6492 20:15:21.449056 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 20:15:21.455304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 20:15:21.455387 ==
6495 20:15:21.455454
6496 20:15:21.455516
6497 20:15:21.455575 TX Vref Scan disable
6498 20:15:21.458682 == TX Byte 0 ==
6499 20:15:21.462353 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6500 20:15:21.465554 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6501 20:15:21.468770 == TX Byte 1 ==
6502 20:15:21.471936 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6503 20:15:21.475682 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6504 20:15:21.475765 ==
6505 20:15:21.478981 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 20:15:21.485311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 20:15:21.485389 ==
6508 20:15:21.485455
6509 20:15:21.485517
6510 20:15:21.488710 TX Vref Scan disable
6511 20:15:21.488778 == TX Byte 0 ==
6512 20:15:21.491897 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6513 20:15:21.495268 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6514 20:15:21.498539 == TX Byte 1 ==
6515 20:15:21.502081 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6516 20:15:21.505123 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6517 20:15:21.505210
6518 20:15:21.508315 [DATLAT]
6519 20:15:21.508434 Freq=400, CH0 RK1
6520 20:15:21.508502
6521 20:15:21.511842 DATLAT Default: 0xe
6522 20:15:21.511933 0, 0xFFFF, sum = 0
6523 20:15:21.515258 1, 0xFFFF, sum = 0
6524 20:15:21.515380 2, 0xFFFF, sum = 0
6525 20:15:21.518467 3, 0xFFFF, sum = 0
6526 20:15:21.518541 4, 0xFFFF, sum = 0
6527 20:15:21.521661 5, 0xFFFF, sum = 0
6528 20:15:21.521770 6, 0xFFFF, sum = 0
6529 20:15:21.524872 7, 0xFFFF, sum = 0
6530 20:15:21.528745 8, 0xFFFF, sum = 0
6531 20:15:21.528857 9, 0xFFFF, sum = 0
6532 20:15:21.531976 10, 0xFFFF, sum = 0
6533 20:15:21.532123 11, 0xFFFF, sum = 0
6534 20:15:21.535041 12, 0xFFFF, sum = 0
6535 20:15:21.535156 13, 0x0, sum = 1
6536 20:15:21.538406 14, 0x0, sum = 2
6537 20:15:21.538482 15, 0x0, sum = 3
6538 20:15:21.541858 16, 0x0, sum = 4
6539 20:15:21.542006 best_step = 14
6540 20:15:21.542076
6541 20:15:21.542136 ==
6542 20:15:21.544810 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 20:15:21.548347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 20:15:21.548454 ==
6545 20:15:21.552037 RX Vref Scan: 0
6546 20:15:21.552138
6547 20:15:21.554797 RX Vref 0 -> 0, step: 1
6548 20:15:21.554882
6549 20:15:21.554964 RX Delay -327 -> 252, step: 8
6550 20:15:21.563691 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6551 20:15:21.566760 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6552 20:15:21.570030 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6553 20:15:21.573754 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6554 20:15:21.580308 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6555 20:15:21.583697 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6556 20:15:21.587203 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6557 20:15:21.590314 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6558 20:15:21.596916 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6559 20:15:21.600585 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6560 20:15:21.603542 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6561 20:15:21.606919 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6562 20:15:21.613615 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6563 20:15:21.616758 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6564 20:15:21.620376 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6565 20:15:21.626985 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6566 20:15:21.627072 ==
6567 20:15:21.630314 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 20:15:21.633322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 20:15:21.633407 ==
6570 20:15:21.633487 DQS Delay:
6571 20:15:21.636816 DQS0 = 28, DQS1 = 40
6572 20:15:21.636894 DQM Delay:
6573 20:15:21.640206 DQM0 = 10, DQM1 = 12
6574 20:15:21.640288 DQ Delay:
6575 20:15:21.643843 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6576 20:15:21.647092 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6577 20:15:21.650018 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6578 20:15:21.653297 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6579 20:15:21.653378
6580 20:15:21.653444
6581 20:15:21.660242 [DQSOSCAuto] RK1, (LSB)MR18= 0xba6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6582 20:15:21.663542 CH0 RK1: MR19=C0C, MR18=BA6D
6583 20:15:21.669909 CH0_RK1: MR19=0xC0C, MR18=0xBA6D, DQSOSC=386, MR23=63, INC=396, DEC=264
6584 20:15:21.673220 [RxdqsGatingPostProcess] freq 400
6585 20:15:21.680242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6586 20:15:21.680325 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 20:15:21.683317 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 20:15:21.686667 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 20:15:21.690112 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 20:15:21.693342 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 20:15:21.696607 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 20:15:21.699934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 20:15:21.703583 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 20:15:21.706752 Pre-setting of DQS Precalculation
6595 20:15:21.710072 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6596 20:15:21.713543 ==
6597 20:15:21.713628 Dram Type= 6, Freq= 0, CH_1, rank 0
6598 20:15:21.720035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 20:15:21.720119 ==
6600 20:15:21.723408 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6601 20:15:21.729867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6602 20:15:21.733071 [CA 0] Center 36 (8~64) winsize 57
6603 20:15:21.736427 [CA 1] Center 36 (8~64) winsize 57
6604 20:15:21.739866 [CA 2] Center 36 (8~64) winsize 57
6605 20:15:21.743125 [CA 3] Center 36 (8~64) winsize 57
6606 20:15:21.746662 [CA 4] Center 36 (8~64) winsize 57
6607 20:15:21.749998 [CA 5] Center 36 (8~64) winsize 57
6608 20:15:21.750103
6609 20:15:21.753457 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6610 20:15:21.753555
6611 20:15:21.756605 [CATrainingPosCal] consider 1 rank data
6612 20:15:21.759764 u2DelayCellTimex100 = 270/100 ps
6613 20:15:21.763118 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 20:15:21.766363 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 20:15:21.770167 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 20:15:21.773113 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 20:15:21.776443 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 20:15:21.783196 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 20:15:21.783299
6620 20:15:21.786992 CA PerBit enable=1, Macro0, CA PI delay=36
6621 20:15:21.787096
6622 20:15:21.789773 [CBTSetCACLKResult] CA Dly = 36
6623 20:15:21.789870 CS Dly: 1 (0~32)
6624 20:15:21.790001 ==
6625 20:15:21.793532 Dram Type= 6, Freq= 0, CH_1, rank 1
6626 20:15:21.796639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 20:15:21.796759 ==
6628 20:15:21.803496 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6629 20:15:21.810192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6630 20:15:21.813215 [CA 0] Center 36 (8~64) winsize 57
6631 20:15:21.816224 [CA 1] Center 36 (8~64) winsize 57
6632 20:15:21.819673 [CA 2] Center 36 (8~64) winsize 57
6633 20:15:21.823157 [CA 3] Center 36 (8~64) winsize 57
6634 20:15:21.826217 [CA 4] Center 36 (8~64) winsize 57
6635 20:15:21.829554 [CA 5] Center 36 (8~64) winsize 57
6636 20:15:21.829650
6637 20:15:21.833254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6638 20:15:21.833324
6639 20:15:21.836331 [CATrainingPosCal] consider 2 rank data
6640 20:15:21.839421 u2DelayCellTimex100 = 270/100 ps
6641 20:15:21.842942 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 20:15:21.846167 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 20:15:21.849283 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 20:15:21.852739 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 20:15:21.856034 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 20:15:21.859233 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 20:15:21.859303
6648 20:15:21.866129 CA PerBit enable=1, Macro0, CA PI delay=36
6649 20:15:21.866210
6650 20:15:21.866279 [CBTSetCACLKResult] CA Dly = 36
6651 20:15:21.869142 CS Dly: 1 (0~32)
6652 20:15:21.869209
6653 20:15:21.872478 ----->DramcWriteLeveling(PI) begin...
6654 20:15:21.872547 ==
6655 20:15:21.875704 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 20:15:21.879191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 20:15:21.879261 ==
6658 20:15:21.882271 Write leveling (Byte 0): 40 => 8
6659 20:15:21.885583 Write leveling (Byte 1): 32 => 0
6660 20:15:21.888963 DramcWriteLeveling(PI) end<-----
6661 20:15:21.889035
6662 20:15:21.889097 ==
6663 20:15:21.892266 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 20:15:21.895877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 20:15:21.899511 ==
6666 20:15:21.899585 [Gating] SW mode calibration
6667 20:15:21.905895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6668 20:15:21.912660 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6669 20:15:21.915485 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6670 20:15:21.922617 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 20:15:21.925712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 20:15:21.928949 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 20:15:21.935398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 20:15:21.938860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 20:15:21.942100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 20:15:21.948672 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 20:15:21.952118 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 20:15:21.955124 Total UI for P1: 0, mck2ui 16
6679 20:15:21.958598 best dqsien dly found for B0: ( 0, 14, 24)
6680 20:15:21.961908 Total UI for P1: 0, mck2ui 16
6681 20:15:21.965757 best dqsien dly found for B1: ( 0, 14, 24)
6682 20:15:21.968513 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6683 20:15:21.971934 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6684 20:15:21.972016
6685 20:15:21.975180 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6686 20:15:21.978536 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 20:15:21.981929 [Gating] SW calibration Done
6688 20:15:21.982047 ==
6689 20:15:21.985158 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 20:15:21.988471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 20:15:21.992119 ==
6692 20:15:21.992201 RX Vref Scan: 0
6693 20:15:21.992266
6694 20:15:21.995089 RX Vref 0 -> 0, step: 1
6695 20:15:21.995171
6696 20:15:21.998559 RX Delay -410 -> 252, step: 16
6697 20:15:22.001858 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6698 20:15:22.005182 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6699 20:15:22.008389 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6700 20:15:22.015218 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6701 20:15:22.018378 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6702 20:15:22.021672 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6703 20:15:22.025205 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6704 20:15:22.031791 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6705 20:15:22.034826 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6706 20:15:22.038404 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6707 20:15:22.041730 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6708 20:15:22.048376 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6709 20:15:22.051839 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6710 20:15:22.054925 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6711 20:15:22.058357 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6712 20:15:22.064961 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6713 20:15:22.065048 ==
6714 20:15:22.068375 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 20:15:22.071805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 20:15:22.071890 ==
6717 20:15:22.071973 DQS Delay:
6718 20:15:22.075060 DQS0 = 27, DQS1 = 43
6719 20:15:22.075142 DQM Delay:
6720 20:15:22.078295 DQM0 = 11, DQM1 = 17
6721 20:15:22.078369 DQ Delay:
6722 20:15:22.081684 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6723 20:15:22.084739 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =0
6724 20:15:22.088270 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6725 20:15:22.091477 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6726 20:15:22.091552
6727 20:15:22.091632
6728 20:15:22.091715 ==
6729 20:15:22.094609 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 20:15:22.098138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 20:15:22.098222 ==
6732 20:15:22.098302
6733 20:15:22.101203
6734 20:15:22.101283 TX Vref Scan disable
6735 20:15:22.104650 == TX Byte 0 ==
6736 20:15:22.107840 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 20:15:22.111404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 20:15:22.114565 == TX Byte 1 ==
6739 20:15:22.118094 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6740 20:15:22.121228 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6741 20:15:22.121304 ==
6742 20:15:22.124442 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 20:15:22.127868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 20:15:22.131238 ==
6745 20:15:22.131317
6746 20:15:22.131405
6747 20:15:22.131483 TX Vref Scan disable
6748 20:15:22.134736 == TX Byte 0 ==
6749 20:15:22.137804 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 20:15:22.141099 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 20:15:22.144571 == TX Byte 1 ==
6752 20:15:22.148100 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6753 20:15:22.151044 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6754 20:15:22.151120
6755 20:15:22.154484 [DATLAT]
6756 20:15:22.154560 Freq=400, CH1 RK0
6757 20:15:22.154649
6758 20:15:22.157749 DATLAT Default: 0xf
6759 20:15:22.157825 0, 0xFFFF, sum = 0
6760 20:15:22.161146 1, 0xFFFF, sum = 0
6761 20:15:22.161224 2, 0xFFFF, sum = 0
6762 20:15:22.164361 3, 0xFFFF, sum = 0
6763 20:15:22.164451 4, 0xFFFF, sum = 0
6764 20:15:22.167814 5, 0xFFFF, sum = 0
6765 20:15:22.167903 6, 0xFFFF, sum = 0
6766 20:15:22.171289 7, 0xFFFF, sum = 0
6767 20:15:22.171377 8, 0xFFFF, sum = 0
6768 20:15:22.174481 9, 0xFFFF, sum = 0
6769 20:15:22.174557 10, 0xFFFF, sum = 0
6770 20:15:22.177593 11, 0xFFFF, sum = 0
6771 20:15:22.177674 12, 0xFFFF, sum = 0
6772 20:15:22.181494 13, 0x0, sum = 1
6773 20:15:22.181569 14, 0x0, sum = 2
6774 20:15:22.184427 15, 0x0, sum = 3
6775 20:15:22.184502 16, 0x0, sum = 4
6776 20:15:22.187838 best_step = 14
6777 20:15:22.187912
6778 20:15:22.187991 ==
6779 20:15:22.190914 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 20:15:22.194166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 20:15:22.194241 ==
6782 20:15:22.197450 RX Vref Scan: 1
6783 20:15:22.197525
6784 20:15:22.197605 RX Vref 0 -> 0, step: 1
6785 20:15:22.197690
6786 20:15:22.200846 RX Delay -327 -> 252, step: 8
6787 20:15:22.200927
6788 20:15:22.204122 Set Vref, RX VrefLevel [Byte0]: 51
6789 20:15:22.207355 [Byte1]: 52
6790 20:15:22.212293
6791 20:15:22.212369 Final RX Vref Byte 0 = 51 to rank0
6792 20:15:22.216031 Final RX Vref Byte 1 = 52 to rank0
6793 20:15:22.219110 Final RX Vref Byte 0 = 51 to rank1
6794 20:15:22.222057 Final RX Vref Byte 1 = 52 to rank1==
6795 20:15:22.225623 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 20:15:22.232256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 20:15:22.232335 ==
6798 20:15:22.232422 DQS Delay:
6799 20:15:22.235437 DQS0 = 32, DQS1 = 40
6800 20:15:22.235518 DQM Delay:
6801 20:15:22.235597 DQM0 = 10, DQM1 = 13
6802 20:15:22.238855 DQ Delay:
6803 20:15:22.242022 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6804 20:15:22.242097 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6805 20:15:22.244987 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6806 20:15:22.248608 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6807 20:15:22.248692
6808 20:15:22.251813
6809 20:15:22.258691 [DQSOSCAuto] RK0, (LSB)MR18= 0x9cd6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6810 20:15:22.261986 CH1 RK0: MR19=C0C, MR18=9CD6
6811 20:15:22.268793 CH1_RK0: MR19=0xC0C, MR18=0x9CD6, DQSOSC=383, MR23=63, INC=402, DEC=268
6812 20:15:22.268883 ==
6813 20:15:22.271788 Dram Type= 6, Freq= 0, CH_1, rank 1
6814 20:15:22.274996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 20:15:22.275075 ==
6816 20:15:22.278551 [Gating] SW mode calibration
6817 20:15:22.284987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6818 20:15:22.291396 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6819 20:15:22.294685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6820 20:15:22.297883 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 20:15:22.304627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 20:15:22.308102 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 20:15:22.311410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 20:15:22.318159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 20:15:22.321495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 20:15:22.324518 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 20:15:22.331102 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 20:15:22.331182 Total UI for P1: 0, mck2ui 16
6829 20:15:22.337844 best dqsien dly found for B0: ( 0, 14, 24)
6830 20:15:22.337927 Total UI for P1: 0, mck2ui 16
6831 20:15:22.341300 best dqsien dly found for B1: ( 0, 14, 24)
6832 20:15:22.347516 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6833 20:15:22.351034 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6834 20:15:22.351113
6835 20:15:22.354161 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6836 20:15:22.357783 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 20:15:22.361056 [Gating] SW calibration Done
6838 20:15:22.361139 ==
6839 20:15:22.364244 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 20:15:22.367516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 20:15:22.367596 ==
6842 20:15:22.371017 RX Vref Scan: 0
6843 20:15:22.371098
6844 20:15:22.371179 RX Vref 0 -> 0, step: 1
6845 20:15:22.371256
6846 20:15:22.374359 RX Delay -410 -> 252, step: 16
6847 20:15:22.380496 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6848 20:15:22.383993 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6849 20:15:22.387558 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6850 20:15:22.390595 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6851 20:15:22.397195 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6852 20:15:22.400453 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6853 20:15:22.403991 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6854 20:15:22.407298 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6855 20:15:22.413892 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6856 20:15:22.417184 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6857 20:15:22.420434 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6858 20:15:22.424115 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6859 20:15:22.430967 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6860 20:15:22.433887 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6861 20:15:22.437084 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6862 20:15:22.440521 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6863 20:15:22.443893 ==
6864 20:15:22.443967 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 20:15:22.450656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 20:15:22.450732 ==
6867 20:15:22.450821 DQS Delay:
6868 20:15:22.453578 DQS0 = 35, DQS1 = 35
6869 20:15:22.453658 DQM Delay:
6870 20:15:22.457005 DQM0 = 17, DQM1 = 12
6871 20:15:22.457078 DQ Delay:
6872 20:15:22.460581 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6873 20:15:22.463994 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6874 20:15:22.467245 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6875 20:15:22.470549 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6876 20:15:22.470625
6877 20:15:22.470706
6878 20:15:22.470790 ==
6879 20:15:22.473705 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 20:15:22.477291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 20:15:22.477370 ==
6882 20:15:22.477459
6883 20:15:22.477533
6884 20:15:22.480307 TX Vref Scan disable
6885 20:15:22.480381 == TX Byte 0 ==
6886 20:15:22.487001 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6887 20:15:22.490541 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6888 20:15:22.490618 == TX Byte 1 ==
6889 20:15:22.497067 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6890 20:15:22.500569 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6891 20:15:22.500653 ==
6892 20:15:22.503549 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 20:15:22.507089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 20:15:22.507172 ==
6895 20:15:22.507253
6896 20:15:22.507341
6897 20:15:22.510138 TX Vref Scan disable
6898 20:15:22.510224 == TX Byte 0 ==
6899 20:15:22.517410 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6900 20:15:22.520289 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6901 20:15:22.520372 == TX Byte 1 ==
6902 20:15:22.524063 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6903 20:15:22.530673 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6904 20:15:22.530756
6905 20:15:22.530822 [DATLAT]
6906 20:15:22.533776 Freq=400, CH1 RK1
6907 20:15:22.533885
6908 20:15:22.533979 DATLAT Default: 0xe
6909 20:15:22.536930 0, 0xFFFF, sum = 0
6910 20:15:22.537014 1, 0xFFFF, sum = 0
6911 20:15:22.540575 2, 0xFFFF, sum = 0
6912 20:15:22.540659 3, 0xFFFF, sum = 0
6913 20:15:22.543586 4, 0xFFFF, sum = 0
6914 20:15:22.543671 5, 0xFFFF, sum = 0
6915 20:15:22.547037 6, 0xFFFF, sum = 0
6916 20:15:22.547122 7, 0xFFFF, sum = 0
6917 20:15:22.550420 8, 0xFFFF, sum = 0
6918 20:15:22.550505 9, 0xFFFF, sum = 0
6919 20:15:22.553565 10, 0xFFFF, sum = 0
6920 20:15:22.553649 11, 0xFFFF, sum = 0
6921 20:15:22.557180 12, 0xFFFF, sum = 0
6922 20:15:22.557263 13, 0x0, sum = 1
6923 20:15:22.560221 14, 0x0, sum = 2
6924 20:15:22.560305 15, 0x0, sum = 3
6925 20:15:22.563734 16, 0x0, sum = 4
6926 20:15:22.563818 best_step = 14
6927 20:15:22.563885
6928 20:15:22.563947 ==
6929 20:15:22.567078 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 20:15:22.573436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 20:15:22.573519 ==
6932 20:15:22.573585 RX Vref Scan: 0
6933 20:15:22.573647
6934 20:15:22.577015 RX Vref 0 -> 0, step: 1
6935 20:15:22.577098
6936 20:15:22.580262 RX Delay -311 -> 252, step: 8
6937 20:15:22.586698 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6938 20:15:22.590079 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6939 20:15:22.593686 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6940 20:15:22.596827 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6941 20:15:22.603569 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6942 20:15:22.606562 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6943 20:15:22.610122 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6944 20:15:22.613278 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6945 20:15:22.620308 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6946 20:15:22.623437 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6947 20:15:22.626499 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6948 20:15:22.629963 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6949 20:15:22.636691 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6950 20:15:22.639792 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6951 20:15:22.643133 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6952 20:15:22.646685 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6953 20:15:22.649683 ==
6954 20:15:22.653087 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 20:15:22.656378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 20:15:22.656446 ==
6957 20:15:22.656508 DQS Delay:
6958 20:15:22.659763 DQS0 = 32, DQS1 = 36
6959 20:15:22.659831 DQM Delay:
6960 20:15:22.663170 DQM0 = 11, DQM1 = 11
6961 20:15:22.663236 DQ Delay:
6962 20:15:22.666420 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6963 20:15:22.669752 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6964 20:15:22.673009 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6965 20:15:22.676527 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6966 20:15:22.676594
6967 20:15:22.676656
6968 20:15:22.683297 [DQSOSCAuto] RK1, (LSB)MR18= 0xac56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6969 20:15:22.686357 CH1 RK1: MR19=C0C, MR18=AC56
6970 20:15:22.692927 CH1_RK1: MR19=0xC0C, MR18=0xAC56, DQSOSC=388, MR23=63, INC=392, DEC=261
6971 20:15:22.696468 [RxdqsGatingPostProcess] freq 400
6972 20:15:22.699536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6973 20:15:22.702862 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 20:15:22.706390 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 20:15:22.709553 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 20:15:22.713352 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 20:15:22.716430 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 20:15:22.719375 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 20:15:22.723102 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 20:15:22.726373 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 20:15:22.729604 Pre-setting of DQS Precalculation
6982 20:15:22.733034 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6983 20:15:22.742929 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6984 20:15:22.749710 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6985 20:15:22.749786
6986 20:15:22.749851
6987 20:15:22.752879 [Calibration Summary] 800 Mbps
6988 20:15:22.752946 CH 0, Rank 0
6989 20:15:22.756023 SW Impedance : PASS
6990 20:15:22.756089 DUTY Scan : NO K
6991 20:15:22.759539 ZQ Calibration : PASS
6992 20:15:22.762519 Jitter Meter : NO K
6993 20:15:22.762585 CBT Training : PASS
6994 20:15:22.765773 Write leveling : PASS
6995 20:15:22.769478 RX DQS gating : PASS
6996 20:15:22.769552 RX DQ/DQS(RDDQC) : PASS
6997 20:15:22.772555 TX DQ/DQS : PASS
6998 20:15:22.775958 RX DATLAT : PASS
6999 20:15:22.776025 RX DQ/DQS(Engine): PASS
7000 20:15:22.779223 TX OE : NO K
7001 20:15:22.779289 All Pass.
7002 20:15:22.779353
7003 20:15:22.782560 CH 0, Rank 1
7004 20:15:22.782627 SW Impedance : PASS
7005 20:15:22.786054 DUTY Scan : NO K
7006 20:15:22.789197 ZQ Calibration : PASS
7007 20:15:22.789265 Jitter Meter : NO K
7008 20:15:22.792381 CBT Training : PASS
7009 20:15:22.795546 Write leveling : NO K
7010 20:15:22.795653 RX DQS gating : PASS
7011 20:15:22.799164 RX DQ/DQS(RDDQC) : PASS
7012 20:15:22.802276 TX DQ/DQS : PASS
7013 20:15:22.802345 RX DATLAT : PASS
7014 20:15:22.805530 RX DQ/DQS(Engine): PASS
7015 20:15:22.805596 TX OE : NO K
7016 20:15:22.808759 All Pass.
7017 20:15:22.808826
7018 20:15:22.808887 CH 1, Rank 0
7019 20:15:22.811930 SW Impedance : PASS
7020 20:15:22.815649 DUTY Scan : NO K
7021 20:15:22.815714 ZQ Calibration : PASS
7022 20:15:22.818907 Jitter Meter : NO K
7023 20:15:22.818971 CBT Training : PASS
7024 20:15:22.822148 Write leveling : PASS
7025 20:15:22.825329 RX DQS gating : PASS
7026 20:15:22.825394 RX DQ/DQS(RDDQC) : PASS
7027 20:15:22.828962 TX DQ/DQS : PASS
7028 20:15:22.831992 RX DATLAT : PASS
7029 20:15:22.832057 RX DQ/DQS(Engine): PASS
7030 20:15:22.835415 TX OE : NO K
7031 20:15:22.835484 All Pass.
7032 20:15:22.835546
7033 20:15:22.838810 CH 1, Rank 1
7034 20:15:22.838883 SW Impedance : PASS
7035 20:15:22.842151 DUTY Scan : NO K
7036 20:15:22.845506 ZQ Calibration : PASS
7037 20:15:22.845572 Jitter Meter : NO K
7038 20:15:22.848572 CBT Training : PASS
7039 20:15:22.852189 Write leveling : NO K
7040 20:15:22.852260 RX DQS gating : PASS
7041 20:15:22.855635 RX DQ/DQS(RDDQC) : PASS
7042 20:15:22.855705 TX DQ/DQS : PASS
7043 20:15:22.858713 RX DATLAT : PASS
7044 20:15:22.862074 RX DQ/DQS(Engine): PASS
7045 20:15:22.862142 TX OE : NO K
7046 20:15:22.865578 All Pass.
7047 20:15:22.865652
7048 20:15:22.865714 DramC Write-DBI off
7049 20:15:22.868955 PER_BANK_REFRESH: Hybrid Mode
7050 20:15:22.872286 TX_TRACKING: ON
7051 20:15:22.878648 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7052 20:15:22.882142 [FAST_K] Save calibration result to emmc
7053 20:15:22.885424 dramc_set_vcore_voltage set vcore to 725000
7054 20:15:22.888961 Read voltage for 1600, 0
7055 20:15:22.889034 Vio18 = 0
7056 20:15:22.892087 Vcore = 725000
7057 20:15:22.892192 Vdram = 0
7058 20:15:22.892285 Vddq = 0
7059 20:15:22.895357 Vmddr = 0
7060 20:15:22.898445 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7061 20:15:22.905109 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7062 20:15:22.905214 MEM_TYPE=3, freq_sel=13
7063 20:15:22.908290 sv_algorithm_assistance_LP4_3733
7064 20:15:22.914818 ============ PULL DRAM RESETB DOWN ============
7065 20:15:22.918602 ========== PULL DRAM RESETB DOWN end =========
7066 20:15:22.921800 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7067 20:15:22.925343 ===================================
7068 20:15:22.928523 LPDDR4 DRAM CONFIGURATION
7069 20:15:22.931589 ===================================
7070 20:15:22.935091 EX_ROW_EN[0] = 0x0
7071 20:15:22.935162 EX_ROW_EN[1] = 0x0
7072 20:15:22.938416 LP4Y_EN = 0x0
7073 20:15:22.938517 WORK_FSP = 0x1
7074 20:15:22.941554 WL = 0x5
7075 20:15:22.941650 RL = 0x5
7076 20:15:22.945355 BL = 0x2
7077 20:15:22.945453 RPST = 0x0
7078 20:15:22.948316 RD_PRE = 0x0
7079 20:15:22.948385 WR_PRE = 0x1
7080 20:15:22.951859 WR_PST = 0x1
7081 20:15:22.951931 DBI_WR = 0x0
7082 20:15:22.955113 DBI_RD = 0x0
7083 20:15:22.955182 OTF = 0x1
7084 20:15:22.958242 ===================================
7085 20:15:22.961626 ===================================
7086 20:15:22.964981 ANA top config
7087 20:15:22.968169 ===================================
7088 20:15:22.971483 DLL_ASYNC_EN = 0
7089 20:15:22.971589 ALL_SLAVE_EN = 0
7090 20:15:22.974898 NEW_RANK_MODE = 1
7091 20:15:22.978291 DLL_IDLE_MODE = 1
7092 20:15:22.981742 LP45_APHY_COMB_EN = 1
7093 20:15:22.981812 TX_ODT_DIS = 0
7094 20:15:22.984934 NEW_8X_MODE = 1
7095 20:15:22.988216 ===================================
7096 20:15:22.991635 ===================================
7097 20:15:22.994726 data_rate = 3200
7098 20:15:22.998066 CKR = 1
7099 20:15:23.001667 DQ_P2S_RATIO = 8
7100 20:15:23.004909 ===================================
7101 20:15:23.008137 CA_P2S_RATIO = 8
7102 20:15:23.008234 DQ_CA_OPEN = 0
7103 20:15:23.011652 DQ_SEMI_OPEN = 0
7104 20:15:23.015326 CA_SEMI_OPEN = 0
7105 20:15:23.018040 CA_FULL_RATE = 0
7106 20:15:23.021669 DQ_CKDIV4_EN = 0
7107 20:15:23.025134 CA_CKDIV4_EN = 0
7108 20:15:23.025251 CA_PREDIV_EN = 0
7109 20:15:23.028311 PH8_DLY = 12
7110 20:15:23.031559 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7111 20:15:23.034714 DQ_AAMCK_DIV = 4
7112 20:15:23.037882 CA_AAMCK_DIV = 4
7113 20:15:23.041792 CA_ADMCK_DIV = 4
7114 20:15:23.041899 DQ_TRACK_CA_EN = 0
7115 20:15:23.044821 CA_PICK = 1600
7116 20:15:23.047791 CA_MCKIO = 1600
7117 20:15:23.051452 MCKIO_SEMI = 0
7118 20:15:23.054593 PLL_FREQ = 3068
7119 20:15:23.058082 DQ_UI_PI_RATIO = 32
7120 20:15:23.061352 CA_UI_PI_RATIO = 0
7121 20:15:23.064560 ===================================
7122 20:15:23.068081 ===================================
7123 20:15:23.068192 memory_type:LPDDR4
7124 20:15:23.071291 GP_NUM : 10
7125 20:15:23.074474 SRAM_EN : 1
7126 20:15:23.074562 MD32_EN : 0
7127 20:15:23.078163 ===================================
7128 20:15:23.081267 [ANA_INIT] >>>>>>>>>>>>>>
7129 20:15:23.084536 <<<<<< [CONFIGURE PHASE]: ANA_TX
7130 20:15:23.087927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7131 20:15:23.091135 ===================================
7132 20:15:23.094272 data_rate = 3200,PCW = 0X7600
7133 20:15:23.097597 ===================================
7134 20:15:23.101214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7135 20:15:23.104478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7136 20:15:23.110975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 20:15:23.114400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7138 20:15:23.117767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7139 20:15:23.121006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7140 20:15:23.124256 [ANA_INIT] flow start
7141 20:15:23.127531 [ANA_INIT] PLL >>>>>>>>
7142 20:15:23.127629 [ANA_INIT] PLL <<<<<<<<
7143 20:15:23.130729 [ANA_INIT] MIDPI >>>>>>>>
7144 20:15:23.134243 [ANA_INIT] MIDPI <<<<<<<<
7145 20:15:23.137433 [ANA_INIT] DLL >>>>>>>>
7146 20:15:23.137544 [ANA_INIT] DLL <<<<<<<<
7147 20:15:23.141362 [ANA_INIT] flow end
7148 20:15:23.144183 ============ LP4 DIFF to SE enter ============
7149 20:15:23.147721 ============ LP4 DIFF to SE exit ============
7150 20:15:23.151098 [ANA_INIT] <<<<<<<<<<<<<
7151 20:15:23.154295 [Flow] Enable top DCM control >>>>>
7152 20:15:23.157628 [Flow] Enable top DCM control <<<<<
7153 20:15:23.160784 Enable DLL master slave shuffle
7154 20:15:23.167365 ==============================================================
7155 20:15:23.167444 Gating Mode config
7156 20:15:23.174376 ==============================================================
7157 20:15:23.174478 Config description:
7158 20:15:23.183979 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7159 20:15:23.190474 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7160 20:15:23.197332 SELPH_MODE 0: By rank 1: By Phase
7161 20:15:23.200568 ==============================================================
7162 20:15:23.204034 GAT_TRACK_EN = 1
7163 20:15:23.207239 RX_GATING_MODE = 2
7164 20:15:23.210455 RX_GATING_TRACK_MODE = 2
7165 20:15:23.213772 SELPH_MODE = 1
7166 20:15:23.217122 PICG_EARLY_EN = 1
7167 20:15:23.220445 VALID_LAT_VALUE = 1
7168 20:15:23.223945 ==============================================================
7169 20:15:23.227313 Enter into Gating configuration >>>>
7170 20:15:23.230536 Exit from Gating configuration <<<<
7171 20:15:23.233861 Enter into DVFS_PRE_config >>>>>
7172 20:15:23.247030 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7173 20:15:23.250245 Exit from DVFS_PRE_config <<<<<
7174 20:15:23.253758 Enter into PICG configuration >>>>
7175 20:15:23.253867 Exit from PICG configuration <<<<
7176 20:15:23.257090 [RX_INPUT] configuration >>>>>
7177 20:15:23.260333 [RX_INPUT] configuration <<<<<
7178 20:15:23.266903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7179 20:15:23.270649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7180 20:15:23.277163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 20:15:23.283883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 20:15:23.290366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 20:15:23.296999 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 20:15:23.300510 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7185 20:15:23.303451 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7186 20:15:23.307103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7187 20:15:23.313668 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7188 20:15:23.316770 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7189 20:15:23.320151 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 20:15:23.323352 ===================================
7191 20:15:23.326655 LPDDR4 DRAM CONFIGURATION
7192 20:15:23.329923 ===================================
7193 20:15:23.333417 EX_ROW_EN[0] = 0x0
7194 20:15:23.333513 EX_ROW_EN[1] = 0x0
7195 20:15:23.336506 LP4Y_EN = 0x0
7196 20:15:23.336601 WORK_FSP = 0x1
7197 20:15:23.339772 WL = 0x5
7198 20:15:23.339867 RL = 0x5
7199 20:15:23.343417 BL = 0x2
7200 20:15:23.343512 RPST = 0x0
7201 20:15:23.346661 RD_PRE = 0x0
7202 20:15:23.346729 WR_PRE = 0x1
7203 20:15:23.349963 WR_PST = 0x1
7204 20:15:23.350032 DBI_WR = 0x0
7205 20:15:23.353211 DBI_RD = 0x0
7206 20:15:23.353279 OTF = 0x1
7207 20:15:23.356607 ===================================
7208 20:15:23.363301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7209 20:15:23.366872 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7210 20:15:23.369816 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 20:15:23.373705 ===================================
7212 20:15:23.376526 LPDDR4 DRAM CONFIGURATION
7213 20:15:23.379771 ===================================
7214 20:15:23.383119 EX_ROW_EN[0] = 0x10
7215 20:15:23.383223 EX_ROW_EN[1] = 0x0
7216 20:15:23.386674 LP4Y_EN = 0x0
7217 20:15:23.386785 WORK_FSP = 0x1
7218 20:15:23.389675 WL = 0x5
7219 20:15:23.389772 RL = 0x5
7220 20:15:23.393372 BL = 0x2
7221 20:15:23.393472 RPST = 0x0
7222 20:15:23.396307 RD_PRE = 0x0
7223 20:15:23.396422 WR_PRE = 0x1
7224 20:15:23.399642 WR_PST = 0x1
7225 20:15:23.399721 DBI_WR = 0x0
7226 20:15:23.402906 DBI_RD = 0x0
7227 20:15:23.403008 OTF = 0x1
7228 20:15:23.406281 ===================================
7229 20:15:23.413298 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7230 20:15:23.413374 ==
7231 20:15:23.416282 Dram Type= 6, Freq= 0, CH_0, rank 0
7232 20:15:23.422811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7233 20:15:23.422923 ==
7234 20:15:23.423017 [Duty_Offset_Calibration]
7235 20:15:23.426013 B0:2 B1:0 CA:1
7236 20:15:23.426102
7237 20:15:23.429279 [DutyScan_Calibration_Flow] k_type=0
7238 20:15:23.438005
7239 20:15:23.438101 ==CLK 0==
7240 20:15:23.441229 Final CLK duty delay cell = -4
7241 20:15:23.444380 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7242 20:15:23.447987 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7243 20:15:23.451182 [-4] AVG Duty = 4906%(X100)
7244 20:15:23.451279
7245 20:15:23.454719 CH0 CLK Duty spec in!! Max-Min= 187%
7246 20:15:23.457810 [DutyScan_Calibration_Flow] ====Done====
7247 20:15:23.457913
7248 20:15:23.460962 [DutyScan_Calibration_Flow] k_type=1
7249 20:15:23.477313
7250 20:15:23.477421 ==DQS 0 ==
7251 20:15:23.480815 Final DQS duty delay cell = 0
7252 20:15:23.483809 [0] MAX Duty = 5249%(X100), DQS PI = 32
7253 20:15:23.487190 [0] MIN Duty = 4969%(X100), DQS PI = 0
7254 20:15:23.487295 [0] AVG Duty = 5109%(X100)
7255 20:15:23.490503
7256 20:15:23.490614 ==DQS 1 ==
7257 20:15:23.493871 Final DQS duty delay cell = -4
7258 20:15:23.497288 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7259 20:15:23.500709 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7260 20:15:23.503894 [-4] AVG Duty = 5000%(X100)
7261 20:15:23.504000
7262 20:15:23.507424 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7263 20:15:23.507522
7264 20:15:23.510737 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7265 20:15:23.514330 [DutyScan_Calibration_Flow] ====Done====
7266 20:15:23.514401
7267 20:15:23.517234 [DutyScan_Calibration_Flow] k_type=3
7268 20:15:23.534720
7269 20:15:23.534824 ==DQM 0 ==
7270 20:15:23.538354 Final DQM duty delay cell = 0
7271 20:15:23.541406 [0] MAX Duty = 5062%(X100), DQS PI = 12
7272 20:15:23.544828 [0] MIN Duty = 4813%(X100), DQS PI = 52
7273 20:15:23.548308 [0] AVG Duty = 4937%(X100)
7274 20:15:23.548406
7275 20:15:23.548511 ==DQM 1 ==
7276 20:15:23.551289 Final DQM duty delay cell = 0
7277 20:15:23.554826 [0] MAX Duty = 5249%(X100), DQS PI = 30
7278 20:15:23.558362 [0] MIN Duty = 5000%(X100), DQS PI = 20
7279 20:15:23.561281 [0] AVG Duty = 5124%(X100)
7280 20:15:23.561379
7281 20:15:23.564952 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7282 20:15:23.565059
7283 20:15:23.568186 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7284 20:15:23.571361 [DutyScan_Calibration_Flow] ====Done====
7285 20:15:23.571475
7286 20:15:23.574827 [DutyScan_Calibration_Flow] k_type=2
7287 20:15:23.592811
7288 20:15:23.592926 ==DQ 0 ==
7289 20:15:23.596061 Final DQ duty delay cell = 0
7290 20:15:23.599576 [0] MAX Duty = 5124%(X100), DQS PI = 34
7291 20:15:23.602655 [0] MIN Duty = 5000%(X100), DQS PI = 0
7292 20:15:23.602760 [0] AVG Duty = 5062%(X100)
7293 20:15:23.606269
7294 20:15:23.606372 ==DQ 1 ==
7295 20:15:23.609283 Final DQ duty delay cell = 4
7296 20:15:23.612730 [4] MAX Duty = 5125%(X100), DQS PI = 4
7297 20:15:23.616214 [4] MIN Duty = 5062%(X100), DQS PI = 0
7298 20:15:23.616315 [4] AVG Duty = 5093%(X100)
7299 20:15:23.616417
7300 20:15:23.619413 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7301 20:15:23.619487
7302 20:15:23.622721 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7303 20:15:23.629137 [DutyScan_Calibration_Flow] ====Done====
7304 20:15:23.629242 ==
7305 20:15:23.632733 Dram Type= 6, Freq= 0, CH_1, rank 0
7306 20:15:23.635739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 20:15:23.635836 ==
7308 20:15:23.639394 [Duty_Offset_Calibration]
7309 20:15:23.639490 B0:0 B1:-1 CA:2
7310 20:15:23.639583
7311 20:15:23.642586 [DutyScan_Calibration_Flow] k_type=0
7312 20:15:23.652871
7313 20:15:23.652944 ==CLK 0==
7314 20:15:23.655986 Final CLK duty delay cell = 0
7315 20:15:23.659639 [0] MAX Duty = 5156%(X100), DQS PI = 10
7316 20:15:23.663032 [0] MIN Duty = 4906%(X100), DQS PI = 46
7317 20:15:23.663101 [0] AVG Duty = 5031%(X100)
7318 20:15:23.666238
7319 20:15:23.669359 CH1 CLK Duty spec in!! Max-Min= 250%
7320 20:15:23.672564 [DutyScan_Calibration_Flow] ====Done====
7321 20:15:23.672667
7322 20:15:23.676114 [DutyScan_Calibration_Flow] k_type=1
7323 20:15:23.692429
7324 20:15:23.692542 ==DQS 0 ==
7325 20:15:23.696154 Final DQS duty delay cell = 0
7326 20:15:23.699240 [0] MAX Duty = 5093%(X100), DQS PI = 24
7327 20:15:23.702776 [0] MIN Duty = 4969%(X100), DQS PI = 0
7328 20:15:23.702876 [0] AVG Duty = 5031%(X100)
7329 20:15:23.705962
7330 20:15:23.706071 ==DQS 1 ==
7331 20:15:23.709683 Final DQS duty delay cell = 0
7332 20:15:23.712528 [0] MAX Duty = 5187%(X100), DQS PI = 62
7333 20:15:23.715990 [0] MIN Duty = 4844%(X100), DQS PI = 34
7334 20:15:23.716099 [0] AVG Duty = 5015%(X100)
7335 20:15:23.716201
7336 20:15:23.722477 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7337 20:15:23.722589
7338 20:15:23.726424 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7339 20:15:23.729209 [DutyScan_Calibration_Flow] ====Done====
7340 20:15:23.729319
7341 20:15:23.732587 [DutyScan_Calibration_Flow] k_type=3
7342 20:15:23.750168
7343 20:15:23.750285 ==DQM 0 ==
7344 20:15:23.753505 Final DQM duty delay cell = 4
7345 20:15:23.756904 [4] MAX Duty = 5125%(X100), DQS PI = 8
7346 20:15:23.760586 [4] MIN Duty = 5000%(X100), DQS PI = 30
7347 20:15:23.760689 [4] AVG Duty = 5062%(X100)
7348 20:15:23.760788
7349 20:15:23.763484 ==DQM 1 ==
7350 20:15:23.767025 Final DQM duty delay cell = 0
7351 20:15:23.770636 [0] MAX Duty = 5281%(X100), DQS PI = 60
7352 20:15:23.773417 [0] MIN Duty = 4844%(X100), DQS PI = 34
7353 20:15:23.773518 [0] AVG Duty = 5062%(X100)
7354 20:15:23.777006
7355 20:15:23.780052 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7356 20:15:23.780158
7357 20:15:23.783687 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7358 20:15:23.786658 [DutyScan_Calibration_Flow] ====Done====
7359 20:15:23.786762
7360 20:15:23.790099 [DutyScan_Calibration_Flow] k_type=2
7361 20:15:23.807326
7362 20:15:23.807443 ==DQ 0 ==
7363 20:15:23.810349 Final DQ duty delay cell = 0
7364 20:15:23.813833 [0] MAX Duty = 5093%(X100), DQS PI = 20
7365 20:15:23.817212 [0] MIN Duty = 4969%(X100), DQS PI = 0
7366 20:15:23.817289 [0] AVG Duty = 5031%(X100)
7367 20:15:23.817352
7368 20:15:23.820431 ==DQ 1 ==
7369 20:15:23.823947 Final DQ duty delay cell = 0
7370 20:15:23.827493 [0] MAX Duty = 5062%(X100), DQS PI = 4
7371 20:15:23.830144 [0] MIN Duty = 4813%(X100), DQS PI = 34
7372 20:15:23.830220 [0] AVG Duty = 4937%(X100)
7373 20:15:23.830324
7374 20:15:23.833872 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7375 20:15:23.834014
7376 20:15:23.836954 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7377 20:15:23.843375 [DutyScan_Calibration_Flow] ====Done====
7378 20:15:23.846911 nWR fixed to 30
7379 20:15:23.847016 [ModeRegInit_LP4] CH0 RK0
7380 20:15:23.850192 [ModeRegInit_LP4] CH0 RK1
7381 20:15:23.853931 [ModeRegInit_LP4] CH1 RK0
7382 20:15:23.854012 [ModeRegInit_LP4] CH1 RK1
7383 20:15:23.856792 match AC timing 5
7384 20:15:23.859945 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7385 20:15:23.863646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7386 20:15:23.870260 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7387 20:15:23.873165 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7388 20:15:23.880080 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7389 20:15:23.880186 [MiockJmeterHQA]
7390 20:15:23.880278
7391 20:15:23.883451 [DramcMiockJmeter] u1RxGatingPI = 0
7392 20:15:23.886823 0 : 4255, 4026
7393 20:15:23.886928 4 : 4252, 4027
7394 20:15:23.887020 8 : 4255, 4030
7395 20:15:23.889866 12 : 4252, 4027
7396 20:15:23.890001 16 : 4253, 4026
7397 20:15:23.893349 20 : 4363, 4138
7398 20:15:23.893428 24 : 4363, 4138
7399 20:15:23.896622 28 : 4252, 4027
7400 20:15:23.896725 32 : 4253, 4026
7401 20:15:23.900066 36 : 4252, 4027
7402 20:15:23.900182 40 : 4252, 4027
7403 20:15:23.900279 44 : 4255, 4029
7404 20:15:23.903135 48 : 4255, 4029
7405 20:15:23.903250 52 : 4250, 4027
7406 20:15:23.906542 56 : 4250, 4027
7407 20:15:23.906646 60 : 4250, 4027
7408 20:15:23.910030 64 : 4253, 4029
7409 20:15:23.910111 68 : 4253, 4029
7410 20:15:23.910183 72 : 4361, 4138
7411 20:15:23.913101 76 : 4360, 4138
7412 20:15:23.913176 80 : 4360, 4138
7413 20:15:23.916403 84 : 4252, 4029
7414 20:15:23.916505 88 : 4253, 3498
7415 20:15:23.920114 92 : 4250, 0
7416 20:15:23.920237 96 : 4363, 0
7417 20:15:23.920332 100 : 4250, 0
7418 20:15:23.923475 104 : 4250, 0
7419 20:15:23.923580 108 : 4250, 0
7420 20:15:23.926639 112 : 4250, 0
7421 20:15:23.926760 116 : 4253, 0
7422 20:15:23.926857 120 : 4361, 0
7423 20:15:23.930213 124 : 4252, 0
7424 20:15:23.930317 128 : 4361, 0
7425 20:15:23.930431 132 : 4255, 0
7426 20:15:23.933090 136 : 4250, 0
7427 20:15:23.933168 140 : 4361, 0
7428 20:15:23.936583 144 : 4255, 0
7429 20:15:23.936695 148 : 4249, 0
7430 20:15:23.936798 152 : 4250, 0
7431 20:15:23.939834 156 : 4253, 0
7432 20:15:23.939951 160 : 4250, 0
7433 20:15:23.943229 164 : 4250, 0
7434 20:15:23.943340 168 : 4253, 0
7435 20:15:23.943435 172 : 4360, 0
7436 20:15:23.946453 176 : 4250, 0
7437 20:15:23.946531 180 : 4363, 0
7438 20:15:23.949605 184 : 4255, 0
7439 20:15:23.949705 188 : 4253, 0
7440 20:15:23.949803 192 : 4250, 0
7441 20:15:23.953455 196 : 4255, 0
7442 20:15:23.953558 200 : 4250, 2
7443 20:15:23.956799 204 : 4250, 2452
7444 20:15:23.956904 208 : 4252, 4030
7445 20:15:23.959643 212 : 4250, 4027
7446 20:15:23.959748 216 : 4250, 4026
7447 20:15:23.959842 220 : 4250, 4026
7448 20:15:23.963227 224 : 4363, 4140
7449 20:15:23.963327 228 : 4360, 4138
7450 20:15:23.966465 232 : 4250, 4027
7451 20:15:23.966571 236 : 4361, 4137
7452 20:15:23.969616 240 : 4250, 4027
7453 20:15:23.969733 244 : 4252, 4027
7454 20:15:23.972986 248 : 4252, 4029
7455 20:15:23.973087 252 : 4363, 4140
7456 20:15:23.976381 256 : 4250, 4027
7457 20:15:23.976482 260 : 4250, 4027
7458 20:15:23.979758 264 : 4361, 4137
7459 20:15:23.979868 268 : 4250, 4027
7460 20:15:23.983296 272 : 4253, 4029
7461 20:15:23.983397 276 : 4360, 4138
7462 20:15:23.983491 280 : 4360, 4138
7463 20:15:23.986444 284 : 4250, 4027
7464 20:15:23.986517 288 : 4255, 4029
7465 20:15:23.989628 292 : 4250, 4027
7466 20:15:23.989728 296 : 4250, 4027
7467 20:15:23.992791 300 : 4252, 4029
7468 20:15:23.992896 304 : 4363, 4140
7469 20:15:23.996551 308 : 4250, 4027
7470 20:15:23.996652 312 : 4250, 3925
7471 20:15:23.999416 316 : 4361, 2076
7472 20:15:23.999497
7473 20:15:23.999559 MIOCK jitter meter ch=0
7474 20:15:23.999622
7475 20:15:24.002790 1T = (316-92) = 224 dly cells
7476 20:15:24.009690 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7477 20:15:24.009833 ==
7478 20:15:24.012732 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 20:15:24.016187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7480 20:15:24.016300 ==
7481 20:15:24.022620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7482 20:15:24.026237 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7483 20:15:24.029466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7484 20:15:24.036100 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7485 20:15:24.045555 [CA 0] Center 43 (13~73) winsize 61
7486 20:15:24.049033 [CA 1] Center 43 (13~73) winsize 61
7487 20:15:24.052221 [CA 2] Center 38 (8~68) winsize 61
7488 20:15:24.055477 [CA 3] Center 37 (8~67) winsize 60
7489 20:15:24.059066 [CA 4] Center 36 (6~67) winsize 62
7490 20:15:24.062314 [CA 5] Center 35 (5~65) winsize 61
7491 20:15:24.062426
7492 20:15:24.065521 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7493 20:15:24.065630
7494 20:15:24.069192 [CATrainingPosCal] consider 1 rank data
7495 20:15:24.072197 u2DelayCellTimex100 = 290/100 ps
7496 20:15:24.075981 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7497 20:15:24.082496 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7498 20:15:24.085636 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7499 20:15:24.089062 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7500 20:15:24.092411 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
7501 20:15:24.095676 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7502 20:15:24.095779
7503 20:15:24.099116 CA PerBit enable=1, Macro0, CA PI delay=35
7504 20:15:24.099214
7505 20:15:24.102725 [CBTSetCACLKResult] CA Dly = 35
7506 20:15:24.105504 CS Dly: 10 (0~41)
7507 20:15:24.109220 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7508 20:15:24.112463 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7509 20:15:24.112561 ==
7510 20:15:24.115635 Dram Type= 6, Freq= 0, CH_0, rank 1
7511 20:15:24.118771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 20:15:24.122021 ==
7513 20:15:24.125641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 20:15:24.129030 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 20:15:24.135717 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 20:15:24.138630 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 20:15:24.149229 [CA 0] Center 43 (13~73) winsize 61
7518 20:15:24.152335 [CA 1] Center 43 (13~73) winsize 61
7519 20:15:24.155793 [CA 2] Center 38 (8~68) winsize 61
7520 20:15:24.159272 [CA 3] Center 38 (8~68) winsize 61
7521 20:15:24.162341 [CA 4] Center 36 (6~66) winsize 61
7522 20:15:24.165815 [CA 5] Center 36 (6~66) winsize 61
7523 20:15:24.165922
7524 20:15:24.168930 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 20:15:24.169018
7526 20:15:24.172438 [CATrainingPosCal] consider 2 rank data
7527 20:15:24.176050 u2DelayCellTimex100 = 290/100 ps
7528 20:15:24.179167 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7529 20:15:24.185876 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7530 20:15:24.189120 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7531 20:15:24.192268 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7532 20:15:24.195703 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7533 20:15:24.199328 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7534 20:15:24.199438
7535 20:15:24.202606 CA PerBit enable=1, Macro0, CA PI delay=35
7536 20:15:24.202715
7537 20:15:24.205667 [CBTSetCACLKResult] CA Dly = 35
7538 20:15:24.209295 CS Dly: 11 (0~43)
7539 20:15:24.212310 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 20:15:24.215848 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 20:15:24.215997
7542 20:15:24.219096 ----->DramcWriteLeveling(PI) begin...
7543 20:15:24.219278 ==
7544 20:15:24.222677 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 20:15:24.225847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 20:15:24.229521 ==
7547 20:15:24.229765 Write leveling (Byte 0): 34 => 34
7548 20:15:24.232458 Write leveling (Byte 1): 30 => 30
7549 20:15:24.236015 DramcWriteLeveling(PI) end<-----
7550 20:15:24.236308
7551 20:15:24.236543 ==
7552 20:15:24.239195 Dram Type= 6, Freq= 0, CH_0, rank 0
7553 20:15:24.246179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 20:15:24.246673 ==
7555 20:15:24.247049 [Gating] SW mode calibration
7556 20:15:24.255810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7557 20:15:24.259339 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7558 20:15:24.265934 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 20:15:24.269036 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 20:15:24.272654 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7561 20:15:24.279274 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7562 20:15:24.282504 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7563 20:15:24.285707 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7564 20:15:24.292188 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 20:15:24.295796 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 20:15:24.298875 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 20:15:24.305451 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 20:15:24.309080 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
7569 20:15:24.312126 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7570 20:15:24.315831 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7571 20:15:24.322250 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7572 20:15:24.325831 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7573 20:15:24.328716 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 20:15:24.335705 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 20:15:24.338948 1 6 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7576 20:15:24.342317 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7577 20:15:24.348558 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7578 20:15:24.352196 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (1 1) (0 0)
7579 20:15:24.355361 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7580 20:15:24.362071 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 20:15:24.364881 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 20:15:24.368455 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 20:15:24.374808 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 20:15:24.378468 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 20:15:24.381536 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 20:15:24.388180 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7587 20:15:24.391248 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7588 20:15:24.394727 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 20:15:24.401368 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 20:15:24.404926 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 20:15:24.408326 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 20:15:24.414990 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 20:15:24.418326 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 20:15:24.420962 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 20:15:24.427835 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 20:15:24.431116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 20:15:24.434713 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 20:15:24.441243 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 20:15:24.444241 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 20:15:24.447799 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7601 20:15:24.454152 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 20:15:24.457740 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 20:15:24.460912 Total UI for P1: 0, mck2ui 16
7604 20:15:24.464074 best dqsien dly found for B0: ( 1, 9, 10)
7605 20:15:24.467522 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7606 20:15:24.474046 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 20:15:24.474523 Total UI for P1: 0, mck2ui 16
7608 20:15:24.480598 best dqsien dly found for B1: ( 1, 9, 18)
7609 20:15:24.484090 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7610 20:15:24.487257 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7611 20:15:24.487736
7612 20:15:24.490525 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7613 20:15:24.493652 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7614 20:15:24.496877 [Gating] SW calibration Done
7615 20:15:24.497441 ==
7616 20:15:24.500469 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 20:15:24.503908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 20:15:24.504484 ==
7619 20:15:24.507275 RX Vref Scan: 0
7620 20:15:24.507861
7621 20:15:24.510371 RX Vref 0 -> 0, step: 1
7622 20:15:24.510843
7623 20:15:24.511313 RX Delay 0 -> 252, step: 8
7624 20:15:24.516924 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7625 20:15:24.520162 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7626 20:15:24.523477 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7627 20:15:24.526872 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7628 20:15:24.530192 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7629 20:15:24.533712 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7630 20:15:24.540005 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7631 20:15:24.543248 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7632 20:15:24.546991 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7633 20:15:24.550224 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7634 20:15:24.556830 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7635 20:15:24.560138 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7636 20:15:24.563468 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7637 20:15:24.566902 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7638 20:15:24.569879 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7639 20:15:24.576882 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7640 20:15:24.577342 ==
7641 20:15:24.580373 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 20:15:24.583144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 20:15:24.583606 ==
7644 20:15:24.583971 DQS Delay:
7645 20:15:24.586550 DQS0 = 0, DQS1 = 0
7646 20:15:24.586963 DQM Delay:
7647 20:15:24.589853 DQM0 = 138, DQM1 = 126
7648 20:15:24.590313 DQ Delay:
7649 20:15:24.593315 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7650 20:15:24.596393 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7651 20:15:24.599469 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7652 20:15:24.603102 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7653 20:15:24.603515
7654 20:15:24.603919
7655 20:15:24.606015 ==
7656 20:15:24.609641 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 20:15:24.612752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 20:15:24.613169 ==
7659 20:15:24.613503
7660 20:15:24.613813
7661 20:15:24.616267 TX Vref Scan disable
7662 20:15:24.616684 == TX Byte 0 ==
7663 20:15:24.622684 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7664 20:15:24.626074 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7665 20:15:24.626493 == TX Byte 1 ==
7666 20:15:24.632584 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7667 20:15:24.635824 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7668 20:15:24.636363 ==
7669 20:15:24.639502 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 20:15:24.642957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 20:15:24.643384 ==
7672 20:15:24.655573
7673 20:15:24.659121 TX Vref early break, caculate TX vref
7674 20:15:24.662321 TX Vref=16, minBit 5, minWin=22, winSum=375
7675 20:15:24.665808 TX Vref=18, minBit 7, minWin=23, winSum=386
7676 20:15:24.668897 TX Vref=20, minBit 2, minWin=24, winSum=397
7677 20:15:24.672104 TX Vref=22, minBit 4, minWin=24, winSum=408
7678 20:15:24.675461 TX Vref=24, minBit 7, minWin=25, winSum=419
7679 20:15:24.682391 TX Vref=26, minBit 1, minWin=26, winSum=424
7680 20:15:24.685555 TX Vref=28, minBit 1, minWin=26, winSum=434
7681 20:15:24.688925 TX Vref=30, minBit 0, minWin=25, winSum=427
7682 20:15:24.692143 TX Vref=32, minBit 1, minWin=25, winSum=418
7683 20:15:24.695698 TX Vref=34, minBit 1, minWin=24, winSum=407
7684 20:15:24.702467 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
7685 20:15:24.702550
7686 20:15:24.705613 Final TX Range 0 Vref 28
7687 20:15:24.705695
7688 20:15:24.705760 ==
7689 20:15:24.708850 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 20:15:24.712150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 20:15:24.712233 ==
7692 20:15:24.712299
7693 20:15:24.712357
7694 20:15:24.715788 TX Vref Scan disable
7695 20:15:24.722172 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7696 20:15:24.722254 == TX Byte 0 ==
7697 20:15:24.725330 u2DelayCellOfst[0]=13 cells (4 PI)
7698 20:15:24.728643 u2DelayCellOfst[1]=16 cells (5 PI)
7699 20:15:24.732074 u2DelayCellOfst[2]=10 cells (3 PI)
7700 20:15:24.735342 u2DelayCellOfst[3]=13 cells (4 PI)
7701 20:15:24.738889 u2DelayCellOfst[4]=10 cells (3 PI)
7702 20:15:24.742336 u2DelayCellOfst[5]=0 cells (0 PI)
7703 20:15:24.745473 u2DelayCellOfst[6]=16 cells (5 PI)
7704 20:15:24.748728 u2DelayCellOfst[7]=16 cells (5 PI)
7705 20:15:24.752170 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7706 20:15:24.755270 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7707 20:15:24.758766 == TX Byte 1 ==
7708 20:15:24.758848 u2DelayCellOfst[8]=0 cells (0 PI)
7709 20:15:24.761935 u2DelayCellOfst[9]=0 cells (0 PI)
7710 20:15:24.765519 u2DelayCellOfst[10]=10 cells (3 PI)
7711 20:15:24.768643 u2DelayCellOfst[11]=3 cells (1 PI)
7712 20:15:24.771681 u2DelayCellOfst[12]=16 cells (5 PI)
7713 20:15:24.775060 u2DelayCellOfst[13]=13 cells (4 PI)
7714 20:15:24.778749 u2DelayCellOfst[14]=16 cells (5 PI)
7715 20:15:24.781943 u2DelayCellOfst[15]=10 cells (3 PI)
7716 20:15:24.785007 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7717 20:15:24.791897 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7718 20:15:24.791981 DramC Write-DBI on
7719 20:15:24.792046 ==
7720 20:15:24.795358 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 20:15:24.798672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 20:15:24.801666 ==
7723 20:15:24.801748
7724 20:15:24.801812
7725 20:15:24.801873 TX Vref Scan disable
7726 20:15:24.805250 == TX Byte 0 ==
7727 20:15:24.808666 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7728 20:15:24.812130 == TX Byte 1 ==
7729 20:15:24.815228 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7730 20:15:24.818925 DramC Write-DBI off
7731 20:15:24.819006
7732 20:15:24.819070 [DATLAT]
7733 20:15:24.819131 Freq=1600, CH0 RK0
7734 20:15:24.819188
7735 20:15:24.821682 DATLAT Default: 0xf
7736 20:15:24.821763 0, 0xFFFF, sum = 0
7737 20:15:24.825286 1, 0xFFFF, sum = 0
7738 20:15:24.825369 2, 0xFFFF, sum = 0
7739 20:15:24.828727 3, 0xFFFF, sum = 0
7740 20:15:24.831730 4, 0xFFFF, sum = 0
7741 20:15:24.831812 5, 0xFFFF, sum = 0
7742 20:15:24.835131 6, 0xFFFF, sum = 0
7743 20:15:24.835212 7, 0xFFFF, sum = 0
7744 20:15:24.838577 8, 0xFFFF, sum = 0
7745 20:15:24.838659 9, 0xFFFF, sum = 0
7746 20:15:24.841880 10, 0xFFFF, sum = 0
7747 20:15:24.842009 11, 0xFFFF, sum = 0
7748 20:15:24.845196 12, 0xFFFF, sum = 0
7749 20:15:24.845280 13, 0xFFFF, sum = 0
7750 20:15:24.848385 14, 0x0, sum = 1
7751 20:15:24.848467 15, 0x0, sum = 2
7752 20:15:24.851873 16, 0x0, sum = 3
7753 20:15:24.851955 17, 0x0, sum = 4
7754 20:15:24.854886 best_step = 15
7755 20:15:24.854967
7756 20:15:24.855032 ==
7757 20:15:24.858197 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 20:15:24.861584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 20:15:24.861666 ==
7760 20:15:24.865135 RX Vref Scan: 1
7761 20:15:24.865217
7762 20:15:24.865280 Set Vref Range= 24 -> 127
7763 20:15:24.865340
7764 20:15:24.868537 RX Vref 24 -> 127, step: 1
7765 20:15:24.868619
7766 20:15:24.871737 RX Delay 19 -> 252, step: 4
7767 20:15:24.871821
7768 20:15:24.874708 Set Vref, RX VrefLevel [Byte0]: 24
7769 20:15:24.878118 [Byte1]: 24
7770 20:15:24.878200
7771 20:15:24.881355 Set Vref, RX VrefLevel [Byte0]: 25
7772 20:15:24.885167 [Byte1]: 25
7773 20:15:24.885251
7774 20:15:24.888224 Set Vref, RX VrefLevel [Byte0]: 26
7775 20:15:24.891343 [Byte1]: 26
7776 20:15:24.895256
7777 20:15:24.895337 Set Vref, RX VrefLevel [Byte0]: 27
7778 20:15:24.899001 [Byte1]: 27
7779 20:15:24.903166
7780 20:15:24.903247 Set Vref, RX VrefLevel [Byte0]: 28
7781 20:15:24.906656 [Byte1]: 28
7782 20:15:24.910588
7783 20:15:24.910669 Set Vref, RX VrefLevel [Byte0]: 29
7784 20:15:24.914202 [Byte1]: 29
7785 20:15:24.918138
7786 20:15:24.918219 Set Vref, RX VrefLevel [Byte0]: 30
7787 20:15:24.921601 [Byte1]: 30
7788 20:15:24.925925
7789 20:15:24.926011 Set Vref, RX VrefLevel [Byte0]: 31
7790 20:15:24.929088 [Byte1]: 31
7791 20:15:24.933752
7792 20:15:24.933833 Set Vref, RX VrefLevel [Byte0]: 32
7793 20:15:24.936826 [Byte1]: 32
7794 20:15:24.941218
7795 20:15:24.941299 Set Vref, RX VrefLevel [Byte0]: 33
7796 20:15:24.944176 [Byte1]: 33
7797 20:15:24.948371
7798 20:15:24.948453 Set Vref, RX VrefLevel [Byte0]: 34
7799 20:15:24.951696 [Byte1]: 34
7800 20:15:24.956199
7801 20:15:24.956280 Set Vref, RX VrefLevel [Byte0]: 35
7802 20:15:24.959279 [Byte1]: 35
7803 20:15:24.963577
7804 20:15:24.963662 Set Vref, RX VrefLevel [Byte0]: 36
7805 20:15:24.967101 [Byte1]: 36
7806 20:15:24.971228
7807 20:15:24.971318 Set Vref, RX VrefLevel [Byte0]: 37
7808 20:15:24.974747 [Byte1]: 37
7809 20:15:24.979004
7810 20:15:24.979086 Set Vref, RX VrefLevel [Byte0]: 38
7811 20:15:24.981743 [Byte1]: 38
7812 20:15:24.986183
7813 20:15:24.986263 Set Vref, RX VrefLevel [Byte0]: 39
7814 20:15:24.989538 [Byte1]: 39
7815 20:15:24.994143
7816 20:15:24.994224 Set Vref, RX VrefLevel [Byte0]: 40
7817 20:15:24.997272 [Byte1]: 40
7818 20:15:25.001317
7819 20:15:25.001398 Set Vref, RX VrefLevel [Byte0]: 41
7820 20:15:25.004581 [Byte1]: 41
7821 20:15:25.008949
7822 20:15:25.009030 Set Vref, RX VrefLevel [Byte0]: 42
7823 20:15:25.012371 [Byte1]: 42
7824 20:15:25.016713
7825 20:15:25.016795 Set Vref, RX VrefLevel [Byte0]: 43
7826 20:15:25.019992 [Byte1]: 43
7827 20:15:25.024159
7828 20:15:25.024241 Set Vref, RX VrefLevel [Byte0]: 44
7829 20:15:25.027499 [Byte1]: 44
7830 20:15:25.032245
7831 20:15:25.032326 Set Vref, RX VrefLevel [Byte0]: 45
7832 20:15:25.035288 [Byte1]: 45
7833 20:15:25.039559
7834 20:15:25.039640 Set Vref, RX VrefLevel [Byte0]: 46
7835 20:15:25.042665 [Byte1]: 46
7836 20:15:25.047115
7837 20:15:25.047196 Set Vref, RX VrefLevel [Byte0]: 47
7838 20:15:25.050480 [Byte1]: 47
7839 20:15:25.054840
7840 20:15:25.054933 Set Vref, RX VrefLevel [Byte0]: 48
7841 20:15:25.057742 [Byte1]: 48
7842 20:15:25.062210
7843 20:15:25.062293 Set Vref, RX VrefLevel [Byte0]: 49
7844 20:15:25.065485 [Byte1]: 49
7845 20:15:25.069629
7846 20:15:25.069769 Set Vref, RX VrefLevel [Byte0]: 50
7847 20:15:25.073157 [Byte1]: 50
7848 20:15:25.077264
7849 20:15:25.077367 Set Vref, RX VrefLevel [Byte0]: 51
7850 20:15:25.080405 [Byte1]: 51
7851 20:15:25.084734
7852 20:15:25.084833 Set Vref, RX VrefLevel [Byte0]: 52
7853 20:15:25.088127 [Byte1]: 52
7854 20:15:25.092633
7855 20:15:25.092733 Set Vref, RX VrefLevel [Byte0]: 53
7856 20:15:25.095832 [Byte1]: 53
7857 20:15:25.099889
7858 20:15:25.099992 Set Vref, RX VrefLevel [Byte0]: 54
7859 20:15:25.103133 [Byte1]: 54
7860 20:15:25.107572
7861 20:15:25.107669 Set Vref, RX VrefLevel [Byte0]: 55
7862 20:15:25.110861 [Byte1]: 55
7863 20:15:25.114917
7864 20:15:25.114988 Set Vref, RX VrefLevel [Byte0]: 56
7865 20:15:25.118376 [Byte1]: 56
7866 20:15:25.122950
7867 20:15:25.123050 Set Vref, RX VrefLevel [Byte0]: 57
7868 20:15:25.125846 [Byte1]: 57
7869 20:15:25.130175
7870 20:15:25.130249 Set Vref, RX VrefLevel [Byte0]: 58
7871 20:15:25.133649 [Byte1]: 58
7872 20:15:25.137793
7873 20:15:25.137887 Set Vref, RX VrefLevel [Byte0]: 59
7874 20:15:25.140853 [Byte1]: 59
7875 20:15:25.145345
7876 20:15:25.145442 Set Vref, RX VrefLevel [Byte0]: 60
7877 20:15:25.148609 [Byte1]: 60
7878 20:15:25.152900
7879 20:15:25.152998 Set Vref, RX VrefLevel [Byte0]: 61
7880 20:15:25.156380 [Byte1]: 61
7881 20:15:25.160537
7882 20:15:25.160607 Set Vref, RX VrefLevel [Byte0]: 62
7883 20:15:25.163957 [Byte1]: 62
7884 20:15:25.168027
7885 20:15:25.168097 Set Vref, RX VrefLevel [Byte0]: 63
7886 20:15:25.171566 [Byte1]: 63
7887 20:15:25.175829
7888 20:15:25.175905 Set Vref, RX VrefLevel [Byte0]: 64
7889 20:15:25.178797 [Byte1]: 64
7890 20:15:25.183340
7891 20:15:25.183411 Set Vref, RX VrefLevel [Byte0]: 65
7892 20:15:25.186377 [Byte1]: 65
7893 20:15:25.191096
7894 20:15:25.191192 Set Vref, RX VrefLevel [Byte0]: 66
7895 20:15:25.194111 [Byte1]: 66
7896 20:15:25.198537
7897 20:15:25.198634 Set Vref, RX VrefLevel [Byte0]: 67
7898 20:15:25.201723 [Byte1]: 67
7899 20:15:25.205922
7900 20:15:25.206046 Set Vref, RX VrefLevel [Byte0]: 68
7901 20:15:25.209049 [Byte1]: 68
7902 20:15:25.213416
7903 20:15:25.213489 Set Vref, RX VrefLevel [Byte0]: 69
7904 20:15:25.216665 [Byte1]: 69
7905 20:15:25.220883
7906 20:15:25.220979 Set Vref, RX VrefLevel [Byte0]: 70
7907 20:15:25.224259 [Byte1]: 70
7908 20:15:25.228462
7909 20:15:25.228533 Set Vref, RX VrefLevel [Byte0]: 71
7910 20:15:25.232128 [Byte1]: 71
7911 20:15:25.236261
7912 20:15:25.236338 Set Vref, RX VrefLevel [Byte0]: 72
7913 20:15:25.239600 [Byte1]: 72
7914 20:15:25.244022
7915 20:15:25.244096 Set Vref, RX VrefLevel [Byte0]: 73
7916 20:15:25.246995 [Byte1]: 73
7917 20:15:25.251520
7918 20:15:25.251619 Set Vref, RX VrefLevel [Byte0]: 74
7919 20:15:25.254458 [Byte1]: 74
7920 20:15:25.258888
7921 20:15:25.258959 Set Vref, RX VrefLevel [Byte0]: 75
7922 20:15:25.262030 [Byte1]: 75
7923 20:15:25.266289
7924 20:15:25.266363 Set Vref, RX VrefLevel [Byte0]: 76
7925 20:15:25.269883 [Byte1]: 76
7926 20:15:25.274284
7927 20:15:25.274359 Set Vref, RX VrefLevel [Byte0]: 77
7928 20:15:25.277344 [Byte1]: 77
7929 20:15:25.281831
7930 20:15:25.281935 Set Vref, RX VrefLevel [Byte0]: 78
7931 20:15:25.284856 [Byte1]: 78
7932 20:15:25.289196
7933 20:15:25.289293 Final RX Vref Byte 0 = 61 to rank0
7934 20:15:25.292641 Final RX Vref Byte 1 = 61 to rank0
7935 20:15:25.295934 Final RX Vref Byte 0 = 61 to rank1
7936 20:15:25.299522 Final RX Vref Byte 1 = 61 to rank1==
7937 20:15:25.302695 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 20:15:25.309364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 20:15:25.309469 ==
7940 20:15:25.309561 DQS Delay:
7941 20:15:25.309649 DQS0 = 0, DQS1 = 0
7942 20:15:25.312683 DQM Delay:
7943 20:15:25.312754 DQM0 = 136, DQM1 = 123
7944 20:15:25.315794 DQ Delay:
7945 20:15:25.318961 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7946 20:15:25.322613 DQ4 =138, DQ5 =124, DQ6 =146, DQ7 =144
7947 20:15:25.325753 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7948 20:15:25.329051 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7949 20:15:25.329147
7950 20:15:25.329236
7951 20:15:25.329323
7952 20:15:25.332403 [DramC_TX_OE_Calibration] TA2
7953 20:15:25.336139 Original DQ_B0 (3 6) =30, OEN = 27
7954 20:15:25.339137 Original DQ_B1 (3 6) =30, OEN = 27
7955 20:15:25.342501 24, 0x0, End_B0=24 End_B1=24
7956 20:15:25.342606 25, 0x0, End_B0=25 End_B1=25
7957 20:15:25.345677 26, 0x0, End_B0=26 End_B1=26
7958 20:15:25.349135 27, 0x0, End_B0=27 End_B1=27
7959 20:15:25.352612 28, 0x0, End_B0=28 End_B1=28
7960 20:15:25.352716 29, 0x0, End_B0=29 End_B1=29
7961 20:15:25.355773 30, 0x0, End_B0=30 End_B1=30
7962 20:15:25.358973 31, 0x4141, End_B0=30 End_B1=30
7963 20:15:25.362285 Byte0 end_step=30 best_step=27
7964 20:15:25.365518 Byte1 end_step=30 best_step=27
7965 20:15:25.368867 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 20:15:25.372125 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 20:15:25.372228
7968 20:15:25.372321
7969 20:15:25.378720 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7970 20:15:25.382132 CH0 RK0: MR19=303, MR18=201E
7971 20:15:25.388667 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7972 20:15:25.388769
7973 20:15:25.392240 ----->DramcWriteLeveling(PI) begin...
7974 20:15:25.392337 ==
7975 20:15:25.395613 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 20:15:25.398795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 20:15:25.398895 ==
7978 20:15:25.402249 Write leveling (Byte 0): 39 => 39
7979 20:15:25.405451 Write leveling (Byte 1): 31 => 31
7980 20:15:25.408752 DramcWriteLeveling(PI) end<-----
7981 20:15:25.408823
7982 20:15:25.408888 ==
7983 20:15:25.411981 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 20:15:25.415184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 20:15:25.415260 ==
7986 20:15:25.418828 [Gating] SW mode calibration
7987 20:15:25.425444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 20:15:25.432173 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 20:15:25.435124 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 20:15:25.438662 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 20:15:25.445216 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 20:15:25.448823 1 4 12 | B1->B0 | 2625 3232 | 1 0 | (0 0) (0 0)
7993 20:15:25.452382 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 20:15:25.458784 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 20:15:25.461890 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 20:15:25.465639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 20:15:25.471749 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 20:15:25.475017 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 20:15:25.478162 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8000 20:15:25.484832 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8001 20:15:25.488275 1 5 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8002 20:15:25.491525 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 20:15:25.497963 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 20:15:25.501486 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 20:15:25.504559 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 20:15:25.511308 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 20:15:25.514590 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8008 20:15:25.517647 1 6 12 | B1->B0 | 2d2d 4141 | 0 0 | (1 1) (0 0)
8009 20:15:25.524533 1 6 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8010 20:15:25.528120 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 20:15:25.531355 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 20:15:25.537659 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 20:15:25.541287 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 20:15:25.544734 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 20:15:25.551089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 20:15:25.554702 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 20:15:25.557660 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 20:15:25.564256 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 20:15:25.567716 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 20:15:25.571024 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 20:15:25.577823 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 20:15:25.580922 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 20:15:25.584309 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 20:15:25.591066 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 20:15:25.594492 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 20:15:25.597642 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 20:15:25.604175 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 20:15:25.607527 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 20:15:25.611191 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 20:15:25.614170 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 20:15:25.620839 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 20:15:25.624053 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 20:15:25.627609 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 20:15:25.630674 Total UI for P1: 0, mck2ui 16
8035 20:15:25.634024 best dqsien dly found for B0: ( 1, 9, 12)
8036 20:15:25.641015 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 20:15:25.644511 Total UI for P1: 0, mck2ui 16
8038 20:15:25.647412 best dqsien dly found for B1: ( 1, 9, 16)
8039 20:15:25.650892 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8040 20:15:25.654339 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8041 20:15:25.654421
8042 20:15:25.657611 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8043 20:15:25.660981 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8044 20:15:25.663909 [Gating] SW calibration Done
8045 20:15:25.663991 ==
8046 20:15:25.667422 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 20:15:25.670497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 20:15:25.670580 ==
8049 20:15:25.674075 RX Vref Scan: 0
8050 20:15:25.674156
8051 20:15:25.677133 RX Vref 0 -> 0, step: 1
8052 20:15:25.677215
8053 20:15:25.677280 RX Delay 0 -> 252, step: 8
8054 20:15:25.683755 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8055 20:15:25.687316 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8056 20:15:25.690843 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8057 20:15:25.693771 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8058 20:15:25.697343 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8059 20:15:25.704120 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
8060 20:15:25.707251 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8061 20:15:25.710597 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8062 20:15:25.714159 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8063 20:15:25.717029 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8064 20:15:25.720673 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8065 20:15:25.727328 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8066 20:15:25.730622 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8067 20:15:25.734016 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8068 20:15:25.737296 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8069 20:15:25.743877 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8070 20:15:25.743960 ==
8071 20:15:25.747331 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 20:15:25.750477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 20:15:25.750560 ==
8074 20:15:25.750625 DQS Delay:
8075 20:15:25.753783 DQS0 = 0, DQS1 = 0
8076 20:15:25.753891 DQM Delay:
8077 20:15:25.756868 DQM0 = 136, DQM1 = 126
8078 20:15:25.756951 DQ Delay:
8079 20:15:25.760490 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8080 20:15:25.763788 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
8081 20:15:25.766699 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8082 20:15:25.770303 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8083 20:15:25.770385
8084 20:15:25.770450
8085 20:15:25.773741 ==
8086 20:15:25.777220 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 20:15:25.780435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 20:15:25.780518 ==
8089 20:15:25.780584
8090 20:15:25.780643
8091 20:15:25.783719 TX Vref Scan disable
8092 20:15:25.783802 == TX Byte 0 ==
8093 20:15:25.787218 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8094 20:15:25.793412 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8095 20:15:25.793495 == TX Byte 1 ==
8096 20:15:25.796984 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8097 20:15:25.803656 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8098 20:15:25.803740 ==
8099 20:15:25.806854 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 20:15:25.809853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 20:15:25.809936 ==
8102 20:15:25.824235
8103 20:15:25.827431 TX Vref early break, caculate TX vref
8104 20:15:25.830748 TX Vref=16, minBit 0, minWin=23, winSum=388
8105 20:15:25.834281 TX Vref=18, minBit 2, minWin=24, winSum=403
8106 20:15:25.837481 TX Vref=20, minBit 0, minWin=25, winSum=409
8107 20:15:25.840605 TX Vref=22, minBit 0, minWin=25, winSum=417
8108 20:15:25.844130 TX Vref=24, minBit 0, minWin=25, winSum=424
8109 20:15:25.850726 TX Vref=26, minBit 0, minWin=26, winSum=434
8110 20:15:25.854249 TX Vref=28, minBit 0, minWin=26, winSum=436
8111 20:15:25.857346 TX Vref=30, minBit 0, minWin=26, winSum=429
8112 20:15:25.860771 TX Vref=32, minBit 0, minWin=26, winSum=419
8113 20:15:25.863879 TX Vref=34, minBit 2, minWin=24, winSum=412
8114 20:15:25.870958 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 28
8115 20:15:25.871044
8116 20:15:25.874153 Final TX Range 0 Vref 28
8117 20:15:25.874237
8118 20:15:25.874303 ==
8119 20:15:25.877323 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 20:15:25.880885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 20:15:25.880968 ==
8122 20:15:25.881035
8123 20:15:25.881096
8124 20:15:25.883866 TX Vref Scan disable
8125 20:15:25.890767 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8126 20:15:25.890850 == TX Byte 0 ==
8127 20:15:25.893725 u2DelayCellOfst[0]=13 cells (4 PI)
8128 20:15:25.897139 u2DelayCellOfst[1]=20 cells (6 PI)
8129 20:15:25.900611 u2DelayCellOfst[2]=13 cells (4 PI)
8130 20:15:25.903970 u2DelayCellOfst[3]=13 cells (4 PI)
8131 20:15:25.907337 u2DelayCellOfst[4]=10 cells (3 PI)
8132 20:15:25.910545 u2DelayCellOfst[5]=0 cells (0 PI)
8133 20:15:25.913685 u2DelayCellOfst[6]=20 cells (6 PI)
8134 20:15:25.917427 u2DelayCellOfst[7]=20 cells (6 PI)
8135 20:15:25.920443 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8136 20:15:25.923627 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8137 20:15:25.927216 == TX Byte 1 ==
8138 20:15:25.927298 u2DelayCellOfst[8]=0 cells (0 PI)
8139 20:15:25.930496 u2DelayCellOfst[9]=0 cells (0 PI)
8140 20:15:25.933771 u2DelayCellOfst[10]=6 cells (2 PI)
8141 20:15:25.937195 u2DelayCellOfst[11]=3 cells (1 PI)
8142 20:15:25.940379 u2DelayCellOfst[12]=13 cells (4 PI)
8143 20:15:25.943748 u2DelayCellOfst[13]=13 cells (4 PI)
8144 20:15:25.947104 u2DelayCellOfst[14]=16 cells (5 PI)
8145 20:15:25.950594 u2DelayCellOfst[15]=10 cells (3 PI)
8146 20:15:25.953672 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8147 20:15:25.960552 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8148 20:15:25.960637 DramC Write-DBI on
8149 20:15:25.960702 ==
8150 20:15:25.963953 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 20:15:25.967578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 20:15:25.970354 ==
8153 20:15:25.970436
8154 20:15:25.970502
8155 20:15:25.970565 TX Vref Scan disable
8156 20:15:25.973882 == TX Byte 0 ==
8157 20:15:25.977059 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8158 20:15:25.980697 == TX Byte 1 ==
8159 20:15:25.983825 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8160 20:15:25.983908 DramC Write-DBI off
8161 20:15:25.987355
8162 20:15:25.987438 [DATLAT]
8163 20:15:25.987504 Freq=1600, CH0 RK1
8164 20:15:25.987566
8165 20:15:25.990351 DATLAT Default: 0xf
8166 20:15:25.990433 0, 0xFFFF, sum = 0
8167 20:15:25.993772 1, 0xFFFF, sum = 0
8168 20:15:25.993855 2, 0xFFFF, sum = 0
8169 20:15:25.997201 3, 0xFFFF, sum = 0
8170 20:15:26.000528 4, 0xFFFF, sum = 0
8171 20:15:26.000612 5, 0xFFFF, sum = 0
8172 20:15:26.003723 6, 0xFFFF, sum = 0
8173 20:15:26.003807 7, 0xFFFF, sum = 0
8174 20:15:26.007131 8, 0xFFFF, sum = 0
8175 20:15:26.007215 9, 0xFFFF, sum = 0
8176 20:15:26.010414 10, 0xFFFF, sum = 0
8177 20:15:26.010498 11, 0xFFFF, sum = 0
8178 20:15:26.013861 12, 0xFFFF, sum = 0
8179 20:15:26.013980 13, 0xFFFF, sum = 0
8180 20:15:26.017047 14, 0x0, sum = 1
8181 20:15:26.017200 15, 0x0, sum = 2
8182 20:15:26.020240 16, 0x0, sum = 3
8183 20:15:26.020323 17, 0x0, sum = 4
8184 20:15:26.023562 best_step = 15
8185 20:15:26.023645
8186 20:15:26.023710 ==
8187 20:15:26.027039 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 20:15:26.030266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 20:15:26.030350 ==
8190 20:15:26.030418 RX Vref Scan: 0
8191 20:15:26.033415
8192 20:15:26.033497 RX Vref 0 -> 0, step: 1
8193 20:15:26.033563
8194 20:15:26.036762 RX Delay 11 -> 252, step: 4
8195 20:15:26.040344 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8196 20:15:26.046654 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8197 20:15:26.050490 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8198 20:15:26.053661 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8199 20:15:26.057022 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8200 20:15:26.060146 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8201 20:15:26.066598 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8202 20:15:26.070196 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8203 20:15:26.073798 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8204 20:15:26.077005 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8205 20:15:26.080386 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8206 20:15:26.086853 iDelay=191, Bit 11, Center 118 (71 ~ 166) 96
8207 20:15:26.090241 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8208 20:15:26.093178 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8209 20:15:26.096767 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8210 20:15:26.100098 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8211 20:15:26.103153 ==
8212 20:15:26.106802 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 20:15:26.109875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 20:15:26.110023 ==
8215 20:15:26.110094 DQS Delay:
8216 20:15:26.113214 DQS0 = 0, DQS1 = 0
8217 20:15:26.113289 DQM Delay:
8218 20:15:26.116479 DQM0 = 132, DQM1 = 123
8219 20:15:26.116593 DQ Delay:
8220 20:15:26.119845 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =128
8221 20:15:26.123605 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8222 20:15:26.126466 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =118
8223 20:15:26.130117 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8224 20:15:26.130232
8225 20:15:26.130329
8226 20:15:26.130422
8227 20:15:26.133291 [DramC_TX_OE_Calibration] TA2
8228 20:15:26.136447 Original DQ_B0 (3 6) =30, OEN = 27
8229 20:15:26.139909 Original DQ_B1 (3 6) =30, OEN = 27
8230 20:15:26.143427 24, 0x0, End_B0=24 End_B1=24
8231 20:15:26.146869 25, 0x0, End_B0=25 End_B1=25
8232 20:15:26.146980 26, 0x0, End_B0=26 End_B1=26
8233 20:15:26.149887 27, 0x0, End_B0=27 End_B1=27
8234 20:15:26.153497 28, 0x0, End_B0=28 End_B1=28
8235 20:15:26.156787 29, 0x0, End_B0=29 End_B1=29
8236 20:15:26.156890 30, 0x0, End_B0=30 End_B1=30
8237 20:15:26.159888 31, 0x4141, End_B0=30 End_B1=30
8238 20:15:26.163404 Byte0 end_step=30 best_step=27
8239 20:15:26.166618 Byte1 end_step=30 best_step=27
8240 20:15:26.169801 Byte0 TX OE(2T, 0.5T) = (3, 3)
8241 20:15:26.173103 Byte1 TX OE(2T, 0.5T) = (3, 3)
8242 20:15:26.173213
8243 20:15:26.173326
8244 20:15:26.180056 [DQSOSCAuto] RK1, (LSB)MR18= 0x220e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8245 20:15:26.183329 CH0 RK1: MR19=303, MR18=220E
8246 20:15:26.189734 CH0_RK1: MR19=0x303, MR18=0x220E, DQSOSC=392, MR23=63, INC=24, DEC=16
8247 20:15:26.193338 [RxdqsGatingPostProcess] freq 1600
8248 20:15:26.196437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8249 20:15:26.199622 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 20:15:26.203106 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 20:15:26.206340 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 20:15:26.209876 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 20:15:26.212961 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 20:15:26.216161 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 20:15:26.219754 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 20:15:26.223222 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 20:15:26.226372 Pre-setting of DQS Precalculation
8258 20:15:26.229758 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8259 20:15:26.229863 ==
8260 20:15:26.232738 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 20:15:26.239503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 20:15:26.239607 ==
8263 20:15:26.242755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 20:15:26.249695 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 20:15:26.252790 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 20:15:26.259481 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 20:15:26.266851 [CA 0] Center 42 (12~72) winsize 61
8268 20:15:26.270172 [CA 1] Center 42 (12~72) winsize 61
8269 20:15:26.273949 [CA 2] Center 38 (9~68) winsize 60
8270 20:15:26.276842 [CA 3] Center 37 (8~67) winsize 60
8271 20:15:26.280320 [CA 4] Center 37 (8~67) winsize 60
8272 20:15:26.283452 [CA 5] Center 37 (7~67) winsize 61
8273 20:15:26.283551
8274 20:15:26.286773 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8275 20:15:26.286884
8276 20:15:26.290147 [CATrainingPosCal] consider 1 rank data
8277 20:15:26.293249 u2DelayCellTimex100 = 290/100 ps
8278 20:15:26.296996 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8279 20:15:26.303199 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8280 20:15:26.306840 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8281 20:15:26.310142 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8282 20:15:26.313324 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8283 20:15:26.316697 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8284 20:15:26.316769
8285 20:15:26.319929 CA PerBit enable=1, Macro0, CA PI delay=37
8286 20:15:26.319999
8287 20:15:26.323685 [CBTSetCACLKResult] CA Dly = 37
8288 20:15:26.323768 CS Dly: 8 (0~39)
8289 20:15:26.330227 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 20:15:26.333418 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 20:15:26.333487 ==
8292 20:15:26.336556 Dram Type= 6, Freq= 0, CH_1, rank 1
8293 20:15:26.339906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 20:15:26.339982 ==
8295 20:15:26.346842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 20:15:26.349997 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 20:15:26.356858 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 20:15:26.360001 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 20:15:26.369770 [CA 0] Center 42 (13~71) winsize 59
8300 20:15:26.373380 [CA 1] Center 41 (12~71) winsize 60
8301 20:15:26.376742 [CA 2] Center 38 (9~67) winsize 59
8302 20:15:26.379943 [CA 3] Center 37 (8~67) winsize 60
8303 20:15:26.383090 [CA 4] Center 37 (8~67) winsize 60
8304 20:15:26.386504 [CA 5] Center 37 (7~67) winsize 61
8305 20:15:26.386604
8306 20:15:26.389626 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 20:15:26.389729
8308 20:15:26.393304 [CATrainingPosCal] consider 2 rank data
8309 20:15:26.396462 u2DelayCellTimex100 = 290/100 ps
8310 20:15:26.400073 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8311 20:15:26.406370 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8312 20:15:26.410063 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 20:15:26.413378 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8314 20:15:26.416705 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 20:15:26.419737 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8316 20:15:26.419843
8317 20:15:26.422985 CA PerBit enable=1, Macro0, CA PI delay=37
8318 20:15:26.423087
8319 20:15:26.426305 [CBTSetCACLKResult] CA Dly = 37
8320 20:15:26.429825 CS Dly: 9 (0~41)
8321 20:15:26.432890 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 20:15:26.436285 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 20:15:26.436402
8324 20:15:26.439700 ----->DramcWriteLeveling(PI) begin...
8325 20:15:26.439817 ==
8326 20:15:26.442752 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 20:15:26.446611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 20:15:26.449509 ==
8329 20:15:26.449606 Write leveling (Byte 0): 23 => 23
8330 20:15:26.452990 Write leveling (Byte 1): 28 => 28
8331 20:15:26.456644 DramcWriteLeveling(PI) end<-----
8332 20:15:26.456744
8333 20:15:26.456834 ==
8334 20:15:26.459475 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 20:15:26.466105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 20:15:26.466182 ==
8337 20:15:26.469477 [Gating] SW mode calibration
8338 20:15:26.475993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8339 20:15:26.479270 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8340 20:15:26.486231 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 20:15:26.489455 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 20:15:26.492922 1 4 8 | B1->B0 | 2f2f 3232 | 1 0 | (1 1) (0 0)
8343 20:15:26.496319 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 20:15:26.502639 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 20:15:26.506055 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 20:15:26.509396 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 20:15:26.516040 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 20:15:26.519128 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 20:15:26.522550 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8350 20:15:26.529076 1 5 8 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (1 0)
8351 20:15:26.532569 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 20:15:26.535859 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 20:15:26.542462 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 20:15:26.545877 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 20:15:26.549164 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 20:15:26.556073 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 20:15:26.559204 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8358 20:15:26.562404 1 6 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
8359 20:15:26.569305 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 20:15:26.572738 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 20:15:26.576213 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 20:15:26.582356 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 20:15:26.585838 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 20:15:26.589030 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 20:15:26.595481 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8366 20:15:26.599353 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8367 20:15:26.602314 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8368 20:15:26.609165 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 20:15:26.612171 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 20:15:26.615684 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 20:15:26.622393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 20:15:26.625751 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 20:15:26.629147 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 20:15:26.635557 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 20:15:26.638716 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 20:15:26.641786 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 20:15:26.648532 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 20:15:26.652136 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 20:15:26.655153 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 20:15:26.662190 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 20:15:26.665169 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8382 20:15:26.668924 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8383 20:15:26.675191 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8384 20:15:26.675308 Total UI for P1: 0, mck2ui 16
8385 20:15:26.678375 best dqsien dly found for B0: ( 1, 9, 6)
8386 20:15:26.685019 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 20:15:26.688445 Total UI for P1: 0, mck2ui 16
8388 20:15:26.691431 best dqsien dly found for B1: ( 1, 9, 12)
8389 20:15:26.695096 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8390 20:15:26.698123 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8391 20:15:26.698232
8392 20:15:26.701907 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8393 20:15:26.704956 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8394 20:15:26.708422 [Gating] SW calibration Done
8395 20:15:26.708520 ==
8396 20:15:26.711464 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 20:15:26.714922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 20:15:26.715032 ==
8399 20:15:26.718473 RX Vref Scan: 0
8400 20:15:26.718574
8401 20:15:26.721268 RX Vref 0 -> 0, step: 1
8402 20:15:26.721349
8403 20:15:26.721409 RX Delay 0 -> 252, step: 8
8404 20:15:26.728064 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8405 20:15:26.731333 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8406 20:15:26.734623 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8407 20:15:26.737762 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8408 20:15:26.741379 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8409 20:15:26.747777 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8410 20:15:26.751151 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8411 20:15:26.754294 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8412 20:15:26.757843 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8413 20:15:26.761101 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8414 20:15:26.767461 iDelay=200, Bit 10, Center 135 (88 ~ 183) 96
8415 20:15:26.770967 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8416 20:15:26.774387 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8417 20:15:26.777512 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8418 20:15:26.781252 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8419 20:15:26.787709 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8420 20:15:26.787820 ==
8421 20:15:26.791042 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 20:15:26.794210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 20:15:26.794304 ==
8424 20:15:26.794403 DQS Delay:
8425 20:15:26.797783 DQS0 = 0, DQS1 = 0
8426 20:15:26.797881 DQM Delay:
8427 20:15:26.801211 DQM0 = 136, DQM1 = 131
8428 20:15:26.801319 DQ Delay:
8429 20:15:26.804226 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8430 20:15:26.808061 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8431 20:15:26.810668 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8432 20:15:26.814113 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8433 20:15:26.814215
8434 20:15:26.814310
8435 20:15:26.817313 ==
8436 20:15:26.820883 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 20:15:26.824431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 20:15:26.824547 ==
8439 20:15:26.824640
8440 20:15:26.824746
8441 20:15:26.827594 TX Vref Scan disable
8442 20:15:26.827695 == TX Byte 0 ==
8443 20:15:26.830771 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8444 20:15:26.837437 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8445 20:15:26.837557 == TX Byte 1 ==
8446 20:15:26.840877 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 20:15:26.847532 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 20:15:26.847617 ==
8449 20:15:26.850522 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 20:15:26.853765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 20:15:26.853874 ==
8452 20:15:26.867203
8453 20:15:26.870617 TX Vref early break, caculate TX vref
8454 20:15:26.874051 TX Vref=16, minBit 8, minWin=21, winSum=363
8455 20:15:26.877387 TX Vref=18, minBit 10, minWin=21, winSum=375
8456 20:15:26.880861 TX Vref=20, minBit 10, minWin=22, winSum=391
8457 20:15:26.883922 TX Vref=22, minBit 9, minWin=24, winSum=398
8458 20:15:26.887163 TX Vref=24, minBit 8, minWin=24, winSum=403
8459 20:15:26.893905 TX Vref=26, minBit 10, minWin=24, winSum=412
8460 20:15:26.897182 TX Vref=28, minBit 10, minWin=24, winSum=419
8461 20:15:26.900386 TX Vref=30, minBit 8, minWin=25, winSum=413
8462 20:15:26.903835 TX Vref=32, minBit 8, minWin=24, winSum=403
8463 20:15:26.907086 TX Vref=34, minBit 10, minWin=23, winSum=396
8464 20:15:26.913775 [TxChooseVref] Worse bit 8, Min win 25, Win sum 413, Final Vref 30
8465 20:15:26.913857
8466 20:15:26.917060 Final TX Range 0 Vref 30
8467 20:15:26.917141
8468 20:15:26.917206 ==
8469 20:15:26.920518 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 20:15:26.923507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 20:15:26.923589 ==
8472 20:15:26.923654
8473 20:15:26.923712
8474 20:15:26.927053 TX Vref Scan disable
8475 20:15:26.933796 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8476 20:15:26.933881 == TX Byte 0 ==
8477 20:15:26.936766 u2DelayCellOfst[0]=16 cells (5 PI)
8478 20:15:26.940515 u2DelayCellOfst[1]=10 cells (3 PI)
8479 20:15:26.943606 u2DelayCellOfst[2]=0 cells (0 PI)
8480 20:15:26.946950 u2DelayCellOfst[3]=6 cells (2 PI)
8481 20:15:26.950470 u2DelayCellOfst[4]=6 cells (2 PI)
8482 20:15:26.953656 u2DelayCellOfst[5]=16 cells (5 PI)
8483 20:15:26.957225 u2DelayCellOfst[6]=16 cells (5 PI)
8484 20:15:26.960411 u2DelayCellOfst[7]=6 cells (2 PI)
8485 20:15:26.963601 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8486 20:15:26.966904 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8487 20:15:26.970494 == TX Byte 1 ==
8488 20:15:26.970576 u2DelayCellOfst[8]=0 cells (0 PI)
8489 20:15:26.973410 u2DelayCellOfst[9]=3 cells (1 PI)
8490 20:15:26.976853 u2DelayCellOfst[10]=13 cells (4 PI)
8491 20:15:26.980345 u2DelayCellOfst[11]=3 cells (1 PI)
8492 20:15:26.983489 u2DelayCellOfst[12]=16 cells (5 PI)
8493 20:15:26.986605 u2DelayCellOfst[13]=20 cells (6 PI)
8494 20:15:26.989841 u2DelayCellOfst[14]=20 cells (6 PI)
8495 20:15:26.993125 u2DelayCellOfst[15]=16 cells (5 PI)
8496 20:15:26.996672 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8497 20:15:27.003223 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8498 20:15:27.003307 DramC Write-DBI on
8499 20:15:27.003374 ==
8500 20:15:27.006624 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 20:15:27.009823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 20:15:27.013085 ==
8503 20:15:27.013168
8504 20:15:27.013233
8505 20:15:27.013293 TX Vref Scan disable
8506 20:15:27.017252 == TX Byte 0 ==
8507 20:15:27.020124 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8508 20:15:27.023647 == TX Byte 1 ==
8509 20:15:27.026894 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8510 20:15:27.030096 DramC Write-DBI off
8511 20:15:27.030178
8512 20:15:27.030244 [DATLAT]
8513 20:15:27.030308 Freq=1600, CH1 RK0
8514 20:15:27.030369
8515 20:15:27.033478 DATLAT Default: 0xf
8516 20:15:27.033561 0, 0xFFFF, sum = 0
8517 20:15:27.036953 1, 0xFFFF, sum = 0
8518 20:15:27.037037 2, 0xFFFF, sum = 0
8519 20:15:27.040376 3, 0xFFFF, sum = 0
8520 20:15:27.043258 4, 0xFFFF, sum = 0
8521 20:15:27.043349 5, 0xFFFF, sum = 0
8522 20:15:27.046856 6, 0xFFFF, sum = 0
8523 20:15:27.046942 7, 0xFFFF, sum = 0
8524 20:15:27.050305 8, 0xFFFF, sum = 0
8525 20:15:27.050380 9, 0xFFFF, sum = 0
8526 20:15:27.053299 10, 0xFFFF, sum = 0
8527 20:15:27.053388 11, 0xFFFF, sum = 0
8528 20:15:27.056751 12, 0xFFFF, sum = 0
8529 20:15:27.056831 13, 0xFFFF, sum = 0
8530 20:15:27.060044 14, 0x0, sum = 1
8531 20:15:27.060120 15, 0x0, sum = 2
8532 20:15:27.063422 16, 0x0, sum = 3
8533 20:15:27.063504 17, 0x0, sum = 4
8534 20:15:27.066836 best_step = 15
8535 20:15:27.066920
8536 20:15:27.066983 ==
8537 20:15:27.070094 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 20:15:27.073258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 20:15:27.073337 ==
8540 20:15:27.073401 RX Vref Scan: 1
8541 20:15:27.076627
8542 20:15:27.076703 Set Vref Range= 24 -> 127
8543 20:15:27.076766
8544 20:15:27.080175 RX Vref 24 -> 127, step: 1
8545 20:15:27.080252
8546 20:15:27.083422 RX Delay 19 -> 252, step: 4
8547 20:15:27.083496
8548 20:15:27.086790 Set Vref, RX VrefLevel [Byte0]: 24
8549 20:15:27.089845 [Byte1]: 24
8550 20:15:27.089917
8551 20:15:27.093124 Set Vref, RX VrefLevel [Byte0]: 25
8552 20:15:27.096824 [Byte1]: 25
8553 20:15:27.096898
8554 20:15:27.099853 Set Vref, RX VrefLevel [Byte0]: 26
8555 20:15:27.103278 [Byte1]: 26
8556 20:15:27.107198
8557 20:15:27.107324 Set Vref, RX VrefLevel [Byte0]: 27
8558 20:15:27.110342 [Byte1]: 27
8559 20:15:27.114650
8560 20:15:27.114729 Set Vref, RX VrefLevel [Byte0]: 28
8561 20:15:27.117808 [Byte1]: 28
8562 20:15:27.122449
8563 20:15:27.122531 Set Vref, RX VrefLevel [Byte0]: 29
8564 20:15:27.125635 [Byte1]: 29
8565 20:15:27.129888
8566 20:15:27.129993 Set Vref, RX VrefLevel [Byte0]: 30
8567 20:15:27.132846 [Byte1]: 30
8568 20:15:27.137580
8569 20:15:27.137654 Set Vref, RX VrefLevel [Byte0]: 31
8570 20:15:27.140408 [Byte1]: 31
8571 20:15:27.144796
8572 20:15:27.144880 Set Vref, RX VrefLevel [Byte0]: 32
8573 20:15:27.148199 [Byte1]: 32
8574 20:15:27.152447
8575 20:15:27.152519 Set Vref, RX VrefLevel [Byte0]: 33
8576 20:15:27.155803 [Byte1]: 33
8577 20:15:27.160294
8578 20:15:27.160369 Set Vref, RX VrefLevel [Byte0]: 34
8579 20:15:27.163581 [Byte1]: 34
8580 20:15:27.167625
8581 20:15:27.167698 Set Vref, RX VrefLevel [Byte0]: 35
8582 20:15:27.170815 [Byte1]: 35
8583 20:15:27.175325
8584 20:15:27.175408 Set Vref, RX VrefLevel [Byte0]: 36
8585 20:15:27.178576 [Byte1]: 36
8586 20:15:27.183054
8587 20:15:27.183134 Set Vref, RX VrefLevel [Byte0]: 37
8588 20:15:27.186171 [Byte1]: 37
8589 20:15:27.190359
8590 20:15:27.190440 Set Vref, RX VrefLevel [Byte0]: 38
8591 20:15:27.194169 [Byte1]: 38
8592 20:15:27.197961
8593 20:15:27.198056 Set Vref, RX VrefLevel [Byte0]: 39
8594 20:15:27.201497 [Byte1]: 39
8595 20:15:27.205677
8596 20:15:27.205758 Set Vref, RX VrefLevel [Byte0]: 40
8597 20:15:27.208716 [Byte1]: 40
8598 20:15:27.213426
8599 20:15:27.213506 Set Vref, RX VrefLevel [Byte0]: 41
8600 20:15:27.216551 [Byte1]: 41
8601 20:15:27.220828
8602 20:15:27.220908 Set Vref, RX VrefLevel [Byte0]: 42
8603 20:15:27.224064 [Byte1]: 42
8604 20:15:27.228171
8605 20:15:27.228251 Set Vref, RX VrefLevel [Byte0]: 43
8606 20:15:27.231787 [Byte1]: 43
8607 20:15:27.235995
8608 20:15:27.236076 Set Vref, RX VrefLevel [Byte0]: 44
8609 20:15:27.238895 [Byte1]: 44
8610 20:15:27.243292
8611 20:15:27.243374 Set Vref, RX VrefLevel [Byte0]: 45
8612 20:15:27.246773 [Byte1]: 45
8613 20:15:27.250809
8614 20:15:27.250890 Set Vref, RX VrefLevel [Byte0]: 46
8615 20:15:27.254104 [Byte1]: 46
8616 20:15:27.258772
8617 20:15:27.258854 Set Vref, RX VrefLevel [Byte0]: 47
8618 20:15:27.262070 [Byte1]: 47
8619 20:15:27.266330
8620 20:15:27.266412 Set Vref, RX VrefLevel [Byte0]: 48
8621 20:15:27.269324 [Byte1]: 48
8622 20:15:27.273862
8623 20:15:27.273985 Set Vref, RX VrefLevel [Byte0]: 49
8624 20:15:27.277220 [Byte1]: 49
8625 20:15:27.281181
8626 20:15:27.281262 Set Vref, RX VrefLevel [Byte0]: 50
8627 20:15:27.284593 [Byte1]: 50
8628 20:15:27.288921
8629 20:15:27.289004 Set Vref, RX VrefLevel [Byte0]: 51
8630 20:15:27.292074 [Byte1]: 51
8631 20:15:27.296428
8632 20:15:27.296510 Set Vref, RX VrefLevel [Byte0]: 52
8633 20:15:27.299994 [Byte1]: 52
8634 20:15:27.304082
8635 20:15:27.304164 Set Vref, RX VrefLevel [Byte0]: 53
8636 20:15:27.307342 [Byte1]: 53
8637 20:15:27.311578
8638 20:15:27.311660 Set Vref, RX VrefLevel [Byte0]: 54
8639 20:15:27.315032 [Byte1]: 54
8640 20:15:27.319534
8641 20:15:27.319615 Set Vref, RX VrefLevel [Byte0]: 55
8642 20:15:27.322563 [Byte1]: 55
8643 20:15:27.326605
8644 20:15:27.326690 Set Vref, RX VrefLevel [Byte0]: 56
8645 20:15:27.330302 [Byte1]: 56
8646 20:15:27.334368
8647 20:15:27.334450 Set Vref, RX VrefLevel [Byte0]: 57
8648 20:15:27.337442 [Byte1]: 57
8649 20:15:27.341830
8650 20:15:27.341912 Set Vref, RX VrefLevel [Byte0]: 58
8651 20:15:27.345144 [Byte1]: 58
8652 20:15:27.349480
8653 20:15:27.349562 Set Vref, RX VrefLevel [Byte0]: 59
8654 20:15:27.352622 [Byte1]: 59
8655 20:15:27.357078
8656 20:15:27.357163 Set Vref, RX VrefLevel [Byte0]: 60
8657 20:15:27.360234 [Byte1]: 60
8658 20:15:27.365024
8659 20:15:27.365100 Set Vref, RX VrefLevel [Byte0]: 61
8660 20:15:27.367763 [Byte1]: 61
8661 20:15:27.372263
8662 20:15:27.372334 Set Vref, RX VrefLevel [Byte0]: 62
8663 20:15:27.375317 [Byte1]: 62
8664 20:15:27.379833
8665 20:15:27.379912 Set Vref, RX VrefLevel [Byte0]: 63
8666 20:15:27.382861 [Byte1]: 63
8667 20:15:27.387230
8668 20:15:27.387305 Set Vref, RX VrefLevel [Byte0]: 64
8669 20:15:27.390565 [Byte1]: 64
8670 20:15:27.394693
8671 20:15:27.394774 Set Vref, RX VrefLevel [Byte0]: 65
8672 20:15:27.398274 [Byte1]: 65
8673 20:15:27.402252
8674 20:15:27.402330 Set Vref, RX VrefLevel [Byte0]: 66
8675 20:15:27.405818 [Byte1]: 66
8676 20:15:27.410215
8677 20:15:27.410292 Set Vref, RX VrefLevel [Byte0]: 67
8678 20:15:27.413130 [Byte1]: 67
8679 20:15:27.417654
8680 20:15:27.417761 Set Vref, RX VrefLevel [Byte0]: 68
8681 20:15:27.420664 [Byte1]: 68
8682 20:15:27.425186
8683 20:15:27.425268 Set Vref, RX VrefLevel [Byte0]: 69
8684 20:15:27.428636 [Byte1]: 69
8685 20:15:27.432711
8686 20:15:27.432792 Set Vref, RX VrefLevel [Byte0]: 70
8687 20:15:27.435975 [Byte1]: 70
8688 20:15:27.440321
8689 20:15:27.440402 Set Vref, RX VrefLevel [Byte0]: 71
8690 20:15:27.443449 [Byte1]: 71
8691 20:15:27.447950
8692 20:15:27.448061 Final RX Vref Byte 0 = 57 to rank0
8693 20:15:27.450972 Final RX Vref Byte 1 = 61 to rank0
8694 20:15:27.454353 Final RX Vref Byte 0 = 57 to rank1
8695 20:15:27.457671 Final RX Vref Byte 1 = 61 to rank1==
8696 20:15:27.461277 Dram Type= 6, Freq= 0, CH_1, rank 0
8697 20:15:27.467911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8698 20:15:27.467995 ==
8699 20:15:27.468061 DQS Delay:
8700 20:15:27.468121 DQS0 = 0, DQS1 = 0
8701 20:15:27.471339 DQM Delay:
8702 20:15:27.471419 DQM0 = 134, DQM1 = 129
8703 20:15:27.474521 DQ Delay:
8704 20:15:27.477735 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8705 20:15:27.481211 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8706 20:15:27.484222 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8707 20:15:27.487717 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8708 20:15:27.487798
8709 20:15:27.487863
8710 20:15:27.487922
8711 20:15:27.491089 [DramC_TX_OE_Calibration] TA2
8712 20:15:27.494241 Original DQ_B0 (3 6) =30, OEN = 27
8713 20:15:27.497656 Original DQ_B1 (3 6) =30, OEN = 27
8714 20:15:27.500748 24, 0x0, End_B0=24 End_B1=24
8715 20:15:27.500830 25, 0x0, End_B0=25 End_B1=25
8716 20:15:27.504448 26, 0x0, End_B0=26 End_B1=26
8717 20:15:27.507615 27, 0x0, End_B0=27 End_B1=27
8718 20:15:27.510958 28, 0x0, End_B0=28 End_B1=28
8719 20:15:27.514075 29, 0x0, End_B0=29 End_B1=29
8720 20:15:27.514157 30, 0x0, End_B0=30 End_B1=30
8721 20:15:27.517484 31, 0x4141, End_B0=30 End_B1=30
8722 20:15:27.521077 Byte0 end_step=30 best_step=27
8723 20:15:27.524168 Byte1 end_step=30 best_step=27
8724 20:15:27.527529 Byte0 TX OE(2T, 0.5T) = (3, 3)
8725 20:15:27.531010 Byte1 TX OE(2T, 0.5T) = (3, 3)
8726 20:15:27.531091
8727 20:15:27.531156
8728 20:15:27.538029 [DQSOSCAuto] RK0, (LSB)MR18= 0x1625, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8729 20:15:27.540908 CH1 RK0: MR19=303, MR18=1625
8730 20:15:27.547659 CH1_RK0: MR19=0x303, MR18=0x1625, DQSOSC=391, MR23=63, INC=24, DEC=16
8731 20:15:27.547741
8732 20:15:27.550920 ----->DramcWriteLeveling(PI) begin...
8733 20:15:27.551002 ==
8734 20:15:27.553863 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 20:15:27.557419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 20:15:27.557501 ==
8737 20:15:27.560790 Write leveling (Byte 0): 23 => 23
8738 20:15:27.563895 Write leveling (Byte 1): 29 => 29
8739 20:15:27.567191 DramcWriteLeveling(PI) end<-----
8740 20:15:27.567273
8741 20:15:27.567337 ==
8742 20:15:27.570844 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 20:15:27.573890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 20:15:27.573992 ==
8745 20:15:27.577079 [Gating] SW mode calibration
8746 20:15:27.583804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8747 20:15:27.590321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8748 20:15:27.594077 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 20:15:27.597057 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 20:15:27.604041 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8751 20:15:27.607391 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 1)
8752 20:15:27.610463 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 20:15:27.617249 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 20:15:27.620594 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 20:15:27.623877 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 20:15:27.630395 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 20:15:27.633725 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8758 20:15:27.637223 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8759 20:15:27.644091 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 1)
8760 20:15:27.647245 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 20:15:27.650513 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 20:15:27.657289 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 20:15:27.660517 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 20:15:27.663729 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 20:15:27.670763 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8766 20:15:27.673741 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8767 20:15:27.677220 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8768 20:15:27.684042 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 20:15:27.687142 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 20:15:27.690247 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 20:15:27.697120 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 20:15:27.700442 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 20:15:27.703456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 20:15:27.707387 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8775 20:15:27.713923 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8776 20:15:27.717194 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 20:15:27.720403 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 20:15:27.727117 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 20:15:27.730150 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 20:15:27.733411 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 20:15:27.740110 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 20:15:27.743745 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 20:15:27.747189 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 20:15:27.753339 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 20:15:27.757040 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 20:15:27.760389 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 20:15:27.766745 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 20:15:27.770157 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 20:15:27.773549 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 20:15:27.780130 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8791 20:15:27.783634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8792 20:15:27.786462 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 20:15:27.789805 Total UI for P1: 0, mck2ui 16
8794 20:15:27.793105 best dqsien dly found for B0: ( 1, 9, 10)
8795 20:15:27.796663 Total UI for P1: 0, mck2ui 16
8796 20:15:27.799844 best dqsien dly found for B1: ( 1, 9, 10)
8797 20:15:27.803091 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8798 20:15:27.806849 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8799 20:15:27.806928
8800 20:15:27.813150 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8801 20:15:27.816360 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8802 20:15:27.819811 [Gating] SW calibration Done
8803 20:15:27.819892 ==
8804 20:15:27.823014 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 20:15:27.826591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 20:15:27.826667 ==
8807 20:15:27.826730 RX Vref Scan: 0
8808 20:15:27.826789
8809 20:15:27.829800 RX Vref 0 -> 0, step: 1
8810 20:15:27.829870
8811 20:15:27.833099 RX Delay 0 -> 252, step: 8
8812 20:15:27.836672 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8813 20:15:27.840019 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8814 20:15:27.842861 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8815 20:15:27.849641 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8816 20:15:27.852925 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8817 20:15:27.856386 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8818 20:15:27.859695 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8819 20:15:27.863035 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8820 20:15:27.869832 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8821 20:15:27.873006 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8822 20:15:27.876086 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8823 20:15:27.879576 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8824 20:15:27.882904 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8825 20:15:27.889762 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8826 20:15:27.892925 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8827 20:15:27.896358 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8828 20:15:27.896442 ==
8829 20:15:27.899602 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 20:15:27.903121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 20:15:27.906286 ==
8832 20:15:27.906372 DQS Delay:
8833 20:15:27.906438 DQS0 = 0, DQS1 = 0
8834 20:15:27.909455 DQM Delay:
8835 20:15:27.909538 DQM0 = 136, DQM1 = 132
8836 20:15:27.912955 DQ Delay:
8837 20:15:27.916240 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8838 20:15:27.919484 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8839 20:15:27.922656 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8840 20:15:27.925873 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8841 20:15:27.925992
8842 20:15:27.926059
8843 20:15:27.926120 ==
8844 20:15:27.929136 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 20:15:27.932623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 20:15:27.932706 ==
8847 20:15:27.932772
8848 20:15:27.936269
8849 20:15:27.936352 TX Vref Scan disable
8850 20:15:27.939559 == TX Byte 0 ==
8851 20:15:27.942602 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8852 20:15:27.945993 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8853 20:15:27.949302 == TX Byte 1 ==
8854 20:15:27.952374 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8855 20:15:27.955627 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8856 20:15:27.955732 ==
8857 20:15:27.958981 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 20:15:27.965462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 20:15:27.965569 ==
8860 20:15:27.978846
8861 20:15:27.982434 TX Vref early break, caculate TX vref
8862 20:15:27.985416 TX Vref=16, minBit 10, minWin=21, winSum=377
8863 20:15:27.988895 TX Vref=18, minBit 8, minWin=23, winSum=390
8864 20:15:27.992424 TX Vref=20, minBit 8, minWin=23, winSum=393
8865 20:15:27.995413 TX Vref=22, minBit 9, minWin=22, winSum=402
8866 20:15:27.998901 TX Vref=24, minBit 9, minWin=24, winSum=409
8867 20:15:28.005400 TX Vref=26, minBit 9, minWin=24, winSum=416
8868 20:15:28.008813 TX Vref=28, minBit 9, minWin=24, winSum=413
8869 20:15:28.012283 TX Vref=30, minBit 8, minWin=24, winSum=408
8870 20:15:28.015348 TX Vref=32, minBit 8, minWin=24, winSum=402
8871 20:15:28.018392 TX Vref=34, minBit 8, minWin=23, winSum=395
8872 20:15:28.021641 TX Vref=36, minBit 8, minWin=22, winSum=388
8873 20:15:28.028550 [TxChooseVref] Worse bit 9, Min win 24, Win sum 416, Final Vref 26
8874 20:15:28.028655
8875 20:15:28.031841 Final TX Range 0 Vref 26
8876 20:15:28.031941
8877 20:15:28.032031 ==
8878 20:15:28.035077 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 20:15:28.038814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 20:15:28.038911 ==
8881 20:15:28.039003
8882 20:15:28.041730
8883 20:15:28.041822 TX Vref Scan disable
8884 20:15:28.048181 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8885 20:15:28.048287 == TX Byte 0 ==
8886 20:15:28.051538 u2DelayCellOfst[0]=16 cells (5 PI)
8887 20:15:28.054837 u2DelayCellOfst[1]=6 cells (2 PI)
8888 20:15:28.058257 u2DelayCellOfst[2]=0 cells (0 PI)
8889 20:15:28.061395 u2DelayCellOfst[3]=3 cells (1 PI)
8890 20:15:28.064894 u2DelayCellOfst[4]=6 cells (2 PI)
8891 20:15:28.068431 u2DelayCellOfst[5]=16 cells (5 PI)
8892 20:15:28.071443 u2DelayCellOfst[6]=16 cells (5 PI)
8893 20:15:28.075166 u2DelayCellOfst[7]=3 cells (1 PI)
8894 20:15:28.078234 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8895 20:15:28.081804 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8896 20:15:28.084858 == TX Byte 1 ==
8897 20:15:28.088420 u2DelayCellOfst[8]=0 cells (0 PI)
8898 20:15:28.088490 u2DelayCellOfst[9]=6 cells (2 PI)
8899 20:15:28.091917 u2DelayCellOfst[10]=10 cells (3 PI)
8900 20:15:28.094791 u2DelayCellOfst[11]=6 cells (2 PI)
8901 20:15:28.098102 u2DelayCellOfst[12]=13 cells (4 PI)
8902 20:15:28.101557 u2DelayCellOfst[13]=20 cells (6 PI)
8903 20:15:28.104994 u2DelayCellOfst[14]=23 cells (7 PI)
8904 20:15:28.108315 u2DelayCellOfst[15]=20 cells (6 PI)
8905 20:15:28.111663 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8906 20:15:28.118691 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8907 20:15:28.118786 DramC Write-DBI on
8908 20:15:28.118863 ==
8909 20:15:28.121890 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 20:15:28.128541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 20:15:28.128690 ==
8912 20:15:28.128818
8913 20:15:28.128939
8914 20:15:28.129057 TX Vref Scan disable
8915 20:15:28.132116 == TX Byte 0 ==
8916 20:15:28.135275 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8917 20:15:28.138754 == TX Byte 1 ==
8918 20:15:28.141750 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8919 20:15:28.145440 DramC Write-DBI off
8920 20:15:28.145549
8921 20:15:28.145649 [DATLAT]
8922 20:15:28.145784 Freq=1600, CH1 RK1
8923 20:15:28.145875
8924 20:15:28.148961 DATLAT Default: 0xf
8925 20:15:28.149061 0, 0xFFFF, sum = 0
8926 20:15:28.152268 1, 0xFFFF, sum = 0
8927 20:15:28.152341 2, 0xFFFF, sum = 0
8928 20:15:28.155515 3, 0xFFFF, sum = 0
8929 20:15:28.158773 4, 0xFFFF, sum = 0
8930 20:15:28.158858 5, 0xFFFF, sum = 0
8931 20:15:28.161821 6, 0xFFFF, sum = 0
8932 20:15:28.161931 7, 0xFFFF, sum = 0
8933 20:15:28.165547 8, 0xFFFF, sum = 0
8934 20:15:28.165635 9, 0xFFFF, sum = 0
8935 20:15:28.168860 10, 0xFFFF, sum = 0
8936 20:15:28.168949 11, 0xFFFF, sum = 0
8937 20:15:28.171888 12, 0xFFFF, sum = 0
8938 20:15:28.171984 13, 0xFFFF, sum = 0
8939 20:15:28.175146 14, 0x0, sum = 1
8940 20:15:28.175249 15, 0x0, sum = 2
8941 20:15:28.178721 16, 0x0, sum = 3
8942 20:15:28.178825 17, 0x0, sum = 4
8943 20:15:28.181763 best_step = 15
8944 20:15:28.181873
8945 20:15:28.181973 ==
8946 20:15:28.185001 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 20:15:28.188477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 20:15:28.188600 ==
8949 20:15:28.191970 RX Vref Scan: 0
8950 20:15:28.192104
8951 20:15:28.192211 RX Vref 0 -> 0, step: 1
8952 20:15:28.192313
8953 20:15:28.195356 RX Delay 19 -> 252, step: 4
8954 20:15:28.198600 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8955 20:15:28.205175 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8956 20:15:28.208694 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8957 20:15:28.211987 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8958 20:15:28.215445 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8959 20:15:28.218720 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8960 20:15:28.222127 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8961 20:15:28.228670 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8962 20:15:28.232004 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8963 20:15:28.235367 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8964 20:15:28.238473 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8965 20:15:28.241867 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8966 20:15:28.248727 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8967 20:15:28.252296 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8968 20:15:28.255365 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8969 20:15:28.258785 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8970 20:15:28.259326 ==
8971 20:15:28.261811 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 20:15:28.268783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 20:15:28.269249 ==
8974 20:15:28.269646 DQS Delay:
8975 20:15:28.271842 DQS0 = 0, DQS1 = 0
8976 20:15:28.272323 DQM Delay:
8977 20:15:28.274931 DQM0 = 133, DQM1 = 130
8978 20:15:28.275543 DQ Delay:
8979 20:15:28.278472 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8980 20:15:28.281794 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8981 20:15:28.284846 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =126
8982 20:15:28.288530 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
8983 20:15:28.289009
8984 20:15:28.289400
8985 20:15:28.289744
8986 20:15:28.291575 [DramC_TX_OE_Calibration] TA2
8987 20:15:28.295124 Original DQ_B0 (3 6) =30, OEN = 27
8988 20:15:28.298248 Original DQ_B1 (3 6) =30, OEN = 27
8989 20:15:28.301694 24, 0x0, End_B0=24 End_B1=24
8990 20:15:28.304911 25, 0x0, End_B0=25 End_B1=25
8991 20:15:28.305414 26, 0x0, End_B0=26 End_B1=26
8992 20:15:28.308306 27, 0x0, End_B0=27 End_B1=27
8993 20:15:28.311826 28, 0x0, End_B0=28 End_B1=28
8994 20:15:28.314791 29, 0x0, End_B0=29 End_B1=29
8995 20:15:28.315293 30, 0x0, End_B0=30 End_B1=30
8996 20:15:28.318076 31, 0x4545, End_B0=30 End_B1=30
8997 20:15:28.321312 Byte0 end_step=30 best_step=27
8998 20:15:28.324985 Byte1 end_step=30 best_step=27
8999 20:15:28.327919 Byte0 TX OE(2T, 0.5T) = (3, 3)
9000 20:15:28.331451 Byte1 TX OE(2T, 0.5T) = (3, 3)
9001 20:15:28.331913
9002 20:15:28.332298
9003 20:15:28.338021 [DQSOSCAuto] RK1, (LSB)MR18= 0x1904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
9004 20:15:28.341333 CH1 RK1: MR19=303, MR18=1904
9005 20:15:28.348120 CH1_RK1: MR19=0x303, MR18=0x1904, DQSOSC=397, MR23=63, INC=23, DEC=15
9006 20:15:28.351329 [RxdqsGatingPostProcess] freq 1600
9007 20:15:28.354729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9008 20:15:28.358064 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 20:15:28.361681 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 20:15:28.364852 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 20:15:28.368144 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 20:15:28.371906 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 20:15:28.374828 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 20:15:28.378093 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 20:15:28.381316 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 20:15:28.384589 Pre-setting of DQS Precalculation
9017 20:15:28.388040 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9018 20:15:28.394698 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9019 20:15:28.404605 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9020 20:15:28.405228
9021 20:15:28.405598
9022 20:15:28.407901 [Calibration Summary] 3200 Mbps
9023 20:15:28.408360 CH 0, Rank 0
9024 20:15:28.411493 SW Impedance : PASS
9025 20:15:28.411957 DUTY Scan : NO K
9026 20:15:28.414540 ZQ Calibration : PASS
9027 20:15:28.415003 Jitter Meter : NO K
9028 20:15:28.417894 CBT Training : PASS
9029 20:15:28.420999 Write leveling : PASS
9030 20:15:28.421471 RX DQS gating : PASS
9031 20:15:28.425124 RX DQ/DQS(RDDQC) : PASS
9032 20:15:28.427775 TX DQ/DQS : PASS
9033 20:15:28.428241 RX DATLAT : PASS
9034 20:15:28.431371 RX DQ/DQS(Engine): PASS
9035 20:15:28.434487 TX OE : PASS
9036 20:15:28.434949 All Pass.
9037 20:15:28.435316
9038 20:15:28.435661 CH 0, Rank 1
9039 20:15:28.438086 SW Impedance : PASS
9040 20:15:28.440962 DUTY Scan : NO K
9041 20:15:28.441413 ZQ Calibration : PASS
9042 20:15:28.444371 Jitter Meter : NO K
9043 20:15:28.447860 CBT Training : PASS
9044 20:15:28.448373 Write leveling : PASS
9045 20:15:28.450959 RX DQS gating : PASS
9046 20:15:28.454344 RX DQ/DQS(RDDQC) : PASS
9047 20:15:28.454807 TX DQ/DQS : PASS
9048 20:15:28.457512 RX DATLAT : PASS
9049 20:15:28.461216 RX DQ/DQS(Engine): PASS
9050 20:15:28.461677 TX OE : PASS
9051 20:15:28.462134 All Pass.
9052 20:15:28.462496
9053 20:15:28.464283 CH 1, Rank 0
9054 20:15:28.467842 SW Impedance : PASS
9055 20:15:28.468259 DUTY Scan : NO K
9056 20:15:28.471034 ZQ Calibration : PASS
9057 20:15:28.471453 Jitter Meter : NO K
9058 20:15:28.474141 CBT Training : PASS
9059 20:15:28.477768 Write leveling : PASS
9060 20:15:28.478231 RX DQS gating : PASS
9061 20:15:28.480834 RX DQ/DQS(RDDQC) : PASS
9062 20:15:28.484057 TX DQ/DQS : PASS
9063 20:15:28.484476 RX DATLAT : PASS
9064 20:15:28.487540 RX DQ/DQS(Engine): PASS
9065 20:15:28.490822 TX OE : PASS
9066 20:15:28.491242 All Pass.
9067 20:15:28.491600
9068 20:15:28.492050 CH 1, Rank 1
9069 20:15:28.494305 SW Impedance : PASS
9070 20:15:28.497611 DUTY Scan : NO K
9071 20:15:28.498065 ZQ Calibration : PASS
9072 20:15:28.500743 Jitter Meter : NO K
9073 20:15:28.504161 CBT Training : PASS
9074 20:15:28.504575 Write leveling : PASS
9075 20:15:28.507283 RX DQS gating : PASS
9076 20:15:28.510742 RX DQ/DQS(RDDQC) : PASS
9077 20:15:28.511163 TX DQ/DQS : PASS
9078 20:15:28.514164 RX DATLAT : PASS
9079 20:15:28.517483 RX DQ/DQS(Engine): PASS
9080 20:15:28.517901 TX OE : PASS
9081 20:15:28.518380 All Pass.
9082 20:15:28.520669
9083 20:15:28.521084 DramC Write-DBI on
9084 20:15:28.524065 PER_BANK_REFRESH: Hybrid Mode
9085 20:15:28.524499 TX_TRACKING: ON
9086 20:15:28.534138 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9087 20:15:28.540615 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9088 20:15:28.550391 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9089 20:15:28.553823 [FAST_K] Save calibration result to emmc
9090 20:15:28.554371 sync common calibartion params.
9091 20:15:28.557093 sync cbt_mode0:1, 1:1
9092 20:15:28.560749 dram_init: ddr_geometry: 2
9093 20:15:28.563885 dram_init: ddr_geometry: 2
9094 20:15:28.564321 dram_init: ddr_geometry: 2
9095 20:15:28.567491 0:dram_rank_size:100000000
9096 20:15:28.570249 1:dram_rank_size:100000000
9097 20:15:28.573794 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9098 20:15:28.577093 DFS_SHUFFLE_HW_MODE: ON
9099 20:15:28.580415 dramc_set_vcore_voltage set vcore to 725000
9100 20:15:28.583628 Read voltage for 1600, 0
9101 20:15:28.584063 Vio18 = 0
9102 20:15:28.587221 Vcore = 725000
9103 20:15:28.587655 Vdram = 0
9104 20:15:28.588098 Vddq = 0
9105 20:15:28.588513 Vmddr = 0
9106 20:15:28.590207 switch to 3200 Mbps bootup
9107 20:15:28.593522 [DramcRunTimeConfig]
9108 20:15:28.593989 PHYPLL
9109 20:15:28.596811 DPM_CONTROL_AFTERK: ON
9110 20:15:28.597247 PER_BANK_REFRESH: ON
9111 20:15:28.600247 REFRESH_OVERHEAD_REDUCTION: ON
9112 20:15:28.604032 CMD_PICG_NEW_MODE: OFF
9113 20:15:28.604466 XRTWTW_NEW_MODE: ON
9114 20:15:28.606760 XRTRTR_NEW_MODE: ON
9115 20:15:28.607196 TX_TRACKING: ON
9116 20:15:28.610300 RDSEL_TRACKING: OFF
9117 20:15:28.610738 DQS Precalculation for DVFS: ON
9118 20:15:28.613470 RX_TRACKING: OFF
9119 20:15:28.613906 HW_GATING DBG: ON
9120 20:15:28.617305 ZQCS_ENABLE_LP4: ON
9121 20:15:28.620354 RX_PICG_NEW_MODE: ON
9122 20:15:28.620859 TX_PICG_NEW_MODE: ON
9123 20:15:28.623518 ENABLE_RX_DCM_DPHY: ON
9124 20:15:28.626805 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9125 20:15:28.626921 DUMMY_READ_FOR_TRACKING: OFF
9126 20:15:28.629849 !!! SPM_CONTROL_AFTERK: OFF
9127 20:15:28.633137 !!! SPM could not control APHY
9128 20:15:28.636509 IMPEDANCE_TRACKING: ON
9129 20:15:28.636594 TEMP_SENSOR: ON
9130 20:15:28.639898 HW_SAVE_FOR_SR: OFF
9131 20:15:28.643396 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9132 20:15:28.646655 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9133 20:15:28.646770 Read ODT Tracking: ON
9134 20:15:28.649923 Refresh Rate DeBounce: ON
9135 20:15:28.653054 DFS_NO_QUEUE_FLUSH: ON
9136 20:15:28.656592 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9137 20:15:28.656699 ENABLE_DFS_RUNTIME_MRW: OFF
9138 20:15:28.660061 DDR_RESERVE_NEW_MODE: ON
9139 20:15:28.663241 MR_CBT_SWITCH_FREQ: ON
9140 20:15:28.663325 =========================
9141 20:15:28.683010 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9142 20:15:28.686273 dram_init: ddr_geometry: 2
9143 20:15:28.704410 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9144 20:15:28.707751 dram_init: dram init end (result: 0)
9145 20:15:28.714766 DRAM-K: Full calibration passed in 24486 msecs
9146 20:15:28.718221 MRC: failed to locate region type 0.
9147 20:15:28.718304 DRAM rank0 size:0x100000000,
9148 20:15:28.721482 DRAM rank1 size=0x100000000
9149 20:15:28.731014 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9150 20:15:28.737853 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9151 20:15:28.744712 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9152 20:15:28.750979 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9153 20:15:28.754228 DRAM rank0 size:0x100000000,
9154 20:15:28.757762 DRAM rank1 size=0x100000000
9155 20:15:28.757846 CBMEM:
9156 20:15:28.760868 IMD: root @ 0xfffff000 254 entries.
9157 20:15:28.764389 IMD: root @ 0xffffec00 62 entries.
9158 20:15:28.767596 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9159 20:15:28.770893 WARNING: RO_VPD is uninitialized or empty.
9160 20:15:28.777307 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9161 20:15:28.784349 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9162 20:15:28.797176 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9163 20:15:28.808697 BS: romstage times (exec / console): total (unknown) / 23983 ms
9164 20:15:28.808811
9165 20:15:28.808918
9166 20:15:28.818675 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9167 20:15:28.822190 ARM64: Exception handlers installed.
9168 20:15:28.825279 ARM64: Testing exception
9169 20:15:28.828612 ARM64: Done test exception
9170 20:15:28.828726 Enumerating buses...
9171 20:15:28.831688 Show all devs... Before device enumeration.
9172 20:15:28.835133 Root Device: enabled 1
9173 20:15:28.838517 CPU_CLUSTER: 0: enabled 1
9174 20:15:28.838632 CPU: 00: enabled 1
9175 20:15:28.841885 Compare with tree...
9176 20:15:28.842026 Root Device: enabled 1
9177 20:15:28.845125 CPU_CLUSTER: 0: enabled 1
9178 20:15:28.848283 CPU: 00: enabled 1
9179 20:15:28.848401 Root Device scanning...
9180 20:15:28.851500 scan_static_bus for Root Device
9181 20:15:28.855227 CPU_CLUSTER: 0 enabled
9182 20:15:28.858490 scan_static_bus for Root Device done
9183 20:15:28.861877 scan_bus: bus Root Device finished in 8 msecs
9184 20:15:28.861990 done
9185 20:15:28.868068 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9186 20:15:28.871837 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9187 20:15:28.878343 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9188 20:15:28.881568 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9189 20:15:28.884817 Allocating resources...
9190 20:15:28.888347 Reading resources...
9191 20:15:28.891314 Root Device read_resources bus 0 link: 0
9192 20:15:28.891426 DRAM rank0 size:0x100000000,
9193 20:15:28.894651 DRAM rank1 size=0x100000000
9194 20:15:28.898052 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9195 20:15:28.901499 CPU: 00 missing read_resources
9196 20:15:28.908094 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9197 20:15:28.911435 Root Device read_resources bus 0 link: 0 done
9198 20:15:28.911536 Done reading resources.
9199 20:15:28.918011 Show resources in subtree (Root Device)...After reading.
9200 20:15:28.921063 Root Device child on link 0 CPU_CLUSTER: 0
9201 20:15:28.924665 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 20:15:28.934835 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 20:15:28.934952 CPU: 00
9204 20:15:28.937781 Root Device assign_resources, bus 0 link: 0
9205 20:15:28.941363 CPU_CLUSTER: 0 missing set_resources
9206 20:15:28.947917 Root Device assign_resources, bus 0 link: 0 done
9207 20:15:28.948024 Done setting resources.
9208 20:15:28.954331 Show resources in subtree (Root Device)...After assigning values.
9209 20:15:28.957839 Root Device child on link 0 CPU_CLUSTER: 0
9210 20:15:28.960912 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 20:15:28.971091 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 20:15:28.971206 CPU: 00
9213 20:15:28.974362 Done allocating resources.
9214 20:15:28.977759 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9215 20:15:28.981467 Enabling resources...
9216 20:15:28.981577 done.
9217 20:15:28.987768 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9218 20:15:28.987886 Initializing devices...
9219 20:15:28.991055 Root Device init
9220 20:15:28.991171 init hardware done!
9221 20:15:28.994426 0x00000018: ctrlr->caps
9222 20:15:28.997692 52.000 MHz: ctrlr->f_max
9223 20:15:28.997796 0.400 MHz: ctrlr->f_min
9224 20:15:29.001188 0x40ff8080: ctrlr->voltages
9225 20:15:29.001300 sclk: 390625
9226 20:15:29.004514 Bus Width = 1
9227 20:15:29.004626 sclk: 390625
9228 20:15:29.007758 Bus Width = 1
9229 20:15:29.007865 Early init status = 3
9230 20:15:29.013841 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9231 20:15:29.017516 in-header: 03 fc 00 00 01 00 00 00
9232 20:15:29.017616 in-data: 00
9233 20:15:29.023797 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9234 20:15:29.027400 in-header: 03 fd 00 00 00 00 00 00
9235 20:15:29.030829 in-data:
9236 20:15:29.034220 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9237 20:15:29.037480 in-header: 03 fc 00 00 01 00 00 00
9238 20:15:29.040639 in-data: 00
9239 20:15:29.044195 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9240 20:15:29.049153 in-header: 03 fd 00 00 00 00 00 00
9241 20:15:29.052148 in-data:
9242 20:15:29.055436 [SSUSB] Setting up USB HOST controller...
9243 20:15:29.059104 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9244 20:15:29.062197 [SSUSB] phy power-on done.
9245 20:15:29.065812 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9246 20:15:29.072198 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9247 20:15:29.075592 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9248 20:15:29.082083 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9249 20:15:29.088782 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9250 20:15:29.095206 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9251 20:15:29.101856 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9252 20:15:29.108777 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9253 20:15:29.111802 SPM: binary array size = 0x9dc
9254 20:15:29.115237 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9255 20:15:29.121856 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9256 20:15:29.128664 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9257 20:15:29.135007 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9258 20:15:29.138257 configure_display: Starting display init
9259 20:15:29.172167 anx7625_power_on_init: Init interface.
9260 20:15:29.175578 anx7625_disable_pd_protocol: Disabled PD feature.
9261 20:15:29.179025 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9262 20:15:29.206649 anx7625_start_dp_work: Secure OCM version=00
9263 20:15:29.210127 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9264 20:15:29.224731 sp_tx_get_edid_block: EDID Block = 1
9265 20:15:29.327344 Extracted contents:
9266 20:15:29.331024 header: 00 ff ff ff ff ff ff 00
9267 20:15:29.333887 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9268 20:15:29.337314 version: 01 04
9269 20:15:29.340436 basic params: 95 1f 11 78 0a
9270 20:15:29.343710 chroma info: 76 90 94 55 54 90 27 21 50 54
9271 20:15:29.347139 established: 00 00 00
9272 20:15:29.353949 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9273 20:15:29.356888 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9274 20:15:29.363854 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9275 20:15:29.370150 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9276 20:15:29.377066 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9277 20:15:29.380647 extensions: 00
9278 20:15:29.380734 checksum: fb
9279 20:15:29.380800
9280 20:15:29.383647 Manufacturer: IVO Model 57d Serial Number 0
9281 20:15:29.387346 Made week 0 of 2020
9282 20:15:29.387427 EDID version: 1.4
9283 20:15:29.390551 Digital display
9284 20:15:29.393758 6 bits per primary color channel
9285 20:15:29.393841 DisplayPort interface
9286 20:15:29.396953 Maximum image size: 31 cm x 17 cm
9287 20:15:29.400512 Gamma: 220%
9288 20:15:29.400594 Check DPMS levels
9289 20:15:29.404002 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9290 20:15:29.407159 First detailed timing is preferred timing
9291 20:15:29.410143 Established timings supported:
9292 20:15:29.413677 Standard timings supported:
9293 20:15:29.416940 Detailed timings
9294 20:15:29.420172 Hex of detail: 383680a07038204018303c0035ae10000019
9295 20:15:29.423525 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9296 20:15:29.430300 0780 0798 07c8 0820 hborder 0
9297 20:15:29.433328 0438 043b 0447 0458 vborder 0
9298 20:15:29.436975 -hsync -vsync
9299 20:15:29.437055 Did detailed timing
9300 20:15:29.443532 Hex of detail: 000000000000000000000000000000000000
9301 20:15:29.443612 Manufacturer-specified data, tag 0
9302 20:15:29.449847 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9303 20:15:29.453402 ASCII string: InfoVision
9304 20:15:29.456817 Hex of detail: 000000fe00523134304e574635205248200a
9305 20:15:29.459909 ASCII string: R140NWF5 RH
9306 20:15:29.459990 Checksum
9307 20:15:29.463250 Checksum: 0xfb (valid)
9308 20:15:29.466470 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9309 20:15:29.469881 DSI data_rate: 832800000 bps
9310 20:15:29.476432 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9311 20:15:29.479850 anx7625_parse_edid: pixelclock(138800).
9312 20:15:29.483321 hactive(1920), hsync(48), hfp(24), hbp(88)
9313 20:15:29.486626 vactive(1080), vsync(12), vfp(3), vbp(17)
9314 20:15:29.489749 anx7625_dsi_config: config dsi.
9315 20:15:29.496440 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9316 20:15:29.509291 anx7625_dsi_config: success to config DSI
9317 20:15:29.512970 anx7625_dp_start: MIPI phy setup OK.
9318 20:15:29.515746 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9319 20:15:29.519247 mtk_ddp_mode_set invalid vrefresh 60
9320 20:15:29.522561 main_disp_path_setup
9321 20:15:29.522642 ovl_layer_smi_id_en
9322 20:15:29.526079 ovl_layer_smi_id_en
9323 20:15:29.526160 ccorr_config
9324 20:15:29.526225 aal_config
9325 20:15:29.529088 gamma_config
9326 20:15:29.529168 postmask_config
9327 20:15:29.532813 dither_config
9328 20:15:29.536370 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9329 20:15:29.543087 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9330 20:15:29.546077 Root Device init finished in 551 msecs
9331 20:15:29.546159 CPU_CLUSTER: 0 init
9332 20:15:29.556151 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9333 20:15:29.559209 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9334 20:15:29.562804 APU_MBOX 0x190000b0 = 0x10001
9335 20:15:29.565809 APU_MBOX 0x190001b0 = 0x10001
9336 20:15:29.569254 APU_MBOX 0x190005b0 = 0x10001
9337 20:15:29.572634 APU_MBOX 0x190006b0 = 0x10001
9338 20:15:29.575592 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9339 20:15:29.588174 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9340 20:15:29.600804 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9341 20:15:29.607522 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9342 20:15:29.619013 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9343 20:15:29.628278 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9344 20:15:29.631722 CPU_CLUSTER: 0 init finished in 81 msecs
9345 20:15:29.634780 Devices initialized
9346 20:15:29.638103 Show all devs... After init.
9347 20:15:29.638194 Root Device: enabled 1
9348 20:15:29.641402 CPU_CLUSTER: 0: enabled 1
9349 20:15:29.644635 CPU: 00: enabled 1
9350 20:15:29.648191 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9351 20:15:29.651238 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9352 20:15:29.654986 ELOG: NV offset 0x57f000 size 0x1000
9353 20:15:29.661607 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9354 20:15:29.667789 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9355 20:15:29.671067 ELOG: Event(17) added with size 13 at 2024-03-03 20:14:52 UTC
9356 20:15:29.677866 out: cmd=0x121: 03 db 21 01 00 00 00 00
9357 20:15:29.681186 in-header: 03 43 00 00 2c 00 00 00
9358 20:15:29.694003 in-data: 1c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 20:15:29.697779 ELOG: Event(A1) added with size 10 at 2024-03-03 20:14:52 UTC
9360 20:15:29.707343 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9361 20:15:29.711206 ELOG: Event(A0) added with size 9 at 2024-03-03 20:14:52 UTC
9362 20:15:29.714071 elog_add_boot_reason: Logged dev mode boot
9363 20:15:29.720589 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9364 20:15:29.720723 Finalize devices...
9365 20:15:29.724272 Devices finalized
9366 20:15:29.727146 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9367 20:15:29.730663 Writing coreboot table at 0xffe64000
9368 20:15:29.737198 0. 000000000010a000-0000000000113fff: RAMSTAGE
9369 20:15:29.740563 1. 0000000040000000-00000000400fffff: RAM
9370 20:15:29.744074 2. 0000000040100000-000000004032afff: RAMSTAGE
9371 20:15:29.747130 3. 000000004032b000-00000000545fffff: RAM
9372 20:15:29.750326 4. 0000000054600000-000000005465ffff: BL31
9373 20:15:29.757033 5. 0000000054660000-00000000ffe63fff: RAM
9374 20:15:29.760440 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9375 20:15:29.763731 7. 0000000100000000-000000023fffffff: RAM
9376 20:15:29.766967 Passing 5 GPIOs to payload:
9377 20:15:29.773577 NAME | PORT | POLARITY | VALUE
9378 20:15:29.776557 EC in RW | 0x000000aa | low | undefined
9379 20:15:29.780128 EC interrupt | 0x00000005 | low | undefined
9380 20:15:29.786670 TPM interrupt | 0x000000ab | high | undefined
9381 20:15:29.790071 SD card detect | 0x00000011 | high | undefined
9382 20:15:29.796784 speaker enable | 0x00000093 | high | undefined
9383 20:15:29.799826 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9384 20:15:29.803255 in-header: 03 f9 00 00 02 00 00 00
9385 20:15:29.803342 in-data: 02 00
9386 20:15:29.806377 ADC[4]: Raw value=901032 ID=7
9387 20:15:29.809674 ADC[3]: Raw value=213179 ID=1
9388 20:15:29.809757 RAM Code: 0x71
9389 20:15:29.813183 ADC[6]: Raw value=74502 ID=0
9390 20:15:29.816479 ADC[5]: Raw value=212441 ID=1
9391 20:15:29.816560 SKU Code: 0x1
9392 20:15:29.822990 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5082
9393 20:15:29.826479 coreboot table: 964 bytes.
9394 20:15:29.829676 IMD ROOT 0. 0xfffff000 0x00001000
9395 20:15:29.832971 IMD SMALL 1. 0xffffe000 0x00001000
9396 20:15:29.835990 RO MCACHE 2. 0xffffc000 0x00001104
9397 20:15:29.839604 CONSOLE 3. 0xfff7c000 0x00080000
9398 20:15:29.842702 FMAP 4. 0xfff7b000 0x00000452
9399 20:15:29.846103 TIME STAMP 5. 0xfff7a000 0x00000910
9400 20:15:29.849244 VBOOT WORK 6. 0xfff66000 0x00014000
9401 20:15:29.852695 RAMOOPS 7. 0xffe66000 0x00100000
9402 20:15:29.856279 COREBOOT 8. 0xffe64000 0x00002000
9403 20:15:29.856363 IMD small region:
9404 20:15:29.859422 IMD ROOT 0. 0xffffec00 0x00000400
9405 20:15:29.862560 VPD 1. 0xffffeb80 0x0000006c
9406 20:15:29.865785 MMC STATUS 2. 0xffffeb60 0x00000004
9407 20:15:29.872754 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9408 20:15:29.872838 Probing TPM: done!
9409 20:15:29.879262 Connected to device vid:did:rid of 1ae0:0028:00
9410 20:15:29.885843 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9411 20:15:29.892817 Initialized TPM device CR50 revision 0
9412 20:15:29.892900 Checking cr50 for pending updates
9413 20:15:29.898915 Reading cr50 TPM mode
9414 20:15:29.908206 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9415 20:15:29.914637 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9416 20:15:29.954242 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9417 20:15:29.957740 Checking segment from ROM address 0x40100000
9418 20:15:29.960991 Checking segment from ROM address 0x4010001c
9419 20:15:29.968099 Loading segment from ROM address 0x40100000
9420 20:15:29.968183 code (compression=0)
9421 20:15:29.974467 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9422 20:15:29.984582 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9423 20:15:29.984667 it's not compressed!
9424 20:15:29.991211 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9425 20:15:29.994470 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9426 20:15:30.015039 Loading segment from ROM address 0x4010001c
9427 20:15:30.015124 Entry Point 0x80000000
9428 20:15:30.018228 Loaded segments
9429 20:15:30.021686 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9430 20:15:30.028169 Jumping to boot code at 0x80000000(0xffe64000)
9431 20:15:30.035012 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9432 20:15:30.041673 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9433 20:15:30.049389 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9434 20:15:30.052856 Checking segment from ROM address 0x40100000
9435 20:15:30.055850 Checking segment from ROM address 0x4010001c
9436 20:15:30.062439 Loading segment from ROM address 0x40100000
9437 20:15:30.062532 code (compression=1)
9438 20:15:30.069163 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9439 20:15:30.079330 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9440 20:15:30.079411 using LZMA
9441 20:15:30.087580 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9442 20:15:30.094446 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9443 20:15:30.098036 Loading segment from ROM address 0x4010001c
9444 20:15:30.098118 Entry Point 0x54601000
9445 20:15:30.101225 Loaded segments
9446 20:15:30.104191 NOTICE: MT8192 bl31_setup
9447 20:15:30.111126 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9448 20:15:30.114333 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9449 20:15:30.117914 WARNING: region 0:
9450 20:15:30.121067 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 20:15:30.121145 WARNING: region 1:
9452 20:15:30.127819 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9453 20:15:30.131486 WARNING: region 2:
9454 20:15:30.134646 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9455 20:15:30.137801 WARNING: region 3:
9456 20:15:30.141000 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 20:15:30.144254 WARNING: region 4:
9458 20:15:30.151574 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 20:15:30.151660 WARNING: region 5:
9460 20:15:30.154419 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 20:15:30.157785 WARNING: region 6:
9462 20:15:30.161156 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 20:15:30.164438 WARNING: region 7:
9464 20:15:30.167890 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 20:15:30.174344 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9466 20:15:30.177568 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9467 20:15:30.181404 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9468 20:15:30.187618 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9469 20:15:30.191225 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9470 20:15:30.194349 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9471 20:15:30.201235 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9472 20:15:30.204244 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9473 20:15:30.211240 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9474 20:15:30.214555 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9475 20:15:30.217835 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9476 20:15:30.224444 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9477 20:15:30.227663 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9478 20:15:30.231017 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9479 20:15:30.237837 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9480 20:15:30.241345 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9481 20:15:30.248159 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9482 20:15:30.251461 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9483 20:15:30.254534 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9484 20:15:30.261371 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9485 20:15:30.264912 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9486 20:15:30.268077 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9487 20:15:30.274652 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9488 20:15:30.277857 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9489 20:15:30.284502 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9490 20:15:30.288110 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9491 20:15:30.291115 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9492 20:15:30.297914 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9493 20:15:30.301519 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9494 20:15:30.304681 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9495 20:15:30.311151 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9496 20:15:30.314653 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9497 20:15:30.321309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9498 20:15:30.324734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9499 20:15:30.327821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9500 20:15:30.331100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9501 20:15:30.334631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9502 20:15:30.341275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9503 20:15:30.344525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9504 20:15:30.347651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9505 20:15:30.351280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9506 20:15:30.358146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9507 20:15:30.361362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9508 20:15:30.364842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9509 20:15:30.367916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9510 20:15:30.374457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9511 20:15:30.378020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9512 20:15:30.381069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9513 20:15:30.387773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9514 20:15:30.391164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9515 20:15:30.397744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9516 20:15:30.400979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9517 20:15:30.404381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9518 20:15:30.411359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9519 20:15:30.414486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9520 20:15:30.420863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9521 20:15:30.424622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9522 20:15:30.431155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9523 20:15:30.434665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9524 20:15:30.438065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9525 20:15:30.444346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9526 20:15:30.447989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9527 20:15:30.454470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9528 20:15:30.458066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9529 20:15:30.464435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9530 20:15:30.467759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9531 20:15:30.471417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9532 20:15:30.477881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9533 20:15:30.481024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9534 20:15:30.487588 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9535 20:15:30.491008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9536 20:15:30.497930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9537 20:15:30.501268 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9538 20:15:30.504390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9539 20:15:30.511197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9540 20:15:30.514291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9541 20:15:30.521525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9542 20:15:30.524470 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9543 20:15:30.531139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9544 20:15:30.534636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9545 20:15:30.541145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9546 20:15:30.544778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9547 20:15:30.547694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9548 20:15:30.554549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9549 20:15:30.558232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9550 20:15:30.564635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9551 20:15:30.568341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9552 20:15:30.571532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9553 20:15:30.577962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9554 20:15:30.581330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9555 20:15:30.587859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9556 20:15:30.591265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9557 20:15:30.598148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9558 20:15:30.601447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9559 20:15:30.608102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9560 20:15:30.611029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9561 20:15:30.614381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9562 20:15:30.618323 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9563 20:15:30.624730 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9564 20:15:30.627939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9565 20:15:30.631377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9566 20:15:30.638153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9567 20:15:30.641444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9568 20:15:30.644858 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9569 20:15:30.651629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9570 20:15:30.654833 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9571 20:15:30.661362 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9572 20:15:30.664868 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9573 20:15:30.667945 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9574 20:15:30.674723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9575 20:15:30.678305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9576 20:15:30.684642 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9577 20:15:30.687913 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9578 20:15:30.691507 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9579 20:15:30.697863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9580 20:15:30.701508 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9581 20:15:30.704706 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9582 20:15:30.711615 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9583 20:15:30.714561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9584 20:15:30.718095 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9585 20:15:30.721200 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9586 20:15:30.728220 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9587 20:15:30.731421 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9588 20:15:30.734634 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9589 20:15:30.741689 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9590 20:15:30.744869 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9591 20:15:30.748384 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9592 20:15:30.754673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9593 20:15:30.758357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9594 20:15:30.764946 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9595 20:15:30.767886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9596 20:15:30.771664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9597 20:15:30.778247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9598 20:15:30.781277 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9599 20:15:30.784527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9600 20:15:30.791442 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9601 20:15:30.795114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9602 20:15:30.801802 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9603 20:15:30.804972 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9604 20:15:30.808765 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9605 20:15:30.814743 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9606 20:15:30.818273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9607 20:15:30.824724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9608 20:15:30.828049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9609 20:15:30.831477 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9610 20:15:30.838197 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9611 20:15:30.841593 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9612 20:15:30.844891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9613 20:15:30.851474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9614 20:15:30.854836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9615 20:15:30.861619 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9616 20:15:30.864853 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9617 20:15:30.868419 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9618 20:15:30.875077 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9619 20:15:30.878131 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9620 20:15:30.884994 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9621 20:15:30.888320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9622 20:15:30.891615 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9623 20:15:30.898404 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9624 20:15:30.901554 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9625 20:15:30.904722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9626 20:15:30.911751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9627 20:15:30.914836 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9628 20:15:30.921480 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9629 20:15:30.925035 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9630 20:15:30.927956 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9631 20:15:30.934856 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9632 20:15:30.937835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9633 20:15:30.944686 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9634 20:15:30.948161 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9635 20:15:30.951724 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9636 20:15:30.958350 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9637 20:15:30.961366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9638 20:15:30.964825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9639 20:15:30.971294 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9640 20:15:30.974620 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9641 20:15:30.981053 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9642 20:15:30.984330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9643 20:15:30.987847 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9644 20:15:30.994765 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9645 20:15:30.997649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9646 20:15:31.004542 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9647 20:15:31.008136 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9648 20:15:31.011303 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9649 20:15:31.017788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9650 20:15:31.020998 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9651 20:15:31.027656 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9652 20:15:31.030951 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9653 20:15:31.034091 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9654 20:15:31.041079 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9655 20:15:31.044176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9656 20:15:31.051243 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9657 20:15:31.053751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9658 20:15:31.060590 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9659 20:15:31.064096 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9660 20:15:31.067398 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9661 20:15:31.073690 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9662 20:15:31.077139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9663 20:15:31.083532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9664 20:15:31.086614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9665 20:15:31.093497 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9666 20:15:31.096761 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9667 20:15:31.100118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9668 20:15:31.106690 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9669 20:15:31.110112 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9670 20:15:31.116766 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9671 20:15:31.119868 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9672 20:15:31.123298 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9673 20:15:31.129880 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9674 20:15:31.133053 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9675 20:15:31.139755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9676 20:15:31.143275 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9677 20:15:31.149783 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9678 20:15:31.152805 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9679 20:15:31.156007 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9680 20:15:31.162817 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9681 20:15:31.166356 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9682 20:15:31.172826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9683 20:15:31.176051 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9684 20:15:31.182619 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9685 20:15:31.186076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9686 20:15:31.189245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9687 20:15:31.196166 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9688 20:15:31.199227 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9689 20:15:31.205923 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9690 20:15:31.209282 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9691 20:15:31.215881 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9692 20:15:31.219391 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9693 20:15:31.222430 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9694 20:15:31.229074 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9695 20:15:31.232526 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9696 20:15:31.235710 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9697 20:15:31.239200 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9698 20:15:31.242342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9699 20:15:31.249227 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9700 20:15:31.252288 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9701 20:15:31.258771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9702 20:15:31.262482 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9703 20:15:31.265836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9704 20:15:31.272204 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9705 20:15:31.275468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9706 20:15:31.279450 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9707 20:15:31.285646 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9708 20:15:31.288677 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9709 20:15:31.295405 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9710 20:15:31.298593 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9711 20:15:31.301859 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9712 20:15:31.308862 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9713 20:15:31.311978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9714 20:15:31.315373 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9715 20:15:31.322052 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9716 20:15:31.325092 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9717 20:15:31.331900 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9718 20:15:31.334936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9719 20:15:31.338515 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9720 20:15:31.345307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9721 20:15:31.348607 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9722 20:15:31.351504 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9723 20:15:31.358458 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9724 20:15:31.361693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9725 20:15:31.365018 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9726 20:15:31.371682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9727 20:15:31.374725 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9728 20:15:31.378200 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9729 20:15:31.385151 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9730 20:15:31.388614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9731 20:15:31.395199 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9732 20:15:31.398262 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9733 20:15:31.401454 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9734 20:15:31.407889 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9735 20:15:31.411336 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9736 20:15:31.414713 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9737 20:15:31.418187 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9738 20:15:31.421253 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9739 20:15:31.428057 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9740 20:15:31.431308 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9741 20:15:31.434519 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9742 20:15:31.438234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9743 20:15:31.444556 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9744 20:15:31.448083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9745 20:15:31.451295 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9746 20:15:31.457894 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9747 20:15:31.461109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9748 20:15:31.464449 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9749 20:15:31.471097 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9750 20:15:31.474282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9751 20:15:31.481049 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9752 20:15:31.484287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9753 20:15:31.491197 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9754 20:15:31.494600 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9755 20:15:31.497716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9756 20:15:31.504426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9757 20:15:31.507515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9758 20:15:31.514460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9759 20:15:31.517878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9760 20:15:31.521186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9761 20:15:31.527545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9762 20:15:31.530826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9763 20:15:31.534070 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9764 20:15:31.540781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9765 20:15:31.544003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9766 20:15:31.550595 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9767 20:15:31.554118 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9768 20:15:31.560793 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9769 20:15:31.563898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9770 20:15:31.567276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9771 20:15:31.573878 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9772 20:15:31.577419 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9773 20:15:31.584036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9774 20:15:31.587221 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9775 20:15:31.594205 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9776 20:15:31.597263 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9777 20:15:31.600568 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9778 20:15:31.607193 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9779 20:15:31.610264 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9780 20:15:31.617120 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9781 20:15:31.620510 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9782 20:15:31.623909 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9783 20:15:31.630243 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9784 20:15:31.633753 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9785 20:15:31.640353 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9786 20:15:31.643728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9787 20:15:31.646964 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9788 20:15:31.653586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9789 20:15:31.657048 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9790 20:15:31.663540 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9791 20:15:31.667086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9792 20:15:31.670602 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9793 20:15:31.676870 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9794 20:15:31.680321 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9795 20:15:31.687208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9796 20:15:31.690139 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9797 20:15:31.693447 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9798 20:15:31.700374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9799 20:15:31.703525 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9800 20:15:31.710165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9801 20:15:31.713392 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9802 20:15:31.716470 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9803 20:15:31.723170 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9804 20:15:31.726610 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9805 20:15:31.733424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9806 20:15:31.736764 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9807 20:15:31.743235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9808 20:15:31.746386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9809 20:15:31.749719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9810 20:15:31.756334 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9811 20:15:31.759956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9812 20:15:31.766737 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9813 20:15:31.769732 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9814 20:15:31.773305 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9815 20:15:31.780033 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9816 20:15:31.783259 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9817 20:15:31.789861 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9818 20:15:31.793019 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9819 20:15:31.796773 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9820 20:15:31.803044 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9821 20:15:31.806213 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9822 20:15:31.812808 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9823 20:15:31.816174 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9824 20:15:31.822916 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9825 20:15:31.826081 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9826 20:15:31.829760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9827 20:15:31.836039 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9828 20:15:31.839323 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9829 20:15:31.846236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9830 20:15:31.849258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9831 20:15:31.855765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9832 20:15:31.859163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9833 20:15:31.866085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9834 20:15:31.868835 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9835 20:15:31.872203 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9836 20:15:31.879188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9837 20:15:31.882164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9838 20:15:31.888788 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9839 20:15:31.892445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9840 20:15:31.898785 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9841 20:15:31.902517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9842 20:15:31.905357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9843 20:15:31.912094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9844 20:15:31.915947 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9845 20:15:31.921944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9846 20:15:31.925568 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9847 20:15:31.932096 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9848 20:15:31.935466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9849 20:15:31.942067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9850 20:15:31.945280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9851 20:15:31.948751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9852 20:15:31.955151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9853 20:15:31.958468 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9854 20:15:31.964871 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9855 20:15:31.968285 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9856 20:15:31.974994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9857 20:15:31.978464 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9858 20:15:31.981810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9859 20:15:31.988358 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9860 20:15:31.991805 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9861 20:15:31.998361 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9862 20:15:32.001900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9863 20:15:32.008432 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9864 20:15:32.011515 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9865 20:15:32.018121 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9866 20:15:32.021334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9867 20:15:32.025116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9868 20:15:32.031387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9869 20:15:32.034878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9870 20:15:32.041568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9871 20:15:32.044942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9872 20:15:32.051526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9873 20:15:32.055062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9874 20:15:32.061581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9875 20:15:32.064879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9876 20:15:32.071432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9877 20:15:32.074615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9878 20:15:32.081217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9879 20:15:32.084721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9880 20:15:32.088156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9881 20:15:32.095420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9882 20:15:32.098153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9883 20:15:32.104873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9884 20:15:32.108388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9885 20:15:32.114595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9886 20:15:32.117911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9887 20:15:32.124625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9888 20:15:32.127942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9889 20:15:32.134522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9890 20:15:32.138353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9891 20:15:32.145006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9892 20:15:32.148442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9893 20:15:32.154885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9894 20:15:32.158450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9895 20:15:32.165473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9896 20:15:32.168774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9897 20:15:32.174915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9898 20:15:32.178608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9899 20:15:32.185344 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9900 20:15:32.186012 INFO: [APUAPC] vio 0
9901 20:15:32.191786 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9902 20:15:32.195080 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9903 20:15:32.198322 INFO: [APUAPC] D0_APC_0: 0x400510
9904 20:15:32.202073 INFO: [APUAPC] D0_APC_1: 0x0
9905 20:15:32.204984 INFO: [APUAPC] D0_APC_2: 0x1540
9906 20:15:32.208314 INFO: [APUAPC] D0_APC_3: 0x0
9907 20:15:32.212102 INFO: [APUAPC] D1_APC_0: 0xffffffff
9908 20:15:32.214990 INFO: [APUAPC] D1_APC_1: 0xffffffff
9909 20:15:32.218532 INFO: [APUAPC] D1_APC_2: 0x3fffff
9910 20:15:32.222101 INFO: [APUAPC] D1_APC_3: 0x0
9911 20:15:32.225140 INFO: [APUAPC] D2_APC_0: 0xffffffff
9912 20:15:32.228470 INFO: [APUAPC] D2_APC_1: 0xffffffff
9913 20:15:32.231568 INFO: [APUAPC] D2_APC_2: 0x3fffff
9914 20:15:32.234553 INFO: [APUAPC] D2_APC_3: 0x0
9915 20:15:32.238197 INFO: [APUAPC] D3_APC_0: 0xffffffff
9916 20:15:32.241476 INFO: [APUAPC] D3_APC_1: 0xffffffff
9917 20:15:32.244747 INFO: [APUAPC] D3_APC_2: 0x3fffff
9918 20:15:32.247861 INFO: [APUAPC] D3_APC_3: 0x0
9919 20:15:32.251158 INFO: [APUAPC] D4_APC_0: 0xffffffff
9920 20:15:32.254602 INFO: [APUAPC] D4_APC_1: 0xffffffff
9921 20:15:32.257750 INFO: [APUAPC] D4_APC_2: 0x3fffff
9922 20:15:32.258269 INFO: [APUAPC] D4_APC_3: 0x0
9923 20:15:32.261174 INFO: [APUAPC] D5_APC_0: 0xffffffff
9924 20:15:32.268100 INFO: [APUAPC] D5_APC_1: 0xffffffff
9925 20:15:32.270990 INFO: [APUAPC] D5_APC_2: 0x3fffff
9926 20:15:32.271457 INFO: [APUAPC] D5_APC_3: 0x0
9927 20:15:32.274820 INFO: [APUAPC] D6_APC_0: 0xffffffff
9928 20:15:32.277833 INFO: [APUAPC] D6_APC_1: 0xffffffff
9929 20:15:32.281223 INFO: [APUAPC] D6_APC_2: 0x3fffff
9930 20:15:32.284438 INFO: [APUAPC] D6_APC_3: 0x0
9931 20:15:32.288202 INFO: [APUAPC] D7_APC_0: 0xffffffff
9932 20:15:32.291268 INFO: [APUAPC] D7_APC_1: 0xffffffff
9933 20:15:32.294596 INFO: [APUAPC] D7_APC_2: 0x3fffff
9934 20:15:32.297984 INFO: [APUAPC] D7_APC_3: 0x0
9935 20:15:32.301560 INFO: [APUAPC] D8_APC_0: 0xffffffff
9936 20:15:32.304625 INFO: [APUAPC] D8_APC_1: 0xffffffff
9937 20:15:32.307843 INFO: [APUAPC] D8_APC_2: 0x3fffff
9938 20:15:32.311206 INFO: [APUAPC] D8_APC_3: 0x0
9939 20:15:32.314287 INFO: [APUAPC] D9_APC_0: 0xffffffff
9940 20:15:32.317646 INFO: [APUAPC] D9_APC_1: 0xffffffff
9941 20:15:32.320907 INFO: [APUAPC] D9_APC_2: 0x3fffff
9942 20:15:32.324339 INFO: [APUAPC] D9_APC_3: 0x0
9943 20:15:32.327606 INFO: [APUAPC] D10_APC_0: 0xffffffff
9944 20:15:32.330664 INFO: [APUAPC] D10_APC_1: 0xffffffff
9945 20:15:32.334224 INFO: [APUAPC] D10_APC_2: 0x3fffff
9946 20:15:32.337371 INFO: [APUAPC] D10_APC_3: 0x0
9947 20:15:32.340719 INFO: [APUAPC] D11_APC_0: 0xffffffff
9948 20:15:32.343967 INFO: [APUAPC] D11_APC_1: 0xffffffff
9949 20:15:32.347374 INFO: [APUAPC] D11_APC_2: 0x3fffff
9950 20:15:32.350560 INFO: [APUAPC] D11_APC_3: 0x0
9951 20:15:32.353666 INFO: [APUAPC] D12_APC_0: 0xffffffff
9952 20:15:32.356902 INFO: [APUAPC] D12_APC_1: 0xffffffff
9953 20:15:32.360418 INFO: [APUAPC] D12_APC_2: 0x3fffff
9954 20:15:32.363628 INFO: [APUAPC] D12_APC_3: 0x0
9955 20:15:32.367399 INFO: [APUAPC] D13_APC_0: 0xffffffff
9956 20:15:32.370056 INFO: [APUAPC] D13_APC_1: 0xffffffff
9957 20:15:32.374105 INFO: [APUAPC] D13_APC_2: 0x3fffff
9958 20:15:32.376867 INFO: [APUAPC] D13_APC_3: 0x0
9959 20:15:32.380238 INFO: [APUAPC] D14_APC_0: 0xffffffff
9960 20:15:32.383258 INFO: [APUAPC] D14_APC_1: 0xffffffff
9961 20:15:32.386728 INFO: [APUAPC] D14_APC_2: 0x3fffff
9962 20:15:32.390029 INFO: [APUAPC] D14_APC_3: 0x0
9963 20:15:32.393507 INFO: [APUAPC] D15_APC_0: 0xffffffff
9964 20:15:32.396704 INFO: [APUAPC] D15_APC_1: 0xffffffff
9965 20:15:32.400414 INFO: [APUAPC] D15_APC_2: 0x3fffff
9966 20:15:32.403660 INFO: [APUAPC] D15_APC_3: 0x0
9967 20:15:32.406600 INFO: [APUAPC] APC_CON: 0x4
9968 20:15:32.410096 INFO: [NOCDAPC] D0_APC_0: 0x0
9969 20:15:32.413279 INFO: [NOCDAPC] D0_APC_1: 0x0
9970 20:15:32.416708 INFO: [NOCDAPC] D1_APC_0: 0x0
9971 20:15:32.420004 INFO: [NOCDAPC] D1_APC_1: 0xfff
9972 20:15:32.423483 INFO: [NOCDAPC] D2_APC_0: 0x0
9973 20:15:32.426694 INFO: [NOCDAPC] D2_APC_1: 0xfff
9974 20:15:32.427263 INFO: [NOCDAPC] D3_APC_0: 0x0
9975 20:15:32.430223 INFO: [NOCDAPC] D3_APC_1: 0xfff
9976 20:15:32.433521 INFO: [NOCDAPC] D4_APC_0: 0x0
9977 20:15:32.436934 INFO: [NOCDAPC] D4_APC_1: 0xfff
9978 20:15:32.439996 INFO: [NOCDAPC] D5_APC_0: 0x0
9979 20:15:32.443179 INFO: [NOCDAPC] D5_APC_1: 0xfff
9980 20:15:32.446434 INFO: [NOCDAPC] D6_APC_0: 0x0
9981 20:15:32.449740 INFO: [NOCDAPC] D6_APC_1: 0xfff
9982 20:15:32.453233 INFO: [NOCDAPC] D7_APC_0: 0x0
9983 20:15:32.456446 INFO: [NOCDAPC] D7_APC_1: 0xfff
9984 20:15:32.459524 INFO: [NOCDAPC] D8_APC_0: 0x0
9985 20:15:32.462901 INFO: [NOCDAPC] D8_APC_1: 0xfff
9986 20:15:32.463361 INFO: [NOCDAPC] D9_APC_0: 0x0
9987 20:15:32.466531 INFO: [NOCDAPC] D9_APC_1: 0xfff
9988 20:15:32.470055 INFO: [NOCDAPC] D10_APC_0: 0x0
9989 20:15:32.473022 INFO: [NOCDAPC] D10_APC_1: 0xfff
9990 20:15:32.476188 INFO: [NOCDAPC] D11_APC_0: 0x0
9991 20:15:32.479886 INFO: [NOCDAPC] D11_APC_1: 0xfff
9992 20:15:32.483087 INFO: [NOCDAPC] D12_APC_0: 0x0
9993 20:15:32.486340 INFO: [NOCDAPC] D12_APC_1: 0xfff
9994 20:15:32.489507 INFO: [NOCDAPC] D13_APC_0: 0x0
9995 20:15:32.493445 INFO: [NOCDAPC] D13_APC_1: 0xfff
9996 20:15:32.496575 INFO: [NOCDAPC] D14_APC_0: 0x0
9997 20:15:32.499580 INFO: [NOCDAPC] D14_APC_1: 0xfff
9998 20:15:32.503148 INFO: [NOCDAPC] D15_APC_0: 0x0
9999 20:15:32.506478 INFO: [NOCDAPC] D15_APC_1: 0xfff
10000 20:15:32.507152 INFO: [NOCDAPC] APC_CON: 0x4
10001 20:15:32.509861 INFO: [APUAPC] set_apusys_apc done
10002 20:15:32.512639 INFO: [DEVAPC] devapc_init done
10003 20:15:32.519636 INFO: GICv3 without legacy support detected.
10004 20:15:32.522718 INFO: ARM GICv3 driver initialized in EL3
10005 20:15:32.526519 INFO: Maximum SPI INTID supported: 639
10006 20:15:32.529572 INFO: BL31: Initializing runtime services
10007 20:15:32.536519 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10008 20:15:32.539262 INFO: SPM: enable CPC mode
10009 20:15:32.542690 INFO: mcdi ready for mcusys-off-idle and system suspend
10010 20:15:32.548990 INFO: BL31: Preparing for EL3 exit to normal world
10011 20:15:32.552688 INFO: Entry point address = 0x80000000
10012 20:15:32.553304 INFO: SPSR = 0x8
10013 20:15:32.559683
10014 20:15:32.560146
10015 20:15:32.560520
10016 20:15:32.562968 Starting depthcharge on Spherion...
10017 20:15:32.563536
10018 20:15:32.564131 Wipe memory regions:
10019 20:15:32.564723
10020 20:15:32.567358 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10021 20:15:32.567947 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10022 20:15:32.568431 Setting prompt string to ['asurada:']
10023 20:15:32.568916 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10024 20:15:32.569765 [0x00000040000000, 0x00000054600000)
10025 20:15:32.688672
10026 20:15:32.689240 [0x00000054660000, 0x00000080000000)
10027 20:15:32.948857
10028 20:15:32.949011 [0x000000821a7280, 0x000000ffe64000)
10029 20:15:33.693831
10030 20:15:33.694043 [0x00000100000000, 0x00000240000000)
10031 20:15:35.584331
10032 20:15:35.587157 Initializing XHCI USB controller at 0x11200000.
10033 20:15:36.626277
10034 20:15:36.629250 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10035 20:15:36.629360
10036 20:15:36.629453
10037 20:15:36.629530
10038 20:15:36.629812 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 20:15:36.730170 asurada: tftpboot 192.168.201.1 12928131/tftp-deploy-47lgp2yt/kernel/image.itb 12928131/tftp-deploy-47lgp2yt/kernel/cmdline
10041 20:15:36.730316 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 20:15:36.730405 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10043 20:15:36.735206 tftpboot 192.168.201.1 12928131/tftp-deploy-47lgp2yt/kernel/image.itbtp-deploy-47lgp2yt/kernel/cmdline
10044 20:15:36.735289
10045 20:15:36.735358 Waiting for link
10046 20:15:36.895250
10047 20:15:36.895383 R8152: Initializing
10048 20:15:36.895459
10049 20:15:36.898685 Version 9 (ocp_data = 6010)
10050 20:15:36.898759
10051 20:15:36.902215 R8152: Done initializing
10052 20:15:36.902291
10053 20:15:36.902358 Adding net device
10054 20:15:38.847924
10055 20:15:38.848608 done.
10056 20:15:38.849138
10057 20:15:38.849564 MAC: 00:e0:4c:72:2d:d6
10058 20:15:38.850109
10059 20:15:38.850984 Sending DHCP discover... done.
10060 20:15:38.851390
10061 20:15:51.290072 Waiting for reply... R8152: Bulk read error 0xffffffbf
10062 20:15:51.290223
10063 20:15:51.293566 Receive failed.
10064 20:15:51.293641
10065 20:15:51.293704 done.
10066 20:15:51.293768
10067 20:15:51.296859 Sending DHCP request... done.
10068 20:15:51.297004
10069 20:15:51.300318 Waiting for reply... done.
10070 20:15:51.300418
10071 20:15:51.300507 My ip is 192.168.201.21
10072 20:15:51.300596
10073 20:15:51.303352 The DHCP server ip is 192.168.201.1
10074 20:15:51.303452
10075 20:15:51.310108 TFTP server IP predefined by user: 192.168.201.1
10076 20:15:51.310184
10077 20:15:51.316750 Bootfile predefined by user: 12928131/tftp-deploy-47lgp2yt/kernel/image.itb
10078 20:15:51.316853
10079 20:15:51.316944 Sending tftp read request... done.
10080 20:15:51.320158
10081 20:15:51.320262 Waiting for the transfer...
10082 20:15:51.320353
10083 20:15:51.572039 00000000 ################################################################
10084 20:15:51.572203
10085 20:15:51.823299 00080000 ################################################################
10086 20:15:51.823466
10087 20:15:52.073804 00100000 ################################################################
10088 20:15:52.073974
10089 20:15:52.323000 00180000 ################################################################
10090 20:15:52.323167
10091 20:15:52.577408 00200000 ################################################################
10092 20:15:52.577576
10093 20:15:52.826651 00280000 ################################################################
10094 20:15:52.826818
10095 20:15:53.078084 00300000 ################################################################
10096 20:15:53.078237
10097 20:15:53.338816 00380000 ################################################################
10098 20:15:53.338966
10099 20:15:53.592350 00400000 ################################################################
10100 20:15:53.592504
10101 20:15:53.845417 00480000 ################################################################
10102 20:15:53.845566
10103 20:15:54.107038 00500000 ################################################################
10104 20:15:54.107184
10105 20:15:54.356695 00580000 ################################################################
10106 20:15:54.356844
10107 20:15:54.607334 00600000 ################################################################
10108 20:15:54.607467
10109 20:15:54.857152 00680000 ################################################################
10110 20:15:54.857301
10111 20:15:55.106007 00700000 ################################################################
10112 20:15:55.106155
10113 20:15:55.353412 00780000 ################################################################
10114 20:15:55.353557
10115 20:15:55.603635 00800000 ################################################################
10116 20:15:55.603806
10117 20:15:55.855679 00880000 ################################################################
10118 20:15:55.855828
10119 20:15:56.112650 00900000 ################################################################
10120 20:15:56.112803
10121 20:15:56.363929 00980000 ################################################################
10122 20:15:56.364074
10123 20:15:56.614676 00a00000 ################################################################
10124 20:15:56.614820
10125 20:15:56.862902 00a80000 ################################################################
10126 20:15:56.863043
10127 20:15:57.111133 00b00000 ################################################################
10128 20:15:57.111267
10129 20:15:57.360490 00b80000 ################################################################
10130 20:15:57.360639
10131 20:15:57.609824 00c00000 ################################################################
10132 20:15:57.610026
10133 20:15:57.862235 00c80000 ################################################################
10134 20:15:57.862377
10135 20:15:58.111318 00d00000 ################################################################
10136 20:15:58.111470
10137 20:15:58.366449 00d80000 ################################################################
10138 20:15:58.366603
10139 20:15:58.624510 00e00000 ################################################################
10140 20:15:58.624643
10141 20:15:58.873083 00e80000 ################################################################
10142 20:15:58.873233
10143 20:15:59.132055 00f00000 ################################################################
10144 20:15:59.132202
10145 20:15:59.380800 00f80000 ################################################################
10146 20:15:59.380948
10147 20:15:59.630157 01000000 ################################################################
10148 20:15:59.630303
10149 20:15:59.888370 01080000 ################################################################
10150 20:15:59.888531
10151 20:16:00.141304 01100000 ################################################################
10152 20:16:00.141445
10153 20:16:00.391332 01180000 ################################################################
10154 20:16:00.391485
10155 20:16:00.641604 01200000 ################################################################
10156 20:16:00.641757
10157 20:16:00.891475 01280000 ################################################################
10158 20:16:00.891610
10159 20:16:01.141838 01300000 ################################################################
10160 20:16:01.142048
10161 20:16:01.391489 01380000 ################################################################
10162 20:16:01.391661
10163 20:16:01.640827 01400000 ################################################################
10164 20:16:01.640978
10165 20:16:01.888898 01480000 ################################################################
10166 20:16:01.889029
10167 20:16:02.137669 01500000 ################################################################
10168 20:16:02.137818
10169 20:16:02.385906 01580000 ################################################################
10170 20:16:02.386077
10171 20:16:02.634451 01600000 ################################################################
10172 20:16:02.634590
10173 20:16:02.883885 01680000 ################################################################
10174 20:16:02.884035
10175 20:16:03.133854 01700000 ################################################################
10176 20:16:03.134045
10177 20:16:03.382195 01780000 ################################################################
10178 20:16:03.382347
10179 20:16:03.630433 01800000 ################################################################
10180 20:16:03.630602
10181 20:16:03.880174 01880000 ################################################################
10182 20:16:03.880332
10183 20:16:04.130072 01900000 ################################################################
10184 20:16:04.130223
10185 20:16:04.379409 01980000 ################################################################
10186 20:16:04.379555
10187 20:16:04.627525 01a00000 ################################################################
10188 20:16:04.627670
10189 20:16:04.877617 01a80000 ################################################################
10190 20:16:04.877795
10191 20:16:05.133980 01b00000 ################################################################
10192 20:16:05.134127
10193 20:16:05.383811 01b80000 ################################################################
10194 20:16:05.383965
10195 20:16:05.632756 01c00000 ################################################################
10196 20:16:05.632899
10197 20:16:05.880123 01c80000 ################################################################
10198 20:16:05.880266
10199 20:16:06.149719 01d00000 ################################################################
10200 20:16:06.149859
10201 20:16:06.419368 01d80000 ################################################################
10202 20:16:06.419504
10203 20:16:06.700058 01e00000 ################################################################
10204 20:16:06.700197
10205 20:16:06.952380 01e80000 ################################################################
10206 20:16:06.952531
10207 20:16:07.202627 01f00000 ################################################################
10208 20:16:07.202777
10209 20:16:07.460755 01f80000 ################################################################
10210 20:16:07.460908
10211 20:16:07.709679 02000000 ################################################################
10212 20:16:07.709818
10213 20:16:07.970331 02080000 ################################################################
10214 20:16:07.970470
10215 20:16:08.222545 02100000 ################################################################
10216 20:16:08.222691
10217 20:16:08.473351 02180000 ################################################################
10218 20:16:08.473523
10219 20:16:08.721543 02200000 ################################################################
10220 20:16:08.721716
10221 20:16:08.970688 02280000 ################################################################
10222 20:16:08.970861
10223 20:16:09.218605 02300000 ################################################################
10224 20:16:09.218778
10225 20:16:09.468706 02380000 ################################################################
10226 20:16:09.468876
10227 20:16:09.717153 02400000 ################################################################
10228 20:16:09.717323
10229 20:16:09.975841 02480000 ################################################################
10230 20:16:09.976003
10231 20:16:10.250108 02500000 ################################################################
10232 20:16:10.250286
10233 20:16:10.499411 02580000 ################################################################
10234 20:16:10.499553
10235 20:16:10.748713 02600000 ################################################################
10236 20:16:10.748862
10237 20:16:10.996874 02680000 ################################################################
10238 20:16:10.997009
10239 20:16:11.246822 02700000 ################################################################
10240 20:16:11.246967
10241 20:16:11.497885 02780000 ################################################################
10242 20:16:11.498072
10243 20:16:11.746842 02800000 ################################################################
10244 20:16:11.746995
10245 20:16:11.995630 02880000 ################################################################
10246 20:16:11.995787
10247 20:16:12.247654 02900000 ################################################################
10248 20:16:12.247806
10249 20:16:12.498132 02980000 ################################################################
10250 20:16:12.498281
10251 20:16:12.752395 02a00000 ################################################################
10252 20:16:12.752537
10253 20:16:13.003059 02a80000 ################################################################
10254 20:16:13.003208
10255 20:16:13.257446 02b00000 ################################################################
10256 20:16:13.257600
10257 20:16:13.531844 02b80000 ################################################################
10258 20:16:13.531981
10259 20:16:13.811430 02c00000 ################################################################
10260 20:16:13.811579
10261 20:16:14.088564 02c80000 ################################################################
10262 20:16:14.088706
10263 20:16:14.360360 02d00000 ################################################################
10264 20:16:14.360539
10265 20:16:14.614842 02d80000 ################################################################
10266 20:16:14.614999
10267 20:16:14.876296 02e00000 ################################################################
10268 20:16:14.876438
10269 20:16:15.148477 02e80000 ################################################################
10270 20:16:15.148622
10271 20:16:15.398156 02f00000 ################################################################
10272 20:16:15.398305
10273 20:16:15.652331 02f80000 ################################################################
10274 20:16:15.652482
10275 20:16:15.900628 03000000 ################################################################
10276 20:16:15.900777
10277 20:16:16.149841 03080000 ################################################################
10278 20:16:16.150046
10279 20:16:16.398986 03100000 ################################################################
10280 20:16:16.399141
10281 20:16:16.648669 03180000 ################################################################
10282 20:16:16.648833
10283 20:16:16.896930 03200000 ################################################################
10284 20:16:16.897105
10285 20:16:17.146344 03280000 ################################################################
10286 20:16:17.146483
10287 20:16:17.397681 03300000 ################################################################
10288 20:16:17.397858
10289 20:16:17.649690 03380000 ################################################################
10290 20:16:17.649840
10291 20:16:17.899037 03400000 ################################################################
10292 20:16:17.899215
10293 20:16:18.152806 03480000 ################################################################
10294 20:16:18.153002
10295 20:16:18.405602 03500000 ################################################################
10296 20:16:18.405738
10297 20:16:18.657676 03580000 ################################################################
10298 20:16:18.657821
10299 20:16:18.905717 03600000 ################################################################
10300 20:16:18.905905
10301 20:16:19.154904 03680000 ################################################################
10302 20:16:19.155084
10303 20:16:19.404597 03700000 ################################################################
10304 20:16:19.404752
10305 20:16:19.653250 03780000 ################################################################
10306 20:16:19.653425
10307 20:16:19.906261 03800000 ################################################################
10308 20:16:19.906409
10309 20:16:20.104726 03880000 ################################################### done.
10310 20:16:20.104899
10311 20:16:20.107993 The bootfile was 59654986 bytes long.
10312 20:16:20.108101
10313 20:16:20.111336 Sending tftp read request... done.
10314 20:16:20.111437
10315 20:16:20.111529 Waiting for the transfer...
10316 20:16:20.114620
10317 20:16:20.114700 00000000 # done.
10318 20:16:20.114768
10319 20:16:20.121278 Command line loaded dynamically from TFTP file: 12928131/tftp-deploy-47lgp2yt/kernel/cmdline
10320 20:16:20.121356
10321 20:16:20.134572 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10322 20:16:20.137853
10323 20:16:20.137956 Loading FIT.
10324 20:16:20.138023
10325 20:16:20.141278 Image ramdisk-1 has 47545634 bytes.
10326 20:16:20.141348
10327 20:16:20.144407 Image fdt-1 has 47278 bytes.
10328 20:16:20.144504
10329 20:16:20.147786 Image kernel-1 has 12060038 bytes.
10330 20:16:20.147882
10331 20:16:20.154702 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10332 20:16:20.154775
10333 20:16:20.171015 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10334 20:16:20.174685
10335 20:16:20.177928 Choosing best match conf-1 for compat google,spherion-rev2.
10336 20:16:20.182061
10337 20:16:20.186986 Connected to device vid:did:rid of 1ae0:0028:00
10338 20:16:20.195006
10339 20:16:20.198136 tpm_get_response: command 0x17b, return code 0x0
10340 20:16:20.198210
10341 20:16:20.201568 ec_init: CrosEC protocol v3 supported (256, 248)
10342 20:16:20.207026
10343 20:16:20.210399 tpm_cleanup: add release locality here.
10344 20:16:20.210500
10345 20:16:20.210594 Shutting down all USB controllers.
10346 20:16:20.213833
10347 20:16:20.213931 Removing current net device
10348 20:16:20.214002
10349 20:16:20.220405 Exiting depthcharge with code 4 at timestamp: 76942461
10350 20:16:20.220484
10351 20:16:20.223996 LZMA decompressing kernel-1 to 0x821a6718
10352 20:16:20.224066
10353 20:16:20.227033 LZMA decompressing kernel-1 to 0x40000000
10354 20:16:21.726962
10355 20:16:21.727576 jumping to kernel
10356 20:16:21.732100 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10357 20:16:21.732235 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10358 20:16:21.732339 Setting prompt string to ['Linux version [0-9]']
10359 20:16:21.732438 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10360 20:16:21.732535 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10361 20:16:21.808516
10362 20:16:21.811646 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10363 20:16:21.815328 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10364 20:16:21.815443 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10365 20:16:21.815544 Setting prompt string to []
10366 20:16:21.815651 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10367 20:16:21.815756 Using line separator: #'\n'#
10368 20:16:21.815844 No login prompt set.
10369 20:16:21.815938 Parsing kernel messages
10370 20:16:21.816024 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10371 20:16:21.816196 [login-action] Waiting for messages, (timeout 00:03:36)
10372 20:16:21.816291 Waiting using forced prompt support (timeout 00:01:48)
10373 20:16:21.835345 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10374 20:16:21.838498 [ 0.000000] random: crng init done
10375 20:16:21.845021 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10376 20:16:21.848259 [ 0.000000] efi: UEFI not found.
10377 20:16:21.855075 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10378 20:16:21.861685 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10379 20:16:21.871386 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10380 20:16:21.881624 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10381 20:16:21.887910 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10382 20:16:21.894355 [ 0.000000] printk: bootconsole [mtk8250] enabled
10383 20:16:21.901395 [ 0.000000] NUMA: No NUMA configuration found
10384 20:16:21.907963 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10385 20:16:21.911091 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10386 20:16:21.914500 [ 0.000000] Zone ranges:
10387 20:16:21.920952 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10388 20:16:21.924212 [ 0.000000] DMA32 empty
10389 20:16:21.930759 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10390 20:16:21.934354 [ 0.000000] Movable zone start for each node
10391 20:16:21.937749 [ 0.000000] Early memory node ranges
10392 20:16:21.944030 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10393 20:16:21.951055 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10394 20:16:21.957584 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10395 20:16:21.964421 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10396 20:16:21.970743 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10397 20:16:21.977662 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10398 20:16:22.033374 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10399 20:16:22.039935 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10400 20:16:22.046476 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10401 20:16:22.049859 [ 0.000000] psci: probing for conduit method from DT.
10402 20:16:22.056420 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10403 20:16:22.059766 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10404 20:16:22.066498 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10405 20:16:22.069803 [ 0.000000] psci: SMC Calling Convention v1.2
10406 20:16:22.076576 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10407 20:16:22.079743 [ 0.000000] Detected VIPT I-cache on CPU0
10408 20:16:22.086229 [ 0.000000] CPU features: detected: GIC system register CPU interface
10409 20:16:22.093011 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10410 20:16:22.099400 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10411 20:16:22.106203 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10412 20:16:22.113347 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10413 20:16:22.119991 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10414 20:16:22.126157 [ 0.000000] alternatives: applying boot alternatives
10415 20:16:22.129542 [ 0.000000] Fallback order for Node 0: 0
10416 20:16:22.139486 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10417 20:16:22.139568 [ 0.000000] Policy zone: Normal
10418 20:16:22.155777 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10419 20:16:22.165626 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10420 20:16:22.177447 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10421 20:16:22.187492 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10422 20:16:22.194068 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10423 20:16:22.197215 <6>[ 0.000000] software IO TLB: area num 8.
10424 20:16:22.253990 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10425 20:16:22.402944 <6>[ 0.000000] Memory: 7920768K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 432000K reserved, 32768K cma-reserved)
10426 20:16:22.409435 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10427 20:16:22.416131 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10428 20:16:22.419292 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10429 20:16:22.426280 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10430 20:16:22.432769 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10431 20:16:22.436140 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10432 20:16:22.445980 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10433 20:16:22.452798 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10434 20:16:22.459250 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10435 20:16:22.466002 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10436 20:16:22.469321 <6>[ 0.000000] GICv3: 608 SPIs implemented
10437 20:16:22.472293 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10438 20:16:22.478937 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10439 20:16:22.482537 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10440 20:16:22.489535 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10441 20:16:22.502284 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10442 20:16:22.515300 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10443 20:16:22.522483 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10444 20:16:22.529870 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10445 20:16:22.542847 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10446 20:16:22.549363 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10447 20:16:22.555935 <6>[ 0.009231] Console: colour dummy device 80x25
10448 20:16:22.566165 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10449 20:16:22.572469 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10450 20:16:22.575670 <6>[ 0.029269] LSM: Security Framework initializing
10451 20:16:22.582413 <6>[ 0.034236] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 20:16:22.592475 <6>[ 0.042051] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 20:16:22.602227 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10454 20:16:22.605468 <6>[ 0.058897] cblist_init_generic: Setting shift to 3 and lim to 1.
10455 20:16:22.615440 <6>[ 0.065236] cblist_init_generic: Setting adjustable number of callback queues.
10456 20:16:22.621976 <6>[ 0.072663] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 20:16:22.625301 <6>[ 0.079101] rcu: Hierarchical SRCU implementation.
10458 20:16:22.631828 <6>[ 0.079103] rcu: Max phase no-delay instances is 1000.
10459 20:16:22.638590 <6>[ 0.079127] printk: bootconsole [mtk8250] printing thread started
10460 20:16:22.645054 <6>[ 0.097423] EFI services will not be available.
10461 20:16:22.648403 <6>[ 0.097600] smp: Bringing up secondary CPUs ...
10462 20:16:22.654843 <6>[ 0.097908] Detected VIPT I-cache on CPU1
10463 20:16:22.661569 <6>[ 0.097976] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10464 20:16:22.668253 <6>[ 0.098008] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10465 20:16:22.677819 <6>[ 0.125899] Detected VIPT I-cache on CPU2
10466 20:16:22.684413 <6>[ 0.125950] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10467 20:16:22.694627 <6>[ 0.125966] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10468 20:16:22.697677 <6>[ 0.126225] Detected VIPT I-cache on CPU3
10469 20:16:22.704107 <6>[ 0.126273] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10470 20:16:22.710946 <6>[ 0.126286] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10471 20:16:22.714239 <6>[ 0.126598] CPU features: detected: Spectre-v4
10472 20:16:22.721085 <6>[ 0.126604] CPU features: detected: Spectre-BHB
10473 20:16:22.724301 <6>[ 0.126609] Detected PIPT I-cache on CPU4
10474 20:16:22.730605 <6>[ 0.126668] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10475 20:16:22.737292 <6>[ 0.126685] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10476 20:16:22.744353 <6>[ 0.126979] Detected PIPT I-cache on CPU5
10477 20:16:22.750554 <6>[ 0.127039] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10478 20:16:22.756982 <6>[ 0.127055] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10479 20:16:22.760747 <6>[ 0.127330] Detected PIPT I-cache on CPU6
10480 20:16:22.767141 <6>[ 0.127394] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10481 20:16:22.773750 <6>[ 0.127410] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10482 20:16:22.780165 <6>[ 0.127703] Detected PIPT I-cache on CPU7
10483 20:16:22.787166 <6>[ 0.127767] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10484 20:16:22.793391 <6>[ 0.127783] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10485 20:16:22.796518 <6>[ 0.127830] smp: Brought up 1 node, 8 CPUs
10486 20:16:22.803236 <6>[ 0.127835] SMP: Total of 8 processors activated.
10487 20:16:22.806689 <6>[ 0.127837] CPU features: detected: 32-bit EL0 Support
10488 20:16:22.816756 <6>[ 0.127839] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10489 20:16:22.823700 <6>[ 0.127842] CPU features: detected: Common not Private translations
10490 20:16:22.829931 <6>[ 0.127844] CPU features: detected: CRC32 instructions
10491 20:16:22.833407 <6>[ 0.127847] CPU features: detected: RCpc load-acquire (LDAPR)
10492 20:16:22.840129 <6>[ 0.127848] CPU features: detected: LSE atomic instructions
10493 20:16:22.846575 <6>[ 0.127850] CPU features: detected: Privileged Access Never
10494 20:16:22.853464 <6>[ 0.127852] CPU features: detected: RAS Extension Support
10495 20:16:22.859871 <6>[ 0.127855] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10496 20:16:22.862809 <6>[ 0.127924] CPU: All CPU(s) started at EL2
10497 20:16:22.869229 <6>[ 0.127926] alternatives: applying system-wide alternatives
10498 20:16:22.897921 ��er�r�jV�<6>[ 0.3<48484] printk: console [ttyS0] printing thread started
10499 20:16:22.900720 6>[ <6>[ 0.348530] printk: console [ttyS0] enabled
10500 20:16:22.907472 0.225489] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10501 20:16:22.916524 <6>[ 0.348534] printk: bootconsole [mtk8250] disabled
10502 20:16:22.922827 <6>[ 0.365897] printk: bootconsole [mtk8250] printing thread stopped
10503 20:16:22.926365 <6>[ 0.367235] SuperH (H)SCI(F) driver initialized
10504 20:16:22.933007 <6>[ 0.367722] msm_serial: driver initialized
10505 20:16:22.939933 <6>[ 0.372331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10506 20:16:22.949251 <6>[ 0.372364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10507 20:16:22.955861 <6>[ 0.372393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10508 20:16:22.975560 <6>[ 0.372422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10509 20:16:22.984459 <6>[ 0.372444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10510 20:16:22.984897 <6>[ 0.372474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10511 20:16:23.000633 <6>[ 0.372503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10512 20:16:23.005165 <6>[ 0.372613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10513 20:16:23.014311 <6>[ 0.372642] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10514 20:16:23.014395 <6>[ 0.384456] loop: module loaded
10515 20:16:23.023487 <6>[ 0.386975] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10516 20:16:23.026798 <4>[ 0.403913] mtk-pmic-keys: Failed to locate of_node [id: -1]
10517 20:16:23.030489 <6>[ 0.404817] megasas: 07.719.03.00-rc1
10518 20:16:23.034130 <6>[ 0.416720] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10519 20:16:23.040408 <6>[ 0.425601] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10520 20:16:23.046984 <6>[ 0.428666] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10521 20:16:23.056983 <6>[ 0.481768] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10522 20:16:24.800158 <6>[ 2.251729] Freeing initrd memory: 46424K
10523 20:16:24.808018 <6>[ 2.257833] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10524 20:16:24.814493 <6>[ 2.262661] tun: Universal TUN/TAP device driver, 1.6
10525 20:16:24.818064 <6>[ 2.263424] thunder_xcv, ver 1.0
10526 20:16:24.821317 <6>[ 2.263442] thunder_bgx, ver 1.0
10527 20:16:24.824651 <6>[ 2.263455] nicpf, ver 1.0
10528 20:16:24.831601 <6>[ 2.264505] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10529 20:16:24.838103 <6>[ 2.264508] hns3: Copyright (c) 2017 Huawei Corporation.
10530 20:16:24.841163 <6>[ 2.264533] hclge is initializing
10531 20:16:24.844541 <6>[ 2.264548] e1000: Intel(R) PRO/1000 Network Driver
10532 20:16:24.851694 <6>[ 2.264550] e1000: Copyright (c) 1999-2006 Intel Corporation.
10533 20:16:24.858888 <6>[ 2.264569] e1000e: Intel(R) PRO/1000 Network Driver
10534 20:16:24.862351 <6>[ 2.264570] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10535 20:16:24.869494 <6>[ 2.264585] igb: Intel(R) Gigabit Ethernet Network Driver
10536 20:16:24.875980 <6>[ 2.264587] igb: Copyright (c) 2007-2014 Intel Corporation.
10537 20:16:24.882828 <6>[ 2.264602] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10538 20:16:24.889186 <6>[ 2.264604] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10539 20:16:24.892652 <6>[ 2.264896] sky2: driver version 1.30
10540 20:16:24.895887 <6>[ 2.265969] VFIO - User Level meta-driver version: 0.3
10541 20:16:24.902448 <6>[ 2.268791] usbcore: registered new interface driver usb-storage
10542 20:16:24.909319 <6>[ 2.268973] usbcore: registered new device driver onboard-usb-hub
10543 20:16:24.916024 <6>[ 2.271787] mt6397-rtc mt6359-rtc: registered as rtc0
10544 20:16:24.922326 <6>[ 2.271940] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:15:47 UTC (1709496947)
10545 20:16:24.929092 <6>[ 2.272551] i2c_dev: i2c /dev entries driver
10546 20:16:24.935649 <6>[ 2.279741] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10547 20:16:24.942311 <6>[ 2.294726] cpu cpu0: EM: created perf domain
10548 20:16:24.945653 <6>[ 2.295065] cpu cpu4: EM: created perf domain
10549 20:16:24.952684 <6>[ 2.299563] sdhci: Secure Digital Host Controller Interface driver
10550 20:16:24.955913 <6>[ 2.299565] sdhci: Copyright(c) Pierre Ossman
10551 20:16:24.962240 <6>[ 2.299933] Synopsys Designware Multimedia Card Interface Driver
10552 20:16:24.968827 <6>[ 2.300309] sdhci-pltfm: SDHCI platform and OF driver helper
10553 20:16:24.975511 <6>[ 2.304560] ledtrig-cpu: registered to indicate activity on CPUs
10554 20:16:24.978546 <6>[ 2.305249] mmc0: CQHCI version 5.10
10555 20:16:24.985270 <6>[ 2.305347] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10556 20:16:24.991951 <6>[ 2.305628] usbcore: registered new interface driver usbhid
10557 20:16:24.995395 <6>[ 2.305629] usbhid: USB HID core driver
10558 20:16:25.001538 <6>[ 2.305760] spi_master spi0: will run message pump with realtime priority
10559 20:16:25.015037 <6>[ 2.334965] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10560 20:16:25.028372 <6>[ 2.337999] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10561 20:16:25.035081 <6>[ 2.339159] cros-ec-spi spi0.0: Chrome EC device registered
10562 20:16:25.044625 <6>[ 2.355548] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10563 20:16:25.048326 <6>[ 2.357873] NET: Registered PF_PACKET protocol family
10564 20:16:25.054727 <6>[ 2.357973] 9pnet: Installing 9P2000 support
10565 20:16:25.057761 <5>[ 2.358017] Key type dns_resolver registered
10566 20:16:25.061106 <6>[ 2.358445] registered taskstats version 1
10567 20:16:25.068114 <5>[ 2.358465] Loading compiled-in X.509 certificates
10568 20:16:25.078068 <4>[ 2.378694] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 20:16:25.087516 <4>[ 2.378860] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 20:16:25.094418 <3>[ 2.378875] debugfs: File 'uA_load' in directory '/' already present!
10571 20:16:25.100650 <3>[ 2.378884] debugfs: File 'min_uV' in directory '/' already present!
10572 20:16:25.107483 <3>[ 2.378887] debugfs: File 'max_uV' in directory '/' already present!
10573 20:16:25.117303 <3>[ 2.378891] debugfs: File 'constraint_flags' in directory '/' already present!
10574 20:16:25.123957 <3>[ 2.380986] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10575 20:16:25.130707 <6>[ 2.389291] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10576 20:16:25.137168 <6>[ 2.389964] xhci-mtk 11200000.usb: xHCI Host Controller
10577 20:16:25.143587 <6>[ 2.389981] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10578 20:16:25.153728 <6>[ 2.390243] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10579 20:16:25.160201 <6>[ 2.390296] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10580 20:16:25.163570 <6>[ 2.390403] xhci-mtk 11200000.usb: xHCI Host Controller
10581 20:16:25.173434 <6>[ 2.390428] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10582 20:16:25.180417 <6>[ 2.390437] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10583 20:16:25.183308 <6>[ 2.390965] hub 1-0:1.0: USB hub found
10584 20:16:25.187158 <6>[ 2.390986] hub 1-0:1.0: 1 port detected
10585 20:16:25.196435 <6>[ 2.391191] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10586 20:16:25.199948 <6>[ 2.391556] hub 2-0:1.0: USB hub found
10587 20:16:25.203491 <6>[ 2.391572] hub 2-0:1.0: 1 port detected
10588 20:16:25.209760 <6>[ 2.394921] mtk-msdc 11f70000.mmc: Got CD GPIO
10589 20:16:25.213202 <6>[ 2.404040] mmc0: Command Queue Engine enabled
10590 20:16:25.219827 <6>[ 2.404053] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 20:16:25.226120 <6>[ 2.404801] mmcblk0: mmc0:0001 DA4128 116 GiB
10592 20:16:25.229618 <6>[ 2.408706] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10593 20:16:25.236242 <6>[ 2.409900] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 20:16:25.242923 <6>[ 2.410376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10595 20:16:25.252967 <6>[ 2.410384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10596 20:16:25.256025 <6>[ 2.410529] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10597 20:16:25.266228 <4>[ 2.410561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10598 20:16:25.272891 <6>[ 2.411146] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10599 20:16:25.279390 <6>[ 2.411206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10600 20:16:25.289127 <6>[ 2.411210] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10601 20:16:25.295852 <6>[ 2.411324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10602 20:16:25.302867 <6>[ 2.411335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10603 20:16:25.312754 <6>[ 2.411343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10604 20:16:25.322207 <6>[ 2.411348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10605 20:16:25.328967 <6>[ 2.412941] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10606 20:16:25.338956 <6>[ 2.412958] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10607 20:16:25.345804 <6>[ 2.412963] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10608 20:16:25.355627 <6>[ 2.412969] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10609 20:16:25.362486 <6>[ 2.412974] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10610 20:16:25.372086 <6>[ 2.412979] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10611 20:16:25.379103 <6>[ 2.412984] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10612 20:16:25.389267 <6>[ 2.412989] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10613 20:16:25.395536 <6>[ 2.412994] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10614 20:16:25.405350 <6>[ 2.412999] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10615 20:16:25.411854 <6>[ 2.413005] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10616 20:16:25.422015 <6>[ 2.413010] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10617 20:16:25.428561 <6>[ 2.413015] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10618 20:16:25.438392 <6>[ 2.413020] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10619 20:16:25.445149 <6>[ 2.413025] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10620 20:16:25.451697 <6>[ 2.413659] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10621 20:16:25.458211 <6>[ 2.414552] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10622 20:16:25.464900 <6>[ 2.415103] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10623 20:16:25.471608 <6>[ 2.415728] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10624 20:16:25.478254 <6>[ 2.416359] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10625 20:16:25.488131 <6>[ 2.416554] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10626 20:16:25.497900 <6>[ 2.416570] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10627 20:16:25.507782 <6>[ 2.416576] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10628 20:16:25.514646 <6>[ 2.416582] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10629 20:16:25.524423 <6>[ 2.416588] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10630 20:16:25.534604 <6>[ 2.416594] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10631 20:16:25.544307 <6>[ 2.416600] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10632 20:16:25.554600 <6>[ 2.416606] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10633 20:16:25.561111 <6>[ 2.416611] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10634 20:16:25.574342 <6>[ 2.416618] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10635 20:16:25.583968 <6>[ 2.416623] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10636 20:16:25.590712 <6>[ 2.417097] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10637 20:16:25.597435 <6>[ 2.777693] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10638 20:16:25.600719 <6>[ 2.808420] hub 2-1:1.0: USB hub found
10639 20:16:25.607435 <6>[ 2.808766] hub 2-1:1.0: 3 ports detected
10640 20:16:25.610964 <6>[ 2.811225] hub 2-1:1.0: USB hub found
10641 20:16:25.613566 <6>[ 2.811531] hub 2-1:1.0: 3 ports detected
10642 20:16:25.620339 <6>[ 2.929448] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10643 20:16:25.631892 <6>[ 3.081918] hub 1-1:1.0: USB hub found
10644 20:16:25.635158 <6>[ 3.082318] hub 1-1:1.0: 4 ports detected
10645 20:16:25.638633 <6>[ 3.086141] hub 1-1:1.0: USB hub found
10646 20:16:25.641744 <6>[ 3.086521] hub 1-1:1.0: 4 ports detected
10647 20:16:25.715685 <6>[ 3.161821] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10648 20:16:25.951211 <6>[ 3.397660] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10649 20:16:26.076116 <6>[ 3.525636] hub 1-1.4:1.0: USB hub found
10650 20:16:26.079575 <6>[ 3.526095] hub 1-1.4:1.0: 2 ports detected
10651 20:16:26.082466 <6>[ 3.530263] hub 1-1.4:1.0: USB hub found
10652 20:16:26.089076 <6>[ 3.530619] hub 1-1.4:1.0: 2 ports detected
10653 20:16:26.371497 <6>[ 3.817598] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10654 20:16:26.555157 <6>[ 4.001634] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10655 20:16:37.267792 <6>[ 14.722670] ALSA device list:
10656 20:16:37.274435 <6>[ 14.722693] No soundcards found.
10657 20:16:37.277738 <6>[ 14.727142] Freeing unused kernel memory: 8448K
10658 20:16:37.281349 <6>[ 14.727292] Run /init as init process
10659 20:16:37.302843 <6>[ 14.757310] NET: Registered PF_INET6 protocol family
10660 20:16:37.305747 <6>[ 14.758342] Segment Routing with IPv6
10661 20:16:37.312532 <6>[ 14.758353] In-situ OAM (IOAM) with IPv6
10662 20:16:37.320203
10663 20:16:37.346622 Welcome to [1mDebian GNU/Linux 11 (bullseye)<30>[ 14.777695] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10664 20:16:37.350233 <30>[ 14.778132] systemd[1]: Detected architecture arm64.
10665 20:16:37.353184 [0m!
10666 20:16:37.353267
10667 20:16:37.370804 <30>[ 14.821859] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10668 20:16:37.489748 <30>[ 14.940675] systemd[1]: Queued start job for default target Graphical Interface.
10669 20:16:37.539476 [[0;32m OK [0m] Created slic<30>[ 14.990746] systemd[1]: Created slice system-getty.slice.
10670 20:16:37.542532 e [0;1;39msystem-getty.slice[0m.
10671 20:16:37.567241 [[0;32m OK [0m] Created slic<30>[ 15.018730] systemd[1]: Created slice system-modprobe.slice.
10672 20:16:37.570842 e [0;1;39msystem-modprobe.slice[0m.
10673 20:16:37.598327 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.046279] systemd[1]: Created slice system-serial\x2dgetty.slice.
10674 20:16:37.601311 m-serial\x2dgetty.slice[0m.
10675 20:16:37.619874 [[0;32m OK [0m] Created slic<30>[ 15.071318] systemd[1]: Created slice User and Session Slice.
10676 20:16:37.623064 e [0;1;39mUser and Session Slice[0m.
10677 20:16:37.645771 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.093888] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10678 20:16:37.649121 ssword …ts to Console Directory Watch[0m.
10679 20:16:37.669528 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.117785] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10680 20:16:37.673006 sword R…uests to Wall Directory Watch[0m.
10681 20:16:37.696931 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.141712] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10682 20:16:37.707278 l Encrypted Volu<30>[ 15.141901] systemd[1]: Reached target Local Encrypted Volumes.
10683 20:16:37.707365 mes[0m.
10684 20:16:37.726936 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.178162] systemd[1]: Reached target Paths.
10685 20:16:37.727025 s[0m.
10686 20:16:37.749548 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.197626] systemd[1]: Reached target Remote File Systems.
10687 20:16:37.749635 te File Systems[0m.
10688 20:16:37.770664 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.222018] systemd[1]: Reached target Slices.
10689 20:16:37.770749 es[0m.
10690 20:16:37.790733 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.241660] systemd[1]: Reached target Swap.
10691 20:16:37.790838 [0m.
10692 20:16:37.813887 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.262134] systemd[1]: Listening on initctl Compatibility Named Pipe.
10693 20:16:37.817220 l Compatibility Named Pipe[0m.
10694 20:16:37.823870 [[0;32m OK [<30>[ 15.277245] systemd[1]: Listening on Journal Audit Socket.
10695 20:16:37.830533 0m] Listening on [0;1;39mJournal Audit Socket[0m.
10696 20:16:37.848233 [[0;32m OK [0m] Listening on<30>[ 15.298805] systemd[1]: Listening on Journal Socket (/dev/log).
10697 20:16:37.850719 [0;1;39mJournal Socket (/dev/log)[0m.
10698 20:16:37.871529 [[0;32m OK [0m] Listening on<30>[ 15.322879] systemd[1]: Listening on Journal Socket.
10699 20:16:37.875115 [0;1;39mJournal Socket[0m.
10700 20:16:37.894068 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 15.342333] systemd[1]: Listening on Network Service Netlink Socket.
10701 20:16:37.897153 k Service Netlink Socket[0m.
10702 20:16:37.915773 [[0;32m OK [0m] Listening on<30>[ 15.366875] systemd[1]: Listening on udev Control Socket.
10703 20:16:37.919135 [0;1;39mudev Control Socket[0m.
10704 20:16:37.939791 [[0;32m OK [0m] Listening on<30>[ 15.390729] systemd[1]: Listening on udev Kernel Socket.
10705 20:16:37.943224 [0;1;39mudev Kernel Socket[0m.
10706 20:16:38.006056 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.453839] systemd[1]: Mounting Huge Pages File System...
10707 20:16:38.006419 m[0m...
10708 20:16:38.029792 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.477645] systemd[1]: Mounting POSIX Message Queue File System...
10709 20:16:38.030116 ile System[0m...
10710 20:16:38.085478 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.533718] systemd[1]: Mounting Kernel Debug File System...
10711 20:16:38.085590 tem[0m...
10712 20:16:38.105824 <30>[ 15.554020] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10713 20:16:38.115817 <30>[ 15.558098] systemd[1]: Starting Create list of static device nodes for the current kernel...
10714 20:16:38.122613 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10715 20:16:38.149650 Starting [0;1;39mLoad Kernel Module co<30>[ 15.597910] systemd[1]: Starting Load Kernel Module configfs...
10716 20:16:38.149756 nfigfs[0m...
10717 20:16:38.173713 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.621936] systemd[1]: Starting Load Kernel Module drm...
10718 20:16:38.173802 m[0m...
10719 20:16:38.193694 <30>[ 15.641981] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10720 20:16:38.222916 Starting [0;1;39mJournal Service[0m..<30>[ 15.674101] systemd[1]: Starting Journal Service...
10721 20:16:38.223012 .
10722 20:16:38.245189 Startin<30>[ 15.696589] systemd[1]: Starting Load Kernel Modules...
10723 20:16:38.248261 g [0;1;39mLoad Kernel Modules[0m...
10724 20:16:38.268582 Startin<30>[ 15.720133] systemd[1]: Starting Remount Root and Kernel File Systems...
10725 20:16:38.272015 g [0;1;39mRemount Root and Kernel File Systems[0m...
10726 20:16:38.293771 Startin<30>[ 15.744866] systemd[1]: Starting Coldplug All udev Devices...
10727 20:16:38.297280 g [0;1;39mColdplug All udev Devices[0m...
10728 20:16:38.314437 [[0;32m OK [<30>[ 15.769128] systemd[1]: Started Journal Service.
10729 20:16:38.320868 0m] Started [0;1;39mJournal Service[0m.
10730 20:16:38.338195 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10731 20:16:38.355487 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10732 20:16:38.371214 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10733 20:16:38.391896 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10734 20:16:38.409019 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10735 20:16:38.427794 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10736 20:16:38.447620 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10737 20:16:38.472933 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10738 20:16:38.486850 See 'systemctl status systemd-remount-fs.service' for details.
10739 20:16:38.540347 Mounting [0;1;39mKernel Configuration File System[0m...
10740 20:16:38.564517 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10741 20:16:38.577904 <46>[ 16.028975] systemd-journald[187]: Received client request to flush runtime journal.
10742 20:16:38.588757 Starting [0;1;39mLoad/Save Random Seed[0m...
10743 20:16:38.611928 Starting [0;1;39mApply Kernel Variables[0m...
10744 20:16:38.633875 Starting [0;1;39mCreate System Users[0m...
10745 20:16:38.656242 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10746 20:16:38.671603 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10747 20:16:38.691883 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10748 20:16:38.708603 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10749 20:16:38.727752 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10750 20:16:38.744397 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10751 20:16:38.783548 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10752 20:16:38.807019 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10753 20:16:38.823265 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10754 20:16:38.838319 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10755 20:16:38.883538 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10756 20:16:38.908162 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10757 20:16:38.927722 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10758 20:16:38.939816 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10759 20:16:39.008564 Starting [0;1;39mNetwork Service[0m...
10760 20:16:39.040789 Starting [0;1;39mNetwork Time Synchronization[0m...
10761 20:16:39.061695 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10762 20:16:39.098532 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10763 20:16:39.154651 <3>[ 16.602205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 20:16:39.161096 <3>[ 16.602279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 20:16:39.171210 <3>[ 16.602292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 20:16:39.177551 <6>[ 16.609010] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10767 20:16:39.187623 Startin<6>[ 16.609045] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10768 20:16:39.197206 g [0;1;39mLoad/<6>[ 16.609050] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10769 20:16:39.207226 Save Screen …o<3>[ 16.627822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 20:16:39.217546 f leds:white:kbd<3>[ 16.627839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 20:16:39.227362 _backlight[0m..<3>[ 16.627843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 20:16:39.234594 <3>[ 16.627850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 20:16:39.243677 <3>[ 16.627853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 20:16:39.250738 <6>[ 16.633434] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10775 20:16:39.257417 <3>[ 16.647861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 20:16:39.267503 <3>[ 16.663167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 20:16:39.273360 <3>[ 16.663198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 20:16:39.283575 <3>[ 16.663208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 20:16:39.286503 <6>[ 16.663445] remoteproc remoteproc0: scp is available
10780 20:16:39.293261 <6>[ 16.663582] remoteproc remoteproc0: powering up scp
10781 20:16:39.293745 .
10782 20:16:39.299869 <6>[ 16.663589] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10783 20:16:39.306401 <6>[ 16.663645] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10784 20:16:39.316490 <3>[ 16.683843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 20:16:39.324202 <3>[ 16.683858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 20:16:39.334506 [[0;32m OK [0m] Started [0;<3>[ 16.683862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 20:16:39.344338 1;39mNetwork Ser<3>[ 16.683867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 20:16:39.344903 vice[0m.
10789 20:16:39.350900 <3>[ 16.683870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 20:16:39.361016 <3>[ 16.695579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 20:16:39.364575 <6>[ 16.727506] mc: Linux media interface: v0.10
10792 20:16:39.371421 <6>[ 16.728118] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10793 20:16:39.377729 <6>[ 16.728135] pci_bus 0000:00: root bus resource [bus 00-ff]
10794 20:16:39.385053 <6>[ 16.728157] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10795 20:16:39.395025 <6>[ 16.728175] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10796 20:16:39.401933 <6>[ 16.728308] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10797 20:16:39.408554 <6>[ 16.728358] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10798 20:16:39.412253 <6>[ 16.728449] pci 0000:00:00.0: supports D1 D2
10799 20:16:39.419231 <6>[ 16.728453] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10800 20:16:39.428799 [[0;32m OK [<4>[ 16.729088] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10801 20:16:39.435633 <4>[ 16.729258] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10802 20:16:39.445261 0m] Started [0;<6>[ 16.729287] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10803 20:16:39.451981 <6>[ 16.730800] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10804 20:16:39.461881 1;39mNetwork Tim<6>[ 16.733290] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10805 20:16:39.468648 <6>[ 16.733327] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10806 20:16:39.478677 e Synchronizatio<6>[ 16.733374] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10807 20:16:39.479244 n[0m.
10808 20:16:39.485765 <6>[ 16.733393] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10809 20:16:39.488959 <6>[ 16.733518] pci 0000:01:00.0: supports D1 D2
10810 20:16:39.497019 <6>[ 16.733521] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10811 20:16:39.503262 <6>[ 16.739454] usbcore: registered new device driver r8152-cfgselector
10812 20:16:39.510132 <6>[ 16.750266] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10813 20:16:39.517089 <6>[ 16.750317] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10814 20:16:39.527436 <6>[ 16.750320] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10815 20:16:39.534061 <6>[ 16.750333] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10816 20:16:39.544279 [[0;32m OK [<6>[ 16.750348] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10817 20:16:39.550949 <6>[ 16.750361] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10818 20:16:39.557634 0m] Finished [0<6>[ 16.750374] pci 0000:00:00.0: PCI bridge to [bus 01]
10819 20:16:39.567940 <6>[ 16.750381] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10820 20:16:39.574878 ;1;39mLoad/Save <6>[ 16.752049] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10821 20:16:39.581757 Screen …s of l<6>[ 16.758678] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10822 20:16:39.587946 eds:white:kbd_ba<6>[ 16.759102] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10823 20:16:39.591446 cklight[0m.
10824 20:16:39.599151 <4>[ 16.768248] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10825 20:16:39.602154 <4>[ 16.768248] Fallback method does not support PEC.
10826 20:16:39.612529 <3>[ 16.785016] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 20:16:39.619374 <6>[ 16.789596] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10828 20:16:39.626490 <6>[ 16.789616] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10829 20:16:39.636363 [[0;32m OK [0m] Found device<6>[ 16.789639] remoteproc remoteproc0: remote processor scp is now up
10830 20:16:39.647084 [0;1;39m/dev/t<3>[ 16.806149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 20:16:39.647736 tyS0[0m.
10832 20:16:39.656842 <6>[ 16.809864] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10833 20:16:39.666827 <6>[ 16.811398] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10834 20:16:39.676885 <3>[ 16.828712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 20:16:39.687074 <6>[ 16.842061] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10836 20:16:39.693191 <3>[ 16.849173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 20:16:39.699593 <6>[ 16.862422] videodev: Linux video capture interface: v2.00
10838 20:16:39.709763 <3>[ 16.881424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 20:16:39.713127 <6>[ 16.889752] Bluetooth: Core ver 2.22
10840 20:16:39.719865 <6>[ 16.889847] NET: Registered PF_BLUETOOTH protocol family
10841 20:16:39.726254 <6>[ 16.889849] Bluetooth: HCI device and connection manager initialized
10842 20:16:39.729238 <6>[ 16.889883] Bluetooth: HCI socket layer initialized
10843 20:16:39.735724 <6>[ 16.889893] Bluetooth: L2CAP socket layer initialized
10844 20:16:39.739253 <6>[ 16.889910] Bluetooth: SCO socket layer initialized
10845 20:16:39.749557 <5>[ 16.891297] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10846 20:16:39.756280 <6>[ 16.897703] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10847 20:16:39.762763 <5>[ 16.899056] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10848 20:16:39.772249 <5>[ 16.899300] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10849 20:16:39.779497 <4>[ 16.899375] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10850 20:16:39.785698 <6>[ 16.899384] cfg80211: failed to load regulatory.db
10851 20:16:39.792417 <6>[ 16.901404] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10852 20:16:39.801930 <6>[ 16.901936] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10853 20:16:39.808645 <6>[ 16.930201] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10854 20:16:39.822375 <6>[ 16.931872] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10855 20:16:39.829151 <6>[ 16.931987] usbcore: registered new interface driver uvcvideo
10856 20:16:39.835026 <3>[ 16.953274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10857 20:16:39.842189 <6>[ 16.953439] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10858 20:16:39.852132 <3>[ 16.954230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 20:16:39.858708 <6>[ 16.958174] usbcore: registered new interface driver btusb
10860 20:16:39.865705 <3>[ 16.958831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 20:16:39.878633 <4>[ 16.959266] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10862 20:16:39.881367 <3>[ 16.959283] Bluetooth: hci0: Failed to load firmware file (-2)
10863 20:16:39.888010 <3>[ 16.959289] Bluetooth: hci0: Failed to set up firmware (-2)
10864 20:16:39.898305 <4>[ 16.959295] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10865 20:16:39.904582 <6>[ 16.970700] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10866 20:16:39.914502 <3>[ 16.979562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 20:16:39.917570 <6>[ 17.001765] r8152 2-1.3:1.0 eth0: v1.12.13
10868 20:16:39.924541 <6>[ 17.001866] usbcore: registered new interface driver r8152
10869 20:16:39.934719 <3>[ 17.002069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 20:16:39.940835 <6>[ 17.013701] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10871 20:16:39.947800 <6>[ 17.013801] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10872 20:16:39.951065 <6>[ 17.033484] mt7921e 0000:01:00.0: ASIC revision: 79610010
10873 20:16:39.957859 <6>[ 17.033824] usbcore: registered new interface driver cdc_ether
10874 20:16:39.965240 <6>[ 17.041222] usbcore: registered new interface driver r8153_ecm
10875 20:16:39.970732 <6>[ 17.061512] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10876 20:16:39.977830 <6>[ 17.128196] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10877 20:16:39.981156 <6>[ 17.128196]
10878 20:16:39.990781 <6>[ 17.385039] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10879 20:16:39.997357 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10880 20:16:40.059432 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10881 20:16:40.074832 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10882 20:16:40.094363 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10883 20:16:40.106813 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10884 20:16:40.126099 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10885 20:16:40.143972 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10886 20:16:40.159483 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10887 20:16:40.178823 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10888 20:16:40.191077 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10889 20:16:40.207000 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10890 20:16:40.226949 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10891 20:16:40.255617 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10892 20:16:40.286581 Starting [0;1;39mUser Login Management[0m...
10893 20:16:40.306612 Starting [0;1;39mNetwork Name Resolution[0m...
10894 20:16:40.328181 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10895 20:16:40.344216 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10896 20:16:40.361131 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10897 20:16:40.396360 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10898 20:16:40.415974 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10899 20:16:40.435221 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10900 20:16:40.476886 Starting [0;1;39mPermit User Sessions[0m...
10901 20:16:40.494883 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10902 20:16:40.518227 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10903 20:16:40.536734 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10904 20:16:40.551900 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10905 20:16:40.567825 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10906 20:16:40.584245 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10907 20:16:40.648657 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10908 20:16:40.687018 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10909 20:16:40.727522
10910 20:16:40.728080
10911 20:16:40.730781 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10912 20:16:40.731345
10913 20:16:40.734569 debian-bullseye-arm64 login: root (automatic login)
10914 20:16:40.735134
10915 20:16:40.735502
10916 20:16:40.749093 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10917 20:16:40.749667
10918 20:16:40.755856 The programs included with the Debian GNU/Linux system are free software;
10919 20:16:40.762780 the exact distribution terms for each program are described in the
10920 20:16:40.765847 individual files in /usr/share/doc/*/copyright.
10921 20:16:40.766455
10922 20:16:40.771967 Debian GNU<6>[ 18.224686] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10923 20:16:40.779028 /Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10924 20:16:40.782057 permitted by applicable law.
10925 20:16:40.783631 Matched prompt #10: / #
10927 20:16:40.784746 Setting prompt string to ['/ #']
10928 20:16:40.785216 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10930 20:16:40.786310 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10931 20:16:40.786793 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
10932 20:16:40.787198 Setting prompt string to ['/ #']
10933 20:16:40.787541 Forcing a shell prompt, looking for ['/ #']
10935 20:16:40.838386 / #
10936 20:16:40.839066 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10937 20:16:40.839640 Waiting using forced prompt support (timeout 00:02:30)
10938 20:16:40.844708
10939 20:16:40.845651 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10940 20:16:40.846246 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
10941 20:16:40.846783 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10942 20:16:40.847270 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
10943 20:16:40.847736 end: 2 depthcharge-action (duration 00:01:43) [common]
10944 20:16:40.848214 start: 3 lava-test-retry (timeout 00:05:00) [common]
10945 20:16:40.848686 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10946 20:16:40.849080 Using namespace: common
10948 20:16:40.950262 / # #
10949 20:16:40.950958 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10950 20:16:40.957143 #
10951 20:16:40.958037 Using /lava-12928131
10953 20:16:41.059449 / # export SHELL=/bin/sh
10954 20:16:41.065990 export SHELL=/bin/sh
10956 20:16:41.167756 / # . /lava-12928131/environment
10957 20:16:41.168554 . /lava-12928131/environment<6>[ 18.587881] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
10958 20:16:41.168988 <6>[ 18.588378] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10959 20:16:41.174080
10961 20:16:41.275932 / # /lava-12928131/bin/lava-test-runner /lava-12928131/0
10962 20:16:41.276612 Test shell timeout: 10s (minimum of the action and connection timeout)
10963 20:16:41.282574 /lava-12928131/bin/lava-test-runner /lava-12928131/0
10964 20:16:41.302594 + export TESTRUN_ID=0_cros-ec
10965 20:16:41.312816 + cd /lava-12928131/0/tests/0_cros-<8>[ 18.762964] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12928131_1.5.2.3.1>
10966 20:16:41.313399 ec
10967 20:16:41.313776 + cat uuid
10968 20:16:41.314461 Received signal: <STARTRUN> 0_cros-ec 12928131_1.5.2.3.1
10969 20:16:41.314844 Starting test lava.0_cros-ec (12928131_1.5.2.3.1)
10970 20:16:41.315286 Skipping test definition patterns.
10971 20:16:41.315838 + UUID=12928131_1.5.2.3.1
10972 20:16:41.316204 + set +x
10973 20:16:41.322200 + python3 -m cros.runners.lava_runner -v
10974 20:16:41.710994 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10975 20:16:41.717572 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10976 20:16:41.721183
10977 20:16:41.724449 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10979 20:16:41.727428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10980 20:16:41.733996 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10981 20:16:41.740798 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10982 20:16:41.741359
10983 20:16:41.751047 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
10984 20:16:41.751590 Bad test result: ski<8
10985 20:16:41.754345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 19.207268] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12928131_1.5.2.3.1>
10986 20:16:41.755112 Received signal: <ENDRUN> 0_cros-ec 12928131_1.5.2.3.1
10987 20:16:41.755526 Ending use of test pattern.
10988 20:16:41.755872 Ending test lava.0_cros-ec (12928131_1.5.2.3.1), duration 0.44
10990 20:16:41.757714 p>
10991 20:16:41.760632 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10992 20:16:41.767367 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10993 20:16:41.767831
10994 20:16:41.774097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10995 20:16:41.774815 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10997 20:16:41.780666 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10998 20:16:41.786975 Checks the standard ABI for the main Embedded Controller. ... ok
10999 20:16:41.787394
11000 20:16:41.790421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11001 20:16:41.791084 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11003 20:16:41.796679 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11004 20:16:41.803426 Checks the main Embedded controller character device. ... ok
11005 20:16:41.803891
11006 20:16:41.807105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11007 20:16:41.807961 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11009 20:16:41.814135 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11010 20:16:41.820302 Checks basic comunication with the main Embedded controller. ... ok
11011 20:16:41.820871
11012 20:16:41.826805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11013 20:16:41.827710 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11015 20:16:41.830052 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11016 20:16:41.839963 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11017 20:16:41.840562
11018 20:16:41.843348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11019 20:16:41.844108 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11021 20:16:41.850029 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11022 20:16:41.856395 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11023 20:16:41.856819
11024 20:16:41.863161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11025 20:16:41.863949 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11027 20:16:41.869484 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11028 20:16:41.876175 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11029 20:16:41.876750
11030 20:16:41.883127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11031 20:16:41.883842 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11033 20:16:41.886130 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11034 20:16:41.896309 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11035 20:16:41.896929
11036 20:16:41.899394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11037 20:16:41.900209 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11039 20:16:41.906263 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11040 20:16:41.912762 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11041 20:16:41.916099
11042 20:16:41.919852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11043 20:16:41.920694 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11045 20:16:41.925909 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11046 20:16:41.932643 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11047 20:16:41.933241
11048 20:16:41.939259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11049 20:16:41.939931 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11051 20:16:41.942369 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11052 20:16:41.952531 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11053 20:16:41.953018
11054 20:16:41.959425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11055 20:16:41.960303 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11057 20:16:41.962049 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11058 20:16:41.972073 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11059 20:16:41.972161
11060 20:16:41.978876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11061 20:16:41.979134 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11063 20:16:41.985252 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11064 20:16:41.992034 Check the cros battery ABI. ... skipped 'No BAT found'
11065 20:16:41.992137
11066 20:16:41.995231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11067 20:16:41.995555 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11069 20:16:42.002004 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11070 20:16:42.008651 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11071 20:16:42.011763
11072 20:16:42.018541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11073 20:16:42.019006 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11075 20:16:42.022281 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11076 20:16:42.028807 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11077 20:16:42.029209
11078 20:16:42.035803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11079 20:16:42.036560 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11081 20:16:42.041933 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11082 20:16:42.048754 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11083 20:16:42.049177
11084 20:16:42.055005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11085 20:16:42.055474
11086 20:16:42.056073 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11088 20:16:42.061896 ----------------------------------------------------------------------
11089 20:16:42.065206 Ran 18 tests in 0.006s
11090 20:16:42.065743
11091 20:16:42.066130 OK (skipped=15)
11092 20:16:42.066456 + set +x
11093 20:16:42.068532 <LAVA_TEST_RUNNER EXIT>
11094 20:16:42.069220 ok: lava_test_shell seems to have completed
11095 20:16:42.070112 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11096 20:16:42.070581 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11097 20:16:42.071010 end: 3 lava-test-retry (duration 00:00:01) [common]
11098 20:16:42.071444 start: 4 finalize (timeout 00:07:55) [common]
11099 20:16:42.071885 start: 4.1 power-off (timeout 00:00:30) [common]
11100 20:16:42.072642 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11101 20:16:42.186119 >> Command sent successfully.
11102 20:16:42.190062 Returned 0 in 0 seconds
11103 20:16:42.291058 end: 4.1 power-off (duration 00:00:00) [common]
11105 20:16:42.292591 start: 4.2 read-feedback (timeout 00:07:55) [common]
11106 20:16:42.293802 Listened to connection for namespace 'common' for up to 1s
11107 20:16:43.294237 Finalising connection for namespace 'common'
11108 20:16:43.294942 Disconnecting from shell: Finalise
11109 20:16:43.295345 / #
11110 20:16:43.396349 end: 4.2 read-feedback (duration 00:00:01) [common]
11111 20:16:43.397131 end: 4 finalize (duration 00:00:01) [common]
11112 20:16:43.397800 Cleaning after the job
11113 20:16:43.398366 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/ramdisk
11114 20:16:43.423621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/kernel
11115 20:16:43.439670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/dtb
11116 20:16:43.440025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928131/tftp-deploy-47lgp2yt/modules
11117 20:16:43.448547 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928131
11118 20:16:43.547829 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928131
11119 20:16:43.548008 Job finished correctly