Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 26
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 13
1 20:10:46.731916 lava-dispatcher, installed at version: 2024.01
2 20:10:46.732135 start: 0 validate
3 20:10:46.732270 Start time: 2024-03-03 20:10:46.732263+00:00 (UTC)
4 20:10:46.732396 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:10:46.732529 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240129.0%2Farm64%2Frootfs.cpio.gz exists
6 20:10:47.002462 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:10:47.003191 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:10:48.774240 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:10:48.774937 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:10:49.036955 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:10:49.037754 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:10:51.797630 validate duration: 5.07
14 20:10:51.797936 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:10:51.798043 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:10:51.798128 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:10:51.798252 Not decompressing ramdisk as can be used compressed.
18 20:10:51.798335 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240129.0/arm64/rootfs.cpio.gz
19 20:10:51.798399 saving as /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/ramdisk/rootfs.cpio.gz
20 20:10:51.798463 total size: 47861385 (45 MB)
21 20:10:51.799768 progress 0 % (0 MB)
22 20:10:51.813508 progress 5 % (2 MB)
23 20:10:51.826577 progress 10 % (4 MB)
24 20:10:51.839489 progress 15 % (6 MB)
25 20:10:51.852269 progress 20 % (9 MB)
26 20:10:51.864864 progress 25 % (11 MB)
27 20:10:51.877552 progress 30 % (13 MB)
28 20:10:51.890471 progress 35 % (16 MB)
29 20:10:51.903133 progress 40 % (18 MB)
30 20:10:51.916184 progress 45 % (20 MB)
31 20:10:51.929270 progress 50 % (22 MB)
32 20:10:51.942995 progress 55 % (25 MB)
33 20:10:51.956343 progress 60 % (27 MB)
34 20:10:51.969786 progress 65 % (29 MB)
35 20:10:51.983569 progress 70 % (31 MB)
36 20:10:51.997543 progress 75 % (34 MB)
37 20:10:52.010892 progress 80 % (36 MB)
38 20:10:52.024563 progress 85 % (38 MB)
39 20:10:52.038056 progress 90 % (41 MB)
40 20:10:52.051447 progress 95 % (43 MB)
41 20:10:52.064607 progress 100 % (45 MB)
42 20:10:52.064982 45 MB downloaded in 0.27 s (171.26 MB/s)
43 20:10:52.065194 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:10:52.065581 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:10:52.065698 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:10:52.065812 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:10:52.065996 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:10:52.066122 saving as /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/kernel/Image
50 20:10:52.066240 total size: 51601920 (49 MB)
51 20:10:52.066358 No compression specified
52 20:10:52.068163 progress 0 % (0 MB)
53 20:10:52.082744 progress 5 % (2 MB)
54 20:10:52.097531 progress 10 % (4 MB)
55 20:10:52.112089 progress 15 % (7 MB)
56 20:10:52.126233 progress 20 % (9 MB)
57 20:10:52.140397 progress 25 % (12 MB)
58 20:10:52.155044 progress 30 % (14 MB)
59 20:10:52.169088 progress 35 % (17 MB)
60 20:10:52.183158 progress 40 % (19 MB)
61 20:10:52.197009 progress 45 % (22 MB)
62 20:10:52.211023 progress 50 % (24 MB)
63 20:10:52.225185 progress 55 % (27 MB)
64 20:10:52.239239 progress 60 % (29 MB)
65 20:10:52.253041 progress 65 % (32 MB)
66 20:10:52.268367 progress 70 % (34 MB)
67 20:10:52.282659 progress 75 % (36 MB)
68 20:10:52.296857 progress 80 % (39 MB)
69 20:10:52.311328 progress 85 % (41 MB)
70 20:10:52.325336 progress 90 % (44 MB)
71 20:10:52.338975 progress 95 % (46 MB)
72 20:10:52.352293 progress 100 % (49 MB)
73 20:10:52.352581 49 MB downloaded in 0.29 s (171.87 MB/s)
74 20:10:52.352742 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:10:52.352977 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:10:52.353071 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:10:52.353158 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:10:52.353308 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:10:52.353383 saving as /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/dtb/mt8192-asurada-spherion-r0.dtb
81 20:10:52.353446 total size: 47278 (0 MB)
82 20:10:52.353509 No compression specified
83 20:10:52.354628 progress 69 % (0 MB)
84 20:10:52.354912 progress 100 % (0 MB)
85 20:10:52.355076 0 MB downloaded in 0.00 s (27.71 MB/s)
86 20:10:52.355202 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:10:52.355429 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:10:52.355516 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:10:52.355605 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:10:52.355735 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:10:52.355805 saving as /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/modules/modules.tar
93 20:10:52.355867 total size: 8632284 (8 MB)
94 20:10:52.355930 Using unxz to decompress xz
95 20:10:52.360475 progress 0 % (0 MB)
96 20:10:52.381236 progress 5 % (0 MB)
97 20:10:52.406065 progress 10 % (0 MB)
98 20:10:52.431251 progress 15 % (1 MB)
99 20:10:52.454615 progress 20 % (1 MB)
100 20:10:52.479621 progress 25 % (2 MB)
101 20:10:52.506388 progress 30 % (2 MB)
102 20:10:52.534886 progress 35 % (2 MB)
103 20:10:52.562486 progress 40 % (3 MB)
104 20:10:52.588984 progress 45 % (3 MB)
105 20:10:52.614460 progress 50 % (4 MB)
106 20:10:52.639847 progress 55 % (4 MB)
107 20:10:52.666430 progress 60 % (4 MB)
108 20:10:52.692329 progress 65 % (5 MB)
109 20:10:52.718838 progress 70 % (5 MB)
110 20:10:52.746130 progress 75 % (6 MB)
111 20:10:52.779310 progress 80 % (6 MB)
112 20:10:52.809831 progress 85 % (7 MB)
113 20:10:52.837424 progress 90 % (7 MB)
114 20:10:52.867160 progress 95 % (7 MB)
115 20:10:52.896973 progress 100 % (8 MB)
116 20:10:52.902758 8 MB downloaded in 0.55 s (15.05 MB/s)
117 20:10:52.903034 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:10:52.903308 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:10:52.903408 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:10:52.903505 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:10:52.903586 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:10:52.903690 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:10:52.903923 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro
125 20:10:52.904062 makedir: /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin
126 20:10:52.904169 makedir: /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/tests
127 20:10:52.904271 makedir: /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/results
128 20:10:52.904389 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-add-keys
129 20:10:52.904550 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-add-sources
130 20:10:52.904682 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-background-process-start
131 20:10:52.904816 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-background-process-stop
132 20:10:52.904946 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-common-functions
133 20:10:52.905075 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-echo-ipv4
134 20:10:52.905203 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-install-packages
135 20:10:52.905331 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-installed-packages
136 20:10:52.905458 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-os-build
137 20:10:52.905587 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-probe-channel
138 20:10:52.905714 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-probe-ip
139 20:10:52.905843 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-target-ip
140 20:10:52.905969 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-target-mac
141 20:10:52.906096 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-target-storage
142 20:10:52.906236 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-case
143 20:10:52.906388 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-event
144 20:10:52.906516 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-feedback
145 20:10:52.906643 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-raise
146 20:10:52.906770 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-reference
147 20:10:52.906898 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-runner
148 20:10:52.907027 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-set
149 20:10:52.907157 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-test-shell
150 20:10:52.907289 Updating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-install-packages (oe)
151 20:10:52.907445 Updating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/bin/lava-installed-packages (oe)
152 20:10:52.907580 Creating /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/environment
153 20:10:52.907695 LAVA metadata
154 20:10:52.907773 - LAVA_JOB_ID=12928116
155 20:10:52.907840 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:10:52.907947 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:10:52.908015 skipped lava-vland-overlay
158 20:10:52.908090 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:10:52.908173 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:10:52.908236 skipped lava-multinode-overlay
161 20:10:52.908309 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:10:52.908393 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:10:52.908468 Loading test definitions
164 20:10:52.908561 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 20:10:52.908635 Using /lava-12928116 at stage 0
166 20:10:52.908948 uuid=12928116_1.5.2.3.1 testdef=None
167 20:10:52.909037 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 20:10:52.909124 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 20:10:52.909677 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 20:10:52.909899 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 20:10:52.910600 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 20:10:52.910837 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 20:10:52.911458 runner path: /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/0/tests/0_igt-gpu-panfrost test_uuid 12928116_1.5.2.3.1
176 20:10:52.911620 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 20:10:52.911862 Creating lava-test-runner.conf files
179 20:10:52.911925 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928116/lava-overlay-_7jg6pro/lava-12928116/0 for stage 0
180 20:10:52.912015 - 0_igt-gpu-panfrost
181 20:10:52.912112 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 20:10:52.912198 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 20:10:52.919815 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 20:10:52.919948 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 20:10:52.920043 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 20:10:52.920131 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 20:10:52.920216 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 20:10:54.790568 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 20:10:54.790955 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 20:10:54.791073 extracting modules file /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928116/extract-overlay-ramdisk-stw49vnb/ramdisk
191 20:10:55.022729 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 20:10:55.022913 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 20:10:55.023016 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928116/compress-overlay-xkyaa740/overlay-1.5.2.4.tar.gz to ramdisk
194 20:10:55.023093 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928116/compress-overlay-xkyaa740/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928116/extract-overlay-ramdisk-stw49vnb/ramdisk
195 20:10:55.029818 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 20:10:55.029941 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 20:10:55.030035 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 20:10:55.030128 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 20:10:55.030212 Building ramdisk /var/lib/lava/dispatcher/tmp/12928116/extract-overlay-ramdisk-stw49vnb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928116/extract-overlay-ramdisk-stw49vnb/ramdisk
200 20:10:56.349093 >> 465518 blocks
201 20:11:02.603246 rename /var/lib/lava/dispatcher/tmp/12928116/extract-overlay-ramdisk-stw49vnb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/ramdisk/ramdisk.cpio.gz
202 20:11:02.603955 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 20:11:02.604199 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 20:11:02.604411 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 20:11:02.604637 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/kernel/Image'
206 20:11:16.442089 Returned 0 in 13 seconds
207 20:11:16.542816 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/kernel/image.itb
208 20:11:17.464066 output: FIT description: Kernel Image image with one or more FDT blobs
209 20:11:17.464447 output: Created: Sun Mar 3 20:11:17 2024
210 20:11:17.464523 output: Image 0 (kernel-1)
211 20:11:17.464595 output: Description:
212 20:11:17.464659 output: Created: Sun Mar 3 20:11:17 2024
213 20:11:17.464725 output: Type: Kernel Image
214 20:11:17.464786 output: Compression: lzma compressed
215 20:11:17.464848 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
216 20:11:17.464904 output: Architecture: AArch64
217 20:11:17.464961 output: OS: Linux
218 20:11:17.465017 output: Load Address: 0x00000000
219 20:11:17.465071 output: Entry Point: 0x00000000
220 20:11:17.465125 output: Hash algo: crc32
221 20:11:17.465179 output: Hash value: 91cb1a17
222 20:11:17.465231 output: Image 1 (fdt-1)
223 20:11:17.465285 output: Description: mt8192-asurada-spherion-r0
224 20:11:17.465341 output: Created: Sun Mar 3 20:11:17 2024
225 20:11:17.465394 output: Type: Flat Device Tree
226 20:11:17.465447 output: Compression: uncompressed
227 20:11:17.465500 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 20:11:17.465553 output: Architecture: AArch64
229 20:11:17.465605 output: Hash algo: crc32
230 20:11:17.465658 output: Hash value: cc4352de
231 20:11:17.465710 output: Image 2 (ramdisk-1)
232 20:11:17.465762 output: Description: unavailable
233 20:11:17.465814 output: Created: Sun Mar 3 20:11:17 2024
234 20:11:17.465867 output: Type: RAMDisk Image
235 20:11:17.465919 output: Compression: Unknown Compression
236 20:11:17.465971 output: Data Size: 60993553 Bytes = 59564.02 KiB = 58.17 MiB
237 20:11:17.466024 output: Architecture: AArch64
238 20:11:17.466076 output: OS: Linux
239 20:11:17.466127 output: Load Address: unavailable
240 20:11:17.466179 output: Entry Point: unavailable
241 20:11:17.466231 output: Hash algo: crc32
242 20:11:17.466283 output: Hash value: 31cc3a6a
243 20:11:17.466334 output: Default Configuration: 'conf-1'
244 20:11:17.466386 output: Configuration 0 (conf-1)
245 20:11:17.466438 output: Description: mt8192-asurada-spherion-r0
246 20:11:17.466490 output: Kernel: kernel-1
247 20:11:17.466541 output: Init Ramdisk: ramdisk-1
248 20:11:17.466593 output: FDT: fdt-1
249 20:11:17.466645 output: Loadables: kernel-1
250 20:11:17.466697 output:
251 20:11:17.466904 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 20:11:17.467007 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 20:11:17.467109 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 20:11:17.467207 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 20:11:17.467306 No LXC device requested
256 20:11:17.467387 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 20:11:17.467476 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 20:11:17.467555 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 20:11:17.467627 Checking files for TFTP limit of 4294967296 bytes.
260 20:11:17.468174 end: 1 tftp-deploy (duration 00:00:26) [common]
261 20:11:17.468276 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 20:11:17.468368 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 20:11:17.468495 substitutions:
264 20:11:17.468561 - {DTB}: 12928116/tftp-deploy-6ddh4bb_/dtb/mt8192-asurada-spherion-r0.dtb
265 20:11:17.468626 - {INITRD}: 12928116/tftp-deploy-6ddh4bb_/ramdisk/ramdisk.cpio.gz
266 20:11:17.468686 - {KERNEL}: 12928116/tftp-deploy-6ddh4bb_/kernel/Image
267 20:11:17.468743 - {LAVA_MAC}: None
268 20:11:17.468799 - {PRESEED_CONFIG}: None
269 20:11:17.468854 - {PRESEED_LOCAL}: None
270 20:11:17.468908 - {RAMDISK}: 12928116/tftp-deploy-6ddh4bb_/ramdisk/ramdisk.cpio.gz
271 20:11:17.468962 - {ROOT_PART}: None
272 20:11:17.469016 - {ROOT}: None
273 20:11:17.469069 - {SERVER_IP}: 192.168.201.1
274 20:11:17.469123 - {TEE}: None
275 20:11:17.469177 Parsed boot commands:
276 20:11:17.469233 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 20:11:17.469409 Parsed boot commands: tftpboot 192.168.201.1 12928116/tftp-deploy-6ddh4bb_/kernel/image.itb 12928116/tftp-deploy-6ddh4bb_/kernel/cmdline
278 20:11:17.469498 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 20:11:17.469586 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 20:11:17.469679 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 20:11:17.469761 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 20:11:17.469832 Not connected, no need to disconnect.
283 20:11:17.469905 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 20:11:17.469983 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 20:11:17.470052 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 20:11:17.474275 Setting prompt string to ['lava-test: # ']
287 20:11:17.474649 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 20:11:17.474758 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 20:11:17.474855 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 20:11:17.474989 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 20:11:17.475234 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 20:11:22.609290 >> Command sent successfully.
293 20:11:22.612183 Returned 0 in 5 seconds
294 20:11:22.712552 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 20:11:22.712875 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 20:11:22.712974 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 20:11:22.713063 Setting prompt string to 'Starting depthcharge on Spherion...'
299 20:11:22.713134 Changing prompt to 'Starting depthcharge on Spherion...'
300 20:11:22.713199 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 20:11:22.713458 [Enter `^Ec?' for help]
302 20:11:22.886684
303 20:11:22.887178
304 20:11:22.887532 F0: 102B 0000
305 20:11:22.887920
306 20:11:22.888242 F3: 1001 0000 [0200]
307 20:11:22.888565
308 20:11:22.889496 F3: 1001 0000
309 20:11:22.889929
310 20:11:22.890269 F7: 102D 0000
311 20:11:22.890588
312 20:11:22.893696 F1: 0000 0000
313 20:11:22.894275
314 20:11:22.894684 V0: 0000 0000 [0001]
315 20:11:22.895024
316 20:11:22.895335 00: 0007 8000
317 20:11:22.895666
318 20:11:22.897485 01: 0000 0000
319 20:11:22.897923
320 20:11:22.898266 BP: 0C00 0209 [0000]
321 20:11:22.898589
322 20:11:22.900854 G0: 1182 0000
323 20:11:22.901287
324 20:11:22.901632 EC: 0000 0021 [4000]
325 20:11:22.901955
326 20:11:22.904428 S7: 0000 0000 [0000]
327 20:11:22.904862
328 20:11:22.905204 CC: 0000 0000 [0001]
329 20:11:22.905527
330 20:11:22.908174 T0: 0000 0040 [010F]
331 20:11:22.908719
332 20:11:22.909118 Jump to BL
333 20:11:22.909579
334 20:11:22.932713
335 20:11:22.933277
336 20:11:22.933635
337 20:11:22.939381 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 20:11:22.943783 ARM64: Exception handlers installed.
339 20:11:22.946958 ARM64: Testing exception
340 20:11:22.950163 ARM64: Done test exception
341 20:11:22.957857 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 20:11:22.968467 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 20:11:22.975181 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 20:11:22.985407 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 20:11:22.992546 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 20:11:22.998744 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 20:11:23.010040 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 20:11:23.016586 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 20:11:23.036199 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 20:11:23.039162 WDT: Last reset was cold boot
351 20:11:23.042323 SPI1(PAD0) initialized at 2873684 Hz
352 20:11:23.046050 SPI5(PAD0) initialized at 992727 Hz
353 20:11:23.048786 VBOOT: Loading verstage.
354 20:11:23.056253 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 20:11:23.059323 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 20:11:23.062771 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 20:11:23.066080 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 20:11:23.073352 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 20:11:23.079893 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 20:11:23.090988 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 20:11:23.091567
362 20:11:23.092043
363 20:11:23.101177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 20:11:23.103817 ARM64: Exception handlers installed.
365 20:11:23.107582 ARM64: Testing exception
366 20:11:23.110504 ARM64: Done test exception
367 20:11:23.113706 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 20:11:23.120502 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 20:11:23.132248 Probing TPM: . done!
370 20:11:23.132812 TPM ready after 0 ms
371 20:11:23.139141 Connected to device vid:did:rid of 1ae0:0028:00
372 20:11:23.146321 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 20:11:23.201791 Initialized TPM device CR50 revision 0
374 20:11:23.213946 tlcl_send_startup: Startup return code is 0
375 20:11:23.214374 TPM: setup succeeded
376 20:11:23.225838 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 20:11:23.234598 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 20:11:23.246337 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 20:11:23.255691 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 20:11:23.258936 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 20:11:23.266258 in-header: 03 07 00 00 08 00 00 00
382 20:11:23.269829 in-data: aa e4 47 04 13 02 00 00
383 20:11:23.273119 Chrome EC: UHEPI supported
384 20:11:23.280513 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 20:11:23.284577 in-header: 03 ad 00 00 08 00 00 00
386 20:11:23.287787 in-data: 00 20 20 08 00 00 00 00
387 20:11:23.288223 Phase 1
388 20:11:23.291622 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 20:11:23.298514 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 20:11:23.301549 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 20:11:23.304854 Recovery requested (1009000e)
392 20:11:23.315623 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 20:11:23.321253 tlcl_extend: response is 0
394 20:11:23.332814 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 20:11:23.336004 tlcl_extend: response is 0
396 20:11:23.343201 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 20:11:23.363477 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 20:11:23.370058 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 20:11:23.370592
400 20:11:23.370933
401 20:11:23.380318 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 20:11:23.383979 ARM64: Exception handlers installed.
403 20:11:23.384409 ARM64: Testing exception
404 20:11:23.387168 ARM64: Done test exception
405 20:11:23.408652 pmic_efuse_setting: Set efuses in 11 msecs
406 20:11:23.412311 pmwrap_interface_init: Select PMIF_VLD_RDY
407 20:11:23.419205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 20:11:23.422100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 20:11:23.426005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 20:11:23.433568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 20:11:23.436270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 20:11:23.440317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 20:11:23.447734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 20:11:23.451440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 20:11:23.455300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 20:11:23.462630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 20:11:23.466169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 20:11:23.469755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 20:11:23.473728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 20:11:23.480952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 20:11:23.488027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 20:11:23.492195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 20:11:23.499270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 20:11:23.503006 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 20:11:23.510641 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 20:11:23.514829 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 20:11:23.521759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 20:11:23.525513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 20:11:23.532283 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 20:11:23.535791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 20:11:23.543034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 20:11:23.546973 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 20:11:23.553874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 20:11:23.557787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 20:11:23.561179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 20:11:23.568176 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 20:11:23.572208 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 20:11:23.579236 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 20:11:23.583216 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 20:11:23.586419 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 20:11:23.594717 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 20:11:23.597939 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 20:11:23.601266 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 20:11:23.608433 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 20:11:23.612575 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 20:11:23.615839 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 20:11:23.619569 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 20:11:23.626747 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 20:11:23.630585 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 20:11:23.634534 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 20:11:23.637970 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 20:11:23.641687 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 20:11:23.645295 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 20:11:23.652578 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 20:11:23.656403 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 20:11:23.660450 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 20:11:23.663804 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 20:11:23.670818 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 20:11:23.678089 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 20:11:23.685715 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 20:11:23.692958 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 20:11:23.700111 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 20:11:23.707059 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 20:11:23.710322 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 20:11:23.714272 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 20:11:23.722422 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1
467 20:11:23.725675 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 20:11:23.733715 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 20:11:23.736720 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 20:11:23.745874 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 20:11:23.755787 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 20:11:23.764692 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 20:11:23.774572 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 20:11:23.783632 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 20:11:23.793728 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 20:11:23.803429 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 20:11:23.806648 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 20:11:23.813458 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 20:11:23.817006 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 20:11:23.820195 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 20:11:23.824288 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 20:11:23.827610 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 20:11:23.831167 ADC[4]: Raw value=903400 ID=7
484 20:11:23.835301 ADC[3]: Raw value=213282 ID=1
485 20:11:23.835901 RAM Code: 0x71
486 20:11:23.838539 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 20:11:23.846140 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 20:11:23.853635 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 20:11:23.860499 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 20:11:23.863833 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 20:11:23.868018 in-header: 03 07 00 00 08 00 00 00
492 20:11:23.871244 in-data: aa e4 47 04 13 02 00 00
493 20:11:23.871775 Chrome EC: UHEPI supported
494 20:11:23.879003 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 20:11:23.882751 in-header: 03 ed 00 00 08 00 00 00
496 20:11:23.885964 in-data: 80 20 60 08 00 00 00 00
497 20:11:23.889630 MRC: failed to locate region type 0.
498 20:11:23.897412 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 20:11:23.900757 DRAM-K: Running full calibration
500 20:11:23.904580 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 20:11:23.908413 header.status = 0x0
502 20:11:23.911869 header.version = 0x6 (expected: 0x6)
503 20:11:23.915551 header.size = 0xd00 (expected: 0xd00)
504 20:11:23.916066 header.flags = 0x0
505 20:11:23.922948 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 20:11:23.940212 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 20:11:23.948045 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 20:11:23.951391 dram_init: ddr_geometry: 2
509 20:11:23.951893 [EMI] MDL number = 2
510 20:11:23.955171 [EMI] Get MDL freq = 0
511 20:11:23.955599 dram_init: ddr_type: 0
512 20:11:23.958198 is_discrete_lpddr4: 1
513 20:11:23.962051 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 20:11:23.962476
515 20:11:23.962812
516 20:11:23.965489 [Bian_co] ETT version 0.0.0.1
517 20:11:23.968716 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 20:11:23.969203
519 20:11:23.972505 dramc_set_vcore_voltage set vcore to 650000
520 20:11:23.975573 Read voltage for 800, 4
521 20:11:23.976196 Vio18 = 0
522 20:11:23.976544 Vcore = 650000
523 20:11:23.979835 Vdram = 0
524 20:11:23.980442 Vddq = 0
525 20:11:23.980794 Vmddr = 0
526 20:11:23.983259 dram_init: config_dvfs: 1
527 20:11:23.986485 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 20:11:23.993575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 20:11:23.998008 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 20:11:24.001206 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 20:11:24.004822 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 20:11:24.008343 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 20:11:24.008770 MEM_TYPE=3, freq_sel=18
534 20:11:24.012694 sv_algorithm_assistance_LP4_1600
535 20:11:24.016645 ============ PULL DRAM RESETB DOWN ============
536 20:11:24.019872 ========== PULL DRAM RESETB DOWN end =========
537 20:11:24.026597 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 20:11:24.029350 ===================================
539 20:11:24.033068 LPDDR4 DRAM CONFIGURATION
540 20:11:24.036721 ===================================
541 20:11:24.037150 EX_ROW_EN[0] = 0x0
542 20:11:24.039594 EX_ROW_EN[1] = 0x0
543 20:11:24.040068 LP4Y_EN = 0x0
544 20:11:24.042676 WORK_FSP = 0x0
545 20:11:24.043103 WL = 0x2
546 20:11:24.046309 RL = 0x2
547 20:11:24.046785 BL = 0x2
548 20:11:24.049297 RPST = 0x0
549 20:11:24.049725 RD_PRE = 0x0
550 20:11:24.053217 WR_PRE = 0x1
551 20:11:24.053643 WR_PST = 0x0
552 20:11:24.056163 DBI_WR = 0x0
553 20:11:24.056617 DBI_RD = 0x0
554 20:11:24.059198 OTF = 0x1
555 20:11:24.062481 ===================================
556 20:11:24.065760 ===================================
557 20:11:24.066193 ANA top config
558 20:11:24.069099 ===================================
559 20:11:24.072785 DLL_ASYNC_EN = 0
560 20:11:24.076144 ALL_SLAVE_EN = 1
561 20:11:24.079277 NEW_RANK_MODE = 1
562 20:11:24.079759 DLL_IDLE_MODE = 1
563 20:11:24.082879 LP45_APHY_COMB_EN = 1
564 20:11:24.086348 TX_ODT_DIS = 1
565 20:11:24.089868 NEW_8X_MODE = 1
566 20:11:24.092338 ===================================
567 20:11:24.095846 ===================================
568 20:11:24.099332 data_rate = 1600
569 20:11:24.099809 CKR = 1
570 20:11:24.102828 DQ_P2S_RATIO = 8
571 20:11:24.106049 ===================================
572 20:11:24.109459 CA_P2S_RATIO = 8
573 20:11:24.112353 DQ_CA_OPEN = 0
574 20:11:24.115710 DQ_SEMI_OPEN = 0
575 20:11:24.119078 CA_SEMI_OPEN = 0
576 20:11:24.119509 CA_FULL_RATE = 0
577 20:11:24.122752 DQ_CKDIV4_EN = 1
578 20:11:24.125685 CA_CKDIV4_EN = 1
579 20:11:24.129087 CA_PREDIV_EN = 0
580 20:11:24.132442 PH8_DLY = 0
581 20:11:24.136077 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 20:11:24.138746 DQ_AAMCK_DIV = 4
583 20:11:24.139182 CA_AAMCK_DIV = 4
584 20:11:24.142144 CA_ADMCK_DIV = 4
585 20:11:24.145929 DQ_TRACK_CA_EN = 0
586 20:11:24.148681 CA_PICK = 800
587 20:11:24.152203 CA_MCKIO = 800
588 20:11:24.155407 MCKIO_SEMI = 0
589 20:11:24.155871 PLL_FREQ = 3068
590 20:11:24.158763 DQ_UI_PI_RATIO = 32
591 20:11:24.162229 CA_UI_PI_RATIO = 0
592 20:11:24.166213 ===================================
593 20:11:24.169647 ===================================
594 20:11:24.173446 memory_type:LPDDR4
595 20:11:24.173876 GP_NUM : 10
596 20:11:24.176939 SRAM_EN : 1
597 20:11:24.177404 MD32_EN : 0
598 20:11:24.180380 ===================================
599 20:11:24.184167 [ANA_INIT] >>>>>>>>>>>>>>
600 20:11:24.188377 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 20:11:24.191367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 20:11:24.191912 ===================================
603 20:11:24.195163 data_rate = 1600,PCW = 0X7600
604 20:11:24.198490 ===================================
605 20:11:24.202224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 20:11:24.208518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 20:11:24.212296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 20:11:24.218590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 20:11:24.222165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 20:11:24.225408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 20:11:24.228297 [ANA_INIT] flow start
612 20:11:24.228727 [ANA_INIT] PLL >>>>>>>>
613 20:11:24.231656 [ANA_INIT] PLL <<<<<<<<
614 20:11:24.236030 [ANA_INIT] MIDPI >>>>>>>>
615 20:11:24.236462 [ANA_INIT] MIDPI <<<<<<<<
616 20:11:24.239096 [ANA_INIT] DLL >>>>>>>>
617 20:11:24.241964 [ANA_INIT] flow end
618 20:11:24.244924 ============ LP4 DIFF to SE enter ============
619 20:11:24.248386 ============ LP4 DIFF to SE exit ============
620 20:11:24.252323 [ANA_INIT] <<<<<<<<<<<<<
621 20:11:24.255374 [Flow] Enable top DCM control >>>>>
622 20:11:24.258281 [Flow] Enable top DCM control <<<<<
623 20:11:24.261735 Enable DLL master slave shuffle
624 20:11:24.265527 ==============================================================
625 20:11:24.268150 Gating Mode config
626 20:11:24.275205 ==============================================================
627 20:11:24.275789 Config description:
628 20:11:24.284688 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 20:11:24.291970 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 20:11:24.295449 SELPH_MODE 0: By rank 1: By Phase
631 20:11:24.301667 ==============================================================
632 20:11:24.305401 GAT_TRACK_EN = 1
633 20:11:24.308374 RX_GATING_MODE = 2
634 20:11:24.311374 RX_GATING_TRACK_MODE = 2
635 20:11:24.314971 SELPH_MODE = 1
636 20:11:24.318609 PICG_EARLY_EN = 1
637 20:11:24.321311 VALID_LAT_VALUE = 1
638 20:11:24.325201 ==============================================================
639 20:11:24.328563 Enter into Gating configuration >>>>
640 20:11:24.331879 Exit from Gating configuration <<<<
641 20:11:24.334744 Enter into DVFS_PRE_config >>>>>
642 20:11:24.348004 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 20:11:24.348596 Exit from DVFS_PRE_config <<<<<
644 20:11:24.351908 Enter into PICG configuration >>>>
645 20:11:24.354940 Exit from PICG configuration <<<<
646 20:11:24.357903 [RX_INPUT] configuration >>>>>
647 20:11:24.360992 [RX_INPUT] configuration <<<<<
648 20:11:24.368295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 20:11:24.371195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 20:11:24.378532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 20:11:24.385149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 20:11:24.391510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 20:11:24.398531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 20:11:24.402030 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 20:11:24.404840 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 20:11:24.408143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 20:11:24.414947 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 20:11:24.417999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 20:11:24.420946 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 20:11:24.424267 ===================================
661 20:11:24.427788 LPDDR4 DRAM CONFIGURATION
662 20:11:24.431366 ===================================
663 20:11:24.432161 EX_ROW_EN[0] = 0x0
664 20:11:24.434603 EX_ROW_EN[1] = 0x0
665 20:11:24.437707 LP4Y_EN = 0x0
666 20:11:24.438130 WORK_FSP = 0x0
667 20:11:24.440862 WL = 0x2
668 20:11:24.441342 RL = 0x2
669 20:11:24.444701 BL = 0x2
670 20:11:24.445150 RPST = 0x0
671 20:11:24.447787 RD_PRE = 0x0
672 20:11:24.448248 WR_PRE = 0x1
673 20:11:24.451276 WR_PST = 0x0
674 20:11:24.451738 DBI_WR = 0x0
675 20:11:24.454434 DBI_RD = 0x0
676 20:11:24.455000 OTF = 0x1
677 20:11:24.457699 ===================================
678 20:11:24.460658 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 20:11:24.467167 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 20:11:24.470726 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 20:11:24.474628 ===================================
682 20:11:24.477030 LPDDR4 DRAM CONFIGURATION
683 20:11:24.480295 ===================================
684 20:11:24.480723 EX_ROW_EN[0] = 0x10
685 20:11:24.483749 EX_ROW_EN[1] = 0x0
686 20:11:24.486973 LP4Y_EN = 0x0
687 20:11:24.487426 WORK_FSP = 0x0
688 20:11:24.490815 WL = 0x2
689 20:11:24.491314 RL = 0x2
690 20:11:24.493733 BL = 0x2
691 20:11:24.494230 RPST = 0x0
692 20:11:24.497063 RD_PRE = 0x0
693 20:11:24.497487 WR_PRE = 0x1
694 20:11:24.500193 WR_PST = 0x0
695 20:11:24.500616 DBI_WR = 0x0
696 20:11:24.503665 DBI_RD = 0x0
697 20:11:24.504131 OTF = 0x1
698 20:11:24.507337 ===================================
699 20:11:24.513544 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 20:11:24.518085 nWR fixed to 40
701 20:11:24.521309 [ModeRegInit_LP4] CH0 RK0
702 20:11:24.521880 [ModeRegInit_LP4] CH0 RK1
703 20:11:24.524722 [ModeRegInit_LP4] CH1 RK0
704 20:11:24.527901 [ModeRegInit_LP4] CH1 RK1
705 20:11:24.528415 match AC timing 13
706 20:11:24.534229 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 20:11:24.537550 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 20:11:24.540668 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 20:11:24.547427 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 20:11:24.550509 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 20:11:24.554485 [EMI DOE] emi_dcm 0
712 20:11:24.557531 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 20:11:24.557971 ==
714 20:11:24.560412 Dram Type= 6, Freq= 0, CH_0, rank 0
715 20:11:24.564139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 20:11:24.564568 ==
717 20:11:24.570740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 20:11:24.577094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 20:11:24.585275 [CA 0] Center 37 (7~68) winsize 62
720 20:11:24.588779 [CA 1] Center 37 (6~68) winsize 63
721 20:11:24.591965 [CA 2] Center 34 (4~65) winsize 62
722 20:11:24.595499 [CA 3] Center 35 (5~65) winsize 61
723 20:11:24.598836 [CA 4] Center 33 (3~64) winsize 62
724 20:11:24.601895 [CA 5] Center 33 (3~64) winsize 62
725 20:11:24.602407
726 20:11:24.604924 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 20:11:24.605347
728 20:11:24.608198 [CATrainingPosCal] consider 1 rank data
729 20:11:24.611994 u2DelayCellTimex100 = 270/100 ps
730 20:11:24.615529 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 20:11:24.621825 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 20:11:24.625333 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 20:11:24.628686 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
734 20:11:24.631639 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 20:11:24.634907 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 20:11:24.635366
737 20:11:24.638069 CA PerBit enable=1, Macro0, CA PI delay=33
738 20:11:24.638510
739 20:11:24.641555 [CBTSetCACLKResult] CA Dly = 33
740 20:11:24.644694 CS Dly: 7 (0~38)
741 20:11:24.645330 ==
742 20:11:24.647976 Dram Type= 6, Freq= 0, CH_0, rank 1
743 20:11:24.651748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 20:11:24.652178 ==
745 20:11:24.658002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 20:11:24.661145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 20:11:24.672264 [CA 0] Center 37 (6~68) winsize 63
748 20:11:24.674992 [CA 1] Center 37 (7~67) winsize 61
749 20:11:24.677923 [CA 2] Center 34 (4~65) winsize 62
750 20:11:24.681613 [CA 3] Center 34 (4~65) winsize 62
751 20:11:24.685190 [CA 4] Center 33 (3~64) winsize 62
752 20:11:24.688013 [CA 5] Center 33 (2~64) winsize 63
753 20:11:24.688468
754 20:11:24.691515 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 20:11:24.692029
756 20:11:24.694746 [CATrainingPosCal] consider 2 rank data
757 20:11:24.697881 u2DelayCellTimex100 = 270/100 ps
758 20:11:24.701369 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 20:11:24.708189 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 20:11:24.711321 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 20:11:24.714525 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 20:11:24.717971 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 20:11:24.721483 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 20:11:24.721975
765 20:11:24.724662 CA PerBit enable=1, Macro0, CA PI delay=33
766 20:11:24.725091
767 20:11:24.727761 [CBTSetCACLKResult] CA Dly = 33
768 20:11:24.728192 CS Dly: 7 (0~38)
769 20:11:24.731477
770 20:11:24.734508 ----->DramcWriteLeveling(PI) begin...
771 20:11:24.735043 ==
772 20:11:24.737942 Dram Type= 6, Freq= 0, CH_0, rank 0
773 20:11:24.741578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 20:11:24.742006 ==
775 20:11:24.744909 Write leveling (Byte 0): 33 => 33
776 20:11:24.748631 Write leveling (Byte 1): 29 => 29
777 20:11:24.749087 DramcWriteLeveling(PI) end<-----
778 20:11:24.749618
779 20:11:24.751787 ==
780 20:11:24.755450 Dram Type= 6, Freq= 0, CH_0, rank 0
781 20:11:24.759467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 20:11:24.760009 ==
783 20:11:24.762397 [Gating] SW mode calibration
784 20:11:24.769374 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 20:11:24.772687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 20:11:24.776192 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 20:11:24.782817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 20:11:24.786520 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 20:11:24.789995 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 20:11:24.796037 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 20:11:24.799391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 20:11:24.802958 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 20:11:24.809355 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 20:11:24.813156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 20:11:24.815951 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 20:11:24.822930 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 20:11:24.826153 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 20:11:24.829078 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 20:11:24.836319 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 20:11:24.839531 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 20:11:24.842744 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 20:11:24.849302 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 20:11:24.852157 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 20:11:24.855514 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 20:11:24.862513 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 20:11:24.865795 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 20:11:24.868973 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 20:11:24.875754 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 20:11:24.878959 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 20:11:24.882257 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 20:11:24.889391 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 20:11:24.892377 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
813 20:11:24.895563 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
814 20:11:24.899090 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 20:11:24.906017 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 20:11:24.908671 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 20:11:24.912478 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 20:11:24.919364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 20:11:24.922433 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 20:11:24.925852 0 10 8 | B1->B0 | 3434 2929 | 0 0 | (1 0) (0 0)
821 20:11:24.932666 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
822 20:11:24.935261 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 20:11:24.938789 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 20:11:24.945552 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 20:11:24.949704 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 20:11:24.952284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 20:11:24.958555 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 20:11:24.962516 0 11 8 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
829 20:11:24.965038 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
830 20:11:24.971790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 20:11:24.975482 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 20:11:24.978284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 20:11:24.985799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 20:11:24.988707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 20:11:24.991983 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 20:11:24.998630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 20:11:25.001613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 20:11:25.005005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 20:11:25.011376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 20:11:25.015018 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 20:11:25.018521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 20:11:25.025116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 20:11:25.028342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 20:11:25.032127 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 20:11:25.038296 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 20:11:25.041246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 20:11:25.044859 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 20:11:25.051218 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 20:11:25.054659 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 20:11:25.058129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 20:11:25.061317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 20:11:25.068486 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 20:11:25.071302 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 20:11:25.079090 Total UI for P1: 0, mck2ui 16
855 20:11:25.079526 best dqsien dly found for B0: ( 0, 14, 8)
856 20:11:25.081407 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 20:11:25.084947 Total UI for P1: 0, mck2ui 16
858 20:11:25.088492 best dqsien dly found for B1: ( 0, 14, 10)
859 20:11:25.091212 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 20:11:25.098027 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 20:11:25.098452
862 20:11:25.101630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 20:11:25.104447 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 20:11:25.107958 [Gating] SW calibration Done
865 20:11:25.108442 ==
866 20:11:25.111517 Dram Type= 6, Freq= 0, CH_0, rank 0
867 20:11:25.114978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 20:11:25.115427 ==
869 20:11:25.115809 RX Vref Scan: 0
870 20:11:25.117584
871 20:11:25.118038 RX Vref 0 -> 0, step: 1
872 20:11:25.118385
873 20:11:25.120863 RX Delay -130 -> 252, step: 16
874 20:11:25.124461 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 20:11:25.130847 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 20:11:25.134624 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 20:11:25.137458 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 20:11:25.140912 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 20:11:25.144416 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 20:11:25.150607 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 20:11:25.154014 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 20:11:25.157150 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 20:11:25.160451 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 20:11:25.163815 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 20:11:25.170417 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 20:11:25.173941 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
887 20:11:25.177037 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 20:11:25.180122 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 20:11:25.186722 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 20:11:25.187252 ==
891 20:11:25.190098 Dram Type= 6, Freq= 0, CH_0, rank 0
892 20:11:25.193484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 20:11:25.193935 ==
894 20:11:25.194272 DQS Delay:
895 20:11:25.196701 DQS0 = 0, DQS1 = 0
896 20:11:25.197121 DQM Delay:
897 20:11:25.200631 DQM0 = 86, DQM1 = 75
898 20:11:25.201048 DQ Delay:
899 20:11:25.203416 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 20:11:25.206661 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
901 20:11:25.210263 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
902 20:11:25.213417 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
903 20:11:25.213842
904 20:11:25.214178
905 20:11:25.214490 ==
906 20:11:25.216915 Dram Type= 6, Freq= 0, CH_0, rank 0
907 20:11:25.220416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 20:11:25.220869 ==
909 20:11:25.221205
910 20:11:25.221511
911 20:11:25.223208 TX Vref Scan disable
912 20:11:25.226743 == TX Byte 0 ==
913 20:11:25.230298 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 20:11:25.233360 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 20:11:25.236783 == TX Byte 1 ==
916 20:11:25.239764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 20:11:25.243234 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 20:11:25.243794 ==
919 20:11:25.246658 Dram Type= 6, Freq= 0, CH_0, rank 0
920 20:11:25.253232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 20:11:25.253655 ==
922 20:11:25.265491 TX Vref=22, minBit 1, minWin=27, winSum=441
923 20:11:25.268922 TX Vref=24, minBit 8, minWin=27, winSum=444
924 20:11:25.272254 TX Vref=26, minBit 8, minWin=27, winSum=447
925 20:11:25.275178 TX Vref=28, minBit 8, minWin=27, winSum=445
926 20:11:25.278659 TX Vref=30, minBit 10, minWin=27, winSum=450
927 20:11:25.285542 TX Vref=32, minBit 8, minWin=27, winSum=446
928 20:11:25.288695 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 30
929 20:11:25.289120
930 20:11:25.291605 Final TX Range 1 Vref 30
931 20:11:25.292081
932 20:11:25.292520 ==
933 20:11:25.295235 Dram Type= 6, Freq= 0, CH_0, rank 0
934 20:11:25.298339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 20:11:25.301752 ==
936 20:11:25.302205
937 20:11:25.302662
938 20:11:25.303095 TX Vref Scan disable
939 20:11:25.305552 == TX Byte 0 ==
940 20:11:25.308769 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 20:11:25.315373 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 20:11:25.315841 == TX Byte 1 ==
943 20:11:25.318906 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 20:11:25.325200 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 20:11:25.325636
946 20:11:25.325980 [DATLAT]
947 20:11:25.326299 Freq=800, CH0 RK0
948 20:11:25.326677
949 20:11:25.328910 DATLAT Default: 0xa
950 20:11:25.329337 0, 0xFFFF, sum = 0
951 20:11:25.331944 1, 0xFFFF, sum = 0
952 20:11:25.334827 2, 0xFFFF, sum = 0
953 20:11:25.335259 3, 0xFFFF, sum = 0
954 20:11:25.338339 4, 0xFFFF, sum = 0
955 20:11:25.338774 5, 0xFFFF, sum = 0
956 20:11:25.341642 6, 0xFFFF, sum = 0
957 20:11:25.342079 7, 0xFFFF, sum = 0
958 20:11:25.345234 8, 0xFFFF, sum = 0
959 20:11:25.345671 9, 0x0, sum = 1
960 20:11:25.348529 10, 0x0, sum = 2
961 20:11:25.348963 11, 0x0, sum = 3
962 20:11:25.349467 12, 0x0, sum = 4
963 20:11:25.352042 best_step = 10
964 20:11:25.352512
965 20:11:25.352875 ==
966 20:11:25.355105 Dram Type= 6, Freq= 0, CH_0, rank 0
967 20:11:25.358621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 20:11:25.359123 ==
969 20:11:25.362341 RX Vref Scan: 1
970 20:11:25.362766
971 20:11:25.364855 Set Vref Range= 32 -> 127
972 20:11:25.365301
973 20:11:25.365647 RX Vref 32 -> 127, step: 1
974 20:11:25.365969
975 20:11:25.368761 RX Delay -95 -> 252, step: 8
976 20:11:25.369191
977 20:11:25.371754 Set Vref, RX VrefLevel [Byte0]: 32
978 20:11:25.375502 [Byte1]: 32
979 20:11:25.378387
980 20:11:25.378819 Set Vref, RX VrefLevel [Byte0]: 33
981 20:11:25.382103 [Byte1]: 33
982 20:11:25.385947
983 20:11:25.386356 Set Vref, RX VrefLevel [Byte0]: 34
984 20:11:25.388756 [Byte1]: 34
985 20:11:25.393309
986 20:11:25.393614 Set Vref, RX VrefLevel [Byte0]: 35
987 20:11:25.397039 [Byte1]: 35
988 20:11:25.401229
989 20:11:25.401540 Set Vref, RX VrefLevel [Byte0]: 36
990 20:11:25.403908 [Byte1]: 36
991 20:11:25.408862
992 20:11:25.409176 Set Vref, RX VrefLevel [Byte0]: 37
993 20:11:25.412341 [Byte1]: 37
994 20:11:25.416375
995 20:11:25.416692 Set Vref, RX VrefLevel [Byte0]: 38
996 20:11:25.419533 [Byte1]: 38
997 20:11:25.424044
998 20:11:25.424361 Set Vref, RX VrefLevel [Byte0]: 39
999 20:11:25.427316 [Byte1]: 39
1000 20:11:25.431482
1001 20:11:25.431825 Set Vref, RX VrefLevel [Byte0]: 40
1002 20:11:25.435479 [Byte1]: 40
1003 20:11:25.439352
1004 20:11:25.439667 Set Vref, RX VrefLevel [Byte0]: 41
1005 20:11:25.442943 [Byte1]: 41
1006 20:11:25.446517
1007 20:11:25.446833 Set Vref, RX VrefLevel [Byte0]: 42
1008 20:11:25.449630 [Byte1]: 42
1009 20:11:25.454305
1010 20:11:25.454713 Set Vref, RX VrefLevel [Byte0]: 43
1011 20:11:25.457218 [Byte1]: 43
1012 20:11:25.461749
1013 20:11:25.462065 Set Vref, RX VrefLevel [Byte0]: 44
1014 20:11:25.464983 [Byte1]: 44
1015 20:11:25.469196
1016 20:11:25.469514 Set Vref, RX VrefLevel [Byte0]: 45
1017 20:11:25.472459 [Byte1]: 45
1018 20:11:25.476599
1019 20:11:25.476995 Set Vref, RX VrefLevel [Byte0]: 46
1020 20:11:25.479711 [Byte1]: 46
1021 20:11:25.484164
1022 20:11:25.484478 Set Vref, RX VrefLevel [Byte0]: 47
1023 20:11:25.487988 [Byte1]: 47
1024 20:11:25.492469
1025 20:11:25.492779 Set Vref, RX VrefLevel [Byte0]: 48
1026 20:11:25.495251 [Byte1]: 48
1027 20:11:25.498993
1028 20:11:25.499075 Set Vref, RX VrefLevel [Byte0]: 49
1029 20:11:25.502622 [Byte1]: 49
1030 20:11:25.506706
1031 20:11:25.506788 Set Vref, RX VrefLevel [Byte0]: 50
1032 20:11:25.509942 [Byte1]: 50
1033 20:11:25.514830
1034 20:11:25.514915 Set Vref, RX VrefLevel [Byte0]: 51
1035 20:11:25.517488 [Byte1]: 51
1036 20:11:25.521897
1037 20:11:25.521979 Set Vref, RX VrefLevel [Byte0]: 52
1038 20:11:25.525508 [Byte1]: 52
1039 20:11:25.529542
1040 20:11:25.529622 Set Vref, RX VrefLevel [Byte0]: 53
1041 20:11:25.533179 [Byte1]: 53
1042 20:11:25.537591
1043 20:11:25.537676 Set Vref, RX VrefLevel [Byte0]: 54
1044 20:11:25.540751 [Byte1]: 54
1045 20:11:25.544581
1046 20:11:25.544661 Set Vref, RX VrefLevel [Byte0]: 55
1047 20:11:25.548188 [Byte1]: 55
1048 20:11:25.552375
1049 20:11:25.552455 Set Vref, RX VrefLevel [Byte0]: 56
1050 20:11:25.555982 [Byte1]: 56
1051 20:11:25.560568
1052 20:11:25.560650 Set Vref, RX VrefLevel [Byte0]: 57
1053 20:11:25.563184 [Byte1]: 57
1054 20:11:25.567966
1055 20:11:25.568046 Set Vref, RX VrefLevel [Byte0]: 58
1056 20:11:25.570685 [Byte1]: 58
1057 20:11:25.575365
1058 20:11:25.575482 Set Vref, RX VrefLevel [Byte0]: 59
1059 20:11:25.578666 [Byte1]: 59
1060 20:11:25.583221
1061 20:11:25.583302 Set Vref, RX VrefLevel [Byte0]: 60
1062 20:11:25.585885 [Byte1]: 60
1063 20:11:25.590882
1064 20:11:25.593359 Set Vref, RX VrefLevel [Byte0]: 61
1065 20:11:25.596824 [Byte1]: 61
1066 20:11:25.596909
1067 20:11:25.600213 Set Vref, RX VrefLevel [Byte0]: 62
1068 20:11:25.603465 [Byte1]: 62
1069 20:11:25.603574
1070 20:11:25.607075 Set Vref, RX VrefLevel [Byte0]: 63
1071 20:11:25.610947 [Byte1]: 63
1072 20:11:25.611029
1073 20:11:25.613500 Set Vref, RX VrefLevel [Byte0]: 64
1074 20:11:25.616712 [Byte1]: 64
1075 20:11:25.621110
1076 20:11:25.621190 Set Vref, RX VrefLevel [Byte0]: 65
1077 20:11:25.624049 [Byte1]: 65
1078 20:11:25.628514
1079 20:11:25.628599 Set Vref, RX VrefLevel [Byte0]: 66
1080 20:11:25.632045 [Byte1]: 66
1081 20:11:25.635909
1082 20:11:25.635993 Set Vref, RX VrefLevel [Byte0]: 67
1083 20:11:25.639073 [Byte1]: 67
1084 20:11:25.644256
1085 20:11:25.644336 Set Vref, RX VrefLevel [Byte0]: 68
1086 20:11:25.646817 [Byte1]: 68
1087 20:11:25.651144
1088 20:11:25.651224 Set Vref, RX VrefLevel [Byte0]: 69
1089 20:11:25.654617 [Byte1]: 69
1090 20:11:25.658827
1091 20:11:25.658922 Set Vref, RX VrefLevel [Byte0]: 70
1092 20:11:25.662437 [Byte1]: 70
1093 20:11:25.666259
1094 20:11:25.666340 Set Vref, RX VrefLevel [Byte0]: 71
1095 20:11:25.669899 [Byte1]: 71
1096 20:11:25.674371
1097 20:11:25.674508 Set Vref, RX VrefLevel [Byte0]: 72
1098 20:11:25.677057 [Byte1]: 72
1099 20:11:25.681718
1100 20:11:25.681800 Set Vref, RX VrefLevel [Byte0]: 73
1101 20:11:25.685110 [Byte1]: 73
1102 20:11:25.689241
1103 20:11:25.692506 Set Vref, RX VrefLevel [Byte0]: 74
1104 20:11:25.695538 [Byte1]: 74
1105 20:11:25.695622
1106 20:11:25.699071 Set Vref, RX VrefLevel [Byte0]: 75
1107 20:11:25.702231 [Byte1]: 75
1108 20:11:25.702316
1109 20:11:25.705440 Set Vref, RX VrefLevel [Byte0]: 76
1110 20:11:25.708870 [Byte1]: 76
1111 20:11:25.708979
1112 20:11:25.712135 Set Vref, RX VrefLevel [Byte0]: 77
1113 20:11:25.715885 [Byte1]: 77
1114 20:11:25.719537
1115 20:11:25.719677 Set Vref, RX VrefLevel [Byte0]: 78
1116 20:11:25.723010 [Byte1]: 78
1117 20:11:25.727668
1118 20:11:25.727798 Set Vref, RX VrefLevel [Byte0]: 79
1119 20:11:25.730544 [Byte1]: 79
1120 20:11:25.734809
1121 20:11:25.734894 Set Vref, RX VrefLevel [Byte0]: 80
1122 20:11:25.738005 [Byte1]: 80
1123 20:11:25.742853
1124 20:11:25.742938 Set Vref, RX VrefLevel [Byte0]: 81
1125 20:11:25.745874 [Byte1]: 81
1126 20:11:25.749708
1127 20:11:25.749794 Final RX Vref Byte 0 = 58 to rank0
1128 20:11:25.752989 Final RX Vref Byte 1 = 53 to rank0
1129 20:11:25.756614 Final RX Vref Byte 0 = 58 to rank1
1130 20:11:25.759549 Final RX Vref Byte 1 = 53 to rank1==
1131 20:11:25.763186 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 20:11:25.770029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 20:11:25.770115 ==
1134 20:11:25.770203 DQS Delay:
1135 20:11:25.772997 DQS0 = 0, DQS1 = 0
1136 20:11:25.773082 DQM Delay:
1137 20:11:25.773168 DQM0 = 86, DQM1 = 76
1138 20:11:25.776554 DQ Delay:
1139 20:11:25.779706 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1140 20:11:25.783419 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1141 20:11:25.785982 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1142 20:11:25.789266 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1143 20:11:25.789347
1144 20:11:25.789411
1145 20:11:25.796345 [DQSOSCAuto] RK0, (LSB)MR18= 0x4426, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1146 20:11:25.799865 CH0 RK0: MR19=606, MR18=4426
1147 20:11:25.847029 CH0_RK0: MR19=0x606, MR18=0x4426, DQSOSC=392, MR23=63, INC=96, DEC=64
1148 20:11:25.847114
1149 20:11:25.847179 ----->DramcWriteLeveling(PI) begin...
1150 20:11:25.847241 ==
1151 20:11:25.847485 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 20:11:25.847931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 20:11:25.848014 ==
1154 20:11:25.848079 Write leveling (Byte 0): 34 => 34
1155 20:11:25.848325 Write leveling (Byte 1): 30 => 30
1156 20:11:25.848389 DramcWriteLeveling(PI) end<-----
1157 20:11:25.848450
1158 20:11:25.848506 ==
1159 20:11:25.848756 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 20:11:25.849003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 20:11:25.849067 ==
1162 20:11:25.849125 [Gating] SW mode calibration
1163 20:11:25.849372 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 20:11:25.861921 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 20:11:25.862005 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 20:11:25.862814 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1167 20:11:25.865444 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 20:11:25.868082 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 20:11:25.871895 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 20:11:25.875261 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 20:11:25.878618 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 20:11:25.885032 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 20:11:25.888422 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 20:11:25.891386 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 20:11:25.898223 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 20:11:25.901120 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 20:11:25.904588 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 20:11:25.911529 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 20:11:25.914532 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 20:11:25.917807 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 20:11:25.924804 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 20:11:25.928075 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1183 20:11:25.931184 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1184 20:11:25.937900 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 20:11:25.941460 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 20:11:25.944551 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 20:11:25.951121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 20:11:25.954488 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 20:11:25.957686 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 20:11:25.965470 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 20:11:25.968098 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1192 20:11:25.971092 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1193 20:11:25.977748 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 20:11:25.981087 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 20:11:25.984570 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 20:11:25.991666 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 20:11:25.994663 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 20:11:25.998518 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 20:11:26.001882 0 10 8 | B1->B0 | 2f2f 2626 | 1 1 | (1 1) (1 0)
1200 20:11:26.005804 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1201 20:11:26.012202 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 20:11:26.016015 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 20:11:26.019261 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 20:11:26.023317 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 20:11:26.029996 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 20:11:26.032785 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1207 20:11:26.036673 0 11 8 | B1->B0 | 2d2d 3838 | 0 1 | (0 0) (0 0)
1208 20:11:26.043226 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1209 20:11:26.045954 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 20:11:26.049745 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 20:11:26.056755 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 20:11:26.059200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 20:11:26.062778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 20:11:26.069437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1215 20:11:26.072984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 20:11:26.076381 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1217 20:11:26.082594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 20:11:26.085866 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 20:11:26.089197 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 20:11:26.095731 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 20:11:26.099370 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 20:11:26.102264 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 20:11:26.109344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 20:11:26.112041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 20:11:26.115696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 20:11:26.121928 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 20:11:26.125288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 20:11:26.129182 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 20:11:26.135491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 20:11:26.138637 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 20:11:26.142009 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1232 20:11:26.148758 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1233 20:11:26.151834 Total UI for P1: 0, mck2ui 16
1234 20:11:26.155627 best dqsien dly found for B0: ( 0, 14, 8)
1235 20:11:26.158636 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 20:11:26.162039 Total UI for P1: 0, mck2ui 16
1237 20:11:26.165128 best dqsien dly found for B1: ( 0, 14, 10)
1238 20:11:26.168763 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1239 20:11:26.171743 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1240 20:11:26.171826
1241 20:11:26.175716 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1242 20:11:26.178314 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1243 20:11:26.181866 [Gating] SW calibration Done
1244 20:11:26.181974 ==
1245 20:11:26.184953 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 20:11:26.191370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1247 20:11:26.191496 ==
1248 20:11:26.191620 RX Vref Scan: 0
1249 20:11:26.191726
1250 20:11:26.194804 RX Vref 0 -> 0, step: 1
1251 20:11:26.194912
1252 20:11:26.198259 RX Delay -130 -> 252, step: 16
1253 20:11:26.201857 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1254 20:11:26.204984 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1255 20:11:26.207876 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1256 20:11:26.214302 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1257 20:11:26.218189 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1258 20:11:26.220986 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1259 20:11:26.224968 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1260 20:11:26.227781 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1261 20:11:26.234320 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1262 20:11:26.237701 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1263 20:11:26.241117 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1264 20:11:26.244695 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1265 20:11:26.248080 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1266 20:11:26.254659 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1267 20:11:26.257923 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1268 20:11:26.261305 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1269 20:11:26.261408 ==
1270 20:11:26.264542 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 20:11:26.268274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 20:11:26.268383 ==
1273 20:11:26.271270 DQS Delay:
1274 20:11:26.271355 DQS0 = 0, DQS1 = 0
1275 20:11:26.274849 DQM Delay:
1276 20:11:26.274922 DQM0 = 87, DQM1 = 76
1277 20:11:26.274985 DQ Delay:
1278 20:11:26.277869 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1279 20:11:26.281044 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1280 20:11:26.284527 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1281 20:11:26.287809 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1282 20:11:26.287892
1283 20:11:26.290989
1284 20:11:26.291070 ==
1285 20:11:26.294323 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 20:11:26.297917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 20:11:26.297999 ==
1288 20:11:26.298070
1289 20:11:26.298133
1290 20:11:26.300960 TX Vref Scan disable
1291 20:11:26.301042 == TX Byte 0 ==
1292 20:11:26.307392 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1293 20:11:26.310750 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1294 20:11:26.310832 == TX Byte 1 ==
1295 20:11:26.317528 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1296 20:11:26.321109 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1297 20:11:26.321190 ==
1298 20:11:26.323987 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 20:11:26.327652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 20:11:26.327745 ==
1301 20:11:26.341929 TX Vref=22, minBit 0, minWin=27, winSum=441
1302 20:11:26.345162 TX Vref=24, minBit 4, minWin=27, winSum=442
1303 20:11:26.348202 TX Vref=26, minBit 4, minWin=27, winSum=445
1304 20:11:26.351635 TX Vref=28, minBit 9, minWin=27, winSum=448
1305 20:11:26.354563 TX Vref=30, minBit 12, minWin=27, winSum=446
1306 20:11:26.361328 TX Vref=32, minBit 8, minWin=27, winSum=446
1307 20:11:26.364229 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 28
1308 20:11:26.364340
1309 20:11:26.367992 Final TX Range 1 Vref 28
1310 20:11:26.368072
1311 20:11:26.368136 ==
1312 20:11:26.370930 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 20:11:26.374527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 20:11:26.378262 ==
1315 20:11:26.378347
1316 20:11:26.378411
1317 20:11:26.378470 TX Vref Scan disable
1318 20:11:26.381782 == TX Byte 0 ==
1319 20:11:26.384694 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1320 20:11:26.391431 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1321 20:11:26.391512 == TX Byte 1 ==
1322 20:11:26.394866 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1323 20:11:26.401783 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1324 20:11:26.401864
1325 20:11:26.401928 [DATLAT]
1326 20:11:26.401987 Freq=800, CH0 RK1
1327 20:11:26.402044
1328 20:11:26.404497 DATLAT Default: 0xa
1329 20:11:26.404577 0, 0xFFFF, sum = 0
1330 20:11:26.408098 1, 0xFFFF, sum = 0
1331 20:11:26.411164 2, 0xFFFF, sum = 0
1332 20:11:26.411245 3, 0xFFFF, sum = 0
1333 20:11:26.414608 4, 0xFFFF, sum = 0
1334 20:11:26.414691 5, 0xFFFF, sum = 0
1335 20:11:26.418308 6, 0xFFFF, sum = 0
1336 20:11:26.418389 7, 0xFFFF, sum = 0
1337 20:11:26.421089 8, 0xFFFF, sum = 0
1338 20:11:26.421171 9, 0x0, sum = 1
1339 20:11:26.424191 10, 0x0, sum = 2
1340 20:11:26.424273 11, 0x0, sum = 3
1341 20:11:26.424338 12, 0x0, sum = 4
1342 20:11:26.427779 best_step = 10
1343 20:11:26.427859
1344 20:11:26.427923 ==
1345 20:11:26.431218 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 20:11:26.435243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 20:11:26.435325 ==
1348 20:11:26.437598 RX Vref Scan: 0
1349 20:11:26.437678
1350 20:11:26.441245 RX Vref 0 -> 0, step: 1
1351 20:11:26.441326
1352 20:11:26.441389 RX Delay -111 -> 252, step: 8
1353 20:11:26.448149 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1354 20:11:26.451541 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1355 20:11:26.454991 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1356 20:11:26.458379 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1357 20:11:26.464497 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1358 20:11:26.467790 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1359 20:11:26.471120 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1360 20:11:26.474616 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1361 20:11:26.477998 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1362 20:11:26.481323 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1363 20:11:26.487579 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1364 20:11:26.491317 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1365 20:11:26.494589 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1366 20:11:26.497919 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1367 20:11:26.504531 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1368 20:11:26.507884 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1369 20:11:26.507965 ==
1370 20:11:26.511018 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 20:11:26.514593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 20:11:26.514686 ==
1373 20:11:26.517325 DQS Delay:
1374 20:11:26.517403 DQS0 = 0, DQS1 = 0
1375 20:11:26.517467 DQM Delay:
1376 20:11:26.520931 DQM0 = 85, DQM1 = 77
1377 20:11:26.521010 DQ Delay:
1378 20:11:26.524081 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1379 20:11:26.527592 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1380 20:11:26.530313 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1381 20:11:26.534311 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1382 20:11:26.534390
1383 20:11:26.534452
1384 20:11:26.543689 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
1385 20:11:26.547231 CH0 RK1: MR19=606, MR18=3A02
1386 20:11:26.550827 CH0_RK1: MR19=0x606, MR18=0x3A02, DQSOSC=395, MR23=63, INC=94, DEC=63
1387 20:11:26.553968 [RxdqsGatingPostProcess] freq 800
1388 20:11:26.560305 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1389 20:11:26.564148 Pre-setting of DQS Precalculation
1390 20:11:26.566726 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1391 20:11:26.570265 ==
1392 20:11:26.573824 Dram Type= 6, Freq= 0, CH_1, rank 0
1393 20:11:26.576823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 20:11:26.576902 ==
1395 20:11:26.580321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 20:11:26.586371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 20:11:26.596715 [CA 0] Center 36 (6~67) winsize 62
1398 20:11:26.600004 [CA 1] Center 36 (6~67) winsize 62
1399 20:11:26.603363 [CA 2] Center 34 (4~65) winsize 62
1400 20:11:26.606358 [CA 3] Center 34 (4~65) winsize 62
1401 20:11:26.610016 [CA 4] Center 34 (4~65) winsize 62
1402 20:11:26.613107 [CA 5] Center 34 (3~65) winsize 63
1403 20:11:26.613189
1404 20:11:26.616841 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 20:11:26.616923
1406 20:11:26.619422 [CATrainingPosCal] consider 1 rank data
1407 20:11:26.622553 u2DelayCellTimex100 = 270/100 ps
1408 20:11:26.626533 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 20:11:26.632866 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1410 20:11:26.635995 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 20:11:26.639236 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 20:11:26.642539 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 20:11:26.646369 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1414 20:11:26.646451
1415 20:11:26.649556 CA PerBit enable=1, Macro0, CA PI delay=34
1416 20:11:26.649637
1417 20:11:26.652630 [CBTSetCACLKResult] CA Dly = 34
1418 20:11:26.652711 CS Dly: 5 (0~36)
1419 20:11:26.656172 ==
1420 20:11:26.659871 Dram Type= 6, Freq= 0, CH_1, rank 1
1421 20:11:26.663316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 20:11:26.663398 ==
1423 20:11:26.666909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1424 20:11:26.674263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1425 20:11:26.682373 [CA 0] Center 36 (6~67) winsize 62
1426 20:11:26.686087 [CA 1] Center 37 (6~68) winsize 63
1427 20:11:26.689821 [CA 2] Center 34 (4~65) winsize 62
1428 20:11:26.693131 [CA 3] Center 34 (4~65) winsize 62
1429 20:11:26.696489 [CA 4] Center 34 (4~65) winsize 62
1430 20:11:26.699792 [CA 5] Center 34 (4~64) winsize 61
1431 20:11:26.699874
1432 20:11:26.702960 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1433 20:11:26.703041
1434 20:11:26.706023 [CATrainingPosCal] consider 2 rank data
1435 20:11:26.709607 u2DelayCellTimex100 = 270/100 ps
1436 20:11:26.712889 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 20:11:26.716033 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1438 20:11:26.722574 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1439 20:11:26.726272 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 20:11:26.729697 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 20:11:26.732515 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1442 20:11:26.732597
1443 20:11:26.735832 CA PerBit enable=1, Macro0, CA PI delay=34
1444 20:11:26.735916
1445 20:11:26.739380 [CBTSetCACLKResult] CA Dly = 34
1446 20:11:26.739455 CS Dly: 6 (0~38)
1447 20:11:26.739519
1448 20:11:26.742449 ----->DramcWriteLeveling(PI) begin...
1449 20:11:26.745780 ==
1450 20:11:26.749106 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 20:11:26.752635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 20:11:26.752719 ==
1453 20:11:26.755986 Write leveling (Byte 0): 26 => 26
1454 20:11:26.759278 Write leveling (Byte 1): 28 => 28
1455 20:11:26.762461 DramcWriteLeveling(PI) end<-----
1456 20:11:26.762543
1457 20:11:26.762607 ==
1458 20:11:26.765974 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 20:11:26.769136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1460 20:11:26.769219 ==
1461 20:11:26.772401 [Gating] SW mode calibration
1462 20:11:26.778837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1463 20:11:26.785967 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1464 20:11:26.789643 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1465 20:11:26.792836 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1466 20:11:26.798887 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1467 20:11:26.802663 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 20:11:26.805313 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 20:11:26.808779 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 20:11:26.815192 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 20:11:26.818822 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 20:11:26.822126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 20:11:26.828859 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 20:11:26.832092 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 20:11:26.835525 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 20:11:26.842260 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 20:11:26.845411 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 20:11:26.848550 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 20:11:26.855395 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 20:11:26.858562 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 20:11:26.862149 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1482 20:11:26.868072 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 20:11:26.871964 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 20:11:26.875131 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 20:11:26.881253 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 20:11:26.885513 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 20:11:26.888271 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 20:11:26.894937 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 20:11:26.897949 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 20:11:26.901397 0 9 8 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
1491 20:11:26.908193 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 20:11:26.912325 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 20:11:26.914999 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 20:11:26.921460 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 20:11:26.925366 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 20:11:26.927924 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 20:11:26.934464 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1498 20:11:26.937674 0 10 8 | B1->B0 | 2d2d 2727 | 0 1 | (0 0) (1 0)
1499 20:11:26.941351 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 20:11:26.947964 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 20:11:26.951264 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 20:11:26.954307 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 20:11:26.961346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 20:11:26.964328 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 20:11:26.968156 0 11 4 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
1506 20:11:26.974847 0 11 8 | B1->B0 | 3d3d 3a3a | 1 0 | (0 0) (0 0)
1507 20:11:26.978084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 20:11:26.981549 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 20:11:26.987934 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 20:11:26.991424 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 20:11:26.994478 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 20:11:27.000540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 20:11:27.004327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1514 20:11:27.007475 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 20:11:27.013788 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 20:11:27.017139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 20:11:27.020678 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 20:11:27.027137 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 20:11:27.030339 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 20:11:27.033750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 20:11:27.040311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 20:11:27.044672 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 20:11:27.047547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 20:11:27.053420 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 20:11:27.056632 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 20:11:27.059981 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 20:11:27.067048 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 20:11:27.069988 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 20:11:27.073307 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1530 20:11:27.080716 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 20:11:27.080799 Total UI for P1: 0, mck2ui 16
1532 20:11:27.083047 best dqsien dly found for B0: ( 0, 14, 4)
1533 20:11:27.086620 Total UI for P1: 0, mck2ui 16
1534 20:11:27.089781 best dqsien dly found for B1: ( 0, 14, 6)
1535 20:11:27.093569 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1536 20:11:27.099883 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1537 20:11:27.099966
1538 20:11:27.103492 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 20:11:27.106786 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1540 20:11:27.110761 [Gating] SW calibration Done
1541 20:11:27.110842 ==
1542 20:11:27.113416 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 20:11:27.116354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 20:11:27.116435 ==
1545 20:11:27.116500 RX Vref Scan: 0
1546 20:11:27.119608
1547 20:11:27.119733 RX Vref 0 -> 0, step: 1
1548 20:11:27.119799
1549 20:11:27.123523 RX Delay -130 -> 252, step: 16
1550 20:11:27.126327 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1551 20:11:27.129828 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1552 20:11:27.136439 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1553 20:11:27.139656 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1554 20:11:27.142967 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1555 20:11:27.146679 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1556 20:11:27.152871 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1557 20:11:27.156592 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1558 20:11:27.160042 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1559 20:11:27.162770 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1560 20:11:27.167039 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1561 20:11:27.173067 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1562 20:11:27.176437 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1563 20:11:27.179564 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1564 20:11:27.183050 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1565 20:11:27.186334 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1566 20:11:27.189780 ==
1567 20:11:27.189862 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 20:11:27.196147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 20:11:27.196229 ==
1570 20:11:27.196293 DQS Delay:
1571 20:11:27.199553 DQS0 = 0, DQS1 = 0
1572 20:11:27.199634 DQM Delay:
1573 20:11:27.202624 DQM0 = 88, DQM1 = 78
1574 20:11:27.202706 DQ Delay:
1575 20:11:27.205972 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1576 20:11:27.209748 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1577 20:11:27.212924 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1578 20:11:27.216159 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1579 20:11:27.216240
1580 20:11:27.216304
1581 20:11:27.216363 ==
1582 20:11:27.219540 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 20:11:27.223004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 20:11:27.223086 ==
1585 20:11:27.223152
1586 20:11:27.223212
1587 20:11:27.225976 TX Vref Scan disable
1588 20:11:27.229333 == TX Byte 0 ==
1589 20:11:27.232705 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 20:11:27.235931 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 20:11:27.239615 == TX Byte 1 ==
1592 20:11:27.243027 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1593 20:11:27.246706 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1594 20:11:27.246788 ==
1595 20:11:27.250202 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 20:11:27.253033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 20:11:27.253115 ==
1598 20:11:27.267520 TX Vref=22, minBit 8, minWin=27, winSum=443
1599 20:11:27.270337 TX Vref=24, minBit 9, minWin=27, winSum=446
1600 20:11:27.273601 TX Vref=26, minBit 13, minWin=27, winSum=448
1601 20:11:27.277026 TX Vref=28, minBit 13, minWin=27, winSum=451
1602 20:11:27.280160 TX Vref=30, minBit 10, minWin=27, winSum=447
1603 20:11:27.286942 TX Vref=32, minBit 9, minWin=26, winSum=442
1604 20:11:27.290276 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 28
1605 20:11:27.290371
1606 20:11:27.293388 Final TX Range 1 Vref 28
1607 20:11:27.293472
1608 20:11:27.293537 ==
1609 20:11:27.296918 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 20:11:27.300513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 20:11:27.303695 ==
1612 20:11:27.303778
1613 20:11:27.303842
1614 20:11:27.303902 TX Vref Scan disable
1615 20:11:27.307455 == TX Byte 0 ==
1616 20:11:27.310728 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1617 20:11:27.317529 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1618 20:11:27.317611 == TX Byte 1 ==
1619 20:11:27.320809 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1620 20:11:27.327387 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1621 20:11:27.327470
1622 20:11:27.327535 [DATLAT]
1623 20:11:27.327596 Freq=800, CH1 RK0
1624 20:11:27.327655
1625 20:11:27.330597 DATLAT Default: 0xa
1626 20:11:27.330679 0, 0xFFFF, sum = 0
1627 20:11:27.334208 1, 0xFFFF, sum = 0
1628 20:11:27.334290 2, 0xFFFF, sum = 0
1629 20:11:27.337363 3, 0xFFFF, sum = 0
1630 20:11:27.340971 4, 0xFFFF, sum = 0
1631 20:11:27.341055 5, 0xFFFF, sum = 0
1632 20:11:27.344204 6, 0xFFFF, sum = 0
1633 20:11:27.344288 7, 0xFFFF, sum = 0
1634 20:11:27.347293 8, 0xFFFF, sum = 0
1635 20:11:27.347377 9, 0x0, sum = 1
1636 20:11:27.350966 10, 0x0, sum = 2
1637 20:11:27.351050 11, 0x0, sum = 3
1638 20:11:27.351117 12, 0x0, sum = 4
1639 20:11:27.353973 best_step = 10
1640 20:11:27.354053
1641 20:11:27.354117 ==
1642 20:11:27.356814 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 20:11:27.360308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 20:11:27.360390 ==
1645 20:11:27.363667 RX Vref Scan: 1
1646 20:11:27.363790
1647 20:11:27.366976 Set Vref Range= 32 -> 127
1648 20:11:27.367088
1649 20:11:27.367183 RX Vref 32 -> 127, step: 1
1650 20:11:27.367260
1651 20:11:27.370203 RX Delay -95 -> 252, step: 8
1652 20:11:27.370285
1653 20:11:27.373907 Set Vref, RX VrefLevel [Byte0]: 32
1654 20:11:27.377048 [Byte1]: 32
1655 20:11:27.380000
1656 20:11:27.380081 Set Vref, RX VrefLevel [Byte0]: 33
1657 20:11:27.383271 [Byte1]: 33
1658 20:11:27.387933
1659 20:11:27.388014 Set Vref, RX VrefLevel [Byte0]: 34
1660 20:11:27.390968 [Byte1]: 34
1661 20:11:27.395219
1662 20:11:27.395299 Set Vref, RX VrefLevel [Byte0]: 35
1663 20:11:27.398452 [Byte1]: 35
1664 20:11:27.403185
1665 20:11:27.403266 Set Vref, RX VrefLevel [Byte0]: 36
1666 20:11:27.406149 [Byte1]: 36
1667 20:11:27.411133
1668 20:11:27.411214 Set Vref, RX VrefLevel [Byte0]: 37
1669 20:11:27.414344 [Byte1]: 37
1670 20:11:27.418708
1671 20:11:27.418789 Set Vref, RX VrefLevel [Byte0]: 38
1672 20:11:27.421169 [Byte1]: 38
1673 20:11:27.425660
1674 20:11:27.425741 Set Vref, RX VrefLevel [Byte0]: 39
1675 20:11:27.429174 [Byte1]: 39
1676 20:11:27.433478
1677 20:11:27.433559 Set Vref, RX VrefLevel [Byte0]: 40
1678 20:11:27.436867 [Byte1]: 40
1679 20:11:27.441107
1680 20:11:27.441218 Set Vref, RX VrefLevel [Byte0]: 41
1681 20:11:27.444403 [Byte1]: 41
1682 20:11:27.448579
1683 20:11:27.451503 Set Vref, RX VrefLevel [Byte0]: 42
1684 20:11:27.454885 [Byte1]: 42
1685 20:11:27.454966
1686 20:11:27.458719 Set Vref, RX VrefLevel [Byte0]: 43
1687 20:11:27.461422 [Byte1]: 43
1688 20:11:27.461506
1689 20:11:27.464749 Set Vref, RX VrefLevel [Byte0]: 44
1690 20:11:27.468052 [Byte1]: 44
1691 20:11:27.471270
1692 20:11:27.471350 Set Vref, RX VrefLevel [Byte0]: 45
1693 20:11:27.474950 [Byte1]: 45
1694 20:11:27.478914
1695 20:11:27.478995 Set Vref, RX VrefLevel [Byte0]: 46
1696 20:11:27.482561 [Byte1]: 46
1697 20:11:27.486921
1698 20:11:27.487003 Set Vref, RX VrefLevel [Byte0]: 47
1699 20:11:27.490146 [Byte1]: 47
1700 20:11:27.495016
1701 20:11:27.495097 Set Vref, RX VrefLevel [Byte0]: 48
1702 20:11:27.497670 [Byte1]: 48
1703 20:11:27.501628
1704 20:11:27.501709 Set Vref, RX VrefLevel [Byte0]: 49
1705 20:11:27.505233 [Byte1]: 49
1706 20:11:27.509359
1707 20:11:27.509439 Set Vref, RX VrefLevel [Byte0]: 50
1708 20:11:27.512641 [Byte1]: 50
1709 20:11:27.517349
1710 20:11:27.517430 Set Vref, RX VrefLevel [Byte0]: 51
1711 20:11:27.520246 [Byte1]: 51
1712 20:11:27.524763
1713 20:11:27.524843 Set Vref, RX VrefLevel [Byte0]: 52
1714 20:11:27.527932 [Byte1]: 52
1715 20:11:27.532127
1716 20:11:27.532207 Set Vref, RX VrefLevel [Byte0]: 53
1717 20:11:27.535463 [Byte1]: 53
1718 20:11:27.540135
1719 20:11:27.540215 Set Vref, RX VrefLevel [Byte0]: 54
1720 20:11:27.543459 [Byte1]: 54
1721 20:11:27.547234
1722 20:11:27.550979 Set Vref, RX VrefLevel [Byte0]: 55
1723 20:11:27.553852 [Byte1]: 55
1724 20:11:27.553934
1725 20:11:27.557336 Set Vref, RX VrefLevel [Byte0]: 56
1726 20:11:27.560517 [Byte1]: 56
1727 20:11:27.560598
1728 20:11:27.563603 Set Vref, RX VrefLevel [Byte0]: 57
1729 20:11:27.566927 [Byte1]: 57
1730 20:11:27.567009
1731 20:11:27.570391 Set Vref, RX VrefLevel [Byte0]: 58
1732 20:11:27.573593 [Byte1]: 58
1733 20:11:27.577510
1734 20:11:27.577658 Set Vref, RX VrefLevel [Byte0]: 59
1735 20:11:27.580776 [Byte1]: 59
1736 20:11:27.585731
1737 20:11:27.585813 Set Vref, RX VrefLevel [Byte0]: 60
1738 20:11:27.588718 [Byte1]: 60
1739 20:11:27.593210
1740 20:11:27.593292 Set Vref, RX VrefLevel [Byte0]: 61
1741 20:11:27.596269 [Byte1]: 61
1742 20:11:27.600323
1743 20:11:27.600405 Set Vref, RX VrefLevel [Byte0]: 62
1744 20:11:27.603471 [Byte1]: 62
1745 20:11:27.608153
1746 20:11:27.608235 Set Vref, RX VrefLevel [Byte0]: 63
1747 20:11:27.611189 [Byte1]: 63
1748 20:11:27.615455
1749 20:11:27.615565 Set Vref, RX VrefLevel [Byte0]: 64
1750 20:11:27.619278 [Byte1]: 64
1751 20:11:27.623231
1752 20:11:27.623313 Set Vref, RX VrefLevel [Byte0]: 65
1753 20:11:27.626545 [Byte1]: 65
1754 20:11:27.631520
1755 20:11:27.631602 Set Vref, RX VrefLevel [Byte0]: 66
1756 20:11:27.634172 [Byte1]: 66
1757 20:11:27.638580
1758 20:11:27.638662 Set Vref, RX VrefLevel [Byte0]: 67
1759 20:11:27.642055 [Byte1]: 67
1760 20:11:27.646268
1761 20:11:27.646351 Set Vref, RX VrefLevel [Byte0]: 68
1762 20:11:27.649176 [Byte1]: 68
1763 20:11:27.653993
1764 20:11:27.654074 Set Vref, RX VrefLevel [Byte0]: 69
1765 20:11:27.656775 [Byte1]: 69
1766 20:11:27.661538
1767 20:11:27.661620 Set Vref, RX VrefLevel [Byte0]: 70
1768 20:11:27.664318 [Byte1]: 70
1769 20:11:27.668655
1770 20:11:27.668737 Set Vref, RX VrefLevel [Byte0]: 71
1771 20:11:27.672535 [Byte1]: 71
1772 20:11:27.676653
1773 20:11:27.676735 Set Vref, RX VrefLevel [Byte0]: 72
1774 20:11:27.682943 [Byte1]: 72
1775 20:11:27.683025
1776 20:11:27.686538 Set Vref, RX VrefLevel [Byte0]: 73
1777 20:11:27.689376 [Byte1]: 73
1778 20:11:27.689459
1779 20:11:27.692699 Set Vref, RX VrefLevel [Byte0]: 74
1780 20:11:27.696183 [Byte1]: 74
1781 20:11:27.696265
1782 20:11:27.699949 Set Vref, RX VrefLevel [Byte0]: 75
1783 20:11:27.703009 [Byte1]: 75
1784 20:11:27.706522
1785 20:11:27.706604 Final RX Vref Byte 0 = 56 to rank0
1786 20:11:27.709839 Final RX Vref Byte 1 = 64 to rank0
1787 20:11:27.713492 Final RX Vref Byte 0 = 56 to rank1
1788 20:11:27.716617 Final RX Vref Byte 1 = 64 to rank1==
1789 20:11:27.719950 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 20:11:27.726755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 20:11:27.726838 ==
1792 20:11:27.726903 DQS Delay:
1793 20:11:27.729986 DQS0 = 0, DQS1 = 0
1794 20:11:27.730068 DQM Delay:
1795 20:11:27.730133 DQM0 = 86, DQM1 = 79
1796 20:11:27.733243 DQ Delay:
1797 20:11:27.736662 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1798 20:11:27.739629 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1799 20:11:27.743308 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1800 20:11:27.746517 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =92
1801 20:11:27.746602
1802 20:11:27.746665
1803 20:11:27.753152 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1804 20:11:27.757277 CH1 RK0: MR19=606, MR18=311D
1805 20:11:27.763249 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1806 20:11:27.763332
1807 20:11:27.766458 ----->DramcWriteLeveling(PI) begin...
1808 20:11:27.766541 ==
1809 20:11:27.769448 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 20:11:27.773067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 20:11:27.773150 ==
1812 20:11:27.776423 Write leveling (Byte 0): 25 => 25
1813 20:11:27.779738 Write leveling (Byte 1): 31 => 31
1814 20:11:27.782541 DramcWriteLeveling(PI) end<-----
1815 20:11:27.782623
1816 20:11:27.782687 ==
1817 20:11:27.786405 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 20:11:27.789396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 20:11:27.789481 ==
1820 20:11:27.792730 [Gating] SW mode calibration
1821 20:11:27.799305 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 20:11:27.806356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 20:11:27.809471 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1824 20:11:27.815753 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1825 20:11:27.819110 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 20:11:27.822273 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 20:11:27.829094 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 20:11:27.832509 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 20:11:27.835941 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 20:11:27.842545 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 20:11:27.845789 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 20:11:27.848700 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 20:11:27.855822 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 20:11:27.858991 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 20:11:27.862523 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 20:11:27.869144 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 20:11:27.872177 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 20:11:27.875415 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 20:11:27.882473 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 20:11:27.885651 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1841 20:11:27.888941 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 20:11:27.895319 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 20:11:27.898779 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 20:11:27.901832 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 20:11:27.908948 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 20:11:27.911936 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 20:11:27.915025 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 20:11:27.918577 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 20:11:27.925307 0 9 8 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
1850 20:11:27.928391 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 20:11:27.931747 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 20:11:27.938470 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 20:11:27.941453 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 20:11:27.945188 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 20:11:27.951819 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 20:11:27.955232 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 0)
1857 20:11:27.957884 0 10 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1858 20:11:27.964630 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 20:11:27.968504 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 20:11:27.971377 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 20:11:27.977700 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 20:11:27.981160 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 20:11:27.984460 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 20:11:27.990815 0 11 4 | B1->B0 | 2f2f 2323 | 1 1 | (0 0) (0 0)
1865 20:11:27.994401 0 11 8 | B1->B0 | 3b3b 2f2f | 0 0 | (0 0) (0 0)
1866 20:11:27.997675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 20:11:28.004660 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 20:11:28.007358 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 20:11:28.011570 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 20:11:28.017641 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 20:11:28.021040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 20:11:28.024786 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 20:11:28.030897 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1874 20:11:28.034224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 20:11:28.037613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 20:11:28.044175 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 20:11:28.047203 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 20:11:28.051015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 20:11:28.057644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 20:11:28.061266 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 20:11:28.064039 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 20:11:28.070873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 20:11:28.073963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 20:11:28.077242 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 20:11:28.084258 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 20:11:28.087336 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 20:11:28.090616 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 20:11:28.096914 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 20:11:28.100666 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1890 20:11:28.103806 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 20:11:28.107499 Total UI for P1: 0, mck2ui 16
1892 20:11:28.110928 best dqsien dly found for B0: ( 0, 14, 8)
1893 20:11:28.113734 Total UI for P1: 0, mck2ui 16
1894 20:11:28.117070 best dqsien dly found for B1: ( 0, 14, 8)
1895 20:11:28.120349 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1896 20:11:28.123933 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1897 20:11:28.124017
1898 20:11:28.126995 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1899 20:11:28.133737 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1900 20:11:28.133820 [Gating] SW calibration Done
1901 20:11:28.133886 ==
1902 20:11:28.137097 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 20:11:28.143997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 20:11:28.144081 ==
1905 20:11:28.144159 RX Vref Scan: 0
1906 20:11:28.144253
1907 20:11:28.147283 RX Vref 0 -> 0, step: 1
1908 20:11:28.147365
1909 20:11:28.150793 RX Delay -130 -> 252, step: 16
1910 20:11:28.153457 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1911 20:11:28.156857 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1912 20:11:28.160612 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1913 20:11:28.166426 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1914 20:11:28.170259 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1915 20:11:28.173020 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1916 20:11:28.176971 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1917 20:11:28.180154 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1918 20:11:28.186494 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1919 20:11:28.189944 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1920 20:11:28.193304 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1921 20:11:28.196634 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1922 20:11:28.203256 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1923 20:11:28.206604 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1924 20:11:28.210076 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1925 20:11:28.213080 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1926 20:11:28.213163 ==
1927 20:11:28.216335 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 20:11:28.219920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 20:11:28.223083 ==
1930 20:11:28.223166 DQS Delay:
1931 20:11:28.223231 DQS0 = 0, DQS1 = 0
1932 20:11:28.226475 DQM Delay:
1933 20:11:28.226558 DQM0 = 86, DQM1 = 78
1934 20:11:28.230057 DQ Delay:
1935 20:11:28.232890 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1936 20:11:28.236851 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1937 20:11:28.236932 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1938 20:11:28.242737 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1939 20:11:28.242819
1940 20:11:28.242883
1941 20:11:28.242942 ==
1942 20:11:28.246023 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 20:11:28.250468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 20:11:28.250550 ==
1945 20:11:28.250616
1946 20:11:28.250676
1947 20:11:28.253201 TX Vref Scan disable
1948 20:11:28.253282 == TX Byte 0 ==
1949 20:11:28.259428 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1950 20:11:28.262872 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1951 20:11:28.262954 == TX Byte 1 ==
1952 20:11:28.269465 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1953 20:11:28.273066 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1954 20:11:28.273150 ==
1955 20:11:28.276283 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 20:11:28.279234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 20:11:28.279359 ==
1958 20:11:28.294251 TX Vref=22, minBit 1, minWin=27, winSum=441
1959 20:11:28.297502 TX Vref=24, minBit 1, minWin=27, winSum=446
1960 20:11:28.300762 TX Vref=26, minBit 8, minWin=27, winSum=450
1961 20:11:28.304480 TX Vref=28, minBit 3, minWin=27, winSum=450
1962 20:11:28.307916 TX Vref=30, minBit 8, minWin=27, winSum=445
1963 20:11:28.314256 TX Vref=32, minBit 7, minWin=27, winSum=445
1964 20:11:28.317402 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 26
1965 20:11:28.317484
1966 20:11:28.321028 Final TX Range 1 Vref 26
1967 20:11:28.321110
1968 20:11:28.321174 ==
1969 20:11:28.323813 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 20:11:28.327125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 20:11:28.327232 ==
1972 20:11:28.330829
1973 20:11:28.330927
1974 20:11:28.331006 TX Vref Scan disable
1975 20:11:28.333766 == TX Byte 0 ==
1976 20:11:28.337293 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1977 20:11:28.343633 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1978 20:11:28.343752 == TX Byte 1 ==
1979 20:11:28.347655 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1980 20:11:28.353727 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1981 20:11:28.353826
1982 20:11:28.353905 [DATLAT]
1983 20:11:28.353965 Freq=800, CH1 RK1
1984 20:11:28.354024
1985 20:11:28.356883 DATLAT Default: 0xa
1986 20:11:28.360410 0, 0xFFFF, sum = 0
1987 20:11:28.360493 1, 0xFFFF, sum = 0
1988 20:11:28.363545 2, 0xFFFF, sum = 0
1989 20:11:28.363627 3, 0xFFFF, sum = 0
1990 20:11:28.367285 4, 0xFFFF, sum = 0
1991 20:11:28.367368 5, 0xFFFF, sum = 0
1992 20:11:28.370479 6, 0xFFFF, sum = 0
1993 20:11:28.370564 7, 0xFFFF, sum = 0
1994 20:11:28.373723 8, 0xFFFF, sum = 0
1995 20:11:28.373810 9, 0x0, sum = 1
1996 20:11:28.376855 10, 0x0, sum = 2
1997 20:11:28.376939 11, 0x0, sum = 3
1998 20:11:28.377006 12, 0x0, sum = 4
1999 20:11:28.380297 best_step = 10
2000 20:11:28.380380
2001 20:11:28.380466 ==
2002 20:11:28.383918 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 20:11:28.387296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 20:11:28.387381 ==
2005 20:11:28.390084 RX Vref Scan: 0
2006 20:11:28.390167
2007 20:11:28.393427 RX Vref 0 -> 0, step: 1
2008 20:11:28.393510
2009 20:11:28.393575 RX Delay -95 -> 252, step: 8
2010 20:11:28.400492 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2011 20:11:28.404302 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2012 20:11:28.406913 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2013 20:11:28.410205 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2014 20:11:28.416832 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2015 20:11:28.420963 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2016 20:11:28.423409 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2017 20:11:28.426987 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2018 20:11:28.430919 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2019 20:11:28.437008 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2020 20:11:28.440473 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2021 20:11:28.443727 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2022 20:11:28.446807 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2023 20:11:28.450171 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2024 20:11:28.456798 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2025 20:11:28.459781 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2026 20:11:28.459863 ==
2027 20:11:28.463379 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 20:11:28.467181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 20:11:28.467278 ==
2030 20:11:28.470147 DQS Delay:
2031 20:11:28.470220 DQS0 = 0, DQS1 = 0
2032 20:11:28.470282 DQM Delay:
2033 20:11:28.473576 DQM0 = 87, DQM1 = 78
2034 20:11:28.473696 DQ Delay:
2035 20:11:28.476910 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2036 20:11:28.479933 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2037 20:11:28.483234 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2038 20:11:28.486550 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2039 20:11:28.486632
2040 20:11:28.486696
2041 20:11:28.496739 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2042 20:11:28.499649 CH1 RK1: MR19=606, MR18=1A13
2043 20:11:28.503523 CH1_RK1: MR19=0x606, MR18=0x1A13, DQSOSC=403, MR23=63, INC=90, DEC=60
2044 20:11:28.506166 [RxdqsGatingPostProcess] freq 800
2045 20:11:28.513604 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 20:11:28.516583 Pre-setting of DQS Precalculation
2047 20:11:28.520297 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 20:11:28.529765 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 20:11:28.536012 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 20:11:28.536094
2051 20:11:28.536158
2052 20:11:28.540141 [Calibration Summary] 1600 Mbps
2053 20:11:28.540222 CH 0, Rank 0
2054 20:11:28.543318 SW Impedance : PASS
2055 20:11:28.543399 DUTY Scan : NO K
2056 20:11:28.546781 ZQ Calibration : PASS
2057 20:11:28.549732 Jitter Meter : NO K
2058 20:11:28.549845 CBT Training : PASS
2059 20:11:28.552563 Write leveling : PASS
2060 20:11:28.556031 RX DQS gating : PASS
2061 20:11:28.556111 RX DQ/DQS(RDDQC) : PASS
2062 20:11:28.559384 TX DQ/DQS : PASS
2063 20:11:28.562999 RX DATLAT : PASS
2064 20:11:28.563083 RX DQ/DQS(Engine): PASS
2065 20:11:28.566149 TX OE : NO K
2066 20:11:28.566231 All Pass.
2067 20:11:28.566295
2068 20:11:28.569546 CH 0, Rank 1
2069 20:11:28.569627 SW Impedance : PASS
2070 20:11:28.572398 DUTY Scan : NO K
2071 20:11:28.575548 ZQ Calibration : PASS
2072 20:11:28.575629 Jitter Meter : NO K
2073 20:11:28.579159 CBT Training : PASS
2074 20:11:28.583496 Write leveling : PASS
2075 20:11:28.583577 RX DQS gating : PASS
2076 20:11:28.585699 RX DQ/DQS(RDDQC) : PASS
2077 20:11:28.589468 TX DQ/DQS : PASS
2078 20:11:28.589549 RX DATLAT : PASS
2079 20:11:28.592107 RX DQ/DQS(Engine): PASS
2080 20:11:28.592188 TX OE : NO K
2081 20:11:28.595539 All Pass.
2082 20:11:28.595620
2083 20:11:28.595709 CH 1, Rank 0
2084 20:11:28.599121 SW Impedance : PASS
2085 20:11:28.599202 DUTY Scan : NO K
2086 20:11:28.602210 ZQ Calibration : PASS
2087 20:11:28.606002 Jitter Meter : NO K
2088 20:11:28.606083 CBT Training : PASS
2089 20:11:28.608589 Write leveling : PASS
2090 20:11:28.612083 RX DQS gating : PASS
2091 20:11:28.612164 RX DQ/DQS(RDDQC) : PASS
2092 20:11:28.615464 TX DQ/DQS : PASS
2093 20:11:28.619034 RX DATLAT : PASS
2094 20:11:28.619115 RX DQ/DQS(Engine): PASS
2095 20:11:28.622285 TX OE : NO K
2096 20:11:28.622367 All Pass.
2097 20:11:28.622430
2098 20:11:28.625271 CH 1, Rank 1
2099 20:11:28.625352 SW Impedance : PASS
2100 20:11:28.629204 DUTY Scan : NO K
2101 20:11:28.632109 ZQ Calibration : PASS
2102 20:11:28.632190 Jitter Meter : NO K
2103 20:11:28.635637 CBT Training : PASS
2104 20:11:28.638697 Write leveling : PASS
2105 20:11:28.638778 RX DQS gating : PASS
2106 20:11:28.642267 RX DQ/DQS(RDDQC) : PASS
2107 20:11:28.645573 TX DQ/DQS : PASS
2108 20:11:28.645655 RX DATLAT : PASS
2109 20:11:28.648502 RX DQ/DQS(Engine): PASS
2110 20:11:28.648583 TX OE : NO K
2111 20:11:28.651854 All Pass.
2112 20:11:28.651934
2113 20:11:28.651998 DramC Write-DBI off
2114 20:11:28.655131 PER_BANK_REFRESH: Hybrid Mode
2115 20:11:28.658379 TX_TRACKING: ON
2116 20:11:28.661873 [GetDramInforAfterCalByMRR] Vendor 6.
2117 20:11:28.665248 [GetDramInforAfterCalByMRR] Revision 606.
2118 20:11:28.668310 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 20:11:28.668392 MR0 0x3b3b
2120 20:11:28.671703 MR8 0x5151
2121 20:11:28.674910 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 20:11:28.674992
2123 20:11:28.675057 MR0 0x3b3b
2124 20:11:28.675116 MR8 0x5151
2125 20:11:28.678586 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 20:11:28.682467
2127 20:11:28.688149 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 20:11:28.691896 [FAST_K] Save calibration result to emmc
2129 20:11:28.694604 [FAST_K] Save calibration result to emmc
2130 20:11:28.698085 dram_init: config_dvfs: 1
2131 20:11:28.701513 dramc_set_vcore_voltage set vcore to 662500
2132 20:11:28.704800 Read voltage for 1200, 2
2133 20:11:28.704882 Vio18 = 0
2134 20:11:28.708057 Vcore = 662500
2135 20:11:28.708139 Vdram = 0
2136 20:11:28.708205 Vddq = 0
2137 20:11:28.708266 Vmddr = 0
2138 20:11:28.714795 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 20:11:28.721797 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 20:11:28.721880 MEM_TYPE=3, freq_sel=15
2141 20:11:28.724703 sv_algorithm_assistance_LP4_1600
2142 20:11:28.727642 ============ PULL DRAM RESETB DOWN ============
2143 20:11:28.734314 ========== PULL DRAM RESETB DOWN end =========
2144 20:11:28.737989 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 20:11:28.741496 ===================================
2146 20:11:28.744640 LPDDR4 DRAM CONFIGURATION
2147 20:11:28.747846 ===================================
2148 20:11:28.747928 EX_ROW_EN[0] = 0x0
2149 20:11:28.751129 EX_ROW_EN[1] = 0x0
2150 20:11:28.754483 LP4Y_EN = 0x0
2151 20:11:28.754565 WORK_FSP = 0x0
2152 20:11:28.757508 WL = 0x4
2153 20:11:28.757589 RL = 0x4
2154 20:11:28.760769 BL = 0x2
2155 20:11:28.760850 RPST = 0x0
2156 20:11:28.764710 RD_PRE = 0x0
2157 20:11:28.764793 WR_PRE = 0x1
2158 20:11:28.767389 WR_PST = 0x0
2159 20:11:28.767471 DBI_WR = 0x0
2160 20:11:28.770842 DBI_RD = 0x0
2161 20:11:28.770924 OTF = 0x1
2162 20:11:28.773861 ===================================
2163 20:11:28.777654 ===================================
2164 20:11:28.780672 ANA top config
2165 20:11:28.784374 ===================================
2166 20:11:28.784457 DLL_ASYNC_EN = 0
2167 20:11:28.787869 ALL_SLAVE_EN = 0
2168 20:11:28.790397 NEW_RANK_MODE = 1
2169 20:11:28.794172 DLL_IDLE_MODE = 1
2170 20:11:28.797180 LP45_APHY_COMB_EN = 1
2171 20:11:28.797262 TX_ODT_DIS = 1
2172 20:11:28.800283 NEW_8X_MODE = 1
2173 20:11:28.804140 ===================================
2174 20:11:28.807393 ===================================
2175 20:11:28.810617 data_rate = 2400
2176 20:11:28.813831 CKR = 1
2177 20:11:28.817507 DQ_P2S_RATIO = 8
2178 20:11:28.820282 ===================================
2179 20:11:28.823606 CA_P2S_RATIO = 8
2180 20:11:28.823695 DQ_CA_OPEN = 0
2181 20:11:28.827169 DQ_SEMI_OPEN = 0
2182 20:11:28.830558 CA_SEMI_OPEN = 0
2183 20:11:28.833451 CA_FULL_RATE = 0
2184 20:11:28.837184 DQ_CKDIV4_EN = 0
2185 20:11:28.840524 CA_CKDIV4_EN = 0
2186 20:11:28.840605 CA_PREDIV_EN = 0
2187 20:11:28.843291 PH8_DLY = 17
2188 20:11:28.846689 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 20:11:28.850024 DQ_AAMCK_DIV = 4
2190 20:11:28.853445 CA_AAMCK_DIV = 4
2191 20:11:28.856833 CA_ADMCK_DIV = 4
2192 20:11:28.856914 DQ_TRACK_CA_EN = 0
2193 20:11:28.860355 CA_PICK = 1200
2194 20:11:28.863372 CA_MCKIO = 1200
2195 20:11:28.866479 MCKIO_SEMI = 0
2196 20:11:28.870013 PLL_FREQ = 2366
2197 20:11:28.872991 DQ_UI_PI_RATIO = 32
2198 20:11:28.876954 CA_UI_PI_RATIO = 0
2199 20:11:28.880004 ===================================
2200 20:11:28.883780 ===================================
2201 20:11:28.883862 memory_type:LPDDR4
2202 20:11:28.886557 GP_NUM : 10
2203 20:11:28.889697 SRAM_EN : 1
2204 20:11:28.889779 MD32_EN : 0
2205 20:11:28.892941 ===================================
2206 20:11:28.896974 [ANA_INIT] >>>>>>>>>>>>>>
2207 20:11:28.900725 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 20:11:28.902997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 20:11:28.906233 ===================================
2210 20:11:28.909440 data_rate = 2400,PCW = 0X5b00
2211 20:11:28.912730 ===================================
2212 20:11:28.916691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 20:11:28.919414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 20:11:28.926017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 20:11:28.929527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 20:11:28.932745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 20:11:28.939516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 20:11:28.939599 [ANA_INIT] flow start
2219 20:11:28.942688 [ANA_INIT] PLL >>>>>>>>
2220 20:11:28.945746 [ANA_INIT] PLL <<<<<<<<
2221 20:11:28.945827 [ANA_INIT] MIDPI >>>>>>>>
2222 20:11:28.949173 [ANA_INIT] MIDPI <<<<<<<<
2223 20:11:28.952827 [ANA_INIT] DLL >>>>>>>>
2224 20:11:28.952908 [ANA_INIT] DLL <<<<<<<<
2225 20:11:28.955847 [ANA_INIT] flow end
2226 20:11:28.959160 ============ LP4 DIFF to SE enter ============
2227 20:11:28.962479 ============ LP4 DIFF to SE exit ============
2228 20:11:28.965649 [ANA_INIT] <<<<<<<<<<<<<
2229 20:11:28.968939 [Flow] Enable top DCM control >>>>>
2230 20:11:28.972094 [Flow] Enable top DCM control <<<<<
2231 20:11:28.976087 Enable DLL master slave shuffle
2232 20:11:28.982009 ==============================================================
2233 20:11:28.982091 Gating Mode config
2234 20:11:28.989347 ==============================================================
2235 20:11:28.989430 Config description:
2236 20:11:28.998669 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 20:11:29.005185 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 20:11:29.012064 SELPH_MODE 0: By rank 1: By Phase
2239 20:11:29.015498 ==============================================================
2240 20:11:29.018438 GAT_TRACK_EN = 1
2241 20:11:29.021994 RX_GATING_MODE = 2
2242 20:11:29.025569 RX_GATING_TRACK_MODE = 2
2243 20:11:29.028900 SELPH_MODE = 1
2244 20:11:29.031862 PICG_EARLY_EN = 1
2245 20:11:29.035045 VALID_LAT_VALUE = 1
2246 20:11:29.042032 ==============================================================
2247 20:11:29.045432 Enter into Gating configuration >>>>
2248 20:11:29.048543 Exit from Gating configuration <<<<
2249 20:11:29.052091 Enter into DVFS_PRE_config >>>>>
2250 20:11:29.062033 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 20:11:29.065235 Exit from DVFS_PRE_config <<<<<
2252 20:11:29.068059 Enter into PICG configuration >>>>
2253 20:11:29.072068 Exit from PICG configuration <<<<
2254 20:11:29.075252 [RX_INPUT] configuration >>>>>
2255 20:11:29.075327 [RX_INPUT] configuration <<<<<
2256 20:11:29.081662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 20:11:29.088354 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 20:11:29.094832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 20:11:29.097956 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 20:11:29.104860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 20:11:29.110815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 20:11:29.114354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 20:11:29.118108 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 20:11:29.124637 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 20:11:29.127701 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 20:11:29.130658 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 20:11:29.137762 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 20:11:29.141061 ===================================
2269 20:11:29.141144 LPDDR4 DRAM CONFIGURATION
2270 20:11:29.143971 ===================================
2271 20:11:29.147578 EX_ROW_EN[0] = 0x0
2272 20:11:29.150654 EX_ROW_EN[1] = 0x0
2273 20:11:29.150736 LP4Y_EN = 0x0
2274 20:11:29.154280 WORK_FSP = 0x0
2275 20:11:29.154362 WL = 0x4
2276 20:11:29.157367 RL = 0x4
2277 20:11:29.157449 BL = 0x2
2278 20:11:29.160865 RPST = 0x0
2279 20:11:29.160947 RD_PRE = 0x0
2280 20:11:29.164805 WR_PRE = 0x1
2281 20:11:29.164888 WR_PST = 0x0
2282 20:11:29.168062 DBI_WR = 0x0
2283 20:11:29.168174 DBI_RD = 0x0
2284 20:11:29.170815 OTF = 0x1
2285 20:11:29.174100 ===================================
2286 20:11:29.177364 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 20:11:29.180922 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 20:11:29.187514 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 20:11:29.190910 ===================================
2290 20:11:29.190992 LPDDR4 DRAM CONFIGURATION
2291 20:11:29.193797 ===================================
2292 20:11:29.197245 EX_ROW_EN[0] = 0x10
2293 20:11:29.197327 EX_ROW_EN[1] = 0x0
2294 20:11:29.200578 LP4Y_EN = 0x0
2295 20:11:29.203918 WORK_FSP = 0x0
2296 20:11:29.204000 WL = 0x4
2297 20:11:29.207352 RL = 0x4
2298 20:11:29.207434 BL = 0x2
2299 20:11:29.210617 RPST = 0x0
2300 20:11:29.210698 RD_PRE = 0x0
2301 20:11:29.213810 WR_PRE = 0x1
2302 20:11:29.213892 WR_PST = 0x0
2303 20:11:29.216975 DBI_WR = 0x0
2304 20:11:29.217056 DBI_RD = 0x0
2305 20:11:29.220208 OTF = 0x1
2306 20:11:29.223621 ===================================
2307 20:11:29.230403 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 20:11:29.230486 ==
2309 20:11:29.233700 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 20:11:29.236720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 20:11:29.236802 ==
2312 20:11:29.240341 [Duty_Offset_Calibration]
2313 20:11:29.240422 B0:1 B1:-1 CA:0
2314 20:11:29.240486
2315 20:11:29.243610 [DutyScan_Calibration_Flow] k_type=0
2316 20:11:29.253263
2317 20:11:29.253345 ==CLK 0==
2318 20:11:29.256661 Final CLK duty delay cell = 0
2319 20:11:29.260131 [0] MAX Duty = 5094%(X100), DQS PI = 14
2320 20:11:29.263300 [0] MIN Duty = 4907%(X100), DQS PI = 8
2321 20:11:29.263382 [0] AVG Duty = 5000%(X100)
2322 20:11:29.266488
2323 20:11:29.269854 CH0 CLK Duty spec in!! Max-Min= 187%
2324 20:11:29.273893 [DutyScan_Calibration_Flow] ====Done====
2325 20:11:29.273975
2326 20:11:29.277177 [DutyScan_Calibration_Flow] k_type=1
2327 20:11:29.291938
2328 20:11:29.292020 ==DQS 0 ==
2329 20:11:29.295736 Final DQS duty delay cell = -4
2330 20:11:29.298928 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2331 20:11:29.301903 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2332 20:11:29.305269 [-4] AVG Duty = 4968%(X100)
2333 20:11:29.305351
2334 20:11:29.305415 ==DQS 1 ==
2335 20:11:29.308575 Final DQS duty delay cell = 0
2336 20:11:29.311834 [0] MAX Duty = 5125%(X100), DQS PI = 54
2337 20:11:29.315381 [0] MIN Duty = 5000%(X100), DQS PI = 22
2338 20:11:29.318474 [0] AVG Duty = 5062%(X100)
2339 20:11:29.318555
2340 20:11:29.321692 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2341 20:11:29.321773
2342 20:11:29.325128 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2343 20:11:29.328101 [DutyScan_Calibration_Flow] ====Done====
2344 20:11:29.328183
2345 20:11:29.331848 [DutyScan_Calibration_Flow] k_type=3
2346 20:11:29.350176
2347 20:11:29.350258 ==DQM 0 ==
2348 20:11:29.352767 Final DQM duty delay cell = 0
2349 20:11:29.356023 [0] MAX Duty = 5062%(X100), DQS PI = 24
2350 20:11:29.359252 [0] MIN Duty = 4875%(X100), DQS PI = 8
2351 20:11:29.363094 [0] AVG Duty = 4968%(X100)
2352 20:11:29.363189
2353 20:11:29.363271 ==DQM 1 ==
2354 20:11:29.366424 Final DQM duty delay cell = 4
2355 20:11:29.369485 [4] MAX Duty = 5187%(X100), DQS PI = 14
2356 20:11:29.373034 [4] MIN Duty = 5000%(X100), DQS PI = 24
2357 20:11:29.375883 [4] AVG Duty = 5093%(X100)
2358 20:11:29.375965
2359 20:11:29.379322 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2360 20:11:29.379404
2361 20:11:29.382737 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2362 20:11:29.385995 [DutyScan_Calibration_Flow] ====Done====
2363 20:11:29.386078
2364 20:11:29.389404 [DutyScan_Calibration_Flow] k_type=2
2365 20:11:29.405381
2366 20:11:29.405463 ==DQ 0 ==
2367 20:11:29.408924 Final DQ duty delay cell = -4
2368 20:11:29.412209 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2369 20:11:29.415236 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2370 20:11:29.418703 [-4] AVG Duty = 4969%(X100)
2371 20:11:29.418785
2372 20:11:29.418849 ==DQ 1 ==
2373 20:11:29.421818 Final DQ duty delay cell = 0
2374 20:11:29.425897 [0] MAX Duty = 5125%(X100), DQS PI = 50
2375 20:11:29.428351 [0] MIN Duty = 5000%(X100), DQS PI = 24
2376 20:11:29.432063 [0] AVG Duty = 5062%(X100)
2377 20:11:29.432146
2378 20:11:29.435227 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2379 20:11:29.435308
2380 20:11:29.438181 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2381 20:11:29.441663 [DutyScan_Calibration_Flow] ====Done====
2382 20:11:29.441745 ==
2383 20:11:29.444940 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 20:11:29.448362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 20:11:29.448444 ==
2386 20:11:29.451966 [Duty_Offset_Calibration]
2387 20:11:29.452049 B0:-1 B1:1 CA:1
2388 20:11:29.452114
2389 20:11:29.454866 [DutyScan_Calibration_Flow] k_type=0
2390 20:11:29.466091
2391 20:11:29.466173 ==CLK 0==
2392 20:11:29.468851 Final CLK duty delay cell = 0
2393 20:11:29.472299 [0] MAX Duty = 5156%(X100), DQS PI = 20
2394 20:11:29.475436 [0] MIN Duty = 4969%(X100), DQS PI = 60
2395 20:11:29.478600 [0] AVG Duty = 5062%(X100)
2396 20:11:29.478682
2397 20:11:29.482223 CH1 CLK Duty spec in!! Max-Min= 187%
2398 20:11:29.485189 [DutyScan_Calibration_Flow] ====Done====
2399 20:11:29.485272
2400 20:11:29.488973 [DutyScan_Calibration_Flow] k_type=1
2401 20:11:29.505273
2402 20:11:29.505354 ==DQS 0 ==
2403 20:11:29.508508 Final DQS duty delay cell = 0
2404 20:11:29.511459 [0] MAX Duty = 5125%(X100), DQS PI = 18
2405 20:11:29.514983 [0] MIN Duty = 4875%(X100), DQS PI = 8
2406 20:11:29.518256 [0] AVG Duty = 5000%(X100)
2407 20:11:29.518339
2408 20:11:29.518404 ==DQS 1 ==
2409 20:11:29.521400 Final DQS duty delay cell = 0
2410 20:11:29.524667 [0] MAX Duty = 5062%(X100), DQS PI = 8
2411 20:11:29.527723 [0] MIN Duty = 4969%(X100), DQS PI = 56
2412 20:11:29.531582 [0] AVG Duty = 5015%(X100)
2413 20:11:29.531700
2414 20:11:29.534161 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2415 20:11:29.534234
2416 20:11:29.537686 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2417 20:11:29.541736 [DutyScan_Calibration_Flow] ====Done====
2418 20:11:29.541806
2419 20:11:29.544596 [DutyScan_Calibration_Flow] k_type=3
2420 20:11:29.560028
2421 20:11:29.560113 ==DQM 0 ==
2422 20:11:29.563557 Final DQM duty delay cell = -4
2423 20:11:29.567190 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2424 20:11:29.570282 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2425 20:11:29.573490 [-4] AVG Duty = 4953%(X100)
2426 20:11:29.573586
2427 20:11:29.573685 ==DQM 1 ==
2428 20:11:29.577109 Final DQM duty delay cell = 0
2429 20:11:29.580015 [0] MAX Duty = 5187%(X100), DQS PI = 6
2430 20:11:29.583063 [0] MIN Duty = 4969%(X100), DQS PI = 32
2431 20:11:29.586706 [0] AVG Duty = 5078%(X100)
2432 20:11:29.586787
2433 20:11:29.589955 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2434 20:11:29.590028
2435 20:11:29.593083 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2436 20:11:29.596682 [DutyScan_Calibration_Flow] ====Done====
2437 20:11:29.596763
2438 20:11:29.599598 [DutyScan_Calibration_Flow] k_type=2
2439 20:11:29.617237
2440 20:11:29.617318 ==DQ 0 ==
2441 20:11:29.620629 Final DQ duty delay cell = 0
2442 20:11:29.623718 [0] MAX Duty = 5156%(X100), DQS PI = 28
2443 20:11:29.627022 [0] MIN Duty = 4907%(X100), DQS PI = 6
2444 20:11:29.627104 [0] AVG Duty = 5031%(X100)
2445 20:11:29.630693
2446 20:11:29.630775 ==DQ 1 ==
2447 20:11:29.633818 Final DQ duty delay cell = 0
2448 20:11:29.636873 [0] MAX Duty = 5124%(X100), DQS PI = 10
2449 20:11:29.640338 [0] MIN Duty = 4969%(X100), DQS PI = 0
2450 20:11:29.640420 [0] AVG Duty = 5046%(X100)
2451 20:11:29.640484
2452 20:11:29.643936 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2453 20:11:29.646744
2454 20:11:29.650206 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2455 20:11:29.653523 [DutyScan_Calibration_Flow] ====Done====
2456 20:11:29.657081 nWR fixed to 30
2457 20:11:29.657164 [ModeRegInit_LP4] CH0 RK0
2458 20:11:29.660381 [ModeRegInit_LP4] CH0 RK1
2459 20:11:29.663386 [ModeRegInit_LP4] CH1 RK0
2460 20:11:29.666681 [ModeRegInit_LP4] CH1 RK1
2461 20:11:29.666763 match AC timing 7
2462 20:11:29.673332 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 20:11:29.676485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 20:11:29.680017 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 20:11:29.686950 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 20:11:29.689822 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 20:11:29.689904 ==
2468 20:11:29.693342 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 20:11:29.696283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 20:11:29.696366 ==
2471 20:11:29.703393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 20:11:29.709588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 20:11:29.716958 [CA 0] Center 39 (9~70) winsize 62
2474 20:11:29.720299 [CA 1] Center 39 (9~70) winsize 62
2475 20:11:29.723664 [CA 2] Center 35 (5~66) winsize 62
2476 20:11:29.727079 [CA 3] Center 35 (5~66) winsize 62
2477 20:11:29.730151 [CA 4] Center 33 (4~63) winsize 60
2478 20:11:29.733623 [CA 5] Center 33 (3~63) winsize 61
2479 20:11:29.733696
2480 20:11:29.736754 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2481 20:11:29.736837
2482 20:11:29.740285 [CATrainingPosCal] consider 1 rank data
2483 20:11:29.743760 u2DelayCellTimex100 = 270/100 ps
2484 20:11:29.746515 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 20:11:29.753613 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 20:11:29.756841 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 20:11:29.760444 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 20:11:29.763518 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2489 20:11:29.767024 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 20:11:29.767107
2491 20:11:29.769911 CA PerBit enable=1, Macro0, CA PI delay=33
2492 20:11:29.769994
2493 20:11:29.773280 [CBTSetCACLKResult] CA Dly = 33
2494 20:11:29.776572 CS Dly: 8 (0~39)
2495 20:11:29.776654 ==
2496 20:11:29.780050 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 20:11:29.783043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 20:11:29.783159 ==
2499 20:11:29.787224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 20:11:29.793363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2501 20:11:29.802472 [CA 0] Center 39 (8~70) winsize 63
2502 20:11:29.805898 [CA 1] Center 39 (9~70) winsize 62
2503 20:11:29.809476 [CA 2] Center 35 (5~66) winsize 62
2504 20:11:29.812617 [CA 3] Center 34 (4~65) winsize 62
2505 20:11:29.816116 [CA 4] Center 33 (3~64) winsize 62
2506 20:11:29.818998 [CA 5] Center 33 (3~63) winsize 61
2507 20:11:29.819080
2508 20:11:29.822688 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 20:11:29.822769
2510 20:11:29.826036 [CATrainingPosCal] consider 2 rank data
2511 20:11:29.829494 u2DelayCellTimex100 = 270/100 ps
2512 20:11:29.832551 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2513 20:11:29.838942 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2514 20:11:29.842440 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 20:11:29.845652 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2516 20:11:29.849230 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2517 20:11:29.852279 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2518 20:11:29.852362
2519 20:11:29.855607 CA PerBit enable=1, Macro0, CA PI delay=33
2520 20:11:29.855729
2521 20:11:29.858657 [CBTSetCACLKResult] CA Dly = 33
2522 20:11:29.862112 CS Dly: 9 (0~41)
2523 20:11:29.862194
2524 20:11:29.865659 ----->DramcWriteLeveling(PI) begin...
2525 20:11:29.865743 ==
2526 20:11:29.868934 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 20:11:29.872227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 20:11:29.872310 ==
2529 20:11:29.875699 Write leveling (Byte 0): 31 => 31
2530 20:11:29.878513 Write leveling (Byte 1): 29 => 29
2531 20:11:29.881754 DramcWriteLeveling(PI) end<-----
2532 20:11:29.881836
2533 20:11:29.881901 ==
2534 20:11:29.885265 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 20:11:29.888562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 20:11:29.888645 ==
2537 20:11:29.891522 [Gating] SW mode calibration
2538 20:11:29.898516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 20:11:29.904798 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 20:11:29.908581 0 15 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
2541 20:11:29.911480 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
2542 20:11:29.918186 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 20:11:29.921991 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 20:11:29.924847 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 20:11:29.931475 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 20:11:29.935038 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2547 20:11:29.938184 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
2548 20:11:29.944829 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2549 20:11:29.948143 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2550 20:11:29.951481 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 20:11:29.958150 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 20:11:29.961291 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 20:11:29.965063 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 20:11:29.971521 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 20:11:29.974416 1 0 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2556 20:11:29.978537 1 1 0 | B1->B0 | 2726 4646 | 1 0 | (0 0) (0 0)
2557 20:11:29.984548 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2558 20:11:29.988008 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 20:11:29.991161 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 20:11:29.997629 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 20:11:30.000986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 20:11:30.004365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 20:11:30.010898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 20:11:30.014673 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2565 20:11:30.017954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 20:11:30.024675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 20:11:30.027625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 20:11:30.031657 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 20:11:30.037738 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 20:11:30.040959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 20:11:30.044127 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 20:11:30.047615 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 20:11:30.054176 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 20:11:30.058003 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 20:11:30.061541 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 20:11:30.067751 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 20:11:30.070902 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 20:11:30.073784 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 20:11:30.080664 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 20:11:30.083640 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 20:11:30.087619 Total UI for P1: 0, mck2ui 16
2582 20:11:30.090543 best dqsien dly found for B0: ( 1, 3, 28)
2583 20:11:30.093835 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2584 20:11:30.100433 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 20:11:30.103710 Total UI for P1: 0, mck2ui 16
2586 20:11:30.106983 best dqsien dly found for B1: ( 1, 4, 2)
2587 20:11:30.110161 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2588 20:11:30.113498 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2589 20:11:30.113581
2590 20:11:30.117523 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2591 20:11:30.120657 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2592 20:11:30.123780 [Gating] SW calibration Done
2593 20:11:30.123862 ==
2594 20:11:30.126755 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 20:11:30.130199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 20:11:30.130281 ==
2597 20:11:30.133696 RX Vref Scan: 0
2598 20:11:30.133778
2599 20:11:30.133841 RX Vref 0 -> 0, step: 1
2600 20:11:30.133901
2601 20:11:30.137003 RX Delay -40 -> 252, step: 8
2602 20:11:30.143492 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2603 20:11:30.146613 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2604 20:11:30.150221 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2605 20:11:30.153973 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2606 20:11:30.157068 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2607 20:11:30.160158 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2608 20:11:30.166913 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2609 20:11:30.170044 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2610 20:11:30.173173 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2611 20:11:30.176921 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2612 20:11:30.179963 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2613 20:11:30.186352 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2614 20:11:30.190302 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2615 20:11:30.193336 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2616 20:11:30.196600 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2617 20:11:30.202870 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2618 20:11:30.202953 ==
2619 20:11:30.206256 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 20:11:30.209525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 20:11:30.209608 ==
2622 20:11:30.209672 DQS Delay:
2623 20:11:30.212921 DQS0 = 0, DQS1 = 0
2624 20:11:30.213003 DQM Delay:
2625 20:11:30.216760 DQM0 = 119, DQM1 = 107
2626 20:11:30.216841 DQ Delay:
2627 20:11:30.219488 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2628 20:11:30.222873 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2629 20:11:30.226425 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2630 20:11:30.229680 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2631 20:11:30.229762
2632 20:11:30.229827
2633 20:11:30.232802 ==
2634 20:11:30.232884 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 20:11:30.239648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 20:11:30.239735 ==
2637 20:11:30.239799
2638 20:11:30.239858
2639 20:11:30.242974 TX Vref Scan disable
2640 20:11:30.243055 == TX Byte 0 ==
2641 20:11:30.246598 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2642 20:11:30.252760 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2643 20:11:30.252840 == TX Byte 1 ==
2644 20:11:30.256474 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2645 20:11:30.262541 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2646 20:11:30.262678 ==
2647 20:11:30.266204 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 20:11:30.270084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 20:11:30.270170 ==
2650 20:11:30.281948 TX Vref=22, minBit 4, minWin=25, winSum=421
2651 20:11:30.284753 TX Vref=24, minBit 1, minWin=25, winSum=425
2652 20:11:30.288037 TX Vref=26, minBit 1, minWin=26, winSum=431
2653 20:11:30.291617 TX Vref=28, minBit 1, minWin=26, winSum=429
2654 20:11:30.294837 TX Vref=30, minBit 1, minWin=26, winSum=435
2655 20:11:30.298129 TX Vref=32, minBit 5, minWin=26, winSum=430
2656 20:11:30.305082 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30
2657 20:11:30.305237
2658 20:11:30.308516 Final TX Range 1 Vref 30
2659 20:11:30.308597
2660 20:11:30.308660 ==
2661 20:11:30.311543 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 20:11:30.314383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 20:11:30.314465 ==
2664 20:11:30.318060
2665 20:11:30.318140
2666 20:11:30.318203 TX Vref Scan disable
2667 20:11:30.321042 == TX Byte 0 ==
2668 20:11:30.324773 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2669 20:11:30.331025 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2670 20:11:30.331106 == TX Byte 1 ==
2671 20:11:30.334728 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2672 20:11:30.341084 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2673 20:11:30.341166
2674 20:11:30.341232 [DATLAT]
2675 20:11:30.341293 Freq=1200, CH0 RK0
2676 20:11:30.341351
2677 20:11:30.344221 DATLAT Default: 0xd
2678 20:11:30.344303 0, 0xFFFF, sum = 0
2679 20:11:30.347862 1, 0xFFFF, sum = 0
2680 20:11:30.351070 2, 0xFFFF, sum = 0
2681 20:11:30.351153 3, 0xFFFF, sum = 0
2682 20:11:30.354629 4, 0xFFFF, sum = 0
2683 20:11:30.354713 5, 0xFFFF, sum = 0
2684 20:11:30.358039 6, 0xFFFF, sum = 0
2685 20:11:30.358122 7, 0xFFFF, sum = 0
2686 20:11:30.361016 8, 0xFFFF, sum = 0
2687 20:11:30.361099 9, 0xFFFF, sum = 0
2688 20:11:30.364654 10, 0xFFFF, sum = 0
2689 20:11:30.364738 11, 0xFFFF, sum = 0
2690 20:11:30.367430 12, 0x0, sum = 1
2691 20:11:30.367513 13, 0x0, sum = 2
2692 20:11:30.370760 14, 0x0, sum = 3
2693 20:11:30.370843 15, 0x0, sum = 4
2694 20:11:30.374204 best_step = 13
2695 20:11:30.374286
2696 20:11:30.374351 ==
2697 20:11:30.377863 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 20:11:30.381176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 20:11:30.381258 ==
2700 20:11:30.381323 RX Vref Scan: 1
2701 20:11:30.381383
2702 20:11:30.384515 Set Vref Range= 32 -> 127
2703 20:11:30.384622
2704 20:11:30.387466 RX Vref 32 -> 127, step: 1
2705 20:11:30.387548
2706 20:11:30.391107 RX Delay -21 -> 252, step: 4
2707 20:11:30.391180
2708 20:11:30.394423 Set Vref, RX VrefLevel [Byte0]: 32
2709 20:11:30.397626 [Byte1]: 32
2710 20:11:30.397697
2711 20:11:30.400716 Set Vref, RX VrefLevel [Byte0]: 33
2712 20:11:30.404338 [Byte1]: 33
2713 20:11:30.407832
2714 20:11:30.407909 Set Vref, RX VrefLevel [Byte0]: 34
2715 20:11:30.411390 [Byte1]: 34
2716 20:11:30.415457
2717 20:11:30.415529 Set Vref, RX VrefLevel [Byte0]: 35
2718 20:11:30.419036 [Byte1]: 35
2719 20:11:30.423725
2720 20:11:30.423807 Set Vref, RX VrefLevel [Byte0]: 36
2721 20:11:30.426930 [Byte1]: 36
2722 20:11:30.431359
2723 20:11:30.431440 Set Vref, RX VrefLevel [Byte0]: 37
2724 20:11:30.434935 [Byte1]: 37
2725 20:11:30.439393
2726 20:11:30.439475 Set Vref, RX VrefLevel [Byte0]: 38
2727 20:11:30.443038 [Byte1]: 38
2728 20:11:30.447471
2729 20:11:30.447553 Set Vref, RX VrefLevel [Byte0]: 39
2730 20:11:30.450623 [Byte1]: 39
2731 20:11:30.455215
2732 20:11:30.455296 Set Vref, RX VrefLevel [Byte0]: 40
2733 20:11:30.458820 [Byte1]: 40
2734 20:11:30.462949
2735 20:11:30.463030 Set Vref, RX VrefLevel [Byte0]: 41
2736 20:11:30.466231 [Byte1]: 41
2737 20:11:30.470838
2738 20:11:30.470923 Set Vref, RX VrefLevel [Byte0]: 42
2739 20:11:30.474317 [Byte1]: 42
2740 20:11:30.479941
2741 20:11:30.480022 Set Vref, RX VrefLevel [Byte0]: 43
2742 20:11:30.482327 [Byte1]: 43
2743 20:11:30.486863
2744 20:11:30.486944 Set Vref, RX VrefLevel [Byte0]: 44
2745 20:11:30.490533 [Byte1]: 44
2746 20:11:30.494986
2747 20:11:30.495068 Set Vref, RX VrefLevel [Byte0]: 45
2748 20:11:30.498257 [Byte1]: 45
2749 20:11:30.503230
2750 20:11:30.503311 Set Vref, RX VrefLevel [Byte0]: 46
2751 20:11:30.506415 [Byte1]: 46
2752 20:11:30.510576
2753 20:11:30.510657 Set Vref, RX VrefLevel [Byte0]: 47
2754 20:11:30.513679 [Byte1]: 47
2755 20:11:30.518659
2756 20:11:30.518740 Set Vref, RX VrefLevel [Byte0]: 48
2757 20:11:30.521988 [Byte1]: 48
2758 20:11:30.526671
2759 20:11:30.526752 Set Vref, RX VrefLevel [Byte0]: 49
2760 20:11:30.530064 [Byte1]: 49
2761 20:11:30.534695
2762 20:11:30.534776 Set Vref, RX VrefLevel [Byte0]: 50
2763 20:11:30.538000 [Byte1]: 50
2764 20:11:30.542324
2765 20:11:30.542405 Set Vref, RX VrefLevel [Byte0]: 51
2766 20:11:30.545899 [Byte1]: 51
2767 20:11:30.550398
2768 20:11:30.550517 Set Vref, RX VrefLevel [Byte0]: 52
2769 20:11:30.553672 [Byte1]: 52
2770 20:11:30.557989
2771 20:11:30.558070 Set Vref, RX VrefLevel [Byte0]: 53
2772 20:11:30.561425 [Byte1]: 53
2773 20:11:30.566520
2774 20:11:30.566627 Set Vref, RX VrefLevel [Byte0]: 54
2775 20:11:30.569196 [Byte1]: 54
2776 20:11:30.573897
2777 20:11:30.573979 Set Vref, RX VrefLevel [Byte0]: 55
2778 20:11:30.577728 [Byte1]: 55
2779 20:11:30.581907
2780 20:11:30.581988 Set Vref, RX VrefLevel [Byte0]: 56
2781 20:11:30.585266 [Byte1]: 56
2782 20:11:30.589974
2783 20:11:30.590056 Set Vref, RX VrefLevel [Byte0]: 57
2784 20:11:30.593410 [Byte1]: 57
2785 20:11:30.598032
2786 20:11:30.598140 Set Vref, RX VrefLevel [Byte0]: 58
2787 20:11:30.601311 [Byte1]: 58
2788 20:11:30.605726
2789 20:11:30.605808 Set Vref, RX VrefLevel [Byte0]: 59
2790 20:11:30.609137 [Byte1]: 59
2791 20:11:30.613681
2792 20:11:30.613763 Set Vref, RX VrefLevel [Byte0]: 60
2793 20:11:30.619886 [Byte1]: 60
2794 20:11:30.619969
2795 20:11:30.623657 Set Vref, RX VrefLevel [Byte0]: 61
2796 20:11:30.626993 [Byte1]: 61
2797 20:11:30.627074
2798 20:11:30.630293 Set Vref, RX VrefLevel [Byte0]: 62
2799 20:11:30.633641 [Byte1]: 62
2800 20:11:30.637799
2801 20:11:30.637880 Set Vref, RX VrefLevel [Byte0]: 63
2802 20:11:30.640882 [Byte1]: 63
2803 20:11:30.645940
2804 20:11:30.646022 Set Vref, RX VrefLevel [Byte0]: 64
2805 20:11:30.649040 [Byte1]: 64
2806 20:11:30.653718
2807 20:11:30.653799 Set Vref, RX VrefLevel [Byte0]: 65
2808 20:11:30.656899 [Byte1]: 65
2809 20:11:30.661690
2810 20:11:30.661771 Set Vref, RX VrefLevel [Byte0]: 66
2811 20:11:30.664403 [Byte1]: 66
2812 20:11:30.669170
2813 20:11:30.669251 Set Vref, RX VrefLevel [Byte0]: 67
2814 20:11:30.672239 [Byte1]: 67
2815 20:11:30.677008
2816 20:11:30.677089 Set Vref, RX VrefLevel [Byte0]: 68
2817 20:11:30.680406 [Byte1]: 68
2818 20:11:30.684821
2819 20:11:30.684902 Set Vref, RX VrefLevel [Byte0]: 69
2820 20:11:30.688472 [Byte1]: 69
2821 20:11:30.693515
2822 20:11:30.693596 Set Vref, RX VrefLevel [Byte0]: 70
2823 20:11:30.696238 [Byte1]: 70
2824 20:11:30.700907
2825 20:11:30.700988 Set Vref, RX VrefLevel [Byte0]: 71
2826 20:11:30.704727 [Byte1]: 71
2827 20:11:30.708980
2828 20:11:30.709062 Set Vref, RX VrefLevel [Byte0]: 72
2829 20:11:30.712216 [Byte1]: 72
2830 20:11:30.716924
2831 20:11:30.717006 Set Vref, RX VrefLevel [Byte0]: 73
2832 20:11:30.719901 [Byte1]: 73
2833 20:11:30.724574
2834 20:11:30.724656 Set Vref, RX VrefLevel [Byte0]: 74
2835 20:11:30.728268 [Byte1]: 74
2836 20:11:30.732771
2837 20:11:30.732852 Set Vref, RX VrefLevel [Byte0]: 75
2838 20:11:30.736006 [Byte1]: 75
2839 20:11:30.740617
2840 20:11:30.740698 Set Vref, RX VrefLevel [Byte0]: 76
2841 20:11:30.743818 [Byte1]: 76
2842 20:11:30.748200
2843 20:11:30.752055 Set Vref, RX VrefLevel [Byte0]: 77
2844 20:11:30.752137 [Byte1]: 77
2845 20:11:30.756370
2846 20:11:30.756451 Final RX Vref Byte 0 = 61 to rank0
2847 20:11:30.759954 Final RX Vref Byte 1 = 57 to rank0
2848 20:11:30.763391 Final RX Vref Byte 0 = 61 to rank1
2849 20:11:30.766525 Final RX Vref Byte 1 = 57 to rank1==
2850 20:11:30.769827 Dram Type= 6, Freq= 0, CH_0, rank 0
2851 20:11:30.776419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 20:11:30.776501 ==
2853 20:11:30.776566 DQS Delay:
2854 20:11:30.776626 DQS0 = 0, DQS1 = 0
2855 20:11:30.780207 DQM Delay:
2856 20:11:30.780289 DQM0 = 119, DQM1 = 108
2857 20:11:30.783124 DQ Delay:
2858 20:11:30.786975 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2859 20:11:30.789471 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2860 20:11:30.793211 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2861 20:11:30.796293 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =114
2862 20:11:30.796406
2863 20:11:30.796488
2864 20:11:30.802710 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2865 20:11:30.806357 CH0 RK0: MR19=403, MR18=10FC
2866 20:11:30.812621 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2867 20:11:30.812704
2868 20:11:30.816341 ----->DramcWriteLeveling(PI) begin...
2869 20:11:30.816425 ==
2870 20:11:30.819674 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 20:11:30.826085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 20:11:30.826168 ==
2873 20:11:30.829238 Write leveling (Byte 0): 33 => 33
2874 20:11:30.829321 Write leveling (Byte 1): 28 => 28
2875 20:11:30.832927 DramcWriteLeveling(PI) end<-----
2876 20:11:30.833008
2877 20:11:30.833074 ==
2878 20:11:30.835975 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 20:11:30.842632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 20:11:30.842715 ==
2881 20:11:30.845757 [Gating] SW mode calibration
2882 20:11:30.852545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2883 20:11:30.855707 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2884 20:11:30.862365 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
2885 20:11:30.865510 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2886 20:11:30.868678 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 20:11:30.875506 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 20:11:30.878785 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 20:11:30.882155 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 20:11:30.888859 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 20:11:30.892359 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2892 20:11:30.895194 1 0 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
2893 20:11:30.902476 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 20:11:30.905447 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 20:11:30.908723 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 20:11:30.915025 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 20:11:30.918773 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 20:11:30.921788 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 20:11:30.928239 1 0 28 | B1->B0 | 2525 3231 | 0 1 | (0 0) (0 0)
2900 20:11:30.931476 1 1 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
2901 20:11:30.934915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 20:11:30.941622 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 20:11:30.944796 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 20:11:30.948422 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 20:11:30.954682 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 20:11:30.957970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 20:11:30.961246 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2908 20:11:30.967851 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2909 20:11:30.971529 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 20:11:30.974346 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 20:11:30.981523 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 20:11:30.984517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 20:11:30.987864 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 20:11:30.994313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 20:11:30.997876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 20:11:31.001038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 20:11:31.007849 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 20:11:31.010887 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 20:11:31.014224 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 20:11:31.020980 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 20:11:31.024311 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 20:11:31.027575 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 20:11:31.034014 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 20:11:31.037573 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2925 20:11:31.040804 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 20:11:31.043972 Total UI for P1: 0, mck2ui 16
2927 20:11:31.047779 best dqsien dly found for B0: ( 1, 3, 30)
2928 20:11:31.051429 Total UI for P1: 0, mck2ui 16
2929 20:11:31.053745 best dqsien dly found for B1: ( 1, 4, 0)
2930 20:11:31.057611 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2931 20:11:31.060703 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2932 20:11:31.060786
2933 20:11:31.064379 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2934 20:11:31.070687 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2935 20:11:31.070773 [Gating] SW calibration Done
2936 20:11:31.070869 ==
2937 20:11:31.074026 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 20:11:31.080230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 20:11:31.080313 ==
2940 20:11:31.080378 RX Vref Scan: 0
2941 20:11:31.080438
2942 20:11:31.083608 RX Vref 0 -> 0, step: 1
2943 20:11:31.083745
2944 20:11:31.086896 RX Delay -40 -> 252, step: 8
2945 20:11:31.090261 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2946 20:11:31.093454 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2947 20:11:31.096852 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2948 20:11:31.103435 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2949 20:11:31.106875 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2950 20:11:31.110978 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2951 20:11:31.113689 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2952 20:11:31.117651 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2953 20:11:31.123446 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2954 20:11:31.126723 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2955 20:11:31.130399 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2956 20:11:31.133472 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2957 20:11:31.136843 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2958 20:11:31.143858 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2959 20:11:31.146865 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2960 20:11:31.149812 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2961 20:11:31.149894 ==
2962 20:11:31.153460 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 20:11:31.156776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 20:11:31.156858 ==
2965 20:11:31.159827 DQS Delay:
2966 20:11:31.159909 DQS0 = 0, DQS1 = 0
2967 20:11:31.163066 DQM Delay:
2968 20:11:31.163147 DQM0 = 117, DQM1 = 108
2969 20:11:31.163212 DQ Delay:
2970 20:11:31.169871 DQ0 =115, DQ1 =123, DQ2 =111, DQ3 =115
2971 20:11:31.173705 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2972 20:11:31.176187 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2973 20:11:31.179886 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2974 20:11:31.180002
2975 20:11:31.180070
2976 20:11:31.180131 ==
2977 20:11:31.183202 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 20:11:31.186294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 20:11:31.186377 ==
2980 20:11:31.186442
2981 20:11:31.186501
2982 20:11:31.189510 TX Vref Scan disable
2983 20:11:31.192870 == TX Byte 0 ==
2984 20:11:31.196527 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2985 20:11:31.199981 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2986 20:11:31.202869 == TX Byte 1 ==
2987 20:11:31.206160 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2988 20:11:31.209512 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2989 20:11:31.209594 ==
2990 20:11:31.213103 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 20:11:31.216521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 20:11:31.219586 ==
2993 20:11:31.229825 TX Vref=22, minBit 1, minWin=25, winSum=420
2994 20:11:31.233490 TX Vref=24, minBit 0, minWin=26, winSum=426
2995 20:11:31.237169 TX Vref=26, minBit 12, minWin=26, winSum=430
2996 20:11:31.240002 TX Vref=28, minBit 1, minWin=26, winSum=432
2997 20:11:31.243189 TX Vref=30, minBit 12, minWin=26, winSum=436
2998 20:11:31.249844 TX Vref=32, minBit 10, minWin=26, winSum=431
2999 20:11:31.253571 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 30
3000 20:11:31.253654
3001 20:11:31.256534 Final TX Range 1 Vref 30
3002 20:11:31.256616
3003 20:11:31.256681 ==
3004 20:11:31.259847 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 20:11:31.263186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 20:11:31.266835 ==
3007 20:11:31.266917
3008 20:11:31.266996
3009 20:11:31.267069 TX Vref Scan disable
3010 20:11:31.270553 == TX Byte 0 ==
3011 20:11:31.273563 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3012 20:11:31.279650 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3013 20:11:31.279793 == TX Byte 1 ==
3014 20:11:31.283312 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3015 20:11:31.289882 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3016 20:11:31.289964
3017 20:11:31.290029 [DATLAT]
3018 20:11:31.290089 Freq=1200, CH0 RK1
3019 20:11:31.290148
3020 20:11:31.293107 DATLAT Default: 0xd
3021 20:11:31.296312 0, 0xFFFF, sum = 0
3022 20:11:31.296396 1, 0xFFFF, sum = 0
3023 20:11:31.299712 2, 0xFFFF, sum = 0
3024 20:11:31.299818 3, 0xFFFF, sum = 0
3025 20:11:31.302751 4, 0xFFFF, sum = 0
3026 20:11:31.302837 5, 0xFFFF, sum = 0
3027 20:11:31.306522 6, 0xFFFF, sum = 0
3028 20:11:31.306632 7, 0xFFFF, sum = 0
3029 20:11:31.309341 8, 0xFFFF, sum = 0
3030 20:11:31.309415 9, 0xFFFF, sum = 0
3031 20:11:31.312776 10, 0xFFFF, sum = 0
3032 20:11:31.312848 11, 0xFFFF, sum = 0
3033 20:11:31.315960 12, 0x0, sum = 1
3034 20:11:31.316040 13, 0x0, sum = 2
3035 20:11:31.319497 14, 0x0, sum = 3
3036 20:11:31.319571 15, 0x0, sum = 4
3037 20:11:31.323341 best_step = 13
3038 20:11:31.323411
3039 20:11:31.323476 ==
3040 20:11:31.326153 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 20:11:31.329221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 20:11:31.329297 ==
3043 20:11:31.332639 RX Vref Scan: 0
3044 20:11:31.332710
3045 20:11:31.332775 RX Vref 0 -> 0, step: 1
3046 20:11:31.332833
3047 20:11:31.336333 RX Delay -21 -> 252, step: 4
3048 20:11:31.342566 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3049 20:11:31.345819 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3050 20:11:31.349493 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3051 20:11:31.352506 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3052 20:11:31.355888 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3053 20:11:31.362606 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3054 20:11:31.365991 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3055 20:11:31.369386 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3056 20:11:31.372475 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3057 20:11:31.376393 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3058 20:11:31.382464 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3059 20:11:31.385732 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3060 20:11:31.388817 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3061 20:11:31.392725 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3062 20:11:31.395613 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3063 20:11:31.402149 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3064 20:11:31.402231 ==
3065 20:11:31.405743 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 20:11:31.408851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 20:11:31.408957 ==
3068 20:11:31.409054 DQS Delay:
3069 20:11:31.412077 DQS0 = 0, DQS1 = 0
3070 20:11:31.412159 DQM Delay:
3071 20:11:31.416021 DQM0 = 116, DQM1 = 109
3072 20:11:31.416102 DQ Delay:
3073 20:11:31.418551 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3074 20:11:31.421839 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3075 20:11:31.425553 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =104
3076 20:11:31.432141 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3077 20:11:31.432249
3078 20:11:31.432346
3079 20:11:31.438708 [DQSOSCAuto] RK1, (LSB)MR18= 0xee9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3080 20:11:31.442264 CH0 RK1: MR19=403, MR18=EE9
3081 20:11:31.448104 CH0_RK1: MR19=0x403, MR18=0xEE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3082 20:11:31.451655 [RxdqsGatingPostProcess] freq 1200
3083 20:11:31.455339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3084 20:11:31.458096 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 20:11:31.461590 best DQS1 dly(2T, 0.5T) = (0, 12)
3086 20:11:31.464941 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 20:11:31.468028 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3088 20:11:31.471825 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 20:11:31.474577 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 20:11:31.478219 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 20:11:31.481257 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 20:11:31.485114 Pre-setting of DQS Precalculation
3093 20:11:31.488019 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3094 20:11:31.488102 ==
3095 20:11:31.491300 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 20:11:31.498127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 20:11:31.498234 ==
3098 20:11:31.501160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 20:11:31.507721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3100 20:11:31.516185 [CA 0] Center 37 (7~68) winsize 62
3101 20:11:31.519326 [CA 1] Center 38 (8~68) winsize 61
3102 20:11:31.522807 [CA 2] Center 34 (4~64) winsize 61
3103 20:11:31.526302 [CA 3] Center 33 (3~64) winsize 62
3104 20:11:31.529541 [CA 4] Center 34 (4~64) winsize 61
3105 20:11:31.532925 [CA 5] Center 33 (3~64) winsize 62
3106 20:11:31.533007
3107 20:11:31.535979 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 20:11:31.536062
3109 20:11:31.539477 [CATrainingPosCal] consider 1 rank data
3110 20:11:31.542522 u2DelayCellTimex100 = 270/100 ps
3111 20:11:31.546140 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3112 20:11:31.552476 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3113 20:11:31.556007 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 20:11:31.559410 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3115 20:11:31.562609 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 20:11:31.565800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3117 20:11:31.565882
3118 20:11:31.569269 CA PerBit enable=1, Macro0, CA PI delay=33
3119 20:11:31.569351
3120 20:11:31.573266 [CBTSetCACLKResult] CA Dly = 33
3121 20:11:31.575784 CS Dly: 6 (0~37)
3122 20:11:31.575866 ==
3123 20:11:31.579252 Dram Type= 6, Freq= 0, CH_1, rank 1
3124 20:11:31.582101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 20:11:31.582183 ==
3126 20:11:31.589301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3127 20:11:31.592546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3128 20:11:31.602514 [CA 0] Center 37 (8~67) winsize 60
3129 20:11:31.605537 [CA 1] Center 38 (7~69) winsize 63
3130 20:11:31.608820 [CA 2] Center 34 (4~65) winsize 62
3131 20:11:31.611767 [CA 3] Center 33 (3~64) winsize 62
3132 20:11:31.615411 [CA 4] Center 34 (4~64) winsize 61
3133 20:11:31.618249 [CA 5] Center 33 (3~64) winsize 62
3134 20:11:31.618331
3135 20:11:31.622157 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3136 20:11:31.622239
3137 20:11:31.625508 [CATrainingPosCal] consider 2 rank data
3138 20:11:31.628466 u2DelayCellTimex100 = 270/100 ps
3139 20:11:31.631696 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3140 20:11:31.635159 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3141 20:11:31.641788 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 20:11:31.645270 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3143 20:11:31.648609 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3144 20:11:31.651584 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3145 20:11:31.651723
3146 20:11:31.655089 CA PerBit enable=1, Macro0, CA PI delay=33
3147 20:11:31.655171
3148 20:11:31.658037 [CBTSetCACLKResult] CA Dly = 33
3149 20:11:31.658119 CS Dly: 7 (0~40)
3150 20:11:31.661430
3151 20:11:31.665033 ----->DramcWriteLeveling(PI) begin...
3152 20:11:31.665116 ==
3153 20:11:31.668015 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 20:11:31.671074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 20:11:31.671176 ==
3156 20:11:31.674925 Write leveling (Byte 0): 25 => 25
3157 20:11:31.678341 Write leveling (Byte 1): 27 => 27
3158 20:11:31.681248 DramcWriteLeveling(PI) end<-----
3159 20:11:31.681330
3160 20:11:31.681395 ==
3161 20:11:31.684674 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 20:11:31.687787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 20:11:31.687869 ==
3164 20:11:31.691381 [Gating] SW mode calibration
3165 20:11:31.697265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3166 20:11:31.703862 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3167 20:11:31.707304 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3168 20:11:31.710670 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 20:11:31.717464 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 20:11:31.720427 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 20:11:31.724097 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 20:11:31.730471 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 20:11:31.733750 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3174 20:11:31.737150 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
3175 20:11:31.743572 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 20:11:31.746938 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 20:11:31.750122 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 20:11:31.756743 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 20:11:31.760322 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 20:11:31.763325 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 20:11:31.770369 1 0 24 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (0 0)
3182 20:11:31.773300 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 20:11:31.777448 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 20:11:31.783872 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 20:11:31.786809 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 20:11:31.790068 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 20:11:31.796748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 20:11:31.799615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 20:11:31.803232 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3190 20:11:31.809904 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3191 20:11:31.813606 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 20:11:31.817131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 20:11:31.822982 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 20:11:31.826361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 20:11:31.829911 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 20:11:31.836485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 20:11:31.839663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 20:11:31.843048 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 20:11:31.850058 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 20:11:31.852899 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 20:11:31.856690 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 20:11:31.862849 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 20:11:31.866060 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 20:11:31.869829 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 20:11:31.876364 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3206 20:11:31.879602 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3207 20:11:31.882641 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 20:11:31.886255 Total UI for P1: 0, mck2ui 16
3209 20:11:31.889714 best dqsien dly found for B0: ( 1, 3, 26)
3210 20:11:31.893019 Total UI for P1: 0, mck2ui 16
3211 20:11:31.896028 best dqsien dly found for B1: ( 1, 3, 26)
3212 20:11:31.899703 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3213 20:11:31.902597 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3214 20:11:31.902679
3215 20:11:31.906015 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 20:11:31.913018 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3217 20:11:31.913101 [Gating] SW calibration Done
3218 20:11:31.913167 ==
3219 20:11:31.916499 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 20:11:31.922662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 20:11:31.922799 ==
3222 20:11:31.922930 RX Vref Scan: 0
3223 20:11:31.922993
3224 20:11:31.925786 RX Vref 0 -> 0, step: 1
3225 20:11:31.925868
3226 20:11:31.929442 RX Delay -40 -> 252, step: 8
3227 20:11:31.932331 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3228 20:11:31.935804 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3229 20:11:31.939601 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3230 20:11:31.945734 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3231 20:11:31.948991 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3232 20:11:31.952411 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3233 20:11:31.955824 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3234 20:11:31.959139 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3235 20:11:31.966274 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3236 20:11:31.968894 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3237 20:11:31.972206 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3238 20:11:31.975713 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3239 20:11:31.978848 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3240 20:11:31.985874 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3241 20:11:31.989216 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3242 20:11:31.992185 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3243 20:11:31.992268 ==
3244 20:11:31.995344 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 20:11:31.999017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 20:11:31.999099 ==
3247 20:11:32.002075 DQS Delay:
3248 20:11:32.002157 DQS0 = 0, DQS1 = 0
3249 20:11:32.005320 DQM Delay:
3250 20:11:32.005401 DQM0 = 118, DQM1 = 110
3251 20:11:32.008632 DQ Delay:
3252 20:11:32.012567 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3253 20:11:32.015435 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3254 20:11:32.018511 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3255 20:11:32.021842 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3256 20:11:32.021924
3257 20:11:32.021989
3258 20:11:32.022049 ==
3259 20:11:32.025108 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 20:11:32.028611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 20:11:32.028694 ==
3262 20:11:32.028759
3263 20:11:32.028819
3264 20:11:32.031997 TX Vref Scan disable
3265 20:11:32.035261 == TX Byte 0 ==
3266 20:11:32.038537 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3267 20:11:32.041838 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3268 20:11:32.045245 == TX Byte 1 ==
3269 20:11:32.048226 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3270 20:11:32.052112 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3271 20:11:32.052194 ==
3272 20:11:32.055217 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 20:11:32.061681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 20:11:32.061763 ==
3275 20:11:32.072031 TX Vref=22, minBit 8, minWin=25, winSum=418
3276 20:11:32.075515 TX Vref=24, minBit 9, minWin=25, winSum=426
3277 20:11:32.078324 TX Vref=26, minBit 10, minWin=25, winSum=430
3278 20:11:32.082499 TX Vref=28, minBit 8, minWin=26, winSum=434
3279 20:11:32.085395 TX Vref=30, minBit 9, minWin=26, winSum=435
3280 20:11:32.091928 TX Vref=32, minBit 7, minWin=26, winSum=430
3281 20:11:32.095636 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3282 20:11:32.095777
3283 20:11:32.098323 Final TX Range 1 Vref 30
3284 20:11:32.098405
3285 20:11:32.098470 ==
3286 20:11:32.102158 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 20:11:32.105348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 20:11:32.108643 ==
3289 20:11:32.108725
3290 20:11:32.108788
3291 20:11:32.108848 TX Vref Scan disable
3292 20:11:32.111501 == TX Byte 0 ==
3293 20:11:32.115367 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3294 20:11:32.121971 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3295 20:11:32.122053 == TX Byte 1 ==
3296 20:11:32.125376 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3297 20:11:32.131828 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3298 20:11:32.131909
3299 20:11:32.131973 [DATLAT]
3300 20:11:32.132034 Freq=1200, CH1 RK0
3301 20:11:32.132091
3302 20:11:32.135029 DATLAT Default: 0xd
3303 20:11:32.135110 0, 0xFFFF, sum = 0
3304 20:11:32.138407 1, 0xFFFF, sum = 0
3305 20:11:32.141371 2, 0xFFFF, sum = 0
3306 20:11:32.141453 3, 0xFFFF, sum = 0
3307 20:11:32.144859 4, 0xFFFF, sum = 0
3308 20:11:32.144940 5, 0xFFFF, sum = 0
3309 20:11:32.148547 6, 0xFFFF, sum = 0
3310 20:11:32.148650 7, 0xFFFF, sum = 0
3311 20:11:32.151486 8, 0xFFFF, sum = 0
3312 20:11:32.151571 9, 0xFFFF, sum = 0
3313 20:11:32.154779 10, 0xFFFF, sum = 0
3314 20:11:32.154857 11, 0xFFFF, sum = 0
3315 20:11:32.158653 12, 0x0, sum = 1
3316 20:11:32.158736 13, 0x0, sum = 2
3317 20:11:32.161596 14, 0x0, sum = 3
3318 20:11:32.161732 15, 0x0, sum = 4
3319 20:11:32.164892 best_step = 13
3320 20:11:32.164973
3321 20:11:32.165037 ==
3322 20:11:32.168191 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 20:11:32.171434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 20:11:32.171515 ==
3325 20:11:32.171580 RX Vref Scan: 1
3326 20:11:32.174396
3327 20:11:32.174477 Set Vref Range= 32 -> 127
3328 20:11:32.174542
3329 20:11:32.177756 RX Vref 32 -> 127, step: 1
3330 20:11:32.177859
3331 20:11:32.181031 RX Delay -21 -> 252, step: 4
3332 20:11:32.181112
3333 20:11:32.184715 Set Vref, RX VrefLevel [Byte0]: 32
3334 20:11:32.187536 [Byte1]: 32
3335 20:11:32.187618
3336 20:11:32.190944 Set Vref, RX VrefLevel [Byte0]: 33
3337 20:11:32.194269 [Byte1]: 33
3338 20:11:32.198539
3339 20:11:32.198620 Set Vref, RX VrefLevel [Byte0]: 34
3340 20:11:32.204536 [Byte1]: 34
3341 20:11:32.204631
3342 20:11:32.208052 Set Vref, RX VrefLevel [Byte0]: 35
3343 20:11:32.211268 [Byte1]: 35
3344 20:11:32.211349
3345 20:11:32.214409 Set Vref, RX VrefLevel [Byte0]: 36
3346 20:11:32.217531 [Byte1]: 36
3347 20:11:32.221802
3348 20:11:32.221883 Set Vref, RX VrefLevel [Byte0]: 37
3349 20:11:32.225228 [Byte1]: 37
3350 20:11:32.229734
3351 20:11:32.229815 Set Vref, RX VrefLevel [Byte0]: 38
3352 20:11:32.233301 [Byte1]: 38
3353 20:11:32.237779
3354 20:11:32.237860 Set Vref, RX VrefLevel [Byte0]: 39
3355 20:11:32.241590 [Byte1]: 39
3356 20:11:32.245519
3357 20:11:32.245604 Set Vref, RX VrefLevel [Byte0]: 40
3358 20:11:32.249311 [Byte1]: 40
3359 20:11:32.253791
3360 20:11:32.253872 Set Vref, RX VrefLevel [Byte0]: 41
3361 20:11:32.257243 [Byte1]: 41
3362 20:11:32.261585
3363 20:11:32.261666 Set Vref, RX VrefLevel [Byte0]: 42
3364 20:11:32.265187 [Byte1]: 42
3365 20:11:32.269287
3366 20:11:32.269368 Set Vref, RX VrefLevel [Byte0]: 43
3367 20:11:32.272807 [Byte1]: 43
3368 20:11:32.277672
3369 20:11:32.277754 Set Vref, RX VrefLevel [Byte0]: 44
3370 20:11:32.281085 [Byte1]: 44
3371 20:11:32.285237
3372 20:11:32.285319 Set Vref, RX VrefLevel [Byte0]: 45
3373 20:11:32.288779 [Byte1]: 45
3374 20:11:32.293070
3375 20:11:32.293153 Set Vref, RX VrefLevel [Byte0]: 46
3376 20:11:32.296507 [Byte1]: 46
3377 20:11:32.301292
3378 20:11:32.301385 Set Vref, RX VrefLevel [Byte0]: 47
3379 20:11:32.304541 [Byte1]: 47
3380 20:11:32.309046
3381 20:11:32.309157 Set Vref, RX VrefLevel [Byte0]: 48
3382 20:11:32.312336 [Byte1]: 48
3383 20:11:32.317540
3384 20:11:32.317621 Set Vref, RX VrefLevel [Byte0]: 49
3385 20:11:32.320419 [Byte1]: 49
3386 20:11:32.325239
3387 20:11:32.325321 Set Vref, RX VrefLevel [Byte0]: 50
3388 20:11:32.328366 [Byte1]: 50
3389 20:11:32.332611
3390 20:11:32.332719 Set Vref, RX VrefLevel [Byte0]: 51
3391 20:11:32.335778 [Byte1]: 51
3392 20:11:32.340556
3393 20:11:32.340639 Set Vref, RX VrefLevel [Byte0]: 52
3394 20:11:32.344623 [Byte1]: 52
3395 20:11:32.348449
3396 20:11:32.348556 Set Vref, RX VrefLevel [Byte0]: 53
3397 20:11:32.351632 [Byte1]: 53
3398 20:11:32.357410
3399 20:11:32.357491 Set Vref, RX VrefLevel [Byte0]: 54
3400 20:11:32.359716 [Byte1]: 54
3401 20:11:32.364489
3402 20:11:32.364570 Set Vref, RX VrefLevel [Byte0]: 55
3403 20:11:32.368230 [Byte1]: 55
3404 20:11:32.372180
3405 20:11:32.372270 Set Vref, RX VrefLevel [Byte0]: 56
3406 20:11:32.375431 [Byte1]: 56
3407 20:11:32.380058
3408 20:11:32.380140 Set Vref, RX VrefLevel [Byte0]: 57
3409 20:11:32.383701 [Byte1]: 57
3410 20:11:32.388349
3411 20:11:32.388432 Set Vref, RX VrefLevel [Byte0]: 58
3412 20:11:32.391378 [Byte1]: 58
3413 20:11:32.396615
3414 20:11:32.396697 Set Vref, RX VrefLevel [Byte0]: 59
3415 20:11:32.402572 [Byte1]: 59
3416 20:11:32.402653
3417 20:11:32.405768 Set Vref, RX VrefLevel [Byte0]: 60
3418 20:11:32.409219 [Byte1]: 60
3419 20:11:32.409301
3420 20:11:32.412646 Set Vref, RX VrefLevel [Byte0]: 61
3421 20:11:32.415653 [Byte1]: 61
3422 20:11:32.420002
3423 20:11:32.420083 Set Vref, RX VrefLevel [Byte0]: 62
3424 20:11:32.423276 [Byte1]: 62
3425 20:11:32.427865
3426 20:11:32.427946 Set Vref, RX VrefLevel [Byte0]: 63
3427 20:11:32.431142 [Byte1]: 63
3428 20:11:32.436111
3429 20:11:32.436193 Set Vref, RX VrefLevel [Byte0]: 64
3430 20:11:32.438814 [Byte1]: 64
3431 20:11:32.443412
3432 20:11:32.443493 Set Vref, RX VrefLevel [Byte0]: 65
3433 20:11:32.447143 [Byte1]: 65
3434 20:11:32.451340
3435 20:11:32.451422 Set Vref, RX VrefLevel [Byte0]: 66
3436 20:11:32.455569 [Byte1]: 66
3437 20:11:32.459447
3438 20:11:32.459529 Set Vref, RX VrefLevel [Byte0]: 67
3439 20:11:32.463012 [Byte1]: 67
3440 20:11:32.467323
3441 20:11:32.467405 Set Vref, RX VrefLevel [Byte0]: 68
3442 20:11:32.470618 [Byte1]: 68
3443 20:11:32.475289
3444 20:11:32.475371 Final RX Vref Byte 0 = 49 to rank0
3445 20:11:32.478683 Final RX Vref Byte 1 = 53 to rank0
3446 20:11:32.481940 Final RX Vref Byte 0 = 49 to rank1
3447 20:11:32.485506 Final RX Vref Byte 1 = 53 to rank1==
3448 20:11:32.488231 Dram Type= 6, Freq= 0, CH_1, rank 0
3449 20:11:32.495329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 20:11:32.495412 ==
3451 20:11:32.495477 DQS Delay:
3452 20:11:32.498701 DQS0 = 0, DQS1 = 0
3453 20:11:32.498783 DQM Delay:
3454 20:11:32.498847 DQM0 = 115, DQM1 = 110
3455 20:11:32.502138 DQ Delay:
3456 20:11:32.504963 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3457 20:11:32.508324 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3458 20:11:32.511625 DQ8 =98, DQ9 =104, DQ10 =112, DQ11 =100
3459 20:11:32.514580 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3460 20:11:32.514662
3461 20:11:32.514727
3462 20:11:32.524807 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3463 20:11:32.524890 CH1 RK0: MR19=403, MR18=1F4
3464 20:11:32.531343 CH1_RK0: MR19=0x403, MR18=0x1F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3465 20:11:32.531432
3466 20:11:32.534370 ----->DramcWriteLeveling(PI) begin...
3467 20:11:32.534453 ==
3468 20:11:32.537976 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 20:11:32.544468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 20:11:32.544550 ==
3471 20:11:32.548119 Write leveling (Byte 0): 25 => 25
3472 20:11:32.550944 Write leveling (Byte 1): 28 => 28
3473 20:11:32.551026 DramcWriteLeveling(PI) end<-----
3474 20:11:32.551142
3475 20:11:32.554277 ==
3476 20:11:32.557782 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 20:11:32.561001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 20:11:32.561084 ==
3479 20:11:32.563898 [Gating] SW mode calibration
3480 20:11:32.570746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3481 20:11:32.573769 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3482 20:11:32.580917 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3483 20:11:32.583713 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 20:11:32.586895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 20:11:32.593603 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 20:11:32.596618 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 20:11:32.600567 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 20:11:32.606657 0 15 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
3489 20:11:32.610080 0 15 28 | B1->B0 | 2424 2a2a | 0 1 | (1 0) (1 0)
3490 20:11:32.614020 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 20:11:32.620627 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 20:11:32.623274 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 20:11:32.626810 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 20:11:32.633115 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 20:11:32.636876 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3496 20:11:32.639703 1 0 24 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
3497 20:11:32.647074 1 0 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
3498 20:11:32.649787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 20:11:32.653290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 20:11:32.659593 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 20:11:32.663037 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 20:11:32.666162 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 20:11:32.673434 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 20:11:32.676555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3505 20:11:32.679832 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3506 20:11:32.685857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 20:11:32.689275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 20:11:32.692385 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 20:11:32.699411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 20:11:32.702082 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 20:11:32.708943 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 20:11:32.712046 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 20:11:32.715428 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 20:11:32.722531 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 20:11:32.725573 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 20:11:32.728417 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 20:11:32.734911 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 20:11:32.738142 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 20:11:32.741474 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 20:11:32.748034 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3521 20:11:32.751584 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3522 20:11:32.755136 Total UI for P1: 0, mck2ui 16
3523 20:11:32.758238 best dqsien dly found for B1: ( 1, 3, 24)
3524 20:11:32.761574 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3525 20:11:32.767972 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 20:11:32.768048 Total UI for P1: 0, mck2ui 16
3527 20:11:32.771322 best dqsien dly found for B0: ( 1, 3, 28)
3528 20:11:32.778155 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3529 20:11:32.781351 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3530 20:11:32.781425
3531 20:11:32.784732 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3532 20:11:32.787869 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3533 20:11:32.791786 [Gating] SW calibration Done
3534 20:11:32.791859 ==
3535 20:11:32.794594 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 20:11:32.798120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 20:11:32.798203 ==
3538 20:11:32.801138 RX Vref Scan: 0
3539 20:11:32.801207
3540 20:11:32.801268 RX Vref 0 -> 0, step: 1
3541 20:11:32.801326
3542 20:11:32.804760 RX Delay -40 -> 252, step: 8
3543 20:11:32.807520 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3544 20:11:32.814326 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3545 20:11:32.817302 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3546 20:11:32.820604 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3547 20:11:32.824399 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3548 20:11:32.827582 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3549 20:11:32.834308 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3550 20:11:32.837164 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3551 20:11:32.840997 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3552 20:11:32.844014 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3553 20:11:32.847333 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3554 20:11:32.853953 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3555 20:11:32.856889 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3556 20:11:32.860358 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3557 20:11:32.863526 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3558 20:11:32.870414 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3559 20:11:32.870487 ==
3560 20:11:32.873764 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 20:11:32.876793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 20:11:32.876862 ==
3563 20:11:32.876924 DQS Delay:
3564 20:11:32.880032 DQS0 = 0, DQS1 = 0
3565 20:11:32.880102 DQM Delay:
3566 20:11:32.883189 DQM0 = 116, DQM1 = 110
3567 20:11:32.883263 DQ Delay:
3568 20:11:32.886441 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3569 20:11:32.889795 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3570 20:11:32.892947 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3571 20:11:32.896875 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3572 20:11:32.896944
3573 20:11:32.900107
3574 20:11:32.900175 ==
3575 20:11:32.904236 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 20:11:32.906798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 20:11:32.906871 ==
3578 20:11:32.906933
3579 20:11:32.906991
3580 20:11:32.909458 TX Vref Scan disable
3581 20:11:32.909530 == TX Byte 0 ==
3582 20:11:32.916025 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 20:11:32.919704 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 20:11:32.919788 == TX Byte 1 ==
3585 20:11:32.926340 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 20:11:32.929426 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 20:11:32.929493 ==
3588 20:11:32.932990 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 20:11:32.936511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 20:11:32.936584 ==
3591 20:11:32.948143 TX Vref=22, minBit 8, minWin=25, winSum=421
3592 20:11:32.951830 TX Vref=24, minBit 3, minWin=26, winSum=427
3593 20:11:32.954871 TX Vref=26, minBit 8, minWin=26, winSum=431
3594 20:11:32.958116 TX Vref=28, minBit 8, minWin=26, winSum=431
3595 20:11:32.961700 TX Vref=30, minBit 8, minWin=26, winSum=434
3596 20:11:32.968050 TX Vref=32, minBit 8, minWin=26, winSum=430
3597 20:11:32.971469 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3598 20:11:32.971565
3599 20:11:32.975033 Final TX Range 1 Vref 30
3600 20:11:32.975107
3601 20:11:32.975168 ==
3602 20:11:32.977920 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 20:11:32.981443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 20:11:32.984519 ==
3605 20:11:32.984588
3606 20:11:32.984654
3607 20:11:32.984711 TX Vref Scan disable
3608 20:11:32.988437 == TX Byte 0 ==
3609 20:11:32.991527 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 20:11:32.998666 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 20:11:32.998742 == TX Byte 1 ==
3612 20:11:33.001462 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 20:11:33.007923 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 20:11:33.007997
3615 20:11:33.008059 [DATLAT]
3616 20:11:33.008125 Freq=1200, CH1 RK1
3617 20:11:33.008182
3618 20:11:33.011441 DATLAT Default: 0xd
3619 20:11:33.015313 0, 0xFFFF, sum = 0
3620 20:11:33.015386 1, 0xFFFF, sum = 0
3621 20:11:33.018734 2, 0xFFFF, sum = 0
3622 20:11:33.018813 3, 0xFFFF, sum = 0
3623 20:11:33.021516 4, 0xFFFF, sum = 0
3624 20:11:33.021586 5, 0xFFFF, sum = 0
3625 20:11:33.024758 6, 0xFFFF, sum = 0
3626 20:11:33.024832 7, 0xFFFF, sum = 0
3627 20:11:33.027659 8, 0xFFFF, sum = 0
3628 20:11:33.027769 9, 0xFFFF, sum = 0
3629 20:11:33.030970 10, 0xFFFF, sum = 0
3630 20:11:33.031039 11, 0xFFFF, sum = 0
3631 20:11:33.034245 12, 0x0, sum = 1
3632 20:11:33.034315 13, 0x0, sum = 2
3633 20:11:33.037572 14, 0x0, sum = 3
3634 20:11:33.037640 15, 0x0, sum = 4
3635 20:11:33.040684 best_step = 13
3636 20:11:33.040751
3637 20:11:33.040809 ==
3638 20:11:33.044321 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 20:11:33.047494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 20:11:33.047563 ==
3641 20:11:33.050459 RX Vref Scan: 0
3642 20:11:33.050538
3643 20:11:33.050599 RX Vref 0 -> 0, step: 1
3644 20:11:33.050657
3645 20:11:33.054039 RX Delay -21 -> 252, step: 4
3646 20:11:33.060378 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3647 20:11:33.063988 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3648 20:11:33.066992 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3649 20:11:33.070913 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3650 20:11:33.073437 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3651 20:11:33.080326 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3652 20:11:33.083369 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3653 20:11:33.086644 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3654 20:11:33.090396 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3655 20:11:33.096864 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3656 20:11:33.099734 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3657 20:11:33.103112 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3658 20:11:33.106687 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3659 20:11:33.110294 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3660 20:11:33.117103 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3661 20:11:33.119730 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3662 20:11:33.119800 ==
3663 20:11:33.122962 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 20:11:33.126515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 20:11:33.126587 ==
3666 20:11:33.129679 DQS Delay:
3667 20:11:33.129753 DQS0 = 0, DQS1 = 0
3668 20:11:33.129813 DQM Delay:
3669 20:11:33.133002 DQM0 = 116, DQM1 = 109
3670 20:11:33.133070 DQ Delay:
3671 20:11:33.136380 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3672 20:11:33.139544 DQ4 =114, DQ5 =126, DQ6 =128, DQ7 =116
3673 20:11:33.146203 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3674 20:11:33.149577 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3675 20:11:33.149648
3676 20:11:33.149709
3677 20:11:33.155752 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3678 20:11:33.159196 CH1 RK1: MR19=303, MR18=F5F0
3679 20:11:33.165941 CH1_RK1: MR19=0x303, MR18=0xF5F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3680 20:11:33.168914 [RxdqsGatingPostProcess] freq 1200
3681 20:11:33.176034 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 20:11:33.176109 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 20:11:33.179161 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 20:11:33.182824 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 20:11:33.185470 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 20:11:33.188858 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 20:11:33.192128 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 20:11:33.195620 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 20:11:33.198522 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 20:11:33.201903 Pre-setting of DQS Precalculation
3691 20:11:33.208910 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 20:11:33.215166 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 20:11:33.221615 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 20:11:33.221704
3695 20:11:33.221770
3696 20:11:33.225451 [Calibration Summary] 2400 Mbps
3697 20:11:33.225568 CH 0, Rank 0
3698 20:11:33.228535 SW Impedance : PASS
3699 20:11:33.232013 DUTY Scan : NO K
3700 20:11:33.232088 ZQ Calibration : PASS
3701 20:11:33.235138 Jitter Meter : NO K
3702 20:11:33.238713 CBT Training : PASS
3703 20:11:33.238789 Write leveling : PASS
3704 20:11:33.241878 RX DQS gating : PASS
3705 20:11:33.244866 RX DQ/DQS(RDDQC) : PASS
3706 20:11:33.245071 TX DQ/DQS : PASS
3707 20:11:33.248421 RX DATLAT : PASS
3708 20:11:33.251517 RX DQ/DQS(Engine): PASS
3709 20:11:33.251706 TX OE : NO K
3710 20:11:33.251799 All Pass.
3711 20:11:33.255584
3712 20:11:33.255655 CH 0, Rank 1
3713 20:11:33.258758 SW Impedance : PASS
3714 20:11:33.258832 DUTY Scan : NO K
3715 20:11:33.261236 ZQ Calibration : PASS
3716 20:11:33.261305 Jitter Meter : NO K
3717 20:11:33.264672 CBT Training : PASS
3718 20:11:33.268263 Write leveling : PASS
3719 20:11:33.268344 RX DQS gating : PASS
3720 20:11:33.271573 RX DQ/DQS(RDDQC) : PASS
3721 20:11:33.274536 TX DQ/DQS : PASS
3722 20:11:33.274616 RX DATLAT : PASS
3723 20:11:33.277724 RX DQ/DQS(Engine): PASS
3724 20:11:33.281016 TX OE : NO K
3725 20:11:33.281089 All Pass.
3726 20:11:33.281149
3727 20:11:33.281214 CH 1, Rank 0
3728 20:11:33.284969 SW Impedance : PASS
3729 20:11:33.287881 DUTY Scan : NO K
3730 20:11:33.287949 ZQ Calibration : PASS
3731 20:11:33.291050 Jitter Meter : NO K
3732 20:11:33.294105 CBT Training : PASS
3733 20:11:33.294179 Write leveling : PASS
3734 20:11:33.297736 RX DQS gating : PASS
3735 20:11:33.300656 RX DQ/DQS(RDDQC) : PASS
3736 20:11:33.300724 TX DQ/DQS : PASS
3737 20:11:33.304359 RX DATLAT : PASS
3738 20:11:33.307279 RX DQ/DQS(Engine): PASS
3739 20:11:33.307345 TX OE : NO K
3740 20:11:33.310825 All Pass.
3741 20:11:33.310902
3742 20:11:33.310962 CH 1, Rank 1
3743 20:11:33.314287 SW Impedance : PASS
3744 20:11:33.314360 DUTY Scan : NO K
3745 20:11:33.317424 ZQ Calibration : PASS
3746 20:11:33.320557 Jitter Meter : NO K
3747 20:11:33.320629 CBT Training : PASS
3748 20:11:33.323556 Write leveling : PASS
3749 20:11:33.327157 RX DQS gating : PASS
3750 20:11:33.327227 RX DQ/DQS(RDDQC) : PASS
3751 20:11:33.330092 TX DQ/DQS : PASS
3752 20:11:33.333641 RX DATLAT : PASS
3753 20:11:33.333711 RX DQ/DQS(Engine): PASS
3754 20:11:33.337164 TX OE : NO K
3755 20:11:33.337239 All Pass.
3756 20:11:33.337299
3757 20:11:33.340978 DramC Write-DBI off
3758 20:11:33.343823 PER_BANK_REFRESH: Hybrid Mode
3759 20:11:33.343891 TX_TRACKING: ON
3760 20:11:33.353767 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 20:11:33.356655 [FAST_K] Save calibration result to emmc
3762 20:11:33.360500 dramc_set_vcore_voltage set vcore to 650000
3763 20:11:33.363440 Read voltage for 600, 5
3764 20:11:33.363511 Vio18 = 0
3765 20:11:33.363573 Vcore = 650000
3766 20:11:33.366732 Vdram = 0
3767 20:11:33.366805 Vddq = 0
3768 20:11:33.366865 Vmddr = 0
3769 20:11:33.373231 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 20:11:33.376390 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 20:11:33.379642 MEM_TYPE=3, freq_sel=19
3772 20:11:33.382793 sv_algorithm_assistance_LP4_1600
3773 20:11:33.386449 ============ PULL DRAM RESETB DOWN ============
3774 20:11:33.392622 ========== PULL DRAM RESETB DOWN end =========
3775 20:11:33.396120 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 20:11:33.399534 ===================================
3777 20:11:33.402394 LPDDR4 DRAM CONFIGURATION
3778 20:11:33.406564 ===================================
3779 20:11:33.406632 EX_ROW_EN[0] = 0x0
3780 20:11:33.409294 EX_ROW_EN[1] = 0x0
3781 20:11:33.409361 LP4Y_EN = 0x0
3782 20:11:33.412723 WORK_FSP = 0x0
3783 20:11:33.412798 WL = 0x2
3784 20:11:33.416152 RL = 0x2
3785 20:11:33.416233 BL = 0x2
3786 20:11:33.419060 RPST = 0x0
3787 20:11:33.419136 RD_PRE = 0x0
3788 20:11:33.422619 WR_PRE = 0x1
3789 20:11:33.425890 WR_PST = 0x0
3790 20:11:33.425961 DBI_WR = 0x0
3791 20:11:33.429282 DBI_RD = 0x0
3792 20:11:33.429355 OTF = 0x1
3793 20:11:33.432794 ===================================
3794 20:11:33.435566 ===================================
3795 20:11:33.435635 ANA top config
3796 20:11:33.439554 ===================================
3797 20:11:33.443198 DLL_ASYNC_EN = 0
3798 20:11:33.445985 ALL_SLAVE_EN = 1
3799 20:11:33.449602 NEW_RANK_MODE = 1
3800 20:11:33.452301 DLL_IDLE_MODE = 1
3801 20:11:33.452377 LP45_APHY_COMB_EN = 1
3802 20:11:33.455503 TX_ODT_DIS = 1
3803 20:11:33.459071 NEW_8X_MODE = 1
3804 20:11:33.462052 ===================================
3805 20:11:33.465413 ===================================
3806 20:11:33.468920 data_rate = 1200
3807 20:11:33.472711 CKR = 1
3808 20:11:33.475431 DQ_P2S_RATIO = 8
3809 20:11:33.478705 ===================================
3810 20:11:33.478808 CA_P2S_RATIO = 8
3811 20:11:33.482421 DQ_CA_OPEN = 0
3812 20:11:33.485246 DQ_SEMI_OPEN = 0
3813 20:11:33.488681 CA_SEMI_OPEN = 0
3814 20:11:33.491943 CA_FULL_RATE = 0
3815 20:11:33.495505 DQ_CKDIV4_EN = 1
3816 20:11:33.495575 CA_CKDIV4_EN = 1
3817 20:11:33.498163 CA_PREDIV_EN = 0
3818 20:11:33.501650 PH8_DLY = 0
3819 20:11:33.504929 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 20:11:33.508202 DQ_AAMCK_DIV = 4
3821 20:11:33.511384 CA_AAMCK_DIV = 4
3822 20:11:33.511459 CA_ADMCK_DIV = 4
3823 20:11:33.514741 DQ_TRACK_CA_EN = 0
3824 20:11:33.518006 CA_PICK = 600
3825 20:11:33.521180 CA_MCKIO = 600
3826 20:11:33.524530 MCKIO_SEMI = 0
3827 20:11:33.528272 PLL_FREQ = 2288
3828 20:11:33.531632 DQ_UI_PI_RATIO = 32
3829 20:11:33.531759 CA_UI_PI_RATIO = 0
3830 20:11:33.534725 ===================================
3831 20:11:33.538108 ===================================
3832 20:11:33.541142 memory_type:LPDDR4
3833 20:11:33.544738 GP_NUM : 10
3834 20:11:33.544815 SRAM_EN : 1
3835 20:11:33.547700 MD32_EN : 0
3836 20:11:33.551203 ===================================
3837 20:11:33.554288 [ANA_INIT] >>>>>>>>>>>>>>
3838 20:11:33.558006 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 20:11:33.561129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 20:11:33.564590 ===================================
3841 20:11:33.567212 data_rate = 1200,PCW = 0X5800
3842 20:11:33.570884 ===================================
3843 20:11:33.573771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 20:11:33.577112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 20:11:33.583963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 20:11:33.587779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 20:11:33.590727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 20:11:33.594220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 20:11:33.597037 [ANA_INIT] flow start
3850 20:11:33.600465 [ANA_INIT] PLL >>>>>>>>
3851 20:11:33.600546 [ANA_INIT] PLL <<<<<<<<
3852 20:11:33.603600 [ANA_INIT] MIDPI >>>>>>>>
3853 20:11:33.607259 [ANA_INIT] MIDPI <<<<<<<<
3854 20:11:33.610121 [ANA_INIT] DLL >>>>>>>>
3855 20:11:33.610194 [ANA_INIT] flow end
3856 20:11:33.613692 ============ LP4 DIFF to SE enter ============
3857 20:11:33.619969 ============ LP4 DIFF to SE exit ============
3858 20:11:33.620050 [ANA_INIT] <<<<<<<<<<<<<
3859 20:11:33.623353 [Flow] Enable top DCM control >>>>>
3860 20:11:33.626601 [Flow] Enable top DCM control <<<<<
3861 20:11:33.630492 Enable DLL master slave shuffle
3862 20:11:33.636376 ==============================================================
3863 20:11:33.636465 Gating Mode config
3864 20:11:33.643199 ==============================================================
3865 20:11:33.647001 Config description:
3866 20:11:33.656375 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 20:11:33.662879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 20:11:33.666626 SELPH_MODE 0: By rank 1: By Phase
3869 20:11:33.672941 ==============================================================
3870 20:11:33.676586 GAT_TRACK_EN = 1
3871 20:11:33.679407 RX_GATING_MODE = 2
3872 20:11:33.679520 RX_GATING_TRACK_MODE = 2
3873 20:11:33.682622 SELPH_MODE = 1
3874 20:11:33.686819 PICG_EARLY_EN = 1
3875 20:11:33.689627 VALID_LAT_VALUE = 1
3876 20:11:33.695967 ==============================================================
3877 20:11:33.699247 Enter into Gating configuration >>>>
3878 20:11:33.702777 Exit from Gating configuration <<<<
3879 20:11:33.705894 Enter into DVFS_PRE_config >>>>>
3880 20:11:33.715882 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 20:11:33.719332 Exit from DVFS_PRE_config <<<<<
3882 20:11:33.722388 Enter into PICG configuration >>>>
3883 20:11:33.726069 Exit from PICG configuration <<<<
3884 20:11:33.729313 [RX_INPUT] configuration >>>>>
3885 20:11:33.732931 [RX_INPUT] configuration <<<<<
3886 20:11:33.735710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 20:11:33.742281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 20:11:33.748904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 20:11:33.755249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 20:11:33.762443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 20:11:33.765776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 20:11:33.771946 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 20:11:33.775481 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 20:11:33.778489 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 20:11:33.781815 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 20:11:33.788822 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 20:11:33.791609 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 20:11:33.795218 ===================================
3899 20:11:33.797892 LPDDR4 DRAM CONFIGURATION
3900 20:11:33.801599 ===================================
3901 20:11:33.801682 EX_ROW_EN[0] = 0x0
3902 20:11:33.804876 EX_ROW_EN[1] = 0x0
3903 20:11:33.804958 LP4Y_EN = 0x0
3904 20:11:33.808365 WORK_FSP = 0x0
3905 20:11:33.808447 WL = 0x2
3906 20:11:33.811924 RL = 0x2
3907 20:11:33.814446 BL = 0x2
3908 20:11:33.814555 RPST = 0x0
3909 20:11:33.817813 RD_PRE = 0x0
3910 20:11:33.817900 WR_PRE = 0x1
3911 20:11:33.821469 WR_PST = 0x0
3912 20:11:33.821563 DBI_WR = 0x0
3913 20:11:33.824727 DBI_RD = 0x0
3914 20:11:33.824803 OTF = 0x1
3915 20:11:33.828106 ===================================
3916 20:11:33.831116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 20:11:33.838000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 20:11:33.840939 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 20:11:33.844041 ===================================
3920 20:11:33.847361 LPDDR4 DRAM CONFIGURATION
3921 20:11:33.850666 ===================================
3922 20:11:33.850751 EX_ROW_EN[0] = 0x10
3923 20:11:33.854418 EX_ROW_EN[1] = 0x0
3924 20:11:33.857166 LP4Y_EN = 0x0
3925 20:11:33.857268 WORK_FSP = 0x0
3926 20:11:33.860748 WL = 0x2
3927 20:11:33.860849 RL = 0x2
3928 20:11:33.863875 BL = 0x2
3929 20:11:33.863985 RPST = 0x0
3930 20:11:33.867074 RD_PRE = 0x0
3931 20:11:33.867173 WR_PRE = 0x1
3932 20:11:33.870457 WR_PST = 0x0
3933 20:11:33.870570 DBI_WR = 0x0
3934 20:11:33.873908 DBI_RD = 0x0
3935 20:11:33.873993 OTF = 0x1
3936 20:11:33.877271 ===================================
3937 20:11:33.883831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 20:11:33.888286 nWR fixed to 30
3939 20:11:33.891174 [ModeRegInit_LP4] CH0 RK0
3940 20:11:33.891269 [ModeRegInit_LP4] CH0 RK1
3941 20:11:33.894590 [ModeRegInit_LP4] CH1 RK0
3942 20:11:33.898072 [ModeRegInit_LP4] CH1 RK1
3943 20:11:33.898155 match AC timing 17
3944 20:11:33.904792 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 20:11:33.908130 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 20:11:33.911012 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 20:11:33.917925 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 20:11:33.920795 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 20:11:33.920894 ==
3950 20:11:33.924277 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 20:11:33.927499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 20:11:33.927598 ==
3953 20:11:33.933907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 20:11:33.940838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3955 20:11:33.944273 [CA 0] Center 36 (6~66) winsize 61
3956 20:11:33.947333 [CA 1] Center 36 (6~66) winsize 61
3957 20:11:33.951131 [CA 2] Center 34 (4~65) winsize 62
3958 20:11:33.953891 [CA 3] Center 34 (3~65) winsize 63
3959 20:11:33.957437 [CA 4] Center 33 (3~64) winsize 62
3960 20:11:33.960506 [CA 5] Center 33 (3~64) winsize 62
3961 20:11:33.960605
3962 20:11:33.963781 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3963 20:11:33.963865
3964 20:11:33.967394 [CATrainingPosCal] consider 1 rank data
3965 20:11:33.970473 u2DelayCellTimex100 = 270/100 ps
3966 20:11:33.973845 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 20:11:33.976870 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 20:11:33.980154 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 20:11:33.986943 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3970 20:11:33.990312 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 20:11:33.993757 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 20:11:33.993850
3973 20:11:33.996772 CA PerBit enable=1, Macro0, CA PI delay=33
3974 20:11:33.996856
3975 20:11:34.000315 [CBTSetCACLKResult] CA Dly = 33
3976 20:11:34.000399 CS Dly: 5 (0~36)
3977 20:11:34.000466 ==
3978 20:11:34.003252 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 20:11:34.010202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 20:11:34.010310 ==
3981 20:11:34.013214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 20:11:34.020121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3983 20:11:34.023609 [CA 0] Center 35 (5~66) winsize 62
3984 20:11:34.026883 [CA 1] Center 36 (6~66) winsize 61
3985 20:11:34.029845 [CA 2] Center 34 (4~64) winsize 61
3986 20:11:34.033737 [CA 3] Center 33 (3~64) winsize 62
3987 20:11:34.036952 [CA 4] Center 33 (2~64) winsize 63
3988 20:11:34.039948 [CA 5] Center 33 (2~64) winsize 63
3989 20:11:34.040048
3990 20:11:34.043238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3991 20:11:34.043352
3992 20:11:34.046765 [CATrainingPosCal] consider 2 rank data
3993 20:11:34.049953 u2DelayCellTimex100 = 270/100 ps
3994 20:11:34.053176 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3995 20:11:34.060018 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 20:11:34.063265 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3997 20:11:34.066922 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 20:11:34.070012 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 20:11:34.073339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 20:11:34.073432
4001 20:11:34.076217 CA PerBit enable=1, Macro0, CA PI delay=33
4002 20:11:34.076302
4003 20:11:34.079921 [CBTSetCACLKResult] CA Dly = 33
4004 20:11:34.083340 CS Dly: 5 (0~36)
4005 20:11:34.083423
4006 20:11:34.086106 ----->DramcWriteLeveling(PI) begin...
4007 20:11:34.086190 ==
4008 20:11:34.089349 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 20:11:34.093149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 20:11:34.093249 ==
4011 20:11:34.096386 Write leveling (Byte 0): 32 => 32
4012 20:11:34.099277 Write leveling (Byte 1): 31 => 31
4013 20:11:34.102513 DramcWriteLeveling(PI) end<-----
4014 20:11:34.102595
4015 20:11:34.102660 ==
4016 20:11:34.106014 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 20:11:34.109129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 20:11:34.109212 ==
4019 20:11:34.112333 [Gating] SW mode calibration
4020 20:11:34.119158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 20:11:34.125962 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 20:11:34.128893 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 20:11:34.132702 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 20:11:34.139056 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 20:11:34.142284 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4026 20:11:34.145382 0 9 16 | B1->B0 | 2f2f 2323 | 0 1 | (0 0) (1 0)
4027 20:11:34.151993 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 20:11:34.155706 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 20:11:34.158813 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 20:11:34.165467 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 20:11:34.168907 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 20:11:34.172039 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 20:11:34.178579 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4034 20:11:34.181847 0 10 16 | B1->B0 | 3535 4040 | 1 1 | (0 0) (0 0)
4035 20:11:34.185525 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 20:11:34.191804 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 20:11:34.195295 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 20:11:34.198459 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 20:11:34.205149 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 20:11:34.208163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 20:11:34.211526 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 20:11:34.217985 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 20:11:34.221350 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 20:11:34.225122 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 20:11:34.231546 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 20:11:34.235295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 20:11:34.238005 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 20:11:34.245167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 20:11:34.248155 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 20:11:34.251413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 20:11:34.257614 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 20:11:34.261173 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 20:11:34.264325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 20:11:34.271364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 20:11:34.274408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 20:11:34.277786 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 20:11:34.283846 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4058 20:11:34.287854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4059 20:11:34.290748 Total UI for P1: 0, mck2ui 16
4060 20:11:34.293681 best dqsien dly found for B0: ( 0, 13, 14)
4061 20:11:34.297360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 20:11:34.300790 Total UI for P1: 0, mck2ui 16
4063 20:11:34.303808 best dqsien dly found for B1: ( 0, 13, 14)
4064 20:11:34.307352 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 20:11:34.310351 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4066 20:11:34.313777
4067 20:11:34.316674 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 20:11:34.320246 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 20:11:34.323374 [Gating] SW calibration Done
4070 20:11:34.323456 ==
4071 20:11:34.326587 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 20:11:34.330579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 20:11:34.330663 ==
4074 20:11:34.333321 RX Vref Scan: 0
4075 20:11:34.333407
4076 20:11:34.333473 RX Vref 0 -> 0, step: 1
4077 20:11:34.333534
4078 20:11:34.336808 RX Delay -230 -> 252, step: 16
4079 20:11:34.339903 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 20:11:34.347120 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4081 20:11:34.349675 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4082 20:11:34.353260 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4083 20:11:34.356140 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4084 20:11:34.362811 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4085 20:11:34.366363 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4086 20:11:34.369562 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 20:11:34.373198 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4088 20:11:34.376145 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4089 20:11:34.382965 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 20:11:34.385846 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4091 20:11:34.389144 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4092 20:11:34.395801 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4093 20:11:34.399820 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4094 20:11:34.402578 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4095 20:11:34.402661 ==
4096 20:11:34.406335 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 20:11:34.409413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 20:11:34.409496 ==
4099 20:11:34.412674 DQS Delay:
4100 20:11:34.412756 DQS0 = 0, DQS1 = 0
4101 20:11:34.415892 DQM Delay:
4102 20:11:34.415975 DQM0 = 43, DQM1 = 32
4103 20:11:34.416041 DQ Delay:
4104 20:11:34.419616 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4105 20:11:34.422395 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49
4106 20:11:34.426307 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4107 20:11:34.429053 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4108 20:11:34.429151
4109 20:11:34.429230
4110 20:11:34.432662 ==
4111 20:11:34.432744 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 20:11:34.438922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 20:11:34.439005 ==
4114 20:11:34.439070
4115 20:11:34.439129
4116 20:11:34.442642 TX Vref Scan disable
4117 20:11:34.442724 == TX Byte 0 ==
4118 20:11:34.449166 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4119 20:11:34.452266 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4120 20:11:34.452348 == TX Byte 1 ==
4121 20:11:34.459239 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4122 20:11:34.461829 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4123 20:11:34.461911 ==
4124 20:11:34.465356 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 20:11:34.468898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 20:11:34.468984 ==
4127 20:11:34.469055
4128 20:11:34.469116
4129 20:11:34.472278 TX Vref Scan disable
4130 20:11:34.474994 == TX Byte 0 ==
4131 20:11:34.478229 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4132 20:11:34.481555 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4133 20:11:34.485199 == TX Byte 1 ==
4134 20:11:34.488627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4135 20:11:34.491494 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4136 20:11:34.491577
4137 20:11:34.494976 [DATLAT]
4138 20:11:34.495058 Freq=600, CH0 RK0
4139 20:11:34.495123
4140 20:11:34.498317 DATLAT Default: 0x9
4141 20:11:34.498399 0, 0xFFFF, sum = 0
4142 20:11:34.501715 1, 0xFFFF, sum = 0
4143 20:11:34.501799 2, 0xFFFF, sum = 0
4144 20:11:34.504493 3, 0xFFFF, sum = 0
4145 20:11:34.504577 4, 0xFFFF, sum = 0
4146 20:11:34.508133 5, 0xFFFF, sum = 0
4147 20:11:34.511794 6, 0xFFFF, sum = 0
4148 20:11:34.511877 7, 0xFFFF, sum = 0
4149 20:11:34.511943 8, 0x0, sum = 1
4150 20:11:34.514521 9, 0x0, sum = 2
4151 20:11:34.514605 10, 0x0, sum = 3
4152 20:11:34.518004 11, 0x0, sum = 4
4153 20:11:34.518086 best_step = 9
4154 20:11:34.518151
4155 20:11:34.518211 ==
4156 20:11:34.521744 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 20:11:34.527947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 20:11:34.528030 ==
4159 20:11:34.528095 RX Vref Scan: 1
4160 20:11:34.528156
4161 20:11:34.531304 RX Vref 0 -> 0, step: 1
4162 20:11:34.531386
4163 20:11:34.534885 RX Delay -179 -> 252, step: 8
4164 20:11:34.534968
4165 20:11:34.538146 Set Vref, RX VrefLevel [Byte0]: 61
4166 20:11:34.540862 [Byte1]: 57
4167 20:11:34.540944
4168 20:11:34.544830 Final RX Vref Byte 0 = 61 to rank0
4169 20:11:34.548124 Final RX Vref Byte 1 = 57 to rank0
4170 20:11:34.551313 Final RX Vref Byte 0 = 61 to rank1
4171 20:11:34.553947 Final RX Vref Byte 1 = 57 to rank1==
4172 20:11:34.557633 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 20:11:34.560961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 20:11:34.561043 ==
4175 20:11:34.564504 DQS Delay:
4176 20:11:34.564586 DQS0 = 0, DQS1 = 0
4177 20:11:34.567619 DQM Delay:
4178 20:11:34.567726 DQM0 = 43, DQM1 = 32
4179 20:11:34.567792 DQ Delay:
4180 20:11:34.570984 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4181 20:11:34.574435 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4182 20:11:34.577162 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4183 20:11:34.580554 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4184 20:11:34.580637
4185 20:11:34.580701
4186 20:11:34.590727 [DQSOSCAuto] RK0, (LSB)MR18= 0x653c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4187 20:11:34.593797 CH0 RK0: MR19=808, MR18=653C
4188 20:11:34.600455 CH0_RK0: MR19=0x808, MR18=0x653C, DQSOSC=390, MR23=63, INC=172, DEC=114
4189 20:11:34.600538
4190 20:11:34.603880 ----->DramcWriteLeveling(PI) begin...
4191 20:11:34.603963 ==
4192 20:11:34.606834 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 20:11:34.610040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 20:11:34.610123 ==
4195 20:11:34.613187 Write leveling (Byte 0): 33 => 33
4196 20:11:34.616987 Write leveling (Byte 1): 33 => 33
4197 20:11:34.620272 DramcWriteLeveling(PI) end<-----
4198 20:11:34.620354
4199 20:11:34.620438 ==
4200 20:11:34.623394 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 20:11:34.626697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 20:11:34.626779 ==
4203 20:11:34.629827 [Gating] SW mode calibration
4204 20:11:34.636053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 20:11:34.643134 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 20:11:34.646265 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 20:11:34.652863 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 20:11:34.656216 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 20:11:34.660117 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 1) (0 0)
4210 20:11:34.666225 0 9 16 | B1->B0 | 2e2e 2929 | 0 1 | (0 0) (1 0)
4211 20:11:34.669642 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 20:11:34.673031 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 20:11:34.679326 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 20:11:34.682570 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 20:11:34.686068 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 20:11:34.692480 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 20:11:34.695711 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4218 20:11:34.699308 0 10 16 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
4219 20:11:34.705739 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 20:11:34.709092 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 20:11:34.712666 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 20:11:34.719020 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 20:11:34.722028 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 20:11:34.725501 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 20:11:34.732244 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4226 20:11:34.735481 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 20:11:34.738710 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 20:11:34.745661 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 20:11:34.748823 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 20:11:34.751793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 20:11:34.756052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 20:11:34.762006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 20:11:34.765068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 20:11:34.768420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 20:11:34.775216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 20:11:34.778385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 20:11:34.781821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 20:11:34.788452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 20:11:34.791778 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 20:11:34.794719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 20:11:34.801601 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4242 20:11:34.804785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 20:11:34.808523 Total UI for P1: 0, mck2ui 16
4244 20:11:34.811178 best dqsien dly found for B0: ( 0, 13, 12)
4245 20:11:34.814674 Total UI for P1: 0, mck2ui 16
4246 20:11:34.817949 best dqsien dly found for B1: ( 0, 13, 12)
4247 20:11:34.821358 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4248 20:11:34.824263 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4249 20:11:34.824346
4250 20:11:34.827764 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4251 20:11:34.834210 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 20:11:34.834290 [Gating] SW calibration Done
4253 20:11:34.837869 ==
4254 20:11:34.840657 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 20:11:34.843935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 20:11:34.844013 ==
4257 20:11:34.844078 RX Vref Scan: 0
4258 20:11:34.844140
4259 20:11:34.847481 RX Vref 0 -> 0, step: 1
4260 20:11:34.847579
4261 20:11:34.850657 RX Delay -230 -> 252, step: 16
4262 20:11:34.853937 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4263 20:11:34.857388 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4264 20:11:34.863802 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4265 20:11:34.867153 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4266 20:11:34.870841 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4267 20:11:34.874003 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4268 20:11:34.880544 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4269 20:11:34.883792 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4270 20:11:34.887124 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4271 20:11:34.890328 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4272 20:11:34.893581 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4273 20:11:34.900646 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4274 20:11:34.903799 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4275 20:11:34.907074 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4276 20:11:34.910253 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4277 20:11:34.916810 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4278 20:11:34.916917 ==
4279 20:11:34.920325 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 20:11:34.924210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 20:11:34.924310 ==
4282 20:11:34.924448 DQS Delay:
4283 20:11:34.926700 DQS0 = 0, DQS1 = 0
4284 20:11:34.926772 DQM Delay:
4285 20:11:34.930088 DQM0 = 41, DQM1 = 36
4286 20:11:34.930191 DQ Delay:
4287 20:11:34.933306 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4288 20:11:34.937057 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4289 20:11:34.939910 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4290 20:11:34.943264 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4291 20:11:34.943337
4292 20:11:34.943399
4293 20:11:34.943460 ==
4294 20:11:34.946317 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 20:11:34.950223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 20:11:34.953059 ==
4297 20:11:34.953142
4298 20:11:34.953207
4299 20:11:34.953267 TX Vref Scan disable
4300 20:11:34.956848 == TX Byte 0 ==
4301 20:11:34.959585 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4302 20:11:34.966937 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4303 20:11:34.967018 == TX Byte 1 ==
4304 20:11:34.969502 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4305 20:11:34.976504 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4306 20:11:34.976584 ==
4307 20:11:34.979357 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 20:11:34.982605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 20:11:34.982680 ==
4310 20:11:34.982740
4311 20:11:34.982799
4312 20:11:34.986008 TX Vref Scan disable
4313 20:11:34.989775 == TX Byte 0 ==
4314 20:11:34.993156 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4315 20:11:34.995867 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4316 20:11:34.998915 == TX Byte 1 ==
4317 20:11:35.002764 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4318 20:11:35.005653 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4319 20:11:35.005735
4320 20:11:35.009097 [DATLAT]
4321 20:11:35.009178 Freq=600, CH0 RK1
4322 20:11:35.009243
4323 20:11:35.012274 DATLAT Default: 0x9
4324 20:11:35.012355 0, 0xFFFF, sum = 0
4325 20:11:35.015789 1, 0xFFFF, sum = 0
4326 20:11:35.015871 2, 0xFFFF, sum = 0
4327 20:11:35.018863 3, 0xFFFF, sum = 0
4328 20:11:35.018945 4, 0xFFFF, sum = 0
4329 20:11:35.022102 5, 0xFFFF, sum = 0
4330 20:11:35.022185 6, 0xFFFF, sum = 0
4331 20:11:35.025387 7, 0xFFFF, sum = 0
4332 20:11:35.025469 8, 0x0, sum = 1
4333 20:11:35.028786 9, 0x0, sum = 2
4334 20:11:35.028868 10, 0x0, sum = 3
4335 20:11:35.031922 11, 0x0, sum = 4
4336 20:11:35.032004 best_step = 9
4337 20:11:35.032075
4338 20:11:35.032135 ==
4339 20:11:35.035290 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 20:11:35.038527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 20:11:35.041843 ==
4342 20:11:35.041924 RX Vref Scan: 0
4343 20:11:35.041989
4344 20:11:35.045293 RX Vref 0 -> 0, step: 1
4345 20:11:35.045375
4346 20:11:35.048505 RX Delay -179 -> 252, step: 8
4347 20:11:35.051551 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4348 20:11:35.054976 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4349 20:11:35.061670 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4350 20:11:35.065040 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4351 20:11:35.067851 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4352 20:11:35.071547 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4353 20:11:35.077906 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4354 20:11:35.081592 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4355 20:11:35.084882 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4356 20:11:35.088074 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4357 20:11:35.095220 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4358 20:11:35.098338 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4359 20:11:35.101204 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4360 20:11:35.104371 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4361 20:11:35.111000 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4362 20:11:35.114231 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4363 20:11:35.114313 ==
4364 20:11:35.117523 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 20:11:35.121193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 20:11:35.121276 ==
4367 20:11:35.123962 DQS Delay:
4368 20:11:35.124043 DQS0 = 0, DQS1 = 0
4369 20:11:35.124107 DQM Delay:
4370 20:11:35.127636 DQM0 = 41, DQM1 = 37
4371 20:11:35.127758 DQ Delay:
4372 20:11:35.131153 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4373 20:11:35.134360 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4374 20:11:35.137887 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4375 20:11:35.140502 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4376 20:11:35.140574
4377 20:11:35.140639
4378 20:11:35.150682 [DQSOSCAuto] RK1, (LSB)MR18= 0x580c, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
4379 20:11:35.150766 CH0 RK1: MR19=808, MR18=580C
4380 20:11:35.157247 CH0_RK1: MR19=0x808, MR18=0x580C, DQSOSC=393, MR23=63, INC=169, DEC=113
4381 20:11:35.160722 [RxdqsGatingPostProcess] freq 600
4382 20:11:35.166971 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4383 20:11:35.170881 Pre-setting of DQS Precalculation
4384 20:11:35.173891 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4385 20:11:35.173996 ==
4386 20:11:35.177300 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 20:11:35.183523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 20:11:35.183626 ==
4389 20:11:35.187299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 20:11:35.193764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 20:11:35.197514 [CA 0] Center 35 (5~66) winsize 62
4392 20:11:35.199931 [CA 1] Center 35 (5~66) winsize 62
4393 20:11:35.203390 [CA 2] Center 34 (4~65) winsize 62
4394 20:11:35.206682 [CA 3] Center 33 (3~64) winsize 62
4395 20:11:35.210192 [CA 4] Center 34 (4~65) winsize 62
4396 20:11:35.213321 [CA 5] Center 33 (3~64) winsize 62
4397 20:11:35.213402
4398 20:11:35.216332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 20:11:35.216413
4400 20:11:35.220063 [CATrainingPosCal] consider 1 rank data
4401 20:11:35.223506 u2DelayCellTimex100 = 270/100 ps
4402 20:11:35.226305 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 20:11:35.232932 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 20:11:35.236276 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 20:11:35.239338 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 20:11:35.243059 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 20:11:35.246363 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 20:11:35.246445
4409 20:11:35.249242 CA PerBit enable=1, Macro0, CA PI delay=33
4410 20:11:35.249324
4411 20:11:35.253199 [CBTSetCACLKResult] CA Dly = 33
4412 20:11:35.256024 CS Dly: 4 (0~35)
4413 20:11:35.256106 ==
4414 20:11:35.259642 Dram Type= 6, Freq= 0, CH_1, rank 1
4415 20:11:35.262644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 20:11:35.262726 ==
4417 20:11:35.269065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 20:11:35.272374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 20:11:35.276862 [CA 0] Center 36 (6~66) winsize 61
4420 20:11:35.280051 [CA 1] Center 36 (6~66) winsize 61
4421 20:11:35.283474 [CA 2] Center 34 (4~65) winsize 62
4422 20:11:35.286816 [CA 3] Center 34 (3~65) winsize 63
4423 20:11:35.290528 [CA 4] Center 34 (4~65) winsize 62
4424 20:11:35.293370 [CA 5] Center 34 (4~65) winsize 62
4425 20:11:35.293452
4426 20:11:35.296598 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 20:11:35.296680
4428 20:11:35.300254 [CATrainingPosCal] consider 2 rank data
4429 20:11:35.303323 u2DelayCellTimex100 = 270/100 ps
4430 20:11:35.306774 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 20:11:35.313675 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 20:11:35.316667 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 20:11:35.319862 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 20:11:35.323405 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 20:11:35.326597 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4436 20:11:35.326699
4437 20:11:35.329735 CA PerBit enable=1, Macro0, CA PI delay=33
4438 20:11:35.329813
4439 20:11:35.333151 [CBTSetCACLKResult] CA Dly = 33
4440 20:11:35.336311 CS Dly: 5 (0~37)
4441 20:11:35.336412
4442 20:11:35.339592 ----->DramcWriteLeveling(PI) begin...
4443 20:11:35.339698 ==
4444 20:11:35.342952 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 20:11:35.346220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 20:11:35.346300 ==
4447 20:11:35.349311 Write leveling (Byte 0): 30 => 30
4448 20:11:35.353114 Write leveling (Byte 1): 30 => 30
4449 20:11:35.355888 DramcWriteLeveling(PI) end<-----
4450 20:11:35.355997
4451 20:11:35.356090 ==
4452 20:11:35.359250 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 20:11:35.362683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 20:11:35.362766 ==
4455 20:11:35.366000 [Gating] SW mode calibration
4456 20:11:35.372763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 20:11:35.379131 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4458 20:11:35.382619 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 20:11:35.386146 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 20:11:35.392900 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4461 20:11:35.395931 0 9 12 | B1->B0 | 3131 3030 | 1 1 | (1 1) (1 0)
4462 20:11:35.399144 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 20:11:35.405518 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 20:11:35.408930 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 20:11:35.411875 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 20:11:35.419165 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 20:11:35.421870 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 20:11:35.425554 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 20:11:35.431863 0 10 12 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (0 0)
4470 20:11:35.435440 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4471 20:11:35.438247 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 20:11:35.445021 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 20:11:35.448719 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 20:11:35.452050 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 20:11:35.458129 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 20:11:35.461706 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 20:11:35.464705 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4478 20:11:35.471432 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 20:11:35.474770 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 20:11:35.478145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 20:11:35.484579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 20:11:35.488009 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 20:11:35.491415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 20:11:35.497945 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 20:11:35.501302 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 20:11:35.504467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 20:11:35.510854 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 20:11:35.514223 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 20:11:35.517548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 20:11:35.524250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 20:11:35.527713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 20:11:35.531261 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 20:11:35.537459 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 20:11:35.540556 Total UI for P1: 0, mck2ui 16
4495 20:11:35.543827 best dqsien dly found for B0: ( 0, 13, 10)
4496 20:11:35.547395 Total UI for P1: 0, mck2ui 16
4497 20:11:35.550245 best dqsien dly found for B1: ( 0, 13, 10)
4498 20:11:35.553803 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4499 20:11:35.556832 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4500 20:11:35.556913
4501 20:11:35.560373 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4502 20:11:35.563886 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4503 20:11:35.567051 [Gating] SW calibration Done
4504 20:11:35.567132 ==
4505 20:11:35.570563 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 20:11:35.573662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 20:11:35.573745 ==
4508 20:11:35.576871 RX Vref Scan: 0
4509 20:11:35.576969
4510 20:11:35.580131 RX Vref 0 -> 0, step: 1
4511 20:11:35.580213
4512 20:11:35.580278 RX Delay -230 -> 252, step: 16
4513 20:11:35.587002 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4514 20:11:35.590527 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4515 20:11:35.593352 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4516 20:11:35.596740 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 20:11:35.603340 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 20:11:35.606815 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4519 20:11:35.610232 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4520 20:11:35.613099 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4521 20:11:35.619787 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4522 20:11:35.623415 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4523 20:11:35.626609 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 20:11:35.630077 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4525 20:11:35.636488 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 20:11:35.639886 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 20:11:35.643149 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4528 20:11:35.646579 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4529 20:11:35.646659 ==
4530 20:11:35.649541 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 20:11:35.655952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 20:11:35.656035 ==
4533 20:11:35.656098 DQS Delay:
4534 20:11:35.659858 DQS0 = 0, DQS1 = 0
4535 20:11:35.659938 DQM Delay:
4536 20:11:35.660002 DQM0 = 47, DQM1 = 38
4537 20:11:35.662678 DQ Delay:
4538 20:11:35.666461 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4539 20:11:35.669627 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4540 20:11:35.672743 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4541 20:11:35.676191 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4542 20:11:35.676272
4543 20:11:35.676335
4544 20:11:35.676394 ==
4545 20:11:35.679242 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 20:11:35.682351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 20:11:35.682432 ==
4548 20:11:35.682495
4549 20:11:35.682554
4550 20:11:35.685798 TX Vref Scan disable
4551 20:11:35.689058 == TX Byte 0 ==
4552 20:11:35.692056 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4553 20:11:35.695512 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4554 20:11:35.698896 == TX Byte 1 ==
4555 20:11:35.702418 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 20:11:35.705590 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 20:11:35.705671 ==
4558 20:11:35.708906 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 20:11:35.715363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 20:11:35.715444 ==
4561 20:11:35.715508
4562 20:11:35.715566
4563 20:11:35.715622 TX Vref Scan disable
4564 20:11:35.719973 == TX Byte 0 ==
4565 20:11:35.722643 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4566 20:11:35.729590 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4567 20:11:35.729671 == TX Byte 1 ==
4568 20:11:35.732806 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 20:11:35.739497 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 20:11:35.739578
4571 20:11:35.739641 [DATLAT]
4572 20:11:35.739707 Freq=600, CH1 RK0
4573 20:11:35.739765
4574 20:11:35.742338 DATLAT Default: 0x9
4575 20:11:35.745987 0, 0xFFFF, sum = 0
4576 20:11:35.746069 1, 0xFFFF, sum = 0
4577 20:11:35.748998 2, 0xFFFF, sum = 0
4578 20:11:35.749079 3, 0xFFFF, sum = 0
4579 20:11:35.752328 4, 0xFFFF, sum = 0
4580 20:11:35.752409 5, 0xFFFF, sum = 0
4581 20:11:35.755803 6, 0xFFFF, sum = 0
4582 20:11:35.755910 7, 0xFFFF, sum = 0
4583 20:11:35.759094 8, 0x0, sum = 1
4584 20:11:35.759176 9, 0x0, sum = 2
4585 20:11:35.762337 10, 0x0, sum = 3
4586 20:11:35.762418 11, 0x0, sum = 4
4587 20:11:35.762483 best_step = 9
4588 20:11:35.762541
4589 20:11:35.765714 ==
4590 20:11:35.765793 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 20:11:35.772330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 20:11:35.772411 ==
4593 20:11:35.772475 RX Vref Scan: 1
4594 20:11:35.772534
4595 20:11:35.775319 RX Vref 0 -> 0, step: 1
4596 20:11:35.775399
4597 20:11:35.778832 RX Delay -179 -> 252, step: 8
4598 20:11:35.778912
4599 20:11:35.782003 Set Vref, RX VrefLevel [Byte0]: 49
4600 20:11:35.785877 [Byte1]: 53
4601 20:11:35.785958
4602 20:11:35.789068 Final RX Vref Byte 0 = 49 to rank0
4603 20:11:35.792148 Final RX Vref Byte 1 = 53 to rank0
4604 20:11:35.795154 Final RX Vref Byte 0 = 49 to rank1
4605 20:11:35.798761 Final RX Vref Byte 1 = 53 to rank1==
4606 20:11:35.801681 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 20:11:35.805474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 20:11:35.808173 ==
4609 20:11:35.808246 DQS Delay:
4610 20:11:35.808308 DQS0 = 0, DQS1 = 0
4611 20:11:35.812296 DQM Delay:
4612 20:11:35.812376 DQM0 = 48, DQM1 = 37
4613 20:11:35.814773 DQ Delay:
4614 20:11:35.818593 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4615 20:11:35.818674 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4616 20:11:35.821609 DQ8 =24, DQ9 =28, DQ10 =36, DQ11 =28
4617 20:11:35.827851 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4618 20:11:35.827932
4619 20:11:35.827995
4620 20:11:35.835037 [DQSOSCAuto] RK0, (LSB)MR18= 0x492e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4621 20:11:35.837836 CH1 RK0: MR19=808, MR18=492E
4622 20:11:35.844771 CH1_RK0: MR19=0x808, MR18=0x492E, DQSOSC=396, MR23=63, INC=167, DEC=111
4623 20:11:35.844857
4624 20:11:35.847797 ----->DramcWriteLeveling(PI) begin...
4625 20:11:35.847882 ==
4626 20:11:35.851117 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 20:11:35.854485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 20:11:35.854566 ==
4629 20:11:35.857554 Write leveling (Byte 0): 28 => 28
4630 20:11:35.860843 Write leveling (Byte 1): 29 => 29
4631 20:11:35.864217 DramcWriteLeveling(PI) end<-----
4632 20:11:35.864297
4633 20:11:35.864360 ==
4634 20:11:35.868007 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 20:11:35.870807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 20:11:35.874160 ==
4637 20:11:35.874240 [Gating] SW mode calibration
4638 20:11:35.880971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4639 20:11:35.887237 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4640 20:11:35.890513 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 20:11:35.896941 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 20:11:35.900613 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 20:11:35.903917 0 9 12 | B1->B0 | 3030 3434 | 0 0 | (1 1) (0 0)
4644 20:11:35.910552 0 9 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4645 20:11:35.913815 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 20:11:35.916836 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 20:11:35.923454 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 20:11:35.927057 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 20:11:35.930243 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 20:11:35.936790 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 20:11:35.939806 0 10 12 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
4652 20:11:35.943329 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)
4653 20:11:35.949903 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 20:11:35.952958 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 20:11:35.956397 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 20:11:35.963201 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 20:11:35.966108 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 20:11:35.969507 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 20:11:35.976127 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4660 20:11:35.979702 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4661 20:11:35.982758 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 20:11:35.989604 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 20:11:35.992289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 20:11:35.996153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 20:11:36.002408 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 20:11:36.005698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 20:11:36.008744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 20:11:36.015809 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 20:11:36.019096 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 20:11:36.022256 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 20:11:36.029714 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 20:11:36.032275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 20:11:36.036197 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 20:11:36.042254 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 20:11:36.045944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4676 20:11:36.049116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 20:11:36.052378 Total UI for P1: 0, mck2ui 16
4678 20:11:36.055211 best dqsien dly found for B0: ( 0, 13, 12)
4679 20:11:36.058615 Total UI for P1: 0, mck2ui 16
4680 20:11:36.061725 best dqsien dly found for B1: ( 0, 13, 14)
4681 20:11:36.065260 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4682 20:11:36.068339 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4683 20:11:36.071624
4684 20:11:36.075331 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4685 20:11:36.078302 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4686 20:11:36.081920 [Gating] SW calibration Done
4687 20:11:36.082009 ==
4688 20:11:36.085115 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 20:11:36.088293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 20:11:36.088374 ==
4691 20:11:36.088438 RX Vref Scan: 0
4692 20:11:36.091477
4693 20:11:36.091556 RX Vref 0 -> 0, step: 1
4694 20:11:36.091619
4695 20:11:36.094792 RX Delay -230 -> 252, step: 16
4696 20:11:36.098455 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4697 20:11:36.104995 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4698 20:11:36.108904 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4699 20:11:36.111660 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4700 20:11:36.114973 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4701 20:11:36.121314 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4702 20:11:36.124326 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4703 20:11:36.127651 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4704 20:11:36.131394 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4705 20:11:36.134466 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4706 20:11:36.141205 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4707 20:11:36.144272 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4708 20:11:36.147970 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4709 20:11:36.150962 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4710 20:11:36.157310 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4711 20:11:36.161324 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4712 20:11:36.161395 ==
4713 20:11:36.164038 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 20:11:36.167473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 20:11:36.167553 ==
4716 20:11:36.170680 DQS Delay:
4717 20:11:36.170761 DQS0 = 0, DQS1 = 0
4718 20:11:36.174081 DQM Delay:
4719 20:11:36.174161 DQM0 = 41, DQM1 = 36
4720 20:11:36.174225 DQ Delay:
4721 20:11:36.177590 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4722 20:11:36.180643 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =41
4723 20:11:36.184173 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4724 20:11:36.187050 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4725 20:11:36.187131
4726 20:11:36.187194
4727 20:11:36.191001 ==
4728 20:11:36.193587 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 20:11:36.197343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 20:11:36.197424 ==
4731 20:11:36.197488
4732 20:11:36.197546
4733 20:11:36.200218 TX Vref Scan disable
4734 20:11:36.200309 == TX Byte 0 ==
4735 20:11:36.206904 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4736 20:11:36.210325 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4737 20:11:36.210405 == TX Byte 1 ==
4738 20:11:36.216831 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4739 20:11:36.220086 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4740 20:11:36.220170 ==
4741 20:11:36.223135 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 20:11:36.226250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 20:11:36.226331 ==
4744 20:11:36.226394
4745 20:11:36.226453
4746 20:11:36.230038 TX Vref Scan disable
4747 20:11:36.233027 == TX Byte 0 ==
4748 20:11:36.236438 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4749 20:11:36.239889 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4750 20:11:36.242983 == TX Byte 1 ==
4751 20:11:36.246564 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4752 20:11:36.249562 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4753 20:11:36.253250
4754 20:11:36.253329 [DATLAT]
4755 20:11:36.253393 Freq=600, CH1 RK1
4756 20:11:36.253452
4757 20:11:36.256077 DATLAT Default: 0x9
4758 20:11:36.256158 0, 0xFFFF, sum = 0
4759 20:11:36.259630 1, 0xFFFF, sum = 0
4760 20:11:36.259748 2, 0xFFFF, sum = 0
4761 20:11:36.262465 3, 0xFFFF, sum = 0
4762 20:11:36.265901 4, 0xFFFF, sum = 0
4763 20:11:36.265982 5, 0xFFFF, sum = 0
4764 20:11:36.269456 6, 0xFFFF, sum = 0
4765 20:11:36.269537 7, 0xFFFF, sum = 0
4766 20:11:36.272615 8, 0x0, sum = 1
4767 20:11:36.272696 9, 0x0, sum = 2
4768 20:11:36.272761 10, 0x0, sum = 3
4769 20:11:36.275498 11, 0x0, sum = 4
4770 20:11:36.275579 best_step = 9
4771 20:11:36.275680
4772 20:11:36.279132 ==
4773 20:11:36.279248 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 20:11:36.285591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 20:11:36.285678 ==
4776 20:11:36.285764 RX Vref Scan: 0
4777 20:11:36.285845
4778 20:11:36.288808 RX Vref 0 -> 0, step: 1
4779 20:11:36.288892
4780 20:11:36.292434 RX Delay -179 -> 252, step: 8
4781 20:11:36.298702 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4782 20:11:36.302113 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4783 20:11:36.305082 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4784 20:11:36.308586 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4785 20:11:36.311957 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4786 20:11:36.318494 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4787 20:11:36.321984 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4788 20:11:36.324737 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4789 20:11:36.328070 iDelay=213, Bit 8, Center 28 (-123 ~ 180) 304
4790 20:11:36.334982 iDelay=213, Bit 9, Center 28 (-123 ~ 180) 304
4791 20:11:36.338413 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4792 20:11:36.341498 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4793 20:11:36.344728 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4794 20:11:36.351342 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4795 20:11:36.355200 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4796 20:11:36.358065 iDelay=213, Bit 15, Center 44 (-107 ~ 196) 304
4797 20:11:36.358149 ==
4798 20:11:36.361506 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 20:11:36.364438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 20:11:36.367562 ==
4801 20:11:36.367661 DQS Delay:
4802 20:11:36.367749 DQS0 = 0, DQS1 = 0
4803 20:11:36.371693 DQM Delay:
4804 20:11:36.371822 DQM0 = 45, DQM1 = 37
4805 20:11:36.374428 DQ Delay:
4806 20:11:36.377564 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4807 20:11:36.377646 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4808 20:11:36.380874 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =28
4809 20:11:36.387412 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =44
4810 20:11:36.387496
4811 20:11:36.387567
4812 20:11:36.394520 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4813 20:11:36.397152 CH1 RK1: MR19=808, MR18=291E
4814 20:11:36.404012 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4815 20:11:36.407599 [RxdqsGatingPostProcess] freq 600
4816 20:11:36.410406 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4817 20:11:36.414337 Pre-setting of DQS Precalculation
4818 20:11:36.420607 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4819 20:11:36.427034 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4820 20:11:36.433510 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4821 20:11:36.433592
4822 20:11:36.433664
4823 20:11:36.437163 [Calibration Summary] 1200 Mbps
4824 20:11:36.437236 CH 0, Rank 0
4825 20:11:36.440470 SW Impedance : PASS
4826 20:11:36.443357 DUTY Scan : NO K
4827 20:11:36.443432 ZQ Calibration : PASS
4828 20:11:36.447030 Jitter Meter : NO K
4829 20:11:36.450545 CBT Training : PASS
4830 20:11:36.450628 Write leveling : PASS
4831 20:11:36.453649 RX DQS gating : PASS
4832 20:11:36.457076 RX DQ/DQS(RDDQC) : PASS
4833 20:11:36.457154 TX DQ/DQS : PASS
4834 20:11:36.460577 RX DATLAT : PASS
4835 20:11:36.463287 RX DQ/DQS(Engine): PASS
4836 20:11:36.463364 TX OE : NO K
4837 20:11:36.463429 All Pass.
4838 20:11:36.467034
4839 20:11:36.467117 CH 0, Rank 1
4840 20:11:36.469972 SW Impedance : PASS
4841 20:11:36.470055 DUTY Scan : NO K
4842 20:11:36.473061 ZQ Calibration : PASS
4843 20:11:36.476972 Jitter Meter : NO K
4844 20:11:36.477081 CBT Training : PASS
4845 20:11:36.480036 Write leveling : PASS
4846 20:11:36.480109 RX DQS gating : PASS
4847 20:11:36.483132 RX DQ/DQS(RDDQC) : PASS
4848 20:11:36.486453 TX DQ/DQS : PASS
4849 20:11:36.486525 RX DATLAT : PASS
4850 20:11:36.489931 RX DQ/DQS(Engine): PASS
4851 20:11:36.493186 TX OE : NO K
4852 20:11:36.493269 All Pass.
4853 20:11:36.493332
4854 20:11:36.493391 CH 1, Rank 0
4855 20:11:36.496170 SW Impedance : PASS
4856 20:11:36.499452 DUTY Scan : NO K
4857 20:11:36.499557 ZQ Calibration : PASS
4858 20:11:36.502806 Jitter Meter : NO K
4859 20:11:36.506360 CBT Training : PASS
4860 20:11:36.506434 Write leveling : PASS
4861 20:11:36.509450 RX DQS gating : PASS
4862 20:11:36.513285 RX DQ/DQS(RDDQC) : PASS
4863 20:11:36.513358 TX DQ/DQS : PASS
4864 20:11:36.516350 RX DATLAT : PASS
4865 20:11:36.519831 RX DQ/DQS(Engine): PASS
4866 20:11:36.519906 TX OE : NO K
4867 20:11:36.523070 All Pass.
4868 20:11:36.523151
4869 20:11:36.523213 CH 1, Rank 1
4870 20:11:36.525867 SW Impedance : PASS
4871 20:11:36.525936 DUTY Scan : NO K
4872 20:11:36.529662 ZQ Calibration : PASS
4873 20:11:36.532935 Jitter Meter : NO K
4874 20:11:36.533006 CBT Training : PASS
4875 20:11:36.535850 Write leveling : PASS
4876 20:11:36.539224 RX DQS gating : PASS
4877 20:11:36.539301 RX DQ/DQS(RDDQC) : PASS
4878 20:11:36.542772 TX DQ/DQS : PASS
4879 20:11:36.546049 RX DATLAT : PASS
4880 20:11:36.546159 RX DQ/DQS(Engine): PASS
4881 20:11:36.549157 TX OE : NO K
4882 20:11:36.549241 All Pass.
4883 20:11:36.549306
4884 20:11:36.552416 DramC Write-DBI off
4885 20:11:36.555609 PER_BANK_REFRESH: Hybrid Mode
4886 20:11:36.555700 TX_TRACKING: ON
4887 20:11:36.565778 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4888 20:11:36.569146 [FAST_K] Save calibration result to emmc
4889 20:11:36.572297 dramc_set_vcore_voltage set vcore to 662500
4890 20:11:36.575610 Read voltage for 933, 3
4891 20:11:36.575702 Vio18 = 0
4892 20:11:36.575770 Vcore = 662500
4893 20:11:36.578681 Vdram = 0
4894 20:11:36.578763 Vddq = 0
4895 20:11:36.578829 Vmddr = 0
4896 20:11:36.585513 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4897 20:11:36.588757 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4898 20:11:36.592145 MEM_TYPE=3, freq_sel=17
4899 20:11:36.595804 sv_algorithm_assistance_LP4_1600
4900 20:11:36.598547 ============ PULL DRAM RESETB DOWN ============
4901 20:11:36.602222 ========== PULL DRAM RESETB DOWN end =========
4902 20:11:36.608828 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4903 20:11:36.612278 ===================================
4904 20:11:36.612389 LPDDR4 DRAM CONFIGURATION
4905 20:11:36.615205 ===================================
4906 20:11:36.618814 EX_ROW_EN[0] = 0x0
4907 20:11:36.621972 EX_ROW_EN[1] = 0x0
4908 20:11:36.622073 LP4Y_EN = 0x0
4909 20:11:36.625184 WORK_FSP = 0x0
4910 20:11:36.625283 WL = 0x3
4911 20:11:36.628562 RL = 0x3
4912 20:11:36.628647 BL = 0x2
4913 20:11:36.631552 RPST = 0x0
4914 20:11:36.631659 RD_PRE = 0x0
4915 20:11:36.635010 WR_PRE = 0x1
4916 20:11:36.635115 WR_PST = 0x0
4917 20:11:36.638331 DBI_WR = 0x0
4918 20:11:36.638438 DBI_RD = 0x0
4919 20:11:36.641629 OTF = 0x1
4920 20:11:36.645222 ===================================
4921 20:11:36.648092 ===================================
4922 20:11:36.648168 ANA top config
4923 20:11:36.651616 ===================================
4924 20:11:36.654751 DLL_ASYNC_EN = 0
4925 20:11:36.658114 ALL_SLAVE_EN = 1
4926 20:11:36.662276 NEW_RANK_MODE = 1
4927 20:11:36.662379 DLL_IDLE_MODE = 1
4928 20:11:36.665162 LP45_APHY_COMB_EN = 1
4929 20:11:36.668089 TX_ODT_DIS = 1
4930 20:11:36.671453 NEW_8X_MODE = 1
4931 20:11:36.674591 ===================================
4932 20:11:36.678035 ===================================
4933 20:11:36.680975 data_rate = 1866
4934 20:11:36.684372 CKR = 1
4935 20:11:36.684474 DQ_P2S_RATIO = 8
4936 20:11:36.687804 ===================================
4937 20:11:36.691033 CA_P2S_RATIO = 8
4938 20:11:36.694241 DQ_CA_OPEN = 0
4939 20:11:36.697902 DQ_SEMI_OPEN = 0
4940 20:11:36.701320 CA_SEMI_OPEN = 0
4941 20:11:36.704213 CA_FULL_RATE = 0
4942 20:11:36.704315 DQ_CKDIV4_EN = 1
4943 20:11:36.707784 CA_CKDIV4_EN = 1
4944 20:11:36.710774 CA_PREDIV_EN = 0
4945 20:11:36.714397 PH8_DLY = 0
4946 20:11:36.717272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4947 20:11:36.720806 DQ_AAMCK_DIV = 4
4948 20:11:36.720892 CA_AAMCK_DIV = 4
4949 20:11:36.723768 CA_ADMCK_DIV = 4
4950 20:11:36.727562 DQ_TRACK_CA_EN = 0
4951 20:11:36.731119 CA_PICK = 933
4952 20:11:36.733782 CA_MCKIO = 933
4953 20:11:36.737042 MCKIO_SEMI = 0
4954 20:11:36.740609 PLL_FREQ = 3732
4955 20:11:36.740686 DQ_UI_PI_RATIO = 32
4956 20:11:36.743633 CA_UI_PI_RATIO = 0
4957 20:11:36.747143 ===================================
4958 20:11:36.750362 ===================================
4959 20:11:36.753796 memory_type:LPDDR4
4960 20:11:36.756576 GP_NUM : 10
4961 20:11:36.756650 SRAM_EN : 1
4962 20:11:36.759843 MD32_EN : 0
4963 20:11:36.763730 ===================================
4964 20:11:36.766857 [ANA_INIT] >>>>>>>>>>>>>>
4965 20:11:36.770201 <<<<<< [CONFIGURE PHASE]: ANA_TX
4966 20:11:36.773270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4967 20:11:36.776471 ===================================
4968 20:11:36.776574 data_rate = 1866,PCW = 0X8f00
4969 20:11:36.780336 ===================================
4970 20:11:36.783477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4971 20:11:36.789514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 20:11:36.796212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 20:11:36.799667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4974 20:11:36.802616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4975 20:11:36.806258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4976 20:11:36.809611 [ANA_INIT] flow start
4977 20:11:36.813112 [ANA_INIT] PLL >>>>>>>>
4978 20:11:36.813187 [ANA_INIT] PLL <<<<<<<<
4979 20:11:36.816271 [ANA_INIT] MIDPI >>>>>>>>
4980 20:11:36.819650 [ANA_INIT] MIDPI <<<<<<<<
4981 20:11:36.819738 [ANA_INIT] DLL >>>>>>>>
4982 20:11:36.822927 [ANA_INIT] flow end
4983 20:11:36.825878 ============ LP4 DIFF to SE enter ============
4984 20:11:36.829319 ============ LP4 DIFF to SE exit ============
4985 20:11:36.832782 [ANA_INIT] <<<<<<<<<<<<<
4986 20:11:36.835846 [Flow] Enable top DCM control >>>>>
4987 20:11:36.839112 [Flow] Enable top DCM control <<<<<
4988 20:11:36.842437 Enable DLL master slave shuffle
4989 20:11:36.849201 ==============================================================
4990 20:11:36.849310 Gating Mode config
4991 20:11:36.855872 ==============================================================
4992 20:11:36.859110 Config description:
4993 20:11:36.865602 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4994 20:11:36.871887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4995 20:11:36.879294 SELPH_MODE 0: By rank 1: By Phase
4996 20:11:36.885054 ==============================================================
4997 20:11:36.888192 GAT_TRACK_EN = 1
4998 20:11:36.888269 RX_GATING_MODE = 2
4999 20:11:36.891789 RX_GATING_TRACK_MODE = 2
5000 20:11:36.894839 SELPH_MODE = 1
5001 20:11:36.898664 PICG_EARLY_EN = 1
5002 20:11:36.901529 VALID_LAT_VALUE = 1
5003 20:11:36.908408 ==============================================================
5004 20:11:36.911450 Enter into Gating configuration >>>>
5005 20:11:36.914927 Exit from Gating configuration <<<<
5006 20:11:36.918459 Enter into DVFS_PRE_config >>>>>
5007 20:11:36.928352 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5008 20:11:36.931517 Exit from DVFS_PRE_config <<<<<
5009 20:11:36.934960 Enter into PICG configuration >>>>
5010 20:11:36.937863 Exit from PICG configuration <<<<
5011 20:11:36.941377 [RX_INPUT] configuration >>>>>
5012 20:11:36.944231 [RX_INPUT] configuration <<<<<
5013 20:11:36.947693 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5014 20:11:36.954577 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5015 20:11:36.961086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 20:11:36.967658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 20:11:36.974052 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 20:11:36.977225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 20:11:36.983556 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5020 20:11:36.987277 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5021 20:11:36.990198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5022 20:11:36.993572 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5023 20:11:37.000457 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5024 20:11:37.003846 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5025 20:11:37.006934 ===================================
5026 20:11:37.010078 LPDDR4 DRAM CONFIGURATION
5027 20:11:37.013375 ===================================
5028 20:11:37.013459 EX_ROW_EN[0] = 0x0
5029 20:11:37.016797 EX_ROW_EN[1] = 0x0
5030 20:11:37.016881 LP4Y_EN = 0x0
5031 20:11:37.020326 WORK_FSP = 0x0
5032 20:11:37.020410 WL = 0x3
5033 20:11:37.023537 RL = 0x3
5034 20:11:37.023620 BL = 0x2
5035 20:11:37.027013 RPST = 0x0
5036 20:11:37.029952 RD_PRE = 0x0
5037 20:11:37.030067 WR_PRE = 0x1
5038 20:11:37.033544 WR_PST = 0x0
5039 20:11:37.033628 DBI_WR = 0x0
5040 20:11:37.036364 DBI_RD = 0x0
5041 20:11:37.036448 OTF = 0x1
5042 20:11:37.039835 ===================================
5043 20:11:37.043039 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5044 20:11:37.049444 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5045 20:11:37.053010 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5046 20:11:37.056423 ===================================
5047 20:11:37.059625 LPDDR4 DRAM CONFIGURATION
5048 20:11:37.063373 ===================================
5049 20:11:37.063457 EX_ROW_EN[0] = 0x10
5050 20:11:37.066325 EX_ROW_EN[1] = 0x0
5051 20:11:37.066408 LP4Y_EN = 0x0
5052 20:11:37.069675 WORK_FSP = 0x0
5053 20:11:37.069762 WL = 0x3
5054 20:11:37.072965 RL = 0x3
5055 20:11:37.076305 BL = 0x2
5056 20:11:37.076388 RPST = 0x0
5057 20:11:37.079656 RD_PRE = 0x0
5058 20:11:37.079775 WR_PRE = 0x1
5059 20:11:37.082335 WR_PST = 0x0
5060 20:11:37.082419 DBI_WR = 0x0
5061 20:11:37.086216 DBI_RD = 0x0
5062 20:11:37.086299 OTF = 0x1
5063 20:11:37.089271 ===================================
5064 20:11:37.095452 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5065 20:11:37.100114 nWR fixed to 30
5066 20:11:37.103734 [ModeRegInit_LP4] CH0 RK0
5067 20:11:37.103819 [ModeRegInit_LP4] CH0 RK1
5068 20:11:37.106262 [ModeRegInit_LP4] CH1 RK0
5069 20:11:37.109594 [ModeRegInit_LP4] CH1 RK1
5070 20:11:37.109678 match AC timing 9
5071 20:11:37.116349 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5072 20:11:37.120046 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5073 20:11:37.123215 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5074 20:11:37.129594 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5075 20:11:37.132721 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5076 20:11:37.132826 ==
5077 20:11:37.136783 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 20:11:37.139402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 20:11:37.139486 ==
5080 20:11:37.145923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 20:11:37.153040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5082 20:11:37.155706 [CA 0] Center 38 (7~69) winsize 63
5083 20:11:37.159009 [CA 1] Center 37 (7~68) winsize 62
5084 20:11:37.162404 [CA 2] Center 34 (4~65) winsize 62
5085 20:11:37.166405 [CA 3] Center 35 (5~65) winsize 61
5086 20:11:37.169236 [CA 4] Center 33 (3~64) winsize 62
5087 20:11:37.172180 [CA 5] Center 33 (3~64) winsize 62
5088 20:11:37.172264
5089 20:11:37.175566 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5090 20:11:37.175649
5091 20:11:37.179527 [CATrainingPosCal] consider 1 rank data
5092 20:11:37.182687 u2DelayCellTimex100 = 270/100 ps
5093 20:11:37.185947 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5094 20:11:37.189411 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5095 20:11:37.192800 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5096 20:11:37.195427 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5097 20:11:37.202273 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5098 20:11:37.205552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5099 20:11:37.205636
5100 20:11:37.208920 CA PerBit enable=1, Macro0, CA PI delay=33
5101 20:11:37.209004
5102 20:11:37.212359 [CBTSetCACLKResult] CA Dly = 33
5103 20:11:37.212440 CS Dly: 7 (0~38)
5104 20:11:37.212505 ==
5105 20:11:37.215170 Dram Type= 6, Freq= 0, CH_0, rank 1
5106 20:11:37.222104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 20:11:37.222220 ==
5108 20:11:37.225538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 20:11:37.232291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5110 20:11:37.235161 [CA 0] Center 37 (7~68) winsize 62
5111 20:11:37.238585 [CA 1] Center 37 (7~68) winsize 62
5112 20:11:37.241604 [CA 2] Center 34 (4~65) winsize 62
5113 20:11:37.245327 [CA 3] Center 35 (5~65) winsize 61
5114 20:11:37.249018 [CA 4] Center 33 (3~64) winsize 62
5115 20:11:37.252227 [CA 5] Center 33 (3~63) winsize 61
5116 20:11:37.252309
5117 20:11:37.255411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5118 20:11:37.255508
5119 20:11:37.258504 [CATrainingPosCal] consider 2 rank data
5120 20:11:37.261827 u2DelayCellTimex100 = 270/100 ps
5121 20:11:37.265022 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 20:11:37.268507 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 20:11:37.275033 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 20:11:37.278263 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5125 20:11:37.281577 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5126 20:11:37.284638 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5127 20:11:37.284720
5128 20:11:37.288270 CA PerBit enable=1, Macro0, CA PI delay=33
5129 20:11:37.288367
5130 20:11:37.291462 [CBTSetCACLKResult] CA Dly = 33
5131 20:11:37.294550 CS Dly: 7 (0~39)
5132 20:11:37.294647
5133 20:11:37.298323 ----->DramcWriteLeveling(PI) begin...
5134 20:11:37.298466 ==
5135 20:11:37.301206 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 20:11:37.304500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 20:11:37.304613 ==
5138 20:11:37.308088 Write leveling (Byte 0): 34 => 34
5139 20:11:37.311259 Write leveling (Byte 1): 29 => 29
5140 20:11:37.314823 DramcWriteLeveling(PI) end<-----
5141 20:11:37.314934
5142 20:11:37.314998 ==
5143 20:11:37.317435 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 20:11:37.320763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 20:11:37.320845 ==
5146 20:11:37.324356 [Gating] SW mode calibration
5147 20:11:37.330712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5148 20:11:37.337562 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5149 20:11:37.341035 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
5150 20:11:37.343863 0 14 4 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
5151 20:11:37.350400 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 20:11:37.353660 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 20:11:37.357085 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 20:11:37.363520 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 20:11:37.367190 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 20:11:37.370274 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5157 20:11:37.377210 0 15 0 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
5158 20:11:37.379985 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5159 20:11:37.383777 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 20:11:37.389980 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 20:11:37.393107 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 20:11:37.396799 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 20:11:37.403130 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 20:11:37.406952 0 15 28 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
5165 20:11:37.409663 1 0 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5166 20:11:37.416313 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5167 20:11:37.419463 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 20:11:37.423209 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 20:11:37.429518 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 20:11:37.433254 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 20:11:37.436020 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 20:11:37.442592 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5173 20:11:37.445769 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 20:11:37.449179 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 20:11:37.456058 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 20:11:37.459319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 20:11:37.462456 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 20:11:37.469430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 20:11:37.472754 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 20:11:37.475911 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 20:11:37.482726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 20:11:37.485580 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 20:11:37.489395 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 20:11:37.495423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 20:11:37.498944 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 20:11:37.502409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 20:11:37.508927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 20:11:37.511780 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5189 20:11:37.515177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5190 20:11:37.518276 Total UI for P1: 0, mck2ui 16
5191 20:11:37.522169 best dqsien dly found for B0: ( 1, 2, 28)
5192 20:11:37.528485 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5193 20:11:37.531942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 20:11:37.535394 Total UI for P1: 0, mck2ui 16
5195 20:11:37.538582 best dqsien dly found for B1: ( 1, 3, 0)
5196 20:11:37.541784 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5197 20:11:37.544782 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5198 20:11:37.544865
5199 20:11:37.548299 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5200 20:11:37.551473 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5201 20:11:37.555017 [Gating] SW calibration Done
5202 20:11:37.555100 ==
5203 20:11:37.557931 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 20:11:37.564668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 20:11:37.564766 ==
5206 20:11:37.564874 RX Vref Scan: 0
5207 20:11:37.564935
5208 20:11:37.567853 RX Vref 0 -> 0, step: 1
5209 20:11:37.567935
5210 20:11:37.571536 RX Delay -80 -> 252, step: 8
5211 20:11:37.574869 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5212 20:11:37.577899 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5213 20:11:37.581575 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5214 20:11:37.584803 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5215 20:11:37.591649 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5216 20:11:37.594283 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5217 20:11:37.597919 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5218 20:11:37.601114 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5219 20:11:37.604157 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5220 20:11:37.607778 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5221 20:11:37.614604 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5222 20:11:37.617415 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5223 20:11:37.620909 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5224 20:11:37.624417 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5225 20:11:37.630777 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5226 20:11:37.634130 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5227 20:11:37.634215 ==
5228 20:11:37.637348 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 20:11:37.640359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 20:11:37.640443 ==
5231 20:11:37.640510 DQS Delay:
5232 20:11:37.643698 DQS0 = 0, DQS1 = 0
5233 20:11:37.643782 DQM Delay:
5234 20:11:37.647426 DQM0 = 97, DQM1 = 84
5235 20:11:37.647510 DQ Delay:
5236 20:11:37.650627 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5237 20:11:37.653772 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5238 20:11:37.657170 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5239 20:11:37.660444 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5240 20:11:37.660531
5241 20:11:37.660597
5242 20:11:37.660658 ==
5243 20:11:37.663745 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 20:11:37.670520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 20:11:37.670605 ==
5246 20:11:37.670671
5247 20:11:37.670733
5248 20:11:37.670792 TX Vref Scan disable
5249 20:11:37.673637 == TX Byte 0 ==
5250 20:11:37.676986 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5251 20:11:37.683286 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5252 20:11:37.683384 == TX Byte 1 ==
5253 20:11:37.686845 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5254 20:11:37.693472 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5255 20:11:37.693556 ==
5256 20:11:37.696812 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 20:11:37.700401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 20:11:37.700485 ==
5259 20:11:37.700552
5260 20:11:37.700613
5261 20:11:37.703601 TX Vref Scan disable
5262 20:11:37.706708 == TX Byte 0 ==
5263 20:11:37.709899 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5264 20:11:37.713980 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5265 20:11:37.716447 == TX Byte 1 ==
5266 20:11:37.719875 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5267 20:11:37.723192 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5268 20:11:37.723274
5269 20:11:37.723339 [DATLAT]
5270 20:11:37.726424 Freq=933, CH0 RK0
5271 20:11:37.726506
5272 20:11:37.726571 DATLAT Default: 0xd
5273 20:11:37.729787 0, 0xFFFF, sum = 0
5274 20:11:37.733283 1, 0xFFFF, sum = 0
5275 20:11:37.733382 2, 0xFFFF, sum = 0
5276 20:11:37.736313 3, 0xFFFF, sum = 0
5277 20:11:37.736396 4, 0xFFFF, sum = 0
5278 20:11:37.739620 5, 0xFFFF, sum = 0
5279 20:11:37.739742 6, 0xFFFF, sum = 0
5280 20:11:37.743179 7, 0xFFFF, sum = 0
5281 20:11:37.743278 8, 0xFFFF, sum = 0
5282 20:11:37.746516 9, 0xFFFF, sum = 0
5283 20:11:37.746614 10, 0x0, sum = 1
5284 20:11:37.749485 11, 0x0, sum = 2
5285 20:11:37.749583 12, 0x0, sum = 3
5286 20:11:37.753366 13, 0x0, sum = 4
5287 20:11:37.753449 best_step = 11
5288 20:11:37.753514
5289 20:11:37.753574 ==
5290 20:11:37.756728 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 20:11:37.759548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 20:11:37.759631 ==
5293 20:11:37.762739 RX Vref Scan: 1
5294 20:11:37.762819
5295 20:11:37.766561 RX Vref 0 -> 0, step: 1
5296 20:11:37.766642
5297 20:11:37.766706 RX Delay -69 -> 252, step: 4
5298 20:11:37.766766
5299 20:11:37.769281 Set Vref, RX VrefLevel [Byte0]: 61
5300 20:11:37.772883 [Byte1]: 57
5301 20:11:37.777645
5302 20:11:37.777766 Final RX Vref Byte 0 = 61 to rank0
5303 20:11:37.781138 Final RX Vref Byte 1 = 57 to rank0
5304 20:11:37.784275 Final RX Vref Byte 0 = 61 to rank1
5305 20:11:37.787732 Final RX Vref Byte 1 = 57 to rank1==
5306 20:11:37.790894 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 20:11:37.797289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 20:11:37.797374 ==
5309 20:11:37.797440 DQS Delay:
5310 20:11:37.800831 DQS0 = 0, DQS1 = 0
5311 20:11:37.800912 DQM Delay:
5312 20:11:37.800976 DQM0 = 96, DQM1 = 85
5313 20:11:37.803993 DQ Delay:
5314 20:11:37.807700 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5315 20:11:37.810803 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5316 20:11:37.814259 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =82
5317 20:11:37.817239 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5318 20:11:37.817322
5319 20:11:37.817387
5320 20:11:37.823701 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5321 20:11:37.826791 CH0 RK0: MR19=505, MR18=2910
5322 20:11:37.833409 CH0_RK0: MR19=0x505, MR18=0x2910, DQSOSC=408, MR23=63, INC=65, DEC=43
5323 20:11:37.833501
5324 20:11:37.836911 ----->DramcWriteLeveling(PI) begin...
5325 20:11:37.836996 ==
5326 20:11:37.840038 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 20:11:37.843352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 20:11:37.843436 ==
5329 20:11:37.847354 Write leveling (Byte 0): 33 => 33
5330 20:11:37.850034 Write leveling (Byte 1): 29 => 29
5331 20:11:37.853575 DramcWriteLeveling(PI) end<-----
5332 20:11:37.853670
5333 20:11:37.853737 ==
5334 20:11:37.856719 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 20:11:37.863205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 20:11:37.863315 ==
5337 20:11:37.863408 [Gating] SW mode calibration
5338 20:11:37.872932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5339 20:11:37.876309 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5340 20:11:37.883053 0 14 0 | B1->B0 | 2d2c 3434 | 1 0 | (0 0) (0 0)
5341 20:11:37.886171 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5342 20:11:37.889610 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 20:11:37.896188 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 20:11:37.899227 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 20:11:37.902660 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 20:11:37.909148 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 20:11:37.912587 0 14 28 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5348 20:11:37.916324 0 15 0 | B1->B0 | 3030 2828 | 1 0 | (0 0) (0 0)
5349 20:11:37.922263 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 20:11:37.925893 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 20:11:37.929118 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 20:11:37.936111 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 20:11:37.938782 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 20:11:37.942362 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 20:11:37.945771 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5356 20:11:37.952523 1 0 0 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
5357 20:11:37.955408 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 20:11:37.961890 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 20:11:37.965148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 20:11:37.968688 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 20:11:37.974897 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 20:11:37.978372 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 20:11:37.982280 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 20:11:37.988110 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 20:11:37.991775 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 20:11:37.995295 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 20:11:38.001566 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 20:11:38.004620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 20:11:38.008206 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 20:11:38.014681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 20:11:38.018022 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 20:11:38.021243 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 20:11:38.028179 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 20:11:38.031009 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 20:11:38.034661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 20:11:38.041323 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 20:11:38.044783 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 20:11:38.047786 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 20:11:38.054101 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5380 20:11:38.057779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 20:11:38.060998 Total UI for P1: 0, mck2ui 16
5382 20:11:38.064318 best dqsien dly found for B0: ( 1, 2, 28)
5383 20:11:38.067615 Total UI for P1: 0, mck2ui 16
5384 20:11:38.071020 best dqsien dly found for B1: ( 1, 2, 30)
5385 20:11:38.074136 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5386 20:11:38.077443 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5387 20:11:38.077527
5388 20:11:38.080881 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5389 20:11:38.084336 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5390 20:11:38.087313 [Gating] SW calibration Done
5391 20:11:38.087409 ==
5392 20:11:38.090943 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 20:11:38.094296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 20:11:38.094385 ==
5395 20:11:38.097367 RX Vref Scan: 0
5396 20:11:38.097481
5397 20:11:38.100441 RX Vref 0 -> 0, step: 1
5398 20:11:38.100513
5399 20:11:38.100574 RX Delay -80 -> 252, step: 8
5400 20:11:38.107645 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5401 20:11:38.111005 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5402 20:11:38.113607 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5403 20:11:38.117414 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5404 20:11:38.121004 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5405 20:11:38.123856 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5406 20:11:38.130282 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5407 20:11:38.134385 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5408 20:11:38.137252 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5409 20:11:38.140140 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5410 20:11:38.144016 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5411 20:11:38.150728 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5412 20:11:38.153629 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5413 20:11:38.156978 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5414 20:11:38.160203 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5415 20:11:38.163699 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5416 20:11:38.163784 ==
5417 20:11:38.167048 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 20:11:38.173624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 20:11:38.173723 ==
5420 20:11:38.173798 DQS Delay:
5421 20:11:38.177075 DQS0 = 0, DQS1 = 0
5422 20:11:38.177159 DQM Delay:
5423 20:11:38.180159 DQM0 = 96, DQM1 = 88
5424 20:11:38.180242 DQ Delay:
5425 20:11:38.183650 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5426 20:11:38.186754 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5427 20:11:38.190319 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5428 20:11:38.193262 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5429 20:11:38.193346
5430 20:11:38.193413
5431 20:11:38.193474 ==
5432 20:11:38.196832 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 20:11:38.200016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 20:11:38.200101 ==
5435 20:11:38.200168
5436 20:11:38.200229
5437 20:11:38.203438 TX Vref Scan disable
5438 20:11:38.206377 == TX Byte 0 ==
5439 20:11:38.209781 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5440 20:11:38.212735 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5441 20:11:38.216207 == TX Byte 1 ==
5442 20:11:38.219484 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5443 20:11:38.222836 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5444 20:11:38.222922 ==
5445 20:11:38.226135 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 20:11:38.232574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 20:11:38.232653 ==
5448 20:11:38.232716
5449 20:11:38.232775
5450 20:11:38.232832 TX Vref Scan disable
5451 20:11:38.236995 == TX Byte 0 ==
5452 20:11:38.240427 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5453 20:11:38.246713 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5454 20:11:38.246786 == TX Byte 1 ==
5455 20:11:38.249885 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5456 20:11:38.257140 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5457 20:11:38.257224
5458 20:11:38.257288 [DATLAT]
5459 20:11:38.257348 Freq=933, CH0 RK1
5460 20:11:38.257407
5461 20:11:38.260144 DATLAT Default: 0xb
5462 20:11:38.263549 0, 0xFFFF, sum = 0
5463 20:11:38.263653 1, 0xFFFF, sum = 0
5464 20:11:38.266311 2, 0xFFFF, sum = 0
5465 20:11:38.266378 3, 0xFFFF, sum = 0
5466 20:11:38.269811 4, 0xFFFF, sum = 0
5467 20:11:38.269884 5, 0xFFFF, sum = 0
5468 20:11:38.273365 6, 0xFFFF, sum = 0
5469 20:11:38.273438 7, 0xFFFF, sum = 0
5470 20:11:38.276228 8, 0xFFFF, sum = 0
5471 20:11:38.276300 9, 0xFFFF, sum = 0
5472 20:11:38.279726 10, 0x0, sum = 1
5473 20:11:38.279829 11, 0x0, sum = 2
5474 20:11:38.282757 12, 0x0, sum = 3
5475 20:11:38.282835 13, 0x0, sum = 4
5476 20:11:38.286057 best_step = 11
5477 20:11:38.286137
5478 20:11:38.286200 ==
5479 20:11:38.289310 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 20:11:38.292584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 20:11:38.292661 ==
5482 20:11:38.295914 RX Vref Scan: 0
5483 20:11:38.296015
5484 20:11:38.296133 RX Vref 0 -> 0, step: 1
5485 20:11:38.296200
5486 20:11:38.298882 RX Delay -61 -> 252, step: 4
5487 20:11:38.305899 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5488 20:11:38.308731 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5489 20:11:38.312037 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5490 20:11:38.315594 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5491 20:11:38.318848 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5492 20:11:38.325556 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5493 20:11:38.329019 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5494 20:11:38.332162 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5495 20:11:38.335452 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5496 20:11:38.338680 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5497 20:11:38.345051 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5498 20:11:38.348492 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5499 20:11:38.351937 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5500 20:11:38.354794 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5501 20:11:38.358436 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5502 20:11:38.364645 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5503 20:11:38.364729 ==
5504 20:11:38.367789 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 20:11:38.371200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 20:11:38.371271 ==
5507 20:11:38.371333 DQS Delay:
5508 20:11:38.374534 DQS0 = 0, DQS1 = 0
5509 20:11:38.374608 DQM Delay:
5510 20:11:38.377554 DQM0 = 95, DQM1 = 88
5511 20:11:38.377643 DQ Delay:
5512 20:11:38.381049 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5513 20:11:38.384403 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5514 20:11:38.387984 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5515 20:11:38.391237 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =92
5516 20:11:38.391312
5517 20:11:38.391382
5518 20:11:38.401036 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5519 20:11:38.401120 CH0 RK1: MR19=504, MR18=26F7
5520 20:11:38.407515 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5521 20:11:38.410995 [RxdqsGatingPostProcess] freq 933
5522 20:11:38.417563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5523 20:11:38.420935 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 20:11:38.423894 best DQS1 dly(2T, 0.5T) = (0, 11)
5525 20:11:38.427576 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 20:11:38.430383 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5527 20:11:38.434478 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 20:11:38.434547 best DQS1 dly(2T, 0.5T) = (0, 10)
5529 20:11:38.437250 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 20:11:38.440395 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5531 20:11:38.444149 Pre-setting of DQS Precalculation
5532 20:11:38.450437 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5533 20:11:38.450509 ==
5534 20:11:38.453920 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 20:11:38.456736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 20:11:38.456806 ==
5537 20:11:38.463559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 20:11:38.470376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5539 20:11:38.473386 [CA 0] Center 36 (6~67) winsize 62
5540 20:11:38.476691 [CA 1] Center 37 (6~68) winsize 63
5541 20:11:38.479649 [CA 2] Center 34 (4~65) winsize 62
5542 20:11:38.483650 [CA 3] Center 33 (3~64) winsize 62
5543 20:11:38.486733 [CA 4] Center 34 (4~64) winsize 61
5544 20:11:38.489829 [CA 5] Center 33 (3~64) winsize 62
5545 20:11:38.489900
5546 20:11:38.493008 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5547 20:11:38.493076
5548 20:11:38.496578 [CATrainingPosCal] consider 1 rank data
5549 20:11:38.499910 u2DelayCellTimex100 = 270/100 ps
5550 20:11:38.503228 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 20:11:38.506727 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5552 20:11:38.509830 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5553 20:11:38.512993 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 20:11:38.516743 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 20:11:38.523039 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 20:11:38.523131
5557 20:11:38.526020 CA PerBit enable=1, Macro0, CA PI delay=33
5558 20:11:38.526097
5559 20:11:38.529398 [CBTSetCACLKResult] CA Dly = 33
5560 20:11:38.529472 CS Dly: 5 (0~36)
5561 20:11:38.529534 ==
5562 20:11:38.532980 Dram Type= 6, Freq= 0, CH_1, rank 1
5563 20:11:38.535890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 20:11:38.539419 ==
5565 20:11:38.542673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 20:11:38.549410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5567 20:11:38.552432 [CA 0] Center 37 (7~67) winsize 61
5568 20:11:38.556164 [CA 1] Center 37 (6~68) winsize 63
5569 20:11:38.559063 [CA 2] Center 34 (4~65) winsize 62
5570 20:11:38.562243 [CA 3] Center 33 (3~64) winsize 62
5571 20:11:38.565857 [CA 4] Center 34 (4~65) winsize 62
5572 20:11:38.569274 [CA 5] Center 33 (3~64) winsize 62
5573 20:11:38.569358
5574 20:11:38.572481 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5575 20:11:38.572566
5576 20:11:38.575590 [CATrainingPosCal] consider 2 rank data
5577 20:11:38.579437 u2DelayCellTimex100 = 270/100 ps
5578 20:11:38.582593 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5579 20:11:38.585597 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5580 20:11:38.589045 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5581 20:11:38.595735 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 20:11:38.599579 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 20:11:38.602616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 20:11:38.602727
5585 20:11:38.605398 CA PerBit enable=1, Macro0, CA PI delay=33
5586 20:11:38.605503
5587 20:11:38.608887 [CBTSetCACLKResult] CA Dly = 33
5588 20:11:38.608965 CS Dly: 6 (0~38)
5589 20:11:38.609074
5590 20:11:38.612623 ----->DramcWriteLeveling(PI) begin...
5591 20:11:38.615544 ==
5592 20:11:38.615643 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 20:11:38.622026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 20:11:38.622111 ==
5595 20:11:38.625598 Write leveling (Byte 0): 26 => 26
5596 20:11:38.628620 Write leveling (Byte 1): 27 => 27
5597 20:11:38.632245 DramcWriteLeveling(PI) end<-----
5598 20:11:38.632314
5599 20:11:38.632375 ==
5600 20:11:38.635654 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 20:11:38.638916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 20:11:38.639058 ==
5603 20:11:38.641894 [Gating] SW mode calibration
5604 20:11:38.648613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5605 20:11:38.652142 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5606 20:11:38.658924 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 20:11:38.662053 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 20:11:38.665308 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 20:11:38.671546 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 20:11:38.675284 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 20:11:38.678430 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5612 20:11:38.685198 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5613 20:11:38.688760 0 14 28 | B1->B0 | 2e2e 2727 | 1 0 | (1 0) (1 0)
5614 20:11:38.692368 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5615 20:11:38.698628 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 20:11:38.701474 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 20:11:38.705072 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 20:11:38.711744 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 20:11:38.714853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 20:11:38.718419 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 20:11:38.724701 0 15 28 | B1->B0 | 3535 3a3a | 0 0 | (0 0) (0 0)
5622 20:11:38.728190 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5623 20:11:38.731498 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 20:11:38.737899 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 20:11:38.741594 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 20:11:38.744212 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 20:11:38.751946 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 20:11:38.754311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5629 20:11:38.757796 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5630 20:11:38.764128 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 20:11:38.767515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 20:11:38.771065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 20:11:38.777774 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 20:11:38.780750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 20:11:38.784018 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 20:11:38.790862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 20:11:38.793879 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 20:11:38.797182 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 20:11:38.803621 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 20:11:38.806939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 20:11:38.810683 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 20:11:38.816849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 20:11:38.820384 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 20:11:38.823858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 20:11:38.830448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5646 20:11:38.833549 Total UI for P1: 0, mck2ui 16
5647 20:11:38.836627 best dqsien dly found for B0: ( 1, 2, 24)
5648 20:11:38.840051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 20:11:38.843515 Total UI for P1: 0, mck2ui 16
5650 20:11:38.846611 best dqsien dly found for B1: ( 1, 2, 26)
5651 20:11:38.849907 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5652 20:11:38.853222 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5653 20:11:38.853303
5654 20:11:38.856536 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5655 20:11:38.863159 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5656 20:11:38.863240 [Gating] SW calibration Done
5657 20:11:38.863307 ==
5658 20:11:38.866969 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 20:11:38.872765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 20:11:38.872845 ==
5661 20:11:38.872932 RX Vref Scan: 0
5662 20:11:38.872995
5663 20:11:38.875831 RX Vref 0 -> 0, step: 1
5664 20:11:38.875928
5665 20:11:38.879662 RX Delay -80 -> 252, step: 8
5666 20:11:38.882366 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5667 20:11:38.885569 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5668 20:11:38.888970 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5669 20:11:38.895580 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5670 20:11:38.899051 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5671 20:11:38.902405 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5672 20:11:38.905530 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5673 20:11:38.908657 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 20:11:38.912157 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5675 20:11:38.918610 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5676 20:11:38.922060 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5677 20:11:38.925462 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5678 20:11:38.928443 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5679 20:11:38.931939 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5680 20:11:38.938287 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5681 20:11:38.941787 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5682 20:11:38.941857 ==
5683 20:11:38.945200 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 20:11:38.948444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 20:11:38.948518 ==
5686 20:11:38.951666 DQS Delay:
5687 20:11:38.951750 DQS0 = 0, DQS1 = 0
5688 20:11:38.951812 DQM Delay:
5689 20:11:38.954928 DQM0 = 100, DQM1 = 90
5690 20:11:38.955011 DQ Delay:
5691 20:11:38.958357 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5692 20:11:38.961520 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5693 20:11:38.965236 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5694 20:11:38.968566 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5695 20:11:38.968684
5696 20:11:38.968777
5697 20:11:38.968882 ==
5698 20:11:38.971791 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 20:11:38.978170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 20:11:38.978289 ==
5701 20:11:38.978384
5702 20:11:38.978489
5703 20:11:38.981528 TX Vref Scan disable
5704 20:11:38.981621 == TX Byte 0 ==
5705 20:11:38.985001 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5706 20:11:38.991491 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5707 20:11:38.991595 == TX Byte 1 ==
5708 20:11:38.994825 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5709 20:11:39.001489 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5710 20:11:39.001611 ==
5711 20:11:39.004697 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 20:11:39.007807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 20:11:39.007888 ==
5714 20:11:39.007953
5715 20:11:39.008015
5716 20:11:39.011268 TX Vref Scan disable
5717 20:11:39.014498 == TX Byte 0 ==
5718 20:11:39.018376 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5719 20:11:39.020835 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5720 20:11:39.024265 == TX Byte 1 ==
5721 20:11:39.027790 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5722 20:11:39.030993 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5723 20:11:39.031109
5724 20:11:39.034357 [DATLAT]
5725 20:11:39.034473 Freq=933, CH1 RK0
5726 20:11:39.034566
5727 20:11:39.038129 DATLAT Default: 0xd
5728 20:11:39.038237 0, 0xFFFF, sum = 0
5729 20:11:39.041006 1, 0xFFFF, sum = 0
5730 20:11:39.041125 2, 0xFFFF, sum = 0
5731 20:11:39.044279 3, 0xFFFF, sum = 0
5732 20:11:39.044367 4, 0xFFFF, sum = 0
5733 20:11:39.047789 5, 0xFFFF, sum = 0
5734 20:11:39.047903 6, 0xFFFF, sum = 0
5735 20:11:39.050754 7, 0xFFFF, sum = 0
5736 20:11:39.050874 8, 0xFFFF, sum = 0
5737 20:11:39.053962 9, 0xFFFF, sum = 0
5738 20:11:39.054066 10, 0x0, sum = 1
5739 20:11:39.057176 11, 0x0, sum = 2
5740 20:11:39.057293 12, 0x0, sum = 3
5741 20:11:39.060256 13, 0x0, sum = 4
5742 20:11:39.060334 best_step = 11
5743 20:11:39.060417
5744 20:11:39.060480 ==
5745 20:11:39.063836 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 20:11:39.070566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 20:11:39.070686 ==
5748 20:11:39.070781 RX Vref Scan: 1
5749 20:11:39.070876
5750 20:11:39.074204 RX Vref 0 -> 0, step: 1
5751 20:11:39.074311
5752 20:11:39.076884 RX Delay -61 -> 252, step: 4
5753 20:11:39.076981
5754 20:11:39.080337 Set Vref, RX VrefLevel [Byte0]: 49
5755 20:11:39.083329 [Byte1]: 53
5756 20:11:39.083407
5757 20:11:39.087160 Final RX Vref Byte 0 = 49 to rank0
5758 20:11:39.090204 Final RX Vref Byte 1 = 53 to rank0
5759 20:11:39.093547 Final RX Vref Byte 0 = 49 to rank1
5760 20:11:39.096781 Final RX Vref Byte 1 = 53 to rank1==
5761 20:11:39.100096 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 20:11:39.103266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 20:11:39.103342 ==
5764 20:11:39.106378 DQS Delay:
5765 20:11:39.106452 DQS0 = 0, DQS1 = 0
5766 20:11:39.109672 DQM Delay:
5767 20:11:39.109755 DQM0 = 100, DQM1 = 93
5768 20:11:39.109821 DQ Delay:
5769 20:11:39.113346 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5770 20:11:39.116170 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5771 20:11:39.119687 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5772 20:11:39.126164 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5773 20:11:39.126252
5774 20:11:39.126318
5775 20:11:39.132748 [DQSOSCAuto] RK0, (LSB)MR18= 0x1606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5776 20:11:39.135848 CH1 RK0: MR19=505, MR18=1606
5777 20:11:39.142831 CH1_RK0: MR19=0x505, MR18=0x1606, DQSOSC=414, MR23=63, INC=63, DEC=42
5778 20:11:39.142908
5779 20:11:39.146184 ----->DramcWriteLeveling(PI) begin...
5780 20:11:39.146263 ==
5781 20:11:39.149187 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 20:11:39.152537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 20:11:39.152606 ==
5784 20:11:39.155854 Write leveling (Byte 0): 28 => 28
5785 20:11:39.159225 Write leveling (Byte 1): 30 => 30
5786 20:11:39.162410 DramcWriteLeveling(PI) end<-----
5787 20:11:39.162485
5788 20:11:39.162548 ==
5789 20:11:39.165883 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 20:11:39.168891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 20:11:39.172309 ==
5792 20:11:39.172422 [Gating] SW mode calibration
5793 20:11:39.179375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 20:11:39.185728 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 20:11:39.188764 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5796 20:11:39.195530 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 20:11:39.198513 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 20:11:39.202223 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 20:11:39.208609 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 20:11:39.212333 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 20:11:39.215252 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5802 20:11:39.221650 0 14 28 | B1->B0 | 2a2a 2f2f | 0 0 | (1 1) (1 0)
5803 20:11:39.225099 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 20:11:39.228305 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 20:11:39.234902 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 20:11:39.238152 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 20:11:39.241651 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 20:11:39.248269 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 20:11:39.251558 0 15 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5810 20:11:39.255048 0 15 28 | B1->B0 | 3c3c 3333 | 0 0 | (0 0) (0 0)
5811 20:11:39.261585 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 20:11:39.265181 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 20:11:39.267980 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 20:11:39.274705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 20:11:39.278148 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 20:11:39.281320 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 20:11:39.287593 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 20:11:39.291004 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5819 20:11:39.294485 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 20:11:39.300768 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 20:11:39.304535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 20:11:39.307571 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 20:11:39.313798 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 20:11:39.317310 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 20:11:39.321041 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 20:11:39.327301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 20:11:39.330249 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 20:11:39.333705 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 20:11:39.340205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 20:11:39.343916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 20:11:39.347576 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 20:11:39.353577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 20:11:39.357002 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 20:11:39.360064 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 20:11:39.366495 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 20:11:39.369811 Total UI for P1: 0, mck2ui 16
5837 20:11:39.373631 best dqsien dly found for B0: ( 1, 2, 28)
5838 20:11:39.373709 Total UI for P1: 0, mck2ui 16
5839 20:11:39.379979 best dqsien dly found for B1: ( 1, 2, 28)
5840 20:11:39.382799 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5841 20:11:39.386581 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5842 20:11:39.386655
5843 20:11:39.390042 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5844 20:11:39.393190 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5845 20:11:39.396661 [Gating] SW calibration Done
5846 20:11:39.396732 ==
5847 20:11:39.399562 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 20:11:39.403081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 20:11:39.403159 ==
5850 20:11:39.405920 RX Vref Scan: 0
5851 20:11:39.405995
5852 20:11:39.409470 RX Vref 0 -> 0, step: 1
5853 20:11:39.409562
5854 20:11:39.409625 RX Delay -80 -> 252, step: 8
5855 20:11:39.416195 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 20:11:39.419768 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5857 20:11:39.422769 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5858 20:11:39.425880 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5859 20:11:39.429672 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 20:11:39.432807 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5861 20:11:39.439075 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5862 20:11:39.442627 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 20:11:39.445704 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5864 20:11:39.449086 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5865 20:11:39.452560 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5866 20:11:39.458781 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5867 20:11:39.462214 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5868 20:11:39.465479 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5869 20:11:39.468850 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 20:11:39.471903 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5871 20:11:39.472018 ==
5872 20:11:39.475090 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 20:11:39.481685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 20:11:39.481767 ==
5875 20:11:39.481832 DQS Delay:
5876 20:11:39.484843 DQS0 = 0, DQS1 = 0
5877 20:11:39.484936 DQM Delay:
5878 20:11:39.488157 DQM0 = 100, DQM1 = 91
5879 20:11:39.488231 DQ Delay:
5880 20:11:39.491562 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5881 20:11:39.495857 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5882 20:11:39.497910 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =87
5883 20:11:39.501787 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5884 20:11:39.501863
5885 20:11:39.501927
5886 20:11:39.501987 ==
5887 20:11:39.505077 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 20:11:39.508040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 20:11:39.508119 ==
5890 20:11:39.508184
5891 20:11:39.508252
5892 20:11:39.511343 TX Vref Scan disable
5893 20:11:39.515027 == TX Byte 0 ==
5894 20:11:39.518338 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5895 20:11:39.521201 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5896 20:11:39.525127 == TX Byte 1 ==
5897 20:11:39.527996 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5898 20:11:39.530917 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5899 20:11:39.530994 ==
5900 20:11:39.534428 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 20:11:39.541131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 20:11:39.541205 ==
5903 20:11:39.541273
5904 20:11:39.541331
5905 20:11:39.541387 TX Vref Scan disable
5906 20:11:39.545080 == TX Byte 0 ==
5907 20:11:39.548335 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5908 20:11:39.555233 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5909 20:11:39.555319 == TX Byte 1 ==
5910 20:11:39.558051 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5911 20:11:39.565062 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5912 20:11:39.565151
5913 20:11:39.565212 [DATLAT]
5914 20:11:39.565276 Freq=933, CH1 RK1
5915 20:11:39.565332
5916 20:11:39.568599 DATLAT Default: 0xb
5917 20:11:39.571325 0, 0xFFFF, sum = 0
5918 20:11:39.571417 1, 0xFFFF, sum = 0
5919 20:11:39.574421 2, 0xFFFF, sum = 0
5920 20:11:39.574510 3, 0xFFFF, sum = 0
5921 20:11:39.578005 4, 0xFFFF, sum = 0
5922 20:11:39.578093 5, 0xFFFF, sum = 0
5923 20:11:39.581272 6, 0xFFFF, sum = 0
5924 20:11:39.581379 7, 0xFFFF, sum = 0
5925 20:11:39.584629 8, 0xFFFF, sum = 0
5926 20:11:39.584735 9, 0xFFFF, sum = 0
5927 20:11:39.587822 10, 0x0, sum = 1
5928 20:11:39.587930 11, 0x0, sum = 2
5929 20:11:39.591355 12, 0x0, sum = 3
5930 20:11:39.591422 13, 0x0, sum = 4
5931 20:11:39.594098 best_step = 11
5932 20:11:39.594169
5933 20:11:39.594249 ==
5934 20:11:39.597685 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 20:11:39.600938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 20:11:39.601033 ==
5937 20:11:39.601134 RX Vref Scan: 0
5938 20:11:39.604142
5939 20:11:39.604228 RX Vref 0 -> 0, step: 1
5940 20:11:39.604327
5941 20:11:39.607304 RX Delay -69 -> 252, step: 4
5942 20:11:39.614475 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5943 20:11:39.617536 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5944 20:11:39.621117 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5945 20:11:39.624213 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5946 20:11:39.627763 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5947 20:11:39.634191 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5948 20:11:39.637338 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5949 20:11:39.640802 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5950 20:11:39.644065 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5951 20:11:39.647256 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5952 20:11:39.650827 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5953 20:11:39.657215 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5954 20:11:39.661003 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5955 20:11:39.663593 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
5956 20:11:39.667024 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5957 20:11:39.674097 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5958 20:11:39.674177 ==
5959 20:11:39.677369 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 20:11:39.680610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 20:11:39.680711 ==
5962 20:11:39.680800 DQS Delay:
5963 20:11:39.683578 DQS0 = 0, DQS1 = 0
5964 20:11:39.683698 DQM Delay:
5965 20:11:39.687095 DQM0 = 101, DQM1 = 93
5966 20:11:39.687173 DQ Delay:
5967 20:11:39.690129 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5968 20:11:39.693332 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =96
5969 20:11:39.696600 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =84
5970 20:11:39.700206 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5971 20:11:39.700291
5972 20:11:39.700357
5973 20:11:39.710336 [DQSOSCAuto] RK1, (LSB)MR18= 0x5fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5974 20:11:39.710464 CH1 RK1: MR19=504, MR18=5FE
5975 20:11:39.716440 CH1_RK1: MR19=0x504, MR18=0x5FE, DQSOSC=420, MR23=63, INC=61, DEC=40
5976 20:11:39.719927 [RxdqsGatingPostProcess] freq 933
5977 20:11:39.726635 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 20:11:39.729915 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 20:11:39.733324 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 20:11:39.736424 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 20:11:39.739796 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 20:11:39.743147 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 20:11:39.746237 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 20:11:39.749502 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 20:11:39.753010 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 20:11:39.753087 Pre-setting of DQS Precalculation
5987 20:11:39.759313 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 20:11:39.766360 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 20:11:39.772944 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 20:11:39.773023
5991 20:11:39.773086
5992 20:11:39.775916 [Calibration Summary] 1866 Mbps
5993 20:11:39.779172 CH 0, Rank 0
5994 20:11:39.779240 SW Impedance : PASS
5995 20:11:39.782889 DUTY Scan : NO K
5996 20:11:39.785917 ZQ Calibration : PASS
5997 20:11:39.785988 Jitter Meter : NO K
5998 20:11:39.789315 CBT Training : PASS
5999 20:11:39.792304 Write leveling : PASS
6000 20:11:39.792380 RX DQS gating : PASS
6001 20:11:39.795468 RX DQ/DQS(RDDQC) : PASS
6002 20:11:39.798769 TX DQ/DQS : PASS
6003 20:11:39.798862 RX DATLAT : PASS
6004 20:11:39.802134 RX DQ/DQS(Engine): PASS
6005 20:11:39.805717 TX OE : NO K
6006 20:11:39.805799 All Pass.
6007 20:11:39.805864
6008 20:11:39.805923 CH 0, Rank 1
6009 20:11:39.809163 SW Impedance : PASS
6010 20:11:39.812123 DUTY Scan : NO K
6011 20:11:39.812193 ZQ Calibration : PASS
6012 20:11:39.815413 Jitter Meter : NO K
6013 20:11:39.815480 CBT Training : PASS
6014 20:11:39.818624 Write leveling : PASS
6015 20:11:39.821871 RX DQS gating : PASS
6016 20:11:39.821944 RX DQ/DQS(RDDQC) : PASS
6017 20:11:39.825272 TX DQ/DQS : PASS
6018 20:11:39.828806 RX DATLAT : PASS
6019 20:11:39.828900 RX DQ/DQS(Engine): PASS
6020 20:11:39.832030 TX OE : NO K
6021 20:11:39.832109 All Pass.
6022 20:11:39.832210
6023 20:11:39.835285 CH 1, Rank 0
6024 20:11:39.835359 SW Impedance : PASS
6025 20:11:39.838515 DUTY Scan : NO K
6026 20:11:39.841423 ZQ Calibration : PASS
6027 20:11:39.841494 Jitter Meter : NO K
6028 20:11:39.845027 CBT Training : PASS
6029 20:11:39.848491 Write leveling : PASS
6030 20:11:39.848560 RX DQS gating : PASS
6031 20:11:39.851844 RX DQ/DQS(RDDQC) : PASS
6032 20:11:39.854874 TX DQ/DQS : PASS
6033 20:11:39.854962 RX DATLAT : PASS
6034 20:11:39.858134 RX DQ/DQS(Engine): PASS
6035 20:11:39.861962 TX OE : NO K
6036 20:11:39.862041 All Pass.
6037 20:11:39.862136
6038 20:11:39.862194 CH 1, Rank 1
6039 20:11:39.864917 SW Impedance : PASS
6040 20:11:39.868069 DUTY Scan : NO K
6041 20:11:39.868169 ZQ Calibration : PASS
6042 20:11:39.871329 Jitter Meter : NO K
6043 20:11:39.874677 CBT Training : PASS
6044 20:11:39.874760 Write leveling : PASS
6045 20:11:39.878181 RX DQS gating : PASS
6046 20:11:39.881181 RX DQ/DQS(RDDQC) : PASS
6047 20:11:39.881291 TX DQ/DQS : PASS
6048 20:11:39.884424 RX DATLAT : PASS
6049 20:11:39.888001 RX DQ/DQS(Engine): PASS
6050 20:11:39.888076 TX OE : NO K
6051 20:11:39.888147 All Pass.
6052 20:11:39.891036
6053 20:11:39.891132 DramC Write-DBI off
6054 20:11:39.894355 PER_BANK_REFRESH: Hybrid Mode
6055 20:11:39.894426 TX_TRACKING: ON
6056 20:11:39.904107 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 20:11:39.907827 [FAST_K] Save calibration result to emmc
6058 20:11:39.910880 dramc_set_vcore_voltage set vcore to 650000
6059 20:11:39.914257 Read voltage for 400, 6
6060 20:11:39.914370 Vio18 = 0
6061 20:11:39.917199 Vcore = 650000
6062 20:11:39.917275 Vdram = 0
6063 20:11:39.917337 Vddq = 0
6064 20:11:39.917397 Vmddr = 0
6065 20:11:39.924134 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 20:11:39.930622 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 20:11:39.930706 MEM_TYPE=3, freq_sel=20
6068 20:11:39.934087 sv_algorithm_assistance_LP4_800
6069 20:11:39.936964 ============ PULL DRAM RESETB DOWN ============
6070 20:11:39.943864 ========== PULL DRAM RESETB DOWN end =========
6071 20:11:39.947259 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 20:11:39.951027 ===================================
6073 20:11:39.953611 LPDDR4 DRAM CONFIGURATION
6074 20:11:39.956689 ===================================
6075 20:11:39.956772 EX_ROW_EN[0] = 0x0
6076 20:11:39.960233 EX_ROW_EN[1] = 0x0
6077 20:11:39.963408 LP4Y_EN = 0x0
6078 20:11:39.963495 WORK_FSP = 0x0
6079 20:11:39.967052 WL = 0x2
6080 20:11:39.967127 RL = 0x2
6081 20:11:39.970541 BL = 0x2
6082 20:11:39.970623 RPST = 0x0
6083 20:11:39.973768 RD_PRE = 0x0
6084 20:11:39.973840 WR_PRE = 0x1
6085 20:11:39.976839 WR_PST = 0x0
6086 20:11:39.976910 DBI_WR = 0x0
6087 20:11:39.980233 DBI_RD = 0x0
6088 20:11:39.980304 OTF = 0x1
6089 20:11:39.983760 ===================================
6090 20:11:39.986838 ===================================
6091 20:11:39.990213 ANA top config
6092 20:11:39.993285 ===================================
6093 20:11:39.993403 DLL_ASYNC_EN = 0
6094 20:11:39.996726 ALL_SLAVE_EN = 1
6095 20:11:39.999676 NEW_RANK_MODE = 1
6096 20:11:40.003129 DLL_IDLE_MODE = 1
6097 20:11:40.006615 LP45_APHY_COMB_EN = 1
6098 20:11:40.006724 TX_ODT_DIS = 1
6099 20:11:40.009669 NEW_8X_MODE = 1
6100 20:11:40.013796 ===================================
6101 20:11:40.016343 ===================================
6102 20:11:40.019636 data_rate = 800
6103 20:11:40.022939 CKR = 1
6104 20:11:40.026231 DQ_P2S_RATIO = 4
6105 20:11:40.029546 ===================================
6106 20:11:40.032588 CA_P2S_RATIO = 4
6107 20:11:40.032676 DQ_CA_OPEN = 0
6108 20:11:40.035954 DQ_SEMI_OPEN = 1
6109 20:11:40.039605 CA_SEMI_OPEN = 1
6110 20:11:40.043009 CA_FULL_RATE = 0
6111 20:11:40.045819 DQ_CKDIV4_EN = 0
6112 20:11:40.048976 CA_CKDIV4_EN = 1
6113 20:11:40.049064 CA_PREDIV_EN = 0
6114 20:11:40.052301 PH8_DLY = 0
6115 20:11:40.055909 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 20:11:40.059301 DQ_AAMCK_DIV = 0
6117 20:11:40.062268 CA_AAMCK_DIV = 0
6118 20:11:40.066032 CA_ADMCK_DIV = 4
6119 20:11:40.068732 DQ_TRACK_CA_EN = 0
6120 20:11:40.068804 CA_PICK = 800
6121 20:11:40.072641 CA_MCKIO = 400
6122 20:11:40.075499 MCKIO_SEMI = 400
6123 20:11:40.078814 PLL_FREQ = 3016
6124 20:11:40.081842 DQ_UI_PI_RATIO = 32
6125 20:11:40.085609 CA_UI_PI_RATIO = 32
6126 20:11:40.088703 ===================================
6127 20:11:40.092137 ===================================
6128 20:11:40.094912 memory_type:LPDDR4
6129 20:11:40.094994 GP_NUM : 10
6130 20:11:40.098302 SRAM_EN : 1
6131 20:11:40.098408 MD32_EN : 0
6132 20:11:40.101649 ===================================
6133 20:11:40.105109 [ANA_INIT] >>>>>>>>>>>>>>
6134 20:11:40.108386 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 20:11:40.111545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 20:11:40.114839 ===================================
6137 20:11:40.118199 data_rate = 800,PCW = 0X7400
6138 20:11:40.121809 ===================================
6139 20:11:40.124952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 20:11:40.131384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 20:11:40.141538 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 20:11:40.144777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 20:11:40.148119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 20:11:40.151325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 20:11:40.155257 [ANA_INIT] flow start
6146 20:11:40.158386 [ANA_INIT] PLL >>>>>>>>
6147 20:11:40.158497 [ANA_INIT] PLL <<<<<<<<
6148 20:11:40.161117 [ANA_INIT] MIDPI >>>>>>>>
6149 20:11:40.164754 [ANA_INIT] MIDPI <<<<<<<<
6150 20:11:40.167784 [ANA_INIT] DLL >>>>>>>>
6151 20:11:40.167885 [ANA_INIT] flow end
6152 20:11:40.171300 ============ LP4 DIFF to SE enter ============
6153 20:11:40.178101 ============ LP4 DIFF to SE exit ============
6154 20:11:40.178206 [ANA_INIT] <<<<<<<<<<<<<
6155 20:11:40.180977 [Flow] Enable top DCM control >>>>>
6156 20:11:40.184236 [Flow] Enable top DCM control <<<<<
6157 20:11:40.187500 Enable DLL master slave shuffle
6158 20:11:40.194162 ==============================================================
6159 20:11:40.194236 Gating Mode config
6160 20:11:40.201311 ==============================================================
6161 20:11:40.204029 Config description:
6162 20:11:40.214062 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 20:11:40.220343 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 20:11:40.223612 SELPH_MODE 0: By rank 1: By Phase
6165 20:11:40.230302 ==============================================================
6166 20:11:40.233723 GAT_TRACK_EN = 0
6167 20:11:40.237269 RX_GATING_MODE = 2
6168 20:11:40.240062 RX_GATING_TRACK_MODE = 2
6169 20:11:40.240143 SELPH_MODE = 1
6170 20:11:40.243860 PICG_EARLY_EN = 1
6171 20:11:40.246953 VALID_LAT_VALUE = 1
6172 20:11:40.253247 ==============================================================
6173 20:11:40.257003 Enter into Gating configuration >>>>
6174 20:11:40.260013 Exit from Gating configuration <<<<
6175 20:11:40.263275 Enter into DVFS_PRE_config >>>>>
6176 20:11:40.273120 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 20:11:40.276640 Exit from DVFS_PRE_config <<<<<
6178 20:11:40.279861 Enter into PICG configuration >>>>
6179 20:11:40.283100 Exit from PICG configuration <<<<
6180 20:11:40.286394 [RX_INPUT] configuration >>>>>
6181 20:11:40.289660 [RX_INPUT] configuration <<<<<
6182 20:11:40.293097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 20:11:40.299912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 20:11:40.306010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 20:11:40.312902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 20:11:40.319306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 20:11:40.326721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 20:11:40.329776 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 20:11:40.332697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 20:11:40.336003 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 20:11:40.342722 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 20:11:40.346165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 20:11:40.349421 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 20:11:40.352121 ===================================
6195 20:11:40.356036 LPDDR4 DRAM CONFIGURATION
6196 20:11:40.359202 ===================================
6197 20:11:40.359282 EX_ROW_EN[0] = 0x0
6198 20:11:40.362210 EX_ROW_EN[1] = 0x0
6199 20:11:40.365730 LP4Y_EN = 0x0
6200 20:11:40.365837 WORK_FSP = 0x0
6201 20:11:40.368980 WL = 0x2
6202 20:11:40.369066 RL = 0x2
6203 20:11:40.372306 BL = 0x2
6204 20:11:40.372387 RPST = 0x0
6205 20:11:40.375603 RD_PRE = 0x0
6206 20:11:40.375720 WR_PRE = 0x1
6207 20:11:40.379138 WR_PST = 0x0
6208 20:11:40.379240 DBI_WR = 0x0
6209 20:11:40.382279 DBI_RD = 0x0
6210 20:11:40.382395 OTF = 0x1
6211 20:11:40.385800 ===================================
6212 20:11:40.388650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 20:11:40.395189 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 20:11:40.398797 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 20:11:40.402260 ===================================
6216 20:11:40.405137 LPDDR4 DRAM CONFIGURATION
6217 20:11:40.408773 ===================================
6218 20:11:40.408891 EX_ROW_EN[0] = 0x10
6219 20:11:40.411999 EX_ROW_EN[1] = 0x0
6220 20:11:40.415480 LP4Y_EN = 0x0
6221 20:11:40.415584 WORK_FSP = 0x0
6222 20:11:40.418434 WL = 0x2
6223 20:11:40.418532 RL = 0x2
6224 20:11:40.421792 BL = 0x2
6225 20:11:40.421869 RPST = 0x0
6226 20:11:40.425248 RD_PRE = 0x0
6227 20:11:40.425364 WR_PRE = 0x1
6228 20:11:40.428704 WR_PST = 0x0
6229 20:11:40.428779 DBI_WR = 0x0
6230 20:11:40.431621 DBI_RD = 0x0
6231 20:11:40.431717 OTF = 0x1
6232 20:11:40.434931 ===================================
6233 20:11:40.441256 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 20:11:40.445599 nWR fixed to 30
6235 20:11:40.449125 [ModeRegInit_LP4] CH0 RK0
6236 20:11:40.449246 [ModeRegInit_LP4] CH0 RK1
6237 20:11:40.452565 [ModeRegInit_LP4] CH1 RK0
6238 20:11:40.455682 [ModeRegInit_LP4] CH1 RK1
6239 20:11:40.455759 match AC timing 19
6240 20:11:40.462079 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 20:11:40.465560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 20:11:40.468624 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 20:11:40.475706 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 20:11:40.478725 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 20:11:40.478804 ==
6246 20:11:40.482473 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 20:11:40.485585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 20:11:40.485662 ==
6249 20:11:40.492188 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 20:11:40.499237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6251 20:11:40.501966 [CA 0] Center 36 (8~64) winsize 57
6252 20:11:40.505195 [CA 1] Center 36 (8~64) winsize 57
6253 20:11:40.508796 [CA 2] Center 36 (8~64) winsize 57
6254 20:11:40.511971 [CA 3] Center 36 (8~64) winsize 57
6255 20:11:40.515266 [CA 4] Center 36 (8~64) winsize 57
6256 20:11:40.518436 [CA 5] Center 36 (8~64) winsize 57
6257 20:11:40.518546
6258 20:11:40.521912 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6259 20:11:40.522017
6260 20:11:40.524811 [CATrainingPosCal] consider 1 rank data
6261 20:11:40.528681 u2DelayCellTimex100 = 270/100 ps
6262 20:11:40.531378 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 20:11:40.534826 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 20:11:40.538202 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 20:11:40.541556 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 20:11:40.544841 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 20:11:40.548302 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 20:11:40.548410
6269 20:11:40.551276 CA PerBit enable=1, Macro0, CA PI delay=36
6270 20:11:40.555403
6271 20:11:40.555485 [CBTSetCACLKResult] CA Dly = 36
6272 20:11:40.558425 CS Dly: 1 (0~32)
6273 20:11:40.558527 ==
6274 20:11:40.561162 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 20:11:40.564816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 20:11:40.564894 ==
6277 20:11:40.571268 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 20:11:40.577474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6279 20:11:40.581318 [CA 0] Center 36 (8~64) winsize 57
6280 20:11:40.584807 [CA 1] Center 36 (8~64) winsize 57
6281 20:11:40.587206 [CA 2] Center 36 (8~64) winsize 57
6282 20:11:40.590701 [CA 3] Center 36 (8~64) winsize 57
6283 20:11:40.594130 [CA 4] Center 36 (8~64) winsize 57
6284 20:11:40.594204 [CA 5] Center 36 (8~64) winsize 57
6285 20:11:40.597232
6286 20:11:40.600873 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6287 20:11:40.600959
6288 20:11:40.604351 [CATrainingPosCal] consider 2 rank data
6289 20:11:40.607882 u2DelayCellTimex100 = 270/100 ps
6290 20:11:40.610415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 20:11:40.614055 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 20:11:40.617209 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 20:11:40.621015 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 20:11:40.623438 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 20:11:40.627059 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 20:11:40.627137
6297 20:11:40.630732 CA PerBit enable=1, Macro0, CA PI delay=36
6298 20:11:40.630810
6299 20:11:40.633504 [CBTSetCACLKResult] CA Dly = 36
6300 20:11:40.636902 CS Dly: 1 (0~32)
6301 20:11:40.637020
6302 20:11:40.640037 ----->DramcWriteLeveling(PI) begin...
6303 20:11:40.640116 ==
6304 20:11:40.643283 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 20:11:40.646789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 20:11:40.646867 ==
6307 20:11:40.650063 Write leveling (Byte 0): 40 => 8
6308 20:11:40.653040 Write leveling (Byte 1): 32 => 0
6309 20:11:40.656329 DramcWriteLeveling(PI) end<-----
6310 20:11:40.656405
6311 20:11:40.656467 ==
6312 20:11:40.659891 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 20:11:40.663220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 20:11:40.666101 ==
6315 20:11:40.666178 [Gating] SW mode calibration
6316 20:11:40.672806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 20:11:40.679681 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 20:11:40.682565 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 20:11:40.689559 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 20:11:40.692751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 20:11:40.696118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 20:11:40.702346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 20:11:40.705790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 20:11:40.708814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 20:11:40.715569 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 20:11:40.719157 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 20:11:40.722148 Total UI for P1: 0, mck2ui 16
6328 20:11:40.725304 best dqsien dly found for B0: ( 0, 14, 24)
6329 20:11:40.728983 Total UI for P1: 0, mck2ui 16
6330 20:11:40.732425 best dqsien dly found for B1: ( 0, 14, 24)
6331 20:11:40.735284 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 20:11:40.738715 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 20:11:40.738795
6334 20:11:40.741898 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 20:11:40.748675 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 20:11:40.748761 [Gating] SW calibration Done
6337 20:11:40.748827 ==
6338 20:11:40.751928 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 20:11:40.758597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 20:11:40.758681 ==
6341 20:11:40.758754 RX Vref Scan: 0
6342 20:11:40.758823
6343 20:11:40.761828 RX Vref 0 -> 0, step: 1
6344 20:11:40.761908
6345 20:11:40.765730 RX Delay -410 -> 252, step: 16
6346 20:11:40.768113 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 20:11:40.771885 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 20:11:40.777952 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 20:11:40.781623 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 20:11:40.784940 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6351 20:11:40.788886 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6352 20:11:40.794951 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6353 20:11:40.798233 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6354 20:11:40.801870 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6355 20:11:40.804631 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 20:11:40.811036 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6357 20:11:40.814578 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6358 20:11:40.817885 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6359 20:11:40.824100 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6360 20:11:40.827647 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 20:11:40.830777 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6362 20:11:40.830851 ==
6363 20:11:40.834116 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 20:11:40.840881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 20:11:40.840966 ==
6366 20:11:40.841031 DQS Delay:
6367 20:11:40.843763 DQS0 = 43, DQS1 = 59
6368 20:11:40.843831 DQM Delay:
6369 20:11:40.843898 DQM0 = 10, DQM1 = 11
6370 20:11:40.847165 DQ Delay:
6371 20:11:40.850255 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6372 20:11:40.850322 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6373 20:11:40.853888 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6374 20:11:40.857625 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6375 20:11:40.857699
6376 20:11:40.860560
6377 20:11:40.860639 ==
6378 20:11:40.863680 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 20:11:40.867601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 20:11:40.867681 ==
6381 20:11:40.867745
6382 20:11:40.867803
6383 20:11:40.870427 TX Vref Scan disable
6384 20:11:40.870497 == TX Byte 0 ==
6385 20:11:40.873608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 20:11:40.880276 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 20:11:40.880354 == TX Byte 1 ==
6388 20:11:40.883674 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 20:11:40.890155 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 20:11:40.890235 ==
6391 20:11:40.893910 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 20:11:40.896661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 20:11:40.896739 ==
6394 20:11:40.896802
6395 20:11:40.896862
6396 20:11:40.899914 TX Vref Scan disable
6397 20:11:40.899999 == TX Byte 0 ==
6398 20:11:40.906587 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 20:11:40.910609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 20:11:40.910682 == TX Byte 1 ==
6401 20:11:40.916587 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6402 20:11:40.919992 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6403 20:11:40.920066
6404 20:11:40.920128 [DATLAT]
6405 20:11:40.923251 Freq=400, CH0 RK0
6406 20:11:40.923351
6407 20:11:40.923440 DATLAT Default: 0xf
6408 20:11:40.926508 0, 0xFFFF, sum = 0
6409 20:11:40.926610 1, 0xFFFF, sum = 0
6410 20:11:40.929900 2, 0xFFFF, sum = 0
6411 20:11:40.929980 3, 0xFFFF, sum = 0
6412 20:11:40.934032 4, 0xFFFF, sum = 0
6413 20:11:40.934103 5, 0xFFFF, sum = 0
6414 20:11:40.936409 6, 0xFFFF, sum = 0
6415 20:11:40.936486 7, 0xFFFF, sum = 0
6416 20:11:40.940181 8, 0xFFFF, sum = 0
6417 20:11:40.940256 9, 0xFFFF, sum = 0
6418 20:11:40.943253 10, 0xFFFF, sum = 0
6419 20:11:40.946574 11, 0xFFFF, sum = 0
6420 20:11:40.946651 12, 0xFFFF, sum = 0
6421 20:11:40.949617 13, 0x0, sum = 1
6422 20:11:40.949691 14, 0x0, sum = 2
6423 20:11:40.952997 15, 0x0, sum = 3
6424 20:11:40.953066 16, 0x0, sum = 4
6425 20:11:40.953134 best_step = 14
6426 20:11:40.953192
6427 20:11:40.956384 ==
6428 20:11:40.959822 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 20:11:40.962569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 20:11:40.962647 ==
6431 20:11:40.962708 RX Vref Scan: 1
6432 20:11:40.962767
6433 20:11:40.966333 RX Vref 0 -> 0, step: 1
6434 20:11:40.966404
6435 20:11:40.969457 RX Delay -359 -> 252, step: 8
6436 20:11:40.969534
6437 20:11:40.972794 Set Vref, RX VrefLevel [Byte0]: 61
6438 20:11:40.976043 [Byte1]: 57
6439 20:11:40.980351
6440 20:11:40.980430 Final RX Vref Byte 0 = 61 to rank0
6441 20:11:40.983326 Final RX Vref Byte 1 = 57 to rank0
6442 20:11:40.986799 Final RX Vref Byte 0 = 61 to rank1
6443 20:11:40.989993 Final RX Vref Byte 1 = 57 to rank1==
6444 20:11:40.993498 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 20:11:40.999372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 20:11:40.999452 ==
6447 20:11:40.999517 DQS Delay:
6448 20:11:41.002827 DQS0 = 48, DQS1 = 60
6449 20:11:41.002910 DQM Delay:
6450 20:11:41.002973 DQM0 = 11, DQM1 = 11
6451 20:11:41.006518 DQ Delay:
6452 20:11:41.009141 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6453 20:11:41.012713 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 20:11:41.016221 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6455 20:11:41.019035 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6456 20:11:41.019109
6457 20:11:41.019178
6458 20:11:41.025884 [DQSOSCAuto] RK0, (LSB)MR18= 0xb577, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6459 20:11:41.029285 CH0 RK0: MR19=C0C, MR18=B577
6460 20:11:41.035895 CH0_RK0: MR19=0xC0C, MR18=0xB577, DQSOSC=387, MR23=63, INC=394, DEC=262
6461 20:11:41.036005 ==
6462 20:11:41.039008 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 20:11:41.042533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 20:11:41.042607 ==
6465 20:11:41.045741 [Gating] SW mode calibration
6466 20:11:41.052454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 20:11:41.058775 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 20:11:41.062324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 20:11:41.065088 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 20:11:41.071718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 20:11:41.075153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 20:11:41.078570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 20:11:41.085128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 20:11:41.088653 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 20:11:41.092040 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 20:11:41.098462 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 20:11:41.101913 Total UI for P1: 0, mck2ui 16
6478 20:11:41.105215 best dqsien dly found for B0: ( 0, 14, 24)
6479 20:11:41.105315 Total UI for P1: 0, mck2ui 16
6480 20:11:41.112071 best dqsien dly found for B1: ( 0, 14, 24)
6481 20:11:41.114775 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 20:11:41.118919 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 20:11:41.119000
6484 20:11:41.121497 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 20:11:41.124764 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 20:11:41.128009 [Gating] SW calibration Done
6487 20:11:41.128086 ==
6488 20:11:41.131805 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 20:11:41.134547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 20:11:41.134649 ==
6491 20:11:41.138024 RX Vref Scan: 0
6492 20:11:41.138102
6493 20:11:41.141141 RX Vref 0 -> 0, step: 1
6494 20:11:41.141210
6495 20:11:41.141270 RX Delay -410 -> 252, step: 16
6496 20:11:41.147898 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6497 20:11:41.151265 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6498 20:11:41.154353 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 20:11:41.161143 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 20:11:41.164148 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6501 20:11:41.167767 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6502 20:11:41.171087 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6503 20:11:41.177431 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6504 20:11:41.180728 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6505 20:11:41.184598 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 20:11:41.187279 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 20:11:41.194045 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 20:11:41.197210 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 20:11:41.201155 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 20:11:41.204124 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 20:11:41.210422 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 20:11:41.210510 ==
6513 20:11:41.213968 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 20:11:41.217233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 20:11:41.217324 ==
6516 20:11:41.217422 DQS Delay:
6517 20:11:41.220150 DQS0 = 43, DQS1 = 59
6518 20:11:41.220227 DQM Delay:
6519 20:11:41.223709 DQM0 = 10, DQM1 = 16
6520 20:11:41.223787 DQ Delay:
6521 20:11:41.227137 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6522 20:11:41.230097 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6523 20:11:41.233638 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6524 20:11:41.236872 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 20:11:41.236955
6526 20:11:41.237025
6527 20:11:41.237085 ==
6528 20:11:41.239960 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 20:11:41.243529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 20:11:41.246548 ==
6531 20:11:41.246627
6532 20:11:41.246694
6533 20:11:41.246756 TX Vref Scan disable
6534 20:11:41.249738 == TX Byte 0 ==
6535 20:11:41.253381 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6536 20:11:41.256608 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6537 20:11:41.259835 == TX Byte 1 ==
6538 20:11:41.263917 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 20:11:41.266243 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 20:11:41.266347 ==
6541 20:11:41.269551 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 20:11:41.276312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 20:11:41.276418 ==
6544 20:11:41.276519
6545 20:11:41.276610
6546 20:11:41.276671 TX Vref Scan disable
6547 20:11:41.280015 == TX Byte 0 ==
6548 20:11:41.282928 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6549 20:11:41.286193 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6550 20:11:41.289314 == TX Byte 1 ==
6551 20:11:41.293125 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6552 20:11:41.295840 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6553 20:11:41.295916
6554 20:11:41.299544 [DATLAT]
6555 20:11:41.299655 Freq=400, CH0 RK1
6556 20:11:41.299745
6557 20:11:41.302511 DATLAT Default: 0xe
6558 20:11:41.302586 0, 0xFFFF, sum = 0
6559 20:11:41.306017 1, 0xFFFF, sum = 0
6560 20:11:41.306124 2, 0xFFFF, sum = 0
6561 20:11:41.309515 3, 0xFFFF, sum = 0
6562 20:11:41.309636 4, 0xFFFF, sum = 0
6563 20:11:41.313065 5, 0xFFFF, sum = 0
6564 20:11:41.313144 6, 0xFFFF, sum = 0
6565 20:11:41.315887 7, 0xFFFF, sum = 0
6566 20:11:41.315963 8, 0xFFFF, sum = 0
6567 20:11:41.319004 9, 0xFFFF, sum = 0
6568 20:11:41.322920 10, 0xFFFF, sum = 0
6569 20:11:41.322999 11, 0xFFFF, sum = 0
6570 20:11:41.325396 12, 0xFFFF, sum = 0
6571 20:11:41.325483 13, 0x0, sum = 1
6572 20:11:41.329282 14, 0x0, sum = 2
6573 20:11:41.329356 15, 0x0, sum = 3
6574 20:11:41.329421 16, 0x0, sum = 4
6575 20:11:41.332410 best_step = 14
6576 20:11:41.332484
6577 20:11:41.332545 ==
6578 20:11:41.335381 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 20:11:41.338967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 20:11:41.339041 ==
6581 20:11:41.342375 RX Vref Scan: 0
6582 20:11:41.342446
6583 20:11:41.345241 RX Vref 0 -> 0, step: 1
6584 20:11:41.345311
6585 20:11:41.345370 RX Delay -359 -> 252, step: 8
6586 20:11:41.354394 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6587 20:11:41.357396 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6588 20:11:41.360810 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 20:11:41.367241 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6590 20:11:41.370477 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6591 20:11:41.373758 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6592 20:11:41.377422 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6593 20:11:41.383542 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6594 20:11:41.387165 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6595 20:11:41.390403 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6596 20:11:41.393780 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6597 20:11:41.400162 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 20:11:41.403420 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6599 20:11:41.407138 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6600 20:11:41.410268 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 20:11:41.417019 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6602 20:11:41.417106 ==
6603 20:11:41.420218 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 20:11:41.423680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 20:11:41.423760 ==
6606 20:11:41.423832 DQS Delay:
6607 20:11:41.426740 DQS0 = 44, DQS1 = 56
6608 20:11:41.426845 DQM Delay:
6609 20:11:41.429962 DQM0 = 7, DQM1 = 11
6610 20:11:41.430072 DQ Delay:
6611 20:11:41.433247 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6612 20:11:41.436917 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6613 20:11:41.439947 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6614 20:11:41.442932 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6615 20:11:41.443014
6616 20:11:41.443079
6617 20:11:41.449816 [DQSOSCAuto] RK1, (LSB)MR18= 0xab38, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6618 20:11:41.452943 CH0 RK1: MR19=C0C, MR18=AB38
6619 20:11:41.459380 CH0_RK1: MR19=0xC0C, MR18=0xAB38, DQSOSC=388, MR23=63, INC=392, DEC=261
6620 20:11:41.462677 [RxdqsGatingPostProcess] freq 400
6621 20:11:41.469536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 20:11:41.473006 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 20:11:41.476162 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 20:11:41.479446 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 20:11:41.482344 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 20:11:41.485556 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 20:11:41.485639 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 20:11:41.489115 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 20:11:41.492677 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 20:11:41.495532 Pre-setting of DQS Precalculation
6631 20:11:41.501934 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 20:11:41.502040 ==
6633 20:11:41.505230 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 20:11:41.509147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 20:11:41.509223 ==
6636 20:11:41.515993 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 20:11:41.522042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 20:11:41.525376 [CA 0] Center 36 (8~64) winsize 57
6639 20:11:41.528781 [CA 1] Center 36 (8~64) winsize 57
6640 20:11:41.531992 [CA 2] Center 36 (8~64) winsize 57
6641 20:11:41.534944 [CA 3] Center 36 (8~64) winsize 57
6642 20:11:41.535019 [CA 4] Center 36 (8~64) winsize 57
6643 20:11:41.538466 [CA 5] Center 36 (8~64) winsize 57
6644 20:11:41.538542
6645 20:11:41.545035 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 20:11:41.545135
6647 20:11:41.548416 [CATrainingPosCal] consider 1 rank data
6648 20:11:41.551668 u2DelayCellTimex100 = 270/100 ps
6649 20:11:41.554815 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 20:11:41.558620 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 20:11:41.561536 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 20:11:41.564805 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 20:11:41.567986 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 20:11:41.571476 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 20:11:41.571547
6656 20:11:41.574682 CA PerBit enable=1, Macro0, CA PI delay=36
6657 20:11:41.574763
6658 20:11:41.577818 [CBTSetCACLKResult] CA Dly = 36
6659 20:11:41.581187 CS Dly: 1 (0~32)
6660 20:11:41.581265 ==
6661 20:11:41.584423 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 20:11:41.588468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 20:11:41.588541 ==
6664 20:11:41.594837 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 20:11:41.601300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6666 20:11:41.604300 [CA 0] Center 36 (8~64) winsize 57
6667 20:11:41.607576 [CA 1] Center 36 (8~64) winsize 57
6668 20:11:41.607650 [CA 2] Center 36 (8~64) winsize 57
6669 20:11:41.611319 [CA 3] Center 36 (8~64) winsize 57
6670 20:11:41.614447 [CA 4] Center 36 (8~64) winsize 57
6671 20:11:41.617267 [CA 5] Center 36 (8~64) winsize 57
6672 20:11:41.617346
6673 20:11:41.620715 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6674 20:11:41.624078
6675 20:11:41.627359 [CATrainingPosCal] consider 2 rank data
6676 20:11:41.630609 u2DelayCellTimex100 = 270/100 ps
6677 20:11:41.634031 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 20:11:41.637111 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 20:11:41.640509 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 20:11:41.644268 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 20:11:41.647347 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 20:11:41.650260 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 20:11:41.650342
6684 20:11:41.654119 CA PerBit enable=1, Macro0, CA PI delay=36
6685 20:11:41.654220
6686 20:11:41.657480 [CBTSetCACLKResult] CA Dly = 36
6687 20:11:41.660825 CS Dly: 1 (0~32)
6688 20:11:41.660925
6689 20:11:41.663642 ----->DramcWriteLeveling(PI) begin...
6690 20:11:41.663765 ==
6691 20:11:41.667021 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 20:11:41.671193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 20:11:41.671277 ==
6694 20:11:41.673557 Write leveling (Byte 0): 40 => 8
6695 20:11:41.676925 Write leveling (Byte 1): 32 => 0
6696 20:11:41.680306 DramcWriteLeveling(PI) end<-----
6697 20:11:41.680378
6698 20:11:41.680439 ==
6699 20:11:41.683528 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 20:11:41.686641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 20:11:41.686727 ==
6702 20:11:41.690070 [Gating] SW mode calibration
6703 20:11:41.696458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 20:11:41.703585 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 20:11:41.706233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 20:11:41.712799 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 20:11:41.716702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 20:11:41.719518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 20:11:41.726035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 20:11:41.730009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 20:11:41.733048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 20:11:41.739393 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 20:11:41.742542 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 20:11:41.746043 Total UI for P1: 0, mck2ui 16
6715 20:11:41.749199 best dqsien dly found for B0: ( 0, 14, 24)
6716 20:11:41.752843 Total UI for P1: 0, mck2ui 16
6717 20:11:41.755645 best dqsien dly found for B1: ( 0, 14, 24)
6718 20:11:41.759083 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 20:11:41.762298 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 20:11:41.762380
6721 20:11:41.765708 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 20:11:41.769220 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 20:11:41.772260 [Gating] SW calibration Done
6724 20:11:41.772337 ==
6725 20:11:41.775813 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 20:11:41.778672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 20:11:41.782143 ==
6728 20:11:41.782225 RX Vref Scan: 0
6729 20:11:41.782291
6730 20:11:41.785407 RX Vref 0 -> 0, step: 1
6731 20:11:41.785485
6732 20:11:41.788831 RX Delay -410 -> 252, step: 16
6733 20:11:41.792262 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6734 20:11:41.795499 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 20:11:41.798750 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6736 20:11:41.804941 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 20:11:41.808503 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 20:11:41.811635 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 20:11:41.818059 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 20:11:41.821711 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 20:11:41.824963 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 20:11:41.828871 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6743 20:11:41.834992 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6744 20:11:41.837961 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6745 20:11:41.841330 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 20:11:41.844699 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 20:11:41.851401 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6748 20:11:41.854631 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6749 20:11:41.854704 ==
6750 20:11:41.857826 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 20:11:41.861462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 20:11:41.861546 ==
6753 20:11:41.864404 DQS Delay:
6754 20:11:41.864486 DQS0 = 43, DQS1 = 51
6755 20:11:41.867872 DQM Delay:
6756 20:11:41.867967 DQM0 = 12, DQM1 = 14
6757 20:11:41.868036 DQ Delay:
6758 20:11:41.871393 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6759 20:11:41.874323 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 20:11:41.877674 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6761 20:11:41.881018 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6762 20:11:41.881092
6763 20:11:41.881153
6764 20:11:41.881211 ==
6765 20:11:41.884149 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 20:11:41.890741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 20:11:41.890826 ==
6768 20:11:41.890892
6769 20:11:41.890954
6770 20:11:41.891013 TX Vref Scan disable
6771 20:11:41.894687 == TX Byte 0 ==
6772 20:11:41.897825 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 20:11:41.900833 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 20:11:41.903888 == TX Byte 1 ==
6775 20:11:41.907359 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6776 20:11:41.910348 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6777 20:11:41.913875 ==
6778 20:11:41.916987 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 20:11:41.920504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 20:11:41.920580 ==
6781 20:11:41.920644
6782 20:11:41.920703
6783 20:11:41.923655 TX Vref Scan disable
6784 20:11:41.923729 == TX Byte 0 ==
6785 20:11:41.927190 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 20:11:41.933323 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 20:11:41.933396 == TX Byte 1 ==
6788 20:11:41.936795 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6789 20:11:41.943652 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6790 20:11:41.943736
6791 20:11:41.943799 [DATLAT]
6792 20:11:41.943859 Freq=400, CH1 RK0
6793 20:11:41.946624
6794 20:11:41.946691 DATLAT Default: 0xf
6795 20:11:41.950230 0, 0xFFFF, sum = 0
6796 20:11:41.950315 1, 0xFFFF, sum = 0
6797 20:11:41.953340 2, 0xFFFF, sum = 0
6798 20:11:41.953414 3, 0xFFFF, sum = 0
6799 20:11:41.956621 4, 0xFFFF, sum = 0
6800 20:11:41.956705 5, 0xFFFF, sum = 0
6801 20:11:41.960197 6, 0xFFFF, sum = 0
6802 20:11:41.960282 7, 0xFFFF, sum = 0
6803 20:11:41.963077 8, 0xFFFF, sum = 0
6804 20:11:41.963162 9, 0xFFFF, sum = 0
6805 20:11:41.966555 10, 0xFFFF, sum = 0
6806 20:11:41.966640 11, 0xFFFF, sum = 0
6807 20:11:41.969957 12, 0xFFFF, sum = 0
6808 20:11:41.970042 13, 0x0, sum = 1
6809 20:11:41.972993 14, 0x0, sum = 2
6810 20:11:41.973077 15, 0x0, sum = 3
6811 20:11:41.976630 16, 0x0, sum = 4
6812 20:11:41.976713 best_step = 14
6813 20:11:41.976780
6814 20:11:41.976841 ==
6815 20:11:41.979465 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 20:11:41.986114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 20:11:41.986196 ==
6818 20:11:41.986262 RX Vref Scan: 1
6819 20:11:41.986323
6820 20:11:41.989477 RX Vref 0 -> 0, step: 1
6821 20:11:41.989550
6822 20:11:41.993089 RX Delay -343 -> 252, step: 8
6823 20:11:41.993159
6824 20:11:41.995959 Set Vref, RX VrefLevel [Byte0]: 49
6825 20:11:41.999905 [Byte1]: 53
6826 20:11:42.002521
6827 20:11:42.002608 Final RX Vref Byte 0 = 49 to rank0
6828 20:11:42.006320 Final RX Vref Byte 1 = 53 to rank0
6829 20:11:42.009474 Final RX Vref Byte 0 = 49 to rank1
6830 20:11:42.012582 Final RX Vref Byte 1 = 53 to rank1==
6831 20:11:42.015926 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 20:11:42.022401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 20:11:42.022511 ==
6834 20:11:42.022608 DQS Delay:
6835 20:11:42.025821 DQS0 = 44, DQS1 = 56
6836 20:11:42.025901 DQM Delay:
6837 20:11:42.025963 DQM0 = 8, DQM1 = 12
6838 20:11:42.029006 DQ Delay:
6839 20:11:42.032785 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6840 20:11:42.032867 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6841 20:11:42.035547 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6842 20:11:42.039092 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6843 20:11:42.039159
6844 20:11:42.042196
6845 20:11:42.049108 [DQSOSCAuto] RK0, (LSB)MR18= 0x9066, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6846 20:11:42.052067 CH1 RK0: MR19=C0C, MR18=9066
6847 20:11:42.058654 CH1_RK0: MR19=0xC0C, MR18=0x9066, DQSOSC=391, MR23=63, INC=386, DEC=257
6848 20:11:42.058739 ==
6849 20:11:42.062066 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 20:11:42.065381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 20:11:42.065465 ==
6852 20:11:42.068926 [Gating] SW mode calibration
6853 20:11:42.074966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 20:11:42.081707 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 20:11:42.084990 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 20:11:42.088218 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 20:11:42.094586 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 20:11:42.098035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 20:11:42.101348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 20:11:42.107925 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 20:11:42.111911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 20:11:42.114581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 20:11:42.121174 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 20:11:42.124773 Total UI for P1: 0, mck2ui 16
6865 20:11:42.127331 best dqsien dly found for B0: ( 0, 14, 24)
6866 20:11:42.131057 Total UI for P1: 0, mck2ui 16
6867 20:11:42.133912 best dqsien dly found for B1: ( 0, 14, 24)
6868 20:11:42.137310 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 20:11:42.140798 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 20:11:42.140882
6871 20:11:42.144206 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 20:11:42.147733 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 20:11:42.150570 [Gating] SW calibration Done
6874 20:11:42.150682 ==
6875 20:11:42.154234 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 20:11:42.157679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 20:11:42.157753 ==
6878 20:11:42.160433 RX Vref Scan: 0
6879 20:11:42.160508
6880 20:11:42.164009 RX Vref 0 -> 0, step: 1
6881 20:11:42.164081
6882 20:11:42.167505 RX Delay -410 -> 252, step: 16
6883 20:11:42.170632 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6884 20:11:42.173403 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 20:11:42.177051 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6886 20:11:42.183594 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 20:11:42.186688 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 20:11:42.189978 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6889 20:11:42.193128 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6890 20:11:42.199934 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 20:11:42.203089 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 20:11:42.206314 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6893 20:11:42.209873 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6894 20:11:42.216886 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6895 20:11:42.219763 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 20:11:42.222755 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 20:11:42.229437 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6898 20:11:42.232941 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 20:11:42.233018 ==
6900 20:11:42.235842 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 20:11:42.239250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 20:11:42.239321 ==
6903 20:11:42.242620 DQS Delay:
6904 20:11:42.242693 DQS0 = 43, DQS1 = 51
6905 20:11:42.246242 DQM Delay:
6906 20:11:42.246310 DQM0 = 12, DQM1 = 13
6907 20:11:42.246377 DQ Delay:
6908 20:11:42.249406 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6909 20:11:42.252310 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6910 20:11:42.255904 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6911 20:11:42.259131 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6912 20:11:42.259205
6913 20:11:42.259267
6914 20:11:42.259326 ==
6915 20:11:42.262322 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 20:11:42.268819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 20:11:42.268895 ==
6918 20:11:42.268965
6919 20:11:42.269024
6920 20:11:42.269082 TX Vref Scan disable
6921 20:11:42.272163 == TX Byte 0 ==
6922 20:11:42.275516 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6923 20:11:42.278605 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6924 20:11:42.282315 == TX Byte 1 ==
6925 20:11:42.285125 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 20:11:42.288929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 20:11:42.289010 ==
6928 20:11:42.292027 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 20:11:42.298259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 20:11:42.298338 ==
6931 20:11:42.298410
6932 20:11:42.298471
6933 20:11:42.298529 TX Vref Scan disable
6934 20:11:42.301700 == TX Byte 0 ==
6935 20:11:42.305212 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6936 20:11:42.308433 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6937 20:11:42.311610 == TX Byte 1 ==
6938 20:11:42.315021 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6939 20:11:42.318080 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6940 20:11:42.318162
6941 20:11:42.321953 [DATLAT]
6942 20:11:42.322034 Freq=400, CH1 RK1
6943 20:11:42.322100
6944 20:11:42.324919 DATLAT Default: 0xe
6945 20:11:42.325028 0, 0xFFFF, sum = 0
6946 20:11:42.328493 1, 0xFFFF, sum = 0
6947 20:11:42.328567 2, 0xFFFF, sum = 0
6948 20:11:42.331486 3, 0xFFFF, sum = 0
6949 20:11:42.331554 4, 0xFFFF, sum = 0
6950 20:11:42.334945 5, 0xFFFF, sum = 0
6951 20:11:42.338104 6, 0xFFFF, sum = 0
6952 20:11:42.338177 7, 0xFFFF, sum = 0
6953 20:11:42.341157 8, 0xFFFF, sum = 0
6954 20:11:42.341231 9, 0xFFFF, sum = 0
6955 20:11:42.344444 10, 0xFFFF, sum = 0
6956 20:11:42.344537 11, 0xFFFF, sum = 0
6957 20:11:42.347977 12, 0xFFFF, sum = 0
6958 20:11:42.348063 13, 0x0, sum = 1
6959 20:11:42.351091 14, 0x0, sum = 2
6960 20:11:42.351162 15, 0x0, sum = 3
6961 20:11:42.354686 16, 0x0, sum = 4
6962 20:11:42.354771 best_step = 14
6963 20:11:42.354837
6964 20:11:42.354893 ==
6965 20:11:42.357646 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 20:11:42.361028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 20:11:42.361139 ==
6968 20:11:42.364456 RX Vref Scan: 0
6969 20:11:42.364557
6970 20:11:42.368307 RX Vref 0 -> 0, step: 1
6971 20:11:42.368416
6972 20:11:42.368512 RX Delay -343 -> 252, step: 8
6973 20:11:42.376466 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6974 20:11:42.379605 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6975 20:11:42.383577 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6976 20:11:42.389804 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6977 20:11:42.393056 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6978 20:11:42.396150 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6979 20:11:42.399986 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6980 20:11:42.406911 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6981 20:11:42.409441 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6982 20:11:42.413430 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6983 20:11:42.416088 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
6984 20:11:42.423066 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6985 20:11:42.426184 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6986 20:11:42.429185 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6987 20:11:42.432333 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6988 20:11:42.439340 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6989 20:11:42.439424 ==
6990 20:11:42.442755 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 20:11:42.446169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 20:11:42.446254 ==
6993 20:11:42.446319 DQS Delay:
6994 20:11:42.448944 DQS0 = 44, DQS1 = 56
6995 20:11:42.449052 DQM Delay:
6996 20:11:42.452309 DQM0 = 8, DQM1 = 11
6997 20:11:42.452393 DQ Delay:
6998 20:11:42.455783 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6999 20:11:42.459590 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7000 20:11:42.462304 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7001 20:11:42.466078 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7002 20:11:42.466161
7003 20:11:42.466227
7004 20:11:42.472076 [DQSOSCAuto] RK1, (LSB)MR18= 0x6354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7005 20:11:42.475994 CH1 RK1: MR19=C0C, MR18=6354
7006 20:11:42.482161 CH1_RK1: MR19=0xC0C, MR18=0x6354, DQSOSC=397, MR23=63, INC=374, DEC=249
7007 20:11:42.485496 [RxdqsGatingPostProcess] freq 400
7008 20:11:42.492773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 20:11:42.495244 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 20:11:42.498816 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 20:11:42.502091 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 20:11:42.505136 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 20:11:42.505219 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 20:11:42.508374 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 20:11:42.512006 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 20:11:42.515037 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 20:11:42.518546 Pre-setting of DQS Precalculation
7018 20:11:42.525364 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 20:11:42.531701 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 20:11:42.538333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 20:11:42.538418
7022 20:11:42.538484
7023 20:11:42.541768 [Calibration Summary] 800 Mbps
7024 20:11:42.544757 CH 0, Rank 0
7025 20:11:42.544840 SW Impedance : PASS
7026 20:11:42.547881 DUTY Scan : NO K
7027 20:11:42.547965 ZQ Calibration : PASS
7028 20:11:42.551572 Jitter Meter : NO K
7029 20:11:42.555128 CBT Training : PASS
7030 20:11:42.555212 Write leveling : PASS
7031 20:11:42.557581 RX DQS gating : PASS
7032 20:11:42.561176 RX DQ/DQS(RDDQC) : PASS
7033 20:11:42.561259 TX DQ/DQS : PASS
7034 20:11:42.564455 RX DATLAT : PASS
7035 20:11:42.567596 RX DQ/DQS(Engine): PASS
7036 20:11:42.567687 TX OE : NO K
7037 20:11:42.571132 All Pass.
7038 20:11:42.571216
7039 20:11:42.571282 CH 0, Rank 1
7040 20:11:42.574134 SW Impedance : PASS
7041 20:11:42.574217 DUTY Scan : NO K
7042 20:11:42.577611 ZQ Calibration : PASS
7043 20:11:42.581128 Jitter Meter : NO K
7044 20:11:42.581212 CBT Training : PASS
7045 20:11:42.584353 Write leveling : NO K
7046 20:11:42.587559 RX DQS gating : PASS
7047 20:11:42.587642 RX DQ/DQS(RDDQC) : PASS
7048 20:11:42.590911 TX DQ/DQS : PASS
7049 20:11:42.593819 RX DATLAT : PASS
7050 20:11:42.593902 RX DQ/DQS(Engine): PASS
7051 20:11:42.597549 TX OE : NO K
7052 20:11:42.597633 All Pass.
7053 20:11:42.597699
7054 20:11:42.600663 CH 1, Rank 0
7055 20:11:42.600746 SW Impedance : PASS
7056 20:11:42.604254 DUTY Scan : NO K
7057 20:11:42.606983 ZQ Calibration : PASS
7058 20:11:42.607067 Jitter Meter : NO K
7059 20:11:42.610418 CBT Training : PASS
7060 20:11:42.613740 Write leveling : PASS
7061 20:11:42.613823 RX DQS gating : PASS
7062 20:11:42.616938 RX DQ/DQS(RDDQC) : PASS
7063 20:11:42.620581 TX DQ/DQS : PASS
7064 20:11:42.620696 RX DATLAT : PASS
7065 20:11:42.623645 RX DQ/DQS(Engine): PASS
7066 20:11:42.627351 TX OE : NO K
7067 20:11:42.627433 All Pass.
7068 20:11:42.627498
7069 20:11:42.627572 CH 1, Rank 1
7070 20:11:42.630275 SW Impedance : PASS
7071 20:11:42.633504 DUTY Scan : NO K
7072 20:11:42.633616 ZQ Calibration : PASS
7073 20:11:42.636888 Jitter Meter : NO K
7074 20:11:42.639810 CBT Training : PASS
7075 20:11:42.639920 Write leveling : NO K
7076 20:11:42.643655 RX DQS gating : PASS
7077 20:11:42.643788 RX DQ/DQS(RDDQC) : PASS
7078 20:11:42.647150 TX DQ/DQS : PASS
7079 20:11:42.650329 RX DATLAT : PASS
7080 20:11:42.650425 RX DQ/DQS(Engine): PASS
7081 20:11:42.653184 TX OE : NO K
7082 20:11:42.653282 All Pass.
7083 20:11:42.653347
7084 20:11:42.656650 DramC Write-DBI off
7085 20:11:42.659934 PER_BANK_REFRESH: Hybrid Mode
7086 20:11:42.660030 TX_TRACKING: ON
7087 20:11:42.670010 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 20:11:42.673188 [FAST_K] Save calibration result to emmc
7089 20:11:42.676427 dramc_set_vcore_voltage set vcore to 725000
7090 20:11:42.680006 Read voltage for 1600, 0
7091 20:11:42.680099 Vio18 = 0
7092 20:11:42.683075 Vcore = 725000
7093 20:11:42.683180 Vdram = 0
7094 20:11:42.683279 Vddq = 0
7095 20:11:42.683365 Vmddr = 0
7096 20:11:42.689413 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 20:11:42.696395 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 20:11:42.696475 MEM_TYPE=3, freq_sel=13
7099 20:11:42.699286 sv_algorithm_assistance_LP4_3733
7100 20:11:42.702660 ============ PULL DRAM RESETB DOWN ============
7101 20:11:42.709396 ========== PULL DRAM RESETB DOWN end =========
7102 20:11:42.712939 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 20:11:42.716442 ===================================
7104 20:11:42.719584 LPDDR4 DRAM CONFIGURATION
7105 20:11:42.722681 ===================================
7106 20:11:42.722766 EX_ROW_EN[0] = 0x0
7107 20:11:42.727070 EX_ROW_EN[1] = 0x0
7108 20:11:42.727154 LP4Y_EN = 0x0
7109 20:11:42.729641 WORK_FSP = 0x1
7110 20:11:42.729724 WL = 0x5
7111 20:11:42.732758 RL = 0x5
7112 20:11:42.732842 BL = 0x2
7113 20:11:42.736272 RPST = 0x0
7114 20:11:42.739246 RD_PRE = 0x0
7115 20:11:42.739327 WR_PRE = 0x1
7116 20:11:42.743005 WR_PST = 0x1
7117 20:11:42.743100 DBI_WR = 0x0
7118 20:11:42.745815 DBI_RD = 0x0
7119 20:11:42.745898 OTF = 0x1
7120 20:11:42.749386 ===================================
7121 20:11:42.752687 ===================================
7122 20:11:42.755775 ANA top config
7123 20:11:42.759406 ===================================
7124 20:11:42.759508 DLL_ASYNC_EN = 0
7125 20:11:42.762955 ALL_SLAVE_EN = 0
7126 20:11:42.765640 NEW_RANK_MODE = 1
7127 20:11:42.769040 DLL_IDLE_MODE = 1
7128 20:11:42.769116 LP45_APHY_COMB_EN = 1
7129 20:11:42.772546 TX_ODT_DIS = 0
7130 20:11:42.775319 NEW_8X_MODE = 1
7131 20:11:42.778697 ===================================
7132 20:11:42.782388 ===================================
7133 20:11:42.785757 data_rate = 3200
7134 20:11:42.789173 CKR = 1
7135 20:11:42.792390 DQ_P2S_RATIO = 8
7136 20:11:42.795940 ===================================
7137 20:11:42.796050 CA_P2S_RATIO = 8
7138 20:11:42.798872 DQ_CA_OPEN = 0
7139 20:11:42.801866 DQ_SEMI_OPEN = 0
7140 20:11:42.805266 CA_SEMI_OPEN = 0
7141 20:11:42.808875 CA_FULL_RATE = 0
7142 20:11:42.811818 DQ_CKDIV4_EN = 0
7143 20:11:42.811901 CA_CKDIV4_EN = 0
7144 20:11:42.815106 CA_PREDIV_EN = 0
7145 20:11:42.818482 PH8_DLY = 12
7146 20:11:42.822217 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 20:11:42.825306 DQ_AAMCK_DIV = 4
7148 20:11:42.828210 CA_AAMCK_DIV = 4
7149 20:11:42.828316 CA_ADMCK_DIV = 4
7150 20:11:42.831562 DQ_TRACK_CA_EN = 0
7151 20:11:42.834883 CA_PICK = 1600
7152 20:11:42.838007 CA_MCKIO = 1600
7153 20:11:42.841543 MCKIO_SEMI = 0
7154 20:11:42.844793 PLL_FREQ = 3068
7155 20:11:42.848021 DQ_UI_PI_RATIO = 32
7156 20:11:42.852266 CA_UI_PI_RATIO = 0
7157 20:11:42.855308 ===================================
7158 20:11:42.858528 ===================================
7159 20:11:42.858628 memory_type:LPDDR4
7160 20:11:42.861281 GP_NUM : 10
7161 20:11:42.864225 SRAM_EN : 1
7162 20:11:42.864325 MD32_EN : 0
7163 20:11:42.867635 ===================================
7164 20:11:42.871405 [ANA_INIT] >>>>>>>>>>>>>>
7165 20:11:42.874115 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 20:11:42.877712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 20:11:42.880918 ===================================
7168 20:11:42.884208 data_rate = 3200,PCW = 0X7600
7169 20:11:42.887863 ===================================
7170 20:11:42.891356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 20:11:42.894406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 20:11:42.900817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 20:11:42.904090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 20:11:42.910546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 20:11:42.913609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 20:11:42.913719 [ANA_INIT] flow start
7177 20:11:42.917195 [ANA_INIT] PLL >>>>>>>>
7178 20:11:42.920439 [ANA_INIT] PLL <<<<<<<<
7179 20:11:42.920514 [ANA_INIT] MIDPI >>>>>>>>
7180 20:11:42.923868 [ANA_INIT] MIDPI <<<<<<<<
7181 20:11:42.926801 [ANA_INIT] DLL >>>>>>>>
7182 20:11:42.926901 [ANA_INIT] DLL <<<<<<<<
7183 20:11:42.930475 [ANA_INIT] flow end
7184 20:11:42.933633 ============ LP4 DIFF to SE enter ============
7185 20:11:42.937227 ============ LP4 DIFF to SE exit ============
7186 20:11:42.940073 [ANA_INIT] <<<<<<<<<<<<<
7187 20:11:42.943832 [Flow] Enable top DCM control >>>>>
7188 20:11:42.947215 [Flow] Enable top DCM control <<<<<
7189 20:11:42.950593 Enable DLL master slave shuffle
7190 20:11:42.956891 ==============================================================
7191 20:11:42.956969 Gating Mode config
7192 20:11:42.963372 ==============================================================
7193 20:11:42.963471 Config description:
7194 20:11:42.973807 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 20:11:42.980140 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 20:11:42.986373 SELPH_MODE 0: By rank 1: By Phase
7197 20:11:42.993391 ==============================================================
7198 20:11:42.993508 GAT_TRACK_EN = 1
7199 20:11:42.996310 RX_GATING_MODE = 2
7200 20:11:42.999636 RX_GATING_TRACK_MODE = 2
7201 20:11:43.002917 SELPH_MODE = 1
7202 20:11:43.006423 PICG_EARLY_EN = 1
7203 20:11:43.009711 VALID_LAT_VALUE = 1
7204 20:11:43.016298 ==============================================================
7205 20:11:43.019610 Enter into Gating configuration >>>>
7206 20:11:43.022612 Exit from Gating configuration <<<<
7207 20:11:43.026401 Enter into DVFS_PRE_config >>>>>
7208 20:11:43.036293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 20:11:43.039737 Exit from DVFS_PRE_config <<<<<
7210 20:11:43.043263 Enter into PICG configuration >>>>
7211 20:11:43.045884 Exit from PICG configuration <<<<
7212 20:11:43.049542 [RX_INPUT] configuration >>>>>
7213 20:11:43.052779 [RX_INPUT] configuration <<<<<
7214 20:11:43.055624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 20:11:43.062911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 20:11:43.069097 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 20:11:43.072607 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 20:11:43.079191 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 20:11:43.085763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 20:11:43.089215 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 20:11:43.095261 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 20:11:43.098986 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 20:11:43.102540 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 20:11:43.105604 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 20:11:43.112178 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 20:11:43.115337 ===================================
7227 20:11:43.115446 LPDDR4 DRAM CONFIGURATION
7228 20:11:43.118660 ===================================
7229 20:11:43.122246 EX_ROW_EN[0] = 0x0
7230 20:11:43.125123 EX_ROW_EN[1] = 0x0
7231 20:11:43.125225 LP4Y_EN = 0x0
7232 20:11:43.128625 WORK_FSP = 0x1
7233 20:11:43.128703 WL = 0x5
7234 20:11:43.132122 RL = 0x5
7235 20:11:43.132197 BL = 0x2
7236 20:11:43.135092 RPST = 0x0
7237 20:11:43.135192 RD_PRE = 0x0
7238 20:11:43.138464 WR_PRE = 0x1
7239 20:11:43.138572 WR_PST = 0x1
7240 20:11:43.142262 DBI_WR = 0x0
7241 20:11:43.142364 DBI_RD = 0x0
7242 20:11:43.144834 OTF = 0x1
7243 20:11:43.148834 ===================================
7244 20:11:43.151340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 20:11:43.154644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 20:11:43.161621 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 20:11:43.165117 ===================================
7248 20:11:43.165197 LPDDR4 DRAM CONFIGURATION
7249 20:11:43.168011 ===================================
7250 20:11:43.171687 EX_ROW_EN[0] = 0x10
7251 20:11:43.174247 EX_ROW_EN[1] = 0x0
7252 20:11:43.174349 LP4Y_EN = 0x0
7253 20:11:43.178107 WORK_FSP = 0x1
7254 20:11:43.178214 WL = 0x5
7255 20:11:43.180863 RL = 0x5
7256 20:11:43.180964 BL = 0x2
7257 20:11:43.184848 RPST = 0x0
7258 20:11:43.184926 RD_PRE = 0x0
7259 20:11:43.187926 WR_PRE = 0x1
7260 20:11:43.188002 WR_PST = 0x1
7261 20:11:43.190796 DBI_WR = 0x0
7262 20:11:43.194405 DBI_RD = 0x0
7263 20:11:43.194506 OTF = 0x1
7264 20:11:43.197272 ===================================
7265 20:11:43.204205 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 20:11:43.204313 ==
7267 20:11:43.207099 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 20:11:43.210982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 20:11:43.211082 ==
7270 20:11:43.213906 [Duty_Offset_Calibration]
7271 20:11:43.214004 B0:1 B1:-1 CA:0
7272 20:11:43.217140
7273 20:11:43.220337 [DutyScan_Calibration_Flow] k_type=0
7274 20:11:43.228673
7275 20:11:43.228747 ==CLK 0==
7276 20:11:43.232268 Final CLK duty delay cell = 0
7277 20:11:43.235290 [0] MAX Duty = 5125%(X100), DQS PI = 20
7278 20:11:43.238676 [0] MIN Duty = 4907%(X100), DQS PI = 8
7279 20:11:43.241780 [0] AVG Duty = 5016%(X100)
7280 20:11:43.241881
7281 20:11:43.244960 CH0 CLK Duty spec in!! Max-Min= 218%
7282 20:11:43.248214 [DutyScan_Calibration_Flow] ====Done====
7283 20:11:43.248290
7284 20:11:43.251326 [DutyScan_Calibration_Flow] k_type=1
7285 20:11:43.267597
7286 20:11:43.267735 ==DQS 0 ==
7287 20:11:43.270937 Final DQS duty delay cell = -4
7288 20:11:43.274497 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7289 20:11:43.278088 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7290 20:11:43.280821 [-4] AVG Duty = 4922%(X100)
7291 20:11:43.280904
7292 20:11:43.280978 ==DQS 1 ==
7293 20:11:43.284321 Final DQS duty delay cell = 0
7294 20:11:43.287998 [0] MAX Duty = 5156%(X100), DQS PI = 2
7295 20:11:43.290874 [0] MIN Duty = 5031%(X100), DQS PI = 18
7296 20:11:43.294472 [0] AVG Duty = 5093%(X100)
7297 20:11:43.294546
7298 20:11:43.297854 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7299 20:11:43.297952
7300 20:11:43.300595 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7301 20:11:43.304388 [DutyScan_Calibration_Flow] ====Done====
7302 20:11:43.304494
7303 20:11:43.306986 [DutyScan_Calibration_Flow] k_type=3
7304 20:11:43.325313
7305 20:11:43.325417 ==DQM 0 ==
7306 20:11:43.328700 Final DQM duty delay cell = 0
7307 20:11:43.332073 [0] MAX Duty = 5124%(X100), DQS PI = 22
7308 20:11:43.335427 [0] MIN Duty = 4907%(X100), DQS PI = 8
7309 20:11:43.338760 [0] AVG Duty = 5015%(X100)
7310 20:11:43.338858
7311 20:11:43.338949 ==DQM 1 ==
7312 20:11:43.342258 Final DQM duty delay cell = 0
7313 20:11:43.344876 [0] MAX Duty = 5000%(X100), DQS PI = 4
7314 20:11:43.348318 [0] MIN Duty = 4813%(X100), DQS PI = 20
7315 20:11:43.351840 [0] AVG Duty = 4906%(X100)
7316 20:11:43.351928
7317 20:11:43.354898 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7318 20:11:43.354998
7319 20:11:43.358571 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7320 20:11:43.361237 [DutyScan_Calibration_Flow] ====Done====
7321 20:11:43.361320
7322 20:11:43.364557 [DutyScan_Calibration_Flow] k_type=2
7323 20:11:43.381757
7324 20:11:43.381861 ==DQ 0 ==
7325 20:11:43.384851 Final DQ duty delay cell = -4
7326 20:11:43.387925 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7327 20:11:43.391593 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7328 20:11:43.394887 [-4] AVG Duty = 4953%(X100)
7329 20:11:43.394958
7330 20:11:43.395022 ==DQ 1 ==
7331 20:11:43.398417 Final DQ duty delay cell = 0
7332 20:11:43.401230 [0] MAX Duty = 5125%(X100), DQS PI = 4
7333 20:11:43.404676 [0] MIN Duty = 5000%(X100), DQS PI = 36
7334 20:11:43.407821 [0] AVG Duty = 5062%(X100)
7335 20:11:43.407905
7336 20:11:43.411541 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7337 20:11:43.411640
7338 20:11:43.414342 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7339 20:11:43.417966 [DutyScan_Calibration_Flow] ====Done====
7340 20:11:43.418059 ==
7341 20:11:43.420847 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 20:11:43.424881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 20:11:43.424990 ==
7344 20:11:43.428200 [Duty_Offset_Calibration]
7345 20:11:43.428267 B0:-1 B1:1 CA:2
7346 20:11:43.431030
7347 20:11:43.433978 [DutyScan_Calibration_Flow] k_type=0
7348 20:11:43.441921
7349 20:11:43.442041 ==CLK 0==
7350 20:11:43.445424 Final CLK duty delay cell = 0
7351 20:11:43.449096 [0] MAX Duty = 5187%(X100), DQS PI = 22
7352 20:11:43.452183 [0] MIN Duty = 5031%(X100), DQS PI = 14
7353 20:11:43.455105 [0] AVG Duty = 5109%(X100)
7354 20:11:43.455213
7355 20:11:43.458413 CH1 CLK Duty spec in!! Max-Min= 156%
7356 20:11:43.461985 [DutyScan_Calibration_Flow] ====Done====
7357 20:11:43.462095
7358 20:11:43.465393 [DutyScan_Calibration_Flow] k_type=1
7359 20:11:43.481805
7360 20:11:43.481910 ==DQS 0 ==
7361 20:11:43.485432 Final DQS duty delay cell = 0
7362 20:11:43.488247 [0] MAX Duty = 5156%(X100), DQS PI = 22
7363 20:11:43.491850 [0] MIN Duty = 4907%(X100), DQS PI = 40
7364 20:11:43.495153 [0] AVG Duty = 5031%(X100)
7365 20:11:43.495250
7366 20:11:43.495340 ==DQS 1 ==
7367 20:11:43.498680 Final DQS duty delay cell = 0
7368 20:11:43.501891 [0] MAX Duty = 5093%(X100), DQS PI = 38
7369 20:11:43.505700 [0] MIN Duty = 4969%(X100), DQS PI = 26
7370 20:11:43.508259 [0] AVG Duty = 5031%(X100)
7371 20:11:43.508329
7372 20:11:43.511442 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7373 20:11:43.511510
7374 20:11:43.514956 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7375 20:11:43.518291 [DutyScan_Calibration_Flow] ====Done====
7376 20:11:43.518359
7377 20:11:43.521267 [DutyScan_Calibration_Flow] k_type=3
7378 20:11:43.539465
7379 20:11:43.539562 ==DQM 0 ==
7380 20:11:43.542280 Final DQM duty delay cell = 0
7381 20:11:43.545602 [0] MAX Duty = 5187%(X100), DQS PI = 4
7382 20:11:43.548721 [0] MIN Duty = 5031%(X100), DQS PI = 40
7383 20:11:43.552355 [0] AVG Duty = 5109%(X100)
7384 20:11:43.552433
7385 20:11:43.552526 ==DQM 1 ==
7386 20:11:43.555420 Final DQM duty delay cell = 0
7387 20:11:43.558924 [0] MAX Duty = 5218%(X100), DQS PI = 36
7388 20:11:43.561920 [0] MIN Duty = 4969%(X100), DQS PI = 0
7389 20:11:43.565512 [0] AVG Duty = 5093%(X100)
7390 20:11:43.565585
7391 20:11:43.568331 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7392 20:11:43.568400
7393 20:11:43.572140 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7394 20:11:43.575250 [DutyScan_Calibration_Flow] ====Done====
7395 20:11:43.575345
7396 20:11:43.578198 [DutyScan_Calibration_Flow] k_type=2
7397 20:11:43.595686
7398 20:11:43.595768 ==DQ 0 ==
7399 20:11:43.598893 Final DQ duty delay cell = 0
7400 20:11:43.602125 [0] MAX Duty = 5156%(X100), DQS PI = 0
7401 20:11:43.605605 [0] MIN Duty = 4906%(X100), DQS PI = 40
7402 20:11:43.605688 [0] AVG Duty = 5031%(X100)
7403 20:11:43.608893
7404 20:11:43.608968 ==DQ 1 ==
7405 20:11:43.612306 Final DQ duty delay cell = 0
7406 20:11:43.615211 [0] MAX Duty = 5156%(X100), DQS PI = 42
7407 20:11:43.618668 [0] MIN Duty = 4969%(X100), DQS PI = 26
7408 20:11:43.622130 [0] AVG Duty = 5062%(X100)
7409 20:11:43.622223
7410 20:11:43.625149 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7411 20:11:43.625243
7412 20:11:43.628450 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7413 20:11:43.631543 [DutyScan_Calibration_Flow] ====Done====
7414 20:11:43.635087 nWR fixed to 30
7415 20:11:43.638912 [ModeRegInit_LP4] CH0 RK0
7416 20:11:43.639008 [ModeRegInit_LP4] CH0 RK1
7417 20:11:43.641646 [ModeRegInit_LP4] CH1 RK0
7418 20:11:43.645042 [ModeRegInit_LP4] CH1 RK1
7419 20:11:43.645138 match AC timing 5
7420 20:11:43.651542 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 20:11:43.654794 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 20:11:43.658236 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 20:11:43.664725 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 20:11:43.667967 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 20:11:43.668040 [MiockJmeterHQA]
7426 20:11:43.668103
7427 20:11:43.671220 [DramcMiockJmeter] u1RxGatingPI = 0
7428 20:11:43.674371 0 : 4257, 4029
7429 20:11:43.674469 4 : 4363, 4137
7430 20:11:43.678176 8 : 4252, 4027
7431 20:11:43.678258 12 : 4362, 4137
7432 20:11:43.681402 16 : 4363, 4137
7433 20:11:43.681503 20 : 4253, 4027
7434 20:11:43.681594 24 : 4252, 4027
7435 20:11:43.684556 28 : 4252, 4027
7436 20:11:43.684650 32 : 4363, 4137
7437 20:11:43.688152 36 : 4252, 4027
7438 20:11:43.688228 40 : 4363, 4137
7439 20:11:43.691212 44 : 4252, 4027
7440 20:11:43.691308 48 : 4252, 4027
7441 20:11:43.694538 52 : 4253, 4026
7442 20:11:43.694632 56 : 4252, 4027
7443 20:11:43.694709 60 : 4360, 4137
7444 20:11:43.697845 64 : 4252, 4029
7445 20:11:43.697944 68 : 4361, 4138
7446 20:11:43.701032 72 : 4250, 4026
7447 20:11:43.701102 76 : 4253, 4029
7448 20:11:43.704695 80 : 4249, 4027
7449 20:11:43.704780 84 : 4361, 4137
7450 20:11:43.707639 88 : 4250, 4027
7451 20:11:43.707759 92 : 4360, 286
7452 20:11:43.707822 96 : 4250, 0
7453 20:11:43.710541 100 : 4250, 0
7454 20:11:43.710607 104 : 4361, 0
7455 20:11:43.713706 108 : 4249, 0
7456 20:11:43.713774 112 : 4250, 0
7457 20:11:43.713835 116 : 4250, 0
7458 20:11:43.717118 120 : 4249, 0
7459 20:11:43.717189 124 : 4253, 0
7460 20:11:43.720579 128 : 4361, 0
7461 20:11:43.720647 132 : 4250, 0
7462 20:11:43.720707 136 : 4250, 0
7463 20:11:43.724159 140 : 4250, 0
7464 20:11:43.724262 144 : 4360, 0
7465 20:11:43.727016 148 : 4361, 0
7466 20:11:43.727084 152 : 4249, 0
7467 20:11:43.727145 156 : 4250, 0
7468 20:11:43.730370 160 : 4250, 0
7469 20:11:43.730437 164 : 4250, 0
7470 20:11:43.730498 168 : 4250, 0
7471 20:11:43.733847 172 : 4250, 0
7472 20:11:43.733917 176 : 4250, 0
7473 20:11:43.737288 180 : 4250, 0
7474 20:11:43.737355 184 : 4250, 0
7475 20:11:43.737415 188 : 4250, 0
7476 20:11:43.740197 192 : 4250, 0
7477 20:11:43.740263 196 : 4360, 0
7478 20:11:43.743199 200 : 4361, 0
7479 20:11:43.743272 204 : 4250, 0
7480 20:11:43.743363 208 : 4250, 0
7481 20:11:43.747534 212 : 4250, 0
7482 20:11:43.747634 216 : 4250, 0
7483 20:11:43.749898 220 : 4250, 0
7484 20:11:43.749997 224 : 4249, 307
7485 20:11:43.753482 228 : 4361, 3283
7486 20:11:43.753582 232 : 4250, 4027
7487 20:11:43.756272 236 : 4361, 4137
7488 20:11:43.756341 240 : 4360, 4137
7489 20:11:43.756406 244 : 4249, 4027
7490 20:11:43.760118 248 : 4250, 4026
7491 20:11:43.760189 252 : 4250, 4027
7492 20:11:43.763260 256 : 4249, 4027
7493 20:11:43.763353 260 : 4250, 4026
7494 20:11:43.766313 264 : 4250, 4026
7495 20:11:43.766415 268 : 4250, 4027
7496 20:11:43.770012 272 : 4250, 4027
7497 20:11:43.770109 276 : 4360, 4137
7498 20:11:43.773078 280 : 4361, 4137
7499 20:11:43.773177 284 : 4250, 4027
7500 20:11:43.776674 288 : 4363, 4140
7501 20:11:43.776773 292 : 4360, 4137
7502 20:11:43.779361 296 : 4250, 4026
7503 20:11:43.779461 300 : 4250, 4026
7504 20:11:43.783363 304 : 4250, 4027
7505 20:11:43.783462 308 : 4249, 4027
7506 20:11:43.783552 312 : 4250, 4026
7507 20:11:43.786281 316 : 4250, 4027
7508 20:11:43.786382 320 : 4250, 4027
7509 20:11:43.789662 324 : 4250, 4027
7510 20:11:43.789760 328 : 4360, 4137
7511 20:11:43.793034 332 : 4361, 4137
7512 20:11:43.793129 336 : 4247, 3659
7513 20:11:43.796051 340 : 4360, 1458
7514 20:11:43.796119
7515 20:11:43.796179 MIOCK jitter meter ch=0
7516 20:11:43.799609
7517 20:11:43.799734 1T = (340-92) = 248 dly cells
7518 20:11:43.806330 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7519 20:11:43.806434 ==
7520 20:11:43.810016 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 20:11:43.812741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 20:11:43.812813 ==
7523 20:11:43.819404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 20:11:43.822399 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 20:11:43.829195 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 20:11:43.832389 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 20:11:43.845908 [CA 0] Center 43 (13~74) winsize 62
7528 20:11:43.846057 [CA 1] Center 43 (13~74) winsize 62
7529 20:11:43.849331 [CA 2] Center 39 (10~69) winsize 60
7530 20:11:43.852510 [CA 3] Center 39 (9~69) winsize 61
7531 20:11:43.856206 [CA 4] Center 37 (8~66) winsize 59
7532 20:11:43.858861 [CA 5] Center 36 (7~66) winsize 60
7533 20:11:43.858955
7534 20:11:43.862417 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 20:11:43.865828
7536 20:11:43.869027 [CATrainingPosCal] consider 1 rank data
7537 20:11:43.869127 u2DelayCellTimex100 = 262/100 ps
7538 20:11:43.875509 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7539 20:11:43.879166 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7540 20:11:43.882210 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7541 20:11:43.885254 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7542 20:11:43.888611 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7543 20:11:43.892298 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7544 20:11:43.892369
7545 20:11:43.895000 CA PerBit enable=1, Macro0, CA PI delay=36
7546 20:11:43.898362
7547 20:11:43.898462 [CBTSetCACLKResult] CA Dly = 36
7548 20:11:43.901934 CS Dly: 11 (0~42)
7549 20:11:43.905505 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 20:11:43.908521 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 20:11:43.911579 ==
7552 20:11:43.914985 Dram Type= 6, Freq= 0, CH_0, rank 1
7553 20:11:43.918144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 20:11:43.918215 ==
7555 20:11:43.924605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 20:11:43.928462 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 20:11:43.931477 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 20:11:43.937815 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 20:11:43.946775 [CA 0] Center 43 (13~74) winsize 62
7560 20:11:43.950320 [CA 1] Center 44 (14~74) winsize 61
7561 20:11:43.953336 [CA 2] Center 38 (9~68) winsize 60
7562 20:11:43.956505 [CA 3] Center 38 (9~68) winsize 60
7563 20:11:43.960200 [CA 4] Center 36 (7~66) winsize 60
7564 20:11:43.962923 [CA 5] Center 36 (7~66) winsize 60
7565 20:11:43.962993
7566 20:11:43.966896 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 20:11:43.966967
7568 20:11:43.969620 [CATrainingPosCal] consider 2 rank data
7569 20:11:43.972852 u2DelayCellTimex100 = 262/100 ps
7570 20:11:43.979572 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7571 20:11:43.982666 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7572 20:11:43.986088 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7573 20:11:43.989314 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7574 20:11:43.993093 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7575 20:11:43.996178 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7576 20:11:43.996282
7577 20:11:43.999336 CA PerBit enable=1, Macro0, CA PI delay=36
7578 20:11:43.999436
7579 20:11:44.002558 [CBTSetCACLKResult] CA Dly = 36
7580 20:11:44.006086 CS Dly: 12 (0~44)
7581 20:11:44.009417 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 20:11:44.012513 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 20:11:44.012613
7584 20:11:44.016379 ----->DramcWriteLeveling(PI) begin...
7585 20:11:44.016479 ==
7586 20:11:44.019339 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 20:11:44.025883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 20:11:44.025989 ==
7589 20:11:44.029074 Write leveling (Byte 0): 36 => 36
7590 20:11:44.032105 Write leveling (Byte 1): 27 => 27
7591 20:11:44.032185 DramcWriteLeveling(PI) end<-----
7592 20:11:44.036123
7593 20:11:44.036204 ==
7594 20:11:44.038884 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 20:11:44.042692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 20:11:44.042769 ==
7597 20:11:44.045834 [Gating] SW mode calibration
7598 20:11:44.052018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7599 20:11:44.055692 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7600 20:11:44.062009 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 20:11:44.065392 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 20:11:44.071641 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 20:11:44.075205 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7604 20:11:44.078294 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7605 20:11:44.085325 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 20:11:44.088321 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7607 20:11:44.091361 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 20:11:44.098066 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 20:11:44.101536 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 20:11:44.104681 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7611 20:11:44.111573 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7612 20:11:44.114454 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7613 20:11:44.117927 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 20:11:44.124386 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7615 20:11:44.128296 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 20:11:44.131201 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 20:11:44.134693 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 20:11:44.141135 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 20:11:44.144116 1 6 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7620 20:11:44.150914 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7621 20:11:44.154434 1 6 20 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
7622 20:11:44.157926 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7623 20:11:44.164125 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 20:11:44.168005 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 20:11:44.170386 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 20:11:44.177437 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 20:11:44.180441 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 20:11:44.183571 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7629 20:11:44.190212 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 20:11:44.194072 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 20:11:44.196988 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 20:11:44.203525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 20:11:44.207276 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 20:11:44.210398 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 20:11:44.216871 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 20:11:44.220099 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 20:11:44.223150 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 20:11:44.230081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 20:11:44.233368 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 20:11:44.236907 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 20:11:44.243822 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 20:11:44.246478 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 20:11:44.249891 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7644 20:11:44.253567 Total UI for P1: 0, mck2ui 16
7645 20:11:44.256113 best dqsien dly found for B0: ( 1, 9, 8)
7646 20:11:44.260149 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 20:11:44.266834 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 20:11:44.269669 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 20:11:44.272980 Total UI for P1: 0, mck2ui 16
7650 20:11:44.275820 best dqsien dly found for B1: ( 1, 9, 18)
7651 20:11:44.279312 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7652 20:11:44.282515 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7653 20:11:44.282618
7654 20:11:44.285859 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7655 20:11:44.292543 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7656 20:11:44.292623 [Gating] SW calibration Done
7657 20:11:44.296028 ==
7658 20:11:44.296107 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 20:11:44.302297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 20:11:44.302398 ==
7661 20:11:44.302490 RX Vref Scan: 0
7662 20:11:44.302578
7663 20:11:44.305798 RX Vref 0 -> 0, step: 1
7664 20:11:44.305913
7665 20:11:44.309166 RX Delay 0 -> 252, step: 8
7666 20:11:44.312175 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7667 20:11:44.315960 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7668 20:11:44.318967 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7669 20:11:44.325378 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7670 20:11:44.328636 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7671 20:11:44.331704 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7672 20:11:44.335441 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7673 20:11:44.338510 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7674 20:11:44.345011 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7675 20:11:44.348414 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7676 20:11:44.351606 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7677 20:11:44.355050 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7678 20:11:44.361582 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7679 20:11:44.364958 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7680 20:11:44.368125 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7681 20:11:44.371346 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7682 20:11:44.371444 ==
7683 20:11:44.374839 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 20:11:44.381319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 20:11:44.381395 ==
7686 20:11:44.381458 DQS Delay:
7687 20:11:44.381517 DQS0 = 0, DQS1 = 0
7688 20:11:44.384367 DQM Delay:
7689 20:11:44.384462 DQM0 = 134, DQM1 = 126
7690 20:11:44.388035 DQ Delay:
7691 20:11:44.391404 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7692 20:11:44.394259 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7693 20:11:44.397591 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7694 20:11:44.401671 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7695 20:11:44.401746
7696 20:11:44.401810
7697 20:11:44.401869 ==
7698 20:11:44.404308 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 20:11:44.410923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 20:11:44.411021 ==
7701 20:11:44.411087
7702 20:11:44.411148
7703 20:11:44.411204 TX Vref Scan disable
7704 20:11:44.414375 == TX Byte 0 ==
7705 20:11:44.417652 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7706 20:11:44.424296 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7707 20:11:44.424380 == TX Byte 1 ==
7708 20:11:44.427446 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7709 20:11:44.434157 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7710 20:11:44.434233 ==
7711 20:11:44.437420 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 20:11:44.440848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 20:11:44.440934 ==
7714 20:11:44.453958
7715 20:11:44.456986 TX Vref early break, caculate TX vref
7716 20:11:44.461145 TX Vref=16, minBit 4, minWin=22, winSum=370
7717 20:11:44.464026 TX Vref=18, minBit 4, minWin=22, winSum=376
7718 20:11:44.467258 TX Vref=20, minBit 1, minWin=23, winSum=391
7719 20:11:44.470577 TX Vref=22, minBit 7, minWin=24, winSum=401
7720 20:11:44.473682 TX Vref=24, minBit 0, minWin=25, winSum=405
7721 20:11:44.479904 TX Vref=26, minBit 3, minWin=25, winSum=420
7722 20:11:44.483398 TX Vref=28, minBit 4, minWin=24, winSum=418
7723 20:11:44.486998 TX Vref=30, minBit 4, minWin=24, winSum=410
7724 20:11:44.489908 TX Vref=32, minBit 0, minWin=24, winSum=401
7725 20:11:44.493684 TX Vref=34, minBit 7, minWin=23, winSum=388
7726 20:11:44.500287 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 26
7727 20:11:44.500362
7728 20:11:44.503364 Final TX Range 0 Vref 26
7729 20:11:44.503474
7730 20:11:44.503564 ==
7731 20:11:44.507108 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 20:11:44.509785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 20:11:44.509860 ==
7734 20:11:44.509923
7735 20:11:44.509981
7736 20:11:44.512869 TX Vref Scan disable
7737 20:11:44.519753 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7738 20:11:44.519857 == TX Byte 0 ==
7739 20:11:44.523116 u2DelayCellOfst[0]=14 cells (4 PI)
7740 20:11:44.526429 u2DelayCellOfst[1]=18 cells (5 PI)
7741 20:11:44.529599 u2DelayCellOfst[2]=14 cells (4 PI)
7742 20:11:44.532650 u2DelayCellOfst[3]=14 cells (4 PI)
7743 20:11:44.536056 u2DelayCellOfst[4]=11 cells (3 PI)
7744 20:11:44.539637 u2DelayCellOfst[5]=0 cells (0 PI)
7745 20:11:44.542715 u2DelayCellOfst[6]=22 cells (6 PI)
7746 20:11:44.546014 u2DelayCellOfst[7]=18 cells (5 PI)
7747 20:11:44.549400 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7748 20:11:44.552726 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7749 20:11:44.556535 == TX Byte 1 ==
7750 20:11:44.559279 u2DelayCellOfst[8]=0 cells (0 PI)
7751 20:11:44.562686 u2DelayCellOfst[9]=0 cells (0 PI)
7752 20:11:44.566208 u2DelayCellOfst[10]=7 cells (2 PI)
7753 20:11:44.569274 u2DelayCellOfst[11]=0 cells (0 PI)
7754 20:11:44.569346 u2DelayCellOfst[12]=11 cells (3 PI)
7755 20:11:44.572508 u2DelayCellOfst[13]=7 cells (2 PI)
7756 20:11:44.576005 u2DelayCellOfst[14]=11 cells (3 PI)
7757 20:11:44.579136 u2DelayCellOfst[15]=7 cells (2 PI)
7758 20:11:44.585583 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7759 20:11:44.588698 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7760 20:11:44.588800 DramC Write-DBI on
7761 20:11:44.592110 ==
7762 20:11:44.595693 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 20:11:44.598871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 20:11:44.598967 ==
7765 20:11:44.599057
7766 20:11:44.599146
7767 20:11:44.602042 TX Vref Scan disable
7768 20:11:44.602135 == TX Byte 0 ==
7769 20:11:44.608700 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7770 20:11:44.608778 == TX Byte 1 ==
7771 20:11:44.612404 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7772 20:11:44.615127 DramC Write-DBI off
7773 20:11:44.615223
7774 20:11:44.615311 [DATLAT]
7775 20:11:44.618723 Freq=1600, CH0 RK0
7776 20:11:44.618793
7777 20:11:44.618856 DATLAT Default: 0xf
7778 20:11:44.621903 0, 0xFFFF, sum = 0
7779 20:11:44.621979 1, 0xFFFF, sum = 0
7780 20:11:44.625362 2, 0xFFFF, sum = 0
7781 20:11:44.625462 3, 0xFFFF, sum = 0
7782 20:11:44.628237 4, 0xFFFF, sum = 0
7783 20:11:44.631586 5, 0xFFFF, sum = 0
7784 20:11:44.631696 6, 0xFFFF, sum = 0
7785 20:11:44.634797 7, 0xFFFF, sum = 0
7786 20:11:44.634867 8, 0xFFFF, sum = 0
7787 20:11:44.637701 9, 0xFFFF, sum = 0
7788 20:11:44.637797 10, 0xFFFF, sum = 0
7789 20:11:44.641094 11, 0xFFFF, sum = 0
7790 20:11:44.641188 12, 0xFFFF, sum = 0
7791 20:11:44.644531 13, 0xFFFF, sum = 0
7792 20:11:44.644627 14, 0x0, sum = 1
7793 20:11:44.647828 15, 0x0, sum = 2
7794 20:11:44.647907 16, 0x0, sum = 3
7795 20:11:44.651693 17, 0x0, sum = 4
7796 20:11:44.651781 best_step = 15
7797 20:11:44.651842
7798 20:11:44.651901 ==
7799 20:11:44.654693 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 20:11:44.660862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 20:11:44.660935 ==
7802 20:11:44.661001 RX Vref Scan: 1
7803 20:11:44.661114
7804 20:11:44.664741 Set Vref Range= 24 -> 127
7805 20:11:44.664814
7806 20:11:44.667716 RX Vref 24 -> 127, step: 1
7807 20:11:44.667805
7808 20:11:44.671233 RX Delay 11 -> 252, step: 4
7809 20:11:44.671376
7810 20:11:44.674115 Set Vref, RX VrefLevel [Byte0]: 24
7811 20:11:44.674218 [Byte1]: 24
7812 20:11:44.678373
7813 20:11:44.678470 Set Vref, RX VrefLevel [Byte0]: 25
7814 20:11:44.681937 [Byte1]: 25
7815 20:11:44.685863
7816 20:11:44.685935 Set Vref, RX VrefLevel [Byte0]: 26
7817 20:11:44.689274 [Byte1]: 26
7818 20:11:44.693540
7819 20:11:44.693611 Set Vref, RX VrefLevel [Byte0]: 27
7820 20:11:44.697185 [Byte1]: 27
7821 20:11:44.701550
7822 20:11:44.701647 Set Vref, RX VrefLevel [Byte0]: 28
7823 20:11:44.704925 [Byte1]: 28
7824 20:11:44.709310
7825 20:11:44.709388 Set Vref, RX VrefLevel [Byte0]: 29
7826 20:11:44.712587 [Byte1]: 29
7827 20:11:44.716981
7828 20:11:44.717054 Set Vref, RX VrefLevel [Byte0]: 30
7829 20:11:44.719777 [Byte1]: 30
7830 20:11:44.724249
7831 20:11:44.724324 Set Vref, RX VrefLevel [Byte0]: 31
7832 20:11:44.727645 [Byte1]: 31
7833 20:11:44.731755
7834 20:11:44.731828 Set Vref, RX VrefLevel [Byte0]: 32
7835 20:11:44.734954 [Byte1]: 32
7836 20:11:44.739295
7837 20:11:44.739395 Set Vref, RX VrefLevel [Byte0]: 33
7838 20:11:44.742758 [Byte1]: 33
7839 20:11:44.747058
7840 20:11:44.747156 Set Vref, RX VrefLevel [Byte0]: 34
7841 20:11:44.750570 [Byte1]: 34
7842 20:11:44.754219
7843 20:11:44.754319 Set Vref, RX VrefLevel [Byte0]: 35
7844 20:11:44.757835 [Byte1]: 35
7845 20:11:44.762146
7846 20:11:44.762243 Set Vref, RX VrefLevel [Byte0]: 36
7847 20:11:44.765652 [Byte1]: 36
7848 20:11:44.769584
7849 20:11:44.769680 Set Vref, RX VrefLevel [Byte0]: 37
7850 20:11:44.773108 [Byte1]: 37
7851 20:11:44.777104
7852 20:11:44.777176 Set Vref, RX VrefLevel [Byte0]: 38
7853 20:11:44.780393 [Byte1]: 38
7854 20:11:44.784991
7855 20:11:44.785092 Set Vref, RX VrefLevel [Byte0]: 39
7856 20:11:44.788736 [Byte1]: 39
7857 20:11:44.792448
7858 20:11:44.792519 Set Vref, RX VrefLevel [Byte0]: 40
7859 20:11:44.795778 [Byte1]: 40
7860 20:11:44.800196
7861 20:11:44.800295 Set Vref, RX VrefLevel [Byte0]: 41
7862 20:11:44.803457 [Byte1]: 41
7863 20:11:44.808304
7864 20:11:44.808382 Set Vref, RX VrefLevel [Byte0]: 42
7865 20:11:44.811317 [Byte1]: 42
7866 20:11:44.816202
7867 20:11:44.816279 Set Vref, RX VrefLevel [Byte0]: 43
7868 20:11:44.819001 [Byte1]: 43
7869 20:11:44.823223
7870 20:11:44.823321 Set Vref, RX VrefLevel [Byte0]: 44
7871 20:11:44.826788 [Byte1]: 44
7872 20:11:44.830987
7873 20:11:44.831062 Set Vref, RX VrefLevel [Byte0]: 45
7874 20:11:44.833719 [Byte1]: 45
7875 20:11:44.838263
7876 20:11:44.838335 Set Vref, RX VrefLevel [Byte0]: 46
7877 20:11:44.841797 [Byte1]: 46
7878 20:11:44.845674
7879 20:11:44.845766 Set Vref, RX VrefLevel [Byte0]: 47
7880 20:11:44.849345 [Byte1]: 47
7881 20:11:44.853347
7882 20:11:44.853425 Set Vref, RX VrefLevel [Byte0]: 48
7883 20:11:44.856574 [Byte1]: 48
7884 20:11:44.861204
7885 20:11:44.861293 Set Vref, RX VrefLevel [Byte0]: 49
7886 20:11:44.864253 [Byte1]: 49
7887 20:11:44.868590
7888 20:11:44.868661 Set Vref, RX VrefLevel [Byte0]: 50
7889 20:11:44.871995 [Byte1]: 50
7890 20:11:44.876614
7891 20:11:44.876685 Set Vref, RX VrefLevel [Byte0]: 51
7892 20:11:44.880067 [Byte1]: 51
7893 20:11:44.884605
7894 20:11:44.884701 Set Vref, RX VrefLevel [Byte0]: 52
7895 20:11:44.887261 [Byte1]: 52
7896 20:11:44.891331
7897 20:11:44.891414 Set Vref, RX VrefLevel [Byte0]: 53
7898 20:11:44.894691 [Byte1]: 53
7899 20:11:44.899230
7900 20:11:44.899311 Set Vref, RX VrefLevel [Byte0]: 54
7901 20:11:44.902579 [Byte1]: 54
7902 20:11:44.906701
7903 20:11:44.906782 Set Vref, RX VrefLevel [Byte0]: 55
7904 20:11:44.910085 [Byte1]: 55
7905 20:11:44.914315
7906 20:11:44.914396 Set Vref, RX VrefLevel [Byte0]: 56
7907 20:11:44.917724 [Byte1]: 56
7908 20:11:44.922035
7909 20:11:44.922116 Set Vref, RX VrefLevel [Byte0]: 57
7910 20:11:44.925406 [Byte1]: 57
7911 20:11:44.929432
7912 20:11:44.929513 Set Vref, RX VrefLevel [Byte0]: 58
7913 20:11:44.932720 [Byte1]: 58
7914 20:11:44.937244
7915 20:11:44.937325 Set Vref, RX VrefLevel [Byte0]: 59
7916 20:11:44.940707 [Byte1]: 59
7917 20:11:44.945273
7918 20:11:44.945380 Set Vref, RX VrefLevel [Byte0]: 60
7919 20:11:44.947995 [Byte1]: 60
7920 20:11:44.952399
7921 20:11:44.952475 Set Vref, RX VrefLevel [Byte0]: 61
7922 20:11:44.956105 [Byte1]: 61
7923 20:11:44.960263
7924 20:11:44.960361 Set Vref, RX VrefLevel [Byte0]: 62
7925 20:11:44.963083 [Byte1]: 62
7926 20:11:44.967543
7927 20:11:44.967643 Set Vref, RX VrefLevel [Byte0]: 63
7928 20:11:44.971278 [Byte1]: 63
7929 20:11:44.975286
7930 20:11:44.975385 Set Vref, RX VrefLevel [Byte0]: 64
7931 20:11:44.978645 [Byte1]: 64
7932 20:11:44.982984
7933 20:11:44.983082 Set Vref, RX VrefLevel [Byte0]: 65
7934 20:11:44.986326 [Byte1]: 65
7935 20:11:44.990491
7936 20:11:44.990591 Set Vref, RX VrefLevel [Byte0]: 66
7937 20:11:44.994050 [Byte1]: 66
7938 20:11:44.998179
7939 20:11:44.998251 Set Vref, RX VrefLevel [Byte0]: 67
7940 20:11:45.001444 [Byte1]: 67
7941 20:11:45.005894
7942 20:11:45.005970 Set Vref, RX VrefLevel [Byte0]: 68
7943 20:11:45.009082 [Byte1]: 68
7944 20:11:45.013282
7945 20:11:45.013356 Set Vref, RX VrefLevel [Byte0]: 69
7946 20:11:45.016978 [Byte1]: 69
7947 20:11:45.021337
7948 20:11:45.021412 Set Vref, RX VrefLevel [Byte0]: 70
7949 20:11:45.024125 [Byte1]: 70
7950 20:11:45.028491
7951 20:11:45.028574 Set Vref, RX VrefLevel [Byte0]: 71
7952 20:11:45.031835 [Byte1]: 71
7953 20:11:45.036184
7954 20:11:45.036265 Set Vref, RX VrefLevel [Byte0]: 72
7955 20:11:45.039630 [Byte1]: 72
7956 20:11:45.043626
7957 20:11:45.043713 Set Vref, RX VrefLevel [Byte0]: 73
7958 20:11:45.046922 [Byte1]: 73
7959 20:11:45.051180
7960 20:11:45.051261 Set Vref, RX VrefLevel [Byte0]: 74
7961 20:11:45.054408 [Byte1]: 74
7962 20:11:45.059237
7963 20:11:45.059319 Set Vref, RX VrefLevel [Byte0]: 75
7964 20:11:45.062476 [Byte1]: 75
7965 20:11:45.066827
7966 20:11:45.066909 Set Vref, RX VrefLevel [Byte0]: 76
7967 20:11:45.069839 [Byte1]: 76
7968 20:11:45.074008
7969 20:11:45.074088 Set Vref, RX VrefLevel [Byte0]: 77
7970 20:11:45.077640 [Byte1]: 77
7971 20:11:45.081780
7972 20:11:45.081861 Set Vref, RX VrefLevel [Byte0]: 78
7973 20:11:45.085690 [Byte1]: 78
7974 20:11:45.089391
7975 20:11:45.089506 Set Vref, RX VrefLevel [Byte0]: 79
7976 20:11:45.092507 [Byte1]: 79
7977 20:11:45.096909
7978 20:11:45.096990 Final RX Vref Byte 0 = 67 to rank0
7979 20:11:45.100501 Final RX Vref Byte 1 = 56 to rank0
7980 20:11:45.103901 Final RX Vref Byte 0 = 67 to rank1
7981 20:11:45.106853 Final RX Vref Byte 1 = 56 to rank1==
7982 20:11:45.110664 Dram Type= 6, Freq= 0, CH_0, rank 0
7983 20:11:45.117263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 20:11:45.117349 ==
7985 20:11:45.117416 DQS Delay:
7986 20:11:45.120367 DQS0 = 0, DQS1 = 0
7987 20:11:45.120451 DQM Delay:
7988 20:11:45.120518 DQM0 = 133, DQM1 = 124
7989 20:11:45.123595 DQ Delay:
7990 20:11:45.126872 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
7991 20:11:45.130101 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =140
7992 20:11:45.133268 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7993 20:11:45.136739 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =130
7994 20:11:45.136823
7995 20:11:45.136888
7996 20:11:45.136947
7997 20:11:45.140140 [DramC_TX_OE_Calibration] TA2
7998 20:11:45.143407 Original DQ_B0 (3 6) =30, OEN = 27
7999 20:11:45.146359 Original DQ_B1 (3 6) =30, OEN = 27
8000 20:11:45.150164 24, 0x0, End_B0=24 End_B1=24
8001 20:11:45.153287 25, 0x0, End_B0=25 End_B1=25
8002 20:11:45.153370 26, 0x0, End_B0=26 End_B1=26
8003 20:11:45.156155 27, 0x0, End_B0=27 End_B1=27
8004 20:11:45.159472 28, 0x0, End_B0=28 End_B1=28
8005 20:11:45.163021 29, 0x0, End_B0=29 End_B1=29
8006 20:11:45.163104 30, 0x0, End_B0=30 End_B1=30
8007 20:11:45.166287 31, 0x4141, End_B0=30 End_B1=30
8008 20:11:45.169266 Byte0 end_step=30 best_step=27
8009 20:11:45.173103 Byte1 end_step=30 best_step=27
8010 20:11:45.175836 Byte0 TX OE(2T, 0.5T) = (3, 3)
8011 20:11:45.179205 Byte1 TX OE(2T, 0.5T) = (3, 3)
8012 20:11:45.179286
8013 20:11:45.179351
8014 20:11:45.185861 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8015 20:11:45.189795 CH0 RK0: MR19=303, MR18=2112
8016 20:11:45.195512 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8017 20:11:45.195615
8018 20:11:45.199111 ----->DramcWriteLeveling(PI) begin...
8019 20:11:45.199214 ==
8020 20:11:45.202526 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 20:11:45.205519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 20:11:45.205589 ==
8023 20:11:45.208951 Write leveling (Byte 0): 34 => 34
8024 20:11:45.212395 Write leveling (Byte 1): 27 => 27
8025 20:11:45.215380 DramcWriteLeveling(PI) end<-----
8026 20:11:45.215478
8027 20:11:45.215569 ==
8028 20:11:45.218720 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 20:11:45.225807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 20:11:45.225889 ==
8031 20:11:45.225955 [Gating] SW mode calibration
8032 20:11:45.235691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8033 20:11:45.238842 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8034 20:11:45.242406 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 20:11:45.248730 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 20:11:45.251939 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 20:11:45.255898 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8038 20:11:45.262028 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8039 20:11:45.265555 1 4 20 | B1->B0 | 2f2e 3434 | 1 1 | (1 1) (1 1)
8040 20:11:45.268342 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 20:11:45.274938 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 20:11:45.278700 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 20:11:45.281635 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 20:11:45.288669 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8045 20:11:45.291758 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8046 20:11:45.295113 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 1)
8047 20:11:45.301470 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8048 20:11:45.305121 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8049 20:11:45.308784 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 20:11:45.314398 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 20:11:45.318110 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 20:11:45.321473 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 20:11:45.328207 1 6 12 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8054 20:11:45.331227 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8055 20:11:45.334439 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8056 20:11:45.340810 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 20:11:45.344161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 20:11:45.347531 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 20:11:45.354436 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 20:11:45.357502 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 20:11:45.360976 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 20:11:45.367419 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8063 20:11:45.370745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8064 20:11:45.374150 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 20:11:45.380985 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 20:11:45.383989 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 20:11:45.387172 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 20:11:45.394053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 20:11:45.397695 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 20:11:45.400950 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 20:11:45.406913 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 20:11:45.410327 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 20:11:45.413986 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 20:11:45.420458 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 20:11:45.423449 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 20:11:45.427105 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8077 20:11:45.433293 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 20:11:45.437440 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8079 20:11:45.439955 Total UI for P1: 0, mck2ui 16
8080 20:11:45.443474 best dqsien dly found for B0: ( 1, 9, 10)
8081 20:11:45.446524 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 20:11:45.450197 Total UI for P1: 0, mck2ui 16
8083 20:11:45.453169 best dqsien dly found for B1: ( 1, 9, 16)
8084 20:11:45.456482 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8085 20:11:45.459659 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8086 20:11:45.463135
8087 20:11:45.466443 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8088 20:11:45.469808 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8089 20:11:45.472990 [Gating] SW calibration Done
8090 20:11:45.473071 ==
8091 20:11:45.476131 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 20:11:45.479840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 20:11:45.479922 ==
8094 20:11:45.479986 RX Vref Scan: 0
8095 20:11:45.482948
8096 20:11:45.483056 RX Vref 0 -> 0, step: 1
8097 20:11:45.483153
8098 20:11:45.486085 RX Delay 0 -> 252, step: 8
8099 20:11:45.490021 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8100 20:11:45.493295 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8101 20:11:45.499209 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8102 20:11:45.502838 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8103 20:11:45.505859 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8104 20:11:45.509292 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8105 20:11:45.512524 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8106 20:11:45.519241 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8107 20:11:45.522693 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8108 20:11:45.525797 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8109 20:11:45.529179 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8110 20:11:45.535967 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8111 20:11:45.538941 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8112 20:11:45.543014 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8113 20:11:45.545625 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8114 20:11:45.549335 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8115 20:11:45.549417 ==
8116 20:11:45.552457 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 20:11:45.559187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 20:11:45.559274 ==
8119 20:11:45.559368 DQS Delay:
8120 20:11:45.562266 DQS0 = 0, DQS1 = 0
8121 20:11:45.562366 DQM Delay:
8122 20:11:45.565781 DQM0 = 133, DQM1 = 128
8123 20:11:45.565854 DQ Delay:
8124 20:11:45.568724 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8125 20:11:45.572414 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8126 20:11:45.575329 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8127 20:11:45.578681 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8128 20:11:45.578762
8129 20:11:45.578827
8130 20:11:45.578886 ==
8131 20:11:45.582171 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 20:11:45.588513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 20:11:45.588596 ==
8134 20:11:45.588661
8135 20:11:45.588721
8136 20:11:45.588779 TX Vref Scan disable
8137 20:11:45.592715 == TX Byte 0 ==
8138 20:11:45.595529 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8139 20:11:45.602129 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8140 20:11:45.602214 == TX Byte 1 ==
8141 20:11:45.605224 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8142 20:11:45.611890 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8143 20:11:45.611972 ==
8144 20:11:45.615364 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 20:11:45.618584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 20:11:45.618665 ==
8147 20:11:45.631734
8148 20:11:45.635296 TX Vref early break, caculate TX vref
8149 20:11:45.638655 TX Vref=16, minBit 1, minWin=22, winSum=375
8150 20:11:45.641970 TX Vref=18, minBit 3, minWin=22, winSum=385
8151 20:11:45.645136 TX Vref=20, minBit 3, minWin=23, winSum=396
8152 20:11:45.648149 TX Vref=22, minBit 1, minWin=24, winSum=401
8153 20:11:45.651562 TX Vref=24, minBit 4, minWin=24, winSum=409
8154 20:11:45.657967 TX Vref=26, minBit 0, minWin=24, winSum=412
8155 20:11:45.661669 TX Vref=28, minBit 0, minWin=24, winSum=408
8156 20:11:45.664941 TX Vref=30, minBit 1, minWin=23, winSum=399
8157 20:11:45.668228 TX Vref=32, minBit 0, minWin=24, winSum=395
8158 20:11:45.671401 TX Vref=34, minBit 1, minWin=23, winSum=386
8159 20:11:45.678217 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 26
8160 20:11:45.678325
8161 20:11:45.681214 Final TX Range 0 Vref 26
8162 20:11:45.681342
8163 20:11:45.681407 ==
8164 20:11:45.684735 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 20:11:45.688078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 20:11:45.688180 ==
8167 20:11:45.688292
8168 20:11:45.688394
8169 20:11:45.691122 TX Vref Scan disable
8170 20:11:45.697704 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8171 20:11:45.697781 == TX Byte 0 ==
8172 20:11:45.701025 u2DelayCellOfst[0]=11 cells (3 PI)
8173 20:11:45.704617 u2DelayCellOfst[1]=14 cells (4 PI)
8174 20:11:45.707874 u2DelayCellOfst[2]=11 cells (3 PI)
8175 20:11:45.710879 u2DelayCellOfst[3]=14 cells (4 PI)
8176 20:11:45.714181 u2DelayCellOfst[4]=7 cells (2 PI)
8177 20:11:45.717084 u2DelayCellOfst[5]=0 cells (0 PI)
8178 20:11:45.720730 u2DelayCellOfst[6]=18 cells (5 PI)
8179 20:11:45.723941 u2DelayCellOfst[7]=18 cells (5 PI)
8180 20:11:45.727125 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8181 20:11:45.730391 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8182 20:11:45.733937 == TX Byte 1 ==
8183 20:11:45.737181 u2DelayCellOfst[8]=0 cells (0 PI)
8184 20:11:45.740587 u2DelayCellOfst[9]=3 cells (1 PI)
8185 20:11:45.743589 u2DelayCellOfst[10]=7 cells (2 PI)
8186 20:11:45.743713 u2DelayCellOfst[11]=3 cells (1 PI)
8187 20:11:45.747290 u2DelayCellOfst[12]=11 cells (3 PI)
8188 20:11:45.750324 u2DelayCellOfst[13]=11 cells (3 PI)
8189 20:11:45.753715 u2DelayCellOfst[14]=18 cells (5 PI)
8190 20:11:45.756953 u2DelayCellOfst[15]=11 cells (3 PI)
8191 20:11:45.763119 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8192 20:11:45.766923 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8193 20:11:45.766998 DramC Write-DBI on
8194 20:11:45.770345 ==
8195 20:11:45.773473 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 20:11:45.777006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 20:11:45.777107 ==
8198 20:11:45.777197
8199 20:11:45.777284
8200 20:11:45.780126 TX Vref Scan disable
8201 20:11:45.780219 == TX Byte 0 ==
8202 20:11:45.786394 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8203 20:11:45.786532 == TX Byte 1 ==
8204 20:11:45.789893 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8205 20:11:45.792823 DramC Write-DBI off
8206 20:11:45.792922
8207 20:11:45.793060 [DATLAT]
8208 20:11:45.796374 Freq=1600, CH0 RK1
8209 20:11:45.796483
8210 20:11:45.796572 DATLAT Default: 0xf
8211 20:11:45.799573 0, 0xFFFF, sum = 0
8212 20:11:45.799680 1, 0xFFFF, sum = 0
8213 20:11:45.802584 2, 0xFFFF, sum = 0
8214 20:11:45.806385 3, 0xFFFF, sum = 0
8215 20:11:45.806461 4, 0xFFFF, sum = 0
8216 20:11:45.809624 5, 0xFFFF, sum = 0
8217 20:11:45.809702 6, 0xFFFF, sum = 0
8218 20:11:45.812518 7, 0xFFFF, sum = 0
8219 20:11:45.812588 8, 0xFFFF, sum = 0
8220 20:11:45.816009 9, 0xFFFF, sum = 0
8221 20:11:45.816084 10, 0xFFFF, sum = 0
8222 20:11:45.819548 11, 0xFFFF, sum = 0
8223 20:11:45.819624 12, 0xFFFF, sum = 0
8224 20:11:45.822752 13, 0xFFFF, sum = 0
8225 20:11:45.822858 14, 0x0, sum = 1
8226 20:11:45.825864 15, 0x0, sum = 2
8227 20:11:45.825969 16, 0x0, sum = 3
8228 20:11:45.829544 17, 0x0, sum = 4
8229 20:11:45.829624 best_step = 15
8230 20:11:45.829716
8231 20:11:45.829805 ==
8232 20:11:45.832414 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 20:11:45.839304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 20:11:45.839416 ==
8235 20:11:45.839515 RX Vref Scan: 0
8236 20:11:45.839606
8237 20:11:45.842929 RX Vref 0 -> 0, step: 1
8238 20:11:45.843034
8239 20:11:45.845739 RX Delay 11 -> 252, step: 4
8240 20:11:45.848986 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8241 20:11:45.852401 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8242 20:11:45.855584 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8243 20:11:45.862580 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8244 20:11:45.866433 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8245 20:11:45.868737 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8246 20:11:45.871946 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8247 20:11:45.875462 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8248 20:11:45.881795 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8249 20:11:45.885534 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8250 20:11:45.888615 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8251 20:11:45.891879 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8252 20:11:45.898363 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8253 20:11:45.901850 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8254 20:11:45.904789 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8255 20:11:45.908200 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8256 20:11:45.908284 ==
8257 20:11:45.911402 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 20:11:45.918265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 20:11:45.918350 ==
8260 20:11:45.918416 DQS Delay:
8261 20:11:45.922209 DQS0 = 0, DQS1 = 0
8262 20:11:45.922292 DQM Delay:
8263 20:11:45.922358 DQM0 = 130, DQM1 = 125
8264 20:11:45.924897 DQ Delay:
8265 20:11:45.927632 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8266 20:11:45.931543 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8267 20:11:45.934698 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8268 20:11:45.938024 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8269 20:11:45.938128
8270 20:11:45.938198
8271 20:11:45.938259
8272 20:11:45.941154 [DramC_TX_OE_Calibration] TA2
8273 20:11:45.944747 Original DQ_B0 (3 6) =30, OEN = 27
8274 20:11:45.948107 Original DQ_B1 (3 6) =30, OEN = 27
8275 20:11:45.950854 24, 0x0, End_B0=24 End_B1=24
8276 20:11:45.954247 25, 0x0, End_B0=25 End_B1=25
8277 20:11:45.954360 26, 0x0, End_B0=26 End_B1=26
8278 20:11:45.957712 27, 0x0, End_B0=27 End_B1=27
8279 20:11:45.960541 28, 0x0, End_B0=28 End_B1=28
8280 20:11:45.963773 29, 0x0, End_B0=29 End_B1=29
8281 20:11:45.967475 30, 0x0, End_B0=30 End_B1=30
8282 20:11:45.967559 31, 0x4141, End_B0=30 End_B1=30
8283 20:11:45.970652 Byte0 end_step=30 best_step=27
8284 20:11:45.974192 Byte1 end_step=30 best_step=27
8285 20:11:45.977360 Byte0 TX OE(2T, 0.5T) = (3, 3)
8286 20:11:45.980880 Byte1 TX OE(2T, 0.5T) = (3, 3)
8287 20:11:45.980971
8288 20:11:45.981038
8289 20:11:45.987301 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8290 20:11:45.990545 CH0 RK1: MR19=303, MR18=1F03
8291 20:11:45.996853 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8292 20:11:46.000442 [RxdqsGatingPostProcess] freq 1600
8293 20:11:46.006992 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8294 20:11:46.007111 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 20:11:46.010358 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 20:11:46.013793 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 20:11:46.016673 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 20:11:46.020508 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 20:11:46.023601 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 20:11:46.026707 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 20:11:46.030197 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 20:11:46.033927 Pre-setting of DQS Precalculation
8303 20:11:46.037337 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8304 20:11:46.039612 ==
8305 20:11:46.039749 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 20:11:46.048001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 20:11:46.048108 ==
8308 20:11:46.050491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 20:11:46.056092 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 20:11:46.059632 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 20:11:46.066186 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 20:11:46.074505 [CA 0] Center 42 (13~72) winsize 60
8313 20:11:46.078357 [CA 1] Center 42 (13~72) winsize 60
8314 20:11:46.081259 [CA 2] Center 37 (9~66) winsize 58
8315 20:11:46.084184 [CA 3] Center 37 (8~66) winsize 59
8316 20:11:46.087800 [CA 4] Center 38 (8~68) winsize 61
8317 20:11:46.090736 [CA 5] Center 37 (8~67) winsize 60
8318 20:11:46.090836
8319 20:11:46.093862 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8320 20:11:46.093936
8321 20:11:46.100486 [CATrainingPosCal] consider 1 rank data
8322 20:11:46.100562 u2DelayCellTimex100 = 262/100 ps
8323 20:11:46.107096 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8324 20:11:46.110641 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8325 20:11:46.114040 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8326 20:11:46.116950 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8327 20:11:46.120295 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8328 20:11:46.123661 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8329 20:11:46.123794
8330 20:11:46.127596 CA PerBit enable=1, Macro0, CA PI delay=37
8331 20:11:46.127733
8332 20:11:46.130450 [CBTSetCACLKResult] CA Dly = 37
8333 20:11:46.134229 CS Dly: 8 (0~39)
8334 20:11:46.136631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 20:11:46.140338 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 20:11:46.140413 ==
8337 20:11:46.143336 Dram Type= 6, Freq= 0, CH_1, rank 1
8338 20:11:46.150430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 20:11:46.150526 ==
8340 20:11:46.154029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 20:11:46.159640 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 20:11:46.163281 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 20:11:46.169757 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 20:11:46.177769 [CA 0] Center 42 (13~71) winsize 59
8345 20:11:46.180694 [CA 1] Center 42 (13~72) winsize 60
8346 20:11:46.184029 [CA 2] Center 37 (8~67) winsize 60
8347 20:11:46.187458 [CA 3] Center 37 (8~66) winsize 59
8348 20:11:46.190991 [CA 4] Center 37 (8~67) winsize 60
8349 20:11:46.194094 [CA 5] Center 37 (7~67) winsize 61
8350 20:11:46.194175
8351 20:11:46.197358 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 20:11:46.197468
8353 20:11:46.200435 [CATrainingPosCal] consider 2 rank data
8354 20:11:46.204024 u2DelayCellTimex100 = 262/100 ps
8355 20:11:46.210653 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8356 20:11:46.213822 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8357 20:11:46.217008 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8358 20:11:46.220169 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8359 20:11:46.223443 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8360 20:11:46.226841 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8361 20:11:46.226947
8362 20:11:46.230523 CA PerBit enable=1, Macro0, CA PI delay=37
8363 20:11:46.230608
8364 20:11:46.233488 [CBTSetCACLKResult] CA Dly = 37
8365 20:11:46.236758 CS Dly: 10 (0~44)
8366 20:11:46.240743 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 20:11:46.243745 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 20:11:46.243827
8369 20:11:46.246723 ----->DramcWriteLeveling(PI) begin...
8370 20:11:46.246804 ==
8371 20:11:46.250146 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 20:11:46.256464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 20:11:46.256545 ==
8374 20:11:46.259979 Write leveling (Byte 0): 25 => 25
8375 20:11:46.263326 Write leveling (Byte 1): 27 => 27
8376 20:11:46.263403 DramcWriteLeveling(PI) end<-----
8377 20:11:46.266277
8378 20:11:46.266352 ==
8379 20:11:46.270153 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 20:11:46.273120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 20:11:46.273198 ==
8382 20:11:46.276370 [Gating] SW mode calibration
8383 20:11:46.283092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8384 20:11:46.286191 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8385 20:11:46.292893 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 20:11:46.296021 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 20:11:46.299416 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 20:11:46.306113 1 4 12 | B1->B0 | 2727 3333 | 0 1 | (0 0) (1 1)
8389 20:11:46.309720 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 20:11:46.312744 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 20:11:46.318787 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 20:11:46.322095 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 20:11:46.328724 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 20:11:46.332424 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 20:11:46.335349 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8396 20:11:46.342163 1 5 12 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (1 0)
8397 20:11:46.345698 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8398 20:11:46.348738 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 20:11:46.355523 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 20:11:46.358643 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 20:11:46.362133 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 20:11:46.368777 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 20:11:46.371489 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 20:11:46.374853 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8405 20:11:46.381217 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 20:11:46.384744 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 20:11:46.387699 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 20:11:46.394348 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 20:11:46.398254 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 20:11:46.400692 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 20:11:46.408060 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8412 20:11:46.411003 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 20:11:46.413766 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 20:11:46.420722 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 20:11:46.424370 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 20:11:46.427099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 20:11:46.433555 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 20:11:46.437294 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 20:11:46.440231 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 20:11:46.446959 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 20:11:46.449984 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 20:11:46.453829 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 20:11:46.460316 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 20:11:46.463566 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 20:11:46.466862 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 20:11:46.473088 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 20:11:46.476474 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8428 20:11:46.480004 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 20:11:46.486241 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 20:11:46.490115 Total UI for P1: 0, mck2ui 16
8431 20:11:46.492556 best dqsien dly found for B0: ( 1, 9, 10)
8432 20:11:46.496663 Total UI for P1: 0, mck2ui 16
8433 20:11:46.499382 best dqsien dly found for B1: ( 1, 9, 12)
8434 20:11:46.502600 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8435 20:11:46.506178 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8436 20:11:46.506280
8437 20:11:46.509593 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 20:11:46.512803 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8439 20:11:46.515708 [Gating] SW calibration Done
8440 20:11:46.515802 ==
8441 20:11:46.519429 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 20:11:46.522626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 20:11:46.522740 ==
8444 20:11:46.525766 RX Vref Scan: 0
8445 20:11:46.525842
8446 20:11:46.529646 RX Vref 0 -> 0, step: 1
8447 20:11:46.529723
8448 20:11:46.529791 RX Delay 0 -> 252, step: 8
8449 20:11:46.535625 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8450 20:11:46.539113 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8451 20:11:46.542697 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8452 20:11:46.545768 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8453 20:11:46.548947 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8454 20:11:46.555473 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8455 20:11:46.559233 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8456 20:11:46.562460 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8457 20:11:46.565819 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8458 20:11:46.568908 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8459 20:11:46.575640 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8460 20:11:46.578704 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8461 20:11:46.582028 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8462 20:11:46.585666 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8463 20:11:46.592123 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8464 20:11:46.595318 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8465 20:11:46.595427 ==
8466 20:11:46.598691 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 20:11:46.601996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 20:11:46.602080 ==
8469 20:11:46.602156 DQS Delay:
8470 20:11:46.605301 DQS0 = 0, DQS1 = 0
8471 20:11:46.605384 DQM Delay:
8472 20:11:46.609062 DQM0 = 136, DQM1 = 128
8473 20:11:46.609171 DQ Delay:
8474 20:11:46.611897 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8475 20:11:46.615194 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8476 20:11:46.618700 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8477 20:11:46.625439 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8478 20:11:46.625547
8479 20:11:46.625641
8480 20:11:46.625730 ==
8481 20:11:46.628571 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 20:11:46.631814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 20:11:46.631898 ==
8484 20:11:46.631965
8485 20:11:46.632026
8486 20:11:46.634744 TX Vref Scan disable
8487 20:11:46.634827 == TX Byte 0 ==
8488 20:11:46.641625 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8489 20:11:46.644543 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 20:11:46.648034 == TX Byte 1 ==
8491 20:11:46.651244 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8492 20:11:46.654622 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8493 20:11:46.654707 ==
8494 20:11:46.657662 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 20:11:46.661587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 20:11:46.664242 ==
8497 20:11:46.674228
8498 20:11:46.677161 TX Vref early break, caculate TX vref
8499 20:11:46.681070 TX Vref=16, minBit 6, minWin=22, winSum=379
8500 20:11:46.684402 TX Vref=18, minBit 0, minWin=22, winSum=388
8501 20:11:46.687480 TX Vref=20, minBit 0, minWin=24, winSum=400
8502 20:11:46.690844 TX Vref=22, minBit 5, minWin=23, winSum=405
8503 20:11:46.693724 TX Vref=24, minBit 0, minWin=25, winSum=417
8504 20:11:46.700278 TX Vref=26, minBit 0, minWin=25, winSum=427
8505 20:11:46.703496 TX Vref=28, minBit 0, minWin=26, winSum=425
8506 20:11:46.707174 TX Vref=30, minBit 0, minWin=25, winSum=416
8507 20:11:46.710476 TX Vref=32, minBit 9, minWin=23, winSum=402
8508 20:11:46.716926 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8509 20:11:46.717010
8510 20:11:46.719857 Final TX Range 0 Vref 28
8511 20:11:46.719941
8512 20:11:46.720007 ==
8513 20:11:46.723265 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 20:11:46.726792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 20:11:46.726903 ==
8516 20:11:46.726998
8517 20:11:46.727089
8518 20:11:46.729816 TX Vref Scan disable
8519 20:11:46.736765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8520 20:11:46.736849 == TX Byte 0 ==
8521 20:11:46.740181 u2DelayCellOfst[0]=18 cells (5 PI)
8522 20:11:46.743076 u2DelayCellOfst[1]=14 cells (4 PI)
8523 20:11:46.746297 u2DelayCellOfst[2]=0 cells (0 PI)
8524 20:11:46.749654 u2DelayCellOfst[3]=7 cells (2 PI)
8525 20:11:46.752767 u2DelayCellOfst[4]=11 cells (3 PI)
8526 20:11:46.756367 u2DelayCellOfst[5]=22 cells (6 PI)
8527 20:11:46.759605 u2DelayCellOfst[6]=22 cells (6 PI)
8528 20:11:46.762963 u2DelayCellOfst[7]=7 cells (2 PI)
8529 20:11:46.765942 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8530 20:11:46.769101 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8531 20:11:46.773045 == TX Byte 1 ==
8532 20:11:46.776271 u2DelayCellOfst[8]=0 cells (0 PI)
8533 20:11:46.776355 u2DelayCellOfst[9]=3 cells (1 PI)
8534 20:11:46.779541 u2DelayCellOfst[10]=11 cells (3 PI)
8535 20:11:46.783019 u2DelayCellOfst[11]=7 cells (2 PI)
8536 20:11:46.785989 u2DelayCellOfst[12]=14 cells (4 PI)
8537 20:11:46.789130 u2DelayCellOfst[13]=18 cells (5 PI)
8538 20:11:46.793267 u2DelayCellOfst[14]=18 cells (5 PI)
8539 20:11:46.795916 u2DelayCellOfst[15]=18 cells (5 PI)
8540 20:11:46.799315 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8541 20:11:46.805567 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8542 20:11:46.805652 DramC Write-DBI on
8543 20:11:46.805719 ==
8544 20:11:46.809251 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 20:11:46.816035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 20:11:46.816117 ==
8547 20:11:46.816183
8548 20:11:46.816276
8549 20:11:46.816333 TX Vref Scan disable
8550 20:11:46.819799 == TX Byte 0 ==
8551 20:11:46.822526 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8552 20:11:46.826093 == TX Byte 1 ==
8553 20:11:46.829309 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8554 20:11:46.832829 DramC Write-DBI off
8555 20:11:46.832906
8556 20:11:46.832985 [DATLAT]
8557 20:11:46.833060 Freq=1600, CH1 RK0
8558 20:11:46.833119
8559 20:11:46.835776 DATLAT Default: 0xf
8560 20:11:46.839432 0, 0xFFFF, sum = 0
8561 20:11:46.839516 1, 0xFFFF, sum = 0
8562 20:11:46.842596 2, 0xFFFF, sum = 0
8563 20:11:46.842679 3, 0xFFFF, sum = 0
8564 20:11:46.845581 4, 0xFFFF, sum = 0
8565 20:11:46.845664 5, 0xFFFF, sum = 0
8566 20:11:46.849343 6, 0xFFFF, sum = 0
8567 20:11:46.849427 7, 0xFFFF, sum = 0
8568 20:11:46.852365 8, 0xFFFF, sum = 0
8569 20:11:46.852448 9, 0xFFFF, sum = 0
8570 20:11:46.856081 10, 0xFFFF, sum = 0
8571 20:11:46.856164 11, 0xFFFF, sum = 0
8572 20:11:46.858929 12, 0xFFFF, sum = 0
8573 20:11:46.859012 13, 0xFFFF, sum = 0
8574 20:11:46.862261 14, 0x0, sum = 1
8575 20:11:46.862345 15, 0x0, sum = 2
8576 20:11:46.865875 16, 0x0, sum = 3
8577 20:11:46.865985 17, 0x0, sum = 4
8578 20:11:46.869214 best_step = 15
8579 20:11:46.869295
8580 20:11:46.869376 ==
8581 20:11:46.871941 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 20:11:46.875746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 20:11:46.875829 ==
8584 20:11:46.878659 RX Vref Scan: 1
8585 20:11:46.878741
8586 20:11:46.878806 Set Vref Range= 24 -> 127
8587 20:11:46.878904
8588 20:11:46.882158 RX Vref 24 -> 127, step: 1
8589 20:11:46.882256
8590 20:11:46.885371 RX Delay 11 -> 252, step: 4
8591 20:11:46.885453
8592 20:11:46.888569 Set Vref, RX VrefLevel [Byte0]: 24
8593 20:11:46.892221 [Byte1]: 24
8594 20:11:46.892302
8595 20:11:46.895640 Set Vref, RX VrefLevel [Byte0]: 25
8596 20:11:46.898683 [Byte1]: 25
8597 20:11:46.902474
8598 20:11:46.902556 Set Vref, RX VrefLevel [Byte0]: 26
8599 20:11:46.905683 [Byte1]: 26
8600 20:11:46.910366
8601 20:11:46.910467 Set Vref, RX VrefLevel [Byte0]: 27
8602 20:11:46.913285 [Byte1]: 27
8603 20:11:46.917591
8604 20:11:46.917702 Set Vref, RX VrefLevel [Byte0]: 28
8605 20:11:46.920634 [Byte1]: 28
8606 20:11:46.925292
8607 20:11:46.925403 Set Vref, RX VrefLevel [Byte0]: 29
8608 20:11:46.928314 [Byte1]: 29
8609 20:11:46.932514
8610 20:11:46.932607 Set Vref, RX VrefLevel [Byte0]: 30
8611 20:11:46.936230 [Byte1]: 30
8612 20:11:46.940384
8613 20:11:46.940465 Set Vref, RX VrefLevel [Byte0]: 31
8614 20:11:46.943899 [Byte1]: 31
8615 20:11:46.947872
8616 20:11:46.947952 Set Vref, RX VrefLevel [Byte0]: 32
8617 20:11:46.951343 [Byte1]: 32
8618 20:11:46.955726
8619 20:11:46.955806 Set Vref, RX VrefLevel [Byte0]: 33
8620 20:11:46.958717 [Byte1]: 33
8621 20:11:46.963866
8622 20:11:46.963946 Set Vref, RX VrefLevel [Byte0]: 34
8623 20:11:46.966174 [Byte1]: 34
8624 20:11:46.971390
8625 20:11:46.971471 Set Vref, RX VrefLevel [Byte0]: 35
8626 20:11:46.974395 [Byte1]: 35
8627 20:11:46.978339
8628 20:11:46.978420 Set Vref, RX VrefLevel [Byte0]: 36
8629 20:11:46.981882 [Byte1]: 36
8630 20:11:46.986614
8631 20:11:46.986695 Set Vref, RX VrefLevel [Byte0]: 37
8632 20:11:46.989480 [Byte1]: 37
8633 20:11:46.993546
8634 20:11:46.993627 Set Vref, RX VrefLevel [Byte0]: 38
8635 20:11:46.997111 [Byte1]: 38
8636 20:11:47.001885
8637 20:11:47.001966 Set Vref, RX VrefLevel [Byte0]: 39
8638 20:11:47.004870 [Byte1]: 39
8639 20:11:47.009065
8640 20:11:47.009146 Set Vref, RX VrefLevel [Byte0]: 40
8641 20:11:47.012184 [Byte1]: 40
8642 20:11:47.016707
8643 20:11:47.016787 Set Vref, RX VrefLevel [Byte0]: 41
8644 20:11:47.019866 [Byte1]: 41
8645 20:11:47.024048
8646 20:11:47.024130 Set Vref, RX VrefLevel [Byte0]: 42
8647 20:11:47.027139 [Byte1]: 42
8648 20:11:47.031526
8649 20:11:47.031609 Set Vref, RX VrefLevel [Byte0]: 43
8650 20:11:47.034840 [Byte1]: 43
8651 20:11:47.039644
8652 20:11:47.039734 Set Vref, RX VrefLevel [Byte0]: 44
8653 20:11:47.042714 [Byte1]: 44
8654 20:11:47.046815
8655 20:11:47.046898 Set Vref, RX VrefLevel [Byte0]: 45
8656 20:11:47.050134 [Byte1]: 45
8657 20:11:47.054332
8658 20:11:47.054413 Set Vref, RX VrefLevel [Byte0]: 46
8659 20:11:47.057596 [Byte1]: 46
8660 20:11:47.062190
8661 20:11:47.062273 Set Vref, RX VrefLevel [Byte0]: 47
8662 20:11:47.065497 [Byte1]: 47
8663 20:11:47.070038
8664 20:11:47.070137 Set Vref, RX VrefLevel [Byte0]: 48
8665 20:11:47.073311 [Byte1]: 48
8666 20:11:47.077468
8667 20:11:47.077599 Set Vref, RX VrefLevel [Byte0]: 49
8668 20:11:47.081023 [Byte1]: 49
8669 20:11:47.085453
8670 20:11:47.085535 Set Vref, RX VrefLevel [Byte0]: 50
8671 20:11:47.088416 [Byte1]: 50
8672 20:11:47.093169
8673 20:11:47.093277 Set Vref, RX VrefLevel [Byte0]: 51
8674 20:11:47.095975 [Byte1]: 51
8675 20:11:47.100782
8676 20:11:47.100869 Set Vref, RX VrefLevel [Byte0]: 52
8677 20:11:47.103336 [Byte1]: 52
8678 20:11:47.107989
8679 20:11:47.108091 Set Vref, RX VrefLevel [Byte0]: 53
8680 20:11:47.111198 [Byte1]: 53
8681 20:11:47.115687
8682 20:11:47.115781 Set Vref, RX VrefLevel [Byte0]: 54
8683 20:11:47.118811 [Byte1]: 54
8684 20:11:47.123253
8685 20:11:47.123330 Set Vref, RX VrefLevel [Byte0]: 55
8686 20:11:47.126818 [Byte1]: 55
8687 20:11:47.130615
8688 20:11:47.130767 Set Vref, RX VrefLevel [Byte0]: 56
8689 20:11:47.133841 [Byte1]: 56
8690 20:11:47.138641
8691 20:11:47.138755 Set Vref, RX VrefLevel [Byte0]: 57
8692 20:11:47.141516 [Byte1]: 57
8693 20:11:47.145998
8694 20:11:47.146072 Set Vref, RX VrefLevel [Byte0]: 58
8695 20:11:47.149477 [Byte1]: 58
8696 20:11:47.153625
8697 20:11:47.153702 Set Vref, RX VrefLevel [Byte0]: 59
8698 20:11:47.156505 [Byte1]: 59
8699 20:11:47.161241
8700 20:11:47.161365 Set Vref, RX VrefLevel [Byte0]: 60
8701 20:11:47.165282 [Byte1]: 60
8702 20:11:47.168598
8703 20:11:47.168690 Set Vref, RX VrefLevel [Byte0]: 61
8704 20:11:47.171846 [Byte1]: 61
8705 20:11:47.176666
8706 20:11:47.176752 Set Vref, RX VrefLevel [Byte0]: 62
8707 20:11:47.179664 [Byte1]: 62
8708 20:11:47.184225
8709 20:11:47.184304 Set Vref, RX VrefLevel [Byte0]: 63
8710 20:11:47.187017 [Byte1]: 63
8711 20:11:47.191455
8712 20:11:47.191534 Set Vref, RX VrefLevel [Byte0]: 64
8713 20:11:47.195003 [Byte1]: 64
8714 20:11:47.199192
8715 20:11:47.199275 Set Vref, RX VrefLevel [Byte0]: 65
8716 20:11:47.202402 [Byte1]: 65
8717 20:11:47.206931
8718 20:11:47.207035 Set Vref, RX VrefLevel [Byte0]: 66
8719 20:11:47.210335 [Byte1]: 66
8720 20:11:47.214827
8721 20:11:47.214907 Set Vref, RX VrefLevel [Byte0]: 67
8722 20:11:47.218371 [Byte1]: 67
8723 20:11:47.221959
8724 20:11:47.222069 Set Vref, RX VrefLevel [Byte0]: 68
8725 20:11:47.225318 [Byte1]: 68
8726 20:11:47.229579
8727 20:11:47.229696 Set Vref, RX VrefLevel [Byte0]: 69
8728 20:11:47.233129 [Byte1]: 69
8729 20:11:47.237168
8730 20:11:47.237243 Set Vref, RX VrefLevel [Byte0]: 70
8731 20:11:47.240704 [Byte1]: 70
8732 20:11:47.245174
8733 20:11:47.245284 Set Vref, RX VrefLevel [Byte0]: 71
8734 20:11:47.248341 [Byte1]: 71
8735 20:11:47.252407
8736 20:11:47.252495 Set Vref, RX VrefLevel [Byte0]: 72
8737 20:11:47.255612 [Byte1]: 72
8738 20:11:47.259877
8739 20:11:47.259951 Set Vref, RX VrefLevel [Byte0]: 73
8740 20:11:47.263782 [Byte1]: 73
8741 20:11:47.267615
8742 20:11:47.267736 Final RX Vref Byte 0 = 54 to rank0
8743 20:11:47.271538 Final RX Vref Byte 1 = 61 to rank0
8744 20:11:47.275345 Final RX Vref Byte 0 = 54 to rank1
8745 20:11:47.277493 Final RX Vref Byte 1 = 61 to rank1==
8746 20:11:47.280658 Dram Type= 6, Freq= 0, CH_1, rank 0
8747 20:11:47.287427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 20:11:47.287509 ==
8749 20:11:47.287575 DQS Delay:
8750 20:11:47.290882 DQS0 = 0, DQS1 = 0
8751 20:11:47.290966 DQM Delay:
8752 20:11:47.291033 DQM0 = 133, DQM1 = 128
8753 20:11:47.293826 DQ Delay:
8754 20:11:47.297075 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8755 20:11:47.300811 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8756 20:11:47.304218 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8757 20:11:47.307253 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8758 20:11:47.307354
8759 20:11:47.307446
8760 20:11:47.307546
8761 20:11:47.311064 [DramC_TX_OE_Calibration] TA2
8762 20:11:47.314070 Original DQ_B0 (3 6) =30, OEN = 27
8763 20:11:47.317363 Original DQ_B1 (3 6) =30, OEN = 27
8764 20:11:47.320420 24, 0x0, End_B0=24 End_B1=24
8765 20:11:47.323414 25, 0x0, End_B0=25 End_B1=25
8766 20:11:47.323525 26, 0x0, End_B0=26 End_B1=26
8767 20:11:47.327273 27, 0x0, End_B0=27 End_B1=27
8768 20:11:47.330251 28, 0x0, End_B0=28 End_B1=28
8769 20:11:47.334333 29, 0x0, End_B0=29 End_B1=29
8770 20:11:47.334410 30, 0x0, End_B0=30 End_B1=30
8771 20:11:47.336620 31, 0x4141, End_B0=30 End_B1=30
8772 20:11:47.340399 Byte0 end_step=30 best_step=27
8773 20:11:47.343813 Byte1 end_step=30 best_step=27
8774 20:11:47.346791 Byte0 TX OE(2T, 0.5T) = (3, 3)
8775 20:11:47.350052 Byte1 TX OE(2T, 0.5T) = (3, 3)
8776 20:11:47.350135
8777 20:11:47.350201
8778 20:11:47.356750 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8779 20:11:47.360063 CH1 RK0: MR19=303, MR18=1A0F
8780 20:11:47.366166 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8781 20:11:47.366256
8782 20:11:47.370170 ----->DramcWriteLeveling(PI) begin...
8783 20:11:47.370254 ==
8784 20:11:47.372894 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 20:11:47.376225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 20:11:47.376309 ==
8787 20:11:47.379233 Write leveling (Byte 0): 22 => 22
8788 20:11:47.382736 Write leveling (Byte 1): 27 => 27
8789 20:11:47.386154 DramcWriteLeveling(PI) end<-----
8790 20:11:47.386237
8791 20:11:47.386302 ==
8792 20:11:47.389317 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 20:11:47.395972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 20:11:47.396056 ==
8795 20:11:47.396123 [Gating] SW mode calibration
8796 20:11:47.405856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8797 20:11:47.409070 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8798 20:11:47.415643 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 20:11:47.418788 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 20:11:47.422259 1 4 8 | B1->B0 | 2727 2323 | 1 0 | (1 1) (0 0)
8801 20:11:47.428897 1 4 12 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8802 20:11:47.432318 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8803 20:11:47.435362 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 20:11:47.441853 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 20:11:47.446180 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 20:11:47.448588 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 20:11:47.455086 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 20:11:47.458195 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8809 20:11:47.461682 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8810 20:11:47.468324 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8811 20:11:47.471916 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 20:11:47.475412 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 20:11:47.481642 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 20:11:47.484991 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 20:11:47.488249 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 20:11:47.491507 1 6 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8817 20:11:47.498352 1 6 12 | B1->B0 | 4343 2424 | 0 0 | (0 0) (0 0)
8818 20:11:47.501533 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 20:11:47.504756 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 20:11:47.512065 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 20:11:47.514935 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 20:11:47.521423 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 20:11:47.524536 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 20:11:47.528611 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 20:11:47.534347 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8826 20:11:47.537750 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8827 20:11:47.541275 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 20:11:47.547781 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 20:11:47.550965 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 20:11:47.554376 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 20:11:47.561178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 20:11:47.564068 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 20:11:47.567547 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 20:11:47.570890 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 20:11:47.577353 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 20:11:47.580787 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 20:11:47.587257 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 20:11:47.590384 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 20:11:47.593874 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 20:11:47.600444 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8841 20:11:47.603659 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 20:11:47.606737 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8843 20:11:47.610676 Total UI for P1: 0, mck2ui 16
8844 20:11:47.613552 best dqsien dly found for B1: ( 1, 9, 10)
8845 20:11:47.616963 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 20:11:47.620008 Total UI for P1: 0, mck2ui 16
8847 20:11:47.623202 best dqsien dly found for B0: ( 1, 9, 12)
8848 20:11:47.629916 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8849 20:11:47.633196 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8850 20:11:47.633278
8851 20:11:47.636478 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8852 20:11:47.639720 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8853 20:11:47.642910 [Gating] SW calibration Done
8854 20:11:47.642991 ==
8855 20:11:47.646414 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 20:11:47.650067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 20:11:47.650149 ==
8858 20:11:47.653234 RX Vref Scan: 0
8859 20:11:47.653315
8860 20:11:47.653380 RX Vref 0 -> 0, step: 1
8861 20:11:47.653441
8862 20:11:47.656191 RX Delay 0 -> 252, step: 8
8863 20:11:47.659442 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8864 20:11:47.666430 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8865 20:11:47.669660 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8866 20:11:47.672603 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8867 20:11:47.675954 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8868 20:11:47.679169 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8869 20:11:47.685886 iDelay=208, Bit 6, Center 151 (96 ~ 207) 112
8870 20:11:47.689238 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8871 20:11:47.692390 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8872 20:11:47.696266 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8873 20:11:47.698934 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8874 20:11:47.705689 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8875 20:11:47.708978 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8876 20:11:47.712719 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8877 20:11:47.715917 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8878 20:11:47.722214 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8879 20:11:47.722296 ==
8880 20:11:47.725955 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 20:11:47.728803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 20:11:47.728901 ==
8883 20:11:47.728966 DQS Delay:
8884 20:11:47.732249 DQS0 = 0, DQS1 = 0
8885 20:11:47.732330 DQM Delay:
8886 20:11:47.735358 DQM0 = 137, DQM1 = 129
8887 20:11:47.735441 DQ Delay:
8888 20:11:47.738533 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8889 20:11:47.741903 DQ4 =135, DQ5 =147, DQ6 =151, DQ7 =135
8890 20:11:47.744980 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8891 20:11:47.748646 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8892 20:11:47.752333
8893 20:11:47.752439
8894 20:11:47.752540 ==
8895 20:11:47.754933 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 20:11:47.758094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 20:11:47.758193 ==
8898 20:11:47.758290
8899 20:11:47.758377
8900 20:11:47.761345 TX Vref Scan disable
8901 20:11:47.761439 == TX Byte 0 ==
8902 20:11:47.768437 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8903 20:11:47.771193 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8904 20:11:47.771288 == TX Byte 1 ==
8905 20:11:47.778089 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8906 20:11:47.781573 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8907 20:11:47.781673 ==
8908 20:11:47.784990 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 20:11:47.788159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 20:11:47.788282 ==
8911 20:11:47.803226
8912 20:11:47.806169 TX Vref early break, caculate TX vref
8913 20:11:47.809554 TX Vref=16, minBit 0, minWin=22, winSum=378
8914 20:11:47.812802 TX Vref=18, minBit 0, minWin=23, winSum=389
8915 20:11:47.816307 TX Vref=20, minBit 1, minWin=23, winSum=396
8916 20:11:47.819804 TX Vref=22, minBit 5, minWin=23, winSum=404
8917 20:11:47.822754 TX Vref=24, minBit 0, minWin=24, winSum=412
8918 20:11:47.829750 TX Vref=26, minBit 0, minWin=25, winSum=418
8919 20:11:47.833268 TX Vref=28, minBit 0, minWin=24, winSum=416
8920 20:11:47.837452 TX Vref=30, minBit 0, minWin=24, winSum=409
8921 20:11:47.839551 TX Vref=32, minBit 0, minWin=23, winSum=405
8922 20:11:47.842656 TX Vref=34, minBit 5, minWin=22, winSum=399
8923 20:11:47.849183 TX Vref=36, minBit 0, minWin=21, winSum=384
8924 20:11:47.852238 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8925 20:11:47.852338
8926 20:11:47.855645 Final TX Range 0 Vref 26
8927 20:11:47.855761
8928 20:11:47.855824 ==
8929 20:11:47.859299 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 20:11:47.862268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 20:11:47.865679 ==
8932 20:11:47.865787
8933 20:11:47.865878
8934 20:11:47.866012 TX Vref Scan disable
8935 20:11:47.872838 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8936 20:11:47.872937 == TX Byte 0 ==
8937 20:11:47.875864 u2DelayCellOfst[0]=14 cells (4 PI)
8938 20:11:47.879301 u2DelayCellOfst[1]=11 cells (3 PI)
8939 20:11:47.882059 u2DelayCellOfst[2]=0 cells (0 PI)
8940 20:11:47.886697 u2DelayCellOfst[3]=7 cells (2 PI)
8941 20:11:47.888820 u2DelayCellOfst[4]=7 cells (2 PI)
8942 20:11:47.892008 u2DelayCellOfst[5]=18 cells (5 PI)
8943 20:11:47.895537 u2DelayCellOfst[6]=18 cells (5 PI)
8944 20:11:47.899060 u2DelayCellOfst[7]=3 cells (1 PI)
8945 20:11:47.902002 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8946 20:11:47.905490 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8947 20:11:47.908705 == TX Byte 1 ==
8948 20:11:47.912012 u2DelayCellOfst[8]=0 cells (0 PI)
8949 20:11:47.915109 u2DelayCellOfst[9]=7 cells (2 PI)
8950 20:11:47.918234 u2DelayCellOfst[10]=11 cells (3 PI)
8951 20:11:47.921811 u2DelayCellOfst[11]=7 cells (2 PI)
8952 20:11:47.925041 u2DelayCellOfst[12]=14 cells (4 PI)
8953 20:11:47.928603 u2DelayCellOfst[13]=18 cells (5 PI)
8954 20:11:47.931414 u2DelayCellOfst[14]=18 cells (5 PI)
8955 20:11:47.931512 u2DelayCellOfst[15]=18 cells (5 PI)
8956 20:11:47.938633 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8957 20:11:47.942163 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8958 20:11:47.945010 DramC Write-DBI on
8959 20:11:47.945094 ==
8960 20:11:47.948375 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 20:11:47.951588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 20:11:47.951680 ==
8963 20:11:47.951749
8964 20:11:47.951814
8965 20:11:47.954904 TX Vref Scan disable
8966 20:11:47.954990 == TX Byte 0 ==
8967 20:11:47.961370 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8968 20:11:47.961461 == TX Byte 1 ==
8969 20:11:47.964661 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8970 20:11:47.967949 DramC Write-DBI off
8971 20:11:47.968032
8972 20:11:47.968097 [DATLAT]
8973 20:11:47.971362 Freq=1600, CH1 RK1
8974 20:11:47.971464
8975 20:11:47.971558 DATLAT Default: 0xf
8976 20:11:47.974546 0, 0xFFFF, sum = 0
8977 20:11:47.974645 1, 0xFFFF, sum = 0
8978 20:11:47.977647 2, 0xFFFF, sum = 0
8979 20:11:47.980897 3, 0xFFFF, sum = 0
8980 20:11:47.980969 4, 0xFFFF, sum = 0
8981 20:11:47.984665 5, 0xFFFF, sum = 0
8982 20:11:47.984765 6, 0xFFFF, sum = 0
8983 20:11:47.987802 7, 0xFFFF, sum = 0
8984 20:11:47.987915 8, 0xFFFF, sum = 0
8985 20:11:47.991096 9, 0xFFFF, sum = 0
8986 20:11:47.991197 10, 0xFFFF, sum = 0
8987 20:11:47.994536 11, 0xFFFF, sum = 0
8988 20:11:47.994650 12, 0xFFFF, sum = 0
8989 20:11:47.997526 13, 0xFFFF, sum = 0
8990 20:11:47.997614 14, 0x0, sum = 1
8991 20:11:48.001043 15, 0x0, sum = 2
8992 20:11:48.001131 16, 0x0, sum = 3
8993 20:11:48.004019 17, 0x0, sum = 4
8994 20:11:48.004107 best_step = 15
8995 20:11:48.004196
8996 20:11:48.004279 ==
8997 20:11:48.007592 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 20:11:48.014368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 20:11:48.014453 ==
9000 20:11:48.014520 RX Vref Scan: 0
9001 20:11:48.014583
9002 20:11:48.017345 RX Vref 0 -> 0, step: 1
9003 20:11:48.017429
9004 20:11:48.020648 RX Delay 11 -> 252, step: 4
9005 20:11:48.024128 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9006 20:11:48.027147 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9007 20:11:48.030729 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9008 20:11:48.036921 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9009 20:11:48.040176 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9010 20:11:48.043599 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9011 20:11:48.046900 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9012 20:11:48.050383 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9013 20:11:48.056776 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9014 20:11:48.060597 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9015 20:11:48.063289 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9016 20:11:48.067043 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9017 20:11:48.073587 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9018 20:11:48.076911 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9019 20:11:48.080413 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9020 20:11:48.083591 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9021 20:11:48.083720 ==
9022 20:11:48.086325 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 20:11:48.093006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 20:11:48.093124 ==
9025 20:11:48.093230 DQS Delay:
9026 20:11:48.096550 DQS0 = 0, DQS1 = 0
9027 20:11:48.096662 DQM Delay:
9028 20:11:48.096751 DQM0 = 134, DQM1 = 126
9029 20:11:48.099905 DQ Delay:
9030 20:11:48.102861 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9031 20:11:48.106265 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9032 20:11:48.109471 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9033 20:11:48.113133 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9034 20:11:48.113233
9035 20:11:48.113320
9036 20:11:48.113432
9037 20:11:48.116300 [DramC_TX_OE_Calibration] TA2
9038 20:11:48.119681 Original DQ_B0 (3 6) =30, OEN = 27
9039 20:11:48.122612 Original DQ_B1 (3 6) =30, OEN = 27
9040 20:11:48.126040 24, 0x0, End_B0=24 End_B1=24
9041 20:11:48.129071 25, 0x0, End_B0=25 End_B1=25
9042 20:11:48.129158 26, 0x0, End_B0=26 End_B1=26
9043 20:11:48.132331 27, 0x0, End_B0=27 End_B1=27
9044 20:11:48.136202 28, 0x0, End_B0=28 End_B1=28
9045 20:11:48.139163 29, 0x0, End_B0=29 End_B1=29
9046 20:11:48.139264 30, 0x0, End_B0=30 End_B1=30
9047 20:11:48.142697 31, 0x4141, End_B0=30 End_B1=30
9048 20:11:48.146120 Byte0 end_step=30 best_step=27
9049 20:11:48.149171 Byte1 end_step=30 best_step=27
9050 20:11:48.152705 Byte0 TX OE(2T, 0.5T) = (3, 3)
9051 20:11:48.155706 Byte1 TX OE(2T, 0.5T) = (3, 3)
9052 20:11:48.155806
9053 20:11:48.155892
9054 20:11:48.162119 [DQSOSCAuto] RK1, (LSB)MR18= 0xa07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9055 20:11:48.166093 CH1 RK1: MR19=303, MR18=A07
9056 20:11:48.172449 CH1_RK1: MR19=0x303, MR18=0xA07, DQSOSC=404, MR23=63, INC=22, DEC=15
9057 20:11:48.175814 [RxdqsGatingPostProcess] freq 1600
9058 20:11:48.178693 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9059 20:11:48.182098 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 20:11:48.185589 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 20:11:48.188390 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 20:11:48.191714 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 20:11:48.195089 best DQS0 dly(2T, 0.5T) = (1, 1)
9064 20:11:48.198927 best DQS1 dly(2T, 0.5T) = (1, 1)
9065 20:11:48.201944 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9066 20:11:48.205406 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9067 20:11:48.208348 Pre-setting of DQS Precalculation
9068 20:11:48.211854 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9069 20:11:48.222220 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9070 20:11:48.228150 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 20:11:48.228236
9072 20:11:48.228322
9073 20:11:48.231962 [Calibration Summary] 3200 Mbps
9074 20:11:48.232047 CH 0, Rank 0
9075 20:11:48.235011 SW Impedance : PASS
9076 20:11:48.235095 DUTY Scan : NO K
9077 20:11:48.237997 ZQ Calibration : PASS
9078 20:11:48.241476 Jitter Meter : NO K
9079 20:11:48.241560 CBT Training : PASS
9080 20:11:48.244827 Write leveling : PASS
9081 20:11:48.248287 RX DQS gating : PASS
9082 20:11:48.248372 RX DQ/DQS(RDDQC) : PASS
9083 20:11:48.251203 TX DQ/DQS : PASS
9084 20:11:48.255046 RX DATLAT : PASS
9085 20:11:48.255131 RX DQ/DQS(Engine): PASS
9086 20:11:48.257922 TX OE : PASS
9087 20:11:48.258039 All Pass.
9088 20:11:48.258126
9089 20:11:48.261896 CH 0, Rank 1
9090 20:11:48.261981 SW Impedance : PASS
9091 20:11:48.264574 DUTY Scan : NO K
9092 20:11:48.267862 ZQ Calibration : PASS
9093 20:11:48.267946 Jitter Meter : NO K
9094 20:11:48.271122 CBT Training : PASS
9095 20:11:48.274702 Write leveling : PASS
9096 20:11:48.274787 RX DQS gating : PASS
9097 20:11:48.278483 RX DQ/DQS(RDDQC) : PASS
9098 20:11:48.278568 TX DQ/DQS : PASS
9099 20:11:48.281381 RX DATLAT : PASS
9100 20:11:48.284277 RX DQ/DQS(Engine): PASS
9101 20:11:48.284400 TX OE : PASS
9102 20:11:48.287621 All Pass.
9103 20:11:48.287731
9104 20:11:48.287818 CH 1, Rank 0
9105 20:11:48.290787 SW Impedance : PASS
9106 20:11:48.290880 DUTY Scan : NO K
9107 20:11:48.294657 ZQ Calibration : PASS
9108 20:11:48.297524 Jitter Meter : NO K
9109 20:11:48.297609 CBT Training : PASS
9110 20:11:48.300592 Write leveling : PASS
9111 20:11:48.303871 RX DQS gating : PASS
9112 20:11:48.303956 RX DQ/DQS(RDDQC) : PASS
9113 20:11:48.307138 TX DQ/DQS : PASS
9114 20:11:48.310486 RX DATLAT : PASS
9115 20:11:48.310571 RX DQ/DQS(Engine): PASS
9116 20:11:48.313688 TX OE : PASS
9117 20:11:48.313773 All Pass.
9118 20:11:48.313858
9119 20:11:48.317100 CH 1, Rank 1
9120 20:11:48.317185 SW Impedance : PASS
9121 20:11:48.320482 DUTY Scan : NO K
9122 20:11:48.323654 ZQ Calibration : PASS
9123 20:11:48.323790 Jitter Meter : NO K
9124 20:11:48.327266 CBT Training : PASS
9125 20:11:48.330040 Write leveling : PASS
9126 20:11:48.330122 RX DQS gating : PASS
9127 20:11:48.333645 RX DQ/DQS(RDDQC) : PASS
9128 20:11:48.337224 TX DQ/DQS : PASS
9129 20:11:48.337306 RX DATLAT : PASS
9130 20:11:48.339953 RX DQ/DQS(Engine): PASS
9131 20:11:48.343322 TX OE : PASS
9132 20:11:48.343404 All Pass.
9133 20:11:48.343470
9134 20:11:48.346914 DramC Write-DBI on
9135 20:11:48.346997 PER_BANK_REFRESH: Hybrid Mode
9136 20:11:48.349819 TX_TRACKING: ON
9137 20:11:48.360102 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9138 20:11:48.366366 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9139 20:11:48.372659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9140 20:11:48.376033 [FAST_K] Save calibration result to emmc
9141 20:11:48.379463 sync common calibartion params.
9142 20:11:48.382882 sync cbt_mode0:1, 1:1
9143 20:11:48.382964 dram_init: ddr_geometry: 2
9144 20:11:48.386181 dram_init: ddr_geometry: 2
9145 20:11:48.389035 dram_init: ddr_geometry: 2
9146 20:11:48.392582 0:dram_rank_size:100000000
9147 20:11:48.392666 1:dram_rank_size:100000000
9148 20:11:48.398810 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9149 20:11:48.402728 DFS_SHUFFLE_HW_MODE: ON
9150 20:11:48.405572 dramc_set_vcore_voltage set vcore to 725000
9151 20:11:48.409374 Read voltage for 1600, 0
9152 20:11:48.409456 Vio18 = 0
9153 20:11:48.409521 Vcore = 725000
9154 20:11:48.412212 Vdram = 0
9155 20:11:48.412326 Vddq = 0
9156 20:11:48.412392 Vmddr = 0
9157 20:11:48.415929 switch to 3200 Mbps bootup
9158 20:11:48.416041 [DramcRunTimeConfig]
9159 20:11:48.418884 PHYPLL
9160 20:11:48.418965 DPM_CONTROL_AFTERK: ON
9161 20:11:48.422381 PER_BANK_REFRESH: ON
9162 20:11:48.425676 REFRESH_OVERHEAD_REDUCTION: ON
9163 20:11:48.425761 CMD_PICG_NEW_MODE: OFF
9164 20:11:48.428580 XRTWTW_NEW_MODE: ON
9165 20:11:48.428661 XRTRTR_NEW_MODE: ON
9166 20:11:48.432455 TX_TRACKING: ON
9167 20:11:48.432538 RDSEL_TRACKING: OFF
9168 20:11:48.435181 DQS Precalculation for DVFS: ON
9169 20:11:48.438983 RX_TRACKING: OFF
9170 20:11:48.439064 HW_GATING DBG: ON
9171 20:11:48.441838 ZQCS_ENABLE_LP4: ON
9172 20:11:48.441920 RX_PICG_NEW_MODE: ON
9173 20:11:48.445503 TX_PICG_NEW_MODE: ON
9174 20:11:48.448852 ENABLE_RX_DCM_DPHY: ON
9175 20:11:48.448934 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9176 20:11:48.451916 DUMMY_READ_FOR_TRACKING: OFF
9177 20:11:48.455191 !!! SPM_CONTROL_AFTERK: OFF
9178 20:11:48.458266 !!! SPM could not control APHY
9179 20:11:48.462010 IMPEDANCE_TRACKING: ON
9180 20:11:48.462092 TEMP_SENSOR: ON
9181 20:11:48.464791 HW_SAVE_FOR_SR: OFF
9182 20:11:48.464873 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9183 20:11:48.472143 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9184 20:11:48.472225 Read ODT Tracking: ON
9185 20:11:48.474857 Refresh Rate DeBounce: ON
9186 20:11:48.477988 DFS_NO_QUEUE_FLUSH: ON
9187 20:11:48.478206 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9188 20:11:48.481646 ENABLE_DFS_RUNTIME_MRW: OFF
9189 20:11:48.484578 DDR_RESERVE_NEW_MODE: ON
9190 20:11:48.487919 MR_CBT_SWITCH_FREQ: ON
9191 20:11:48.488025 =========================
9192 20:11:48.507522 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9193 20:11:48.510873 dram_init: ddr_geometry: 2
9194 20:11:48.528882 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9195 20:11:48.532600 dram_init: dram init end (result: 0)
9196 20:11:48.539184 DRAM-K: Full calibration passed in 24628 msecs
9197 20:11:48.542823 MRC: failed to locate region type 0.
9198 20:11:48.542925 DRAM rank0 size:0x100000000,
9199 20:11:48.545806 DRAM rank1 size=0x100000000
9200 20:11:48.555613 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9201 20:11:48.562057 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9202 20:11:48.568851 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9203 20:11:48.578273 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9204 20:11:48.578375 DRAM rank0 size:0x100000000,
9205 20:11:48.581680 DRAM rank1 size=0x100000000
9206 20:11:48.581750 CBMEM:
9207 20:11:48.584918 IMD: root @ 0xfffff000 254 entries.
9208 20:11:48.588220 IMD: root @ 0xffffec00 62 entries.
9209 20:11:48.591953 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9210 20:11:48.598679 WARNING: RO_VPD is uninitialized or empty.
9211 20:11:48.601431 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9212 20:11:48.609413 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9213 20:11:48.621989 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9214 20:11:48.633385 BS: romstage times (exec / console): total (unknown) / 24120 ms
9215 20:11:48.633497
9216 20:11:48.633590
9217 20:11:48.643377 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9218 20:11:48.646573 ARM64: Exception handlers installed.
9219 20:11:48.649762 ARM64: Testing exception
9220 20:11:48.652922 ARM64: Done test exception
9221 20:11:48.653004 Enumerating buses...
9222 20:11:48.656335 Show all devs... Before device enumeration.
9223 20:11:48.659612 Root Device: enabled 1
9224 20:11:48.662783 CPU_CLUSTER: 0: enabled 1
9225 20:11:48.662865 CPU: 00: enabled 1
9226 20:11:48.666370 Compare with tree...
9227 20:11:48.666451 Root Device: enabled 1
9228 20:11:48.669669 CPU_CLUSTER: 0: enabled 1
9229 20:11:48.673098 CPU: 00: enabled 1
9230 20:11:48.673179 Root Device scanning...
9231 20:11:48.676556 scan_static_bus for Root Device
9232 20:11:48.679808 CPU_CLUSTER: 0 enabled
9233 20:11:48.682567 scan_static_bus for Root Device done
9234 20:11:48.686316 scan_bus: bus Root Device finished in 8 msecs
9235 20:11:48.686430 done
9236 20:11:48.692859 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9237 20:11:48.695898 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9238 20:11:48.702428 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9239 20:11:48.705771 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9240 20:11:48.709027 Allocating resources...
9241 20:11:48.712710 Reading resources...
9242 20:11:48.715894 Root Device read_resources bus 0 link: 0
9243 20:11:48.719518 DRAM rank0 size:0x100000000,
9244 20:11:48.719601 DRAM rank1 size=0x100000000
9245 20:11:48.725331 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9246 20:11:48.725414 CPU: 00 missing read_resources
9247 20:11:48.732160 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9248 20:11:48.735631 Root Device read_resources bus 0 link: 0 done
9249 20:11:48.738749 Done reading resources.
9250 20:11:48.741960 Show resources in subtree (Root Device)...After reading.
9251 20:11:48.745247 Root Device child on link 0 CPU_CLUSTER: 0
9252 20:11:48.748439 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 20:11:48.758605 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 20:11:48.758688 CPU: 00
9255 20:11:48.764843 Root Device assign_resources, bus 0 link: 0
9256 20:11:48.768323 CPU_CLUSTER: 0 missing set_resources
9257 20:11:48.771960 Root Device assign_resources, bus 0 link: 0 done
9258 20:11:48.774579 Done setting resources.
9259 20:11:48.778141 Show resources in subtree (Root Device)...After assigning values.
9260 20:11:48.781430 Root Device child on link 0 CPU_CLUSTER: 0
9261 20:11:48.787851 CPU_CLUSTER: 0 child on link 0 CPU: 00
9262 20:11:48.794148 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9263 20:11:48.797897 CPU: 00
9264 20:11:48.797979 Done allocating resources.
9265 20:11:48.804397 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9266 20:11:48.807724 Enabling resources...
9267 20:11:48.807806 done.
9268 20:11:48.810647 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9269 20:11:48.814228 Initializing devices...
9270 20:11:48.814363 Root Device init
9271 20:11:48.817661 init hardware done!
9272 20:11:48.820577 0x00000018: ctrlr->caps
9273 20:11:48.820662 52.000 MHz: ctrlr->f_max
9274 20:11:48.823969 0.400 MHz: ctrlr->f_min
9275 20:11:48.827339 0x40ff8080: ctrlr->voltages
9276 20:11:48.827423 sclk: 390625
9277 20:11:48.827488 Bus Width = 1
9278 20:11:48.830906 sclk: 390625
9279 20:11:48.830987 Bus Width = 1
9280 20:11:48.833877 Early init status = 3
9281 20:11:48.837228 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9282 20:11:48.840778 in-header: 03 fc 00 00 01 00 00 00
9283 20:11:48.844105 in-data: 00
9284 20:11:48.847751 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9285 20:11:48.852281 in-header: 03 fd 00 00 00 00 00 00
9286 20:11:48.855300 in-data:
9287 20:11:48.858979 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9288 20:11:48.863077 in-header: 03 fc 00 00 01 00 00 00
9289 20:11:48.866367 in-data: 00
9290 20:11:48.869609 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9291 20:11:48.875266 in-header: 03 fd 00 00 00 00 00 00
9292 20:11:48.878729 in-data:
9293 20:11:48.881793 [SSUSB] Setting up USB HOST controller...
9294 20:11:48.885173 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9295 20:11:48.888364 [SSUSB] phy power-on done.
9296 20:11:48.891662 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9297 20:11:48.898338 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9298 20:11:48.901479 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9299 20:11:48.908627 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9300 20:11:48.914754 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9301 20:11:48.921782 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9302 20:11:48.927680 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9303 20:11:48.934822 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9304 20:11:48.937754 SPM: binary array size = 0x9dc
9305 20:11:48.941050 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9306 20:11:48.947677 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9307 20:11:48.954109 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9308 20:11:48.960608 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9309 20:11:48.964374 configure_display: Starting display init
9310 20:11:48.998571 anx7625_power_on_init: Init interface.
9311 20:11:49.002041 anx7625_disable_pd_protocol: Disabled PD feature.
9312 20:11:49.005037 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9313 20:11:49.033405 anx7625_start_dp_work: Secure OCM version=00
9314 20:11:49.035874 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9315 20:11:49.053838 sp_tx_get_edid_block: EDID Block = 1
9316 20:11:49.153978 Extracted contents:
9317 20:11:49.156825 header: 00 ff ff ff ff ff ff 00
9318 20:11:49.160005 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9319 20:11:49.163232 version: 01 04
9320 20:11:49.166447 basic params: 95 1f 11 78 0a
9321 20:11:49.170143 chroma info: 76 90 94 55 54 90 27 21 50 54
9322 20:11:49.173134 established: 00 00 00
9323 20:11:49.179736 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9324 20:11:49.182943 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9325 20:11:49.189681 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9326 20:11:49.196132 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9327 20:11:49.202811 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9328 20:11:49.206249 extensions: 00
9329 20:11:49.206346 checksum: fb
9330 20:11:49.206442
9331 20:11:49.212866 Manufacturer: IVO Model 57d Serial Number 0
9332 20:11:49.212949 Made week 0 of 2020
9333 20:11:49.216484 EDID version: 1.4
9334 20:11:49.216566 Digital display
9335 20:11:49.219170 6 bits per primary color channel
9336 20:11:49.222824 DisplayPort interface
9337 20:11:49.222905 Maximum image size: 31 cm x 17 cm
9338 20:11:49.226081 Gamma: 220%
9339 20:11:49.226163 Check DPMS levels
9340 20:11:49.232399 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9341 20:11:49.236079 First detailed timing is preferred timing
9342 20:11:49.238776 Established timings supported:
9343 20:11:49.238858 Standard timings supported:
9344 20:11:49.242573 Detailed timings
9345 20:11:49.245858 Hex of detail: 383680a07038204018303c0035ae10000019
9346 20:11:49.252022 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9347 20:11:49.255477 0780 0798 07c8 0820 hborder 0
9348 20:11:49.259218 0438 043b 0447 0458 vborder 0
9349 20:11:49.262497 -hsync -vsync
9350 20:11:49.262578 Did detailed timing
9351 20:11:49.268448 Hex of detail: 000000000000000000000000000000000000
9352 20:11:49.272068 Manufacturer-specified data, tag 0
9353 20:11:49.275277 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9354 20:11:49.278643 ASCII string: InfoVision
9355 20:11:49.281904 Hex of detail: 000000fe00523134304e574635205248200a
9356 20:11:49.284923 ASCII string: R140NWF5 RH
9357 20:11:49.285046 Checksum
9358 20:11:49.288637 Checksum: 0xfb (valid)
9359 20:11:49.291403 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9360 20:11:49.294951 DSI data_rate: 832800000 bps
9361 20:11:49.301709 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9362 20:11:49.304908 anx7625_parse_edid: pixelclock(138800).
9363 20:11:49.308760 hactive(1920), hsync(48), hfp(24), hbp(88)
9364 20:11:49.311599 vactive(1080), vsync(12), vfp(3), vbp(17)
9365 20:11:49.314448 anx7625_dsi_config: config dsi.
9366 20:11:49.321377 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9367 20:11:49.335818 anx7625_dsi_config: success to config DSI
9368 20:11:49.338905 anx7625_dp_start: MIPI phy setup OK.
9369 20:11:49.342364 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9370 20:11:49.345799 mtk_ddp_mode_set invalid vrefresh 60
9371 20:11:49.349115 main_disp_path_setup
9372 20:11:49.349197 ovl_layer_smi_id_en
9373 20:11:49.352383 ovl_layer_smi_id_en
9374 20:11:49.352466 ccorr_config
9375 20:11:49.352533 aal_config
9376 20:11:49.355313 gamma_config
9377 20:11:49.355396 postmask_config
9378 20:11:49.358914 dither_config
9379 20:11:49.362027 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9380 20:11:49.368491 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9381 20:11:49.372042 Root Device init finished in 553 msecs
9382 20:11:49.375229 CPU_CLUSTER: 0 init
9383 20:11:49.381961 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9384 20:11:49.388266 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9385 20:11:49.388350 APU_MBOX 0x190000b0 = 0x10001
9386 20:11:49.391768 APU_MBOX 0x190001b0 = 0x10001
9387 20:11:49.395289 APU_MBOX 0x190005b0 = 0x10001
9388 20:11:49.398104 APU_MBOX 0x190006b0 = 0x10001
9389 20:11:49.404870 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9390 20:11:49.414354 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9391 20:11:49.427178 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9392 20:11:49.433420 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9393 20:11:49.445097 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9394 20:11:49.454490 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9395 20:11:49.457627 CPU_CLUSTER: 0 init finished in 81 msecs
9396 20:11:49.461217 Devices initialized
9397 20:11:49.464488 Show all devs... After init.
9398 20:11:49.464570 Root Device: enabled 1
9399 20:11:49.467598 CPU_CLUSTER: 0: enabled 1
9400 20:11:49.470724 CPU: 00: enabled 1
9401 20:11:49.474285 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9402 20:11:49.478032 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9403 20:11:49.480657 ELOG: NV offset 0x57f000 size 0x1000
9404 20:11:49.487819 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9405 20:11:49.494387 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9406 20:11:49.497218 ELOG: Event(17) added with size 13 at 2024-03-03 20:11:49 UTC
9407 20:11:49.503824 out: cmd=0x121: 03 db 21 01 00 00 00 00
9408 20:11:49.507211 in-header: 03 a0 00 00 2c 00 00 00
9409 20:11:49.520276 in-data: bf 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9410 20:11:49.523341 ELOG: Event(A1) added with size 10 at 2024-03-03 20:11:49 UTC
9411 20:11:49.530470 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9412 20:11:49.536829 ELOG: Event(A0) added with size 9 at 2024-03-03 20:11:49 UTC
9413 20:11:49.539864 elog_add_boot_reason: Logged dev mode boot
9414 20:11:49.546784 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9415 20:11:49.546866 Finalize devices...
9416 20:11:49.549796 Devices finalized
9417 20:11:49.553529 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9418 20:11:49.556725 Writing coreboot table at 0xffe64000
9419 20:11:49.563087 0. 000000000010a000-0000000000113fff: RAMSTAGE
9420 20:11:49.566426 1. 0000000040000000-00000000400fffff: RAM
9421 20:11:49.569817 2. 0000000040100000-000000004032afff: RAMSTAGE
9422 20:11:49.573016 3. 000000004032b000-00000000545fffff: RAM
9423 20:11:49.576171 4. 0000000054600000-000000005465ffff: BL31
9424 20:11:49.582945 5. 0000000054660000-00000000ffe63fff: RAM
9425 20:11:49.586429 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9426 20:11:49.589631 7. 0000000100000000-000000023fffffff: RAM
9427 20:11:49.592748 Passing 5 GPIOs to payload:
9428 20:11:49.596889 NAME | PORT | POLARITY | VALUE
9429 20:11:49.602786 EC in RW | 0x000000aa | low | undefined
9430 20:11:49.605919 EC interrupt | 0x00000005 | low | undefined
9431 20:11:49.612376 TPM interrupt | 0x000000ab | high | undefined
9432 20:11:49.615928 SD card detect | 0x00000011 | high | undefined
9433 20:11:49.622482 speaker enable | 0x00000093 | high | undefined
9434 20:11:49.625404 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9435 20:11:49.628952 in-header: 03 f9 00 00 02 00 00 00
9436 20:11:49.629049 in-data: 02 00
9437 20:11:49.632388 ADC[4]: Raw value=904139 ID=7
9438 20:11:49.635945 ADC[3]: Raw value=213282 ID=1
9439 20:11:49.636043 RAM Code: 0x71
9440 20:11:49.638721 ADC[6]: Raw value=75036 ID=0
9441 20:11:49.642022 ADC[5]: Raw value=212543 ID=1
9442 20:11:49.642120 SKU Code: 0x1
9443 20:11:49.649387 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5d53
9444 20:11:49.652317 coreboot table: 964 bytes.
9445 20:11:49.655788 IMD ROOT 0. 0xfffff000 0x00001000
9446 20:11:49.658939 IMD SMALL 1. 0xffffe000 0x00001000
9447 20:11:49.661772 RO MCACHE 2. 0xffffc000 0x00001104
9448 20:11:49.665596 CONSOLE 3. 0xfff7c000 0x00080000
9449 20:11:49.668810 FMAP 4. 0xfff7b000 0x00000452
9450 20:11:49.671860 TIME STAMP 5. 0xfff7a000 0x00000910
9451 20:11:49.675077 VBOOT WORK 6. 0xfff66000 0x00014000
9452 20:11:49.678377 RAMOOPS 7. 0xffe66000 0x00100000
9453 20:11:49.682335 COREBOOT 8. 0xffe64000 0x00002000
9454 20:11:49.682433 IMD small region:
9455 20:11:49.684951 IMD ROOT 0. 0xffffec00 0x00000400
9456 20:11:49.688317 VPD 1. 0xffffeb80 0x0000006c
9457 20:11:49.691621 MMC STATUS 2. 0xffffeb60 0x00000004
9458 20:11:49.698569 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9459 20:11:49.698651 Probing TPM: done!
9460 20:11:49.705024 Connected to device vid:did:rid of 1ae0:0028:00
9461 20:11:49.712020 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9462 20:11:49.719273 Initialized TPM device CR50 revision 0
9463 20:11:49.719371 Checking cr50 for pending updates
9464 20:11:49.724968 Reading cr50 TPM mode
9465 20:11:49.733431 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9466 20:11:49.739944 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9467 20:11:49.779839 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9468 20:11:49.783061 Checking segment from ROM address 0x40100000
9469 20:11:49.789417 Checking segment from ROM address 0x4010001c
9470 20:11:49.793170 Loading segment from ROM address 0x40100000
9471 20:11:49.793280 code (compression=0)
9472 20:11:49.802810 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9473 20:11:49.809735 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9474 20:11:49.809833 it's not compressed!
9475 20:11:49.815983 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9476 20:11:49.822691 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9477 20:11:49.840409 Loading segment from ROM address 0x4010001c
9478 20:11:49.840492 Entry Point 0x80000000
9479 20:11:49.843874 Loaded segments
9480 20:11:49.847025 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9481 20:11:49.853725 Jumping to boot code at 0x80000000(0xffe64000)
9482 20:11:49.860194 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9483 20:11:49.866536 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9484 20:11:49.874856 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9485 20:11:49.877891 Checking segment from ROM address 0x40100000
9486 20:11:49.881685 Checking segment from ROM address 0x4010001c
9487 20:11:49.887944 Loading segment from ROM address 0x40100000
9488 20:11:49.888026 code (compression=1)
9489 20:11:49.894805 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9490 20:11:49.904305 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9491 20:11:49.904387 using LZMA
9492 20:11:49.913036 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9493 20:11:49.919534 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9494 20:11:49.923275 Loading segment from ROM address 0x4010001c
9495 20:11:49.923400 Entry Point 0x54601000
9496 20:11:49.926987 Loaded segments
9497 20:11:49.929537 NOTICE: MT8192 bl31_setup
9498 20:11:49.937061 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9499 20:11:49.940070 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9500 20:11:49.943521 WARNING: region 0:
9501 20:11:49.946594 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 20:11:49.946676 WARNING: region 1:
9503 20:11:49.953518 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9504 20:11:49.956503 WARNING: region 2:
9505 20:11:49.960179 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9506 20:11:49.963133 WARNING: region 3:
9507 20:11:49.966763 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 20:11:49.969796 WARNING: region 4:
9509 20:11:49.976180 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 20:11:49.976262 WARNING: region 5:
9511 20:11:49.979971 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 20:11:49.983301 WARNING: region 6:
9513 20:11:49.986389 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 20:11:49.989777 WARNING: region 7:
9515 20:11:49.992772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 20:11:49.999475 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9517 20:11:50.002653 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9518 20:11:50.009466 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9519 20:11:50.012518 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9520 20:11:50.016082 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9521 20:11:50.022921 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9522 20:11:50.025710 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9523 20:11:50.029555 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9524 20:11:50.036510 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9525 20:11:50.039184 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9526 20:11:50.045563 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9527 20:11:50.049006 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9528 20:11:50.052867 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9529 20:11:50.059076 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9530 20:11:50.062624 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9531 20:11:50.066203 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9532 20:11:50.072431 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9533 20:11:50.075893 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9534 20:11:50.082798 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9535 20:11:50.085644 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9536 20:11:50.089030 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9537 20:11:50.095341 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9538 20:11:50.099158 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9539 20:11:50.105694 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9540 20:11:50.108606 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9541 20:11:50.112730 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9542 20:11:50.118727 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9543 20:11:50.122109 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9544 20:11:50.128535 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9545 20:11:50.131991 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9546 20:11:50.135386 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9547 20:11:50.141549 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9548 20:11:50.145317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9549 20:11:50.148229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9550 20:11:50.151890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9551 20:11:50.158715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9552 20:11:50.162100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9553 20:11:50.165533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9554 20:11:50.168326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9555 20:11:50.175121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9556 20:11:50.178691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9557 20:11:50.181575 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9558 20:11:50.188439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9559 20:11:50.191325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9560 20:11:50.195245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9561 20:11:50.198039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9562 20:11:50.204719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9563 20:11:50.207817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9564 20:11:50.211599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9565 20:11:50.218045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9566 20:11:50.221019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9567 20:11:50.227967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9568 20:11:50.231070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9569 20:11:50.234769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9570 20:11:50.241369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9571 20:11:50.244371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9572 20:11:50.251366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9573 20:11:50.254296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9574 20:11:50.260764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9575 20:11:50.264203 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9576 20:11:50.271648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9577 20:11:50.274703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9578 20:11:50.277873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9579 20:11:50.284327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9580 20:11:50.287614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9581 20:11:50.294290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9582 20:11:50.297671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9583 20:11:50.303994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9584 20:11:50.307807 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9585 20:11:50.313966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9586 20:11:50.317531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9587 20:11:50.320838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9588 20:11:50.327170 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9589 20:11:50.330753 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9590 20:11:50.337371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9591 20:11:50.341129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9592 20:11:50.347231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9593 20:11:50.350578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9594 20:11:50.354034 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9595 20:11:50.361113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9596 20:11:50.363928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9597 20:11:50.370739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9598 20:11:50.373920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9599 20:11:50.380428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9600 20:11:50.383422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9601 20:11:50.390298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9602 20:11:50.393462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9603 20:11:50.396959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9604 20:11:50.403275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9605 20:11:50.406565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9606 20:11:50.413999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9607 20:11:50.416959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9608 20:11:50.423278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9609 20:11:50.427177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9610 20:11:50.433145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9611 20:11:50.436979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9612 20:11:50.439782 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9613 20:11:50.446519 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9614 20:11:50.449562 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9615 20:11:50.453238 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9616 20:11:50.456930 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9617 20:11:50.463125 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9618 20:11:50.466563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9619 20:11:50.473065 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9620 20:11:50.476893 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9621 20:11:50.479536 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9622 20:11:50.486160 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9623 20:11:50.489439 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9624 20:11:50.496460 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9625 20:11:50.499816 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9626 20:11:50.502706 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9627 20:11:50.509583 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9628 20:11:50.512941 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9629 20:11:50.519087 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9630 20:11:50.522621 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9631 20:11:50.525652 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9632 20:11:50.532274 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9633 20:11:50.535565 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9634 20:11:50.539233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9635 20:11:50.545840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9636 20:11:50.549725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9637 20:11:50.552358 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9638 20:11:50.555537 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9639 20:11:50.562167 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9640 20:11:50.565182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9641 20:11:50.568895 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9642 20:11:50.575531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9643 20:11:50.578824 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9644 20:11:50.585416 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9645 20:11:50.588269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9646 20:11:50.591770 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9647 20:11:50.598457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9648 20:11:50.601703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9649 20:11:50.608112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9650 20:11:50.611720 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9651 20:11:50.614711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9652 20:11:50.621534 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9653 20:11:50.624976 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9654 20:11:50.631691 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9655 20:11:50.634985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9656 20:11:50.638405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9657 20:11:50.644775 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9658 20:11:50.648056 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9659 20:11:50.654714 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9660 20:11:50.658202 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9661 20:11:50.661385 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9662 20:11:50.667971 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9663 20:11:50.671518 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9664 20:11:50.677672 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9665 20:11:50.681408 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9666 20:11:50.684910 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9667 20:11:50.691224 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9668 20:11:50.694615 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9669 20:11:50.697795 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9670 20:11:50.704166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9671 20:11:50.707485 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9672 20:11:50.714646 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9673 20:11:50.717843 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9674 20:11:50.720876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9675 20:11:50.727789 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9676 20:11:50.730729 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9677 20:11:50.737214 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9678 20:11:50.740607 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9679 20:11:50.747800 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9680 20:11:50.750993 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9681 20:11:50.754104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9682 20:11:50.760232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9683 20:11:50.763777 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9684 20:11:50.770496 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9685 20:11:50.773699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9686 20:11:50.777046 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9687 20:11:50.783112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9688 20:11:50.786682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9689 20:11:50.793022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9690 20:11:50.796357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9691 20:11:50.799796 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9692 20:11:50.806594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9693 20:11:50.810064 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9694 20:11:50.816140 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9695 20:11:50.819585 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9696 20:11:50.823181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9697 20:11:50.829466 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9698 20:11:50.833030 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9699 20:11:50.839538 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9700 20:11:50.842772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9701 20:11:50.845937 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9702 20:11:50.852610 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9703 20:11:50.855696 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9704 20:11:50.862287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9705 20:11:50.865566 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9706 20:11:50.869041 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9707 20:11:50.875614 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9708 20:11:50.878878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9709 20:11:50.885929 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9710 20:11:50.889393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9711 20:11:50.895801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9712 20:11:50.898842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9713 20:11:50.902109 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9714 20:11:50.908457 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9715 20:11:50.912121 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9716 20:11:50.918391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9717 20:11:50.921607 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9718 20:11:50.928408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9719 20:11:50.931968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9720 20:11:50.934885 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9721 20:11:50.941557 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9722 20:11:50.944554 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9723 20:11:50.951423 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9724 20:11:50.954996 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9725 20:11:50.962276 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9726 20:11:50.964545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9727 20:11:50.968043 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9728 20:11:50.974370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9729 20:11:50.977671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9730 20:11:50.984117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9731 20:11:50.987611 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9732 20:11:50.994303 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9733 20:11:50.997455 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9734 20:11:51.000715 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9735 20:11:51.007792 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9736 20:11:51.010995 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9737 20:11:51.016856 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9738 20:11:51.020303 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9739 20:11:51.027154 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9740 20:11:51.030816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9741 20:11:51.036746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9742 20:11:51.039961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9743 20:11:51.043510 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9744 20:11:51.049759 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9745 20:11:51.053107 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9746 20:11:51.056242 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9747 20:11:51.059562 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9748 20:11:51.066697 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9749 20:11:51.069789 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9750 20:11:51.073218 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9751 20:11:51.079654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9752 20:11:51.082969 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9753 20:11:51.089550 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9754 20:11:51.092786 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9755 20:11:51.095919 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9756 20:11:51.102316 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9757 20:11:51.105654 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9758 20:11:51.109132 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9759 20:11:51.115547 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9760 20:11:51.119073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9761 20:11:51.122848 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9762 20:11:51.128888 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9763 20:11:51.132597 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9764 20:11:51.139189 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9765 20:11:51.142423 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9766 20:11:51.145641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9767 20:11:51.152286 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9768 20:11:51.155334 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9769 20:11:51.158949 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9770 20:11:51.165343 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9771 20:11:51.168486 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9772 20:11:51.175248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9773 20:11:51.178386 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9774 20:11:51.182023 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9775 20:11:51.188166 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9776 20:11:51.191632 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9777 20:11:51.198083 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9778 20:11:51.201644 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9779 20:11:51.205248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9780 20:11:51.211215 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9781 20:11:51.214783 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9782 20:11:51.217894 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9783 20:11:51.224501 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9784 20:11:51.227885 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9785 20:11:51.231315 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9786 20:11:51.234461 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9787 20:11:51.241298 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9788 20:11:51.244255 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9789 20:11:51.247943 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9790 20:11:51.250727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9791 20:11:51.258020 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9792 20:11:51.261042 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9793 20:11:51.264158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9794 20:11:51.267661 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9795 20:11:51.273805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9796 20:11:51.277540 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9797 20:11:51.281032 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9798 20:11:51.287100 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9799 20:11:51.290758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9800 20:11:51.296991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9801 20:11:51.300403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9802 20:11:51.307614 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9803 20:11:51.310512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9804 20:11:51.313750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9805 20:11:51.320159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9806 20:11:51.323706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9807 20:11:51.330517 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9808 20:11:51.333091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9809 20:11:51.336763 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9810 20:11:51.343271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9811 20:11:51.346705 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9812 20:11:51.353348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9813 20:11:51.356777 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9814 20:11:51.359527 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9815 20:11:51.366425 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9816 20:11:51.369533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9817 20:11:51.375941 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9818 20:11:51.379976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9819 20:11:51.386147 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9820 20:11:51.389298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9821 20:11:51.392595 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9822 20:11:51.399783 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9823 20:11:51.402902 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9824 20:11:51.409200 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9825 20:11:51.412605 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9826 20:11:51.419202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9827 20:11:51.422663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9828 20:11:51.425963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9829 20:11:51.432071 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9830 20:11:51.435410 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9831 20:11:51.442026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9832 20:11:51.445254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9833 20:11:51.451664 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9834 20:11:51.455096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9835 20:11:51.458462 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9836 20:11:51.465372 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9837 20:11:51.468455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9838 20:11:51.474808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9839 20:11:51.478308 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9840 20:11:51.481678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9841 20:11:51.487909 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9842 20:11:51.491593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9843 20:11:51.498271 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9844 20:11:51.501506 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9845 20:11:51.504706 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9846 20:11:51.511095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9847 20:11:51.514738 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9848 20:11:51.521213 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9849 20:11:51.524868 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9850 20:11:51.530823 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9851 20:11:51.534289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9852 20:11:51.540965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9853 20:11:51.543881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9854 20:11:51.547326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9855 20:11:51.553875 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9856 20:11:51.557277 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9857 20:11:51.563959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9858 20:11:51.567149 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9859 20:11:51.570822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9860 20:11:51.577028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9861 20:11:51.580610 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9862 20:11:51.586767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9863 20:11:51.590240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9864 20:11:51.596556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9865 20:11:51.599981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9866 20:11:51.603058 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9867 20:11:51.609617 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9868 20:11:51.613478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9869 20:11:51.619512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9870 20:11:51.623722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9871 20:11:51.629376 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9872 20:11:51.633075 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9873 20:11:51.636139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9874 20:11:51.642772 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9875 20:11:51.646359 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9876 20:11:51.652790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9877 20:11:51.656184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9878 20:11:51.662978 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9879 20:11:51.665916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9880 20:11:51.669043 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9881 20:11:51.676174 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9882 20:11:51.679437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9883 20:11:51.685814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9884 20:11:51.689332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9885 20:11:51.695740 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9886 20:11:51.698939 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9887 20:11:51.705328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9888 20:11:51.709205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9889 20:11:51.715559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9890 20:11:51.718580 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9891 20:11:51.722308 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9892 20:11:51.728901 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9893 20:11:51.732195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9894 20:11:51.738545 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9895 20:11:51.742074 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9896 20:11:51.748317 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9897 20:11:51.752000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9898 20:11:51.758318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9899 20:11:51.761242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9900 20:11:51.764501 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9901 20:11:51.771555 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9902 20:11:51.774793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9903 20:11:51.781542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9904 20:11:51.784726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9905 20:11:51.791476 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9906 20:11:51.794499 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9907 20:11:51.801047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9908 20:11:51.804568 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9909 20:11:51.807806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9910 20:11:51.814429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9911 20:11:51.817636 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9912 20:11:51.824125 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9913 20:11:51.827641 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9914 20:11:51.833662 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9915 20:11:51.837412 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9916 20:11:51.843955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9917 20:11:51.846966 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9918 20:11:51.850278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9919 20:11:51.856928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9920 20:11:51.860140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9921 20:11:51.867005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9922 20:11:51.870433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9923 20:11:51.876696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9924 20:11:51.880611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9925 20:11:51.886730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9926 20:11:51.890048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9927 20:11:51.896391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9928 20:11:51.899951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9929 20:11:51.906539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9930 20:11:51.909612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9931 20:11:51.916101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9932 20:11:51.920077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9933 20:11:51.926244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9934 20:11:51.929287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9935 20:11:51.936274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9936 20:11:51.939400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9937 20:11:51.945901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9938 20:11:51.949289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9939 20:11:51.956192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9940 20:11:51.959062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9941 20:11:51.965847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9942 20:11:51.968878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9943 20:11:51.975591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9944 20:11:51.978762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9945 20:11:51.985949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9946 20:11:51.988655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9947 20:11:51.995508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9948 20:11:51.998499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9949 20:11:52.005248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9950 20:11:52.008212 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9951 20:11:52.011797 INFO: [APUAPC] vio 0
9952 20:11:52.015165 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9953 20:11:52.021577 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9954 20:11:52.024973 INFO: [APUAPC] D0_APC_0: 0x400510
9955 20:11:52.025055 INFO: [APUAPC] D0_APC_1: 0x0
9956 20:11:52.028849 INFO: [APUAPC] D0_APC_2: 0x1540
9957 20:11:52.031588 INFO: [APUAPC] D0_APC_3: 0x0
9958 20:11:52.034700 INFO: [APUAPC] D1_APC_0: 0xffffffff
9959 20:11:52.037988 INFO: [APUAPC] D1_APC_1: 0xffffffff
9960 20:11:52.041317 INFO: [APUAPC] D1_APC_2: 0x3fffff
9961 20:11:52.044847 INFO: [APUAPC] D1_APC_3: 0x0
9962 20:11:52.047866 INFO: [APUAPC] D2_APC_0: 0xffffffff
9963 20:11:52.051225 INFO: [APUAPC] D2_APC_1: 0xffffffff
9964 20:11:52.054706 INFO: [APUAPC] D2_APC_2: 0x3fffff
9965 20:11:52.057861 INFO: [APUAPC] D2_APC_3: 0x0
9966 20:11:52.061008 INFO: [APUAPC] D3_APC_0: 0xffffffff
9967 20:11:52.064324 INFO: [APUAPC] D3_APC_1: 0xffffffff
9968 20:11:52.067544 INFO: [APUAPC] D3_APC_2: 0x3fffff
9969 20:11:52.071326 INFO: [APUAPC] D3_APC_3: 0x0
9970 20:11:52.074555 INFO: [APUAPC] D4_APC_0: 0xffffffff
9971 20:11:52.077699 INFO: [APUAPC] D4_APC_1: 0xffffffff
9972 20:11:52.081229 INFO: [APUAPC] D4_APC_2: 0x3fffff
9973 20:11:52.084387 INFO: [APUAPC] D4_APC_3: 0x0
9974 20:11:52.087502 INFO: [APUAPC] D5_APC_0: 0xffffffff
9975 20:11:52.090676 INFO: [APUAPC] D5_APC_1: 0xffffffff
9976 20:11:52.094831 INFO: [APUAPC] D5_APC_2: 0x3fffff
9977 20:11:52.097160 INFO: [APUAPC] D5_APC_3: 0x0
9978 20:11:52.100547 INFO: [APUAPC] D6_APC_0: 0xffffffff
9979 20:11:52.104044 INFO: [APUAPC] D6_APC_1: 0xffffffff
9980 20:11:52.107045 INFO: [APUAPC] D6_APC_2: 0x3fffff
9981 20:11:52.110880 INFO: [APUAPC] D6_APC_3: 0x0
9982 20:11:52.113954 INFO: [APUAPC] D7_APC_0: 0xffffffff
9983 20:11:52.116907 INFO: [APUAPC] D7_APC_1: 0xffffffff
9984 20:11:52.120809 INFO: [APUAPC] D7_APC_2: 0x3fffff
9985 20:11:52.123591 INFO: [APUAPC] D7_APC_3: 0x0
9986 20:11:52.126917 INFO: [APUAPC] D8_APC_0: 0xffffffff
9987 20:11:52.130530 INFO: [APUAPC] D8_APC_1: 0xffffffff
9988 20:11:52.133370 INFO: [APUAPC] D8_APC_2: 0x3fffff
9989 20:11:52.137402 INFO: [APUAPC] D8_APC_3: 0x0
9990 20:11:52.139982 INFO: [APUAPC] D9_APC_0: 0xffffffff
9991 20:11:52.143925 INFO: [APUAPC] D9_APC_1: 0xffffffff
9992 20:11:52.146748 INFO: [APUAPC] D9_APC_2: 0x3fffff
9993 20:11:52.150578 INFO: [APUAPC] D9_APC_3: 0x0
9994 20:11:52.153285 INFO: [APUAPC] D10_APC_0: 0xffffffff
9995 20:11:52.156777 INFO: [APUAPC] D10_APC_1: 0xffffffff
9996 20:11:52.159926 INFO: [APUAPC] D10_APC_2: 0x3fffff
9997 20:11:52.163279 INFO: [APUAPC] D10_APC_3: 0x0
9998 20:11:52.166847 INFO: [APUAPC] D11_APC_0: 0xffffffff
9999 20:11:52.169793 INFO: [APUAPC] D11_APC_1: 0xffffffff
10000 20:11:52.173200 INFO: [APUAPC] D11_APC_2: 0x3fffff
10001 20:11:52.176606 INFO: [APUAPC] D11_APC_3: 0x0
10002 20:11:52.180109 INFO: [APUAPC] D12_APC_0: 0xffffffff
10003 20:11:52.182944 INFO: [APUAPC] D12_APC_1: 0xffffffff
10004 20:11:52.186299 INFO: [APUAPC] D12_APC_2: 0x3fffff
10005 20:11:52.189765 INFO: [APUAPC] D12_APC_3: 0x0
10006 20:11:52.192912 INFO: [APUAPC] D13_APC_0: 0xffffffff
10007 20:11:52.196279 INFO: [APUAPC] D13_APC_1: 0xffffffff
10008 20:11:52.199389 INFO: [APUAPC] D13_APC_2: 0x3fffff
10009 20:11:52.203106 INFO: [APUAPC] D13_APC_3: 0x0
10010 20:11:52.206341 INFO: [APUAPC] D14_APC_0: 0xffffffff
10011 20:11:52.209589 INFO: [APUAPC] D14_APC_1: 0xffffffff
10012 20:11:52.212950 INFO: [APUAPC] D14_APC_2: 0x3fffff
10013 20:11:52.216008 INFO: [APUAPC] D14_APC_3: 0x0
10014 20:11:52.219438 INFO: [APUAPC] D15_APC_0: 0xffffffff
10015 20:11:52.222530 INFO: [APUAPC] D15_APC_1: 0xffffffff
10016 20:11:52.226548 INFO: [APUAPC] D15_APC_2: 0x3fffff
10017 20:11:52.229634 INFO: [APUAPC] D15_APC_3: 0x0
10018 20:11:52.232613 INFO: [APUAPC] APC_CON: 0x4
10019 20:11:52.235747 INFO: [NOCDAPC] D0_APC_0: 0x0
10020 20:11:52.239311 INFO: [NOCDAPC] D0_APC_1: 0x0
10021 20:11:52.242323 INFO: [NOCDAPC] D1_APC_0: 0x0
10022 20:11:52.245922 INFO: [NOCDAPC] D1_APC_1: 0xfff
10023 20:11:52.245996 INFO: [NOCDAPC] D2_APC_0: 0x0
10024 20:11:52.248751 INFO: [NOCDAPC] D2_APC_1: 0xfff
10025 20:11:52.252868 INFO: [NOCDAPC] D3_APC_0: 0x0
10026 20:11:52.255615 INFO: [NOCDAPC] D3_APC_1: 0xfff
10027 20:11:52.259162 INFO: [NOCDAPC] D4_APC_0: 0x0
10028 20:11:52.262529 INFO: [NOCDAPC] D4_APC_1: 0xfff
10029 20:11:52.265722 INFO: [NOCDAPC] D5_APC_0: 0x0
10030 20:11:52.268916 INFO: [NOCDAPC] D5_APC_1: 0xfff
10031 20:11:52.271999 INFO: [NOCDAPC] D6_APC_0: 0x0
10032 20:11:52.275448 INFO: [NOCDAPC] D6_APC_1: 0xfff
10033 20:11:52.278856 INFO: [NOCDAPC] D7_APC_0: 0x0
10034 20:11:52.282111 INFO: [NOCDAPC] D7_APC_1: 0xfff
10035 20:11:52.282203 INFO: [NOCDAPC] D8_APC_0: 0x0
10036 20:11:52.285348 INFO: [NOCDAPC] D8_APC_1: 0xfff
10037 20:11:52.289188 INFO: [NOCDAPC] D9_APC_0: 0x0
10038 20:11:52.292131 INFO: [NOCDAPC] D9_APC_1: 0xfff
10039 20:11:52.295916 INFO: [NOCDAPC] D10_APC_0: 0x0
10040 20:11:52.298733 INFO: [NOCDAPC] D10_APC_1: 0xfff
10041 20:11:52.302301 INFO: [NOCDAPC] D11_APC_0: 0x0
10042 20:11:52.305335 INFO: [NOCDAPC] D11_APC_1: 0xfff
10043 20:11:52.308431 INFO: [NOCDAPC] D12_APC_0: 0x0
10044 20:11:52.311927 INFO: [NOCDAPC] D12_APC_1: 0xfff
10045 20:11:52.315071 INFO: [NOCDAPC] D13_APC_0: 0x0
10046 20:11:52.318353 INFO: [NOCDAPC] D13_APC_1: 0xfff
10047 20:11:52.321918 INFO: [NOCDAPC] D14_APC_0: 0x0
10048 20:11:52.324969 INFO: [NOCDAPC] D14_APC_1: 0xfff
10049 20:11:52.325043 INFO: [NOCDAPC] D15_APC_0: 0x0
10050 20:11:52.327949 INFO: [NOCDAPC] D15_APC_1: 0xfff
10051 20:11:52.331419 INFO: [NOCDAPC] APC_CON: 0x4
10052 20:11:52.335568 INFO: [APUAPC] set_apusys_apc done
10053 20:11:52.338393 INFO: [DEVAPC] devapc_init done
10054 20:11:52.344774 INFO: GICv3 without legacy support detected.
10055 20:11:52.348009 INFO: ARM GICv3 driver initialized in EL3
10056 20:11:52.351548 INFO: Maximum SPI INTID supported: 639
10057 20:11:52.354709 INFO: BL31: Initializing runtime services
10058 20:11:52.361059 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10059 20:11:52.364427 INFO: SPM: enable CPC mode
10060 20:11:52.367949 INFO: mcdi ready for mcusys-off-idle and system suspend
10061 20:11:52.374765 INFO: BL31: Preparing for EL3 exit to normal world
10062 20:11:52.377731 INFO: Entry point address = 0x80000000
10063 20:11:52.377801 INFO: SPSR = 0x8
10064 20:11:52.384520
10065 20:11:52.384591
10066 20:11:52.384652
10067 20:11:52.388053 Starting depthcharge on Spherion...
10068 20:11:52.388153
10069 20:11:52.388242 Wipe memory regions:
10070 20:11:52.388335
10071 20:11:52.389204 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10072 20:11:52.389333 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10073 20:11:52.389423 Setting prompt string to ['asurada:']
10074 20:11:52.389505 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10075 20:11:52.391248 [0x00000040000000, 0x00000054600000)
10076 20:11:52.513263
10077 20:11:52.516872 [0x00000054660000, 0x00000080000000)
10078 20:11:52.773943
10079 20:11:52.774084 [0x000000821a7280, 0x000000ffe64000)
10080 20:11:53.518795
10081 20:11:53.518934 [0x00000100000000, 0x00000240000000)
10082 20:11:55.408039
10083 20:11:55.411243 Initializing XHCI USB controller at 0x11200000.
10084 20:11:56.449362
10085 20:11:56.452716 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10086 20:11:56.452827
10087 20:11:56.452900
10088 20:11:56.452959
10089 20:11:56.453245 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 20:11:56.553535 asurada: tftpboot 192.168.201.1 12928116/tftp-deploy-6ddh4bb_/kernel/image.itb 12928116/tftp-deploy-6ddh4bb_/kernel/cmdline
10092 20:11:56.553678 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 20:11:56.553763 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10094 20:11:56.557974 tftpboot 192.168.201.1 12928116/tftp-deploy-6ddh4bb_/kernel/image.itp-deploy-6ddh4bb_/kernel/cmdline
10095 20:11:56.558095
10096 20:11:56.558224 Waiting for link
10097 20:11:56.718235
10098 20:11:56.718351 R8152: Initializing
10099 20:11:56.718422
10100 20:11:56.721592 Version 6 (ocp_data = 5c30)
10101 20:11:56.721668
10102 20:11:56.724925 R8152: Done initializing
10103 20:11:56.725000
10104 20:11:56.725064 Adding net device
10105 20:11:58.581045
10106 20:11:58.581181 done.
10107 20:11:58.581249
10108 20:11:58.581321 MAC: 00:e0:4c:68:02:81
10109 20:11:58.581381
10110 20:11:58.584763 Sending DHCP discover... done.
10111 20:11:58.584834
10112 20:12:08.484756 Waiting for reply... R8152: Bulk read error 0xffffffbf
10113 20:12:08.484894
10114 20:12:08.488105 Receive failed.
10115 20:12:08.488190
10116 20:12:08.488277 done.
10117 20:12:08.488366
10118 20:12:08.491936 Sending DHCP request... done.
10119 20:12:08.492042
10120 20:12:08.494798 Waiting for reply... done.
10121 20:12:08.494885
10122 20:12:08.494949 My ip is 192.168.201.14
10123 20:12:08.495008
10124 20:12:08.498362 The DHCP server ip is 192.168.201.1
10125 20:12:08.498496
10126 20:12:08.504507 TFTP server IP predefined by user: 192.168.201.1
10127 20:12:08.504620
10128 20:12:08.511325 Bootfile predefined by user: 12928116/tftp-deploy-6ddh4bb_/kernel/image.itb
10129 20:12:08.511434
10130 20:12:08.514953 Sending tftp read request... done.
10131 20:12:08.515054
10132 20:12:08.518840 Waiting for the transfer...
10133 20:12:08.518925
10134 20:12:09.051817 00000000 ################################################################
10135 20:12:09.051972
10136 20:12:09.594878 00080000 ################################################################
10137 20:12:09.595031
10138 20:12:10.127827 00100000 ################################################################
10139 20:12:10.127965
10140 20:12:10.668041 00180000 ################################################################
10141 20:12:10.668196
10142 20:12:11.194156 00200000 ################################################################
10143 20:12:11.194317
10144 20:12:11.738203 00280000 ################################################################
10145 20:12:11.738336
10146 20:12:12.313558 00300000 ################################################################
10147 20:12:12.313703
10148 20:12:12.876375 00380000 ################################################################
10149 20:12:12.876527
10150 20:12:13.423269 00400000 ################################################################
10151 20:12:13.423419
10152 20:12:14.025410 00480000 ################################################################
10153 20:12:14.025541
10154 20:12:14.587983 00500000 ################################################################
10155 20:12:14.588117
10156 20:12:15.142375 00580000 ################################################################
10157 20:12:15.142515
10158 20:12:15.693880 00600000 ################################################################
10159 20:12:15.694037
10160 20:12:16.263348 00680000 ################################################################
10161 20:12:16.263485
10162 20:12:16.851035 00700000 ################################################################
10163 20:12:16.851175
10164 20:12:17.441941 00780000 ################################################################
10165 20:12:17.442081
10166 20:12:18.011542 00800000 ################################################################
10167 20:12:18.011727
10168 20:12:18.616436 00880000 ################################################################
10169 20:12:18.616579
10170 20:12:19.209259 00900000 ################################################################
10171 20:12:19.209393
10172 20:12:19.829259 00980000 ################################################################
10173 20:12:19.829394
10174 20:12:20.460851 00a00000 ################################################################
10175 20:12:20.460990
10176 20:12:21.100251 00a80000 ################################################################
10177 20:12:21.100390
10178 20:12:21.725247 00b00000 ################################################################
10179 20:12:21.725389
10180 20:12:22.353512 00b80000 ################################################################
10181 20:12:22.353648
10182 20:12:22.973292 00c00000 ################################################################
10183 20:12:22.973432
10184 20:12:23.604172 00c80000 ################################################################
10185 20:12:23.604313
10186 20:12:24.222687 00d00000 ################################################################
10187 20:12:24.222834
10188 20:12:24.853827 00d80000 ################################################################
10189 20:12:24.853971
10190 20:12:25.482125 00e00000 ################################################################
10191 20:12:25.482270
10192 20:12:26.120992 00e80000 ################################################################
10193 20:12:26.121131
10194 20:12:26.738221 00f00000 ################################################################
10195 20:12:26.738365
10196 20:12:27.338838 00f80000 ################################################################
10197 20:12:27.338983
10198 20:12:27.952042 01000000 ################################################################
10199 20:12:27.952188
10200 20:12:28.617873 01080000 ################################################################
10201 20:12:28.618426
10202 20:12:29.349389 01100000 ################################################################
10203 20:12:29.349918
10204 20:12:30.059189 01180000 ################################################################
10205 20:12:30.059742
10206 20:12:30.754799 01200000 ################################################################
10207 20:12:30.755337
10208 20:12:31.457575 01280000 ################################################################
10209 20:12:31.458096
10210 20:12:32.149189 01300000 ################################################################
10211 20:12:32.149706
10212 20:12:32.856053 01380000 ################################################################
10213 20:12:32.856586
10214 20:12:33.564793 01400000 ################################################################
10215 20:12:33.565285
10216 20:12:34.281385 01480000 ################################################################
10217 20:12:34.281971
10218 20:12:35.002031 01500000 ################################################################
10219 20:12:35.002685
10220 20:12:35.708286 01580000 ################################################################
10221 20:12:35.708782
10222 20:12:36.417567 01600000 ################################################################
10223 20:12:36.418140
10224 20:12:37.135478 01680000 ################################################################
10225 20:12:37.135628
10226 20:12:37.823605 01700000 ################################################################
10227 20:12:37.824224
10228 20:12:38.554790 01780000 ################################################################
10229 20:12:38.555309
10230 20:12:39.288225 01800000 ################################################################
10231 20:12:39.288742
10232 20:12:40.011746 01880000 ################################################################
10233 20:12:40.012310
10234 20:12:40.746352 01900000 ################################################################
10235 20:12:40.746865
10236 20:12:41.478815 01980000 ################################################################
10237 20:12:41.479369
10238 20:12:42.203317 01a00000 ################################################################
10239 20:12:42.203926
10240 20:12:42.921782 01a80000 ################################################################
10241 20:12:42.922296
10242 20:12:43.645122 01b00000 ################################################################
10243 20:12:43.645637
10244 20:12:44.378765 01b80000 ################################################################
10245 20:12:44.379278
10246 20:12:45.104484 01c00000 ################################################################
10247 20:12:45.105007
10248 20:12:45.832364 01c80000 ################################################################
10249 20:12:45.832882
10250 20:12:46.553535 01d00000 ################################################################
10251 20:12:46.554100
10252 20:12:47.269423 01d80000 ################################################################
10253 20:12:47.269927
10254 20:12:47.984982 01e00000 ################################################################
10255 20:12:47.985491
10256 20:12:48.713838 01e80000 ################################################################
10257 20:12:48.714328
10258 20:12:49.423453 01f00000 ################################################################
10259 20:12:49.423989
10260 20:12:50.148744 01f80000 ################################################################
10261 20:12:50.149274
10262 20:12:50.876013 02000000 ################################################################
10263 20:12:50.876502
10264 20:12:51.566661 02080000 ################################################################
10265 20:12:51.567150
10266 20:12:52.290239 02100000 ################################################################
10267 20:12:52.290760
10268 20:12:52.965370 02180000 ################################################################
10269 20:12:52.965877
10270 20:12:53.669581 02200000 ################################################################
10271 20:12:53.670092
10272 20:12:54.385637 02280000 ################################################################
10273 20:12:54.386272
10274 20:12:55.112717 02300000 ################################################################
10275 20:12:55.113232
10276 20:12:55.836258 02380000 ################################################################
10277 20:12:55.836786
10278 20:12:56.551532 02400000 ################################################################
10279 20:12:56.552101
10280 20:12:57.280929 02480000 ################################################################
10281 20:12:57.281453
10282 20:12:58.010922 02500000 ################################################################
10283 20:12:58.011591
10284 20:12:58.727546 02580000 ################################################################
10285 20:12:58.728131
10286 20:12:59.438187 02600000 ################################################################
10287 20:12:59.438721
10288 20:13:00.156497 02680000 ################################################################
10289 20:13:00.157028
10290 20:13:00.888374 02700000 ################################################################
10291 20:13:00.888915
10292 20:13:01.606022 02780000 ################################################################
10293 20:13:01.606596
10294 20:13:02.326109 02800000 ################################################################
10295 20:13:02.326626
10296 20:13:03.030937 02880000 ################################################################
10297 20:13:03.031539
10298 20:13:03.732526 02900000 ################################################################
10299 20:13:03.733041
10300 20:13:04.445245 02980000 ################################################################
10301 20:13:04.445996
10302 20:13:05.162078 02a00000 ################################################################
10303 20:13:05.162669
10304 20:13:05.892094 02a80000 ################################################################
10305 20:13:05.892648
10306 20:13:06.557583 02b00000 ################################################################
10307 20:13:06.557808
10308 20:13:07.277203 02b80000 ################################################################
10309 20:13:07.277732
10310 20:13:07.975016 02c00000 ################################################################
10311 20:13:07.975151
10312 20:13:08.558760 02c80000 ################################################################
10313 20:13:08.558908
10314 20:13:09.130651 02d00000 ################################################################
10315 20:13:09.130805
10316 20:13:09.724399 02d80000 ################################################################
10317 20:13:09.724556
10318 20:13:10.303107 02e00000 ################################################################
10319 20:13:10.303254
10320 20:13:10.878321 02e80000 ################################################################
10321 20:13:10.878473
10322 20:13:11.441104 02f00000 ################################################################
10323 20:13:11.441255
10324 20:13:12.020496 02f80000 ################################################################
10325 20:13:12.020645
10326 20:13:12.596188 03000000 ################################################################
10327 20:13:12.596340
10328 20:13:13.180830 03080000 ################################################################
10329 20:13:13.180981
10330 20:13:13.768383 03100000 ################################################################
10331 20:13:13.768534
10332 20:13:14.345754 03180000 ################################################################
10333 20:13:14.345907
10334 20:13:14.936127 03200000 ################################################################
10335 20:13:14.936277
10336 20:13:15.514607 03280000 ################################################################
10337 20:13:15.514754
10338 20:13:16.093926 03300000 ################################################################
10339 20:13:16.094070
10340 20:13:16.642416 03380000 ################################################################
10341 20:13:16.642568
10342 20:13:17.209785 03400000 ################################################################
10343 20:13:17.209930
10344 20:13:17.795627 03480000 ################################################################
10345 20:13:17.795814
10346 20:13:18.387118 03500000 ################################################################
10347 20:13:18.387266
10348 20:13:18.975927 03580000 ################################################################
10349 20:13:18.976074
10350 20:13:19.567089 03600000 ################################################################
10351 20:13:19.567247
10352 20:13:20.146024 03680000 ################################################################
10353 20:13:20.146174
10354 20:13:20.824119 03700000 ################################################################
10355 20:13:20.824580
10356 20:13:21.510744 03780000 ################################################################
10357 20:13:21.511275
10358 20:13:22.214769 03800000 ################################################################
10359 20:13:22.215410
10360 20:13:22.905536 03880000 ################################################################
10361 20:13:22.906065
10362 20:13:23.534866 03900000 ################################################################
10363 20:13:23.535036
10364 20:13:24.123107 03980000 ################################################################
10365 20:13:24.123259
10366 20:13:24.708366 03a00000 ################################################################
10367 20:13:24.708516
10368 20:13:25.310520 03a80000 ################################################################
10369 20:13:25.310727
10370 20:13:25.954053 03b00000 ################################################################
10371 20:13:25.954446
10372 20:13:26.548715 03b80000 ################################################################
10373 20:13:26.548878
10374 20:13:27.140571 03c00000 ################################################################
10375 20:13:27.140722
10376 20:13:27.730476 03c80000 ################################################################
10377 20:13:27.730624
10378 20:13:28.334854 03d00000 ################################################################
10379 20:13:28.334999
10380 20:13:28.937781 03d80000 ################################################################
10381 20:13:28.937927
10382 20:13:29.533708 03e00000 ################################################################
10383 20:13:29.533856
10384 20:13:30.118164 03e80000 ################################################################
10385 20:13:30.118305
10386 20:13:30.712288 03f00000 ################################################################
10387 20:13:30.712437
10388 20:13:31.311996 03f80000 ################################################################
10389 20:13:31.312141
10390 20:13:31.916058 04000000 ################################################################
10391 20:13:31.916220
10392 20:13:32.510377 04080000 ################################################################
10393 20:13:32.510533
10394 20:13:33.105369 04100000 ################################################################
10395 20:13:33.105514
10396 20:13:33.712029 04180000 ################################################################
10397 20:13:33.712188
10398 20:13:34.310448 04200000 ################################################################
10399 20:13:34.310597
10400 20:13:34.908154 04280000 ################################################################
10401 20:13:34.908300
10402 20:13:35.487248 04300000 ################################################################
10403 20:13:35.487395
10404 20:13:36.075335 04380000 ################################################################
10405 20:13:36.075485
10406 20:13:36.647127 04400000 ################################################################
10407 20:13:36.647280
10408 20:13:37.226545 04480000 ################################################################
10409 20:13:37.226696
10410 20:13:37.813939 04500000 ################################################################
10411 20:13:37.814089
10412 20:13:38.073112 04580000 ############################ done.
10413 20:13:38.073257
10414 20:13:38.075800 The bootfile was 73102906 bytes long.
10415 20:13:38.075929
10416 20:13:38.079175 Sending tftp read request... done.
10417 20:13:38.079259
10418 20:13:38.079324 Waiting for the transfer...
10419 20:13:38.079398
10420 20:13:38.082530 00000000 # done.
10421 20:13:38.082613
10422 20:13:38.088637 Command line loaded dynamically from TFTP file: 12928116/tftp-deploy-6ddh4bb_/kernel/cmdline
10423 20:13:38.088720
10424 20:13:38.101758 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10425 20:13:38.101845
10426 20:13:38.105386 Loading FIT.
10427 20:13:38.105467
10428 20:13:38.108685 Image ramdisk-1 has 60993553 bytes.
10429 20:13:38.108766
10430 20:13:38.111997 Image fdt-1 has 47278 bytes.
10431 20:13:38.112080
10432 20:13:38.115409 Image kernel-1 has 12060038 bytes.
10433 20:13:38.115492
10434 20:13:38.121423 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10435 20:13:38.121507
10436 20:13:38.142394 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10437 20:13:38.142484
10438 20:13:38.144618 Choosing best match conf-1 for compat google,spherion-rev2.
10439 20:13:38.149755
10440 20:13:38.153483 Connected to device vid:did:rid of 1ae0:0028:00
10441 20:13:38.161436
10442 20:13:38.163994 tpm_get_response: command 0x17b, return code 0x0
10443 20:13:38.164077
10444 20:13:38.167271 ec_init: CrosEC protocol v3 supported (256, 248)
10445 20:13:38.171440
10446 20:13:38.174788 tpm_cleanup: add release locality here.
10447 20:13:38.174871
10448 20:13:38.174936 Shutting down all USB controllers.
10449 20:13:38.178085
10450 20:13:38.178166 Removing current net device
10451 20:13:38.178231
10452 20:13:38.184942 Exiting depthcharge with code 4 at timestamp: 135248446
10453 20:13:38.185024
10454 20:13:38.187846 LZMA decompressing kernel-1 to 0x821a6718
10455 20:13:38.187929
10456 20:13:38.191221 LZMA decompressing kernel-1 to 0x40000000
10457 20:13:39.691142
10458 20:13:39.691298 jumping to kernel
10459 20:13:39.691843 end: 2.2.4 bootloader-commands (duration 00:01:47) [common]
10460 20:13:39.691944 start: 2.2.5 auto-login-action (timeout 00:02:38) [common]
10461 20:13:39.692021 Setting prompt string to ['Linux version [0-9]']
10462 20:13:39.692090 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10463 20:13:39.692160 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10464 20:13:39.773980
10465 20:13:39.777195 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10466 20:13:39.780930 start: 2.2.5.1 login-action (timeout 00:02:38) [common]
10467 20:13:39.781036 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10468 20:13:39.781108 Setting prompt string to []
10469 20:13:39.781189 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10470 20:13:39.781264 Using line separator: #'\n'#
10471 20:13:39.781324 No login prompt set.
10472 20:13:39.781386 Parsing kernel messages
10473 20:13:39.781440 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10474 20:13:39.781540 [login-action] Waiting for messages, (timeout 00:02:38)
10475 20:13:39.781602 Waiting using forced prompt support (timeout 00:01:19)
10476 20:13:39.800138 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10477 20:13:39.803454 [ 0.000000] random: crng init done
10478 20:13:39.810736 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10479 20:13:39.813635 [ 0.000000] efi: UEFI not found.
10480 20:13:39.820386 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10481 20:13:39.829823 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10482 20:13:39.839792 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10483 20:13:39.846758 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10484 20:13:39.853351 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10485 20:13:39.859623 [ 0.000000] printk: bootconsole [mtk8250] enabled
10486 20:13:39.866640 [ 0.000000] NUMA: No NUMA configuration found
10487 20:13:39.872618 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10488 20:13:39.880159 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10489 20:13:39.880288 [ 0.000000] Zone ranges:
10490 20:13:39.886321 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10491 20:13:39.889406 [ 0.000000] DMA32 empty
10492 20:13:39.896092 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10493 20:13:39.899297 [ 0.000000] Movable zone start for each node
10494 20:13:39.902828 [ 0.000000] Early memory node ranges
10495 20:13:39.909008 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10496 20:13:39.915947 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10497 20:13:39.922591 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10498 20:13:39.929253 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10499 20:13:39.935531 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10500 20:13:39.942318 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10501 20:13:39.998588 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10502 20:13:40.005894 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10503 20:13:40.011830 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10504 20:13:40.015195 [ 0.000000] psci: probing for conduit method from DT.
10505 20:13:40.021626 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10506 20:13:40.025073 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10507 20:13:40.031716 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10508 20:13:40.035266 [ 0.000000] psci: SMC Calling Convention v1.2
10509 20:13:40.041442 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10510 20:13:40.045121 [ 0.000000] Detected VIPT I-cache on CPU0
10511 20:13:40.051369 [ 0.000000] CPU features: detected: GIC system register CPU interface
10512 20:13:40.058195 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10513 20:13:40.064988 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10514 20:13:40.071473 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10515 20:13:40.081030 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10516 20:13:40.088768 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10517 20:13:40.091096 [ 0.000000] alternatives: applying boot alternatives
10518 20:13:40.098047 [ 0.000000] Fallback order for Node 0: 0
10519 20:13:40.104757 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10520 20:13:40.107794 [ 0.000000] Policy zone: Normal
10521 20:13:40.120530 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10522 20:13:40.130283 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10523 20:13:40.142794 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10524 20:13:40.153272 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10525 20:13:40.159536 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10526 20:13:40.162430 <6>[ 0.000000] software IO TLB: area num 8.
10527 20:13:40.219591 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10528 20:13:40.368914 <6>[ 0.000000] Memory: 7907632K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 445136K reserved, 32768K cma-reserved)
10529 20:13:40.376121 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10530 20:13:40.382545 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10531 20:13:40.385328 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10532 20:13:40.392186 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10533 20:13:40.398584 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10534 20:13:40.405324 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10535 20:13:40.411581 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10536 20:13:40.418956 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10537 20:13:40.424867 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10538 20:13:40.431324 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10539 20:13:40.435309 <6>[ 0.000000] GICv3: 608 SPIs implemented
10540 20:13:40.437750 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10541 20:13:40.444287 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10542 20:13:40.448248 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10543 20:13:40.454567 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10544 20:13:40.467455 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10545 20:13:40.481036 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10546 20:13:40.487099 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10547 20:13:40.495458 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10548 20:13:40.509089 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10549 20:13:40.515656 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10550 20:13:40.522321 <6>[ 0.009185] Console: colour dummy device 80x25
10551 20:13:40.532006 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10552 20:13:40.538725 <6>[ 0.024378] pid_max: default: 32768 minimum: 301
10553 20:13:40.541822 <6>[ 0.029250] LSM: Security Framework initializing
10554 20:13:40.548408 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10555 20:13:40.558272 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10556 20:13:40.565379 <6>[ 0.051421] cblist_init_generic: Setting adjustable number of callback queues.
10557 20:13:40.572330 <6>[ 0.058864] cblist_init_generic: Setting shift to 3 and lim to 1.
10558 20:13:40.581798 <6>[ 0.065242] cblist_init_generic: Setting adjustable number of callback queues.
10559 20:13:40.588639 <6>[ 0.072669] cblist_init_generic: Setting shift to 3 and lim to 1.
10560 20:13:40.591594 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10561 20:13:40.598247 <6>[ 0.079113] rcu: Max phase no-delay instances is 1000.
10562 20:13:40.604995 <6>[ 0.079137] printk: bootconsole [mtk8250] printing thread started
10563 20:13:40.611652 <6>[ 0.097459] EFI services will not be available.
10564 20:13:40.614587 <6>[ 0.097658] smp: Bringing up secondary CPUs ...
10565 20:13:40.618299 <6>[ 0.097966] Detected VIPT I-cache on CPU1
10566 20:13:40.627968 <6>[ 0.098032] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10567 20:13:40.635200 <6>[ 0.098063] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10568 20:13:40.643728 <6>[ 0.125918] Detected VIPT I-cache on CPU2
10569 20:13:40.653780 <6>[ 0.125964] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10570 20:13:40.660396 <6>[ 0.125978] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10571 20:13:40.663529 <6>[ 0.126234] Detected VIPT I-cache on CPU3
10572 20:13:40.670095 <6>[ 0.126279] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10573 20:13:40.676525 <6>[ 0.126292] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10574 20:13:40.684064 <6>[ 0.126604] CPU features: detected: Spectre-v4
10575 20:13:40.686407 <6>[ 0.126611] CPU features: detected: Spectre-BHB
10576 20:13:40.689951 <6>[ 0.126616] Detected PIPT I-cache on CPU4
10577 20:13:40.696374 <6>[ 0.126674] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10578 20:13:40.703102 <6>[ 0.126691] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10579 20:13:40.709373 <6>[ 0.126985] Detected PIPT I-cache on CPU5
10580 20:13:40.716377 <6>[ 0.127046] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10581 20:13:40.722588 <6>[ 0.127062] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10582 20:13:40.725823 <6>[ 0.127339] Detected PIPT I-cache on CPU6
10583 20:13:40.735907 <6>[ 0.127404] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10584 20:13:40.742500 <6>[ 0.127419] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10585 20:13:40.745813 <6>[ 0.127710] Detected PIPT I-cache on CPU7
10586 20:13:40.752661 <6>[ 0.127773] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10587 20:13:40.759284 <6>[ 0.127789] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10588 20:13:40.762590 <6>[ 0.127835] smp: Brought up 1 node, 8 CPUs
10589 20:13:40.769266 <6>[ 0.127840] SMP: Total of 8 processors activated.
10590 20:13:40.775634 <6>[ 0.127843] CPU features: detected: 32-bit EL0 Support
10591 20:13:40.782806 <6>[ 0.127845] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10592 20:13:40.789587 <6>[ 0.127848] CPU features: detected: Common not Private translations
10593 20:13:40.795349 <6>[ 0.127850] CPU features: detected: CRC32 instructions
10594 20:13:40.801770 <6>[ 0.127852] CPU features: detected: RCpc load-acquire (LDAPR)
10595 20:13:40.805349 <6>[ 0.127854] CPU features: detected: LSE atomic instructions
10596 20:13:40.811616 <6>[ 0.127856] CPU features: detected: Privileged Access Never
10597 20:13:40.818678 <6>[ 0.127857] CPU features: detected: RAS Extension Support
10598 20:13:40.824722 <6>[ 0.127860] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10599 20:13:40.827980 <6>[ 0.127926] CPU: All CPU(s) started at EL2
10600 20:13:40.834572 <6>[ 0.127927] alternatives: applying system-wide alternatives
10601 20:13:40.838045 <6>[ 0.141088] devtmpfs: initialized
10602 20:13:40.870737 � B�͡����������ɥ��郪��Bzɑ�Ɂ�b��ʲ�ѕͥkR�<6>[ 0.355440] printk<: console [ttyS0] printing thread started
10603 20:13:40.873986 6<6>[ 0.355461] printk: console [ttyS0] enabled
10604 20:13:40.877205 >[ 0.225616] pnp: PnP ACPI: disabled
10605 20:13:40.886904 <6>[ 0.355465] printk: bootconsole [mtk8250] disabled
10606 20:13:40.893102 <6>[ 0.369452] printk: bootconsole [mtk8250] printing thread stopped
10607 20:13:40.895968 <6>[ 0.370841] SuperH (H)SCI(F) driver initialized
10608 20:13:40.902945 <6>[ 0.371322] msm_serial: driver initialized
10609 20:13:40.910218 <6>[ 0.375913] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10610 20:13:40.919413 <6>[ 0.375942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10611 20:13:40.926364 <6>[ 0.375972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10612 20:13:40.936161 <6>[ 0.376000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10613 20:13:40.946072 <6>[ 0.376022] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10614 20:13:40.958857 <6>[ 0.376050] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10615 20:13:40.975040 <6>[ 0.376078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10616 20:13:40.975871 <6>[ 0.376198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10617 20:13:40.980760 <6>[ 0.376227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10618 20:13:40.984988 <6>[ 0.388692] loop: module loaded
10619 20:13:40.992514 <6>[ 0.391173] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10620 20:13:40.996035 <4>[ 0.407786] mtk-pmic-keys: Failed to locate of_node [id: -1]
10621 20:13:40.999885 <6>[ 0.408721] megasas: 07.719.03.00-rc1
10622 20:13:41.006394 <6>[ 0.420802] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10623 20:13:41.009633 <6>[ 0.420915] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10624 20:13:41.017084 <6>[ 0.432865] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10625 20:13:41.030053 <6>[ 0.491980] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10626 20:13:43.417972 <6>[ 2.902821] Freeing initrd memory: 59560K
10627 20:13:43.425998 <6>[ 2.910182] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10628 20:13:43.432300 <6>[ 2.914791] tun: Universal TUN/TAP device driver, 1.6
10629 20:13:43.436554 <6>[ 2.915528] thunder_xcv, ver 1.0
10630 20:13:43.438845 <6>[ 2.915547] thunder_bgx, ver 1.0
10631 20:13:43.442325 <6>[ 2.915561] nicpf, ver 1.0
10632 20:13:43.449306 <6>[ 2.916593] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10633 20:13:43.456242 <6>[ 2.916596] hns3: Copyright (c) 2017 Huawei Corporation.
10634 20:13:43.458847 <6>[ 2.916620] hclge is initializing
10635 20:13:43.462481 <6>[ 2.916634] e1000: Intel(R) PRO/1000 Network Driver
10636 20:13:43.469257 <6>[ 2.916636] e1000: Copyright (c) 1999-2006 Intel Corporation.
10637 20:13:43.476938 <6>[ 2.916652] e1000e: Intel(R) PRO/1000 Network Driver
10638 20:13:43.482965 <6>[ 2.916653] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10639 20:13:43.486674 <6>[ 2.916668] igb: Intel(R) Gigabit Ethernet Network Driver
10640 20:13:43.492996 <6>[ 2.916671] igb: Copyright (c) 2007-2014 Intel Corporation.
10641 20:13:43.499971 <6>[ 2.916687] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10642 20:13:43.507094 <6>[ 2.916689] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10643 20:13:43.510154 <6>[ 2.916975] sky2: driver version 1.30
10644 20:13:43.516572 <6>[ 2.918037] VFIO - User Level meta-driver version: 0.3
10645 20:13:43.520118 <6>[ 2.920772] usbcore: registered new interface driver usb-storage
10646 20:13:43.526349 <6>[ 2.920958] usbcore: registered new device driver onboard-usb-hub
10647 20:13:43.533489 <6>[ 2.923709] mt6397-rtc mt6359-rtc: registered as rtc0
10648 20:13:43.542970 <6>[ 2.923861] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:13:43 UTC (1709496823)
10649 20:13:43.546518 <6>[ 2.924460] i2c_dev: i2c /dev entries driver
10650 20:13:43.553078 <6>[ 2.931531] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10651 20:13:43.559530 <6>[ 2.946516] cpu cpu0: EM: created perf domain
10652 20:13:43.562763 <6>[ 2.946842] cpu cpu4: EM: created perf domain
10653 20:13:43.570065 <6>[ 2.948060] sdhci: Secure Digital Host Controller Interface driver
10654 20:13:43.575891 <6>[ 2.948061] sdhci: Copyright(c) Pierre Ossman
10655 20:13:43.579431 <6>[ 2.948416] Synopsys Designware Multimedia Card Interface Driver
10656 20:13:43.586082 <6>[ 2.948777] sdhci-pltfm: SDHCI platform and OF driver helper
10657 20:13:43.592250 <6>[ 2.951651] ledtrig-cpu: registered to indicate activity on CPUs
10658 20:13:43.595758 <6>[ 2.951922] mmc0: CQHCI version 5.10
10659 20:13:43.602085 <6>[ 2.952380] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10660 20:13:43.609144 <6>[ 2.952661] usbcore: registered new interface driver usbhid
10661 20:13:43.612088 <6>[ 2.952662] usbhid: USB HID core driver
10662 20:13:43.618745 <6>[ 2.952764] spi_master spi0: will run message pump with realtime priority
10663 20:13:43.631965 <6>[ 2.983961] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10664 20:13:43.645201 <6>[ 2.986756] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10665 20:13:43.651563 <6>[ 2.987764] cros-ec-spi spi0.0: Chrome EC device registered
10666 20:13:43.662291 <6>[ 3.005130] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10667 20:13:43.668783 <6>[ 3.007419] NET: Registered PF_PACKET protocol family
10668 20:13:43.671839 <6>[ 3.007516] 9pnet: Installing 9P2000 support
10669 20:13:43.675586 <5>[ 3.007557] Key type dns_resolver registered
10670 20:13:43.682061 <6>[ 3.007927] registered taskstats version 1
10671 20:13:43.684662 <5>[ 3.007946] Loading compiled-in X.509 certificates
10672 20:13:43.694935 <4>[ 3.022538] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10673 20:13:43.707823 <4>[ 3.022707] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 20:13:43.714433 <3>[ 3.022718] debugfs: File 'uA_load' in directory '/' already present!
10675 20:13:43.721438 <3>[ 3.022725] debugfs: File 'min_uV' in directory '/' already present!
10676 20:13:43.727871 <3>[ 3.022728] debugfs: File 'max_uV' in directory '/' already present!
10677 20:13:43.734492 <3>[ 3.022731] debugfs: File 'constraint_flags' in directory '/' already present!
10678 20:13:43.741026 <3>[ 3.024772] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 20:13:43.747808 <6>[ 3.033091] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 20:13:43.754473 <6>[ 3.033749] xhci-mtk 11200000.usb: xHCI Host Controller
10681 20:13:43.760757 <6>[ 3.033770] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 20:13:43.770968 <6>[ 3.033993] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 20:13:43.777646 <6>[ 3.034042] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 20:13:43.785017 <6>[ 3.034146] xhci-mtk 11200000.usb: xHCI Host Controller
10685 20:13:43.790195 <6>[ 3.034153] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 20:13:43.797209 <6>[ 3.034161] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 20:13:43.800413 <6>[ 3.034878] hub 1-0:1.0: USB hub found
10688 20:13:43.807093 <6>[ 3.034971] hub 1-0:1.0: 1 port detected
10689 20:13:43.813946 <6>[ 3.035205] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 20:13:43.817139 <6>[ 3.035439] hub 2-0:1.0: USB hub found
10691 20:13:43.824185 <6>[ 3.035456] hub 2-0:1.0: 1 port detected
10692 20:13:43.826525 <6>[ 3.038846] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 20:13:43.829902 <6>[ 3.051471] mmc0: Command Queue Engine enabled
10694 20:13:43.836586 <6>[ 3.051484] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10695 20:13:43.843296 <6>[ 3.052137] mmcblk0: mmc0:0001 DA4128 116 GiB
10696 20:13:43.850301 <6>[ 3.053181] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10697 20:13:43.859648 <6>[ 3.053188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10698 20:13:43.866180 <4>[ 3.053356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10699 20:13:43.876268 <6>[ 3.053996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10700 20:13:43.882871 <6>[ 3.053999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10701 20:13:43.893217 <6>[ 3.054126] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10702 20:13:43.899092 <6>[ 3.054137] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10703 20:13:43.906380 <6>[ 3.054141] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10704 20:13:43.915640 <6>[ 3.054147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10705 20:13:43.923183 <6>[ 3.055632] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10706 20:13:43.929007 <6>[ 3.055841] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10707 20:13:43.940213 <6>[ 3.055868] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10708 20:13:43.945385 <6>[ 3.055873] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10709 20:13:43.955227 <6>[ 3.055879] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10710 20:13:43.965350 <6>[ 3.055884] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10711 20:13:43.972174 <6>[ 3.055889] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10712 20:13:43.981974 <6>[ 3.055895] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10713 20:13:43.988909 <6>[ 3.055900] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10714 20:13:43.998372 <6>[ 3.055905] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10715 20:13:44.005581 <6>[ 3.055912] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10716 20:13:44.014961 <6>[ 3.055918] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10717 20:13:44.022542 <6>[ 3.055923] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10718 20:13:44.032181 <6>[ 3.055928] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10719 20:13:44.037886 <6>[ 3.055934] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10720 20:13:44.048734 <6>[ 3.055940] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10721 20:13:44.054836 <6>[ 3.056582] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10722 20:13:44.057741 <6>[ 3.057251] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10723 20:13:44.064729 <6>[ 3.057650] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10724 20:13:44.070760 <6>[ 3.058006] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10725 20:13:44.077452 <6>[ 3.058309] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10726 20:13:44.084067 <6>[ 3.058573] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10727 20:13:44.090584 <6>[ 3.058960] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10728 20:13:44.097610 <6>[ 3.059607] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10729 20:13:44.107066 <6>[ 3.059807] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10730 20:13:44.113817 <6>[ 3.059824] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10731 20:13:44.123409 <6>[ 3.059830] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10732 20:13:44.133955 <6>[ 3.059836] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10733 20:13:44.143335 <6>[ 3.059842] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10734 20:13:44.153846 <6>[ 3.059849] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10735 20:13:44.163008 <6>[ 3.059854] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10736 20:13:44.169672 <6>[ 3.059860] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10737 20:13:44.179629 <6>[ 3.059865] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10738 20:13:44.189411 <6>[ 3.059872] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10739 20:13:44.199435 <6>[ 3.059877] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10740 20:13:44.209306 <6>[ 3.060606] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10741 20:13:44.216189 <6>[ 3.457463] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10742 20:13:44.219151 <6>[ 3.609477] hub 1-1:1.0: USB hub found
10743 20:13:44.222700 <6>[ 3.609843] hub 1-1:1.0: 4 ports detected
10744 20:13:44.229130 <6>[ 3.612892] hub 1-1:1.0: USB hub found
10745 20:13:44.232546 <6>[ 3.613151] hub 1-1:1.0: 4 ports detected
10746 20:13:44.257160 <6>[ 3.737659] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10747 20:13:44.277918 <6>[ 3.763094] hub 2-1:1.0: USB hub found
10748 20:13:44.281549 <6>[ 3.763516] hub 2-1:1.0: 3 ports detected
10749 20:13:44.284545 <6>[ 3.766815] hub 2-1:1.0: USB hub found
10750 20:13:44.290796 <6>[ 3.767169] hub 2-1:1.0: 3 ports detected
10751 20:13:44.445181 <6>[ 3.925669] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10752 20:13:44.566008 <6>[ 4.053118] hub 1-1.4:1.0: USB hub found
10753 20:13:44.569302 <6>[ 4.053558] hub 1-1.4:1.0: 2 ports detected
10754 20:13:44.572679 <6>[ 4.057074] hub 1-1.4:1.0: USB hub found
10755 20:13:44.579516 <6>[ 4.057431] hub 1-1.4:1.0: 2 ports detected
10756 20:13:44.649652 <6>[ 4.129810] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10757 20:13:44.864972 <6>[ 4.345498] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10758 20:13:45.049112 <6>[ 4.529658] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10759 20:13:55.873969 <6>[ 15.363091] ALSA device list:
10760 20:13:55.880179 <6>[ 15.363257] No soundcards found.
10761 20:13:55.883649 <6>[ 15.367348] Freeing unused kernel memory: 8448K
10762 20:13:55.886643 <6>[ 15.367460] Run /init as init process
10763 20:13:55.908862 <6>[ 15.395559] NET: Registered PF_INET6 protocol family
10764 20:13:55.912044 <6>[ 15.396718] Segment Routing with IPv6
10765 20:13:55.918521 <6>[ 15.396729] In-situ OAM (IOAM) with IPv6
10766 20:13:55.928293
10767 20:13:55.961477 Welcome to [1<30>[ 15.420367] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10768 20:13:55.967927 <30>[ 15.420387] systemd[1]: Detected architecture arm64.
10769 20:13:55.971354 mDebian GNU/Linux 12 (bookworm)[0m!
10770 20:13:55.971436
10771 20:13:55.988344 <30>[ 15.473815] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10772 20:13:56.119646 <30>[ 15.605073] systemd[1]: Queued start job for default target graphical.target.
10773 20:13:56.157170 [[0;32m OK [0m] Created slic<30>[ 15.639277] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10774 20:13:56.160661 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10775 20:13:56.184522 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.666253] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10776 20:13:56.187583 m-modpr…lice[0m - Slice /system/modprobe.
10777 20:13:56.216982 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.698601] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10778 20:13:56.223048 m-seria…[0m - Slice /system/serial-getty.
10779 20:13:56.244853 [[0;32m OK [0m] Created slic<30>[ 15.726672] systemd[1]: Created slice user.slice - User and Session Slice.
10780 20:13:56.247574 e [0;1;39muser.slice[0m - User and Session Slice.
10781 20:13:56.271894 [[0;32m OK [0m] Started [0;<30>[ 15.750549] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10782 20:13:56.275783 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10783 20:13:56.299583 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 15.778459] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10784 20:13:56.302905 -passwo… Requests to Wall Directory Watch.
10785 20:13:56.337085 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 15.805769] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10786 20:13:56.346889 tsetup.…get[0<30>[ 15.806001] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10787 20:13:56.346981 m - Local Encrypted Volumes.
10788 20:13:56.371719 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 15.850174] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10789 20:13:56.374895 grityse…Local Integrity Protected Volumes.
10790 20:13:56.396125 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 15.877722] systemd[1]: Reached target paths.target - Path Units.
10791 20:13:56.396213 s.target[0m - Path Units.
10792 20:13:56.420217 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 15.902138] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10793 20:13:56.423572 te-fs.target[0m - Remote File Systems.
10794 20:13:56.443442 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 15.925676] systemd[1]: Reached target slices.target - Slice Units.
10795 20:13:56.446730 es.target[0m - Slice Units.
10796 20:13:56.468378 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 15.950149] systemd[1]: Reached target swap.target - Swaps.
10797 20:13:56.468493 .target[0m - Swaps.
10798 20:13:56.492355 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 15.974190] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10799 20:13:56.499054 tysetup… - Local Verity Protected Volumes.
10800 20:13:56.520344 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.002095] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10801 20:13:56.526371 d-initc… initctl Compatibility Named Pipe.
10802 20:13:56.548638 [[0;32m OK [0m] Listening on<30>[ 16.031024] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10803 20:13:56.555482 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10804 20:13:56.580310 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.058253] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10805 20:13:56.582880 d-journ…t[0m - Journal Socket (/dev/log).
10806 20:13:56.604991 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.086267] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10807 20:13:56.607942 d-journald.socket[0m - Journal Socket.
10808 20:13:56.628358 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.110335] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10809 20:13:56.634623 d-udevd….socket[0m - udev Control Socket.
10810 20:13:56.656408 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 16.138129] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10811 20:13:56.662309 d-udevd…l.socket[0m - udev Kernel Socket.
10812 20:13:56.716016 Mounting [0;1;39mdev-hugepages.mount[<30>[ 16.197841] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10813 20:13:56.718569 0m - Huge Pages File System...
10814 20:13:56.744093 Mounting [0;1;39mdev-mqueue.mount…P<30>[ 16.226035] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10815 20:13:56.747475 OSIX Message Queue File System...
10816 20:13:56.777205 Mounting [0;1;39msys-kernel-debug.…<30>[ 16.258109] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10817 20:13:56.779075 [0m - Kernel Debug File System...
10818 20:13:56.810485 <30>[ 16.286091] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10819 20:13:56.820220 <30>[ 16.291210] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10820 20:13:56.826705 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10821 20:13:56.853135 Starting [0;1;39mmodpr<30>[ 16.334725] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10822 20:13:56.856510 obe@configfs…m - Load Kernel Module configfs...
10823 20:13:56.884829 Starting [0;1;39mmodpr<30>[ 16.366908] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10824 20:13:56.898028 obe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 16.379373] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10825 20:13:56.898225 .
10826 20:13:56.939781 Starting [0;1;39mmodprobe@drm.service<30>[ 16.422008] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10827 20:13:56.943646 [0m - Load Kernel Module drm...
10828 20:13:56.969277 Starting [0;1;39mmodpr<30>[ 16.450958] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10829 20:13:56.972632 obe@efi_psto…- Load Kernel Module efi_pstore...
10830 20:13:57.001377 Starting [0;1;39mmodpr<30>[ 16.483019] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10831 20:13:57.004256 obe@loop.ser…e[0m - Load Kernel Module loop...
10832 20:13:57.036100 Starting [0;1;39msystemd-journald.serv<30>[ 16.518102] systemd[1]: Starting systemd-journald.service - Journal Service...
10833 20:13:57.039577 ice[0m - Journal Service...
10834 20:13:57.058549 Startin<30>[ 16.544239] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10835 20:13:57.065060 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10836 20:13:57.115809 Starting [0;1;39msystemd-network-g… <30>[ 16.594154] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10837 20:13:57.118787 units from Kernel command line...
10838 20:13:57.147612 Starting [0;1;39msystemd-remount-f…n<30>[ 16.626480] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10839 20:13:57.151014 t Root and Kernel File Systems...
10840 20:13:57.171872 <30>[ 16.657103] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10841 20:13:57.178720 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10842 20:13:57.204963 [[0;32m OK [0m] Started [0;<30>[ 16.687243] systemd[1]: Started systemd-journald.service - Journal Service.
10843 20:13:57.208586 1;39msystemd-journald.service[0m - Journal Service.
10844 20:13:57.229765 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10845 20:13:57.249772 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10846 20:13:57.269371 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10847 20:13:57.288828 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10848 20:13:57.309848 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10849 20:13:57.329279 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10850 20:13:57.349598 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10851 20:13:57.373589 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10852 20:13:57.394755 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10853 20:13:57.414696 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10854 20:13:57.438046 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10855 20:13:57.458637 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10856 20:13:57.477099 See 'systemctl status systemd-remount-fs.service' for details.
10857 20:13:57.501181 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10858 20:13:57.527321 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10859 20:13:57.584645 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10860 20:13:57.608618 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10861 20:13:57.631555 <46>[ 17.115890] systemd-journald[195]: Received client request to flush runtime journal.
10862 20:13:57.643941 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10863 20:13:57.663262 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10864 20:13:57.685676 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10865 20:13:57.714554 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10866 20:13:57.733485 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10867 20:13:57.753388 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10868 20:13:57.773660 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10869 20:13:57.793226 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10870 20:13:57.840623 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10871 20:13:57.863252 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10872 20:13:57.883955 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10873 20:13:57.903586 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10874 20:13:57.927596 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10875 20:13:57.951874 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10876 20:13:57.974956 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10877 20:13:58.026881 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10878 20:13:58.053806 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10879 20:13:58.064004 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10880 20:13:58.109843 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10881 20:13:58.138643 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10882 20:13:58.160387 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10883 20:13:58.275202 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10884 20:13:58.297942 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10885 20:13:58.316832 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10886 20:13:58.341545 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard <6>[ 17.827085] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10887 20:13:58.352368 unused blocks on<3>[ 17.827269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 20:13:58.354938 ce a week.
10889 20:13:58.361724 <3>[ 17.827301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10890 20:13:58.371456 <3>[ 17.827316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 20:13:58.378332 <3>[ 17.850562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 20:13:58.387996 [[0;32m OK [<3>[ 17.850587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 20:13:58.397862 0m] Reached targ<3>[ 17.850593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 20:13:58.407594 et [0;1;39mtime<3>[ 17.850599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 20:13:58.414172 <3>[ 17.850603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 20:13:58.421512 <6>[ 17.857849] remoteproc remoteproc0: scp is available
10897 20:13:58.424433 <6>[ 17.858034] remoteproc remoteproc0: powering up scp
10898 20:13:58.434051 <6>[ 17.858044] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10899 20:13:58.440635 <6>[ 17.858076] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10900 20:13:58.447293 <3>[ 17.868593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 20:13:58.457879 rs.target[0m - <3>[ 17.871223] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 20:13:58.463784 <3>[ 17.871243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 20:13:58.467601 Timer Units.
10904 20:13:58.473650 <3>[ 17.871251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 20:13:58.483825 <3>[ 17.872126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 20:13:58.490416 <3>[ 17.872144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 20:13:58.500111 [[0;32m OK [<3>[ 17.872152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 20:13:58.510010 0m] Listening on<3>[ 17.872168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 20:13:58.521098 [0;1;39mdbus.s<3>[ 17.872181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 20:13:58.527171 <6>[ 17.874167] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10911 20:13:58.537140 ocket[…- D-Bu<6>[ 17.874212] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10912 20:13:58.547330 <6>[ 17.874223] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10913 20:13:58.554062 <3>[ 17.882923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 20:13:58.560500 <4>[ 17.964168] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10915 20:13:58.567362 <4>[ 17.965714] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10916 20:13:58.577072 <6>[ 17.965728] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10917 20:13:58.580600 <6>[ 17.977563] mc: Linux media interface: v0.10
10918 20:13:58.591464 s System Message<6>[ 17.984274] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10919 20:13:58.598072 <6>[ 17.984276] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10920 20:13:58.604560 <6>[ 17.984289] remoteproc remoteproc0: remote processor scp is now up
10921 20:13:58.605023 Bus Socket.
10922 20:13:58.614075 <4>[ 17.995453] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 20:13:58.620755 <4>[ 17.995453] Fallback method does not support PEC.
10924 20:13:58.627664 <6>[ 18.005256] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10925 20:13:58.631795 <6>[ 18.005284] pci_bus 0000:00: root bus resource [bus 00-ff]
10926 20:13:58.637542 <6>[ 18.005292] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10927 20:13:58.647826 <6>[ 18.005297] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10928 20:13:58.654574 <6>[ 18.005343] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10929 20:13:58.664761 [[0;32m OK [<6>[ 18.005410] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10930 20:13:58.667779 <6>[ 18.005505] pci 0000:00:00.0: supports D1 D2
10931 20:13:58.674051 <6>[ 18.005508] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10932 20:13:58.684269 <3>[ 18.021296] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 20:13:58.695167 0m] Reached targ<3>[ 18.043334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 20:13:58.701183 <6>[ 18.051662] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10935 20:13:58.707917 <6>[ 18.064213] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10936 20:13:58.717849 <6>[ 18.064249] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10937 20:13:58.724381 <6>[ 18.064266] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10938 20:13:58.731221 et [0;1;39msock<6>[ 18.064281] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10939 20:13:58.738797 <6>[ 18.064394] pci 0000:01:00.0: supports D1 D2
10940 20:13:58.745738 ets.target[0m -<6>[ 18.064396] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10941 20:13:58.755928 <3>[ 18.087515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 20:13:58.756444 Socket Units.
10943 20:13:58.761727 <6>[ 18.091385] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10944 20:13:58.772530 <6>[ 18.091434] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10945 20:13:58.779296 <6>[ 18.091437] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10946 20:13:58.786093 <6>[ 18.091447] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10947 20:13:58.795901 [[0;32m OK [<6>[ 18.091460] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10948 20:13:58.806566 0m] Reached targ<6>[ 18.091472] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10949 20:13:58.813234 et [0;1;39mbasi<6>[ 18.091484] pci 0000:00:00.0: PCI bridge to [bus 01]
10950 20:13:58.823297 c.target[0m - B<6>[ 18.091489] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10951 20:13:58.827380 <6>[ 18.091596] usbcore: registered new device driver r8152-cfgselector
10952 20:13:58.830374 asic System.
10953 20:13:58.840162 <6>[ 18.093208] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10954 20:13:58.843819 <6>[ 18.095730] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10955 20:13:58.849910 <6>[ 18.097787] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10956 20:13:58.857480 <6>[ 18.097992] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10957 20:13:58.865147 <6>[ 18.113414] videodev: Linux video capture interface: v2.00
10958 20:13:58.870665 <6>[ 18.121096] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10959 20:13:58.880606 <6>[ 18.122800] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10960 20:13:58.887797 <3>[ 18.124904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 20:13:58.897655 <3>[ 18.146093] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 20:13:58.907809 <6>[ 18.154250] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10963 20:13:58.917568 <6>[ 18.154652] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10964 20:13:58.924662 <6>[ 18.178779] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10965 20:13:58.927725 <6>[ 18.190795] Bluetooth: Core ver 2.22
10966 20:13:58.934212 <6>[ 18.190868] NET: Registered PF_BLUETOOTH protocol family
10967 20:13:58.940559 <6>[ 18.190870] Bluetooth: HCI device and connection manager initialized
10968 20:13:58.944382 <6>[ 18.190899] Bluetooth: HCI socket layer initialized
10969 20:13:58.950272 <6>[ 18.190904] Bluetooth: L2CAP socket layer initialized
10970 20:13:58.956846 <6>[ 18.190916] Bluetooth: SCO socket layer initialized
10971 20:13:58.963499 <3>[ 18.191073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 20:13:58.974118 <5>[ 18.191420] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10973 20:13:58.980919 <4>[ 18.201101] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10974 20:13:58.990441 <4>[ 18.201142] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10975 20:13:58.996274 <5>[ 18.205807] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10976 20:13:59.003444 <5>[ 18.206279] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10977 20:13:59.013743 <4>[ 18.206369] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10978 20:13:59.019293 <6>[ 18.206377] cfg80211: failed to load regulatory.db
10979 20:13:59.026106 <6>[ 18.228359] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10980 20:13:59.039557 <6>[ 18.229414] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10981 20:13:59.043195 <6>[ 18.229542] usbcore: registered new interface driver uvcvideo
10982 20:13:59.051967 <3>[ 18.253017] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 20:13:59.062594 <3>[ 18.253832] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10984 20:13:59.065198 <6>[ 18.256458] r8152 2-1.3:1.0 eth0: v1.12.13
10985 20:13:59.072618 <6>[ 18.256554] usbcore: registered new interface driver r8152
10986 20:13:59.075640 <6>[ 18.258282] usbcore: registered new interface driver btusb
10987 20:13:59.088945 <4>[ 18.258773] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10988 20:13:59.091973 <3>[ 18.258783] Bluetooth: hci0: Failed to load firmware file (-2)
10989 20:13:59.098733 <3>[ 18.258786] Bluetooth: hci0: Failed to set up firmware (-2)
10990 20:13:59.108815 <4>[ 18.258789] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10991 20:13:59.115626 <6>[ 18.265347] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10992 20:13:59.124763 <3>[ 18.265829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 20:13:59.131392 <6>[ 18.280793] usbcore: registered new interface driver cdc_ether
10994 20:13:59.138289 <6>[ 18.281612] usbcore: registered new interface driver r8153_ecm
10995 20:13:59.145061 <3>[ 18.288256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 20:13:59.154532 Startin<6>[ 18.309784] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10997 20:13:59.161941 <6>[ 18.309852] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10998 20:13:59.168237 <6>[ 18.309974] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10999 20:13:59.174369 <6>[ 18.329489] mt7921e 0000:01:00.0: ASIC revision: 79610010
11000 20:13:59.181671 <6>[ 18.424343] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11001 20:13:59.185062 <6>[ 18.424343]
11002 20:13:59.187778 g [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11003 20:13:59.198615 <6>[ 18.681080] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11004 20:13:59.211725 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11005 20:13:59.231627 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11006 20:13:59.249036 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11007 20:13:59.279747 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11008 20:13:59.322423 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11009 20:13:59.348733 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11010 20:13:59.385473 [[0;32m OK [0m] Reached target [0;1;39mblue<46>[ 18.854805] systemd-journald[195]: Data hash table of /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11011 20:13:59.402246 <46>[ 18.854827] systemd-journald[195]: /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal: Journal header limits reached or header out-of-date, rotating.
11012 20:13:59.405555 tooth.target[0m - Bluetooth Support.
11013 20:13:59.429365 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11014 20:13:59.470605 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11015 20:13:59.517900 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11016 20:13:59.538194 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11017 20:13:59.552014 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11018 20:13:59.569662 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11019 20:13:59.621825 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11020 20:13:59.646528 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11021 20:13:59.672429 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11022 20:13:59.726403 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11023 20:13:59.746189 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11024 20:13:59.773462 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11025 20:13:59.809778
11026 20:13:59.810480
11027 20:13:59.813149 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11028 20:13:59.813608
11029 20:13:59.816597 debian-bookworm-arm64 login: root (automatic login)
11030 20:13:59.816985
11031 20:13:59.817289
11032 20:13:59.829827 Linux debian-bookworm-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
11033 20:13:59.830041
11034 20:13:59.836757 The programs included with the Debian GNU/Linux system are free software;
11035 20:13:59.843231 the exact distribution terms for each program are described in the
11036 20:13:59.846155 individual files in /usr/share/doc/*/copyright.
11037 20:13:59.846360
11038 20:13:59.853143 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11039 20:13:59.856914 permitted by applicable law.
11040 20:13:59.857653 Matched prompt #10: / #
11042 20:13:59.858193 Setting prompt string to ['/ #']
11043 20:13:59.858416 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11045 20:13:59.858887 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11046 20:13:59.859114 start: 2.2.6 expect-shell-connection (timeout 00:02:18) [common]
11047 20:13:59.859334 Setting prompt string to ['/ #']
11048 20:13:59.859544 Forcing a shell prompt, looking for ['/ #']
11050 20:13:59.910137 / #
11051 20:13:59.910432 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11052 20:13:59.910595 Waiting using forced prompt support (timeout 00:02:30)
11053 20:13:59.916549
11054 20:13:59.917071 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11055 20:13:59.917312 start: 2.2.7 export-device-env (timeout 00:02:18) [common]
11056 20:13:59.917510 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 20:13:59.917700 end: 2.2 depthcharge-retry (duration 00:02:42) [common]
11058 20:13:59.917870 end: 2 depthcharge-action (duration 00:02:42) [common]
11059 20:13:59.918104 start: 3 lava-test-retry (timeout 00:06:52) [common]
11060 20:13:59.918324 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
11061 20:13:59.918502 Using namespace: common
11063 20:14:00.019082 / # #
11064 20:14:00.019641 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11065 20:14:00.025909 #
11066 20:14:00.026630 Using /lava-12928116
11068 20:14:00.127815 / # export SHELL=/bin/sh
11069 20:14:00.128049 <6>[ 19.565730] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11070 20:14:00.133502 export SHELL=/bin/sh
11072 20:14:00.234395 / # . /lava-12928116/environment
11073 20:14:00.240653 . /lava-12928116/environment
11075 20:14:00.342034 / # /lava-12928116/bin/lava-test-runner /lava-12928116/0
11076 20:14:00.342349 Test shell timeout: 10s (minimum of the action and connection timeout)
11077 20:14:00.348050 /lava-12928116/bin/lava-test-runner /lava-12928116/0
11078 20:14:00.370962 + export TESTRUN_ID=0_igt-gpu-panfrost
11079 20:14:00.378298 + cd /lava-12928116/0/te<8>[ 19.862351] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12928116_1.5.2.3.1>
11080 20:14:00.379025 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12928116_1.5.2.3.1
11081 20:14:00.379412 Starting test lava.0_igt-gpu-panfrost (12928116_1.5.2.3.1)
11082 20:14:00.379858 Skipping test definition patterns.
11083 20:14:00.381381 sts/0_igt-gpu-panfrost
11084 20:14:00.381801 + cat uuid
11085 20:14:00.384105 + UUID=12928116_1.5.2.3.1
11086 20:14:00.384531 + set +x
11087 20:14:00.393983 + IGT_FORCE_DRIVER=panfrost /usr/bin/ig<8>[ 19.880735] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11088 20:14:00.394664 Received signal: <TESTSET> START panfrost_gem_new
11089 20:14:00.395054 Starting test_set panfrost_gem_new
11090 20:14:00.401316 t-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11091 20:14:00.416570 IGT-Version: 1.2<14>[ 19.905227] [IGT] panfrost_gem_new: executing
11092 20:14:00.426084 8-g0830aa7 (aarch64) (Linux: 6.1<14>[ 19.911561] [IGT] panfrost_gem_new: exiting, ret=77
11093 20:14:00.432804 <8>[ 19.917545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11094 20:14:00.433583 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11096 20:14:00.436222 .80-cip16-rt9 aarch64)
11097 20:14:00.439537 Using IGT_SRANDOM=1709496840 for randomisation
11098 20:14:00.446260 Test requirement not met<14>[ 19.932206] [IGT] panfrost_gem_new: executing
11099 20:14:00.452850 in function drm_open_driver, fi<14>[ 19.939611] [IGT] panfrost_gem_new: exiting, ret=77
11100 20:14:00.462754 le ../lib/drmtes<8>[ 19.944658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11101 20:14:00.463183 t.c:694:
11102 20:14:00.463797 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11104 20:14:00.465591 Test requirement: !(fd<0)
11105 20:14:00.469157 No known gpu found for chipset flags 0x32 (panfrost)
11106 20:14:00.472235 Last errno: 2, No such file or directory
11107 20:14:00.482083 [1mSubtest gem-new-4096: SKIP (0.000s)[0m<14>[ 19.965550] [IGT] panfrost_gem_new: executing
11108 20:14:00.482522
11109 20:14:00.488667 IGT-Version: 1<14>[ 19.969403] [IGT] panfrost_gem_new: exiting, ret=77
11110 20:14:00.492057 .28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11111 20:14:00.502393 Using IGT_SRANDOM=1709496840 for rando<8>[ 19.987563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11112 20:14:00.503191 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11114 20:14:00.505879 misation
11115 20:14:00.508661 Test r<8>[ 19.988976] <LAVA_SIGNAL_TESTSET STOP>
11116 20:14:00.509372 Received signal: <TESTSET> STOP
11117 20:14:00.509824 Closing test_set panfrost_gem_new
11118 20:14:00.515298 equirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11119 20:14:00.518680 Test requirement: !(fd<0)
11120 20:14:00.522173 No known gpu found for chipset flags 0x32 (panfrost)
11121 20:14:00.525044 Last errno: 2, No such file or directory
11122 20:14:00.535082 [1mSubtest gem-new-0: SK<8>[ 20.018391] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11123 20:14:00.535847 IP (0.000s)[0m
11124 20:14:00.536577 Received signal: <TESTSET> START panfrost_get_param
11125 20:14:00.536928 Starting test_set panfrost_get_param
11126 20:14:00.544692 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.<14>[ 20.033329] [IGT] panfrost_get_param: executing
11127 20:14:00.548702 1.80-cip16-rt9 aarch64)
11128 20:14:00.554953 Using IGT_SRANDOM=17094<14>[ 20.038752] [IGT] panfrost_get_param: exiting, ret=77
11129 20:14:00.561685 96840 for random<8>[ 20.043240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11130 20:14:00.562331 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11132 20:14:00.564562 isation
11133 20:14:00.568464 Test re<14>[ 20.056614] [IGT] panfrost_get_param: executing
11134 20:14:00.577840 quirement not met in function drm_open_driver, f<14>[ 20.062894] [IGT] panfrost_get_param: exiting, ret=77
11135 20:14:00.588243 ile ../lib/drmte<8>[ 20.067341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11136 20:14:00.588546 st.c:694:
11137 20:14:00.589009 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11139 20:14:00.590937 Test requirement: !(fd<0)
11140 20:14:00.594842 No known gpu found for chipset flags 0x32 (panfrost)
11141 20:14:00.597523 Last errno: 2, No such file or directory
11142 20:14:00.604566 [1mSubtest gem-new-zeroed<14>[ 20.093288] [IGT] panfrost_get_param: executing
11143 20:14:00.607887 : SKIP (0.000s)[0m
11144 20:14:00.618358 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-r<14>[ 20.102718] [IGT] panfrost_get_param: exiting, ret=77
11145 20:14:00.618659 t9 aarch64)
11146 20:14:00.627259 Usi<8>[ 20.108183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11147 20:14:00.627872 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11149 20:14:00.631101 ng IGT_SRANDOM=1<8>[ 20.109807] <LAVA_SIGNAL_TESTSET STOP>
11150 20:14:00.631625 Received signal: <TESTSET> STOP
11151 20:14:00.631896 Closing test_set panfrost_get_param
11152 20:14:00.634445 709496840 for randomisation
11153 20:14:00.641124 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11154 20:14:00.644182 Test requirement: !(fd<0)
11155 20:14:00.647584 No known gpu found for chipset flags 0x32 (panfrost)
11156 20:14:00.654457 <8>[ 20.138619] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11157 20:14:00.655438 Received signal: <TESTSET> START panfrost_prime
11158 20:14:00.655865 Starting test_set panfrost_prime
11159 20:14:00.657675 Last errno: 2, No such file or directory
11160 20:14:00.663790 [1mSubtest base-params: SKIP (0.000s)<14>[ 20.152748] [IGT] panfrost_prime: executing
11161 20:14:00.667460 [0m
11162 20:14:00.674096 IGT-Version: 1.28-g0830aa7<14>[ 20.159517] [IGT] panfrost_prime: exiting, ret=77
11163 20:14:00.680309 (aarch64) (Linu<8>[ 20.163929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11164 20:14:00.680973 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11166 20:14:00.687022 x: 6.1.80-cip16-<8>[ 20.165334] <LAVA_SIGNAL_TESTSET STOP>
11167 20:14:00.687426 rt9 aarch64)
11168 20:14:00.688151 Received signal: <TESTSET> STOP
11169 20:14:00.688491 Closing test_set panfrost_prime
11170 20:14:00.693354 Using IGT_SRANDOM=1709496840 for randomisation
11171 20:14:00.697722 Te<8>[ 20.182452] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11172 20:14:00.698497 Received signal: <TESTSET> START panfrost_submit
11173 20:14:00.698857 Starting test_set panfrost_submit
11174 20:14:00.710320 st requirement not met in function drm_open_driver, file ../lib/<14>[ 20.195336] [IGT] panfrost_submit: executing
11175 20:14:00.710724 drmtest.c:694:
11176 20:14:00.716962 <14>[ 20.197287] [IGT] panfrost_submit: exiting, ret=77
11177 20:14:00.723115 Test requirement<8>[ 20.201831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11178 20:14:00.723516 : !(fd<0)
11179 20:14:00.724214 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11181 20:14:00.730313 No kn<14>[ 20.217360] [IGT] panfrost_submit: executing
11182 20:14:00.736425 own gpu found for chipset flags <14>[ 20.225319] [IGT] panfrost_submit: exiting, ret=77
11183 20:14:00.740308 0x32 (panfrost)
11184 20:14:00.746080 <8>[ 20.229967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11185 20:14:00.746682
11186 20:14:00.747311 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11188 20:14:00.749790 Last errno: 2, No such file or directory
11189 20:14:00.756114 [1mSubtest get-bad-p<14>[ 20.242630] [IGT] panfrost_submit: executing
11190 20:14:00.763082 aram: SKIP (0.00<14>[ 20.244718] [IGT] panfrost_submit: exiting, ret=77
11191 20:14:00.763556 0s)[0m
11192 20:14:00.772751 IGT-Ver<8>[ 20.249663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11193 20:14:00.773400 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11195 20:14:00.779537 sion: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11196 20:14:00.786247 Using IGT_SRAND<14>[ 20.271543] [IGT] panfrost_submit: executing
11197 20:14:00.786644 OM=1709496840 for randomisation
11198 20:14:00.792308 Test requiremen<14>[ 20.278588] [IGT] panfrost_submit: exiting, ret=77
11199 20:14:00.802753 t not met in fun<8>[ 20.284010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11200 20:14:00.803549 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11202 20:14:00.812221 ction drm_open_driver, file ../lib/drmtest.c:694<14>[ 20.299070] [IGT] panfrost_submit: executing
11203 20:14:00.812624 :
11204 20:14:00.819400 Test requirem<14>[ 20.301422] [IGT] panfrost_submit: exiting, ret=77
11205 20:14:00.819984 ent: !(fd<0)
11206 20:14:00.825330 No known gpu found for chipset flags 0x32 (panfrost)
11207 20:14:00.829644 Last errno: 2, No such file or directory
11208 20:14:00.838972 [<8>[ 20.317415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11209 20:14:00.839762 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11211 20:14:00.842034 1mSubtest get-bad-padding: SKIP (0.000s)[0m
11212 20:14:00.849353 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11213 20:14:00.851622 Using IGT_<14>[ 20.339370] [IGT] panfrost_submit: executing
11214 20:14:00.862184 SRANDOM=1709496840 for randomisa<14>[ 20.347570] [IGT] panfrost_submit: exiting, ret=77
11215 20:14:00.862569 tion
11216 20:14:00.871450 Test requi<8>[ 20.353253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11217 20:14:00.872089 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11219 20:14:00.881488 rement not met in function drm_open_driver, file ../lib/drmtest.<14>[ 20.367865] [IGT] panfrost_submit: executing
11220 20:14:00.881856 c:694:
11221 20:14:00.888747 Test requirement: !(fd<0<14>[ 20.375305] [IGT] panfrost_submit: exiting, ret=77
11222 20:14:00.889110 )
11223 20:14:00.898313 No known gpu <8>[ 20.379888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11224 20:14:00.898833 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11226 20:14:00.905218 found for chipset flags 0x32 (pa<14>[ 20.393139] [IGT] panfrost_submit: executing
11227 20:14:00.905493 nfrost)
11228 20:14:00.914417 Last errno: 2, No such file or director<14>[ 20.398709] [IGT] panfrost_submit: exiting, ret=77
11229 20:14:00.914694 y
11230 20:14:00.921692 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11232 20:14:00.924887 [1mSubtest g<8>[ 20.403831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11233 20:14:00.927810 em-prime-import:<14>[ 20.417066] [IGT] panfrost_submit: executing
11234 20:14:00.930650 SKIP (0.000s)[0m
11235 20:14:00.937476 IGT-Version:<14>[ 20.423075] [IGT] panfrost_submit: exiting, ret=77
11236 20:14:00.947792 1.28-g0830aa7 (<8>[ 20.427615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11237 20:14:00.948372 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11239 20:14:00.951252 aarch64) (Linux:<8>[ 20.428862] <LAVA_SIGNAL_TESTSET STOP>
11240 20:14:00.951843 Received signal: <TESTSET> STOP
11241 20:14:00.952078 Closing test_set panfrost_submit
11242 20:14:00.954753 6.1.80-cip16-rt9 aarch64)
11243 20:14:00.961486 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12928116_1.5.2.3.1
11244 20:14:00.961802 Ending use of test pattern.
11245 20:14:00.962017 Ending test lava.0_igt-gpu-panfrost (12928116_1.5.2.3.1), duration 0.58
11247 20:14:00.963572 Using IGT_SRANDOM=17<8>[ 20.445677] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12928116_1.5.2.3.1>
11248 20:14:00.963874 09496840 for randomisation
11249 20:14:00.970385 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11250 20:14:00.974767 Test requirement: !(fd<0)
11251 20:14:00.980700 No known gpu found for chipset flags 0x32 (panfrost)
11252 20:14:00.984851 Last errno: 2, No such file or directory
11253 20:14:00.986761 [1mSubtest pan-submit: SKIP (0.000s)[0m
11254 20:14:00.993828 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11255 20:14:00.996857 Using IGT_SRANDOM=1709496840 for randomisation
11256 20:14:01.003513 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11257 20:14:01.006779 Test requirement: !(fd<0)
11258 20:14:01.009910 No known gpu found for chipset flags 0x32 (panfrost)
11259 20:14:01.013685 Last errno: 2, No such file or directory
11260 20:14:01.019938 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11261 20:14:01.026703 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11262 20:14:01.029634 Using IGT_SRANDOM=1709496840 for randomisation
11263 20:14:01.036624 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11264 20:14:01.040211 Test requirement: !(fd<0)
11265 20:14:01.043205 No known gpu found for chipset flags 0x32 (panfrost)
11266 20:14:01.046244 Last errno: 2, No such file or directory
11267 20:14:01.053563 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11268 20:14:01.060081 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11269 20:14:01.062636 Using IGT_SRANDOM=1709496840 for randomisation
11270 20:14:01.069594 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11271 20:14:01.073226 Test requirement: !(fd<0)
11272 20:14:01.076386 No known gpu found for chipset flags 0x32 (panfrost)
11273 20:14:01.083360 Last errno: 2, No such file or directory
11274 20:14:01.085805 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11275 20:14:01.092993 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11276 20:14:01.096361 Using IGT_SRANDOM=1709496840 for randomisation
11277 20:14:01.105555 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11278 20:14:01.105915 Test requirement: !(fd<0)
11279 20:14:01.112479 No known gpu found for chipset flags 0x32 (panfrost)
11280 20:14:01.115550 Last errno: 2, No such file or directory
11281 20:14:01.119299 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11282 20:14:01.125400 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11283 20:14:01.132352 Using IGT_SRANDOM=1709496840 for randomisation
11284 20:14:01.138855 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11285 20:14:01.142126 Test requirement: !(fd<0)
11286 20:14:01.146155 No known gpu found for chipset flags 0x32 (panfrost)
11287 20:14:01.148686 Last errno: 2, No such file or directory
11288 20:14:01.155413 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11289 20:14:01.162612 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11290 20:14:01.165515 Using IGT_SRANDOM=1709496840 for randomisation
11291 20:14:01.171462 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11292 20:14:01.176051 Test requirement: !(fd<0)
11293 20:14:01.179142 No known gpu found for chipset flags 0x32 (panfrost)
11294 20:14:01.182136 Last errno: 2, No such file or directory
11295 20:14:01.185126 [1mSubtest pan-reset: SKIP (0.000s)[0m
11296 20:14:01.192195 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11297 20:14:01.194809 Using IGT_SRANDOM=1709496840 for randomisation
11298 20:14:01.204983 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11299 20:14:01.205263 Test requirement: !(fd<0)
11300 20:14:01.211376 No known gpu found for chipset flags 0x32 (panfrost)
11301 20:14:01.214908 Last errno: 2, No such file or directory
11302 20:14:01.218242 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11303 20:14:01.224235 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16-rt9 aarch64)
11304 20:14:01.227626 Using IGT_SRANDOM=1709496840 for randomisation
11305 20:14:01.238176 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11306 20:14:01.238567 Test requirement: !(fd<0)
11307 20:14:01.244185 No known gpu found for chipset flags 0x32 (panfrost)
11308 20:14:01.247645 Last errno: 2, No such file or directory
11309 20:14:01.251237 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11310 20:14:01.254173 + set +x
11311 20:14:01.254568 <LAVA_TEST_RUNNER EXIT>
11312 20:14:01.255076 ok: lava_test_shell seems to have completed
11313 20:14:01.256108 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11314 20:14:01.256581 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11315 20:14:01.256876 end: 3 lava-test-retry (duration 00:00:01) [common]
11316 20:14:01.257172 start: 4 finalize (timeout 00:06:51) [common]
11317 20:14:01.257476 start: 4.1 power-off (timeout 00:00:30) [common]
11318 20:14:01.257961 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11319 20:14:01.372568 >> Command sent successfully.
11320 20:14:01.382598 Returned 0 in 0 seconds
11321 20:14:01.483747 end: 4.1 power-off (duration 00:00:00) [common]
11323 20:14:01.485159 start: 4.2 read-feedback (timeout 00:06:50) [common]
11324 20:14:01.486390 Listened to connection for namespace 'common' for up to 1s
11325 20:14:02.487024 Finalising connection for namespace 'common'
11326 20:14:02.487792 Disconnecting from shell: Finalise
11327 20:14:02.488190 / #
11328 20:14:02.589027 end: 4.2 read-feedback (duration 00:00:01) [common]
11329 20:14:02.589645 end: 4 finalize (duration 00:00:01) [common]
11330 20:14:02.590060 Cleaning after the job
11331 20:14:02.590395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/ramdisk
11332 20:14:02.615190 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/kernel
11333 20:14:02.629919 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/dtb
11334 20:14:02.630168 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928116/tftp-deploy-6ddh4bb_/modules
11335 20:14:02.639105 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928116
11336 20:14:02.769627 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928116
11337 20:14:02.769802 Job finished correctly