Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 13
1 20:13:39.478389 lava-dispatcher, installed at version: 2024.01
2 20:13:39.478600 start: 0 validate
3 20:13:39.478731 Start time: 2024-03-03 20:13:39.478723+00:00 (UTC)
4 20:13:39.478862 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:13:39.478991 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240221.0%2Farm64%2Finitrd.cpio.gz exists
6 20:13:39.746885 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:13:39.747056 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:13:40.018925 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:13:40.019091 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:13:40.284819 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:13:40.284995 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240221.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:13:40.542907 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:13:40.543097 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:13:40.810907 validate duration: 1.33
16 20:13:40.811172 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:13:40.811267 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:13:40.811352 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:13:40.811479 Not decompressing ramdisk as can be used compressed.
20 20:13:40.811565 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240221.0/arm64/initrd.cpio.gz
21 20:13:40.811629 saving as /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/ramdisk/initrd.cpio.gz
22 20:13:40.811696 total size: 5628149 (5 MB)
23 20:13:40.812825 progress 0 % (0 MB)
24 20:13:40.814526 progress 5 % (0 MB)
25 20:13:40.816139 progress 10 % (0 MB)
26 20:13:40.817665 progress 15 % (0 MB)
27 20:13:40.819270 progress 20 % (1 MB)
28 20:13:40.820725 progress 25 % (1 MB)
29 20:13:40.822314 progress 30 % (1 MB)
30 20:13:40.823877 progress 35 % (1 MB)
31 20:13:40.825313 progress 40 % (2 MB)
32 20:13:40.826904 progress 45 % (2 MB)
33 20:13:40.828346 progress 50 % (2 MB)
34 20:13:40.829950 progress 55 % (2 MB)
35 20:13:40.831505 progress 60 % (3 MB)
36 20:13:40.832954 progress 65 % (3 MB)
37 20:13:40.834535 progress 70 % (3 MB)
38 20:13:40.835940 progress 75 % (4 MB)
39 20:13:40.837550 progress 80 % (4 MB)
40 20:13:40.838948 progress 85 % (4 MB)
41 20:13:40.840543 progress 90 % (4 MB)
42 20:13:40.842164 progress 95 % (5 MB)
43 20:13:40.843625 progress 100 % (5 MB)
44 20:13:40.843837 5 MB downloaded in 0.03 s (166.99 MB/s)
45 20:13:40.843993 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:13:40.844235 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:13:40.844322 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:13:40.844407 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:13:40.844540 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:13:40.844609 saving as /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/kernel/Image
52 20:13:40.844670 total size: 51601920 (49 MB)
53 20:13:40.844780 No compression specified
54 20:13:40.845891 progress 0 % (0 MB)
55 20:13:40.859287 progress 5 % (2 MB)
56 20:13:40.872811 progress 10 % (4 MB)
57 20:13:40.886294 progress 15 % (7 MB)
58 20:13:40.899433 progress 20 % (9 MB)
59 20:13:40.912886 progress 25 % (12 MB)
60 20:13:40.926387 progress 30 % (14 MB)
61 20:13:40.939936 progress 35 % (17 MB)
62 20:13:40.953358 progress 40 % (19 MB)
63 20:13:40.966925 progress 45 % (22 MB)
64 20:13:40.980383 progress 50 % (24 MB)
65 20:13:40.993859 progress 55 % (27 MB)
66 20:13:41.007044 progress 60 % (29 MB)
67 20:13:41.020490 progress 65 % (32 MB)
68 20:13:41.034136 progress 70 % (34 MB)
69 20:13:41.047607 progress 75 % (36 MB)
70 20:13:41.061046 progress 80 % (39 MB)
71 20:13:41.074498 progress 85 % (41 MB)
72 20:13:41.087976 progress 90 % (44 MB)
73 20:13:41.101422 progress 95 % (46 MB)
74 20:13:41.114405 progress 100 % (49 MB)
75 20:13:41.114635 49 MB downloaded in 0.27 s (182.29 MB/s)
76 20:13:41.114788 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:13:41.115025 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:13:41.115114 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:13:41.115201 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:13:41.115341 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:13:41.115420 saving as /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/dtb/mt8192-asurada-spherion-r0.dtb
83 20:13:41.115482 total size: 47278 (0 MB)
84 20:13:41.115544 No compression specified
85 20:13:41.116698 progress 69 % (0 MB)
86 20:13:41.116998 progress 100 % (0 MB)
87 20:13:41.117155 0 MB downloaded in 0.00 s (26.99 MB/s)
88 20:13:41.117277 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:13:41.117498 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:13:41.117582 start: 1.4 download-retry (timeout 00:10:00) [common]
92 20:13:41.117664 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 20:13:41.117776 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240221.0/arm64/full.rootfs.tar.xz
94 20:13:41.117847 saving as /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/nfsrootfs/full.rootfs.tar
95 20:13:41.117909 total size: 120336284 (114 MB)
96 20:13:41.117970 Using unxz to decompress xz
97 20:13:41.122209 progress 0 % (0 MB)
98 20:13:41.464219 progress 5 % (5 MB)
99 20:13:41.790183 progress 10 % (11 MB)
100 20:13:42.079980 progress 15 % (17 MB)
101 20:13:42.436606 progress 20 % (22 MB)
102 20:13:42.772055 progress 25 % (28 MB)
103 20:13:42.927876 progress 30 % (34 MB)
104 20:13:43.096830 progress 35 % (40 MB)
105 20:13:43.407916 progress 40 % (45 MB)
106 20:13:43.778178 progress 45 % (51 MB)
107 20:13:44.120837 progress 50 % (57 MB)
108 20:13:44.453774 progress 55 % (63 MB)
109 20:13:44.797072 progress 60 % (68 MB)
110 20:13:45.134917 progress 65 % (74 MB)
111 20:13:45.469867 progress 70 % (80 MB)
112 20:13:45.831421 progress 75 % (86 MB)
113 20:13:46.213537 progress 80 % (91 MB)
114 20:13:46.554932 progress 85 % (97 MB)
115 20:13:46.894417 progress 90 % (103 MB)
116 20:13:47.219663 progress 95 % (109 MB)
117 20:13:47.575088 progress 100 % (114 MB)
118 20:13:47.580383 114 MB downloaded in 6.46 s (17.76 MB/s)
119 20:13:47.580646 end: 1.4.1 http-download (duration 00:00:06) [common]
121 20:13:47.580945 end: 1.4 download-retry (duration 00:00:06) [common]
122 20:13:47.581036 start: 1.5 download-retry (timeout 00:09:53) [common]
123 20:13:47.581124 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 20:13:47.581278 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:13:47.581350 saving as /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/modules/modules.tar
126 20:13:47.581410 total size: 8632284 (8 MB)
127 20:13:47.581475 Using unxz to decompress xz
128 20:13:47.586037 progress 0 % (0 MB)
129 20:13:47.605982 progress 5 % (0 MB)
130 20:13:47.629888 progress 10 % (0 MB)
131 20:13:47.653897 progress 15 % (1 MB)
132 20:13:47.676259 progress 20 % (1 MB)
133 20:13:47.700306 progress 25 % (2 MB)
134 20:13:47.726060 progress 30 % (2 MB)
135 20:13:47.752344 progress 35 % (2 MB)
136 20:13:47.777382 progress 40 % (3 MB)
137 20:13:47.801281 progress 45 % (3 MB)
138 20:13:47.825802 progress 50 % (4 MB)
139 20:13:47.850450 progress 55 % (4 MB)
140 20:13:47.875559 progress 60 % (4 MB)
141 20:13:47.899743 progress 65 % (5 MB)
142 20:13:47.924975 progress 70 % (5 MB)
143 20:13:47.950037 progress 75 % (6 MB)
144 20:13:47.976427 progress 80 % (6 MB)
145 20:13:48.000941 progress 85 % (7 MB)
146 20:13:48.027248 progress 90 % (7 MB)
147 20:13:48.056480 progress 95 % (7 MB)
148 20:13:48.084780 progress 100 % (8 MB)
149 20:13:48.090102 8 MB downloaded in 0.51 s (16.18 MB/s)
150 20:13:48.090347 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:13:48.090615 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:13:48.090707 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 20:13:48.090807 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 20:13:51.636941 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x
156 20:13:51.637162 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 20:13:51.637308 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 20:13:51.637543 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a
159 20:13:51.637731 makedir: /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin
160 20:13:51.637878 makedir: /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/tests
161 20:13:51.638018 makedir: /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/results
162 20:13:51.638167 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-add-keys
163 20:13:51.638374 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-add-sources
164 20:13:51.638571 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-background-process-start
165 20:13:51.638747 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-background-process-stop
166 20:13:51.638882 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-common-functions
167 20:13:51.639012 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-echo-ipv4
168 20:13:51.639142 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-install-packages
169 20:13:51.639270 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-installed-packages
170 20:13:51.639397 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-os-build
171 20:13:51.639525 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-probe-channel
172 20:13:51.639653 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-probe-ip
173 20:13:51.639783 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-target-ip
174 20:13:51.639910 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-target-mac
175 20:13:51.640035 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-target-storage
176 20:13:51.640164 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-case
177 20:13:51.640293 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-event
178 20:13:51.640548 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-feedback
179 20:13:51.641230 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-raise
180 20:13:51.641371 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-reference
181 20:13:51.641505 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-runner
182 20:13:51.641633 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-set
183 20:13:51.641818 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-test-shell
184 20:13:51.641951 Updating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-add-keys (debian)
185 20:13:51.642107 Updating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-add-sources (debian)
186 20:13:51.642254 Updating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-install-packages (debian)
187 20:13:51.642396 Updating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-installed-packages (debian)
188 20:13:51.642536 Updating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/bin/lava-os-build (debian)
189 20:13:51.642658 Creating /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/environment
190 20:13:51.642754 LAVA metadata
191 20:13:51.642826 - LAVA_JOB_ID=12928117
192 20:13:51.642890 - LAVA_DISPATCHER_IP=192.168.201.1
193 20:13:51.642993 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 20:13:51.643059 skipped lava-vland-overlay
195 20:13:51.643133 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 20:13:51.643224 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 20:13:51.643285 skipped lava-multinode-overlay
198 20:13:51.643356 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 20:13:51.643436 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 20:13:51.643509 Loading test definitions
201 20:13:51.643596 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 20:13:51.643668 Using /lava-12928117 at stage 0
203 20:13:51.643951 uuid=12928117_1.6.2.3.1 testdef=None
204 20:13:51.644039 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 20:13:51.644124 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 20:13:51.644580 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 20:13:51.644839 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 20:13:51.645400 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 20:13:51.645629 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 20:13:51.646166 runner path: /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/0/tests/0_timesync-off test_uuid 12928117_1.6.2.3.1
213 20:13:51.646325 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 20:13:51.646727 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 20:13:51.646845 Using /lava-12928117 at stage 0
217 20:13:51.646985 Fetching tests from https://github.com/kernelci/test-definitions.git
218 20:13:51.647075 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/0/tests/1_kselftest-alsa'
219 20:13:54.134338 Running '/usr/bin/git checkout kernelci.org
220 20:13:54.232353 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 20:13:54.233315 uuid=12928117_1.6.2.3.5 testdef=None
222 20:13:54.233510 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 20:13:54.233883 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 20:13:54.235127 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 20:13:54.235496 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 20:13:54.236779 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 20:13:54.237135 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 20:13:54.238739 runner path: /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/0/tests/1_kselftest-alsa test_uuid 12928117_1.6.2.3.5
232 20:13:54.238861 BOARD='mt8192-asurada-spherion-r0'
233 20:13:54.238956 BRANCH='cip-gitlab'
234 20:13:54.239043 SKIPFILE='/dev/null'
235 20:13:54.239131 SKIP_INSTALL='True'
236 20:13:54.239216 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 20:13:54.239301 TST_CASENAME=''
238 20:13:54.239383 TST_CMDFILES='alsa'
239 20:13:54.239531 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 20:13:54.239743 Creating lava-test-runner.conf files
242 20:13:54.239839 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928117/lava-overlay-sp90bi5a/lava-12928117/0 for stage 0
243 20:13:54.239972 - 0_timesync-off
244 20:13:54.240079 - 1_kselftest-alsa
245 20:13:54.240217 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 20:13:54.240342 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 20:14:01.740987 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 20:14:01.741510 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 20:14:01.741625 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 20:14:01.741746 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 20:14:01.741854 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 20:14:01.915676 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 20:14:01.916082 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 20:14:01.916218 extracting modules file /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x
255 20:14:02.139839 extracting modules file /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928117/extract-overlay-ramdisk-dn8f0ff2/ramdisk
256 20:14:02.369589 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 20:14:02.369770 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 20:14:02.369886 [common] Applying overlay to NFS
259 20:14:02.369971 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928117/compress-overlay-xjw5mli0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x
260 20:14:03.297045 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 20:14:03.297216 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 20:14:03.297319 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 20:14:03.297410 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 20:14:03.297490 Building ramdisk /var/lib/lava/dispatcher/tmp/12928117/extract-overlay-ramdisk-dn8f0ff2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928117/extract-overlay-ramdisk-dn8f0ff2/ramdisk
265 20:14:03.670677 >> 130580 blocks
266 20:14:05.686655 rename /var/lib/lava/dispatcher/tmp/12928117/extract-overlay-ramdisk-dn8f0ff2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/ramdisk/ramdisk.cpio.gz
267 20:14:05.687124 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 20:14:05.687244 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 20:14:05.687349 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 20:14:05.687454 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/kernel/Image'
271 20:14:18.177276 Returned 0 in 12 seconds
272 20:14:18.278283 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/kernel/image.itb
273 20:14:18.667209 output: FIT description: Kernel Image image with one or more FDT blobs
274 20:14:18.667585 output: Created: Sun Mar 3 20:14:18 2024
275 20:14:18.667661 output: Image 0 (kernel-1)
276 20:14:18.667729 output: Description:
277 20:14:18.667793 output: Created: Sun Mar 3 20:14:18 2024
278 20:14:18.667858 output: Type: Kernel Image
279 20:14:18.667922 output: Compression: lzma compressed
280 20:14:18.667984 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
281 20:14:18.668044 output: Architecture: AArch64
282 20:14:18.668106 output: OS: Linux
283 20:14:18.668165 output: Load Address: 0x00000000
284 20:14:18.668219 output: Entry Point: 0x00000000
285 20:14:18.668276 output: Hash algo: crc32
286 20:14:18.668330 output: Hash value: 91cb1a17
287 20:14:18.668383 output: Image 1 (fdt-1)
288 20:14:18.668438 output: Description: mt8192-asurada-spherion-r0
289 20:14:18.668493 output: Created: Sun Mar 3 20:14:18 2024
290 20:14:18.668547 output: Type: Flat Device Tree
291 20:14:18.668600 output: Compression: uncompressed
292 20:14:18.668653 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 20:14:18.668713 output: Architecture: AArch64
294 20:14:18.668805 output: Hash algo: crc32
295 20:14:18.668858 output: Hash value: cc4352de
296 20:14:18.668911 output: Image 2 (ramdisk-1)
297 20:14:18.668963 output: Description: unavailable
298 20:14:18.669016 output: Created: Sun Mar 3 20:14:18 2024
299 20:14:18.669069 output: Type: RAMDisk Image
300 20:14:18.669121 output: Compression: Unknown Compression
301 20:14:18.669174 output: Data Size: 18766798 Bytes = 18326.95 KiB = 17.90 MiB
302 20:14:18.669226 output: Architecture: AArch64
303 20:14:18.669279 output: OS: Linux
304 20:14:18.669331 output: Load Address: unavailable
305 20:14:18.669383 output: Entry Point: unavailable
306 20:14:18.669436 output: Hash algo: crc32
307 20:14:18.669488 output: Hash value: e4a07eff
308 20:14:18.669541 output: Default Configuration: 'conf-1'
309 20:14:18.669594 output: Configuration 0 (conf-1)
310 20:14:18.669646 output: Description: mt8192-asurada-spherion-r0
311 20:14:18.669698 output: Kernel: kernel-1
312 20:14:18.669751 output: Init Ramdisk: ramdisk-1
313 20:14:18.669803 output: FDT: fdt-1
314 20:14:18.669855 output: Loadables: kernel-1
315 20:14:18.669907 output:
316 20:14:18.670116 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 20:14:18.670218 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 20:14:18.670322 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 20:14:18.670418 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 20:14:18.670502 No LXC device requested
321 20:14:18.670582 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 20:14:18.670668 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 20:14:18.670748 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 20:14:18.670821 Checking files for TFTP limit of 4294967296 bytes.
325 20:14:18.671326 end: 1 tftp-deploy (duration 00:00:38) [common]
326 20:14:18.671435 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 20:14:18.671528 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 20:14:18.671662 substitutions:
329 20:14:18.671732 - {DTB}: 12928117/tftp-deploy-_x39tgoc/dtb/mt8192-asurada-spherion-r0.dtb
330 20:14:18.671797 - {INITRD}: 12928117/tftp-deploy-_x39tgoc/ramdisk/ramdisk.cpio.gz
331 20:14:18.671857 - {KERNEL}: 12928117/tftp-deploy-_x39tgoc/kernel/Image
332 20:14:18.671915 - {LAVA_MAC}: None
333 20:14:18.671972 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x
334 20:14:18.672027 - {NFS_SERVER_IP}: 192.168.201.1
335 20:14:18.672082 - {PRESEED_CONFIG}: None
336 20:14:18.672135 - {PRESEED_LOCAL}: None
337 20:14:18.672189 - {RAMDISK}: 12928117/tftp-deploy-_x39tgoc/ramdisk/ramdisk.cpio.gz
338 20:14:18.672242 - {ROOT_PART}: None
339 20:14:18.672296 - {ROOT}: None
340 20:14:18.672349 - {SERVER_IP}: 192.168.201.1
341 20:14:18.672402 - {TEE}: None
342 20:14:18.672455 Parsed boot commands:
343 20:14:18.672508 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 20:14:18.672692 Parsed boot commands: tftpboot 192.168.201.1 12928117/tftp-deploy-_x39tgoc/kernel/image.itb 12928117/tftp-deploy-_x39tgoc/kernel/cmdline
345 20:14:18.672828 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 20:14:18.672911 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 20:14:18.673003 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 20:14:18.673092 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 20:14:18.673169 Not connected, no need to disconnect.
350 20:14:18.673242 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 20:14:18.673320 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 20:14:18.673388 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 20:14:18.677586 Setting prompt string to ['lava-test: # ']
354 20:14:18.677953 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 20:14:18.678065 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 20:14:18.678163 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 20:14:18.678262 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 20:14:18.678469 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 20:14:23.832370 >> Command sent successfully.
360 20:14:23.842941 Returned 0 in 5 seconds
361 20:14:23.943951 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 20:14:23.944414 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 20:14:23.944624 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 20:14:23.944820 Setting prompt string to 'Starting depthcharge on Spherion...'
366 20:14:23.944925 Changing prompt to 'Starting depthcharge on Spherion...'
367 20:14:23.945023 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 20:14:23.945420 [Enter `^Ec?' for help]
369 20:14:24.117613
370 20:14:24.118475
371 20:14:24.118987 F0: 102B 0000
372 20:14:24.119487
373 20:14:24.119964 F3: 1001 0000 [0200]
374 20:14:24.120416
375 20:14:24.121279 F3: 1001 0000
376 20:14:24.121691
377 20:14:24.122148 F7: 102D 0000
378 20:14:24.122595
379 20:14:24.124245 F1: 0000 0000
380 20:14:24.124773
381 20:14:24.125269 V0: 0000 0000 [0001]
382 20:14:24.125846
383 20:14:24.126309 00: 0007 8000
384 20:14:24.126778
385 20:14:24.127794 01: 0000 0000
386 20:14:24.128371
387 20:14:24.128944 BP: 0C00 0209 [0000]
388 20:14:24.129399
389 20:14:24.131730 G0: 1182 0000
390 20:14:24.132227
391 20:14:24.132799 EC: 0000 0021 [4000]
392 20:14:24.133235
393 20:14:24.134880 S7: 0000 0000 [0000]
394 20:14:24.135325
395 20:14:24.135775 CC: 0000 0000 [0001]
396 20:14:24.136199
397 20:14:24.138568 T0: 0000 0040 [010F]
398 20:14:24.139017
399 20:14:24.139487 Jump to BL
400 20:14:24.140005
401 20:14:24.165002
402 20:14:24.165588
403 20:14:24.166090
404 20:14:24.170640 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 20:14:24.174762 ARM64: Exception handlers installed.
406 20:14:24.178491 ARM64: Testing exception
407 20:14:24.181075 ARM64: Done test exception
408 20:14:24.188039 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 20:14:24.198473 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 20:14:24.205082 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 20:14:24.215392 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 20:14:24.221921 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 20:14:24.231926 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 20:14:24.243261 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 20:14:24.249444 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 20:14:24.267328 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 20:14:24.270973 WDT: Last reset was cold boot
418 20:14:24.273545 SPI1(PAD0) initialized at 2873684 Hz
419 20:14:24.277027 SPI5(PAD0) initialized at 992727 Hz
420 20:14:24.280787 VBOOT: Loading verstage.
421 20:14:24.286834 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:14:24.290463 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:14:24.293865 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:14:24.297225 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:14:24.305752 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:14:24.311493 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:14:24.321807 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 20:14:24.322456
429 20:14:24.322953
430 20:14:24.332556 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:14:24.336039 ARM64: Exception handlers installed.
432 20:14:24.338770 ARM64: Testing exception
433 20:14:24.339354 ARM64: Done test exception
434 20:14:24.345492 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:14:24.349244 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:14:24.363105 Probing TPM: . done!
437 20:14:24.363693 TPM ready after 0 ms
438 20:14:24.369666 Connected to device vid:did:rid of 1ae0:0028:00
439 20:14:24.376626 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 20:14:24.379880 Initialized TPM device CR50 revision 0
441 20:14:24.430839 tlcl_send_startup: Startup return code is 0
442 20:14:24.431425 TPM: setup succeeded
443 20:14:24.443246 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:14:24.451575 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:14:24.461106 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:14:24.470267 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:14:24.473710 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:14:24.477181 in-header: 03 07 00 00 08 00 00 00
449 20:14:24.480426 in-data: aa e4 47 04 13 02 00 00
450 20:14:24.484367 Chrome EC: UHEPI supported
451 20:14:24.490188 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:14:24.493912 in-header: 03 9d 00 00 08 00 00 00
453 20:14:24.496917 in-data: 10 20 20 08 00 00 00 00
454 20:14:24.497727 Phase 1
455 20:14:24.503534 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:14:24.509955 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:14:24.513714 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:14:24.517272 Recovery requested (1009000e)
459 20:14:24.521108 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:14:24.530263 tlcl_extend: response is 0
461 20:14:24.538243 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:14:24.543696 tlcl_extend: response is 0
463 20:14:24.550399 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:14:24.570674 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
465 20:14:24.577722 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 20:14:24.578313
467 20:14:24.578693
468 20:14:24.587548 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:14:24.592557 ARM64: Exception handlers installed.
470 20:14:24.594791 ARM64: Testing exception
471 20:14:24.595371 ARM64: Done test exception
472 20:14:24.613804 pmic_efuse_setting: Set efuses in 11 msecs
473 20:14:24.621405 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:14:24.625054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:14:24.632034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:14:24.636287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:14:24.639466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:14:24.646366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:14:24.649501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:14:24.653270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:14:24.660549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:14:24.664362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:14:24.669803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:14:24.673284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:14:24.677435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:14:24.683793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:14:24.690115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:14:24.693646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:14:24.700675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:14:24.706725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:14:24.709951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:14:24.717326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:14:24.723806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:14:24.727737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:14:24.733989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:14:24.740703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:14:24.744296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:14:24.751216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:14:24.757921 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:14:24.761358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:14:24.764800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:14:24.770641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:14:24.774143 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:14:24.780426 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:14:24.783806 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:14:24.790914 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:14:24.793856 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:14:24.800767 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:14:24.805196 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:14:24.811330 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:14:24.814004 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:14:24.820834 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:14:24.824260 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:14:24.827182 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:14:24.833897 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:14:24.837410 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:14:24.841019 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:14:24.848025 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:14:24.850931 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:14:24.854316 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:14:24.857053 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:14:24.863932 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:14:24.867349 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:14:24.870383 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:14:24.881349 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:14:24.887720 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:14:24.890448 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:14:24.900764 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:14:24.907942 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:14:24.913951 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:14:24.918131 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:14:24.920793 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:14:24.928906 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x5
534 20:14:24.936258 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:14:24.938754 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 20:14:24.945516 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:14:24.953464 [RTC]rtc_get_frequency_meter,154: input=15, output=763
538 20:14:24.962923 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 20:14:24.972451 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 20:14:24.982590 [RTC]rtc_get_frequency_meter,154: input=17, output=811
541 20:14:24.991966 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 20:14:25.000983 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 20:14:25.010254 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 20:14:25.013555 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 20:14:25.021458 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 20:14:25.024017 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 20:14:25.027851 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 20:14:25.034469 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 20:14:25.038656 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 20:14:25.040558 ADC[4]: Raw value=670800 ID=5
551 20:14:25.041113 ADC[3]: Raw value=212180 ID=1
552 20:14:25.044786 RAM Code: 0x51
553 20:14:25.047952 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 20:14:25.053728 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 20:14:25.060971 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 20:14:25.067851 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 20:14:25.070560 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 20:14:25.073751 in-header: 03 07 00 00 08 00 00 00
559 20:14:25.076957 in-data: aa e4 47 04 13 02 00 00
560 20:14:25.082520 Chrome EC: UHEPI supported
561 20:14:25.087503 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 20:14:25.091151 in-header: 03 d5 00 00 08 00 00 00
563 20:14:25.094610 in-data: 98 20 60 08 00 00 00 00
564 20:14:25.097667 MRC: failed to locate region type 0.
565 20:14:25.104641 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 20:14:25.105269 DRAM-K: Running full calibration
567 20:14:25.110408 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 20:14:25.113481 header.status = 0x0
569 20:14:25.117920 header.version = 0x6 (expected: 0x6)
570 20:14:25.120630 header.size = 0xd00 (expected: 0xd00)
571 20:14:25.121285 header.flags = 0x0
572 20:14:25.126878 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 20:14:25.146154 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
574 20:14:25.152102 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 20:14:25.155817 dram_init: ddr_geometry: 0
576 20:14:25.159008 [EMI] MDL number = 0
577 20:14:25.159580 [EMI] Get MDL freq = 0
578 20:14:25.162194 dram_init: ddr_type: 0
579 20:14:25.162667 is_discrete_lpddr4: 1
580 20:14:25.165732 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 20:14:25.166312
582 20:14:25.166686
583 20:14:25.169424 [Bian_co] ETT version 0.0.0.1
584 20:14:25.172807 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 20:14:25.173376
586 20:14:25.179571 dramc_set_vcore_voltage set vcore to 650000
587 20:14:25.180161 Read voltage for 800, 4
588 20:14:25.182677 Vio18 = 0
589 20:14:25.183172 Vcore = 650000
590 20:14:25.183559 Vdram = 0
591 20:14:25.186750 Vddq = 0
592 20:14:25.187230 Vmddr = 0
593 20:14:25.188936 dram_init: config_dvfs: 1
594 20:14:25.192890 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 20:14:25.199081 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 20:14:25.203058 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 20:14:25.206597 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 20:14:25.209229 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 20:14:25.213164 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 20:14:25.216901 MEM_TYPE=3, freq_sel=18
601 20:14:25.219339 sv_algorithm_assistance_LP4_1600
602 20:14:25.222169 ============ PULL DRAM RESETB DOWN ============
603 20:14:25.226075 ========== PULL DRAM RESETB DOWN end =========
604 20:14:25.232907 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 20:14:25.235888 ===================================
606 20:14:25.236480 LPDDR4 DRAM CONFIGURATION
607 20:14:25.239195 ===================================
608 20:14:25.242147 EX_ROW_EN[0] = 0x0
609 20:14:25.245769 EX_ROW_EN[1] = 0x0
610 20:14:25.246245 LP4Y_EN = 0x0
611 20:14:25.249068 WORK_FSP = 0x0
612 20:14:25.249643 WL = 0x2
613 20:14:25.252652 RL = 0x2
614 20:14:25.253284 BL = 0x2
615 20:14:25.256824 RPST = 0x0
616 20:14:25.257406 RD_PRE = 0x0
617 20:14:25.259834 WR_PRE = 0x1
618 20:14:25.260461 WR_PST = 0x0
619 20:14:25.262123 DBI_WR = 0x0
620 20:14:25.262618 DBI_RD = 0x0
621 20:14:25.266196 OTF = 0x1
622 20:14:25.269592 ===================================
623 20:14:25.273217 ===================================
624 20:14:25.273804 ANA top config
625 20:14:25.276420 ===================================
626 20:14:25.279109 DLL_ASYNC_EN = 0
627 20:14:25.281956 ALL_SLAVE_EN = 1
628 20:14:25.282428 NEW_RANK_MODE = 1
629 20:14:25.285717 DLL_IDLE_MODE = 1
630 20:14:25.288993 LP45_APHY_COMB_EN = 1
631 20:14:25.292120 TX_ODT_DIS = 1
632 20:14:25.295944 NEW_8X_MODE = 1
633 20:14:25.298635 ===================================
634 20:14:25.302202 ===================================
635 20:14:25.302709 data_rate = 1600
636 20:14:25.305452 CKR = 1
637 20:14:25.310420 DQ_P2S_RATIO = 8
638 20:14:25.312066 ===================================
639 20:14:25.315298 CA_P2S_RATIO = 8
640 20:14:25.318500 DQ_CA_OPEN = 0
641 20:14:25.321720 DQ_SEMI_OPEN = 0
642 20:14:25.322256 CA_SEMI_OPEN = 0
643 20:14:25.325195 CA_FULL_RATE = 0
644 20:14:25.328530 DQ_CKDIV4_EN = 1
645 20:14:25.331731 CA_CKDIV4_EN = 1
646 20:14:25.335583 CA_PREDIV_EN = 0
647 20:14:25.339611 PH8_DLY = 0
648 20:14:25.340230 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 20:14:25.341829 DQ_AAMCK_DIV = 4
650 20:14:25.345184 CA_AAMCK_DIV = 4
651 20:14:25.348539 CA_ADMCK_DIV = 4
652 20:14:25.351810 DQ_TRACK_CA_EN = 0
653 20:14:25.355912 CA_PICK = 800
654 20:14:25.356481 CA_MCKIO = 800
655 20:14:25.358647 MCKIO_SEMI = 0
656 20:14:25.362662 PLL_FREQ = 3068
657 20:14:25.365634 DQ_UI_PI_RATIO = 32
658 20:14:25.368893 CA_UI_PI_RATIO = 0
659 20:14:25.373100 ===================================
660 20:14:25.375740 ===================================
661 20:14:25.379064 memory_type:LPDDR4
662 20:14:25.379635 GP_NUM : 10
663 20:14:25.382311 SRAM_EN : 1
664 20:14:25.382884 MD32_EN : 0
665 20:14:25.385337 ===================================
666 20:14:25.388468 [ANA_INIT] >>>>>>>>>>>>>>
667 20:14:25.392470 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 20:14:25.395806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 20:14:25.398548 ===================================
670 20:14:25.401976 data_rate = 1600,PCW = 0X7600
671 20:14:25.405426 ===================================
672 20:14:25.408816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 20:14:25.415135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 20:14:25.418451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 20:14:25.425309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 20:14:25.428226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 20:14:25.431812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 20:14:25.432396 [ANA_INIT] flow start
679 20:14:25.436040 [ANA_INIT] PLL >>>>>>>>
680 20:14:25.439288 [ANA_INIT] PLL <<<<<<<<
681 20:14:25.439871 [ANA_INIT] MIDPI >>>>>>>>
682 20:14:25.441407 [ANA_INIT] MIDPI <<<<<<<<
683 20:14:25.444941 [ANA_INIT] DLL >>>>>>>>
684 20:14:25.445412 [ANA_INIT] flow end
685 20:14:25.452136 ============ LP4 DIFF to SE enter ============
686 20:14:25.455675 ============ LP4 DIFF to SE exit ============
687 20:14:25.456253 [ANA_INIT] <<<<<<<<<<<<<
688 20:14:25.458402 [Flow] Enable top DCM control >>>>>
689 20:14:25.462215 [Flow] Enable top DCM control <<<<<
690 20:14:25.464794 Enable DLL master slave shuffle
691 20:14:25.471857 ==============================================================
692 20:14:25.475598 Gating Mode config
693 20:14:25.479004 ==============================================================
694 20:14:25.481550 Config description:
695 20:14:25.491676 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 20:14:25.498638 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 20:14:25.502236 SELPH_MODE 0: By rank 1: By Phase
698 20:14:25.508329 ==============================================================
699 20:14:25.511891 GAT_TRACK_EN = 1
700 20:14:25.514843 RX_GATING_MODE = 2
701 20:14:25.515321 RX_GATING_TRACK_MODE = 2
702 20:14:25.518357 SELPH_MODE = 1
703 20:14:25.521412 PICG_EARLY_EN = 1
704 20:14:25.524933 VALID_LAT_VALUE = 1
705 20:14:25.531846 ==============================================================
706 20:14:25.534687 Enter into Gating configuration >>>>
707 20:14:25.538193 Exit from Gating configuration <<<<
708 20:14:25.541291 Enter into DVFS_PRE_config >>>>>
709 20:14:25.551628 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 20:14:25.555279 Exit from DVFS_PRE_config <<<<<
711 20:14:25.558664 Enter into PICG configuration >>>>
712 20:14:25.561412 Exit from PICG configuration <<<<
713 20:14:25.564923 [RX_INPUT] configuration >>>>>
714 20:14:25.568469 [RX_INPUT] configuration <<<<<
715 20:14:25.571892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 20:14:25.578318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 20:14:25.585470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 20:14:25.591857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 20:14:25.595443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 20:14:25.601541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 20:14:25.605363 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 20:14:25.611999 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 20:14:25.614967 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 20:14:25.618509 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 20:14:25.621761 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 20:14:25.628224 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 20:14:25.631503 ===================================
728 20:14:25.631981 LPDDR4 DRAM CONFIGURATION
729 20:14:25.634965 ===================================
730 20:14:25.637851 EX_ROW_EN[0] = 0x0
731 20:14:25.641591 EX_ROW_EN[1] = 0x0
732 20:14:25.642070 LP4Y_EN = 0x0
733 20:14:25.644441 WORK_FSP = 0x0
734 20:14:25.644970 WL = 0x2
735 20:14:25.648132 RL = 0x2
736 20:14:25.648750 BL = 0x2
737 20:14:25.651315 RPST = 0x0
738 20:14:25.651792 RD_PRE = 0x0
739 20:14:25.654534 WR_PRE = 0x1
740 20:14:25.655012 WR_PST = 0x0
741 20:14:25.658125 DBI_WR = 0x0
742 20:14:25.658697 DBI_RD = 0x0
743 20:14:25.661405 OTF = 0x1
744 20:14:25.664481 ===================================
745 20:14:25.668594 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 20:14:25.671558 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 20:14:25.678075 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 20:14:25.681420 ===================================
749 20:14:25.681996 LPDDR4 DRAM CONFIGURATION
750 20:14:25.685284 ===================================
751 20:14:25.687858 EX_ROW_EN[0] = 0x10
752 20:14:25.691046 EX_ROW_EN[1] = 0x0
753 20:14:25.691532 LP4Y_EN = 0x0
754 20:14:25.694246 WORK_FSP = 0x0
755 20:14:25.694848 WL = 0x2
756 20:14:25.697956 RL = 0x2
757 20:14:25.698435 BL = 0x2
758 20:14:25.701403 RPST = 0x0
759 20:14:25.702039 RD_PRE = 0x0
760 20:14:25.705624 WR_PRE = 0x1
761 20:14:25.706202 WR_PST = 0x0
762 20:14:25.707536 DBI_WR = 0x0
763 20:14:25.708011 DBI_RD = 0x0
764 20:14:25.711303 OTF = 0x1
765 20:14:25.714863 ===================================
766 20:14:25.721439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 20:14:25.724288 nWR fixed to 40
768 20:14:25.724906 [ModeRegInit_LP4] CH0 RK0
769 20:14:25.727827 [ModeRegInit_LP4] CH0 RK1
770 20:14:25.731533 [ModeRegInit_LP4] CH1 RK0
771 20:14:25.732105 [ModeRegInit_LP4] CH1 RK1
772 20:14:25.734602 match AC timing 12
773 20:14:25.737673 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 20:14:25.744475 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 20:14:25.747632 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 20:14:25.750884 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 20:14:25.758356 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 20:14:25.758960 [EMI DOE] emi_dcm 0
779 20:14:25.764388 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 20:14:25.765011 ==
781 20:14:25.767822 Dram Type= 6, Freq= 0, CH_0, rank 0
782 20:14:25.771151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 20:14:25.771736 ==
784 20:14:25.777325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 20:14:25.780898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 20:14:25.791339 [CA 0] Center 37 (7~68) winsize 62
787 20:14:25.794468 [CA 1] Center 37 (7~68) winsize 62
788 20:14:25.797812 [CA 2] Center 35 (5~66) winsize 62
789 20:14:25.801030 [CA 3] Center 35 (5~66) winsize 62
790 20:14:25.803942 [CA 4] Center 34 (4~65) winsize 62
791 20:14:25.807767 [CA 5] Center 34 (3~65) winsize 63
792 20:14:25.808351
793 20:14:25.810981 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 20:14:25.811705
795 20:14:25.815503 [CATrainingPosCal] consider 1 rank data
796 20:14:25.817750 u2DelayCellTimex100 = 270/100 ps
797 20:14:25.821417 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 20:14:25.824685 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 20:14:25.831623 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 20:14:25.834866 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 20:14:25.837945 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 20:14:25.841606 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
803 20:14:25.842094
804 20:14:25.844115 CA PerBit enable=1, Macro0, CA PI delay=34
805 20:14:25.844584
806 20:14:25.848123 [CBTSetCACLKResult] CA Dly = 34
807 20:14:25.848698 CS Dly: 5 (0~36)
808 20:14:25.849143 ==
809 20:14:25.850701 Dram Type= 6, Freq= 0, CH_0, rank 1
810 20:14:25.857466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 20:14:25.858037 ==
812 20:14:25.861154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 20:14:25.867468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 20:14:25.877009 [CA 0] Center 37 (7~68) winsize 62
815 20:14:25.880131 [CA 1] Center 37 (6~68) winsize 63
816 20:14:25.883752 [CA 2] Center 35 (4~66) winsize 63
817 20:14:25.887605 [CA 3] Center 35 (4~66) winsize 63
818 20:14:25.889896 [CA 4] Center 34 (4~65) winsize 62
819 20:14:25.894133 [CA 5] Center 34 (3~65) winsize 63
820 20:14:25.894722
821 20:14:25.896856 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 20:14:25.897332
823 20:14:25.900011 [CATrainingPosCal] consider 2 rank data
824 20:14:25.903237 u2DelayCellTimex100 = 270/100 ps
825 20:14:25.907190 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 20:14:25.909927 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 20:14:25.916816 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 20:14:25.920060 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
829 20:14:25.923046 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
830 20:14:25.926549 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
831 20:14:25.927129
832 20:14:25.930703 CA PerBit enable=1, Macro0, CA PI delay=34
833 20:14:25.931193
834 20:14:25.933051 [CBTSetCACLKResult] CA Dly = 34
835 20:14:25.933523 CS Dly: 5 (0~37)
836 20:14:25.933898
837 20:14:25.937984 ----->DramcWriteLeveling(PI) begin...
838 20:14:25.939621 ==
839 20:14:25.943806 Dram Type= 6, Freq= 0, CH_0, rank 0
840 20:14:25.947332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 20:14:25.947913 ==
842 20:14:25.949853 Write leveling (Byte 0): 28 => 28
843 20:14:25.953238 Write leveling (Byte 1): 27 => 27
844 20:14:25.957216 DramcWriteLeveling(PI) end<-----
845 20:14:25.957980
846 20:14:25.958386 ==
847 20:14:25.959988 Dram Type= 6, Freq= 0, CH_0, rank 0
848 20:14:25.963485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 20:14:25.964083 ==
850 20:14:25.966849 [Gating] SW mode calibration
851 20:14:25.973425 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 20:14:25.976861 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 20:14:25.983867 0 6 0 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 0)
854 20:14:25.986882 0 6 4 | B1->B0 | 2e2e 2828 | 1 0 | (1 0) (0 0)
855 20:14:25.989754 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 20:14:25.996637 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 20:14:26.000095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:14:26.003374 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:14:26.009922 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:14:26.013685 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:14:26.016863 0 7 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (1 1)
862 20:14:26.023530 0 7 4 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
863 20:14:26.027007 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 20:14:26.029611 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 20:14:26.036756 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 20:14:26.039817 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 20:14:26.043677 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 20:14:26.049705 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 20:14:26.053346 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 20:14:26.056905 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
871 20:14:26.063069 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 20:14:26.066732 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 20:14:26.069505 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 20:14:26.072958 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 20:14:26.079615 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 20:14:26.083011 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 20:14:26.086159 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 20:14:26.093093 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 20:14:26.096793 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 20:14:26.099791 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 20:14:26.107010 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 20:14:26.110062 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 20:14:26.113694 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 20:14:26.119695 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 20:14:26.122949 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 20:14:26.126566 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 20:14:26.129791 Total UI for P1: 0, mck2ui 16
888 20:14:26.133114 best dqsien dly found for B0: ( 0, 10, 0)
889 20:14:26.136691 Total UI for P1: 0, mck2ui 16
890 20:14:26.139872 best dqsien dly found for B1: ( 0, 10, 0)
891 20:14:26.143213 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 20:14:26.146768 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 20:14:26.147351
894 20:14:26.153361 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 20:14:26.156155 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 20:14:26.156774 [Gating] SW calibration Done
897 20:14:26.159555 ==
898 20:14:26.163573 Dram Type= 6, Freq= 0, CH_0, rank 0
899 20:14:26.167558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 20:14:26.168135 ==
901 20:14:26.168517 RX Vref Scan: 0
902 20:14:26.168920
903 20:14:26.170027 RX Vref 0 -> 0, step: 1
904 20:14:26.170425
905 20:14:26.173472 RX Delay -130 -> 252, step: 16
906 20:14:26.177469 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 20:14:26.180225 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 20:14:26.183797 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 20:14:26.187508 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 20:14:26.193554 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 20:14:26.196804 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 20:14:26.200229 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 20:14:26.203670 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 20:14:26.207375 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 20:14:26.213962 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 20:14:26.217050 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 20:14:26.220761 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 20:14:26.223486 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 20:14:26.227008 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 20:14:26.233950 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 20:14:26.236977 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 20:14:26.237541 ==
923 20:14:26.241363 Dram Type= 6, Freq= 0, CH_0, rank 0
924 20:14:26.244869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 20:14:26.245439 ==
926 20:14:26.247433 DQS Delay:
927 20:14:26.248006 DQS0 = 0, DQS1 = 0
928 20:14:26.248385 DQM Delay:
929 20:14:26.250812 DQM0 = 82, DQM1 = 74
930 20:14:26.251379 DQ Delay:
931 20:14:26.253206 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 20:14:26.257579 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 20:14:26.260421 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 20:14:26.263742 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 20:14:26.264309
936 20:14:26.264679
937 20:14:26.265070 ==
938 20:14:26.267003 Dram Type= 6, Freq= 0, CH_0, rank 0
939 20:14:26.273550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 20:14:26.274125 ==
941 20:14:26.274504
942 20:14:26.274851
943 20:14:26.275181 TX Vref Scan disable
944 20:14:26.277513 == TX Byte 0 ==
945 20:14:26.280192 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
946 20:14:26.286906 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
947 20:14:26.287574 == TX Byte 1 ==
948 20:14:26.291289 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
949 20:14:26.296949 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
950 20:14:26.297501 ==
951 20:14:26.300530 Dram Type= 6, Freq= 0, CH_0, rank 0
952 20:14:26.303135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 20:14:26.303611 ==
954 20:14:26.316089 TX Vref=22, minBit 2, minWin=27, winSum=441
955 20:14:26.319441 TX Vref=24, minBit 2, minWin=27, winSum=442
956 20:14:26.322564 TX Vref=26, minBit 3, minWin=27, winSum=446
957 20:14:26.325953 TX Vref=28, minBit 11, minWin=27, winSum=452
958 20:14:26.328990 TX Vref=30, minBit 0, minWin=28, winSum=450
959 20:14:26.336589 TX Vref=32, minBit 1, minWin=27, winSum=448
960 20:14:26.339609 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 30
961 20:14:26.340175
962 20:14:26.343314 Final TX Range 1 Vref 30
963 20:14:26.343887
964 20:14:26.344320 ==
965 20:14:26.346525 Dram Type= 6, Freq= 0, CH_0, rank 0
966 20:14:26.349537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 20:14:26.350106 ==
968 20:14:26.352261
969 20:14:26.352872
970 20:14:26.353254 TX Vref Scan disable
971 20:14:26.355410 == TX Byte 0 ==
972 20:14:26.359324 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 20:14:26.366685 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 20:14:26.367251 == TX Byte 1 ==
975 20:14:26.369790 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
976 20:14:26.375914 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
977 20:14:26.376485
978 20:14:26.376915 [DATLAT]
979 20:14:26.377269 Freq=800, CH0 RK0
980 20:14:26.377602
981 20:14:26.378780 DATLAT Default: 0xa
982 20:14:26.379261 0, 0xFFFF, sum = 0
983 20:14:26.382894 1, 0xFFFF, sum = 0
984 20:14:26.383482 2, 0xFFFF, sum = 0
985 20:14:26.385819 3, 0xFFFF, sum = 0
986 20:14:26.388886 4, 0xFFFF, sum = 0
987 20:14:26.389400 5, 0xFFFF, sum = 0
988 20:14:26.392158 6, 0xFFFF, sum = 0
989 20:14:26.392645 7, 0xFFFF, sum = 0
990 20:14:26.395795 8, 0x0, sum = 1
991 20:14:26.396372 9, 0x0, sum = 2
992 20:14:26.396826 10, 0x0, sum = 3
993 20:14:26.398799 11, 0x0, sum = 4
994 20:14:26.399277 best_step = 9
995 20:14:26.399661
996 20:14:26.400009 ==
997 20:14:26.402291 Dram Type= 6, Freq= 0, CH_0, rank 0
998 20:14:26.409323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 20:14:26.409899 ==
1000 20:14:26.410276 RX Vref Scan: 1
1001 20:14:26.410618
1002 20:14:26.412140 Set Vref Range= 32 -> 127
1003 20:14:26.412609
1004 20:14:26.415400 RX Vref 32 -> 127, step: 1
1005 20:14:26.415873
1006 20:14:26.419253 RX Delay -111 -> 252, step: 8
1007 20:14:26.419827
1008 20:14:26.421980 Set Vref, RX VrefLevel [Byte0]: 32
1009 20:14:26.425511 [Byte1]: 32
1010 20:14:26.425981
1011 20:14:26.428352 Set Vref, RX VrefLevel [Byte0]: 33
1012 20:14:26.432179 [Byte1]: 33
1013 20:14:26.432951
1014 20:14:26.435816 Set Vref, RX VrefLevel [Byte0]: 34
1015 20:14:26.438631 [Byte1]: 34
1016 20:14:26.443271
1017 20:14:26.443838 Set Vref, RX VrefLevel [Byte0]: 35
1018 20:14:26.445758 [Byte1]: 35
1019 20:14:26.450590
1020 20:14:26.451057 Set Vref, RX VrefLevel [Byte0]: 36
1021 20:14:26.452946 [Byte1]: 36
1022 20:14:26.457627
1023 20:14:26.458093 Set Vref, RX VrefLevel [Byte0]: 37
1024 20:14:26.460654 [Byte1]: 37
1025 20:14:26.465813
1026 20:14:26.466293 Set Vref, RX VrefLevel [Byte0]: 38
1027 20:14:26.468901 [Byte1]: 38
1028 20:14:26.472901
1029 20:14:26.473346 Set Vref, RX VrefLevel [Byte0]: 39
1030 20:14:26.475767 [Byte1]: 39
1031 20:14:26.479993
1032 20:14:26.480255 Set Vref, RX VrefLevel [Byte0]: 40
1033 20:14:26.484557 [Byte1]: 40
1034 20:14:26.487995
1035 20:14:26.488173 Set Vref, RX VrefLevel [Byte0]: 41
1036 20:14:26.491189 [Byte1]: 41
1037 20:14:26.495519
1038 20:14:26.495757 Set Vref, RX VrefLevel [Byte0]: 42
1039 20:14:26.499202 [Byte1]: 42
1040 20:14:26.502698
1041 20:14:26.502887 Set Vref, RX VrefLevel [Byte0]: 43
1042 20:14:26.506168 [Byte1]: 43
1043 20:14:26.510254
1044 20:14:26.510453 Set Vref, RX VrefLevel [Byte0]: 44
1045 20:14:26.514188 [Byte1]: 44
1046 20:14:26.517711
1047 20:14:26.517828 Set Vref, RX VrefLevel [Byte0]: 45
1048 20:14:26.521502 [Byte1]: 45
1049 20:14:26.525956
1050 20:14:26.526073 Set Vref, RX VrefLevel [Byte0]: 46
1051 20:14:26.528849 [Byte1]: 46
1052 20:14:26.533407
1053 20:14:26.533571 Set Vref, RX VrefLevel [Byte0]: 47
1054 20:14:26.536600 [Byte1]: 47
1055 20:14:26.541504
1056 20:14:26.541941 Set Vref, RX VrefLevel [Byte0]: 48
1057 20:14:26.544495 [Byte1]: 48
1058 20:14:26.549193
1059 20:14:26.549648 Set Vref, RX VrefLevel [Byte0]: 49
1060 20:14:26.552429 [Byte1]: 49
1061 20:14:26.556788
1062 20:14:26.557236 Set Vref, RX VrefLevel [Byte0]: 50
1063 20:14:26.560176 [Byte1]: 50
1064 20:14:26.564302
1065 20:14:26.564768 Set Vref, RX VrefLevel [Byte0]: 51
1066 20:14:26.567782 [Byte1]: 51
1067 20:14:26.572525
1068 20:14:26.572776 Set Vref, RX VrefLevel [Byte0]: 52
1069 20:14:26.574775 [Byte1]: 52
1070 20:14:26.579037
1071 20:14:26.579217 Set Vref, RX VrefLevel [Byte0]: 53
1072 20:14:26.582693 [Byte1]: 53
1073 20:14:26.587443
1074 20:14:26.587575 Set Vref, RX VrefLevel [Byte0]: 54
1075 20:14:26.589940 [Byte1]: 54
1076 20:14:26.594641
1077 20:14:26.594760 Set Vref, RX VrefLevel [Byte0]: 55
1078 20:14:26.597725 [Byte1]: 55
1079 20:14:26.602048
1080 20:14:26.602141 Set Vref, RX VrefLevel [Byte0]: 56
1081 20:14:26.605720 [Byte1]: 56
1082 20:14:26.609582
1083 20:14:26.609667 Set Vref, RX VrefLevel [Byte0]: 57
1084 20:14:26.613591 [Byte1]: 57
1085 20:14:26.617855
1086 20:14:26.617940 Set Vref, RX VrefLevel [Byte0]: 58
1087 20:14:26.621214 [Byte1]: 58
1088 20:14:26.625199
1089 20:14:26.625283 Set Vref, RX VrefLevel [Byte0]: 59
1090 20:14:26.628663 [Byte1]: 59
1091 20:14:26.633290
1092 20:14:26.633378 Set Vref, RX VrefLevel [Byte0]: 60
1093 20:14:26.636189 [Byte1]: 60
1094 20:14:26.640999
1095 20:14:26.641157 Set Vref, RX VrefLevel [Byte0]: 61
1096 20:14:26.643870 [Byte1]: 61
1097 20:14:26.648494
1098 20:14:26.648578 Set Vref, RX VrefLevel [Byte0]: 62
1099 20:14:26.651884 [Byte1]: 62
1100 20:14:26.655588
1101 20:14:26.655674 Set Vref, RX VrefLevel [Byte0]: 63
1102 20:14:26.659280 [Byte1]: 63
1103 20:14:26.663622
1104 20:14:26.663708 Set Vref, RX VrefLevel [Byte0]: 64
1105 20:14:26.666701 [Byte1]: 64
1106 20:14:26.671062
1107 20:14:26.671147 Set Vref, RX VrefLevel [Byte0]: 65
1108 20:14:26.674212 [Byte1]: 65
1109 20:14:26.679137
1110 20:14:26.679222 Set Vref, RX VrefLevel [Byte0]: 66
1111 20:14:26.682030 [Byte1]: 66
1112 20:14:26.686944
1113 20:14:26.687030 Set Vref, RX VrefLevel [Byte0]: 67
1114 20:14:26.689466 [Byte1]: 67
1115 20:14:26.694017
1116 20:14:26.694101 Set Vref, RX VrefLevel [Byte0]: 68
1117 20:14:26.698168 [Byte1]: 68
1118 20:14:26.701664
1119 20:14:26.702087 Set Vref, RX VrefLevel [Byte0]: 69
1120 20:14:26.705869 [Byte1]: 69
1121 20:14:26.710354
1122 20:14:26.710777 Set Vref, RX VrefLevel [Byte0]: 70
1123 20:14:26.712631 [Byte1]: 70
1124 20:14:26.716823
1125 20:14:26.717125 Set Vref, RX VrefLevel [Byte0]: 71
1126 20:14:26.720345 [Byte1]: 71
1127 20:14:26.724621
1128 20:14:26.724869 Set Vref, RX VrefLevel [Byte0]: 72
1129 20:14:26.727703 [Byte1]: 72
1130 20:14:26.732323
1131 20:14:26.732477 Final RX Vref Byte 0 = 53 to rank0
1132 20:14:26.735938 Final RX Vref Byte 1 = 55 to rank0
1133 20:14:26.739579 Final RX Vref Byte 0 = 53 to rank1
1134 20:14:26.742415 Final RX Vref Byte 1 = 55 to rank1==
1135 20:14:26.746762 Dram Type= 6, Freq= 0, CH_0, rank 0
1136 20:14:26.752464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1137 20:14:26.752680 ==
1138 20:14:26.752821 DQS Delay:
1139 20:14:26.752928 DQS0 = 0, DQS1 = 0
1140 20:14:26.755775 DQM Delay:
1141 20:14:26.755991 DQM0 = 83, DQM1 = 73
1142 20:14:26.759062 DQ Delay:
1143 20:14:26.763286 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1144 20:14:26.763520 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1145 20:14:26.766567 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1146 20:14:26.769557 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1147 20:14:26.772799
1148 20:14:26.773075
1149 20:14:26.778868 [DQSOSCAuto] RK0, (LSB)MR18= 0x3030, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1150 20:14:26.782789 CH0 RK0: MR19=606, MR18=3030
1151 20:14:26.790504 CH0_RK0: MR19=0x606, MR18=0x3030, DQSOSC=397, MR23=63, INC=93, DEC=62
1152 20:14:26.791164
1153 20:14:26.792632 ----->DramcWriteLeveling(PI) begin...
1154 20:14:26.793133 ==
1155 20:14:26.796364 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 20:14:26.799270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1157 20:14:26.799841 ==
1158 20:14:26.802192 Write leveling (Byte 0): 27 => 27
1159 20:14:26.805821 Write leveling (Byte 1): 27 => 27
1160 20:14:26.809324 DramcWriteLeveling(PI) end<-----
1161 20:14:26.809891
1162 20:14:26.810264 ==
1163 20:14:26.813208 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 20:14:26.816459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1165 20:14:26.817095 ==
1166 20:14:26.819512 [Gating] SW mode calibration
1167 20:14:26.826064 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1168 20:14:26.832883 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1169 20:14:26.836879 0 6 0 | B1->B0 | 3232 3030 | 0 0 | (0 0) (1 0)
1170 20:14:26.840148 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
1171 20:14:26.845823 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 20:14:26.849441 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 20:14:26.852526 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 20:14:26.859465 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 20:14:26.862689 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 20:14:26.865577 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 20:14:26.872959 0 7 0 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
1178 20:14:26.876157 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1179 20:14:26.879210 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 20:14:26.886050 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 20:14:26.889207 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 20:14:26.893255 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 20:14:26.898913 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 20:14:26.902757 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 20:14:26.906002 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1186 20:14:26.909607 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1187 20:14:26.915734 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 20:14:26.918994 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 20:14:26.922685 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 20:14:26.929079 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 20:14:26.932241 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 20:14:26.935687 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 20:14:26.942164 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 20:14:26.946260 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 20:14:26.949256 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 20:14:26.956144 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 20:14:26.959488 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 20:14:26.963234 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 20:14:26.969382 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 20:14:26.972648 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 20:14:26.975691 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1202 20:14:26.983323 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 20:14:26.983887 Total UI for P1: 0, mck2ui 16
1204 20:14:26.986476 best dqsien dly found for B0: ( 0, 10, 2)
1205 20:14:26.989290 Total UI for P1: 0, mck2ui 16
1206 20:14:26.992777 best dqsien dly found for B1: ( 0, 10, 0)
1207 20:14:26.996139 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1208 20:14:27.002910 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1209 20:14:27.003480
1210 20:14:27.006226 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1211 20:14:27.009463 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1212 20:14:27.013060 [Gating] SW calibration Done
1213 20:14:27.013623 ==
1214 20:14:27.016529 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 20:14:27.019423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1216 20:14:27.020005 ==
1217 20:14:27.022286 RX Vref Scan: 0
1218 20:14:27.022854
1219 20:14:27.023244 RX Vref 0 -> 0, step: 1
1220 20:14:27.023600
1221 20:14:27.025832 RX Delay -130 -> 252, step: 16
1222 20:14:27.029110 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1223 20:14:27.036018 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1224 20:14:27.039693 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1225 20:14:27.084392 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1226 20:14:27.085007 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1227 20:14:27.085386 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1228 20:14:27.086100 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1229 20:14:27.086486 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1230 20:14:27.086830 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1231 20:14:27.087222 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1232 20:14:27.087562 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1233 20:14:27.087955 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1234 20:14:27.088292 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1235 20:14:27.088687 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1236 20:14:27.109583 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1237 20:14:27.110197 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1238 20:14:27.110577 ==
1239 20:14:27.110925 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 20:14:27.111626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1241 20:14:27.112015 ==
1242 20:14:27.112347 DQS Delay:
1243 20:14:27.112663 DQS0 = 0, DQS1 = 0
1244 20:14:27.113028 DQM Delay:
1245 20:14:27.113348 DQM0 = 84, DQM1 = 74
1246 20:14:27.113657 DQ Delay:
1247 20:14:27.114036 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1248 20:14:27.114368 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1249 20:14:27.116638 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1250 20:14:27.117145 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1251 20:14:27.117523
1252 20:14:27.120530
1253 20:14:27.121222 ==
1254 20:14:27.121602 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 20:14:27.128047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1256 20:14:27.128625 ==
1257 20:14:27.129072
1258 20:14:27.129423
1259 20:14:27.129758 TX Vref Scan disable
1260 20:14:27.130450 == TX Byte 0 ==
1261 20:14:27.133711 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1262 20:14:27.140882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1263 20:14:27.141455 == TX Byte 1 ==
1264 20:14:27.144270 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1265 20:14:27.150376 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1266 20:14:27.150933 ==
1267 20:14:27.154367 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 20:14:27.157145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1269 20:14:27.157622 ==
1270 20:14:27.169638 TX Vref=22, minBit 2, minWin=27, winSum=442
1271 20:14:27.172885 TX Vref=24, minBit 2, minWin=27, winSum=446
1272 20:14:27.176095 TX Vref=26, minBit 14, minWin=27, winSum=451
1273 20:14:27.179649 TX Vref=28, minBit 1, minWin=28, winSum=453
1274 20:14:27.182700 TX Vref=30, minBit 0, minWin=28, winSum=456
1275 20:14:27.185940 TX Vref=32, minBit 2, minWin=28, winSum=457
1276 20:14:27.192989 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 32
1277 20:14:27.193565
1278 20:14:27.196649 Final TX Range 1 Vref 32
1279 20:14:27.197261
1280 20:14:27.197637 ==
1281 20:14:27.199869 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 20:14:27.203542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1283 20:14:27.204112 ==
1284 20:14:27.204482
1285 20:14:27.207025
1286 20:14:27.207583 TX Vref Scan disable
1287 20:14:27.209162 == TX Byte 0 ==
1288 20:14:27.213369 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1289 20:14:27.216785 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1290 20:14:27.219408 == TX Byte 1 ==
1291 20:14:27.222960 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1292 20:14:27.226659 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1293 20:14:27.229549
1294 20:14:27.230107 [DATLAT]
1295 20:14:27.230477 Freq=800, CH0 RK1
1296 20:14:27.230829
1297 20:14:27.232884 DATLAT Default: 0x9
1298 20:14:27.233356 0, 0xFFFF, sum = 0
1299 20:14:27.236496 1, 0xFFFF, sum = 0
1300 20:14:27.237030 2, 0xFFFF, sum = 0
1301 20:14:27.239410 3, 0xFFFF, sum = 0
1302 20:14:27.239884 4, 0xFFFF, sum = 0
1303 20:14:27.243454 5, 0xFFFF, sum = 0
1304 20:14:27.246009 6, 0xFFFF, sum = 0
1305 20:14:27.246488 7, 0xFFFF, sum = 0
1306 20:14:27.246868 8, 0x0, sum = 1
1307 20:14:27.249458 9, 0x0, sum = 2
1308 20:14:27.249964 10, 0x0, sum = 3
1309 20:14:27.252527 11, 0x0, sum = 4
1310 20:14:27.253149 best_step = 9
1311 20:14:27.253561
1312 20:14:27.254075 ==
1313 20:14:27.256168 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 20:14:27.263427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1315 20:14:27.263994 ==
1316 20:14:27.264366 RX Vref Scan: 0
1317 20:14:27.264767
1318 20:14:27.266335 RX Vref 0 -> 0, step: 1
1319 20:14:27.266803
1320 20:14:27.269656 RX Delay -111 -> 252, step: 8
1321 20:14:27.272986 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1322 20:14:27.276151 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1323 20:14:27.283070 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1324 20:14:27.286213 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1325 20:14:27.290088 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1326 20:14:27.292678 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1327 20:14:27.296480 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1328 20:14:27.299640 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1329 20:14:27.305705 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1330 20:14:27.309449 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1331 20:14:27.313067 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1332 20:14:27.315951 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1333 20:14:27.322747 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1334 20:14:27.326199 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1335 20:14:27.328983 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1336 20:14:27.332745 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1337 20:14:27.333319 ==
1338 20:14:27.335613 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 20:14:27.338938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1340 20:14:27.342492 ==
1341 20:14:27.343064 DQS Delay:
1342 20:14:27.343436 DQS0 = 0, DQS1 = 0
1343 20:14:27.345690 DQM Delay:
1344 20:14:27.346158 DQM0 = 86, DQM1 = 74
1345 20:14:27.348906 DQ Delay:
1346 20:14:27.352695 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1347 20:14:27.353317 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1348 20:14:27.355880 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1349 20:14:27.359509 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1350 20:14:27.359980
1351 20:14:27.362662
1352 20:14:27.369167 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1353 20:14:27.372842 CH0 RK1: MR19=606, MR18=3E3E
1354 20:14:27.379267 CH0_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1355 20:14:27.383460 [RxdqsGatingPostProcess] freq 800
1356 20:14:27.386190 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1357 20:14:27.388923 Pre-setting of DQS Precalculation
1358 20:14:27.392978 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1359 20:14:27.395752 ==
1360 20:14:27.398976 Dram Type= 6, Freq= 0, CH_1, rank 0
1361 20:14:27.402282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1362 20:14:27.402750 ==
1363 20:14:27.405870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1364 20:14:27.412638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1365 20:14:27.421606 [CA 0] Center 36 (6~67) winsize 62
1366 20:14:27.425555 [CA 1] Center 36 (5~67) winsize 63
1367 20:14:27.429594 [CA 2] Center 34 (4~65) winsize 62
1368 20:14:27.433401 [CA 3] Center 34 (4~64) winsize 61
1369 20:14:27.435565 [CA 4] Center 33 (3~64) winsize 62
1370 20:14:27.438721 [CA 5] Center 33 (3~64) winsize 62
1371 20:14:27.439048
1372 20:14:27.441953 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1373 20:14:27.442395
1374 20:14:27.445127 [CATrainingPosCal] consider 1 rank data
1375 20:14:27.448326 u2DelayCellTimex100 = 270/100 ps
1376 20:14:27.452155 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1377 20:14:27.454986 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1378 20:14:27.462749 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1379 20:14:27.465460 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1380 20:14:27.468686 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1381 20:14:27.471976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1382 20:14:27.472541
1383 20:14:27.476617 CA PerBit enable=1, Macro0, CA PI delay=33
1384 20:14:27.477241
1385 20:14:27.479262 [CBTSetCACLKResult] CA Dly = 33
1386 20:14:27.479827 CS Dly: 4 (0~35)
1387 20:14:27.480199 ==
1388 20:14:27.482514 Dram Type= 6, Freq= 0, CH_1, rank 1
1389 20:14:27.489527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1390 20:14:27.490110 ==
1391 20:14:27.491761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 20:14:27.498348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 20:14:27.508329 [CA 0] Center 36 (6~67) winsize 62
1394 20:14:27.511472 [CA 1] Center 36 (5~67) winsize 63
1395 20:14:27.514416 [CA 2] Center 34 (4~65) winsize 62
1396 20:14:27.518375 [CA 3] Center 34 (4~64) winsize 61
1397 20:14:27.520922 [CA 4] Center 33 (3~64) winsize 62
1398 20:14:27.524922 [CA 5] Center 33 (3~63) winsize 61
1399 20:14:27.525497
1400 20:14:27.528218 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1401 20:14:27.528836
1402 20:14:27.531362 [CATrainingPosCal] consider 2 rank data
1403 20:14:27.535186 u2DelayCellTimex100 = 270/100 ps
1404 20:14:27.537865 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1405 20:14:27.542076 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1406 20:14:27.548780 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1407 20:14:27.551100 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1408 20:14:27.554307 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1409 20:14:27.557635 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1410 20:14:27.558104
1411 20:14:27.560828 CA PerBit enable=1, Macro0, CA PI delay=33
1412 20:14:27.561295
1413 20:14:27.564884 [CBTSetCACLKResult] CA Dly = 33
1414 20:14:27.565450 CS Dly: 4 (0~36)
1415 20:14:27.565819
1416 20:14:27.568389 ----->DramcWriteLeveling(PI) begin...
1417 20:14:27.571261 ==
1418 20:14:27.571853 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 20:14:27.577853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1420 20:14:27.578431 ==
1421 20:14:27.582329 Write leveling (Byte 0): 26 => 26
1422 20:14:27.584950 Write leveling (Byte 1): 25 => 25
1423 20:14:27.585517 DramcWriteLeveling(PI) end<-----
1424 20:14:27.588442
1425 20:14:27.589071 ==
1426 20:14:27.591064 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 20:14:27.594739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1428 20:14:27.595212 ==
1429 20:14:27.598036 [Gating] SW mode calibration
1430 20:14:27.605579 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1431 20:14:27.608332 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1432 20:14:27.614376 0 6 0 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 0)
1433 20:14:27.617935 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1434 20:14:27.620792 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 20:14:27.627649 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 20:14:27.631502 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 20:14:27.634392 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 20:14:27.641378 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 20:14:27.645133 0 6 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1440 20:14:27.647209 0 7 0 | B1->B0 | 3030 4444 | 1 0 | (0 0) (0 0)
1441 20:14:27.654525 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1442 20:14:27.657873 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 20:14:27.663470 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 20:14:27.667347 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 20:14:27.670831 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 20:14:27.674228 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 20:14:27.680753 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 20:14:27.684142 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1449 20:14:27.687982 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 20:14:27.693810 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 20:14:27.698016 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 20:14:27.701466 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 20:14:27.707163 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 20:14:27.710884 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 20:14:27.714114 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 20:14:27.720964 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 20:14:27.723960 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 20:14:27.727095 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 20:14:27.733816 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 20:14:27.737506 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 20:14:27.740693 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 20:14:27.744030 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 20:14:27.750939 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1464 20:14:27.754232 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1465 20:14:27.757095 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1466 20:14:27.760514 Total UI for P1: 0, mck2ui 16
1467 20:14:27.764985 best dqsien dly found for B0: ( 0, 9, 30)
1468 20:14:27.767612 Total UI for P1: 0, mck2ui 16
1469 20:14:27.770636 best dqsien dly found for B1: ( 0, 10, 0)
1470 20:14:27.774118 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1471 20:14:27.777650 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1472 20:14:27.778120
1473 20:14:27.783917 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1474 20:14:27.787213 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1475 20:14:27.790445 [Gating] SW calibration Done
1476 20:14:27.790928 ==
1477 20:14:27.793980 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 20:14:27.797024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1479 20:14:27.797594 ==
1480 20:14:27.797969 RX Vref Scan: 0
1481 20:14:27.800373
1482 20:14:27.800989 RX Vref 0 -> 0, step: 1
1483 20:14:27.801371
1484 20:14:27.803304 RX Delay -130 -> 252, step: 16
1485 20:14:27.808577 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1486 20:14:27.810346 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1487 20:14:27.817140 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1488 20:14:27.820835 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1489 20:14:27.823958 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1490 20:14:27.827116 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1491 20:14:27.830046 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1492 20:14:27.837061 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1493 20:14:27.839754 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1494 20:14:27.843541 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1495 20:14:27.846802 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1496 20:14:27.849871 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1497 20:14:27.856996 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1498 20:14:27.860882 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1499 20:14:27.863488 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1500 20:14:27.866962 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1501 20:14:27.867539 ==
1502 20:14:27.869878 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 20:14:27.876991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1504 20:14:27.877576 ==
1505 20:14:27.877952 DQS Delay:
1506 20:14:27.880557 DQS0 = 0, DQS1 = 0
1507 20:14:27.881062 DQM Delay:
1508 20:14:27.881481 DQM0 = 81, DQM1 = 73
1509 20:14:27.884697 DQ Delay:
1510 20:14:27.886331 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1511 20:14:27.889824 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1512 20:14:27.893321 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1513 20:14:27.896858 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1514 20:14:27.897430
1515 20:14:27.897803
1516 20:14:27.898149 ==
1517 20:14:27.900400 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 20:14:27.903097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1519 20:14:27.903571 ==
1520 20:14:27.903944
1521 20:14:27.904288
1522 20:14:27.906792 TX Vref Scan disable
1523 20:14:27.907261 == TX Byte 0 ==
1524 20:14:27.913417 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1525 20:14:27.916645 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1526 20:14:27.919922 == TX Byte 1 ==
1527 20:14:27.923200 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1528 20:14:27.926372 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1529 20:14:27.926844 ==
1530 20:14:27.929732 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 20:14:27.933891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1532 20:14:27.934634 ==
1533 20:14:27.947183 TX Vref=22, minBit 8, minWin=27, winSum=446
1534 20:14:27.950534 TX Vref=24, minBit 10, minWin=27, winSum=450
1535 20:14:27.953442 TX Vref=26, minBit 0, minWin=28, winSum=451
1536 20:14:27.957026 TX Vref=28, minBit 0, minWin=28, winSum=452
1537 20:14:27.961221 TX Vref=30, minBit 0, minWin=28, winSum=455
1538 20:14:27.967225 TX Vref=32, minBit 0, minWin=28, winSum=456
1539 20:14:27.970544 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 32
1540 20:14:27.971137
1541 20:14:27.974328 Final TX Range 1 Vref 32
1542 20:14:27.974904
1543 20:14:27.975277 ==
1544 20:14:27.976956 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 20:14:27.980700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1546 20:14:27.981320 ==
1547 20:14:27.983404
1548 20:14:27.983961
1549 20:14:27.984329 TX Vref Scan disable
1550 20:14:27.988011 == TX Byte 0 ==
1551 20:14:27.991889 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1552 20:14:27.993848 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1553 20:14:27.997352 == TX Byte 1 ==
1554 20:14:28.000082 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1555 20:14:28.003583 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1556 20:14:28.007569
1557 20:14:28.008130 [DATLAT]
1558 20:14:28.008499 Freq=800, CH1 RK0
1559 20:14:28.008898
1560 20:14:28.010650 DATLAT Default: 0xa
1561 20:14:28.011213 0, 0xFFFF, sum = 0
1562 20:14:28.013416 1, 0xFFFF, sum = 0
1563 20:14:28.013889 2, 0xFFFF, sum = 0
1564 20:14:28.017009 3, 0xFFFF, sum = 0
1565 20:14:28.017575 4, 0xFFFF, sum = 0
1566 20:14:28.021274 5, 0xFFFF, sum = 0
1567 20:14:28.023627 6, 0xFFFF, sum = 0
1568 20:14:28.024100 7, 0xFFFF, sum = 0
1569 20:14:28.024475 8, 0x0, sum = 1
1570 20:14:28.026961 9, 0x0, sum = 2
1571 20:14:28.027546 10, 0x0, sum = 3
1572 20:14:28.030605 11, 0x0, sum = 4
1573 20:14:28.031186 best_step = 9
1574 20:14:28.031564
1575 20:14:28.031915 ==
1576 20:14:28.034093 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 20:14:28.040447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1578 20:14:28.041106 ==
1579 20:14:28.041485 RX Vref Scan: 1
1580 20:14:28.041834
1581 20:14:28.043738 Set Vref Range= 32 -> 127
1582 20:14:28.044202
1583 20:14:28.047029 RX Vref 32 -> 127, step: 1
1584 20:14:28.047602
1585 20:14:28.047972 RX Delay -111 -> 252, step: 8
1586 20:14:28.050817
1587 20:14:28.051380 Set Vref, RX VrefLevel [Byte0]: 32
1588 20:14:28.054042 [Byte1]: 32
1589 20:14:28.057839
1590 20:14:28.058303 Set Vref, RX VrefLevel [Byte0]: 33
1591 20:14:28.060887 [Byte1]: 33
1592 20:14:28.066084
1593 20:14:28.066645 Set Vref, RX VrefLevel [Byte0]: 34
1594 20:14:28.068945 [Byte1]: 34
1595 20:14:28.073108
1596 20:14:28.073762 Set Vref, RX VrefLevel [Byte0]: 35
1597 20:14:28.076775 [Byte1]: 35
1598 20:14:28.081515
1599 20:14:28.082174 Set Vref, RX VrefLevel [Byte0]: 36
1600 20:14:28.084737 [Byte1]: 36
1601 20:14:28.088777
1602 20:14:28.089350 Set Vref, RX VrefLevel [Byte0]: 37
1603 20:14:28.091911 [Byte1]: 37
1604 20:14:28.096805
1605 20:14:28.097376 Set Vref, RX VrefLevel [Byte0]: 38
1606 20:14:28.099401 [Byte1]: 38
1607 20:14:28.104030
1608 20:14:28.104525 Set Vref, RX VrefLevel [Byte0]: 39
1609 20:14:28.107135 [Byte1]: 39
1610 20:14:28.112017
1611 20:14:28.112588 Set Vref, RX VrefLevel [Byte0]: 40
1612 20:14:28.114911 [Byte1]: 40
1613 20:14:28.119236
1614 20:14:28.119801 Set Vref, RX VrefLevel [Byte0]: 41
1615 20:14:28.122413 [Byte1]: 41
1616 20:14:28.127372
1617 20:14:28.127939 Set Vref, RX VrefLevel [Byte0]: 42
1618 20:14:28.130290 [Byte1]: 42
1619 20:14:28.134487
1620 20:14:28.135057 Set Vref, RX VrefLevel [Byte0]: 43
1621 20:14:28.137925 [Byte1]: 43
1622 20:14:28.142301
1623 20:14:28.142768 Set Vref, RX VrefLevel [Byte0]: 44
1624 20:14:28.145137 [Byte1]: 44
1625 20:14:28.149523
1626 20:14:28.149986 Set Vref, RX VrefLevel [Byte0]: 45
1627 20:14:28.153222 [Byte1]: 45
1628 20:14:28.157439
1629 20:14:28.158003 Set Vref, RX VrefLevel [Byte0]: 46
1630 20:14:28.160609 [Byte1]: 46
1631 20:14:28.165270
1632 20:14:28.165837 Set Vref, RX VrefLevel [Byte0]: 47
1633 20:14:28.168759 [Byte1]: 47
1634 20:14:28.174004
1635 20:14:28.174573 Set Vref, RX VrefLevel [Byte0]: 48
1636 20:14:28.175826 [Byte1]: 48
1637 20:14:28.180519
1638 20:14:28.181146 Set Vref, RX VrefLevel [Byte0]: 49
1639 20:14:28.183784 [Byte1]: 49
1640 20:14:28.188974
1641 20:14:28.189543 Set Vref, RX VrefLevel [Byte0]: 50
1642 20:14:28.191791 [Byte1]: 50
1643 20:14:28.195660
1644 20:14:28.196225 Set Vref, RX VrefLevel [Byte0]: 51
1645 20:14:28.199180 [Byte1]: 51
1646 20:14:28.204418
1647 20:14:28.204918 Set Vref, RX VrefLevel [Byte0]: 52
1648 20:14:28.207054 [Byte1]: 52
1649 20:14:28.211619
1650 20:14:28.212188 Set Vref, RX VrefLevel [Byte0]: 53
1651 20:14:28.214152 [Byte1]: 53
1652 20:14:28.218929
1653 20:14:28.219495 Set Vref, RX VrefLevel [Byte0]: 54
1654 20:14:28.222476 [Byte1]: 54
1655 20:14:28.226964
1656 20:14:28.227530 Set Vref, RX VrefLevel [Byte0]: 55
1657 20:14:28.232557 [Byte1]: 55
1658 20:14:28.233070
1659 20:14:28.236023 Set Vref, RX VrefLevel [Byte0]: 56
1660 20:14:28.239190 [Byte1]: 56
1661 20:14:28.239655
1662 20:14:28.242499 Set Vref, RX VrefLevel [Byte0]: 57
1663 20:14:28.245737 [Byte1]: 57
1664 20:14:28.249159
1665 20:14:28.249715 Set Vref, RX VrefLevel [Byte0]: 58
1666 20:14:28.252873 [Byte1]: 58
1667 20:14:28.256578
1668 20:14:28.257097 Set Vref, RX VrefLevel [Byte0]: 59
1669 20:14:28.260826 [Byte1]: 59
1670 20:14:28.264558
1671 20:14:28.265205 Set Vref, RX VrefLevel [Byte0]: 60
1672 20:14:28.268116 [Byte1]: 60
1673 20:14:28.272279
1674 20:14:28.272902 Set Vref, RX VrefLevel [Byte0]: 61
1675 20:14:28.275807 [Byte1]: 61
1676 20:14:28.280099
1677 20:14:28.280684 Set Vref, RX VrefLevel [Byte0]: 62
1678 20:14:28.283181 [Byte1]: 62
1679 20:14:28.287624
1680 20:14:28.288189 Set Vref, RX VrefLevel [Byte0]: 63
1681 20:14:28.291414 [Byte1]: 63
1682 20:14:28.295338
1683 20:14:28.295812 Set Vref, RX VrefLevel [Byte0]: 64
1684 20:14:28.298478 [Byte1]: 64
1685 20:14:28.303305
1686 20:14:28.303909 Set Vref, RX VrefLevel [Byte0]: 65
1687 20:14:28.305937 [Byte1]: 65
1688 20:14:28.311291
1689 20:14:28.311859 Set Vref, RX VrefLevel [Byte0]: 66
1690 20:14:28.313646 [Byte1]: 66
1691 20:14:28.318556
1692 20:14:28.319124 Set Vref, RX VrefLevel [Byte0]: 67
1693 20:14:28.321649 [Byte1]: 67
1694 20:14:28.325551
1695 20:14:28.326193 Set Vref, RX VrefLevel [Byte0]: 68
1696 20:14:28.330170 [Byte1]: 68
1697 20:14:28.333505
1698 20:14:28.333983 Set Vref, RX VrefLevel [Byte0]: 69
1699 20:14:28.336899 [Byte1]: 69
1700 20:14:28.341248
1701 20:14:28.341820 Set Vref, RX VrefLevel [Byte0]: 70
1702 20:14:28.344144 [Byte1]: 70
1703 20:14:28.349090
1704 20:14:28.349673 Set Vref, RX VrefLevel [Byte0]: 71
1705 20:14:28.352989 [Byte1]: 71
1706 20:14:28.356468
1707 20:14:28.357088 Set Vref, RX VrefLevel [Byte0]: 72
1708 20:14:28.360372 [Byte1]: 72
1709 20:14:28.364035
1710 20:14:28.364821 Set Vref, RX VrefLevel [Byte0]: 73
1711 20:14:28.367722 [Byte1]: 73
1712 20:14:28.371771
1713 20:14:28.372337 Set Vref, RX VrefLevel [Byte0]: 74
1714 20:14:28.374849 [Byte1]: 74
1715 20:14:28.379116
1716 20:14:28.379640 Set Vref, RX VrefLevel [Byte0]: 75
1717 20:14:28.383740 [Byte1]: 75
1718 20:14:28.387535
1719 20:14:28.388100 Final RX Vref Byte 0 = 59 to rank0
1720 20:14:28.390069 Final RX Vref Byte 1 = 54 to rank0
1721 20:14:28.393767 Final RX Vref Byte 0 = 59 to rank1
1722 20:14:28.397392 Final RX Vref Byte 1 = 54 to rank1==
1723 20:14:28.400212 Dram Type= 6, Freq= 0, CH_1, rank 0
1724 20:14:28.406476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1725 20:14:28.406952 ==
1726 20:14:28.407323 DQS Delay:
1727 20:14:28.407681 DQS0 = 0, DQS1 = 0
1728 20:14:28.411151 DQM Delay:
1729 20:14:28.411724 DQM0 = 79, DQM1 = 72
1730 20:14:28.413452 DQ Delay:
1731 20:14:28.417170 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1732 20:14:28.420217 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1733 20:14:28.420822 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1734 20:14:28.426628 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1735 20:14:28.427189
1736 20:14:28.427561
1737 20:14:28.433715 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1738 20:14:28.437214 CH1 RK0: MR19=606, MR18=5050
1739 20:14:28.443565 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1740 20:14:28.444035
1741 20:14:28.446630 ----->DramcWriteLeveling(PI) begin...
1742 20:14:28.447121 ==
1743 20:14:28.449924 Dram Type= 6, Freq= 0, CH_1, rank 1
1744 20:14:28.453384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1745 20:14:28.453951 ==
1746 20:14:28.456981 Write leveling (Byte 0): 27 => 27
1747 20:14:28.461153 Write leveling (Byte 1): 25 => 25
1748 20:14:28.463952 DramcWriteLeveling(PI) end<-----
1749 20:14:28.464529
1750 20:14:28.464954 ==
1751 20:14:28.466849 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 20:14:28.470440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 20:14:28.471020 ==
1754 20:14:28.473268 [Gating] SW mode calibration
1755 20:14:28.481268 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1756 20:14:28.486740 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1757 20:14:28.490056 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1758 20:14:28.493236 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 20:14:28.500094 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 20:14:28.503243 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 20:14:28.506470 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 20:14:28.513049 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 20:14:28.517630 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 20:14:28.519936 0 6 28 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
1765 20:14:28.526556 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1766 20:14:28.531134 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 20:14:28.532942 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 20:14:28.539713 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 20:14:28.543056 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 20:14:28.546381 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 20:14:28.553564 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 20:14:28.556506 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1773 20:14:28.560002 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1774 20:14:28.564341 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1775 20:14:28.570524 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 20:14:28.573486 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 20:14:28.577664 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 20:14:28.583760 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 20:14:28.586604 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 20:14:28.589807 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 20:14:28.596198 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 20:14:28.601684 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 20:14:28.603166 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 20:14:28.609722 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 20:14:28.613073 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 20:14:28.616241 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 20:14:28.622976 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1788 20:14:28.627991 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1789 20:14:28.629586 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1790 20:14:28.636460 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1791 20:14:28.637072 Total UI for P1: 0, mck2ui 16
1792 20:14:28.644019 best dqsien dly found for B0: ( 0, 9, 28)
1793 20:14:28.644820 Total UI for P1: 0, mck2ui 16
1794 20:14:28.649560 best dqsien dly found for B1: ( 0, 10, 0)
1795 20:14:28.653335 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1796 20:14:28.656689 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1797 20:14:28.657315
1798 20:14:28.659539 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1799 20:14:28.662987 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1800 20:14:28.666579 [Gating] SW calibration Done
1801 20:14:28.667178 ==
1802 20:14:28.669495 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 20:14:28.673303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 20:14:28.673894 ==
1805 20:14:28.676217 RX Vref Scan: 0
1806 20:14:28.676823
1807 20:14:28.677200 RX Vref 0 -> 0, step: 1
1808 20:14:28.677549
1809 20:14:28.679688 RX Delay -130 -> 252, step: 16
1810 20:14:28.683343 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1811 20:14:28.689413 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1812 20:14:28.692939 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1813 20:14:28.696050 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1814 20:14:28.699598 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1815 20:14:28.703052 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1816 20:14:28.709486 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1817 20:14:28.713503 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1818 20:14:28.715914 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1819 20:14:28.719434 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1820 20:14:28.722947 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1821 20:14:28.729885 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1822 20:14:28.732989 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1823 20:14:28.736045 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1824 20:14:28.739557 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1825 20:14:28.742794 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1826 20:14:28.746223 ==
1827 20:14:28.749413 Dram Type= 6, Freq= 0, CH_1, rank 1
1828 20:14:28.753627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1829 20:14:28.754208 ==
1830 20:14:28.754584 DQS Delay:
1831 20:14:28.756534 DQS0 = 0, DQS1 = 0
1832 20:14:28.757051 DQM Delay:
1833 20:14:28.759640 DQM0 = 84, DQM1 = 73
1834 20:14:28.760111 DQ Delay:
1835 20:14:28.762578 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1836 20:14:28.766401 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1837 20:14:28.769524 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1838 20:14:28.772636 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1839 20:14:28.773451
1840 20:14:28.773909
1841 20:14:28.774262 ==
1842 20:14:28.776766 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 20:14:28.779412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1844 20:14:28.779992 ==
1845 20:14:28.780364
1846 20:14:28.780740
1847 20:14:28.782350 TX Vref Scan disable
1848 20:14:28.786300 == TX Byte 0 ==
1849 20:14:28.788906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1850 20:14:28.792415 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1851 20:14:28.796077 == TX Byte 1 ==
1852 20:14:28.799342 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1853 20:14:28.802916 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1854 20:14:28.803393 ==
1855 20:14:28.805622 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 20:14:28.808942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 20:14:28.812476 ==
1858 20:14:28.824185 TX Vref=22, minBit 0, minWin=28, winSum=453
1859 20:14:28.827442 TX Vref=24, minBit 0, minWin=28, winSum=453
1860 20:14:28.830545 TX Vref=26, minBit 5, minWin=28, winSum=458
1861 20:14:28.833487 TX Vref=28, minBit 4, minWin=28, winSum=456
1862 20:14:28.836939 TX Vref=30, minBit 0, minWin=28, winSum=456
1863 20:14:28.845117 TX Vref=32, minBit 0, minWin=28, winSum=457
1864 20:14:28.846970 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 26
1865 20:14:28.847455
1866 20:14:28.850067 Final TX Range 1 Vref 26
1867 20:14:28.850541
1868 20:14:28.850910 ==
1869 20:14:28.853364 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 20:14:28.857229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1871 20:14:28.857704 ==
1872 20:14:28.860052
1873 20:14:28.860518
1874 20:14:28.860943 TX Vref Scan disable
1875 20:14:28.863562 == TX Byte 0 ==
1876 20:14:28.867465 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1877 20:14:28.870414 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1878 20:14:28.874023 == TX Byte 1 ==
1879 20:14:28.877965 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1880 20:14:28.880935 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1881 20:14:28.883939
1882 20:14:28.884468 [DATLAT]
1883 20:14:28.884900 Freq=800, CH1 RK1
1884 20:14:28.885262
1885 20:14:28.887022 DATLAT Default: 0x9
1886 20:14:28.887583 0, 0xFFFF, sum = 0
1887 20:14:28.890300 1, 0xFFFF, sum = 0
1888 20:14:28.890778 2, 0xFFFF, sum = 0
1889 20:14:28.894360 3, 0xFFFF, sum = 0
1890 20:14:28.894932 4, 0xFFFF, sum = 0
1891 20:14:28.897093 5, 0xFFFF, sum = 0
1892 20:14:28.897571 6, 0xFFFF, sum = 0
1893 20:14:28.900747 7, 0xFFFF, sum = 0
1894 20:14:28.901319 8, 0x0, sum = 1
1895 20:14:28.904503 9, 0x0, sum = 2
1896 20:14:28.905130 10, 0x0, sum = 3
1897 20:14:28.907593 11, 0x0, sum = 4
1898 20:14:28.908163 best_step = 9
1899 20:14:28.908532
1900 20:14:28.908926 ==
1901 20:14:28.910182 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 20:14:28.919681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1903 20:14:28.920238 ==
1904 20:14:28.920616 RX Vref Scan: 0
1905 20:14:28.921054
1906 20:14:28.921812 RX Vref 0 -> 0, step: 1
1907 20:14:28.922276
1908 20:14:28.924218 RX Delay -111 -> 252, step: 8
1909 20:14:28.927294 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1910 20:14:28.930214 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1911 20:14:28.937751 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1912 20:14:28.941322 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1913 20:14:28.944026 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1914 20:14:28.947420 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1915 20:14:28.951373 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1916 20:14:28.953810 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1917 20:14:28.960606 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
1918 20:14:28.964071 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
1919 20:14:28.967443 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1920 20:14:28.970298 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1921 20:14:28.977448 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1922 20:14:28.981463 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1923 20:14:28.983635 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1924 20:14:28.987366 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1925 20:14:28.987941 ==
1926 20:14:28.990791 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 20:14:28.994063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1928 20:14:28.997114 ==
1929 20:14:28.997588 DQS Delay:
1930 20:14:28.997961 DQS0 = 0, DQS1 = 0
1931 20:14:29.000057 DQM Delay:
1932 20:14:29.000526 DQM0 = 82, DQM1 = 72
1933 20:14:29.003908 DQ Delay:
1934 20:14:29.004373 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1935 20:14:29.007848 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1936 20:14:29.010604 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1937 20:14:29.014702 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1938 20:14:29.016912
1939 20:14:29.017379
1940 20:14:29.023754 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1941 20:14:29.027172 CH1 RK1: MR19=606, MR18=3D3D
1942 20:14:29.033648 CH1_RK1: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1943 20:14:29.034234 [RxdqsGatingPostProcess] freq 800
1944 20:14:29.040781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1945 20:14:29.043382 Pre-setting of DQS Precalculation
1946 20:14:29.047003 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1947 20:14:29.057166 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1948 20:14:29.063639 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1949 20:14:29.064192
1950 20:14:29.064558
1951 20:14:29.067672 [Calibration Summary] 1600 Mbps
1952 20:14:29.068138 CH 0, Rank 0
1953 20:14:29.070873 SW Impedance : PASS
1954 20:14:29.071337 DUTY Scan : NO K
1955 20:14:29.073931 ZQ Calibration : PASS
1956 20:14:29.077142 Jitter Meter : NO K
1957 20:14:29.077702 CBT Training : PASS
1958 20:14:29.080830 Write leveling : PASS
1959 20:14:29.083725 RX DQS gating : PASS
1960 20:14:29.084284 RX DQ/DQS(RDDQC) : PASS
1961 20:14:29.087075 TX DQ/DQS : PASS
1962 20:14:29.090748 RX DATLAT : PASS
1963 20:14:29.091389 RX DQ/DQS(Engine): PASS
1964 20:14:29.093562 TX OE : NO K
1965 20:14:29.094029 All Pass.
1966 20:14:29.094398
1967 20:14:29.097056 CH 0, Rank 1
1968 20:14:29.097522 SW Impedance : PASS
1969 20:14:29.101234 DUTY Scan : NO K
1970 20:14:29.103519 ZQ Calibration : PASS
1971 20:14:29.103983 Jitter Meter : NO K
1972 20:14:29.107151 CBT Training : PASS
1973 20:14:29.107719 Write leveling : PASS
1974 20:14:29.110018 RX DQS gating : PASS
1975 20:14:29.114427 RX DQ/DQS(RDDQC) : PASS
1976 20:14:29.114987 TX DQ/DQS : PASS
1977 20:14:29.116758 RX DATLAT : PASS
1978 20:14:29.120452 RX DQ/DQS(Engine): PASS
1979 20:14:29.121068 TX OE : NO K
1980 20:14:29.124253 All Pass.
1981 20:14:29.124866
1982 20:14:29.125247 CH 1, Rank 0
1983 20:14:29.127042 SW Impedance : PASS
1984 20:14:29.127507 DUTY Scan : NO K
1985 20:14:29.130392 ZQ Calibration : PASS
1986 20:14:29.133922 Jitter Meter : NO K
1987 20:14:29.134497 CBT Training : PASS
1988 20:14:29.137835 Write leveling : PASS
1989 20:14:29.140688 RX DQS gating : PASS
1990 20:14:29.141241 RX DQ/DQS(RDDQC) : PASS
1991 20:14:29.143779 TX DQ/DQS : PASS
1992 20:14:29.144249 RX DATLAT : PASS
1993 20:14:29.147193 RX DQ/DQS(Engine): PASS
1994 20:14:29.150553 TX OE : NO K
1995 20:14:29.151142 All Pass.
1996 20:14:29.151523
1997 20:14:29.151961 CH 1, Rank 1
1998 20:14:29.153400 SW Impedance : PASS
1999 20:14:29.156834 DUTY Scan : NO K
2000 20:14:29.157599 ZQ Calibration : PASS
2001 20:14:29.160335 Jitter Meter : NO K
2002 20:14:29.163623 CBT Training : PASS
2003 20:14:29.164086 Write leveling : PASS
2004 20:14:29.167579 RX DQS gating : PASS
2005 20:14:29.170789 RX DQ/DQS(RDDQC) : PASS
2006 20:14:29.171346 TX DQ/DQS : PASS
2007 20:14:29.174091 RX DATLAT : PASS
2008 20:14:29.177592 RX DQ/DQS(Engine): PASS
2009 20:14:29.178119 TX OE : NO K
2010 20:14:29.180013 All Pass.
2011 20:14:29.180475
2012 20:14:29.180899 DramC Write-DBI off
2013 20:14:29.183865 PER_BANK_REFRESH: Hybrid Mode
2014 20:14:29.184332 TX_TRACKING: ON
2015 20:14:29.187155 [GetDramInforAfterCalByMRR] Vendor 6.
2016 20:14:29.193154 [GetDramInforAfterCalByMRR] Revision 606.
2017 20:14:29.196809 [GetDramInforAfterCalByMRR] Revision 2 0.
2018 20:14:29.197322 MR0 0x3939
2019 20:14:29.197701 MR8 0x1111
2020 20:14:29.199887 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2021 20:14:29.200586
2022 20:14:29.203610 MR0 0x3939
2023 20:14:29.204070 MR8 0x1111
2024 20:14:29.206921 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2025 20:14:29.207515
2026 20:14:29.216540 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2027 20:14:29.220153 [FAST_K] Save calibration result to emmc
2028 20:14:29.223055 [FAST_K] Save calibration result to emmc
2029 20:14:29.226528 dram_init: config_dvfs: 1
2030 20:14:29.230215 dramc_set_vcore_voltage set vcore to 662500
2031 20:14:29.233643 Read voltage for 1200, 2
2032 20:14:29.234219 Vio18 = 0
2033 20:14:29.234707 Vcore = 662500
2034 20:14:29.236663 Vdram = 0
2035 20:14:29.237187 Vddq = 0
2036 20:14:29.237666 Vmddr = 0
2037 20:14:29.243536 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2038 20:14:29.246232 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2039 20:14:29.250523 MEM_TYPE=3, freq_sel=15
2040 20:14:29.253028 sv_algorithm_assistance_LP4_1600
2041 20:14:29.256462 ============ PULL DRAM RESETB DOWN ============
2042 20:14:29.259982 ========== PULL DRAM RESETB DOWN end =========
2043 20:14:29.266446 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2044 20:14:29.269641 ===================================
2045 20:14:29.270266 LPDDR4 DRAM CONFIGURATION
2046 20:14:29.273521 ===================================
2047 20:14:29.277100 EX_ROW_EN[0] = 0x0
2048 20:14:29.280183 EX_ROW_EN[1] = 0x0
2049 20:14:29.280648 LP4Y_EN = 0x0
2050 20:14:29.283521 WORK_FSP = 0x0
2051 20:14:29.284079 WL = 0x4
2052 20:14:29.286781 RL = 0x4
2053 20:14:29.287343 BL = 0x2
2054 20:14:29.290256 RPST = 0x0
2055 20:14:29.290817 RD_PRE = 0x0
2056 20:14:29.293048 WR_PRE = 0x1
2057 20:14:29.293523 WR_PST = 0x0
2058 20:14:29.297036 DBI_WR = 0x0
2059 20:14:29.297501 DBI_RD = 0x0
2060 20:14:29.300240 OTF = 0x1
2061 20:14:29.303248 ===================================
2062 20:14:29.306503 ===================================
2063 20:14:29.306971 ANA top config
2064 20:14:29.309893 ===================================
2065 20:14:29.313230 DLL_ASYNC_EN = 0
2066 20:14:29.316211 ALL_SLAVE_EN = 0
2067 20:14:29.319426 NEW_RANK_MODE = 1
2068 20:14:29.319971 DLL_IDLE_MODE = 1
2069 20:14:29.323569 LP45_APHY_COMB_EN = 1
2070 20:14:29.326416 TX_ODT_DIS = 1
2071 20:14:29.329938 NEW_8X_MODE = 1
2072 20:14:29.332822 ===================================
2073 20:14:29.335884 ===================================
2074 20:14:29.341653 data_rate = 2400
2075 20:14:29.342213 CKR = 1
2076 20:14:29.342948 DQ_P2S_RATIO = 8
2077 20:14:29.346201 ===================================
2078 20:14:29.349863 CA_P2S_RATIO = 8
2079 20:14:29.353223 DQ_CA_OPEN = 0
2080 20:14:29.356282 DQ_SEMI_OPEN = 0
2081 20:14:29.359365 CA_SEMI_OPEN = 0
2082 20:14:29.359931 CA_FULL_RATE = 0
2083 20:14:29.362484 DQ_CKDIV4_EN = 0
2084 20:14:29.366279 CA_CKDIV4_EN = 0
2085 20:14:29.369298 CA_PREDIV_EN = 0
2086 20:14:29.373218 PH8_DLY = 17
2087 20:14:29.376132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2088 20:14:29.376599 DQ_AAMCK_DIV = 4
2089 20:14:29.379424 CA_AAMCK_DIV = 4
2090 20:14:29.383319 CA_ADMCK_DIV = 4
2091 20:14:29.386618 DQ_TRACK_CA_EN = 0
2092 20:14:29.389556 CA_PICK = 1200
2093 20:14:29.392462 CA_MCKIO = 1200
2094 20:14:29.392970 MCKIO_SEMI = 0
2095 20:14:29.396109 PLL_FREQ = 2366
2096 20:14:29.399574 DQ_UI_PI_RATIO = 32
2097 20:14:29.402748 CA_UI_PI_RATIO = 0
2098 20:14:29.406402 ===================================
2099 20:14:29.409423 ===================================
2100 20:14:29.412831 memory_type:LPDDR4
2101 20:14:29.413393 GP_NUM : 10
2102 20:14:29.416009 SRAM_EN : 1
2103 20:14:29.419316 MD32_EN : 0
2104 20:14:29.422476 ===================================
2105 20:14:29.423001 [ANA_INIT] >>>>>>>>>>>>>>
2106 20:14:29.425944 <<<<<< [CONFIGURE PHASE]: ANA_TX
2107 20:14:29.429412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2108 20:14:29.433243 ===================================
2109 20:14:29.436429 data_rate = 2400,PCW = 0X5b00
2110 20:14:29.439875 ===================================
2111 20:14:29.442346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2112 20:14:29.449616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2113 20:14:29.452827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2114 20:14:29.459153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2115 20:14:29.463122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2116 20:14:29.467210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2117 20:14:29.467783 [ANA_INIT] flow start
2118 20:14:29.469364 [ANA_INIT] PLL >>>>>>>>
2119 20:14:29.473355 [ANA_INIT] PLL <<<<<<<<
2120 20:14:29.473916 [ANA_INIT] MIDPI >>>>>>>>
2121 20:14:29.476186 [ANA_INIT] MIDPI <<<<<<<<
2122 20:14:29.479290 [ANA_INIT] DLL >>>>>>>>
2123 20:14:29.482716 [ANA_INIT] DLL <<<<<<<<
2124 20:14:29.483187 [ANA_INIT] flow end
2125 20:14:29.486213 ============ LP4 DIFF to SE enter ============
2126 20:14:29.492446 ============ LP4 DIFF to SE exit ============
2127 20:14:29.493064 [ANA_INIT] <<<<<<<<<<<<<
2128 20:14:29.495772 [Flow] Enable top DCM control >>>>>
2129 20:14:29.499425 [Flow] Enable top DCM control <<<<<
2130 20:14:29.502559 Enable DLL master slave shuffle
2131 20:14:29.509132 ==============================================================
2132 20:14:29.509701 Gating Mode config
2133 20:14:29.516399 ==============================================================
2134 20:14:29.519395 Config description:
2135 20:14:29.527197 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2136 20:14:29.532830 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2137 20:14:29.539753 SELPH_MODE 0: By rank 1: By Phase
2138 20:14:29.546427 ==============================================================
2139 20:14:29.549882 GAT_TRACK_EN = 1
2140 20:14:29.550652 RX_GATING_MODE = 2
2141 20:14:29.552691 RX_GATING_TRACK_MODE = 2
2142 20:14:29.555906 SELPH_MODE = 1
2143 20:14:29.559939 PICG_EARLY_EN = 1
2144 20:14:29.562616 VALID_LAT_VALUE = 1
2145 20:14:29.569052 ==============================================================
2146 20:14:29.572445 Enter into Gating configuration >>>>
2147 20:14:29.575594 Exit from Gating configuration <<<<
2148 20:14:29.578712 Enter into DVFS_PRE_config >>>>>
2149 20:14:29.589429 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2150 20:14:29.592324 Exit from DVFS_PRE_config <<<<<
2151 20:14:29.596036 Enter into PICG configuration >>>>
2152 20:14:29.599476 Exit from PICG configuration <<<<
2153 20:14:29.602310 [RX_INPUT] configuration >>>>>
2154 20:14:29.602790 [RX_INPUT] configuration <<<<<
2155 20:14:29.609111 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2156 20:14:29.616454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2157 20:14:29.619811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2158 20:14:29.625831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2159 20:14:29.632823 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2160 20:14:29.639912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2161 20:14:29.642527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2162 20:14:29.646495 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2163 20:14:29.652277 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2164 20:14:29.656300 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2165 20:14:29.659466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2166 20:14:29.662348 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 20:14:29.665699 ===================================
2168 20:14:29.669424 LPDDR4 DRAM CONFIGURATION
2169 20:14:29.672019 ===================================
2170 20:14:29.676266 EX_ROW_EN[0] = 0x0
2171 20:14:29.676894 EX_ROW_EN[1] = 0x0
2172 20:14:29.678814 LP4Y_EN = 0x0
2173 20:14:29.679288 WORK_FSP = 0x0
2174 20:14:29.682715 WL = 0x4
2175 20:14:29.683292 RL = 0x4
2176 20:14:29.685771 BL = 0x2
2177 20:14:29.689126 RPST = 0x0
2178 20:14:29.689707 RD_PRE = 0x0
2179 20:14:29.692112 WR_PRE = 0x1
2180 20:14:29.692588 WR_PST = 0x0
2181 20:14:29.695945 DBI_WR = 0x0
2182 20:14:29.696541 DBI_RD = 0x0
2183 20:14:29.699303 OTF = 0x1
2184 20:14:29.702688 ===================================
2185 20:14:29.705756 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2186 20:14:29.709276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2187 20:14:29.711817 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 20:14:29.715278 ===================================
2189 20:14:29.718638 LPDDR4 DRAM CONFIGURATION
2190 20:14:29.722374 ===================================
2191 20:14:29.725354 EX_ROW_EN[0] = 0x10
2192 20:14:29.725835 EX_ROW_EN[1] = 0x0
2193 20:14:29.729092 LP4Y_EN = 0x0
2194 20:14:29.729638 WORK_FSP = 0x0
2195 20:14:29.732606 WL = 0x4
2196 20:14:29.733148 RL = 0x4
2197 20:14:29.735427 BL = 0x2
2198 20:14:29.736011 RPST = 0x0
2199 20:14:29.739367 RD_PRE = 0x0
2200 20:14:29.742510 WR_PRE = 0x1
2201 20:14:29.743094 WR_PST = 0x0
2202 20:14:29.745309 DBI_WR = 0x0
2203 20:14:29.745786 DBI_RD = 0x0
2204 20:14:29.748695 OTF = 0x1
2205 20:14:29.751905 ===================================
2206 20:14:29.755058 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2207 20:14:29.758397 ==
2208 20:14:29.758972 Dram Type= 6, Freq= 0, CH_0, rank 0
2209 20:14:29.764891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2210 20:14:29.765376 ==
2211 20:14:29.768847 [Duty_Offset_Calibration]
2212 20:14:29.769321 B0:0 B1:2 CA:1
2213 20:14:29.769798
2214 20:14:29.772335 [DutyScan_Calibration_Flow] k_type=0
2215 20:14:29.781869
2216 20:14:29.782445 ==CLK 0==
2217 20:14:29.784944 Final CLK duty delay cell = 0
2218 20:14:29.788165 [0] MAX Duty = 5093%(X100), DQS PI = 12
2219 20:14:29.791712 [0] MIN Duty = 4938%(X100), DQS PI = 52
2220 20:14:29.792295 [0] AVG Duty = 5015%(X100)
2221 20:14:29.794778
2222 20:14:29.797964 CH0 CLK Duty spec in!! Max-Min= 155%
2223 20:14:29.801432 [DutyScan_Calibration_Flow] ====Done====
2224 20:14:29.802013
2225 20:14:29.804093 [DutyScan_Calibration_Flow] k_type=1
2226 20:14:29.820930
2227 20:14:29.821516 ==DQS 0 ==
2228 20:14:29.824051 Final DQS duty delay cell = 0
2229 20:14:29.828044 [0] MAX Duty = 5125%(X100), DQS PI = 30
2230 20:14:29.830861 [0] MIN Duty = 5031%(X100), DQS PI = 6
2231 20:14:29.831492 [0] AVG Duty = 5078%(X100)
2232 20:14:29.834138
2233 20:14:29.834698 ==DQS 1 ==
2234 20:14:29.837102 Final DQS duty delay cell = 0
2235 20:14:29.840624 [0] MAX Duty = 5031%(X100), DQS PI = 50
2236 20:14:29.844175 [0] MIN Duty = 4906%(X100), DQS PI = 16
2237 20:14:29.844702 [0] AVG Duty = 4968%(X100)
2238 20:14:29.847438
2239 20:14:29.850608 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2240 20:14:29.851127
2241 20:14:29.853887 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2242 20:14:29.856900 [DutyScan_Calibration_Flow] ====Done====
2243 20:14:29.857368
2244 20:14:29.859948 [DutyScan_Calibration_Flow] k_type=3
2245 20:14:29.876749
2246 20:14:29.877311 ==DQM 0 ==
2247 20:14:29.881103 Final DQM duty delay cell = 0
2248 20:14:29.884024 [0] MAX Duty = 5156%(X100), DQS PI = 20
2249 20:14:29.886890 [0] MIN Duty = 4969%(X100), DQS PI = 40
2250 20:14:29.890253 [0] AVG Duty = 5062%(X100)
2251 20:14:29.890731
2252 20:14:29.891316 ==DQM 1 ==
2253 20:14:29.893371 Final DQM duty delay cell = 0
2254 20:14:29.896524 [0] MAX Duty = 5000%(X100), DQS PI = 54
2255 20:14:29.900554 [0] MIN Duty = 4813%(X100), DQS PI = 22
2256 20:14:29.903553 [0] AVG Duty = 4906%(X100)
2257 20:14:29.904048
2258 20:14:29.906574 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2259 20:14:29.907051
2260 20:14:29.909975 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2261 20:14:29.913920 [DutyScan_Calibration_Flow] ====Done====
2262 20:14:29.914395
2263 20:14:29.916297 [DutyScan_Calibration_Flow] k_type=2
2264 20:14:29.931926
2265 20:14:29.932539 ==DQ 0 ==
2266 20:14:29.935615 Final DQ duty delay cell = -4
2267 20:14:29.938562 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2268 20:14:29.943084 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2269 20:14:29.945196 [-4] AVG Duty = 4937%(X100)
2270 20:14:29.945674
2271 20:14:29.946153 ==DQ 1 ==
2272 20:14:29.948945 Final DQ duty delay cell = -4
2273 20:14:29.951609 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2274 20:14:29.955104 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2275 20:14:29.958403 [-4] AVG Duty = 4969%(X100)
2276 20:14:29.958904
2277 20:14:29.962517 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2278 20:14:29.962993
2279 20:14:29.964807 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2280 20:14:29.968455 [DutyScan_Calibration_Flow] ====Done====
2281 20:14:29.968992 ==
2282 20:14:29.971592 Dram Type= 6, Freq= 0, CH_1, rank 0
2283 20:14:29.976475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2284 20:14:29.977116 ==
2285 20:14:29.979129 [Duty_Offset_Calibration]
2286 20:14:29.979605 B0:0 B1:4 CA:-5
2287 20:14:29.980088
2288 20:14:29.983815 [DutyScan_Calibration_Flow] k_type=0
2289 20:14:29.992363
2290 20:14:29.992988 ==CLK 0==
2291 20:14:29.995864 Final CLK duty delay cell = 0
2292 20:14:29.999073 [0] MAX Duty = 5094%(X100), DQS PI = 24
2293 20:14:30.002634 [0] MIN Duty = 4875%(X100), DQS PI = 46
2294 20:14:30.003212 [0] AVG Duty = 4984%(X100)
2295 20:14:30.006285
2296 20:14:30.008961 CH1 CLK Duty spec in!! Max-Min= 219%
2297 20:14:30.012900 [DutyScan_Calibration_Flow] ====Done====
2298 20:14:30.013472
2299 20:14:30.015601 [DutyScan_Calibration_Flow] k_type=1
2300 20:14:30.030987
2301 20:14:30.031566 ==DQS 0 ==
2302 20:14:30.034111 Final DQS duty delay cell = 0
2303 20:14:30.037881 [0] MAX Duty = 5125%(X100), DQS PI = 16
2304 20:14:30.040852 [0] MIN Duty = 4875%(X100), DQS PI = 42
2305 20:14:30.044278 [0] AVG Duty = 5000%(X100)
2306 20:14:30.044910
2307 20:14:30.045398 ==DQS 1 ==
2308 20:14:30.047863 Final DQS duty delay cell = -4
2309 20:14:30.051143 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2310 20:14:30.053861 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2311 20:14:30.057657 [-4] AVG Duty = 4953%(X100)
2312 20:14:30.058135
2313 20:14:30.060503 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2314 20:14:30.061078
2315 20:14:30.064339 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2316 20:14:30.067268 [DutyScan_Calibration_Flow] ====Done====
2317 20:14:30.067743
2318 20:14:30.070816 [DutyScan_Calibration_Flow] k_type=3
2319 20:14:30.085888
2320 20:14:30.086459 ==DQM 0 ==
2321 20:14:30.089533 Final DQM duty delay cell = -4
2322 20:14:30.092462 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2323 20:14:30.096449 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2324 20:14:30.099548 [-4] AVG Duty = 4969%(X100)
2325 20:14:30.100122
2326 20:14:30.100604 ==DQM 1 ==
2327 20:14:30.102498 Final DQM duty delay cell = -4
2328 20:14:30.105530 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2329 20:14:30.109474 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2330 20:14:30.112143 [-4] AVG Duty = 4984%(X100)
2331 20:14:30.112625
2332 20:14:30.116779 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2333 20:14:30.117352
2334 20:14:30.118893 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2335 20:14:30.122300 [DutyScan_Calibration_Flow] ====Done====
2336 20:14:30.122874
2337 20:14:30.126456 [DutyScan_Calibration_Flow] k_type=2
2338 20:14:30.143076
2339 20:14:30.143657 ==DQ 0 ==
2340 20:14:30.146069 Final DQ duty delay cell = 0
2341 20:14:30.149620 [0] MAX Duty = 5062%(X100), DQS PI = 0
2342 20:14:30.152808 [0] MIN Duty = 4969%(X100), DQS PI = 42
2343 20:14:30.153343 [0] AVG Duty = 5015%(X100)
2344 20:14:30.154029
2345 20:14:30.156680 ==DQ 1 ==
2346 20:14:30.160752 Final DQ duty delay cell = 0
2347 20:14:30.162841 [0] MAX Duty = 5031%(X100), DQS PI = 8
2348 20:14:30.166176 [0] MIN Duty = 4875%(X100), DQS PI = 30
2349 20:14:30.166738 [0] AVG Duty = 4953%(X100)
2350 20:14:30.167104
2351 20:14:30.170678 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2352 20:14:30.171144
2353 20:14:30.173244 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2354 20:14:30.179545 [DutyScan_Calibration_Flow] ====Done====
2355 20:14:30.183083 nWR fixed to 30
2356 20:14:30.183755 [ModeRegInit_LP4] CH0 RK0
2357 20:14:30.186247 [ModeRegInit_LP4] CH0 RK1
2358 20:14:30.189495 [ModeRegInit_LP4] CH1 RK0
2359 20:14:30.190110 [ModeRegInit_LP4] CH1 RK1
2360 20:14:30.193301 match AC timing 6
2361 20:14:30.196437 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2362 20:14:30.199364 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2363 20:14:30.205958 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2364 20:14:30.209119 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2365 20:14:30.216001 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2366 20:14:30.216173 ==
2367 20:14:30.219579 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 20:14:30.222420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2369 20:14:30.222601 ==
2370 20:14:30.229041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2371 20:14:30.232496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2372 20:14:30.242173 [CA 0] Center 39 (9~70) winsize 62
2373 20:14:30.245512 [CA 1] Center 39 (8~70) winsize 63
2374 20:14:30.248991 [CA 2] Center 36 (5~67) winsize 63
2375 20:14:30.252825 [CA 3] Center 35 (4~66) winsize 63
2376 20:14:30.255494 [CA 4] Center 34 (3~65) winsize 63
2377 20:14:30.259398 [CA 5] Center 33 (3~64) winsize 62
2378 20:14:30.259775
2379 20:14:30.263087 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2380 20:14:30.263445
2381 20:14:30.265978 [CATrainingPosCal] consider 1 rank data
2382 20:14:30.269648 u2DelayCellTimex100 = 270/100 ps
2383 20:14:30.272631 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2384 20:14:30.275914 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2385 20:14:30.283007 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2386 20:14:30.286147 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2387 20:14:30.289276 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2388 20:14:30.293035 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2389 20:14:30.293591
2390 20:14:30.296380 CA PerBit enable=1, Macro0, CA PI delay=33
2391 20:14:30.297091
2392 20:14:30.299126 [CBTSetCACLKResult] CA Dly = 33
2393 20:14:30.299580 CS Dly: 7 (0~38)
2394 20:14:30.299940 ==
2395 20:14:30.302919 Dram Type= 6, Freq= 0, CH_0, rank 1
2396 20:14:30.309407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2397 20:14:30.309966 ==
2398 20:14:30.312868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2399 20:14:30.319469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2400 20:14:30.328963 [CA 0] Center 39 (9~70) winsize 62
2401 20:14:30.331846 [CA 1] Center 39 (8~70) winsize 63
2402 20:14:30.334814 [CA 2] Center 36 (5~67) winsize 63
2403 20:14:30.338218 [CA 3] Center 35 (4~66) winsize 63
2404 20:14:30.341537 [CA 4] Center 33 (3~64) winsize 62
2405 20:14:30.345104 [CA 5] Center 33 (3~64) winsize 62
2406 20:14:30.345662
2407 20:14:30.348074 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2408 20:14:30.348634
2409 20:14:30.351613 [CATrainingPosCal] consider 2 rank data
2410 20:14:30.354355 u2DelayCellTimex100 = 270/100 ps
2411 20:14:30.358002 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2412 20:14:30.361426 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2413 20:14:30.367872 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2414 20:14:30.371899 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2415 20:14:30.374533 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2416 20:14:30.377876 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2417 20:14:30.378333
2418 20:14:30.381756 CA PerBit enable=1, Macro0, CA PI delay=33
2419 20:14:30.382314
2420 20:14:30.385510 [CBTSetCACLKResult] CA Dly = 33
2421 20:14:30.386171 CS Dly: 7 (0~39)
2422 20:14:30.386544
2423 20:14:30.387985 ----->DramcWriteLeveling(PI) begin...
2424 20:14:30.391426 ==
2425 20:14:30.394921 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 20:14:30.397913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 20:14:30.398377 ==
2428 20:14:30.401290 Write leveling (Byte 0): 26 => 26
2429 20:14:30.404503 Write leveling (Byte 1): 26 => 26
2430 20:14:30.408794 DramcWriteLeveling(PI) end<-----
2431 20:14:30.409415
2432 20:14:30.409790 ==
2433 20:14:30.411820 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 20:14:30.415762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 20:14:30.416324 ==
2436 20:14:30.419040 [Gating] SW mode calibration
2437 20:14:30.424926 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2438 20:14:30.428322 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2439 20:14:30.435125 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 20:14:30.438742 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 20:14:30.442078 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 20:14:30.448057 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 20:14:30.452110 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2444 20:14:30.455194 0 11 20 | B1->B0 | 2d2d 2c2c | 0 0 | (1 0) (0 0)
2445 20:14:30.461810 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 20:14:30.464643 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 20:14:30.469683 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 20:14:30.475477 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 20:14:30.478302 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 20:14:30.481630 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 20:14:30.488176 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 20:14:30.492460 0 12 20 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (1 1)
2453 20:14:30.495745 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 20:14:30.502448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 20:14:30.504577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 20:14:30.508094 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 20:14:30.515088 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 20:14:30.518085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 20:14:30.521091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2460 20:14:30.528019 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2461 20:14:30.531817 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2462 20:14:30.536166 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 20:14:30.538572 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 20:14:30.545406 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 20:14:30.547808 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 20:14:30.551558 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 20:14:30.557851 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 20:14:30.560913 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 20:14:30.565574 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 20:14:30.572100 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 20:14:30.575241 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 20:14:30.578237 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 20:14:30.585145 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 20:14:30.588242 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 20:14:30.592028 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 20:14:30.598211 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2477 20:14:30.602284 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2478 20:14:30.604413 Total UI for P1: 0, mck2ui 16
2479 20:14:30.608159 best dqsien dly found for B0: ( 0, 15, 20)
2480 20:14:30.610958 Total UI for P1: 0, mck2ui 16
2481 20:14:30.615140 best dqsien dly found for B1: ( 0, 15, 20)
2482 20:14:30.618835 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2483 20:14:30.621598 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2484 20:14:30.622164
2485 20:14:30.625005 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2486 20:14:30.627739 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2487 20:14:30.631407 [Gating] SW calibration Done
2488 20:14:30.631992 ==
2489 20:14:30.635459 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 20:14:30.637362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2491 20:14:30.640832 ==
2492 20:14:30.641305 RX Vref Scan: 0
2493 20:14:30.641674
2494 20:14:30.645086 RX Vref 0 -> 0, step: 1
2495 20:14:30.645654
2496 20:14:30.647953 RX Delay -40 -> 252, step: 8
2497 20:14:30.651456 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2498 20:14:30.654375 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2499 20:14:30.658033 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2500 20:14:30.661631 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2501 20:14:30.667485 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2502 20:14:30.670930 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2503 20:14:30.674202 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2504 20:14:30.677706 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2505 20:14:30.680662 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2506 20:14:30.684593 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2507 20:14:30.691437 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2508 20:14:30.694118 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2509 20:14:30.697517 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2510 20:14:30.700939 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2511 20:14:30.707962 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2512 20:14:30.711706 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2513 20:14:30.712265 ==
2514 20:14:30.714994 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 20:14:30.717560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2516 20:14:30.718038 ==
2517 20:14:30.718402 DQS Delay:
2518 20:14:30.721259 DQS0 = 0, DQS1 = 0
2519 20:14:30.721761 DQM Delay:
2520 20:14:30.724200 DQM0 = 115, DQM1 = 106
2521 20:14:30.724664 DQ Delay:
2522 20:14:30.727743 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2523 20:14:30.730849 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2524 20:14:30.733822 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2525 20:14:30.737588 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2526 20:14:30.740588
2527 20:14:30.741186
2528 20:14:30.741551 ==
2529 20:14:30.743932 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 20:14:30.748316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 20:14:30.748937 ==
2532 20:14:30.749313
2533 20:14:30.749654
2534 20:14:30.750801 TX Vref Scan disable
2535 20:14:30.751312 == TX Byte 0 ==
2536 20:14:30.757258 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2537 20:14:30.761265 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2538 20:14:30.761735 == TX Byte 1 ==
2539 20:14:30.767293 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2540 20:14:30.770589 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2541 20:14:30.771147 ==
2542 20:14:30.774461 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 20:14:30.778055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 20:14:30.778630 ==
2545 20:14:30.790060 TX Vref=22, minBit 1, minWin=25, winSum=413
2546 20:14:30.793413 TX Vref=24, minBit 12, minWin=24, winSum=413
2547 20:14:30.796039 TX Vref=26, minBit 10, minWin=25, winSum=423
2548 20:14:30.799316 TX Vref=28, minBit 5, minWin=26, winSum=430
2549 20:14:30.802692 TX Vref=30, minBit 4, minWin=26, winSum=429
2550 20:14:30.809263 TX Vref=32, minBit 10, minWin=25, winSum=427
2551 20:14:30.812703 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2552 20:14:30.813393
2553 20:14:30.816161 Final TX Range 1 Vref 28
2554 20:14:30.816988
2555 20:14:30.817395 ==
2556 20:14:30.819581 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 20:14:30.823391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2558 20:14:30.825632 ==
2559 20:14:30.826099
2560 20:14:30.826468
2561 20:14:30.826809 TX Vref Scan disable
2562 20:14:30.829381 == TX Byte 0 ==
2563 20:14:30.832947 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2564 20:14:30.836292 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2565 20:14:30.839744 == TX Byte 1 ==
2566 20:14:30.842906 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2567 20:14:30.845939 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2568 20:14:30.849201
2569 20:14:30.849670 [DATLAT]
2570 20:14:30.850042 Freq=1200, CH0 RK0
2571 20:14:30.850388
2572 20:14:30.853080 DATLAT Default: 0xd
2573 20:14:30.853642 0, 0xFFFF, sum = 0
2574 20:14:30.857105 1, 0xFFFF, sum = 0
2575 20:14:30.857729 2, 0xFFFF, sum = 0
2576 20:14:30.859442 3, 0xFFFF, sum = 0
2577 20:14:30.862274 4, 0xFFFF, sum = 0
2578 20:14:30.862751 5, 0xFFFF, sum = 0
2579 20:14:30.865750 6, 0xFFFF, sum = 0
2580 20:14:30.866321 7, 0xFFFF, sum = 0
2581 20:14:30.869122 8, 0xFFFF, sum = 0
2582 20:14:30.869693 9, 0xFFFF, sum = 0
2583 20:14:30.872218 10, 0xFFFF, sum = 0
2584 20:14:30.872693 11, 0x0, sum = 1
2585 20:14:30.876882 12, 0x0, sum = 2
2586 20:14:30.877447 13, 0x0, sum = 3
2587 20:14:30.878896 14, 0x0, sum = 4
2588 20:14:30.879371 best_step = 12
2589 20:14:30.879740
2590 20:14:30.880085 ==
2591 20:14:30.882625 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 20:14:30.885931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2593 20:14:30.886523 ==
2594 20:14:30.889480 RX Vref Scan: 1
2595 20:14:30.890067
2596 20:14:30.892467 Set Vref Range= 32 -> 127
2597 20:14:30.893080
2598 20:14:30.893457 RX Vref 32 -> 127, step: 1
2599 20:14:30.893807
2600 20:14:30.895983 RX Delay -21 -> 252, step: 4
2601 20:14:30.896566
2602 20:14:30.898998 Set Vref, RX VrefLevel [Byte0]: 32
2603 20:14:30.902529 [Byte1]: 32
2604 20:14:30.906134
2605 20:14:30.906726 Set Vref, RX VrefLevel [Byte0]: 33
2606 20:14:30.909060 [Byte1]: 33
2607 20:14:30.914404
2608 20:14:30.915191 Set Vref, RX VrefLevel [Byte0]: 34
2609 20:14:30.917564 [Byte1]: 34
2610 20:14:30.921935
2611 20:14:30.922497 Set Vref, RX VrefLevel [Byte0]: 35
2612 20:14:30.925305 [Byte1]: 35
2613 20:14:30.929874
2614 20:14:30.930336 Set Vref, RX VrefLevel [Byte0]: 36
2615 20:14:30.933092 [Byte1]: 36
2616 20:14:30.937576
2617 20:14:30.938041 Set Vref, RX VrefLevel [Byte0]: 37
2618 20:14:30.941354 [Byte1]: 37
2619 20:14:30.945468
2620 20:14:30.945928 Set Vref, RX VrefLevel [Byte0]: 38
2621 20:14:30.948831 [Byte1]: 38
2622 20:14:30.953986
2623 20:14:30.954559 Set Vref, RX VrefLevel [Byte0]: 39
2624 20:14:30.956921 [Byte1]: 39
2625 20:14:30.961551
2626 20:14:30.962022 Set Vref, RX VrefLevel [Byte0]: 40
2627 20:14:30.964779 [Byte1]: 40
2628 20:14:30.969886
2629 20:14:30.970444 Set Vref, RX VrefLevel [Byte0]: 41
2630 20:14:30.972748 [Byte1]: 41
2631 20:14:30.977601
2632 20:14:30.978275 Set Vref, RX VrefLevel [Byte0]: 42
2633 20:14:30.980664 [Byte1]: 42
2634 20:14:30.985942
2635 20:14:30.986505 Set Vref, RX VrefLevel [Byte0]: 43
2636 20:14:30.988526 [Byte1]: 43
2637 20:14:30.993564
2638 20:14:30.994126 Set Vref, RX VrefLevel [Byte0]: 44
2639 20:14:30.996646 [Byte1]: 44
2640 20:14:31.001718
2641 20:14:31.002200 Set Vref, RX VrefLevel [Byte0]: 45
2642 20:14:31.004445 [Byte1]: 45
2643 20:14:31.009134
2644 20:14:31.009750 Set Vref, RX VrefLevel [Byte0]: 46
2645 20:14:31.012587 [Byte1]: 46
2646 20:14:31.017134
2647 20:14:31.017695 Set Vref, RX VrefLevel [Byte0]: 47
2648 20:14:31.020187 [Byte1]: 47
2649 20:14:31.024990
2650 20:14:31.025552 Set Vref, RX VrefLevel [Byte0]: 48
2651 20:14:31.028598 [Byte1]: 48
2652 20:14:31.033362
2653 20:14:31.033919 Set Vref, RX VrefLevel [Byte0]: 49
2654 20:14:31.039286 [Byte1]: 49
2655 20:14:31.039884
2656 20:14:31.043125 Set Vref, RX VrefLevel [Byte0]: 50
2657 20:14:31.045843 [Byte1]: 50
2658 20:14:31.046314
2659 20:14:31.049449 Set Vref, RX VrefLevel [Byte0]: 51
2660 20:14:31.052612 [Byte1]: 51
2661 20:14:31.056974
2662 20:14:31.057524 Set Vref, RX VrefLevel [Byte0]: 52
2663 20:14:31.059595 [Byte1]: 52
2664 20:14:31.064699
2665 20:14:31.065322 Set Vref, RX VrefLevel [Byte0]: 53
2666 20:14:31.067683 [Byte1]: 53
2667 20:14:31.073101
2668 20:14:31.073659 Set Vref, RX VrefLevel [Byte0]: 54
2669 20:14:31.076052 [Byte1]: 54
2670 20:14:31.080518
2671 20:14:31.081149 Set Vref, RX VrefLevel [Byte0]: 55
2672 20:14:31.083569 [Byte1]: 55
2673 20:14:31.088314
2674 20:14:31.088915 Set Vref, RX VrefLevel [Byte0]: 56
2675 20:14:31.091931 [Byte1]: 56
2676 20:14:31.096655
2677 20:14:31.097261 Set Vref, RX VrefLevel [Byte0]: 57
2678 20:14:31.099656 [Byte1]: 57
2679 20:14:31.104205
2680 20:14:31.104806 Set Vref, RX VrefLevel [Byte0]: 58
2681 20:14:31.107269 [Byte1]: 58
2682 20:14:31.112020
2683 20:14:31.112483 Set Vref, RX VrefLevel [Byte0]: 59
2684 20:14:31.116145 [Byte1]: 59
2685 20:14:31.120339
2686 20:14:31.120994 Set Vref, RX VrefLevel [Byte0]: 60
2687 20:14:31.123537 [Byte1]: 60
2688 20:14:31.127749
2689 20:14:31.128473 Set Vref, RX VrefLevel [Byte0]: 61
2690 20:14:31.131391 [Byte1]: 61
2691 20:14:31.136176
2692 20:14:31.136786 Set Vref, RX VrefLevel [Byte0]: 62
2693 20:14:31.139201 [Byte1]: 62
2694 20:14:31.144729
2695 20:14:31.145294 Set Vref, RX VrefLevel [Byte0]: 63
2696 20:14:31.147401 [Byte1]: 63
2697 20:14:31.151783
2698 20:14:31.152349 Set Vref, RX VrefLevel [Byte0]: 64
2699 20:14:31.155047 [Byte1]: 64
2700 20:14:31.159435
2701 20:14:31.160168 Set Vref, RX VrefLevel [Byte0]: 65
2702 20:14:31.163148 [Byte1]: 65
2703 20:14:31.167743
2704 20:14:31.168303 Set Vref, RX VrefLevel [Byte0]: 66
2705 20:14:31.171548 [Byte1]: 66
2706 20:14:31.175543
2707 20:14:31.176123 Final RX Vref Byte 0 = 53 to rank0
2708 20:14:31.179349 Final RX Vref Byte 1 = 50 to rank0
2709 20:14:31.182197 Final RX Vref Byte 0 = 53 to rank1
2710 20:14:31.185637 Final RX Vref Byte 1 = 50 to rank1==
2711 20:14:31.188823 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 20:14:31.195652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2713 20:14:31.196222 ==
2714 20:14:31.196595 DQS Delay:
2715 20:14:31.197032 DQS0 = 0, DQS1 = 0
2716 20:14:31.198658 DQM Delay:
2717 20:14:31.199122 DQM0 = 114, DQM1 = 105
2718 20:14:31.201883 DQ Delay:
2719 20:14:31.205299 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2720 20:14:31.209190 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =120
2721 20:14:31.212295 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2722 20:14:31.215277 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2723 20:14:31.215844
2724 20:14:31.216209
2725 20:14:31.221701 [DQSOSCAuto] RK0, (LSB)MR18= 0x303, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2726 20:14:31.225197 CH0 RK0: MR19=404, MR18=303
2727 20:14:31.231958 CH0_RK0: MR19=0x404, MR18=0x303, DQSOSC=408, MR23=63, INC=39, DEC=26
2728 20:14:31.232526
2729 20:14:31.235221 ----->DramcWriteLeveling(PI) begin...
2730 20:14:31.235812 ==
2731 20:14:31.238426 Dram Type= 6, Freq= 0, CH_0, rank 1
2732 20:14:31.241609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2733 20:14:31.242079 ==
2734 20:14:31.245436 Write leveling (Byte 0): 27 => 27
2735 20:14:31.248506 Write leveling (Byte 1): 24 => 24
2736 20:14:31.253439 DramcWriteLeveling(PI) end<-----
2737 20:14:31.254079
2738 20:14:31.254451 ==
2739 20:14:31.255379 Dram Type= 6, Freq= 0, CH_0, rank 1
2740 20:14:31.262119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2741 20:14:31.262692 ==
2742 20:14:31.263065 [Gating] SW mode calibration
2743 20:14:31.271840 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2744 20:14:31.274936 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2745 20:14:31.279548 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2746 20:14:31.285184 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2747 20:14:31.288947 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 20:14:31.293022 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2749 20:14:31.298275 0 11 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2750 20:14:31.301464 0 11 20 | B1->B0 | 3131 2828 | 0 0 | (1 0) (1 0)
2751 20:14:31.305323 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2752 20:14:31.312271 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 20:14:31.315851 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 20:14:31.318509 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 20:14:31.325784 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 20:14:31.328516 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 20:14:31.332527 0 12 16 | B1->B0 | 2727 3736 | 0 1 | (0 0) (0 0)
2758 20:14:31.339653 0 12 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2759 20:14:31.342065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2760 20:14:31.345533 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 20:14:31.351953 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 20:14:31.355153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 20:14:31.358546 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 20:14:31.364611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 20:14:31.368355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2766 20:14:31.371769 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2767 20:14:31.378606 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 20:14:31.381790 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 20:14:31.384961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 20:14:31.388181 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 20:14:31.394667 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 20:14:31.398401 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 20:14:31.401502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 20:14:31.408509 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 20:14:31.411894 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 20:14:31.414977 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 20:14:31.421765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 20:14:31.425063 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 20:14:31.428434 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 20:14:31.435166 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 20:14:31.439694 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 20:14:31.441282 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2783 20:14:31.449249 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2784 20:14:31.449837 Total UI for P1: 0, mck2ui 16
2785 20:14:31.455321 best dqsien dly found for B0: ( 0, 15, 20)
2786 20:14:31.455927 Total UI for P1: 0, mck2ui 16
2787 20:14:31.458784 best dqsien dly found for B1: ( 0, 15, 20)
2788 20:14:31.464784 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2789 20:14:31.468314 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2790 20:14:31.468982
2791 20:14:31.472838 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2792 20:14:31.474940 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2793 20:14:31.478682 [Gating] SW calibration Done
2794 20:14:31.479261 ==
2795 20:14:31.481849 Dram Type= 6, Freq= 0, CH_0, rank 1
2796 20:14:31.484693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2797 20:14:31.485248 ==
2798 20:14:31.488489 RX Vref Scan: 0
2799 20:14:31.489169
2800 20:14:31.489663 RX Vref 0 -> 0, step: 1
2801 20:14:31.490124
2802 20:14:31.491212 RX Delay -40 -> 252, step: 8
2803 20:14:31.495358 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2804 20:14:31.501926 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2805 20:14:31.504646 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2806 20:14:31.507881 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2807 20:14:31.511057 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2808 20:14:31.514905 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2809 20:14:31.521723 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2810 20:14:31.525131 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2811 20:14:31.528190 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2812 20:14:31.531828 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2813 20:14:31.535122 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2814 20:14:31.538475 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2815 20:14:31.545690 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2816 20:14:31.547721 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2817 20:14:31.551510 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2818 20:14:31.555611 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2819 20:14:31.556188 ==
2820 20:14:31.557706 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 20:14:31.564969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2822 20:14:31.565548 ==
2823 20:14:31.565923 DQS Delay:
2824 20:14:31.568042 DQS0 = 0, DQS1 = 0
2825 20:14:31.568509 DQM Delay:
2826 20:14:31.571176 DQM0 = 115, DQM1 = 107
2827 20:14:31.571748 DQ Delay:
2828 20:14:31.575223 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =107
2829 20:14:31.577447 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2830 20:14:31.581252 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2831 20:14:31.585543 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2832 20:14:31.586016
2833 20:14:31.586385
2834 20:14:31.586725 ==
2835 20:14:31.587532 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 20:14:31.590871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2837 20:14:31.594548 ==
2838 20:14:31.595121
2839 20:14:31.595490
2840 20:14:31.595831 TX Vref Scan disable
2841 20:14:31.597842 == TX Byte 0 ==
2842 20:14:31.600840 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2843 20:14:31.604985 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2844 20:14:31.607850 == TX Byte 1 ==
2845 20:14:31.611187 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2846 20:14:31.614748 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2847 20:14:31.615327 ==
2848 20:14:31.618054 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 20:14:31.625015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2850 20:14:31.625591 ==
2851 20:14:31.635628 TX Vref=22, minBit 8, minWin=25, winSum=418
2852 20:14:31.638723 TX Vref=24, minBit 8, minWin=25, winSum=423
2853 20:14:31.641980 TX Vref=26, minBit 9, minWin=25, winSum=426
2854 20:14:31.645511 TX Vref=28, minBit 8, minWin=26, winSum=429
2855 20:14:31.648874 TX Vref=30, minBit 10, minWin=25, winSum=433
2856 20:14:31.656917 TX Vref=32, minBit 8, minWin=26, winSum=435
2857 20:14:31.658683 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 32
2858 20:14:31.659177
2859 20:14:31.662022 Final TX Range 1 Vref 32
2860 20:14:31.662719
2861 20:14:31.663112 ==
2862 20:14:31.665811 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 20:14:31.668764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2864 20:14:31.669347 ==
2865 20:14:31.672398
2866 20:14:31.673028
2867 20:14:31.673401 TX Vref Scan disable
2868 20:14:31.676131 == TX Byte 0 ==
2869 20:14:31.678851 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2870 20:14:31.685883 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2871 20:14:31.686465 == TX Byte 1 ==
2872 20:14:31.688501 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2873 20:14:31.695363 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2874 20:14:31.695925
2875 20:14:31.696297 [DATLAT]
2876 20:14:31.696640 Freq=1200, CH0 RK1
2877 20:14:31.697009
2878 20:14:31.698848 DATLAT Default: 0xc
2879 20:14:31.699314 0, 0xFFFF, sum = 0
2880 20:14:31.701517 1, 0xFFFF, sum = 0
2881 20:14:31.705473 2, 0xFFFF, sum = 0
2882 20:14:31.706054 3, 0xFFFF, sum = 0
2883 20:14:31.708569 4, 0xFFFF, sum = 0
2884 20:14:31.709081 5, 0xFFFF, sum = 0
2885 20:14:31.711767 6, 0xFFFF, sum = 0
2886 20:14:31.712346 7, 0xFFFF, sum = 0
2887 20:14:31.715807 8, 0xFFFF, sum = 0
2888 20:14:31.716388 9, 0xFFFF, sum = 0
2889 20:14:31.718898 10, 0xFFFF, sum = 0
2890 20:14:31.719478 11, 0x0, sum = 1
2891 20:14:31.721930 12, 0x0, sum = 2
2892 20:14:31.722405 13, 0x0, sum = 3
2893 20:14:31.724986 14, 0x0, sum = 4
2894 20:14:31.725563 best_step = 12
2895 20:14:31.725934
2896 20:14:31.726275 ==
2897 20:14:31.728177 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 20:14:31.731643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2899 20:14:31.732115 ==
2900 20:14:31.735694 RX Vref Scan: 0
2901 20:14:31.736268
2902 20:14:31.738114 RX Vref 0 -> 0, step: 1
2903 20:14:31.738583
2904 20:14:31.738952 RX Delay -21 -> 252, step: 4
2905 20:14:31.745651 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2906 20:14:31.749457 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2907 20:14:31.752304 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2908 20:14:31.755480 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2909 20:14:31.759344 iDelay=199, Bit 4, Center 120 (47 ~ 194) 148
2910 20:14:31.765781 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2911 20:14:31.770034 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2912 20:14:31.772587 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2913 20:14:31.776382 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2914 20:14:31.779321 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2915 20:14:31.785542 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2916 20:14:31.788911 iDelay=199, Bit 11, Center 98 (35 ~ 162) 128
2917 20:14:31.792379 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2918 20:14:31.795864 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2919 20:14:31.799137 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2920 20:14:31.807691 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
2921 20:14:31.808288 ==
2922 20:14:31.809121 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 20:14:31.812418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2924 20:14:31.812932 ==
2925 20:14:31.813306 DQS Delay:
2926 20:14:31.815561 DQS0 = 0, DQS1 = 0
2927 20:14:31.816024 DQM Delay:
2928 20:14:31.819251 DQM0 = 115, DQM1 = 106
2929 20:14:31.819795 DQ Delay:
2930 20:14:31.822056 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2931 20:14:31.825951 DQ4 =120, DQ5 =108, DQ6 =122, DQ7 =124
2932 20:14:31.829256 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =98
2933 20:14:31.832170 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2934 20:14:31.832772
2935 20:14:31.833155
2936 20:14:31.842987 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2937 20:14:31.845617 CH0 RK1: MR19=404, MR18=C0C
2938 20:14:31.848933 CH0_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2939 20:14:31.852194 [RxdqsGatingPostProcess] freq 1200
2940 20:14:31.859260 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2941 20:14:31.862176 Pre-setting of DQS Precalculation
2942 20:14:31.865468 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2943 20:14:31.865945 ==
2944 20:14:31.868788 Dram Type= 6, Freq= 0, CH_1, rank 0
2945 20:14:31.875355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2946 20:14:31.875949 ==
2947 20:14:31.879261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2948 20:14:31.885339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2949 20:14:31.894152 [CA 0] Center 37 (7~68) winsize 62
2950 20:14:31.897641 [CA 1] Center 37 (7~68) winsize 62
2951 20:14:31.901090 [CA 2] Center 34 (4~65) winsize 62
2952 20:14:31.904134 [CA 3] Center 33 (3~64) winsize 62
2953 20:14:31.908497 [CA 4] Center 32 (2~63) winsize 62
2954 20:14:31.910613 [CA 5] Center 32 (1~63) winsize 63
2955 20:14:31.911098
2956 20:14:31.913801 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2957 20:14:31.914369
2958 20:14:31.917320 [CATrainingPosCal] consider 1 rank data
2959 20:14:31.920640 u2DelayCellTimex100 = 270/100 ps
2960 20:14:31.923896 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2961 20:14:31.930924 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2962 20:14:31.934013 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2963 20:14:31.937031 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2964 20:14:31.940525 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2965 20:14:31.944502 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2966 20:14:31.945175
2967 20:14:31.947445 CA PerBit enable=1, Macro0, CA PI delay=32
2968 20:14:31.948023
2969 20:14:31.950397 [CBTSetCACLKResult] CA Dly = 32
2970 20:14:31.950996 CS Dly: 5 (0~36)
2971 20:14:31.953675 ==
2972 20:14:31.957176 Dram Type= 6, Freq= 0, CH_1, rank 1
2973 20:14:31.960564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2974 20:14:31.961222 ==
2975 20:14:31.963729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2976 20:14:31.970972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2977 20:14:31.979628 [CA 0] Center 37 (7~68) winsize 62
2978 20:14:31.982831 [CA 1] Center 37 (7~68) winsize 62
2979 20:14:31.985881 [CA 2] Center 34 (3~65) winsize 63
2980 20:14:31.989420 [CA 3] Center 33 (3~64) winsize 62
2981 20:14:31.992890 [CA 4] Center 32 (2~63) winsize 62
2982 20:14:31.996752 [CA 5] Center 32 (1~63) winsize 63
2983 20:14:31.997331
2984 20:14:31.999537 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2985 20:14:32.000025
2986 20:14:32.002504 [CATrainingPosCal] consider 2 rank data
2987 20:14:32.006132 u2DelayCellTimex100 = 270/100 ps
2988 20:14:32.009202 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2989 20:14:32.012298 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2990 20:14:32.019174 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2991 20:14:32.022757 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2992 20:14:32.025697 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2993 20:14:32.029216 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2994 20:14:32.029685
2995 20:14:32.032638 CA PerBit enable=1, Macro0, CA PI delay=32
2996 20:14:32.033220
2997 20:14:32.035989 [CBTSetCACLKResult] CA Dly = 32
2998 20:14:32.036453 CS Dly: 6 (0~38)
2999 20:14:32.036864
3000 20:14:32.039403 ----->DramcWriteLeveling(PI) begin...
3001 20:14:32.042133 ==
3002 20:14:32.046169 Dram Type= 6, Freq= 0, CH_1, rank 0
3003 20:14:32.049284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3004 20:14:32.049850 ==
3005 20:14:32.052393 Write leveling (Byte 0): 21 => 21
3006 20:14:32.055695 Write leveling (Byte 1): 21 => 21
3007 20:14:32.060130 DramcWriteLeveling(PI) end<-----
3008 20:14:32.060595
3009 20:14:32.061023 ==
3010 20:14:32.063689 Dram Type= 6, Freq= 0, CH_1, rank 0
3011 20:14:32.065518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3012 20:14:32.066038 ==
3013 20:14:32.069182 [Gating] SW mode calibration
3014 20:14:32.075501 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3015 20:14:32.083100 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3016 20:14:32.085573 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3017 20:14:32.089222 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 20:14:32.095540 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 20:14:32.099232 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3020 20:14:32.102681 0 11 16 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
3021 20:14:32.105498 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3022 20:14:32.112115 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 20:14:32.115327 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 20:14:32.118619 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 20:14:32.125089 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 20:14:32.128542 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 20:14:32.131895 0 12 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3028 20:14:32.138436 0 12 16 | B1->B0 | 3636 3f3f | 1 0 | (0 0) (0 0)
3029 20:14:32.141792 0 12 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3030 20:14:32.145711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 20:14:32.152032 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 20:14:32.155890 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 20:14:32.158634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 20:14:32.165423 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 20:14:32.168694 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 20:14:32.173023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3037 20:14:32.179269 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 20:14:32.182221 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 20:14:32.186919 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 20:14:32.192448 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 20:14:32.195832 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 20:14:32.198975 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 20:14:32.205997 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 20:14:32.208534 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 20:14:32.212167 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 20:14:32.219348 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 20:14:32.222307 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 20:14:32.225909 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 20:14:32.228309 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 20:14:32.235099 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 20:14:32.241496 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 20:14:32.242414 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3053 20:14:32.248292 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3054 20:14:32.252015 Total UI for P1: 0, mck2ui 16
3055 20:14:32.254943 best dqsien dly found for B0: ( 0, 15, 16)
3056 20:14:32.258292 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3057 20:14:32.262065 Total UI for P1: 0, mck2ui 16
3058 20:14:32.264862 best dqsien dly found for B1: ( 0, 15, 20)
3059 20:14:32.268553 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3060 20:14:32.272302 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3061 20:14:32.272948
3062 20:14:32.275536 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3063 20:14:32.279563 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3064 20:14:32.281755 [Gating] SW calibration Done
3065 20:14:32.282219 ==
3066 20:14:32.285232 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 20:14:32.291724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3068 20:14:32.292289 ==
3069 20:14:32.292661 RX Vref Scan: 0
3070 20:14:32.293062
3071 20:14:32.295608 RX Vref 0 -> 0, step: 1
3072 20:14:32.296185
3073 20:14:32.298628 RX Delay -40 -> 252, step: 8
3074 20:14:32.301873 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3075 20:14:32.304995 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3076 20:14:32.308376 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3077 20:14:32.311695 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3078 20:14:32.318833 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3079 20:14:32.321586 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3080 20:14:32.325401 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3081 20:14:32.328398 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3082 20:14:32.331736 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3083 20:14:32.338808 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3084 20:14:32.341611 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3085 20:14:32.345599 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3086 20:14:32.348258 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3087 20:14:32.351491 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3088 20:14:32.358517 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3089 20:14:32.362149 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3090 20:14:32.362713 ==
3091 20:14:32.365678 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 20:14:32.368270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3093 20:14:32.368897 ==
3094 20:14:32.371510 DQS Delay:
3095 20:14:32.372010 DQS0 = 0, DQS1 = 0
3096 20:14:32.372494 DQM Delay:
3097 20:14:32.375615 DQM0 = 116, DQM1 = 110
3098 20:14:32.376268 DQ Delay:
3099 20:14:32.378157 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3100 20:14:32.382165 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3101 20:14:32.384870 DQ8 =91, DQ9 =103, DQ10 =111, DQ11 =99
3102 20:14:32.391576 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3103 20:14:32.392126
3104 20:14:32.392494
3105 20:14:32.392885 ==
3106 20:14:32.395254 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 20:14:32.398169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 20:14:32.398640 ==
3109 20:14:32.399007
3110 20:14:32.399349
3111 20:14:32.401785 TX Vref Scan disable
3112 20:14:32.402274 == TX Byte 0 ==
3113 20:14:32.408208 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3114 20:14:32.411986 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3115 20:14:32.412452 == TX Byte 1 ==
3116 20:14:32.418720 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3117 20:14:32.421789 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3118 20:14:32.422342 ==
3119 20:14:32.424902 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 20:14:32.428117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 20:14:32.428675 ==
3122 20:14:32.440489 TX Vref=22, minBit 3, minWin=25, winSum=415
3123 20:14:32.444170 TX Vref=24, minBit 11, minWin=25, winSum=420
3124 20:14:32.447249 TX Vref=26, minBit 3, minWin=25, winSum=424
3125 20:14:32.451114 TX Vref=28, minBit 0, minWin=26, winSum=431
3126 20:14:32.453698 TX Vref=30, minBit 1, minWin=26, winSum=427
3127 20:14:32.457456 TX Vref=32, minBit 9, minWin=25, winSum=429
3128 20:14:32.464174 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
3129 20:14:32.464778
3130 20:14:32.466897 Final TX Range 1 Vref 28
3131 20:14:32.467643
3132 20:14:32.468075 ==
3133 20:14:32.470631 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 20:14:32.473643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3135 20:14:32.474193 ==
3136 20:14:32.474561
3137 20:14:32.477072
3138 20:14:32.477532 TX Vref Scan disable
3139 20:14:32.480543 == TX Byte 0 ==
3140 20:14:32.483697 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3141 20:14:32.487033 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3142 20:14:32.490365 == TX Byte 1 ==
3143 20:14:32.493558 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3144 20:14:32.497632 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3145 20:14:32.498200
3146 20:14:32.500647 [DATLAT]
3147 20:14:32.501294 Freq=1200, CH1 RK0
3148 20:14:32.501677
3149 20:14:32.503792 DATLAT Default: 0xd
3150 20:14:32.504418 0, 0xFFFF, sum = 0
3151 20:14:32.507273 1, 0xFFFF, sum = 0
3152 20:14:32.508007 2, 0xFFFF, sum = 0
3153 20:14:32.510021 3, 0xFFFF, sum = 0
3154 20:14:32.510492 4, 0xFFFF, sum = 0
3155 20:14:32.513915 5, 0xFFFF, sum = 0
3156 20:14:32.514545 6, 0xFFFF, sum = 0
3157 20:14:32.516663 7, 0xFFFF, sum = 0
3158 20:14:32.520458 8, 0xFFFF, sum = 0
3159 20:14:32.521004 9, 0xFFFF, sum = 0
3160 20:14:32.523951 10, 0xFFFF, sum = 0
3161 20:14:32.524517 11, 0x0, sum = 1
3162 20:14:32.526856 12, 0x0, sum = 2
3163 20:14:32.527419 13, 0x0, sum = 3
3164 20:14:32.527793 14, 0x0, sum = 4
3165 20:14:32.530265 best_step = 12
3166 20:14:32.530729
3167 20:14:32.531091 ==
3168 20:14:32.533363 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 20:14:32.537377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3170 20:14:32.537933 ==
3171 20:14:32.540270 RX Vref Scan: 1
3172 20:14:32.540774
3173 20:14:32.544341 Set Vref Range= 32 -> 127
3174 20:14:32.544962
3175 20:14:32.545341 RX Vref 32 -> 127, step: 1
3176 20:14:32.545687
3177 20:14:32.546631 RX Delay -21 -> 252, step: 4
3178 20:14:32.547025
3179 20:14:32.549848 Set Vref, RX VrefLevel [Byte0]: 32
3180 20:14:32.553549 [Byte1]: 32
3181 20:14:32.556806
3182 20:14:32.557269 Set Vref, RX VrefLevel [Byte0]: 33
3183 20:14:32.560101 [Byte1]: 33
3184 20:14:32.564700
3185 20:14:32.565158 Set Vref, RX VrefLevel [Byte0]: 34
3186 20:14:32.568365 [Byte1]: 34
3187 20:14:32.572668
3188 20:14:32.573200 Set Vref, RX VrefLevel [Byte0]: 35
3189 20:14:32.576396 [Byte1]: 35
3190 20:14:32.580557
3191 20:14:32.581194 Set Vref, RX VrefLevel [Byte0]: 36
3192 20:14:32.584600 [Byte1]: 36
3193 20:14:32.589054
3194 20:14:32.589624 Set Vref, RX VrefLevel [Byte0]: 37
3195 20:14:32.592060 [Byte1]: 37
3196 20:14:32.596406
3197 20:14:32.597067 Set Vref, RX VrefLevel [Byte0]: 38
3198 20:14:32.600036 [Byte1]: 38
3199 20:14:32.604351
3200 20:14:32.604978 Set Vref, RX VrefLevel [Byte0]: 39
3201 20:14:32.607652 [Byte1]: 39
3202 20:14:32.612338
3203 20:14:32.612872 Set Vref, RX VrefLevel [Byte0]: 40
3204 20:14:32.615812 [Byte1]: 40
3205 20:14:32.620832
3206 20:14:32.621463 Set Vref, RX VrefLevel [Byte0]: 41
3207 20:14:32.623470 [Byte1]: 41
3208 20:14:32.628263
3209 20:14:32.628927 Set Vref, RX VrefLevel [Byte0]: 42
3210 20:14:32.632011 [Byte1]: 42
3211 20:14:32.635948
3212 20:14:32.636412 Set Vref, RX VrefLevel [Byte0]: 43
3213 20:14:32.639016 [Byte1]: 43
3214 20:14:32.644579
3215 20:14:32.645188 Set Vref, RX VrefLevel [Byte0]: 44
3216 20:14:32.647387 [Byte1]: 44
3217 20:14:32.652390
3218 20:14:32.653014 Set Vref, RX VrefLevel [Byte0]: 45
3219 20:14:32.655481 [Byte1]: 45
3220 20:14:32.659992
3221 20:14:32.660470 Set Vref, RX VrefLevel [Byte0]: 46
3222 20:14:32.663796 [Byte1]: 46
3223 20:14:32.667573
3224 20:14:32.668053 Set Vref, RX VrefLevel [Byte0]: 47
3225 20:14:32.673504 [Byte1]: 47
3226 20:14:32.676025
3227 20:14:32.676768 Set Vref, RX VrefLevel [Byte0]: 48
3228 20:14:32.679110 [Byte1]: 48
3229 20:14:32.684129
3230 20:14:32.684696 Set Vref, RX VrefLevel [Byte0]: 49
3231 20:14:32.690330 [Byte1]: 49
3232 20:14:32.690898
3233 20:14:32.693351 Set Vref, RX VrefLevel [Byte0]: 50
3234 20:14:32.696644 [Byte1]: 50
3235 20:14:32.697387
3236 20:14:32.700020 Set Vref, RX VrefLevel [Byte0]: 51
3237 20:14:32.703369 [Byte1]: 51
3238 20:14:32.707212
3239 20:14:32.707678 Set Vref, RX VrefLevel [Byte0]: 52
3240 20:14:32.710514 [Byte1]: 52
3241 20:14:32.715298
3242 20:14:32.715764 Set Vref, RX VrefLevel [Byte0]: 53
3243 20:14:32.719112 [Byte1]: 53
3244 20:14:32.722975
3245 20:14:32.723637 Set Vref, RX VrefLevel [Byte0]: 54
3246 20:14:32.726394 [Byte1]: 54
3247 20:14:32.731010
3248 20:14:32.731526 Set Vref, RX VrefLevel [Byte0]: 55
3249 20:14:32.734549 [Byte1]: 55
3250 20:14:32.738840
3251 20:14:32.739492 Set Vref, RX VrefLevel [Byte0]: 56
3252 20:14:32.742424 [Byte1]: 56
3253 20:14:32.746564
3254 20:14:32.747086 Set Vref, RX VrefLevel [Byte0]: 57
3255 20:14:32.751168 [Byte1]: 57
3256 20:14:32.755099
3257 20:14:32.755624 Set Vref, RX VrefLevel [Byte0]: 58
3258 20:14:32.759204 [Byte1]: 58
3259 20:14:32.763026
3260 20:14:32.763547 Set Vref, RX VrefLevel [Byte0]: 59
3261 20:14:32.766503 [Byte1]: 59
3262 20:14:32.770943
3263 20:14:32.771470 Set Vref, RX VrefLevel [Byte0]: 60
3264 20:14:32.774661 [Byte1]: 60
3265 20:14:32.778906
3266 20:14:32.779428 Set Vref, RX VrefLevel [Byte0]: 61
3267 20:14:32.781898 [Byte1]: 61
3268 20:14:32.787086
3269 20:14:32.787613 Set Vref, RX VrefLevel [Byte0]: 62
3270 20:14:32.790336 [Byte1]: 62
3271 20:14:32.794422
3272 20:14:32.794841 Set Vref, RX VrefLevel [Byte0]: 63
3273 20:14:32.797671 [Byte1]: 63
3274 20:14:32.802377
3275 20:14:32.802809 Set Vref, RX VrefLevel [Byte0]: 64
3276 20:14:32.805763 [Byte1]: 64
3277 20:14:32.810096
3278 20:14:32.810562 Final RX Vref Byte 0 = 55 to rank0
3279 20:14:32.813229 Final RX Vref Byte 1 = 49 to rank0
3280 20:14:32.816673 Final RX Vref Byte 0 = 55 to rank1
3281 20:14:32.820382 Final RX Vref Byte 1 = 49 to rank1==
3282 20:14:32.823693 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 20:14:32.830318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3284 20:14:32.830852 ==
3285 20:14:32.831188 DQS Delay:
3286 20:14:32.831499 DQS0 = 0, DQS1 = 0
3287 20:14:32.833284 DQM Delay:
3288 20:14:32.833705 DQM0 = 115, DQM1 = 106
3289 20:14:32.837139 DQ Delay:
3290 20:14:32.839970 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3291 20:14:32.843936 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3292 20:14:32.846662 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3293 20:14:32.850514 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3294 20:14:32.850982
3295 20:14:32.851316
3296 20:14:32.856929 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3297 20:14:32.860445 CH1 RK0: MR19=404, MR18=1414
3298 20:14:32.866887 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3299 20:14:32.867398
3300 20:14:32.871008 ----->DramcWriteLeveling(PI) begin...
3301 20:14:32.871436 ==
3302 20:14:32.874124 Dram Type= 6, Freq= 0, CH_1, rank 1
3303 20:14:32.876899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3304 20:14:32.880818 ==
3305 20:14:32.881245 Write leveling (Byte 0): 22 => 22
3306 20:14:32.884084 Write leveling (Byte 1): 22 => 22
3307 20:14:32.887195 DramcWriteLeveling(PI) end<-----
3308 20:14:32.887721
3309 20:14:32.888056 ==
3310 20:14:32.890249 Dram Type= 6, Freq= 0, CH_1, rank 1
3311 20:14:32.897653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3312 20:14:32.898186 ==
3313 20:14:32.898524 [Gating] SW mode calibration
3314 20:14:32.907217 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3315 20:14:32.909945 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3316 20:14:32.913622 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3317 20:14:32.920226 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3318 20:14:32.923787 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3319 20:14:32.926474 0 11 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3320 20:14:32.933416 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3321 20:14:32.936827 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3322 20:14:32.939944 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3323 20:14:32.947419 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3324 20:14:32.950375 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3325 20:14:32.953239 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3326 20:14:32.960656 0 12 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3327 20:14:32.963822 0 12 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3328 20:14:32.967424 0 12 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3329 20:14:32.973582 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3330 20:14:32.977101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3331 20:14:32.980401 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3332 20:14:32.986822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3333 20:14:32.990413 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 20:14:32.993247 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 20:14:32.999860 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3336 20:14:33.003569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3337 20:14:33.006820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3338 20:14:33.009918 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 20:14:33.016596 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3340 20:14:33.020232 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3341 20:14:33.026815 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 20:14:33.029698 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 20:14:33.033903 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 20:14:33.036544 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 20:14:33.043327 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 20:14:33.046212 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 20:14:33.050441 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 20:14:33.056552 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 20:14:33.059710 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 20:14:33.062868 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 20:14:33.069868 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3352 20:14:33.073510 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3353 20:14:33.076210 Total UI for P1: 0, mck2ui 16
3354 20:14:33.079127 best dqsien dly found for B0: ( 0, 15, 12)
3355 20:14:33.082561 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3356 20:14:33.089593 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3357 20:14:33.092824 Total UI for P1: 0, mck2ui 16
3358 20:14:33.096462 best dqsien dly found for B1: ( 0, 15, 18)
3359 20:14:33.098961 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3360 20:14:33.102910 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3361 20:14:33.103453
3362 20:14:33.106463 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3363 20:14:33.109010 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3364 20:14:33.112422 [Gating] SW calibration Done
3365 20:14:33.112981 ==
3366 20:14:33.115468 Dram Type= 6, Freq= 0, CH_1, rank 1
3367 20:14:33.118431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3368 20:14:33.118721 ==
3369 20:14:33.123901 RX Vref Scan: 0
3370 20:14:33.124166
3371 20:14:33.125031 RX Vref 0 -> 0, step: 1
3372 20:14:33.125216
3373 20:14:33.125360 RX Delay -40 -> 252, step: 8
3374 20:14:33.132638 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3375 20:14:33.135869 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3376 20:14:33.139712 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3377 20:14:33.141987 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3378 20:14:33.145256 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3379 20:14:33.151974 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3380 20:14:33.154827 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3381 20:14:33.158305 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3382 20:14:33.161922 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3383 20:14:33.165447 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3384 20:14:33.171524 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3385 20:14:33.175485 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3386 20:14:33.179488 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3387 20:14:33.182568 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3388 20:14:33.185313 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3389 20:14:33.192110 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3390 20:14:33.192554 ==
3391 20:14:33.195012 Dram Type= 6, Freq= 0, CH_1, rank 1
3392 20:14:33.198813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3393 20:14:33.199284 ==
3394 20:14:33.199624 DQS Delay:
3395 20:14:33.202120 DQS0 = 0, DQS1 = 0
3396 20:14:33.202540 DQM Delay:
3397 20:14:33.205758 DQM0 = 115, DQM1 = 106
3398 20:14:33.206177 DQ Delay:
3399 20:14:33.208646 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3400 20:14:33.211908 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3401 20:14:33.215213 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3402 20:14:33.219282 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3403 20:14:33.219817
3404 20:14:33.220148
3405 20:14:33.222068 ==
3406 20:14:33.225275 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 20:14:33.228808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3408 20:14:33.229382 ==
3409 20:14:33.229834
3410 20:14:33.230268
3411 20:14:33.231810 TX Vref Scan disable
3412 20:14:33.232396 == TX Byte 0 ==
3413 20:14:33.235467 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3414 20:14:33.241800 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3415 20:14:33.242319 == TX Byte 1 ==
3416 20:14:33.245550 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3417 20:14:33.252105 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3418 20:14:33.252667 ==
3419 20:14:33.255205 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 20:14:33.258652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 20:14:33.259110 ==
3422 20:14:33.270525 TX Vref=22, minBit 1, minWin=25, winSum=418
3423 20:14:33.273904 TX Vref=24, minBit 0, minWin=26, winSum=425
3424 20:14:33.277015 TX Vref=26, minBit 3, minWin=26, winSum=428
3425 20:14:33.280419 TX Vref=28, minBit 8, minWin=26, winSum=432
3426 20:14:33.284235 TX Vref=30, minBit 0, minWin=26, winSum=432
3427 20:14:33.290846 TX Vref=32, minBit 9, minWin=26, winSum=432
3428 20:14:33.293689 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3429 20:14:33.294256
3430 20:14:33.297234 Final TX Range 1 Vref 28
3431 20:14:33.297696
3432 20:14:33.298056 ==
3433 20:14:33.300536 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 20:14:33.303729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3435 20:14:33.304295 ==
3436 20:14:33.304659
3437 20:14:33.306943
3438 20:14:33.307448 TX Vref Scan disable
3439 20:14:33.310151 == TX Byte 0 ==
3440 20:14:33.313507 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3441 20:14:33.317897 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3442 20:14:33.320188 == TX Byte 1 ==
3443 20:14:33.324261 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3444 20:14:33.326899 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3445 20:14:33.327364
3446 20:14:33.331097 [DATLAT]
3447 20:14:33.331798 Freq=1200, CH1 RK1
3448 20:14:33.332254
3449 20:14:33.334265 DATLAT Default: 0xc
3450 20:14:33.334726 0, 0xFFFF, sum = 0
3451 20:14:33.337713 1, 0xFFFF, sum = 0
3452 20:14:33.338181 2, 0xFFFF, sum = 0
3453 20:14:33.340088 3, 0xFFFF, sum = 0
3454 20:14:33.340553 4, 0xFFFF, sum = 0
3455 20:14:33.343635 5, 0xFFFF, sum = 0
3456 20:14:33.344100 6, 0xFFFF, sum = 0
3457 20:14:33.346924 7, 0xFFFF, sum = 0
3458 20:14:33.350105 8, 0xFFFF, sum = 0
3459 20:14:33.350571 9, 0xFFFF, sum = 0
3460 20:14:33.353266 10, 0xFFFF, sum = 0
3461 20:14:33.353689 11, 0x0, sum = 1
3462 20:14:33.356400 12, 0x0, sum = 2
3463 20:14:33.356855 13, 0x0, sum = 3
3464 20:14:33.357193 14, 0x0, sum = 4
3465 20:14:33.360122 best_step = 12
3466 20:14:33.360536
3467 20:14:33.360912 ==
3468 20:14:33.363866 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 20:14:33.366641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3470 20:14:33.367181 ==
3471 20:14:33.369561 RX Vref Scan: 0
3472 20:14:33.369976
3473 20:14:33.370299 RX Vref 0 -> 0, step: 1
3474 20:14:33.373311
3475 20:14:33.373862 RX Delay -29 -> 252, step: 4
3476 20:14:33.380280 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3477 20:14:33.384255 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3478 20:14:33.387390 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3479 20:14:33.390600 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3480 20:14:33.393878 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3481 20:14:33.400988 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3482 20:14:33.404868 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3483 20:14:33.407746 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3484 20:14:33.410900 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3485 20:14:33.413979 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3486 20:14:33.420566 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3487 20:14:33.423755 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3488 20:14:33.427488 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3489 20:14:33.431725 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3490 20:14:33.434033 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3491 20:14:33.440492 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3492 20:14:33.441071 ==
3493 20:14:33.443927 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 20:14:33.447718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3495 20:14:33.448141 ==
3496 20:14:33.448471 DQS Delay:
3497 20:14:33.450400 DQS0 = 0, DQS1 = 0
3498 20:14:33.450927 DQM Delay:
3499 20:14:33.453851 DQM0 = 115, DQM1 = 103
3500 20:14:33.454374 DQ Delay:
3501 20:14:33.457032 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3502 20:14:33.460449 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3503 20:14:33.464424 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3504 20:14:33.467081 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3505 20:14:33.467604
3506 20:14:33.467935
3507 20:14:33.476972 [DQSOSCAuto] RK1, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
3508 20:14:33.480792 CH1 RK1: MR19=404, MR18=505
3509 20:14:33.483804 CH1_RK1: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
3510 20:14:33.486809 [RxdqsGatingPostProcess] freq 1200
3511 20:14:33.493292 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3512 20:14:33.497060 Pre-setting of DQS Precalculation
3513 20:14:33.499849 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3514 20:14:33.510715 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3515 20:14:33.517402 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3516 20:14:33.518005
3517 20:14:33.518506
3518 20:14:33.520439 [Calibration Summary] 2400 Mbps
3519 20:14:33.521046 CH 0, Rank 0
3520 20:14:33.523749 SW Impedance : PASS
3521 20:14:33.524309 DUTY Scan : NO K
3522 20:14:33.526791 ZQ Calibration : PASS
3523 20:14:33.530472 Jitter Meter : NO K
3524 20:14:33.531231 CBT Training : PASS
3525 20:14:33.533454 Write leveling : PASS
3526 20:14:33.537107 RX DQS gating : PASS
3527 20:14:33.537697 RX DQ/DQS(RDDQC) : PASS
3528 20:14:33.540646 TX DQ/DQS : PASS
3529 20:14:33.544673 RX DATLAT : PASS
3530 20:14:33.545291 RX DQ/DQS(Engine): PASS
3531 20:14:33.546572 TX OE : NO K
3532 20:14:33.547035 All Pass.
3533 20:14:33.547400
3534 20:14:33.550201 CH 0, Rank 1
3535 20:14:33.550766 SW Impedance : PASS
3536 20:14:33.553610 DUTY Scan : NO K
3537 20:14:33.554074 ZQ Calibration : PASS
3538 20:14:33.556414 Jitter Meter : NO K
3539 20:14:33.561259 CBT Training : PASS
3540 20:14:33.561731 Write leveling : PASS
3541 20:14:33.563881 RX DQS gating : PASS
3542 20:14:33.567296 RX DQ/DQS(RDDQC) : PASS
3543 20:14:33.567893 TX DQ/DQS : PASS
3544 20:14:33.569821 RX DATLAT : PASS
3545 20:14:33.573458 RX DQ/DQS(Engine): PASS
3546 20:14:33.574050 TX OE : NO K
3547 20:14:33.576586 All Pass.
3548 20:14:33.577123
3549 20:14:33.577487 CH 1, Rank 0
3550 20:14:33.579817 SW Impedance : PASS
3551 20:14:33.580277 DUTY Scan : NO K
3552 20:14:33.583419 ZQ Calibration : PASS
3553 20:14:33.586823 Jitter Meter : NO K
3554 20:14:33.587307 CBT Training : PASS
3555 20:14:33.590196 Write leveling : PASS
3556 20:14:33.593317 RX DQS gating : PASS
3557 20:14:33.593780 RX DQ/DQS(RDDQC) : PASS
3558 20:14:33.596778 TX DQ/DQS : PASS
3559 20:14:33.597250 RX DATLAT : PASS
3560 20:14:33.600110 RX DQ/DQS(Engine): PASS
3561 20:14:33.603944 TX OE : NO K
3562 20:14:33.604480 All Pass.
3563 20:14:33.604850
3564 20:14:33.605162 CH 1, Rank 1
3565 20:14:33.606913 SW Impedance : PASS
3566 20:14:33.610746 DUTY Scan : NO K
3567 20:14:33.611165 ZQ Calibration : PASS
3568 20:14:33.614210 Jitter Meter : NO K
3569 20:14:33.616842 CBT Training : PASS
3570 20:14:33.617260 Write leveling : PASS
3571 20:14:33.620638 RX DQS gating : PASS
3572 20:14:33.623547 RX DQ/DQS(RDDQC) : PASS
3573 20:14:33.623964 TX DQ/DQS : PASS
3574 20:14:33.626476 RX DATLAT : PASS
3575 20:14:33.630123 RX DQ/DQS(Engine): PASS
3576 20:14:33.630538 TX OE : NO K
3577 20:14:33.630864 All Pass.
3578 20:14:33.633518
3579 20:14:33.633932 DramC Write-DBI off
3580 20:14:33.636886 PER_BANK_REFRESH: Hybrid Mode
3581 20:14:33.637329 TX_TRACKING: ON
3582 20:14:33.646887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3583 20:14:33.650356 [FAST_K] Save calibration result to emmc
3584 20:14:33.653870 dramc_set_vcore_voltage set vcore to 650000
3585 20:14:33.658339 Read voltage for 600, 5
3586 20:14:33.658867 Vio18 = 0
3587 20:14:33.659943 Vcore = 650000
3588 20:14:33.660358 Vdram = 0
3589 20:14:33.660688 Vddq = 0
3590 20:14:33.661119 Vmddr = 0
3591 20:14:33.666757 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3592 20:14:33.673776 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3593 20:14:33.674201 MEM_TYPE=3, freq_sel=19
3594 20:14:33.676776 sv_algorithm_assistance_LP4_1600
3595 20:14:33.680622 ============ PULL DRAM RESETB DOWN ============
3596 20:14:33.686647 ========== PULL DRAM RESETB DOWN end =========
3597 20:14:33.690211 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3598 20:14:33.693479 ===================================
3599 20:14:33.696504 LPDDR4 DRAM CONFIGURATION
3600 20:14:33.700317 ===================================
3601 20:14:33.700889 EX_ROW_EN[0] = 0x0
3602 20:14:33.703353 EX_ROW_EN[1] = 0x0
3603 20:14:33.703816 LP4Y_EN = 0x0
3604 20:14:33.706683 WORK_FSP = 0x0
3605 20:14:33.707199 WL = 0x2
3606 20:14:33.709753 RL = 0x2
3607 20:14:33.710196 BL = 0x2
3608 20:14:33.713139 RPST = 0x0
3609 20:14:33.713581 RD_PRE = 0x0
3610 20:14:33.717028 WR_PRE = 0x1
3611 20:14:33.720262 WR_PST = 0x0
3612 20:14:33.720842 DBI_WR = 0x0
3613 20:14:33.723647 DBI_RD = 0x0
3614 20:14:33.724230 OTF = 0x1
3615 20:14:33.726740 ===================================
3616 20:14:33.730026 ===================================
3617 20:14:33.730602 ANA top config
3618 20:14:33.733214 ===================================
3619 20:14:33.736991 DLL_ASYNC_EN = 0
3620 20:14:33.740075 ALL_SLAVE_EN = 1
3621 20:14:33.743707 NEW_RANK_MODE = 1
3622 20:14:33.746646 DLL_IDLE_MODE = 1
3623 20:14:33.747125 LP45_APHY_COMB_EN = 1
3624 20:14:33.750076 TX_ODT_DIS = 1
3625 20:14:33.752930 NEW_8X_MODE = 1
3626 20:14:33.756794 ===================================
3627 20:14:33.760076 ===================================
3628 20:14:33.763235 data_rate = 1200
3629 20:14:33.766551 CKR = 1
3630 20:14:33.767032 DQ_P2S_RATIO = 8
3631 20:14:33.770075 ===================================
3632 20:14:33.773527 CA_P2S_RATIO = 8
3633 20:14:33.776201 DQ_CA_OPEN = 0
3634 20:14:33.780209 DQ_SEMI_OPEN = 0
3635 20:14:33.783184 CA_SEMI_OPEN = 0
3636 20:14:33.786362 CA_FULL_RATE = 0
3637 20:14:33.786881 DQ_CKDIV4_EN = 1
3638 20:14:33.790202 CA_CKDIV4_EN = 1
3639 20:14:33.793349 CA_PREDIV_EN = 0
3640 20:14:33.796144 PH8_DLY = 0
3641 20:14:33.800413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3642 20:14:33.803425 DQ_AAMCK_DIV = 4
3643 20:14:33.803948 CA_AAMCK_DIV = 4
3644 20:14:33.806797 CA_ADMCK_DIV = 4
3645 20:14:33.809292 DQ_TRACK_CA_EN = 0
3646 20:14:33.812673 CA_PICK = 600
3647 20:14:33.816287 CA_MCKIO = 600
3648 20:14:33.819088 MCKIO_SEMI = 0
3649 20:14:33.822920 PLL_FREQ = 2288
3650 20:14:33.826185 DQ_UI_PI_RATIO = 32
3651 20:14:33.826722 CA_UI_PI_RATIO = 0
3652 20:14:33.829013 ===================================
3653 20:14:33.832326 ===================================
3654 20:14:33.835811 memory_type:LPDDR4
3655 20:14:33.839850 GP_NUM : 10
3656 20:14:33.840332 SRAM_EN : 1
3657 20:14:33.842214 MD32_EN : 0
3658 20:14:33.845675 ===================================
3659 20:14:33.849078 [ANA_INIT] >>>>>>>>>>>>>>
3660 20:14:33.852035 <<<<<< [CONFIGURE PHASE]: ANA_TX
3661 20:14:33.855460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3662 20:14:33.858832 ===================================
3663 20:14:33.859297 data_rate = 1200,PCW = 0X5800
3664 20:14:33.862205 ===================================
3665 20:14:33.866610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3666 20:14:33.872777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3667 20:14:33.878763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3668 20:14:33.881990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3669 20:14:33.885416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3670 20:14:33.888887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3671 20:14:33.891985 [ANA_INIT] flow start
3672 20:14:33.895941 [ANA_INIT] PLL >>>>>>>>
3673 20:14:33.896406 [ANA_INIT] PLL <<<<<<<<
3674 20:14:33.898446 [ANA_INIT] MIDPI >>>>>>>>
3675 20:14:33.901464 [ANA_INIT] MIDPI <<<<<<<<
3676 20:14:33.901938 [ANA_INIT] DLL >>>>>>>>
3677 20:14:33.905034 [ANA_INIT] flow end
3678 20:14:33.908483 ============ LP4 DIFF to SE enter ============
3679 20:14:33.912679 ============ LP4 DIFF to SE exit ============
3680 20:14:33.915014 [ANA_INIT] <<<<<<<<<<<<<
3681 20:14:33.918341 [Flow] Enable top DCM control >>>>>
3682 20:14:33.922245 [Flow] Enable top DCM control <<<<<
3683 20:14:33.925533 Enable DLL master slave shuffle
3684 20:14:33.931875 ==============================================================
3685 20:14:33.932617 Gating Mode config
3686 20:14:33.937891 ==============================================================
3687 20:14:33.943064 Config description:
3688 20:14:33.947937 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3689 20:14:33.954282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3690 20:14:33.961033 SELPH_MODE 0: By rank 1: By Phase
3691 20:14:33.964834 ==============================================================
3692 20:14:33.968281 GAT_TRACK_EN = 1
3693 20:14:33.971079 RX_GATING_MODE = 2
3694 20:14:33.974687 RX_GATING_TRACK_MODE = 2
3695 20:14:33.978683 SELPH_MODE = 1
3696 20:14:33.981375 PICG_EARLY_EN = 1
3697 20:14:33.984277 VALID_LAT_VALUE = 1
3698 20:14:33.991756 ==============================================================
3699 20:14:33.994970 Enter into Gating configuration >>>>
3700 20:14:33.998504 Exit from Gating configuration <<<<
3701 20:14:34.001609 Enter into DVFS_PRE_config >>>>>
3702 20:14:34.011208 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3703 20:14:34.014457 Exit from DVFS_PRE_config <<<<<
3704 20:14:34.018114 Enter into PICG configuration >>>>
3705 20:14:34.021096 Exit from PICG configuration <<<<
3706 20:14:34.024988 [RX_INPUT] configuration >>>>>
3707 20:14:34.025553 [RX_INPUT] configuration <<<<<
3708 20:14:34.031008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3709 20:14:34.037167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3710 20:14:34.043802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3711 20:14:34.046958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3712 20:14:34.053976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3713 20:14:34.060365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3714 20:14:34.063214 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3715 20:14:34.070523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3716 20:14:34.073634 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3717 20:14:34.076537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3718 20:14:34.080156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3719 20:14:34.086982 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3720 20:14:34.089690 ===================================
3721 20:14:34.090158 LPDDR4 DRAM CONFIGURATION
3722 20:14:34.093040 ===================================
3723 20:14:34.096827 EX_ROW_EN[0] = 0x0
3724 20:14:34.100402 EX_ROW_EN[1] = 0x0
3725 20:14:34.100913 LP4Y_EN = 0x0
3726 20:14:34.103196 WORK_FSP = 0x0
3727 20:14:34.103753 WL = 0x2
3728 20:14:34.107310 RL = 0x2
3729 20:14:34.107873 BL = 0x2
3730 20:14:34.109781 RPST = 0x0
3731 20:14:34.110250 RD_PRE = 0x0
3732 20:14:34.113049 WR_PRE = 0x1
3733 20:14:34.113511 WR_PST = 0x0
3734 20:14:34.116924 DBI_WR = 0x0
3735 20:14:34.117460 DBI_RD = 0x0
3736 20:14:34.120664 OTF = 0x1
3737 20:14:34.123229 ===================================
3738 20:14:34.126644 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3739 20:14:34.129877 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3740 20:14:34.136374 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3741 20:14:34.140631 ===================================
3742 20:14:34.141238 LPDDR4 DRAM CONFIGURATION
3743 20:14:34.142831 ===================================
3744 20:14:34.146278 EX_ROW_EN[0] = 0x10
3745 20:14:34.149157 EX_ROW_EN[1] = 0x0
3746 20:14:34.149623 LP4Y_EN = 0x0
3747 20:14:34.152883 WORK_FSP = 0x0
3748 20:14:34.153576 WL = 0x2
3749 20:14:34.155889 RL = 0x2
3750 20:14:34.156353 BL = 0x2
3751 20:14:34.159632 RPST = 0x0
3752 20:14:34.160197 RD_PRE = 0x0
3753 20:14:34.162360 WR_PRE = 0x1
3754 20:14:34.162824 WR_PST = 0x0
3755 20:14:34.165859 DBI_WR = 0x0
3756 20:14:34.166423 DBI_RD = 0x0
3757 20:14:34.169277 OTF = 0x1
3758 20:14:34.172628 ===================================
3759 20:14:34.179059 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3760 20:14:34.183221 nWR fixed to 30
3761 20:14:34.185507 [ModeRegInit_LP4] CH0 RK0
3762 20:14:34.185972 [ModeRegInit_LP4] CH0 RK1
3763 20:14:34.188894 [ModeRegInit_LP4] CH1 RK0
3764 20:14:34.192511 [ModeRegInit_LP4] CH1 RK1
3765 20:14:34.193125 match AC timing 16
3766 20:14:34.198716 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3767 20:14:34.202455 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3768 20:14:34.205603 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3769 20:14:34.212327 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3770 20:14:34.215820 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3771 20:14:34.216301 ==
3772 20:14:34.219323 Dram Type= 6, Freq= 0, CH_0, rank 0
3773 20:14:34.222540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3774 20:14:34.223128 ==
3775 20:14:34.229559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3776 20:14:34.235747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3777 20:14:34.238817 [CA 0] Center 35 (5~66) winsize 62
3778 20:14:34.242224 [CA 1] Center 35 (5~66) winsize 62
3779 20:14:34.246127 [CA 2] Center 34 (4~65) winsize 62
3780 20:14:34.250045 [CA 3] Center 34 (4~65) winsize 62
3781 20:14:34.252614 [CA 4] Center 33 (3~64) winsize 62
3782 20:14:34.256421 [CA 5] Center 33 (3~64) winsize 62
3783 20:14:34.256946
3784 20:14:34.258856 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3785 20:14:34.259335
3786 20:14:34.261885 [CATrainingPosCal] consider 1 rank data
3787 20:14:34.265519 u2DelayCellTimex100 = 270/100 ps
3788 20:14:34.268873 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3789 20:14:34.272347 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3790 20:14:34.275795 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3791 20:14:34.279491 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3792 20:14:34.281659 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3793 20:14:34.285202 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3794 20:14:34.289915
3795 20:14:34.292114 CA PerBit enable=1, Macro0, CA PI delay=33
3796 20:14:34.292538
3797 20:14:34.295057 [CBTSetCACLKResult] CA Dly = 33
3798 20:14:34.295478 CS Dly: 4 (0~35)
3799 20:14:34.295809 ==
3800 20:14:34.298405 Dram Type= 6, Freq= 0, CH_0, rank 1
3801 20:14:34.301483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3802 20:14:34.301907 ==
3803 20:14:34.308794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3804 20:14:34.315170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3805 20:14:34.318180 [CA 0] Center 36 (6~66) winsize 61
3806 20:14:34.322118 [CA 1] Center 35 (5~66) winsize 62
3807 20:14:34.324886 [CA 2] Center 34 (4~65) winsize 62
3808 20:14:34.328209 [CA 3] Center 34 (4~65) winsize 62
3809 20:14:34.331720 [CA 4] Center 33 (3~64) winsize 62
3810 20:14:34.334847 [CA 5] Center 33 (3~64) winsize 62
3811 20:14:34.335332
3812 20:14:34.338589 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3813 20:14:34.339008
3814 20:14:34.341502 [CATrainingPosCal] consider 2 rank data
3815 20:14:34.345223 u2DelayCellTimex100 = 270/100 ps
3816 20:14:34.348233 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3817 20:14:34.351664 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3818 20:14:34.355194 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3819 20:14:34.358184 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3820 20:14:34.365360 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3821 20:14:34.367751 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3822 20:14:34.368176
3823 20:14:34.371320 CA PerBit enable=1, Macro0, CA PI delay=33
3824 20:14:34.371745
3825 20:14:34.374238 [CBTSetCACLKResult] CA Dly = 33
3826 20:14:34.374660 CS Dly: 4 (0~36)
3827 20:14:34.374990
3828 20:14:34.377991 ----->DramcWriteLeveling(PI) begin...
3829 20:14:34.378626 ==
3830 20:14:34.381334 Dram Type= 6, Freq= 0, CH_0, rank 0
3831 20:14:34.387290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3832 20:14:34.387715 ==
3833 20:14:34.391383 Write leveling (Byte 0): 31 => 31
3834 20:14:34.394266 Write leveling (Byte 1): 31 => 31
3835 20:14:34.394686 DramcWriteLeveling(PI) end<-----
3836 20:14:34.398233
3837 20:14:34.398652 ==
3838 20:14:34.401111 Dram Type= 6, Freq= 0, CH_0, rank 0
3839 20:14:34.404438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3840 20:14:34.404901 ==
3841 20:14:34.407454 [Gating] SW mode calibration
3842 20:14:34.414506 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3843 20:14:34.417496 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3844 20:14:34.424042 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3845 20:14:34.427768 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3846 20:14:34.430657 0 5 8 | B1->B0 | 3232 3333 | 1 1 | (1 1) (0 0)
3847 20:14:34.437650 0 5 12 | B1->B0 | 2a2a 2424 | 0 0 | (1 1) (0 0)
3848 20:14:34.440532 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3849 20:14:34.443831 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3850 20:14:34.452531 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3851 20:14:34.453668 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3852 20:14:34.457226 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 20:14:34.463465 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 20:14:34.467155 0 6 8 | B1->B0 | 2828 3434 | 1 0 | (0 0) (1 1)
3855 20:14:34.470601 0 6 12 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
3856 20:14:34.477942 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3857 20:14:34.480265 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3858 20:14:34.483359 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3859 20:14:34.490272 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 20:14:34.494160 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 20:14:34.496477 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 20:14:34.503822 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3863 20:14:34.506763 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3864 20:14:34.509768 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3865 20:14:34.516494 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 20:14:34.519993 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 20:14:34.523290 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 20:14:34.530354 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 20:14:34.533019 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 20:14:34.536627 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 20:14:34.543874 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 20:14:34.546116 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 20:14:34.549400 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 20:14:34.556241 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 20:14:34.559778 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 20:14:34.563295 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 20:14:34.569375 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 20:14:34.572560 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3879 20:14:34.576045 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3880 20:14:34.580074 Total UI for P1: 0, mck2ui 16
3881 20:14:34.585049 best dqsien dly found for B0: ( 0, 9, 8)
3882 20:14:34.590434 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3883 20:14:34.590993 Total UI for P1: 0, mck2ui 16
3884 20:14:34.596837 best dqsien dly found for B1: ( 0, 9, 10)
3885 20:14:34.598954 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3886 20:14:34.602538 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3887 20:14:34.603005
3888 20:14:34.605709 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3889 20:14:34.609451 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3890 20:14:34.612979 [Gating] SW calibration Done
3891 20:14:34.613482 ==
3892 20:14:34.616367 Dram Type= 6, Freq= 0, CH_0, rank 0
3893 20:14:34.619256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3894 20:14:34.619752 ==
3895 20:14:34.622453 RX Vref Scan: 0
3896 20:14:34.623054
3897 20:14:34.623430 RX Vref 0 -> 0, step: 1
3898 20:14:34.623772
3899 20:14:34.625566 RX Delay -230 -> 252, step: 16
3900 20:14:34.630143 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3901 20:14:34.636017 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3902 20:14:34.639219 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3903 20:14:34.643623 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3904 20:14:34.645681 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3905 20:14:34.652189 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3906 20:14:34.655320 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3907 20:14:34.659151 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3908 20:14:34.662185 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3909 20:14:34.669236 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3910 20:14:34.672094 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3911 20:14:34.675428 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3912 20:14:34.678928 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3913 20:14:34.685437 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3914 20:14:34.689460 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3915 20:14:34.691782 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3916 20:14:34.692261 ==
3917 20:14:34.694842 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 20:14:34.698264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3919 20:14:34.701529 ==
3920 20:14:34.702007 DQS Delay:
3921 20:14:34.702495 DQS0 = 0, DQS1 = 0
3922 20:14:34.704685 DQM Delay:
3923 20:14:34.705217 DQM0 = 37, DQM1 = 33
3924 20:14:34.708921 DQ Delay:
3925 20:14:34.709381 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3926 20:14:34.711115 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3927 20:14:34.714927 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3928 20:14:34.718003 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3929 20:14:34.718418
3930 20:14:34.721535
3931 20:14:34.721947 ==
3932 20:14:34.725044 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 20:14:34.727828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3934 20:14:34.728287 ==
3935 20:14:34.728621
3936 20:14:34.728977
3937 20:14:34.730941 TX Vref Scan disable
3938 20:14:34.731357 == TX Byte 0 ==
3939 20:14:34.737817 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3940 20:14:34.740933 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3941 20:14:34.741359 == TX Byte 1 ==
3942 20:14:34.747726 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3943 20:14:34.751157 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3944 20:14:34.751583 ==
3945 20:14:34.754368 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 20:14:34.758015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3947 20:14:34.758440 ==
3948 20:14:34.758772
3949 20:14:34.759078
3950 20:14:34.760672 TX Vref Scan disable
3951 20:14:34.764300 == TX Byte 0 ==
3952 20:14:34.767665 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3953 20:14:34.770572 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3954 20:14:34.773923 == TX Byte 1 ==
3955 20:14:34.777779 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3956 20:14:34.780914 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3957 20:14:34.783937
3958 20:14:34.784356 [DATLAT]
3959 20:14:34.784762 Freq=600, CH0 RK0
3960 20:14:34.785094
3961 20:14:34.787282 DATLAT Default: 0x9
3962 20:14:34.787716 0, 0xFFFF, sum = 0
3963 20:14:34.791716 1, 0xFFFF, sum = 0
3964 20:14:34.792284 2, 0xFFFF, sum = 0
3965 20:14:34.794907 3, 0xFFFF, sum = 0
3966 20:14:34.795330 4, 0xFFFF, sum = 0
3967 20:14:34.797318 5, 0xFFFF, sum = 0
3968 20:14:34.800815 6, 0xFFFF, sum = 0
3969 20:14:34.801283 7, 0x0, sum = 1
3970 20:14:34.801650 8, 0x0, sum = 2
3971 20:14:34.804136 9, 0x0, sum = 3
3972 20:14:34.804607 10, 0x0, sum = 4
3973 20:14:34.807172 best_step = 8
3974 20:14:34.807589
3975 20:14:34.807914 ==
3976 20:14:34.810690 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 20:14:34.814117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3978 20:14:34.814552 ==
3979 20:14:34.817506 RX Vref Scan: 1
3980 20:14:34.817921
3981 20:14:34.818246 RX Vref 0 -> 0, step: 1
3982 20:14:34.818553
3983 20:14:34.820507 RX Delay -195 -> 252, step: 8
3984 20:14:34.820959
3985 20:14:34.824268 Set Vref, RX VrefLevel [Byte0]: 53
3986 20:14:34.826962 [Byte1]: 50
3987 20:14:34.831805
3988 20:14:34.832226 Final RX Vref Byte 0 = 53 to rank0
3989 20:14:34.835235 Final RX Vref Byte 1 = 50 to rank0
3990 20:14:34.838234 Final RX Vref Byte 0 = 53 to rank1
3991 20:14:34.841278 Final RX Vref Byte 1 = 50 to rank1==
3992 20:14:34.844155 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 20:14:34.850947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3994 20:14:34.851368 ==
3995 20:14:34.851699 DQS Delay:
3996 20:14:34.852004 DQS0 = 0, DQS1 = 0
3997 20:14:34.854066 DQM Delay:
3998 20:14:34.854497 DQM0 = 40, DQM1 = 30
3999 20:14:34.857644 DQ Delay:
4000 20:14:34.861461 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4001 20:14:34.864780 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4002 20:14:34.867401 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4003 20:14:34.870812 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4004 20:14:34.871236
4005 20:14:34.871564
4006 20:14:34.877624 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4007 20:14:34.880659 CH0 RK0: MR19=808, MR18=5A5A
4008 20:14:34.887377 CH0_RK0: MR19=0x808, MR18=0x5A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4009 20:14:34.887957
4010 20:14:34.890403 ----->DramcWriteLeveling(PI) begin...
4011 20:14:34.890827 ==
4012 20:14:34.893886 Dram Type= 6, Freq= 0, CH_0, rank 1
4013 20:14:34.897382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4014 20:14:34.897821 ==
4015 20:14:34.900622 Write leveling (Byte 0): 29 => 29
4016 20:14:34.903661 Write leveling (Byte 1): 29 => 29
4017 20:14:34.906874 DramcWriteLeveling(PI) end<-----
4018 20:14:34.907293
4019 20:14:34.907622 ==
4020 20:14:34.910142 Dram Type= 6, Freq= 0, CH_0, rank 1
4021 20:14:34.913835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4022 20:14:34.918318 ==
4023 20:14:34.918734 [Gating] SW mode calibration
4024 20:14:34.924357 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4025 20:14:34.930879 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4026 20:14:34.934315 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 20:14:34.940828 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 20:14:34.943683 0 5 8 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 1)
4029 20:14:34.947987 0 5 12 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
4030 20:14:34.953663 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 20:14:34.956462 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 20:14:34.960165 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 20:14:34.966955 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 20:14:34.969972 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 20:14:34.973519 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4036 20:14:34.979855 0 6 8 | B1->B0 | 2c2c 3232 | 0 1 | (0 0) (0 0)
4037 20:14:34.983269 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4038 20:14:34.986935 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 20:14:34.994342 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 20:14:34.996387 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 20:14:35.000489 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 20:14:35.007046 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 20:14:35.010185 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 20:14:35.014211 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4045 20:14:35.019872 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4046 20:14:35.024151 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 20:14:35.026464 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 20:14:35.030301 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 20:14:35.036571 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 20:14:35.039917 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 20:14:35.044485 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 20:14:35.049620 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 20:14:35.053332 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 20:14:35.056160 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 20:14:35.063074 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 20:14:35.066341 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 20:14:35.069689 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 20:14:35.076474 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 20:14:35.079666 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 20:14:35.082870 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4061 20:14:35.090078 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4062 20:14:35.090510 Total UI for P1: 0, mck2ui 16
4063 20:14:35.096816 best dqsien dly found for B0: ( 0, 9, 8)
4064 20:14:35.099505 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 20:14:35.102668 Total UI for P1: 0, mck2ui 16
4066 20:14:35.106202 best dqsien dly found for B1: ( 0, 9, 10)
4067 20:14:35.109098 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4068 20:14:35.112282 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4069 20:14:35.112779
4070 20:14:35.117053 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4071 20:14:35.120199 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4072 20:14:35.123084 [Gating] SW calibration Done
4073 20:14:35.123555 ==
4074 20:14:35.125928 Dram Type= 6, Freq= 0, CH_0, rank 1
4075 20:14:35.132585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4076 20:14:35.133165 ==
4077 20:14:35.133540 RX Vref Scan: 0
4078 20:14:35.133890
4079 20:14:35.136286 RX Vref 0 -> 0, step: 1
4080 20:14:35.136892
4081 20:14:35.139378 RX Delay -230 -> 252, step: 16
4082 20:14:35.142393 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4083 20:14:35.145854 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4084 20:14:35.149031 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4085 20:14:35.155710 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4086 20:14:35.159191 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4087 20:14:35.162194 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4088 20:14:35.165559 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4089 20:14:35.168982 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4090 20:14:35.176026 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4091 20:14:35.178796 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4092 20:14:35.183062 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4093 20:14:35.185246 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4094 20:14:35.192246 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4095 20:14:35.196088 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4096 20:14:35.198671 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4097 20:14:35.202593 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4098 20:14:35.205073 ==
4099 20:14:35.208897 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 20:14:35.212114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 20:14:35.212586 ==
4102 20:14:35.213020 DQS Delay:
4103 20:14:35.215051 DQS0 = 0, DQS1 = 0
4104 20:14:35.215522 DQM Delay:
4105 20:14:35.219322 DQM0 = 41, DQM1 = 33
4106 20:14:35.219844 DQ Delay:
4107 20:14:35.221919 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4108 20:14:35.225324 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4109 20:14:35.228514 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4110 20:14:35.232600 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4111 20:14:35.233337
4112 20:14:35.233716
4113 20:14:35.234059 ==
4114 20:14:35.235313 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 20:14:35.239269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 20:14:35.239745 ==
4117 20:14:35.240113
4118 20:14:35.240454
4119 20:14:35.241953 TX Vref Scan disable
4120 20:14:35.245369 == TX Byte 0 ==
4121 20:14:35.248407 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4122 20:14:35.251441 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4123 20:14:35.255703 == TX Byte 1 ==
4124 20:14:35.258745 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4125 20:14:35.261684 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4126 20:14:35.262157 ==
4127 20:14:35.265067 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 20:14:35.271574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 20:14:35.272130 ==
4130 20:14:35.272507
4131 20:14:35.272893
4132 20:14:35.273228 TX Vref Scan disable
4133 20:14:35.275427 == TX Byte 0 ==
4134 20:14:35.279339 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4135 20:14:35.285221 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4136 20:14:35.285695 == TX Byte 1 ==
4137 20:14:35.289425 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4138 20:14:35.295671 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4139 20:14:35.296253
4140 20:14:35.296627 [DATLAT]
4141 20:14:35.297022 Freq=600, CH0 RK1
4142 20:14:35.297362
4143 20:14:35.299038 DATLAT Default: 0x8
4144 20:14:35.299505 0, 0xFFFF, sum = 0
4145 20:14:35.302521 1, 0xFFFF, sum = 0
4146 20:14:35.303093 2, 0xFFFF, sum = 0
4147 20:14:35.305794 3, 0xFFFF, sum = 0
4148 20:14:35.308508 4, 0xFFFF, sum = 0
4149 20:14:35.309018 5, 0xFFFF, sum = 0
4150 20:14:35.312030 6, 0xFFFF, sum = 0
4151 20:14:35.312519 7, 0x0, sum = 1
4152 20:14:35.312941 8, 0x0, sum = 2
4153 20:14:35.315442 9, 0x0, sum = 3
4154 20:14:35.316157 10, 0x0, sum = 4
4155 20:14:35.319088 best_step = 8
4156 20:14:35.319558
4157 20:14:35.319981 ==
4158 20:14:35.322180 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 20:14:35.326188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 20:14:35.326753 ==
4161 20:14:35.328892 RX Vref Scan: 0
4162 20:14:35.329367
4163 20:14:35.329737 RX Vref 0 -> 0, step: 1
4164 20:14:35.330082
4165 20:14:35.331948 RX Delay -195 -> 252, step: 8
4166 20:14:35.339180 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4167 20:14:35.343007 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4168 20:14:35.346418 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4169 20:14:35.350149 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4170 20:14:35.356376 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4171 20:14:35.359451 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4172 20:14:35.362416 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4173 20:14:35.365479 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4174 20:14:35.372292 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4175 20:14:35.375573 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4176 20:14:35.379717 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4177 20:14:35.381801 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4178 20:14:35.388987 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4179 20:14:35.391765 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4180 20:14:35.395639 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4181 20:14:35.398790 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4182 20:14:35.399316 ==
4183 20:14:35.402092 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 20:14:35.408532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4185 20:14:35.409085 ==
4186 20:14:35.409428 DQS Delay:
4187 20:14:35.412289 DQS0 = 0, DQS1 = 0
4188 20:14:35.412860 DQM Delay:
4189 20:14:35.413213 DQM0 = 41, DQM1 = 33
4190 20:14:35.415260 DQ Delay:
4191 20:14:35.418173 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4192 20:14:35.421593 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4193 20:14:35.426207 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4194 20:14:35.428804 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4195 20:14:35.429230
4196 20:14:35.429565
4197 20:14:35.434886 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4198 20:14:35.438727 CH0 RK1: MR19=808, MR18=6B6B
4199 20:14:35.445358 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4200 20:14:35.448262 [RxdqsGatingPostProcess] freq 600
4201 20:14:35.451425 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4202 20:14:35.455572 Pre-setting of DQS Precalculation
4203 20:14:35.461676 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4204 20:14:35.462148 ==
4205 20:14:35.465262 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 20:14:35.468633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 20:14:35.469250 ==
4208 20:14:35.474980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4209 20:14:35.481430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4210 20:14:35.484757 [CA 0] Center 35 (5~66) winsize 62
4211 20:14:35.488953 [CA 1] Center 35 (5~65) winsize 61
4212 20:14:35.491507 [CA 2] Center 33 (3~64) winsize 62
4213 20:14:35.495409 [CA 3] Center 33 (3~64) winsize 62
4214 20:14:35.498457 [CA 4] Center 33 (2~64) winsize 63
4215 20:14:35.501302 [CA 5] Center 33 (2~64) winsize 63
4216 20:14:35.501771
4217 20:14:35.505233 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4218 20:14:35.505777
4219 20:14:35.507870 [CATrainingPosCal] consider 1 rank data
4220 20:14:35.511415 u2DelayCellTimex100 = 270/100 ps
4221 20:14:35.514530 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4222 20:14:35.517620 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4223 20:14:35.521629 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4224 20:14:35.524786 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4225 20:14:35.527776 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4226 20:14:35.531268 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4227 20:14:35.531831
4228 20:14:35.537806 CA PerBit enable=1, Macro0, CA PI delay=33
4229 20:14:35.538377
4230 20:14:35.538753 [CBTSetCACLKResult] CA Dly = 33
4231 20:14:35.541099 CS Dly: 5 (0~36)
4232 20:14:35.541662 ==
4233 20:14:35.544400 Dram Type= 6, Freq= 0, CH_1, rank 1
4234 20:14:35.547265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4235 20:14:35.547738 ==
4236 20:14:35.554288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4237 20:14:35.560451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4238 20:14:35.564617 [CA 0] Center 35 (5~66) winsize 62
4239 20:14:35.567364 [CA 1] Center 34 (4~65) winsize 62
4240 20:14:35.571500 [CA 2] Center 33 (3~64) winsize 62
4241 20:14:35.573733 [CA 3] Center 33 (3~64) winsize 62
4242 20:14:35.577235 [CA 4] Center 32 (2~63) winsize 62
4243 20:14:35.581359 [CA 5] Center 32 (2~63) winsize 62
4244 20:14:35.581947
4245 20:14:35.583903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4246 20:14:35.584373
4247 20:14:35.589937 [CATrainingPosCal] consider 2 rank data
4248 20:14:35.591534 u2DelayCellTimex100 = 270/100 ps
4249 20:14:35.593790 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4250 20:14:35.596995 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4251 20:14:35.600222 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4252 20:14:35.603936 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4253 20:14:35.606887 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4254 20:14:35.613686 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4255 20:14:35.614157
4256 20:14:35.617274 CA PerBit enable=1, Macro0, CA PI delay=32
4257 20:14:35.617745
4258 20:14:35.620276 [CBTSetCACLKResult] CA Dly = 32
4259 20:14:35.620932 CS Dly: 5 (0~36)
4260 20:14:35.621314
4261 20:14:35.625289 ----->DramcWriteLeveling(PI) begin...
4262 20:14:35.625767 ==
4263 20:14:35.626545 Dram Type= 6, Freq= 0, CH_1, rank 0
4264 20:14:35.633514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4265 20:14:35.634076 ==
4266 20:14:35.636536 Write leveling (Byte 0): 28 => 28
4267 20:14:35.637033 Write leveling (Byte 1): 29 => 29
4268 20:14:35.640411 DramcWriteLeveling(PI) end<-----
4269 20:14:35.641014
4270 20:14:35.643476 ==
4271 20:14:35.646294 Dram Type= 6, Freq= 0, CH_1, rank 0
4272 20:14:35.649659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4273 20:14:35.650221 ==
4274 20:14:35.652831 [Gating] SW mode calibration
4275 20:14:35.660023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4276 20:14:35.662973 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4277 20:14:35.669655 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 20:14:35.673388 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4279 20:14:35.676454 0 5 8 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (1 0)
4280 20:14:35.683395 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 20:14:35.686335 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 20:14:35.690111 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 20:14:35.696565 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 20:14:35.699632 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 20:14:35.703552 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 20:14:35.709374 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4287 20:14:35.713109 0 6 8 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
4288 20:14:35.716146 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 20:14:35.723212 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 20:14:35.726564 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 20:14:35.729650 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 20:14:35.736939 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 20:14:35.740890 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 20:14:35.742403 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4295 20:14:35.749175 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4296 20:14:35.753006 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 20:14:35.756814 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 20:14:35.762443 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 20:14:35.765551 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 20:14:35.769630 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 20:14:35.775521 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 20:14:35.779008 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 20:14:35.782365 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 20:14:35.786203 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 20:14:35.792743 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 20:14:35.796176 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 20:14:35.798758 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 20:14:35.805478 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 20:14:35.809097 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 20:14:35.812182 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4311 20:14:35.819027 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 20:14:35.822233 Total UI for P1: 0, mck2ui 16
4313 20:14:35.825120 best dqsien dly found for B0: ( 0, 9, 4)
4314 20:14:35.829406 Total UI for P1: 0, mck2ui 16
4315 20:14:35.832181 best dqsien dly found for B1: ( 0, 9, 6)
4316 20:14:35.835193 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4317 20:14:35.838784 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4318 20:14:35.839322
4319 20:14:35.842174 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4320 20:14:35.845406 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4321 20:14:35.849155 [Gating] SW calibration Done
4322 20:14:35.849714 ==
4323 20:14:35.851795 Dram Type= 6, Freq= 0, CH_1, rank 0
4324 20:14:35.855393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4325 20:14:35.855964 ==
4326 20:14:35.858597 RX Vref Scan: 0
4327 20:14:35.859183
4328 20:14:35.861490 RX Vref 0 -> 0, step: 1
4329 20:14:35.861962
4330 20:14:35.862335 RX Delay -230 -> 252, step: 16
4331 20:14:35.868743 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4332 20:14:35.871756 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4333 20:14:35.874785 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4334 20:14:35.878400 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4335 20:14:35.884749 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4336 20:14:35.887878 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4337 20:14:35.891466 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4338 20:14:35.894781 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4339 20:14:35.898221 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4340 20:14:35.904572 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4341 20:14:35.907929 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4342 20:14:35.911194 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4343 20:14:35.914297 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4344 20:14:35.921662 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4345 20:14:35.927761 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4346 20:14:35.928703 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4347 20:14:35.929156 ==
4348 20:14:35.932222 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 20:14:35.937699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4350 20:14:35.938277 ==
4351 20:14:35.938651 DQS Delay:
4352 20:14:35.938994 DQS0 = 0, DQS1 = 0
4353 20:14:35.941377 DQM Delay:
4354 20:14:35.941847 DQM0 = 38, DQM1 = 31
4355 20:14:35.944751 DQ Delay:
4356 20:14:35.947989 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4357 20:14:35.950740 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4358 20:14:35.951213 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4359 20:14:35.957564 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4360 20:14:35.958033
4361 20:14:35.958396
4362 20:14:35.958733 ==
4363 20:14:35.960823 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 20:14:35.964845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4365 20:14:35.965308 ==
4366 20:14:35.965673
4367 20:14:35.966009
4368 20:14:35.967662 TX Vref Scan disable
4369 20:14:35.968118 == TX Byte 0 ==
4370 20:14:35.973657 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4371 20:14:35.977256 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4372 20:14:35.977724 == TX Byte 1 ==
4373 20:14:35.983867 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4374 20:14:35.987251 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4375 20:14:35.987617 ==
4376 20:14:35.991298 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 20:14:35.994284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4378 20:14:35.994610 ==
4379 20:14:35.997304
4380 20:14:35.997622
4381 20:14:35.997871 TX Vref Scan disable
4382 20:14:36.000481 == TX Byte 0 ==
4383 20:14:36.003402 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4384 20:14:36.010196 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4385 20:14:36.010634 == TX Byte 1 ==
4386 20:14:36.014004 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4387 20:14:36.021391 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4388 20:14:36.021959
4389 20:14:36.022318 [DATLAT]
4390 20:14:36.022653 Freq=600, CH1 RK0
4391 20:14:36.022982
4392 20:14:36.024302 DATLAT Default: 0x9
4393 20:14:36.024794 0, 0xFFFF, sum = 0
4394 20:14:36.027259 1, 0xFFFF, sum = 0
4395 20:14:36.027865 2, 0xFFFF, sum = 0
4396 20:14:36.030617 3, 0xFFFF, sum = 0
4397 20:14:36.033620 4, 0xFFFF, sum = 0
4398 20:14:36.034086 5, 0xFFFF, sum = 0
4399 20:14:36.037199 6, 0xFFFF, sum = 0
4400 20:14:36.037684 7, 0x0, sum = 1
4401 20:14:36.038055 8, 0x0, sum = 2
4402 20:14:36.040657 9, 0x0, sum = 3
4403 20:14:36.041267 10, 0x0, sum = 4
4404 20:14:36.043729 best_step = 8
4405 20:14:36.044182
4406 20:14:36.044632 ==
4407 20:14:36.047067 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 20:14:36.052602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4409 20:14:36.053204 ==
4410 20:14:36.053935 RX Vref Scan: 1
4411 20:14:36.054309
4412 20:14:36.054642 RX Vref 0 -> 0, step: 1
4413 20:14:36.054967
4414 20:14:36.057732 RX Delay -195 -> 252, step: 8
4415 20:14:36.058210
4416 20:14:36.060667 Set Vref, RX VrefLevel [Byte0]: 55
4417 20:14:36.064320 [Byte1]: 49
4418 20:14:36.067753
4419 20:14:36.068290 Final RX Vref Byte 0 = 55 to rank0
4420 20:14:36.071462 Final RX Vref Byte 1 = 49 to rank0
4421 20:14:36.074989 Final RX Vref Byte 0 = 55 to rank1
4422 20:14:36.078015 Final RX Vref Byte 1 = 49 to rank1==
4423 20:14:36.081550 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 20:14:36.087227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4425 20:14:36.088025 ==
4426 20:14:36.088420 DQS Delay:
4427 20:14:36.088822 DQS0 = 0, DQS1 = 0
4428 20:14:36.092019 DQM Delay:
4429 20:14:36.092579 DQM0 = 37, DQM1 = 30
4430 20:14:36.095187 DQ Delay:
4431 20:14:36.098030 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4432 20:14:36.101180 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4433 20:14:36.104003 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =24
4434 20:14:36.107354 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4435 20:14:36.107860
4436 20:14:36.108237
4437 20:14:36.114776 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4438 20:14:36.117311 CH1 RK0: MR19=808, MR18=7272
4439 20:14:36.124110 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4440 20:14:36.124680
4441 20:14:36.127650 ----->DramcWriteLeveling(PI) begin...
4442 20:14:36.128219 ==
4443 20:14:36.130731 Dram Type= 6, Freq= 0, CH_1, rank 1
4444 20:14:36.134463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4445 20:14:36.135033 ==
4446 20:14:36.137357 Write leveling (Byte 0): 29 => 29
4447 20:14:36.140993 Write leveling (Byte 1): 28 => 28
4448 20:14:36.144549 DramcWriteLeveling(PI) end<-----
4449 20:14:36.145169
4450 20:14:36.145539 ==
4451 20:14:36.146958 Dram Type= 6, Freq= 0, CH_1, rank 1
4452 20:14:36.150991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4453 20:14:36.151560 ==
4454 20:14:36.153847 [Gating] SW mode calibration
4455 20:14:36.161050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4456 20:14:36.168345 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4457 20:14:36.171691 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 20:14:36.176747 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4459 20:14:36.180017 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4460 20:14:36.183661 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 20:14:36.190269 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 20:14:36.193513 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 20:14:36.196851 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 20:14:36.203303 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 20:14:36.206575 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 20:14:36.209615 0 6 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
4467 20:14:36.217919 0 6 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4468 20:14:36.219543 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 20:14:36.223644 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 20:14:36.229633 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 20:14:36.233334 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 20:14:36.236926 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 20:14:36.243290 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 20:14:36.246112 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4475 20:14:36.250055 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4476 20:14:36.256193 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 20:14:36.259899 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 20:14:36.263147 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 20:14:36.266268 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 20:14:36.273229 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 20:14:36.277318 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 20:14:36.279410 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 20:14:36.285982 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 20:14:36.289413 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 20:14:36.292541 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 20:14:36.299567 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 20:14:36.303685 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 20:14:36.305651 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 20:14:36.312504 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 20:14:36.315624 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4491 20:14:36.319772 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4492 20:14:36.323380 Total UI for P1: 0, mck2ui 16
4493 20:14:36.326010 best dqsien dly found for B0: ( 0, 9, 4)
4494 20:14:36.333729 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 20:14:36.335453 Total UI for P1: 0, mck2ui 16
4496 20:14:36.339412 best dqsien dly found for B1: ( 0, 9, 8)
4497 20:14:36.343042 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4498 20:14:36.345674 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4499 20:14:36.346140
4500 20:14:36.348834 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4501 20:14:36.352542 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4502 20:14:36.355445 [Gating] SW calibration Done
4503 20:14:36.356010 ==
4504 20:14:36.359288 Dram Type= 6, Freq= 0, CH_1, rank 1
4505 20:14:36.361920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4506 20:14:36.362387 ==
4507 20:14:36.366248 RX Vref Scan: 0
4508 20:14:36.366812
4509 20:14:36.367181 RX Vref 0 -> 0, step: 1
4510 20:14:36.367523
4511 20:14:36.369025 RX Delay -230 -> 252, step: 16
4512 20:14:36.375442 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4513 20:14:36.379189 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 20:14:36.382330 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4515 20:14:36.385420 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4516 20:14:36.388918 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 20:14:36.396833 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4518 20:14:36.398370 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 20:14:36.402094 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4520 20:14:36.405269 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4521 20:14:36.411822 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4522 20:14:36.414842 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4523 20:14:36.418916 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4524 20:14:36.421983 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 20:14:36.428005 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 20:14:36.431921 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4527 20:14:36.434758 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 20:14:36.435249 ==
4529 20:14:36.438188 Dram Type= 6, Freq= 0, CH_1, rank 1
4530 20:14:36.441417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4531 20:14:36.444880 ==
4532 20:14:36.445396 DQS Delay:
4533 20:14:36.445818 DQS0 = 0, DQS1 = 0
4534 20:14:36.447978 DQM Delay:
4535 20:14:36.448438 DQM0 = 39, DQM1 = 33
4536 20:14:36.451648 DQ Delay:
4537 20:14:36.452075 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4538 20:14:36.455290 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4539 20:14:36.459671 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4540 20:14:36.461651 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4541 20:14:36.464375
4542 20:14:36.464884
4543 20:14:36.465222 ==
4544 20:14:36.468971 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 20:14:36.471527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 20:14:36.472006 ==
4547 20:14:36.472373
4548 20:14:36.472751
4549 20:14:36.475795 TX Vref Scan disable
4550 20:14:36.476397 == TX Byte 0 ==
4551 20:14:36.480784 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4552 20:14:36.484593 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4553 20:14:36.485194 == TX Byte 1 ==
4554 20:14:36.491151 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4555 20:14:36.494743 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4556 20:14:36.495226 ==
4557 20:14:36.498101 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 20:14:36.501227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 20:14:36.501692 ==
4560 20:14:36.502053
4561 20:14:36.502388
4562 20:14:36.505069 TX Vref Scan disable
4563 20:14:36.507507 == TX Byte 0 ==
4564 20:14:36.511186 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4565 20:14:36.514066 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4566 20:14:36.517189 == TX Byte 1 ==
4567 20:14:36.520947 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 20:14:36.527370 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 20:14:36.527930
4570 20:14:36.528407 [DATLAT]
4571 20:14:36.528814 Freq=600, CH1 RK1
4572 20:14:36.529157
4573 20:14:36.530465 DATLAT Default: 0x8
4574 20:14:36.530935 0, 0xFFFF, sum = 0
4575 20:14:36.533634 1, 0xFFFF, sum = 0
4576 20:14:36.538034 2, 0xFFFF, sum = 0
4577 20:14:36.538642 3, 0xFFFF, sum = 0
4578 20:14:36.540980 4, 0xFFFF, sum = 0
4579 20:14:36.541546 5, 0xFFFF, sum = 0
4580 20:14:36.543959 6, 0xFFFF, sum = 0
4581 20:14:36.544562 7, 0x0, sum = 1
4582 20:14:36.544988 8, 0x0, sum = 2
4583 20:14:36.547448 9, 0x0, sum = 3
4584 20:14:36.548030 10, 0x0, sum = 4
4585 20:14:36.550657 best_step = 8
4586 20:14:36.551321
4587 20:14:36.551696 ==
4588 20:14:36.554106 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 20:14:36.557911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4590 20:14:36.558469 ==
4591 20:14:36.560178 RX Vref Scan: 0
4592 20:14:36.560640
4593 20:14:36.561040 RX Vref 0 -> 0, step: 1
4594 20:14:36.561384
4595 20:14:36.563705 RX Delay -195 -> 252, step: 8
4596 20:14:36.571516 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4597 20:14:36.574336 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4598 20:14:36.577694 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4599 20:14:36.581421 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4600 20:14:36.588098 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4601 20:14:36.591221 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4602 20:14:36.594311 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4603 20:14:36.597875 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4604 20:14:36.600696 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4605 20:14:36.607565 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4606 20:14:36.611161 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4607 20:14:36.614120 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4608 20:14:36.618009 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4609 20:14:36.624079 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4610 20:14:36.627588 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4611 20:14:36.630564 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4612 20:14:36.631130 ==
4613 20:14:36.633862 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 20:14:36.640586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4615 20:14:36.641191 ==
4616 20:14:36.641561 DQS Delay:
4617 20:14:36.643717 DQS0 = 0, DQS1 = 0
4618 20:14:36.644265 DQM Delay:
4619 20:14:36.644638 DQM0 = 36, DQM1 = 30
4620 20:14:36.647576 DQ Delay:
4621 20:14:36.651221 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4622 20:14:36.653890 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4623 20:14:36.657300 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4624 20:14:36.660581 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4625 20:14:36.661275
4626 20:14:36.661681
4627 20:14:36.667322 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4628 20:14:36.670712 CH1 RK1: MR19=808, MR18=5858
4629 20:14:36.676971 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4630 20:14:36.680362 [RxdqsGatingPostProcess] freq 600
4631 20:14:36.684009 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4632 20:14:36.686788 Pre-setting of DQS Precalculation
4633 20:14:36.693142 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4634 20:14:36.700464 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4635 20:14:36.707075 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4636 20:14:36.707639
4637 20:14:36.708046
4638 20:14:36.710335 [Calibration Summary] 1200 Mbps
4639 20:14:36.710828 CH 0, Rank 0
4640 20:14:36.713107 SW Impedance : PASS
4641 20:14:36.716857 DUTY Scan : NO K
4642 20:14:36.717415 ZQ Calibration : PASS
4643 20:14:36.719987 Jitter Meter : NO K
4644 20:14:36.722920 CBT Training : PASS
4645 20:14:36.723481 Write leveling : PASS
4646 20:14:36.726741 RX DQS gating : PASS
4647 20:14:36.729768 RX DQ/DQS(RDDQC) : PASS
4648 20:14:36.730331 TX DQ/DQS : PASS
4649 20:14:36.732876 RX DATLAT : PASS
4650 20:14:36.736244 RX DQ/DQS(Engine): PASS
4651 20:14:36.736844 TX OE : NO K
4652 20:14:36.739653 All Pass.
4653 20:14:36.740207
4654 20:14:36.740578 CH 0, Rank 1
4655 20:14:36.743091 SW Impedance : PASS
4656 20:14:36.743563 DUTY Scan : NO K
4657 20:14:36.745849 ZQ Calibration : PASS
4658 20:14:36.750969 Jitter Meter : NO K
4659 20:14:36.751440 CBT Training : PASS
4660 20:14:36.752843 Write leveling : PASS
4661 20:14:36.755750 RX DQS gating : PASS
4662 20:14:36.756385 RX DQ/DQS(RDDQC) : PASS
4663 20:14:36.760054 TX DQ/DQS : PASS
4664 20:14:36.760612 RX DATLAT : PASS
4665 20:14:36.762941 RX DQ/DQS(Engine): PASS
4666 20:14:36.766269 TX OE : NO K
4667 20:14:36.766771 All Pass.
4668 20:14:36.767145
4669 20:14:36.769567 CH 1, Rank 0
4670 20:14:36.770127 SW Impedance : PASS
4671 20:14:36.773248 DUTY Scan : NO K
4672 20:14:36.773773 ZQ Calibration : PASS
4673 20:14:36.776003 Jitter Meter : NO K
4674 20:14:36.779120 CBT Training : PASS
4675 20:14:36.779683 Write leveling : PASS
4676 20:14:36.782621 RX DQS gating : PASS
4677 20:14:36.785594 RX DQ/DQS(RDDQC) : PASS
4678 20:14:36.786104 TX DQ/DQS : PASS
4679 20:14:36.788791 RX DATLAT : PASS
4680 20:14:36.792545 RX DQ/DQS(Engine): PASS
4681 20:14:36.793100 TX OE : NO K
4682 20:14:36.795902 All Pass.
4683 20:14:36.796460
4684 20:14:36.796897 CH 1, Rank 1
4685 20:14:36.799316 SW Impedance : PASS
4686 20:14:36.799783 DUTY Scan : NO K
4687 20:14:36.802637 ZQ Calibration : PASS
4688 20:14:36.805437 Jitter Meter : NO K
4689 20:14:36.805972 CBT Training : PASS
4690 20:14:36.809379 Write leveling : PASS
4691 20:14:36.812351 RX DQS gating : PASS
4692 20:14:36.812971 RX DQ/DQS(RDDQC) : PASS
4693 20:14:36.816183 TX DQ/DQS : PASS
4694 20:14:36.818821 RX DATLAT : PASS
4695 20:14:36.819294 RX DQ/DQS(Engine): PASS
4696 20:14:36.822337 TX OE : NO K
4697 20:14:36.822946 All Pass.
4698 20:14:36.823327
4699 20:14:36.825448 DramC Write-DBI off
4700 20:14:36.830088 PER_BANK_REFRESH: Hybrid Mode
4701 20:14:36.830653 TX_TRACKING: ON
4702 20:14:36.838882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4703 20:14:36.842125 [FAST_K] Save calibration result to emmc
4704 20:14:36.846661 dramc_set_vcore_voltage set vcore to 662500
4705 20:14:36.848914 Read voltage for 933, 3
4706 20:14:36.849476 Vio18 = 0
4707 20:14:36.849846 Vcore = 662500
4708 20:14:36.852324 Vdram = 0
4709 20:14:36.852852 Vddq = 0
4710 20:14:36.853336 Vmddr = 0
4711 20:14:36.858887 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4712 20:14:36.862072 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4713 20:14:36.865191 MEM_TYPE=3, freq_sel=17
4714 20:14:36.868836 sv_algorithm_assistance_LP4_1600
4715 20:14:36.871966 ============ PULL DRAM RESETB DOWN ============
4716 20:14:36.875016 ========== PULL DRAM RESETB DOWN end =========
4717 20:14:36.882598 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4718 20:14:36.885233 ===================================
4719 20:14:36.885799 LPDDR4 DRAM CONFIGURATION
4720 20:14:36.888914 ===================================
4721 20:14:36.891765 EX_ROW_EN[0] = 0x0
4722 20:14:36.894685 EX_ROW_EN[1] = 0x0
4723 20:14:36.895243 LP4Y_EN = 0x0
4724 20:14:36.898458 WORK_FSP = 0x0
4725 20:14:36.899021 WL = 0x3
4726 20:14:36.901529 RL = 0x3
4727 20:14:36.902027 BL = 0x2
4728 20:14:36.904878 RPST = 0x0
4729 20:14:36.905503 RD_PRE = 0x0
4730 20:14:36.908372 WR_PRE = 0x1
4731 20:14:36.909115 WR_PST = 0x0
4732 20:14:36.912334 DBI_WR = 0x0
4733 20:14:36.912840 DBI_RD = 0x0
4734 20:14:36.915173 OTF = 0x1
4735 20:14:36.918387 ===================================
4736 20:14:36.921401 ===================================
4737 20:14:36.921871 ANA top config
4738 20:14:36.924885 ===================================
4739 20:14:36.928043 DLL_ASYNC_EN = 0
4740 20:14:36.931832 ALL_SLAVE_EN = 1
4741 20:14:36.935050 NEW_RANK_MODE = 1
4742 20:14:36.935684 DLL_IDLE_MODE = 1
4743 20:14:36.937932 LP45_APHY_COMB_EN = 1
4744 20:14:36.941405 TX_ODT_DIS = 1
4745 20:14:36.945406 NEW_8X_MODE = 1
4746 20:14:36.948050 ===================================
4747 20:14:36.951213 ===================================
4748 20:14:36.954394 data_rate = 1866
4749 20:14:36.954861 CKR = 1
4750 20:14:36.957611 DQ_P2S_RATIO = 8
4751 20:14:36.961737 ===================================
4752 20:14:36.964599 CA_P2S_RATIO = 8
4753 20:14:36.967716 DQ_CA_OPEN = 0
4754 20:14:36.971571 DQ_SEMI_OPEN = 0
4755 20:14:36.974247 CA_SEMI_OPEN = 0
4756 20:14:36.974646 CA_FULL_RATE = 0
4757 20:14:36.979483 DQ_CKDIV4_EN = 1
4758 20:14:36.980534 CA_CKDIV4_EN = 1
4759 20:14:36.984027 CA_PREDIV_EN = 0
4760 20:14:36.987249 PH8_DLY = 0
4761 20:14:36.991175 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4762 20:14:36.991313 DQ_AAMCK_DIV = 4
4763 20:14:36.993973 CA_AAMCK_DIV = 4
4764 20:14:36.997550 CA_ADMCK_DIV = 4
4765 20:14:37.001452 DQ_TRACK_CA_EN = 0
4766 20:14:37.003763 CA_PICK = 933
4767 20:14:37.007010 CA_MCKIO = 933
4768 20:14:37.007166 MCKIO_SEMI = 0
4769 20:14:37.010457 PLL_FREQ = 3732
4770 20:14:37.014041 DQ_UI_PI_RATIO = 32
4771 20:14:37.018325 CA_UI_PI_RATIO = 0
4772 20:14:37.020751 ===================================
4773 20:14:37.024145 ===================================
4774 20:14:37.027822 memory_type:LPDDR4
4775 20:14:37.028247 GP_NUM : 10
4776 20:14:37.030815 SRAM_EN : 1
4777 20:14:37.034384 MD32_EN : 0
4778 20:14:37.037322 ===================================
4779 20:14:37.037845 [ANA_INIT] >>>>>>>>>>>>>>
4780 20:14:37.040801 <<<<<< [CONFIGURE PHASE]: ANA_TX
4781 20:14:37.044239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4782 20:14:37.046922 ===================================
4783 20:14:37.050192 data_rate = 1866,PCW = 0X8f00
4784 20:14:37.053497 ===================================
4785 20:14:37.057244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4786 20:14:37.063365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4787 20:14:37.066906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 20:14:37.073133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4789 20:14:37.076534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4790 20:14:37.079745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4791 20:14:37.083319 [ANA_INIT] flow start
4792 20:14:37.083422 [ANA_INIT] PLL >>>>>>>>
4793 20:14:37.087017 [ANA_INIT] PLL <<<<<<<<
4794 20:14:37.090066 [ANA_INIT] MIDPI >>>>>>>>
4795 20:14:37.090492 [ANA_INIT] MIDPI <<<<<<<<
4796 20:14:37.093367 [ANA_INIT] DLL >>>>>>>>
4797 20:14:37.096828 [ANA_INIT] flow end
4798 20:14:37.100064 ============ LP4 DIFF to SE enter ============
4799 20:14:37.103565 ============ LP4 DIFF to SE exit ============
4800 20:14:37.106467 [ANA_INIT] <<<<<<<<<<<<<
4801 20:14:37.109821 [Flow] Enable top DCM control >>>>>
4802 20:14:37.112970 [Flow] Enable top DCM control <<<<<
4803 20:14:37.116415 Enable DLL master slave shuffle
4804 20:14:37.119458 ==============================================================
4805 20:14:37.123509 Gating Mode config
4806 20:14:37.129775 ==============================================================
4807 20:14:37.129892 Config description:
4808 20:14:37.139937 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4809 20:14:37.147842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4810 20:14:37.149543 SELPH_MODE 0: By rank 1: By Phase
4811 20:14:37.156692 ==============================================================
4812 20:14:37.159275 GAT_TRACK_EN = 1
4813 20:14:37.163277 RX_GATING_MODE = 2
4814 20:14:37.166396 RX_GATING_TRACK_MODE = 2
4815 20:14:37.170612 SELPH_MODE = 1
4816 20:14:37.172837 PICG_EARLY_EN = 1
4817 20:14:37.176501 VALID_LAT_VALUE = 1
4818 20:14:37.179627 ==============================================================
4819 20:14:37.182821 Enter into Gating configuration >>>>
4820 20:14:37.186296 Exit from Gating configuration <<<<
4821 20:14:37.189069 Enter into DVFS_PRE_config >>>>>
4822 20:14:37.203251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4823 20:14:37.206037 Exit from DVFS_PRE_config <<<<<
4824 20:14:37.206415 Enter into PICG configuration >>>>
4825 20:14:37.209596 Exit from PICG configuration <<<<
4826 20:14:37.212815 [RX_INPUT] configuration >>>>>
4827 20:14:37.216420 [RX_INPUT] configuration <<<<<
4828 20:14:37.222873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4829 20:14:37.226205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4830 20:14:37.232964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4831 20:14:37.239475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4832 20:14:37.245878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4833 20:14:37.252686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4834 20:14:37.255942 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4835 20:14:37.259140 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4836 20:14:37.262289 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4837 20:14:37.269118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4838 20:14:37.272448 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4839 20:14:37.275463 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4840 20:14:37.279300 ===================================
4841 20:14:37.282057 LPDDR4 DRAM CONFIGURATION
4842 20:14:37.286283 ===================================
4843 20:14:37.289559 EX_ROW_EN[0] = 0x0
4844 20:14:37.290120 EX_ROW_EN[1] = 0x0
4845 20:14:37.292003 LP4Y_EN = 0x0
4846 20:14:37.292463 WORK_FSP = 0x0
4847 20:14:37.295945 WL = 0x3
4848 20:14:37.296423 RL = 0x3
4849 20:14:37.299226 BL = 0x2
4850 20:14:37.299691 RPST = 0x0
4851 20:14:37.302634 RD_PRE = 0x0
4852 20:14:37.303196 WR_PRE = 0x1
4853 20:14:37.305443 WR_PST = 0x0
4854 20:14:37.305906 DBI_WR = 0x0
4855 20:14:37.309311 DBI_RD = 0x0
4856 20:14:37.309776 OTF = 0x1
4857 20:14:37.311802 ===================================
4858 20:14:37.319016 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4859 20:14:37.322120 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4860 20:14:37.325780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 20:14:37.328778 ===================================
4862 20:14:37.332406 LPDDR4 DRAM CONFIGURATION
4863 20:14:37.335757 ===================================
4864 20:14:37.338501 EX_ROW_EN[0] = 0x10
4865 20:14:37.339108 EX_ROW_EN[1] = 0x0
4866 20:14:37.342198 LP4Y_EN = 0x0
4867 20:14:37.342730 WORK_FSP = 0x0
4868 20:14:37.345496 WL = 0x3
4869 20:14:37.346159 RL = 0x3
4870 20:14:37.348397 BL = 0x2
4871 20:14:37.348895 RPST = 0x0
4872 20:14:37.351627 RD_PRE = 0x0
4873 20:14:37.352099 WR_PRE = 0x1
4874 20:14:37.355568 WR_PST = 0x0
4875 20:14:37.356042 DBI_WR = 0x0
4876 20:14:37.358325 DBI_RD = 0x0
4877 20:14:37.358792 OTF = 0x1
4878 20:14:37.362323 ===================================
4879 20:14:37.368905 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4880 20:14:37.373645 nWR fixed to 30
4881 20:14:37.376310 [ModeRegInit_LP4] CH0 RK0
4882 20:14:37.376897 [ModeRegInit_LP4] CH0 RK1
4883 20:14:37.379816 [ModeRegInit_LP4] CH1 RK0
4884 20:14:37.382818 [ModeRegInit_LP4] CH1 RK1
4885 20:14:37.383286 match AC timing 8
4886 20:14:37.389937 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4887 20:14:37.392984 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4888 20:14:37.396126 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4889 20:14:37.402787 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4890 20:14:37.406427 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4891 20:14:37.406986 ==
4892 20:14:37.409008 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 20:14:37.413435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 20:14:37.413910 ==
4895 20:14:37.418966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4896 20:14:37.425597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4897 20:14:37.429673 [CA 0] Center 38 (8~69) winsize 62
4898 20:14:37.432411 [CA 1] Center 38 (8~69) winsize 62
4899 20:14:37.436073 [CA 2] Center 36 (6~67) winsize 62
4900 20:14:37.438721 [CA 3] Center 36 (5~67) winsize 63
4901 20:14:37.442157 [CA 4] Center 35 (5~65) winsize 61
4902 20:14:37.445861 [CA 5] Center 34 (4~65) winsize 62
4903 20:14:37.446497
4904 20:14:37.448695 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4905 20:14:37.449203
4906 20:14:37.452004 [CATrainingPosCal] consider 1 rank data
4907 20:14:37.455577 u2DelayCellTimex100 = 270/100 ps
4908 20:14:37.459268 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4909 20:14:37.462301 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4910 20:14:37.465577 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4911 20:14:37.468674 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4912 20:14:37.475134 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4913 20:14:37.479398 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4914 20:14:37.479964
4915 20:14:37.482141 CA PerBit enable=1, Macro0, CA PI delay=34
4916 20:14:37.482605
4917 20:14:37.485698 [CBTSetCACLKResult] CA Dly = 34
4918 20:14:37.486238 CS Dly: 7 (0~38)
4919 20:14:37.486605 ==
4920 20:14:37.488531 Dram Type= 6, Freq= 0, CH_0, rank 1
4921 20:14:37.495331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4922 20:14:37.495885 ==
4923 20:14:37.498916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4924 20:14:37.505255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4925 20:14:37.508544 [CA 0] Center 38 (8~69) winsize 62
4926 20:14:37.511944 [CA 1] Center 38 (8~69) winsize 62
4927 20:14:37.515322 [CA 2] Center 36 (5~67) winsize 63
4928 20:14:37.518113 [CA 3] Center 35 (5~66) winsize 62
4929 20:14:37.521788 [CA 4] Center 34 (4~65) winsize 62
4930 20:14:37.524398 [CA 5] Center 34 (4~65) winsize 62
4931 20:14:37.524985
4932 20:14:37.528138 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4933 20:14:37.528795
4934 20:14:37.531747 [CATrainingPosCal] consider 2 rank data
4935 20:14:37.535510 u2DelayCellTimex100 = 270/100 ps
4936 20:14:37.538039 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4937 20:14:37.545249 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 20:14:37.547836 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4939 20:14:37.551514 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4940 20:14:37.554712 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4941 20:14:37.558089 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4942 20:14:37.558513
4943 20:14:37.561475 CA PerBit enable=1, Macro0, CA PI delay=34
4944 20:14:37.561919
4945 20:14:37.564649 [CBTSetCACLKResult] CA Dly = 34
4946 20:14:37.565222 CS Dly: 7 (0~39)
4947 20:14:37.568513
4948 20:14:37.571205 ----->DramcWriteLeveling(PI) begin...
4949 20:14:37.571638 ==
4950 20:14:37.574439 Dram Type= 6, Freq= 0, CH_0, rank 0
4951 20:14:37.577652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4952 20:14:37.578083 ==
4953 20:14:37.581302 Write leveling (Byte 0): 28 => 28
4954 20:14:37.585041 Write leveling (Byte 1): 28 => 28
4955 20:14:37.587281 DramcWriteLeveling(PI) end<-----
4956 20:14:37.587709
4957 20:14:37.588040 ==
4958 20:14:37.591735 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 20:14:37.594331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 20:14:37.594979 ==
4961 20:14:37.597400 [Gating] SW mode calibration
4962 20:14:37.604300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4963 20:14:37.611214 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4964 20:14:37.614001 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4965 20:14:37.617818 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 20:14:37.624133 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 20:14:37.627355 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 20:14:37.631146 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 20:14:37.638151 0 10 20 | B1->B0 | 3232 3030 | 1 0 | (1 0) (0 0)
4970 20:14:37.640822 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4971 20:14:37.644113 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4972 20:14:37.650452 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 20:14:37.654051 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 20:14:37.656933 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 20:14:37.663558 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 20:14:37.667042 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 20:14:37.669934 0 11 20 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4978 20:14:37.676946 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4979 20:14:37.680361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4980 20:14:37.683267 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 20:14:37.690592 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 20:14:37.693167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 20:14:37.696887 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 20:14:37.703563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 20:14:37.706565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4986 20:14:37.709526 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4987 20:14:37.716884 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 20:14:37.720497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 20:14:37.722975 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 20:14:37.730570 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 20:14:37.732977 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 20:14:37.736172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 20:14:37.744358 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 20:14:37.747401 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 20:14:37.749429 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 20:14:37.756314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 20:14:37.759138 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 20:14:37.762607 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 20:14:37.769579 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 20:14:37.772435 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 20:14:37.775580 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5002 20:14:37.782447 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5003 20:14:37.785931 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 20:14:37.789454 Total UI for P1: 0, mck2ui 16
5005 20:14:37.792452 best dqsien dly found for B0: ( 0, 14, 22)
5006 20:14:37.796065 Total UI for P1: 0, mck2ui 16
5007 20:14:37.799069 best dqsien dly found for B1: ( 0, 14, 22)
5008 20:14:37.802545 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5009 20:14:37.805407 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5010 20:14:37.805897
5011 20:14:37.809114 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5012 20:14:37.812518 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5013 20:14:37.815632 [Gating] SW calibration Done
5014 20:14:37.816104 ==
5015 20:14:37.818706 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 20:14:37.822711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 20:14:37.825425 ==
5018 20:14:37.825895 RX Vref Scan: 0
5019 20:14:37.826266
5020 20:14:37.828846 RX Vref 0 -> 0, step: 1
5021 20:14:37.829412
5022 20:14:37.832155 RX Delay -80 -> 252, step: 8
5023 20:14:37.834913 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5024 20:14:37.838382 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5025 20:14:37.841935 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5026 20:14:37.845317 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5027 20:14:37.851903 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5028 20:14:37.854821 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5029 20:14:37.858582 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5030 20:14:37.861614 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5031 20:14:37.864865 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5032 20:14:37.868363 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5033 20:14:37.874697 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5034 20:14:37.879329 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5035 20:14:37.881618 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5036 20:14:37.885095 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5037 20:14:37.888033 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5038 20:14:37.894945 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5039 20:14:37.895482 ==
5040 20:14:37.897824 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 20:14:37.901291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 20:14:37.901758 ==
5043 20:14:37.902121 DQS Delay:
5044 20:14:37.904920 DQS0 = 0, DQS1 = 0
5045 20:14:37.905379 DQM Delay:
5046 20:14:37.907865 DQM0 = 95, DQM1 = 86
5047 20:14:37.908324 DQ Delay:
5048 20:14:37.911426 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5049 20:14:37.914794 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5050 20:14:37.917949 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5051 20:14:37.920747 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =95
5052 20:14:37.921228
5053 20:14:37.921589
5054 20:14:37.921929 ==
5055 20:14:37.924665 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 20:14:37.927406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 20:14:37.931129 ==
5058 20:14:37.931692
5059 20:14:37.932075
5060 20:14:37.932458 TX Vref Scan disable
5061 20:14:37.935237 == TX Byte 0 ==
5062 20:14:37.937579 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5063 20:14:37.941093 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5064 20:14:37.943999 == TX Byte 1 ==
5065 20:14:37.947783 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5066 20:14:37.951288 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5067 20:14:37.953798 ==
5068 20:14:37.957944 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 20:14:37.961084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 20:14:37.961654 ==
5071 20:14:37.962028
5072 20:14:37.962375
5073 20:14:37.963653 TX Vref Scan disable
5074 20:14:37.964126 == TX Byte 0 ==
5075 20:14:37.970392 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5076 20:14:37.973937 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5077 20:14:37.974495 == TX Byte 1 ==
5078 20:14:37.981033 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5079 20:14:37.984463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5080 20:14:37.985081
5081 20:14:37.985457 [DATLAT]
5082 20:14:37.987858 Freq=933, CH0 RK0
5083 20:14:37.988414
5084 20:14:37.988838 DATLAT Default: 0xd
5085 20:14:37.990842 0, 0xFFFF, sum = 0
5086 20:14:37.991583 1, 0xFFFF, sum = 0
5087 20:14:37.994338 2, 0xFFFF, sum = 0
5088 20:14:37.994900 3, 0xFFFF, sum = 0
5089 20:14:37.996759 4, 0xFFFF, sum = 0
5090 20:14:37.997242 5, 0xFFFF, sum = 0
5091 20:14:38.000479 6, 0xFFFF, sum = 0
5092 20:14:38.003779 7, 0xFFFF, sum = 0
5093 20:14:38.004371 8, 0xFFFF, sum = 0
5094 20:14:38.007493 9, 0xFFFF, sum = 0
5095 20:14:38.007963 10, 0x0, sum = 1
5096 20:14:38.008336 11, 0x0, sum = 2
5097 20:14:38.010848 12, 0x0, sum = 3
5098 20:14:38.011419 13, 0x0, sum = 4
5099 20:14:38.013294 best_step = 11
5100 20:14:38.013755
5101 20:14:38.014115 ==
5102 20:14:38.017253 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 20:14:38.020642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 20:14:38.021150 ==
5105 20:14:38.023085 RX Vref Scan: 1
5106 20:14:38.023598
5107 20:14:38.023964 RX Vref 0 -> 0, step: 1
5108 20:14:38.028066
5109 20:14:38.028627 RX Delay -69 -> 252, step: 4
5110 20:14:38.029143
5111 20:14:38.030371 Set Vref, RX VrefLevel [Byte0]: 53
5112 20:14:38.034175 [Byte1]: 50
5113 20:14:38.037797
5114 20:14:38.038370 Final RX Vref Byte 0 = 53 to rank0
5115 20:14:38.041051 Final RX Vref Byte 1 = 50 to rank0
5116 20:14:38.044485 Final RX Vref Byte 0 = 53 to rank1
5117 20:14:38.048051 Final RX Vref Byte 1 = 50 to rank1==
5118 20:14:38.051214 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 20:14:38.057664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 20:14:38.058140 ==
5121 20:14:38.058514 DQS Delay:
5122 20:14:38.061405 DQS0 = 0, DQS1 = 0
5123 20:14:38.061919 DQM Delay:
5124 20:14:38.062297 DQM0 = 96, DQM1 = 87
5125 20:14:38.064590 DQ Delay:
5126 20:14:38.067327 DQ0 =92, DQ1 =96, DQ2 =94, DQ3 =92
5127 20:14:38.070963 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5128 20:14:38.074562 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5129 20:14:38.077851 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5130 20:14:38.078324
5131 20:14:38.078694
5132 20:14:38.083980 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5133 20:14:38.087198 CH0 RK0: MR19=505, MR18=2525
5134 20:14:38.093764 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5135 20:14:38.094327
5136 20:14:38.097710 ----->DramcWriteLeveling(PI) begin...
5137 20:14:38.098269 ==
5138 20:14:38.100820 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 20:14:38.104446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 20:14:38.105065 ==
5141 20:14:38.106819 Write leveling (Byte 0): 28 => 28
5142 20:14:38.110473 Write leveling (Byte 1): 28 => 28
5143 20:14:38.113571 DramcWriteLeveling(PI) end<-----
5144 20:14:38.114122
5145 20:14:38.114495 ==
5146 20:14:38.116898 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 20:14:38.120778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 20:14:38.123581 ==
5149 20:14:38.124047 [Gating] SW mode calibration
5150 20:14:38.133675 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 20:14:38.137400 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5152 20:14:38.140366 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 20:14:38.147235 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 20:14:38.150372 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 20:14:38.153256 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 20:14:38.159773 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5157 20:14:38.163341 0 10 20 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5158 20:14:38.167422 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5159 20:14:38.173483 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 20:14:38.176575 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 20:14:38.179863 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 20:14:38.186683 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 20:14:38.190277 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 20:14:38.193565 0 11 16 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
5165 20:14:38.200009 0 11 20 | B1->B0 | 2929 3837 | 0 1 | (0 0) (0 0)
5166 20:14:38.203090 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5167 20:14:38.206494 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 20:14:38.213866 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 20:14:38.216781 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 20:14:38.220317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 20:14:38.226002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 20:14:38.229820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5173 20:14:38.233364 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5174 20:14:38.240322 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 20:14:38.243085 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 20:14:38.246267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 20:14:38.253383 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 20:14:38.255788 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 20:14:38.259019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 20:14:38.265771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 20:14:38.269349 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 20:14:38.272938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 20:14:38.279712 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 20:14:38.282432 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 20:14:38.287241 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 20:14:38.293297 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 20:14:38.296247 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 20:14:38.299276 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 20:14:38.305573 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5190 20:14:38.309696 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 20:14:38.311909 Total UI for P1: 0, mck2ui 16
5192 20:14:38.315462 best dqsien dly found for B0: ( 0, 14, 20)
5193 20:14:38.319822 Total UI for P1: 0, mck2ui 16
5194 20:14:38.322383 best dqsien dly found for B1: ( 0, 14, 20)
5195 20:14:38.325769 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5196 20:14:38.329279 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5197 20:14:38.329884
5198 20:14:38.331858 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5199 20:14:38.335491 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5200 20:14:38.339401 [Gating] SW calibration Done
5201 20:14:38.339964 ==
5202 20:14:38.342921 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 20:14:38.345651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 20:14:38.348917 ==
5205 20:14:38.349484 RX Vref Scan: 0
5206 20:14:38.349858
5207 20:14:38.352318 RX Vref 0 -> 0, step: 1
5208 20:14:38.352926
5209 20:14:38.355053 RX Delay -80 -> 252, step: 8
5210 20:14:38.358412 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5211 20:14:38.362822 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 20:14:38.365057 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5213 20:14:38.369113 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5214 20:14:38.371414 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5215 20:14:38.378105 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5216 20:14:38.381688 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5217 20:14:38.384855 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 20:14:38.388637 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5219 20:14:38.392195 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5220 20:14:38.398784 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5221 20:14:38.402709 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 20:14:38.404759 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5223 20:14:38.408397 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5224 20:14:38.411244 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5225 20:14:38.417889 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5226 20:14:38.418456 ==
5227 20:14:38.421264 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 20:14:38.425405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 20:14:38.425879 ==
5230 20:14:38.426252 DQS Delay:
5231 20:14:38.428508 DQS0 = 0, DQS1 = 0
5232 20:14:38.429103 DQM Delay:
5233 20:14:38.431106 DQM0 = 96, DQM1 = 83
5234 20:14:38.431667 DQ Delay:
5235 20:14:38.434541 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5236 20:14:38.437918 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5237 20:14:38.441649 DQ8 =71, DQ9 =67, DQ10 =87, DQ11 =79
5238 20:14:38.444666 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5239 20:14:38.445279
5240 20:14:38.445654
5241 20:14:38.445998 ==
5242 20:14:38.448340 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 20:14:38.452175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 20:14:38.452786 ==
5245 20:14:38.454472
5246 20:14:38.454939
5247 20:14:38.455302 TX Vref Scan disable
5248 20:14:38.458302 == TX Byte 0 ==
5249 20:14:38.460676 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5250 20:14:38.464249 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5251 20:14:38.467336 == TX Byte 1 ==
5252 20:14:38.471340 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5253 20:14:38.474094 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5254 20:14:38.474567 ==
5255 20:14:38.477778 Dram Type= 6, Freq= 0, CH_0, rank 1
5256 20:14:38.483936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5257 20:14:38.484485 ==
5258 20:14:38.484897
5259 20:14:38.485245
5260 20:14:38.485572 TX Vref Scan disable
5261 20:14:38.488490 == TX Byte 0 ==
5262 20:14:38.491641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5263 20:14:38.499001 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5264 20:14:38.499652 == TX Byte 1 ==
5265 20:14:38.502070 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5266 20:14:38.509435 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5267 20:14:38.510008
5268 20:14:38.510383 [DATLAT]
5269 20:14:38.510731 Freq=933, CH0 RK1
5270 20:14:38.511073
5271 20:14:38.512248 DATLAT Default: 0xb
5272 20:14:38.512760 0, 0xFFFF, sum = 0
5273 20:14:38.515428 1, 0xFFFF, sum = 0
5274 20:14:38.516015 2, 0xFFFF, sum = 0
5275 20:14:38.519096 3, 0xFFFF, sum = 0
5276 20:14:38.521403 4, 0xFFFF, sum = 0
5277 20:14:38.521896 5, 0xFFFF, sum = 0
5278 20:14:38.524831 6, 0xFFFF, sum = 0
5279 20:14:38.525308 7, 0xFFFF, sum = 0
5280 20:14:38.528887 8, 0xFFFF, sum = 0
5281 20:14:38.529465 9, 0xFFFF, sum = 0
5282 20:14:38.531461 10, 0x0, sum = 1
5283 20:14:38.532032 11, 0x0, sum = 2
5284 20:14:38.535181 12, 0x0, sum = 3
5285 20:14:38.535757 13, 0x0, sum = 4
5286 20:14:38.536137 best_step = 11
5287 20:14:38.536487
5288 20:14:38.537966 ==
5289 20:14:38.541687 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 20:14:38.545286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 20:14:38.545845 ==
5292 20:14:38.546216 RX Vref Scan: 0
5293 20:14:38.546563
5294 20:14:38.548741 RX Vref 0 -> 0, step: 1
5295 20:14:38.549357
5296 20:14:38.551412 RX Delay -77 -> 252, step: 4
5297 20:14:38.554882 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5298 20:14:38.561719 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5299 20:14:38.564897 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5300 20:14:38.568183 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5301 20:14:38.571205 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5302 20:14:38.575479 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5303 20:14:38.580996 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5304 20:14:38.584386 iDelay=203, Bit 7, Center 110 (19 ~ 202) 184
5305 20:14:38.588197 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5306 20:14:38.591493 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5307 20:14:38.594126 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5308 20:14:38.597622 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5309 20:14:38.604560 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5310 20:14:38.608344 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5311 20:14:38.610929 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5312 20:14:38.614043 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5313 20:14:38.614553 ==
5314 20:14:38.617242 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 20:14:38.624283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 20:14:38.625091 ==
5317 20:14:38.625525 DQS Delay:
5318 20:14:38.625881 DQS0 = 0, DQS1 = 0
5319 20:14:38.627745 DQM Delay:
5320 20:14:38.628214 DQM0 = 98, DQM1 = 86
5321 20:14:38.630891 DQ Delay:
5322 20:14:38.634643 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5323 20:14:38.637190 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =110
5324 20:14:38.641072 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5325 20:14:38.643888 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5326 20:14:38.644314
5327 20:14:38.644645
5328 20:14:38.650645 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5329 20:14:38.653869 CH0 RK1: MR19=505, MR18=2B2B
5330 20:14:38.660657 CH0_RK1: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5331 20:14:38.663671 [RxdqsGatingPostProcess] freq 933
5332 20:14:38.667681 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5333 20:14:38.670350 Pre-setting of DQS Precalculation
5334 20:14:38.677154 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5335 20:14:38.677677 ==
5336 20:14:38.680591 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 20:14:38.683835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 20:14:38.684307 ==
5339 20:14:38.691556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5340 20:14:38.697155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5341 20:14:38.700331 [CA 0] Center 37 (7~68) winsize 62
5342 20:14:38.703624 [CA 1] Center 37 (6~68) winsize 63
5343 20:14:38.706528 [CA 2] Center 35 (5~65) winsize 61
5344 20:14:38.710205 [CA 3] Center 34 (3~65) winsize 63
5345 20:14:38.713248 [CA 4] Center 32 (2~63) winsize 62
5346 20:14:38.716358 [CA 5] Center 33 (3~64) winsize 62
5347 20:14:38.716991
5348 20:14:38.720192 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5349 20:14:38.720800
5350 20:14:38.723593 [CATrainingPosCal] consider 1 rank data
5351 20:14:38.727351 u2DelayCellTimex100 = 270/100 ps
5352 20:14:38.729983 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5353 20:14:38.733260 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5354 20:14:38.737412 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5355 20:14:38.740187 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5356 20:14:38.742866 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5357 20:14:38.746779 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5358 20:14:38.749495
5359 20:14:38.752999 CA PerBit enable=1, Macro0, CA PI delay=32
5360 20:14:38.753466
5361 20:14:38.756120 [CBTSetCACLKResult] CA Dly = 32
5362 20:14:38.756584 CS Dly: 5 (0~36)
5363 20:14:38.756981 ==
5364 20:14:38.759436 Dram Type= 6, Freq= 0, CH_1, rank 1
5365 20:14:38.762544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5366 20:14:38.763011 ==
5367 20:14:38.769054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5368 20:14:38.775942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5369 20:14:38.779327 [CA 0] Center 37 (7~68) winsize 62
5370 20:14:38.782754 [CA 1] Center 37 (6~68) winsize 63
5371 20:14:38.786964 [CA 2] Center 34 (4~65) winsize 62
5372 20:14:38.789167 [CA 3] Center 34 (4~64) winsize 61
5373 20:14:38.792759 [CA 4] Center 33 (3~63) winsize 61
5374 20:14:38.796179 [CA 5] Center 33 (3~63) winsize 61
5375 20:14:38.796571
5376 20:14:38.799460 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5377 20:14:38.799848
5378 20:14:38.802016 [CATrainingPosCal] consider 2 rank data
5379 20:14:38.805376 u2DelayCellTimex100 = 270/100 ps
5380 20:14:38.809239 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5381 20:14:38.812415 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5382 20:14:38.815357 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5383 20:14:38.821782 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5384 20:14:38.825119 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5385 20:14:38.829175 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5386 20:14:38.829747
5387 20:14:38.832694 CA PerBit enable=1, Macro0, CA PI delay=33
5388 20:14:38.833280
5389 20:14:38.835624 [CBTSetCACLKResult] CA Dly = 33
5390 20:14:38.836183 CS Dly: 5 (0~37)
5391 20:14:38.836550
5392 20:14:38.840501 ----->DramcWriteLeveling(PI) begin...
5393 20:14:38.841124 ==
5394 20:14:38.841857 Dram Type= 6, Freq= 0, CH_1, rank 0
5395 20:14:38.848899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5396 20:14:38.849461 ==
5397 20:14:38.851936 Write leveling (Byte 0): 23 => 23
5398 20:14:38.855368 Write leveling (Byte 1): 23 => 23
5399 20:14:38.855835 DramcWriteLeveling(PI) end<-----
5400 20:14:38.858654
5401 20:14:38.859114 ==
5402 20:14:38.862141 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 20:14:38.865728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 20:14:38.866291 ==
5405 20:14:38.869273 [Gating] SW mode calibration
5406 20:14:38.875053 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5407 20:14:38.878599 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5408 20:14:38.885119 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 20:14:38.888127 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 20:14:38.891463 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 20:14:38.897911 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 20:14:38.901441 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5413 20:14:38.905071 0 10 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
5414 20:14:38.911540 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5415 20:14:38.914642 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 20:14:38.917968 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 20:14:38.928690 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 20:14:38.929272 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 20:14:38.931498 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 20:14:38.937923 0 11 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5421 20:14:38.941302 0 11 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
5422 20:14:38.944570 0 11 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5423 20:14:38.951905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 20:14:38.955750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 20:14:38.957837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 20:14:38.964918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 20:14:38.967426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 20:14:38.971752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5429 20:14:38.977306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 20:14:38.980816 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 20:14:38.984266 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 20:14:38.990824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 20:14:38.995413 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 20:14:38.997288 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 20:14:39.004242 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 20:14:39.007463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 20:14:39.011275 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 20:14:39.017428 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 20:14:39.020407 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 20:14:39.023661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 20:14:39.030117 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 20:14:39.034584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 20:14:39.037022 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 20:14:39.044418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 20:14:39.046918 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5446 20:14:39.050388 Total UI for P1: 0, mck2ui 16
5447 20:14:39.053301 best dqsien dly found for B0: ( 0, 14, 18)
5448 20:14:39.058192 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5449 20:14:39.060797 Total UI for P1: 0, mck2ui 16
5450 20:14:39.064176 best dqsien dly found for B1: ( 0, 14, 20)
5451 20:14:39.067862 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5452 20:14:39.069815 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5453 20:14:39.073426
5454 20:14:39.076864 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5455 20:14:39.080587 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5456 20:14:39.083578 [Gating] SW calibration Done
5457 20:14:39.084138 ==
5458 20:14:39.087382 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 20:14:39.090042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5460 20:14:39.090531 ==
5461 20:14:39.090944 RX Vref Scan: 0
5462 20:14:39.091295
5463 20:14:39.094109 RX Vref 0 -> 0, step: 1
5464 20:14:39.094709
5465 20:14:39.097130 RX Delay -80 -> 252, step: 8
5466 20:14:39.099662 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5467 20:14:39.102762 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5468 20:14:39.110152 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5469 20:14:39.112848 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 20:14:39.116193 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5471 20:14:39.119625 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5472 20:14:39.123651 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5473 20:14:39.126215 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5474 20:14:39.133246 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5475 20:14:39.136655 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5476 20:14:39.139364 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5477 20:14:39.142874 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5478 20:14:39.149175 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5479 20:14:39.152485 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5480 20:14:39.155878 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5481 20:14:39.159470 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5482 20:14:39.159958 ==
5483 20:14:39.162629 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 20:14:39.165687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 20:14:39.169212 ==
5486 20:14:39.169691 DQS Delay:
5487 20:14:39.170177 DQS0 = 0, DQS1 = 0
5488 20:14:39.173458 DQM Delay:
5489 20:14:39.173936 DQM0 = 95, DQM1 = 86
5490 20:14:39.175277 DQ Delay:
5491 20:14:39.175759 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5492 20:14:39.178826 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5493 20:14:39.182430 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5494 20:14:39.185811 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =91
5495 20:14:39.189321
5496 20:14:39.190055
5497 20:14:39.190541 ==
5498 20:14:39.192618 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 20:14:39.196195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 20:14:39.196821 ==
5501 20:14:39.197313
5502 20:14:39.197768
5503 20:14:39.198680 TX Vref Scan disable
5504 20:14:39.199102 == TX Byte 0 ==
5505 20:14:39.205232 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5506 20:14:39.208590 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5507 20:14:39.209101 == TX Byte 1 ==
5508 20:14:39.215009 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5509 20:14:39.218836 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5510 20:14:39.219406 ==
5511 20:14:39.221834 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 20:14:39.224996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5513 20:14:39.225471 ==
5514 20:14:39.225842
5515 20:14:39.226184
5516 20:14:39.228865 TX Vref Scan disable
5517 20:14:39.232184 == TX Byte 0 ==
5518 20:14:39.234976 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5519 20:14:39.238664 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5520 20:14:39.241728 == TX Byte 1 ==
5521 20:14:39.245531 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5522 20:14:39.248656 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5523 20:14:39.249247
5524 20:14:39.251222 [DATLAT]
5525 20:14:39.251690 Freq=933, CH1 RK0
5526 20:14:39.252064
5527 20:14:39.254984 DATLAT Default: 0xd
5528 20:14:39.255455 0, 0xFFFF, sum = 0
5529 20:14:39.257875 1, 0xFFFF, sum = 0
5530 20:14:39.258348 2, 0xFFFF, sum = 0
5531 20:14:39.261513 3, 0xFFFF, sum = 0
5532 20:14:39.261990 4, 0xFFFF, sum = 0
5533 20:14:39.265074 5, 0xFFFF, sum = 0
5534 20:14:39.265651 6, 0xFFFF, sum = 0
5535 20:14:39.268055 7, 0xFFFF, sum = 0
5536 20:14:39.268531 8, 0xFFFF, sum = 0
5537 20:14:39.271825 9, 0xFFFF, sum = 0
5538 20:14:39.272408 10, 0x0, sum = 1
5539 20:14:39.275014 11, 0x0, sum = 2
5540 20:14:39.275493 12, 0x0, sum = 3
5541 20:14:39.278153 13, 0x0, sum = 4
5542 20:14:39.278723 best_step = 11
5543 20:14:39.279094
5544 20:14:39.279583 ==
5545 20:14:39.282875 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 20:14:39.289433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 20:14:39.290066 ==
5548 20:14:39.290445 RX Vref Scan: 1
5549 20:14:39.290861
5550 20:14:39.291566 RX Vref 0 -> 0, step: 1
5551 20:14:39.291947
5552 20:14:39.294531 RX Delay -69 -> 252, step: 4
5553 20:14:39.295096
5554 20:14:39.297858 Set Vref, RX VrefLevel [Byte0]: 55
5555 20:14:39.301292 [Byte1]: 49
5556 20:14:39.301865
5557 20:14:39.304680 Final RX Vref Byte 0 = 55 to rank0
5558 20:14:39.308275 Final RX Vref Byte 1 = 49 to rank0
5559 20:14:39.311276 Final RX Vref Byte 0 = 55 to rank1
5560 20:14:39.315363 Final RX Vref Byte 1 = 49 to rank1==
5561 20:14:39.317643 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 20:14:39.321405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5563 20:14:39.323969 ==
5564 20:14:39.324439 DQS Delay:
5565 20:14:39.324852 DQS0 = 0, DQS1 = 0
5566 20:14:39.327838 DQM Delay:
5567 20:14:39.328397 DQM0 = 93, DQM1 = 87
5568 20:14:39.330975 DQ Delay:
5569 20:14:39.331539 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5570 20:14:39.334247 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =90
5571 20:14:39.337430 DQ8 =70, DQ9 =78, DQ10 =90, DQ11 =80
5572 20:14:39.341019 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5573 20:14:39.344266
5574 20:14:39.344912
5575 20:14:39.350872 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5576 20:14:39.354839 CH1 RK0: MR19=505, MR18=3333
5577 20:14:39.360272 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5578 20:14:39.360873
5579 20:14:39.363700 ----->DramcWriteLeveling(PI) begin...
5580 20:14:39.364271 ==
5581 20:14:39.367609 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 20:14:39.370501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5583 20:14:39.371069 ==
5584 20:14:39.373687 Write leveling (Byte 0): 22 => 22
5585 20:14:39.376859 Write leveling (Byte 1): 24 => 24
5586 20:14:39.380027 DramcWriteLeveling(PI) end<-----
5587 20:14:39.380538
5588 20:14:39.380939 ==
5589 20:14:39.385078 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 20:14:39.386936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 20:14:39.387410 ==
5592 20:14:39.390635 [Gating] SW mode calibration
5593 20:14:39.396816 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 20:14:39.403678 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5595 20:14:39.406694 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 20:14:39.413661 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 20:14:39.416079 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 20:14:39.419525 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5599 20:14:39.426338 0 10 16 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
5600 20:14:39.430370 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5601 20:14:39.433451 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 20:14:39.439879 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 20:14:39.442787 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 20:14:39.446096 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 20:14:39.452966 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 20:14:39.456972 0 11 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5607 20:14:39.459749 0 11 16 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
5608 20:14:39.467144 0 11 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5609 20:14:39.469680 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 20:14:39.473070 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 20:14:39.479700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 20:14:39.482938 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 20:14:39.486012 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 20:14:39.492423 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 20:14:39.495824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5616 20:14:39.499136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5617 20:14:39.505648 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 20:14:39.509853 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 20:14:39.512462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 20:14:39.515721 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 20:14:39.522310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 20:14:39.525664 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 20:14:39.528754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 20:14:39.536036 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 20:14:39.538590 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 20:14:39.542036 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 20:14:39.548699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 20:14:39.551972 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 20:14:39.555044 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 20:14:39.562054 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5631 20:14:39.565479 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5632 20:14:39.568285 Total UI for P1: 0, mck2ui 16
5633 20:14:39.572206 best dqsien dly found for B0: ( 0, 14, 12)
5634 20:14:39.574990 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5635 20:14:39.581756 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 20:14:39.585605 Total UI for P1: 0, mck2ui 16
5637 20:14:39.588167 best dqsien dly found for B1: ( 0, 14, 18)
5638 20:14:39.592098 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
5639 20:14:39.595746 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5640 20:14:39.596328
5641 20:14:39.598105 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
5642 20:14:39.601493 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5643 20:14:39.605634 [Gating] SW calibration Done
5644 20:14:39.606176 ==
5645 20:14:39.607835 Dram Type= 6, Freq= 0, CH_1, rank 1
5646 20:14:39.611836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5647 20:14:39.612310 ==
5648 20:14:39.615262 RX Vref Scan: 0
5649 20:14:39.615732
5650 20:14:39.617693 RX Vref 0 -> 0, step: 1
5651 20:14:39.618163
5652 20:14:39.618535 RX Delay -80 -> 252, step: 8
5653 20:14:39.625099 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5654 20:14:39.628737 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5655 20:14:39.631942 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5656 20:14:39.635324 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5657 20:14:39.637849 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5658 20:14:39.644743 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5659 20:14:39.648042 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5660 20:14:39.651241 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 20:14:39.653952 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5662 20:14:39.657585 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5663 20:14:39.664036 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5664 20:14:39.667440 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5665 20:14:39.670541 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5666 20:14:39.674590 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5667 20:14:39.678246 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5668 20:14:39.684742 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5669 20:14:39.685364 ==
5670 20:14:39.687406 Dram Type= 6, Freq= 0, CH_1, rank 1
5671 20:14:39.691081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5672 20:14:39.691645 ==
5673 20:14:39.692014 DQS Delay:
5674 20:14:39.694240 DQS0 = 0, DQS1 = 0
5675 20:14:39.694705 DQM Delay:
5676 20:14:39.697702 DQM0 = 98, DQM1 = 87
5677 20:14:39.698169 DQ Delay:
5678 20:14:39.700388 DQ0 =107, DQ1 =91, DQ2 =87, DQ3 =95
5679 20:14:39.703867 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =91
5680 20:14:39.707153 DQ8 =71, DQ9 =75, DQ10 =83, DQ11 =79
5681 20:14:39.710731 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5682 20:14:39.711199
5683 20:14:39.711563
5684 20:14:39.711902 ==
5685 20:14:39.714207 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 20:14:39.717394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 20:14:39.717865 ==
5688 20:14:39.718233
5689 20:14:39.720414
5690 20:14:39.721020 TX Vref Scan disable
5691 20:14:39.723583 == TX Byte 0 ==
5692 20:14:39.727586 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5693 20:14:39.730590 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5694 20:14:39.734558 == TX Byte 1 ==
5695 20:14:39.737457 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5696 20:14:39.740238 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5697 20:14:39.740850 ==
5698 20:14:39.743922 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 20:14:39.750116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 20:14:39.750699 ==
5701 20:14:39.751191
5702 20:14:39.751646
5703 20:14:39.752091 TX Vref Scan disable
5704 20:14:39.754735 == TX Byte 0 ==
5705 20:14:39.757694 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5706 20:14:39.764851 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5707 20:14:39.765419 == TX Byte 1 ==
5708 20:14:39.767775 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5709 20:14:39.774177 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5710 20:14:39.774781
5711 20:14:39.775278 [DATLAT]
5712 20:14:39.775741 Freq=933, CH1 RK1
5713 20:14:39.776196
5714 20:14:39.777613 DATLAT Default: 0xb
5715 20:14:39.778090 0, 0xFFFF, sum = 0
5716 20:14:39.780928 1, 0xFFFF, sum = 0
5717 20:14:39.784559 2, 0xFFFF, sum = 0
5718 20:14:39.785176 3, 0xFFFF, sum = 0
5719 20:14:39.787846 4, 0xFFFF, sum = 0
5720 20:14:39.788435 5, 0xFFFF, sum = 0
5721 20:14:39.791501 6, 0xFFFF, sum = 0
5722 20:14:39.792089 7, 0xFFFF, sum = 0
5723 20:14:39.794253 8, 0xFFFF, sum = 0
5724 20:14:39.795008 9, 0xFFFF, sum = 0
5725 20:14:39.797285 10, 0x0, sum = 1
5726 20:14:39.797756 11, 0x0, sum = 2
5727 20:14:39.800895 12, 0x0, sum = 3
5728 20:14:39.801368 13, 0x0, sum = 4
5729 20:14:39.801758 best_step = 11
5730 20:14:39.804008
5731 20:14:39.804567 ==
5732 20:14:39.807906 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 20:14:39.810492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5734 20:14:39.810960 ==
5735 20:14:39.811329 RX Vref Scan: 0
5736 20:14:39.811673
5737 20:14:39.814883 RX Vref 0 -> 0, step: 1
5738 20:14:39.815347
5739 20:14:39.817171 RX Delay -77 -> 252, step: 4
5740 20:14:39.823913 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5741 20:14:39.827232 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5742 20:14:39.830469 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5743 20:14:39.834074 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5744 20:14:39.837211 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5745 20:14:39.840432 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5746 20:14:39.847051 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5747 20:14:39.850604 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5748 20:14:39.853390 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5749 20:14:39.857495 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5750 20:14:39.860887 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5751 20:14:39.866776 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5752 20:14:39.870085 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5753 20:14:39.873487 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5754 20:14:39.876553 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5755 20:14:39.880804 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5756 20:14:39.881386 ==
5757 20:14:39.882984 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 20:14:39.890076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5759 20:14:39.890660 ==
5760 20:14:39.891153 DQS Delay:
5761 20:14:39.892844 DQS0 = 0, DQS1 = 0
5762 20:14:39.893324 DQM Delay:
5763 20:14:39.893807 DQM0 = 96, DQM1 = 87
5764 20:14:39.896145 DQ Delay:
5765 20:14:39.899761 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5766 20:14:39.903776 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =96
5767 20:14:39.907181 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5768 20:14:39.909267 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5769 20:14:39.909735
5770 20:14:39.910100
5771 20:14:39.915872 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5772 20:14:39.920094 CH1 RK1: MR19=505, MR18=2626
5773 20:14:39.926546 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5774 20:14:39.930001 [RxdqsGatingPostProcess] freq 933
5775 20:14:39.936877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5776 20:14:39.937450 Pre-setting of DQS Precalculation
5777 20:14:39.943878 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5778 20:14:39.949569 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5779 20:14:39.956054 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5780 20:14:39.956605
5781 20:14:39.957040
5782 20:14:39.959346 [Calibration Summary] 1866 Mbps
5783 20:14:39.963188 CH 0, Rank 0
5784 20:14:39.963766 SW Impedance : PASS
5785 20:14:39.966142 DUTY Scan : NO K
5786 20:14:39.968922 ZQ Calibration : PASS
5787 20:14:39.969407 Jitter Meter : NO K
5788 20:14:39.972634 CBT Training : PASS
5789 20:14:39.976422 Write leveling : PASS
5790 20:14:39.977051 RX DQS gating : PASS
5791 20:14:39.978906 RX DQ/DQS(RDDQC) : PASS
5792 20:14:39.982739 TX DQ/DQS : PASS
5793 20:14:39.983174 RX DATLAT : PASS
5794 20:14:39.985447 RX DQ/DQS(Engine): PASS
5795 20:14:39.989121 TX OE : NO K
5796 20:14:39.989683 All Pass.
5797 20:14:39.990058
5798 20:14:39.990402 CH 0, Rank 1
5799 20:14:39.991871 SW Impedance : PASS
5800 20:14:39.995889 DUTY Scan : NO K
5801 20:14:39.996467 ZQ Calibration : PASS
5802 20:14:39.998739 Jitter Meter : NO K
5803 20:14:39.999296 CBT Training : PASS
5804 20:14:40.001726 Write leveling : PASS
5805 20:14:40.005272 RX DQS gating : PASS
5806 20:14:40.005825 RX DQ/DQS(RDDQC) : PASS
5807 20:14:40.008836 TX DQ/DQS : PASS
5808 20:14:40.012558 RX DATLAT : PASS
5809 20:14:40.013086 RX DQ/DQS(Engine): PASS
5810 20:14:40.015181 TX OE : NO K
5811 20:14:40.015659 All Pass.
5812 20:14:40.016141
5813 20:14:40.018393 CH 1, Rank 0
5814 20:14:40.018968 SW Impedance : PASS
5815 20:14:40.021449 DUTY Scan : NO K
5816 20:14:40.024511 ZQ Calibration : PASS
5817 20:14:40.025208 Jitter Meter : NO K
5818 20:14:40.028060 CBT Training : PASS
5819 20:14:40.031918 Write leveling : PASS
5820 20:14:40.032496 RX DQS gating : PASS
5821 20:14:40.035635 RX DQ/DQS(RDDQC) : PASS
5822 20:14:40.037997 TX DQ/DQS : PASS
5823 20:14:40.038505 RX DATLAT : PASS
5824 20:14:40.041562 RX DQ/DQS(Engine): PASS
5825 20:14:40.045126 TX OE : NO K
5826 20:14:40.045698 All Pass.
5827 20:14:40.046068
5828 20:14:40.046409 CH 1, Rank 1
5829 20:14:40.047891 SW Impedance : PASS
5830 20:14:40.052327 DUTY Scan : NO K
5831 20:14:40.052928 ZQ Calibration : PASS
5832 20:14:40.056413 Jitter Meter : NO K
5833 20:14:40.058097 CBT Training : PASS
5834 20:14:40.058564 Write leveling : PASS
5835 20:14:40.061332 RX DQS gating : PASS
5836 20:14:40.064393 RX DQ/DQS(RDDQC) : PASS
5837 20:14:40.064903 TX DQ/DQS : PASS
5838 20:14:40.067551 RX DATLAT : PASS
5839 20:14:40.068016 RX DQ/DQS(Engine): PASS
5840 20:14:40.070768 TX OE : NO K
5841 20:14:40.071252 All Pass.
5842 20:14:40.071618
5843 20:14:40.074998 DramC Write-DBI off
5844 20:14:40.078085 PER_BANK_REFRESH: Hybrid Mode
5845 20:14:40.078555 TX_TRACKING: ON
5846 20:14:40.087830 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5847 20:14:40.091141 [FAST_K] Save calibration result to emmc
5848 20:14:40.094373 dramc_set_vcore_voltage set vcore to 650000
5849 20:14:40.097720 Read voltage for 400, 6
5850 20:14:40.098284 Vio18 = 0
5851 20:14:40.101542 Vcore = 650000
5852 20:14:40.102102 Vdram = 0
5853 20:14:40.102471 Vddq = 0
5854 20:14:40.102809 Vmddr = 0
5855 20:14:40.107627 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5856 20:14:40.115287 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5857 20:14:40.115851 MEM_TYPE=3, freq_sel=20
5858 20:14:40.117180 sv_algorithm_assistance_LP4_800
5859 20:14:40.120585 ============ PULL DRAM RESETB DOWN ============
5860 20:14:40.127534 ========== PULL DRAM RESETB DOWN end =========
5861 20:14:40.131126 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5862 20:14:40.134240 ===================================
5863 20:14:40.137825 LPDDR4 DRAM CONFIGURATION
5864 20:14:40.140160 ===================================
5865 20:14:40.140637 EX_ROW_EN[0] = 0x0
5866 20:14:40.143856 EX_ROW_EN[1] = 0x0
5867 20:14:40.144317 LP4Y_EN = 0x0
5868 20:14:40.147315 WORK_FSP = 0x0
5869 20:14:40.150945 WL = 0x2
5870 20:14:40.151508 RL = 0x2
5871 20:14:40.153797 BL = 0x2
5872 20:14:40.154258 RPST = 0x0
5873 20:14:40.156874 RD_PRE = 0x0
5874 20:14:40.157336 WR_PRE = 0x1
5875 20:14:40.160979 WR_PST = 0x0
5876 20:14:40.161541 DBI_WR = 0x0
5877 20:14:40.163385 DBI_RD = 0x0
5878 20:14:40.163843 OTF = 0x1
5879 20:14:40.167333 ===================================
5880 20:14:40.170900 ===================================
5881 20:14:40.174503 ANA top config
5882 20:14:40.177047 ===================================
5883 20:14:40.177537 DLL_ASYNC_EN = 0
5884 20:14:40.180495 ALL_SLAVE_EN = 1
5885 20:14:40.183587 NEW_RANK_MODE = 1
5886 20:14:40.186910 DLL_IDLE_MODE = 1
5887 20:14:40.187371 LP45_APHY_COMB_EN = 1
5888 20:14:40.190059 TX_ODT_DIS = 1
5889 20:14:40.194050 NEW_8X_MODE = 1
5890 20:14:40.197104 ===================================
5891 20:14:40.200217 ===================================
5892 20:14:40.203278 data_rate = 800
5893 20:14:40.206906 CKR = 1
5894 20:14:40.210598 DQ_P2S_RATIO = 4
5895 20:14:40.213029 ===================================
5896 20:14:40.213493 CA_P2S_RATIO = 4
5897 20:14:40.217021 DQ_CA_OPEN = 0
5898 20:14:40.220666 DQ_SEMI_OPEN = 1
5899 20:14:40.223634 CA_SEMI_OPEN = 1
5900 20:14:40.226148 CA_FULL_RATE = 0
5901 20:14:40.229415 DQ_CKDIV4_EN = 0
5902 20:14:40.233148 CA_CKDIV4_EN = 1
5903 20:14:40.233716 CA_PREDIV_EN = 0
5904 20:14:40.236394 PH8_DLY = 0
5905 20:14:40.240446 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5906 20:14:40.243053 DQ_AAMCK_DIV = 0
5907 20:14:40.247013 CA_AAMCK_DIV = 0
5908 20:14:40.247574 CA_ADMCK_DIV = 4
5909 20:14:40.249303 DQ_TRACK_CA_EN = 0
5910 20:14:40.253444 CA_PICK = 800
5911 20:14:40.256911 CA_MCKIO = 400
5912 20:14:40.259627 MCKIO_SEMI = 400
5913 20:14:40.263494 PLL_FREQ = 3016
5914 20:14:40.267376 DQ_UI_PI_RATIO = 32
5915 20:14:40.269416 CA_UI_PI_RATIO = 32
5916 20:14:40.273322 ===================================
5917 20:14:40.276101 ===================================
5918 20:14:40.276580 memory_type:LPDDR4
5919 20:14:40.279210 GP_NUM : 10
5920 20:14:40.282237 SRAM_EN : 1
5921 20:14:40.282702 MD32_EN : 0
5922 20:14:40.285932 ===================================
5923 20:14:40.289335 [ANA_INIT] >>>>>>>>>>>>>>
5924 20:14:40.293205 <<<<<< [CONFIGURE PHASE]: ANA_TX
5925 20:14:40.295742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5926 20:14:40.299093 ===================================
5927 20:14:40.302622 data_rate = 800,PCW = 0X7400
5928 20:14:40.305690 ===================================
5929 20:14:40.309177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5930 20:14:40.312181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5931 20:14:40.325440 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5932 20:14:40.328857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5933 20:14:40.332567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5934 20:14:40.335955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5935 20:14:40.338474 [ANA_INIT] flow start
5936 20:14:40.342288 [ANA_INIT] PLL >>>>>>>>
5937 20:14:40.342748 [ANA_INIT] PLL <<<<<<<<
5938 20:14:40.345003 [ANA_INIT] MIDPI >>>>>>>>
5939 20:14:40.349169 [ANA_INIT] MIDPI <<<<<<<<
5940 20:14:40.349732 [ANA_INIT] DLL >>>>>>>>
5941 20:14:40.352205 [ANA_INIT] flow end
5942 20:14:40.356344 ============ LP4 DIFF to SE enter ============
5943 20:14:40.358433 ============ LP4 DIFF to SE exit ============
5944 20:14:40.361784 [ANA_INIT] <<<<<<<<<<<<<
5945 20:14:40.365315 [Flow] Enable top DCM control >>>>>
5946 20:14:40.369697 [Flow] Enable top DCM control <<<<<
5947 20:14:40.372045 Enable DLL master slave shuffle
5948 20:14:40.379045 ==============================================================
5949 20:14:40.379599 Gating Mode config
5950 20:14:40.385271 ==============================================================
5951 20:14:40.385754 Config description:
5952 20:14:40.395350 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5953 20:14:40.401408 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5954 20:14:40.408086 SELPH_MODE 0: By rank 1: By Phase
5955 20:14:40.414438 ==============================================================
5956 20:14:40.414910 GAT_TRACK_EN = 0
5957 20:14:40.419150 RX_GATING_MODE = 2
5958 20:14:40.421498 RX_GATING_TRACK_MODE = 2
5959 20:14:40.426053 SELPH_MODE = 1
5960 20:14:40.428431 PICG_EARLY_EN = 1
5961 20:14:40.431392 VALID_LAT_VALUE = 1
5962 20:14:40.438132 ==============================================================
5963 20:14:40.441269 Enter into Gating configuration >>>>
5964 20:14:40.444512 Exit from Gating configuration <<<<
5965 20:14:40.447629 Enter into DVFS_PRE_config >>>>>
5966 20:14:40.457665 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5967 20:14:40.460630 Exit from DVFS_PRE_config <<<<<
5968 20:14:40.464487 Enter into PICG configuration >>>>
5969 20:14:40.468079 Exit from PICG configuration <<<<
5970 20:14:40.470900 [RX_INPUT] configuration >>>>>
5971 20:14:40.475074 [RX_INPUT] configuration <<<<<
5972 20:14:40.477493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5973 20:14:40.484221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5974 20:14:40.491220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5975 20:14:40.497231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5976 20:14:40.500241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5977 20:14:40.507437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5978 20:14:40.510467 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5979 20:14:40.517382 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5980 20:14:40.520644 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5981 20:14:40.523449 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5982 20:14:40.527978 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5983 20:14:40.533372 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5984 20:14:40.536660 ===================================
5985 20:14:40.537171 LPDDR4 DRAM CONFIGURATION
5986 20:14:40.540647 ===================================
5987 20:14:40.543319 EX_ROW_EN[0] = 0x0
5988 20:14:40.547578 EX_ROW_EN[1] = 0x0
5989 20:14:40.548138 LP4Y_EN = 0x0
5990 20:14:40.551107 WORK_FSP = 0x0
5991 20:14:40.551667 WL = 0x2
5992 20:14:40.553442 RL = 0x2
5993 20:14:40.553903 BL = 0x2
5994 20:14:40.556883 RPST = 0x0
5995 20:14:40.557455 RD_PRE = 0x0
5996 20:14:40.560883 WR_PRE = 0x1
5997 20:14:40.561446 WR_PST = 0x0
5998 20:14:40.562859 DBI_WR = 0x0
5999 20:14:40.563320 DBI_RD = 0x0
6000 20:14:40.566908 OTF = 0x1
6001 20:14:40.569544 ===================================
6002 20:14:40.573121 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6003 20:14:40.576458 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6004 20:14:40.583111 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 20:14:40.586346 ===================================
6006 20:14:40.586819 LPDDR4 DRAM CONFIGURATION
6007 20:14:40.590009 ===================================
6008 20:14:40.594444 EX_ROW_EN[0] = 0x10
6009 20:14:40.595987 EX_ROW_EN[1] = 0x0
6010 20:14:40.596455 LP4Y_EN = 0x0
6011 20:14:40.599840 WORK_FSP = 0x0
6012 20:14:40.600401 WL = 0x2
6013 20:14:40.603305 RL = 0x2
6014 20:14:40.603877 BL = 0x2
6015 20:14:40.606341 RPST = 0x0
6016 20:14:40.606905 RD_PRE = 0x0
6017 20:14:40.609288 WR_PRE = 0x1
6018 20:14:40.609757 WR_PST = 0x0
6019 20:14:40.612581 DBI_WR = 0x0
6020 20:14:40.613164 DBI_RD = 0x0
6021 20:14:40.616568 OTF = 0x1
6022 20:14:40.619390 ===================================
6023 20:14:40.626039 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6024 20:14:40.630103 nWR fixed to 30
6025 20:14:40.633332 [ModeRegInit_LP4] CH0 RK0
6026 20:14:40.633860 [ModeRegInit_LP4] CH0 RK1
6027 20:14:40.636266 [ModeRegInit_LP4] CH1 RK0
6028 20:14:40.640388 [ModeRegInit_LP4] CH1 RK1
6029 20:14:40.641022 match AC timing 18
6030 20:14:40.645547 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6031 20:14:40.649685 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6032 20:14:40.653069 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6033 20:14:40.659428 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6034 20:14:40.662122 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6035 20:14:40.662584 ==
6036 20:14:40.665466 Dram Type= 6, Freq= 0, CH_0, rank 0
6037 20:14:40.669505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6038 20:14:40.670069 ==
6039 20:14:40.675776 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6040 20:14:40.683007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6041 20:14:40.686081 [CA 0] Center 36 (8~64) winsize 57
6042 20:14:40.689018 [CA 1] Center 36 (8~64) winsize 57
6043 20:14:40.692437 [CA 2] Center 36 (8~64) winsize 57
6044 20:14:40.695486 [CA 3] Center 36 (8~64) winsize 57
6045 20:14:40.696095 [CA 4] Center 36 (8~64) winsize 57
6046 20:14:40.698936 [CA 5] Center 36 (8~64) winsize 57
6047 20:14:40.699494
6048 20:14:40.705350 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6049 20:14:40.705811
6050 20:14:40.710200 [CATrainingPosCal] consider 1 rank data
6051 20:14:40.712478 u2DelayCellTimex100 = 270/100 ps
6052 20:14:40.715537 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 20:14:40.718996 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 20:14:40.721618 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 20:14:40.725497 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 20:14:40.728331 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 20:14:40.731796 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 20:14:40.732384
6059 20:14:40.735154 CA PerBit enable=1, Macro0, CA PI delay=36
6060 20:14:40.735574
6061 20:14:40.738371 [CBTSetCACLKResult] CA Dly = 36
6062 20:14:40.742368 CS Dly: 1 (0~32)
6063 20:14:40.742885 ==
6064 20:14:40.745781 Dram Type= 6, Freq= 0, CH_0, rank 1
6065 20:14:40.748666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6066 20:14:40.749145 ==
6067 20:14:40.755986 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6068 20:14:40.761419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6069 20:14:40.761839 [CA 0] Center 36 (8~64) winsize 57
6070 20:14:40.765764 [CA 1] Center 36 (8~64) winsize 57
6071 20:14:40.768656 [CA 2] Center 36 (8~64) winsize 57
6072 20:14:40.771894 [CA 3] Center 36 (8~64) winsize 57
6073 20:14:40.774767 [CA 4] Center 36 (8~64) winsize 57
6074 20:14:40.778643 [CA 5] Center 36 (8~64) winsize 57
6075 20:14:40.779161
6076 20:14:40.781445 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6077 20:14:40.781862
6078 20:14:40.784630 [CATrainingPosCal] consider 2 rank data
6079 20:14:40.788301 u2DelayCellTimex100 = 270/100 ps
6080 20:14:40.791511 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 20:14:40.798472 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 20:14:40.801651 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 20:14:40.804887 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 20:14:40.808483 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 20:14:40.811848 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 20:14:40.812339
6087 20:14:40.814634 CA PerBit enable=1, Macro0, CA PI delay=36
6088 20:14:40.815104
6089 20:14:40.818048 [CBTSetCACLKResult] CA Dly = 36
6090 20:14:40.818557 CS Dly: 1 (0~32)
6091 20:14:40.821171
6092 20:14:40.824627 ----->DramcWriteLeveling(PI) begin...
6093 20:14:40.825092 ==
6094 20:14:40.828300 Dram Type= 6, Freq= 0, CH_0, rank 0
6095 20:14:40.831653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6096 20:14:40.832078 ==
6097 20:14:40.834312 Write leveling (Byte 0): 32 => 0
6098 20:14:40.838068 Write leveling (Byte 1): 32 => 0
6099 20:14:40.840844 DramcWriteLeveling(PI) end<-----
6100 20:14:40.841270
6101 20:14:40.841605 ==
6102 20:14:40.844515 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 20:14:40.847776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 20:14:40.848343 ==
6105 20:14:40.851434 [Gating] SW mode calibration
6106 20:14:40.858367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6107 20:14:40.864885 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6108 20:14:40.867879 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6109 20:14:40.871277 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6110 20:14:40.877660 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6111 20:14:40.881412 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6112 20:14:40.884321 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6113 20:14:40.888080 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6114 20:14:40.894634 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6115 20:14:40.898242 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6116 20:14:40.901476 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6117 20:14:40.903957 Total UI for P1: 0, mck2ui 16
6118 20:14:40.908891 best dqsien dly found for B0: ( 0, 10, 16)
6119 20:14:40.910804 Total UI for P1: 0, mck2ui 16
6120 20:14:40.913985 best dqsien dly found for B1: ( 0, 10, 16)
6121 20:14:40.920299 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6122 20:14:40.924016 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6123 20:14:40.924582
6124 20:14:40.927716 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6125 20:14:40.930580 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6126 20:14:40.933750 [Gating] SW calibration Done
6127 20:14:40.934261 ==
6128 20:14:40.937208 Dram Type= 6, Freq= 0, CH_0, rank 0
6129 20:14:40.940170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6130 20:14:40.940643 ==
6131 20:14:40.943657 RX Vref Scan: 0
6132 20:14:40.944214
6133 20:14:40.944582 RX Vref 0 -> 0, step: 1
6134 20:14:40.945005
6135 20:14:40.947609 RX Delay -410 -> 252, step: 16
6136 20:14:40.953521 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6137 20:14:40.956802 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6138 20:14:40.960134 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6139 20:14:40.963880 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6140 20:14:40.969898 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6141 20:14:40.973614 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6142 20:14:40.976859 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6143 20:14:40.980454 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6144 20:14:40.986626 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6145 20:14:40.989678 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6146 20:14:40.993174 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6147 20:14:40.996834 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6148 20:14:41.002783 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6149 20:14:41.006516 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6150 20:14:41.009620 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6151 20:14:41.016753 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6152 20:14:41.017322 ==
6153 20:14:41.019197 Dram Type= 6, Freq= 0, CH_0, rank 0
6154 20:14:41.024254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6155 20:14:41.024877 ==
6156 20:14:41.025261 DQS Delay:
6157 20:14:41.026084 DQS0 = 51, DQS1 = 59
6158 20:14:41.026491 DQM Delay:
6159 20:14:41.029411 DQM0 = 12, DQM1 = 15
6160 20:14:41.029868 DQ Delay:
6161 20:14:41.035205 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6162 20:14:41.036538 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6163 20:14:41.040110 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6164 20:14:41.043458 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6165 20:14:41.044020
6166 20:14:41.044382
6167 20:14:41.044755 ==
6168 20:14:41.045812 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 20:14:41.049378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 20:14:41.049851 ==
6171 20:14:41.050221
6172 20:14:41.050560
6173 20:14:41.052645 TX Vref Scan disable
6174 20:14:41.053453 == TX Byte 0 ==
6175 20:14:41.059308 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6176 20:14:41.062567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6177 20:14:41.063053 == TX Byte 1 ==
6178 20:14:41.069024 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6179 20:14:41.073590 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6180 20:14:41.074163 ==
6181 20:14:41.075421 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 20:14:41.078957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 20:14:41.079543 ==
6184 20:14:41.082623
6185 20:14:41.083196
6186 20:14:41.083683 TX Vref Scan disable
6187 20:14:41.085558 == TX Byte 0 ==
6188 20:14:41.089675 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 20:14:41.092628 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 20:14:41.095819 == TX Byte 1 ==
6191 20:14:41.098883 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 20:14:41.102658 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 20:14:41.103142
6194 20:14:41.105699 [DATLAT]
6195 20:14:41.106209 Freq=400, CH0 RK0
6196 20:14:41.106768
6197 20:14:41.108580 DATLAT Default: 0xf
6198 20:14:41.109099 0, 0xFFFF, sum = 0
6199 20:14:41.112495 1, 0xFFFF, sum = 0
6200 20:14:41.113112 2, 0xFFFF, sum = 0
6201 20:14:41.115497 3, 0xFFFF, sum = 0
6202 20:14:41.116160 4, 0xFFFF, sum = 0
6203 20:14:41.119041 5, 0xFFFF, sum = 0
6204 20:14:41.119530 6, 0xFFFF, sum = 0
6205 20:14:41.122119 7, 0xFFFF, sum = 0
6206 20:14:41.122684 8, 0xFFFF, sum = 0
6207 20:14:41.125302 9, 0xFFFF, sum = 0
6208 20:14:41.125774 10, 0xFFFF, sum = 0
6209 20:14:41.128897 11, 0xFFFF, sum = 0
6210 20:14:41.129387 12, 0x0, sum = 1
6211 20:14:41.131841 13, 0x0, sum = 2
6212 20:14:41.132268 14, 0x0, sum = 3
6213 20:14:41.135319 15, 0x0, sum = 4
6214 20:14:41.135846 best_step = 13
6215 20:14:41.136179
6216 20:14:41.136485 ==
6217 20:14:41.139173 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 20:14:41.145482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6219 20:14:41.146005 ==
6220 20:14:41.146343 RX Vref Scan: 1
6221 20:14:41.146655
6222 20:14:41.149996 RX Vref 0 -> 0, step: 1
6223 20:14:41.150513
6224 20:14:41.152839 RX Delay -359 -> 252, step: 8
6225 20:14:41.153370
6226 20:14:41.155461 Set Vref, RX VrefLevel [Byte0]: 53
6227 20:14:41.158237 [Byte1]: 50
6228 20:14:41.158767
6229 20:14:41.162002 Final RX Vref Byte 0 = 53 to rank0
6230 20:14:41.165266 Final RX Vref Byte 1 = 50 to rank0
6231 20:14:41.168412 Final RX Vref Byte 0 = 53 to rank1
6232 20:14:41.172302 Final RX Vref Byte 1 = 50 to rank1==
6233 20:14:41.175251 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 20:14:41.181785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 20:14:41.182308 ==
6236 20:14:41.182645 DQS Delay:
6237 20:14:41.184838 DQS0 = 56, DQS1 = 68
6238 20:14:41.185360 DQM Delay:
6239 20:14:41.185699 DQM0 = 12, DQM1 = 16
6240 20:14:41.189054 DQ Delay:
6241 20:14:41.191920 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =8
6242 20:14:41.192456 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6243 20:14:41.194877 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6244 20:14:41.198659 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6245 20:14:41.199179
6246 20:14:41.201418
6247 20:14:41.208787 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6248 20:14:41.212028 CH0 RK0: MR19=C0C, MR18=A9A9
6249 20:14:41.218003 CH0_RK0: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6250 20:14:41.218456 ==
6251 20:14:41.221299 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 20:14:41.225628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 20:14:41.226164 ==
6254 20:14:41.227998 [Gating] SW mode calibration
6255 20:14:41.234585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 20:14:41.241129 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6257 20:14:41.244093 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 20:14:41.248361 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 20:14:41.255713 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 20:14:41.257465 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6261 20:14:41.261112 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 20:14:41.268854 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 20:14:41.270935 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 20:14:41.274606 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6265 20:14:41.280307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 20:14:41.280921 Total UI for P1: 0, mck2ui 16
6267 20:14:41.286975 best dqsien dly found for B0: ( 0, 10, 16)
6268 20:14:41.287618 Total UI for P1: 0, mck2ui 16
6269 20:14:41.293562 best dqsien dly found for B1: ( 0, 10, 24)
6270 20:14:41.297542 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6271 20:14:41.300422 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6272 20:14:41.300901
6273 20:14:41.304494 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6274 20:14:41.306954 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6275 20:14:41.310619 [Gating] SW calibration Done
6276 20:14:41.311138 ==
6277 20:14:41.314265 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 20:14:41.316587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6279 20:14:41.317223 ==
6280 20:14:41.319780 RX Vref Scan: 0
6281 20:14:41.320197
6282 20:14:41.320525 RX Vref 0 -> 0, step: 1
6283 20:14:41.324322
6284 20:14:41.324915 RX Delay -410 -> 252, step: 16
6285 20:14:41.329946 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6286 20:14:41.333284 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6287 20:14:41.336888 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6288 20:14:41.340758 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6289 20:14:41.347050 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6290 20:14:41.350208 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6291 20:14:41.353696 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6292 20:14:41.356690 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6293 20:14:41.363173 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6294 20:14:41.367104 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6295 20:14:41.369813 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6296 20:14:41.373003 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6297 20:14:41.380233 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 20:14:41.383552 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6299 20:14:41.386216 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6300 20:14:41.393112 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 20:14:41.393651 ==
6302 20:14:41.396516 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 20:14:41.400026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6304 20:14:41.400552 ==
6305 20:14:41.400952 DQS Delay:
6306 20:14:41.402547 DQS0 = 43, DQS1 = 59
6307 20:14:41.402965 DQM Delay:
6308 20:14:41.406259 DQM0 = 6, DQM1 = 15
6309 20:14:41.406780 DQ Delay:
6310 20:14:41.409645 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6311 20:14:41.413000 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6312 20:14:41.416400 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6313 20:14:41.419742 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6314 20:14:41.420164
6315 20:14:41.420494
6316 20:14:41.420864 ==
6317 20:14:41.422347 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 20:14:41.425849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 20:14:41.426271 ==
6320 20:14:41.426605
6321 20:14:41.426911
6322 20:14:41.429688 TX Vref Scan disable
6323 20:14:41.430114 == TX Byte 0 ==
6324 20:14:41.436112 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6325 20:14:41.439387 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6326 20:14:41.439911 == TX Byte 1 ==
6327 20:14:41.446398 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6328 20:14:41.449441 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6329 20:14:41.449913 ==
6330 20:14:41.453272 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 20:14:41.455519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 20:14:41.455988 ==
6333 20:14:41.456358
6334 20:14:41.456696
6335 20:14:41.459152 TX Vref Scan disable
6336 20:14:41.463662 == TX Byte 0 ==
6337 20:14:41.466465 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6338 20:14:41.468927 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6339 20:14:41.469399 == TX Byte 1 ==
6340 20:14:41.476780 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6341 20:14:41.479159 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6342 20:14:41.479627
6343 20:14:41.479993 [DATLAT]
6344 20:14:41.482409 Freq=400, CH0 RK1
6345 20:14:41.482969
6346 20:14:41.483336 DATLAT Default: 0xd
6347 20:14:41.485744 0, 0xFFFF, sum = 0
6348 20:14:41.486216 1, 0xFFFF, sum = 0
6349 20:14:41.489047 2, 0xFFFF, sum = 0
6350 20:14:41.489620 3, 0xFFFF, sum = 0
6351 20:14:41.492016 4, 0xFFFF, sum = 0
6352 20:14:41.495405 5, 0xFFFF, sum = 0
6353 20:14:41.496009 6, 0xFFFF, sum = 0
6354 20:14:41.498888 7, 0xFFFF, sum = 0
6355 20:14:41.499449 8, 0xFFFF, sum = 0
6356 20:14:41.502193 9, 0xFFFF, sum = 0
6357 20:14:41.502666 10, 0xFFFF, sum = 0
6358 20:14:41.505813 11, 0xFFFF, sum = 0
6359 20:14:41.506391 12, 0x0, sum = 1
6360 20:14:41.508826 13, 0x0, sum = 2
6361 20:14:41.509298 14, 0x0, sum = 3
6362 20:14:41.511829 15, 0x0, sum = 4
6363 20:14:41.512148 best_step = 13
6364 20:14:41.512212
6365 20:14:41.512271 ==
6366 20:14:41.515318 Dram Type= 6, Freq= 0, CH_0, rank 1
6367 20:14:41.517983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6368 20:14:41.518068 ==
6369 20:14:41.521580 RX Vref Scan: 0
6370 20:14:41.521662
6371 20:14:41.524842 RX Vref 0 -> 0, step: 1
6372 20:14:41.524924
6373 20:14:41.524988 RX Delay -359 -> 252, step: 8
6374 20:14:41.533802 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6375 20:14:41.536721 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6376 20:14:41.540541 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6377 20:14:41.548429 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6378 20:14:41.550164 iDelay=217, Bit 4, Center -40 (-295 ~ 216) 512
6379 20:14:41.553165 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6380 20:14:41.557331 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6381 20:14:41.563502 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6382 20:14:41.567394 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6383 20:14:41.570342 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6384 20:14:41.573692 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6385 20:14:41.581069 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6386 20:14:41.583448 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6387 20:14:41.587145 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6388 20:14:41.590659 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6389 20:14:41.597381 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6390 20:14:41.597941 ==
6391 20:14:41.600175 Dram Type= 6, Freq= 0, CH_0, rank 1
6392 20:14:41.603307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6393 20:14:41.603867 ==
6394 20:14:41.604232 DQS Delay:
6395 20:14:41.607564 DQS0 = 52, DQS1 = 64
6396 20:14:41.608122 DQM Delay:
6397 20:14:41.609959 DQM0 = 9, DQM1 = 14
6398 20:14:41.610417 DQ Delay:
6399 20:14:41.613395 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6400 20:14:41.616379 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6401 20:14:41.619878 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6402 20:14:41.623354 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6403 20:14:41.623913
6404 20:14:41.624278
6405 20:14:41.629956 [DQSOSCAuto] RK1, (LSB)MR18= 0xb9b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6406 20:14:41.633451 CH0 RK1: MR19=C0C, MR18=B9B9
6407 20:14:41.640191 CH0_RK1: MR19=0xC0C, MR18=0xB9B9, DQSOSC=386, MR23=63, INC=396, DEC=264
6408 20:14:41.643669 [RxdqsGatingPostProcess] freq 400
6409 20:14:41.649493 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6410 20:14:41.652773 Pre-setting of DQS Precalculation
6411 20:14:41.656333 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6412 20:14:41.656927 ==
6413 20:14:41.660276 Dram Type= 6, Freq= 0, CH_1, rank 0
6414 20:14:41.663327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6415 20:14:41.666432 ==
6416 20:14:41.669700 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6417 20:14:41.675770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6418 20:14:41.679605 [CA 0] Center 36 (8~64) winsize 57
6419 20:14:41.682778 [CA 1] Center 36 (8~64) winsize 57
6420 20:14:41.686325 [CA 2] Center 36 (8~64) winsize 57
6421 20:14:41.688997 [CA 3] Center 36 (8~64) winsize 57
6422 20:14:41.692906 [CA 4] Center 36 (8~64) winsize 57
6423 20:14:41.695979 [CA 5] Center 36 (8~64) winsize 57
6424 20:14:41.696493
6425 20:14:41.699331 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6426 20:14:41.699857
6427 20:14:41.702559 [CATrainingPosCal] consider 1 rank data
6428 20:14:41.705703 u2DelayCellTimex100 = 270/100 ps
6429 20:14:41.709279 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 20:14:41.712634 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 20:14:41.716196 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 20:14:41.718830 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6433 20:14:41.722532 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 20:14:41.725561 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 20:14:41.726026
6436 20:14:41.731930 CA PerBit enable=1, Macro0, CA PI delay=36
6437 20:14:41.732345
6438 20:14:41.732675 [CBTSetCACLKResult] CA Dly = 36
6439 20:14:41.735986 CS Dly: 1 (0~32)
6440 20:14:41.736515 ==
6441 20:14:41.739158 Dram Type= 6, Freq= 0, CH_1, rank 1
6442 20:14:41.741810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6443 20:14:41.742275 ==
6444 20:14:41.749511 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6445 20:14:41.756505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6446 20:14:41.758656 [CA 0] Center 36 (8~64) winsize 57
6447 20:14:41.762071 [CA 1] Center 36 (8~64) winsize 57
6448 20:14:41.766077 [CA 2] Center 36 (8~64) winsize 57
6449 20:14:41.766603 [CA 3] Center 36 (8~64) winsize 57
6450 20:14:41.768558 [CA 4] Center 36 (8~64) winsize 57
6451 20:14:41.772102 [CA 5] Center 36 (8~64) winsize 57
6452 20:14:41.772620
6453 20:14:41.778845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6454 20:14:41.779376
6455 20:14:41.783727 [CATrainingPosCal] consider 2 rank data
6456 20:14:41.785432 u2DelayCellTimex100 = 270/100 ps
6457 20:14:41.788420 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 20:14:41.792039 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 20:14:41.795492 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 20:14:41.799147 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 20:14:41.801572 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 20:14:41.805687 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 20:14:41.806249
6464 20:14:41.808449 CA PerBit enable=1, Macro0, CA PI delay=36
6465 20:14:41.808949
6466 20:14:41.812340 [CBTSetCACLKResult] CA Dly = 36
6467 20:14:41.814769 CS Dly: 1 (0~32)
6468 20:14:41.815189
6469 20:14:41.818323 ----->DramcWriteLeveling(PI) begin...
6470 20:14:41.818752 ==
6471 20:14:41.821569 Dram Type= 6, Freq= 0, CH_1, rank 0
6472 20:14:41.825537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6473 20:14:41.825962 ==
6474 20:14:41.828465 Write leveling (Byte 0): 32 => 0
6475 20:14:41.831257 Write leveling (Byte 1): 32 => 0
6476 20:14:41.834954 DramcWriteLeveling(PI) end<-----
6477 20:14:41.835471
6478 20:14:41.835804 ==
6479 20:14:41.839119 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 20:14:41.841471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 20:14:41.841895 ==
6482 20:14:41.845598 [Gating] SW mode calibration
6483 20:14:41.851801 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 20:14:41.858024 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6485 20:14:41.861382 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 20:14:41.865534 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 20:14:41.871174 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 20:14:41.874610 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6489 20:14:41.877874 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 20:14:41.884865 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 20:14:41.887983 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 20:14:41.891283 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6493 20:14:41.899439 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 20:14:41.899960 Total UI for P1: 0, mck2ui 16
6495 20:14:41.904287 best dqsien dly found for B0: ( 0, 10, 16)
6496 20:14:41.904783 Total UI for P1: 0, mck2ui 16
6497 20:14:41.911515 best dqsien dly found for B1: ( 0, 10, 16)
6498 20:14:41.915070 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6499 20:14:41.917951 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6500 20:14:41.918418
6501 20:14:41.921001 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6502 20:14:41.924754 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6503 20:14:41.928594 [Gating] SW calibration Done
6504 20:14:41.929176 ==
6505 20:14:41.930712 Dram Type= 6, Freq= 0, CH_1, rank 0
6506 20:14:41.934904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6507 20:14:41.935427 ==
6508 20:14:41.937519 RX Vref Scan: 0
6509 20:14:41.937941
6510 20:14:41.940456 RX Vref 0 -> 0, step: 1
6511 20:14:41.940925
6512 20:14:41.941263 RX Delay -410 -> 252, step: 16
6513 20:14:41.947829 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6514 20:14:41.950817 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6515 20:14:41.954062 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6516 20:14:41.958272 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6517 20:14:41.964469 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6518 20:14:41.968441 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6519 20:14:41.970927 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6520 20:14:41.977541 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6521 20:14:41.980881 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6522 20:14:41.984464 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 20:14:41.987492 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 20:14:41.993640 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 20:14:41.997459 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 20:14:42.000330 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 20:14:42.003777 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6528 20:14:42.012453 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6529 20:14:42.013089 ==
6530 20:14:42.013825 Dram Type= 6, Freq= 0, CH_1, rank 0
6531 20:14:42.017060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6532 20:14:42.017527 ==
6533 20:14:42.017896 DQS Delay:
6534 20:14:42.020247 DQS0 = 43, DQS1 = 59
6535 20:14:42.020940 DQM Delay:
6536 20:14:42.023354 DQM0 = 6, DQM1 = 14
6537 20:14:42.023811 DQ Delay:
6538 20:14:42.026801 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6539 20:14:42.030350 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6540 20:14:42.033030 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6541 20:14:42.036628 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6542 20:14:42.037207
6543 20:14:42.037538
6544 20:14:42.037843 ==
6545 20:14:42.039926 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 20:14:42.043440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 20:14:42.043861 ==
6548 20:14:42.044190
6549 20:14:42.044558
6550 20:14:42.046693 TX Vref Scan disable
6551 20:14:42.051099 == TX Byte 0 ==
6552 20:14:42.053385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6553 20:14:42.056638 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6554 20:14:42.059812 == TX Byte 1 ==
6555 20:14:42.063358 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6556 20:14:42.066508 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6557 20:14:42.067029 ==
6558 20:14:42.069815 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 20:14:42.073442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 20:14:42.076115 ==
6561 20:14:42.076581
6562 20:14:42.077000
6563 20:14:42.077345 TX Vref Scan disable
6564 20:14:42.079582 == TX Byte 0 ==
6565 20:14:42.083219 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 20:14:42.086780 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 20:14:42.089326 == TX Byte 1 ==
6568 20:14:42.092797 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 20:14:42.096090 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 20:14:42.096701
6571 20:14:42.100015 [DATLAT]
6572 20:14:42.100574 Freq=400, CH1 RK0
6573 20:14:42.101076
6574 20:14:42.103959 DATLAT Default: 0xf
6575 20:14:42.104422 0, 0xFFFF, sum = 0
6576 20:14:42.105820 1, 0xFFFF, sum = 0
6577 20:14:42.106282 2, 0xFFFF, sum = 0
6578 20:14:42.109391 3, 0xFFFF, sum = 0
6579 20:14:42.109917 4, 0xFFFF, sum = 0
6580 20:14:42.112357 5, 0xFFFF, sum = 0
6581 20:14:42.112817 6, 0xFFFF, sum = 0
6582 20:14:42.116368 7, 0xFFFF, sum = 0
6583 20:14:42.116944 8, 0xFFFF, sum = 0
6584 20:14:42.119441 9, 0xFFFF, sum = 0
6585 20:14:42.124615 10, 0xFFFF, sum = 0
6586 20:14:42.125187 11, 0xFFFF, sum = 0
6587 20:14:42.125896 12, 0x0, sum = 1
6588 20:14:42.126252 13, 0x0, sum = 2
6589 20:14:42.128863 14, 0x0, sum = 3
6590 20:14:42.129291 15, 0x0, sum = 4
6591 20:14:42.129628 best_step = 13
6592 20:14:42.129940
6593 20:14:42.133044 ==
6594 20:14:42.135893 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 20:14:42.139417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6596 20:14:42.140120 ==
6597 20:14:42.140481 RX Vref Scan: 1
6598 20:14:42.140859
6599 20:14:42.142315 RX Vref 0 -> 0, step: 1
6600 20:14:42.142750
6601 20:14:42.145938 RX Delay -359 -> 252, step: 8
6602 20:14:42.146375
6603 20:14:42.148842 Set Vref, RX VrefLevel [Byte0]: 55
6604 20:14:42.153324 [Byte1]: 49
6605 20:14:42.155882
6606 20:14:42.156404 Final RX Vref Byte 0 = 55 to rank0
6607 20:14:42.159481 Final RX Vref Byte 1 = 49 to rank0
6608 20:14:42.162773 Final RX Vref Byte 0 = 55 to rank1
6609 20:14:42.166049 Final RX Vref Byte 1 = 49 to rank1==
6610 20:14:42.169494 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 20:14:42.175935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 20:14:42.176442 ==
6613 20:14:42.176821 DQS Delay:
6614 20:14:42.179104 DQS0 = 48, DQS1 = 64
6615 20:14:42.179621 DQM Delay:
6616 20:14:42.179957 DQM0 = 8, DQM1 = 16
6617 20:14:42.182305 DQ Delay:
6618 20:14:42.185421 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6619 20:14:42.185842 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6620 20:14:42.189190 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6621 20:14:42.192573 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6622 20:14:42.193132
6623 20:14:42.195653
6624 20:14:42.202638 [DQSOSCAuto] RK0, (LSB)MR18= 0xd8d8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6625 20:14:42.205562 CH1 RK0: MR19=C0C, MR18=D8D8
6626 20:14:42.212599 CH1_RK0: MR19=0xC0C, MR18=0xD8D8, DQSOSC=383, MR23=63, INC=402, DEC=268
6627 20:14:42.213165 ==
6628 20:14:42.215728 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 20:14:42.219208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 20:14:42.219731 ==
6631 20:14:42.222533 [Gating] SW mode calibration
6632 20:14:42.228454 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6633 20:14:42.235833 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6634 20:14:42.238315 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6635 20:14:42.242023 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6636 20:14:42.248921 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6637 20:14:42.251521 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6638 20:14:42.255207 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6639 20:14:42.261486 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6640 20:14:42.265667 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 20:14:42.268687 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6642 20:14:42.274911 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 20:14:42.275395 Total UI for P1: 0, mck2ui 16
6644 20:14:42.281557 best dqsien dly found for B0: ( 0, 10, 16)
6645 20:14:42.282125 Total UI for P1: 0, mck2ui 16
6646 20:14:42.285354 best dqsien dly found for B1: ( 0, 10, 16)
6647 20:14:42.291260 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6648 20:14:42.294675 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6649 20:14:42.295239
6650 20:14:42.297879 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6651 20:14:42.300970 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6652 20:14:42.304524 [Gating] SW calibration Done
6653 20:14:42.305114 ==
6654 20:14:42.307411 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 20:14:42.310746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6656 20:14:42.311212 ==
6657 20:14:42.313881 RX Vref Scan: 0
6658 20:14:42.314345
6659 20:14:42.314712 RX Vref 0 -> 0, step: 1
6660 20:14:42.317372
6661 20:14:42.317929 RX Delay -410 -> 252, step: 16
6662 20:14:42.324179 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6663 20:14:42.327307 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6664 20:14:42.330574 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6665 20:14:42.334005 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6666 20:14:42.341572 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6667 20:14:42.343749 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6668 20:14:42.347494 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6669 20:14:42.353646 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6670 20:14:42.357619 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6671 20:14:42.360893 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6672 20:14:42.363314 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6673 20:14:42.370145 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6674 20:14:42.373526 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6675 20:14:42.376792 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6676 20:14:42.380266 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6677 20:14:42.387084 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6678 20:14:42.387633 ==
6679 20:14:42.390247 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 20:14:42.392981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6681 20:14:42.393460 ==
6682 20:14:42.393826 DQS Delay:
6683 20:14:42.396964 DQS0 = 43, DQS1 = 59
6684 20:14:42.397533 DQM Delay:
6685 20:14:42.400238 DQM0 = 10, DQM1 = 18
6686 20:14:42.400844 DQ Delay:
6687 20:14:42.403194 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6688 20:14:42.407184 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6689 20:14:42.409961 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6690 20:14:42.413645 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6691 20:14:42.414212
6692 20:14:42.414581
6693 20:14:42.414921 ==
6694 20:14:42.416587 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 20:14:42.419911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 20:14:42.420484 ==
6697 20:14:42.420947
6698 20:14:42.421303
6699 20:14:42.423318 TX Vref Scan disable
6700 20:14:42.426338 == TX Byte 0 ==
6701 20:14:42.429510 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6702 20:14:42.433011 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6703 20:14:42.436031 == TX Byte 1 ==
6704 20:14:42.440022 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6705 20:14:42.442771 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6706 20:14:42.443358 ==
6707 20:14:42.445816 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 20:14:42.449590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 20:14:42.450162 ==
6710 20:14:42.450531
6711 20:14:42.453228
6712 20:14:42.453693 TX Vref Scan disable
6713 20:14:42.456287 == TX Byte 0 ==
6714 20:14:42.459954 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6715 20:14:42.462633 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6716 20:14:42.465848 == TX Byte 1 ==
6717 20:14:42.469026 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6718 20:14:42.472786 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6719 20:14:42.473320
6720 20:14:42.473655 [DATLAT]
6721 20:14:42.477062 Freq=400, CH1 RK1
6722 20:14:42.477510
6723 20:14:42.479827 DATLAT Default: 0xd
6724 20:14:42.480246 0, 0xFFFF, sum = 0
6725 20:14:42.483252 1, 0xFFFF, sum = 0
6726 20:14:42.483845 2, 0xFFFF, sum = 0
6727 20:14:42.485877 3, 0xFFFF, sum = 0
6728 20:14:42.486309 4, 0xFFFF, sum = 0
6729 20:14:42.488871 5, 0xFFFF, sum = 0
6730 20:14:42.489332 6, 0xFFFF, sum = 0
6731 20:14:42.492505 7, 0xFFFF, sum = 0
6732 20:14:42.492964 8, 0xFFFF, sum = 0
6733 20:14:42.496112 9, 0xFFFF, sum = 0
6734 20:14:42.496645 10, 0xFFFF, sum = 0
6735 20:14:42.499024 11, 0xFFFF, sum = 0
6736 20:14:42.499556 12, 0x0, sum = 1
6737 20:14:42.502139 13, 0x0, sum = 2
6738 20:14:42.502678 14, 0x0, sum = 3
6739 20:14:42.505354 15, 0x0, sum = 4
6740 20:14:42.505886 best_step = 13
6741 20:14:42.506221
6742 20:14:42.506533 ==
6743 20:14:42.508952 Dram Type= 6, Freq= 0, CH_1, rank 1
6744 20:14:42.515746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6745 20:14:42.516289 ==
6746 20:14:42.516632 RX Vref Scan: 0
6747 20:14:42.517030
6748 20:14:42.518357 RX Vref 0 -> 0, step: 1
6749 20:14:42.518776
6750 20:14:42.521688 RX Delay -359 -> 252, step: 8
6751 20:14:42.528996 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6752 20:14:42.531986 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6753 20:14:42.535447 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6754 20:14:42.538418 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6755 20:14:42.544907 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6756 20:14:42.548417 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6757 20:14:42.551646 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6758 20:14:42.555181 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6759 20:14:42.562458 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6760 20:14:42.564874 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6761 20:14:42.568084 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6762 20:14:42.574873 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6763 20:14:42.578692 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6764 20:14:42.581097 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6765 20:14:42.584795 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6766 20:14:42.591731 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6767 20:14:42.592302 ==
6768 20:14:42.594575 Dram Type= 6, Freq= 0, CH_1, rank 1
6769 20:14:42.598127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6770 20:14:42.598703 ==
6771 20:14:42.599073 DQS Delay:
6772 20:14:42.601305 DQS0 = 48, DQS1 = 64
6773 20:14:42.601914 DQM Delay:
6774 20:14:42.604463 DQM0 = 9, DQM1 = 15
6775 20:14:42.605216 DQ Delay:
6776 20:14:42.607866 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6777 20:14:42.610833 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6778 20:14:42.614745 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6779 20:14:42.617658 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6780 20:14:42.618220
6781 20:14:42.618586
6782 20:14:42.624871 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6783 20:14:42.627390 CH1 RK1: MR19=C0C, MR18=B0B0
6784 20:14:42.634612 CH1_RK1: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6785 20:14:42.638012 [RxdqsGatingPostProcess] freq 400
6786 20:14:42.644178 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6787 20:14:42.647691 Pre-setting of DQS Precalculation
6788 20:14:42.650592 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6789 20:14:42.657371 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6790 20:14:42.663833 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6791 20:14:42.667380
6792 20:14:42.667849
6793 20:14:42.668217 [Calibration Summary] 800 Mbps
6794 20:14:42.670333 CH 0, Rank 0
6795 20:14:42.670801 SW Impedance : PASS
6796 20:14:42.673474 DUTY Scan : NO K
6797 20:14:42.677255 ZQ Calibration : PASS
6798 20:14:42.677727 Jitter Meter : NO K
6799 20:14:42.680204 CBT Training : PASS
6800 20:14:42.683723 Write leveling : PASS
6801 20:14:42.684302 RX DQS gating : PASS
6802 20:14:42.686849 RX DQ/DQS(RDDQC) : PASS
6803 20:14:42.691009 TX DQ/DQS : PASS
6804 20:14:42.691585 RX DATLAT : PASS
6805 20:14:42.693439 RX DQ/DQS(Engine): PASS
6806 20:14:42.697554 TX OE : NO K
6807 20:14:42.698135 All Pass.
6808 20:14:42.698629
6809 20:14:42.699089 CH 0, Rank 1
6810 20:14:42.699904 SW Impedance : PASS
6811 20:14:42.703568 DUTY Scan : NO K
6812 20:14:42.704145 ZQ Calibration : PASS
6813 20:14:42.707073 Jitter Meter : NO K
6814 20:14:42.710163 CBT Training : PASS
6815 20:14:42.710742 Write leveling : NO K
6816 20:14:42.713265 RX DQS gating : PASS
6817 20:14:42.713749 RX DQ/DQS(RDDQC) : PASS
6818 20:14:42.717576 TX DQ/DQS : PASS
6819 20:14:42.719905 RX DATLAT : PASS
6820 20:14:42.720391 RX DQ/DQS(Engine): PASS
6821 20:14:42.722997 TX OE : NO K
6822 20:14:42.723522 All Pass.
6823 20:14:42.724003
6824 20:14:42.726164 CH 1, Rank 0
6825 20:14:42.726627 SW Impedance : PASS
6826 20:14:42.730583 DUTY Scan : NO K
6827 20:14:42.733814 ZQ Calibration : PASS
6828 20:14:42.734267 Jitter Meter : NO K
6829 20:14:42.737975 CBT Training : PASS
6830 20:14:42.739838 Write leveling : PASS
6831 20:14:42.740252 RX DQS gating : PASS
6832 20:14:42.742918 RX DQ/DQS(RDDQC) : PASS
6833 20:14:42.746888 TX DQ/DQS : PASS
6834 20:14:42.747413 RX DATLAT : PASS
6835 20:14:42.749839 RX DQ/DQS(Engine): PASS
6836 20:14:42.753416 TX OE : NO K
6837 20:14:42.753930 All Pass.
6838 20:14:42.754261
6839 20:14:42.754566 CH 1, Rank 1
6840 20:14:42.756548 SW Impedance : PASS
6841 20:14:42.760010 DUTY Scan : NO K
6842 20:14:42.760577 ZQ Calibration : PASS
6843 20:14:42.763332 Jitter Meter : NO K
6844 20:14:42.766917 CBT Training : PASS
6845 20:14:42.767387 Write leveling : NO K
6846 20:14:42.770812 RX DQS gating : PASS
6847 20:14:42.773316 RX DQ/DQS(RDDQC) : PASS
6848 20:14:42.773881 TX DQ/DQS : PASS
6849 20:14:42.777928 RX DATLAT : PASS
6850 20:14:42.778496 RX DQ/DQS(Engine): PASS
6851 20:14:42.779597 TX OE : NO K
6852 20:14:42.780060 All Pass.
6853 20:14:42.780425
6854 20:14:42.782812 DramC Write-DBI off
6855 20:14:42.786256 PER_BANK_REFRESH: Hybrid Mode
6856 20:14:42.786817 TX_TRACKING: ON
6857 20:14:42.796008 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6858 20:14:42.799654 [FAST_K] Save calibration result to emmc
6859 20:14:42.802564 dramc_set_vcore_voltage set vcore to 725000
6860 20:14:42.805813 Read voltage for 1600, 0
6861 20:14:42.806279 Vio18 = 0
6862 20:14:42.809154 Vcore = 725000
6863 20:14:42.809719 Vdram = 0
6864 20:14:42.810090 Vddq = 0
6865 20:14:42.810428 Vmddr = 0
6866 20:14:42.818228 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6867 20:14:42.822050 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6868 20:14:42.822520 MEM_TYPE=3, freq_sel=13
6869 20:14:42.825404 sv_algorithm_assistance_LP4_3733
6870 20:14:42.828940 ============ PULL DRAM RESETB DOWN ============
6871 20:14:42.835294 ========== PULL DRAM RESETB DOWN end =========
6872 20:14:42.839124 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6873 20:14:42.842111 ===================================
6874 20:14:42.845316 LPDDR4 DRAM CONFIGURATION
6875 20:14:42.848902 ===================================
6876 20:14:42.849460 EX_ROW_EN[0] = 0x0
6877 20:14:42.852290 EX_ROW_EN[1] = 0x0
6878 20:14:42.856398 LP4Y_EN = 0x0
6879 20:14:42.857019 WORK_FSP = 0x1
6880 20:14:42.859746 WL = 0x5
6881 20:14:42.860311 RL = 0x5
6882 20:14:42.861722 BL = 0x2
6883 20:14:42.862187 RPST = 0x0
6884 20:14:42.864785 RD_PRE = 0x0
6885 20:14:42.865249 WR_PRE = 0x1
6886 20:14:42.868761 WR_PST = 0x1
6887 20:14:42.869338 DBI_WR = 0x0
6888 20:14:42.872273 DBI_RD = 0x0
6889 20:14:42.872876 OTF = 0x1
6890 20:14:42.875467 ===================================
6891 20:14:42.878350 ===================================
6892 20:14:42.882089 ANA top config
6893 20:14:42.885220 ===================================
6894 20:14:42.885689 DLL_ASYNC_EN = 0
6895 20:14:42.888150 ALL_SLAVE_EN = 0
6896 20:14:42.891384 NEW_RANK_MODE = 1
6897 20:14:42.895302 DLL_IDLE_MODE = 1
6898 20:14:42.898954 LP45_APHY_COMB_EN = 1
6899 20:14:42.899517 TX_ODT_DIS = 0
6900 20:14:42.901604 NEW_8X_MODE = 1
6901 20:14:42.904579 ===================================
6902 20:14:42.908260 ===================================
6903 20:14:42.911748 data_rate = 3200
6904 20:14:42.915997 CKR = 1
6905 20:14:42.918287 DQ_P2S_RATIO = 8
6906 20:14:42.921296 ===================================
6907 20:14:42.925039 CA_P2S_RATIO = 8
6908 20:14:42.925558 DQ_CA_OPEN = 0
6909 20:14:42.927629 DQ_SEMI_OPEN = 0
6910 20:14:42.931590 CA_SEMI_OPEN = 0
6911 20:14:42.934555 CA_FULL_RATE = 0
6912 20:14:42.937410 DQ_CKDIV4_EN = 0
6913 20:14:42.942463 CA_CKDIV4_EN = 0
6914 20:14:42.942980 CA_PREDIV_EN = 0
6915 20:14:42.944523 PH8_DLY = 12
6916 20:14:42.947907 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6917 20:14:42.951044 DQ_AAMCK_DIV = 4
6918 20:14:42.954494 CA_AAMCK_DIV = 4
6919 20:14:42.958664 CA_ADMCK_DIV = 4
6920 20:14:42.959180 DQ_TRACK_CA_EN = 0
6921 20:14:42.960753 CA_PICK = 1600
6922 20:14:42.963991 CA_MCKIO = 1600
6923 20:14:42.968387 MCKIO_SEMI = 0
6924 20:14:42.970796 PLL_FREQ = 3068
6925 20:14:42.973803 DQ_UI_PI_RATIO = 32
6926 20:14:42.977196 CA_UI_PI_RATIO = 0
6927 20:14:42.981677 ===================================
6928 20:14:42.984146 ===================================
6929 20:14:42.984667 memory_type:LPDDR4
6930 20:14:42.987592 GP_NUM : 10
6931 20:14:42.991415 SRAM_EN : 1
6932 20:14:42.991938 MD32_EN : 0
6933 20:14:42.994992 ===================================
6934 20:14:42.997140 [ANA_INIT] >>>>>>>>>>>>>>
6935 20:14:43.000831 <<<<<< [CONFIGURE PHASE]: ANA_TX
6936 20:14:43.003719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6937 20:14:43.007101 ===================================
6938 20:14:43.010667 data_rate = 3200,PCW = 0X7600
6939 20:14:43.014906 ===================================
6940 20:14:43.017164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6941 20:14:43.020802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6942 20:14:43.027653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6943 20:14:43.033020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6944 20:14:43.036739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6945 20:14:43.039712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6946 20:14:43.040137 [ANA_INIT] flow start
6947 20:14:43.043947 [ANA_INIT] PLL >>>>>>>>
6948 20:14:43.047058 [ANA_INIT] PLL <<<<<<<<
6949 20:14:43.047576 [ANA_INIT] MIDPI >>>>>>>>
6950 20:14:43.050125 [ANA_INIT] MIDPI <<<<<<<<
6951 20:14:43.053289 [ANA_INIT] DLL >>>>>>>>
6952 20:14:43.053710 [ANA_INIT] DLL <<<<<<<<
6953 20:14:43.056822 [ANA_INIT] flow end
6954 20:14:43.059712 ============ LP4 DIFF to SE enter ============
6955 20:14:43.063299 ============ LP4 DIFF to SE exit ============
6956 20:14:43.066341 [ANA_INIT] <<<<<<<<<<<<<
6957 20:14:43.069438 [Flow] Enable top DCM control >>>>>
6958 20:14:43.073345 [Flow] Enable top DCM control <<<<<
6959 20:14:43.077205 Enable DLL master slave shuffle
6960 20:14:43.083049 ==============================================================
6961 20:14:43.083600 Gating Mode config
6962 20:14:43.090378 ==============================================================
6963 20:14:43.093009 Config description:
6964 20:14:43.100200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6965 20:14:43.105888 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6966 20:14:43.113213 SELPH_MODE 0: By rank 1: By Phase
6967 20:14:43.119420 ==============================================================
6968 20:14:43.122327 GAT_TRACK_EN = 1
6969 20:14:43.122846 RX_GATING_MODE = 2
6970 20:14:43.126319 RX_GATING_TRACK_MODE = 2
6971 20:14:43.129408 SELPH_MODE = 1
6972 20:14:43.132534 PICG_EARLY_EN = 1
6973 20:14:43.135935 VALID_LAT_VALUE = 1
6974 20:14:43.142640 ==============================================================
6975 20:14:43.146134 Enter into Gating configuration >>>>
6976 20:14:43.148897 Exit from Gating configuration <<<<
6977 20:14:43.153524 Enter into DVFS_PRE_config >>>>>
6978 20:14:43.162888 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6979 20:14:43.165490 Exit from DVFS_PRE_config <<<<<
6980 20:14:43.168786 Enter into PICG configuration >>>>
6981 20:14:43.172441 Exit from PICG configuration <<<<
6982 20:14:43.175570 [RX_INPUT] configuration >>>>>
6983 20:14:43.178502 [RX_INPUT] configuration <<<<<
6984 20:14:43.181951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6985 20:14:43.188756 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6986 20:14:43.195445 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6987 20:14:43.199113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6988 20:14:43.205257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6989 20:14:43.212567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6990 20:14:43.215681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6991 20:14:43.222071 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6992 20:14:43.225182 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6993 20:14:43.228581 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6994 20:14:43.232011 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6995 20:14:43.238686 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6996 20:14:43.241942 ===================================
6997 20:14:43.242505 LPDDR4 DRAM CONFIGURATION
6998 20:14:43.245491 ===================================
6999 20:14:43.248793 EX_ROW_EN[0] = 0x0
7000 20:14:43.251377 EX_ROW_EN[1] = 0x0
7001 20:14:43.251840 LP4Y_EN = 0x0
7002 20:14:43.254802 WORK_FSP = 0x1
7003 20:14:43.255268 WL = 0x5
7004 20:14:43.258130 RL = 0x5
7005 20:14:43.258720 BL = 0x2
7006 20:14:43.261915 RPST = 0x0
7007 20:14:43.262380 RD_PRE = 0x0
7008 20:14:43.264668 WR_PRE = 0x1
7009 20:14:43.265185 WR_PST = 0x1
7010 20:14:43.268012 DBI_WR = 0x0
7011 20:14:43.268590 DBI_RD = 0x0
7012 20:14:43.272040 OTF = 0x1
7013 20:14:43.275669 ===================================
7014 20:14:43.278456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7015 20:14:43.281076 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7016 20:14:43.288359 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7017 20:14:43.291036 ===================================
7018 20:14:43.291520 LPDDR4 DRAM CONFIGURATION
7019 20:14:43.295076 ===================================
7020 20:14:43.297648 EX_ROW_EN[0] = 0x10
7021 20:14:43.301509 EX_ROW_EN[1] = 0x0
7022 20:14:43.301978 LP4Y_EN = 0x0
7023 20:14:43.304668 WORK_FSP = 0x1
7024 20:14:43.305272 WL = 0x5
7025 20:14:43.307492 RL = 0x5
7026 20:14:43.307959 BL = 0x2
7027 20:14:43.311438 RPST = 0x0
7028 20:14:43.312005 RD_PRE = 0x0
7029 20:14:43.314490 WR_PRE = 0x1
7030 20:14:43.315062 WR_PST = 0x1
7031 20:14:43.317904 DBI_WR = 0x0
7032 20:14:43.318479 DBI_RD = 0x0
7033 20:14:43.320590 OTF = 0x1
7034 20:14:43.324521 ===================================
7035 20:14:43.330503 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7036 20:14:43.331021 ==
7037 20:14:43.335134 Dram Type= 6, Freq= 0, CH_0, rank 0
7038 20:14:43.337497 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7039 20:14:43.337970 ==
7040 20:14:43.340821 [Duty_Offset_Calibration]
7041 20:14:43.341287 B0:0 B1:2 CA:1
7042 20:14:43.341658
7043 20:14:43.344579 [DutyScan_Calibration_Flow] k_type=0
7044 20:14:43.355265
7045 20:14:43.355836 ==CLK 0==
7046 20:14:43.359340 Final CLK duty delay cell = 0
7047 20:14:43.361351 [0] MAX Duty = 5187%(X100), DQS PI = 24
7048 20:14:43.364979 [0] MIN Duty = 4938%(X100), DQS PI = 52
7049 20:14:43.365557 [0] AVG Duty = 5062%(X100)
7050 20:14:43.368353
7051 20:14:43.372016 CH0 CLK Duty spec in!! Max-Min= 249%
7052 20:14:43.375000 [DutyScan_Calibration_Flow] ====Done====
7053 20:14:43.375570
7054 20:14:43.378296 [DutyScan_Calibration_Flow] k_type=1
7055 20:14:43.395424
7056 20:14:43.396004 ==DQS 0 ==
7057 20:14:43.398326 Final DQS duty delay cell = 0
7058 20:14:43.401839 [0] MAX Duty = 5156%(X100), DQS PI = 32
7059 20:14:43.405398 [0] MIN Duty = 5031%(X100), DQS PI = 10
7060 20:14:43.408518 [0] AVG Duty = 5093%(X100)
7061 20:14:43.409020
7062 20:14:43.409392 ==DQS 1 ==
7063 20:14:43.411897 Final DQS duty delay cell = 0
7064 20:14:43.415159 [0] MAX Duty = 5031%(X100), DQS PI = 4
7065 20:14:43.417900 [0] MIN Duty = 4844%(X100), DQS PI = 18
7066 20:14:43.421211 [0] AVG Duty = 4937%(X100)
7067 20:14:43.421681
7068 20:14:43.424993 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7069 20:14:43.425462
7070 20:14:43.428316 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7071 20:14:43.431459 [DutyScan_Calibration_Flow] ====Done====
7072 20:14:43.431928
7073 20:14:43.434284 [DutyScan_Calibration_Flow] k_type=3
7074 20:14:43.452470
7075 20:14:43.453097 ==DQM 0 ==
7076 20:14:43.455589 Final DQM duty delay cell = 0
7077 20:14:43.459258 [0] MAX Duty = 5187%(X100), DQS PI = 22
7078 20:14:43.462860 [0] MIN Duty = 4907%(X100), DQS PI = 42
7079 20:14:43.465636 [0] AVG Duty = 5047%(X100)
7080 20:14:43.466189
7081 20:14:43.466567 ==DQM 1 ==
7082 20:14:43.468944 Final DQM duty delay cell = 0
7083 20:14:43.472269 [0] MAX Duty = 5031%(X100), DQS PI = 50
7084 20:14:43.475337 [0] MIN Duty = 4782%(X100), DQS PI = 14
7085 20:14:43.479335 [0] AVG Duty = 4906%(X100)
7086 20:14:43.479804
7087 20:14:43.481887 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7088 20:14:43.482357
7089 20:14:43.485426 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7090 20:14:43.488382 [DutyScan_Calibration_Flow] ====Done====
7091 20:14:43.488886
7092 20:14:43.492342 [DutyScan_Calibration_Flow] k_type=2
7093 20:14:43.508542
7094 20:14:43.509150 ==DQ 0 ==
7095 20:14:43.511701 Final DQ duty delay cell = 0
7096 20:14:43.514920 [0] MAX Duty = 5218%(X100), DQS PI = 18
7097 20:14:43.518821 [0] MIN Duty = 4938%(X100), DQS PI = 56
7098 20:14:43.521751 [0] AVG Duty = 5078%(X100)
7099 20:14:43.522216
7100 20:14:43.522582 ==DQ 1 ==
7101 20:14:43.524831 Final DQ duty delay cell = -4
7102 20:14:43.528069 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7103 20:14:43.531930 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7104 20:14:43.534742 [-4] AVG Duty = 4953%(X100)
7105 20:14:43.535208
7106 20:14:43.538066 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7107 20:14:43.538530
7108 20:14:43.541851 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7109 20:14:43.544642 [DutyScan_Calibration_Flow] ====Done====
7110 20:14:43.545160 ==
7111 20:14:43.548184 Dram Type= 6, Freq= 0, CH_1, rank 0
7112 20:14:43.551394 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7113 20:14:43.551818 ==
7114 20:14:43.554726 [Duty_Offset_Calibration]
7115 20:14:43.555242 B0:0 B1:4 CA:-5
7116 20:14:43.555579
7117 20:14:43.558143 [DutyScan_Calibration_Flow] k_type=0
7118 20:14:43.571307
7119 20:14:43.571822 ==CLK 0==
7120 20:14:43.572767 Final CLK duty delay cell = 0
7121 20:14:43.576119 [0] MAX Duty = 5156%(X100), DQS PI = 20
7122 20:14:43.579270 [0] MIN Duty = 4906%(X100), DQS PI = 52
7123 20:14:43.582814 [0] AVG Duty = 5031%(X100)
7124 20:14:43.583332
7125 20:14:43.586147 CH1 CLK Duty spec in!! Max-Min= 250%
7126 20:14:43.589708 [DutyScan_Calibration_Flow] ====Done====
7127 20:14:43.590243
7128 20:14:43.592286 [DutyScan_Calibration_Flow] k_type=1
7129 20:14:43.607889
7130 20:14:43.608505 ==DQS 0 ==
7131 20:14:43.611297 Final DQS duty delay cell = 0
7132 20:14:43.614691 [0] MAX Duty = 5187%(X100), DQS PI = 20
7133 20:14:43.618077 [0] MIN Duty = 4876%(X100), DQS PI = 42
7134 20:14:43.621403 [0] AVG Duty = 5031%(X100)
7135 20:14:43.621870
7136 20:14:43.622328 ==DQS 1 ==
7137 20:14:43.624287 Final DQS duty delay cell = -4
7138 20:14:43.627613 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7139 20:14:43.630807 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7140 20:14:43.634389 [-4] AVG Duty = 4922%(X100)
7141 20:14:43.634854
7142 20:14:43.637547 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7143 20:14:43.638012
7144 20:14:43.641018 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7145 20:14:43.645533 [DutyScan_Calibration_Flow] ====Done====
7146 20:14:43.646091
7147 20:14:43.647192 [DutyScan_Calibration_Flow] k_type=3
7148 20:14:43.664919
7149 20:14:43.665478 ==DQM 0 ==
7150 20:14:43.667059 Final DQM duty delay cell = -4
7151 20:14:43.670693 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7152 20:14:43.673457 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7153 20:14:43.677671 [-4] AVG Duty = 4937%(X100)
7154 20:14:43.678247
7155 20:14:43.678614 ==DQM 1 ==
7156 20:14:43.680526 Final DQM duty delay cell = -4
7157 20:14:43.683467 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7158 20:14:43.687054 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7159 20:14:43.689932 [-4] AVG Duty = 4984%(X100)
7160 20:14:43.690403
7161 20:14:43.693597 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7162 20:14:43.694159
7163 20:14:43.696884 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7164 20:14:43.700488 [DutyScan_Calibration_Flow] ====Done====
7165 20:14:43.701091
7166 20:14:43.703444 [DutyScan_Calibration_Flow] k_type=2
7167 20:14:43.721179
7168 20:14:43.721938 ==DQ 0 ==
7169 20:14:43.725165 Final DQ duty delay cell = 0
7170 20:14:43.727656 [0] MAX Duty = 5093%(X100), DQS PI = 34
7171 20:14:43.731135 [0] MIN Duty = 4938%(X100), DQS PI = 46
7172 20:14:43.731638 [0] AVG Duty = 5015%(X100)
7173 20:14:43.734440
7174 20:14:43.734902 ==DQ 1 ==
7175 20:14:43.738451 Final DQ duty delay cell = 0
7176 20:14:43.741073 [0] MAX Duty = 5031%(X100), DQS PI = 4
7177 20:14:43.744244 [0] MIN Duty = 4876%(X100), DQS PI = 28
7178 20:14:43.744746 [0] AVG Duty = 4953%(X100)
7179 20:14:43.745171
7180 20:14:43.747693 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7181 20:14:43.751007
7182 20:14:43.754197 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7183 20:14:43.757760 [DutyScan_Calibration_Flow] ====Done====
7184 20:14:43.761305 nWR fixed to 30
7185 20:14:43.761774 [ModeRegInit_LP4] CH0 RK0
7186 20:14:43.764379 [ModeRegInit_LP4] CH0 RK1
7187 20:14:43.767478 [ModeRegInit_LP4] CH1 RK0
7188 20:14:43.770996 [ModeRegInit_LP4] CH1 RK1
7189 20:14:43.771555 match AC timing 4
7190 20:14:43.774047 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7191 20:14:43.781916 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7192 20:14:43.784150 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7193 20:14:43.791086 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7194 20:14:43.794257 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7195 20:14:43.794824 [MiockJmeterHQA]
7196 20:14:43.795193
7197 20:14:43.797127 [DramcMiockJmeter] u1RxGatingPI = 0
7198 20:14:43.800816 0 : 4363, 4138
7199 20:14:43.801390 4 : 4257, 4029
7200 20:14:43.805130 8 : 4253, 4027
7201 20:14:43.805705 12 : 4363, 4137
7202 20:14:43.806079 16 : 4253, 4027
7203 20:14:43.806778 20 : 4252, 4027
7204 20:14:43.807147 24 : 4253, 4027
7205 20:14:43.810658 28 : 4253, 4026
7206 20:14:43.811235 32 : 4255, 4029
7207 20:14:43.813850 36 : 4257, 4032
7208 20:14:43.814427 40 : 4252, 4027
7209 20:14:43.817512 44 : 4252, 4027
7210 20:14:43.818089 48 : 4253, 4026
7211 20:14:43.818465 52 : 4252, 4027
7212 20:14:43.820934 56 : 4252, 4027
7213 20:14:43.821517 60 : 4255, 4029
7214 20:14:43.823705 64 : 4363, 4138
7215 20:14:43.824250 68 : 4366, 4139
7216 20:14:43.826973 72 : 4250, 4027
7217 20:14:43.827548 76 : 4253, 4027
7218 20:14:43.830215 80 : 4252, 4027
7219 20:14:43.830748 84 : 4250, 4027
7220 20:14:43.831376 88 : 4252, 4029
7221 20:14:43.833694 92 : 4250, 4027
7222 20:14:43.834291 96 : 4252, 4029
7223 20:14:43.837178 100 : 4250, 2693
7224 20:14:43.837654 104 : 4253, 0
7225 20:14:43.840328 108 : 4252, 0
7226 20:14:43.840862 112 : 4366, 0
7227 20:14:43.841246 116 : 4363, 0
7228 20:14:43.844109 120 : 4363, 0
7229 20:14:43.844680 124 : 4253, 0
7230 20:14:43.846745 128 : 4360, 0
7231 20:14:43.847218 132 : 4250, 0
7232 20:14:43.847658 136 : 4250, 0
7233 20:14:43.849877 140 : 4250, 0
7234 20:14:43.850349 144 : 4250, 0
7235 20:14:43.850725 148 : 4253, 0
7236 20:14:43.853425 152 : 4250, 0
7237 20:14:43.853908 156 : 4250, 0
7238 20:14:43.856643 160 : 4255, 0
7239 20:14:43.857173 164 : 4361, 0
7240 20:14:43.857544 168 : 4250, 0
7241 20:14:43.860563 172 : 4361, 0
7242 20:14:43.861202 176 : 4250, 0
7243 20:14:43.863152 180 : 4251, 0
7244 20:14:43.863684 184 : 4250, 0
7245 20:14:43.864075 188 : 4250, 0
7246 20:14:43.866838 192 : 4250, 0
7247 20:14:43.867373 196 : 4250, 0
7248 20:14:43.870054 200 : 4255, 0
7249 20:14:43.870524 204 : 4250, 0
7250 20:14:43.870897 208 : 4250, 0
7251 20:14:43.873103 212 : 4250, 0
7252 20:14:43.873578 216 : 4361, 0
7253 20:14:43.877102 220 : 4361, 545
7254 20:14:43.877666 224 : 4251, 3997
7255 20:14:43.878039 228 : 4360, 4137
7256 20:14:43.880430 232 : 4250, 4027
7257 20:14:43.880951 236 : 4250, 4027
7258 20:14:43.883750 240 : 4363, 4140
7259 20:14:43.884336 244 : 4250, 4027
7260 20:14:43.887319 248 : 4250, 4026
7261 20:14:43.887792 252 : 4360, 4138
7262 20:14:43.889649 256 : 4360, 4138
7263 20:14:43.890124 260 : 4250, 4027
7264 20:14:43.893803 264 : 4361, 4137
7265 20:14:43.894373 268 : 4250, 4027
7266 20:14:43.896637 272 : 4253, 4029
7267 20:14:43.897173 276 : 4250, 4027
7268 20:14:43.900466 280 : 4363, 4140
7269 20:14:43.901091 284 : 4250, 4027
7270 20:14:43.901471 288 : 4250, 4027
7271 20:14:43.903892 292 : 4250, 4027
7272 20:14:43.904463 296 : 4252, 4029
7273 20:14:43.907191 300 : 4250, 4026
7274 20:14:43.907756 304 : 4360, 4138
7275 20:14:43.910685 308 : 4361, 4138
7276 20:14:43.911159 312 : 4250, 4027
7277 20:14:43.913178 316 : 4250, 4026
7278 20:14:43.913654 320 : 4250, 4027
7279 20:14:43.917958 324 : 4250, 4027
7280 20:14:43.918528 328 : 4250, 4027
7281 20:14:43.919988 332 : 4250, 4026
7282 20:14:43.920456 336 : 4250, 3969
7283 20:14:43.922806 340 : 4250, 2105
7284 20:14:43.923278
7285 20:14:43.923641 MIOCK jitter meter ch=0
7286 20:14:43.923985
7287 20:14:43.927100 1T = (340-104) = 236 dly cells
7288 20:14:43.933354 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7289 20:14:43.933825 ==
7290 20:14:43.936702 Dram Type= 6, Freq= 0, CH_0, rank 0
7291 20:14:43.939775 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7292 20:14:43.940339 ==
7293 20:14:43.946059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7294 20:14:43.949724 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7295 20:14:43.952580 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7296 20:14:43.959059 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7297 20:14:43.969295 [CA 0] Center 41 (11~72) winsize 62
7298 20:14:43.971677 [CA 1] Center 41 (11~72) winsize 62
7299 20:14:43.975313 [CA 2] Center 37 (7~67) winsize 61
7300 20:14:43.977927 [CA 3] Center 37 (7~67) winsize 61
7301 20:14:43.981367 [CA 4] Center 35 (5~66) winsize 62
7302 20:14:43.985234 [CA 5] Center 35 (5~65) winsize 61
7303 20:14:43.985801
7304 20:14:43.988151 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7305 20:14:43.988745
7306 20:14:43.991545 [CATrainingPosCal] consider 1 rank data
7307 20:14:43.994300 u2DelayCellTimex100 = 275/100 ps
7308 20:14:44.001272 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7309 20:14:44.005002 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7310 20:14:44.008567 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7311 20:14:44.011154 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7312 20:14:44.014262 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7313 20:14:44.017761 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7314 20:14:44.018183
7315 20:14:44.021602 CA PerBit enable=1, Macro0, CA PI delay=35
7316 20:14:44.022128
7317 20:14:44.024421 [CBTSetCACLKResult] CA Dly = 35
7318 20:14:44.028048 CS Dly: 11 (0~42)
7319 20:14:44.031534 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7320 20:14:44.034281 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7321 20:14:44.034727 ==
7322 20:14:44.037652 Dram Type= 6, Freq= 0, CH_0, rank 1
7323 20:14:44.044973 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7324 20:14:44.045499 ==
7325 20:14:44.047606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7326 20:14:44.050728 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7327 20:14:44.057324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7328 20:14:44.064682 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7329 20:14:44.071048 [CA 0] Center 42 (12~73) winsize 62
7330 20:14:44.075035 [CA 1] Center 42 (12~73) winsize 62
7331 20:14:44.077360 [CA 2] Center 38 (9~68) winsize 60
7332 20:14:44.081293 [CA 3] Center 37 (8~67) winsize 60
7333 20:14:44.084908 [CA 4] Center 36 (6~66) winsize 61
7334 20:14:44.087453 [CA 5] Center 36 (6~66) winsize 61
7335 20:14:44.087975
7336 20:14:44.091409 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7337 20:14:44.091832
7338 20:14:44.094264 [CATrainingPosCal] consider 2 rank data
7339 20:14:44.098483 u2DelayCellTimex100 = 275/100 ps
7340 20:14:44.100923 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7341 20:14:44.107720 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7342 20:14:44.111825 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7343 20:14:44.113948 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7344 20:14:44.117507 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7345 20:14:44.121610 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7346 20:14:44.122133
7347 20:14:44.124274 CA PerBit enable=1, Macro0, CA PI delay=35
7348 20:14:44.124844
7349 20:14:44.128929 [CBTSetCACLKResult] CA Dly = 35
7350 20:14:44.131087 CS Dly: 11 (0~42)
7351 20:14:44.133811 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7352 20:14:44.137473 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7353 20:14:44.137895
7354 20:14:44.141446 ----->DramcWriteLeveling(PI) begin...
7355 20:14:44.141967 ==
7356 20:14:44.144252 Dram Type= 6, Freq= 0, CH_0, rank 0
7357 20:14:44.150377 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7358 20:14:44.150801 ==
7359 20:14:44.153802 Write leveling (Byte 0): 30 => 30
7360 20:14:44.154222 Write leveling (Byte 1): 26 => 26
7361 20:14:44.156781 DramcWriteLeveling(PI) end<-----
7362 20:14:44.157201
7363 20:14:44.160035 ==
7364 20:14:44.160451 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 20:14:44.166826 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 20:14:44.167244 ==
7367 20:14:44.170823 [Gating] SW mode calibration
7368 20:14:44.177092 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7369 20:14:44.180674 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7370 20:14:44.187484 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7371 20:14:44.190429 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7372 20:14:44.193383 0 12 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7373 20:14:44.200574 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7374 20:14:44.204218 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7375 20:14:44.206979 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7376 20:14:44.214574 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 20:14:44.216907 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7378 20:14:44.219616 0 13 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7379 20:14:44.227543 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
7380 20:14:44.229578 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7381 20:14:44.233217 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 20:14:44.240306 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 20:14:44.243494 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7384 20:14:44.246154 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 20:14:44.253618 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7386 20:14:44.256686 0 14 0 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
7387 20:14:44.259682 0 14 4 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
7388 20:14:44.266526 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7389 20:14:44.269983 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 20:14:44.273443 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7391 20:14:44.279508 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 20:14:44.284144 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7393 20:14:44.286052 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 20:14:44.293511 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7395 20:14:44.296350 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7396 20:14:44.299094 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 20:14:44.306299 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 20:14:44.309509 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 20:14:44.312419 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 20:14:44.316792 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 20:14:44.322552 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 20:14:44.325800 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 20:14:44.329663 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 20:14:44.336429 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 20:14:44.339165 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 20:14:44.342423 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 20:14:44.349168 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 20:14:44.352978 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 20:14:44.355802 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 20:14:44.362841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7411 20:14:44.366551 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7412 20:14:44.369444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7413 20:14:44.372333 Total UI for P1: 0, mck2ui 16
7414 20:14:44.375886 best dqsien dly found for B0: ( 1, 1, 2)
7415 20:14:44.382559 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7416 20:14:44.383106 Total UI for P1: 0, mck2ui 16
7417 20:14:44.389383 best dqsien dly found for B1: ( 1, 1, 4)
7418 20:14:44.393036 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7419 20:14:44.396600 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7420 20:14:44.397235
7421 20:14:44.398651 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7422 20:14:44.402387 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7423 20:14:44.405358 [Gating] SW calibration Done
7424 20:14:44.405944 ==
7425 20:14:44.409921 Dram Type= 6, Freq= 0, CH_0, rank 0
7426 20:14:44.412197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7427 20:14:44.412666 ==
7428 20:14:44.415578 RX Vref Scan: 0
7429 20:14:44.416139
7430 20:14:44.416510 RX Vref 0 -> 0, step: 1
7431 20:14:44.416892
7432 20:14:44.418770 RX Delay 0 -> 252, step: 8
7433 20:14:44.421930 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7434 20:14:44.428384 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7435 20:14:44.432410 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7436 20:14:44.435168 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7437 20:14:44.440192 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7438 20:14:44.442070 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7439 20:14:44.448187 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7440 20:14:44.451884 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7441 20:14:44.455222 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7442 20:14:44.459922 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7443 20:14:44.461485 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7444 20:14:44.468919 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7445 20:14:44.471712 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7446 20:14:44.475945 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7447 20:14:44.478666 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7448 20:14:44.481619 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7449 20:14:44.485601 ==
7450 20:14:44.488438 Dram Type= 6, Freq= 0, CH_0, rank 0
7451 20:14:44.491625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7452 20:14:44.492186 ==
7453 20:14:44.492557 DQS Delay:
7454 20:14:44.496447 DQS0 = 0, DQS1 = 0
7455 20:14:44.497064 DQM Delay:
7456 20:14:44.498296 DQM0 = 130, DQM1 = 124
7457 20:14:44.498761 DQ Delay:
7458 20:14:44.501435 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7459 20:14:44.504967 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7460 20:14:44.508502 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7461 20:14:44.511260 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7462 20:14:44.511761
7463 20:14:44.512132
7464 20:14:44.512470 ==
7465 20:14:44.514721 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 20:14:44.521336 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7467 20:14:44.521902 ==
7468 20:14:44.522484
7469 20:14:44.522867
7470 20:14:44.523206 TX Vref Scan disable
7471 20:14:44.525624 == TX Byte 0 ==
7472 20:14:44.529120 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7473 20:14:44.534596 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7474 20:14:44.535215 == TX Byte 1 ==
7475 20:14:44.538637 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7476 20:14:44.544699 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7477 20:14:44.545206 ==
7478 20:14:44.548905 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 20:14:44.551568 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7480 20:14:44.552091 ==
7481 20:14:44.564415
7482 20:14:44.567934 TX Vref early break, caculate TX vref
7483 20:14:44.570723 TX Vref=16, minBit 8, minWin=20, winSum=366
7484 20:14:44.574066 TX Vref=18, minBit 9, minWin=22, winSum=379
7485 20:14:44.577026 TX Vref=20, minBit 8, minWin=22, winSum=386
7486 20:14:44.580810 TX Vref=22, minBit 8, minWin=23, winSum=396
7487 20:14:44.584002 TX Vref=24, minBit 9, minWin=24, winSum=408
7488 20:14:44.591036 TX Vref=26, minBit 10, minWin=24, winSum=412
7489 20:14:44.593895 TX Vref=28, minBit 0, minWin=25, winSum=411
7490 20:14:44.597440 TX Vref=30, minBit 1, minWin=24, winSum=404
7491 20:14:44.601369 TX Vref=32, minBit 6, minWin=24, winSum=399
7492 20:14:44.604310 TX Vref=34, minBit 8, minWin=23, winSum=389
7493 20:14:44.610421 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
7494 20:14:44.611012
7495 20:14:44.614465 Final TX Range 0 Vref 28
7496 20:14:44.615026
7497 20:14:44.615395 ==
7498 20:14:44.617886 Dram Type= 6, Freq= 0, CH_0, rank 0
7499 20:14:44.620863 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7500 20:14:44.621426 ==
7501 20:14:44.621794
7502 20:14:44.622135
7503 20:14:44.623820 TX Vref Scan disable
7504 20:14:44.630553 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7505 20:14:44.631117 == TX Byte 0 ==
7506 20:14:44.633661 u2DelayCellOfst[0]=14 cells (4 PI)
7507 20:14:44.636887 u2DelayCellOfst[1]=17 cells (5 PI)
7508 20:14:44.640480 u2DelayCellOfst[2]=14 cells (4 PI)
7509 20:14:44.643985 u2DelayCellOfst[3]=10 cells (3 PI)
7510 20:14:44.646962 u2DelayCellOfst[4]=7 cells (2 PI)
7511 20:14:44.650338 u2DelayCellOfst[5]=0 cells (0 PI)
7512 20:14:44.653906 u2DelayCellOfst[6]=17 cells (5 PI)
7513 20:14:44.656811 u2DelayCellOfst[7]=17 cells (5 PI)
7514 20:14:44.661357 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7515 20:14:44.665242 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7516 20:14:44.667163 == TX Byte 1 ==
7517 20:14:44.670812 u2DelayCellOfst[8]=3 cells (1 PI)
7518 20:14:44.671385 u2DelayCellOfst[9]=0 cells (0 PI)
7519 20:14:44.673595 u2DelayCellOfst[10]=10 cells (3 PI)
7520 20:14:44.676866 u2DelayCellOfst[11]=3 cells (1 PI)
7521 20:14:44.680175 u2DelayCellOfst[12]=17 cells (5 PI)
7522 20:14:44.683108 u2DelayCellOfst[13]=17 cells (5 PI)
7523 20:14:44.687485 u2DelayCellOfst[14]=17 cells (5 PI)
7524 20:14:44.689928 u2DelayCellOfst[15]=14 cells (4 PI)
7525 20:14:44.693561 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7526 20:14:44.699999 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7527 20:14:44.700561 DramC Write-DBI on
7528 20:14:44.700960 ==
7529 20:14:44.703457 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 20:14:44.710862 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7531 20:14:44.711436 ==
7532 20:14:44.711809
7533 20:14:44.712238
7534 20:14:44.712576 TX Vref Scan disable
7535 20:14:44.714121 == TX Byte 0 ==
7536 20:14:44.717443 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7537 20:14:44.720474 == TX Byte 1 ==
7538 20:14:44.723623 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7539 20:14:44.726778 DramC Write-DBI off
7540 20:14:44.727245
7541 20:14:44.727611 [DATLAT]
7542 20:14:44.727954 Freq=1600, CH0 RK0
7543 20:14:44.728287
7544 20:14:44.730165 DATLAT Default: 0xf
7545 20:14:44.733615 0, 0xFFFF, sum = 0
7546 20:14:44.734103 1, 0xFFFF, sum = 0
7547 20:14:44.736561 2, 0xFFFF, sum = 0
7548 20:14:44.737245 3, 0xFFFF, sum = 0
7549 20:14:44.740136 4, 0xFFFF, sum = 0
7550 20:14:44.740607 5, 0xFFFF, sum = 0
7551 20:14:44.743289 6, 0xFFFF, sum = 0
7552 20:14:44.743813 7, 0xFFFF, sum = 0
7553 20:14:44.747487 8, 0xFFFF, sum = 0
7554 20:14:44.748085 9, 0xFFFF, sum = 0
7555 20:14:44.750470 10, 0xFFFF, sum = 0
7556 20:14:44.751081 11, 0xFFFF, sum = 0
7557 20:14:44.753041 12, 0xFFF, sum = 0
7558 20:14:44.753543 13, 0x0, sum = 1
7559 20:14:44.756307 14, 0x0, sum = 2
7560 20:14:44.756962 15, 0x0, sum = 3
7561 20:14:44.760460 16, 0x0, sum = 4
7562 20:14:44.761097 best_step = 14
7563 20:14:44.761589
7564 20:14:44.762041 ==
7565 20:14:44.763327 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 20:14:44.769397 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7567 20:14:44.769879 ==
7568 20:14:44.770368 RX Vref Scan: 1
7569 20:14:44.770822
7570 20:14:44.772435 Set Vref Range= 24 -> 127
7571 20:14:44.772961
7572 20:14:44.779707 RX Vref 24 -> 127, step: 1
7573 20:14:44.780293
7574 20:14:44.780933 RX Delay 11 -> 252, step: 4
7575 20:14:44.781405
7576 20:14:44.781861 Set Vref, RX VrefLevel [Byte0]: 24
7577 20:14:44.782711 [Byte1]: 24
7578 20:14:44.786750
7579 20:14:44.787208 Set Vref, RX VrefLevel [Byte0]: 25
7580 20:14:44.790387 [Byte1]: 25
7581 20:14:44.794475
7582 20:14:44.795039 Set Vref, RX VrefLevel [Byte0]: 26
7583 20:14:44.798640 [Byte1]: 26
7584 20:14:44.802229
7585 20:14:44.802788 Set Vref, RX VrefLevel [Byte0]: 27
7586 20:14:44.805913 [Byte1]: 27
7587 20:14:44.809733
7588 20:14:44.810297 Set Vref, RX VrefLevel [Byte0]: 28
7589 20:14:44.813434 [Byte1]: 28
7590 20:14:44.818085
7591 20:14:44.818646 Set Vref, RX VrefLevel [Byte0]: 29
7592 20:14:44.821001 [Byte1]: 29
7593 20:14:44.825176
7594 20:14:44.825738 Set Vref, RX VrefLevel [Byte0]: 30
7595 20:14:44.828427 [Byte1]: 30
7596 20:14:44.832862
7597 20:14:44.833419 Set Vref, RX VrefLevel [Byte0]: 31
7598 20:14:44.836069 [Byte1]: 31
7599 20:14:44.840995
7600 20:14:44.841555 Set Vref, RX VrefLevel [Byte0]: 32
7601 20:14:44.843616 [Byte1]: 32
7602 20:14:44.848666
7603 20:14:44.849277 Set Vref, RX VrefLevel [Byte0]: 33
7604 20:14:44.851478 [Byte1]: 33
7605 20:14:44.855974
7606 20:14:44.856542 Set Vref, RX VrefLevel [Byte0]: 34
7607 20:14:44.858772 [Byte1]: 34
7608 20:14:44.863676
7609 20:14:44.864236 Set Vref, RX VrefLevel [Byte0]: 35
7610 20:14:44.866336 [Byte1]: 35
7611 20:14:44.870821
7612 20:14:44.871279 Set Vref, RX VrefLevel [Byte0]: 36
7613 20:14:44.874264 [Byte1]: 36
7614 20:14:44.878130
7615 20:14:44.878618 Set Vref, RX VrefLevel [Byte0]: 37
7616 20:14:44.881245 [Byte1]: 37
7617 20:14:44.886237
7618 20:14:44.886812 Set Vref, RX VrefLevel [Byte0]: 38
7619 20:14:44.889603 [Byte1]: 38
7620 20:14:44.893722
7621 20:14:44.894199 Set Vref, RX VrefLevel [Byte0]: 39
7622 20:14:44.896839 [Byte1]: 39
7623 20:14:44.901146
7624 20:14:44.901726 Set Vref, RX VrefLevel [Byte0]: 40
7625 20:14:44.904365 [Byte1]: 40
7626 20:14:44.909083
7627 20:14:44.909665 Set Vref, RX VrefLevel [Byte0]: 41
7628 20:14:44.912149 [Byte1]: 41
7629 20:14:44.916449
7630 20:14:44.917096 Set Vref, RX VrefLevel [Byte0]: 42
7631 20:14:44.920677 [Byte1]: 42
7632 20:14:44.924107
7633 20:14:44.924680 Set Vref, RX VrefLevel [Byte0]: 43
7634 20:14:44.927713 [Byte1]: 43
7635 20:14:44.932038
7636 20:14:44.932602 Set Vref, RX VrefLevel [Byte0]: 44
7637 20:14:44.934809 [Byte1]: 44
7638 20:14:44.938918
7639 20:14:44.939391 Set Vref, RX VrefLevel [Byte0]: 45
7640 20:14:44.942326 [Byte1]: 45
7641 20:14:44.947444
7642 20:14:44.948020 Set Vref, RX VrefLevel [Byte0]: 46
7643 20:14:44.950534 [Byte1]: 46
7644 20:14:44.954826
7645 20:14:44.955405 Set Vref, RX VrefLevel [Byte0]: 47
7646 20:14:44.958092 [Byte1]: 47
7647 20:14:44.962730
7648 20:14:44.963306 Set Vref, RX VrefLevel [Byte0]: 48
7649 20:14:44.965125 [Byte1]: 48
7650 20:14:44.969628
7651 20:14:44.970215 Set Vref, RX VrefLevel [Byte0]: 49
7652 20:14:44.973118 [Byte1]: 49
7653 20:14:44.977818
7654 20:14:44.978397 Set Vref, RX VrefLevel [Byte0]: 50
7655 20:14:44.980476 [Byte1]: 50
7656 20:14:44.984890
7657 20:14:44.985468 Set Vref, RX VrefLevel [Byte0]: 51
7658 20:14:44.988469 [Byte1]: 51
7659 20:14:44.992237
7660 20:14:44.992747 Set Vref, RX VrefLevel [Byte0]: 52
7661 20:14:44.995823 [Byte1]: 52
7662 20:14:44.999992
7663 20:14:45.000558 Set Vref, RX VrefLevel [Byte0]: 53
7664 20:14:45.004957 [Byte1]: 53
7665 20:14:45.008121
7666 20:14:45.008685 Set Vref, RX VrefLevel [Byte0]: 54
7667 20:14:45.011045 [Byte1]: 54
7668 20:14:45.015524
7669 20:14:45.015987 Set Vref, RX VrefLevel [Byte0]: 55
7670 20:14:45.019452 [Byte1]: 55
7671 20:14:45.023111
7672 20:14:45.023675 Set Vref, RX VrefLevel [Byte0]: 56
7673 20:14:45.026568 [Byte1]: 56
7674 20:14:45.030650
7675 20:14:45.031216 Set Vref, RX VrefLevel [Byte0]: 57
7676 20:14:45.034109 [Byte1]: 57
7677 20:14:45.037829
7678 20:14:45.038466 Set Vref, RX VrefLevel [Byte0]: 58
7679 20:14:45.041684 [Byte1]: 58
7680 20:14:45.046272
7681 20:14:45.046837 Set Vref, RX VrefLevel [Byte0]: 59
7682 20:14:45.049365 [Byte1]: 59
7683 20:14:45.053929
7684 20:14:45.054492 Set Vref, RX VrefLevel [Byte0]: 60
7685 20:14:45.056563 [Byte1]: 60
7686 20:14:45.061361
7687 20:14:45.061923 Set Vref, RX VrefLevel [Byte0]: 61
7688 20:14:45.064879 [Byte1]: 61
7689 20:14:45.069186
7690 20:14:45.069756 Set Vref, RX VrefLevel [Byte0]: 62
7691 20:14:45.072425 [Byte1]: 62
7692 20:14:45.076574
7693 20:14:45.077205 Set Vref, RX VrefLevel [Byte0]: 63
7694 20:14:45.079670 [Byte1]: 63
7695 20:14:45.083852
7696 20:14:45.084422 Set Vref, RX VrefLevel [Byte0]: 64
7697 20:14:45.087087 [Byte1]: 64
7698 20:14:45.091544
7699 20:14:45.092110 Set Vref, RX VrefLevel [Byte0]: 65
7700 20:14:45.094584 [Byte1]: 65
7701 20:14:45.099699
7702 20:14:45.100270 Set Vref, RX VrefLevel [Byte0]: 66
7703 20:14:45.102304 [Byte1]: 66
7704 20:14:45.106681
7705 20:14:45.107246 Set Vref, RX VrefLevel [Byte0]: 67
7706 20:14:45.109943 [Byte1]: 67
7707 20:14:45.114604
7708 20:14:45.115175 Set Vref, RX VrefLevel [Byte0]: 68
7709 20:14:45.118308 [Byte1]: 68
7710 20:14:45.123894
7711 20:14:45.124684 Set Vref, RX VrefLevel [Byte0]: 69
7712 20:14:45.127156 [Byte1]: 69
7713 20:14:45.129400
7714 20:14:45.129863 Set Vref, RX VrefLevel [Byte0]: 70
7715 20:14:45.133711 [Byte1]: 70
7716 20:14:45.136778
7717 20:14:45.137484 Set Vref, RX VrefLevel [Byte0]: 71
7718 20:14:45.140786 [Byte1]: 71
7719 20:14:45.144365
7720 20:14:45.144871 Set Vref, RX VrefLevel [Byte0]: 72
7721 20:14:45.147665 [Byte1]: 72
7722 20:14:45.152780
7723 20:14:45.153202 Final RX Vref Byte 0 = 53 to rank0
7724 20:14:45.155976 Final RX Vref Byte 1 = 54 to rank0
7725 20:14:45.158895 Final RX Vref Byte 0 = 53 to rank1
7726 20:14:45.162580 Final RX Vref Byte 1 = 54 to rank1==
7727 20:14:45.166123 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 20:14:45.172114 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7729 20:14:45.172645 ==
7730 20:14:45.173036 DQS Delay:
7731 20:14:45.175883 DQS0 = 0, DQS1 = 0
7732 20:14:45.176418 DQM Delay:
7733 20:14:45.176804 DQM0 = 126, DQM1 = 121
7734 20:14:45.179066 DQ Delay:
7735 20:14:45.182069 DQ0 =124, DQ1 =126, DQ2 =124, DQ3 =122
7736 20:14:45.185310 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7737 20:14:45.189038 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7738 20:14:45.193153 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7739 20:14:45.193687
7740 20:14:45.194019
7741 20:14:45.194328
7742 20:14:45.196013 [DramC_TX_OE_Calibration] TA2
7743 20:14:45.198607 Original DQ_B0 (3 6) =30, OEN = 27
7744 20:14:45.201568 Original DQ_B1 (3 6) =30, OEN = 27
7745 20:14:45.205405 24, 0x0, End_B0=24 End_B1=24
7746 20:14:45.208769 25, 0x0, End_B0=25 End_B1=25
7747 20:14:45.209302 26, 0x0, End_B0=26 End_B1=26
7748 20:14:45.211488 27, 0x0, End_B0=27 End_B1=27
7749 20:14:45.214858 28, 0x0, End_B0=28 End_B1=28
7750 20:14:45.218674 29, 0x0, End_B0=29 End_B1=29
7751 20:14:45.219267 30, 0x0, End_B0=30 End_B1=30
7752 20:14:45.222684 31, 0x4141, End_B0=30 End_B1=30
7753 20:14:45.225108 Byte0 end_step=30 best_step=27
7754 20:14:45.227769 Byte1 end_step=30 best_step=27
7755 20:14:45.231738 Byte0 TX OE(2T, 0.5T) = (3, 3)
7756 20:14:45.235607 Byte1 TX OE(2T, 0.5T) = (3, 3)
7757 20:14:45.236029
7758 20:14:45.236361
7759 20:14:45.242549 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7760 20:14:45.244402 CH0 RK0: MR19=303, MR18=1C1C
7761 20:14:45.251178 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7762 20:14:45.251601
7763 20:14:45.254931 ----->DramcWriteLeveling(PI) begin...
7764 20:14:45.255462 ==
7765 20:14:45.257573 Dram Type= 6, Freq= 0, CH_0, rank 1
7766 20:14:45.260970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7767 20:14:45.261495 ==
7768 20:14:45.264685 Write leveling (Byte 0): 31 => 31
7769 20:14:45.268162 Write leveling (Byte 1): 28 => 28
7770 20:14:45.271209 DramcWriteLeveling(PI) end<-----
7771 20:14:45.271676
7772 20:14:45.272042 ==
7773 20:14:45.274476 Dram Type= 6, Freq= 0, CH_0, rank 1
7774 20:14:45.278493 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7775 20:14:45.281707 ==
7776 20:14:45.282281 [Gating] SW mode calibration
7777 20:14:45.287971 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7778 20:14:45.293912 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7779 20:14:45.297296 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7780 20:14:45.305733 0 12 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7781 20:14:45.308512 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7782 20:14:45.311372 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7783 20:14:45.318034 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7784 20:14:45.320763 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7785 20:14:45.324377 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7786 20:14:45.330996 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7787 20:14:45.334152 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
7788 20:14:45.337478 0 13 4 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
7789 20:14:45.343617 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7790 20:14:45.347812 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7791 20:14:45.350466 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7792 20:14:45.357108 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7793 20:14:45.360379 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 20:14:45.363949 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7795 20:14:45.370544 0 14 0 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
7796 20:14:45.373422 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7797 20:14:45.377338 0 14 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7798 20:14:45.383610 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7799 20:14:45.386930 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7800 20:14:45.390012 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 20:14:45.396954 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 20:14:45.400426 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7803 20:14:45.403612 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7804 20:14:45.409705 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7805 20:14:45.413162 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7806 20:14:45.416746 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 20:14:45.423777 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 20:14:45.426703 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 20:14:45.429451 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 20:14:45.436158 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 20:14:45.439862 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 20:14:45.442755 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 20:14:45.449870 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 20:14:45.452628 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 20:14:45.456562 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 20:14:45.462639 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 20:14:45.465932 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 20:14:45.468909 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7819 20:14:45.475628 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7820 20:14:45.479389 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7821 20:14:45.483059 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7822 20:14:45.486362 Total UI for P1: 0, mck2ui 16
7823 20:14:45.489371 best dqsien dly found for B0: ( 1, 1, 0)
7824 20:14:45.492560 Total UI for P1: 0, mck2ui 16
7825 20:14:45.495653 best dqsien dly found for B1: ( 1, 1, 2)
7826 20:14:45.499210 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7827 20:14:45.502205 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7828 20:14:45.502695
7829 20:14:45.506328 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7830 20:14:45.512294 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7831 20:14:45.512925 [Gating] SW calibration Done
7832 20:14:45.513309 ==
7833 20:14:45.515910 Dram Type= 6, Freq= 0, CH_0, rank 1
7834 20:14:45.522273 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7835 20:14:45.522837 ==
7836 20:14:45.523207 RX Vref Scan: 0
7837 20:14:45.523553
7838 20:14:45.525286 RX Vref 0 -> 0, step: 1
7839 20:14:45.525755
7840 20:14:45.528796 RX Delay 0 -> 252, step: 8
7841 20:14:45.534318 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7842 20:14:45.535281 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7843 20:14:45.539005 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7844 20:14:45.545222 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7845 20:14:45.548535 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7846 20:14:45.552320 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7847 20:14:45.554962 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7848 20:14:45.558192 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7849 20:14:45.564894 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7850 20:14:45.568513 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7851 20:14:45.571829 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7852 20:14:45.575151 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7853 20:14:45.578648 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7854 20:14:45.585324 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7855 20:14:45.588314 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7856 20:14:45.591517 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7857 20:14:45.592091 ==
7858 20:14:45.594504 Dram Type= 6, Freq= 0, CH_0, rank 1
7859 20:14:45.598293 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7860 20:14:45.601609 ==
7861 20:14:45.602172 DQS Delay:
7862 20:14:45.602545 DQS0 = 0, DQS1 = 0
7863 20:14:45.604616 DQM Delay:
7864 20:14:45.605134 DQM0 = 131, DQM1 = 124
7865 20:14:45.607981 DQ Delay:
7866 20:14:45.611351 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7867 20:14:45.614780 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7868 20:14:45.617804 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7869 20:14:45.621676 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7870 20:14:45.622237
7871 20:14:45.622603
7872 20:14:45.622944 ==
7873 20:14:45.625187 Dram Type= 6, Freq= 0, CH_0, rank 1
7874 20:14:45.627847 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7875 20:14:45.628316 ==
7876 20:14:45.631473
7877 20:14:45.632033
7878 20:14:45.632400 TX Vref Scan disable
7879 20:14:45.634455 == TX Byte 0 ==
7880 20:14:45.637585 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7881 20:14:45.640746 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7882 20:14:45.644647 == TX Byte 1 ==
7883 20:14:45.648059 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7884 20:14:45.650547 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7885 20:14:45.651011 ==
7886 20:14:45.655369 Dram Type= 6, Freq= 0, CH_0, rank 1
7887 20:14:45.660615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7888 20:14:45.661260 ==
7889 20:14:45.673340
7890 20:14:45.676458 TX Vref early break, caculate TX vref
7891 20:14:45.680683 TX Vref=16, minBit 9, minWin=22, winSum=381
7892 20:14:45.682422 TX Vref=18, minBit 7, minWin=23, winSum=394
7893 20:14:45.685454 TX Vref=20, minBit 7, minWin=23, winSum=395
7894 20:14:45.689466 TX Vref=22, minBit 7, minWin=24, winSum=403
7895 20:14:45.692619 TX Vref=24, minBit 8, minWin=24, winSum=409
7896 20:14:45.699252 TX Vref=26, minBit 7, minWin=25, winSum=421
7897 20:14:45.702507 TX Vref=28, minBit 1, minWin=25, winSum=420
7898 20:14:45.706060 TX Vref=30, minBit 0, minWin=25, winSum=414
7899 20:14:45.709122 TX Vref=32, minBit 8, minWin=23, winSum=407
7900 20:14:45.712757 TX Vref=34, minBit 8, minWin=23, winSum=398
7901 20:14:45.719207 [TxChooseVref] Worse bit 7, Min win 25, Win sum 421, Final Vref 26
7902 20:14:45.719773
7903 20:14:45.723097 Final TX Range 0 Vref 26
7904 20:14:45.723660
7905 20:14:45.724028 ==
7906 20:14:45.725742 Dram Type= 6, Freq= 0, CH_0, rank 1
7907 20:14:45.728449 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7908 20:14:45.728960 ==
7909 20:14:45.729326
7910 20:14:45.729663
7911 20:14:45.732466 TX Vref Scan disable
7912 20:14:45.738763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7913 20:14:45.739229 == TX Byte 0 ==
7914 20:14:45.742471 u2DelayCellOfst[0]=10 cells (3 PI)
7915 20:14:45.745439 u2DelayCellOfst[1]=14 cells (4 PI)
7916 20:14:45.749820 u2DelayCellOfst[2]=10 cells (3 PI)
7917 20:14:45.752097 u2DelayCellOfst[3]=10 cells (3 PI)
7918 20:14:45.755111 u2DelayCellOfst[4]=7 cells (2 PI)
7919 20:14:45.758194 u2DelayCellOfst[5]=0 cells (0 PI)
7920 20:14:45.761777 u2DelayCellOfst[6]=17 cells (5 PI)
7921 20:14:45.765191 u2DelayCellOfst[7]=14 cells (4 PI)
7922 20:14:45.768271 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7923 20:14:45.772405 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7924 20:14:45.774967 == TX Byte 1 ==
7925 20:14:45.778898 u2DelayCellOfst[8]=3 cells (1 PI)
7926 20:14:45.779364 u2DelayCellOfst[9]=0 cells (0 PI)
7927 20:14:45.781722 u2DelayCellOfst[10]=10 cells (3 PI)
7928 20:14:45.785103 u2DelayCellOfst[11]=7 cells (2 PI)
7929 20:14:45.789912 u2DelayCellOfst[12]=14 cells (4 PI)
7930 20:14:45.792283 u2DelayCellOfst[13]=14 cells (4 PI)
7931 20:14:45.795189 u2DelayCellOfst[14]=21 cells (6 PI)
7932 20:14:45.798571 u2DelayCellOfst[15]=14 cells (4 PI)
7933 20:14:45.802150 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7934 20:14:45.808301 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7935 20:14:45.808932 DramC Write-DBI on
7936 20:14:45.809315 ==
7937 20:14:45.811485 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 20:14:45.818471 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7939 20:14:45.819037 ==
7940 20:14:45.819413
7941 20:14:45.819750
7942 20:14:45.820078 TX Vref Scan disable
7943 20:14:45.822033 == TX Byte 0 ==
7944 20:14:45.825354 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7945 20:14:45.828750 == TX Byte 1 ==
7946 20:14:45.832005 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7947 20:14:45.835688 DramC Write-DBI off
7948 20:14:45.836274
7949 20:14:45.836646 [DATLAT]
7950 20:14:45.837119 Freq=1600, CH0 RK1
7951 20:14:45.837467
7952 20:14:45.838646 DATLAT Default: 0xe
7953 20:14:45.839108 0, 0xFFFF, sum = 0
7954 20:14:45.842100 1, 0xFFFF, sum = 0
7955 20:14:45.846717 2, 0xFFFF, sum = 0
7956 20:14:45.847285 3, 0xFFFF, sum = 0
7957 20:14:45.848921 4, 0xFFFF, sum = 0
7958 20:14:45.849393 5, 0xFFFF, sum = 0
7959 20:14:45.852144 6, 0xFFFF, sum = 0
7960 20:14:45.852755 7, 0xFFFF, sum = 0
7961 20:14:45.855067 8, 0xFFFF, sum = 0
7962 20:14:45.855540 9, 0xFFFF, sum = 0
7963 20:14:45.858723 10, 0xFFFF, sum = 0
7964 20:14:45.859294 11, 0xFFFF, sum = 0
7965 20:14:45.861790 12, 0x8FFF, sum = 0
7966 20:14:45.862263 13, 0x0, sum = 1
7967 20:14:45.865536 14, 0x0, sum = 2
7968 20:14:45.866009 15, 0x0, sum = 3
7969 20:14:45.868473 16, 0x0, sum = 4
7970 20:14:45.868983 best_step = 14
7971 20:14:45.869351
7972 20:14:45.869688 ==
7973 20:14:45.871453 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 20:14:45.879254 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7975 20:14:45.879817 ==
7976 20:14:45.880188 RX Vref Scan: 0
7977 20:14:45.880534
7978 20:14:45.881424 RX Vref 0 -> 0, step: 1
7979 20:14:45.881828
7980 20:14:45.885044 RX Delay 11 -> 252, step: 4
7981 20:14:45.888042 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7982 20:14:45.891681 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7983 20:14:45.894727 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7984 20:14:45.901686 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7985 20:14:45.904894 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7986 20:14:45.908511 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7987 20:14:45.911560 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7988 20:14:45.914492 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7989 20:14:45.921689 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7990 20:14:45.924458 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7991 20:14:45.927383 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7992 20:14:45.930781 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7993 20:14:45.937449 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7994 20:14:45.941500 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7995 20:14:45.944312 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7996 20:14:45.947757 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7997 20:14:45.948180 ==
7998 20:14:45.951087 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 20:14:45.957379 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8000 20:14:45.957957 ==
8001 20:14:45.958331 DQS Delay:
8002 20:14:45.961669 DQS0 = 0, DQS1 = 0
8003 20:14:45.962231 DQM Delay:
8004 20:14:45.962607 DQM0 = 128, DQM1 = 120
8005 20:14:45.963870 DQ Delay:
8006 20:14:45.967278 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8007 20:14:45.970165 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8008 20:14:45.973824 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8009 20:14:45.977339 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8010 20:14:45.977904
8011 20:14:45.978276
8012 20:14:45.978617
8013 20:14:45.980508 [DramC_TX_OE_Calibration] TA2
8014 20:14:45.983894 Original DQ_B0 (3 6) =30, OEN = 27
8015 20:14:45.987713 Original DQ_B1 (3 6) =30, OEN = 27
8016 20:14:45.990649 24, 0x0, End_B0=24 End_B1=24
8017 20:14:45.993234 25, 0x0, End_B0=25 End_B1=25
8018 20:14:45.993708 26, 0x0, End_B0=26 End_B1=26
8019 20:14:45.996808 27, 0x0, End_B0=27 End_B1=27
8020 20:14:46.000106 28, 0x0, End_B0=28 End_B1=28
8021 20:14:46.003490 29, 0x0, End_B0=29 End_B1=29
8022 20:14:46.004060 30, 0x0, End_B0=30 End_B1=30
8023 20:14:46.007212 31, 0x4141, End_B0=30 End_B1=30
8024 20:14:46.010172 Byte0 end_step=30 best_step=27
8025 20:14:46.013144 Byte1 end_step=30 best_step=27
8026 20:14:46.017302 Byte0 TX OE(2T, 0.5T) = (3, 3)
8027 20:14:46.020194 Byte1 TX OE(2T, 0.5T) = (3, 3)
8028 20:14:46.020801
8029 20:14:46.021177
8030 20:14:46.026805 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8031 20:14:46.029914 CH0 RK1: MR19=303, MR18=2424
8032 20:14:46.036388 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8033 20:14:46.039399 [RxdqsGatingPostProcess] freq 1600
8034 20:14:46.042980 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8035 20:14:46.046102 Pre-setting of DQS Precalculation
8036 20:14:46.052952 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8037 20:14:46.053500 ==
8038 20:14:46.056894 Dram Type= 6, Freq= 0, CH_1, rank 0
8039 20:14:46.059535 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8040 20:14:46.060177 ==
8041 20:14:46.066935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8042 20:14:46.069478 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8043 20:14:46.072583 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8044 20:14:46.079979 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8045 20:14:46.088649 [CA 0] Center 41 (11~72) winsize 62
8046 20:14:46.091668 [CA 1] Center 41 (11~72) winsize 62
8047 20:14:46.094499 [CA 2] Center 37 (8~67) winsize 60
8048 20:14:46.098451 [CA 3] Center 36 (7~66) winsize 60
8049 20:14:46.101304 [CA 4] Center 34 (4~64) winsize 61
8050 20:14:46.105342 [CA 5] Center 34 (4~64) winsize 61
8051 20:14:46.105909
8052 20:14:46.108666 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8053 20:14:46.109281
8054 20:14:46.111913 [CATrainingPosCal] consider 1 rank data
8055 20:14:46.115791 u2DelayCellTimex100 = 275/100 ps
8056 20:14:46.121380 CA0 delay=41 (11~72),Diff = 7 PI (24 cell)
8057 20:14:46.124437 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8058 20:14:46.127633 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8059 20:14:46.131331 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8060 20:14:46.135146 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8061 20:14:46.137731 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8062 20:14:46.138201
8063 20:14:46.141336 CA PerBit enable=1, Macro0, CA PI delay=34
8064 20:14:46.141914
8065 20:14:46.144676 [CBTSetCACLKResult] CA Dly = 34
8066 20:14:46.148483 CS Dly: 8 (0~39)
8067 20:14:46.150890 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8068 20:14:46.154389 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8069 20:14:46.154952 ==
8070 20:14:46.157701 Dram Type= 6, Freq= 0, CH_1, rank 1
8071 20:14:46.161423 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8072 20:14:46.165425 ==
8073 20:14:46.167462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8074 20:14:46.171172 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8075 20:14:46.177483 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8076 20:14:46.185361 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8077 20:14:46.190614 [CA 0] Center 40 (10~70) winsize 61
8078 20:14:46.194041 [CA 1] Center 39 (9~70) winsize 62
8079 20:14:46.197453 [CA 2] Center 35 (6~65) winsize 60
8080 20:14:46.200941 [CA 3] Center 35 (5~65) winsize 61
8081 20:14:46.204093 [CA 4] Center 32 (3~62) winsize 60
8082 20:14:46.207217 [CA 5] Center 33 (4~63) winsize 60
8083 20:14:46.207719
8084 20:14:46.210524 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8085 20:14:46.211099
8086 20:14:46.213927 [CATrainingPosCal] consider 2 rank data
8087 20:14:46.217184 u2DelayCellTimex100 = 275/100 ps
8088 20:14:46.220744 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8089 20:14:46.226729 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8090 20:14:46.231002 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8091 20:14:46.233684 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8092 20:14:46.237587 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8093 20:14:46.240509 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8094 20:14:46.241117
8095 20:14:46.243592 CA PerBit enable=1, Macro0, CA PI delay=33
8096 20:14:46.244077
8097 20:14:46.246738 [CBTSetCACLKResult] CA Dly = 33
8098 20:14:46.250525 CS Dly: 9 (0~41)
8099 20:14:46.253743 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8100 20:14:46.256985 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8101 20:14:46.257515
8102 20:14:46.259980 ----->DramcWriteLeveling(PI) begin...
8103 20:14:46.260473 ==
8104 20:14:46.262965 Dram Type= 6, Freq= 0, CH_1, rank 0
8105 20:14:46.270329 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8106 20:14:46.270799 ==
8107 20:14:46.273717 Write leveling (Byte 0): 21 => 21
8108 20:14:46.274187 Write leveling (Byte 1): 21 => 21
8109 20:14:46.277264 DramcWriteLeveling(PI) end<-----
8110 20:14:46.277687
8111 20:14:46.279871 ==
8112 20:14:46.280341 Dram Type= 6, Freq= 0, CH_1, rank 0
8113 20:14:46.286414 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8114 20:14:46.286925 ==
8115 20:14:46.289472 [Gating] SW mode calibration
8116 20:14:46.297081 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8117 20:14:46.299720 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8118 20:14:46.306879 0 12 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
8119 20:14:46.309635 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 20:14:46.313391 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 20:14:46.319805 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 20:14:46.323478 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 20:14:46.326128 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 20:14:46.333674 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8125 20:14:46.336200 0 12 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8126 20:14:46.339765 0 13 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8127 20:14:46.346142 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8128 20:14:46.349572 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 20:14:46.353380 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 20:14:46.360231 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 20:14:46.362780 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 20:14:46.366469 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 20:14:46.372201 0 13 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8134 20:14:46.375735 0 14 0 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
8135 20:14:46.379161 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8136 20:14:46.385576 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 20:14:46.389177 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 20:14:46.392806 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 20:14:46.399108 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 20:14:46.403134 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 20:14:46.405927 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8142 20:14:46.412311 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8143 20:14:46.415853 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8144 20:14:46.418923 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 20:14:46.426170 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 20:14:46.428987 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 20:14:46.432486 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 20:14:46.437669 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 20:14:46.442616 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 20:14:46.445322 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 20:14:46.448991 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 20:14:46.455580 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 20:14:46.459453 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 20:14:46.462579 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 20:14:46.468606 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 20:14:46.471791 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8157 20:14:46.475214 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8158 20:14:46.482597 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8159 20:14:46.485456 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8160 20:14:46.488232 Total UI for P1: 0, mck2ui 16
8161 20:14:46.491679 best dqsien dly found for B0: ( 1, 0, 28)
8162 20:14:46.495257 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8163 20:14:46.498210 Total UI for P1: 0, mck2ui 16
8164 20:14:46.502264 best dqsien dly found for B1: ( 1, 1, 4)
8165 20:14:46.504894 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8166 20:14:46.508552 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8167 20:14:46.511495
8168 20:14:46.515162 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8169 20:14:46.518337 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8170 20:14:46.522428 [Gating] SW calibration Done
8171 20:14:46.522991 ==
8172 20:14:46.524475 Dram Type= 6, Freq= 0, CH_1, rank 0
8173 20:14:46.527756 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8174 20:14:46.528325 ==
8175 20:14:46.531155 RX Vref Scan: 0
8176 20:14:46.531625
8177 20:14:46.531994 RX Vref 0 -> 0, step: 1
8178 20:14:46.532340
8179 20:14:46.534264 RX Delay 0 -> 252, step: 8
8180 20:14:46.538224 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8181 20:14:46.541994 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8182 20:14:46.547470 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8183 20:14:46.550903 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8184 20:14:46.554174 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8185 20:14:46.557871 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8186 20:14:46.561067 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8187 20:14:46.568118 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8188 20:14:46.571495 iDelay=200, Bit 8, Center 107 (56 ~ 159) 104
8189 20:14:46.573895 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8190 20:14:46.577675 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8191 20:14:46.584134 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8192 20:14:46.587553 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8193 20:14:46.590231 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8194 20:14:46.593849 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8195 20:14:46.597072 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8196 20:14:46.601696 ==
8197 20:14:46.603236 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 20:14:46.607047 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 20:14:46.607614 ==
8200 20:14:46.607989 DQS Delay:
8201 20:14:46.610173 DQS0 = 0, DQS1 = 0
8202 20:14:46.610644 DQM Delay:
8203 20:14:46.613222 DQM0 = 129, DQM1 = 126
8204 20:14:46.613693 DQ Delay:
8205 20:14:46.616802 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8206 20:14:46.620590 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8207 20:14:46.624052 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8208 20:14:46.627573 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8209 20:14:46.628048
8210 20:14:46.628419
8211 20:14:46.628833 ==
8212 20:14:46.630796 Dram Type= 6, Freq= 0, CH_1, rank 0
8213 20:14:46.637005 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8214 20:14:46.637668 ==
8215 20:14:46.638054
8216 20:14:46.638399
8217 20:14:46.639892 TX Vref Scan disable
8218 20:14:46.640363 == TX Byte 0 ==
8219 20:14:46.643686 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8220 20:14:46.650187 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8221 20:14:46.650675 == TX Byte 1 ==
8222 20:14:46.652967 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8223 20:14:46.659855 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8224 20:14:46.660421 ==
8225 20:14:46.663705 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 20:14:46.666103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8227 20:14:46.666576 ==
8228 20:14:46.678584
8229 20:14:46.682172 TX Vref early break, caculate TX vref
8230 20:14:46.685569 TX Vref=16, minBit 1, minWin=21, winSum=368
8231 20:14:46.688929 TX Vref=18, minBit 0, minWin=22, winSum=374
8232 20:14:46.691881 TX Vref=20, minBit 3, minWin=22, winSum=388
8233 20:14:46.695729 TX Vref=22, minBit 3, minWin=23, winSum=393
8234 20:14:46.698793 TX Vref=24, minBit 3, minWin=23, winSum=402
8235 20:14:46.705234 TX Vref=26, minBit 0, minWin=25, winSum=414
8236 20:14:46.709556 TX Vref=28, minBit 3, minWin=24, winSum=413
8237 20:14:46.711895 TX Vref=30, minBit 1, minWin=24, winSum=405
8238 20:14:46.715407 TX Vref=32, minBit 3, minWin=23, winSum=398
8239 20:14:46.718400 TX Vref=34, minBit 3, minWin=22, winSum=388
8240 20:14:46.725163 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8241 20:14:46.725730
8242 20:14:46.728378 Final TX Range 0 Vref 26
8243 20:14:46.729203
8244 20:14:46.729600 ==
8245 20:14:46.732682 Dram Type= 6, Freq= 0, CH_1, rank 0
8246 20:14:46.735127 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8247 20:14:46.735694 ==
8248 20:14:46.736068
8249 20:14:46.736408
8250 20:14:46.738453 TX Vref Scan disable
8251 20:14:46.745195 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8252 20:14:46.745760 == TX Byte 0 ==
8253 20:14:46.749070 u2DelayCellOfst[0]=17 cells (5 PI)
8254 20:14:46.751793 u2DelayCellOfst[1]=10 cells (3 PI)
8255 20:14:46.755912 u2DelayCellOfst[2]=0 cells (0 PI)
8256 20:14:46.758327 u2DelayCellOfst[3]=7 cells (2 PI)
8257 20:14:46.761245 u2DelayCellOfst[4]=10 cells (3 PI)
8258 20:14:46.764902 u2DelayCellOfst[5]=17 cells (5 PI)
8259 20:14:46.769132 u2DelayCellOfst[6]=17 cells (5 PI)
8260 20:14:46.771835 u2DelayCellOfst[7]=7 cells (2 PI)
8261 20:14:46.774513 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8262 20:14:46.778236 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8263 20:14:46.781168 == TX Byte 1 ==
8264 20:14:46.781640 u2DelayCellOfst[8]=0 cells (0 PI)
8265 20:14:46.784651 u2DelayCellOfst[9]=3 cells (1 PI)
8266 20:14:46.787929 u2DelayCellOfst[10]=7 cells (2 PI)
8267 20:14:46.791548 u2DelayCellOfst[11]=0 cells (0 PI)
8268 20:14:46.795039 u2DelayCellOfst[12]=14 cells (4 PI)
8269 20:14:46.798096 u2DelayCellOfst[13]=17 cells (5 PI)
8270 20:14:46.801918 u2DelayCellOfst[14]=17 cells (5 PI)
8271 20:14:46.804540 u2DelayCellOfst[15]=14 cells (4 PI)
8272 20:14:46.807956 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8273 20:14:46.814485 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8274 20:14:46.815047 DramC Write-DBI on
8275 20:14:46.815421 ==
8276 20:14:46.817979 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 20:14:46.821569 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8278 20:14:46.824433 ==
8279 20:14:46.825039
8280 20:14:46.825416
8281 20:14:46.825761 TX Vref Scan disable
8282 20:14:46.827801 == TX Byte 0 ==
8283 20:14:46.830992 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8284 20:14:46.834640 == TX Byte 1 ==
8285 20:14:46.837892 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8286 20:14:46.841388 DramC Write-DBI off
8287 20:14:46.841868
8288 20:14:46.842237 [DATLAT]
8289 20:14:46.842577 Freq=1600, CH1 RK0
8290 20:14:46.842910
8291 20:14:46.844775 DATLAT Default: 0xf
8292 20:14:46.845243 0, 0xFFFF, sum = 0
8293 20:14:46.847779 1, 0xFFFF, sum = 0
8294 20:14:46.850710 2, 0xFFFF, sum = 0
8295 20:14:46.851180 3, 0xFFFF, sum = 0
8296 20:14:46.855214 4, 0xFFFF, sum = 0
8297 20:14:46.855785 5, 0xFFFF, sum = 0
8298 20:14:46.857689 6, 0xFFFF, sum = 0
8299 20:14:46.858162 7, 0xFFFF, sum = 0
8300 20:14:46.861680 8, 0xFFFF, sum = 0
8301 20:14:46.862252 9, 0xFFFF, sum = 0
8302 20:14:46.864329 10, 0xFFFF, sum = 0
8303 20:14:46.864841 11, 0xFFFF, sum = 0
8304 20:14:46.867619 12, 0xFFF, sum = 0
8305 20:14:46.868188 13, 0x0, sum = 1
8306 20:14:46.871201 14, 0x0, sum = 2
8307 20:14:46.871794 15, 0x0, sum = 3
8308 20:14:46.874442 16, 0x0, sum = 4
8309 20:14:46.874917 best_step = 14
8310 20:14:46.875285
8311 20:14:46.875631 ==
8312 20:14:46.877302 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 20:14:46.881098 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8314 20:14:46.883855 ==
8315 20:14:46.884277 RX Vref Scan: 1
8316 20:14:46.884614
8317 20:14:46.887226 Set Vref Range= 24 -> 127
8318 20:14:46.887644
8319 20:14:46.890568 RX Vref 24 -> 127, step: 1
8320 20:14:46.891091
8321 20:14:46.891426 RX Delay 11 -> 252, step: 4
8322 20:14:46.891739
8323 20:14:46.893993 Set Vref, RX VrefLevel [Byte0]: 24
8324 20:14:46.896960 [Byte1]: 24
8325 20:14:46.901367
8326 20:14:46.901785 Set Vref, RX VrefLevel [Byte0]: 25
8327 20:14:46.904408 [Byte1]: 25
8328 20:14:46.909433
8329 20:14:46.909949 Set Vref, RX VrefLevel [Byte0]: 26
8330 20:14:46.911928 [Byte1]: 26
8331 20:14:46.916142
8332 20:14:46.916575 Set Vref, RX VrefLevel [Byte0]: 27
8333 20:14:46.919521 [Byte1]: 27
8334 20:14:46.923993
8335 20:14:46.924513 Set Vref, RX VrefLevel [Byte0]: 28
8336 20:14:46.927547 [Byte1]: 28
8337 20:14:46.931346
8338 20:14:46.931771 Set Vref, RX VrefLevel [Byte0]: 29
8339 20:14:46.935163 [Byte1]: 29
8340 20:14:46.939163
8341 20:14:46.939629 Set Vref, RX VrefLevel [Byte0]: 30
8342 20:14:46.942150 [Byte1]: 30
8343 20:14:46.946909
8344 20:14:46.947623 Set Vref, RX VrefLevel [Byte0]: 31
8345 20:14:46.949821 [Byte1]: 31
8346 20:14:46.954399
8347 20:14:46.955005 Set Vref, RX VrefLevel [Byte0]: 32
8348 20:14:46.957325 [Byte1]: 32
8349 20:14:46.962543
8350 20:14:46.963099 Set Vref, RX VrefLevel [Byte0]: 33
8351 20:14:46.965231 [Byte1]: 33
8352 20:14:46.969707
8353 20:14:46.970268 Set Vref, RX VrefLevel [Byte0]: 34
8354 20:14:46.972802 [Byte1]: 34
8355 20:14:46.977554
8356 20:14:46.978114 Set Vref, RX VrefLevel [Byte0]: 35
8357 20:14:46.980897 [Byte1]: 35
8358 20:14:46.984905
8359 20:14:46.985375 Set Vref, RX VrefLevel [Byte0]: 36
8360 20:14:46.987987 [Byte1]: 36
8361 20:14:46.992905
8362 20:14:46.993394 Set Vref, RX VrefLevel [Byte0]: 37
8363 20:14:46.995770 [Byte1]: 37
8364 20:14:46.999731
8365 20:14:47.000152 Set Vref, RX VrefLevel [Byte0]: 38
8366 20:14:47.002999 [Byte1]: 38
8367 20:14:47.007990
8368 20:14:47.008538 Set Vref, RX VrefLevel [Byte0]: 39
8369 20:14:47.011031 [Byte1]: 39
8370 20:14:47.016084
8371 20:14:47.016601 Set Vref, RX VrefLevel [Byte0]: 40
8372 20:14:47.018456 [Byte1]: 40
8373 20:14:47.023018
8374 20:14:47.023546 Set Vref, RX VrefLevel [Byte0]: 41
8375 20:14:47.026071 [Byte1]: 41
8376 20:14:47.030873
8377 20:14:47.031293 Set Vref, RX VrefLevel [Byte0]: 42
8378 20:14:47.034187 [Byte1]: 42
8379 20:14:47.038864
8380 20:14:47.039284 Set Vref, RX VrefLevel [Byte0]: 43
8381 20:14:47.041401 [Byte1]: 43
8382 20:14:47.046689
8383 20:14:47.047196 Set Vref, RX VrefLevel [Byte0]: 44
8384 20:14:47.048954 [Byte1]: 44
8385 20:14:47.053279
8386 20:14:47.053700 Set Vref, RX VrefLevel [Byte0]: 45
8387 20:14:47.056684 [Byte1]: 45
8388 20:14:47.061572
8389 20:14:47.061990 Set Vref, RX VrefLevel [Byte0]: 46
8390 20:14:47.063957 [Byte1]: 46
8391 20:14:47.068483
8392 20:14:47.068951 Set Vref, RX VrefLevel [Byte0]: 47
8393 20:14:47.072033 [Byte1]: 47
8394 20:14:47.076336
8395 20:14:47.076794 Set Vref, RX VrefLevel [Byte0]: 48
8396 20:14:47.079725 [Byte1]: 48
8397 20:14:47.084078
8398 20:14:47.084603 Set Vref, RX VrefLevel [Byte0]: 49
8399 20:14:47.087586 [Byte1]: 49
8400 20:14:47.091463
8401 20:14:47.091974 Set Vref, RX VrefLevel [Byte0]: 50
8402 20:14:47.094879 [Byte1]: 50
8403 20:14:47.099068
8404 20:14:47.099584 Set Vref, RX VrefLevel [Byte0]: 51
8405 20:14:47.103932 [Byte1]: 51
8406 20:14:47.107327
8407 20:14:47.107839 Set Vref, RX VrefLevel [Byte0]: 52
8408 20:14:47.110871 [Byte1]: 52
8409 20:14:47.114246
8410 20:14:47.114769 Set Vref, RX VrefLevel [Byte0]: 53
8411 20:14:47.117600 [Byte1]: 53
8412 20:14:47.122126
8413 20:14:47.122641 Set Vref, RX VrefLevel [Byte0]: 54
8414 20:14:47.125347 [Byte1]: 54
8415 20:14:47.129530
8416 20:14:47.130048 Set Vref, RX VrefLevel [Byte0]: 55
8417 20:14:47.133395 [Byte1]: 55
8418 20:14:47.137614
8419 20:14:47.138127 Set Vref, RX VrefLevel [Byte0]: 56
8420 20:14:47.141167 [Byte1]: 56
8421 20:14:47.144891
8422 20:14:47.145402 Set Vref, RX VrefLevel [Byte0]: 57
8423 20:14:47.147957 [Byte1]: 57
8424 20:14:47.152308
8425 20:14:47.152768 Set Vref, RX VrefLevel [Byte0]: 58
8426 20:14:47.156052 [Byte1]: 58
8427 20:14:47.160422
8428 20:14:47.160988 Set Vref, RX VrefLevel [Byte0]: 59
8429 20:14:47.163342 [Byte1]: 59
8430 20:14:47.168643
8431 20:14:47.169198 Set Vref, RX VrefLevel [Byte0]: 60
8432 20:14:47.170727 [Byte1]: 60
8433 20:14:47.175228
8434 20:14:47.175745 Set Vref, RX VrefLevel [Byte0]: 61
8435 20:14:47.178614 [Byte1]: 61
8436 20:14:47.182866
8437 20:14:47.183377 Set Vref, RX VrefLevel [Byte0]: 62
8438 20:14:47.185630 [Byte1]: 62
8439 20:14:47.191315
8440 20:14:47.191834 Set Vref, RX VrefLevel [Byte0]: 63
8441 20:14:47.193799 [Byte1]: 63
8442 20:14:47.198568
8443 20:14:47.199085 Set Vref, RX VrefLevel [Byte0]: 64
8444 20:14:47.202270 [Byte1]: 64
8445 20:14:47.205724
8446 20:14:47.206246 Set Vref, RX VrefLevel [Byte0]: 65
8447 20:14:47.209001 [Byte1]: 65
8448 20:14:47.214213
8449 20:14:47.214724 Set Vref, RX VrefLevel [Byte0]: 66
8450 20:14:47.216690 [Byte1]: 66
8451 20:14:47.221598
8452 20:14:47.222112 Set Vref, RX VrefLevel [Byte0]: 67
8453 20:14:47.224678 [Byte1]: 67
8454 20:14:47.228310
8455 20:14:47.228877 Set Vref, RX VrefLevel [Byte0]: 68
8456 20:14:47.231833 [Byte1]: 68
8457 20:14:47.236451
8458 20:14:47.237013 Set Vref, RX VrefLevel [Byte0]: 69
8459 20:14:47.239214 [Byte1]: 69
8460 20:14:47.243906
8461 20:14:47.244424 Set Vref, RX VrefLevel [Byte0]: 70
8462 20:14:47.246712 [Byte1]: 70
8463 20:14:47.250804
8464 20:14:47.251225 Set Vref, RX VrefLevel [Byte0]: 71
8465 20:14:47.254264 [Byte1]: 71
8466 20:14:47.259767
8467 20:14:47.260262 Set Vref, RX VrefLevel [Byte0]: 72
8468 20:14:47.262078 [Byte1]: 72
8469 20:14:47.266442
8470 20:14:47.266961 Set Vref, RX VrefLevel [Byte0]: 73
8471 20:14:47.270444 [Byte1]: 73
8472 20:14:47.273641
8473 20:14:47.274081 Set Vref, RX VrefLevel [Byte0]: 74
8474 20:14:47.277301 [Byte1]: 74
8475 20:14:47.281293
8476 20:14:47.281712 Set Vref, RX VrefLevel [Byte0]: 75
8477 20:14:47.284652 [Byte1]: 75
8478 20:14:47.289713
8479 20:14:47.290225 Set Vref, RX VrefLevel [Byte0]: 76
8480 20:14:47.292129 [Byte1]: 76
8481 20:14:47.296763
8482 20:14:47.297290 Set Vref, RX VrefLevel [Byte0]: 77
8483 20:14:47.299973 [Byte1]: 77
8484 20:14:47.304583
8485 20:14:47.305061 Final RX Vref Byte 0 = 60 to rank0
8486 20:14:47.307990 Final RX Vref Byte 1 = 55 to rank0
8487 20:14:47.311889 Final RX Vref Byte 0 = 60 to rank1
8488 20:14:47.314321 Final RX Vref Byte 1 = 55 to rank1==
8489 20:14:47.317472 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 20:14:47.324273 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8491 20:14:47.324729 ==
8492 20:14:47.325085 DQS Delay:
8493 20:14:47.327757 DQS0 = 0, DQS1 = 0
8494 20:14:47.328182 DQM Delay:
8495 20:14:47.328517 DQM0 = 128, DQM1 = 124
8496 20:14:47.330701 DQ Delay:
8497 20:14:47.334469 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8498 20:14:47.337327 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8499 20:14:47.340539 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8500 20:14:47.344595 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8501 20:14:47.345219
8502 20:14:47.345568
8503 20:14:47.345882
8504 20:14:47.347862 [DramC_TX_OE_Calibration] TA2
8505 20:14:47.351472 Original DQ_B0 (3 6) =30, OEN = 27
8506 20:14:47.353864 Original DQ_B1 (3 6) =30, OEN = 27
8507 20:14:47.358064 24, 0x0, End_B0=24 End_B1=24
8508 20:14:47.358593 25, 0x0, End_B0=25 End_B1=25
8509 20:14:47.361394 26, 0x0, End_B0=26 End_B1=26
8510 20:14:47.364175 27, 0x0, End_B0=27 End_B1=27
8511 20:14:47.368211 28, 0x0, End_B0=28 End_B1=28
8512 20:14:47.371172 29, 0x0, End_B0=29 End_B1=29
8513 20:14:47.371700 30, 0x0, End_B0=30 End_B1=30
8514 20:14:47.374682 31, 0x4141, End_B0=30 End_B1=30
8515 20:14:47.376917 Byte0 end_step=30 best_step=27
8516 20:14:47.381046 Byte1 end_step=30 best_step=27
8517 20:14:47.383990 Byte0 TX OE(2T, 0.5T) = (3, 3)
8518 20:14:47.387249 Byte1 TX OE(2T, 0.5T) = (3, 3)
8519 20:14:47.387770
8520 20:14:47.388107
8521 20:14:47.393910 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8522 20:14:47.397459 CH1 RK0: MR19=303, MR18=2323
8523 20:14:47.403787 CH1_RK0: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8524 20:14:47.404314
8525 20:14:47.407796 ----->DramcWriteLeveling(PI) begin...
8526 20:14:47.408327 ==
8527 20:14:47.410299 Dram Type= 6, Freq= 0, CH_1, rank 1
8528 20:14:47.414476 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8529 20:14:47.415013 ==
8530 20:14:47.417270 Write leveling (Byte 0): 23 => 23
8531 20:14:47.420539 Write leveling (Byte 1): 22 => 22
8532 20:14:47.423793 DramcWriteLeveling(PI) end<-----
8533 20:14:47.424311
8534 20:14:47.424649 ==
8535 20:14:47.427023 Dram Type= 6, Freq= 0, CH_1, rank 1
8536 20:14:47.430147 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8537 20:14:47.433323 ==
8538 20:14:47.433751 [Gating] SW mode calibration
8539 20:14:47.440208 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8540 20:14:47.446727 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8541 20:14:47.450541 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8542 20:14:47.456657 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8543 20:14:47.460146 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8544 20:14:47.463499 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8545 20:14:47.469429 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8546 20:14:47.473699 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8547 20:14:47.476390 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8548 20:14:47.483615 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8549 20:14:47.486214 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8550 20:14:47.489404 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8551 20:14:47.496038 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8552 20:14:47.499448 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8553 20:14:47.502954 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8554 20:14:47.510030 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8555 20:14:47.512965 0 13 24 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
8556 20:14:47.516115 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8557 20:14:47.522334 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 20:14:47.525938 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8559 20:14:47.529664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8560 20:14:47.535750 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 20:14:47.541195 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8562 20:14:47.542836 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8563 20:14:47.549452 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8564 20:14:47.552641 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8565 20:14:47.555820 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 20:14:47.562503 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 20:14:47.566434 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 20:14:47.569147 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 20:14:47.572837 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 20:14:47.578586 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 20:14:47.582155 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 20:14:47.589199 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 20:14:47.592562 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 20:14:47.596894 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 20:14:47.599331 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 20:14:47.605697 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 20:14:47.609367 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 20:14:47.612828 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8579 20:14:47.618720 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8580 20:14:47.622385 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8581 20:14:47.625645 Total UI for P1: 0, mck2ui 16
8582 20:14:47.628376 best dqsien dly found for B0: ( 1, 0, 22)
8583 20:14:47.631737 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8584 20:14:47.635284 Total UI for P1: 0, mck2ui 16
8585 20:14:47.638359 best dqsien dly found for B1: ( 1, 0, 28)
8586 20:14:47.641622 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8587 20:14:47.649307 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8588 20:14:47.649858
8589 20:14:47.652369 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8590 20:14:47.654958 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8591 20:14:47.659033 [Gating] SW calibration Done
8592 20:14:47.659608 ==
8593 20:14:47.661357 Dram Type= 6, Freq= 0, CH_1, rank 1
8594 20:14:47.665122 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8595 20:14:47.665697 ==
8596 20:14:47.668207 RX Vref Scan: 0
8597 20:14:47.668671
8598 20:14:47.669102 RX Vref 0 -> 0, step: 1
8599 20:14:47.669447
8600 20:14:47.671464 RX Delay 0 -> 252, step: 8
8601 20:14:47.676322 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8602 20:14:47.678083 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8603 20:14:47.684815 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8604 20:14:47.687942 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8605 20:14:47.691147 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8606 20:14:47.694543 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8607 20:14:47.697962 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8608 20:14:47.705335 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8609 20:14:47.708412 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8610 20:14:47.711266 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8611 20:14:47.714532 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8612 20:14:47.717853 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8613 20:14:47.724893 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8614 20:14:47.728122 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8615 20:14:47.731050 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8616 20:14:47.734708 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8617 20:14:47.735277 ==
8618 20:14:47.738149 Dram Type= 6, Freq= 0, CH_1, rank 1
8619 20:14:47.744775 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8620 20:14:47.745353 ==
8621 20:14:47.745728 DQS Delay:
8622 20:14:47.748146 DQS0 = 0, DQS1 = 0
8623 20:14:47.748765 DQM Delay:
8624 20:14:47.751091 DQM0 = 132, DQM1 = 125
8625 20:14:47.751669 DQ Delay:
8626 20:14:47.754926 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8627 20:14:47.757462 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8628 20:14:47.761114 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8629 20:14:47.764024 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8630 20:14:47.764509
8631 20:14:47.764938
8632 20:14:47.765287 ==
8633 20:14:47.767354 Dram Type= 6, Freq= 0, CH_1, rank 1
8634 20:14:47.774180 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8635 20:14:47.774741 ==
8636 20:14:47.775108
8637 20:14:47.775442
8638 20:14:47.775763 TX Vref Scan disable
8639 20:14:47.777153 == TX Byte 0 ==
8640 20:14:47.781137 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8641 20:14:47.787614 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8642 20:14:47.788083 == TX Byte 1 ==
8643 20:14:47.790543 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8644 20:14:47.797347 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8645 20:14:47.797910 ==
8646 20:14:47.800603 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 20:14:47.803869 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 20:14:47.804435 ==
8649 20:14:47.818184
8650 20:14:47.820295 TX Vref early break, caculate TX vref
8651 20:14:47.823756 TX Vref=16, minBit 0, minWin=22, winSum=375
8652 20:14:47.827401 TX Vref=18, minBit 0, minWin=22, winSum=384
8653 20:14:47.830657 TX Vref=20, minBit 0, minWin=23, winSum=391
8654 20:14:47.834165 TX Vref=22, minBit 0, minWin=24, winSum=401
8655 20:14:47.837130 TX Vref=24, minBit 0, minWin=24, winSum=410
8656 20:14:47.844141 TX Vref=26, minBit 0, minWin=25, winSum=416
8657 20:14:47.847045 TX Vref=28, minBit 0, minWin=24, winSum=416
8658 20:14:47.851028 TX Vref=30, minBit 0, minWin=23, winSum=414
8659 20:14:47.853962 TX Vref=32, minBit 0, minWin=23, winSum=400
8660 20:14:47.857362 TX Vref=34, minBit 0, minWin=23, winSum=396
8661 20:14:47.860268 TX Vref=36, minBit 0, minWin=22, winSum=385
8662 20:14:47.866917 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8663 20:14:47.867480
8664 20:14:47.870213 Final TX Range 0 Vref 26
8665 20:14:47.870775
8666 20:14:47.871143 ==
8667 20:14:47.873215 Dram Type= 6, Freq= 0, CH_1, rank 1
8668 20:14:47.876645 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8669 20:14:47.877292 ==
8670 20:14:47.877744
8671 20:14:47.878093
8672 20:14:47.879794 TX Vref Scan disable
8673 20:14:47.886587 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8674 20:14:47.887056 == TX Byte 0 ==
8675 20:14:47.889815 u2DelayCellOfst[0]=14 cells (4 PI)
8676 20:14:47.893920 u2DelayCellOfst[1]=10 cells (3 PI)
8677 20:14:47.896977 u2DelayCellOfst[2]=0 cells (0 PI)
8678 20:14:47.900060 u2DelayCellOfst[3]=7 cells (2 PI)
8679 20:14:47.903327 u2DelayCellOfst[4]=7 cells (2 PI)
8680 20:14:47.906446 u2DelayCellOfst[5]=17 cells (5 PI)
8681 20:14:47.910276 u2DelayCellOfst[6]=14 cells (4 PI)
8682 20:14:47.913415 u2DelayCellOfst[7]=3 cells (1 PI)
8683 20:14:47.916850 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8684 20:14:47.919653 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8685 20:14:47.923231 == TX Byte 1 ==
8686 20:14:47.927106 u2DelayCellOfst[8]=0 cells (0 PI)
8687 20:14:47.927673 u2DelayCellOfst[9]=7 cells (2 PI)
8688 20:14:47.929857 u2DelayCellOfst[10]=14 cells (4 PI)
8689 20:14:47.933177 u2DelayCellOfst[11]=7 cells (2 PI)
8690 20:14:47.936494 u2DelayCellOfst[12]=17 cells (5 PI)
8691 20:14:47.939701 u2DelayCellOfst[13]=21 cells (6 PI)
8692 20:14:47.944130 u2DelayCellOfst[14]=21 cells (6 PI)
8693 20:14:47.946055 u2DelayCellOfst[15]=21 cells (6 PI)
8694 20:14:47.952806 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8695 20:14:47.955926 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8696 20:14:47.956397 DramC Write-DBI on
8697 20:14:47.956816 ==
8698 20:14:47.960389 Dram Type= 6, Freq= 0, CH_1, rank 1
8699 20:14:47.965929 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8700 20:14:47.966489 ==
8701 20:14:47.966856
8702 20:14:47.967193
8703 20:14:47.967516 TX Vref Scan disable
8704 20:14:47.970221 == TX Byte 0 ==
8705 20:14:47.973306 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8706 20:14:47.976788 == TX Byte 1 ==
8707 20:14:47.980155 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8708 20:14:47.983460 DramC Write-DBI off
8709 20:14:47.984025
8710 20:14:47.984391 [DATLAT]
8711 20:14:47.984788 Freq=1600, CH1 RK1
8712 20:14:47.985138
8713 20:14:47.987279 DATLAT Default: 0xe
8714 20:14:47.987870 0, 0xFFFF, sum = 0
8715 20:14:47.989858 1, 0xFFFF, sum = 0
8716 20:14:47.993864 2, 0xFFFF, sum = 0
8717 20:14:47.994454 3, 0xFFFF, sum = 0
8718 20:14:47.996776 4, 0xFFFF, sum = 0
8719 20:14:47.997336 5, 0xFFFF, sum = 0
8720 20:14:47.999693 6, 0xFFFF, sum = 0
8721 20:14:48.000163 7, 0xFFFF, sum = 0
8722 20:14:48.004039 8, 0xFFFF, sum = 0
8723 20:14:48.004616 9, 0xFFFF, sum = 0
8724 20:14:48.007060 10, 0xFFFF, sum = 0
8725 20:14:48.007549 11, 0xFFFF, sum = 0
8726 20:14:48.010603 12, 0xF7F, sum = 0
8727 20:14:48.011181 13, 0x0, sum = 1
8728 20:14:48.013258 14, 0x0, sum = 2
8729 20:14:48.013799 15, 0x0, sum = 3
8730 20:14:48.016784 16, 0x0, sum = 4
8731 20:14:48.017355 best_step = 14
8732 20:14:48.017765
8733 20:14:48.018111 ==
8734 20:14:48.019796 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 20:14:48.023422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8736 20:14:48.026481 ==
8737 20:14:48.027046 RX Vref Scan: 0
8738 20:14:48.027417
8739 20:14:48.029894 RX Vref 0 -> 0, step: 1
8740 20:14:48.030396
8741 20:14:48.030768 RX Delay 3 -> 252, step: 4
8742 20:14:48.037851 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8743 20:14:48.040748 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8744 20:14:48.043340 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8745 20:14:48.047278 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8746 20:14:48.051603 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8747 20:14:48.057104 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8748 20:14:48.060650 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8749 20:14:48.064243 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8750 20:14:48.067009 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8751 20:14:48.069901 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8752 20:14:48.076984 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8753 20:14:48.080207 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8754 20:14:48.083638 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8755 20:14:48.086985 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8756 20:14:48.093231 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8757 20:14:48.096969 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8758 20:14:48.097542 ==
8759 20:14:48.099668 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 20:14:48.103110 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8761 20:14:48.103578 ==
8762 20:14:48.107222 DQS Delay:
8763 20:14:48.107794 DQS0 = 0, DQS1 = 0
8764 20:14:48.108227 DQM Delay:
8765 20:14:48.110361 DQM0 = 127, DQM1 = 123
8766 20:14:48.111098 DQ Delay:
8767 20:14:48.113062 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8768 20:14:48.116381 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8769 20:14:48.120477 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8770 20:14:48.126772 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8771 20:14:48.127374
8772 20:14:48.127746
8773 20:14:48.128088
8774 20:14:48.130196 [DramC_TX_OE_Calibration] TA2
8775 20:14:48.133458 Original DQ_B0 (3 6) =30, OEN = 27
8776 20:14:48.133936 Original DQ_B1 (3 6) =30, OEN = 27
8777 20:14:48.136569 24, 0x0, End_B0=24 End_B1=24
8778 20:14:48.139637 25, 0x0, End_B0=25 End_B1=25
8779 20:14:48.142701 26, 0x0, End_B0=26 End_B1=26
8780 20:14:48.146235 27, 0x0, End_B0=27 End_B1=27
8781 20:14:48.146725 28, 0x0, End_B0=28 End_B1=28
8782 20:14:48.149428 29, 0x0, End_B0=29 End_B1=29
8783 20:14:48.153307 30, 0x0, End_B0=30 End_B1=30
8784 20:14:48.156451 31, 0x4141, End_B0=30 End_B1=30
8785 20:14:48.159166 Byte0 end_step=30 best_step=27
8786 20:14:48.163071 Byte1 end_step=30 best_step=27
8787 20:14:48.163656 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 20:14:48.166369 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 20:14:48.166938
8790 20:14:48.167307
8791 20:14:48.176249 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8792 20:14:48.179196 CH1 RK1: MR19=303, MR18=1B1B
8793 20:14:48.183673 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8794 20:14:48.185963 [RxdqsGatingPostProcess] freq 1600
8795 20:14:48.192496 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8796 20:14:48.195967 Pre-setting of DQS Precalculation
8797 20:14:48.199672 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8798 20:14:48.209414 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8799 20:14:48.215683 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8800 20:14:48.216252
8801 20:14:48.216659
8802 20:14:48.219332 [Calibration Summary] 3200 Mbps
8803 20:14:48.219980 CH 0, Rank 0
8804 20:14:48.222541 SW Impedance : PASS
8805 20:14:48.223007 DUTY Scan : NO K
8806 20:14:48.225553 ZQ Calibration : PASS
8807 20:14:48.230899 Jitter Meter : NO K
8808 20:14:48.231486 CBT Training : PASS
8809 20:14:48.233316 Write leveling : PASS
8810 20:14:48.236102 RX DQS gating : PASS
8811 20:14:48.236669 RX DQ/DQS(RDDQC) : PASS
8812 20:14:48.238854 TX DQ/DQS : PASS
8813 20:14:48.242689 RX DATLAT : PASS
8814 20:14:48.243156 RX DQ/DQS(Engine): PASS
8815 20:14:48.245953 TX OE : PASS
8816 20:14:48.246530 All Pass.
8817 20:14:48.246900
8818 20:14:48.249382 CH 0, Rank 1
8819 20:14:48.249949 SW Impedance : PASS
8820 20:14:48.251879 DUTY Scan : NO K
8821 20:14:48.255052 ZQ Calibration : PASS
8822 20:14:48.255525 Jitter Meter : NO K
8823 20:14:48.259039 CBT Training : PASS
8824 20:14:48.259614 Write leveling : PASS
8825 20:14:48.262287 RX DQS gating : PASS
8826 20:14:48.265340 RX DQ/DQS(RDDQC) : PASS
8827 20:14:48.265803 TX DQ/DQS : PASS
8828 20:14:48.268402 RX DATLAT : PASS
8829 20:14:48.271805 RX DQ/DQS(Engine): PASS
8830 20:14:48.272369 TX OE : PASS
8831 20:14:48.275451 All Pass.
8832 20:14:48.276021
8833 20:14:48.276390 CH 1, Rank 0
8834 20:14:48.278419 SW Impedance : PASS
8835 20:14:48.278884 DUTY Scan : NO K
8836 20:14:48.281983 ZQ Calibration : PASS
8837 20:14:48.285553 Jitter Meter : NO K
8838 20:14:48.286014 CBT Training : PASS
8839 20:14:48.289361 Write leveling : PASS
8840 20:14:48.291561 RX DQS gating : PASS
8841 20:14:48.292024 RX DQ/DQS(RDDQC) : PASS
8842 20:14:48.295014 TX DQ/DQS : PASS
8843 20:14:48.298116 RX DATLAT : PASS
8844 20:14:48.298662 RX DQ/DQS(Engine): PASS
8845 20:14:48.301690 TX OE : PASS
8846 20:14:48.302158 All Pass.
8847 20:14:48.302522
8848 20:14:48.305676 CH 1, Rank 1
8849 20:14:48.306249 SW Impedance : PASS
8850 20:14:48.308658 DUTY Scan : NO K
8851 20:14:48.312210 ZQ Calibration : PASS
8852 20:14:48.312817 Jitter Meter : NO K
8853 20:14:48.315479 CBT Training : PASS
8854 20:14:48.319221 Write leveling : PASS
8855 20:14:48.319791 RX DQS gating : PASS
8856 20:14:48.322232 RX DQ/DQS(RDDQC) : PASS
8857 20:14:48.322804 TX DQ/DQS : PASS
8858 20:14:48.325181 RX DATLAT : PASS
8859 20:14:48.328274 RX DQ/DQS(Engine): PASS
8860 20:14:48.328909 TX OE : PASS
8861 20:14:48.331526 All Pass.
8862 20:14:48.332117
8863 20:14:48.332491 DramC Write-DBI on
8864 20:14:48.335712 PER_BANK_REFRESH: Hybrid Mode
8865 20:14:48.339168 TX_TRACKING: ON
8866 20:14:48.345113 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8867 20:14:48.355040 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8868 20:14:48.362747 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8869 20:14:48.364560 [FAST_K] Save calibration result to emmc
8870 20:14:48.367578 sync common calibartion params.
8871 20:14:48.368041 sync cbt_mode0:0, 1:0
8872 20:14:48.371549 dram_init: ddr_geometry: 0
8873 20:14:48.374714 dram_init: ddr_geometry: 0
8874 20:14:48.377969 dram_init: ddr_geometry: 0
8875 20:14:48.378437 0:dram_rank_size:80000000
8876 20:14:48.381878 1:dram_rank_size:80000000
8877 20:14:48.388275 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8878 20:14:48.388796 DFS_SHUFFLE_HW_MODE: ON
8879 20:14:48.390982 dramc_set_vcore_voltage set vcore to 725000
8880 20:14:48.394599 Read voltage for 1600, 0
8881 20:14:48.395165 Vio18 = 0
8882 20:14:48.397951 Vcore = 725000
8883 20:14:48.398427 Vdram = 0
8884 20:14:48.398802 Vddq = 0
8885 20:14:48.401318 Vmddr = 0
8886 20:14:48.401788 switch to 3200 Mbps bootup
8887 20:14:48.404745 [DramcRunTimeConfig]
8888 20:14:48.405234 PHYPLL
8889 20:14:48.407433 DPM_CONTROL_AFTERK: ON
8890 20:14:48.407900 PER_BANK_REFRESH: ON
8891 20:14:48.411363 REFRESH_OVERHEAD_REDUCTION: ON
8892 20:14:48.414326 CMD_PICG_NEW_MODE: OFF
8893 20:14:48.414800 XRTWTW_NEW_MODE: ON
8894 20:14:48.417579 XRTRTR_NEW_MODE: ON
8895 20:14:48.418003 TX_TRACKING: ON
8896 20:14:48.420412 RDSEL_TRACKING: OFF
8897 20:14:48.424343 DQS Precalculation for DVFS: ON
8898 20:14:48.424798 RX_TRACKING: OFF
8899 20:14:48.428166 HW_GATING DBG: ON
8900 20:14:48.428588 ZQCS_ENABLE_LP4: ON
8901 20:14:48.431447 RX_PICG_NEW_MODE: ON
8902 20:14:48.431985 TX_PICG_NEW_MODE: ON
8903 20:14:48.433650 ENABLE_RX_DCM_DPHY: ON
8904 20:14:48.437478 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8905 20:14:48.440798 DUMMY_READ_FOR_TRACKING: OFF
8906 20:14:48.444066 !!! SPM_CONTROL_AFTERK: OFF
8907 20:14:48.444534 !!! SPM could not control APHY
8908 20:14:48.447886 IMPEDANCE_TRACKING: ON
8909 20:14:48.448575 TEMP_SENSOR: ON
8910 20:14:48.450939 HW_SAVE_FOR_SR: OFF
8911 20:14:48.454742 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8912 20:14:48.457051 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8913 20:14:48.460702 Read ODT Tracking: ON
8914 20:14:48.461168 Refresh Rate DeBounce: ON
8915 20:14:48.464248 DFS_NO_QUEUE_FLUSH: ON
8916 20:14:48.467064 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8917 20:14:48.471701 ENABLE_DFS_RUNTIME_MRW: OFF
8918 20:14:48.472233 DDR_RESERVE_NEW_MODE: ON
8919 20:14:48.473638 MR_CBT_SWITCH_FREQ: ON
8920 20:14:48.476922 =========================
8921 20:14:48.495241 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8922 20:14:48.497733 dram_init: ddr_geometry: 0
8923 20:14:48.516241 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8924 20:14:48.519343 dram_init: dram init end (result: 0)
8925 20:14:48.526626 DRAM-K: Full calibration passed in 23409 msecs
8926 20:14:48.529484 MRC: failed to locate region type 0.
8927 20:14:48.530058 DRAM rank0 size:0x80000000,
8928 20:14:48.532893 DRAM rank1 size=0x80000000
8929 20:14:48.542681 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8930 20:14:48.550121 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8931 20:14:48.555550 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8932 20:14:48.562270 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8933 20:14:48.565726 DRAM rank0 size:0x80000000,
8934 20:14:48.568344 DRAM rank1 size=0x80000000
8935 20:14:48.568849 CBMEM:
8936 20:14:48.572218 IMD: root @ 0xfffff000 254 entries.
8937 20:14:48.575776 IMD: root @ 0xffffec00 62 entries.
8938 20:14:48.578668 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8939 20:14:48.581955 WARNING: RO_VPD is uninitialized or empty.
8940 20:14:48.588777 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8941 20:14:48.595705 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8942 20:14:48.608526 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8943 20:14:48.620404 BS: romstage times (exec / console): total (unknown) / 22956 ms
8944 20:14:48.621027
8945 20:14:48.621397
8946 20:14:48.629452 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8947 20:14:48.632907 ARM64: Exception handlers installed.
8948 20:14:48.636027 ARM64: Testing exception
8949 20:14:48.639545 ARM64: Done test exception
8950 20:14:48.640119 Enumerating buses...
8951 20:14:48.642627 Show all devs... Before device enumeration.
8952 20:14:48.646212 Root Device: enabled 1
8953 20:14:48.648975 CPU_CLUSTER: 0: enabled 1
8954 20:14:48.649444 CPU: 00: enabled 1
8955 20:14:48.653045 Compare with tree...
8956 20:14:48.653511 Root Device: enabled 1
8957 20:14:48.656630 CPU_CLUSTER: 0: enabled 1
8958 20:14:48.659540 CPU: 00: enabled 1
8959 20:14:48.660009 Root Device scanning...
8960 20:14:48.662296 scan_static_bus for Root Device
8961 20:14:48.665543 CPU_CLUSTER: 0 enabled
8962 20:14:48.669429 scan_static_bus for Root Device done
8963 20:14:48.672423 scan_bus: bus Root Device finished in 8 msecs
8964 20:14:48.672984 done
8965 20:14:48.678749 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8966 20:14:48.683509 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8967 20:14:48.689136 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8968 20:14:48.695507 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8969 20:14:48.695980 Allocating resources...
8970 20:14:48.698383 Reading resources...
8971 20:14:48.702438 Root Device read_resources bus 0 link: 0
8972 20:14:48.705113 DRAM rank0 size:0x80000000,
8973 20:14:48.705686 DRAM rank1 size=0x80000000
8974 20:14:48.709098 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8975 20:14:48.712598 CPU: 00 missing read_resources
8976 20:14:48.719554 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8977 20:14:48.721708 Root Device read_resources bus 0 link: 0 done
8978 20:14:48.725580 Done reading resources.
8979 20:14:48.729444 Show resources in subtree (Root Device)...After reading.
8980 20:14:48.732291 Root Device child on link 0 CPU_CLUSTER: 0
8981 20:14:48.735387 CPU_CLUSTER: 0 child on link 0 CPU: 00
8982 20:14:48.745077 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8983 20:14:48.745696 CPU: 00
8984 20:14:48.748547 Root Device assign_resources, bus 0 link: 0
8985 20:14:48.751323 CPU_CLUSTER: 0 missing set_resources
8986 20:14:48.757848 Root Device assign_resources, bus 0 link: 0 done
8987 20:14:48.758410 Done setting resources.
8988 20:14:48.765260 Show resources in subtree (Root Device)...After assigning values.
8989 20:14:48.768328 Root Device child on link 0 CPU_CLUSTER: 0
8990 20:14:48.771861 CPU_CLUSTER: 0 child on link 0 CPU: 00
8991 20:14:48.781827 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8992 20:14:48.782389 CPU: 00
8993 20:14:48.784358 Done allocating resources.
8994 20:14:48.791634 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8995 20:14:48.792296 Enabling resources...
8996 20:14:48.794640 done.
8997 20:14:48.797796 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8998 20:14:48.800693 Initializing devices...
8999 20:14:48.801193 Root Device init
9000 20:14:48.804650 init hardware done!
9001 20:14:48.805163 0x00000018: ctrlr->caps
9002 20:14:48.807574 52.000 MHz: ctrlr->f_max
9003 20:14:48.810678 0.400 MHz: ctrlr->f_min
9004 20:14:48.811163 0x40ff8080: ctrlr->voltages
9005 20:14:48.814608 sclk: 390625
9006 20:14:48.815183 Bus Width = 1
9007 20:14:48.817927 sclk: 390625
9008 20:14:48.818500 Bus Width = 1
9009 20:14:48.820525 Early init status = 3
9010 20:14:48.824372 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9011 20:14:48.827617 in-header: 03 fc 00 00 01 00 00 00
9012 20:14:48.831195 in-data: 00
9013 20:14:48.834229 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9014 20:14:48.839807 in-header: 03 fd 00 00 00 00 00 00
9015 20:14:48.842778 in-data:
9016 20:14:48.845417 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9017 20:14:48.849440 in-header: 03 fc 00 00 01 00 00 00
9018 20:14:48.852800 in-data: 00
9019 20:14:48.856268 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9020 20:14:48.860793 in-header: 03 fd 00 00 00 00 00 00
9021 20:14:48.864601 in-data:
9022 20:14:48.867828 [SSUSB] Setting up USB HOST controller...
9023 20:14:48.870886 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9024 20:14:48.874633 [SSUSB] phy power-on done.
9025 20:14:48.878352 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9026 20:14:48.884353 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9027 20:14:48.887573 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9028 20:14:48.893983 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9029 20:14:48.901123 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9030 20:14:48.907342 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9031 20:14:48.914018 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9032 20:14:48.920901 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9033 20:14:48.923942 SPM: binary array size = 0x9dc
9034 20:14:48.928878 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9035 20:14:48.933987 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9036 20:14:48.940852 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9037 20:14:48.947954 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9038 20:14:48.950869 configure_display: Starting display init
9039 20:14:48.984443 anx7625_power_on_init: Init interface.
9040 20:14:48.988078 anx7625_disable_pd_protocol: Disabled PD feature.
9041 20:14:48.991429 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9042 20:14:49.019935 anx7625_start_dp_work: Secure OCM version=00
9043 20:14:49.022443 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9044 20:14:49.036607 sp_tx_get_edid_block: EDID Block = 1
9045 20:14:49.139423 Extracted contents:
9046 20:14:49.144424 header: 00 ff ff ff ff ff ff 00
9047 20:14:49.146706 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9048 20:14:49.149159 version: 01 04
9049 20:14:49.152802 basic params: 95 1f 11 78 0a
9050 20:14:49.156453 chroma info: 76 90 94 55 54 90 27 21 50 54
9051 20:14:49.159471 established: 00 00 00
9052 20:14:49.165771 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9053 20:14:49.173419 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9054 20:14:49.175861 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9055 20:14:49.182174 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9056 20:14:49.188489 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9057 20:14:49.192319 extensions: 00
9058 20:14:49.192930 checksum: fb
9059 20:14:49.193306
9060 20:14:49.195616 Manufacturer: IVO Model 57d Serial Number 0
9061 20:14:49.198975 Made week 0 of 2020
9062 20:14:49.202643 EDID version: 1.4
9063 20:14:49.203215 Digital display
9064 20:14:49.205360 6 bits per primary color channel
9065 20:14:49.205941 DisplayPort interface
9066 20:14:49.208687 Maximum image size: 31 cm x 17 cm
9067 20:14:49.212022 Gamma: 220%
9068 20:14:49.212595 Check DPMS levels
9069 20:14:49.215366 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9070 20:14:49.221918 First detailed timing is preferred timing
9071 20:14:49.222496 Established timings supported:
9072 20:14:49.225555 Standard timings supported:
9073 20:14:49.229157 Detailed timings
9074 20:14:49.231902 Hex of detail: 383680a07038204018303c0035ae10000019
9075 20:14:49.238229 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9076 20:14:49.241662 0780 0798 07c8 0820 hborder 0
9077 20:14:49.244796 0438 043b 0447 0458 vborder 0
9078 20:14:49.248581 -hsync -vsync
9079 20:14:49.249221 Did detailed timing
9080 20:14:49.255071 Hex of detail: 000000000000000000000000000000000000
9081 20:14:49.260537 Manufacturer-specified data, tag 0
9082 20:14:49.262113 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9083 20:14:49.264990 ASCII string: InfoVision
9084 20:14:49.268221 Hex of detail: 000000fe00523134304e574635205248200a
9085 20:14:49.271787 ASCII string: R140NWF5 RH
9086 20:14:49.272356 Checksum
9087 20:14:49.274877 Checksum: 0xfb (valid)
9088 20:14:49.278447 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9089 20:14:49.281849 DSI data_rate: 832800000 bps
9090 20:14:49.287762 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9091 20:14:49.291711 anx7625_parse_edid: pixelclock(138800).
9092 20:14:49.294652 hactive(1920), hsync(48), hfp(24), hbp(88)
9093 20:14:49.298195 vactive(1080), vsync(12), vfp(3), vbp(17)
9094 20:14:49.301416 anx7625_dsi_config: config dsi.
9095 20:14:49.308606 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9096 20:14:49.321457 anx7625_dsi_config: success to config DSI
9097 20:14:49.325044 anx7625_dp_start: MIPI phy setup OK.
9098 20:14:49.328265 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9099 20:14:49.332434 mtk_ddp_mode_set invalid vrefresh 60
9100 20:14:49.334326 main_disp_path_setup
9101 20:14:49.334792 ovl_layer_smi_id_en
9102 20:14:49.338085 ovl_layer_smi_id_en
9103 20:14:49.338663 ccorr_config
9104 20:14:49.339037 aal_config
9105 20:14:49.341083 gamma_config
9106 20:14:49.341553 postmask_config
9107 20:14:49.345125 dither_config
9108 20:14:49.347742 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9109 20:14:49.354558 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9110 20:14:49.357787 Root Device init finished in 553 msecs
9111 20:14:49.361359 CPU_CLUSTER: 0 init
9112 20:14:49.368649 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9113 20:14:49.371495 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9114 20:14:49.374586 APU_MBOX 0x190000b0 = 0x10001
9115 20:14:49.377758 APU_MBOX 0x190001b0 = 0x10001
9116 20:14:49.380656 APU_MBOX 0x190005b0 = 0x10001
9117 20:14:49.384247 APU_MBOX 0x190006b0 = 0x10001
9118 20:14:49.390662 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9119 20:14:49.400135 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9120 20:14:49.412813 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9121 20:14:49.419200 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9122 20:14:49.431477 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9123 20:14:49.440807 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9124 20:14:49.443403 CPU_CLUSTER: 0 init finished in 81 msecs
9125 20:14:49.446706 Devices initialized
9126 20:14:49.450041 Show all devs... After init.
9127 20:14:49.450625 Root Device: enabled 1
9128 20:14:49.453093 CPU_CLUSTER: 0: enabled 1
9129 20:14:49.456508 CPU: 00: enabled 1
9130 20:14:49.460136 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9131 20:14:49.463374 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9132 20:14:49.467221 ELOG: NV offset 0x57f000 size 0x1000
9133 20:14:49.473287 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9134 20:14:49.479616 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9135 20:14:49.483146 ELOG: Event(17) added with size 13 at 2024-03-03 20:14:49 UTC
9136 20:14:49.486708 out: cmd=0x121: 03 db 21 01 00 00 00 00
9137 20:14:49.490336 in-header: 03 0b 00 00 2c 00 00 00
9138 20:14:49.503701 in-data: 58 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9139 20:14:49.510814 ELOG: Event(A1) added with size 10 at 2024-03-03 20:14:49 UTC
9140 20:14:49.517298 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9141 20:14:49.523501 ELOG: Event(A0) added with size 9 at 2024-03-03 20:14:49 UTC
9142 20:14:49.526941 elog_add_boot_reason: Logged dev mode boot
9143 20:14:49.531035 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9144 20:14:49.533713 Finalize devices...
9145 20:14:49.534286 Devices finalized
9146 20:14:49.540125 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9147 20:14:49.543597 Writing coreboot table at 0xffe64000
9148 20:14:49.546453 0. 000000000010a000-0000000000113fff: RAMSTAGE
9149 20:14:49.550484 1. 0000000040000000-00000000400fffff: RAM
9150 20:14:49.557597 2. 0000000040100000-000000004032afff: RAMSTAGE
9151 20:14:49.560495 3. 000000004032b000-00000000545fffff: RAM
9152 20:14:49.564175 4. 0000000054600000-000000005465ffff: BL31
9153 20:14:49.567378 5. 0000000054660000-00000000ffe63fff: RAM
9154 20:14:49.573793 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9155 20:14:49.577471 7. 0000000100000000-000000013fffffff: RAM
9156 20:14:49.577970 Passing 5 GPIOs to payload:
9157 20:14:49.583922 NAME | PORT | POLARITY | VALUE
9158 20:14:49.586251 EC in RW | 0x000000aa | low | undefined
9159 20:14:49.592669 EC interrupt | 0x00000005 | low | undefined
9160 20:14:49.596032 TPM interrupt | 0x000000ab | high | undefined
9161 20:14:49.603051 SD card detect | 0x00000011 | high | undefined
9162 20:14:49.606517 speaker enable | 0x00000093 | high | undefined
9163 20:14:49.609922 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9164 20:14:49.613360 in-header: 03 f8 00 00 02 00 00 00
9165 20:14:49.616701 in-data: 03 00
9166 20:14:49.617316 ADC[4]: Raw value=669327 ID=5
9167 20:14:49.620385 ADC[3]: Raw value=212549 ID=1
9168 20:14:49.622694 RAM Code: 0x51
9169 20:14:49.623163 ADC[6]: Raw value=74410 ID=0
9170 20:14:49.626050 ADC[5]: Raw value=211444 ID=1
9171 20:14:49.630040 SKU Code: 0x1
9172 20:14:49.634056 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c2bf
9173 20:14:49.635991 coreboot table: 964 bytes.
9174 20:14:49.640822 IMD ROOT 0. 0xfffff000 0x00001000
9175 20:14:49.642801 IMD SMALL 1. 0xffffe000 0x00001000
9176 20:14:49.647430 RO MCACHE 2. 0xffffc000 0x00001104
9177 20:14:49.649467 CONSOLE 3. 0xfff7c000 0x00080000
9178 20:14:49.652773 FMAP 4. 0xfff7b000 0x00000452
9179 20:14:49.655942 TIME STAMP 5. 0xfff7a000 0x00000910
9180 20:14:49.660193 VBOOT WORK 6. 0xfff66000 0x00014000
9181 20:14:49.662209 RAMOOPS 7. 0xffe66000 0x00100000
9182 20:14:49.666218 COREBOOT 8. 0xffe64000 0x00002000
9183 20:14:49.666713 IMD small region:
9184 20:14:49.669413 IMD ROOT 0. 0xffffec00 0x00000400
9185 20:14:49.676442 VPD 1. 0xffffeb80 0x0000006c
9186 20:14:49.679726 MMC STATUS 2. 0xffffeb60 0x00000004
9187 20:14:49.682175 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9188 20:14:49.685684 Probing TPM: done!
9189 20:14:49.690070 Connected to device vid:did:rid of 1ae0:0028:00
9190 20:14:49.699299 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9191 20:14:49.702656 Initialized TPM device CR50 revision 0
9192 20:14:49.707166 Checking cr50 for pending updates
9193 20:14:49.710020 Reading cr50 TPM mode
9194 20:14:49.718370 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9195 20:14:49.724835 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9196 20:14:49.765222 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9197 20:14:49.769007 Checking segment from ROM address 0x40100000
9198 20:14:49.772265 Checking segment from ROM address 0x4010001c
9199 20:14:49.778983 Loading segment from ROM address 0x40100000
9200 20:14:49.779605 code (compression=0)
9201 20:14:49.788960 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9202 20:14:49.795190 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9203 20:14:49.795753 it's not compressed!
9204 20:14:49.801976 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9205 20:14:49.805461 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9206 20:14:49.825837 Loading segment from ROM address 0x4010001c
9207 20:14:49.826395 Entry Point 0x80000000
9208 20:14:49.829374 Loaded segments
9209 20:14:49.832332 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9210 20:14:49.839095 Jumping to boot code at 0x80000000(0xffe64000)
9211 20:14:49.845576 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9212 20:14:49.852588 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9213 20:14:49.860006 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9214 20:14:49.864054 Checking segment from ROM address 0x40100000
9215 20:14:49.866678 Checking segment from ROM address 0x4010001c
9216 20:14:49.873565 Loading segment from ROM address 0x40100000
9217 20:14:49.874167 code (compression=1)
9218 20:14:49.879978 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9219 20:14:49.891058 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9220 20:14:49.891636 using LZMA
9221 20:14:49.898963 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9222 20:14:49.905607 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9223 20:14:49.908609 Loading segment from ROM address 0x4010001c
9224 20:14:49.909228 Entry Point 0x54601000
9225 20:14:49.912004 Loaded segments
9226 20:14:49.916364 NOTICE: MT8192 bl31_setup
9227 20:14:49.922709 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9228 20:14:49.925606 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9229 20:14:49.928801 WARNING: region 0:
9230 20:14:49.932493 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9231 20:14:49.933113 WARNING: region 1:
9232 20:14:49.938935 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9233 20:14:49.942363 WARNING: region 2:
9234 20:14:49.945382 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9235 20:14:49.948958 WARNING: region 3:
9236 20:14:49.952255 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9237 20:14:49.955676 WARNING: region 4:
9238 20:14:49.962393 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9239 20:14:49.962972 WARNING: region 5:
9240 20:14:49.965218 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 20:14:49.968380 WARNING: region 6:
9242 20:14:49.972035 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9243 20:14:49.975117 WARNING: region 7:
9244 20:14:49.978731 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9245 20:14:49.985642 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9246 20:14:49.988889 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9247 20:14:49.991955 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9248 20:14:49.998752 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9249 20:14:50.001494 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9250 20:14:50.005087 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9251 20:14:50.012032 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9252 20:14:50.014695 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9253 20:14:50.022785 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9254 20:14:50.025612 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9255 20:14:50.029154 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9256 20:14:50.035054 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9257 20:14:50.038766 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9258 20:14:50.042865 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9259 20:14:50.049423 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9260 20:14:50.051818 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9261 20:14:50.058399 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9262 20:14:50.061820 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9263 20:14:50.065037 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9264 20:14:50.071903 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9265 20:14:50.075598 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9266 20:14:50.078357 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9267 20:14:50.085001 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9268 20:14:50.088459 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9269 20:14:50.094896 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9270 20:14:50.098763 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9271 20:14:50.105647 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9272 20:14:50.108384 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9273 20:14:50.111519 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9274 20:14:50.119055 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9275 20:14:50.121590 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9276 20:14:50.124855 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9277 20:14:50.132098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9278 20:14:50.134795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9279 20:14:50.138470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9280 20:14:50.141691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9281 20:14:50.148549 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9282 20:14:50.151660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9283 20:14:50.154887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9284 20:14:50.158385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9285 20:14:50.164746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9286 20:14:50.168316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9287 20:14:50.171645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9288 20:14:50.174691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9289 20:14:50.181419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9290 20:14:50.184893 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9291 20:14:50.187855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9292 20:14:50.195177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9293 20:14:50.197673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9294 20:14:50.201844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9295 20:14:50.208112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9296 20:14:50.211424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9297 20:14:50.218509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9298 20:14:50.221240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9299 20:14:50.225042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9300 20:14:50.231277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9301 20:14:50.234912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9302 20:14:50.241676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9303 20:14:50.244754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9304 20:14:50.251385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9305 20:14:50.254607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9306 20:14:50.262344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9307 20:14:50.264953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9308 20:14:50.268612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9309 20:14:50.274855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9310 20:14:50.278225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9311 20:14:50.285209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9312 20:14:50.288537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9313 20:14:50.294828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9314 20:14:50.297917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9315 20:14:50.301830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9316 20:14:50.308002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9317 20:14:50.311494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9318 20:14:50.317906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9319 20:14:50.321504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9320 20:14:50.328087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9321 20:14:50.331578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9322 20:14:50.334831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9323 20:14:50.341580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9324 20:14:50.344938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9325 20:14:50.351541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9326 20:14:50.354107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9327 20:14:50.361397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9328 20:14:50.364438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9329 20:14:50.370927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9330 20:14:50.374809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9331 20:14:50.377511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9332 20:14:50.384311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9333 20:14:50.387966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9334 20:14:50.394175 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9335 20:14:50.397293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9336 20:14:50.405109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9337 20:14:50.407904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9338 20:14:50.410915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9339 20:14:50.417535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9340 20:14:50.421127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9341 20:14:50.427717 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9342 20:14:50.430565 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9343 20:14:50.434277 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9344 20:14:50.437424 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9345 20:14:50.444511 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9346 20:14:50.447076 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9347 20:14:50.451367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9348 20:14:50.457239 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9349 20:14:50.460393 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9350 20:14:50.466991 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9351 20:14:50.470995 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9352 20:14:50.474255 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9353 20:14:50.481112 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9354 20:14:50.483793 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9355 20:14:50.490553 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9356 20:14:50.494043 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9357 20:14:50.497295 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9358 20:14:50.503995 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9359 20:14:50.507393 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9360 20:14:50.513918 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9361 20:14:50.516984 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9362 20:14:50.521042 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9363 20:14:50.527340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9364 20:14:50.530145 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9365 20:14:50.533597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9366 20:14:50.537139 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9367 20:14:50.540442 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9368 20:14:50.547090 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9369 20:14:50.550365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9370 20:14:50.557513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9371 20:14:50.559974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9372 20:14:50.563791 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9373 20:14:50.570683 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9374 20:14:50.573607 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9375 20:14:50.577067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9376 20:14:50.583415 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9377 20:14:50.587251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9378 20:14:50.594097 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9379 20:14:50.597227 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9380 20:14:50.600396 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9381 20:14:50.606745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9382 20:14:50.610268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9383 20:14:50.617007 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9384 20:14:50.620667 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9385 20:14:50.624143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9386 20:14:50.630327 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9387 20:14:50.633991 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9388 20:14:50.640860 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9389 20:14:50.643889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9390 20:14:50.646777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9391 20:14:50.653531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9392 20:14:50.657109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9393 20:14:50.660411 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9394 20:14:50.667308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9395 20:14:50.670167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9396 20:14:50.677278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9397 20:14:50.680380 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9398 20:14:50.683827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9399 20:14:50.690594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9400 20:14:50.693872 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9401 20:14:50.700004 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9402 20:14:50.703766 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9403 20:14:50.706988 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9404 20:14:50.714248 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9405 20:14:50.717004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9406 20:14:50.721083 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9407 20:14:50.727327 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9408 20:14:50.730779 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9409 20:14:50.737691 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9410 20:14:50.739991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9411 20:14:50.743556 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9412 20:14:50.750529 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9413 20:14:50.753825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9414 20:14:50.760040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9415 20:14:50.763422 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9416 20:14:50.766770 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9417 20:14:50.773192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9418 20:14:50.776350 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9419 20:14:50.783721 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9420 20:14:50.786674 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9421 20:14:50.790613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9422 20:14:50.796448 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9423 20:14:50.799861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9424 20:14:50.803533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9425 20:14:50.809843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9426 20:14:50.813213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9427 20:14:50.819691 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9428 20:14:50.823411 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9429 20:14:50.827043 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9430 20:14:50.833818 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9431 20:14:50.836483 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9432 20:14:50.842939 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9433 20:14:50.846475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9434 20:14:50.852955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9435 20:14:50.857364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9436 20:14:50.859755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9437 20:14:50.866329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9438 20:14:50.869609 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9439 20:14:50.876673 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9440 20:14:50.879500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9441 20:14:50.883101 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9442 20:14:50.889529 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9443 20:14:50.892288 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9444 20:14:50.899542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9445 20:14:50.902390 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9446 20:14:50.910138 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9447 20:14:50.912376 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9448 20:14:50.916464 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9449 20:14:50.922323 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9450 20:14:50.925959 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9451 20:14:50.932381 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9452 20:14:50.935802 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9453 20:14:50.939958 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9454 20:14:50.945731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9455 20:14:50.948742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9456 20:14:50.955616 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9457 20:14:50.958935 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9458 20:14:50.965642 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9459 20:14:50.969264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9460 20:14:50.972546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9461 20:14:50.979343 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9462 20:14:50.982579 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9463 20:14:50.988826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9464 20:14:50.992170 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9465 20:14:50.995902 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9466 20:14:51.002228 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9467 20:14:51.005177 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9468 20:14:51.012412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9469 20:14:51.015484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9470 20:14:51.022227 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9471 20:14:51.025117 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9472 20:14:51.028443 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9473 20:14:51.035721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9474 20:14:51.038404 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9475 20:14:51.041382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9476 20:14:51.045162 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9477 20:14:51.051975 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9478 20:14:51.055075 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9479 20:14:51.059129 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9480 20:14:51.065021 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9481 20:14:51.068684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9482 20:14:51.074609 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9483 20:14:51.078955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9484 20:14:51.081472 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9485 20:14:51.087899 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9486 20:14:51.092570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9487 20:14:51.094286 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9488 20:14:51.101012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9489 20:14:51.104624 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9490 20:14:51.110004 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9491 20:14:51.114290 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9492 20:14:51.117797 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9493 20:14:51.124071 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9494 20:14:51.127614 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9495 20:14:51.130503 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9496 20:14:51.137592 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9497 20:14:51.140970 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9498 20:14:51.144166 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9499 20:14:51.150636 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9500 20:14:51.153999 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9501 20:14:51.160791 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9502 20:14:51.164322 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9503 20:14:51.167494 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9504 20:14:51.174836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9505 20:14:51.177486 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9506 20:14:51.180170 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9507 20:14:51.187283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9508 20:14:51.191033 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9509 20:14:51.193923 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9510 20:14:51.201076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9511 20:14:51.203983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9512 20:14:51.210309 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9513 20:14:51.213676 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9514 20:14:51.217654 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9515 20:14:51.220558 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9516 20:14:51.227288 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9517 20:14:51.230701 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9518 20:14:51.233517 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9519 20:14:51.237202 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9520 20:14:51.243179 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9521 20:14:51.247153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9522 20:14:51.249474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9523 20:14:51.253463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9524 20:14:51.259996 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9525 20:14:51.263001 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9526 20:14:51.266667 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9527 20:14:51.272933 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9528 20:14:51.276497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9529 20:14:51.283502 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9530 20:14:51.286305 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9531 20:14:51.290118 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9532 20:14:51.296535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9533 20:14:51.299958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9534 20:14:51.306002 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9535 20:14:51.309209 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9536 20:14:51.312554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9537 20:14:51.319381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9538 20:14:51.322896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9539 20:14:51.329584 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9540 20:14:51.333099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9541 20:14:51.339048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9542 20:14:51.342201 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9543 20:14:51.345581 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9544 20:14:51.352158 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9545 20:14:51.355770 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9546 20:14:51.361995 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9547 20:14:51.365538 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9548 20:14:51.372015 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9549 20:14:51.375056 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9550 20:14:51.378426 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9551 20:14:51.384851 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9552 20:14:51.388800 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9553 20:14:51.394774 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9554 20:14:51.398731 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9555 20:14:51.401455 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9556 20:14:51.408354 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9557 20:14:51.411955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9558 20:14:51.418586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9559 20:14:51.421604 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9560 20:14:51.424670 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9561 20:14:51.431503 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9562 20:14:51.435128 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9563 20:14:51.441236 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9564 20:14:51.444682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9565 20:14:51.451034 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9566 20:14:51.455285 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9567 20:14:51.457999 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9568 20:14:51.465139 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9569 20:14:51.468201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9570 20:14:51.475046 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9571 20:14:51.478470 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9572 20:14:51.481077 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9573 20:14:51.487867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9574 20:14:51.491356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9575 20:14:51.497829 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9576 20:14:51.500909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9577 20:14:51.504601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9578 20:14:51.511670 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9579 20:14:51.513736 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9580 20:14:51.521075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9581 20:14:51.524792 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9582 20:14:51.527094 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9583 20:14:51.533932 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9584 20:14:51.538048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9585 20:14:51.543991 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9586 20:14:51.547834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9587 20:14:51.553714 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9588 20:14:51.557437 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9589 20:14:51.564074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9590 20:14:51.567850 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9591 20:14:51.570336 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9592 20:14:51.578033 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9593 20:14:51.580210 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9594 20:14:51.587082 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9595 20:14:51.590511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9596 20:14:51.593189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9597 20:14:51.599858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9598 20:14:51.603787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9599 20:14:51.609908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9600 20:14:51.613509 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9601 20:14:51.621086 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9602 20:14:51.623335 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9603 20:14:51.626741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9604 20:14:51.633294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9605 20:14:51.636138 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9606 20:14:51.642630 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9607 20:14:51.646177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9608 20:14:51.652653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9609 20:14:51.656750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9610 20:14:51.659483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9611 20:14:51.666379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9612 20:14:51.669579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9613 20:14:51.675935 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9614 20:14:51.679900 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9615 20:14:51.685749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9616 20:14:51.688962 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9617 20:14:51.696388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9618 20:14:51.699198 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9619 20:14:51.702797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9620 20:14:51.709366 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9621 20:14:51.712635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9622 20:14:51.718796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9623 20:14:51.722770 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9624 20:14:51.728895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9625 20:14:51.732172 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9626 20:14:51.738871 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9627 20:14:51.742040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9628 20:14:51.745314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9629 20:14:51.751768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9630 20:14:51.755064 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9631 20:14:51.762058 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9632 20:14:51.765233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9633 20:14:51.771934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9634 20:14:51.774763 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9635 20:14:51.781908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9636 20:14:51.785232 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9637 20:14:51.788482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9638 20:14:51.794643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9639 20:14:51.798319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9640 20:14:51.805065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9641 20:14:51.808052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9642 20:14:51.814737 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9643 20:14:51.817807 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9644 20:14:51.824784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9645 20:14:51.828545 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9646 20:14:51.831193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9647 20:14:51.837846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9648 20:14:51.840756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9649 20:14:51.847899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9650 20:14:51.850886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9651 20:14:51.857515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9652 20:14:51.861151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9653 20:14:51.867259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9654 20:14:51.870773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9655 20:14:51.877473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9656 20:14:51.880585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9657 20:14:51.887509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9658 20:14:51.890691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9659 20:14:51.898251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9660 20:14:51.901136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9661 20:14:51.904203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9662 20:14:51.912898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9663 20:14:51.914341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9664 20:14:51.920304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9665 20:14:51.923606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9666 20:14:51.930355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9667 20:14:51.933418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9668 20:14:51.939844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9669 20:14:51.943918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9670 20:14:51.950061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9671 20:14:51.953198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9672 20:14:51.960181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9673 20:14:51.966892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9674 20:14:51.969805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9675 20:14:51.976846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9676 20:14:51.980133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9677 20:14:51.986418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9678 20:14:51.989617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9679 20:14:51.992775 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9680 20:14:51.996261 INFO: [APUAPC] vio 0
9681 20:14:52.000177 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9682 20:14:52.006672 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9683 20:14:52.009443 INFO: [APUAPC] D0_APC_0: 0x400510
9684 20:14:52.013158 INFO: [APUAPC] D0_APC_1: 0x0
9685 20:14:52.016548 INFO: [APUAPC] D0_APC_2: 0x1540
9686 20:14:52.017287 INFO: [APUAPC] D0_APC_3: 0x0
9687 20:14:52.019775 INFO: [APUAPC] D1_APC_0: 0xffffffff
9688 20:14:52.026138 INFO: [APUAPC] D1_APC_1: 0xffffffff
9689 20:14:52.030125 INFO: [APUAPC] D1_APC_2: 0x3fffff
9690 20:14:52.030707 INFO: [APUAPC] D1_APC_3: 0x0
9691 20:14:52.033262 INFO: [APUAPC] D2_APC_0: 0xffffffff
9692 20:14:52.036272 INFO: [APUAPC] D2_APC_1: 0xffffffff
9693 20:14:52.040205 INFO: [APUAPC] D2_APC_2: 0x3fffff
9694 20:14:52.042655 INFO: [APUAPC] D2_APC_3: 0x0
9695 20:14:52.047256 INFO: [APUAPC] D3_APC_0: 0xffffffff
9696 20:14:52.049452 INFO: [APUAPC] D3_APC_1: 0xffffffff
9697 20:14:52.052800 INFO: [APUAPC] D3_APC_2: 0x3fffff
9698 20:14:52.056030 INFO: [APUAPC] D3_APC_3: 0x0
9699 20:14:52.059334 INFO: [APUAPC] D4_APC_0: 0xffffffff
9700 20:14:52.062730 INFO: [APUAPC] D4_APC_1: 0xffffffff
9701 20:14:52.066049 INFO: [APUAPC] D4_APC_2: 0x3fffff
9702 20:14:52.068963 INFO: [APUAPC] D4_APC_3: 0x0
9703 20:14:52.072644 INFO: [APUAPC] D5_APC_0: 0xffffffff
9704 20:14:52.075714 INFO: [APUAPC] D5_APC_1: 0xffffffff
9705 20:14:52.079508 INFO: [APUAPC] D5_APC_2: 0x3fffff
9706 20:14:52.082950 INFO: [APUAPC] D5_APC_3: 0x0
9707 20:14:52.086121 INFO: [APUAPC] D6_APC_0: 0xffffffff
9708 20:14:52.088703 INFO: [APUAPC] D6_APC_1: 0xffffffff
9709 20:14:52.092869 INFO: [APUAPC] D6_APC_2: 0x3fffff
9710 20:14:52.095916 INFO: [APUAPC] D6_APC_3: 0x0
9711 20:14:52.098858 INFO: [APUAPC] D7_APC_0: 0xffffffff
9712 20:14:52.102310 INFO: [APUAPC] D7_APC_1: 0xffffffff
9713 20:14:52.106013 INFO: [APUAPC] D7_APC_2: 0x3fffff
9714 20:14:52.109450 INFO: [APUAPC] D7_APC_3: 0x0
9715 20:14:52.111651 INFO: [APUAPC] D8_APC_0: 0xffffffff
9716 20:14:52.115634 INFO: [APUAPC] D8_APC_1: 0xffffffff
9717 20:14:52.119280 INFO: [APUAPC] D8_APC_2: 0x3fffff
9718 20:14:52.122199 INFO: [APUAPC] D8_APC_3: 0x0
9719 20:14:52.125583 INFO: [APUAPC] D9_APC_0: 0xffffffff
9720 20:14:52.129017 INFO: [APUAPC] D9_APC_1: 0xffffffff
9721 20:14:52.133175 INFO: [APUAPC] D9_APC_2: 0x3fffff
9722 20:14:52.135599 INFO: [APUAPC] D9_APC_3: 0x0
9723 20:14:52.138520 INFO: [APUAPC] D10_APC_0: 0xffffffff
9724 20:14:52.142272 INFO: [APUAPC] D10_APC_1: 0xffffffff
9725 20:14:52.145744 INFO: [APUAPC] D10_APC_2: 0x3fffff
9726 20:14:52.148878 INFO: [APUAPC] D10_APC_3: 0x0
9727 20:14:52.152576 INFO: [APUAPC] D11_APC_0: 0xffffffff
9728 20:14:52.155860 INFO: [APUAPC] D11_APC_1: 0xffffffff
9729 20:14:52.158642 INFO: [APUAPC] D11_APC_2: 0x3fffff
9730 20:14:52.161792 INFO: [APUAPC] D11_APC_3: 0x0
9731 20:14:52.164892 INFO: [APUAPC] D12_APC_0: 0xffffffff
9732 20:14:52.168271 INFO: [APUAPC] D12_APC_1: 0xffffffff
9733 20:14:52.171579 INFO: [APUAPC] D12_APC_2: 0x3fffff
9734 20:14:52.174614 INFO: [APUAPC] D12_APC_3: 0x0
9735 20:14:52.178751 INFO: [APUAPC] D13_APC_0: 0xffffffff
9736 20:14:52.181283 INFO: [APUAPC] D13_APC_1: 0xffffffff
9737 20:14:52.184552 INFO: [APUAPC] D13_APC_2: 0x3fffff
9738 20:14:52.188515 INFO: [APUAPC] D13_APC_3: 0x0
9739 20:14:52.191283 INFO: [APUAPC] D14_APC_0: 0xffffffff
9740 20:14:52.194848 INFO: [APUAPC] D14_APC_1: 0xffffffff
9741 20:14:52.198444 INFO: [APUAPC] D14_APC_2: 0x3fffff
9742 20:14:52.202530 INFO: [APUAPC] D14_APC_3: 0x0
9743 20:14:52.204439 INFO: [APUAPC] D15_APC_0: 0xffffffff
9744 20:14:52.207859 INFO: [APUAPC] D15_APC_1: 0xffffffff
9745 20:14:52.211133 INFO: [APUAPC] D15_APC_2: 0x3fffff
9746 20:14:52.214728 INFO: [APUAPC] D15_APC_3: 0x0
9747 20:14:52.217714 INFO: [APUAPC] APC_CON: 0x4
9748 20:14:52.221303 INFO: [NOCDAPC] D0_APC_0: 0x0
9749 20:14:52.224819 INFO: [NOCDAPC] D0_APC_1: 0x0
9750 20:14:52.228232 INFO: [NOCDAPC] D1_APC_0: 0x0
9751 20:14:52.230957 INFO: [NOCDAPC] D1_APC_1: 0xfff
9752 20:14:52.231539 INFO: [NOCDAPC] D2_APC_0: 0x0
9753 20:14:52.234133 INFO: [NOCDAPC] D2_APC_1: 0xfff
9754 20:14:52.237748 INFO: [NOCDAPC] D3_APC_0: 0x0
9755 20:14:52.241361 INFO: [NOCDAPC] D3_APC_1: 0xfff
9756 20:14:52.245416 INFO: [NOCDAPC] D4_APC_0: 0x0
9757 20:14:52.247956 INFO: [NOCDAPC] D4_APC_1: 0xfff
9758 20:14:52.250948 INFO: [NOCDAPC] D5_APC_0: 0x0
9759 20:14:52.254944 INFO: [NOCDAPC] D5_APC_1: 0xfff
9760 20:14:52.257398 INFO: [NOCDAPC] D6_APC_0: 0x0
9761 20:14:52.261944 INFO: [NOCDAPC] D6_APC_1: 0xfff
9762 20:14:52.264504 INFO: [NOCDAPC] D7_APC_0: 0x0
9763 20:14:52.265125 INFO: [NOCDAPC] D7_APC_1: 0xfff
9764 20:14:52.267143 INFO: [NOCDAPC] D8_APC_0: 0x0
9765 20:14:52.271289 INFO: [NOCDAPC] D8_APC_1: 0xfff
9766 20:14:52.273682 INFO: [NOCDAPC] D9_APC_0: 0x0
9767 20:14:52.277708 INFO: [NOCDAPC] D9_APC_1: 0xfff
9768 20:14:52.280673 INFO: [NOCDAPC] D10_APC_0: 0x0
9769 20:14:52.284261 INFO: [NOCDAPC] D10_APC_1: 0xfff
9770 20:14:52.287408 INFO: [NOCDAPC] D11_APC_0: 0x0
9771 20:14:52.291270 INFO: [NOCDAPC] D11_APC_1: 0xfff
9772 20:14:52.294441 INFO: [NOCDAPC] D12_APC_0: 0x0
9773 20:14:52.296984 INFO: [NOCDAPC] D12_APC_1: 0xfff
9774 20:14:52.300899 INFO: [NOCDAPC] D13_APC_0: 0x0
9775 20:14:52.304537 INFO: [NOCDAPC] D13_APC_1: 0xfff
9776 20:14:52.307166 INFO: [NOCDAPC] D14_APC_0: 0x0
9777 20:14:52.310623 INFO: [NOCDAPC] D14_APC_1: 0xfff
9778 20:14:52.311220 INFO: [NOCDAPC] D15_APC_0: 0x0
9779 20:14:52.314733 INFO: [NOCDAPC] D15_APC_1: 0xfff
9780 20:14:52.316761 INFO: [NOCDAPC] APC_CON: 0x4
9781 20:14:52.320331 INFO: [APUAPC] set_apusys_apc done
9782 20:14:52.323489 INFO: [DEVAPC] devapc_init done
9783 20:14:52.327505 INFO: GICv3 without legacy support detected.
9784 20:14:52.334248 INFO: ARM GICv3 driver initialized in EL3
9785 20:14:52.337621 INFO: Maximum SPI INTID supported: 639
9786 20:14:52.340902 INFO: BL31: Initializing runtime services
9787 20:14:52.347208 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9788 20:14:52.350443 INFO: SPM: enable CPC mode
9789 20:14:52.353557 INFO: mcdi ready for mcusys-off-idle and system suspend
9790 20:14:52.360395 INFO: BL31: Preparing for EL3 exit to normal world
9791 20:14:52.363889 INFO: Entry point address = 0x80000000
9792 20:14:52.364472 INFO: SPSR = 0x8
9793 20:14:52.369691
9794 20:14:52.370251
9795 20:14:52.370621
9796 20:14:52.373385 Starting depthcharge on Spherion...
9797 20:14:52.373852
9798 20:14:52.374221 Wipe memory regions:
9799 20:14:52.374564
9800 20:14:52.377283 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9801 20:14:52.377834 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9802 20:14:52.378287 Setting prompt string to ['asurada:']
9803 20:14:52.378999 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9804 20:14:52.379760 [0x00000040000000, 0x00000054600000)
9805 20:14:52.498833
9806 20:14:52.499436 [0x00000054660000, 0x00000080000000)
9807 20:14:52.759315
9808 20:14:52.759918 [0x000000821a7280, 0x000000ffe64000)
9809 20:14:53.504581
9810 20:14:53.505199 [0x00000100000000, 0x00000140000000)
9811 20:14:53.885053
9812 20:14:53.888584 Initializing XHCI USB controller at 0x11200000.
9813 20:14:54.926901
9814 20:14:54.929872 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9815 20:14:54.930388
9816 20:14:54.930720
9817 20:14:54.931032
9818 20:14:54.931795 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9820 20:14:55.033022 asurada: tftpboot 192.168.201.1 12928117/tftp-deploy-_x39tgoc/kernel/image.itb 12928117/tftp-deploy-_x39tgoc/kernel/cmdline
9821 20:14:55.033668 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9822 20:14:55.034125 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9823 20:14:55.040345 tftpboot 192.168.201.1 12928117/tftp-deploy-_x39tgoc/kernel/image.itbtp-deploy-_x39tgoc/kernel/cmdline
9824 20:14:55.040960
9825 20:14:55.041334 Waiting for link
9826 20:14:55.200101
9827 20:14:55.200653 R8152: Initializing
9828 20:14:55.201131
9829 20:14:55.202479 Version 9 (ocp_data = 6010)
9830 20:14:55.202962
9831 20:14:55.206649 R8152: Done initializing
9832 20:14:55.207222
9833 20:14:55.207592 Adding net device
9834 20:14:57.088163
9835 20:14:57.088701 done.
9836 20:14:57.089131
9837 20:14:57.089452 MAC: 00:e0:4c:68:03:bd
9838 20:14:57.089788
9839 20:14:57.091367 Sending DHCP discover... done.
9840 20:14:57.091824
9841 20:15:06.825170 Waiting for reply... R8152: Bulk read error 0xffffffbf
9842 20:15:06.825774
9843 20:15:06.828451 Receive failed.
9844 20:15:06.829074
9845 20:15:06.829515 done.
9846 20:15:06.829866
9847 20:15:06.831020 Sending DHCP request... done.
9848 20:15:06.831431
9849 20:15:06.835395 Waiting for reply... done.
9850 20:15:06.835987
9851 20:15:06.837962 My ip is 192.168.201.16
9852 20:15:06.838439
9853 20:15:06.841773 The DHCP server ip is 192.168.201.1
9854 20:15:06.842348
9855 20:15:06.844689 TFTP server IP predefined by user: 192.168.201.1
9856 20:15:06.845195
9857 20:15:06.852434 Bootfile predefined by user: 12928117/tftp-deploy-_x39tgoc/kernel/image.itb
9858 20:15:06.853049
9859 20:15:06.854513 Sending tftp read request... done.
9860 20:15:06.854981
9861 20:15:06.862446 Waiting for the transfer...
9862 20:15:06.863021
9863 20:15:07.180958 00000000 ################################################################
9864 20:15:07.181102
9865 20:15:07.467114 00080000 ################################################################
9866 20:15:07.467254
9867 20:15:07.750369 00100000 ################################################################
9868 20:15:07.750517
9869 20:15:08.029243 00180000 ################################################################
9870 20:15:08.029411
9871 20:15:08.333132 00200000 ################################################################
9872 20:15:08.333281
9873 20:15:08.614937 00280000 ################################################################
9874 20:15:08.615074
9875 20:15:08.896986 00300000 ################################################################
9876 20:15:08.897122
9877 20:15:09.170432 00380000 ################################################################
9878 20:15:09.170568
9879 20:15:09.422817 00400000 ################################################################
9880 20:15:09.422954
9881 20:15:09.672561 00480000 ################################################################
9882 20:15:09.672720
9883 20:15:09.924467 00500000 ################################################################
9884 20:15:09.924600
9885 20:15:10.174250 00580000 ################################################################
9886 20:15:10.174390
9887 20:15:10.425460 00600000 ################################################################
9888 20:15:10.425602
9889 20:15:10.676044 00680000 ################################################################
9890 20:15:10.676179
9891 20:15:10.927164 00700000 ################################################################
9892 20:15:10.927311
9893 20:15:11.178470 00780000 ################################################################
9894 20:15:11.178621
9895 20:15:11.429717 00800000 ################################################################
9896 20:15:11.429858
9897 20:15:11.680263 00880000 ################################################################
9898 20:15:11.680398
9899 20:15:11.931007 00900000 ################################################################
9900 20:15:11.931132
9901 20:15:12.187355 00980000 ################################################################
9902 20:15:12.187489
9903 20:15:12.438352 00a00000 ################################################################
9904 20:15:12.438487
9905 20:15:12.688402 00a80000 ################################################################
9906 20:15:12.688558
9907 20:15:12.939946 00b00000 ################################################################
9908 20:15:12.940079
9909 20:15:13.191796 00b80000 ################################################################
9910 20:15:13.191928
9911 20:15:13.442379 00c00000 ################################################################
9912 20:15:13.442511
9913 20:15:13.694195 00c80000 ################################################################
9914 20:15:13.694333
9915 20:15:13.946708 00d00000 ################################################################
9916 20:15:13.946839
9917 20:15:14.196627 00d80000 ################################################################
9918 20:15:14.196803
9919 20:15:14.447429 00e00000 ################################################################
9920 20:15:14.447560
9921 20:15:14.698371 00e80000 ################################################################
9922 20:15:14.698507
9923 20:15:14.948948 00f00000 ################################################################
9924 20:15:14.949078
9925 20:15:15.199705 00f80000 ################################################################
9926 20:15:15.199838
9927 20:15:15.451254 01000000 ################################################################
9928 20:15:15.451380
9929 20:15:15.703254 01080000 ################################################################
9930 20:15:15.703386
9931 20:15:15.982740 01100000 ################################################################
9932 20:15:15.982876
9933 20:15:16.268871 01180000 ################################################################
9934 20:15:16.269001
9935 20:15:16.546536 01200000 ################################################################
9936 20:15:16.546669
9937 20:15:16.825939 01280000 ################################################################
9938 20:15:16.826075
9939 20:15:17.104475 01300000 ################################################################
9940 20:15:17.104605
9941 20:15:17.384466 01380000 ################################################################
9942 20:15:17.384594
9943 20:15:17.665095 01400000 ################################################################
9944 20:15:17.665234
9945 20:15:17.945681 01480000 ################################################################
9946 20:15:17.945818
9947 20:15:18.225942 01500000 ################################################################
9948 20:15:18.226076
9949 20:15:18.504872 01580000 ################################################################
9950 20:15:18.505022
9951 20:15:18.787545 01600000 ################################################################
9952 20:15:18.787707
9953 20:15:19.065557 01680000 ################################################################
9954 20:15:19.065686
9955 20:15:19.344096 01700000 ################################################################
9956 20:15:19.344236
9957 20:15:19.631952 01780000 ################################################################
9958 20:15:19.632088
9959 20:15:19.912953 01800000 ################################################################
9960 20:15:19.913089
9961 20:15:20.180137 01880000 ################################################################
9962 20:15:20.180282
9963 20:15:20.471455 01900000 ################################################################
9964 20:15:20.471591
9965 20:15:20.750476 01980000 ################################################################
9966 20:15:20.750611
9967 20:15:21.029395 01a00000 ################################################################
9968 20:15:21.029557
9969 20:15:21.296223 01a80000 ################################################################
9970 20:15:21.296365
9971 20:15:21.547048 01b00000 ################################################################
9972 20:15:21.547186
9973 20:15:21.802740 01b80000 ################################################################
9974 20:15:21.802875
9975 20:15:22.054371 01c00000 ################################################################
9976 20:15:22.054501
9977 20:15:22.303976 01c80000 ################################################################
9978 20:15:22.304125
9979 20:15:22.528825 01d00000 ########################################################## done.
9980 20:15:22.528968
9981 20:15:22.530643 The bootfile was 30876150 bytes long.
9982 20:15:22.530821
9983 20:15:22.534253 Sending tftp read request... done.
9984 20:15:22.534440
9985 20:15:22.534540 Waiting for the transfer...
9986 20:15:22.534629
9987 20:15:22.537853 00000000 # done.
9988 20:15:22.538045
9989 20:15:22.544349 Command line loaded dynamically from TFTP file: 12928117/tftp-deploy-_x39tgoc/kernel/cmdline
9990 20:15:22.544521
9991 20:15:22.568023 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9992 20:15:22.568289
9993 20:15:22.568431 Loading FIT.
9994 20:15:22.568562
9995 20:15:22.570831 Image ramdisk-1 has 18766798 bytes.
9996 20:15:22.571126
9997 20:15:22.574181 Image fdt-1 has 47278 bytes.
9998 20:15:22.574431
9999 20:15:22.577031 Image kernel-1 has 12060038 bytes.
10000 20:15:22.577274
10001 20:15:22.588195 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10002 20:15:22.588694
10003 20:15:22.604821 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10004 20:15:22.605419
10005 20:15:22.610479 Choosing best match conf-1 for compat google,spherion-rev3.
10006 20:15:22.611054
10007 20:15:22.618330 Connected to device vid:did:rid of 1ae0:0028:00
10008 20:15:22.625336
10009 20:15:22.629583 tpm_get_response: command 0x17b, return code 0x0
10010 20:15:22.630159
10011 20:15:22.632047 ec_init: CrosEC protocol v3 supported (256, 248)
10012 20:15:22.636513
10013 20:15:22.639996 tpm_cleanup: add release locality here.
10014 20:15:22.640571
10015 20:15:22.640986 Shutting down all USB controllers.
10016 20:15:22.643056
10017 20:15:22.643460 Removing current net device
10018 20:15:22.643808
10019 20:15:22.649529 Exiting depthcharge with code 4 at timestamp: 58481695
10020 20:15:22.650010
10021 20:15:22.652816 LZMA decompressing kernel-1 to 0x821a6718
10022 20:15:22.653281
10023 20:15:22.656735 LZMA decompressing kernel-1 to 0x40000000
10024 20:15:24.154044
10025 20:15:24.154617 jumping to kernel
10026 20:15:24.156890 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10027 20:15:24.157498 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10028 20:15:24.158136 Setting prompt string to ['Linux version [0-9]']
10029 20:15:24.158564 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 20:15:24.158952 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10031 20:15:24.205522
10032 20:15:24.209006 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10033 20:15:24.212598 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10034 20:15:24.213245 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10035 20:15:24.213639 Setting prompt string to []
10036 20:15:24.214058 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10037 20:15:24.214450 Using line separator: #'\n'#
10038 20:15:24.214779 No login prompt set.
10039 20:15:24.215102 Parsing kernel messages
10040 20:15:24.215478 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10041 20:15:24.216057 [login-action] Waiting for messages, (timeout 00:03:54)
10042 20:15:24.216413 Waiting using forced prompt support (timeout 00:01:57)
10043 20:15:24.233208 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10044 20:15:24.236501 [ 0.000000] random: crng init done
10045 20:15:24.242201 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10046 20:15:24.244787 [ 0.000000] efi: UEFI not found.
10047 20:15:24.251746 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10048 20:15:24.261603 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10049 20:15:24.272104 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10050 20:15:24.278437 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10051 20:15:24.284648 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10052 20:15:24.291600 [ 0.000000] printk: bootconsole [mtk8250] enabled
10053 20:15:24.298202 [ 0.000000] NUMA: No NUMA configuration found
10054 20:15:24.305387 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10055 20:15:24.311182 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10056 20:15:24.311652 [ 0.000000] Zone ranges:
10057 20:15:24.318304 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10058 20:15:24.321116 [ 0.000000] DMA32 empty
10059 20:15:24.328266 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10060 20:15:24.330939 [ 0.000000] Movable zone start for each node
10061 20:15:24.334585 [ 0.000000] Early memory node ranges
10062 20:15:24.341309 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10063 20:15:24.347952 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10064 20:15:24.354661 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10065 20:15:24.361278 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10066 20:15:24.367391 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10067 20:15:24.374573 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10068 20:15:24.404450 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10069 20:15:24.411013 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10070 20:15:24.417982 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10071 20:15:24.421131 [ 0.000000] psci: probing for conduit method from DT.
10072 20:15:24.427336 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10073 20:15:24.430712 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10074 20:15:24.437768 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10075 20:15:24.441202 [ 0.000000] psci: SMC Calling Convention v1.2
10076 20:15:24.447535 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10077 20:15:24.450396 [ 0.000000] Detected VIPT I-cache on CPU0
10078 20:15:24.457335 [ 0.000000] CPU features: detected: GIC system register CPU interface
10079 20:15:24.464551 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10080 20:15:24.470356 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10081 20:15:24.476955 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10082 20:15:24.488219 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10083 20:15:24.494078 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10084 20:15:24.497553 [ 0.000000] alternatives: applying boot alternatives
10085 20:15:24.503524 [ 0.000000] Fallback order for Node 0: 0
10086 20:15:24.511192 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10087 20:15:24.514229 [ 0.000000] Policy zone: Normal
10088 20:15:24.536988 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10089 20:15:24.546323 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10090 20:15:24.556224 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10091 20:15:24.563402 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10092 20:15:24.569557 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10093 20:15:24.577162 <6>[ 0.000000] software IO TLB: area num 8.
10094 20:15:24.631070 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10095 20:15:24.712110 <6>[ 0.000000] Memory: 3834456K/4191232K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 324008K reserved, 32768K cma-reserved)
10096 20:15:24.717957 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10097 20:15:24.725042 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10098 20:15:24.728160 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10099 20:15:24.734877 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10100 20:15:24.741626 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10101 20:15:24.745098 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10102 20:15:24.754347 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10103 20:15:24.760930 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10104 20:15:24.767528 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10105 20:15:24.774284 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10106 20:15:24.777431 <6>[ 0.000000] GICv3: 608 SPIs implemented
10107 20:15:24.781367 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10108 20:15:24.787331 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10109 20:15:24.790525 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10110 20:15:24.797468 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10111 20:15:24.810174 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10112 20:15:24.823309 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10113 20:15:24.830059 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10114 20:15:24.837683 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10115 20:15:24.851349 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10116 20:15:24.857446 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10117 20:15:24.864368 <6>[ 0.009228] Console: colour dummy device 80x25
10118 20:15:24.874368 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10119 20:15:24.881555 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10120 20:15:24.884606 <6>[ 0.029300] LSM: Security Framework initializing
10121 20:15:24.891822 <6>[ 0.034212] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10122 20:15:24.900593 <6>[ 0.041817] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10123 20:15:24.907368 <6>[ 0.051040] cblist_init_generic: Setting adjustable number of callback queues.
10124 20:15:24.913998 <6>[ 0.058482] cblist_init_generic: Setting shift to 3 and lim to 1.
10125 20:15:24.924181 <6>[ 0.064821] cblist_init_generic: Setting adjustable number of callback queues.
10126 20:15:24.927860 <6>[ 0.072249] cblist_init_generic: Setting shift to 3 and lim to 1.
10127 20:15:24.934744 <6>[ 0.078688] rcu: Hierarchical SRCU implementation.
10128 20:15:24.941457 <6>[ 0.078690] rcu: Max phase no-delay instances is 1000.
10129 20:15:24.947107 <6>[ 0.078714] printk: bootconsole [mtk8250] printing thread started
10130 20:15:24.953713 <6>[ 0.097040] EFI services will not be available.
10131 20:15:24.957552 <6>[ 0.097241] smp: Bringing up secondary CPUs ...
10132 20:15:24.960286 <6>[ 0.097551] Detected VIPT I-cache on CPU1
10133 20:15:24.970348 <6>[ 0.097619] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10134 20:15:24.976766 <6>[ 0.097650] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10135 20:15:24.985623 <6>[ 0.125491] Detected VIPT I-cache on CPU2
10136 20:15:24.992913 <6>[ 0.125537] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10137 20:15:24.999246 <6>[ 0.125551] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10138 20:15:25.005560 <6>[ 0.125806] Detected VIPT I-cache on CPU3
10139 20:15:25.011983 <6>[ 0.125852] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10140 20:15:25.019637 <6>[ 0.125865] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10141 20:15:25.021756 <6>[ 0.126177] CPU features: detected: Spectre-v4
10142 20:15:25.028688 <6>[ 0.126184] CPU features: detected: Spectre-BHB
10143 20:15:25.031604 <6>[ 0.126189] Detected PIPT I-cache on CPU4
10144 20:15:25.038549 <6>[ 0.126249] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10145 20:15:25.044958 <6>[ 0.126266] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10146 20:15:25.051186 <6>[ 0.126560] Detected PIPT I-cache on CPU5
10147 20:15:25.057856 <6>[ 0.126623] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10148 20:15:25.064408 <6>[ 0.126639] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10149 20:15:25.067816 <6>[ 0.126915] Detected PIPT I-cache on CPU6
10150 20:15:25.075206 <6>[ 0.126977] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10151 20:15:25.084530 <6>[ 0.126993] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10152 20:15:25.088175 <6>[ 0.127287] Detected PIPT I-cache on CPU7
10153 20:15:25.094601 <6>[ 0.127353] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10154 20:15:25.101303 <6>[ 0.127369] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10155 20:15:25.104627 <6>[ 0.127416] smp: Brought up 1 node, 8 CPUs
10156 20:15:25.110526 <6>[ 0.127420] SMP: Total of 8 processors activated.
10157 20:15:25.114726 <6>[ 0.127423] CPU features: detected: 32-bit EL0 Support
10158 20:15:25.124133 <6>[ 0.127425] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10159 20:15:25.131182 <6>[ 0.127428] CPU features: detected: Common not Private translations
10160 20:15:25.137448 <6>[ 0.127430] CPU features: detected: CRC32 instructions
10161 20:15:25.143390 <6>[ 0.127433] CPU features: detected: RCpc load-acquire (LDAPR)
10162 20:15:25.146796 <6>[ 0.127434] CPU features: detected: LSE atomic instructions
10163 20:15:25.153423 <6>[ 0.127436] CPU features: detected: Privileged Access Never
10164 20:15:25.160283 <6>[ 0.127437] CPU features: detected: RAS Extension Support
10165 20:15:25.166507 <6>[ 0.127440] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10166 20:15:25.169874 <6>[ 0.127506] CPU: All CPU(s) started at EL2
10167 20:15:25.176515 <6>[ 0.127507] alternatives: applying system-wide alternatives
10168 20:15:25.202672 �� SH�<6>[ 0.3471<68] printk: console [ttyS0] printing thread started
10169 20:15:25.211627 6>[ 0.224358] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10170 20:15:25.215112 <6>[ 0.347179] printk: console [ttyS0] enabled
10171 20:15:25.218939 <6>[ 0.347183] printk: bootconsole [mtk8250] disabled
10172 20:15:25.224851 <6>[ 0.360155] printk: bootconsole [mtk8250] printing thread stopped
10173 20:15:25.231552 <6>[ 0.361415] SuperH (H)SCI(F) driver initialized
10174 20:15:25.235257 <6>[ 0.361921] msm_serial: driver initialized
10175 20:15:25.244838 <6>[ 0.366635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10176 20:15:25.251156 <6>[ 0.366665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10177 20:15:25.261496 <6>[ 0.366694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10178 20:15:25.271369 <6>[ 0.366724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10179 20:15:25.281440 <6>[ 0.366745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10180 20:15:25.291460 <6>[ 0.366773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10181 20:15:25.295280 <6>[ 0.366800] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10182 20:15:25.315587 <6>[ 0.366924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10183 20:15:25.320440 <6>[ 0.366953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10184 20:15:25.321063 <6>[ 0.380105] loop: module loaded
10185 20:15:25.325596 <6>[ 0.382663] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10186 20:15:25.329716 <4>[ 0.407108] mtk-pmic-keys: Failed to locate of_node [id: -1]
10187 20:15:25.336599 <6>[ 0.408181] megasas: 07.719.03.00-rc1
10188 20:15:25.340148 <6>[ 0.420947] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10189 20:15:25.343424 <6>[ 0.423663] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10190 20:15:25.350430 <6>[ 0.435892] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10191 20:15:25.363241 <6>[ 0.487899] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10192 20:15:25.875273 <6>[ 1.018678] Freeing initrd memory: 18320K
10193 20:15:25.883106 <6>[ 1.026156] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10194 20:15:25.890781 <6>[ 1.031074] tun: Universal TUN/TAP device driver, 1.6
10195 20:15:25.893156 <6>[ 1.031861] thunder_xcv, ver 1.0
10196 20:15:25.898008 <6>[ 1.031880] thunder_bgx, ver 1.0
10197 20:15:25.899648 <6>[ 1.031893] nicpf, ver 1.0
10198 20:15:25.907012 <6>[ 1.032986] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10199 20:15:25.913293 <6>[ 1.032989] hns3: Copyright (c) 2017 Huawei Corporation.
10200 20:15:25.916165 <6>[ 1.033015] hclge is initializing
10201 20:15:25.922870 <6>[ 1.033028] e1000: Intel(R) PRO/1000 Network Driver
10202 20:15:25.927239 <6>[ 1.033030] e1000: Copyright (c) 1999-2006 Intel Corporation.
10203 20:15:25.934615 <6>[ 1.033048] e1000e: Intel(R) PRO/1000 Network Driver
10204 20:15:25.937978 <6>[ 1.033049] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10205 20:15:25.944181 <6>[ 1.033067] igb: Intel(R) Gigabit Ethernet Network Driver
10206 20:15:25.951281 <6>[ 1.033069] igb: Copyright (c) 2007-2014 Intel Corporation.
10207 20:15:25.958418 <6>[ 1.033084] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10208 20:15:25.961448 <6>[ 1.033086] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10209 20:15:25.968144 <6>[ 1.033376] sky2: driver version 1.30
10210 20:15:25.971659 <6>[ 1.034485] VFIO - User Level meta-driver version: 0.3
10211 20:15:25.977966 <6>[ 1.037357] usbcore: registered new interface driver usb-storage
10212 20:15:25.985187 <6>[ 1.037536] usbcore: registered new device driver onboard-usb-hub
10213 20:15:25.992495 <6>[ 1.040397] mt6397-rtc mt6359-rtc: registered as rtc0
10214 20:15:25.998307 <6>[ 1.040555] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:15:26 UTC (1709496926)
10215 20:15:26.005441 <6>[ 1.041182] i2c_dev: i2c /dev entries driver
10216 20:15:26.011632 <6>[ 1.048529] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10217 20:15:26.017755 <6>[ 1.064517] cpu cpu0: EM: created perf domain
10218 20:15:26.022246 <6>[ 1.064829] cpu cpu4: EM: created perf domain
10219 20:15:26.028174 <6>[ 1.066448] sdhci: Secure Digital Host Controller Interface driver
10220 20:15:26.031069 <6>[ 1.066450] sdhci: Copyright(c) Pierre Ossman
10221 20:15:26.038716 <6>[ 1.066772] Synopsys Designware Multimedia Card Interface Driver
10222 20:15:26.044459 <6>[ 1.067099] sdhci-pltfm: SDHCI platform and OF driver helper
10223 20:15:26.050917 <6>[ 1.071456] ledtrig-cpu: registered to indicate activity on CPUs
10224 20:15:26.054807 <6>[ 1.072169] mmc0: CQHCI version 5.10
10225 20:15:26.060671 <6>[ 1.072219] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10226 20:15:26.067287 <6>[ 1.072487] usbcore: registered new interface driver usbhid
10227 20:15:26.072125 <6>[ 1.072489] usbhid: USB HID core driver
10228 20:15:26.077664 <6>[ 1.072598] spi_master spi0: will run message pump with realtime priority
10229 20:15:26.090517 <6>[ 1.100812] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10230 20:15:26.104080 <6>[ 1.102820] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10231 20:15:26.111087 <6>[ 1.103651] cros-ec-spi spi0.0: Chrome EC device registered
10232 20:15:26.120274 <6>[ 1.114791] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10233 20:15:26.123580 <6>[ 1.115649] NET: Registered PF_PACKET protocol family
10234 20:15:26.130689 <6>[ 1.115721] 9pnet: Installing 9P2000 support
10235 20:15:26.134175 <5>[ 1.115754] Key type dns_resolver registered
10236 20:15:26.137200 <6>[ 1.116068] registered taskstats version 1
10237 20:15:26.143925 <5>[ 1.116083] Loading compiled-in X.509 certificates
10238 20:15:26.153868 <4>[ 1.131523] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10239 20:15:26.163765 <4>[ 1.131665] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10240 20:15:26.170079 <3>[ 1.131676] debugfs: File 'uA_load' in directory '/' already present!
10241 20:15:26.176883 <3>[ 1.131683] debugfs: File 'min_uV' in directory '/' already present!
10242 20:15:26.184452 <3>[ 1.131686] debugfs: File 'max_uV' in directory '/' already present!
10243 20:15:26.190102 <3>[ 1.131690] debugfs: File 'constraint_flags' in directory '/' already present!
10244 20:15:26.199934 <3>[ 1.133659] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10245 20:15:26.206723 <6>[ 1.141090] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10246 20:15:26.209810 <6>[ 1.141699] xhci-mtk 11200000.usb: xHCI Host Controller
10247 20:15:26.220412 <6>[ 1.141719] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10248 20:15:26.229733 <6>[ 1.141976] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10249 20:15:26.233467 <6>[ 1.142029] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10250 20:15:26.239774 <6>[ 1.142149] xhci-mtk 11200000.usb: xHCI Host Controller
10251 20:15:26.246733 <6>[ 1.142159] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10252 20:15:26.256460 <6>[ 1.142168] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10253 20:15:26.259229 <6>[ 1.143111] hub 1-0:1.0: USB hub found
10254 20:15:26.263161 <6>[ 1.143135] hub 1-0:1.0: 1 port detected
10255 20:15:26.272627 <6>[ 1.143508] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10256 20:15:26.276419 <6>[ 1.143769] hub 2-0:1.0: USB hub found
10257 20:15:26.279110 <6>[ 1.143783] hub 2-0:1.0: 1 port detected
10258 20:15:26.282518 <6>[ 1.146870] mtk-msdc 11f70000.mmc: Got CD GPIO
10259 20:15:26.293942 <6>[ 1.153571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10260 20:15:26.298862 <6>[ 1.153579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10261 20:15:26.309462 <4>[ 1.153663] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10262 20:15:26.315270 <6>[ 1.154151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10263 20:15:26.325452 <6>[ 1.154152] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10264 20:15:26.332330 <6>[ 1.154485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10265 20:15:26.341715 <6>[ 1.154497] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10266 20:15:26.348630 <6>[ 1.154500] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10267 20:15:26.358652 <6>[ 1.154504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10268 20:15:26.365224 <6>[ 1.155717] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10269 20:15:26.374943 <6>[ 1.155728] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10270 20:15:26.381904 <6>[ 1.155731] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10271 20:15:26.392335 <6>[ 1.155733] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10272 20:15:26.398199 <6>[ 1.155736] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10273 20:15:26.407795 <6>[ 1.155738] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10274 20:15:26.414721 <6>[ 1.155741] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10275 20:15:26.424648 <6>[ 1.155743] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10276 20:15:26.431352 <6>[ 1.155745] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10277 20:15:26.440942 <6>[ 1.155747] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10278 20:15:26.450989 <6>[ 1.155750] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10279 20:15:26.457635 <6>[ 1.155752] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10280 20:15:26.467271 <6>[ 1.155754] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10281 20:15:26.474018 <6>[ 1.155757] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10282 20:15:26.483839 <6>[ 1.155759] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10283 20:15:26.490854 <6>[ 1.156176] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10284 20:15:26.497333 <6>[ 1.157009] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10285 20:15:26.503595 <6>[ 1.157402] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10286 20:15:26.510491 <6>[ 1.157735] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10287 20:15:26.517256 <6>[ 1.158050] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10288 20:15:26.523718 <6>[ 1.158223] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10289 20:15:26.533249 <6>[ 1.158234] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10290 20:15:26.543802 <6>[ 1.158236] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10291 20:15:26.552768 <6>[ 1.158239] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10292 20:15:26.563430 <6>[ 1.158243] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10293 20:15:26.570571 <6>[ 1.158246] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10294 20:15:26.579250 <6>[ 1.158249] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10295 20:15:26.589963 <6>[ 1.158251] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10296 20:15:26.599897 <6>[ 1.158254] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10297 20:15:26.609302 <6>[ 1.158258] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10298 20:15:26.618882 <6>[ 1.158261] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10299 20:15:26.629169 <6>[ 1.159048] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10300 20:15:26.632123 <6>[ 1.166359] mmc0: Command Queue Engine enabled
10301 20:15:26.639404 <6>[ 1.166375] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10302 20:15:26.642411 <6>[ 1.166989] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10303 20:15:26.649291 <6>[ 1.171023] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10304 20:15:26.655792 <6>[ 1.172094] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10305 20:15:26.658389 <6>[ 1.172681] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10306 20:15:26.665673 <6>[ 1.173216] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10307 20:15:26.673109 <6>[ 1.180927] Trying to probe devices needed for running init ...
10308 20:15:26.678991 <6>[ 1.528668] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10309 20:15:26.682293 <6>[ 1.559353] hub 2-1:1.0: USB hub found
10310 20:15:26.688543 <6>[ 1.559704] hub 2-1:1.0: 3 ports detected
10311 20:15:26.691771 <6>[ 1.561805] hub 2-1:1.0: USB hub found
10312 20:15:26.695074 <6>[ 1.562139] hub 2-1:1.0: 3 ports detected
10313 20:15:26.701649 <6>[ 1.680496] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10314 20:15:26.708234 <6>[ 1.833270] hub 1-1:1.0: USB hub found
10315 20:15:26.711717 <6>[ 1.833636] hub 1-1:1.0: 4 ports detected
10316 20:15:26.715640 <6>[ 1.836942] hub 1-1:1.0: USB hub found
10317 20:15:26.717930 <6>[ 1.837364] hub 1-1:1.0: 4 ports detected
10318 20:15:26.774624 <6>[ 1.912760] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10319 20:15:27.011400 <6>[ 2.148531] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10320 20:15:27.135231 <6>[ 2.276416] hub 1-1.4:1.0: USB hub found
10321 20:15:27.138655 <6>[ 2.276871] hub 1-1.4:1.0: 2 ports detected
10322 20:15:27.142179 <6>[ 2.280318] hub 1-1.4:1.0: USB hub found
10323 20:15:27.148770 <6>[ 2.280756] hub 1-1.4:1.0: 2 ports detected
10324 20:15:27.430798 <6>[ 2.568523] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10325 20:15:27.614535 <6>[ 2.752519] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10326 20:15:38.326778 <6>[ 13.473761] ALSA device list:
10327 20:15:38.333281 <6>[ 13.473900] No soundcards found.
10328 20:15:38.336857 <6>[ 13.477976] Freeing unused kernel memory: 8448K
10329 20:15:38.340246 <6>[ 13.478087] Run /init as init process
10330 20:15:38.343814 Loading, please wait...
10331 20:15:38.369826 Starting systemd-udevd version 252.22-1~deb12u1
10332 20:15:38.370431
10333 20:15:38.584172 <6>[ 13.721543] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10334 20:15:38.587420 <6>[ 13.725851] remoteproc remoteproc0: scp is available
10335 20:15:38.594626 <6>[ 13.726108] remoteproc remoteproc0: powering up scp
10336 20:15:38.604160 <6>[ 13.726121] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10337 20:15:38.607222 <6>[ 13.726205] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10338 20:15:38.621546 <6>[ 13.764041] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10339 20:15:38.631629 <6>[ 13.764086] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10340 20:15:38.637724 <6>[ 13.764092] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10341 20:15:38.648216 <3>[ 13.783833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10342 20:15:38.654175 <3>[ 13.783862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10343 20:15:38.664032 <3>[ 13.783874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10344 20:15:38.672031 <3>[ 13.783951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10345 20:15:38.680574 <3>[ 13.783959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10346 20:15:38.687394 <3>[ 13.783966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10347 20:15:38.696988 <3>[ 13.783976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10348 20:15:38.703421 <3>[ 13.783983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10349 20:15:38.713829 <3>[ 13.784019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10350 20:15:38.720402 <3>[ 13.784070] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10351 20:15:38.730983 <3>[ 13.784078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10352 20:15:38.737157 <3>[ 13.784085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10353 20:15:38.745436 <3>[ 13.784133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10354 20:15:38.754492 <3>[ 13.784141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10355 20:15:38.761482 <3>[ 13.784148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10356 20:15:38.768616 <3>[ 13.784156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10357 20:15:38.778476 <3>[ 13.784162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10358 20:15:38.781111 <6>[ 13.790385] mc: Linux media interface: v0.10
10359 20:15:38.787867 <6>[ 13.791169] usbcore: registered new device driver r8152-cfgselector
10360 20:15:38.797959 <3>[ 13.799552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10361 20:15:38.800566 <6>[ 13.817326] videodev: Linux video capture interface: v2.00
10362 20:15:38.810605 <6>[ 13.829515] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10363 20:15:38.815207 <6>[ 13.832433] Bluetooth: Core ver 2.22
10364 20:15:38.821121 <6>[ 13.833203] NET: Registered PF_BLUETOOTH protocol family
10365 20:15:38.827019 <6>[ 13.833209] Bluetooth: HCI device and connection manager initialized
10366 20:15:38.830407 <6>[ 13.833230] Bluetooth: HCI socket layer initialized
10367 20:15:38.836921 <6>[ 13.833240] Bluetooth: L2CAP socket layer initialized
10368 20:15:38.840430 <6>[ 13.833259] Bluetooth: SCO socket layer initialized
10369 20:15:38.851294 <4>[ 13.836634] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10370 20:15:38.856925 <4>[ 13.846760] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10371 20:15:38.863402 <6>[ 13.851589] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10372 20:15:38.870162 <6>[ 13.856161] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10373 20:15:38.877601 <6>[ 13.856182] remoteproc remoteproc0: remote processor scp is now up
10374 20:15:38.886975 <4>[ 13.857228] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10375 20:15:38.893198 <4>[ 13.857228] Fallback method does not support PEC.
10376 20:15:38.899871 <3>[ 13.872886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10377 20:15:38.906340 <6>[ 13.901690] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10378 20:15:38.912991 <6>[ 13.901717] pci_bus 0000:00: root bus resource [bus 00-ff]
10379 20:15:38.919527 <6>[ 13.901723] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10380 20:15:38.929920 <6>[ 13.901730] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10381 20:15:38.936268 <6>[ 13.901765] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10382 20:15:38.943119 <6>[ 13.901785] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10383 20:15:38.949594 <6>[ 13.901860] pci 0000:00:00.0: supports D1 D2
10384 20:15:38.956497 <6>[ 13.901863] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10385 20:15:38.962942 <6>[ 13.903442] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10386 20:15:38.969586 <6>[ 13.903576] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10387 20:15:38.976216 <6>[ 13.903609] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10388 20:15:38.985977 <6>[ 13.903631] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10389 20:15:38.991923 <6>[ 13.903649] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10390 20:15:38.995879 <6>[ 13.903780] pci 0000:01:00.0: supports D1 D2
10391 20:15:39.002956 <6>[ 13.903783] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10392 20:15:39.012557 <6>[ 13.905846] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10393 20:15:39.021754 <3>[ 13.906023] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10394 20:15:39.028922 <6>[ 13.907543] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10395 20:15:39.035564 <6>[ 13.916303] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10396 20:15:39.045642 <6>[ 13.916363] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10397 20:15:39.051832 <6>[ 13.916372] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10398 20:15:39.057988 <6>[ 13.916392] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10399 20:15:39.068217 <6>[ 13.916408] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10400 20:15:39.074941 <6>[ 13.916423] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10401 20:15:39.081603 <6>[ 13.916439] pci 0000:00:00.0: PCI bridge to [bus 01]
10402 20:15:39.088310 <6>[ 13.916447] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10403 20:15:39.095126 <6>[ 13.916578] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10404 20:15:39.101144 <6>[ 13.917483] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10405 20:15:39.108109 <6>[ 13.917817] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10406 20:15:39.114829 <6>[ 13.940775] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10407 20:15:39.124676 <6>[ 13.949674] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10408 20:15:39.134392 <6>[ 13.950035] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10409 20:15:39.144393 <6>[ 13.955099] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10410 20:15:39.155600 <4>[ 13.966426] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10411 20:15:39.161648 <4>[ 13.966476] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10412 20:15:39.167755 <6>[ 13.972148] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10413 20:15:39.180593 <6>[ 13.973269] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10414 20:15:39.187218 <6>[ 13.973363] usbcore: registered new interface driver uvcvideo
10415 20:15:39.195025 <5>[ 13.980177] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10416 20:15:39.201337 <5>[ 13.994816] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10417 20:15:39.210537 <5>[ 13.995027] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10418 20:15:39.220035 <4>[ 13.995086] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10419 20:15:39.223710 <6>[ 13.995092] cfg80211: failed to load regulatory.db
10420 20:15:39.230443 <6>[ 14.009503] usbcore: registered new interface driver btusb
10421 20:15:39.236899 <6>[ 14.009924] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10422 20:15:39.246764 <4>[ 14.011787] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10423 20:15:39.253063 <3>[ 14.011803] Bluetooth: hci0: Failed to load firmware file (-2)
10424 20:15:39.259573 <3>[ 14.011809] Bluetooth: hci0: Failed to set up firmware (-2)
10425 20:15:39.269643 <4>[ 14.011812] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10426 20:15:39.273030 <6>[ 14.016411] r8152 2-1.3:1.0 eth0: v1.12.13
10427 20:15:39.279804 <6>[ 14.016477] usbcore: registered new interface driver r8152
10428 20:15:39.286367 <6>[ 14.052326] usbcore: registered new interface driver cdc_ether
10429 20:15:39.289411 <6>[ 14.064797] usbcore: registered new interface driver r8153_ecm
10430 20:15:39.297508 <6>[ 14.088875] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10431 20:15:39.306058 <6>[ 14.110272] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10432 20:15:39.309245 <6>[ 14.110383] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10433 20:15:39.316397 <6>[ 14.128380] mt7921e 0000:01:00.0: ASIC revision: 79610010
10434 20:15:39.325643 <6>[ 14.223018] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10435 20:15:39.326221 <6>[ 14.223018]
10436 20:15:39.329678 Begin: Loading essential drivers ... done.
10437 20:15:39.342110 Begin: Running /scripts/init-premoun<6>[ 14.483604] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10438 20:15:39.342714 t ... done.
10439 20:15:39.348765 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10440 20:15:39.358344 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10441 20:15:39.362212 Device /sys/class/net/enx00e04c6803bd found
10442 20:15:39.365022 done.
10443 20:15:39.389641 Begin: Waiting up to 180 secs for any network device to become available ... done.
10444 20:15:39.441972 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10445 20:15:40.197942 <6>[ 15.340384] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10446 20:15:40.497962 <6>[ 15.643969] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10447 20:15:41.393881 IP-Config: no response after 2 secs - giving up
10448 20:15:41.445309 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10449 20:15:41.470476 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10450 20:15:42.186060 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10451 20:15:42.192887 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10452 20:15:42.199826 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10453 20:15:42.206019 host : mt8192-asurada-spherion-r0-cbg-4
10454 20:15:42.212318 domain : lava-rack
10455 20:15:42.219009 rootserver: 192.168.201.1 rootpath:
10456 20:15:42.219636 filename :
10457 20:15:42.332243 done.
10458 20:15:42.339856 Begin: Running /scripts/nfs-bottom ... done.
10459 20:15:42.360309 Begin: Running /scripts/init-bottom ... done.
10460 20:15:43.701904 <6>[ 18.847338] NET: Registered PF_INET6 protocol family
10461 20:15:43.704769 <6>[ 18.849071] Segment Routing with IPv6
10462 20:15:43.710689 <6>[ 18.849089] In-situ OAM (IOAM) with IPv6
10463 20:15:43.884603 <30>[ 19.001489] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10464 20:15:43.890583 <30>[ 19.001530] systemd[1]: Detected architecture arm64.
10465 20:15:43.891160
10466 20:15:43.897275 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10467 20:15:43.897837
10468 20:15:43.898205
10469 20:15:43.925726 <30>[ 19.070477] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10470 20:15:45.020348 <30>[ 20.162169] systemd[1]: Queued start job for default target graphical.target.
10471 20:15:45.053862 [[0;32m OK [0m] Created slic<30>[ 20.193803] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10472 20:15:45.057399 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10473 20:15:45.057872
10474 20:15:45.082212 [[0;32m OK [0m] Created slic<30>[ 20.222274] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10475 20:15:45.085462 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10476 20:15:45.088977
10477 20:15:45.110468 [[0;32m OK [0m] Created slic<30>[ 20.250312] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10478 20:15:45.117019 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10479 20:15:45.117599
10480 20:15:45.137705 [[0;32m OK [0m] Created slic<30>[ 20.277922] systemd[1]: Created slice user.slice - User and Session Slice.
10481 20:15:45.140648 e [0;1;39muser.slice[0m - User and Session Slice.
10482 20:15:45.141174
10483 20:15:45.168430 [[0;32m OK [0m] Started [0;<30>[ 20.305398] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10484 20:15:45.171767 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10485 20:15:45.172379
10486 20:15:45.196171 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 20.332768] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10487 20:15:45.199463 -passwo… Requests to Wall Directory Watch.
10488 20:15:45.200054
10489 20:15:45.233432 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 20.360708] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10490 20:15:45.240209 <30>[ 20.360837] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10491 20:15:45.244225 ice[0m - /dev/ttyS0...
10492 20:15:45.244695
10493 20:15:45.265127 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 20.404551] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10494 20:15:45.268262 tsetup.…get[0m - Local Encrypted Volumes.
10495 20:15:45.268875
10496 20:15:45.292012 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 20.428655] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10497 20:15:45.294987 grityse…Local Integrity Protected Volumes.
10498 20:15:45.295563
10499 20:15:45.316746 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 20.456641] systemd[1]: Reached target paths.target - Path Units.
10500 20:15:45.317332 s.target[0m - Path Units.
10501 20:15:45.317704
10502 20:15:45.340857 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 20.481111] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10503 20:15:45.344219 te-fs.target[0m - Remote File Systems.
10504 20:15:45.344687
10505 20:15:45.364984 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 20.504552] systemd[1]: Reached target slices.target - Slice Units.
10506 20:15:45.367584 es.target[0m - Slice Units.
10507 20:15:45.368054
10508 20:15:45.389000 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 20.529012] systemd[1]: Reached target swap.target - Swaps.
10509 20:15:45.389582 .target[0m - Swaps.
10510 20:15:45.389960
10511 20:15:45.412937 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 20.553061] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10512 20:15:45.419566 tysetup… - Local Verity Protected Volumes.
10513 20:15:45.420147
10514 20:15:45.440324 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.580971] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10515 20:15:45.447240 d-initc… initctl Compatibility Named Pipe.
10516 20:15:45.447801
10517 20:15:45.471116 [[0;32m OK [<30>[ 20.611563] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10518 20:15:45.478053 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10519 20:15:45.478651
10520 20:15:45.497845 [[0;32m OK [0m] Listening on<30>[ 20.638121] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10521 20:15:45.506889 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10522 20:15:45.507473
10523 20:15:45.524847 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.665278] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10524 20:15:45.527979 d-journald.socket[0m - Journal Socket.
10525 20:15:45.528447
10526 20:15:45.550978 [[0;32m OK [0m] Listening on<30>[ 20.690193] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10527 20:15:45.556504 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10528 20:15:45.557249
10529 20:15:45.576869 [[0;32m OK [<30>[ 20.719637] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10530 20:15:45.585833 0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10531 20:15:45.586431
10532 20:15:45.604593 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.745024] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10533 20:15:45.608179 d-udevd…l.socket[0m - udev Kernel Socket.
10534 20:15:45.611467
10535 20:15:45.665119 Mounting [0;1;39mdev-hugepages.mount[<30>[ 20.805001] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10536 20:15:45.668087 0m - Huge Pages File System...
10537 20:15:45.668565
10538 20:15:45.693866 Mounting [0;1;39mdev-m<30>[ 20.834163] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10539 20:15:45.697035 queue.mount…POSIX Message Queue File System...
10540 20:15:45.697535
10541 20:15:45.724788 Mounting [0;1;39msys-kernel-debug.…<30>[ 20.865053] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10542 20:15:45.728016 [0m - Kernel Debug File System...
10543 20:15:45.728503
10544 20:15:45.758985 <30>[ 20.893070] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10545 20:15:45.768954 <30>[ 20.899276] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10546 20:15:45.775409 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10547 20:15:45.775994
10548 20:15:45.802121 Starting [0;1;39mmodpr<30>[ 20.942531] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10549 20:15:45.805563 obe@configfs…m - Load Kernel Module configfs...
10550 20:15:45.806054
10551 20:15:45.834519 Starting [0;1;39mmodpr<30>[ 20.974590] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10552 20:15:45.837944 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10553 20:15:45.838570
10554 20:15:45.863994 Startin<30>[ 21.007809] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10555 20:15:45.870766 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10556 20:15:45.871253
10557 20:15:45.884357 <6>[ 21.025501] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10558 20:15:45.902651 Startin<30>[ 21.043014] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10559 20:15:45.906567 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10560 20:15:45.907056
10561 20:15:45.961007 Starting [0;1;39mmodprobe@fuse.ser…e<30>[ 21.101347] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10562 20:15:45.964191 [0m - Load Kernel Module fuse...
10563 20:15:45.964764
10564 20:15:45.991101 Startin<30>[ 21.134779] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10565 20:15:46.001473 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 21.145956] fuse: init (API version 7.37)
10566 20:15:46.001956 el Module loop...
10567 20:15:46.002327
10568 20:15:46.036552 Startin<30>[ 21.179115] systemd[1]: Starting systemd-journald.service - Journal Service...
10569 20:15:46.042305 g [0;1;39msystemd-journald.service[0m - Journal Service...
10570 20:15:46.042865
10571 20:15:46.088743 Starting [0;1;39msystemd-modules-l…r<30>[ 21.229223] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10572 20:15:46.092233 vice[0m - Load Kernel Modules...
10573 20:15:46.092700
10574 20:15:46.127528 <30>[ 21.267452] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10575 20:15:46.134282 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10576 20:15:46.134758
10577 20:15:46.167896 Startin<30>[ 21.307612] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10578 20:15:46.174275 g [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10579 20:15:46.174749
10580 20:15:46.237155 Starting [0;1;39msyste<30>[ 21.377496] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10581 20:15:46.240778 md-udev-trig…[0m - Coldplug All udev Devices...
10582 20:15:46.241265
10583 20:15:46.252829 <3>[ 21.393761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10584 20:15:46.268696 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepag<30>[ 21.408914] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10585 20:15:46.271619 es.mount[0m - Huge Pages File System.
10586 20:15:46.272084
10587 20:15:46.288412 <3>[ 21.428530] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10588 20:15:46.301747 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<30>[ 21.433210] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10589 20:15:46.304971 mount[…- POSIX Message Queue File System.
10590 20:15:46.305401
10591 20:15:46.316576 <3>[ 21.458582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10592 20:15:46.327224 [[0;32m OK [0m] Mounted [0;<30>[ 21.469659] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10593 20:15:46.337220 1;39msys-kernel-<3>[ 21.477321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10594 20:15:46.341618 debug.m…nt[0m - Kernel Debug File System.
10595 20:15:46.342051
10596 20:15:46.356259 <3>[ 21.497721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10597 20:15:46.370606 [[0;32m OK [0m] Finished [0<30>[ 21.510029] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10598 20:15:46.380836 ;1;39mkmod-static-nodes…reate <3>[ 21.522216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10599 20:15:46.383578 List of Static Device Nodes.
10600 20:15:46.384001
10601 20:15:46.400531 <3>[ 21.543464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10602 20:15:46.412133 [[0;32m OK [<30>[ 21.554597] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10603 20:15:46.422297 <30>[ 21.555183] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10604 20:15:46.428827 <3>[ 21.564275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10605 20:15:46.442055 0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 21.583029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10606 20:15:46.445019 Load Kernel Module configfs.
10607 20:15:46.445488
10608 20:15:46.463962 [[0;32m OK [<30>[ 21.606435] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10609 20:15:46.473966 0m] Finished [0<30>[ 21.607312] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10610 20:15:46.480617 <3>[ 21.607944] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 20:15:46.487759 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10612 20:15:46.488647
10613 20:15:46.507722 [[0;32m OK [<30>[ 21.650408] systemd[1]: modprobe@drm.service: Deactivated successfully.
10614 20:15:46.515555 <30>[ 21.651290] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10615 20:15:46.520885 0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10616 20:15:46.521456
10617 20:15:46.546317 [[0;32m OK [0m] Started [0;<30>[ 21.685901] systemd[1]: Started systemd-journald.service - Journal Service.
10618 20:15:46.548830 1;39msystemd-journald.service[0m - Journal Service.
10619 20:15:46.549308
10620 20:15:46.574925 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10621 20:15:46.575553
10622 20:15:46.595295 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10623 20:15:46.595850
10624 20:15:46.616081 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10625 20:15:46.616646
10626 20:15:46.645583 [[0;32m OK [<4>[ 21.778040] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10627 20:15:46.652317 0m] Finished [0<3>[ 21.778052] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10628 20:15:46.658672 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10629 20:15:46.659226
10630 20:15:46.683457 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10631 20:15:46.684034
10632 20:15:46.705850 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10633 20:15:46.706407
10634 20:15:46.726222 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10635 20:15:46.726788
10636 20:15:46.747779 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10637 20:15:46.748361
10638 20:15:46.789607 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10639 20:15:46.790161
10640 20:15:46.814293 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10641 20:15:46.814887
10642 20:15:46.837874 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10643 20:15:46.838464
10644 20:15:46.881536 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10645 20:15:46.881643
10646 20:15:46.891636 <46>[ 22.034690] systemd-journald[308]: Received client request to flush runtime journal.
10647 20:15:46.910082 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10648 20:15:46.910210
10649 20:15:46.934722 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10650 20:15:46.934940
10651 20:15:47.212825 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10652 20:15:47.212963
10653 20:15:47.228652 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10654 20:15:47.228806
10655 20:15:47.245007 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10656 20:15:47.245128
10657 20:15:47.673895 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10658 20:15:47.674125
10659 20:15:48.336041 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10660 20:15:48.336288
10661 20:15:48.353769 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10662 20:15:48.354031
10663 20:15:48.417196 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10664 20:15:48.417804
10665 20:15:48.545276 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10666 20:15:48.545863
10667 20:15:48.565568 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10668 20:15:48.566142
10669 20:15:48.584344 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10670 20:15:48.584930
10671 20:15:48.632904 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10672 20:15:48.633625
10673 20:15:48.655718 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10674 20:15:48.656248
10675 20:15:48.819402 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10676 20:15:48.819562
10677 20:15:48.883527 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10678 20:15:48.883952
10679 20:15:48.937125 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10680 20:15:48.937689
10681 20:15:49.212685 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10682 20:15:49.212870
10683 20:15:49.270215 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10684 20:15:49.270574
10685 20:15:49.289309 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10686 20:15:49.289917
10687 20:15:49.322298 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10688 20:15:49.322754
10689 20:15:49.420594 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10690 20:15:49.421203
10691 20:15:49.439198 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10692 20:15:49.439674
10693 20:15:49.457395 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10694 20:15:49.457822
10695 20:15:49.527358 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10696 20:15:49.527950
10697 20:15:49.542035 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10698 20:15:49.542538
10699 20:15:49.562013 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10700 20:15:49.562618
10701 20:15:49.615007 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10702 20:15:49.615563
10703 20:15:49.634389 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10704 20:15:49.635035
10705 20:15:49.663220 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10706 20:15:49.663776
10707 20:15:49.693796 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10708 20:15:49.694484
10709 20:15:49.712849 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10710 20:15:49.713392
10711 20:15:49.735824 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Clean<46>[ 24.880511] systemd-journald[308]: Time jumped backwards, rotating.
10712 20:15:49.739045 up of Temporary Directories.
10713 20:15:49.739829
10714 20:15:49.756201 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10715 20:15:49.756689
10716 20:15:49.779734 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10717 20:15:49.780206
10718 20:15:50.330970 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10719 20:15:50.331112
10720 20:15:50.348594 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10721 20:15:50.348681
10722 20:15:50.516266 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10723 20:15:50.516437
10724 20:15:50.842441 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10725 20:15:50.843007
10726 20:15:50.859995 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10727 20:15:50.860472
10728 20:15:51.125260 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10729 20:15:51.125410
10730 20:15:51.144064 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10731 20:15:51.144164
10732 20:15:51.159947 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10733 20:15:51.160027
10734 20:15:51.225282 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10735 20:15:51.225452
10736 20:15:51.264688 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10737 20:15:51.265180
10738 20:15:51.333387 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10739 20:15:51.333946
10740 20:15:51.359418 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10741 20:15:51.359930
10742 20:15:51.544190 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10743 20:15:51.544332
10744 20:15:51.591135 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10745 20:15:51.591242
10746 20:15:51.643513 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10747 20:15:51.644071
10748 20:15:51.665166 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10749 20:15:51.665592
10750 20:15:51.681934 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10751 20:15:51.682509
10752 20:15:51.716610 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10753 20:15:51.717196
10754 20:15:51.734488 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10755 20:15:51.735042
10756 20:15:51.766369 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10757 20:15:51.766930
10758 20:15:51.786011 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10759 20:15:51.786576
10760 20:15:51.851044 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10761 20:15:51.851753
10762 20:15:51.874992 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10763 20:15:51.875806
10764 20:15:51.926771 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10765 20:15:51.927331
10766 20:15:52.037334 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10767 20:15:52.037553
10768 20:15:52.124009
10769 20:15:52.124628
10770 20:15:52.127491 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10771 20:15:52.128015
10772 20:15:52.130287 debian-bookworm-arm64 login: root (automatic login)
10773 20:15:52.130813
10774 20:15:52.131239
10775 20:15:52.450103 Linux debian-bookworm-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10776 20:15:52.450631
10777 20:15:52.457305 The programs included with the Debian GNU/Linux system are free software;
10778 20:15:52.462882 the exact distribution terms for each program are described in the
10779 20:15:52.466345 individual files in /usr/share/doc/*/copyright.
10780 20:15:52.466764
10781 20:15:52.473187 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10782 20:15:52.475927 permitted by applicable law.
10783 20:15:53.498866 Matched prompt #10: / #
10785 20:15:53.499992 Setting prompt string to ['/ #']
10786 20:15:53.500423 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10788 20:15:53.501445 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10789 20:15:53.501886 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10790 20:15:53.502280 Setting prompt string to ['/ #']
10791 20:15:53.502622 Forcing a shell prompt, looking for ['/ #']
10793 20:15:53.553535 / #
10794 20:15:53.554510 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10795 20:15:53.555195 Waiting using forced prompt support (timeout 00:02:30)
10796 20:15:53.560862
10797 20:15:53.561846 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10798 20:15:53.562384 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10800 20:15:53.663641 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x'
10801 20:15:53.670457 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928117/extract-nfsrootfs-vuq8kp0x'
10803 20:15:53.772190 / # export NFS_SERVER_IP='192.168.201.1'
10804 20:15:53.778542 export NFS_SERVER_IP='192.168.201.1'
10805 20:15:53.779368 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10806 20:15:53.779898 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10807 20:15:53.780389 end: 2 depthcharge-action (duration 00:01:35) [common]
10808 20:15:53.780933 start: 3 lava-test-retry (timeout 00:07:47) [common]
10809 20:15:53.781426 start: 3.1 lava-test-shell (timeout 00:07:47) [common]
10810 20:15:53.781852 Using namespace: common
10812 20:15:53.883069 / # #
10813 20:15:53.883736 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10814 20:15:53.889820 #
10815 20:15:53.890619 Using /lava-12928117
10817 20:15:53.991924 / # export SHELL=/bin/bash
10818 20:15:53.998526 export SHELL=/bin/bash
10820 20:15:54.100306 / # . /lava-12928117/environment
10821 20:15:54.107142 . /lava-12928117/environment
10823 20:15:54.214865 / # /lava-12928117/bin/lava-test-runner /lava-12928117/0
10824 20:15:54.215551 Test shell timeout: 10s (minimum of the action and connection timeout)
10825 20:15:54.221188 /lava-12928117/bin/lava-test-runner /lava-12928117/0
10826 20:15:54.469791 + export TESTRUN_ID=0_timesync-off
10827 20:15:54.472402 + TESTRUN_ID=0_timesync-off
10828 20:15:54.475932 + cd /lava-12928117/0/tests/0_timesync-off
10829 20:15:54.479614 ++ cat uuid
10830 20:15:54.482200 + UUID=12928117_1.6.2.3.1
10831 20:15:54.482624 + set +x
10832 20:15:54.489179 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12928117_1.6.2.3.1>
10833 20:15:54.489884 Received signal: <STARTRUN> 0_timesync-off 12928117_1.6.2.3.1
10834 20:15:54.490251 Starting test lava.0_timesync-off (12928117_1.6.2.3.1)
10835 20:15:54.490659 Skipping test definition patterns.
10836 20:15:54.492010 + systemctl stop systemd-timesyncd
10837 20:15:54.563141 + set +x
10838 20:15:54.566508 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12928117_1.6.2.3.1>
10839 20:15:54.567197 Received signal: <ENDRUN> 0_timesync-off 12928117_1.6.2.3.1
10840 20:15:54.567618 Ending use of test pattern.
10841 20:15:54.567933 Ending test lava.0_timesync-off (12928117_1.6.2.3.1), duration 0.08
10843 20:15:54.645129 + export TESTRUN_ID=1_kselftest-alsa
10844 20:15:54.648326 + TESTRUN_ID=1_kselftest-alsa
10845 20:15:54.655244 + cd /lava-12928117/0/tests/1_kselftest-alsa
10846 20:15:54.655670 ++ cat uuid
10847 20:15:54.660003 + UUID=12928117_1.6.2.3.5
10848 20:15:54.660431 + set +x
10849 20:15:54.666155 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12928117_1.6.2.3.5>
10850 20:15:54.666836 Received signal: <STARTRUN> 1_kselftest-alsa 12928117_1.6.2.3.5
10851 20:15:54.667204 Starting test lava.1_kselftest-alsa (12928117_1.6.2.3.5)
10852 20:15:54.667588 Skipping test definition patterns.
10853 20:15:54.669183 + cd ./automated/linux/kselftest/
10854 20:15:54.698961 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10855 20:15:54.737558 INFO: install_deps skipped
10856 20:15:55.240496 --2024-03-03 20:15:55-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10857 20:15:55.246782 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10858 20:15:55.375037 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10859 20:15:55.508250 HTTP request sent, awaiting response... 200 OK
10860 20:15:55.511267 Length: 1746752 (1.7M) [application/octet-stream]
10861 20:15:55.514588 Saving to: 'kselftest.tar.xz'
10862 20:15:55.515168
10863 20:15:55.515539
10864 20:15:55.775687 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10865 20:15:56.040263 kselftest.tar.xz 2%[ ] 47.81K 181KB/s
10866 20:15:56.487227 kselftest.tar.xz 12%[=> ] 218.91K 412KB/s
10867 20:15:56.576350 kselftest.tar.xz 47%[========> ] 808.57K 827KB/s
10868 20:15:56.582207 kselftest.tar.xz 100%[===================>] 1.67M 1.56MB/s in 1.1s
10869 20:15:56.582674
10870 20:15:56.735371 2024-03-03 20:15:56 (1.56 MB/s) - 'kselftest.tar.xz' saved [1746752/1746752]
10871 20:15:56.735523
10872 20:16:00.977153 skiplist:
10873 20:16:00.980145 ========================================
10874 20:16:00.984211 ========================================
10875 20:16:01.034210 alsa:mixer-test
10876 20:16:01.055702 ============== Tests to run ===============
10877 20:16:01.056154 alsa:mixer-test
10878 20:16:01.062622 ===========End Tests to run ===============
10879 20:16:01.066391 shardfile-alsa pass
10880 20:16:01.175295 <12>[ 36.324070] kselftest: Running tests in alsa
10881 20:16:01.182772 TAP version 13
10882 20:16:01.197340 1..1
10883 20:16:01.213014 # selftests: alsa: mixer-test
10884 20:16:01.737034 # TAP version 13
10885 20:16:01.737655 # 1..0
10886 20:16:01.743196 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10887 20:16:01.746251 ok 1 selftests: alsa: mixer-test
10888 20:16:02.872065
10889 20:16:02.874796 WARNING: Optional imports not found, TAP 13 output will be
10890 20:16:02.882072 ignored. To parse yaml, see requirements in docs:
10891 20:16:02.888044 https://tappy.readthedocs.io/en/latest/consumers.html#tap-version-13
10892 20:16:02.888609 alsa_mixer-test pass
10893 20:16:02.924547 + ../../utils/send-to-lava.sh ./output/result.txt
10894 20:16:02.996565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10895 20:16:02.997468 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10897 20:16:03.218271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10898 20:16:03.218846 + set +x
10899 20:16:03.219454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10901 20:16:03.225122 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12928117_1.6.2.3.5>
10902 20:16:03.226020 Received signal: <ENDRUN> 1_kselftest-alsa 12928117_1.6.2.3.5
10903 20:16:03.226429 Ending use of test pattern.
10904 20:16:03.226770 Ending test lava.1_kselftest-alsa (12928117_1.6.2.3.5), duration 8.56
10906 20:16:03.227990 <LAVA_TEST_RUNNER EXIT>
10907 20:16:03.228636 ok: lava_test_shell seems to have completed
10908 20:16:03.229190 alsa_mixer-test: pass
shardfile-alsa: pass
10909 20:16:03.229642 end: 3.1 lava-test-shell (duration 00:00:09) [common]
10910 20:16:03.230078 end: 3 lava-test-retry (duration 00:00:09) [common]
10911 20:16:03.230547 start: 4 finalize (timeout 00:07:38) [common]
10912 20:16:03.231023 start: 4.1 power-off (timeout 00:00:30) [common]
10913 20:16:03.231861 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10914 20:16:03.319883 >> Command sent successfully.
10915 20:16:03.324384 Returned 0 in 0 seconds
10916 20:16:03.425335 end: 4.1 power-off (duration 00:00:00) [common]
10918 20:16:03.426857 start: 4.2 read-feedback (timeout 00:07:37) [common]
10919 20:16:03.428246 Listened to connection for namespace 'common' for up to 1s
10920 20:16:04.428909 Finalising connection for namespace 'common'
10921 20:16:04.429624 Disconnecting from shell: Finalise
10922 20:16:04.430048 / #
10923 20:16:04.531209 end: 4.2 read-feedback (duration 00:00:01) [common]
10924 20:16:04.531937 end: 4 finalize (duration 00:00:01) [common]
10925 20:16:04.532589 Cleaning after the job
10926 20:16:04.533138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/ramdisk
10927 20:16:04.548146 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/kernel
10928 20:16:04.583977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/dtb
10929 20:16:04.584272 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/nfsrootfs
10930 20:16:04.671098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928117/tftp-deploy-_x39tgoc/modules
10931 20:16:04.678682 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928117
10932 20:16:05.314635 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928117
10933 20:16:05.314811 Job finished correctly