Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 14
1 20:11:15.975247 lava-dispatcher, installed at version: 2024.01
2 20:11:15.975451 start: 0 validate
3 20:11:15.975576 Start time: 2024-03-03 20:11:15.975569+00:00 (UTC)
4 20:11:15.975702 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:11:15.975852 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 20:11:16.235864 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:11:16.236214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:11:32.752814 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:11:32.753143 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:11:33.022308 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:11:33.023032 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:11:33.544445 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:11:33.545176 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:11:36.554887 validate duration: 20.58
16 20:11:36.555192 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:11:36.555319 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:11:36.555433 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:11:36.555595 Not decompressing ramdisk as can be used compressed.
20 20:11:36.555694 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 20:11:36.555786 saving as /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/ramdisk/initrd.cpio.gz
22 20:11:36.555851 total size: 4663047 (4 MB)
23 20:11:36.813038 progress 0 % (0 MB)
24 20:11:36.814545 progress 5 % (0 MB)
25 20:11:36.815780 progress 10 % (0 MB)
26 20:11:36.817015 progress 15 % (0 MB)
27 20:11:36.818317 progress 20 % (0 MB)
28 20:11:36.819535 progress 25 % (1 MB)
29 20:11:36.820741 progress 30 % (1 MB)
30 20:11:36.821973 progress 35 % (1 MB)
31 20:11:36.823193 progress 40 % (1 MB)
32 20:11:36.824554 progress 45 % (2 MB)
33 20:11:36.825754 progress 50 % (2 MB)
34 20:11:36.826977 progress 55 % (2 MB)
35 20:11:36.828186 progress 60 % (2 MB)
36 20:11:36.829392 progress 65 % (2 MB)
37 20:11:36.830673 progress 70 % (3 MB)
38 20:11:36.831883 progress 75 % (3 MB)
39 20:11:36.833088 progress 80 % (3 MB)
40 20:11:36.834328 progress 85 % (3 MB)
41 20:11:36.835690 progress 90 % (4 MB)
42 20:11:36.836885 progress 95 % (4 MB)
43 20:11:36.838145 progress 100 % (4 MB)
44 20:11:36.838289 4 MB downloaded in 0.28 s (15.75 MB/s)
45 20:11:36.838442 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:11:36.838685 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:11:36.838774 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:11:36.838860 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:11:36.838996 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:11:36.839066 saving as /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/kernel/Image
52 20:11:36.839129 total size: 51601920 (49 MB)
53 20:11:36.839193 No compression specified
54 20:11:36.840301 progress 0 % (0 MB)
55 20:11:36.853228 progress 5 % (2 MB)
56 20:11:36.866285 progress 10 % (4 MB)
57 20:11:36.879601 progress 15 % (7 MB)
58 20:11:36.892478 progress 20 % (9 MB)
59 20:11:36.905496 progress 25 % (12 MB)
60 20:11:36.918544 progress 30 % (14 MB)
61 20:11:36.931661 progress 35 % (17 MB)
62 20:11:36.944591 progress 40 % (19 MB)
63 20:11:36.957611 progress 45 % (22 MB)
64 20:11:36.970675 progress 50 % (24 MB)
65 20:11:36.983979 progress 55 % (27 MB)
66 20:11:36.996824 progress 60 % (29 MB)
67 20:11:37.009820 progress 65 % (32 MB)
68 20:11:37.022862 progress 70 % (34 MB)
69 20:11:37.036180 progress 75 % (36 MB)
70 20:11:37.049724 progress 80 % (39 MB)
71 20:11:37.063139 progress 85 % (41 MB)
72 20:11:37.076449 progress 90 % (44 MB)
73 20:11:37.089580 progress 95 % (46 MB)
74 20:11:37.102251 progress 100 % (49 MB)
75 20:11:37.102519 49 MB downloaded in 0.26 s (186.84 MB/s)
76 20:11:37.102681 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:11:37.102917 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:11:37.103007 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:11:37.103142 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:11:37.103293 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:11:37.103365 saving as /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/dtb/mt8192-asurada-spherion-r0.dtb
83 20:11:37.103426 total size: 47278 (0 MB)
84 20:11:37.103488 No compression specified
85 20:11:37.104597 progress 69 % (0 MB)
86 20:11:37.104870 progress 100 % (0 MB)
87 20:11:37.105027 0 MB downloaded in 0.00 s (28.21 MB/s)
88 20:11:37.105150 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:11:37.105371 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:11:37.105456 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:11:37.105537 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:11:37.105646 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 20:11:37.105716 saving as /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/nfsrootfs/full.rootfs.tar
95 20:11:37.105778 total size: 200856304 (191 MB)
96 20:11:37.105838 Using unxz to decompress xz
97 20:11:37.109460 progress 0 % (0 MB)
98 20:11:37.638022 progress 5 % (9 MB)
99 20:11:38.151150 progress 10 % (19 MB)
100 20:11:38.735958 progress 15 % (28 MB)
101 20:11:39.101303 progress 20 % (38 MB)
102 20:11:39.425435 progress 25 % (47 MB)
103 20:11:40.023031 progress 30 % (57 MB)
104 20:11:40.577212 progress 35 % (67 MB)
105 20:11:41.171204 progress 40 % (76 MB)
106 20:11:41.733280 progress 45 % (86 MB)
107 20:11:42.315188 progress 50 % (95 MB)
108 20:11:42.941743 progress 55 % (105 MB)
109 20:11:43.617546 progress 60 % (114 MB)
110 20:11:43.743180 progress 65 % (124 MB)
111 20:11:43.883018 progress 70 % (134 MB)
112 20:11:43.971655 progress 75 % (143 MB)
113 20:11:44.040068 progress 80 % (153 MB)
114 20:11:44.113616 progress 85 % (162 MB)
115 20:11:44.208532 progress 90 % (172 MB)
116 20:11:44.496770 progress 95 % (182 MB)
117 20:11:45.090044 progress 100 % (191 MB)
118 20:11:45.096116 191 MB downloaded in 7.99 s (23.97 MB/s)
119 20:11:45.096431 end: 1.4.1 http-download (duration 00:00:08) [common]
121 20:11:45.096708 end: 1.4 download-retry (duration 00:00:08) [common]
122 20:11:45.096800 start: 1.5 download-retry (timeout 00:09:51) [common]
123 20:11:45.096887 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 20:11:45.097037 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:11:45.097109 saving as /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/modules/modules.tar
126 20:11:45.097170 total size: 8632284 (8 MB)
127 20:11:45.097234 Using unxz to decompress xz
128 20:11:45.365425 progress 0 % (0 MB)
129 20:11:45.392631 progress 5 % (0 MB)
130 20:11:45.426253 progress 10 % (0 MB)
131 20:11:45.454749 progress 15 % (1 MB)
132 20:11:45.477626 progress 20 % (1 MB)
133 20:11:45.502771 progress 25 % (2 MB)
134 20:11:45.529184 progress 30 % (2 MB)
135 20:11:45.555473 progress 35 % (2 MB)
136 20:11:45.580697 progress 40 % (3 MB)
137 20:11:45.605682 progress 45 % (3 MB)
138 20:11:45.630944 progress 50 % (4 MB)
139 20:11:45.655830 progress 55 % (4 MB)
140 20:11:45.681138 progress 60 % (4 MB)
141 20:11:45.706732 progress 65 % (5 MB)
142 20:11:45.732359 progress 70 % (5 MB)
143 20:11:45.757758 progress 75 % (6 MB)
144 20:11:45.784345 progress 80 % (6 MB)
145 20:11:45.809474 progress 85 % (7 MB)
146 20:11:45.836356 progress 90 % (7 MB)
147 20:11:45.865147 progress 95 % (7 MB)
148 20:11:45.893646 progress 100 % (8 MB)
149 20:11:45.899366 8 MB downloaded in 0.80 s (10.26 MB/s)
150 20:11:45.899673 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:11:45.899950 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:11:45.900046 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 20:11:45.900141 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 20:11:49.100865 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy
156 20:11:49.101118 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 20:11:49.101289 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 20:11:49.101485 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602
159 20:11:49.101610 makedir: /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin
160 20:11:49.101709 makedir: /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/tests
161 20:11:49.101805 makedir: /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/results
162 20:11:49.101908 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-add-keys
163 20:11:49.102093 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-add-sources
164 20:11:49.102219 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-background-process-start
165 20:11:49.102343 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-background-process-stop
166 20:11:49.102463 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-common-functions
167 20:11:49.102583 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-echo-ipv4
168 20:11:49.102702 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-install-packages
169 20:11:49.102821 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-installed-packages
170 20:11:49.102939 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-os-build
171 20:11:49.103056 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-probe-channel
172 20:11:49.103176 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-probe-ip
173 20:11:49.103294 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-target-ip
174 20:11:49.103410 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-target-mac
175 20:11:49.103527 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-target-storage
176 20:11:49.103646 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-case
177 20:11:49.103765 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-event
178 20:11:49.103882 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-feedback
179 20:11:49.104000 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-raise
180 20:11:49.104116 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-reference
181 20:11:49.104233 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-runner
182 20:11:49.104351 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-set
183 20:11:49.104468 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-test-shell
184 20:11:49.104587 Updating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-add-keys (debian)
185 20:11:49.104735 Updating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-add-sources (debian)
186 20:11:49.104871 Updating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-install-packages (debian)
187 20:11:49.105003 Updating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-installed-packages (debian)
188 20:11:49.105135 Updating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/bin/lava-os-build (debian)
189 20:11:49.105250 Creating /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/environment
190 20:11:49.105345 LAVA metadata
191 20:11:49.105414 - LAVA_JOB_ID=12928082
192 20:11:49.105476 - LAVA_DISPATCHER_IP=192.168.201.1
193 20:11:49.105583 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 20:11:49.105649 skipped lava-vland-overlay
195 20:11:49.105723 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 20:11:49.105801 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 20:11:49.105861 skipped lava-multinode-overlay
198 20:11:49.105930 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 20:11:49.106051 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 20:11:49.106126 Loading test definitions
201 20:11:49.106215 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 20:11:49.106284 Using /lava-12928082 at stage 0
203 20:11:49.106556 uuid=12928082_1.6.2.3.1 testdef=None
204 20:11:49.106644 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 20:11:49.106728 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 20:11:49.107169 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 20:11:49.107389 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 20:11:49.107918 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 20:11:49.108153 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 20:11:49.108731 runner path: /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/0/tests/0_timesync-off test_uuid 12928082_1.6.2.3.1
213 20:11:49.108891 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 20:11:49.109114 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 20:11:49.109186 Using /lava-12928082 at stage 0
217 20:11:49.109283 Fetching tests from https://github.com/kernelci/test-definitions.git
218 20:11:49.109370 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/0/tests/1_kselftest-arm64'
219 20:11:52.117819 Running '/usr/bin/git checkout kernelci.org
220 20:11:52.211304 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 20:11:52.212014 uuid=12928082_1.6.2.3.5 testdef=None
222 20:11:52.212172 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 20:11:52.212425 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 20:11:52.213157 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 20:11:52.213388 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 20:11:52.214409 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 20:11:52.214653 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 20:11:52.215575 runner path: /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/0/tests/1_kselftest-arm64 test_uuid 12928082_1.6.2.3.5
232 20:11:52.215669 BOARD='mt8192-asurada-spherion-r0'
233 20:11:52.215736 BRANCH='cip-gitlab'
234 20:11:52.215797 SKIPFILE='/dev/null'
235 20:11:52.215856 SKIP_INSTALL='True'
236 20:11:52.215913 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 20:11:52.215972 TST_CASENAME=''
238 20:11:52.216028 TST_CMDFILES='arm64'
239 20:11:52.216170 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 20:11:52.216378 Creating lava-test-runner.conf files
242 20:11:52.216445 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928082/lava-overlay-i7s47602/lava-12928082/0 for stage 0
243 20:11:52.216539 - 0_timesync-off
244 20:11:52.216610 - 1_kselftest-arm64
245 20:11:52.216706 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 20:11:52.216797 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 20:11:59.632171 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 20:11:59.632333 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 20:11:59.632428 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 20:11:59.632573 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 20:11:59.632682 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 20:11:59.745437 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 20:11:59.745806 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 20:11:59.745921 extracting modules file /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy
255 20:11:59.948799 extracting modules file /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928082/extract-overlay-ramdisk-z0c9km95/ramdisk
256 20:12:00.155542 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 20:12:00.155702 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 20:12:00.155800 [common] Applying overlay to NFS
259 20:12:00.155877 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928082/compress-overlay-msmobqlg/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy
260 20:12:01.064331 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 20:12:01.064492 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 20:12:01.064590 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 20:12:01.064684 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 20:12:01.064764 Building ramdisk /var/lib/lava/dispatcher/tmp/12928082/extract-overlay-ramdisk-z0c9km95/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928082/extract-overlay-ramdisk-z0c9km95/ramdisk
265 20:12:01.369416 >> 119447 blocks
266 20:12:03.244380 rename /var/lib/lava/dispatcher/tmp/12928082/extract-overlay-ramdisk-z0c9km95/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/ramdisk/ramdisk.cpio.gz
267 20:12:03.244819 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 20:12:03.244937 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 20:12:03.245037 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 20:12:03.245170 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/kernel/Image'
271 20:12:15.649789 Returned 0 in 12 seconds
272 20:12:15.750474 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/kernel/image.itb
273 20:12:16.093255 output: FIT description: Kernel Image image with one or more FDT blobs
274 20:12:16.093611 output: Created: Sun Mar 3 20:12:16 2024
275 20:12:16.093688 output: Image 0 (kernel-1)
276 20:12:16.093758 output: Description:
277 20:12:16.093824 output: Created: Sun Mar 3 20:12:16 2024
278 20:12:16.093889 output: Type: Kernel Image
279 20:12:16.093977 output: Compression: lzma compressed
280 20:12:16.094081 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
281 20:12:16.094137 output: Architecture: AArch64
282 20:12:16.094194 output: OS: Linux
283 20:12:16.094252 output: Load Address: 0x00000000
284 20:12:16.094311 output: Entry Point: 0x00000000
285 20:12:16.094367 output: Hash algo: crc32
286 20:12:16.094424 output: Hash value: 91cb1a17
287 20:12:16.094479 output: Image 1 (fdt-1)
288 20:12:16.094538 output: Description: mt8192-asurada-spherion-r0
289 20:12:16.094596 output: Created: Sun Mar 3 20:12:16 2024
290 20:12:16.094650 output: Type: Flat Device Tree
291 20:12:16.094704 output: Compression: uncompressed
292 20:12:16.094757 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 20:12:16.094811 output: Architecture: AArch64
294 20:12:16.094864 output: Hash algo: crc32
295 20:12:16.094917 output: Hash value: cc4352de
296 20:12:16.094971 output: Image 2 (ramdisk-1)
297 20:12:16.095025 output: Description: unavailable
298 20:12:16.095078 output: Created: Sun Mar 3 20:12:16 2024
299 20:12:16.095132 output: Type: RAMDisk Image
300 20:12:16.095186 output: Compression: Unknown Compression
301 20:12:16.095240 output: Data Size: 17808406 Bytes = 17391.02 KiB = 16.98 MiB
302 20:12:16.095294 output: Architecture: AArch64
303 20:12:16.095348 output: OS: Linux
304 20:12:16.095401 output: Load Address: unavailable
305 20:12:16.095455 output: Entry Point: unavailable
306 20:12:16.095508 output: Hash algo: crc32
307 20:12:16.095561 output: Hash value: 6cdaa85b
308 20:12:16.095615 output: Default Configuration: 'conf-1'
309 20:12:16.095669 output: Configuration 0 (conf-1)
310 20:12:16.095722 output: Description: mt8192-asurada-spherion-r0
311 20:12:16.095775 output: Kernel: kernel-1
312 20:12:16.095828 output: Init Ramdisk: ramdisk-1
313 20:12:16.095881 output: FDT: fdt-1
314 20:12:16.095934 output: Loadables: kernel-1
315 20:12:16.095987 output:
316 20:12:16.096188 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 20:12:16.096287 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 20:12:16.096394 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 20:12:16.096487 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 20:12:16.096569 No LXC device requested
321 20:12:16.096650 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 20:12:16.096736 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 20:12:16.096813 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 20:12:16.096879 Checking files for TFTP limit of 4294967296 bytes.
325 20:12:16.097375 end: 1 tftp-deploy (duration 00:00:40) [common]
326 20:12:16.097485 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 20:12:16.097579 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 20:12:16.097712 substitutions:
329 20:12:16.097784 - {DTB}: 12928082/tftp-deploy-uyoxvert/dtb/mt8192-asurada-spherion-r0.dtb
330 20:12:16.097851 - {INITRD}: 12928082/tftp-deploy-uyoxvert/ramdisk/ramdisk.cpio.gz
331 20:12:16.097912 - {KERNEL}: 12928082/tftp-deploy-uyoxvert/kernel/Image
332 20:12:16.098014 - {LAVA_MAC}: None
333 20:12:16.098075 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy
334 20:12:16.098132 - {NFS_SERVER_IP}: 192.168.201.1
335 20:12:16.098188 - {PRESEED_CONFIG}: None
336 20:12:16.098243 - {PRESEED_LOCAL}: None
337 20:12:16.098299 - {RAMDISK}: 12928082/tftp-deploy-uyoxvert/ramdisk/ramdisk.cpio.gz
338 20:12:16.098355 - {ROOT_PART}: None
339 20:12:16.098410 - {ROOT}: None
340 20:12:16.098465 - {SERVER_IP}: 192.168.201.1
341 20:12:16.098519 - {TEE}: None
342 20:12:16.098575 Parsed boot commands:
343 20:12:16.098630 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 20:12:16.098807 Parsed boot commands: tftpboot 192.168.201.1 12928082/tftp-deploy-uyoxvert/kernel/image.itb 12928082/tftp-deploy-uyoxvert/kernel/cmdline
345 20:12:16.098898 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 20:12:16.098984 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 20:12:16.099076 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 20:12:16.099162 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 20:12:16.099240 Not connected, no need to disconnect.
350 20:12:16.099314 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 20:12:16.099395 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 20:12:16.099467 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 20:12:16.102965 Setting prompt string to ['lava-test: # ']
354 20:12:16.103307 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 20:12:16.103419 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 20:12:16.103516 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 20:12:16.103646 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 20:12:16.103837 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 20:12:21.236434 >> Command sent successfully.
360 20:12:21.238999 Returned 0 in 5 seconds
361 20:12:21.339394 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 20:12:21.339758 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 20:12:21.339865 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 20:12:21.339954 Setting prompt string to 'Starting depthcharge on Spherion...'
366 20:12:21.340022 Changing prompt to 'Starting depthcharge on Spherion...'
367 20:12:21.340093 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 20:12:21.340358 [Enter `^Ec?' for help]
369 20:12:21.513022
370 20:12:21.513173
371 20:12:21.513297 F0: 102B 0000
372 20:12:21.513365
373 20:12:21.513426 F3: 1001 0000 [0200]
374 20:12:21.513491
375 20:12:21.516633 F3: 1001 0000
376 20:12:21.516719
377 20:12:21.516788 F7: 102D 0000
378 20:12:21.516852
379 20:12:21.520055 F1: 0000 0000
380 20:12:21.520157
381 20:12:21.520225 V0: 0000 0000 [0001]
382 20:12:21.520305
383 20:12:21.523400 00: 0007 8000
384 20:12:21.523499
385 20:12:21.523601 01: 0000 0000
386 20:12:21.523666
387 20:12:21.526443 BP: 0C00 0209 [0000]
388 20:12:21.526529
389 20:12:21.526597 G0: 1182 0000
390 20:12:21.526660
391 20:12:21.526720 EC: 0000 0021 [4000]
392 20:12:21.530200
393 20:12:21.530286 S7: 0000 0000 [0000]
394 20:12:21.530355
395 20:12:21.533989 CC: 0000 0000 [0001]
396 20:12:21.534076
397 20:12:21.534144 T0: 0000 0040 [010F]
398 20:12:21.534211
399 20:12:21.534270 Jump to BL
400 20:12:21.534330
401 20:12:21.559934
402 20:12:21.560063
403 20:12:21.560177
404 20:12:21.566812 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 20:12:21.570634 ARM64: Exception handlers installed.
406 20:12:21.574481 ARM64: Testing exception
407 20:12:21.577834 ARM64: Done test exception
408 20:12:21.584544 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 20:12:21.594716 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 20:12:21.601514 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 20:12:21.611479 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 20:12:21.618490 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 20:12:21.624729 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 20:12:21.637138 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 20:12:21.643591 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 20:12:21.663046 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 20:12:21.666221 WDT: Last reset was cold boot
418 20:12:21.669682 SPI1(PAD0) initialized at 2873684 Hz
419 20:12:21.672980 SPI5(PAD0) initialized at 992727 Hz
420 20:12:21.676308 VBOOT: Loading verstage.
421 20:12:21.682755 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:12:21.686106 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:12:21.689812 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:12:21.693055 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:12:21.700149 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:12:21.706826 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:12:21.717735 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 20:12:21.717820
429 20:12:21.717888
430 20:12:21.727823 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:12:21.731108 ARM64: Exception handlers installed.
432 20:12:21.734304 ARM64: Testing exception
433 20:12:21.734382 ARM64: Done test exception
434 20:12:21.741147 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:12:21.744349 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:12:21.758892 Probing TPM: . done!
437 20:12:21.758987 TPM ready after 0 ms
438 20:12:21.765589 Connected to device vid:did:rid of 1ae0:0028:00
439 20:12:21.772740 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 20:12:21.776283 Initialized TPM device CR50 revision 0
441 20:12:21.840586 tlcl_send_startup: Startup return code is 0
442 20:12:21.840687 TPM: setup succeeded
443 20:12:21.852117 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:12:21.860845 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:12:21.870740 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:12:21.879853 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:12:21.883497 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:12:21.893711 in-header: 03 07 00 00 08 00 00 00
449 20:12:21.897326 in-data: aa e4 47 04 13 02 00 00
450 20:12:21.901301 Chrome EC: UHEPI supported
451 20:12:21.908411 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:12:21.911982 in-header: 03 ad 00 00 08 00 00 00
453 20:12:21.915668 in-data: 00 20 20 08 00 00 00 00
454 20:12:21.915743 Phase 1
455 20:12:21.919348 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:12:21.926788 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:12:21.930560 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:12:21.933845 Recovery requested (1009000e)
459 20:12:21.942819 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:12:21.948183 tlcl_extend: response is 0
461 20:12:21.957616 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:12:21.963189 tlcl_extend: response is 0
463 20:12:21.970591 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:12:21.990720 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 20:12:21.997754 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 20:12:21.997868
467 20:12:21.997999
468 20:12:22.007813 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:12:22.011361 ARM64: Exception handlers installed.
470 20:12:22.011444 ARM64: Testing exception
471 20:12:22.014559 ARM64: Done test exception
472 20:12:22.036329 pmic_efuse_setting: Set efuses in 11 msecs
473 20:12:22.039563 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:12:22.046308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:12:22.050065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:12:22.053524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:12:22.059985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:12:22.063538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:12:22.070923 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:12:22.074787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:12:22.078350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:12:22.082119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:12:22.089757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:12:22.093407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:12:22.097046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:12:22.100197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:12:22.107240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:12:22.113893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:12:22.121087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:12:22.124828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:12:22.131831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:12:22.135425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:12:22.142001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:12:22.149230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:12:22.152840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:12:22.159587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:12:22.162823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:12:22.169277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:12:22.176004 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:12:22.179706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:12:22.186091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:12:22.189623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:12:22.192902 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:12:22.199627 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:12:22.206027 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:12:22.209643 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:12:22.216150 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:12:22.219880 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:12:22.226317 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:12:22.229274 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:12:22.236029 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:12:22.239848 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:12:22.243098 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:12:22.246614 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:12:22.254091 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:12:22.257386 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:12:22.260659 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:12:22.263911 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:12:22.270547 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:12:22.273895 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:12:22.277490 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:12:22.284391 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:12:22.287669 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:12:22.290610 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:12:22.297680 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:12:22.307370 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:12:22.310826 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:12:22.318181 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:12:22.328741 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:12:22.332457 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:12:22.336459 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:12:22.343199 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:12:22.347475 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
534 20:12:22.354507 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:12:22.358564 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 20:12:22.362003 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:12:22.373242 [RTC]rtc_get_frequency_meter,154: input=15, output=771
538 20:12:22.383124 [RTC]rtc_get_frequency_meter,154: input=23, output=955
539 20:12:22.391998 [RTC]rtc_get_frequency_meter,154: input=19, output=866
540 20:12:22.401311 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 20:12:22.411039 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 20:12:22.414531 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 20:12:22.420884 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 20:12:22.424557 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 20:12:22.427930 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 20:12:22.431384 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 20:12:22.435018 ADC[4]: Raw value=902876 ID=7
548 20:12:22.438657 ADC[3]: Raw value=213179 ID=1
549 20:12:22.438775 RAM Code: 0x71
550 20:12:22.442299 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 20:12:22.450037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 20:12:22.457191 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 20:12:22.463980 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 20:12:22.467386 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 20:12:22.470844 in-header: 03 07 00 00 08 00 00 00
556 20:12:22.474288 in-data: aa e4 47 04 13 02 00 00
557 20:12:22.477422 Chrome EC: UHEPI supported
558 20:12:22.484046 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 20:12:22.487308 in-header: 03 ed 00 00 08 00 00 00
560 20:12:22.491063 in-data: 80 20 60 08 00 00 00 00
561 20:12:22.493846 MRC: failed to locate region type 0.
562 20:12:22.500569 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 20:12:22.500674 DRAM-K: Running full calibration
564 20:12:22.507371 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 20:12:22.510513 header.status = 0x0
566 20:12:22.514010 header.version = 0x6 (expected: 0x6)
567 20:12:22.517219 header.size = 0xd00 (expected: 0xd00)
568 20:12:22.517319 header.flags = 0x0
569 20:12:22.523784 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 20:12:22.542734 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
571 20:12:22.549512 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 20:12:22.552817 dram_init: ddr_geometry: 2
573 20:12:22.552917 [EMI] MDL number = 2
574 20:12:22.555972 [EMI] Get MDL freq = 0
575 20:12:22.559616 dram_init: ddr_type: 0
576 20:12:22.559722 is_discrete_lpddr4: 1
577 20:12:22.562983 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 20:12:22.563082
579 20:12:22.563178
580 20:12:22.566147 [Bian_co] ETT version 0.0.0.1
581 20:12:22.572913 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 20:12:22.573021
583 20:12:22.576159 dramc_set_vcore_voltage set vcore to 650000
584 20:12:22.576261 Read voltage for 800, 4
585 20:12:22.579709 Vio18 = 0
586 20:12:22.579807 Vcore = 650000
587 20:12:22.579902 Vdram = 0
588 20:12:22.582980 Vddq = 0
589 20:12:22.583086 Vmddr = 0
590 20:12:22.586218 dram_init: config_dvfs: 1
591 20:12:22.589506 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 20:12:22.596342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 20:12:22.599667 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 20:12:22.603190 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 20:12:22.606233 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 20:12:22.609714 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 20:12:22.612861 MEM_TYPE=3, freq_sel=18
598 20:12:22.616767 sv_algorithm_assistance_LP4_1600
599 20:12:22.619748 ============ PULL DRAM RESETB DOWN ============
600 20:12:22.623365 ========== PULL DRAM RESETB DOWN end =========
601 20:12:22.630105 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 20:12:22.633101 ===================================
603 20:12:22.633206 LPDDR4 DRAM CONFIGURATION
604 20:12:22.636143 ===================================
605 20:12:22.639527 EX_ROW_EN[0] = 0x0
606 20:12:22.642800 EX_ROW_EN[1] = 0x0
607 20:12:22.642903 LP4Y_EN = 0x0
608 20:12:22.646833 WORK_FSP = 0x0
609 20:12:22.646934 WL = 0x2
610 20:12:22.649857 RL = 0x2
611 20:12:22.649959 BL = 0x2
612 20:12:22.653243 RPST = 0x0
613 20:12:22.653342 RD_PRE = 0x0
614 20:12:22.656394 WR_PRE = 0x1
615 20:12:22.656495 WR_PST = 0x0
616 20:12:22.659541 DBI_WR = 0x0
617 20:12:22.659648 DBI_RD = 0x0
618 20:12:22.662982 OTF = 0x1
619 20:12:22.666571 ===================================
620 20:12:22.669761 ===================================
621 20:12:22.669864 ANA top config
622 20:12:22.673113 ===================================
623 20:12:22.676471 DLL_ASYNC_EN = 0
624 20:12:22.679518 ALL_SLAVE_EN = 1
625 20:12:22.683311 NEW_RANK_MODE = 1
626 20:12:22.683412 DLL_IDLE_MODE = 1
627 20:12:22.686377 LP45_APHY_COMB_EN = 1
628 20:12:22.689547 TX_ODT_DIS = 1
629 20:12:22.692911 NEW_8X_MODE = 1
630 20:12:22.696591 ===================================
631 20:12:22.700011 ===================================
632 20:12:22.700115 data_rate = 1600
633 20:12:22.703496 CKR = 1
634 20:12:22.707199 DQ_P2S_RATIO = 8
635 20:12:22.710533 ===================================
636 20:12:22.714084 CA_P2S_RATIO = 8
637 20:12:22.714159 DQ_CA_OPEN = 0
638 20:12:22.717658 DQ_SEMI_OPEN = 0
639 20:12:22.721422 CA_SEMI_OPEN = 0
640 20:12:22.725645 CA_FULL_RATE = 0
641 20:12:22.725749 DQ_CKDIV4_EN = 1
642 20:12:22.729115 CA_CKDIV4_EN = 1
643 20:12:22.732724 CA_PREDIV_EN = 0
644 20:12:22.736332 PH8_DLY = 0
645 20:12:22.736440 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 20:12:22.739889 DQ_AAMCK_DIV = 4
647 20:12:22.743288 CA_AAMCK_DIV = 4
648 20:12:22.747044 CA_ADMCK_DIV = 4
649 20:12:22.750945 DQ_TRACK_CA_EN = 0
650 20:12:22.751055 CA_PICK = 800
651 20:12:22.754194 CA_MCKIO = 800
652 20:12:22.758590 MCKIO_SEMI = 0
653 20:12:22.761736 PLL_FREQ = 3068
654 20:12:22.761823 DQ_UI_PI_RATIO = 32
655 20:12:22.765593 CA_UI_PI_RATIO = 0
656 20:12:22.769389 ===================================
657 20:12:22.772890 ===================================
658 20:12:22.776359 memory_type:LPDDR4
659 20:12:22.776445 GP_NUM : 10
660 20:12:22.779971 SRAM_EN : 1
661 20:12:22.780056 MD32_EN : 0
662 20:12:22.783371 ===================================
663 20:12:22.787397 [ANA_INIT] >>>>>>>>>>>>>>
664 20:12:22.791211 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 20:12:22.795114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 20:12:22.795260 ===================================
667 20:12:22.798654 data_rate = 1600,PCW = 0X7600
668 20:12:22.802414 ===================================
669 20:12:22.805647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 20:12:22.813363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 20:12:22.816729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 20:12:22.820730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 20:12:22.824737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 20:12:22.828063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 20:12:22.831533 [ANA_INIT] flow start
676 20:12:22.831704 [ANA_INIT] PLL >>>>>>>>
677 20:12:22.835386 [ANA_INIT] PLL <<<<<<<<
678 20:12:22.839140 [ANA_INIT] MIDPI >>>>>>>>
679 20:12:22.839300 [ANA_INIT] MIDPI <<<<<<<<
680 20:12:22.842703 [ANA_INIT] DLL >>>>>>>>
681 20:12:22.842819 [ANA_INIT] flow end
682 20:12:22.846455 ============ LP4 DIFF to SE enter ============
683 20:12:22.853868 ============ LP4 DIFF to SE exit ============
684 20:12:22.854064 [ANA_INIT] <<<<<<<<<<<<<
685 20:12:22.857472 [Flow] Enable top DCM control >>>>>
686 20:12:22.861511 [Flow] Enable top DCM control <<<<<
687 20:12:22.865447 Enable DLL master slave shuffle
688 20:12:22.869001 ==============================================================
689 20:12:22.872569 Gating Mode config
690 20:12:22.876349 ==============================================================
691 20:12:22.880608 Config description:
692 20:12:22.887732 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 20:12:22.895692 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 20:12:22.899331 SELPH_MODE 0: By rank 1: By Phase
695 20:12:22.906581 ==============================================================
696 20:12:22.906669 GAT_TRACK_EN = 1
697 20:12:22.910343 RX_GATING_MODE = 2
698 20:12:22.914065 RX_GATING_TRACK_MODE = 2
699 20:12:22.917703 SELPH_MODE = 1
700 20:12:22.921505 PICG_EARLY_EN = 1
701 20:12:22.921621 VALID_LAT_VALUE = 1
702 20:12:22.928960 ==============================================================
703 20:12:22.932869 Enter into Gating configuration >>>>
704 20:12:22.937198 Exit from Gating configuration <<<<
705 20:12:22.940243 Enter into DVFS_PRE_config >>>>>
706 20:12:22.951473 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 20:12:22.951595 Exit from DVFS_PRE_config <<<<<
708 20:12:22.955291 Enter into PICG configuration >>>>
709 20:12:22.958828 Exit from PICG configuration <<<<
710 20:12:22.962537 [RX_INPUT] configuration >>>>>
711 20:12:22.966241 [RX_INPUT] configuration <<<<<
712 20:12:22.970098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 20:12:22.973786 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 20:12:22.981167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 20:12:22.988843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 20:12:22.992070 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 20:12:22.999854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 20:12:23.003344 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 20:12:23.006991 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 20:12:23.010668 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 20:12:23.018266 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 20:12:23.021865 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 20:12:23.025968 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 20:12:23.029530 ===================================
725 20:12:23.029626 LPDDR4 DRAM CONFIGURATION
726 20:12:23.033012 ===================================
727 20:12:23.036802 EX_ROW_EN[0] = 0x0
728 20:12:23.036895 EX_ROW_EN[1] = 0x0
729 20:12:23.040390 LP4Y_EN = 0x0
730 20:12:23.040497 WORK_FSP = 0x0
731 20:12:23.044105 WL = 0x2
732 20:12:23.044209 RL = 0x2
733 20:12:23.047747 BL = 0x2
734 20:12:23.047866 RPST = 0x0
735 20:12:23.051383 RD_PRE = 0x0
736 20:12:23.051466 WR_PRE = 0x1
737 20:12:23.054687 WR_PST = 0x0
738 20:12:23.054773 DBI_WR = 0x0
739 20:12:23.058172 DBI_RD = 0x0
740 20:12:23.058245 OTF = 0x1
741 20:12:23.061554 ===================================
742 20:12:23.064786 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 20:12:23.068356 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 20:12:23.074903 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 20:12:23.078236 ===================================
746 20:12:23.078324 LPDDR4 DRAM CONFIGURATION
747 20:12:23.081751 ===================================
748 20:12:23.084788 EX_ROW_EN[0] = 0x10
749 20:12:23.089058 EX_ROW_EN[1] = 0x0
750 20:12:23.089144 LP4Y_EN = 0x0
751 20:12:23.091464 WORK_FSP = 0x0
752 20:12:23.091549 WL = 0x2
753 20:12:23.095093 RL = 0x2
754 20:12:23.095179 BL = 0x2
755 20:12:23.098255 RPST = 0x0
756 20:12:23.098341 RD_PRE = 0x0
757 20:12:23.101765 WR_PRE = 0x1
758 20:12:23.101853 WR_PST = 0x0
759 20:12:23.104986 DBI_WR = 0x0
760 20:12:23.105120 DBI_RD = 0x0
761 20:12:23.108217 OTF = 0x1
762 20:12:23.111329 ===================================
763 20:12:23.117968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 20:12:23.121804 nWR fixed to 40
765 20:12:23.124898 [ModeRegInit_LP4] CH0 RK0
766 20:12:23.125001 [ModeRegInit_LP4] CH0 RK1
767 20:12:23.128205 [ModeRegInit_LP4] CH1 RK0
768 20:12:23.131754 [ModeRegInit_LP4] CH1 RK1
769 20:12:23.131834 match AC timing 13
770 20:12:23.137950 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 20:12:23.141813 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 20:12:23.144943 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 20:12:23.152007 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 20:12:23.154982 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 20:12:23.155102 [EMI DOE] emi_dcm 0
776 20:12:23.161881 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 20:12:23.161995 ==
778 20:12:23.165036 Dram Type= 6, Freq= 0, CH_0, rank 0
779 20:12:23.168220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 20:12:23.168357 ==
781 20:12:23.175190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 20:12:23.178439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 20:12:23.188875 [CA 0] Center 38 (7~69) winsize 63
784 20:12:23.192024 [CA 1] Center 38 (7~69) winsize 63
785 20:12:23.195337 [CA 2] Center 35 (5~66) winsize 62
786 20:12:23.198880 [CA 3] Center 35 (5~66) winsize 62
787 20:12:23.202343 [CA 4] Center 34 (4~65) winsize 62
788 20:12:23.205332 [CA 5] Center 33 (3~64) winsize 62
789 20:12:23.205458
790 20:12:23.208729 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 20:12:23.208840
792 20:12:23.212170 [CATrainingPosCal] consider 1 rank data
793 20:12:23.215567 u2DelayCellTimex100 = 270/100 ps
794 20:12:23.218697 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 20:12:23.222405 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 20:12:23.225836 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 20:12:23.232363 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 20:12:23.235620 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 20:12:23.239156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 20:12:23.239272
801 20:12:23.242329 CA PerBit enable=1, Macro0, CA PI delay=33
802 20:12:23.242468
803 20:12:23.245567 [CBTSetCACLKResult] CA Dly = 33
804 20:12:23.245718 CS Dly: 6 (0~37)
805 20:12:23.245846 ==
806 20:12:23.248947 Dram Type= 6, Freq= 0, CH_0, rank 1
807 20:12:23.255895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 20:12:23.255989 ==
809 20:12:23.259129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 20:12:23.265659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 20:12:23.275130 [CA 0] Center 38 (7~69) winsize 63
812 20:12:23.278795 [CA 1] Center 38 (7~69) winsize 63
813 20:12:23.281843 [CA 2] Center 36 (5~67) winsize 63
814 20:12:23.285251 [CA 3] Center 35 (5~66) winsize 62
815 20:12:23.288289 [CA 4] Center 35 (4~66) winsize 63
816 20:12:23.292224 [CA 5] Center 34 (4~65) winsize 62
817 20:12:23.292312
818 20:12:23.295042 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 20:12:23.295130
820 20:12:23.298379 [CATrainingPosCal] consider 2 rank data
821 20:12:23.302233 u2DelayCellTimex100 = 270/100 ps
822 20:12:23.305019 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 20:12:23.308668 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 20:12:23.315172 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 20:12:23.318838 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 20:12:23.321872 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 20:12:23.325366 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 20:12:23.325454
829 20:12:23.329051 CA PerBit enable=1, Macro0, CA PI delay=34
830 20:12:23.329142
831 20:12:23.332016 [CBTSetCACLKResult] CA Dly = 34
832 20:12:23.332104 CS Dly: 6 (0~37)
833 20:12:23.332178
834 20:12:23.335161 ----->DramcWriteLeveling(PI) begin...
835 20:12:23.335250 ==
836 20:12:23.338995 Dram Type= 6, Freq= 0, CH_0, rank 0
837 20:12:23.345446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 20:12:23.345534 ==
839 20:12:23.348672 Write leveling (Byte 0): 28 => 28
840 20:12:23.352327 Write leveling (Byte 1): 28 => 28
841 20:12:23.352415 DramcWriteLeveling(PI) end<-----
842 20:12:23.352484
843 20:12:23.355352 ==
844 20:12:23.359014 Dram Type= 6, Freq= 0, CH_0, rank 0
845 20:12:23.362342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 20:12:23.362435 ==
847 20:12:23.365621 [Gating] SW mode calibration
848 20:12:23.372958 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 20:12:23.377205 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 20:12:23.380856 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 20:12:23.383975 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 20:12:23.390885 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 20:12:23.394357 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 20:12:23.397895 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 20:12:23.404859 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 20:12:23.408109 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 20:12:23.411436 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:12:23.415140 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:12:23.421708 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:12:23.424883 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:12:23.428434 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:12:23.435011 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:12:23.438359 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 20:12:23.441800 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 20:12:23.448537 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 20:12:23.451664 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 20:12:23.454758 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
868 20:12:23.461822 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 20:12:23.465045 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 20:12:23.468257 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 20:12:23.475010 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 20:12:23.478432 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 20:12:23.481899 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 20:12:23.484930 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 20:12:23.491669 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
876 20:12:23.494832 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 20:12:23.498243 0 9 12 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
878 20:12:23.504779 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 20:12:23.508480 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 20:12:23.511708 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 20:12:23.518302 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 20:12:23.521599 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 20:12:23.525123 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 20:12:23.531905 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
885 20:12:23.535044 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
886 20:12:23.539109 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 20:12:23.545099 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 20:12:23.548402 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 20:12:23.552037 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 20:12:23.558357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 20:12:23.561876 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
892 20:12:23.565187 0 11 8 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
893 20:12:23.568417 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
894 20:12:23.575164 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 20:12:23.578654 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 20:12:23.581841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 20:12:23.588233 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 20:12:23.592047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 20:12:23.595096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
900 20:12:23.601731 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 20:12:23.605669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 20:12:23.608628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 20:12:23.615372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 20:12:23.618324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 20:12:23.621656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 20:12:23.628424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 20:12:23.631793 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 20:12:23.634961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 20:12:23.641744 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 20:12:23.645234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 20:12:23.648282 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 20:12:23.651912 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 20:12:23.658389 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 20:12:23.661820 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 20:12:23.664883 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 20:12:23.671899 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 20:12:23.675236 Total UI for P1: 0, mck2ui 16
918 20:12:23.678462 best dqsien dly found for B0: ( 0, 14, 4)
919 20:12:23.681970 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 20:12:23.684983 Total UI for P1: 0, mck2ui 16
921 20:12:23.688477 best dqsien dly found for B1: ( 0, 14, 8)
922 20:12:23.691578 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 20:12:23.694779 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 20:12:23.694854
925 20:12:23.698447 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 20:12:23.701978 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 20:12:23.704932 [Gating] SW calibration Done
928 20:12:23.705008 ==
929 20:12:23.708291 Dram Type= 6, Freq= 0, CH_0, rank 0
930 20:12:23.711966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 20:12:23.714979 ==
932 20:12:23.715053 RX Vref Scan: 0
933 20:12:23.715117
934 20:12:23.718674 RX Vref 0 -> 0, step: 1
935 20:12:23.718747
936 20:12:23.721847 RX Delay -130 -> 252, step: 16
937 20:12:23.725259 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 20:12:23.728288 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 20:12:23.731654 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 20:12:23.735215 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 20:12:23.742047 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 20:12:23.745271 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 20:12:23.748879 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
944 20:12:23.752007 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 20:12:23.755362 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 20:12:23.758556 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 20:12:23.765330 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 20:12:23.768536 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 20:12:23.772166 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 20:12:23.775361 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 20:12:23.778447 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 20:12:23.785322 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 20:12:23.785420 ==
954 20:12:23.788495 Dram Type= 6, Freq= 0, CH_0, rank 0
955 20:12:23.792388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 20:12:23.792465 ==
957 20:12:23.792528 DQS Delay:
958 20:12:23.795215 DQS0 = 0, DQS1 = 0
959 20:12:23.795298 DQM Delay:
960 20:12:23.798840 DQM0 = 93, DQM1 = 80
961 20:12:23.798921 DQ Delay:
962 20:12:23.802036 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
963 20:12:23.805374 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
964 20:12:23.808795 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 20:12:23.811926 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 20:12:23.812011
967 20:12:23.812095
968 20:12:23.812158 ==
969 20:12:23.815402 Dram Type= 6, Freq= 0, CH_0, rank 0
970 20:12:23.818472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 20:12:23.822246 ==
972 20:12:23.822330
973 20:12:23.822396
974 20:12:23.822458 TX Vref Scan disable
975 20:12:23.825315 == TX Byte 0 ==
976 20:12:23.828717 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
977 20:12:23.832411 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
978 20:12:23.835269 == TX Byte 1 ==
979 20:12:23.838735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
980 20:12:23.842005 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
981 20:12:23.842117 ==
982 20:12:23.845505 Dram Type= 6, Freq= 0, CH_0, rank 0
983 20:12:23.851837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 20:12:23.851914 ==
985 20:12:23.863836 TX Vref=22, minBit 5, minWin=27, winSum=440
986 20:12:23.867372 TX Vref=24, minBit 11, minWin=26, winSum=443
987 20:12:23.870585 TX Vref=26, minBit 7, minWin=27, winSum=451
988 20:12:23.873844 TX Vref=28, minBit 8, minWin=27, winSum=454
989 20:12:23.876964 TX Vref=30, minBit 7, minWin=28, winSum=455
990 20:12:23.884045 TX Vref=32, minBit 11, minWin=27, winSum=452
991 20:12:23.887533 [TxChooseVref] Worse bit 7, Min win 28, Win sum 455, Final Vref 30
992 20:12:23.887611
993 20:12:23.891002 Final TX Range 1 Vref 30
994 20:12:23.891088
995 20:12:23.891151 ==
996 20:12:23.894115 Dram Type= 6, Freq= 0, CH_0, rank 0
997 20:12:23.897746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 20:12:23.897847 ==
999 20:12:23.897950
1000 20:12:23.898074
1001 20:12:23.900606 TX Vref Scan disable
1002 20:12:23.904283 == TX Byte 0 ==
1003 20:12:23.907491 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1004 20:12:23.910722 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1005 20:12:23.914315 == TX Byte 1 ==
1006 20:12:23.917484 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1007 20:12:23.921226 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1008 20:12:23.921331
1009 20:12:23.924682 [DATLAT]
1010 20:12:23.924784 Freq=800, CH0 RK0
1011 20:12:23.924875
1012 20:12:23.927589 DATLAT Default: 0xa
1013 20:12:23.927674 0, 0xFFFF, sum = 0
1014 20:12:23.930831 1, 0xFFFF, sum = 0
1015 20:12:23.930949 2, 0xFFFF, sum = 0
1016 20:12:23.934138 3, 0xFFFF, sum = 0
1017 20:12:23.934227 4, 0xFFFF, sum = 0
1018 20:12:23.937604 5, 0xFFFF, sum = 0
1019 20:12:23.937702 6, 0xFFFF, sum = 0
1020 20:12:23.940981 7, 0xFFFF, sum = 0
1021 20:12:23.941067 8, 0xFFFF, sum = 0
1022 20:12:23.944318 9, 0x0, sum = 1
1023 20:12:23.944407 10, 0x0, sum = 2
1024 20:12:23.947866 11, 0x0, sum = 3
1025 20:12:23.947955 12, 0x0, sum = 4
1026 20:12:23.950857 best_step = 10
1027 20:12:23.950969
1028 20:12:23.951063 ==
1029 20:12:23.954280 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 20:12:23.957540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 20:12:23.957624 ==
1032 20:12:23.960944 RX Vref Scan: 1
1033 20:12:23.961027
1034 20:12:23.961093 Set Vref Range= 32 -> 127
1035 20:12:23.961153
1036 20:12:23.964203 RX Vref 32 -> 127, step: 1
1037 20:12:23.964286
1038 20:12:23.967790 RX Delay -95 -> 252, step: 8
1039 20:12:23.967889
1040 20:12:23.971037 Set Vref, RX VrefLevel [Byte0]: 32
1041 20:12:23.974267 [Byte1]: 32
1042 20:12:23.974350
1043 20:12:23.977783 Set Vref, RX VrefLevel [Byte0]: 33
1044 20:12:23.981010 [Byte1]: 33
1045 20:12:23.981093
1046 20:12:23.984443 Set Vref, RX VrefLevel [Byte0]: 34
1047 20:12:23.987852 [Byte1]: 34
1048 20:12:23.991709
1049 20:12:23.991792 Set Vref, RX VrefLevel [Byte0]: 35
1050 20:12:23.994905 [Byte1]: 35
1051 20:12:23.999315
1052 20:12:23.999414 Set Vref, RX VrefLevel [Byte0]: 36
1053 20:12:24.002539 [Byte1]: 36
1054 20:12:24.007006
1055 20:12:24.007116 Set Vref, RX VrefLevel [Byte0]: 37
1056 20:12:24.010043 [Byte1]: 37
1057 20:12:24.014918
1058 20:12:24.015001 Set Vref, RX VrefLevel [Byte0]: 38
1059 20:12:24.018217 [Byte1]: 38
1060 20:12:24.022368
1061 20:12:24.022450 Set Vref, RX VrefLevel [Byte0]: 39
1062 20:12:24.025390 [Byte1]: 39
1063 20:12:24.029873
1064 20:12:24.029981 Set Vref, RX VrefLevel [Byte0]: 40
1065 20:12:24.033284 [Byte1]: 40
1066 20:12:24.037450
1067 20:12:24.037533 Set Vref, RX VrefLevel [Byte0]: 41
1068 20:12:24.040934 [Byte1]: 41
1069 20:12:24.045498
1070 20:12:24.045581 Set Vref, RX VrefLevel [Byte0]: 42
1071 20:12:24.048345 [Byte1]: 42
1072 20:12:24.052899
1073 20:12:24.052986 Set Vref, RX VrefLevel [Byte0]: 43
1074 20:12:24.056471 [Byte1]: 43
1075 20:12:24.060413
1076 20:12:24.060496 Set Vref, RX VrefLevel [Byte0]: 44
1077 20:12:24.063819 [Byte1]: 44
1078 20:12:24.068223
1079 20:12:24.068305 Set Vref, RX VrefLevel [Byte0]: 45
1080 20:12:24.071798 [Byte1]: 45
1081 20:12:24.075483
1082 20:12:24.075566 Set Vref, RX VrefLevel [Byte0]: 46
1083 20:12:24.079072 [Byte1]: 46
1084 20:12:24.083052
1085 20:12:24.083135 Set Vref, RX VrefLevel [Byte0]: 47
1086 20:12:24.086309 [Byte1]: 47
1087 20:12:24.090729
1088 20:12:24.090812 Set Vref, RX VrefLevel [Byte0]: 48
1089 20:12:24.093716 [Byte1]: 48
1090 20:12:24.098131
1091 20:12:24.098214 Set Vref, RX VrefLevel [Byte0]: 49
1092 20:12:24.101536 [Byte1]: 49
1093 20:12:24.105853
1094 20:12:24.105935 Set Vref, RX VrefLevel [Byte0]: 50
1095 20:12:24.108784 [Byte1]: 50
1096 20:12:24.113326
1097 20:12:24.113409 Set Vref, RX VrefLevel [Byte0]: 51
1098 20:12:24.120000 [Byte1]: 51
1099 20:12:24.120109
1100 20:12:24.123297 Set Vref, RX VrefLevel [Byte0]: 52
1101 20:12:24.126365 [Byte1]: 52
1102 20:12:24.126448
1103 20:12:24.130062 Set Vref, RX VrefLevel [Byte0]: 53
1104 20:12:24.133116 [Byte1]: 53
1105 20:12:24.133198
1106 20:12:24.136324 Set Vref, RX VrefLevel [Byte0]: 54
1107 20:12:24.139566 [Byte1]: 54
1108 20:12:24.143702
1109 20:12:24.143784 Set Vref, RX VrefLevel [Byte0]: 55
1110 20:12:24.147414 [Byte1]: 55
1111 20:12:24.151615
1112 20:12:24.151698 Set Vref, RX VrefLevel [Byte0]: 56
1113 20:12:24.154623 [Byte1]: 56
1114 20:12:24.159134
1115 20:12:24.159217 Set Vref, RX VrefLevel [Byte0]: 57
1116 20:12:24.162376 [Byte1]: 57
1117 20:12:24.166566
1118 20:12:24.166649 Set Vref, RX VrefLevel [Byte0]: 58
1119 20:12:24.169969 [Byte1]: 58
1120 20:12:24.174184
1121 20:12:24.174267 Set Vref, RX VrefLevel [Byte0]: 59
1122 20:12:24.177259 [Byte1]: 59
1123 20:12:24.182077
1124 20:12:24.182159 Set Vref, RX VrefLevel [Byte0]: 60
1125 20:12:24.185022 [Byte1]: 60
1126 20:12:24.189207
1127 20:12:24.189290 Set Vref, RX VrefLevel [Byte0]: 61
1128 20:12:24.192458 [Byte1]: 61
1129 20:12:24.196938
1130 20:12:24.197020 Set Vref, RX VrefLevel [Byte0]: 62
1131 20:12:24.200336 [Byte1]: 62
1132 20:12:24.204234
1133 20:12:24.204317 Set Vref, RX VrefLevel [Byte0]: 63
1134 20:12:24.208031 [Byte1]: 63
1135 20:12:24.211939
1136 20:12:24.212038 Set Vref, RX VrefLevel [Byte0]: 64
1137 20:12:24.218730 [Byte1]: 64
1138 20:12:24.218817
1139 20:12:24.222130 Set Vref, RX VrefLevel [Byte0]: 65
1140 20:12:24.225225 [Byte1]: 65
1141 20:12:24.225309
1142 20:12:24.228538 Set Vref, RX VrefLevel [Byte0]: 66
1143 20:12:24.231737 [Byte1]: 66
1144 20:12:24.231840
1145 20:12:24.235423 Set Vref, RX VrefLevel [Byte0]: 67
1146 20:12:24.238252 [Byte1]: 67
1147 20:12:24.242195
1148 20:12:24.242278 Set Vref, RX VrefLevel [Byte0]: 68
1149 20:12:24.245543 [Byte1]: 68
1150 20:12:24.249979
1151 20:12:24.250064 Set Vref, RX VrefLevel [Byte0]: 69
1152 20:12:24.253369 [Byte1]: 69
1153 20:12:24.257620
1154 20:12:24.257704 Set Vref, RX VrefLevel [Byte0]: 70
1155 20:12:24.260865 [Byte1]: 70
1156 20:12:24.265226
1157 20:12:24.265321 Set Vref, RX VrefLevel [Byte0]: 71
1158 20:12:24.268576 [Byte1]: 71
1159 20:12:24.272582
1160 20:12:24.272695 Set Vref, RX VrefLevel [Byte0]: 72
1161 20:12:24.276234 [Byte1]: 72
1162 20:12:24.280531
1163 20:12:24.280609 Set Vref, RX VrefLevel [Byte0]: 73
1164 20:12:24.283684 [Byte1]: 73
1165 20:12:24.287893
1166 20:12:24.287980 Set Vref, RX VrefLevel [Byte0]: 74
1167 20:12:24.291436 [Byte1]: 74
1168 20:12:24.295741
1169 20:12:24.295847 Set Vref, RX VrefLevel [Byte0]: 75
1170 20:12:24.299043 [Byte1]: 75
1171 20:12:24.303453
1172 20:12:24.303542 Set Vref, RX VrefLevel [Byte0]: 76
1173 20:12:24.306724 [Byte1]: 76
1174 20:12:24.310968
1175 20:12:24.311044 Set Vref, RX VrefLevel [Byte0]: 77
1176 20:12:24.314163 [Byte1]: 77
1177 20:12:24.318749
1178 20:12:24.318825 Final RX Vref Byte 0 = 61 to rank0
1179 20:12:24.321991 Final RX Vref Byte 1 = 61 to rank0
1180 20:12:24.325387 Final RX Vref Byte 0 = 61 to rank1
1181 20:12:24.328280 Final RX Vref Byte 1 = 61 to rank1==
1182 20:12:24.331858 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 20:12:24.338692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 20:12:24.338772 ==
1185 20:12:24.338837 DQS Delay:
1186 20:12:24.338933 DQS0 = 0, DQS1 = 0
1187 20:12:24.341828 DQM Delay:
1188 20:12:24.341903 DQM0 = 93, DQM1 = 83
1189 20:12:24.345252 DQ Delay:
1190 20:12:24.348297 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1191 20:12:24.351729 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1192 20:12:24.355244 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1193 20:12:24.358754 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1194 20:12:24.358838
1195 20:12:24.358901
1196 20:12:24.365328 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1197 20:12:24.368393 CH0 RK0: MR19=606, MR18=3D38
1198 20:12:24.375293 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1199 20:12:24.375371
1200 20:12:24.378653 ----->DramcWriteLeveling(PI) begin...
1201 20:12:24.378730 ==
1202 20:12:24.381867 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 20:12:24.385430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 20:12:24.385503 ==
1205 20:12:24.388460 Write leveling (Byte 0): 31 => 31
1206 20:12:24.391953 Write leveling (Byte 1): 30 => 30
1207 20:12:24.395656 DramcWriteLeveling(PI) end<-----
1208 20:12:24.395733
1209 20:12:24.395797 ==
1210 20:12:24.398627 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 20:12:24.402048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 20:12:24.402124 ==
1213 20:12:24.405133 [Gating] SW mode calibration
1214 20:12:24.411648 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 20:12:24.418765 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 20:12:24.421833 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 20:12:24.425230 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 20:12:24.431873 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 20:12:24.435464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 20:12:24.438742 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 20:12:24.482792 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 20:12:24.483349 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 20:12:24.483617 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 20:12:24.483910 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 20:12:24.484008 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 20:12:24.484110 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 20:12:24.484207 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 20:12:24.484484 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 20:12:24.484831 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 20:12:24.484930 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 20:12:24.516042 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 20:12:24.516442 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 20:12:24.517135 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1234 20:12:24.517390 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 20:12:24.517459 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 20:12:24.517971 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 20:12:24.518240 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 20:12:24.520898 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 20:12:24.524243 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 20:12:24.527759 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 20:12:24.531321 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1242 20:12:24.537757 0 9 8 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (1 1)
1243 20:12:24.540869 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 20:12:24.544296 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 20:12:24.550954 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 20:12:24.554004 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 20:12:24.557339 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 20:12:24.560906 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 20:12:24.567670 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
1250 20:12:24.570839 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1251 20:12:24.574282 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 20:12:24.580927 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 20:12:24.584410 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 20:12:24.587793 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 20:12:24.594299 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 20:12:24.597553 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 20:12:24.600845 0 11 4 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
1258 20:12:24.607503 0 11 8 | B1->B0 | 3737 4242 | 0 0 | (1 1) (0 0)
1259 20:12:24.611042 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 20:12:24.614090 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 20:12:24.622015 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 20:12:24.625244 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 20:12:24.629164 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 20:12:24.632509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 20:12:24.636249 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 20:12:24.642764 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 20:12:24.646323 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 20:12:24.649870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 20:12:24.653324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 20:12:24.660093 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 20:12:24.663621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 20:12:24.666929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 20:12:24.673785 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 20:12:24.676753 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 20:12:24.679897 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 20:12:24.686779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 20:12:24.690372 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 20:12:24.693514 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 20:12:24.700083 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 20:12:24.703352 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 20:12:24.706905 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 20:12:24.713005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 20:12:24.713087 Total UI for P1: 0, mck2ui 16
1284 20:12:24.719950 best dqsien dly found for B0: ( 0, 14, 4)
1285 20:12:24.720073 Total UI for P1: 0, mck2ui 16
1286 20:12:24.723432 best dqsien dly found for B1: ( 0, 14, 4)
1287 20:12:24.730089 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1288 20:12:24.733245 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1289 20:12:24.733397
1290 20:12:24.736724 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1291 20:12:24.740036 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 20:12:24.743111 [Gating] SW calibration Done
1293 20:12:24.743268 ==
1294 20:12:24.746378 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 20:12:24.750079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 20:12:24.750176 ==
1297 20:12:24.753124 RX Vref Scan: 0
1298 20:12:24.753259
1299 20:12:24.753385 RX Vref 0 -> 0, step: 1
1300 20:12:24.753492
1301 20:12:24.756700 RX Delay -130 -> 252, step: 16
1302 20:12:24.759703 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1303 20:12:24.766339 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1304 20:12:24.769784 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1305 20:12:24.773101 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1306 20:12:24.776637 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1307 20:12:24.779767 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1308 20:12:24.786463 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1309 20:12:24.789689 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1310 20:12:24.793166 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1311 20:12:24.796786 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1312 20:12:24.799624 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1313 20:12:24.806334 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1314 20:12:24.809860 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1315 20:12:24.813026 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1316 20:12:24.816504 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1317 20:12:24.819655 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1318 20:12:24.819742 ==
1319 20:12:24.823246 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 20:12:24.829639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 20:12:24.829726 ==
1322 20:12:24.829794 DQS Delay:
1323 20:12:24.833321 DQS0 = 0, DQS1 = 0
1324 20:12:24.833407 DQM Delay:
1325 20:12:24.836318 DQM0 = 89, DQM1 = 78
1326 20:12:24.836405 DQ Delay:
1327 20:12:24.839658 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1328 20:12:24.843091 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1329 20:12:24.846531 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1330 20:12:24.849708 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
1331 20:12:24.849794
1332 20:12:24.849863
1333 20:12:24.849926 ==
1334 20:12:24.853102 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 20:12:24.856520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 20:12:24.856606 ==
1337 20:12:24.856674
1338 20:12:24.856739
1339 20:12:24.860028 TX Vref Scan disable
1340 20:12:24.863211 == TX Byte 0 ==
1341 20:12:24.866548 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1342 20:12:24.869841 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1343 20:12:24.869928 == TX Byte 1 ==
1344 20:12:24.876775 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1345 20:12:24.880178 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1346 20:12:24.880265 ==
1347 20:12:24.883300 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 20:12:24.886781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 20:12:24.886867 ==
1350 20:12:24.901100 TX Vref=22, minBit 8, minWin=27, winSum=445
1351 20:12:24.904446 TX Vref=24, minBit 8, minWin=27, winSum=446
1352 20:12:24.907987 TX Vref=26, minBit 8, minWin=27, winSum=452
1353 20:12:24.910991 TX Vref=28, minBit 8, minWin=27, winSum=454
1354 20:12:24.914517 TX Vref=30, minBit 8, minWin=27, winSum=458
1355 20:12:24.917854 TX Vref=32, minBit 10, minWin=27, winSum=456
1356 20:12:24.924382 [TxChooseVref] Worse bit 8, Min win 27, Win sum 458, Final Vref 30
1357 20:12:24.924474
1358 20:12:24.927679 Final TX Range 1 Vref 30
1359 20:12:24.927787
1360 20:12:24.927879 ==
1361 20:12:24.930988 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 20:12:24.934805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 20:12:24.934892 ==
1364 20:12:24.934957
1365 20:12:24.935016
1366 20:12:24.937916 TX Vref Scan disable
1367 20:12:24.941033 == TX Byte 0 ==
1368 20:12:24.944177 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1369 20:12:24.947727 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1370 20:12:24.950826 == TX Byte 1 ==
1371 20:12:24.954119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1372 20:12:24.957651 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1373 20:12:24.961134
1374 20:12:24.961214 [DATLAT]
1375 20:12:24.961277 Freq=800, CH0 RK1
1376 20:12:24.961337
1377 20:12:24.964131 DATLAT Default: 0xa
1378 20:12:24.964214 0, 0xFFFF, sum = 0
1379 20:12:24.967693 1, 0xFFFF, sum = 0
1380 20:12:24.967776 2, 0xFFFF, sum = 0
1381 20:12:24.970798 3, 0xFFFF, sum = 0
1382 20:12:24.970880 4, 0xFFFF, sum = 0
1383 20:12:24.974163 5, 0xFFFF, sum = 0
1384 20:12:24.974245 6, 0xFFFF, sum = 0
1385 20:12:24.977329 7, 0xFFFF, sum = 0
1386 20:12:24.980622 8, 0xFFFF, sum = 0
1387 20:12:24.980705 9, 0x0, sum = 1
1388 20:12:24.980770 10, 0x0, sum = 2
1389 20:12:24.984225 11, 0x0, sum = 3
1390 20:12:24.984306 12, 0x0, sum = 4
1391 20:12:24.987625 best_step = 10
1392 20:12:24.987706
1393 20:12:24.987769 ==
1394 20:12:24.991205 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 20:12:24.994427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 20:12:24.994509 ==
1397 20:12:24.997990 RX Vref Scan: 0
1398 20:12:24.998085
1399 20:12:24.998149 RX Vref 0 -> 0, step: 1
1400 20:12:24.998209
1401 20:12:25.000885 RX Delay -79 -> 252, step: 8
1402 20:12:25.007777 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1403 20:12:25.011245 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1404 20:12:25.014171 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 20:12:25.017700 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1406 20:12:25.021361 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 20:12:25.027462 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1408 20:12:25.030891 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 20:12:25.034276 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 20:12:25.037839 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1411 20:12:25.041126 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1412 20:12:25.047793 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1413 20:12:25.051190 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1414 20:12:25.054688 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1415 20:12:25.057822 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 20:12:25.061115 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 20:12:25.068112 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1418 20:12:25.068234 ==
1419 20:12:25.071343 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 20:12:25.074878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 20:12:25.074987 ==
1422 20:12:25.075080 DQS Delay:
1423 20:12:25.078260 DQS0 = 0, DQS1 = 0
1424 20:12:25.078335 DQM Delay:
1425 20:12:25.081371 DQM0 = 91, DQM1 = 81
1426 20:12:25.081478 DQ Delay:
1427 20:12:25.084327 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1428 20:12:25.088073 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1429 20:12:25.091224 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1430 20:12:25.094539 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1431 20:12:25.094628
1432 20:12:25.094693
1433 20:12:25.101357 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1434 20:12:25.104347 CH0 RK1: MR19=606, MR18=3F19
1435 20:12:25.111446 CH0_RK1: MR19=0x606, MR18=0x3F19, DQSOSC=393, MR23=63, INC=95, DEC=63
1436 20:12:25.114641 [RxdqsGatingPostProcess] freq 800
1437 20:12:25.121274 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 20:12:25.121359 Pre-setting of DQS Precalculation
1439 20:12:25.127925 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 20:12:25.128010 ==
1441 20:12:25.131150 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 20:12:25.134532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 20:12:25.134617 ==
1444 20:12:25.141100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 20:12:25.147575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 20:12:25.155899 [CA 0] Center 36 (6~67) winsize 62
1447 20:12:25.159236 [CA 1] Center 36 (6~67) winsize 62
1448 20:12:25.162757 [CA 2] Center 35 (5~65) winsize 61
1449 20:12:25.166110 [CA 3] Center 34 (4~65) winsize 62
1450 20:12:25.169545 [CA 4] Center 34 (4~65) winsize 62
1451 20:12:25.172580 [CA 5] Center 33 (3~64) winsize 62
1452 20:12:25.172665
1453 20:12:25.175696 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1454 20:12:25.175780
1455 20:12:25.179636 [CATrainingPosCal] consider 1 rank data
1456 20:12:25.182643 u2DelayCellTimex100 = 270/100 ps
1457 20:12:25.185833 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1458 20:12:25.189417 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 20:12:25.196054 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1460 20:12:25.199831 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 20:12:25.202785 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 20:12:25.205825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 20:12:25.205957
1464 20:12:25.209340 CA PerBit enable=1, Macro0, CA PI delay=33
1465 20:12:25.209424
1466 20:12:25.212815 [CBTSetCACLKResult] CA Dly = 33
1467 20:12:25.212900 CS Dly: 5 (0~36)
1468 20:12:25.212967 ==
1469 20:12:25.216133 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 20:12:25.222991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 20:12:25.223076 ==
1472 20:12:25.226333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 20:12:25.232777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 20:12:25.242164 [CA 0] Center 37 (7~68) winsize 62
1475 20:12:25.245641 [CA 1] Center 37 (7~68) winsize 62
1476 20:12:25.248714 [CA 2] Center 35 (5~66) winsize 62
1477 20:12:25.252255 [CA 3] Center 34 (4~65) winsize 62
1478 20:12:25.255752 [CA 4] Center 35 (5~65) winsize 61
1479 20:12:25.258852 [CA 5] Center 34 (4~65) winsize 62
1480 20:12:25.258936
1481 20:12:25.262387 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1482 20:12:25.262471
1483 20:12:25.265482 [CATrainingPosCal] consider 2 rank data
1484 20:12:25.269263 u2DelayCellTimex100 = 270/100 ps
1485 20:12:25.272406 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1486 20:12:25.275728 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1487 20:12:25.278823 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 20:12:25.283032 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 20:12:25.286471 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1490 20:12:25.290288 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 20:12:25.293825
1492 20:12:25.297730 CA PerBit enable=1, Macro0, CA PI delay=34
1493 20:12:25.297842
1494 20:12:25.297962 [CBTSetCACLKResult] CA Dly = 34
1495 20:12:25.301062 CS Dly: 5 (0~37)
1496 20:12:25.301146
1497 20:12:25.304663 ----->DramcWriteLeveling(PI) begin...
1498 20:12:25.304749 ==
1499 20:12:25.308471 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 20:12:25.312479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 20:12:25.312559 ==
1502 20:12:25.316161 Write leveling (Byte 0): 26 => 26
1503 20:12:25.316259 Write leveling (Byte 1): 31 => 31
1504 20:12:25.320040 DramcWriteLeveling(PI) end<-----
1505 20:12:25.320119
1506 20:12:25.320182 ==
1507 20:12:25.323077 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 20:12:25.329799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 20:12:25.329922 ==
1510 20:12:25.330015 [Gating] SW mode calibration
1511 20:12:25.340136 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 20:12:25.343360 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 20:12:25.346634 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 20:12:25.353000 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1515 20:12:25.356348 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 20:12:25.360147 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 20:12:25.366513 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 20:12:25.369986 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 20:12:25.373077 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 20:12:25.380189 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 20:12:25.383013 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 20:12:25.386550 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 20:12:25.393092 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 20:12:25.396592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 20:12:25.399786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 20:12:25.406826 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 20:12:25.410236 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 20:12:25.413647 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1529 20:12:25.416949 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1530 20:12:25.423550 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1531 20:12:25.426787 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 20:12:25.430127 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 20:12:25.436794 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 20:12:25.440461 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 20:12:25.443588 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 20:12:25.450084 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 20:12:25.453666 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 20:12:25.456966 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1539 20:12:25.463315 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1540 20:12:25.466898 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 20:12:25.470209 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 20:12:25.476808 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 20:12:25.480213 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 20:12:25.483792 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 20:12:25.487013 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1546 20:12:25.493669 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
1547 20:12:25.497105 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 20:12:25.500516 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 20:12:25.506929 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 20:12:25.510463 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 20:12:25.513715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 20:12:25.520254 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 20:12:25.523964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 20:12:25.526906 0 11 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
1555 20:12:25.533886 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 20:12:25.536896 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 20:12:25.540473 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 20:12:25.546848 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 20:12:25.550213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 20:12:25.553332 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 20:12:25.560373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1562 20:12:25.563681 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1563 20:12:25.567070 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 20:12:25.573676 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 20:12:25.576785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 20:12:25.580357 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 20:12:25.583555 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 20:12:25.590393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 20:12:25.593761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 20:12:25.596926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 20:12:25.603607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 20:12:25.606924 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 20:12:25.610597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 20:12:25.616998 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 20:12:25.620193 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 20:12:25.623379 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 20:12:25.630167 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 20:12:25.633495 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1579 20:12:25.636737 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 20:12:25.640333 Total UI for P1: 0, mck2ui 16
1581 20:12:25.643893 best dqsien dly found for B0: ( 0, 14, 2)
1582 20:12:25.647176 Total UI for P1: 0, mck2ui 16
1583 20:12:25.650481 best dqsien dly found for B1: ( 0, 14, 2)
1584 20:12:25.653440 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1585 20:12:25.657000 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1586 20:12:25.657085
1587 20:12:25.660331 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1588 20:12:25.667100 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1589 20:12:25.667186 [Gating] SW calibration Done
1590 20:12:25.667252 ==
1591 20:12:25.670123 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 20:12:25.676978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 20:12:25.677063 ==
1594 20:12:25.677130 RX Vref Scan: 0
1595 20:12:25.677192
1596 20:12:25.680306 RX Vref 0 -> 0, step: 1
1597 20:12:25.680390
1598 20:12:25.683913 RX Delay -130 -> 252, step: 16
1599 20:12:25.686870 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 20:12:25.690411 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 20:12:25.693493 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1602 20:12:25.700502 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 20:12:25.703700 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1604 20:12:25.707137 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1605 20:12:25.710742 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 20:12:25.713890 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 20:12:25.717093 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1608 20:12:25.723766 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1609 20:12:25.727452 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1610 20:12:25.730735 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 20:12:25.734273 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 20:12:25.737181 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 20:12:25.744235 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1614 20:12:25.747292 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1615 20:12:25.747376 ==
1616 20:12:25.750825 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 20:12:25.753890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 20:12:25.754012 ==
1619 20:12:25.757410 DQS Delay:
1620 20:12:25.757494 DQS0 = 0, DQS1 = 0
1621 20:12:25.757576 DQM Delay:
1622 20:12:25.760698 DQM0 = 92, DQM1 = 85
1623 20:12:25.760782 DQ Delay:
1624 20:12:25.764151 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1625 20:12:25.767373 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1626 20:12:25.770685 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1627 20:12:25.774236 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1628 20:12:25.774321
1629 20:12:25.774387
1630 20:12:25.774448 ==
1631 20:12:25.777640 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 20:12:25.784255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 20:12:25.784340 ==
1634 20:12:25.784407
1635 20:12:25.784468
1636 20:12:25.784527 TX Vref Scan disable
1637 20:12:25.787546 == TX Byte 0 ==
1638 20:12:25.791099 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1639 20:12:25.794260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1640 20:12:25.798078 == TX Byte 1 ==
1641 20:12:25.801070 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1642 20:12:25.804310 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1643 20:12:25.807869 ==
1644 20:12:25.811233 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 20:12:25.814593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 20:12:25.814677 ==
1647 20:12:25.827676 TX Vref=22, minBit 8, minWin=27, winSum=447
1648 20:12:25.830798 TX Vref=24, minBit 8, minWin=27, winSum=448
1649 20:12:25.834055 TX Vref=26, minBit 15, minWin=27, winSum=456
1650 20:12:25.837291 TX Vref=28, minBit 15, minWin=27, winSum=456
1651 20:12:25.840433 TX Vref=30, minBit 8, minWin=27, winSum=456
1652 20:12:25.847182 TX Vref=32, minBit 8, minWin=27, winSum=456
1653 20:12:25.850410 [TxChooseVref] Worse bit 15, Min win 27, Win sum 456, Final Vref 26
1654 20:12:25.850495
1655 20:12:25.853782 Final TX Range 1 Vref 26
1656 20:12:25.853894
1657 20:12:25.854012 ==
1658 20:12:25.857155 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 20:12:25.860873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 20:12:25.860958 ==
1661 20:12:25.863784
1662 20:12:25.863901
1663 20:12:25.863970 TX Vref Scan disable
1664 20:12:25.868100 == TX Byte 0 ==
1665 20:12:25.871553 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1666 20:12:25.874902 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1667 20:12:25.878256 == TX Byte 1 ==
1668 20:12:25.881670 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1669 20:12:25.884832 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1670 20:12:25.884916
1671 20:12:25.887954 [DATLAT]
1672 20:12:25.888038 Freq=800, CH1 RK0
1673 20:12:25.888104
1674 20:12:25.891370 DATLAT Default: 0xa
1675 20:12:25.891453 0, 0xFFFF, sum = 0
1676 20:12:25.894634 1, 0xFFFF, sum = 0
1677 20:12:25.894720 2, 0xFFFF, sum = 0
1678 20:12:25.898572 3, 0xFFFF, sum = 0
1679 20:12:25.898668 4, 0xFFFF, sum = 0
1680 20:12:25.901417 5, 0xFFFF, sum = 0
1681 20:12:25.901502 6, 0xFFFF, sum = 0
1682 20:12:25.904821 7, 0xFFFF, sum = 0
1683 20:12:25.904906 8, 0xFFFF, sum = 0
1684 20:12:25.908288 9, 0x0, sum = 1
1685 20:12:25.908376 10, 0x0, sum = 2
1686 20:12:25.911533 11, 0x0, sum = 3
1687 20:12:25.911619 12, 0x0, sum = 4
1688 20:12:25.914613 best_step = 10
1689 20:12:25.914696
1690 20:12:25.914762 ==
1691 20:12:25.918202 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 20:12:25.921345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 20:12:25.921429 ==
1694 20:12:25.921496 RX Vref Scan: 1
1695 20:12:25.925064
1696 20:12:25.925147 Set Vref Range= 32 -> 127
1697 20:12:25.925213
1698 20:12:25.928278 RX Vref 32 -> 127, step: 1
1699 20:12:25.928362
1700 20:12:25.931346 RX Delay -95 -> 252, step: 8
1701 20:12:25.931430
1702 20:12:25.935039 Set Vref, RX VrefLevel [Byte0]: 32
1703 20:12:25.938590 [Byte1]: 32
1704 20:12:25.938674
1705 20:12:25.941528 Set Vref, RX VrefLevel [Byte0]: 33
1706 20:12:25.944823 [Byte1]: 33
1707 20:12:25.944907
1708 20:12:25.948011 Set Vref, RX VrefLevel [Byte0]: 34
1709 20:12:25.951757 [Byte1]: 34
1710 20:12:25.955206
1711 20:12:25.955289 Set Vref, RX VrefLevel [Byte0]: 35
1712 20:12:25.958456 [Byte1]: 35
1713 20:12:25.962675
1714 20:12:25.962759 Set Vref, RX VrefLevel [Byte0]: 36
1715 20:12:25.966157 [Byte1]: 36
1716 20:12:25.970567
1717 20:12:25.970651 Set Vref, RX VrefLevel [Byte0]: 37
1718 20:12:25.973806 [Byte1]: 37
1719 20:12:25.977861
1720 20:12:25.978005 Set Vref, RX VrefLevel [Byte0]: 38
1721 20:12:25.981313 [Byte1]: 38
1722 20:12:25.985376
1723 20:12:25.985460 Set Vref, RX VrefLevel [Byte0]: 39
1724 20:12:25.988885 [Byte1]: 39
1725 20:12:25.993264
1726 20:12:25.993347 Set Vref, RX VrefLevel [Byte0]: 40
1727 20:12:25.996539 [Byte1]: 40
1728 20:12:26.000811
1729 20:12:26.000894 Set Vref, RX VrefLevel [Byte0]: 41
1730 20:12:26.004201 [Byte1]: 41
1731 20:12:26.008648
1732 20:12:26.008732 Set Vref, RX VrefLevel [Byte0]: 42
1733 20:12:26.012236 [Byte1]: 42
1734 20:12:26.016013
1735 20:12:26.016097 Set Vref, RX VrefLevel [Byte0]: 43
1736 20:12:26.019394 [Byte1]: 43
1737 20:12:26.023987
1738 20:12:26.024071 Set Vref, RX VrefLevel [Byte0]: 44
1739 20:12:26.027045 [Byte1]: 44
1740 20:12:26.031397
1741 20:12:26.031481 Set Vref, RX VrefLevel [Byte0]: 45
1742 20:12:26.034535 [Byte1]: 45
1743 20:12:26.038712
1744 20:12:26.038796 Set Vref, RX VrefLevel [Byte0]: 46
1745 20:12:26.042262 [Byte1]: 46
1746 20:12:26.046322
1747 20:12:26.046405 Set Vref, RX VrefLevel [Byte0]: 47
1748 20:12:26.049775 [Byte1]: 47
1749 20:12:26.054251
1750 20:12:26.054335 Set Vref, RX VrefLevel [Byte0]: 48
1751 20:12:26.057386 [Byte1]: 48
1752 20:12:26.061331
1753 20:12:26.061414 Set Vref, RX VrefLevel [Byte0]: 49
1754 20:12:26.064745 [Byte1]: 49
1755 20:12:26.069229
1756 20:12:26.069313 Set Vref, RX VrefLevel [Byte0]: 50
1757 20:12:26.072522 [Byte1]: 50
1758 20:12:26.076791
1759 20:12:26.076874 Set Vref, RX VrefLevel [Byte0]: 51
1760 20:12:26.080220 [Byte1]: 51
1761 20:12:26.084322
1762 20:12:26.084406 Set Vref, RX VrefLevel [Byte0]: 52
1763 20:12:26.087617 [Byte1]: 52
1764 20:12:26.091814
1765 20:12:26.091898 Set Vref, RX VrefLevel [Byte0]: 53
1766 20:12:26.095331 [Byte1]: 53
1767 20:12:26.099683
1768 20:12:26.099766 Set Vref, RX VrefLevel [Byte0]: 54
1769 20:12:26.102990 [Byte1]: 54
1770 20:12:26.106992
1771 20:12:26.107122 Set Vref, RX VrefLevel [Byte0]: 55
1772 20:12:26.110851 [Byte1]: 55
1773 20:12:26.114761
1774 20:12:26.114844 Set Vref, RX VrefLevel [Byte0]: 56
1775 20:12:26.118083 [Byte1]: 56
1776 20:12:26.122230
1777 20:12:26.122313 Set Vref, RX VrefLevel [Byte0]: 57
1778 20:12:26.125622 [Byte1]: 57
1779 20:12:26.130153
1780 20:12:26.130236 Set Vref, RX VrefLevel [Byte0]: 58
1781 20:12:26.133381 [Byte1]: 58
1782 20:12:26.137571
1783 20:12:26.137655 Set Vref, RX VrefLevel [Byte0]: 59
1784 20:12:26.140789 [Byte1]: 59
1785 20:12:26.145185
1786 20:12:26.145269 Set Vref, RX VrefLevel [Byte0]: 60
1787 20:12:26.148251 [Byte1]: 60
1788 20:12:26.152551
1789 20:12:26.152635 Set Vref, RX VrefLevel [Byte0]: 61
1790 20:12:26.155940 [Byte1]: 61
1791 20:12:26.160551
1792 20:12:26.160635 Set Vref, RX VrefLevel [Byte0]: 62
1793 20:12:26.163659 [Byte1]: 62
1794 20:12:26.167737
1795 20:12:26.167820 Set Vref, RX VrefLevel [Byte0]: 63
1796 20:12:26.171219 [Byte1]: 63
1797 20:12:26.175464
1798 20:12:26.175574 Set Vref, RX VrefLevel [Byte0]: 64
1799 20:12:26.178948 [Byte1]: 64
1800 20:12:26.183088
1801 20:12:26.183172 Set Vref, RX VrefLevel [Byte0]: 65
1802 20:12:26.186381 [Byte1]: 65
1803 20:12:26.190743
1804 20:12:26.190827 Set Vref, RX VrefLevel [Byte0]: 66
1805 20:12:26.194088 [Byte1]: 66
1806 20:12:26.198360
1807 20:12:26.198444 Set Vref, RX VrefLevel [Byte0]: 67
1808 20:12:26.201994 [Byte1]: 67
1809 20:12:26.205844
1810 20:12:26.205958 Set Vref, RX VrefLevel [Byte0]: 68
1811 20:12:26.209412 [Byte1]: 68
1812 20:12:26.213536
1813 20:12:26.213619 Set Vref, RX VrefLevel [Byte0]: 69
1814 20:12:26.216620 [Byte1]: 69
1815 20:12:26.221128
1816 20:12:26.221212 Set Vref, RX VrefLevel [Byte0]: 70
1817 20:12:26.224240 [Byte1]: 70
1818 20:12:26.228613
1819 20:12:26.228697 Set Vref, RX VrefLevel [Byte0]: 71
1820 20:12:26.232091 [Byte1]: 71
1821 20:12:26.236371
1822 20:12:26.236454 Set Vref, RX VrefLevel [Byte0]: 72
1823 20:12:26.239575 [Byte1]: 72
1824 20:12:26.243712
1825 20:12:26.243822 Set Vref, RX VrefLevel [Byte0]: 73
1826 20:12:26.247278 [Byte1]: 73
1827 20:12:26.251653
1828 20:12:26.251752 Set Vref, RX VrefLevel [Byte0]: 74
1829 20:12:26.254914 [Byte1]: 74
1830 20:12:26.259256
1831 20:12:26.259354 Final RX Vref Byte 0 = 52 to rank0
1832 20:12:26.262384 Final RX Vref Byte 1 = 62 to rank0
1833 20:12:26.266021 Final RX Vref Byte 0 = 52 to rank1
1834 20:12:26.269233 Final RX Vref Byte 1 = 62 to rank1==
1835 20:12:26.272677 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 20:12:26.279271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 20:12:26.279347 ==
1838 20:12:26.279423 DQS Delay:
1839 20:12:26.279486 DQS0 = 0, DQS1 = 0
1840 20:12:26.282661 DQM Delay:
1841 20:12:26.282757 DQM0 = 92, DQM1 = 83
1842 20:12:26.285741 DQ Delay:
1843 20:12:26.289637 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1844 20:12:26.289742 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1845 20:12:26.292450 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1846 20:12:26.298750 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1847 20:12:26.298852
1848 20:12:26.298952
1849 20:12:26.305859 [DQSOSCAuto] RK0, (LSB)MR18= 0x304e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1850 20:12:26.309277 CH1 RK0: MR19=606, MR18=304E
1851 20:12:26.315649 CH1_RK0: MR19=0x606, MR18=0x304E, DQSOSC=390, MR23=63, INC=97, DEC=64
1852 20:12:26.315753
1853 20:12:26.319476 ----->DramcWriteLeveling(PI) begin...
1854 20:12:26.319578 ==
1855 20:12:26.322621 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 20:12:26.325699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 20:12:26.325809 ==
1858 20:12:26.328976 Write leveling (Byte 0): 29 => 29
1859 20:12:26.332617 Write leveling (Byte 1): 30 => 30
1860 20:12:26.336158 DramcWriteLeveling(PI) end<-----
1861 20:12:26.336262
1862 20:12:26.336353 ==
1863 20:12:26.339079 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 20:12:26.342255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 20:12:26.342364 ==
1866 20:12:26.345669 [Gating] SW mode calibration
1867 20:12:26.352706 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 20:12:26.358949 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 20:12:26.362595 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 20:12:26.366172 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1871 20:12:26.372466 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 20:12:26.375774 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 20:12:26.379124 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 20:12:26.386135 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 20:12:26.389274 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 20:12:26.392575 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 20:12:26.399273 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 20:12:26.402625 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 20:12:26.405999 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 20:12:26.412415 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 20:12:26.415873 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 20:12:26.419249 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 20:12:26.422846 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 20:12:26.429231 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 20:12:26.432670 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 20:12:26.436336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1887 20:12:26.442435 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 20:12:26.445715 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 20:12:26.449001 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 20:12:26.455788 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 20:12:26.459114 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 20:12:26.462784 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 20:12:26.468917 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 20:12:26.472490 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 20:12:26.475720 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1896 20:12:26.482551 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 20:12:26.486114 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 20:12:26.489001 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 20:12:26.495775 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 20:12:26.499469 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 20:12:26.502574 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1902 20:12:26.509044 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1903 20:12:26.512653 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
1904 20:12:26.515743 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 20:12:26.519197 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 20:12:26.526086 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 20:12:26.529216 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 20:12:26.532553 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 20:12:26.539358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 20:12:26.542701 0 11 4 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
1911 20:12:26.545922 0 11 8 | B1->B0 | 4545 3c3c | 0 0 | (0 0) (0 0)
1912 20:12:26.552561 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 20:12:26.555964 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 20:12:26.559227 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 20:12:26.565703 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 20:12:26.569429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 20:12:26.572424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 20:12:26.579226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 20:12:26.582326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 20:12:26.585614 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 20:12:26.592321 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 20:12:26.595609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 20:12:26.599380 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 20:12:26.605819 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 20:12:26.609158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 20:12:26.612800 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 20:12:26.616044 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 20:12:26.622445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 20:12:26.625723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 20:12:26.629439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 20:12:26.635938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 20:12:26.639172 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 20:12:26.642691 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1934 20:12:26.649314 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1935 20:12:26.652562 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1936 20:12:26.656017 Total UI for P1: 0, mck2ui 16
1937 20:12:26.659435 best dqsien dly found for B1: ( 0, 14, 2)
1938 20:12:26.662594 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 20:12:26.665761 Total UI for P1: 0, mck2ui 16
1940 20:12:26.669521 best dqsien dly found for B0: ( 0, 14, 8)
1941 20:12:26.673289 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1942 20:12:26.676361 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1943 20:12:26.676445
1944 20:12:26.679318 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1945 20:12:26.686086 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1946 20:12:26.686171 [Gating] SW calibration Done
1947 20:12:26.686236 ==
1948 20:12:26.689132 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 20:12:26.695877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 20:12:26.695961 ==
1951 20:12:26.696029 RX Vref Scan: 0
1952 20:12:26.696092
1953 20:12:26.699077 RX Vref 0 -> 0, step: 1
1954 20:12:26.699161
1955 20:12:26.702531 RX Delay -130 -> 252, step: 16
1956 20:12:26.705861 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1957 20:12:26.709011 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1958 20:12:26.712444 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1959 20:12:26.719249 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1960 20:12:26.722531 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1961 20:12:26.725836 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1962 20:12:26.728833 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1963 20:12:26.731992 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1964 20:12:26.739003 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1965 20:12:26.742031 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1966 20:12:26.745860 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1967 20:12:26.749028 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1968 20:12:26.752161 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1969 20:12:26.758729 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1970 20:12:26.762252 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1971 20:12:26.765432 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1972 20:12:26.765511 ==
1973 20:12:26.768924 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 20:12:26.772177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 20:12:26.775722 ==
1976 20:12:26.775799 DQS Delay:
1977 20:12:26.775865 DQS0 = 0, DQS1 = 0
1978 20:12:26.778641 DQM Delay:
1979 20:12:26.778717 DQM0 = 91, DQM1 = 85
1980 20:12:26.782024 DQ Delay:
1981 20:12:26.782102 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1982 20:12:26.785371 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1983 20:12:26.788870 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1984 20:12:26.792348 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1985 20:12:26.795398
1986 20:12:26.795470
1987 20:12:26.795531 ==
1988 20:12:26.798978 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 20:12:26.802093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 20:12:26.802165 ==
1991 20:12:26.802227
1992 20:12:26.802285
1993 20:12:26.805771 TX Vref Scan disable
1994 20:12:26.805844 == TX Byte 0 ==
1995 20:12:26.812176 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1996 20:12:26.815847 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1997 20:12:26.815921 == TX Byte 1 ==
1998 20:12:26.822121 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1999 20:12:26.825505 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2000 20:12:26.825581 ==
2001 20:12:26.829013 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 20:12:26.832052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 20:12:26.832125 ==
2004 20:12:26.845600 TX Vref=22, minBit 13, minWin=27, winSum=452
2005 20:12:26.848817 TX Vref=24, minBit 8, minWin=27, winSum=451
2006 20:12:26.851985 TX Vref=26, minBit 13, minWin=27, winSum=455
2007 20:12:26.855506 TX Vref=28, minBit 8, minWin=28, winSum=459
2008 20:12:26.858724 TX Vref=30, minBit 8, minWin=28, winSum=459
2009 20:12:26.865770 TX Vref=32, minBit 8, minWin=28, winSum=459
2010 20:12:26.868863 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
2011 20:12:26.868939
2012 20:12:26.872523 Final TX Range 1 Vref 28
2013 20:12:26.872599
2014 20:12:26.872660 ==
2015 20:12:26.875850 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 20:12:26.879129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 20:12:26.879201 ==
2018 20:12:26.879263
2019 20:12:26.882299
2020 20:12:26.882369 TX Vref Scan disable
2021 20:12:26.885668 == TX Byte 0 ==
2022 20:12:26.888901 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2023 20:12:26.892481 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2024 20:12:26.895590 == TX Byte 1 ==
2025 20:12:26.898929 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2026 20:12:26.902263 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2027 20:12:26.906013
2028 20:12:26.906083 [DATLAT]
2029 20:12:26.906145 Freq=800, CH1 RK1
2030 20:12:26.906208
2031 20:12:26.909192 DATLAT Default: 0xa
2032 20:12:26.909261 0, 0xFFFF, sum = 0
2033 20:12:26.912245 1, 0xFFFF, sum = 0
2034 20:12:26.912317 2, 0xFFFF, sum = 0
2035 20:12:26.915878 3, 0xFFFF, sum = 0
2036 20:12:26.915958 4, 0xFFFF, sum = 0
2037 20:12:26.919266 5, 0xFFFF, sum = 0
2038 20:12:26.919338 6, 0xFFFF, sum = 0
2039 20:12:26.922271 7, 0xFFFF, sum = 0
2040 20:12:26.925833 8, 0xFFFF, sum = 0
2041 20:12:26.925906 9, 0x0, sum = 1
2042 20:12:26.926010 10, 0x0, sum = 2
2043 20:12:26.929059 11, 0x0, sum = 3
2044 20:12:26.929129 12, 0x0, sum = 4
2045 20:12:26.932503 best_step = 10
2046 20:12:26.932573
2047 20:12:26.932633 ==
2048 20:12:26.936207 Dram Type= 6, Freq= 0, CH_1, rank 1
2049 20:12:26.939074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2050 20:12:26.939147 ==
2051 20:12:26.942581 RX Vref Scan: 0
2052 20:12:26.942653
2053 20:12:26.942718 RX Vref 0 -> 0, step: 1
2054 20:12:26.942776
2055 20:12:26.946147 RX Delay -79 -> 252, step: 8
2056 20:12:26.952537 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2057 20:12:26.956204 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2058 20:12:26.959113 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2059 20:12:26.962430 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2060 20:12:26.965863 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2061 20:12:26.969191 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2062 20:12:26.975820 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2063 20:12:26.979216 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2064 20:12:26.982676 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2065 20:12:26.985861 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2066 20:12:26.989106 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2067 20:12:26.996022 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2068 20:12:26.999286 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2069 20:12:27.002801 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2070 20:12:27.006170 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2071 20:12:27.009190 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2072 20:12:27.012731 ==
2073 20:12:27.012803 Dram Type= 6, Freq= 0, CH_1, rank 1
2074 20:12:27.019758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2075 20:12:27.019837 ==
2076 20:12:27.019901 DQS Delay:
2077 20:12:27.022625 DQS0 = 0, DQS1 = 0
2078 20:12:27.022700 DQM Delay:
2079 20:12:27.022761 DQM0 = 92, DQM1 = 85
2080 20:12:27.026187 DQ Delay:
2081 20:12:27.029579 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2082 20:12:27.032523 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2083 20:12:27.036272 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2084 20:12:27.039258 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =96
2085 20:12:27.039330
2086 20:12:27.039393
2087 20:12:27.045764 [DQSOSCAuto] RK1, (LSB)MR18= 0x380d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2088 20:12:27.049272 CH1 RK1: MR19=606, MR18=380D
2089 20:12:27.056299 CH1_RK1: MR19=0x606, MR18=0x380D, DQSOSC=395, MR23=63, INC=94, DEC=63
2090 20:12:27.059370 [RxdqsGatingPostProcess] freq 800
2091 20:12:27.062859 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2092 20:12:27.066032 Pre-setting of DQS Precalculation
2093 20:12:27.072453 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2094 20:12:27.079434 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2095 20:12:27.086112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2096 20:12:27.086191
2097 20:12:27.086255
2098 20:12:27.089209 [Calibration Summary] 1600 Mbps
2099 20:12:27.089284 CH 0, Rank 0
2100 20:12:27.092780 SW Impedance : PASS
2101 20:12:27.095825 DUTY Scan : NO K
2102 20:12:27.095898 ZQ Calibration : PASS
2103 20:12:27.099477 Jitter Meter : NO K
2104 20:12:27.102631 CBT Training : PASS
2105 20:12:27.102707 Write leveling : PASS
2106 20:12:27.105783 RX DQS gating : PASS
2107 20:12:27.109248 RX DQ/DQS(RDDQC) : PASS
2108 20:12:27.109320 TX DQ/DQS : PASS
2109 20:12:27.112652 RX DATLAT : PASS
2110 20:12:27.115676 RX DQ/DQS(Engine): PASS
2111 20:12:27.115748 TX OE : NO K
2112 20:12:27.119421 All Pass.
2113 20:12:27.119492
2114 20:12:27.119552 CH 0, Rank 1
2115 20:12:27.122723 SW Impedance : PASS
2116 20:12:27.122795 DUTY Scan : NO K
2117 20:12:27.125856 ZQ Calibration : PASS
2118 20:12:27.129235 Jitter Meter : NO K
2119 20:12:27.129306 CBT Training : PASS
2120 20:12:27.132914 Write leveling : PASS
2121 20:12:27.132984 RX DQS gating : PASS
2122 20:12:27.136000 RX DQ/DQS(RDDQC) : PASS
2123 20:12:27.139502 TX DQ/DQS : PASS
2124 20:12:27.139576 RX DATLAT : PASS
2125 20:12:27.142510 RX DQ/DQS(Engine): PASS
2126 20:12:27.146371 TX OE : NO K
2127 20:12:27.146445 All Pass.
2128 20:12:27.146507
2129 20:12:27.146569 CH 1, Rank 0
2130 20:12:27.149316 SW Impedance : PASS
2131 20:12:27.152506 DUTY Scan : NO K
2132 20:12:27.152581 ZQ Calibration : PASS
2133 20:12:27.156021 Jitter Meter : NO K
2134 20:12:27.159357 CBT Training : PASS
2135 20:12:27.159429 Write leveling : PASS
2136 20:12:27.162623 RX DQS gating : PASS
2137 20:12:27.166065 RX DQ/DQS(RDDQC) : PASS
2138 20:12:27.166154 TX DQ/DQS : PASS
2139 20:12:27.169310 RX DATLAT : PASS
2140 20:12:27.169381 RX DQ/DQS(Engine): PASS
2141 20:12:27.172563 TX OE : NO K
2142 20:12:27.172636 All Pass.
2143 20:12:27.172696
2144 20:12:27.176095 CH 1, Rank 1
2145 20:12:27.176167 SW Impedance : PASS
2146 20:12:27.179706 DUTY Scan : NO K
2147 20:12:27.182664 ZQ Calibration : PASS
2148 20:12:27.182736 Jitter Meter : NO K
2149 20:12:27.186250 CBT Training : PASS
2150 20:12:27.189431 Write leveling : PASS
2151 20:12:27.189501 RX DQS gating : PASS
2152 20:12:27.192907 RX DQ/DQS(RDDQC) : PASS
2153 20:12:27.196272 TX DQ/DQS : PASS
2154 20:12:27.196348 RX DATLAT : PASS
2155 20:12:27.199377 RX DQ/DQS(Engine): PASS
2156 20:12:27.202730 TX OE : NO K
2157 20:12:27.202805 All Pass.
2158 20:12:27.202866
2159 20:12:27.202922 DramC Write-DBI off
2160 20:12:27.205982 PER_BANK_REFRESH: Hybrid Mode
2161 20:12:27.209197 TX_TRACKING: ON
2162 20:12:27.212834 [GetDramInforAfterCalByMRR] Vendor 6.
2163 20:12:27.216568 [GetDramInforAfterCalByMRR] Revision 606.
2164 20:12:27.219556 [GetDramInforAfterCalByMRR] Revision 2 0.
2165 20:12:27.219630 MR0 0x3b3b
2166 20:12:27.222674 MR8 0x5151
2167 20:12:27.226044 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 20:12:27.226119
2169 20:12:27.226181 MR0 0x3b3b
2170 20:12:27.226240 MR8 0x5151
2171 20:12:27.229303 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 20:12:27.229373
2173 20:12:27.239751 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2174 20:12:27.242798 [FAST_K] Save calibration result to emmc
2175 20:12:27.246421 [FAST_K] Save calibration result to emmc
2176 20:12:27.249775 dram_init: config_dvfs: 1
2177 20:12:27.252655 dramc_set_vcore_voltage set vcore to 662500
2178 20:12:27.256170 Read voltage for 1200, 2
2179 20:12:27.256243 Vio18 = 0
2180 20:12:27.256309 Vcore = 662500
2181 20:12:27.259563 Vdram = 0
2182 20:12:27.259634 Vddq = 0
2183 20:12:27.259693 Vmddr = 0
2184 20:12:27.266267 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2185 20:12:27.269576 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2186 20:12:27.272883 MEM_TYPE=3, freq_sel=15
2187 20:12:27.276129 sv_algorithm_assistance_LP4_1600
2188 20:12:27.279434 ============ PULL DRAM RESETB DOWN ============
2189 20:12:27.282991 ========== PULL DRAM RESETB DOWN end =========
2190 20:12:27.289623 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2191 20:12:27.293054 ===================================
2192 20:12:27.296302 LPDDR4 DRAM CONFIGURATION
2193 20:12:27.299424 ===================================
2194 20:12:27.299537 EX_ROW_EN[0] = 0x0
2195 20:12:27.303048 EX_ROW_EN[1] = 0x0
2196 20:12:27.303163 LP4Y_EN = 0x0
2197 20:12:27.306500 WORK_FSP = 0x0
2198 20:12:27.306587 WL = 0x4
2199 20:12:27.309617 RL = 0x4
2200 20:12:27.309700 BL = 0x2
2201 20:12:27.312918 RPST = 0x0
2202 20:12:27.313022 RD_PRE = 0x0
2203 20:12:27.316731 WR_PRE = 0x1
2204 20:12:27.316825 WR_PST = 0x0
2205 20:12:27.319989 DBI_WR = 0x0
2206 20:12:27.320084 DBI_RD = 0x0
2207 20:12:27.323307 OTF = 0x1
2208 20:12:27.326310 ===================================
2209 20:12:27.329723 ===================================
2210 20:12:27.329836 ANA top config
2211 20:12:27.333628 ===================================
2212 20:12:27.336546 DLL_ASYNC_EN = 0
2213 20:12:27.340112 ALL_SLAVE_EN = 0
2214 20:12:27.343246 NEW_RANK_MODE = 1
2215 20:12:27.343331 DLL_IDLE_MODE = 1
2216 20:12:27.346665 LP45_APHY_COMB_EN = 1
2217 20:12:27.350321 TX_ODT_DIS = 1
2218 20:12:27.353556 NEW_8X_MODE = 1
2219 20:12:27.356539 ===================================
2220 20:12:27.359935 ===================================
2221 20:12:27.363163 data_rate = 2400
2222 20:12:27.363246 CKR = 1
2223 20:12:27.366734 DQ_P2S_RATIO = 8
2224 20:12:27.369696 ===================================
2225 20:12:27.373318 CA_P2S_RATIO = 8
2226 20:12:27.376568 DQ_CA_OPEN = 0
2227 20:12:27.380147 DQ_SEMI_OPEN = 0
2228 20:12:27.380230 CA_SEMI_OPEN = 0
2229 20:12:27.383377 CA_FULL_RATE = 0
2230 20:12:27.386604 DQ_CKDIV4_EN = 0
2231 20:12:27.389914 CA_CKDIV4_EN = 0
2232 20:12:27.393066 CA_PREDIV_EN = 0
2233 20:12:27.397036 PH8_DLY = 17
2234 20:12:27.397120 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2235 20:12:27.400173 DQ_AAMCK_DIV = 4
2236 20:12:27.403373 CA_AAMCK_DIV = 4
2237 20:12:27.406757 CA_ADMCK_DIV = 4
2238 20:12:27.410348 DQ_TRACK_CA_EN = 0
2239 20:12:27.413478 CA_PICK = 1200
2240 20:12:27.416567 CA_MCKIO = 1200
2241 20:12:27.416658 MCKIO_SEMI = 0
2242 20:12:27.420006 PLL_FREQ = 2366
2243 20:12:27.423394 DQ_UI_PI_RATIO = 32
2244 20:12:27.426664 CA_UI_PI_RATIO = 0
2245 20:12:27.429845 ===================================
2246 20:12:27.433469 ===================================
2247 20:12:27.437215 memory_type:LPDDR4
2248 20:12:27.437327 GP_NUM : 10
2249 20:12:27.439818 SRAM_EN : 1
2250 20:12:27.439933 MD32_EN : 0
2251 20:12:27.443117 ===================================
2252 20:12:27.446628 [ANA_INIT] >>>>>>>>>>>>>>
2253 20:12:27.450035 <<<<<< [CONFIGURE PHASE]: ANA_TX
2254 20:12:27.453304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2255 20:12:27.456605 ===================================
2256 20:12:27.460281 data_rate = 2400,PCW = 0X5b00
2257 20:12:27.463352 ===================================
2258 20:12:27.466760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2259 20:12:27.470103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 20:12:27.476450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 20:12:27.483629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2262 20:12:27.486758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2263 20:12:27.490281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2264 20:12:27.490386 [ANA_INIT] flow start
2265 20:12:27.493703 [ANA_INIT] PLL >>>>>>>>
2266 20:12:27.497001 [ANA_INIT] PLL <<<<<<<<
2267 20:12:27.497104 [ANA_INIT] MIDPI >>>>>>>>
2268 20:12:27.500186 [ANA_INIT] MIDPI <<<<<<<<
2269 20:12:27.503378 [ANA_INIT] DLL >>>>>>>>
2270 20:12:27.503480 [ANA_INIT] DLL <<<<<<<<
2271 20:12:27.506945 [ANA_INIT] flow end
2272 20:12:27.510682 ============ LP4 DIFF to SE enter ============
2273 20:12:27.513370 ============ LP4 DIFF to SE exit ============
2274 20:12:27.517039 [ANA_INIT] <<<<<<<<<<<<<
2275 20:12:27.520385 [Flow] Enable top DCM control >>>>>
2276 20:12:27.523399 [Flow] Enable top DCM control <<<<<
2277 20:12:27.526738 Enable DLL master slave shuffle
2278 20:12:27.533602 ==============================================================
2279 20:12:27.533703 Gating Mode config
2280 20:12:27.540015 ==============================================================
2281 20:12:27.540131 Config description:
2282 20:12:27.550102 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2283 20:12:27.557117 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2284 20:12:27.563684 SELPH_MODE 0: By rank 1: By Phase
2285 20:12:27.566788 ==============================================================
2286 20:12:27.570051 GAT_TRACK_EN = 1
2287 20:12:27.573515 RX_GATING_MODE = 2
2288 20:12:27.576849 RX_GATING_TRACK_MODE = 2
2289 20:12:27.580373 SELPH_MODE = 1
2290 20:12:27.583593 PICG_EARLY_EN = 1
2291 20:12:27.587057 VALID_LAT_VALUE = 1
2292 20:12:27.590424 ==============================================================
2293 20:12:27.593696 Enter into Gating configuration >>>>
2294 20:12:27.596959 Exit from Gating configuration <<<<
2295 20:12:27.600457 Enter into DVFS_PRE_config >>>>>
2296 20:12:27.613503 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2297 20:12:27.616943 Exit from DVFS_PRE_config <<<<<
2298 20:12:27.617026 Enter into PICG configuration >>>>
2299 20:12:27.620267 Exit from PICG configuration <<<<
2300 20:12:27.623866 [RX_INPUT] configuration >>>>>
2301 20:12:27.627010 [RX_INPUT] configuration <<<<<
2302 20:12:27.633648 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2303 20:12:27.637320 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2304 20:12:27.643834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 20:12:27.650344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 20:12:27.656980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 20:12:27.663649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 20:12:27.667377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2309 20:12:27.670308 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2310 20:12:27.673641 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2311 20:12:27.680798 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2312 20:12:27.683755 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2313 20:12:27.687193 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2314 20:12:27.690594 ===================================
2315 20:12:27.693709 LPDDR4 DRAM CONFIGURATION
2316 20:12:27.697321 ===================================
2317 20:12:27.697405 EX_ROW_EN[0] = 0x0
2318 20:12:27.700691 EX_ROW_EN[1] = 0x0
2319 20:12:27.703487 LP4Y_EN = 0x0
2320 20:12:27.703557 WORK_FSP = 0x0
2321 20:12:27.706805 WL = 0x4
2322 20:12:27.706876 RL = 0x4
2323 20:12:27.710371 BL = 0x2
2324 20:12:27.710440 RPST = 0x0
2325 20:12:27.713626 RD_PRE = 0x0
2326 20:12:27.713726 WR_PRE = 0x1
2327 20:12:27.716852 WR_PST = 0x0
2328 20:12:27.716923 DBI_WR = 0x0
2329 20:12:27.720711 DBI_RD = 0x0
2330 20:12:27.720794 OTF = 0x1
2331 20:12:27.723508 ===================================
2332 20:12:27.726989 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2333 20:12:27.734012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2334 20:12:27.737264 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2335 20:12:27.740467 ===================================
2336 20:12:27.743730 LPDDR4 DRAM CONFIGURATION
2337 20:12:27.747142 ===================================
2338 20:12:27.747217 EX_ROW_EN[0] = 0x10
2339 20:12:27.750525 EX_ROW_EN[1] = 0x0
2340 20:12:27.750593 LP4Y_EN = 0x0
2341 20:12:27.754001 WORK_FSP = 0x0
2342 20:12:27.754071 WL = 0x4
2343 20:12:27.757373 RL = 0x4
2344 20:12:27.757445 BL = 0x2
2345 20:12:27.760455 RPST = 0x0
2346 20:12:27.760523 RD_PRE = 0x0
2347 20:12:27.763888 WR_PRE = 0x1
2348 20:12:27.763963 WR_PST = 0x0
2349 20:12:27.767639 DBI_WR = 0x0
2350 20:12:27.767715 DBI_RD = 0x0
2351 20:12:27.770708 OTF = 0x1
2352 20:12:27.774107 ===================================
2353 20:12:27.780316 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2354 20:12:27.780395 ==
2355 20:12:27.783713 Dram Type= 6, Freq= 0, CH_0, rank 0
2356 20:12:27.787215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 20:12:27.787288 ==
2358 20:12:27.790468 [Duty_Offset_Calibration]
2359 20:12:27.790536 B0:2 B1:0 CA:1
2360 20:12:27.790599
2361 20:12:27.793855 [DutyScan_Calibration_Flow] k_type=0
2362 20:12:27.803770
2363 20:12:27.803877 ==CLK 0==
2364 20:12:27.807563 Final CLK duty delay cell = -4
2365 20:12:27.810637 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2366 20:12:27.813710 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2367 20:12:27.817694 [-4] AVG Duty = 4953%(X100)
2368 20:12:27.817775
2369 20:12:27.820362 CH0 CLK Duty spec in!! Max-Min= 156%
2370 20:12:27.823829 [DutyScan_Calibration_Flow] ====Done====
2371 20:12:27.823942
2372 20:12:27.827299 [DutyScan_Calibration_Flow] k_type=1
2373 20:12:27.842504
2374 20:12:27.842627 ==DQS 0 ==
2375 20:12:27.846068 Final DQS duty delay cell = 0
2376 20:12:27.849176 [0] MAX Duty = 5187%(X100), DQS PI = 30
2377 20:12:27.852446 [0] MIN Duty = 4938%(X100), DQS PI = 2
2378 20:12:27.852528 [0] AVG Duty = 5062%(X100)
2379 20:12:27.856107
2380 20:12:27.856187 ==DQS 1 ==
2381 20:12:27.859490 Final DQS duty delay cell = -4
2382 20:12:27.862523 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2383 20:12:27.865841 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2384 20:12:27.869376 [-4] AVG Duty = 5015%(X100)
2385 20:12:27.869484
2386 20:12:27.872600 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2387 20:12:27.872707
2388 20:12:27.876015 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2389 20:12:27.879187 [DutyScan_Calibration_Flow] ====Done====
2390 20:12:27.879294
2391 20:12:27.882554 [DutyScan_Calibration_Flow] k_type=3
2392 20:12:27.899408
2393 20:12:27.899488 ==DQM 0 ==
2394 20:12:27.903189 Final DQM duty delay cell = 0
2395 20:12:27.905930 [0] MAX Duty = 5062%(X100), DQS PI = 24
2396 20:12:27.909373 [0] MIN Duty = 4844%(X100), DQS PI = 0
2397 20:12:27.909455 [0] AVG Duty = 4953%(X100)
2398 20:12:27.912903
2399 20:12:27.913012 ==DQM 1 ==
2400 20:12:27.916307 Final DQM duty delay cell = 0
2401 20:12:27.919394 [0] MAX Duty = 5218%(X100), DQS PI = 48
2402 20:12:27.922665 [0] MIN Duty = 5000%(X100), DQS PI = 12
2403 20:12:27.922743 [0] AVG Duty = 5109%(X100)
2404 20:12:27.922815
2405 20:12:27.929745 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2406 20:12:27.929854
2407 20:12:27.932708 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2408 20:12:27.936323 [DutyScan_Calibration_Flow] ====Done====
2409 20:12:27.936399
2410 20:12:27.939514 [DutyScan_Calibration_Flow] k_type=2
2411 20:12:27.955732
2412 20:12:27.955859 ==DQ 0 ==
2413 20:12:27.959182 Final DQ duty delay cell = -4
2414 20:12:27.962341 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2415 20:12:27.965707 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2416 20:12:27.969189 [-4] AVG Duty = 4984%(X100)
2417 20:12:27.969279
2418 20:12:27.969345 ==DQ 1 ==
2419 20:12:27.972894 Final DQ duty delay cell = 4
2420 20:12:27.975704 [4] MAX Duty = 5093%(X100), DQS PI = 6
2421 20:12:27.979427 [4] MIN Duty = 5031%(X100), DQS PI = 0
2422 20:12:27.979510 [4] AVG Duty = 5062%(X100)
2423 20:12:27.979604
2424 20:12:27.982241 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2425 20:12:27.985797
2426 20:12:27.989523 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2427 20:12:27.992559 [DutyScan_Calibration_Flow] ====Done====
2428 20:12:27.992642 ==
2429 20:12:27.995847 Dram Type= 6, Freq= 0, CH_1, rank 0
2430 20:12:27.999095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2431 20:12:27.999198 ==
2432 20:12:28.002960 [Duty_Offset_Calibration]
2433 20:12:28.003052 B0:0 B1:-1 CA:2
2434 20:12:28.003148
2435 20:12:28.005601 [DutyScan_Calibration_Flow] k_type=0
2436 20:12:28.016343
2437 20:12:28.016458 ==CLK 0==
2438 20:12:28.019278 Final CLK duty delay cell = 0
2439 20:12:28.022435 [0] MAX Duty = 5156%(X100), DQS PI = 14
2440 20:12:28.026204 [0] MIN Duty = 4938%(X100), DQS PI = 44
2441 20:12:28.026294 [0] AVG Duty = 5047%(X100)
2442 20:12:28.029288
2443 20:12:28.029389 CH1 CLK Duty spec in!! Max-Min= 218%
2444 20:12:28.036007 [DutyScan_Calibration_Flow] ====Done====
2445 20:12:28.036121
2446 20:12:28.039020 [DutyScan_Calibration_Flow] k_type=1
2447 20:12:28.055302
2448 20:12:28.055386 ==DQS 0 ==
2449 20:12:28.058753 Final DQS duty delay cell = 0
2450 20:12:28.062166 [0] MAX Duty = 5093%(X100), DQS PI = 24
2451 20:12:28.065570 [0] MIN Duty = 4969%(X100), DQS PI = 0
2452 20:12:28.065679 [0] AVG Duty = 5031%(X100)
2453 20:12:28.069330
2454 20:12:28.069413 ==DQS 1 ==
2455 20:12:28.071930 Final DQS duty delay cell = 0
2456 20:12:28.075605 [0] MAX Duty = 5156%(X100), DQS PI = 0
2457 20:12:28.078846 [0] MIN Duty = 4813%(X100), DQS PI = 36
2458 20:12:28.078948 [0] AVG Duty = 4984%(X100)
2459 20:12:28.079040
2460 20:12:28.085455 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2461 20:12:28.085557
2462 20:12:28.088902 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2463 20:12:28.091981 [DutyScan_Calibration_Flow] ====Done====
2464 20:12:28.092056
2465 20:12:28.095833 [DutyScan_Calibration_Flow] k_type=3
2466 20:12:28.113036
2467 20:12:28.113157 ==DQM 0 ==
2468 20:12:28.115503 Final DQM duty delay cell = 4
2469 20:12:28.118874 [4] MAX Duty = 5093%(X100), DQS PI = 6
2470 20:12:28.122581 [4] MIN Duty = 4938%(X100), DQS PI = 44
2471 20:12:28.125813 [4] AVG Duty = 5015%(X100)
2472 20:12:28.125888
2473 20:12:28.125976 ==DQM 1 ==
2474 20:12:28.129232 Final DQM duty delay cell = 0
2475 20:12:28.132833 [0] MAX Duty = 5280%(X100), DQS PI = 60
2476 20:12:28.136032 [0] MIN Duty = 4875%(X100), DQS PI = 36
2477 20:12:28.139575 [0] AVG Duty = 5077%(X100)
2478 20:12:28.139658
2479 20:12:28.142365 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2480 20:12:28.142449
2481 20:12:28.145857 CH1 DQM 1 Duty spec in!! Max-Min= 405%
2482 20:12:28.149100 [DutyScan_Calibration_Flow] ====Done====
2483 20:12:28.149183
2484 20:12:28.152848 [DutyScan_Calibration_Flow] k_type=2
2485 20:12:28.168965
2486 20:12:28.169076 ==DQ 0 ==
2487 20:12:28.172674 Final DQ duty delay cell = 0
2488 20:12:28.175872 [0] MAX Duty = 5062%(X100), DQS PI = 20
2489 20:12:28.179513 [0] MIN Duty = 4938%(X100), DQS PI = 46
2490 20:12:28.179597 [0] AVG Duty = 5000%(X100)
2491 20:12:28.179664
2492 20:12:28.182547 ==DQ 1 ==
2493 20:12:28.185847 Final DQ duty delay cell = 0
2494 20:12:28.189248 [0] MAX Duty = 5031%(X100), DQS PI = 2
2495 20:12:28.192709 [0] MIN Duty = 4813%(X100), DQS PI = 34
2496 20:12:28.192793 [0] AVG Duty = 4922%(X100)
2497 20:12:28.192860
2498 20:12:28.195898 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2499 20:12:28.195983
2500 20:12:28.199699 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2501 20:12:28.205919 [DutyScan_Calibration_Flow] ====Done====
2502 20:12:28.209494 nWR fixed to 30
2503 20:12:28.209579 [ModeRegInit_LP4] CH0 RK0
2504 20:12:28.212647 [ModeRegInit_LP4] CH0 RK1
2505 20:12:28.215910 [ModeRegInit_LP4] CH1 RK0
2506 20:12:28.215993 [ModeRegInit_LP4] CH1 RK1
2507 20:12:28.219287 match AC timing 7
2508 20:12:28.222521 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2509 20:12:28.226006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2510 20:12:28.233315 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2511 20:12:28.236203 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2512 20:12:28.243111 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2513 20:12:28.243207 ==
2514 20:12:28.246206 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 20:12:28.249545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 20:12:28.249633 ==
2517 20:12:28.256252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2518 20:12:28.259289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2519 20:12:28.269013 [CA 0] Center 38 (8~69) winsize 62
2520 20:12:28.272553 [CA 1] Center 38 (7~69) winsize 63
2521 20:12:28.275729 [CA 2] Center 35 (5~66) winsize 62
2522 20:12:28.278826 [CA 3] Center 35 (4~66) winsize 63
2523 20:12:28.282555 [CA 4] Center 34 (4~65) winsize 62
2524 20:12:28.285724 [CA 5] Center 33 (3~63) winsize 61
2525 20:12:28.285801
2526 20:12:28.289018 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2527 20:12:28.289100
2528 20:12:28.292195 [CATrainingPosCal] consider 1 rank data
2529 20:12:28.295873 u2DelayCellTimex100 = 270/100 ps
2530 20:12:28.299166 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2531 20:12:28.302797 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2532 20:12:28.308964 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2533 20:12:28.312229 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2534 20:12:28.315842 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2535 20:12:28.318794 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2536 20:12:28.318877
2537 20:12:28.322462 CA PerBit enable=1, Macro0, CA PI delay=33
2538 20:12:28.322545
2539 20:12:28.325799 [CBTSetCACLKResult] CA Dly = 33
2540 20:12:28.325881 CS Dly: 6 (0~37)
2541 20:12:28.325992 ==
2542 20:12:28.329240 Dram Type= 6, Freq= 0, CH_0, rank 1
2543 20:12:28.335505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2544 20:12:28.335595 ==
2545 20:12:28.338930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2546 20:12:28.345629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2547 20:12:28.354661 [CA 0] Center 39 (8~70) winsize 63
2548 20:12:28.358180 [CA 1] Center 38 (8~69) winsize 62
2549 20:12:28.361132 [CA 2] Center 35 (5~66) winsize 62
2550 20:12:28.364562 [CA 3] Center 35 (5~66) winsize 62
2551 20:12:28.368136 [CA 4] Center 34 (4~65) winsize 62
2552 20:12:28.371710 [CA 5] Center 34 (4~64) winsize 61
2553 20:12:28.371793
2554 20:12:28.374917 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2555 20:12:28.375001
2556 20:12:28.378227 [CATrainingPosCal] consider 2 rank data
2557 20:12:28.381585 u2DelayCellTimex100 = 270/100 ps
2558 20:12:28.384685 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2559 20:12:28.388357 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2560 20:12:28.395016 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2561 20:12:28.398295 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 20:12:28.401486 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2563 20:12:28.404581 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2564 20:12:28.404665
2565 20:12:28.408198 CA PerBit enable=1, Macro0, CA PI delay=33
2566 20:12:28.408281
2567 20:12:28.411473 [CBTSetCACLKResult] CA Dly = 33
2568 20:12:28.411556 CS Dly: 7 (0~39)
2569 20:12:28.411622
2570 20:12:28.414840 ----->DramcWriteLeveling(PI) begin...
2571 20:12:28.414924 ==
2572 20:12:28.418194 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 20:12:28.424915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 20:12:28.424999 ==
2575 20:12:28.427911 Write leveling (Byte 0): 36 => 36
2576 20:12:28.431641 Write leveling (Byte 1): 31 => 31
2577 20:12:28.431724 DramcWriteLeveling(PI) end<-----
2578 20:12:28.434920
2579 20:12:28.435003 ==
2580 20:12:28.438300 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 20:12:28.441471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 20:12:28.441556 ==
2583 20:12:28.444683 [Gating] SW mode calibration
2584 20:12:28.451875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2585 20:12:28.455114 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2586 20:12:28.461628 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2587 20:12:28.464937 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2588 20:12:28.468516 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 20:12:28.475119 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 20:12:28.478218 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 20:12:28.481623 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 20:12:28.488127 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2593 20:12:28.491913 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2594 20:12:28.495064 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
2595 20:12:28.501563 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 20:12:28.505403 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 20:12:28.508287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 20:12:28.511880 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 20:12:28.518475 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 20:12:28.521596 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2601 20:12:28.524994 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2602 20:12:28.531720 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2603 20:12:28.535018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 20:12:28.538564 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 20:12:28.545101 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 20:12:28.548316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 20:12:28.551987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 20:12:28.558248 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 20:12:28.561791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2610 20:12:28.565353 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2611 20:12:28.572108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 20:12:28.575306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 20:12:28.578544 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 20:12:28.584999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 20:12:28.588837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 20:12:28.591807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 20:12:28.598375 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 20:12:28.601691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 20:12:28.605340 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 20:12:28.608525 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 20:12:28.614784 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 20:12:28.618135 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 20:12:28.621750 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 20:12:28.628341 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2625 20:12:28.631908 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2626 20:12:28.635397 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2627 20:12:28.638144 Total UI for P1: 0, mck2ui 16
2628 20:12:28.641661 best dqsien dly found for B0: ( 1, 3, 26)
2629 20:12:28.648310 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 20:12:28.651684 Total UI for P1: 0, mck2ui 16
2631 20:12:28.655343 best dqsien dly found for B1: ( 1, 4, 0)
2632 20:12:28.658127 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2633 20:12:28.661401 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2634 20:12:28.661485
2635 20:12:28.664929 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2636 20:12:28.668210 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2637 20:12:28.671581 [Gating] SW calibration Done
2638 20:12:28.671665 ==
2639 20:12:28.674913 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 20:12:28.678143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 20:12:28.678229 ==
2642 20:12:28.681630 RX Vref Scan: 0
2643 20:12:28.681713
2644 20:12:28.681779 RX Vref 0 -> 0, step: 1
2645 20:12:28.681841
2646 20:12:28.685088 RX Delay -40 -> 252, step: 8
2647 20:12:28.688594 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2648 20:12:28.695020 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2649 20:12:28.698292 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2650 20:12:28.701841 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2651 20:12:28.704918 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2652 20:12:28.708379 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2653 20:12:28.715172 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2654 20:12:28.718422 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2655 20:12:28.721892 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2656 20:12:28.725664 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2657 20:12:28.728587 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2658 20:12:28.731702 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2659 20:12:28.738395 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2660 20:12:28.742252 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2661 20:12:28.745140 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2662 20:12:28.748420 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2663 20:12:28.748504 ==
2664 20:12:28.752045 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 20:12:28.758505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 20:12:28.758610 ==
2667 20:12:28.758713 DQS Delay:
2668 20:12:28.758779 DQS0 = 0, DQS1 = 0
2669 20:12:28.761991 DQM Delay:
2670 20:12:28.762075 DQM0 = 123, DQM1 = 110
2671 20:12:28.765459 DQ Delay:
2672 20:12:28.768605 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2673 20:12:28.771872 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2674 20:12:28.775302 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2675 20:12:28.778741 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2676 20:12:28.778825
2677 20:12:28.778891
2678 20:12:28.778950 ==
2679 20:12:28.781854 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 20:12:28.785369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 20:12:28.785469 ==
2682 20:12:28.785567
2683 20:12:28.788453
2684 20:12:28.788553 TX Vref Scan disable
2685 20:12:28.792222 == TX Byte 0 ==
2686 20:12:28.795401 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2687 20:12:28.798701 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2688 20:12:28.802617 == TX Byte 1 ==
2689 20:12:28.805721 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2690 20:12:28.808548 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2691 20:12:28.808647 ==
2692 20:12:28.812222 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 20:12:28.818786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 20:12:28.818872 ==
2695 20:12:28.829460 TX Vref=22, minBit 7, minWin=23, winSum=412
2696 20:12:28.832813 TX Vref=24, minBit 0, minWin=25, winSum=417
2697 20:12:28.836013 TX Vref=26, minBit 0, minWin=26, winSum=427
2698 20:12:28.839489 TX Vref=28, minBit 0, minWin=25, winSum=427
2699 20:12:28.842456 TX Vref=30, minBit 4, minWin=26, winSum=430
2700 20:12:28.849563 TX Vref=32, minBit 3, minWin=26, winSum=427
2701 20:12:28.852439 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 30
2702 20:12:28.852543
2703 20:12:28.855876 Final TX Range 1 Vref 30
2704 20:12:28.855965
2705 20:12:28.856038 ==
2706 20:12:28.858933 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 20:12:28.862560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 20:12:28.862649 ==
2709 20:12:28.865818
2710 20:12:28.865931
2711 20:12:28.866048 TX Vref Scan disable
2712 20:12:28.869154 == TX Byte 0 ==
2713 20:12:28.872606 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2714 20:12:28.879116 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2715 20:12:28.879200 == TX Byte 1 ==
2716 20:12:28.882292 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2717 20:12:28.888985 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2718 20:12:28.889068
2719 20:12:28.889134 [DATLAT]
2720 20:12:28.889195 Freq=1200, CH0 RK0
2721 20:12:28.889255
2722 20:12:28.892071 DATLAT Default: 0xd
2723 20:12:28.892297 0, 0xFFFF, sum = 0
2724 20:12:28.895836 1, 0xFFFF, sum = 0
2725 20:12:28.899101 2, 0xFFFF, sum = 0
2726 20:12:28.899213 3, 0xFFFF, sum = 0
2727 20:12:28.902246 4, 0xFFFF, sum = 0
2728 20:12:28.902320 5, 0xFFFF, sum = 0
2729 20:12:28.905570 6, 0xFFFF, sum = 0
2730 20:12:28.905657 7, 0xFFFF, sum = 0
2731 20:12:28.908970 8, 0xFFFF, sum = 0
2732 20:12:28.909056 9, 0xFFFF, sum = 0
2733 20:12:28.912333 10, 0xFFFF, sum = 0
2734 20:12:28.912418 11, 0xFFFF, sum = 0
2735 20:12:28.915566 12, 0x0, sum = 1
2736 20:12:28.915650 13, 0x0, sum = 2
2737 20:12:28.918730 14, 0x0, sum = 3
2738 20:12:28.918822 15, 0x0, sum = 4
2739 20:12:28.922160 best_step = 13
2740 20:12:28.922244
2741 20:12:28.922310 ==
2742 20:12:28.925688 Dram Type= 6, Freq= 0, CH_0, rank 0
2743 20:12:28.929209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2744 20:12:28.929293 ==
2745 20:12:28.929359 RX Vref Scan: 1
2746 20:12:28.929420
2747 20:12:28.932398 Set Vref Range= 32 -> 127
2748 20:12:28.932481
2749 20:12:28.935943 RX Vref 32 -> 127, step: 1
2750 20:12:28.936044
2751 20:12:28.938889 RX Delay -13 -> 252, step: 4
2752 20:12:28.939018
2753 20:12:28.942233 Set Vref, RX VrefLevel [Byte0]: 32
2754 20:12:28.945834 [Byte1]: 32
2755 20:12:28.945934
2756 20:12:28.948681 Set Vref, RX VrefLevel [Byte0]: 33
2757 20:12:28.952060 [Byte1]: 33
2758 20:12:28.955663
2759 20:12:28.955746 Set Vref, RX VrefLevel [Byte0]: 34
2760 20:12:28.958644 [Byte1]: 34
2761 20:12:28.963235
2762 20:12:28.963309 Set Vref, RX VrefLevel [Byte0]: 35
2763 20:12:28.966903 [Byte1]: 35
2764 20:12:28.971612
2765 20:12:28.971703 Set Vref, RX VrefLevel [Byte0]: 36
2766 20:12:28.974667 [Byte1]: 36
2767 20:12:28.979172
2768 20:12:28.979256 Set Vref, RX VrefLevel [Byte0]: 37
2769 20:12:28.982822 [Byte1]: 37
2770 20:12:28.986907
2771 20:12:28.987027 Set Vref, RX VrefLevel [Byte0]: 38
2772 20:12:28.990449 [Byte1]: 38
2773 20:12:28.995302
2774 20:12:28.995389 Set Vref, RX VrefLevel [Byte0]: 39
2775 20:12:28.998186 [Byte1]: 39
2776 20:12:29.002801
2777 20:12:29.002885 Set Vref, RX VrefLevel [Byte0]: 40
2778 20:12:29.006322 [Byte1]: 40
2779 20:12:29.010604
2780 20:12:29.010689 Set Vref, RX VrefLevel [Byte0]: 41
2781 20:12:29.013930 [Byte1]: 41
2782 20:12:29.018685
2783 20:12:29.018768 Set Vref, RX VrefLevel [Byte0]: 42
2784 20:12:29.021817 [Byte1]: 42
2785 20:12:29.026229
2786 20:12:29.026314 Set Vref, RX VrefLevel [Byte0]: 43
2787 20:12:29.029680 [Byte1]: 43
2788 20:12:29.034289
2789 20:12:29.034374 Set Vref, RX VrefLevel [Byte0]: 44
2790 20:12:29.037540 [Byte1]: 44
2791 20:12:29.042110
2792 20:12:29.042190 Set Vref, RX VrefLevel [Byte0]: 45
2793 20:12:29.045797 [Byte1]: 45
2794 20:12:29.050241
2795 20:12:29.050323 Set Vref, RX VrefLevel [Byte0]: 46
2796 20:12:29.053776 [Byte1]: 46
2797 20:12:29.058109
2798 20:12:29.058185 Set Vref, RX VrefLevel [Byte0]: 47
2799 20:12:29.061464 [Byte1]: 47
2800 20:12:29.066165
2801 20:12:29.066276 Set Vref, RX VrefLevel [Byte0]: 48
2802 20:12:29.069370 [Byte1]: 48
2803 20:12:29.073619
2804 20:12:29.073723 Set Vref, RX VrefLevel [Byte0]: 49
2805 20:12:29.077238 [Byte1]: 49
2806 20:12:29.082008
2807 20:12:29.082095 Set Vref, RX VrefLevel [Byte0]: 50
2808 20:12:29.085133 [Byte1]: 50
2809 20:12:29.089652
2810 20:12:29.089738 Set Vref, RX VrefLevel [Byte0]: 51
2811 20:12:29.093027 [Byte1]: 51
2812 20:12:29.097386
2813 20:12:29.097472 Set Vref, RX VrefLevel [Byte0]: 52
2814 20:12:29.100897 [Byte1]: 52
2815 20:12:29.105626
2816 20:12:29.105712 Set Vref, RX VrefLevel [Byte0]: 53
2817 20:12:29.108474 [Byte1]: 53
2818 20:12:29.113362
2819 20:12:29.113447 Set Vref, RX VrefLevel [Byte0]: 54
2820 20:12:29.116928 [Byte1]: 54
2821 20:12:29.121315
2822 20:12:29.121398 Set Vref, RX VrefLevel [Byte0]: 55
2823 20:12:29.124334 [Byte1]: 55
2824 20:12:29.128964
2825 20:12:29.129048 Set Vref, RX VrefLevel [Byte0]: 56
2826 20:12:29.132544 [Byte1]: 56
2827 20:12:29.137200
2828 20:12:29.137319 Set Vref, RX VrefLevel [Byte0]: 57
2829 20:12:29.140061 [Byte1]: 57
2830 20:12:29.144796
2831 20:12:29.144906 Set Vref, RX VrefLevel [Byte0]: 58
2832 20:12:29.148263 [Byte1]: 58
2833 20:12:29.152529
2834 20:12:29.152603 Set Vref, RX VrefLevel [Byte0]: 59
2835 20:12:29.155955 [Byte1]: 59
2836 20:12:29.160828
2837 20:12:29.160925 Set Vref, RX VrefLevel [Byte0]: 60
2838 20:12:29.164005 [Byte1]: 60
2839 20:12:29.168521
2840 20:12:29.168624 Set Vref, RX VrefLevel [Byte0]: 61
2841 20:12:29.171641 [Byte1]: 61
2842 20:12:29.176242
2843 20:12:29.176322 Set Vref, RX VrefLevel [Byte0]: 62
2844 20:12:29.179834 [Byte1]: 62
2845 20:12:29.184238
2846 20:12:29.184308 Set Vref, RX VrefLevel [Byte0]: 63
2847 20:12:29.187485 [Byte1]: 63
2848 20:12:29.192431
2849 20:12:29.192506 Set Vref, RX VrefLevel [Byte0]: 64
2850 20:12:29.195268 [Byte1]: 64
2851 20:12:29.199945
2852 20:12:29.200026 Set Vref, RX VrefLevel [Byte0]: 65
2853 20:12:29.203463 [Byte1]: 65
2854 20:12:29.207727
2855 20:12:29.207807 Set Vref, RX VrefLevel [Byte0]: 66
2856 20:12:29.211580 [Byte1]: 66
2857 20:12:29.215810
2858 20:12:29.215883 Set Vref, RX VrefLevel [Byte0]: 67
2859 20:12:29.219130 [Byte1]: 67
2860 20:12:29.223764
2861 20:12:29.223836 Set Vref, RX VrefLevel [Byte0]: 68
2862 20:12:29.227034 [Byte1]: 68
2863 20:12:29.231472
2864 20:12:29.231547 Set Vref, RX VrefLevel [Byte0]: 69
2865 20:12:29.235165 [Byte1]: 69
2866 20:12:29.239639
2867 20:12:29.239713 Set Vref, RX VrefLevel [Byte0]: 70
2868 20:12:29.243016 [Byte1]: 70
2869 20:12:29.247302
2870 20:12:29.247389 Final RX Vref Byte 0 = 56 to rank0
2871 20:12:29.250874 Final RX Vref Byte 1 = 50 to rank0
2872 20:12:29.254288 Final RX Vref Byte 0 = 56 to rank1
2873 20:12:29.257511 Final RX Vref Byte 1 = 50 to rank1==
2874 20:12:29.260619 Dram Type= 6, Freq= 0, CH_0, rank 0
2875 20:12:29.267674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 20:12:29.267757 ==
2877 20:12:29.267825 DQS Delay:
2878 20:12:29.267885 DQS0 = 0, DQS1 = 0
2879 20:12:29.270846 DQM Delay:
2880 20:12:29.270954 DQM0 = 123, DQM1 = 109
2881 20:12:29.274059 DQ Delay:
2882 20:12:29.277452 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2883 20:12:29.280919 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =130
2884 20:12:29.284436 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2885 20:12:29.287562 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2886 20:12:29.287645
2887 20:12:29.287709
2888 20:12:29.294183 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2889 20:12:29.297565 CH0 RK0: MR19=404, MR18=804
2890 20:12:29.304032 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2891 20:12:29.304115
2892 20:12:29.307718 ----->DramcWriteLeveling(PI) begin...
2893 20:12:29.307801 ==
2894 20:12:29.310894 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 20:12:29.314373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 20:12:29.314456 ==
2897 20:12:29.317410 Write leveling (Byte 0): 34 => 34
2898 20:12:29.321105 Write leveling (Byte 1): 30 => 30
2899 20:12:29.324334 DramcWriteLeveling(PI) end<-----
2900 20:12:29.324416
2901 20:12:29.324480 ==
2902 20:12:29.327873 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 20:12:29.331180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 20:12:29.334482 ==
2905 20:12:29.334564 [Gating] SW mode calibration
2906 20:12:29.340977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2907 20:12:29.347882 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2908 20:12:29.351312 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2909 20:12:29.357908 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 20:12:29.361392 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 20:12:29.364375 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 20:12:29.371257 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 20:12:29.374583 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 20:12:29.377948 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 20:12:29.381184 0 15 28 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
2916 20:12:29.387869 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 20:12:29.391327 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 20:12:29.394617 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 20:12:29.401603 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 20:12:29.404446 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 20:12:29.407952 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 20:12:29.414961 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2923 20:12:29.417911 1 0 28 | B1->B0 | 3636 3e3e | 0 0 | (0 0) (1 1)
2924 20:12:29.421385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 20:12:29.428136 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 20:12:29.431237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 20:12:29.434577 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 20:12:29.441628 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 20:12:29.444676 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 20:12:29.448130 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 20:12:29.454756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 20:12:29.458148 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2933 20:12:29.461361 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 20:12:29.464825 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 20:12:29.471732 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 20:12:29.474940 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 20:12:29.478142 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 20:12:29.484976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 20:12:29.488593 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 20:12:29.492288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 20:12:29.498585 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 20:12:29.501879 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 20:12:29.505353 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 20:12:29.511796 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 20:12:29.515276 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 20:12:29.518660 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2947 20:12:29.521663 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2948 20:12:29.528239 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 20:12:29.531990 Total UI for P1: 0, mck2ui 16
2950 20:12:29.535443 best dqsien dly found for B0: ( 1, 3, 26)
2951 20:12:29.538861 Total UI for P1: 0, mck2ui 16
2952 20:12:29.541814 best dqsien dly found for B1: ( 1, 3, 28)
2953 20:12:29.545136 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2954 20:12:29.548393 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2955 20:12:29.548477
2956 20:12:29.551647 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2957 20:12:29.555352 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2958 20:12:29.558644 [Gating] SW calibration Done
2959 20:12:29.558728 ==
2960 20:12:29.561957 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 20:12:29.564999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 20:12:29.565098 ==
2963 20:12:29.568422 RX Vref Scan: 0
2964 20:12:29.568535
2965 20:12:29.568600 RX Vref 0 -> 0, step: 1
2966 20:12:29.568662
2967 20:12:29.572089 RX Delay -40 -> 252, step: 8
2968 20:12:29.575588 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2969 20:12:29.581980 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2970 20:12:29.585454 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2971 20:12:29.588593 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2972 20:12:29.591702 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2973 20:12:29.595739 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2974 20:12:29.601795 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2975 20:12:29.605189 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2976 20:12:29.608459 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2977 20:12:29.612166 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2978 20:12:29.615295 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2979 20:12:29.621984 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2980 20:12:29.625149 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2981 20:12:29.628341 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2982 20:12:29.631733 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2983 20:12:29.635057 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2984 20:12:29.638891 ==
2985 20:12:29.639028 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 20:12:29.645789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 20:12:29.645888 ==
2988 20:12:29.645975 DQS Delay:
2989 20:12:29.648748 DQS0 = 0, DQS1 = 0
2990 20:12:29.648831 DQM Delay:
2991 20:12:29.652027 DQM0 = 120, DQM1 = 108
2992 20:12:29.652109 DQ Delay:
2993 20:12:29.655585 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2994 20:12:29.658584 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2995 20:12:29.662450 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2996 20:12:29.665639 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2997 20:12:29.665722
2998 20:12:29.665787
2999 20:12:29.665875 ==
3000 20:12:29.668632 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 20:12:29.672058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 20:12:29.675216 ==
3003 20:12:29.675299
3004 20:12:29.675364
3005 20:12:29.675423 TX Vref Scan disable
3006 20:12:29.678581 == TX Byte 0 ==
3007 20:12:29.682585 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3008 20:12:29.685233 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3009 20:12:29.688751 == TX Byte 1 ==
3010 20:12:29.692327 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3011 20:12:29.695545 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3012 20:12:29.698716 ==
3013 20:12:29.698801 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 20:12:29.705511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 20:12:29.705600 ==
3016 20:12:29.716880 TX Vref=22, minBit 3, minWin=23, winSum=409
3017 20:12:29.720162 TX Vref=24, minBit 3, minWin=24, winSum=416
3018 20:12:29.723908 TX Vref=26, minBit 1, minWin=24, winSum=414
3019 20:12:29.726623 TX Vref=28, minBit 0, minWin=25, winSum=420
3020 20:12:29.729964 TX Vref=30, minBit 2, minWin=25, winSum=427
3021 20:12:29.733153 TX Vref=32, minBit 2, minWin=25, winSum=422
3022 20:12:29.740127 [TxChooseVref] Worse bit 2, Min win 25, Win sum 427, Final Vref 30
3023 20:12:29.740238
3024 20:12:29.743280 Final TX Range 1 Vref 30
3025 20:12:29.743354
3026 20:12:29.743417 ==
3027 20:12:29.746830 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 20:12:29.750230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 20:12:29.750308 ==
3030 20:12:29.750370
3031 20:12:29.750435
3032 20:12:29.753713 TX Vref Scan disable
3033 20:12:29.756685 == TX Byte 0 ==
3034 20:12:29.759903 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3035 20:12:29.763524 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3036 20:12:29.766694 == TX Byte 1 ==
3037 20:12:29.769817 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3038 20:12:29.773358 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3039 20:12:29.773442
3040 20:12:29.776826 [DATLAT]
3041 20:12:29.776900 Freq=1200, CH0 RK1
3042 20:12:29.776963
3043 20:12:29.779862 DATLAT Default: 0xd
3044 20:12:29.779946 0, 0xFFFF, sum = 0
3045 20:12:29.783467 1, 0xFFFF, sum = 0
3046 20:12:29.783554 2, 0xFFFF, sum = 0
3047 20:12:29.787049 3, 0xFFFF, sum = 0
3048 20:12:29.787134 4, 0xFFFF, sum = 0
3049 20:12:29.789922 5, 0xFFFF, sum = 0
3050 20:12:29.790019 6, 0xFFFF, sum = 0
3051 20:12:29.793716 7, 0xFFFF, sum = 0
3052 20:12:29.793851 8, 0xFFFF, sum = 0
3053 20:12:29.796855 9, 0xFFFF, sum = 0
3054 20:12:29.796940 10, 0xFFFF, sum = 0
3055 20:12:29.799793 11, 0xFFFF, sum = 0
3056 20:12:29.803626 12, 0x0, sum = 1
3057 20:12:29.803743 13, 0x0, sum = 2
3058 20:12:29.803863 14, 0x0, sum = 3
3059 20:12:29.806811 15, 0x0, sum = 4
3060 20:12:29.806972 best_step = 13
3061 20:12:29.807055
3062 20:12:29.807117 ==
3063 20:12:29.810218 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 20:12:29.816796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 20:12:29.816877 ==
3066 20:12:29.816942 RX Vref Scan: 0
3067 20:12:29.817003
3068 20:12:29.820521 RX Vref 0 -> 0, step: 1
3069 20:12:29.820596
3070 20:12:29.823834 RX Delay -21 -> 252, step: 4
3071 20:12:29.827054 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3072 20:12:29.830378 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3073 20:12:29.836780 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3074 20:12:29.840150 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3075 20:12:29.843611 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3076 20:12:29.846708 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3077 20:12:29.850385 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3078 20:12:29.856953 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3079 20:12:29.860261 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3080 20:12:29.863475 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3081 20:12:29.866622 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3082 20:12:29.870641 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3083 20:12:29.877329 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3084 20:12:29.880124 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3085 20:12:29.884062 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3086 20:12:29.886597 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3087 20:12:29.886698 ==
3088 20:12:29.890480 Dram Type= 6, Freq= 0, CH_0, rank 1
3089 20:12:29.893285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 20:12:29.896851 ==
3091 20:12:29.896923 DQS Delay:
3092 20:12:29.896984 DQS0 = 0, DQS1 = 0
3093 20:12:29.900017 DQM Delay:
3094 20:12:29.900114 DQM0 = 119, DQM1 = 108
3095 20:12:29.903904 DQ Delay:
3096 20:12:29.907021 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3097 20:12:29.910412 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3098 20:12:29.914087 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3099 20:12:29.916796 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
3100 20:12:29.916865
3101 20:12:29.916924
3102 20:12:29.923624 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3103 20:12:29.927044 CH0 RK1: MR19=403, MR18=CF4
3104 20:12:29.933703 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3105 20:12:29.936830 [RxdqsGatingPostProcess] freq 1200
3106 20:12:29.940131 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3107 20:12:29.943775 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 20:12:29.946963 best DQS1 dly(2T, 0.5T) = (0, 12)
3109 20:12:29.950494 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 20:12:29.953754 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3111 20:12:29.957098 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 20:12:29.960179 best DQS1 dly(2T, 0.5T) = (0, 11)
3113 20:12:29.963475 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 20:12:29.967140 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3115 20:12:29.970193 Pre-setting of DQS Precalculation
3116 20:12:29.974068 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3117 20:12:29.974142 ==
3118 20:12:29.977320 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 20:12:29.984043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 20:12:29.984144 ==
3121 20:12:29.987000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3122 20:12:29.993945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3123 20:12:30.002364 [CA 0] Center 37 (7~68) winsize 62
3124 20:12:30.005543 [CA 1] Center 37 (7~68) winsize 62
3125 20:12:30.009454 [CA 2] Center 35 (5~65) winsize 61
3126 20:12:30.012901 [CA 3] Center 34 (4~65) winsize 62
3127 20:12:30.016182 [CA 4] Center 34 (4~65) winsize 62
3128 20:12:30.019323 [CA 5] Center 33 (3~64) winsize 62
3129 20:12:30.019439
3130 20:12:30.022439 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3131 20:12:30.022524
3132 20:12:30.025819 [CATrainingPosCal] consider 1 rank data
3133 20:12:30.029014 u2DelayCellTimex100 = 270/100 ps
3134 20:12:30.032291 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 20:12:30.036138 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 20:12:30.042359 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3137 20:12:30.045472 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3138 20:12:30.049035 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3139 20:12:30.052394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3140 20:12:30.052478
3141 20:12:30.055868 CA PerBit enable=1, Macro0, CA PI delay=33
3142 20:12:30.055952
3143 20:12:30.059249 [CBTSetCACLKResult] CA Dly = 33
3144 20:12:30.059333 CS Dly: 5 (0~36)
3145 20:12:30.059400 ==
3146 20:12:30.062439 Dram Type= 6, Freq= 0, CH_1, rank 1
3147 20:12:30.069146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 20:12:30.069230 ==
3149 20:12:30.072560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3150 20:12:30.079044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3151 20:12:30.088433 [CA 0] Center 38 (8~68) winsize 61
3152 20:12:30.091477 [CA 1] Center 38 (7~69) winsize 63
3153 20:12:30.094456 [CA 2] Center 35 (5~66) winsize 62
3154 20:12:30.097928 [CA 3] Center 35 (5~65) winsize 61
3155 20:12:30.101524 [CA 4] Center 34 (4~64) winsize 61
3156 20:12:30.104639 [CA 5] Center 34 (4~64) winsize 61
3157 20:12:30.104723
3158 20:12:30.108167 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3159 20:12:30.108252
3160 20:12:30.111396 [CATrainingPosCal] consider 2 rank data
3161 20:12:30.114811 u2DelayCellTimex100 = 270/100 ps
3162 20:12:30.118025 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3163 20:12:30.121421 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3164 20:12:30.128217 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3165 20:12:30.131455 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3166 20:12:30.134823 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3167 20:12:30.138221 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3168 20:12:30.138305
3169 20:12:30.141204 CA PerBit enable=1, Macro0, CA PI delay=34
3170 20:12:30.141288
3171 20:12:30.144830 [CBTSetCACLKResult] CA Dly = 34
3172 20:12:30.144914 CS Dly: 6 (0~39)
3173 20:12:30.144981
3174 20:12:30.148456 ----->DramcWriteLeveling(PI) begin...
3175 20:12:30.151418 ==
3176 20:12:30.151503 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 20:12:30.157983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 20:12:30.158068 ==
3179 20:12:30.161500 Write leveling (Byte 0): 26 => 26
3180 20:12:30.164821 Write leveling (Byte 1): 28 => 28
3181 20:12:30.168165 DramcWriteLeveling(PI) end<-----
3182 20:12:30.168249
3183 20:12:30.168315 ==
3184 20:12:30.171541 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 20:12:30.175027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 20:12:30.175111 ==
3187 20:12:30.178097 [Gating] SW mode calibration
3188 20:12:30.184603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3189 20:12:30.188193 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3190 20:12:30.194563 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 20:12:30.197927 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 20:12:30.201566 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 20:12:30.208317 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 20:12:30.211652 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 20:12:30.214820 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3196 20:12:30.221506 0 15 24 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
3197 20:12:30.224726 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 20:12:30.228280 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 20:12:30.235245 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 20:12:30.238504 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 20:12:30.241658 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 20:12:30.248286 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 20:12:30.251718 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 20:12:30.255206 1 0 24 | B1->B0 | 3c3c 4242 | 1 0 | (0 0) (0 0)
3205 20:12:30.258604 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 20:12:30.264978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 20:12:30.268198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 20:12:30.271780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 20:12:30.278723 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 20:12:30.281847 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 20:12:30.285205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 20:12:30.291773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3213 20:12:30.294910 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 20:12:30.298525 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 20:12:30.304973 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 20:12:30.308425 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 20:12:30.312008 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 20:12:30.318628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 20:12:30.321786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 20:12:30.325112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 20:12:30.332000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 20:12:30.334858 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 20:12:30.338396 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 20:12:30.341553 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 20:12:30.348606 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 20:12:30.351781 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 20:12:30.355179 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 20:12:30.361489 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3229 20:12:30.365188 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 20:12:30.368585 Total UI for P1: 0, mck2ui 16
3231 20:12:30.371700 best dqsien dly found for B0: ( 1, 3, 24)
3232 20:12:30.375025 Total UI for P1: 0, mck2ui 16
3233 20:12:30.378511 best dqsien dly found for B1: ( 1, 3, 26)
3234 20:12:30.381715 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3235 20:12:30.385020 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3236 20:12:30.385092
3237 20:12:30.388606 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3238 20:12:30.391834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3239 20:12:30.395049 [Gating] SW calibration Done
3240 20:12:30.395122 ==
3241 20:12:30.398458 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 20:12:30.401714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 20:12:30.405485 ==
3244 20:12:30.405557 RX Vref Scan: 0
3245 20:12:30.405619
3246 20:12:30.408715 RX Vref 0 -> 0, step: 1
3247 20:12:30.408788
3248 20:12:30.411866 RX Delay -40 -> 252, step: 8
3249 20:12:30.415340 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3250 20:12:30.418333 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3251 20:12:30.421891 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3252 20:12:30.425229 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3253 20:12:30.428385 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3254 20:12:30.435335 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3255 20:12:30.438455 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3256 20:12:30.441831 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3257 20:12:30.445293 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3258 20:12:30.449011 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3259 20:12:30.455273 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3260 20:12:30.458669 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3261 20:12:30.461991 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3262 20:12:30.465204 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3263 20:12:30.468758 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3264 20:12:30.475284 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3265 20:12:30.475370 ==
3266 20:12:30.478498 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 20:12:30.481934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 20:12:30.482061 ==
3269 20:12:30.482128 DQS Delay:
3270 20:12:30.485508 DQS0 = 0, DQS1 = 0
3271 20:12:30.485592 DQM Delay:
3272 20:12:30.489059 DQM0 = 119, DQM1 = 112
3273 20:12:30.489143 DQ Delay:
3274 20:12:30.492310 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3275 20:12:30.495263 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3276 20:12:30.498804 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3277 20:12:30.502358 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3278 20:12:30.502441
3279 20:12:30.502508
3280 20:12:30.502569 ==
3281 20:12:30.505260 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 20:12:30.512356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 20:12:30.512441 ==
3284 20:12:30.512508
3285 20:12:30.512569
3286 20:12:30.512627 TX Vref Scan disable
3287 20:12:30.516071 == TX Byte 0 ==
3288 20:12:30.519390 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3289 20:12:30.522389 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3290 20:12:30.526312 == TX Byte 1 ==
3291 20:12:30.529338 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 20:12:30.532810 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 20:12:30.535745 ==
3294 20:12:30.539201 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 20:12:30.542978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 20:12:30.543063 ==
3297 20:12:30.553596 TX Vref=22, minBit 10, minWin=24, winSum=405
3298 20:12:30.556839 TX Vref=24, minBit 10, minWin=24, winSum=410
3299 20:12:30.560380 TX Vref=26, minBit 3, minWin=25, winSum=416
3300 20:12:30.563290 TX Vref=28, minBit 9, minWin=25, winSum=420
3301 20:12:30.566770 TX Vref=30, minBit 10, minWin=25, winSum=424
3302 20:12:30.573822 TX Vref=32, minBit 8, minWin=25, winSum=420
3303 20:12:30.576768 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 30
3304 20:12:30.576853
3305 20:12:30.580319 Final TX Range 1 Vref 30
3306 20:12:30.580403
3307 20:12:30.580469 ==
3308 20:12:30.583431 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 20:12:30.586910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 20:12:30.590050 ==
3311 20:12:30.590135
3312 20:12:30.590201
3313 20:12:30.590261 TX Vref Scan disable
3314 20:12:30.593826 == TX Byte 0 ==
3315 20:12:30.597189 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3316 20:12:30.600319 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3317 20:12:30.603533 == TX Byte 1 ==
3318 20:12:30.606974 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3319 20:12:30.610272 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3320 20:12:30.613701
3321 20:12:30.613785 [DATLAT]
3322 20:12:30.613851 Freq=1200, CH1 RK0
3323 20:12:30.613913
3324 20:12:30.617167 DATLAT Default: 0xd
3325 20:12:30.617250 0, 0xFFFF, sum = 0
3326 20:12:30.620733 1, 0xFFFF, sum = 0
3327 20:12:30.620818 2, 0xFFFF, sum = 0
3328 20:12:30.623900 3, 0xFFFF, sum = 0
3329 20:12:30.623985 4, 0xFFFF, sum = 0
3330 20:12:30.627300 5, 0xFFFF, sum = 0
3331 20:12:30.627386 6, 0xFFFF, sum = 0
3332 20:12:30.630513 7, 0xFFFF, sum = 0
3333 20:12:30.630625 8, 0xFFFF, sum = 0
3334 20:12:30.633701 9, 0xFFFF, sum = 0
3335 20:12:30.637437 10, 0xFFFF, sum = 0
3336 20:12:30.637549 11, 0xFFFF, sum = 0
3337 20:12:30.640596 12, 0x0, sum = 1
3338 20:12:30.640712 13, 0x0, sum = 2
3339 20:12:30.640783 14, 0x0, sum = 3
3340 20:12:30.643685 15, 0x0, sum = 4
3341 20:12:30.643780 best_step = 13
3342 20:12:30.643847
3343 20:12:30.647125 ==
3344 20:12:30.647209 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 20:12:30.653724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 20:12:30.653808 ==
3347 20:12:30.653875 RX Vref Scan: 1
3348 20:12:30.653936
3349 20:12:30.657210 Set Vref Range= 32 -> 127
3350 20:12:30.657294
3351 20:12:30.660489 RX Vref 32 -> 127, step: 1
3352 20:12:30.660573
3353 20:12:30.663774 RX Delay -13 -> 252, step: 4
3354 20:12:30.663858
3355 20:12:30.667246 Set Vref, RX VrefLevel [Byte0]: 32
3356 20:12:30.670659 [Byte1]: 32
3357 20:12:30.670742
3358 20:12:30.673702 Set Vref, RX VrefLevel [Byte0]: 33
3359 20:12:30.677434 [Byte1]: 33
3360 20:12:30.677516
3361 20:12:30.680383 Set Vref, RX VrefLevel [Byte0]: 34
3362 20:12:30.684120 [Byte1]: 34
3363 20:12:30.687773
3364 20:12:30.687855 Set Vref, RX VrefLevel [Byte0]: 35
3365 20:12:30.691365 [Byte1]: 35
3366 20:12:30.695813
3367 20:12:30.695894 Set Vref, RX VrefLevel [Byte0]: 36
3368 20:12:30.699015 [Byte1]: 36
3369 20:12:30.703509
3370 20:12:30.703591 Set Vref, RX VrefLevel [Byte0]: 37
3371 20:12:30.707015 [Byte1]: 37
3372 20:12:30.711647
3373 20:12:30.711729 Set Vref, RX VrefLevel [Byte0]: 38
3374 20:12:30.714739 [Byte1]: 38
3375 20:12:30.719169
3376 20:12:30.719250 Set Vref, RX VrefLevel [Byte0]: 39
3377 20:12:30.722694 [Byte1]: 39
3378 20:12:30.727602
3379 20:12:30.727683 Set Vref, RX VrefLevel [Byte0]: 40
3380 20:12:30.730605 [Byte1]: 40
3381 20:12:30.734911
3382 20:12:30.734998 Set Vref, RX VrefLevel [Byte0]: 41
3383 20:12:30.738695 [Byte1]: 41
3384 20:12:30.743515
3385 20:12:30.743597 Set Vref, RX VrefLevel [Byte0]: 42
3386 20:12:30.746244 [Byte1]: 42
3387 20:12:30.750847
3388 20:12:30.750929 Set Vref, RX VrefLevel [Byte0]: 43
3389 20:12:30.754347 [Byte1]: 43
3390 20:12:30.758850
3391 20:12:30.758932 Set Vref, RX VrefLevel [Byte0]: 44
3392 20:12:30.762105 [Byte1]: 44
3393 20:12:30.766955
3394 20:12:30.767036 Set Vref, RX VrefLevel [Byte0]: 45
3395 20:12:30.770375 [Byte1]: 45
3396 20:12:30.774920
3397 20:12:30.775002 Set Vref, RX VrefLevel [Byte0]: 46
3398 20:12:30.777936 [Byte1]: 46
3399 20:12:30.782453
3400 20:12:30.782535 Set Vref, RX VrefLevel [Byte0]: 47
3401 20:12:30.785937 [Byte1]: 47
3402 20:12:30.791045
3403 20:12:30.791127 Set Vref, RX VrefLevel [Byte0]: 48
3404 20:12:30.793746 [Byte1]: 48
3405 20:12:30.798466
3406 20:12:30.798548 Set Vref, RX VrefLevel [Byte0]: 49
3407 20:12:30.802091 [Byte1]: 49
3408 20:12:30.806329
3409 20:12:30.806410 Set Vref, RX VrefLevel [Byte0]: 50
3410 20:12:30.809417 [Byte1]: 50
3411 20:12:30.814057
3412 20:12:30.814138 Set Vref, RX VrefLevel [Byte0]: 51
3413 20:12:30.817635 [Byte1]: 51
3414 20:12:30.821975
3415 20:12:30.822057 Set Vref, RX VrefLevel [Byte0]: 52
3416 20:12:30.825464 [Byte1]: 52
3417 20:12:30.829881
3418 20:12:30.830001 Set Vref, RX VrefLevel [Byte0]: 53
3419 20:12:30.833338 [Byte1]: 53
3420 20:12:30.837912
3421 20:12:30.838022 Set Vref, RX VrefLevel [Byte0]: 54
3422 20:12:30.841232 [Byte1]: 54
3423 20:12:30.845895
3424 20:12:30.846017 Set Vref, RX VrefLevel [Byte0]: 55
3425 20:12:30.848776 [Byte1]: 55
3426 20:12:30.853407
3427 20:12:30.853489 Set Vref, RX VrefLevel [Byte0]: 56
3428 20:12:30.856756 [Byte1]: 56
3429 20:12:30.861729
3430 20:12:30.861811 Set Vref, RX VrefLevel [Byte0]: 57
3431 20:12:30.864593 [Byte1]: 57
3432 20:12:30.869536
3433 20:12:30.869620 Set Vref, RX VrefLevel [Byte0]: 58
3434 20:12:30.872809 [Byte1]: 58
3435 20:12:30.877200
3436 20:12:30.877284 Set Vref, RX VrefLevel [Byte0]: 59
3437 20:12:30.880565 [Byte1]: 59
3438 20:12:30.885044
3439 20:12:30.885128 Set Vref, RX VrefLevel [Byte0]: 60
3440 20:12:30.888256 [Byte1]: 60
3441 20:12:30.892809
3442 20:12:30.892909 Set Vref, RX VrefLevel [Byte0]: 61
3443 20:12:30.896363 [Byte1]: 61
3444 20:12:30.901070
3445 20:12:30.901154 Set Vref, RX VrefLevel [Byte0]: 62
3446 20:12:30.904221 [Byte1]: 62
3447 20:12:30.908807
3448 20:12:30.908891 Set Vref, RX VrefLevel [Byte0]: 63
3449 20:12:30.912167 [Byte1]: 63
3450 20:12:30.916589
3451 20:12:30.916678 Set Vref, RX VrefLevel [Byte0]: 64
3452 20:12:30.920164 [Byte1]: 64
3453 20:12:30.924432
3454 20:12:30.924516 Set Vref, RX VrefLevel [Byte0]: 65
3455 20:12:30.927935 [Byte1]: 65
3456 20:12:30.932501
3457 20:12:30.932584 Set Vref, RX VrefLevel [Byte0]: 66
3458 20:12:30.935585 [Byte1]: 66
3459 20:12:30.940571
3460 20:12:30.940655 Final RX Vref Byte 0 = 52 to rank0
3461 20:12:30.943656 Final RX Vref Byte 1 = 53 to rank0
3462 20:12:30.947116 Final RX Vref Byte 0 = 52 to rank1
3463 20:12:30.950427 Final RX Vref Byte 1 = 53 to rank1==
3464 20:12:30.953489 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 20:12:30.960326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 20:12:30.960411 ==
3467 20:12:30.960477 DQS Delay:
3468 20:12:30.960538 DQS0 = 0, DQS1 = 0
3469 20:12:30.963817 DQM Delay:
3470 20:12:30.963901 DQM0 = 119, DQM1 = 112
3471 20:12:30.966988 DQ Delay:
3472 20:12:30.970460 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3473 20:12:30.973594 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3474 20:12:30.977272 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3475 20:12:30.980501 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3476 20:12:30.980585
3477 20:12:30.980651
3478 20:12:30.987254 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3479 20:12:30.990280 CH1 RK0: MR19=304, MR18=FF12
3480 20:12:30.997376 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3481 20:12:30.997461
3482 20:12:31.000384 ----->DramcWriteLeveling(PI) begin...
3483 20:12:31.000470 ==
3484 20:12:31.003944 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 20:12:31.007217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 20:12:31.010759 ==
3487 20:12:31.010843 Write leveling (Byte 0): 25 => 25
3488 20:12:31.014068 Write leveling (Byte 1): 27 => 27
3489 20:12:31.017228 DramcWriteLeveling(PI) end<-----
3490 20:12:31.017315
3491 20:12:31.017381 ==
3492 20:12:31.020668 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 20:12:31.026983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 20:12:31.027068 ==
3495 20:12:31.027134 [Gating] SW mode calibration
3496 20:12:31.036858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 20:12:31.040574 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 20:12:31.043896 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 20:12:31.050635 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 20:12:31.053756 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 20:12:31.057210 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 20:12:31.063958 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 20:12:31.067190 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 20:12:31.070907 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (1 0) (1 0)
3505 20:12:31.077280 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (0 1)
3506 20:12:31.080972 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 20:12:31.084290 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 20:12:31.090630 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 20:12:31.094222 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 20:12:31.097466 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 20:12:31.101109 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 20:12:31.107795 1 0 24 | B1->B0 | 3e3e 2a2a | 1 0 | (0 0) (0 0)
3513 20:12:31.111018 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3514 20:12:31.114201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 20:12:31.120906 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 20:12:31.124463 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 20:12:31.127570 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 20:12:31.134550 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 20:12:31.137830 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 20:12:31.140880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3521 20:12:31.147532 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3522 20:12:31.151005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 20:12:31.154190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 20:12:31.161074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 20:12:31.164295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 20:12:31.167415 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 20:12:31.173922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 20:12:31.177454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 20:12:31.180923 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 20:12:31.187252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 20:12:31.190920 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 20:12:31.194044 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 20:12:31.197295 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 20:12:31.203933 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 20:12:31.207425 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 20:12:31.210744 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3537 20:12:31.217315 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 20:12:31.221057 Total UI for P1: 0, mck2ui 16
3539 20:12:31.223662 best dqsien dly found for B0: ( 1, 3, 24)
3540 20:12:31.227270 Total UI for P1: 0, mck2ui 16
3541 20:12:31.230781 best dqsien dly found for B1: ( 1, 3, 24)
3542 20:12:31.234296 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3543 20:12:31.237486 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3544 20:12:31.237570
3545 20:12:31.240420 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 20:12:31.243810 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 20:12:31.247004 [Gating] SW calibration Done
3548 20:12:31.247088 ==
3549 20:12:31.250488 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 20:12:31.253717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 20:12:31.253833 ==
3552 20:12:31.257017 RX Vref Scan: 0
3553 20:12:31.257100
3554 20:12:31.260152 RX Vref 0 -> 0, step: 1
3555 20:12:31.260236
3556 20:12:31.260302 RX Delay -40 -> 252, step: 8
3557 20:12:31.266958 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3558 20:12:31.270373 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3559 20:12:31.273585 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3560 20:12:31.277459 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3561 20:12:31.280205 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3562 20:12:31.286949 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3563 20:12:31.290038 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3564 20:12:31.293394 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3565 20:12:31.296966 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3566 20:12:31.300384 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3567 20:12:31.306911 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3568 20:12:31.310019 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3569 20:12:31.313467 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3570 20:12:31.316807 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3571 20:12:31.320302 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3572 20:12:31.326821 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3573 20:12:31.326905 ==
3574 20:12:31.329857 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 20:12:31.333471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 20:12:31.333555 ==
3577 20:12:31.333621 DQS Delay:
3578 20:12:31.336872 DQS0 = 0, DQS1 = 0
3579 20:12:31.336956 DQM Delay:
3580 20:12:31.340095 DQM0 = 120, DQM1 = 114
3581 20:12:31.340180 DQ Delay:
3582 20:12:31.343457 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3583 20:12:31.346984 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3584 20:12:31.349865 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3585 20:12:31.353153 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =127
3586 20:12:31.353237
3587 20:12:31.353302
3588 20:12:31.356551 ==
3589 20:12:31.359898 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 20:12:31.363480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 20:12:31.363566 ==
3592 20:12:31.363632
3593 20:12:31.363694
3594 20:12:31.366710 TX Vref Scan disable
3595 20:12:31.366794 == TX Byte 0 ==
3596 20:12:31.369762 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3597 20:12:31.376537 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3598 20:12:31.376621 == TX Byte 1 ==
3599 20:12:31.380177 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3600 20:12:31.386444 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3601 20:12:31.386529 ==
3602 20:12:31.390104 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 20:12:31.392946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 20:12:31.393031 ==
3605 20:12:31.405430 TX Vref=22, minBit 1, minWin=25, winSum=418
3606 20:12:31.408552 TX Vref=24, minBit 8, minWin=25, winSum=419
3607 20:12:31.411713 TX Vref=26, minBit 9, minWin=25, winSum=426
3608 20:12:31.415294 TX Vref=28, minBit 1, minWin=26, winSum=429
3609 20:12:31.418712 TX Vref=30, minBit 1, minWin=26, winSum=427
3610 20:12:31.425004 TX Vref=32, minBit 1, minWin=26, winSum=427
3611 20:12:31.428391 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3612 20:12:31.428476
3613 20:12:31.431779 Final TX Range 1 Vref 28
3614 20:12:31.431864
3615 20:12:31.431930 ==
3616 20:12:31.435364 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 20:12:31.438494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 20:12:31.438593 ==
3619 20:12:31.441682
3620 20:12:31.441766
3621 20:12:31.441831 TX Vref Scan disable
3622 20:12:31.445062 == TX Byte 0 ==
3623 20:12:31.448116 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3624 20:12:31.451603 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3625 20:12:31.454908 == TX Byte 1 ==
3626 20:12:31.458559 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3627 20:12:31.461815 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3628 20:12:31.465220
3629 20:12:31.465302 [DATLAT]
3630 20:12:31.465368 Freq=1200, CH1 RK1
3631 20:12:31.465467
3632 20:12:31.468248 DATLAT Default: 0xd
3633 20:12:31.468357 0, 0xFFFF, sum = 0
3634 20:12:31.471690 1, 0xFFFF, sum = 0
3635 20:12:31.471797 2, 0xFFFF, sum = 0
3636 20:12:31.475091 3, 0xFFFF, sum = 0
3637 20:12:31.475197 4, 0xFFFF, sum = 0
3638 20:12:31.478631 5, 0xFFFF, sum = 0
3639 20:12:31.481575 6, 0xFFFF, sum = 0
3640 20:12:31.481686 7, 0xFFFF, sum = 0
3641 20:12:31.484751 8, 0xFFFF, sum = 0
3642 20:12:31.484837 9, 0xFFFF, sum = 0
3643 20:12:31.488101 10, 0xFFFF, sum = 0
3644 20:12:31.488186 11, 0xFFFF, sum = 0
3645 20:12:31.491716 12, 0x0, sum = 1
3646 20:12:31.491800 13, 0x0, sum = 2
3647 20:12:31.495075 14, 0x0, sum = 3
3648 20:12:31.495159 15, 0x0, sum = 4
3649 20:12:31.495226 best_step = 13
3650 20:12:31.495287
3651 20:12:31.498133 ==
3652 20:12:31.501417 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 20:12:31.504893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 20:12:31.504977 ==
3655 20:12:31.505043 RX Vref Scan: 0
3656 20:12:31.505103
3657 20:12:31.508340 RX Vref 0 -> 0, step: 1
3658 20:12:31.508423
3659 20:12:31.511345 RX Delay -13 -> 252, step: 4
3660 20:12:31.514719 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3661 20:12:31.521645 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3662 20:12:31.524834 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3663 20:12:31.528252 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3664 20:12:31.531426 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3665 20:12:31.534984 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3666 20:12:31.541318 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3667 20:12:31.544741 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3668 20:12:31.547957 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3669 20:12:31.551290 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3670 20:12:31.554595 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3671 20:12:31.561117 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3672 20:12:31.564767 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3673 20:12:31.567777 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3674 20:12:31.571293 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3675 20:12:31.574784 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3676 20:12:31.578145 ==
3677 20:12:31.578223 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 20:12:31.584413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 20:12:31.584518 ==
3680 20:12:31.584610 DQS Delay:
3681 20:12:31.587912 DQS0 = 0, DQS1 = 0
3682 20:12:31.587985 DQM Delay:
3683 20:12:31.591015 DQM0 = 119, DQM1 = 113
3684 20:12:31.591112 DQ Delay:
3685 20:12:31.594647 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3686 20:12:31.597974 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3687 20:12:31.601048 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3688 20:12:31.604333 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3689 20:12:31.604435
3690 20:12:31.604524
3691 20:12:31.614478 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3692 20:12:31.614555 CH1 RK1: MR19=403, MR18=9EE
3693 20:12:31.621156 CH1_RK1: MR19=0x403, MR18=0x9EE, DQSOSC=406, MR23=63, INC=39, DEC=26
3694 20:12:31.624531 [RxdqsGatingPostProcess] freq 1200
3695 20:12:31.631150 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 20:12:31.634331 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 20:12:31.637621 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 20:12:31.641181 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 20:12:31.644239 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 20:12:31.647533 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 20:12:31.647617 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 20:12:31.651154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 20:12:31.654230 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 20:12:31.657740 Pre-setting of DQS Precalculation
3705 20:12:31.664325 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 20:12:31.671038 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 20:12:31.677980 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 20:12:31.678063
3709 20:12:31.678128
3710 20:12:31.681253 [Calibration Summary] 2400 Mbps
3711 20:12:31.684246 CH 0, Rank 0
3712 20:12:31.684330 SW Impedance : PASS
3713 20:12:31.687401 DUTY Scan : NO K
3714 20:12:31.687484 ZQ Calibration : PASS
3715 20:12:31.690660 Jitter Meter : NO K
3716 20:12:31.694246 CBT Training : PASS
3717 20:12:31.694328 Write leveling : PASS
3718 20:12:31.697327 RX DQS gating : PASS
3719 20:12:31.700752 RX DQ/DQS(RDDQC) : PASS
3720 20:12:31.700835 TX DQ/DQS : PASS
3721 20:12:31.703857 RX DATLAT : PASS
3722 20:12:31.707427 RX DQ/DQS(Engine): PASS
3723 20:12:31.707509 TX OE : NO K
3724 20:12:31.710840 All Pass.
3725 20:12:31.710923
3726 20:12:31.710988 CH 0, Rank 1
3727 20:12:31.714090 SW Impedance : PASS
3728 20:12:31.714172 DUTY Scan : NO K
3729 20:12:31.717159 ZQ Calibration : PASS
3730 20:12:31.720814 Jitter Meter : NO K
3731 20:12:31.720898 CBT Training : PASS
3732 20:12:31.724215 Write leveling : PASS
3733 20:12:31.727341 RX DQS gating : PASS
3734 20:12:31.727425 RX DQ/DQS(RDDQC) : PASS
3735 20:12:31.730966 TX DQ/DQS : PASS
3736 20:12:31.731050 RX DATLAT : PASS
3737 20:12:31.734198 RX DQ/DQS(Engine): PASS
3738 20:12:31.737463 TX OE : NO K
3739 20:12:31.737547 All Pass.
3740 20:12:31.737614
3741 20:12:31.737674 CH 1, Rank 0
3742 20:12:31.740674 SW Impedance : PASS
3743 20:12:31.744045 DUTY Scan : NO K
3744 20:12:31.744129 ZQ Calibration : PASS
3745 20:12:31.747093 Jitter Meter : NO K
3746 20:12:31.750701 CBT Training : PASS
3747 20:12:31.750785 Write leveling : PASS
3748 20:12:31.754141 RX DQS gating : PASS
3749 20:12:31.757212 RX DQ/DQS(RDDQC) : PASS
3750 20:12:31.757296 TX DQ/DQS : PASS
3751 20:12:31.760765 RX DATLAT : PASS
3752 20:12:31.763858 RX DQ/DQS(Engine): PASS
3753 20:12:31.763941 TX OE : NO K
3754 20:12:31.767225 All Pass.
3755 20:12:31.767309
3756 20:12:31.767374 CH 1, Rank 1
3757 20:12:31.770703 SW Impedance : PASS
3758 20:12:31.770786 DUTY Scan : NO K
3759 20:12:31.773774 ZQ Calibration : PASS
3760 20:12:31.777211 Jitter Meter : NO K
3761 20:12:31.777305 CBT Training : PASS
3762 20:12:31.780409 Write leveling : PASS
3763 20:12:31.783996 RX DQS gating : PASS
3764 20:12:31.784079 RX DQ/DQS(RDDQC) : PASS
3765 20:12:31.787222 TX DQ/DQS : PASS
3766 20:12:31.787306 RX DATLAT : PASS
3767 20:12:31.790760 RX DQ/DQS(Engine): PASS
3768 20:12:31.793835 TX OE : NO K
3769 20:12:31.793936 All Pass.
3770 20:12:31.794023
3771 20:12:31.797064 DramC Write-DBI off
3772 20:12:31.797148 PER_BANK_REFRESH: Hybrid Mode
3773 20:12:31.800541 TX_TRACKING: ON
3774 20:12:31.810587 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 20:12:31.813894 [FAST_K] Save calibration result to emmc
3776 20:12:31.816873 dramc_set_vcore_voltage set vcore to 650000
3777 20:12:31.816957 Read voltage for 600, 5
3778 20:12:31.820518 Vio18 = 0
3779 20:12:31.820601 Vcore = 650000
3780 20:12:31.820668 Vdram = 0
3781 20:12:31.823945 Vddq = 0
3782 20:12:31.824028 Vmddr = 0
3783 20:12:31.826979 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 20:12:31.833605 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 20:12:31.836802 MEM_TYPE=3, freq_sel=19
3786 20:12:31.840463 sv_algorithm_assistance_LP4_1600
3787 20:12:31.843827 ============ PULL DRAM RESETB DOWN ============
3788 20:12:31.847064 ========== PULL DRAM RESETB DOWN end =========
3789 20:12:31.853509 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 20:12:31.857114 ===================================
3791 20:12:31.857199 LPDDR4 DRAM CONFIGURATION
3792 20:12:31.860286 ===================================
3793 20:12:31.863734 EX_ROW_EN[0] = 0x0
3794 20:12:31.863818 EX_ROW_EN[1] = 0x0
3795 20:12:31.866957 LP4Y_EN = 0x0
3796 20:12:31.867040 WORK_FSP = 0x0
3797 20:12:31.870620 WL = 0x2
3798 20:12:31.870704 RL = 0x2
3799 20:12:31.874197 BL = 0x2
3800 20:12:31.874284 RPST = 0x0
3801 20:12:31.876994 RD_PRE = 0x0
3802 20:12:31.880305 WR_PRE = 0x1
3803 20:12:31.880389 WR_PST = 0x0
3804 20:12:31.884203 DBI_WR = 0x0
3805 20:12:31.884287 DBI_RD = 0x0
3806 20:12:31.887067 OTF = 0x1
3807 20:12:31.890429 ===================================
3808 20:12:31.893555 ===================================
3809 20:12:31.893639 ANA top config
3810 20:12:31.896969 ===================================
3811 20:12:31.900652 DLL_ASYNC_EN = 0
3812 20:12:31.903479 ALL_SLAVE_EN = 1
3813 20:12:31.903562 NEW_RANK_MODE = 1
3814 20:12:31.906997 DLL_IDLE_MODE = 1
3815 20:12:31.910445 LP45_APHY_COMB_EN = 1
3816 20:12:31.913982 TX_ODT_DIS = 1
3817 20:12:31.914065 NEW_8X_MODE = 1
3818 20:12:31.916900 ===================================
3819 20:12:31.920563 ===================================
3820 20:12:31.923755 data_rate = 1200
3821 20:12:31.926782 CKR = 1
3822 20:12:31.930219 DQ_P2S_RATIO = 8
3823 20:12:31.933488 ===================================
3824 20:12:31.937111 CA_P2S_RATIO = 8
3825 20:12:31.940352 DQ_CA_OPEN = 0
3826 20:12:31.940436 DQ_SEMI_OPEN = 0
3827 20:12:31.943511 CA_SEMI_OPEN = 0
3828 20:12:31.946842 CA_FULL_RATE = 0
3829 20:12:31.950520 DQ_CKDIV4_EN = 1
3830 20:12:31.953737 CA_CKDIV4_EN = 1
3831 20:12:31.956861 CA_PREDIV_EN = 0
3832 20:12:31.956944 PH8_DLY = 0
3833 20:12:31.960200 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 20:12:31.963710 DQ_AAMCK_DIV = 4
3835 20:12:31.966840 CA_AAMCK_DIV = 4
3836 20:12:31.969960 CA_ADMCK_DIV = 4
3837 20:12:31.973459 DQ_TRACK_CA_EN = 0
3838 20:12:31.973543 CA_PICK = 600
3839 20:12:31.976791 CA_MCKIO = 600
3840 20:12:31.979832 MCKIO_SEMI = 0
3841 20:12:31.983472 PLL_FREQ = 2288
3842 20:12:31.986575 DQ_UI_PI_RATIO = 32
3843 20:12:31.989975 CA_UI_PI_RATIO = 0
3844 20:12:31.993239 ===================================
3845 20:12:31.996853 ===================================
3846 20:12:31.996937 memory_type:LPDDR4
3847 20:12:32.000061 GP_NUM : 10
3848 20:12:32.003196 SRAM_EN : 1
3849 20:12:32.003280 MD32_EN : 0
3850 20:12:32.006706 ===================================
3851 20:12:32.010156 [ANA_INIT] >>>>>>>>>>>>>>
3852 20:12:32.013568 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 20:12:32.016599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 20:12:32.019782 ===================================
3855 20:12:32.023396 data_rate = 1200,PCW = 0X5800
3856 20:12:32.026435 ===================================
3857 20:12:32.030043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 20:12:32.033679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 20:12:32.039991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 20:12:32.043023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 20:12:32.046489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 20:12:32.049949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 20:12:32.053263 [ANA_INIT] flow start
3864 20:12:32.056694 [ANA_INIT] PLL >>>>>>>>
3865 20:12:32.056778 [ANA_INIT] PLL <<<<<<<<
3866 20:12:32.059780 [ANA_INIT] MIDPI >>>>>>>>
3867 20:12:32.063281 [ANA_INIT] MIDPI <<<<<<<<
3868 20:12:32.066720 [ANA_INIT] DLL >>>>>>>>
3869 20:12:32.066804 [ANA_INIT] flow end
3870 20:12:32.069979 ============ LP4 DIFF to SE enter ============
3871 20:12:32.076707 ============ LP4 DIFF to SE exit ============
3872 20:12:32.076817 [ANA_INIT] <<<<<<<<<<<<<
3873 20:12:32.079861 [Flow] Enable top DCM control >>>>>
3874 20:12:32.083065 [Flow] Enable top DCM control <<<<<
3875 20:12:32.086496 Enable DLL master slave shuffle
3876 20:12:32.093429 ==============================================================
3877 20:12:32.093513 Gating Mode config
3878 20:12:32.099760 ==============================================================
3879 20:12:32.103038 Config description:
3880 20:12:32.113384 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 20:12:32.120013 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 20:12:32.122827 SELPH_MODE 0: By rank 1: By Phase
3883 20:12:32.129461 ==============================================================
3884 20:12:32.133066 GAT_TRACK_EN = 1
3885 20:12:32.133150 RX_GATING_MODE = 2
3886 20:12:32.136178 RX_GATING_TRACK_MODE = 2
3887 20:12:32.139734 SELPH_MODE = 1
3888 20:12:32.142795 PICG_EARLY_EN = 1
3889 20:12:32.146397 VALID_LAT_VALUE = 1
3890 20:12:32.152881 ==============================================================
3891 20:12:32.156579 Enter into Gating configuration >>>>
3892 20:12:32.159481 Exit from Gating configuration <<<<
3893 20:12:32.162921 Enter into DVFS_PRE_config >>>>>
3894 20:12:32.172717 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 20:12:32.176549 Exit from DVFS_PRE_config <<<<<
3896 20:12:32.179514 Enter into PICG configuration >>>>
3897 20:12:32.183048 Exit from PICG configuration <<<<
3898 20:12:32.186081 [RX_INPUT] configuration >>>>>
3899 20:12:32.189493 [RX_INPUT] configuration <<<<<
3900 20:12:32.192948 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 20:12:32.199342 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 20:12:32.206043 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 20:12:32.209412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 20:12:32.216187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 20:12:32.222555 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 20:12:32.226049 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 20:12:32.229287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 20:12:32.236195 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 20:12:32.239503 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 20:12:32.242685 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 20:12:32.249227 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 20:12:32.252781 ===================================
3913 20:12:32.252866 LPDDR4 DRAM CONFIGURATION
3914 20:12:32.255860 ===================================
3915 20:12:32.259463 EX_ROW_EN[0] = 0x0
3916 20:12:32.259547 EX_ROW_EN[1] = 0x0
3917 20:12:32.262651 LP4Y_EN = 0x0
3918 20:12:32.265719 WORK_FSP = 0x0
3919 20:12:32.265802 WL = 0x2
3920 20:12:32.269293 RL = 0x2
3921 20:12:32.269377 BL = 0x2
3922 20:12:32.272452 RPST = 0x0
3923 20:12:32.272536 RD_PRE = 0x0
3924 20:12:32.275753 WR_PRE = 0x1
3925 20:12:32.275837 WR_PST = 0x0
3926 20:12:32.279274 DBI_WR = 0x0
3927 20:12:32.279357 DBI_RD = 0x0
3928 20:12:32.282678 OTF = 0x1
3929 20:12:32.285903 ===================================
3930 20:12:32.289085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 20:12:32.292490 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 20:12:32.299337 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 20:12:32.302367 ===================================
3934 20:12:32.302451 LPDDR4 DRAM CONFIGURATION
3935 20:12:32.306019 ===================================
3936 20:12:32.309422 EX_ROW_EN[0] = 0x10
3937 20:12:32.309505 EX_ROW_EN[1] = 0x0
3938 20:12:32.312455 LP4Y_EN = 0x0
3939 20:12:32.312538 WORK_FSP = 0x0
3940 20:12:32.315638 WL = 0x2
3941 20:12:32.315722 RL = 0x2
3942 20:12:32.319192 BL = 0x2
3943 20:12:32.322505 RPST = 0x0
3944 20:12:32.322589 RD_PRE = 0x0
3945 20:12:32.326260 WR_PRE = 0x1
3946 20:12:32.326343 WR_PST = 0x0
3947 20:12:32.329266 DBI_WR = 0x0
3948 20:12:32.329349 DBI_RD = 0x0
3949 20:12:32.332404 OTF = 0x1
3950 20:12:32.335703 ===================================
3951 20:12:32.339233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 20:12:32.344293 nWR fixed to 30
3953 20:12:32.347979 [ModeRegInit_LP4] CH0 RK0
3954 20:12:32.348063 [ModeRegInit_LP4] CH0 RK1
3955 20:12:32.351093 [ModeRegInit_LP4] CH1 RK0
3956 20:12:32.354476 [ModeRegInit_LP4] CH1 RK1
3957 20:12:32.354578 match AC timing 17
3958 20:12:32.361298 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 20:12:32.364235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 20:12:32.367871 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 20:12:32.374760 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 20:12:32.377723 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 20:12:32.377807 ==
3964 20:12:32.380849 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 20:12:32.384444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 20:12:32.384529 ==
3967 20:12:32.390937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 20:12:32.397386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3969 20:12:32.400846 [CA 0] Center 36 (6~67) winsize 62
3970 20:12:32.404242 [CA 1] Center 36 (6~67) winsize 62
3971 20:12:32.407345 [CA 2] Center 34 (4~65) winsize 62
3972 20:12:32.410739 [CA 3] Center 34 (3~65) winsize 63
3973 20:12:32.414014 [CA 4] Center 34 (3~65) winsize 63
3974 20:12:32.417704 [CA 5] Center 33 (2~64) winsize 63
3975 20:12:32.417788
3976 20:12:32.420790 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3977 20:12:32.420874
3978 20:12:32.424264 [CATrainingPosCal] consider 1 rank data
3979 20:12:32.427536 u2DelayCellTimex100 = 270/100 ps
3980 20:12:32.430770 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 20:12:32.433837 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3982 20:12:32.437382 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 20:12:32.440506 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3984 20:12:32.443807 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3985 20:12:32.450816 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3986 20:12:32.450899
3987 20:12:32.454286 CA PerBit enable=1, Macro0, CA PI delay=33
3988 20:12:32.454370
3989 20:12:32.457281 [CBTSetCACLKResult] CA Dly = 33
3990 20:12:32.457364 CS Dly: 4 (0~35)
3991 20:12:32.457430 ==
3992 20:12:32.461074 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 20:12:32.464196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 20:12:32.467327 ==
3995 20:12:32.470598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 20:12:32.477366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3997 20:12:32.480569 [CA 0] Center 36 (6~67) winsize 62
3998 20:12:32.483900 [CA 1] Center 36 (6~67) winsize 62
3999 20:12:32.486992 [CA 2] Center 35 (5~66) winsize 62
4000 20:12:32.490542 [CA 3] Center 35 (4~66) winsize 63
4001 20:12:32.493843 [CA 4] Center 34 (3~65) winsize 63
4002 20:12:32.497306 [CA 5] Center 34 (4~65) winsize 62
4003 20:12:32.497390
4004 20:12:32.500503 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4005 20:12:32.500587
4006 20:12:32.503663 [CATrainingPosCal] consider 2 rank data
4007 20:12:32.507301 u2DelayCellTimex100 = 270/100 ps
4008 20:12:32.510388 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4009 20:12:32.513867 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4010 20:12:32.517101 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4011 20:12:32.520844 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4012 20:12:32.524107 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4013 20:12:32.530980 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4014 20:12:32.531069
4015 20:12:32.533917 CA PerBit enable=1, Macro0, CA PI delay=34
4016 20:12:32.534023
4017 20:12:32.537221 [CBTSetCACLKResult] CA Dly = 34
4018 20:12:32.537304 CS Dly: 5 (0~38)
4019 20:12:32.537371
4020 20:12:32.540457 ----->DramcWriteLeveling(PI) begin...
4021 20:12:32.540542 ==
4022 20:12:32.543912 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 20:12:32.550269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 20:12:32.550354 ==
4025 20:12:32.553716 Write leveling (Byte 0): 31 => 31
4026 20:12:32.553800 Write leveling (Byte 1): 31 => 31
4027 20:12:32.556811 DramcWriteLeveling(PI) end<-----
4028 20:12:32.556895
4029 20:12:32.560720 ==
4030 20:12:32.560804 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 20:12:32.567106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 20:12:32.567190 ==
4033 20:12:32.570180 [Gating] SW mode calibration
4034 20:12:32.576821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 20:12:32.580053 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 20:12:32.586548 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 20:12:32.590215 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 20:12:32.593650 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4039 20:12:32.599881 0 9 12 | B1->B0 | 3131 2d2d | 1 1 | (0 1) (0 1)
4040 20:12:32.603371 0 9 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (1 0)
4041 20:12:32.606584 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 20:12:32.613112 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 20:12:32.616273 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 20:12:32.619734 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 20:12:32.626420 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 20:12:32.629983 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4047 20:12:32.633347 0 10 12 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
4048 20:12:32.639827 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4049 20:12:32.643060 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 20:12:32.646396 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 20:12:32.653044 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 20:12:32.656465 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 20:12:32.659998 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 20:12:32.663025 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 20:12:32.669965 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4056 20:12:32.673032 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 20:12:32.676495 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 20:12:32.683171 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 20:12:32.686534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 20:12:32.689788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 20:12:32.696382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 20:12:32.699917 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 20:12:32.703224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 20:12:32.709745 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 20:12:32.712730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 20:12:32.716322 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 20:12:32.723028 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 20:12:32.726032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 20:12:32.729421 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 20:12:32.736181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 20:12:32.739749 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4072 20:12:32.743060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 20:12:32.746532 Total UI for P1: 0, mck2ui 16
4074 20:12:32.749554 best dqsien dly found for B0: ( 0, 13, 12)
4075 20:12:32.752848 Total UI for P1: 0, mck2ui 16
4076 20:12:32.756079 best dqsien dly found for B1: ( 0, 13, 14)
4077 20:12:32.759333 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4078 20:12:32.762594 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4079 20:12:32.762664
4080 20:12:32.769539 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 20:12:32.772920 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4082 20:12:32.773030 [Gating] SW calibration Done
4083 20:12:32.776031 ==
4084 20:12:32.779550 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 20:12:32.782937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 20:12:32.783042 ==
4087 20:12:32.783140 RX Vref Scan: 0
4088 20:12:32.783230
4089 20:12:32.786028 RX Vref 0 -> 0, step: 1
4090 20:12:32.786102
4091 20:12:32.789241 RX Delay -230 -> 252, step: 16
4092 20:12:32.792388 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4093 20:12:32.795921 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4094 20:12:32.802299 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4095 20:12:32.805907 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4096 20:12:32.809032 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4097 20:12:32.812440 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4098 20:12:32.819176 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4099 20:12:32.822272 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4100 20:12:32.825765 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4101 20:12:32.828985 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4102 20:12:32.832370 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4103 20:12:32.838767 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4104 20:12:32.842331 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4105 20:12:32.845483 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4106 20:12:32.849031 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4107 20:12:32.855872 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4108 20:12:32.855949 ==
4109 20:12:32.859182 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 20:12:32.862404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 20:12:32.862478 ==
4112 20:12:32.862544 DQS Delay:
4113 20:12:32.865556 DQS0 = 0, DQS1 = 0
4114 20:12:32.865628 DQM Delay:
4115 20:12:32.869272 DQM0 = 52, DQM1 = 39
4116 20:12:32.869347 DQ Delay:
4117 20:12:32.872267 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4118 20:12:32.875801 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4119 20:12:32.878783 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4120 20:12:32.882200 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4121 20:12:32.882276
4122 20:12:32.882339
4123 20:12:32.882398 ==
4124 20:12:32.885999 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 20:12:32.888654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 20:12:32.888727 ==
4127 20:12:32.888791
4128 20:12:32.892477
4129 20:12:32.892579 TX Vref Scan disable
4130 20:12:32.895555 == TX Byte 0 ==
4131 20:12:32.898985 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4132 20:12:32.902157 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4133 20:12:32.905600 == TX Byte 1 ==
4134 20:12:32.908640 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4135 20:12:32.912108 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4136 20:12:32.912195 ==
4137 20:12:32.915629 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 20:12:32.921942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 20:12:32.922054 ==
4140 20:12:32.922118
4141 20:12:32.922177
4142 20:12:32.922234 TX Vref Scan disable
4143 20:12:32.926440 == TX Byte 0 ==
4144 20:12:32.929879 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4145 20:12:32.936610 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4146 20:12:32.936685 == TX Byte 1 ==
4147 20:12:32.939951 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4148 20:12:32.946247 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4149 20:12:32.946326
4150 20:12:32.946392 [DATLAT]
4151 20:12:32.946452 Freq=600, CH0 RK0
4152 20:12:32.946510
4153 20:12:32.949729 DATLAT Default: 0x9
4154 20:12:32.949806 0, 0xFFFF, sum = 0
4155 20:12:32.952785 1, 0xFFFF, sum = 0
4156 20:12:32.952860 2, 0xFFFF, sum = 0
4157 20:12:32.956268 3, 0xFFFF, sum = 0
4158 20:12:32.959730 4, 0xFFFF, sum = 0
4159 20:12:32.959806 5, 0xFFFF, sum = 0
4160 20:12:32.962946 6, 0xFFFF, sum = 0
4161 20:12:32.963022 7, 0xFFFF, sum = 0
4162 20:12:32.966208 8, 0x0, sum = 1
4163 20:12:32.966284 9, 0x0, sum = 2
4164 20:12:32.966348 10, 0x0, sum = 3
4165 20:12:32.969881 11, 0x0, sum = 4
4166 20:12:32.969962 best_step = 9
4167 20:12:32.970026
4168 20:12:32.970084 ==
4169 20:12:32.973551 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 20:12:32.980029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 20:12:32.980107 ==
4172 20:12:32.980170 RX Vref Scan: 1
4173 20:12:32.980250
4174 20:12:32.982994 RX Vref 0 -> 0, step: 1
4175 20:12:32.983068
4176 20:12:32.986332 RX Delay -179 -> 252, step: 8
4177 20:12:32.986404
4178 20:12:32.989563 Set Vref, RX VrefLevel [Byte0]: 56
4179 20:12:32.993197 [Byte1]: 50
4180 20:12:32.993273
4181 20:12:32.996156 Final RX Vref Byte 0 = 56 to rank0
4182 20:12:32.999838 Final RX Vref Byte 1 = 50 to rank0
4183 20:12:33.003136 Final RX Vref Byte 0 = 56 to rank1
4184 20:12:33.006241 Final RX Vref Byte 1 = 50 to rank1==
4185 20:12:33.009408 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 20:12:33.012583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 20:12:33.012682 ==
4188 20:12:33.016079 DQS Delay:
4189 20:12:33.016147 DQS0 = 0, DQS1 = 0
4190 20:12:33.016207 DQM Delay:
4191 20:12:33.019391 DQM0 = 49, DQM1 = 38
4192 20:12:33.019462 DQ Delay:
4193 20:12:33.022794 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4194 20:12:33.026161 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4195 20:12:33.029386 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4196 20:12:33.032604 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4197 20:12:33.032676
4198 20:12:33.032738
4199 20:12:33.042827 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4200 20:12:33.045714 CH0 RK0: MR19=808, MR18=5852
4201 20:12:33.052758 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4202 20:12:33.052832
4203 20:12:33.055678 ----->DramcWriteLeveling(PI) begin...
4204 20:12:33.055747 ==
4205 20:12:33.059216 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 20:12:33.062431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 20:12:33.062500 ==
4208 20:12:33.066066 Write leveling (Byte 0): 33 => 33
4209 20:12:33.068966 Write leveling (Byte 1): 30 => 30
4210 20:12:33.072142 DramcWriteLeveling(PI) end<-----
4211 20:12:33.072210
4212 20:12:33.072269 ==
4213 20:12:33.075604 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 20:12:33.078774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 20:12:33.078848 ==
4216 20:12:33.082182 [Gating] SW mode calibration
4217 20:12:33.088641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 20:12:33.095465 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 20:12:33.098809 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 20:12:33.102138 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 20:12:33.108742 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 20:12:33.112170 0 9 12 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
4223 20:12:33.115326 0 9 16 | B1->B0 | 2828 2727 | 1 0 | (1 0) (1 0)
4224 20:12:33.122035 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 20:12:33.125592 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 20:12:33.128700 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 20:12:33.135238 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 20:12:33.138635 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 20:12:33.141923 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 20:12:33.148408 0 10 12 | B1->B0 | 3232 3636 | 0 0 | (1 1) (0 0)
4231 20:12:33.151928 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4232 20:12:33.155665 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 20:12:33.162137 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 20:12:33.165136 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 20:12:33.168673 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 20:12:33.171966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 20:12:33.178537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 20:12:33.181640 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4239 20:12:33.185249 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 20:12:33.191827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 20:12:33.195427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 20:12:33.198348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 20:12:33.204776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 20:12:33.208387 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 20:12:33.211404 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 20:12:33.218166 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 20:12:33.221513 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 20:12:33.224951 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 20:12:33.231736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 20:12:33.234840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 20:12:33.238190 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 20:12:33.244872 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 20:12:33.248316 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 20:12:33.251370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4255 20:12:33.258189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4256 20:12:33.258272 Total UI for P1: 0, mck2ui 16
4257 20:12:33.265183 best dqsien dly found for B0: ( 0, 13, 12)
4258 20:12:33.268527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 20:12:33.271505 Total UI for P1: 0, mck2ui 16
4260 20:12:33.274728 best dqsien dly found for B1: ( 0, 13, 14)
4261 20:12:33.278419 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 20:12:33.281524 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4263 20:12:33.281607
4264 20:12:33.285176 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 20:12:33.288190 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4266 20:12:33.291576 [Gating] SW calibration Done
4267 20:12:33.291659 ==
4268 20:12:33.294863 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 20:12:33.298263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 20:12:33.301615 ==
4271 20:12:33.301698 RX Vref Scan: 0
4272 20:12:33.301764
4273 20:12:33.305051 RX Vref 0 -> 0, step: 1
4274 20:12:33.305134
4275 20:12:33.308188 RX Delay -230 -> 252, step: 16
4276 20:12:33.311465 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4277 20:12:33.315110 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4278 20:12:33.318068 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4279 20:12:33.321506 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4280 20:12:33.328249 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4281 20:12:33.331470 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4282 20:12:33.334511 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4283 20:12:33.338060 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4284 20:12:33.344609 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4285 20:12:33.348384 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4286 20:12:33.351694 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4287 20:12:33.354662 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4288 20:12:33.358102 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4289 20:12:33.364737 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4290 20:12:33.367792 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4291 20:12:33.371487 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4292 20:12:33.371570 ==
4293 20:12:33.374560 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 20:12:33.381003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 20:12:33.381087 ==
4296 20:12:33.381153 DQS Delay:
4297 20:12:33.384596 DQS0 = 0, DQS1 = 0
4298 20:12:33.384679 DQM Delay:
4299 20:12:33.384743 DQM0 = 50, DQM1 = 42
4300 20:12:33.387719 DQ Delay:
4301 20:12:33.391171 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4302 20:12:33.394693 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4303 20:12:33.394777 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4304 20:12:33.401357 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4305 20:12:33.401439
4306 20:12:33.401504
4307 20:12:33.401563 ==
4308 20:12:33.404403 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 20:12:33.407810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 20:12:33.407893 ==
4311 20:12:33.407959
4312 20:12:33.408019
4313 20:12:33.411343 TX Vref Scan disable
4314 20:12:33.411426 == TX Byte 0 ==
4315 20:12:33.417970 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4316 20:12:33.421295 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4317 20:12:33.421378 == TX Byte 1 ==
4318 20:12:33.427871 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4319 20:12:33.431369 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4320 20:12:33.431452 ==
4321 20:12:33.434675 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 20:12:33.437640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 20:12:33.437724 ==
4324 20:12:33.437790
4325 20:12:33.437850
4326 20:12:33.440881 TX Vref Scan disable
4327 20:12:33.444473 == TX Byte 0 ==
4328 20:12:33.447702 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4329 20:12:33.451246 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4330 20:12:33.454396 == TX Byte 1 ==
4331 20:12:33.457635 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4332 20:12:33.461202 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4333 20:12:33.464219
4334 20:12:33.464301 [DATLAT]
4335 20:12:33.464366 Freq=600, CH0 RK1
4336 20:12:33.464426
4337 20:12:33.468229 DATLAT Default: 0x9
4338 20:12:33.468312 0, 0xFFFF, sum = 0
4339 20:12:33.471402 1, 0xFFFF, sum = 0
4340 20:12:33.471486 2, 0xFFFF, sum = 0
4341 20:12:33.474747 3, 0xFFFF, sum = 0
4342 20:12:33.474833 4, 0xFFFF, sum = 0
4343 20:12:33.477851 5, 0xFFFF, sum = 0
4344 20:12:33.480972 6, 0xFFFF, sum = 0
4345 20:12:33.481058 7, 0xFFFF, sum = 0
4346 20:12:33.481125 8, 0x0, sum = 1
4347 20:12:33.484455 9, 0x0, sum = 2
4348 20:12:33.484539 10, 0x0, sum = 3
4349 20:12:33.487585 11, 0x0, sum = 4
4350 20:12:33.487670 best_step = 9
4351 20:12:33.487737
4352 20:12:33.487798 ==
4353 20:12:33.490893 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 20:12:33.497473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 20:12:33.497557 ==
4356 20:12:33.497624 RX Vref Scan: 0
4357 20:12:33.497685
4358 20:12:33.501050 RX Vref 0 -> 0, step: 1
4359 20:12:33.501133
4360 20:12:33.504406 RX Delay -179 -> 252, step: 8
4361 20:12:33.507578 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4362 20:12:33.514375 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4363 20:12:33.517627 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4364 20:12:33.520845 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4365 20:12:33.523900 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4366 20:12:33.527397 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4367 20:12:33.534371 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4368 20:12:33.537379 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4369 20:12:33.540730 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4370 20:12:33.543991 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4371 20:12:33.547570 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4372 20:12:33.554175 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4373 20:12:33.557392 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4374 20:12:33.560673 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4375 20:12:33.563858 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4376 20:12:33.570738 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4377 20:12:33.570826 ==
4378 20:12:33.573623 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 20:12:33.577036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 20:12:33.577135 ==
4381 20:12:33.577212 DQS Delay:
4382 20:12:33.580417 DQS0 = 0, DQS1 = 0
4383 20:12:33.580491 DQM Delay:
4384 20:12:33.583748 DQM0 = 47, DQM1 = 40
4385 20:12:33.583830 DQ Delay:
4386 20:12:33.587094 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4387 20:12:33.590624 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4388 20:12:33.593723 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4389 20:12:33.597052 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4390 20:12:33.597134
4391 20:12:33.597200
4392 20:12:33.603795 [DQSOSCAuto] RK1, (LSB)MR18= 0x632f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4393 20:12:33.607250 CH0 RK1: MR19=808, MR18=632F
4394 20:12:33.613783 CH0_RK1: MR19=0x808, MR18=0x632F, DQSOSC=391, MR23=63, INC=171, DEC=114
4395 20:12:33.617286 [RxdqsGatingPostProcess] freq 600
4396 20:12:33.623976 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 20:12:33.626839 Pre-setting of DQS Precalculation
4398 20:12:33.630306 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 20:12:33.630388 ==
4400 20:12:33.633760 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 20:12:33.636883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 20:12:33.636968 ==
4403 20:12:33.643718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 20:12:33.650371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4405 20:12:33.653489 [CA 0] Center 35 (5~66) winsize 62
4406 20:12:33.656809 [CA 1] Center 35 (4~66) winsize 63
4407 20:12:33.660189 [CA 2] Center 34 (4~65) winsize 62
4408 20:12:33.663189 [CA 3] Center 33 (3~64) winsize 62
4409 20:12:33.666863 [CA 4] Center 33 (3~64) winsize 62
4410 20:12:33.670438 [CA 5] Center 33 (3~64) winsize 62
4411 20:12:33.670521
4412 20:12:33.673231 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4413 20:12:33.673328
4414 20:12:33.676502 [CATrainingPosCal] consider 1 rank data
4415 20:12:33.680070 u2DelayCellTimex100 = 270/100 ps
4416 20:12:33.683381 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 20:12:33.686784 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4418 20:12:33.689993 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 20:12:33.693267 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 20:12:33.697077 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 20:12:33.703399 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 20:12:33.703486
4423 20:12:33.706877 CA PerBit enable=1, Macro0, CA PI delay=33
4424 20:12:33.706960
4425 20:12:33.710235 [CBTSetCACLKResult] CA Dly = 33
4426 20:12:33.710318 CS Dly: 4 (0~35)
4427 20:12:33.710383 ==
4428 20:12:33.713346 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 20:12:33.716416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 20:12:33.720123 ==
4431 20:12:33.723530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 20:12:33.729848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4433 20:12:33.733097 [CA 0] Center 35 (5~66) winsize 62
4434 20:12:33.736446 [CA 1] Center 35 (5~66) winsize 62
4435 20:12:33.739732 [CA 2] Center 34 (4~65) winsize 62
4436 20:12:33.743018 [CA 3] Center 34 (4~64) winsize 61
4437 20:12:33.746608 [CA 4] Center 34 (4~64) winsize 61
4438 20:12:33.749554 [CA 5] Center 33 (3~64) winsize 62
4439 20:12:33.749637
4440 20:12:33.753035 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4441 20:12:33.753118
4442 20:12:33.756286 [CATrainingPosCal] consider 2 rank data
4443 20:12:33.759712 u2DelayCellTimex100 = 270/100 ps
4444 20:12:33.762901 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 20:12:33.766322 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 20:12:33.769826 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 20:12:33.773038 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4448 20:12:33.779905 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4449 20:12:33.783132 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 20:12:33.783217
4451 20:12:33.786675 CA PerBit enable=1, Macro0, CA PI delay=33
4452 20:12:33.786759
4453 20:12:33.789575 [CBTSetCACLKResult] CA Dly = 33
4454 20:12:33.789660 CS Dly: 4 (0~36)
4455 20:12:33.789727
4456 20:12:33.793125 ----->DramcWriteLeveling(PI) begin...
4457 20:12:33.793212 ==
4458 20:12:33.796394 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 20:12:33.803006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 20:12:33.803092 ==
4461 20:12:33.806514 Write leveling (Byte 0): 30 => 30
4462 20:12:33.809483 Write leveling (Byte 1): 30 => 30
4463 20:12:33.809568 DramcWriteLeveling(PI) end<-----
4464 20:12:33.809634
4465 20:12:33.813236 ==
4466 20:12:33.813320 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 20:12:33.819658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 20:12:33.819743 ==
4469 20:12:33.822797 [Gating] SW mode calibration
4470 20:12:33.829586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 20:12:33.832770 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 20:12:33.839232 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 20:12:33.842727 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 20:12:33.845976 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4475 20:12:33.853103 0 9 12 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (1 1)
4476 20:12:33.856174 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 20:12:33.859262 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 20:12:33.865880 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 20:12:33.869116 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 20:12:33.872637 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 20:12:33.879091 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 20:12:33.882727 0 10 8 | B1->B0 | 2828 2a2a | 1 0 | (1 1) (0 0)
4483 20:12:33.885870 0 10 12 | B1->B0 | 3a39 3e3e | 1 0 | (0 0) (0 0)
4484 20:12:33.892457 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 20:12:33.895788 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 20:12:33.898974 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 20:12:33.905835 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 20:12:33.908760 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 20:12:33.912300 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 20:12:33.919047 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 20:12:33.922099 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4492 20:12:33.925373 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 20:12:33.932840 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 20:12:33.935425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 20:12:33.938740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 20:12:33.942232 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 20:12:33.948974 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 20:12:33.951962 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 20:12:33.955399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 20:12:33.961898 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 20:12:33.965389 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 20:12:33.968745 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 20:12:33.975490 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 20:12:33.978626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 20:12:33.981780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 20:12:33.988621 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4507 20:12:33.991685 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4508 20:12:33.995301 Total UI for P1: 0, mck2ui 16
4509 20:12:33.998264 best dqsien dly found for B1: ( 0, 13, 8)
4510 20:12:34.001807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 20:12:34.005281 Total UI for P1: 0, mck2ui 16
4512 20:12:34.008625 best dqsien dly found for B0: ( 0, 13, 12)
4513 20:12:34.011418 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4514 20:12:34.014883 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4515 20:12:34.018356
4516 20:12:34.021526 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4517 20:12:34.025000 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4518 20:12:34.028342 [Gating] SW calibration Done
4519 20:12:34.028426 ==
4520 20:12:34.031682 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 20:12:34.034783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 20:12:34.034868 ==
4523 20:12:34.034934 RX Vref Scan: 0
4524 20:12:34.034997
4525 20:12:34.038673 RX Vref 0 -> 0, step: 1
4526 20:12:34.038756
4527 20:12:34.041800 RX Delay -230 -> 252, step: 16
4528 20:12:34.044964 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4529 20:12:34.048275 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4530 20:12:34.055137 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4531 20:12:34.058440 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4532 20:12:34.061276 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4533 20:12:34.064562 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4534 20:12:34.071315 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4535 20:12:34.074651 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4536 20:12:34.078216 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4537 20:12:34.081384 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4538 20:12:34.084637 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4539 20:12:34.091458 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4540 20:12:34.094659 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4541 20:12:34.098085 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4542 20:12:34.101360 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4543 20:12:34.108059 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4544 20:12:34.108144 ==
4545 20:12:34.111272 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 20:12:34.114582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 20:12:34.114667 ==
4548 20:12:34.114734 DQS Delay:
4549 20:12:34.117916 DQS0 = 0, DQS1 = 0
4550 20:12:34.118005 DQM Delay:
4551 20:12:34.121353 DQM0 = 50, DQM1 = 41
4552 20:12:34.121437 DQ Delay:
4553 20:12:34.124631 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4554 20:12:34.128108 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4555 20:12:34.131527 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4556 20:12:34.134245 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4557 20:12:34.134329
4558 20:12:34.134394
4559 20:12:34.134455 ==
4560 20:12:34.137704 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 20:12:34.140885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 20:12:34.144650 ==
4563 20:12:34.144734
4564 20:12:34.144801
4565 20:12:34.144863 TX Vref Scan disable
4566 20:12:34.147710 == TX Byte 0 ==
4567 20:12:34.150944 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 20:12:34.154318 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 20:12:34.157726 == TX Byte 1 ==
4570 20:12:34.160924 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 20:12:34.164066 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 20:12:34.167499 ==
4573 20:12:34.170717 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 20:12:34.174217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 20:12:34.174301 ==
4576 20:12:34.174368
4577 20:12:34.174429
4578 20:12:34.177628 TX Vref Scan disable
4579 20:12:34.177711 == TX Byte 0 ==
4580 20:12:34.184649 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4581 20:12:34.187706 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4582 20:12:34.187791 == TX Byte 1 ==
4583 20:12:34.193919 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4584 20:12:34.197517 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4585 20:12:34.197601
4586 20:12:34.197667 [DATLAT]
4587 20:12:34.200852 Freq=600, CH1 RK0
4588 20:12:34.200936
4589 20:12:34.201003 DATLAT Default: 0x9
4590 20:12:34.203937 0, 0xFFFF, sum = 0
4591 20:12:34.204023 1, 0xFFFF, sum = 0
4592 20:12:34.207462 2, 0xFFFF, sum = 0
4593 20:12:34.207547 3, 0xFFFF, sum = 0
4594 20:12:34.210666 4, 0xFFFF, sum = 0
4595 20:12:34.213781 5, 0xFFFF, sum = 0
4596 20:12:34.213866 6, 0xFFFF, sum = 0
4597 20:12:34.217240 7, 0xFFFF, sum = 0
4598 20:12:34.217325 8, 0x0, sum = 1
4599 20:12:34.217392 9, 0x0, sum = 2
4600 20:12:34.220982 10, 0x0, sum = 3
4601 20:12:34.221067 11, 0x0, sum = 4
4602 20:12:34.223976 best_step = 9
4603 20:12:34.224060
4604 20:12:34.224126 ==
4605 20:12:34.227479 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 20:12:34.230723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 20:12:34.230807 ==
4608 20:12:34.234091 RX Vref Scan: 1
4609 20:12:34.234174
4610 20:12:34.234241 RX Vref 0 -> 0, step: 1
4611 20:12:34.234302
4612 20:12:34.237483 RX Delay -179 -> 252, step: 8
4613 20:12:34.237567
4614 20:12:34.240472 Set Vref, RX VrefLevel [Byte0]: 52
4615 20:12:34.243758 [Byte1]: 53
4616 20:12:34.247724
4617 20:12:34.247808 Final RX Vref Byte 0 = 52 to rank0
4618 20:12:34.251035 Final RX Vref Byte 1 = 53 to rank0
4619 20:12:34.254558 Final RX Vref Byte 0 = 52 to rank1
4620 20:12:34.257852 Final RX Vref Byte 1 = 53 to rank1==
4621 20:12:34.261136 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 20:12:34.267878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 20:12:34.267962 ==
4624 20:12:34.268029 DQS Delay:
4625 20:12:34.271052 DQS0 = 0, DQS1 = 0
4626 20:12:34.271136 DQM Delay:
4627 20:12:34.271201 DQM0 = 49, DQM1 = 41
4628 20:12:34.274595 DQ Delay:
4629 20:12:34.277615 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4630 20:12:34.281066 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4631 20:12:34.284750 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4632 20:12:34.287992 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4633 20:12:34.288075
4634 20:12:34.288142
4635 20:12:34.294117 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4636 20:12:34.297380 CH1 RK0: MR19=808, MR18=4C73
4637 20:12:34.304298 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4638 20:12:34.304383
4639 20:12:34.307333 ----->DramcWriteLeveling(PI) begin...
4640 20:12:34.307419 ==
4641 20:12:34.311132 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 20:12:34.314175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 20:12:34.314260 ==
4644 20:12:34.317301 Write leveling (Byte 0): 30 => 30
4645 20:12:34.320916 Write leveling (Byte 1): 29 => 29
4646 20:12:34.324256 DramcWriteLeveling(PI) end<-----
4647 20:12:34.324340
4648 20:12:34.324406 ==
4649 20:12:34.327403 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 20:12:34.330553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 20:12:34.330638 ==
4652 20:12:34.333798 [Gating] SW mode calibration
4653 20:12:34.340750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 20:12:34.347061 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 20:12:34.350377 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 20:12:34.357116 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 20:12:34.360514 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4658 20:12:34.363801 0 9 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 0)
4659 20:12:34.370743 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4660 20:12:34.373661 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 20:12:34.377282 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 20:12:34.380681 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 20:12:34.387431 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 20:12:34.390884 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 20:12:34.393814 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4666 20:12:34.400444 0 10 12 | B1->B0 | 4040 3030 | 0 0 | (0 0) (0 0)
4667 20:12:34.404064 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 20:12:34.407325 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 20:12:34.413810 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 20:12:34.417411 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 20:12:34.420613 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 20:12:34.427524 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 20:12:34.430520 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4674 20:12:34.434052 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4675 20:12:34.440898 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 20:12:34.443711 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 20:12:34.447007 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 20:12:34.453752 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 20:12:34.456974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 20:12:34.460597 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 20:12:34.467428 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 20:12:34.470330 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 20:12:34.473732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 20:12:34.480253 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 20:12:34.483533 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 20:12:34.486935 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 20:12:34.493765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 20:12:34.496710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 20:12:34.500192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4690 20:12:34.507067 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4691 20:12:34.510396 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 20:12:34.513643 Total UI for P1: 0, mck2ui 16
4693 20:12:34.516986 best dqsien dly found for B0: ( 0, 13, 12)
4694 20:12:34.520256 Total UI for P1: 0, mck2ui 16
4695 20:12:34.523430 best dqsien dly found for B1: ( 0, 13, 10)
4696 20:12:34.526905 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4697 20:12:34.530082 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4698 20:12:34.530153
4699 20:12:34.533598 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4700 20:12:34.536909 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 20:12:34.540140 [Gating] SW calibration Done
4702 20:12:34.540235 ==
4703 20:12:34.543630 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 20:12:34.546805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 20:12:34.546950 ==
4706 20:12:34.550041 RX Vref Scan: 0
4707 20:12:34.550147
4708 20:12:34.553178 RX Vref 0 -> 0, step: 1
4709 20:12:34.553289
4710 20:12:34.553382 RX Delay -230 -> 252, step: 16
4711 20:12:34.559750 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4712 20:12:34.563117 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4713 20:12:34.566508 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4714 20:12:34.570077 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4715 20:12:34.576765 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4716 20:12:34.580336 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4717 20:12:34.583118 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4718 20:12:34.586678 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4719 20:12:34.589723 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4720 20:12:34.596317 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4721 20:12:34.599933 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4722 20:12:34.602907 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4723 20:12:34.606226 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4724 20:12:34.613027 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4725 20:12:34.616375 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4726 20:12:34.619682 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4727 20:12:34.619777 ==
4728 20:12:34.623064 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 20:12:34.626354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 20:12:34.629513 ==
4731 20:12:34.629610 DQS Delay:
4732 20:12:34.629698 DQS0 = 0, DQS1 = 0
4733 20:12:34.633201 DQM Delay:
4734 20:12:34.633299 DQM0 = 52, DQM1 = 46
4735 20:12:34.636214 DQ Delay:
4736 20:12:34.636290 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4737 20:12:34.639376 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4738 20:12:34.642692 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4739 20:12:34.646746 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4740 20:12:34.646820
4741 20:12:34.649571
4742 20:12:34.649643 ==
4743 20:12:34.652751 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 20:12:34.656061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 20:12:34.656162 ==
4746 20:12:34.656255
4747 20:12:34.656343
4748 20:12:34.659323 TX Vref Scan disable
4749 20:12:34.659393 == TX Byte 0 ==
4750 20:12:34.665887 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4751 20:12:34.669512 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4752 20:12:34.669615 == TX Byte 1 ==
4753 20:12:34.676007 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4754 20:12:34.679561 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4755 20:12:34.679663 ==
4756 20:12:34.682629 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 20:12:34.686336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 20:12:34.686412 ==
4759 20:12:34.686475
4760 20:12:34.686540
4761 20:12:34.689565 TX Vref Scan disable
4762 20:12:34.692679 == TX Byte 0 ==
4763 20:12:34.696430 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4764 20:12:34.699442 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4765 20:12:34.702832 == TX Byte 1 ==
4766 20:12:34.706056 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4767 20:12:34.709128 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4768 20:12:34.709203
4769 20:12:34.712583 [DATLAT]
4770 20:12:34.712654 Freq=600, CH1 RK1
4771 20:12:34.712715
4772 20:12:34.716197 DATLAT Default: 0x9
4773 20:12:34.716284 0, 0xFFFF, sum = 0
4774 20:12:34.719311 1, 0xFFFF, sum = 0
4775 20:12:34.719383 2, 0xFFFF, sum = 0
4776 20:12:34.722884 3, 0xFFFF, sum = 0
4777 20:12:34.722982 4, 0xFFFF, sum = 0
4778 20:12:34.726245 5, 0xFFFF, sum = 0
4779 20:12:34.726319 6, 0xFFFF, sum = 0
4780 20:12:34.729341 7, 0xFFFF, sum = 0
4781 20:12:34.729414 8, 0x0, sum = 1
4782 20:12:34.732678 9, 0x0, sum = 2
4783 20:12:34.732751 10, 0x0, sum = 3
4784 20:12:34.736191 11, 0x0, sum = 4
4785 20:12:34.736262 best_step = 9
4786 20:12:34.736322
4787 20:12:34.736378 ==
4788 20:12:34.739427 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 20:12:34.742599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 20:12:34.746115 ==
4791 20:12:34.746198 RX Vref Scan: 0
4792 20:12:34.746263
4793 20:12:34.749438 RX Vref 0 -> 0, step: 1
4794 20:12:34.749521
4795 20:12:34.752712 RX Delay -163 -> 252, step: 8
4796 20:12:34.755825 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4797 20:12:34.759096 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4798 20:12:34.766026 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4799 20:12:34.769154 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4800 20:12:34.772446 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4801 20:12:34.775597 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4802 20:12:34.778990 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4803 20:12:34.785643 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4804 20:12:34.788895 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4805 20:12:34.792385 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4806 20:12:34.795869 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4807 20:12:34.799022 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4808 20:12:34.805337 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4809 20:12:34.809100 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4810 20:12:34.812441 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4811 20:12:34.815337 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4812 20:12:34.815419 ==
4813 20:12:34.818871 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 20:12:34.825592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 20:12:34.825692 ==
4816 20:12:34.825771 DQS Delay:
4817 20:12:34.828560 DQS0 = 0, DQS1 = 0
4818 20:12:34.828643 DQM Delay:
4819 20:12:34.832400 DQM0 = 50, DQM1 = 44
4820 20:12:34.832482 DQ Delay:
4821 20:12:34.835454 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4822 20:12:34.838720 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4823 20:12:34.842186 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4824 20:12:34.845569 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4825 20:12:34.845652
4826 20:12:34.845716
4827 20:12:34.852108 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4828 20:12:34.855288 CH1 RK1: MR19=808, MR18=5C22
4829 20:12:34.862351 CH1_RK1: MR19=0x808, MR18=0x5C22, DQSOSC=392, MR23=63, INC=170, DEC=113
4830 20:12:34.865548 [RxdqsGatingPostProcess] freq 600
4831 20:12:34.868558 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 20:12:34.871984 Pre-setting of DQS Precalculation
4833 20:12:34.878354 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 20:12:34.885218 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 20:12:34.891969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 20:12:34.892052
4837 20:12:34.892116
4838 20:12:34.894940 [Calibration Summary] 1200 Mbps
4839 20:12:34.895022 CH 0, Rank 0
4840 20:12:34.898321 SW Impedance : PASS
4841 20:12:34.901683 DUTY Scan : NO K
4842 20:12:34.901765 ZQ Calibration : PASS
4843 20:12:34.905100 Jitter Meter : NO K
4844 20:12:34.908569 CBT Training : PASS
4845 20:12:34.908651 Write leveling : PASS
4846 20:12:34.911642 RX DQS gating : PASS
4847 20:12:34.915115 RX DQ/DQS(RDDQC) : PASS
4848 20:12:34.915197 TX DQ/DQS : PASS
4849 20:12:34.918460 RX DATLAT : PASS
4850 20:12:34.921937 RX DQ/DQS(Engine): PASS
4851 20:12:34.922039 TX OE : NO K
4852 20:12:34.925384 All Pass.
4853 20:12:34.925467
4854 20:12:34.925532 CH 0, Rank 1
4855 20:12:34.928334 SW Impedance : PASS
4856 20:12:34.928416 DUTY Scan : NO K
4857 20:12:34.931491 ZQ Calibration : PASS
4858 20:12:34.935187 Jitter Meter : NO K
4859 20:12:34.935270 CBT Training : PASS
4860 20:12:34.938098 Write leveling : PASS
4861 20:12:34.941831 RX DQS gating : PASS
4862 20:12:34.941913 RX DQ/DQS(RDDQC) : PASS
4863 20:12:34.945138 TX DQ/DQS : PASS
4864 20:12:34.945220 RX DATLAT : PASS
4865 20:12:34.948275 RX DQ/DQS(Engine): PASS
4866 20:12:34.951844 TX OE : NO K
4867 20:12:34.951926 All Pass.
4868 20:12:34.951991
4869 20:12:34.952050 CH 1, Rank 0
4870 20:12:34.954783 SW Impedance : PASS
4871 20:12:34.958265 DUTY Scan : NO K
4872 20:12:34.958347 ZQ Calibration : PASS
4873 20:12:34.961488 Jitter Meter : NO K
4874 20:12:34.964900 CBT Training : PASS
4875 20:12:34.964982 Write leveling : PASS
4876 20:12:34.968355 RX DQS gating : PASS
4877 20:12:34.971518 RX DQ/DQS(RDDQC) : PASS
4878 20:12:34.971600 TX DQ/DQS : PASS
4879 20:12:34.975084 RX DATLAT : PASS
4880 20:12:34.978272 RX DQ/DQS(Engine): PASS
4881 20:12:34.978355 TX OE : NO K
4882 20:12:34.981302 All Pass.
4883 20:12:34.981383
4884 20:12:34.981447 CH 1, Rank 1
4885 20:12:34.984931 SW Impedance : PASS
4886 20:12:34.985013 DUTY Scan : NO K
4887 20:12:34.988108 ZQ Calibration : PASS
4888 20:12:34.991488 Jitter Meter : NO K
4889 20:12:34.991570 CBT Training : PASS
4890 20:12:34.994824 Write leveling : PASS
4891 20:12:34.994909 RX DQS gating : PASS
4892 20:12:34.998249 RX DQ/DQS(RDDQC) : PASS
4893 20:12:35.001382 TX DQ/DQS : PASS
4894 20:12:35.001464 RX DATLAT : PASS
4895 20:12:35.004927 RX DQ/DQS(Engine): PASS
4896 20:12:35.007910 TX OE : NO K
4897 20:12:35.007992 All Pass.
4898 20:12:35.008057
4899 20:12:35.011282 DramC Write-DBI off
4900 20:12:35.011365 PER_BANK_REFRESH: Hybrid Mode
4901 20:12:35.014879 TX_TRACKING: ON
4902 20:12:35.024765 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 20:12:35.027997 [FAST_K] Save calibration result to emmc
4904 20:12:35.031066 dramc_set_vcore_voltage set vcore to 662500
4905 20:12:35.031148 Read voltage for 933, 3
4906 20:12:35.034374 Vio18 = 0
4907 20:12:35.034455 Vcore = 662500
4908 20:12:35.034524 Vdram = 0
4909 20:12:35.037771 Vddq = 0
4910 20:12:35.037853 Vmddr = 0
4911 20:12:35.040998 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 20:12:35.048157 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 20:12:35.051229 MEM_TYPE=3, freq_sel=17
4914 20:12:35.054623 sv_algorithm_assistance_LP4_1600
4915 20:12:35.057889 ============ PULL DRAM RESETB DOWN ============
4916 20:12:35.060947 ========== PULL DRAM RESETB DOWN end =========
4917 20:12:35.067581 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 20:12:35.071226 ===================================
4919 20:12:35.071308 LPDDR4 DRAM CONFIGURATION
4920 20:12:35.074365 ===================================
4921 20:12:35.077625 EX_ROW_EN[0] = 0x0
4922 20:12:35.077706 EX_ROW_EN[1] = 0x0
4923 20:12:35.081563 LP4Y_EN = 0x0
4924 20:12:35.081646 WORK_FSP = 0x0
4925 20:12:35.084349 WL = 0x3
4926 20:12:35.084430 RL = 0x3
4927 20:12:35.087815 BL = 0x2
4928 20:12:35.087897 RPST = 0x0
4929 20:12:35.091122 RD_PRE = 0x0
4930 20:12:35.094647 WR_PRE = 0x1
4931 20:12:35.094729 WR_PST = 0x0
4932 20:12:35.097677 DBI_WR = 0x0
4933 20:12:35.097758 DBI_RD = 0x0
4934 20:12:35.100877 OTF = 0x1
4935 20:12:35.104274 ===================================
4936 20:12:35.108128 ===================================
4937 20:12:35.108211 ANA top config
4938 20:12:35.111141 ===================================
4939 20:12:35.114128 DLL_ASYNC_EN = 0
4940 20:12:35.117792 ALL_SLAVE_EN = 1
4941 20:12:35.117874 NEW_RANK_MODE = 1
4942 20:12:35.120743 DLL_IDLE_MODE = 1
4943 20:12:35.124067 LP45_APHY_COMB_EN = 1
4944 20:12:35.127443 TX_ODT_DIS = 1
4945 20:12:35.127526 NEW_8X_MODE = 1
4946 20:12:35.130929 ===================================
4947 20:12:35.134318 ===================================
4948 20:12:35.137285 data_rate = 1866
4949 20:12:35.140877 CKR = 1
4950 20:12:35.144326 DQ_P2S_RATIO = 8
4951 20:12:35.147283 ===================================
4952 20:12:35.150866 CA_P2S_RATIO = 8
4953 20:12:35.154111 DQ_CA_OPEN = 0
4954 20:12:35.154188 DQ_SEMI_OPEN = 0
4955 20:12:35.157751 CA_SEMI_OPEN = 0
4956 20:12:35.160778 CA_FULL_RATE = 0
4957 20:12:35.164255 DQ_CKDIV4_EN = 1
4958 20:12:35.167620 CA_CKDIV4_EN = 1
4959 20:12:35.170777 CA_PREDIV_EN = 0
4960 20:12:35.170876 PH8_DLY = 0
4961 20:12:35.174218 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 20:12:35.177592 DQ_AAMCK_DIV = 4
4963 20:12:35.180910 CA_AAMCK_DIV = 4
4964 20:12:35.184184 CA_ADMCK_DIV = 4
4965 20:12:35.187753 DQ_TRACK_CA_EN = 0
4966 20:12:35.187837 CA_PICK = 933
4967 20:12:35.190767 CA_MCKIO = 933
4968 20:12:35.194128 MCKIO_SEMI = 0
4969 20:12:35.197605 PLL_FREQ = 3732
4970 20:12:35.200579 DQ_UI_PI_RATIO = 32
4971 20:12:35.204147 CA_UI_PI_RATIO = 0
4972 20:12:35.207722 ===================================
4973 20:12:35.210777 ===================================
4974 20:12:35.210860 memory_type:LPDDR4
4975 20:12:35.214268 GP_NUM : 10
4976 20:12:35.217396 SRAM_EN : 1
4977 20:12:35.217479 MD32_EN : 0
4978 20:12:35.220814 ===================================
4979 20:12:35.224175 [ANA_INIT] >>>>>>>>>>>>>>
4980 20:12:35.227748 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 20:12:35.230795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 20:12:35.234092 ===================================
4983 20:12:35.237369 data_rate = 1866,PCW = 0X8f00
4984 20:12:35.240532 ===================================
4985 20:12:35.243881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 20:12:35.247612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 20:12:35.253986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 20:12:35.257330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 20:12:35.263602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 20:12:35.267272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 20:12:35.267360 [ANA_INIT] flow start
4992 20:12:35.270228 [ANA_INIT] PLL >>>>>>>>
4993 20:12:35.273894 [ANA_INIT] PLL <<<<<<<<
4994 20:12:35.274018 [ANA_INIT] MIDPI >>>>>>>>
4995 20:12:35.277231 [ANA_INIT] MIDPI <<<<<<<<
4996 20:12:35.280366 [ANA_INIT] DLL >>>>>>>>
4997 20:12:35.280450 [ANA_INIT] flow end
4998 20:12:35.283632 ============ LP4 DIFF to SE enter ============
4999 20:12:35.290196 ============ LP4 DIFF to SE exit ============
5000 20:12:35.290281 [ANA_INIT] <<<<<<<<<<<<<
5001 20:12:35.293567 [Flow] Enable top DCM control >>>>>
5002 20:12:35.297018 [Flow] Enable top DCM control <<<<<
5003 20:12:35.300419 Enable DLL master slave shuffle
5004 20:12:35.306877 ==============================================================
5005 20:12:35.306959 Gating Mode config
5006 20:12:35.313549 ==============================================================
5007 20:12:35.317050 Config description:
5008 20:12:35.326647 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 20:12:35.333464 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 20:12:35.337159 SELPH_MODE 0: By rank 1: By Phase
5011 20:12:35.343498 ==============================================================
5012 20:12:35.346868 GAT_TRACK_EN = 1
5013 20:12:35.350086 RX_GATING_MODE = 2
5014 20:12:35.350162 RX_GATING_TRACK_MODE = 2
5015 20:12:35.353184 SELPH_MODE = 1
5016 20:12:35.356807 PICG_EARLY_EN = 1
5017 20:12:35.359913 VALID_LAT_VALUE = 1
5018 20:12:35.366623 ==============================================================
5019 20:12:35.369798 Enter into Gating configuration >>>>
5020 20:12:35.373227 Exit from Gating configuration <<<<
5021 20:12:35.376652 Enter into DVFS_PRE_config >>>>>
5022 20:12:35.386475 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 20:12:35.390052 Exit from DVFS_PRE_config <<<<<
5024 20:12:35.393381 Enter into PICG configuration >>>>
5025 20:12:35.396588 Exit from PICG configuration <<<<
5026 20:12:35.399591 [RX_INPUT] configuration >>>>>
5027 20:12:35.403145 [RX_INPUT] configuration <<<<<
5028 20:12:35.406250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 20:12:35.412946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 20:12:35.419540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 20:12:35.426226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 20:12:35.429531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 20:12:35.436197 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 20:12:35.439489 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 20:12:35.445812 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 20:12:35.449071 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 20:12:35.452673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 20:12:35.456020 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 20:12:35.462617 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 20:12:35.465910 ===================================
5041 20:12:35.469171 LPDDR4 DRAM CONFIGURATION
5042 20:12:35.472268 ===================================
5043 20:12:35.472348 EX_ROW_EN[0] = 0x0
5044 20:12:35.475821 EX_ROW_EN[1] = 0x0
5045 20:12:35.475897 LP4Y_EN = 0x0
5046 20:12:35.478833 WORK_FSP = 0x0
5047 20:12:35.478909 WL = 0x3
5048 20:12:35.482369 RL = 0x3
5049 20:12:35.482440 BL = 0x2
5050 20:12:35.485736 RPST = 0x0
5051 20:12:35.485840 RD_PRE = 0x0
5052 20:12:35.488989 WR_PRE = 0x1
5053 20:12:35.489064 WR_PST = 0x0
5054 20:12:35.492603 DBI_WR = 0x0
5055 20:12:35.492672 DBI_RD = 0x0
5056 20:12:35.495652 OTF = 0x1
5057 20:12:35.498982 ===================================
5058 20:12:35.502352 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 20:12:35.505455 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 20:12:35.512142 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 20:12:35.515613 ===================================
5062 20:12:35.515685 LPDDR4 DRAM CONFIGURATION
5063 20:12:35.518696 ===================================
5064 20:12:35.522070 EX_ROW_EN[0] = 0x10
5065 20:12:35.525692 EX_ROW_EN[1] = 0x0
5066 20:12:35.525766 LP4Y_EN = 0x0
5067 20:12:35.528831 WORK_FSP = 0x0
5068 20:12:35.528903 WL = 0x3
5069 20:12:35.532272 RL = 0x3
5070 20:12:35.532341 BL = 0x2
5071 20:12:35.535685 RPST = 0x0
5072 20:12:35.535754 RD_PRE = 0x0
5073 20:12:35.538836 WR_PRE = 0x1
5074 20:12:35.538908 WR_PST = 0x0
5075 20:12:35.542174 DBI_WR = 0x0
5076 20:12:35.542243 DBI_RD = 0x0
5077 20:12:35.545416 OTF = 0x1
5078 20:12:35.549051 ===================================
5079 20:12:35.555767 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 20:12:35.558826 nWR fixed to 30
5081 20:12:35.558902 [ModeRegInit_LP4] CH0 RK0
5082 20:12:35.562173 [ModeRegInit_LP4] CH0 RK1
5083 20:12:35.565626 [ModeRegInit_LP4] CH1 RK0
5084 20:12:35.568766 [ModeRegInit_LP4] CH1 RK1
5085 20:12:35.568856 match AC timing 9
5086 20:12:35.575685 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 20:12:35.578613 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 20:12:35.582193 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 20:12:35.588922 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 20:12:35.592049 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 20:12:35.592121 ==
5092 20:12:35.595590 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 20:12:35.598909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 20:12:35.598980 ==
5095 20:12:35.605434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 20:12:35.612070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5097 20:12:35.615533 [CA 0] Center 37 (7~68) winsize 62
5098 20:12:35.618627 [CA 1] Center 38 (8~69) winsize 62
5099 20:12:35.622056 [CA 2] Center 35 (5~66) winsize 62
5100 20:12:35.625629 [CA 3] Center 35 (5~65) winsize 61
5101 20:12:35.628645 [CA 4] Center 34 (4~65) winsize 62
5102 20:12:35.631723 [CA 5] Center 33 (3~64) winsize 62
5103 20:12:35.631797
5104 20:12:35.635202 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5105 20:12:35.635274
5106 20:12:35.638425 [CATrainingPosCal] consider 1 rank data
5107 20:12:35.641838 u2DelayCellTimex100 = 270/100 ps
5108 20:12:35.645492 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 20:12:35.648411 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5110 20:12:35.651794 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5111 20:12:35.655460 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5112 20:12:35.658361 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5113 20:12:35.661775 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5114 20:12:35.661844
5115 20:12:35.665330 CA PerBit enable=1, Macro0, CA PI delay=33
5116 20:12:35.668910
5117 20:12:35.668980 [CBTSetCACLKResult] CA Dly = 33
5118 20:12:35.672004 CS Dly: 7 (0~38)
5119 20:12:35.672077 ==
5120 20:12:35.675489 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 20:12:35.678595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 20:12:35.678669 ==
5123 20:12:35.685326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 20:12:35.692221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5125 20:12:35.695525 [CA 0] Center 38 (8~69) winsize 62
5126 20:12:35.699021 [CA 1] Center 38 (8~69) winsize 62
5127 20:12:35.701884 [CA 2] Center 35 (5~66) winsize 62
5128 20:12:35.705171 [CA 3] Center 35 (5~66) winsize 62
5129 20:12:35.709048 [CA 4] Center 34 (4~65) winsize 62
5130 20:12:35.711947 [CA 5] Center 34 (4~65) winsize 62
5131 20:12:35.712020
5132 20:12:35.715341 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5133 20:12:35.715411
5134 20:12:35.718556 [CATrainingPosCal] consider 2 rank data
5135 20:12:35.722018 u2DelayCellTimex100 = 270/100 ps
5136 20:12:35.725674 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5137 20:12:35.728455 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5138 20:12:35.731957 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5139 20:12:35.735061 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5140 20:12:35.738653 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5141 20:12:35.741492 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5142 20:12:35.741565
5143 20:12:35.748286 CA PerBit enable=1, Macro0, CA PI delay=34
5144 20:12:35.748362
5145 20:12:35.748425 [CBTSetCACLKResult] CA Dly = 34
5146 20:12:35.751753 CS Dly: 7 (0~39)
5147 20:12:35.751824
5148 20:12:35.755057 ----->DramcWriteLeveling(PI) begin...
5149 20:12:35.755133 ==
5150 20:12:35.758271 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 20:12:35.761496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 20:12:35.761571 ==
5153 20:12:35.765037 Write leveling (Byte 0): 32 => 32
5154 20:12:35.768250 Write leveling (Byte 1): 28 => 28
5155 20:12:35.771826 DramcWriteLeveling(PI) end<-----
5156 20:12:35.771899
5157 20:12:35.771960 ==
5158 20:12:35.774940 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 20:12:35.778175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 20:12:35.781718 ==
5161 20:12:35.781796 [Gating] SW mode calibration
5162 20:12:35.791592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 20:12:35.794890 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 20:12:35.798143 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5165 20:12:35.804834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 20:12:35.808349 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 20:12:35.811439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 20:12:35.818247 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 20:12:35.821917 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5170 20:12:35.824820 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5171 20:12:35.831585 0 14 28 | B1->B0 | 3232 2323 | 0 0 | (0 0) (1 0)
5172 20:12:35.834955 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5173 20:12:35.838519 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 20:12:35.844639 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 20:12:35.847852 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 20:12:35.851125 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 20:12:35.858120 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 20:12:35.861587 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5179 20:12:35.864919 0 15 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
5180 20:12:35.871013 1 0 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5181 20:12:35.874418 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 20:12:35.877635 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 20:12:35.884705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 20:12:35.887741 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 20:12:35.891436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 20:12:35.897721 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5187 20:12:35.900916 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5188 20:12:35.904150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5189 20:12:35.910827 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 20:12:35.914070 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 20:12:35.917739 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 20:12:35.920792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 20:12:35.927648 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 20:12:35.931086 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 20:12:35.934316 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 20:12:35.940881 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 20:12:35.944256 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 20:12:35.947739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 20:12:35.954346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 20:12:35.957690 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 20:12:35.961118 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 20:12:35.967347 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5203 20:12:35.970663 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5204 20:12:35.974216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5205 20:12:35.977320 Total UI for P1: 0, mck2ui 16
5206 20:12:35.980627 best dqsien dly found for B0: ( 1, 2, 26)
5207 20:12:35.987095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 20:12:35.987180 Total UI for P1: 0, mck2ui 16
5209 20:12:35.994244 best dqsien dly found for B1: ( 1, 2, 30)
5210 20:12:35.997423 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5211 20:12:36.000908 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5212 20:12:36.000981
5213 20:12:36.004277 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5214 20:12:36.007495 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5215 20:12:36.010500 [Gating] SW calibration Done
5216 20:12:36.010577 ==
5217 20:12:36.014049 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 20:12:36.017430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 20:12:36.017531 ==
5220 20:12:36.021006 RX Vref Scan: 0
5221 20:12:36.021090
5222 20:12:36.021155 RX Vref 0 -> 0, step: 1
5223 20:12:36.021216
5224 20:12:36.023844 RX Delay -80 -> 252, step: 8
5225 20:12:36.027415 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5226 20:12:36.034100 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5227 20:12:36.037189 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5228 20:12:36.040626 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5229 20:12:36.043746 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5230 20:12:36.047231 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5231 20:12:36.053919 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5232 20:12:36.057191 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5233 20:12:36.060185 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5234 20:12:36.063584 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5235 20:12:36.066819 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5236 20:12:36.070571 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5237 20:12:36.077014 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5238 20:12:36.080483 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5239 20:12:36.083910 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5240 20:12:36.086851 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5241 20:12:36.086983 ==
5242 20:12:36.090429 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 20:12:36.093741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 20:12:36.093826 ==
5245 20:12:36.097200 DQS Delay:
5246 20:12:36.097284 DQS0 = 0, DQS1 = 0
5247 20:12:36.100429 DQM Delay:
5248 20:12:36.100512 DQM0 = 105, DQM1 = 90
5249 20:12:36.100579 DQ Delay:
5250 20:12:36.103875 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5251 20:12:36.107103 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5252 20:12:36.110704 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5253 20:12:36.117052 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5254 20:12:36.117140
5255 20:12:36.117205
5256 20:12:36.117266 ==
5257 20:12:36.120450 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 20:12:36.123511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 20:12:36.123595 ==
5260 20:12:36.123662
5261 20:12:36.123724
5262 20:12:36.126825 TX Vref Scan disable
5263 20:12:36.126909 == TX Byte 0 ==
5264 20:12:36.133471 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5265 20:12:36.137038 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5266 20:12:36.137122 == TX Byte 1 ==
5267 20:12:36.143491 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5268 20:12:36.147095 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5269 20:12:36.147179 ==
5270 20:12:36.150263 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 20:12:36.153782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 20:12:36.153867 ==
5273 20:12:36.153934
5274 20:12:36.154035
5275 20:12:36.157006 TX Vref Scan disable
5276 20:12:36.160375 == TX Byte 0 ==
5277 20:12:36.163714 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 20:12:36.167106 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 20:12:36.170127 == TX Byte 1 ==
5280 20:12:36.173791 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5281 20:12:36.176915 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5282 20:12:36.177000
5283 20:12:36.180067 [DATLAT]
5284 20:12:36.180151 Freq=933, CH0 RK0
5285 20:12:36.180218
5286 20:12:36.183580 DATLAT Default: 0xd
5287 20:12:36.183664 0, 0xFFFF, sum = 0
5288 20:12:36.186880 1, 0xFFFF, sum = 0
5289 20:12:36.186970 2, 0xFFFF, sum = 0
5290 20:12:36.190132 3, 0xFFFF, sum = 0
5291 20:12:36.190217 4, 0xFFFF, sum = 0
5292 20:12:36.193373 5, 0xFFFF, sum = 0
5293 20:12:36.193458 6, 0xFFFF, sum = 0
5294 20:12:36.197017 7, 0xFFFF, sum = 0
5295 20:12:36.197102 8, 0xFFFF, sum = 0
5296 20:12:36.200126 9, 0xFFFF, sum = 0
5297 20:12:36.200210 10, 0x0, sum = 1
5298 20:12:36.203397 11, 0x0, sum = 2
5299 20:12:36.203482 12, 0x0, sum = 3
5300 20:12:36.206616 13, 0x0, sum = 4
5301 20:12:36.206701 best_step = 11
5302 20:12:36.206767
5303 20:12:36.206828 ==
5304 20:12:36.210456 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 20:12:36.216860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 20:12:36.216945 ==
5307 20:12:36.217011 RX Vref Scan: 1
5308 20:12:36.217073
5309 20:12:36.220121 RX Vref 0 -> 0, step: 1
5310 20:12:36.220205
5311 20:12:36.223320 RX Delay -53 -> 252, step: 4
5312 20:12:36.223404
5313 20:12:36.226594 Set Vref, RX VrefLevel [Byte0]: 56
5314 20:12:36.230312 [Byte1]: 50
5315 20:12:36.230396
5316 20:12:36.233244 Final RX Vref Byte 0 = 56 to rank0
5317 20:12:36.236528 Final RX Vref Byte 1 = 50 to rank0
5318 20:12:36.239893 Final RX Vref Byte 0 = 56 to rank1
5319 20:12:36.243122 Final RX Vref Byte 1 = 50 to rank1==
5320 20:12:36.246442 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 20:12:36.250066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 20:12:36.250150 ==
5323 20:12:36.253186 DQS Delay:
5324 20:12:36.253270 DQS0 = 0, DQS1 = 0
5325 20:12:36.253335 DQM Delay:
5326 20:12:36.256769 DQM0 = 107, DQM1 = 91
5327 20:12:36.256852 DQ Delay:
5328 20:12:36.259765 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5329 20:12:36.263335 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5330 20:12:36.266502 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5331 20:12:36.270310 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5332 20:12:36.270394
5333 20:12:36.273535
5334 20:12:36.279863 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5335 20:12:36.282996 CH0 RK0: MR19=505, MR18=211D
5336 20:12:36.289867 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5337 20:12:36.289975
5338 20:12:36.293014 ----->DramcWriteLeveling(PI) begin...
5339 20:12:36.293099 ==
5340 20:12:36.296320 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 20:12:36.299876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 20:12:36.299961 ==
5343 20:12:36.302935 Write leveling (Byte 0): 31 => 31
5344 20:12:36.306179 Write leveling (Byte 1): 30 => 30
5345 20:12:36.309644 DramcWriteLeveling(PI) end<-----
5346 20:12:36.309728
5347 20:12:36.309793 ==
5348 20:12:36.313324 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 20:12:36.316320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 20:12:36.316404 ==
5351 20:12:36.319747 [Gating] SW mode calibration
5352 20:12:36.326127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 20:12:36.332964 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 20:12:36.336288 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 20:12:36.339493 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 20:12:36.346145 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 20:12:36.349581 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 20:12:36.352879 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 20:12:36.359585 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 20:12:36.362631 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5361 20:12:36.366107 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5362 20:12:36.372497 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 20:12:36.375907 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 20:12:36.379404 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 20:12:36.386406 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 20:12:36.389218 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 20:12:36.392678 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 20:12:36.399318 0 15 24 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
5369 20:12:36.402766 0 15 28 | B1->B0 | 3a3a 3e3e | 0 0 | (1 1) (1 1)
5370 20:12:36.405919 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 20:12:36.412877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 20:12:36.415974 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 20:12:36.419051 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 20:12:36.426198 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 20:12:36.429401 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 20:12:36.432353 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5377 20:12:36.438969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 20:12:36.442543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 20:12:36.445833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 20:12:36.448952 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 20:12:36.455793 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 20:12:36.459111 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 20:12:36.462415 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 20:12:36.468787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 20:12:36.472199 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 20:12:36.475903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 20:12:36.482380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 20:12:36.485614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 20:12:36.488769 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 20:12:36.495645 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 20:12:36.498803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 20:12:36.502124 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 20:12:36.508800 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5394 20:12:36.512003 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 20:12:36.515389 Total UI for P1: 0, mck2ui 16
5396 20:12:36.518954 best dqsien dly found for B0: ( 1, 2, 28)
5397 20:12:36.522360 Total UI for P1: 0, mck2ui 16
5398 20:12:36.525800 best dqsien dly found for B1: ( 1, 2, 28)
5399 20:12:36.528868 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5400 20:12:36.532147 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5401 20:12:36.532229
5402 20:12:36.535496 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5403 20:12:36.539146 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5404 20:12:36.542489 [Gating] SW calibration Done
5405 20:12:36.542571 ==
5406 20:12:36.545661 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 20:12:36.549181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 20:12:36.549263 ==
5409 20:12:36.552198 RX Vref Scan: 0
5410 20:12:36.552280
5411 20:12:36.555639 RX Vref 0 -> 0, step: 1
5412 20:12:36.555728
5413 20:12:36.555792 RX Delay -80 -> 252, step: 8
5414 20:12:36.562337 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5415 20:12:36.565925 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5416 20:12:36.569064 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5417 20:12:36.572343 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5418 20:12:36.575466 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5419 20:12:36.578932 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5420 20:12:36.585643 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5421 20:12:36.589014 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5422 20:12:36.592149 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5423 20:12:36.595361 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5424 20:12:36.598778 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5425 20:12:36.605525 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5426 20:12:36.608642 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5427 20:12:36.612230 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5428 20:12:36.615375 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5429 20:12:36.618509 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5430 20:12:36.618604 ==
5431 20:12:36.622064 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 20:12:36.629017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 20:12:36.629124 ==
5434 20:12:36.629221 DQS Delay:
5435 20:12:36.629311 DQS0 = 0, DQS1 = 0
5436 20:12:36.632413 DQM Delay:
5437 20:12:36.632509 DQM0 = 104, DQM1 = 90
5438 20:12:36.635153 DQ Delay:
5439 20:12:36.638534 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5440 20:12:36.642178 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5441 20:12:36.645282 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5442 20:12:36.648304 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5443 20:12:36.648402
5444 20:12:36.648493
5445 20:12:36.648580 ==
5446 20:12:36.651803 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 20:12:36.655234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 20:12:36.655333 ==
5449 20:12:36.655422
5450 20:12:36.655510
5451 20:12:36.658451 TX Vref Scan disable
5452 20:12:36.661587 == TX Byte 0 ==
5453 20:12:36.665210 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5454 20:12:36.668417 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5455 20:12:36.671645 == TX Byte 1 ==
5456 20:12:36.675145 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5457 20:12:36.678414 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5458 20:12:36.678490 ==
5459 20:12:36.681913 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 20:12:36.685158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 20:12:36.685259 ==
5462 20:12:36.688331
5463 20:12:36.688425
5464 20:12:36.688515 TX Vref Scan disable
5465 20:12:36.691592 == TX Byte 0 ==
5466 20:12:36.694720 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5467 20:12:36.701761 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5468 20:12:36.701858 == TX Byte 1 ==
5469 20:12:36.705006 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5470 20:12:36.711658 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5471 20:12:36.711758
5472 20:12:36.711848 [DATLAT]
5473 20:12:36.711935 Freq=933, CH0 RK1
5474 20:12:36.712022
5475 20:12:36.714734 DATLAT Default: 0xb
5476 20:12:36.714801 0, 0xFFFF, sum = 0
5477 20:12:36.718113 1, 0xFFFF, sum = 0
5478 20:12:36.718181 2, 0xFFFF, sum = 0
5479 20:12:36.721626 3, 0xFFFF, sum = 0
5480 20:12:36.721723 4, 0xFFFF, sum = 0
5481 20:12:36.725003 5, 0xFFFF, sum = 0
5482 20:12:36.728445 6, 0xFFFF, sum = 0
5483 20:12:36.728543 7, 0xFFFF, sum = 0
5484 20:12:36.731625 8, 0xFFFF, sum = 0
5485 20:12:36.731696 9, 0xFFFF, sum = 0
5486 20:12:36.734834 10, 0x0, sum = 1
5487 20:12:36.734902 11, 0x0, sum = 2
5488 20:12:36.734966 12, 0x0, sum = 3
5489 20:12:36.738232 13, 0x0, sum = 4
5490 20:12:36.738302 best_step = 11
5491 20:12:36.738361
5492 20:12:36.741523 ==
5493 20:12:36.741617 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 20:12:36.747968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 20:12:36.748070 ==
5496 20:12:36.748161 RX Vref Scan: 0
5497 20:12:36.748251
5498 20:12:36.751552 RX Vref 0 -> 0, step: 1
5499 20:12:36.751648
5500 20:12:36.754669 RX Delay -53 -> 252, step: 4
5501 20:12:36.758157 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5502 20:12:36.764698 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5503 20:12:36.768321 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5504 20:12:36.771353 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5505 20:12:36.774491 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5506 20:12:36.778191 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5507 20:12:36.784764 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5508 20:12:36.788200 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5509 20:12:36.791261 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5510 20:12:36.794573 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5511 20:12:36.798038 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5512 20:12:36.801427 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5513 20:12:36.807783 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5514 20:12:36.811372 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5515 20:12:36.814972 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5516 20:12:36.818181 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5517 20:12:36.818252 ==
5518 20:12:36.821351 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 20:12:36.828267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 20:12:36.828346 ==
5521 20:12:36.828410 DQS Delay:
5522 20:12:36.831100 DQS0 = 0, DQS1 = 0
5523 20:12:36.831171 DQM Delay:
5524 20:12:36.831234 DQM0 = 104, DQM1 = 93
5525 20:12:36.834422 DQ Delay:
5526 20:12:36.837876 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5527 20:12:36.841104 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5528 20:12:36.844715 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5529 20:12:36.847867 DQ12 =98, DQ13 =96, DQ14 =102, DQ15 =98
5530 20:12:36.847968
5531 20:12:36.848056
5532 20:12:36.854219 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5533 20:12:36.857823 CH0 RK1: MR19=505, MR18=2C0B
5534 20:12:36.864157 CH0_RK1: MR19=0x505, MR18=0x2C0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5535 20:12:36.867459 [RxdqsGatingPostProcess] freq 933
5536 20:12:36.874444 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5537 20:12:36.877702 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 20:12:36.877800 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 20:12:36.880693 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 20:12:36.884070 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 20:12:36.887354 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 20:12:36.890698 best DQS1 dly(2T, 0.5T) = (0, 10)
5543 20:12:36.894234 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 20:12:36.897354 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5545 20:12:36.900742 Pre-setting of DQS Precalculation
5546 20:12:36.907694 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5547 20:12:36.907768 ==
5548 20:12:36.910891 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 20:12:36.914491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 20:12:36.914562 ==
5551 20:12:36.920727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 20:12:36.924236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5553 20:12:36.927984 [CA 0] Center 37 (7~68) winsize 62
5554 20:12:36.931598 [CA 1] Center 37 (7~68) winsize 62
5555 20:12:36.934521 [CA 2] Center 36 (6~66) winsize 61
5556 20:12:36.938287 [CA 3] Center 34 (4~65) winsize 62
5557 20:12:36.941122 [CA 4] Center 35 (5~65) winsize 61
5558 20:12:36.944456 [CA 5] Center 34 (4~65) winsize 62
5559 20:12:36.944576
5560 20:12:36.947963 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5561 20:12:36.948063
5562 20:12:36.951226 [CATrainingPosCal] consider 1 rank data
5563 20:12:36.954604 u2DelayCellTimex100 = 270/100 ps
5564 20:12:36.957546 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5565 20:12:36.964263 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5566 20:12:36.967648 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5567 20:12:36.970738 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5568 20:12:36.974277 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5569 20:12:36.977888 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5570 20:12:36.977981
5571 20:12:36.980980 CA PerBit enable=1, Macro0, CA PI delay=34
5572 20:12:36.981056
5573 20:12:36.984344 [CBTSetCACLKResult] CA Dly = 34
5574 20:12:36.987712 CS Dly: 6 (0~37)
5575 20:12:36.987786 ==
5576 20:12:36.990956 Dram Type= 6, Freq= 0, CH_1, rank 1
5577 20:12:36.994212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 20:12:36.994284 ==
5579 20:12:36.997755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 20:12:37.004217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5581 20:12:37.007994 [CA 0] Center 38 (8~68) winsize 61
5582 20:12:37.011381 [CA 1] Center 38 (8~69) winsize 62
5583 20:12:37.014851 [CA 2] Center 36 (7~66) winsize 60
5584 20:12:37.018047 [CA 3] Center 35 (5~65) winsize 61
5585 20:12:37.021726 [CA 4] Center 35 (5~65) winsize 61
5586 20:12:37.024805 [CA 5] Center 35 (5~65) winsize 61
5587 20:12:37.024901
5588 20:12:37.027960 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5589 20:12:37.028056
5590 20:12:37.031167 [CATrainingPosCal] consider 2 rank data
5591 20:12:37.034767 u2DelayCellTimex100 = 270/100 ps
5592 20:12:37.037993 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5593 20:12:37.044504 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5594 20:12:37.047842 CA2 delay=36 (7~66),Diff = 1 PI (6 cell)
5595 20:12:37.051429 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5596 20:12:37.054453 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5597 20:12:37.057660 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5598 20:12:37.057756
5599 20:12:37.060943 CA PerBit enable=1, Macro0, CA PI delay=35
5600 20:12:37.061038
5601 20:12:37.064888 [CBTSetCACLKResult] CA Dly = 35
5602 20:12:37.064983 CS Dly: 7 (0~40)
5603 20:12:37.065073
5604 20:12:37.071053 ----->DramcWriteLeveling(PI) begin...
5605 20:12:37.071150 ==
5606 20:12:37.074578 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 20:12:37.077804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 20:12:37.077900 ==
5609 20:12:37.081406 Write leveling (Byte 0): 28 => 28
5610 20:12:37.084439 Write leveling (Byte 1): 29 => 29
5611 20:12:37.087565 DramcWriteLeveling(PI) end<-----
5612 20:12:37.087638
5613 20:12:37.087699 ==
5614 20:12:37.091088 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 20:12:37.094283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 20:12:37.094355 ==
5617 20:12:37.097889 [Gating] SW mode calibration
5618 20:12:37.104446 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5619 20:12:37.110800 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5620 20:12:37.114089 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 20:12:37.117698 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 20:12:37.123942 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 20:12:37.127312 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 20:12:37.130967 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 20:12:37.137361 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5626 20:12:37.140950 0 14 24 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 0)
5627 20:12:37.144116 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5628 20:12:37.150717 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 20:12:37.154293 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 20:12:37.157472 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 20:12:37.164302 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 20:12:37.167368 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 20:12:37.170734 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 20:12:37.173694 0 15 24 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (0 0)
5635 20:12:37.180283 0 15 28 | B1->B0 | 3f3f 3e3e | 0 0 | (0 0) (0 0)
5636 20:12:37.184127 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 20:12:37.187488 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 20:12:37.193658 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 20:12:37.197418 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 20:12:37.200376 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 20:12:37.207158 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 20:12:37.210357 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5643 20:12:37.213762 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5644 20:12:37.220617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 20:12:37.223669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 20:12:37.226938 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 20:12:37.233898 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 20:12:37.237051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 20:12:37.240145 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 20:12:37.247165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 20:12:37.250413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 20:12:37.253666 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 20:12:37.260147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 20:12:37.263418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 20:12:37.266770 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 20:12:37.273823 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 20:12:37.277181 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 20:12:37.280313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5659 20:12:37.286823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 20:12:37.286927 Total UI for P1: 0, mck2ui 16
5661 20:12:37.290526 best dqsien dly found for B0: ( 1, 2, 24)
5662 20:12:37.294031 Total UI for P1: 0, mck2ui 16
5663 20:12:37.296917 best dqsien dly found for B1: ( 1, 2, 24)
5664 20:12:37.300048 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5665 20:12:37.306819 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5666 20:12:37.306901
5667 20:12:37.310339 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5668 20:12:37.313375 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5669 20:12:37.316679 [Gating] SW calibration Done
5670 20:12:37.316752 ==
5671 20:12:37.320302 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 20:12:37.323713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 20:12:37.323784 ==
5674 20:12:37.323846 RX Vref Scan: 0
5675 20:12:37.326765
5676 20:12:37.326833 RX Vref 0 -> 0, step: 1
5677 20:12:37.326899
5678 20:12:37.329788 RX Delay -80 -> 252, step: 8
5679 20:12:37.333440 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5680 20:12:37.336819 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5681 20:12:37.343249 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5682 20:12:37.346692 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5683 20:12:37.350157 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5684 20:12:37.353172 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5685 20:12:37.356821 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5686 20:12:37.363376 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5687 20:12:37.366552 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5688 20:12:37.370025 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5689 20:12:37.373315 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5690 20:12:37.376506 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5691 20:12:37.379926 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5692 20:12:37.386428 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5693 20:12:37.389646 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5694 20:12:37.393137 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5695 20:12:37.393220 ==
5696 20:12:37.396268 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 20:12:37.399862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 20:12:37.399945 ==
5699 20:12:37.403062 DQS Delay:
5700 20:12:37.403143 DQS0 = 0, DQS1 = 0
5701 20:12:37.406312 DQM Delay:
5702 20:12:37.406394 DQM0 = 103, DQM1 = 94
5703 20:12:37.406459 DQ Delay:
5704 20:12:37.410035 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =103
5705 20:12:37.413131 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5706 20:12:37.416446 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5707 20:12:37.422808 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5708 20:12:37.422890
5709 20:12:37.422954
5710 20:12:37.423013 ==
5711 20:12:37.426401 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 20:12:37.429456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 20:12:37.429540 ==
5714 20:12:37.429607
5715 20:12:37.429666
5716 20:12:37.432998 TX Vref Scan disable
5717 20:12:37.433080 == TX Byte 0 ==
5718 20:12:37.439566 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5719 20:12:37.442733 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5720 20:12:37.442816 == TX Byte 1 ==
5721 20:12:37.449752 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5722 20:12:37.452809 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5723 20:12:37.452892 ==
5724 20:12:37.456042 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 20:12:37.459356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 20:12:37.459440 ==
5727 20:12:37.459505
5728 20:12:37.459564
5729 20:12:37.462778 TX Vref Scan disable
5730 20:12:37.466257 == TX Byte 0 ==
5731 20:12:37.469490 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5732 20:12:37.472922 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5733 20:12:37.475884 == TX Byte 1 ==
5734 20:12:37.479302 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5735 20:12:37.482575 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5736 20:12:37.482658
5737 20:12:37.486053 [DATLAT]
5738 20:12:37.486135 Freq=933, CH1 RK0
5739 20:12:37.486201
5740 20:12:37.489371 DATLAT Default: 0xd
5741 20:12:37.489454 0, 0xFFFF, sum = 0
5742 20:12:37.492623 1, 0xFFFF, sum = 0
5743 20:12:37.492707 2, 0xFFFF, sum = 0
5744 20:12:37.495696 3, 0xFFFF, sum = 0
5745 20:12:37.495781 4, 0xFFFF, sum = 0
5746 20:12:37.499051 5, 0xFFFF, sum = 0
5747 20:12:37.499136 6, 0xFFFF, sum = 0
5748 20:12:37.502521 7, 0xFFFF, sum = 0
5749 20:12:37.502606 8, 0xFFFF, sum = 0
5750 20:12:37.505909 9, 0xFFFF, sum = 0
5751 20:12:37.506034 10, 0x0, sum = 1
5752 20:12:37.509127 11, 0x0, sum = 2
5753 20:12:37.509212 12, 0x0, sum = 3
5754 20:12:37.512194 13, 0x0, sum = 4
5755 20:12:37.512279 best_step = 11
5756 20:12:37.512344
5757 20:12:37.512405 ==
5758 20:12:37.516159 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 20:12:37.522263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 20:12:37.522347 ==
5761 20:12:37.522414 RX Vref Scan: 1
5762 20:12:37.522476
5763 20:12:37.525721 RX Vref 0 -> 0, step: 1
5764 20:12:37.525805
5765 20:12:37.528904 RX Delay -53 -> 252, step: 4
5766 20:12:37.528989
5767 20:12:37.532443 Set Vref, RX VrefLevel [Byte0]: 52
5768 20:12:37.536448 [Byte1]: 53
5769 20:12:37.536531
5770 20:12:37.539008 Final RX Vref Byte 0 = 52 to rank0
5771 20:12:37.542183 Final RX Vref Byte 1 = 53 to rank0
5772 20:12:37.545704 Final RX Vref Byte 0 = 52 to rank1
5773 20:12:37.549024 Final RX Vref Byte 1 = 53 to rank1==
5774 20:12:37.552444 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 20:12:37.555579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 20:12:37.555663 ==
5777 20:12:37.558718 DQS Delay:
5778 20:12:37.558801 DQS0 = 0, DQS1 = 0
5779 20:12:37.558868 DQM Delay:
5780 20:12:37.562180 DQM0 = 104, DQM1 = 97
5781 20:12:37.562264 DQ Delay:
5782 20:12:37.565867 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5783 20:12:37.568651 DQ4 =104, DQ5 =112, DQ6 =116, DQ7 =102
5784 20:12:37.572386 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5785 20:12:37.578920 DQ12 =110, DQ13 =102, DQ14 =102, DQ15 =102
5786 20:12:37.579032
5787 20:12:37.579130
5788 20:12:37.585649 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5789 20:12:37.588690 CH1 RK0: MR19=505, MR18=1932
5790 20:12:37.595358 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5791 20:12:37.595468
5792 20:12:37.598494 ----->DramcWriteLeveling(PI) begin...
5793 20:12:37.598579 ==
5794 20:12:37.602164 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 20:12:37.605160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 20:12:37.605244 ==
5797 20:12:37.608663 Write leveling (Byte 0): 29 => 29
5798 20:12:37.612023 Write leveling (Byte 1): 28 => 28
5799 20:12:37.615388 DramcWriteLeveling(PI) end<-----
5800 20:12:37.615471
5801 20:12:37.615537 ==
5802 20:12:37.618440 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 20:12:37.621962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 20:12:37.622047 ==
5805 20:12:37.625570 [Gating] SW mode calibration
5806 20:12:37.631871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5807 20:12:37.638842 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5808 20:12:37.642079 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5809 20:12:37.645475 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 20:12:37.651933 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 20:12:37.655157 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 20:12:37.658918 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 20:12:37.665423 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 20:12:37.668564 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (0 1) (1 1)
5815 20:12:37.671851 0 14 28 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
5816 20:12:37.678453 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5817 20:12:37.681703 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 20:12:37.685220 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 20:12:37.691752 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 20:12:37.695176 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 20:12:37.698732 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 20:12:37.705236 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5823 20:12:37.708130 0 15 28 | B1->B0 | 3e3e 3737 | 0 0 | (0 0) (0 0)
5824 20:12:37.711492 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 20:12:37.718242 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 20:12:37.721580 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 20:12:37.724841 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 20:12:37.731442 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 20:12:37.734731 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 20:12:37.738236 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5831 20:12:37.744714 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 20:12:37.748188 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 20:12:37.751612 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 20:12:37.757816 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 20:12:37.761273 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 20:12:37.764560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 20:12:37.771387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 20:12:37.774477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 20:12:37.777715 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 20:12:37.784371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 20:12:37.788108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 20:12:37.791059 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 20:12:37.797981 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 20:12:37.801029 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 20:12:37.804474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 20:12:37.811045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5847 20:12:37.814450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 20:12:37.818061 Total UI for P1: 0, mck2ui 16
5849 20:12:37.821046 best dqsien dly found for B0: ( 1, 2, 24)
5850 20:12:37.824656 Total UI for P1: 0, mck2ui 16
5851 20:12:37.827745 best dqsien dly found for B1: ( 1, 2, 26)
5852 20:12:37.831318 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5853 20:12:37.834355 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5854 20:12:37.834439
5855 20:12:37.837620 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5856 20:12:37.841097 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5857 20:12:37.844586 [Gating] SW calibration Done
5858 20:12:37.844669 ==
5859 20:12:37.847920 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 20:12:37.851278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 20:12:37.851362 ==
5862 20:12:37.854490 RX Vref Scan: 0
5863 20:12:37.854573
5864 20:12:37.854666 RX Vref 0 -> 0, step: 1
5865 20:12:37.857530
5866 20:12:37.857613 RX Delay -80 -> 252, step: 8
5867 20:12:37.864199 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5868 20:12:37.867610 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5869 20:12:37.871050 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5870 20:12:37.874204 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5871 20:12:37.877757 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5872 20:12:37.881011 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5873 20:12:37.887877 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5874 20:12:37.891106 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5875 20:12:37.894278 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5876 20:12:37.897580 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5877 20:12:37.900761 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5878 20:12:37.904507 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5879 20:12:37.907704 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5880 20:12:37.914229 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5881 20:12:37.917766 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5882 20:12:37.920849 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5883 20:12:37.920933 ==
5884 20:12:37.924268 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 20:12:37.927745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 20:12:37.927829 ==
5887 20:12:37.931169 DQS Delay:
5888 20:12:37.931252 DQS0 = 0, DQS1 = 0
5889 20:12:37.934260 DQM Delay:
5890 20:12:37.934343 DQM0 = 102, DQM1 = 97
5891 20:12:37.934410 DQ Delay:
5892 20:12:37.937779 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5893 20:12:37.940796 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5894 20:12:37.944244 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5895 20:12:37.951171 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5896 20:12:37.951271
5897 20:12:37.951338
5898 20:12:37.951399 ==
5899 20:12:37.954120 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 20:12:37.957788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 20:12:37.957873 ==
5902 20:12:37.957943
5903 20:12:37.958045
5904 20:12:37.961063 TX Vref Scan disable
5905 20:12:37.961147 == TX Byte 0 ==
5906 20:12:37.967834 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5907 20:12:37.971061 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5908 20:12:37.971146 == TX Byte 1 ==
5909 20:12:37.977766 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5910 20:12:37.980786 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5911 20:12:37.980870 ==
5912 20:12:37.984020 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 20:12:37.987512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 20:12:37.987597 ==
5915 20:12:37.987663
5916 20:12:37.987724
5917 20:12:37.991002 TX Vref Scan disable
5918 20:12:37.994234 == TX Byte 0 ==
5919 20:12:37.997695 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5920 20:12:38.000706 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5921 20:12:38.003906 == TX Byte 1 ==
5922 20:12:38.007439 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5923 20:12:38.010620 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5924 20:12:38.010704
5925 20:12:38.014186 [DATLAT]
5926 20:12:38.014270 Freq=933, CH1 RK1
5927 20:12:38.014336
5928 20:12:38.017262 DATLAT Default: 0xb
5929 20:12:38.017345 0, 0xFFFF, sum = 0
5930 20:12:38.020873 1, 0xFFFF, sum = 0
5931 20:12:38.020958 2, 0xFFFF, sum = 0
5932 20:12:38.023957 3, 0xFFFF, sum = 0
5933 20:12:38.024042 4, 0xFFFF, sum = 0
5934 20:12:38.027860 5, 0xFFFF, sum = 0
5935 20:12:38.027965 6, 0xFFFF, sum = 0
5936 20:12:38.030792 7, 0xFFFF, sum = 0
5937 20:12:38.030877 8, 0xFFFF, sum = 0
5938 20:12:38.034167 9, 0xFFFF, sum = 0
5939 20:12:38.034252 10, 0x0, sum = 1
5940 20:12:38.037239 11, 0x0, sum = 2
5941 20:12:38.037324 12, 0x0, sum = 3
5942 20:12:38.040855 13, 0x0, sum = 4
5943 20:12:38.040940 best_step = 11
5944 20:12:38.041006
5945 20:12:38.041067 ==
5946 20:12:38.044146 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 20:12:38.050635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 20:12:38.050720 ==
5949 20:12:38.050786 RX Vref Scan: 0
5950 20:12:38.050848
5951 20:12:38.054209 RX Vref 0 -> 0, step: 1
5952 20:12:38.054293
5953 20:12:38.057285 RX Delay -45 -> 252, step: 4
5954 20:12:38.060675 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5955 20:12:38.064008 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5956 20:12:38.070434 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5957 20:12:38.074070 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5958 20:12:38.077277 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5959 20:12:38.080542 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5960 20:12:38.083938 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5961 20:12:38.090430 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5962 20:12:38.094103 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5963 20:12:38.097192 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5964 20:12:38.100587 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5965 20:12:38.103891 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5966 20:12:38.107113 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5967 20:12:38.113820 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5968 20:12:38.117302 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5969 20:12:38.120482 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5970 20:12:38.120567 ==
5971 20:12:38.124071 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 20:12:38.127159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 20:12:38.130341 ==
5974 20:12:38.130426 DQS Delay:
5975 20:12:38.130492 DQS0 = 0, DQS1 = 0
5976 20:12:38.134080 DQM Delay:
5977 20:12:38.134163 DQM0 = 105, DQM1 = 97
5978 20:12:38.136841 DQ Delay:
5979 20:12:38.140331 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5980 20:12:38.143581 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =102
5981 20:12:38.147229 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =90
5982 20:12:38.150409 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5983 20:12:38.150493
5984 20:12:38.150559
5985 20:12:38.157075 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5986 20:12:38.160373 CH1 RK1: MR19=504, MR18=20FD
5987 20:12:38.167280 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5988 20:12:38.170296 [RxdqsGatingPostProcess] freq 933
5989 20:12:38.173820 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5990 20:12:38.177596 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 20:12:38.180634 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 20:12:38.183930 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 20:12:38.187106 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 20:12:38.190276 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 20:12:38.193625 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 20:12:38.196974 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 20:12:38.200393 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 20:12:38.203601 Pre-setting of DQS Precalculation
5999 20:12:38.206720 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6000 20:12:38.217179 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6001 20:12:38.223557 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6002 20:12:38.223642
6003 20:12:38.223708
6004 20:12:38.226899 [Calibration Summary] 1866 Mbps
6005 20:12:38.226983 CH 0, Rank 0
6006 20:12:38.229889 SW Impedance : PASS
6007 20:12:38.230010 DUTY Scan : NO K
6008 20:12:38.233219 ZQ Calibration : PASS
6009 20:12:38.236921 Jitter Meter : NO K
6010 20:12:38.237009 CBT Training : PASS
6011 20:12:38.240079 Write leveling : PASS
6012 20:12:38.243372 RX DQS gating : PASS
6013 20:12:38.243455 RX DQ/DQS(RDDQC) : PASS
6014 20:12:38.246406 TX DQ/DQS : PASS
6015 20:12:38.249789 RX DATLAT : PASS
6016 20:12:38.249873 RX DQ/DQS(Engine): PASS
6017 20:12:38.253125 TX OE : NO K
6018 20:12:38.253209 All Pass.
6019 20:12:38.253275
6020 20:12:38.256237 CH 0, Rank 1
6021 20:12:38.256321 SW Impedance : PASS
6022 20:12:38.259547 DUTY Scan : NO K
6023 20:12:38.263228 ZQ Calibration : PASS
6024 20:12:38.263312 Jitter Meter : NO K
6025 20:12:38.266592 CBT Training : PASS
6026 20:12:38.269350 Write leveling : PASS
6027 20:12:38.269434 RX DQS gating : PASS
6028 20:12:38.272876 RX DQ/DQS(RDDQC) : PASS
6029 20:12:38.276020 TX DQ/DQS : PASS
6030 20:12:38.276104 RX DATLAT : PASS
6031 20:12:38.279626 RX DQ/DQS(Engine): PASS
6032 20:12:38.279710 TX OE : NO K
6033 20:12:38.282765 All Pass.
6034 20:12:38.282849
6035 20:12:38.282915 CH 1, Rank 0
6036 20:12:38.286227 SW Impedance : PASS
6037 20:12:38.286311 DUTY Scan : NO K
6038 20:12:38.289681 ZQ Calibration : PASS
6039 20:12:38.293218 Jitter Meter : NO K
6040 20:12:38.293302 CBT Training : PASS
6041 20:12:38.296008 Write leveling : PASS
6042 20:12:38.299348 RX DQS gating : PASS
6043 20:12:38.299432 RX DQ/DQS(RDDQC) : PASS
6044 20:12:38.302873 TX DQ/DQS : PASS
6045 20:12:38.306209 RX DATLAT : PASS
6046 20:12:38.306292 RX DQ/DQS(Engine): PASS
6047 20:12:38.309429 TX OE : NO K
6048 20:12:38.309513 All Pass.
6049 20:12:38.309578
6050 20:12:38.312818 CH 1, Rank 1
6051 20:12:38.312901 SW Impedance : PASS
6052 20:12:38.316036 DUTY Scan : NO K
6053 20:12:38.319479 ZQ Calibration : PASS
6054 20:12:38.319563 Jitter Meter : NO K
6055 20:12:38.322758 CBT Training : PASS
6056 20:12:38.325976 Write leveling : PASS
6057 20:12:38.326061 RX DQS gating : PASS
6058 20:12:38.329402 RX DQ/DQS(RDDQC) : PASS
6059 20:12:38.329476 TX DQ/DQS : PASS
6060 20:12:38.332567 RX DATLAT : PASS
6061 20:12:38.335977 RX DQ/DQS(Engine): PASS
6062 20:12:38.336052 TX OE : NO K
6063 20:12:38.339241 All Pass.
6064 20:12:38.339314
6065 20:12:38.339374 DramC Write-DBI off
6066 20:12:38.342440 PER_BANK_REFRESH: Hybrid Mode
6067 20:12:38.345851 TX_TRACKING: ON
6068 20:12:38.352952 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6069 20:12:38.355937 [FAST_K] Save calibration result to emmc
6070 20:12:38.359668 dramc_set_vcore_voltage set vcore to 650000
6071 20:12:38.362466 Read voltage for 400, 6
6072 20:12:38.362548 Vio18 = 0
6073 20:12:38.365858 Vcore = 650000
6074 20:12:38.365945 Vdram = 0
6075 20:12:38.366047 Vddq = 0
6076 20:12:38.369115 Vmddr = 0
6077 20:12:38.372410 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6078 20:12:38.379174 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6079 20:12:38.379260 MEM_TYPE=3, freq_sel=20
6080 20:12:38.382718 sv_algorithm_assistance_LP4_800
6081 20:12:38.389356 ============ PULL DRAM RESETB DOWN ============
6082 20:12:38.392559 ========== PULL DRAM RESETB DOWN end =========
6083 20:12:38.395759 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6084 20:12:38.399263 ===================================
6085 20:12:38.402281 LPDDR4 DRAM CONFIGURATION
6086 20:12:38.405787 ===================================
6087 20:12:38.405896 EX_ROW_EN[0] = 0x0
6088 20:12:38.409111 EX_ROW_EN[1] = 0x0
6089 20:12:38.412545 LP4Y_EN = 0x0
6090 20:12:38.412628 WORK_FSP = 0x0
6091 20:12:38.415605 WL = 0x2
6092 20:12:38.415687 RL = 0x2
6093 20:12:38.419202 BL = 0x2
6094 20:12:38.419285 RPST = 0x0
6095 20:12:38.422914 RD_PRE = 0x0
6096 20:12:38.422996 WR_PRE = 0x1
6097 20:12:38.425894 WR_PST = 0x0
6098 20:12:38.425998 DBI_WR = 0x0
6099 20:12:38.429187 DBI_RD = 0x0
6100 20:12:38.429271 OTF = 0x1
6101 20:12:38.432416 ===================================
6102 20:12:38.435535 ===================================
6103 20:12:38.439020 ANA top config
6104 20:12:38.442485 ===================================
6105 20:12:38.442570 DLL_ASYNC_EN = 0
6106 20:12:38.445671 ALL_SLAVE_EN = 1
6107 20:12:38.449033 NEW_RANK_MODE = 1
6108 20:12:38.452318 DLL_IDLE_MODE = 1
6109 20:12:38.455937 LP45_APHY_COMB_EN = 1
6110 20:12:38.456021 TX_ODT_DIS = 1
6111 20:12:38.459193 NEW_8X_MODE = 1
6112 20:12:38.462660 ===================================
6113 20:12:38.465959 ===================================
6114 20:12:38.469074 data_rate = 800
6115 20:12:38.472475 CKR = 1
6116 20:12:38.475579 DQ_P2S_RATIO = 4
6117 20:12:38.478665 ===================================
6118 20:12:38.478748 CA_P2S_RATIO = 4
6119 20:12:38.482051 DQ_CA_OPEN = 0
6120 20:12:38.485549 DQ_SEMI_OPEN = 1
6121 20:12:38.488980 CA_SEMI_OPEN = 1
6122 20:12:38.491952 CA_FULL_RATE = 0
6123 20:12:38.495469 DQ_CKDIV4_EN = 0
6124 20:12:38.495553 CA_CKDIV4_EN = 1
6125 20:12:38.498772 CA_PREDIV_EN = 0
6126 20:12:38.502168 PH8_DLY = 0
6127 20:12:38.505351 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6128 20:12:38.508918 DQ_AAMCK_DIV = 0
6129 20:12:38.512252 CA_AAMCK_DIV = 0
6130 20:12:38.512336 CA_ADMCK_DIV = 4
6131 20:12:38.515385 DQ_TRACK_CA_EN = 0
6132 20:12:38.519055 CA_PICK = 800
6133 20:12:38.522215 CA_MCKIO = 400
6134 20:12:38.525242 MCKIO_SEMI = 400
6135 20:12:38.528899 PLL_FREQ = 3016
6136 20:12:38.532057 DQ_UI_PI_RATIO = 32
6137 20:12:38.535192 CA_UI_PI_RATIO = 32
6138 20:12:38.538722 ===================================
6139 20:12:38.542476 ===================================
6140 20:12:38.542560 memory_type:LPDDR4
6141 20:12:38.545377 GP_NUM : 10
6142 20:12:38.545460 SRAM_EN : 1
6143 20:12:38.548888 MD32_EN : 0
6144 20:12:38.551842 ===================================
6145 20:12:38.555225 [ANA_INIT] >>>>>>>>>>>>>>
6146 20:12:38.558503 <<<<<< [CONFIGURE PHASE]: ANA_TX
6147 20:12:38.562049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6148 20:12:38.565109 ===================================
6149 20:12:38.565193 data_rate = 800,PCW = 0X7400
6150 20:12:38.568610 ===================================
6151 20:12:38.571925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6152 20:12:38.578585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 20:12:38.592282 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 20:12:38.594935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6155 20:12:38.598670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6156 20:12:38.601979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6157 20:12:38.605407 [ANA_INIT] flow start
6158 20:12:38.605490 [ANA_INIT] PLL >>>>>>>>
6159 20:12:38.608890 [ANA_INIT] PLL <<<<<<<<
6160 20:12:38.611718 [ANA_INIT] MIDPI >>>>>>>>
6161 20:12:38.611802 [ANA_INIT] MIDPI <<<<<<<<
6162 20:12:38.615405 [ANA_INIT] DLL >>>>>>>>
6163 20:12:38.618771 [ANA_INIT] flow end
6164 20:12:38.621675 ============ LP4 DIFF to SE enter ============
6165 20:12:38.625266 ============ LP4 DIFF to SE exit ============
6166 20:12:38.628250 [ANA_INIT] <<<<<<<<<<<<<
6167 20:12:38.631797 [Flow] Enable top DCM control >>>>>
6168 20:12:38.634861 [Flow] Enable top DCM control <<<<<
6169 20:12:38.638591 Enable DLL master slave shuffle
6170 20:12:38.641746 ==============================================================
6171 20:12:38.645146 Gating Mode config
6172 20:12:38.651978 ==============================================================
6173 20:12:38.652092 Config description:
6174 20:12:38.661699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6175 20:12:38.668236 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6176 20:12:38.675000 SELPH_MODE 0: By rank 1: By Phase
6177 20:12:38.678119 ==============================================================
6178 20:12:38.681556 GAT_TRACK_EN = 0
6179 20:12:38.684644 RX_GATING_MODE = 2
6180 20:12:38.687976 RX_GATING_TRACK_MODE = 2
6181 20:12:38.691485 SELPH_MODE = 1
6182 20:12:38.694795 PICG_EARLY_EN = 1
6183 20:12:38.697977 VALID_LAT_VALUE = 1
6184 20:12:38.701289 ==============================================================
6185 20:12:38.704889 Enter into Gating configuration >>>>
6186 20:12:38.708036 Exit from Gating configuration <<<<
6187 20:12:38.711474 Enter into DVFS_PRE_config >>>>>
6188 20:12:38.724584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6189 20:12:38.728165 Exit from DVFS_PRE_config <<<<<
6190 20:12:38.731125 Enter into PICG configuration >>>>
6191 20:12:38.731209 Exit from PICG configuration <<<<
6192 20:12:38.734881 [RX_INPUT] configuration >>>>>
6193 20:12:38.738268 [RX_INPUT] configuration <<<<<
6194 20:12:38.744760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6195 20:12:38.748072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6196 20:12:38.754525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 20:12:38.761021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 20:12:38.767755 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 20:12:38.774334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 20:12:38.777593 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6201 20:12:38.781287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6202 20:12:38.784372 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6203 20:12:38.791242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6204 20:12:38.794597 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6205 20:12:38.797806 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 20:12:38.801075 ===================================
6207 20:12:38.804547 LPDDR4 DRAM CONFIGURATION
6208 20:12:38.807458 ===================================
6209 20:12:38.810734 EX_ROW_EN[0] = 0x0
6210 20:12:38.810817 EX_ROW_EN[1] = 0x0
6211 20:12:38.814037 LP4Y_EN = 0x0
6212 20:12:38.814120 WORK_FSP = 0x0
6213 20:12:38.817829 WL = 0x2
6214 20:12:38.817943 RL = 0x2
6215 20:12:38.820878 BL = 0x2
6216 20:12:38.820962 RPST = 0x0
6217 20:12:38.824423 RD_PRE = 0x0
6218 20:12:38.824506 WR_PRE = 0x1
6219 20:12:38.827523 WR_PST = 0x0
6220 20:12:38.827607 DBI_WR = 0x0
6221 20:12:38.830851 DBI_RD = 0x0
6222 20:12:38.830935 OTF = 0x1
6223 20:12:38.834015 ===================================
6224 20:12:38.840865 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6225 20:12:38.844206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6226 20:12:38.847640 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 20:12:38.850758 ===================================
6228 20:12:38.854297 LPDDR4 DRAM CONFIGURATION
6229 20:12:38.857437 ===================================
6230 20:12:38.857521 EX_ROW_EN[0] = 0x10
6231 20:12:38.860770 EX_ROW_EN[1] = 0x0
6232 20:12:38.864242 LP4Y_EN = 0x0
6233 20:12:38.864326 WORK_FSP = 0x0
6234 20:12:38.867421 WL = 0x2
6235 20:12:38.867504 RL = 0x2
6236 20:12:38.870783 BL = 0x2
6237 20:12:38.870867 RPST = 0x0
6238 20:12:38.873988 RD_PRE = 0x0
6239 20:12:38.874078 WR_PRE = 0x1
6240 20:12:38.877161 WR_PST = 0x0
6241 20:12:38.877244 DBI_WR = 0x0
6242 20:12:38.880894 DBI_RD = 0x0
6243 20:12:38.880978 OTF = 0x1
6244 20:12:38.883840 ===================================
6245 20:12:38.890517 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6246 20:12:38.894862 nWR fixed to 30
6247 20:12:38.898550 [ModeRegInit_LP4] CH0 RK0
6248 20:12:38.898634 [ModeRegInit_LP4] CH0 RK1
6249 20:12:38.901759 [ModeRegInit_LP4] CH1 RK0
6250 20:12:38.905152 [ModeRegInit_LP4] CH1 RK1
6251 20:12:38.905236 match AC timing 19
6252 20:12:38.911622 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6253 20:12:38.914841 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6254 20:12:38.918255 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6255 20:12:38.924975 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6256 20:12:38.927943 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6257 20:12:38.928027 ==
6258 20:12:38.931627 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 20:12:38.934797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 20:12:38.934881 ==
6261 20:12:38.941301 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 20:12:38.948188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6263 20:12:38.951933 [CA 0] Center 36 (8~64) winsize 57
6264 20:12:38.954750 [CA 1] Center 36 (8~64) winsize 57
6265 20:12:38.958442 [CA 2] Center 36 (8~64) winsize 57
6266 20:12:38.958525 [CA 3] Center 36 (8~64) winsize 57
6267 20:12:38.961782 [CA 4] Center 36 (8~64) winsize 57
6268 20:12:38.964883 [CA 5] Center 36 (8~64) winsize 57
6269 20:12:38.964967
6270 20:12:38.968466 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6271 20:12:38.971412
6272 20:12:38.974730 [CATrainingPosCal] consider 1 rank data
6273 20:12:38.974829 u2DelayCellTimex100 = 270/100 ps
6274 20:12:38.981496 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 20:12:38.984814 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 20:12:38.988323 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 20:12:38.991563 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 20:12:38.995048 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 20:12:38.998115 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 20:12:38.998200
6281 20:12:39.001417 CA PerBit enable=1, Macro0, CA PI delay=36
6282 20:12:39.001501
6283 20:12:39.004748 [CBTSetCACLKResult] CA Dly = 36
6284 20:12:39.008284 CS Dly: 1 (0~32)
6285 20:12:39.008367 ==
6286 20:12:39.011519 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 20:12:39.014805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 20:12:39.014906 ==
6289 20:12:39.021279 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 20:12:39.024852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6291 20:12:39.028257 [CA 0] Center 36 (8~64) winsize 57
6292 20:12:39.031849 [CA 1] Center 36 (8~64) winsize 57
6293 20:12:39.034745 [CA 2] Center 36 (8~64) winsize 57
6294 20:12:39.038136 [CA 3] Center 36 (8~64) winsize 57
6295 20:12:39.041210 [CA 4] Center 36 (8~64) winsize 57
6296 20:12:39.044826 [CA 5] Center 36 (8~64) winsize 57
6297 20:12:39.044909
6298 20:12:39.047826 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6299 20:12:39.047909
6300 20:12:39.051277 [CATrainingPosCal] consider 2 rank data
6301 20:12:39.054807 u2DelayCellTimex100 = 270/100 ps
6302 20:12:39.057876 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 20:12:39.061509 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 20:12:39.064480 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 20:12:39.071055 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 20:12:39.074663 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 20:12:39.078021 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 20:12:39.078108
6309 20:12:39.081029 CA PerBit enable=1, Macro0, CA PI delay=36
6310 20:12:39.081113
6311 20:12:39.084630 [CBTSetCACLKResult] CA Dly = 36
6312 20:12:39.084714 CS Dly: 1 (0~32)
6313 20:12:39.084780
6314 20:12:39.087985 ----->DramcWriteLeveling(PI) begin...
6315 20:12:39.088070 ==
6316 20:12:39.091586 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 20:12:39.097843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 20:12:39.097926 ==
6319 20:12:39.101312 Write leveling (Byte 0): 40 => 8
6320 20:12:39.101396 Write leveling (Byte 1): 32 => 0
6321 20:12:39.104731 DramcWriteLeveling(PI) end<-----
6322 20:12:39.104815
6323 20:12:39.107762 ==
6324 20:12:39.107845 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 20:12:39.114590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 20:12:39.114675 ==
6327 20:12:39.117724 [Gating] SW mode calibration
6328 20:12:39.124315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6329 20:12:39.127975 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6330 20:12:39.134854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 20:12:39.137755 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 20:12:39.141049 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 20:12:39.147801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 20:12:39.151265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 20:12:39.154828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 20:12:39.157799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 20:12:39.164654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 20:12:39.167675 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 20:12:39.171319 Total UI for P1: 0, mck2ui 16
6340 20:12:39.174516 best dqsien dly found for B0: ( 0, 14, 24)
6341 20:12:39.177816 Total UI for P1: 0, mck2ui 16
6342 20:12:39.181183 best dqsien dly found for B1: ( 0, 14, 24)
6343 20:12:39.184942 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6344 20:12:39.187797 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6345 20:12:39.187881
6346 20:12:39.191357 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 20:12:39.197838 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 20:12:39.197954 [Gating] SW calibration Done
6349 20:12:39.198083 ==
6350 20:12:39.200897 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 20:12:39.208242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 20:12:39.208326 ==
6353 20:12:39.208392 RX Vref Scan: 0
6354 20:12:39.208453
6355 20:12:39.211213 RX Vref 0 -> 0, step: 1
6356 20:12:39.211297
6357 20:12:39.214301 RX Delay -410 -> 252, step: 16
6358 20:12:39.217757 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6359 20:12:39.221074 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6360 20:12:39.227459 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6361 20:12:39.230716 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6362 20:12:39.234331 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6363 20:12:39.237254 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6364 20:12:39.244118 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6365 20:12:39.247644 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6366 20:12:39.250607 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6367 20:12:39.254116 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6368 20:12:39.260960 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6369 20:12:39.263753 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6370 20:12:39.267338 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6371 20:12:39.270434 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6372 20:12:39.276979 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6373 20:12:39.280653 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6374 20:12:39.280735 ==
6375 20:12:39.283777 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 20:12:39.286910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 20:12:39.286992 ==
6378 20:12:39.290459 DQS Delay:
6379 20:12:39.290541 DQS0 = 27, DQS1 = 43
6380 20:12:39.293586 DQM Delay:
6381 20:12:39.293668 DQM0 = 12, DQM1 = 13
6382 20:12:39.293731 DQ Delay:
6383 20:12:39.297181 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6384 20:12:39.300178 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6385 20:12:39.303716 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6386 20:12:39.306850 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6387 20:12:39.306932
6388 20:12:39.306995
6389 20:12:39.307055 ==
6390 20:12:39.310135 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 20:12:39.316623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 20:12:39.316706 ==
6393 20:12:39.316770
6394 20:12:39.316830
6395 20:12:39.320234 TX Vref Scan disable
6396 20:12:39.320315 == TX Byte 0 ==
6397 20:12:39.323462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 20:12:39.326862 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 20:12:39.329828 == TX Byte 1 ==
6400 20:12:39.333338 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6401 20:12:39.336554 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6402 20:12:39.339650 ==
6403 20:12:39.343260 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 20:12:39.346358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 20:12:39.346440 ==
6406 20:12:39.346505
6407 20:12:39.346565
6408 20:12:39.349866 TX Vref Scan disable
6409 20:12:39.350007 == TX Byte 0 ==
6410 20:12:39.353311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 20:12:39.360013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 20:12:39.360098 == TX Byte 1 ==
6413 20:12:39.363002 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 20:12:39.369717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 20:12:39.369799
6416 20:12:39.369863 [DATLAT]
6417 20:12:39.369922 Freq=400, CH0 RK0
6418 20:12:39.369989
6419 20:12:39.373266 DATLAT Default: 0xf
6420 20:12:39.376381 0, 0xFFFF, sum = 0
6421 20:12:39.376464 1, 0xFFFF, sum = 0
6422 20:12:39.379567 2, 0xFFFF, sum = 0
6423 20:12:39.379650 3, 0xFFFF, sum = 0
6424 20:12:39.382688 4, 0xFFFF, sum = 0
6425 20:12:39.382771 5, 0xFFFF, sum = 0
6426 20:12:39.386612 6, 0xFFFF, sum = 0
6427 20:12:39.386695 7, 0xFFFF, sum = 0
6428 20:12:39.389758 8, 0xFFFF, sum = 0
6429 20:12:39.389841 9, 0xFFFF, sum = 0
6430 20:12:39.392732 10, 0xFFFF, sum = 0
6431 20:12:39.392815 11, 0xFFFF, sum = 0
6432 20:12:39.396330 12, 0xFFFF, sum = 0
6433 20:12:39.396413 13, 0x0, sum = 1
6434 20:12:39.399606 14, 0x0, sum = 2
6435 20:12:39.399689 15, 0x0, sum = 3
6436 20:12:39.402619 16, 0x0, sum = 4
6437 20:12:39.402702 best_step = 14
6438 20:12:39.402766
6439 20:12:39.402826 ==
6440 20:12:39.406319 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 20:12:39.413349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 20:12:39.413431 ==
6443 20:12:39.413495 RX Vref Scan: 1
6444 20:12:39.413556
6445 20:12:39.416148 RX Vref 0 -> 0, step: 1
6446 20:12:39.416229
6447 20:12:39.419221 RX Delay -327 -> 252, step: 8
6448 20:12:39.419302
6449 20:12:39.422697 Set Vref, RX VrefLevel [Byte0]: 56
6450 20:12:39.426173 [Byte1]: 50
6451 20:12:39.426255
6452 20:12:39.429341 Final RX Vref Byte 0 = 56 to rank0
6453 20:12:39.432552 Final RX Vref Byte 1 = 50 to rank0
6454 20:12:39.435963 Final RX Vref Byte 0 = 56 to rank1
6455 20:12:39.439324 Final RX Vref Byte 1 = 50 to rank1==
6456 20:12:39.442986 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 20:12:39.445903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 20:12:39.449238 ==
6459 20:12:39.449319 DQS Delay:
6460 20:12:39.449384 DQS0 = 28, DQS1 = 48
6461 20:12:39.452485 DQM Delay:
6462 20:12:39.452567 DQM0 = 12, DQM1 = 14
6463 20:12:39.456059 DQ Delay:
6464 20:12:39.456140 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6465 20:12:39.458930 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6466 20:12:39.462461 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6467 20:12:39.465663 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6468 20:12:39.465744
6469 20:12:39.465807
6470 20:12:39.475683 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
6471 20:12:39.478722 CH0 RK0: MR19=C0C, MR18=B0A7
6472 20:12:39.485653 CH0_RK0: MR19=0xC0C, MR18=0xB0A7, DQSOSC=387, MR23=63, INC=394, DEC=262
6473 20:12:39.485735 ==
6474 20:12:39.488840 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 20:12:39.492485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 20:12:39.492569 ==
6477 20:12:39.495708 [Gating] SW mode calibration
6478 20:12:39.502375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6479 20:12:39.505495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6480 20:12:39.512124 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 20:12:39.515403 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 20:12:39.518803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 20:12:39.525402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 20:12:39.528690 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 20:12:39.531902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 20:12:39.539446 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 20:12:39.541888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 20:12:39.545117 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 20:12:39.548486 Total UI for P1: 0, mck2ui 16
6490 20:12:39.551652 best dqsien dly found for B0: ( 0, 14, 24)
6491 20:12:39.555256 Total UI for P1: 0, mck2ui 16
6492 20:12:39.558384 best dqsien dly found for B1: ( 0, 14, 24)
6493 20:12:39.561861 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6494 20:12:39.565103 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6495 20:12:39.568405
6496 20:12:39.571655 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 20:12:39.575523 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 20:12:39.578256 [Gating] SW calibration Done
6499 20:12:39.578339 ==
6500 20:12:39.581990 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 20:12:39.584975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 20:12:39.585059 ==
6503 20:12:39.585125 RX Vref Scan: 0
6504 20:12:39.585185
6505 20:12:39.588156 RX Vref 0 -> 0, step: 1
6506 20:12:39.588240
6507 20:12:39.591548 RX Delay -410 -> 252, step: 16
6508 20:12:39.595081 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6509 20:12:39.601559 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6510 20:12:39.604690 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6511 20:12:39.608316 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6512 20:12:39.611367 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6513 20:12:39.618194 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6514 20:12:39.621466 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6515 20:12:39.624943 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6516 20:12:39.628140 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6517 20:12:39.634704 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6518 20:12:39.638095 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6519 20:12:39.641523 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6520 20:12:39.644770 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6521 20:12:39.651457 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6522 20:12:39.654801 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6523 20:12:39.657879 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6524 20:12:39.657990 ==
6525 20:12:39.661246 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 20:12:39.667890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 20:12:39.667989 ==
6528 20:12:39.668085 DQS Delay:
6529 20:12:39.671246 DQS0 = 27, DQS1 = 43
6530 20:12:39.671332 DQM Delay:
6531 20:12:39.671398 DQM0 = 9, DQM1 = 15
6532 20:12:39.674699 DQ Delay:
6533 20:12:39.677877 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6534 20:12:39.678024 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6535 20:12:39.681087 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6536 20:12:39.684692 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6537 20:12:39.684794
6538 20:12:39.684885
6539 20:12:39.687595 ==
6540 20:12:39.691296 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 20:12:39.694590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 20:12:39.694663 ==
6543 20:12:39.694743
6544 20:12:39.694830
6545 20:12:39.697726 TX Vref Scan disable
6546 20:12:39.697822 == TX Byte 0 ==
6547 20:12:39.701183 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6548 20:12:39.707600 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6549 20:12:39.707701 == TX Byte 1 ==
6550 20:12:39.711009 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6551 20:12:39.714277 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6552 20:12:39.717774 ==
6553 20:12:39.720983 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 20:12:39.724126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 20:12:39.724227 ==
6556 20:12:39.724318
6557 20:12:39.724404
6558 20:12:39.727686 TX Vref Scan disable
6559 20:12:39.727781 == TX Byte 0 ==
6560 20:12:39.730951 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6561 20:12:39.737741 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6562 20:12:39.737815 == TX Byte 1 ==
6563 20:12:39.741041 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6564 20:12:39.747584 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6565 20:12:39.747712
6566 20:12:39.747822 [DATLAT]
6567 20:12:39.747910 Freq=400, CH0 RK1
6568 20:12:39.747999
6569 20:12:39.750724 DATLAT Default: 0xe
6570 20:12:39.750821 0, 0xFFFF, sum = 0
6571 20:12:39.754156 1, 0xFFFF, sum = 0
6572 20:12:39.754258 2, 0xFFFF, sum = 0
6573 20:12:39.757374 3, 0xFFFF, sum = 0
6574 20:12:39.760614 4, 0xFFFF, sum = 0
6575 20:12:39.760713 5, 0xFFFF, sum = 0
6576 20:12:39.764257 6, 0xFFFF, sum = 0
6577 20:12:39.764351 7, 0xFFFF, sum = 0
6578 20:12:39.767329 8, 0xFFFF, sum = 0
6579 20:12:39.767426 9, 0xFFFF, sum = 0
6580 20:12:39.770692 10, 0xFFFF, sum = 0
6581 20:12:39.770760 11, 0xFFFF, sum = 0
6582 20:12:39.774303 12, 0xFFFF, sum = 0
6583 20:12:39.774369 13, 0x0, sum = 1
6584 20:12:39.777295 14, 0x0, sum = 2
6585 20:12:39.777364 15, 0x0, sum = 3
6586 20:12:39.780854 16, 0x0, sum = 4
6587 20:12:39.780951 best_step = 14
6588 20:12:39.781038
6589 20:12:39.781122 ==
6590 20:12:39.783787 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 20:12:39.787347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 20:12:39.790608 ==
6593 20:12:39.790681 RX Vref Scan: 0
6594 20:12:39.790742
6595 20:12:39.793887 RX Vref 0 -> 0, step: 1
6596 20:12:39.794009
6597 20:12:39.797135 RX Delay -327 -> 252, step: 8
6598 20:12:39.800657 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6599 20:12:39.807524 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6600 20:12:39.810259 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6601 20:12:39.813688 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6602 20:12:39.817019 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6603 20:12:39.824008 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6604 20:12:39.826917 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6605 20:12:39.830160 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6606 20:12:39.834159 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6607 20:12:39.840463 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6608 20:12:39.843437 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6609 20:12:39.847248 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6610 20:12:39.850053 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6611 20:12:39.856714 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6612 20:12:39.860066 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6613 20:12:39.863570 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6614 20:12:39.863668 ==
6615 20:12:39.866716 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 20:12:39.873550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 20:12:39.873650 ==
6618 20:12:39.873740 DQS Delay:
6619 20:12:39.876684 DQS0 = 28, DQS1 = 40
6620 20:12:39.876778 DQM Delay:
6621 20:12:39.876865 DQM0 = 11, DQM1 = 12
6622 20:12:39.880279 DQ Delay:
6623 20:12:39.883270 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6624 20:12:39.886740 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6625 20:12:39.886810 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6626 20:12:39.890125 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =24
6627 20:12:39.893384
6628 20:12:39.893477
6629 20:12:39.900234 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6630 20:12:39.903233 CH0 RK1: MR19=C0C, MR18=B86A
6631 20:12:39.909870 CH0_RK1: MR19=0xC0C, MR18=0xB86A, DQSOSC=386, MR23=63, INC=396, DEC=264
6632 20:12:39.912969 [RxdqsGatingPostProcess] freq 400
6633 20:12:39.916351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6634 20:12:39.919969 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 20:12:39.923521 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 20:12:39.926238 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 20:12:39.929715 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 20:12:39.932903 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 20:12:39.936483 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 20:12:39.939611 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 20:12:39.943071 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 20:12:39.946198 Pre-setting of DQS Precalculation
6643 20:12:39.949614 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6644 20:12:39.949690 ==
6645 20:12:39.952833 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 20:12:39.959542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 20:12:39.959643 ==
6648 20:12:39.963076 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 20:12:39.969537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6650 20:12:39.972744 [CA 0] Center 36 (8~64) winsize 57
6651 20:12:39.976318 [CA 1] Center 36 (8~64) winsize 57
6652 20:12:39.979483 [CA 2] Center 36 (8~64) winsize 57
6653 20:12:39.983212 [CA 3] Center 36 (8~64) winsize 57
6654 20:12:39.986161 [CA 4] Center 36 (8~64) winsize 57
6655 20:12:39.989608 [CA 5] Center 36 (8~64) winsize 57
6656 20:12:39.989679
6657 20:12:39.992690 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6658 20:12:39.992758
6659 20:12:39.996061 [CATrainingPosCal] consider 1 rank data
6660 20:12:39.999512 u2DelayCellTimex100 = 270/100 ps
6661 20:12:40.002610 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 20:12:40.006075 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 20:12:40.009425 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 20:12:40.012860 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 20:12:40.016229 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 20:12:40.019409 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 20:12:40.019476
6668 20:12:40.026478 CA PerBit enable=1, Macro0, CA PI delay=36
6669 20:12:40.026550
6670 20:12:40.026613 [CBTSetCACLKResult] CA Dly = 36
6671 20:12:40.029548 CS Dly: 1 (0~32)
6672 20:12:40.029614 ==
6673 20:12:40.032551 Dram Type= 6, Freq= 0, CH_1, rank 1
6674 20:12:40.035994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 20:12:40.036071 ==
6676 20:12:40.043024 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 20:12:40.049326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6678 20:12:40.052949 [CA 0] Center 36 (8~64) winsize 57
6679 20:12:40.056474 [CA 1] Center 36 (8~64) winsize 57
6680 20:12:40.059279 [CA 2] Center 36 (8~64) winsize 57
6681 20:12:40.062859 [CA 3] Center 36 (8~64) winsize 57
6682 20:12:40.062928 [CA 4] Center 36 (8~64) winsize 57
6683 20:12:40.065764 [CA 5] Center 36 (8~64) winsize 57
6684 20:12:40.065857
6685 20:12:40.072746 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6686 20:12:40.072843
6687 20:12:40.076284 [CATrainingPosCal] consider 2 rank data
6688 20:12:40.079223 u2DelayCellTimex100 = 270/100 ps
6689 20:12:40.082819 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 20:12:40.085851 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 20:12:40.089452 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 20:12:40.092602 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 20:12:40.096198 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 20:12:40.099254 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 20:12:40.099322
6696 20:12:40.102393 CA PerBit enable=1, Macro0, CA PI delay=36
6697 20:12:40.102460
6698 20:12:40.105885 [CBTSetCACLKResult] CA Dly = 36
6699 20:12:40.109092 CS Dly: 1 (0~32)
6700 20:12:40.109158
6701 20:12:40.112596 ----->DramcWriteLeveling(PI) begin...
6702 20:12:40.112664 ==
6703 20:12:40.115707 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 20:12:40.119471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 20:12:40.119540 ==
6706 20:12:40.122305 Write leveling (Byte 0): 40 => 8
6707 20:12:40.125756 Write leveling (Byte 1): 32 => 0
6708 20:12:40.128951 DramcWriteLeveling(PI) end<-----
6709 20:12:40.129018
6710 20:12:40.129079 ==
6711 20:12:40.132519 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 20:12:40.135443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 20:12:40.135511 ==
6714 20:12:40.139083 [Gating] SW mode calibration
6715 20:12:40.145621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6716 20:12:40.152495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6717 20:12:40.155390 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 20:12:40.158622 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 20:12:40.165620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 20:12:40.168936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 20:12:40.171829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 20:12:40.178418 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 20:12:40.181764 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 20:12:40.185360 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 20:12:40.192084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 20:12:40.195224 Total UI for P1: 0, mck2ui 16
6727 20:12:40.198658 best dqsien dly found for B0: ( 0, 14, 24)
6728 20:12:40.201743 Total UI for P1: 0, mck2ui 16
6729 20:12:40.204994 best dqsien dly found for B1: ( 0, 14, 24)
6730 20:12:40.208094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6731 20:12:40.211593 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6732 20:12:40.211660
6733 20:12:40.214831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 20:12:40.218430 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 20:12:40.221393 [Gating] SW calibration Done
6736 20:12:40.221458 ==
6737 20:12:40.224987 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 20:12:40.228031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 20:12:40.228096 ==
6740 20:12:40.231552 RX Vref Scan: 0
6741 20:12:40.231620
6742 20:12:40.234689 RX Vref 0 -> 0, step: 1
6743 20:12:40.234754
6744 20:12:40.234814 RX Delay -410 -> 252, step: 16
6745 20:12:40.241393 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6746 20:12:40.244912 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6747 20:12:40.248125 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6748 20:12:40.251346 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6749 20:12:40.257970 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6750 20:12:40.261560 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6751 20:12:40.264518 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6752 20:12:40.268023 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6753 20:12:40.274502 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6754 20:12:40.278083 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6755 20:12:40.281423 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6756 20:12:40.287731 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6757 20:12:40.291164 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6758 20:12:40.294794 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6759 20:12:40.297718 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6760 20:12:40.304752 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6761 20:12:40.304847 ==
6762 20:12:40.307901 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 20:12:40.311241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 20:12:40.311310 ==
6765 20:12:40.311371 DQS Delay:
6766 20:12:40.314621 DQS0 = 27, DQS1 = 43
6767 20:12:40.314688 DQM Delay:
6768 20:12:40.317648 DQM0 = 6, DQM1 = 17
6769 20:12:40.317740 DQ Delay:
6770 20:12:40.321425 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6771 20:12:40.324475 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6772 20:12:40.327603 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6773 20:12:40.331103 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6774 20:12:40.331174
6775 20:12:40.331236
6776 20:12:40.331293 ==
6777 20:12:40.334685 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 20:12:40.337812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 20:12:40.337905 ==
6780 20:12:40.338011
6781 20:12:40.338069
6782 20:12:40.341297 TX Vref Scan disable
6783 20:12:40.341363 == TX Byte 0 ==
6784 20:12:40.347610 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 20:12:40.350928 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 20:12:40.351028 == TX Byte 1 ==
6787 20:12:40.357826 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6788 20:12:40.360777 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6789 20:12:40.360873 ==
6790 20:12:40.364481 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 20:12:40.367615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 20:12:40.367688 ==
6793 20:12:40.367749
6794 20:12:40.367807
6795 20:12:40.371315 TX Vref Scan disable
6796 20:12:40.374342 == TX Byte 0 ==
6797 20:12:40.377673 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 20:12:40.380979 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 20:12:40.384450 == TX Byte 1 ==
6800 20:12:40.387438 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6801 20:12:40.391124 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6802 20:12:40.391199
6803 20:12:40.391260 [DATLAT]
6804 20:12:40.394437 Freq=400, CH1 RK0
6805 20:12:40.394505
6806 20:12:40.394564 DATLAT Default: 0xf
6807 20:12:40.397925 0, 0xFFFF, sum = 0
6808 20:12:40.398031 1, 0xFFFF, sum = 0
6809 20:12:40.400901 2, 0xFFFF, sum = 0
6810 20:12:40.404339 3, 0xFFFF, sum = 0
6811 20:12:40.404436 4, 0xFFFF, sum = 0
6812 20:12:40.407616 5, 0xFFFF, sum = 0
6813 20:12:40.407713 6, 0xFFFF, sum = 0
6814 20:12:40.410693 7, 0xFFFF, sum = 0
6815 20:12:40.410761 8, 0xFFFF, sum = 0
6816 20:12:40.414019 9, 0xFFFF, sum = 0
6817 20:12:40.414086 10, 0xFFFF, sum = 0
6818 20:12:40.417579 11, 0xFFFF, sum = 0
6819 20:12:40.417675 12, 0xFFFF, sum = 0
6820 20:12:40.420939 13, 0x0, sum = 1
6821 20:12:40.421033 14, 0x0, sum = 2
6822 20:12:40.424180 15, 0x0, sum = 3
6823 20:12:40.424274 16, 0x0, sum = 4
6824 20:12:40.427652 best_step = 14
6825 20:12:40.427720
6826 20:12:40.427780 ==
6827 20:12:40.431168 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 20:12:40.434234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 20:12:40.434300 ==
6830 20:12:40.434359 RX Vref Scan: 1
6831 20:12:40.437190
6832 20:12:40.437254 RX Vref 0 -> 0, step: 1
6833 20:12:40.437311
6834 20:12:40.440729 RX Delay -327 -> 252, step: 8
6835 20:12:40.440820
6836 20:12:40.444062 Set Vref, RX VrefLevel [Byte0]: 52
6837 20:12:40.447125 [Byte1]: 53
6838 20:12:40.451446
6839 20:12:40.451548 Final RX Vref Byte 0 = 52 to rank0
6840 20:12:40.454843 Final RX Vref Byte 1 = 53 to rank0
6841 20:12:40.458196 Final RX Vref Byte 0 = 52 to rank1
6842 20:12:40.461317 Final RX Vref Byte 1 = 53 to rank1==
6843 20:12:40.464720 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 20:12:40.471066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 20:12:40.471139 ==
6846 20:12:40.471203 DQS Delay:
6847 20:12:40.474506 DQS0 = 32, DQS1 = 40
6848 20:12:40.474599 DQM Delay:
6849 20:12:40.474688 DQM0 = 12, DQM1 = 12
6850 20:12:40.478017 DQ Delay:
6851 20:12:40.481040 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6852 20:12:40.481135 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6853 20:12:40.484444 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6854 20:12:40.487946 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6855 20:12:40.488041
6856 20:12:40.488129
6857 20:12:40.497810 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6858 20:12:40.501219 CH1 RK0: MR19=C0C, MR18=99D3
6859 20:12:40.507510 CH1_RK0: MR19=0xC0C, MR18=0x99D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6860 20:12:40.507581 ==
6861 20:12:40.511186 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 20:12:40.514206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 20:12:40.514273 ==
6864 20:12:40.517601 [Gating] SW mode calibration
6865 20:12:40.524415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6866 20:12:40.530967 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6867 20:12:40.534006 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 20:12:40.537284 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 20:12:40.544259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 20:12:40.547367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 20:12:40.551051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 20:12:40.554000 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 20:12:40.560974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 20:12:40.564262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 20:12:40.567338 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 20:12:40.570765 Total UI for P1: 0, mck2ui 16
6877 20:12:40.573850 best dqsien dly found for B0: ( 0, 14, 24)
6878 20:12:40.577469 Total UI for P1: 0, mck2ui 16
6879 20:12:40.580682 best dqsien dly found for B1: ( 0, 14, 24)
6880 20:12:40.583988 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6881 20:12:40.590388 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6882 20:12:40.590465
6883 20:12:40.593791 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 20:12:40.597040 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 20:12:40.600467 [Gating] SW calibration Done
6886 20:12:40.600576 ==
6887 20:12:40.603536 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 20:12:40.607272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 20:12:40.607340 ==
6890 20:12:40.610367 RX Vref Scan: 0
6891 20:12:40.610436
6892 20:12:40.610495 RX Vref 0 -> 0, step: 1
6893 20:12:40.610552
6894 20:12:40.613979 RX Delay -410 -> 252, step: 16
6895 20:12:40.617038 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6896 20:12:40.623989 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6897 20:12:40.626733 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6898 20:12:40.630463 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6899 20:12:40.633877 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6900 20:12:40.640303 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6901 20:12:40.643704 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6902 20:12:40.647232 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6903 20:12:40.650395 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6904 20:12:40.656780 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6905 20:12:40.660331 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6906 20:12:40.663309 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6907 20:12:40.666911 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6908 20:12:40.673358 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6909 20:12:40.676955 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6910 20:12:40.680039 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6911 20:12:40.680136 ==
6912 20:12:40.683321 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 20:12:40.690348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 20:12:40.690433 ==
6915 20:12:40.690503 DQS Delay:
6916 20:12:40.693150 DQS0 = 35, DQS1 = 43
6917 20:12:40.693252 DQM Delay:
6918 20:12:40.693345 DQM0 = 16, DQM1 = 18
6919 20:12:40.696373 DQ Delay:
6920 20:12:40.699808 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6921 20:12:40.703647 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6922 20:12:40.706322 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6923 20:12:40.710149 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6924 20:12:40.710253
6925 20:12:40.710345
6926 20:12:40.710434 ==
6927 20:12:40.713375 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 20:12:40.716300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 20:12:40.716395 ==
6930 20:12:40.716484
6931 20:12:40.716571
6932 20:12:40.719850 TX Vref Scan disable
6933 20:12:40.719941 == TX Byte 0 ==
6934 20:12:40.726631 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6935 20:12:40.729599 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6936 20:12:40.729693 == TX Byte 1 ==
6937 20:12:40.736528 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6938 20:12:40.739505 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6939 20:12:40.739601 ==
6940 20:12:40.742953 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 20:12:40.746457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 20:12:40.746555 ==
6943 20:12:40.746643
6944 20:12:40.746728
6945 20:12:40.749799 TX Vref Scan disable
6946 20:12:40.749894 == TX Byte 0 ==
6947 20:12:40.756200 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6948 20:12:40.759658 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6949 20:12:40.759736 == TX Byte 1 ==
6950 20:12:40.766064 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6951 20:12:40.769297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6952 20:12:40.769395
6953 20:12:40.769486 [DATLAT]
6954 20:12:40.772996 Freq=400, CH1 RK1
6955 20:12:40.773091
6956 20:12:40.773179 DATLAT Default: 0xe
6957 20:12:40.775996 0, 0xFFFF, sum = 0
6958 20:12:40.776067 1, 0xFFFF, sum = 0
6959 20:12:40.779585 2, 0xFFFF, sum = 0
6960 20:12:40.779656 3, 0xFFFF, sum = 0
6961 20:12:40.782944 4, 0xFFFF, sum = 0
6962 20:12:40.783062 5, 0xFFFF, sum = 0
6963 20:12:40.786140 6, 0xFFFF, sum = 0
6964 20:12:40.786225 7, 0xFFFF, sum = 0
6965 20:12:40.789491 8, 0xFFFF, sum = 0
6966 20:12:40.789574 9, 0xFFFF, sum = 0
6967 20:12:40.792591 10, 0xFFFF, sum = 0
6968 20:12:40.792675 11, 0xFFFF, sum = 0
6969 20:12:40.796247 12, 0xFFFF, sum = 0
6970 20:12:40.796330 13, 0x0, sum = 1
6971 20:12:40.799511 14, 0x0, sum = 2
6972 20:12:40.799594 15, 0x0, sum = 3
6973 20:12:40.802826 16, 0x0, sum = 4
6974 20:12:40.802909 best_step = 14
6975 20:12:40.802974
6976 20:12:40.803033 ==
6977 20:12:40.806252 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 20:12:40.812763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 20:12:40.812845 ==
6980 20:12:40.812911 RX Vref Scan: 0
6981 20:12:40.812972
6982 20:12:40.815917 RX Vref 0 -> 0, step: 1
6983 20:12:40.815999
6984 20:12:40.819605 RX Delay -327 -> 252, step: 8
6985 20:12:40.826146 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6986 20:12:40.829571 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6987 20:12:40.832925 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6988 20:12:40.835886 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6989 20:12:40.842822 iDelay=217, Bit 4, Center -20 (-247 ~ 208) 456
6990 20:12:40.846353 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6991 20:12:40.849444 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6992 20:12:40.852765 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6993 20:12:40.859389 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6994 20:12:40.862638 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6995 20:12:40.866089 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6996 20:12:40.869421 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6997 20:12:40.875890 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6998 20:12:40.878960 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6999 20:12:40.882926 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7000 20:12:40.888887 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7001 20:12:40.888970 ==
7002 20:12:40.892640 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 20:12:40.895811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 20:12:40.895894 ==
7005 20:12:40.895959 DQS Delay:
7006 20:12:40.898981 DQS0 = 32, DQS1 = 36
7007 20:12:40.899065 DQM Delay:
7008 20:12:40.902289 DQM0 = 10, DQM1 = 11
7009 20:12:40.902373 DQ Delay:
7010 20:12:40.905684 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7011 20:12:40.908917 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
7012 20:12:40.912481 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7013 20:12:40.915540 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7014 20:12:40.915624
7015 20:12:40.915689
7016 20:12:40.922202 [DQSOSCAuto] RK1, (LSB)MR18= 0xa750, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
7017 20:12:40.925425 CH1 RK1: MR19=C0C, MR18=A750
7018 20:12:40.932032 CH1_RK1: MR19=0xC0C, MR18=0xA750, DQSOSC=389, MR23=63, INC=390, DEC=260
7019 20:12:40.935332 [RxdqsGatingPostProcess] freq 400
7020 20:12:40.942170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7021 20:12:40.942254 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 20:12:40.945303 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 20:12:40.948769 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 20:12:40.952287 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 20:12:40.955164 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 20:12:40.958742 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 20:12:40.961748 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 20:12:40.965615 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 20:12:40.968748 Pre-setting of DQS Precalculation
7030 20:12:40.975048 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7031 20:12:40.981902 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7032 20:12:40.988325 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7033 20:12:40.988410
7034 20:12:40.988476
7035 20:12:40.991993 [Calibration Summary] 800 Mbps
7036 20:12:40.992076 CH 0, Rank 0
7037 20:12:40.995211 SW Impedance : PASS
7038 20:12:40.995294 DUTY Scan : NO K
7039 20:12:40.998384 ZQ Calibration : PASS
7040 20:12:41.001843 Jitter Meter : NO K
7041 20:12:41.001927 CBT Training : PASS
7042 20:12:41.004919 Write leveling : PASS
7043 20:12:41.008351 RX DQS gating : PASS
7044 20:12:41.008436 RX DQ/DQS(RDDQC) : PASS
7045 20:12:41.011789 TX DQ/DQS : PASS
7046 20:12:41.015385 RX DATLAT : PASS
7047 20:12:41.015469 RX DQ/DQS(Engine): PASS
7048 20:12:41.018516 TX OE : NO K
7049 20:12:41.018600 All Pass.
7050 20:12:41.018666
7051 20:12:41.021621 CH 0, Rank 1
7052 20:12:41.021705 SW Impedance : PASS
7053 20:12:41.025360 DUTY Scan : NO K
7054 20:12:41.028370 ZQ Calibration : PASS
7055 20:12:41.028454 Jitter Meter : NO K
7056 20:12:41.031940 CBT Training : PASS
7057 20:12:41.034967 Write leveling : NO K
7058 20:12:41.035050 RX DQS gating : PASS
7059 20:12:41.038412 RX DQ/DQS(RDDQC) : PASS
7060 20:12:41.038496 TX DQ/DQS : PASS
7061 20:12:41.041847 RX DATLAT : PASS
7062 20:12:41.045081 RX DQ/DQS(Engine): PASS
7063 20:12:41.045164 TX OE : NO K
7064 20:12:41.048562 All Pass.
7065 20:12:41.048648
7066 20:12:41.048714 CH 1, Rank 0
7067 20:12:41.052063 SW Impedance : PASS
7068 20:12:41.052147 DUTY Scan : NO K
7069 20:12:41.055166 ZQ Calibration : PASS
7070 20:12:41.058371 Jitter Meter : NO K
7071 20:12:41.058455 CBT Training : PASS
7072 20:12:41.061960 Write leveling : PASS
7073 20:12:41.065224 RX DQS gating : PASS
7074 20:12:41.065308 RX DQ/DQS(RDDQC) : PASS
7075 20:12:41.068431 TX DQ/DQS : PASS
7076 20:12:41.071467 RX DATLAT : PASS
7077 20:12:41.071551 RX DQ/DQS(Engine): PASS
7078 20:12:41.075066 TX OE : NO K
7079 20:12:41.075137 All Pass.
7080 20:12:41.075198
7081 20:12:41.078376 CH 1, Rank 1
7082 20:12:41.078450 SW Impedance : PASS
7083 20:12:41.081486 DUTY Scan : NO K
7084 20:12:41.084720 ZQ Calibration : PASS
7085 20:12:41.084796 Jitter Meter : NO K
7086 20:12:41.088116 CBT Training : PASS
7087 20:12:41.088184 Write leveling : NO K
7088 20:12:41.091629 RX DQS gating : PASS
7089 20:12:41.094767 RX DQ/DQS(RDDQC) : PASS
7090 20:12:41.094835 TX DQ/DQS : PASS
7091 20:12:41.098164 RX DATLAT : PASS
7092 20:12:41.101365 RX DQ/DQS(Engine): PASS
7093 20:12:41.101430 TX OE : NO K
7094 20:12:41.104709 All Pass.
7095 20:12:41.104778
7096 20:12:41.104837 DramC Write-DBI off
7097 20:12:41.108138 PER_BANK_REFRESH: Hybrid Mode
7098 20:12:41.111578 TX_TRACKING: ON
7099 20:12:41.118521 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7100 20:12:41.121815 [FAST_K] Save calibration result to emmc
7101 20:12:41.124859 dramc_set_vcore_voltage set vcore to 725000
7102 20:12:41.128406 Read voltage for 1600, 0
7103 20:12:41.128473 Vio18 = 0
7104 20:12:41.131765 Vcore = 725000
7105 20:12:41.131834 Vdram = 0
7106 20:12:41.131893 Vddq = 0
7107 20:12:41.135116 Vmddr = 0
7108 20:12:41.138165 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7109 20:12:41.144712 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7110 20:12:41.144789 MEM_TYPE=3, freq_sel=13
7111 20:12:41.148325 sv_algorithm_assistance_LP4_3733
7112 20:12:41.154820 ============ PULL DRAM RESETB DOWN ============
7113 20:12:41.158023 ========== PULL DRAM RESETB DOWN end =========
7114 20:12:41.161483 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7115 20:12:41.164709 ===================================
7116 20:12:41.167866 LPDDR4 DRAM CONFIGURATION
7117 20:12:41.171235 ===================================
7118 20:12:41.174713 EX_ROW_EN[0] = 0x0
7119 20:12:41.174787 EX_ROW_EN[1] = 0x0
7120 20:12:41.178112 LP4Y_EN = 0x0
7121 20:12:41.178183 WORK_FSP = 0x1
7122 20:12:41.181587 WL = 0x5
7123 20:12:41.181662 RL = 0x5
7124 20:12:41.184676 BL = 0x2
7125 20:12:41.184750 RPST = 0x0
7126 20:12:41.188158 RD_PRE = 0x0
7127 20:12:41.188232 WR_PRE = 0x1
7128 20:12:41.191554 WR_PST = 0x1
7129 20:12:41.191625 DBI_WR = 0x0
7130 20:12:41.194833 DBI_RD = 0x0
7131 20:12:41.194904 OTF = 0x1
7132 20:12:41.198141 ===================================
7133 20:12:41.201628 ===================================
7134 20:12:41.204741 ANA top config
7135 20:12:41.208347 ===================================
7136 20:12:41.208419 DLL_ASYNC_EN = 0
7137 20:12:41.211397 ALL_SLAVE_EN = 0
7138 20:12:41.214762 NEW_RANK_MODE = 1
7139 20:12:41.218211 DLL_IDLE_MODE = 1
7140 20:12:41.221420 LP45_APHY_COMB_EN = 1
7141 20:12:41.221490 TX_ODT_DIS = 0
7142 20:12:41.224645 NEW_8X_MODE = 1
7143 20:12:41.228130 ===================================
7144 20:12:41.231437 ===================================
7145 20:12:41.234561 data_rate = 3200
7146 20:12:41.237795 CKR = 1
7147 20:12:41.241153 DQ_P2S_RATIO = 8
7148 20:12:41.244774 ===================================
7149 20:12:41.244846 CA_P2S_RATIO = 8
7150 20:12:41.247806 DQ_CA_OPEN = 0
7151 20:12:41.251514 DQ_SEMI_OPEN = 0
7152 20:12:41.254797 CA_SEMI_OPEN = 0
7153 20:12:41.257886 CA_FULL_RATE = 0
7154 20:12:41.261597 DQ_CKDIV4_EN = 0
7155 20:12:41.261673 CA_CKDIV4_EN = 0
7156 20:12:41.264412 CA_PREDIV_EN = 0
7157 20:12:41.268010 PH8_DLY = 12
7158 20:12:41.271323 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7159 20:12:41.274560 DQ_AAMCK_DIV = 4
7160 20:12:41.277703 CA_AAMCK_DIV = 4
7161 20:12:41.277775 CA_ADMCK_DIV = 4
7162 20:12:41.281145 DQ_TRACK_CA_EN = 0
7163 20:12:41.284701 CA_PICK = 1600
7164 20:12:41.287883 CA_MCKIO = 1600
7165 20:12:41.291069 MCKIO_SEMI = 0
7166 20:12:41.294569 PLL_FREQ = 3068
7167 20:12:41.297839 DQ_UI_PI_RATIO = 32
7168 20:12:41.297930 CA_UI_PI_RATIO = 0
7169 20:12:41.301192 ===================================
7170 20:12:41.304852 ===================================
7171 20:12:41.307952 memory_type:LPDDR4
7172 20:12:41.311295 GP_NUM : 10
7173 20:12:41.311372 SRAM_EN : 1
7174 20:12:41.314434 MD32_EN : 0
7175 20:12:41.317805 ===================================
7176 20:12:41.321014 [ANA_INIT] >>>>>>>>>>>>>>
7177 20:12:41.324546 <<<<<< [CONFIGURE PHASE]: ANA_TX
7178 20:12:41.328194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7179 20:12:41.331255 ===================================
7180 20:12:41.331330 data_rate = 3200,PCW = 0X7600
7181 20:12:41.334636 ===================================
7182 20:12:41.337648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7183 20:12:41.344392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 20:12:41.351222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 20:12:41.354320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7186 20:12:41.357716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7187 20:12:41.361256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7188 20:12:41.364264 [ANA_INIT] flow start
7189 20:12:41.367566 [ANA_INIT] PLL >>>>>>>>
7190 20:12:41.367639 [ANA_INIT] PLL <<<<<<<<
7191 20:12:41.371043 [ANA_INIT] MIDPI >>>>>>>>
7192 20:12:41.374321 [ANA_INIT] MIDPI <<<<<<<<
7193 20:12:41.374392 [ANA_INIT] DLL >>>>>>>>
7194 20:12:41.377713 [ANA_INIT] DLL <<<<<<<<
7195 20:12:41.380884 [ANA_INIT] flow end
7196 20:12:41.384721 ============ LP4 DIFF to SE enter ============
7197 20:12:41.387677 ============ LP4 DIFF to SE exit ============
7198 20:12:41.391347 [ANA_INIT] <<<<<<<<<<<<<
7199 20:12:41.394555 [Flow] Enable top DCM control >>>>>
7200 20:12:41.397782 [Flow] Enable top DCM control <<<<<
7201 20:12:41.401235 Enable DLL master slave shuffle
7202 20:12:41.404359 ==============================================================
7203 20:12:41.407984 Gating Mode config
7204 20:12:41.411119 ==============================================================
7205 20:12:41.414592 Config description:
7206 20:12:41.424260 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7207 20:12:41.431454 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7208 20:12:41.434176 SELPH_MODE 0: By rank 1: By Phase
7209 20:12:41.441150 ==============================================================
7210 20:12:41.444109 GAT_TRACK_EN = 1
7211 20:12:41.447678 RX_GATING_MODE = 2
7212 20:12:41.451210 RX_GATING_TRACK_MODE = 2
7213 20:12:41.454469 SELPH_MODE = 1
7214 20:12:41.457824 PICG_EARLY_EN = 1
7215 20:12:41.457914 VALID_LAT_VALUE = 1
7216 20:12:41.464113 ==============================================================
7217 20:12:41.467627 Enter into Gating configuration >>>>
7218 20:12:41.470968 Exit from Gating configuration <<<<
7219 20:12:41.474490 Enter into DVFS_PRE_config >>>>>
7220 20:12:41.484395 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7221 20:12:41.487543 Exit from DVFS_PRE_config <<<<<
7222 20:12:41.490899 Enter into PICG configuration >>>>
7223 20:12:41.494032 Exit from PICG configuration <<<<
7224 20:12:41.497269 [RX_INPUT] configuration >>>>>
7225 20:12:41.500537 [RX_INPUT] configuration <<<<<
7226 20:12:41.504119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7227 20:12:41.510608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7228 20:12:41.517228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 20:12:41.523912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 20:12:41.530507 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 20:12:41.537435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 20:12:41.540502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7233 20:12:41.543732 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7234 20:12:41.546917 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7235 20:12:41.553614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7236 20:12:41.557417 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7237 20:12:41.560253 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 20:12:41.563803 ===================================
7239 20:12:41.567122 LPDDR4 DRAM CONFIGURATION
7240 20:12:41.570953 ===================================
7241 20:12:41.571026 EX_ROW_EN[0] = 0x0
7242 20:12:41.573766 EX_ROW_EN[1] = 0x0
7243 20:12:41.573835 LP4Y_EN = 0x0
7244 20:12:41.576838 WORK_FSP = 0x1
7245 20:12:41.576911 WL = 0x5
7246 20:12:41.580333 RL = 0x5
7247 20:12:41.580407 BL = 0x2
7248 20:12:41.583677 RPST = 0x0
7249 20:12:41.586922 RD_PRE = 0x0
7250 20:12:41.586998 WR_PRE = 0x1
7251 20:12:41.590170 WR_PST = 0x1
7252 20:12:41.590243 DBI_WR = 0x0
7253 20:12:41.593802 DBI_RD = 0x0
7254 20:12:41.593876 OTF = 0x1
7255 20:12:41.597169 ===================================
7256 20:12:41.600493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7257 20:12:41.603652 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7258 20:12:41.610580 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 20:12:41.613628 ===================================
7260 20:12:41.617395 LPDDR4 DRAM CONFIGURATION
7261 20:12:41.620177 ===================================
7262 20:12:41.620249 EX_ROW_EN[0] = 0x10
7263 20:12:41.623808 EX_ROW_EN[1] = 0x0
7264 20:12:41.623881 LP4Y_EN = 0x0
7265 20:12:41.626856 WORK_FSP = 0x1
7266 20:12:41.626927 WL = 0x5
7267 20:12:41.630175 RL = 0x5
7268 20:12:41.630245 BL = 0x2
7269 20:12:41.633770 RPST = 0x0
7270 20:12:41.633839 RD_PRE = 0x0
7271 20:12:41.636767 WR_PRE = 0x1
7272 20:12:41.636835 WR_PST = 0x1
7273 20:12:41.640381 DBI_WR = 0x0
7274 20:12:41.640451 DBI_RD = 0x0
7275 20:12:41.643674 OTF = 0x1
7276 20:12:41.646714 ===================================
7277 20:12:41.653731 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7278 20:12:41.653807 ==
7279 20:12:41.657007 Dram Type= 6, Freq= 0, CH_0, rank 0
7280 20:12:41.660182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 20:12:41.660256 ==
7282 20:12:41.663243 [Duty_Offset_Calibration]
7283 20:12:41.663314 B0:2 B1:0 CA:1
7284 20:12:41.663377
7285 20:12:41.666964 [DutyScan_Calibration_Flow] k_type=0
7286 20:12:41.677298
7287 20:12:41.677372 ==CLK 0==
7288 20:12:41.680395 Final CLK duty delay cell = -4
7289 20:12:41.683801 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7290 20:12:41.687375 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7291 20:12:41.690570 [-4] AVG Duty = 4922%(X100)
7292 20:12:41.690647
7293 20:12:41.693758 CH0 CLK Duty spec in!! Max-Min= 218%
7294 20:12:41.697070 [DutyScan_Calibration_Flow] ====Done====
7295 20:12:41.697145
7296 20:12:41.700414 [DutyScan_Calibration_Flow] k_type=1
7297 20:12:41.716454
7298 20:12:41.716537 ==DQS 0 ==
7299 20:12:41.719933 Final DQS duty delay cell = 0
7300 20:12:41.723728 [0] MAX Duty = 5249%(X100), DQS PI = 32
7301 20:12:41.726577 [0] MIN Duty = 4969%(X100), DQS PI = 0
7302 20:12:41.726671 [0] AVG Duty = 5109%(X100)
7303 20:12:41.730195
7304 20:12:41.730297 ==DQS 1 ==
7305 20:12:41.733599 Final DQS duty delay cell = -4
7306 20:12:41.736792 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7307 20:12:41.739912 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7308 20:12:41.743361 [-4] AVG Duty = 4969%(X100)
7309 20:12:41.743444
7310 20:12:41.747043 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7311 20:12:41.747127
7312 20:12:41.750243 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7313 20:12:41.753469 [DutyScan_Calibration_Flow] ====Done====
7314 20:12:41.753554
7315 20:12:41.756678 [DutyScan_Calibration_Flow] k_type=3
7316 20:12:41.774110
7317 20:12:41.774287 ==DQM 0 ==
7318 20:12:41.777668 Final DQM duty delay cell = 0
7319 20:12:41.780798 [0] MAX Duty = 5124%(X100), DQS PI = 26
7320 20:12:41.784516 [0] MIN Duty = 4813%(X100), DQS PI = 50
7321 20:12:41.784600 [0] AVG Duty = 4968%(X100)
7322 20:12:41.787490
7323 20:12:41.787574 ==DQM 1 ==
7324 20:12:41.791018 Final DQM duty delay cell = 0
7325 20:12:41.794265 [0] MAX Duty = 5249%(X100), DQS PI = 28
7326 20:12:41.797227 [0] MIN Duty = 5031%(X100), DQS PI = 6
7327 20:12:41.800509 [0] AVG Duty = 5140%(X100)
7328 20:12:41.800593
7329 20:12:41.803933 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7330 20:12:41.804018
7331 20:12:41.807603 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7332 20:12:41.810886 [DutyScan_Calibration_Flow] ====Done====
7333 20:12:41.810969
7334 20:12:41.814144 [DutyScan_Calibration_Flow] k_type=2
7335 20:12:41.831407
7336 20:12:41.831490 ==DQ 0 ==
7337 20:12:41.834523 Final DQ duty delay cell = 0
7338 20:12:41.837864 [0] MAX Duty = 5124%(X100), DQS PI = 34
7339 20:12:41.841186 [0] MIN Duty = 5000%(X100), DQS PI = 2
7340 20:12:41.841270 [0] AVG Duty = 5062%(X100)
7341 20:12:41.841337
7342 20:12:41.844607 ==DQ 1 ==
7343 20:12:41.848021 Final DQ duty delay cell = 0
7344 20:12:41.851683 [0] MAX Duty = 4969%(X100), DQS PI = 52
7345 20:12:41.854821 [0] MIN Duty = 4875%(X100), DQS PI = 0
7346 20:12:41.854905 [0] AVG Duty = 4922%(X100)
7347 20:12:41.854971
7348 20:12:41.858022 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7349 20:12:41.858136
7350 20:12:41.861015 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7351 20:12:41.867874 [DutyScan_Calibration_Flow] ====Done====
7352 20:12:41.867958 ==
7353 20:12:41.871269 Dram Type= 6, Freq= 0, CH_1, rank 0
7354 20:12:41.874419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 20:12:41.874504 ==
7356 20:12:41.877751 [Duty_Offset_Calibration]
7357 20:12:41.877865 B0:0 B1:-1 CA:2
7358 20:12:41.877966
7359 20:12:41.881193 [DutyScan_Calibration_Flow] k_type=0
7360 20:12:41.891254
7361 20:12:41.891341 ==CLK 0==
7362 20:12:41.894753 Final CLK duty delay cell = 0
7363 20:12:41.898149 [0] MAX Duty = 5156%(X100), DQS PI = 12
7364 20:12:41.901286 [0] MIN Duty = 4906%(X100), DQS PI = 46
7365 20:12:41.904648 [0] AVG Duty = 5031%(X100)
7366 20:12:41.904729
7367 20:12:41.907860 CH1 CLK Duty spec in!! Max-Min= 250%
7368 20:12:41.911431 [DutyScan_Calibration_Flow] ====Done====
7369 20:12:41.911513
7370 20:12:41.914325 [DutyScan_Calibration_Flow] k_type=1
7371 20:12:41.931055
7372 20:12:41.931136 ==DQS 0 ==
7373 20:12:41.934557 Final DQS duty delay cell = 0
7374 20:12:41.937639 [0] MAX Duty = 5124%(X100), DQS PI = 26
7375 20:12:41.941109 [0] MIN Duty = 4969%(X100), DQS PI = 2
7376 20:12:41.941192 [0] AVG Duty = 5046%(X100)
7377 20:12:41.944466
7378 20:12:41.944547 ==DQS 1 ==
7379 20:12:41.947973 Final DQS duty delay cell = 0
7380 20:12:41.951225 [0] MAX Duty = 5187%(X100), DQS PI = 0
7381 20:12:41.954415 [0] MIN Duty = 4844%(X100), DQS PI = 34
7382 20:12:41.957640 [0] AVG Duty = 5015%(X100)
7383 20:12:41.957721
7384 20:12:41.960910 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7385 20:12:41.960993
7386 20:12:41.964296 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7387 20:12:41.967644 [DutyScan_Calibration_Flow] ====Done====
7388 20:12:41.967726
7389 20:12:41.970948 [DutyScan_Calibration_Flow] k_type=3
7390 20:12:41.988744
7391 20:12:41.988827 ==DQM 0 ==
7392 20:12:41.992108 Final DQM duty delay cell = 4
7393 20:12:41.995125 [4] MAX Duty = 5125%(X100), DQS PI = 8
7394 20:12:41.998643 [4] MIN Duty = 5000%(X100), DQS PI = 34
7395 20:12:41.998725 [4] AVG Duty = 5062%(X100)
7396 20:12:42.001977
7397 20:12:42.002059 ==DQM 1 ==
7398 20:12:42.005200 Final DQM duty delay cell = 0
7399 20:12:42.008892 [0] MAX Duty = 5281%(X100), DQS PI = 60
7400 20:12:42.011912 [0] MIN Duty = 4876%(X100), DQS PI = 34
7401 20:12:42.011994 [0] AVG Duty = 5078%(X100)
7402 20:12:42.015316
7403 20:12:42.018531 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7404 20:12:42.018613
7405 20:12:42.022172 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7406 20:12:42.025167 [DutyScan_Calibration_Flow] ====Done====
7407 20:12:42.025249
7408 20:12:42.028588 [DutyScan_Calibration_Flow] k_type=2
7409 20:12:42.045460
7410 20:12:42.045541 ==DQ 0 ==
7411 20:12:42.048982 Final DQ duty delay cell = 0
7412 20:12:42.052260 [0] MAX Duty = 5062%(X100), DQS PI = 18
7413 20:12:42.055508 [0] MIN Duty = 4969%(X100), DQS PI = 2
7414 20:12:42.055590 [0] AVG Duty = 5015%(X100)
7415 20:12:42.058801
7416 20:12:42.058883 ==DQ 1 ==
7417 20:12:42.062198 Final DQ duty delay cell = 0
7418 20:12:42.065473 [0] MAX Duty = 5062%(X100), DQS PI = 2
7419 20:12:42.068641 [0] MIN Duty = 4813%(X100), DQS PI = 34
7420 20:12:42.068725 [0] AVG Duty = 4937%(X100)
7421 20:12:42.068791
7422 20:12:42.072384 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7423 20:12:42.072469
7424 20:12:42.075810 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7425 20:12:42.082289 [DutyScan_Calibration_Flow] ====Done====
7426 20:12:42.085254 nWR fixed to 30
7427 20:12:42.085339 [ModeRegInit_LP4] CH0 RK0
7428 20:12:42.088929 [ModeRegInit_LP4] CH0 RK1
7429 20:12:42.091789 [ModeRegInit_LP4] CH1 RK0
7430 20:12:42.091874 [ModeRegInit_LP4] CH1 RK1
7431 20:12:42.095503 match AC timing 5
7432 20:12:42.098885 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7433 20:12:42.101829 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7434 20:12:42.108545 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7435 20:12:42.112112 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7436 20:12:42.118455 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7437 20:12:42.118539 [MiockJmeterHQA]
7438 20:12:42.118604
7439 20:12:42.121987 [DramcMiockJmeter] u1RxGatingPI = 0
7440 20:12:42.125190 0 : 4257, 4029
7441 20:12:42.125275 4 : 4252, 4027
7442 20:12:42.125343 8 : 4252, 4027
7443 20:12:42.128688 12 : 4253, 4029
7444 20:12:42.128773 16 : 4252, 4027
7445 20:12:42.131876 20 : 4363, 4137
7446 20:12:42.131961 24 : 4361, 4137
7447 20:12:42.135457 28 : 4253, 4027
7448 20:12:42.135542 32 : 4252, 4027
7449 20:12:42.135610 36 : 4252, 4027
7450 20:12:42.138643 40 : 4250, 4027
7451 20:12:42.138728 44 : 4255, 4029
7452 20:12:42.141935 48 : 4361, 4137
7453 20:12:42.142024 52 : 4250, 4027
7454 20:12:42.145129 56 : 4250, 4027
7455 20:12:42.145206 60 : 4250, 4027
7456 20:12:42.148192 64 : 4253, 4029
7457 20:12:42.148265 68 : 4250, 4027
7458 20:12:42.148327 72 : 4361, 4137
7459 20:12:42.151688 76 : 4361, 4137
7460 20:12:42.151762 80 : 4250, 4027
7461 20:12:42.155132 84 : 4250, 4026
7462 20:12:42.155205 88 : 4250, 3275
7463 20:12:42.158328 92 : 4249, 0
7464 20:12:42.158404 96 : 4250, 0
7465 20:12:42.158465 100 : 4250, 0
7466 20:12:42.162241 104 : 4250, 0
7467 20:12:42.162315 108 : 4361, 0
7468 20:12:42.165036 112 : 4360, 0
7469 20:12:42.165111 116 : 4250, 0
7470 20:12:42.165177 120 : 4360, 0
7471 20:12:42.168545 124 : 4361, 0
7472 20:12:42.168619 128 : 4250, 0
7473 20:12:42.168680 132 : 4250, 0
7474 20:12:42.171507 136 : 4249, 0
7475 20:12:42.171577 140 : 4250, 0
7476 20:12:42.175130 144 : 4250, 0
7477 20:12:42.175201 148 : 4250, 0
7478 20:12:42.175261 152 : 4250, 0
7479 20:12:42.178570 156 : 4252, 0
7480 20:12:42.178646 160 : 4250, 0
7481 20:12:42.181745 164 : 4250, 0
7482 20:12:42.181821 168 : 4363, 0
7483 20:12:42.181887 172 : 4360, 0
7484 20:12:42.185122 176 : 4361, 0
7485 20:12:42.185200 180 : 4250, 0
7486 20:12:42.185263 184 : 4250, 0
7487 20:12:42.188816 188 : 4250, 0
7488 20:12:42.188896 192 : 4250, 0
7489 20:12:42.191959 196 : 4252, 0
7490 20:12:42.192032 200 : 4252, 12
7491 20:12:42.195318 204 : 4250, 2558
7492 20:12:42.195394 208 : 4360, 4138
7493 20:12:42.195456 212 : 4250, 4027
7494 20:12:42.198392 216 : 4250, 4026
7495 20:12:42.198463 220 : 4363, 4139
7496 20:12:42.201767 224 : 4250, 4027
7497 20:12:42.201838 228 : 4250, 4027
7498 20:12:42.205114 232 : 4250, 4026
7499 20:12:42.205187 236 : 4253, 4029
7500 20:12:42.208456 240 : 4250, 4027
7501 20:12:42.208527 244 : 4250, 4027
7502 20:12:42.211704 248 : 4361, 4137
7503 20:12:42.211775 252 : 4250, 4026
7504 20:12:42.214716 256 : 4250, 4027
7505 20:12:42.214786 260 : 4360, 4138
7506 20:12:42.218269 264 : 4250, 4027
7507 20:12:42.218340 268 : 4252, 4027
7508 20:12:42.221312 272 : 4363, 4139
7509 20:12:42.221383 276 : 4250, 4027
7510 20:12:42.221447 280 : 4250, 4027
7511 20:12:42.224745 284 : 4252, 4026
7512 20:12:42.224820 288 : 4252, 4029
7513 20:12:42.228051 292 : 4250, 4027
7514 20:12:42.228123 296 : 4250, 4027
7515 20:12:42.231608 300 : 4361, 4137
7516 20:12:42.231681 304 : 4250, 4026
7517 20:12:42.234548 308 : 4250, 4027
7518 20:12:42.234618 312 : 4360, 3920
7519 20:12:42.238189 316 : 4253, 1748
7520 20:12:42.238259
7521 20:12:42.238319 MIOCK jitter meter ch=0
7522 20:12:42.238377
7523 20:12:42.241513 1T = (316-92) = 224 dly cells
7524 20:12:42.248310 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7525 20:12:42.248387 ==
7526 20:12:42.251247 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 20:12:42.254542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 20:12:42.254617 ==
7529 20:12:42.261037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 20:12:42.264726 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 20:12:42.268457 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 20:12:42.274622 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 20:12:42.284323 [CA 0] Center 43 (13~73) winsize 61
7534 20:12:42.287735 [CA 1] Center 43 (13~73) winsize 61
7535 20:12:42.290880 [CA 2] Center 38 (8~68) winsize 61
7536 20:12:42.294418 [CA 3] Center 37 (8~67) winsize 60
7537 20:12:42.297694 [CA 4] Center 36 (6~66) winsize 61
7538 20:12:42.300750 [CA 5] Center 35 (5~65) winsize 61
7539 20:12:42.300827
7540 20:12:42.304298 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 20:12:42.304372
7542 20:12:42.307843 [CATrainingPosCal] consider 1 rank data
7543 20:12:42.311253 u2DelayCellTimex100 = 290/100 ps
7544 20:12:42.314340 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7545 20:12:42.320846 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7546 20:12:42.324239 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7547 20:12:42.327557 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7548 20:12:42.330842 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7549 20:12:42.334243 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7550 20:12:42.334314
7551 20:12:42.337535 CA PerBit enable=1, Macro0, CA PI delay=35
7552 20:12:42.337605
7553 20:12:42.340719 [CBTSetCACLKResult] CA Dly = 35
7554 20:12:42.344242 CS Dly: 9 (0~40)
7555 20:12:42.347753 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 20:12:42.351036 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 20:12:42.351108 ==
7558 20:12:42.354244 Dram Type= 6, Freq= 0, CH_0, rank 1
7559 20:12:42.357772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 20:12:42.357844 ==
7561 20:12:42.364266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7562 20:12:42.367751 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7563 20:12:42.374311 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7564 20:12:42.377388 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7565 20:12:42.387480 [CA 0] Center 43 (13~74) winsize 62
7566 20:12:42.391203 [CA 1] Center 43 (14~73) winsize 60
7567 20:12:42.394429 [CA 2] Center 38 (9~68) winsize 60
7568 20:12:42.397872 [CA 3] Center 38 (9~68) winsize 60
7569 20:12:42.401064 [CA 4] Center 37 (7~67) winsize 61
7570 20:12:42.404359 [CA 5] Center 36 (7~66) winsize 60
7571 20:12:42.404434
7572 20:12:42.407576 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7573 20:12:42.407653
7574 20:12:42.411096 [CATrainingPosCal] consider 2 rank data
7575 20:12:42.414551 u2DelayCellTimex100 = 290/100 ps
7576 20:12:42.417594 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7577 20:12:42.424489 CA1 delay=43 (14~73),Diff = 7 PI (23 cell)
7578 20:12:42.427639 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7579 20:12:42.431023 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7580 20:12:42.434259 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7581 20:12:42.437338 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7582 20:12:42.437413
7583 20:12:42.441060 CA PerBit enable=1, Macro0, CA PI delay=36
7584 20:12:42.441138
7585 20:12:42.444241 [CBTSetCACLKResult] CA Dly = 36
7586 20:12:42.447701 CS Dly: 10 (0~43)
7587 20:12:42.450792 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7588 20:12:42.454128 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7589 20:12:42.454201
7590 20:12:42.457337 ----->DramcWriteLeveling(PI) begin...
7591 20:12:42.457417 ==
7592 20:12:42.460802 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 20:12:42.464275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 20:12:42.467483 ==
7595 20:12:42.467556 Write leveling (Byte 0): 36 => 36
7596 20:12:42.470568 Write leveling (Byte 1): 30 => 30
7597 20:12:42.473952 DramcWriteLeveling(PI) end<-----
7598 20:12:42.474025
7599 20:12:42.474086 ==
7600 20:12:42.477387 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 20:12:42.484122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 20:12:42.484199 ==
7603 20:12:42.484263 [Gating] SW mode calibration
7604 20:12:42.494332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7605 20:12:42.497601 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7606 20:12:42.504130 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 20:12:42.507175 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 20:12:42.510841 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7609 20:12:42.513816 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7610 20:12:42.520533 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7611 20:12:42.524163 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7612 20:12:42.527167 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 20:12:42.533950 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 20:12:42.537643 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 20:12:42.540687 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 20:12:42.547134 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7617 20:12:42.550638 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7618 20:12:42.554143 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7619 20:12:42.560895 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7620 20:12:42.563924 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 20:12:42.567392 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 20:12:42.573818 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 20:12:42.577522 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 20:12:42.580326 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7625 20:12:42.587573 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7626 20:12:42.590281 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7627 20:12:42.593658 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 20:12:42.600584 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 20:12:42.604083 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 20:12:42.607250 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 20:12:42.613858 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 20:12:42.616865 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7633 20:12:42.620530 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 20:12:42.626825 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7635 20:12:42.630559 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 20:12:42.633764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 20:12:42.636929 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 20:12:42.644074 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 20:12:42.646905 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 20:12:42.650566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 20:12:42.657070 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 20:12:42.660568 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 20:12:42.663763 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 20:12:42.670700 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 20:12:42.673607 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 20:12:42.677135 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 20:12:42.683818 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 20:12:42.686989 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 20:12:42.690210 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7650 20:12:42.696670 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 20:12:42.696749 Total UI for P1: 0, mck2ui 16
7652 20:12:42.703817 best dqsien dly found for B0: ( 1, 9, 10)
7653 20:12:42.706859 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7654 20:12:42.710191 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 20:12:42.713353 Total UI for P1: 0, mck2ui 16
7656 20:12:42.717071 best dqsien dly found for B1: ( 1, 9, 18)
7657 20:12:42.720052 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7658 20:12:42.723516 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7659 20:12:42.723588
7660 20:12:42.730381 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7661 20:12:42.733550 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7662 20:12:42.733621 [Gating] SW calibration Done
7663 20:12:42.736654 ==
7664 20:12:42.740343 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 20:12:42.743629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 20:12:42.743705 ==
7667 20:12:42.743771 RX Vref Scan: 0
7668 20:12:42.743830
7669 20:12:42.746973 RX Vref 0 -> 0, step: 1
7670 20:12:42.747047
7671 20:12:42.750104 RX Delay 0 -> 252, step: 8
7672 20:12:42.753754 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7673 20:12:42.756642 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7674 20:12:42.760477 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7675 20:12:42.763608 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7676 20:12:42.770019 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7677 20:12:42.773672 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7678 20:12:42.776802 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7679 20:12:42.779943 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7680 20:12:42.783635 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7681 20:12:42.789932 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7682 20:12:42.793300 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7683 20:12:42.796536 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7684 20:12:42.800087 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7685 20:12:42.806970 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7686 20:12:42.809875 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7687 20:12:42.813451 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7688 20:12:42.813534 ==
7689 20:12:42.817057 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 20:12:42.820024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 20:12:42.820108 ==
7692 20:12:42.823420 DQS Delay:
7693 20:12:42.823502 DQS0 = 0, DQS1 = 0
7694 20:12:42.823568 DQM Delay:
7695 20:12:42.826734 DQM0 = 137, DQM1 = 127
7696 20:12:42.826817 DQ Delay:
7697 20:12:42.830095 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7698 20:12:42.833598 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7699 20:12:42.839758 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7700 20:12:42.843301 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7701 20:12:42.843384
7702 20:12:42.843450
7703 20:12:42.843509 ==
7704 20:12:42.846733 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 20:12:42.849950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 20:12:42.850035 ==
7707 20:12:42.850100
7708 20:12:42.850160
7709 20:12:42.853546 TX Vref Scan disable
7710 20:12:42.853629 == TX Byte 0 ==
7711 20:12:42.859978 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7712 20:12:42.863128 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7713 20:12:42.863212 == TX Byte 1 ==
7714 20:12:42.870184 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7715 20:12:42.872985 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7716 20:12:42.873068 ==
7717 20:12:42.876660 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 20:12:42.879629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 20:12:42.879713 ==
7720 20:12:42.895566
7721 20:12:42.898560 TX Vref early break, caculate TX vref
7722 20:12:42.902229 TX Vref=16, minBit 12, minWin=21, winSum=373
7723 20:12:42.905309 TX Vref=18, minBit 6, minWin=23, winSum=384
7724 20:12:42.909037 TX Vref=20, minBit 12, minWin=23, winSum=397
7725 20:12:42.912198 TX Vref=22, minBit 7, minWin=24, winSum=406
7726 20:12:42.915487 TX Vref=24, minBit 1, minWin=25, winSum=411
7727 20:12:42.922021 TX Vref=26, minBit 12, minWin=25, winSum=423
7728 20:12:42.925586 TX Vref=28, minBit 0, minWin=25, winSum=428
7729 20:12:42.928603 TX Vref=30, minBit 0, minWin=25, winSum=423
7730 20:12:42.932100 TX Vref=32, minBit 0, minWin=25, winSum=413
7731 20:12:42.935506 TX Vref=34, minBit 1, minWin=24, winSum=407
7732 20:12:42.938981 TX Vref=36, minBit 1, minWin=24, winSum=395
7733 20:12:42.945289 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
7734 20:12:42.945373
7735 20:12:42.948729 Final TX Range 0 Vref 28
7736 20:12:42.948812
7737 20:12:42.948877 ==
7738 20:12:42.952164 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 20:12:42.955404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 20:12:42.955488 ==
7741 20:12:42.955554
7742 20:12:42.955627
7743 20:12:42.958619 TX Vref Scan disable
7744 20:12:42.965305 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7745 20:12:42.965389 == TX Byte 0 ==
7746 20:12:42.968830 u2DelayCellOfst[0]=10 cells (3 PI)
7747 20:12:42.972104 u2DelayCellOfst[1]=16 cells (5 PI)
7748 20:12:42.975347 u2DelayCellOfst[2]=10 cells (3 PI)
7749 20:12:42.978572 u2DelayCellOfst[3]=10 cells (3 PI)
7750 20:12:42.982199 u2DelayCellOfst[4]=6 cells (2 PI)
7751 20:12:42.985284 u2DelayCellOfst[5]=0 cells (0 PI)
7752 20:12:42.988476 u2DelayCellOfst[6]=16 cells (5 PI)
7753 20:12:42.992095 u2DelayCellOfst[7]=13 cells (4 PI)
7754 20:12:42.995104 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7755 20:12:42.998814 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7756 20:12:43.001822 == TX Byte 1 ==
7757 20:12:43.005404 u2DelayCellOfst[8]=0 cells (0 PI)
7758 20:12:43.008731 u2DelayCellOfst[9]=0 cells (0 PI)
7759 20:12:43.008814 u2DelayCellOfst[10]=6 cells (2 PI)
7760 20:12:43.012022 u2DelayCellOfst[11]=3 cells (1 PI)
7761 20:12:43.015053 u2DelayCellOfst[12]=10 cells (3 PI)
7762 20:12:43.018399 u2DelayCellOfst[13]=13 cells (4 PI)
7763 20:12:43.022178 u2DelayCellOfst[14]=13 cells (4 PI)
7764 20:12:43.025265 u2DelayCellOfst[15]=10 cells (3 PI)
7765 20:12:43.028453 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7766 20:12:43.035294 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7767 20:12:43.035377 DramC Write-DBI on
7768 20:12:43.035443 ==
7769 20:12:43.038720 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 20:12:43.045139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 20:12:43.045263 ==
7772 20:12:43.045356
7773 20:12:43.045445
7774 20:12:43.045532 TX Vref Scan disable
7775 20:12:43.048814 == TX Byte 0 ==
7776 20:12:43.052459 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7777 20:12:43.055454 == TX Byte 1 ==
7778 20:12:43.059159 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7779 20:12:43.062319 DramC Write-DBI off
7780 20:12:43.062401
7781 20:12:43.062467 [DATLAT]
7782 20:12:43.062527 Freq=1600, CH0 RK0
7783 20:12:43.062586
7784 20:12:43.065585 DATLAT Default: 0xf
7785 20:12:43.065668 0, 0xFFFF, sum = 0
7786 20:12:43.068910 1, 0xFFFF, sum = 0
7787 20:12:43.068995 2, 0xFFFF, sum = 0
7788 20:12:43.072509 3, 0xFFFF, sum = 0
7789 20:12:43.075732 4, 0xFFFF, sum = 0
7790 20:12:43.075816 5, 0xFFFF, sum = 0
7791 20:12:43.078784 6, 0xFFFF, sum = 0
7792 20:12:43.078869 7, 0xFFFF, sum = 0
7793 20:12:43.081963 8, 0xFFFF, sum = 0
7794 20:12:43.082048 9, 0xFFFF, sum = 0
7795 20:12:43.085512 10, 0xFFFF, sum = 0
7796 20:12:43.085596 11, 0xFFFF, sum = 0
7797 20:12:43.089194 12, 0xFFFF, sum = 0
7798 20:12:43.089306 13, 0xFFFF, sum = 0
7799 20:12:43.092473 14, 0x0, sum = 1
7800 20:12:43.092557 15, 0x0, sum = 2
7801 20:12:43.095674 16, 0x0, sum = 3
7802 20:12:43.095785 17, 0x0, sum = 4
7803 20:12:43.098839 best_step = 15
7804 20:12:43.098949
7805 20:12:43.099043 ==
7806 20:12:43.102171 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 20:12:43.105555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 20:12:43.105665 ==
7809 20:12:43.105758 RX Vref Scan: 1
7810 20:12:43.108597
7811 20:12:43.108706 Set Vref Range= 24 -> 127
7812 20:12:43.108802
7813 20:12:43.112258 RX Vref 24 -> 127, step: 1
7814 20:12:43.112368
7815 20:12:43.115287 RX Delay 19 -> 252, step: 4
7816 20:12:43.115396
7817 20:12:43.118775 Set Vref, RX VrefLevel [Byte0]: 24
7818 20:12:43.122034 [Byte1]: 24
7819 20:12:43.122117
7820 20:12:43.125221 Set Vref, RX VrefLevel [Byte0]: 25
7821 20:12:43.128498 [Byte1]: 25
7822 20:12:43.128607
7823 20:12:43.132025 Set Vref, RX VrefLevel [Byte0]: 26
7824 20:12:43.135623 [Byte1]: 26
7825 20:12:43.139742
7826 20:12:43.139824 Set Vref, RX VrefLevel [Byte0]: 27
7827 20:12:43.142483 [Byte1]: 27
7828 20:12:43.146946
7829 20:12:43.147028 Set Vref, RX VrefLevel [Byte0]: 28
7830 20:12:43.150176 [Byte1]: 28
7831 20:12:43.154201
7832 20:12:43.154312 Set Vref, RX VrefLevel [Byte0]: 29
7833 20:12:43.157832 [Byte1]: 29
7834 20:12:43.162053
7835 20:12:43.162135 Set Vref, RX VrefLevel [Byte0]: 30
7836 20:12:43.165192 [Byte1]: 30
7837 20:12:43.169459
7838 20:12:43.169544 Set Vref, RX VrefLevel [Byte0]: 31
7839 20:12:43.172793 [Byte1]: 31
7840 20:12:43.177173
7841 20:12:43.177256 Set Vref, RX VrefLevel [Byte0]: 32
7842 20:12:43.180584 [Byte1]: 32
7843 20:12:43.184613
7844 20:12:43.184695 Set Vref, RX VrefLevel [Byte0]: 33
7845 20:12:43.188029 [Byte1]: 33
7846 20:12:43.192168
7847 20:12:43.192250 Set Vref, RX VrefLevel [Byte0]: 34
7848 20:12:43.195585 [Byte1]: 34
7849 20:12:43.200322
7850 20:12:43.200405 Set Vref, RX VrefLevel [Byte0]: 35
7851 20:12:43.203046 [Byte1]: 35
7852 20:12:43.207699
7853 20:12:43.207782 Set Vref, RX VrefLevel [Byte0]: 36
7854 20:12:43.211162 [Byte1]: 36
7855 20:12:43.215274
7856 20:12:43.215357 Set Vref, RX VrefLevel [Byte0]: 37
7857 20:12:43.218390 [Byte1]: 37
7858 20:12:43.222687
7859 20:12:43.222770 Set Vref, RX VrefLevel [Byte0]: 38
7860 20:12:43.225817 [Byte1]: 38
7861 20:12:43.230068
7862 20:12:43.230150 Set Vref, RX VrefLevel [Byte0]: 39
7863 20:12:43.233733 [Byte1]: 39
7864 20:12:43.237663
7865 20:12:43.237771 Set Vref, RX VrefLevel [Byte0]: 40
7866 20:12:43.241158 [Byte1]: 40
7867 20:12:43.245523
7868 20:12:43.245606 Set Vref, RX VrefLevel [Byte0]: 41
7869 20:12:43.248661 [Byte1]: 41
7870 20:12:43.252802
7871 20:12:43.252885 Set Vref, RX VrefLevel [Byte0]: 42
7872 20:12:43.256487 [Byte1]: 42
7873 20:12:43.260581
7874 20:12:43.260664 Set Vref, RX VrefLevel [Byte0]: 43
7875 20:12:43.263769 [Byte1]: 43
7876 20:12:43.268003
7877 20:12:43.268085 Set Vref, RX VrefLevel [Byte0]: 44
7878 20:12:43.271546 [Byte1]: 44
7879 20:12:43.275569
7880 20:12:43.275652 Set Vref, RX VrefLevel [Byte0]: 45
7881 20:12:43.278963 [Byte1]: 45
7882 20:12:43.283314
7883 20:12:43.283396 Set Vref, RX VrefLevel [Byte0]: 46
7884 20:12:43.286637 [Byte1]: 46
7885 20:12:43.290633
7886 20:12:43.290716 Set Vref, RX VrefLevel [Byte0]: 47
7887 20:12:43.294067 [Byte1]: 47
7888 20:12:43.298307
7889 20:12:43.298391 Set Vref, RX VrefLevel [Byte0]: 48
7890 20:12:43.301749 [Byte1]: 48
7891 20:12:43.305830
7892 20:12:43.305929 Set Vref, RX VrefLevel [Byte0]: 49
7893 20:12:43.309304 [Byte1]: 49
7894 20:12:43.313278
7895 20:12:43.313378 Set Vref, RX VrefLevel [Byte0]: 50
7896 20:12:43.316889 [Byte1]: 50
7897 20:12:43.320921
7898 20:12:43.320994 Set Vref, RX VrefLevel [Byte0]: 51
7899 20:12:43.324124 [Byte1]: 51
7900 20:12:43.328520
7901 20:12:43.328619 Set Vref, RX VrefLevel [Byte0]: 52
7902 20:12:43.332036 [Byte1]: 52
7903 20:12:43.336272
7904 20:12:43.336344 Set Vref, RX VrefLevel [Byte0]: 53
7905 20:12:43.339404 [Byte1]: 53
7906 20:12:43.343659
7907 20:12:43.343757 Set Vref, RX VrefLevel [Byte0]: 54
7908 20:12:43.346940 [Byte1]: 54
7909 20:12:43.351293
7910 20:12:43.351391 Set Vref, RX VrefLevel [Byte0]: 55
7911 20:12:43.354474 [Byte1]: 55
7912 20:12:43.359070
7913 20:12:43.359142 Set Vref, RX VrefLevel [Byte0]: 56
7914 20:12:43.362189 [Byte1]: 56
7915 20:12:43.366615
7916 20:12:43.366688 Set Vref, RX VrefLevel [Byte0]: 57
7917 20:12:43.369916 [Byte1]: 57
7918 20:12:43.374043
7919 20:12:43.374144 Set Vref, RX VrefLevel [Byte0]: 58
7920 20:12:43.377293 [Byte1]: 58
7921 20:12:43.381679
7922 20:12:43.381779 Set Vref, RX VrefLevel [Byte0]: 59
7923 20:12:43.385237 [Byte1]: 59
7924 20:12:43.389312
7925 20:12:43.389415 Set Vref, RX VrefLevel [Byte0]: 60
7926 20:12:43.392592 [Byte1]: 60
7927 20:12:43.396891
7928 20:12:43.396990 Set Vref, RX VrefLevel [Byte0]: 61
7929 20:12:43.400234 [Byte1]: 61
7930 20:12:43.404570
7931 20:12:43.404668 Set Vref, RX VrefLevel [Byte0]: 62
7932 20:12:43.407845 [Byte1]: 62
7933 20:12:43.411698
7934 20:12:43.411796 Set Vref, RX VrefLevel [Byte0]: 63
7935 20:12:43.415114 [Byte1]: 63
7936 20:12:43.419597
7937 20:12:43.419673 Set Vref, RX VrefLevel [Byte0]: 64
7938 20:12:43.422673 [Byte1]: 64
7939 20:12:43.427041
7940 20:12:43.427115 Set Vref, RX VrefLevel [Byte0]: 65
7941 20:12:43.430150 [Byte1]: 65
7942 20:12:43.434501
7943 20:12:43.434575 Set Vref, RX VrefLevel [Byte0]: 66
7944 20:12:43.437886 [Byte1]: 66
7945 20:12:43.442479
7946 20:12:43.442553 Set Vref, RX VrefLevel [Byte0]: 67
7947 20:12:43.445605 [Byte1]: 67
7948 20:12:43.449773
7949 20:12:43.449871 Set Vref, RX VrefLevel [Byte0]: 68
7950 20:12:43.452801 [Byte1]: 68
7951 20:12:43.457573
7952 20:12:43.457680 Set Vref, RX VrefLevel [Byte0]: 69
7953 20:12:43.460756 [Byte1]: 69
7954 20:12:43.464668
7955 20:12:43.464756 Set Vref, RX VrefLevel [Byte0]: 70
7956 20:12:43.468499 [Byte1]: 70
7957 20:12:43.472604
7958 20:12:43.472676 Set Vref, RX VrefLevel [Byte0]: 71
7959 20:12:43.475785 [Byte1]: 71
7960 20:12:43.480240
7961 20:12:43.480312 Set Vref, RX VrefLevel [Byte0]: 72
7962 20:12:43.483444 [Byte1]: 72
7963 20:12:43.487650
7964 20:12:43.487731 Set Vref, RX VrefLevel [Byte0]: 73
7965 20:12:43.490920 [Byte1]: 73
7966 20:12:43.495240
7967 20:12:43.495313 Set Vref, RX VrefLevel [Byte0]: 74
7968 20:12:43.498382 [Byte1]: 74
7969 20:12:43.502473
7970 20:12:43.506219 Set Vref, RX VrefLevel [Byte0]: 75
7971 20:12:43.509399 [Byte1]: 75
7972 20:12:43.509474
7973 20:12:43.512679 Set Vref, RX VrefLevel [Byte0]: 76
7974 20:12:43.515720 [Byte1]: 76
7975 20:12:43.515793
7976 20:12:43.519260 Set Vref, RX VrefLevel [Byte0]: 77
7977 20:12:43.522303 [Byte1]: 77
7978 20:12:43.522374
7979 20:12:43.525662 Set Vref, RX VrefLevel [Byte0]: 78
7980 20:12:43.528871 [Byte1]: 78
7981 20:12:43.532885
7982 20:12:43.532959 Set Vref, RX VrefLevel [Byte0]: 79
7983 20:12:43.536235 [Byte1]: 79
7984 20:12:43.540724
7985 20:12:43.540796 Set Vref, RX VrefLevel [Byte0]: 80
7986 20:12:43.543710 [Byte1]: 80
7987 20:12:43.548215
7988 20:12:43.548313 Final RX Vref Byte 0 = 62 to rank0
7989 20:12:43.551571 Final RX Vref Byte 1 = 63 to rank0
7990 20:12:43.554837 Final RX Vref Byte 0 = 62 to rank1
7991 20:12:43.558179 Final RX Vref Byte 1 = 63 to rank1==
7992 20:12:43.561799 Dram Type= 6, Freq= 0, CH_0, rank 0
7993 20:12:43.568270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 20:12:43.568356 ==
7995 20:12:43.568423 DQS Delay:
7996 20:12:43.568483 DQS0 = 0, DQS1 = 0
7997 20:12:43.571228 DQM Delay:
7998 20:12:43.571312 DQM0 = 136, DQM1 = 124
7999 20:12:43.574699 DQ Delay:
8000 20:12:43.578041 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8001 20:12:43.581762 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
8002 20:12:43.584500 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8003 20:12:43.588083 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
8004 20:12:43.588168
8005 20:12:43.588234
8006 20:12:43.588294
8007 20:12:43.591486 [DramC_TX_OE_Calibration] TA2
8008 20:12:43.594447 Original DQ_B0 (3 6) =30, OEN = 27
8009 20:12:43.598112 Original DQ_B1 (3 6) =30, OEN = 27
8010 20:12:43.601495 24, 0x0, End_B0=24 End_B1=24
8011 20:12:43.601585 25, 0x0, End_B0=25 End_B1=25
8012 20:12:43.604542 26, 0x0, End_B0=26 End_B1=26
8013 20:12:43.607987 27, 0x0, End_B0=27 End_B1=27
8014 20:12:43.611375 28, 0x0, End_B0=28 End_B1=28
8015 20:12:43.614682 29, 0x0, End_B0=29 End_B1=29
8016 20:12:43.614767 30, 0x0, End_B0=30 End_B1=30
8017 20:12:43.617892 31, 0x4141, End_B0=30 End_B1=30
8018 20:12:43.621474 Byte0 end_step=30 best_step=27
8019 20:12:43.624486 Byte1 end_step=30 best_step=27
8020 20:12:43.627766 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 20:12:43.631257 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 20:12:43.631341
8023 20:12:43.631408
8024 20:12:43.637945 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8025 20:12:43.641375 CH0 RK0: MR19=303, MR18=1E1C
8026 20:12:43.647847 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8027 20:12:43.647932
8028 20:12:43.651387 ----->DramcWriteLeveling(PI) begin...
8029 20:12:43.651472 ==
8030 20:12:43.654835 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 20:12:43.658033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 20:12:43.658119 ==
8033 20:12:43.661484 Write leveling (Byte 0): 37 => 37
8034 20:12:43.664865 Write leveling (Byte 1): 30 => 30
8035 20:12:43.668066 DramcWriteLeveling(PI) end<-----
8036 20:12:43.668150
8037 20:12:43.668217 ==
8038 20:12:43.671239 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 20:12:43.674616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 20:12:43.674702 ==
8041 20:12:43.678101 [Gating] SW mode calibration
8042 20:12:43.684537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8043 20:12:43.691220 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8044 20:12:43.694772 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 20:12:43.698482 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 20:12:43.704315 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 20:12:43.708048 1 4 12 | B1->B0 | 2626 3333 | 1 0 | (0 0) (0 0)
8048 20:12:43.710942 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 20:12:43.717764 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 20:12:43.721217 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 20:12:43.724157 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 20:12:43.730748 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 20:12:43.734470 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 20:12:43.737667 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 20:12:43.744044 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
8056 20:12:43.747338 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8057 20:12:43.750733 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 20:12:43.757644 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 20:12:43.760915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 20:12:43.764420 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 20:12:43.771138 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 20:12:43.774099 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8063 20:12:43.777590 1 6 12 | B1->B0 | 2d2d 4040 | 1 0 | (0 0) (0 0)
8064 20:12:43.784234 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 20:12:43.787738 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 20:12:43.790788 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 20:12:43.794224 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 20:12:43.801054 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 20:12:43.804243 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 20:12:43.807423 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 20:12:43.814372 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8072 20:12:43.817355 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8073 20:12:43.820866 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8074 20:12:43.827284 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 20:12:43.830759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 20:12:43.833889 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 20:12:43.840400 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 20:12:43.843967 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 20:12:43.847379 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 20:12:43.853690 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 20:12:43.857168 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 20:12:43.860417 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 20:12:43.867265 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 20:12:43.870387 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 20:12:43.873970 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 20:12:43.880465 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8087 20:12:43.883608 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8088 20:12:43.887124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 20:12:43.890239 Total UI for P1: 0, mck2ui 16
8090 20:12:43.893630 best dqsien dly found for B0: ( 1, 9, 10)
8091 20:12:43.900357 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 20:12:43.900441 Total UI for P1: 0, mck2ui 16
8093 20:12:43.906891 best dqsien dly found for B1: ( 1, 9, 14)
8094 20:12:43.910443 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8095 20:12:43.913635 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8096 20:12:43.913722
8097 20:12:43.917007 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8098 20:12:43.920705 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8099 20:12:43.923427 [Gating] SW calibration Done
8100 20:12:43.923511 ==
8101 20:12:43.926769 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 20:12:43.930349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 20:12:43.930434 ==
8104 20:12:43.933351 RX Vref Scan: 0
8105 20:12:43.933434
8106 20:12:43.933500 RX Vref 0 -> 0, step: 1
8107 20:12:43.933561
8108 20:12:43.936877 RX Delay 0 -> 252, step: 8
8109 20:12:43.940274 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8110 20:12:43.946708 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8111 20:12:43.950246 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8112 20:12:43.953703 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8113 20:12:43.956536 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8114 20:12:43.960079 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8115 20:12:43.966909 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8116 20:12:43.969889 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8117 20:12:43.973414 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8118 20:12:43.976591 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8119 20:12:43.980036 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8120 20:12:43.986690 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8121 20:12:43.990050 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8122 20:12:43.993192 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8123 20:12:43.996613 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8124 20:12:43.999814 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8125 20:12:44.003059 ==
8126 20:12:44.003143 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 20:12:44.009775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 20:12:44.009860 ==
8129 20:12:44.009927 DQS Delay:
8130 20:12:44.012943 DQS0 = 0, DQS1 = 0
8131 20:12:44.013027 DQM Delay:
8132 20:12:44.016657 DQM0 = 136, DQM1 = 126
8133 20:12:44.016741 DQ Delay:
8134 20:12:44.019770 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8135 20:12:44.023229 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8136 20:12:44.026403 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8137 20:12:44.029921 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8138 20:12:44.030027
8139 20:12:44.030093
8140 20:12:44.030155 ==
8141 20:12:44.033244 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 20:12:44.039922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 20:12:44.040006 ==
8144 20:12:44.040073
8145 20:12:44.040135
8146 20:12:44.040193 TX Vref Scan disable
8147 20:12:44.043267 == TX Byte 0 ==
8148 20:12:44.046620 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8149 20:12:44.053267 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8150 20:12:44.053351 == TX Byte 1 ==
8151 20:12:44.056435 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8152 20:12:44.063078 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8153 20:12:44.063162 ==
8154 20:12:44.066539 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 20:12:44.069918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 20:12:44.070011 ==
8157 20:12:44.084334
8158 20:12:44.087593 TX Vref early break, caculate TX vref
8159 20:12:44.090905 TX Vref=16, minBit 0, minWin=23, winSum=389
8160 20:12:44.094201 TX Vref=18, minBit 0, minWin=24, winSum=399
8161 20:12:44.097209 TX Vref=20, minBit 8, minWin=24, winSum=407
8162 20:12:44.100864 TX Vref=22, minBit 0, minWin=25, winSum=415
8163 20:12:44.103883 TX Vref=24, minBit 0, minWin=25, winSum=422
8164 20:12:44.110571 TX Vref=26, minBit 0, minWin=26, winSum=430
8165 20:12:44.114102 TX Vref=28, minBit 0, minWin=25, winSum=428
8166 20:12:44.117311 TX Vref=30, minBit 0, minWin=26, winSum=427
8167 20:12:44.120511 TX Vref=32, minBit 0, minWin=25, winSum=416
8168 20:12:44.124028 TX Vref=34, minBit 1, minWin=24, winSum=408
8169 20:12:44.126988 TX Vref=36, minBit 2, minWin=24, winSum=401
8170 20:12:44.133711 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8171 20:12:44.133794
8172 20:12:44.136961 Final TX Range 0 Vref 26
8173 20:12:44.137034
8174 20:12:44.137096 ==
8175 20:12:44.140499 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 20:12:44.143452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 20:12:44.143521 ==
8178 20:12:44.143582
8179 20:12:44.147088
8180 20:12:44.147160 TX Vref Scan disable
8181 20:12:44.154032 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8182 20:12:44.154107 == TX Byte 0 ==
8183 20:12:44.156992 u2DelayCellOfst[0]=13 cells (4 PI)
8184 20:12:44.160063 u2DelayCellOfst[1]=20 cells (6 PI)
8185 20:12:44.163203 u2DelayCellOfst[2]=13 cells (4 PI)
8186 20:12:44.167143 u2DelayCellOfst[3]=13 cells (4 PI)
8187 20:12:44.170157 u2DelayCellOfst[4]=10 cells (3 PI)
8188 20:12:44.173843 u2DelayCellOfst[5]=0 cells (0 PI)
8189 20:12:44.176806 u2DelayCellOfst[6]=20 cells (6 PI)
8190 20:12:44.179979 u2DelayCellOfst[7]=20 cells (6 PI)
8191 20:12:44.183385 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8192 20:12:44.186781 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8193 20:12:44.190280 == TX Byte 1 ==
8194 20:12:44.193287 u2DelayCellOfst[8]=0 cells (0 PI)
8195 20:12:44.196743 u2DelayCellOfst[9]=0 cells (0 PI)
8196 20:12:44.196814 u2DelayCellOfst[10]=6 cells (2 PI)
8197 20:12:44.200480 u2DelayCellOfst[11]=3 cells (1 PI)
8198 20:12:44.203451 u2DelayCellOfst[12]=13 cells (4 PI)
8199 20:12:44.206781 u2DelayCellOfst[13]=10 cells (3 PI)
8200 20:12:44.209950 u2DelayCellOfst[14]=16 cells (5 PI)
8201 20:12:44.213336 u2DelayCellOfst[15]=10 cells (3 PI)
8202 20:12:44.219868 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8203 20:12:44.223400 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8204 20:12:44.223470 DramC Write-DBI on
8205 20:12:44.223531 ==
8206 20:12:44.226924 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 20:12:44.233210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 20:12:44.233279 ==
8209 20:12:44.233340
8210 20:12:44.233401
8211 20:12:44.236597 TX Vref Scan disable
8212 20:12:44.236669 == TX Byte 0 ==
8213 20:12:44.243007 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8214 20:12:44.243076 == TX Byte 1 ==
8215 20:12:44.246540 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8216 20:12:44.250057 DramC Write-DBI off
8217 20:12:44.250136
8218 20:12:44.250197 [DATLAT]
8219 20:12:44.253232 Freq=1600, CH0 RK1
8220 20:12:44.253304
8221 20:12:44.253364 DATLAT Default: 0xf
8222 20:12:44.256351 0, 0xFFFF, sum = 0
8223 20:12:44.256422 1, 0xFFFF, sum = 0
8224 20:12:44.259937 2, 0xFFFF, sum = 0
8225 20:12:44.260011 3, 0xFFFF, sum = 0
8226 20:12:44.262974 4, 0xFFFF, sum = 0
8227 20:12:44.263046 5, 0xFFFF, sum = 0
8228 20:12:44.266197 6, 0xFFFF, sum = 0
8229 20:12:44.266267 7, 0xFFFF, sum = 0
8230 20:12:44.269591 8, 0xFFFF, sum = 0
8231 20:12:44.269668 9, 0xFFFF, sum = 0
8232 20:12:44.273019 10, 0xFFFF, sum = 0
8233 20:12:44.276193 11, 0xFFFF, sum = 0
8234 20:12:44.276262 12, 0xFFFF, sum = 0
8235 20:12:44.279649 13, 0xFFFF, sum = 0
8236 20:12:44.279716 14, 0x0, sum = 1
8237 20:12:44.282961 15, 0x0, sum = 2
8238 20:12:44.283033 16, 0x0, sum = 3
8239 20:12:44.286397 17, 0x0, sum = 4
8240 20:12:44.286481 best_step = 15
8241 20:12:44.286543
8242 20:12:44.286601 ==
8243 20:12:44.289515 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 20:12:44.292951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 20:12:44.293024 ==
8246 20:12:44.296208 RX Vref Scan: 0
8247 20:12:44.296277
8248 20:12:44.299269 RX Vref 0 -> 0, step: 1
8249 20:12:44.299337
8250 20:12:44.299397 RX Delay 11 -> 252, step: 4
8251 20:12:44.306549 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8252 20:12:44.309856 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8253 20:12:44.313234 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8254 20:12:44.316255 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8255 20:12:44.319700 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8256 20:12:44.326134 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8257 20:12:44.329836 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8258 20:12:44.333007 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8259 20:12:44.336324 iDelay=191, Bit 8, Center 114 (67 ~ 162) 96
8260 20:12:44.339637 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8261 20:12:44.346193 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8262 20:12:44.349659 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8263 20:12:44.353153 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8264 20:12:44.356302 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8265 20:12:44.359796 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8266 20:12:44.366199 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8267 20:12:44.366275 ==
8268 20:12:44.369532 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 20:12:44.372922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 20:12:44.372992 ==
8271 20:12:44.373054 DQS Delay:
8272 20:12:44.376115 DQS0 = 0, DQS1 = 0
8273 20:12:44.376185 DQM Delay:
8274 20:12:44.379541 DQM0 = 133, DQM1 = 123
8275 20:12:44.379609 DQ Delay:
8276 20:12:44.382900 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8277 20:12:44.386429 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8278 20:12:44.390057 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8279 20:12:44.392912 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8280 20:12:44.392982
8281 20:12:44.396258
8282 20:12:44.396327
8283 20:12:44.396391 [DramC_TX_OE_Calibration] TA2
8284 20:12:44.399337 Original DQ_B0 (3 6) =30, OEN = 27
8285 20:12:44.402692 Original DQ_B1 (3 6) =30, OEN = 27
8286 20:12:44.406298 24, 0x0, End_B0=24 End_B1=24
8287 20:12:44.409652 25, 0x0, End_B0=25 End_B1=25
8288 20:12:44.412736 26, 0x0, End_B0=26 End_B1=26
8289 20:12:44.412807 27, 0x0, End_B0=27 End_B1=27
8290 20:12:44.416032 28, 0x0, End_B0=28 End_B1=28
8291 20:12:44.419215 29, 0x0, End_B0=29 End_B1=29
8292 20:12:44.422654 30, 0x0, End_B0=30 End_B1=30
8293 20:12:44.426113 31, 0x4141, End_B0=30 End_B1=30
8294 20:12:44.426184 Byte0 end_step=30 best_step=27
8295 20:12:44.429636 Byte1 end_step=30 best_step=27
8296 20:12:44.432739 Byte0 TX OE(2T, 0.5T) = (3, 3)
8297 20:12:44.436213 Byte1 TX OE(2T, 0.5T) = (3, 3)
8298 20:12:44.436280
8299 20:12:44.436339
8300 20:12:44.443063 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8301 20:12:44.445874 CH0 RK1: MR19=303, MR18=200D
8302 20:12:44.452625 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8303 20:12:44.455946 [RxdqsGatingPostProcess] freq 1600
8304 20:12:44.462559 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8305 20:12:44.466246 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 20:12:44.466318 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 20:12:44.469417 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 20:12:44.472594 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 20:12:44.476260 best DQS0 dly(2T, 0.5T) = (1, 1)
8310 20:12:44.479211 best DQS1 dly(2T, 0.5T) = (1, 1)
8311 20:12:44.482384 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8312 20:12:44.486157 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8313 20:12:44.489063 Pre-setting of DQS Precalculation
8314 20:12:44.492319 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8315 20:12:44.495750 ==
8316 20:12:44.495825 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 20:12:44.502613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 20:12:44.502690 ==
8319 20:12:44.505831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 20:12:44.512378 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 20:12:44.515992 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 20:12:44.522035 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 20:12:44.530133 [CA 0] Center 42 (12~72) winsize 61
8324 20:12:44.533707 [CA 1] Center 42 (12~72) winsize 61
8325 20:12:44.536967 [CA 2] Center 38 (9~68) winsize 60
8326 20:12:44.540302 [CA 3] Center 37 (8~67) winsize 60
8327 20:12:44.543566 [CA 4] Center 37 (8~67) winsize 60
8328 20:12:44.546938 [CA 5] Center 37 (7~67) winsize 61
8329 20:12:44.547010
8330 20:12:44.550330 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 20:12:44.550404
8332 20:12:44.553459 [CATrainingPosCal] consider 1 rank data
8333 20:12:44.556791 u2DelayCellTimex100 = 290/100 ps
8334 20:12:44.560139 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8335 20:12:44.566956 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8336 20:12:44.570130 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8337 20:12:44.573545 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8338 20:12:44.576801 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8339 20:12:44.579942 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8340 20:12:44.580014
8341 20:12:44.583561 CA PerBit enable=1, Macro0, CA PI delay=37
8342 20:12:44.583633
8343 20:12:44.586595 [CBTSetCACLKResult] CA Dly = 37
8344 20:12:44.589908 CS Dly: 8 (0~39)
8345 20:12:44.593527 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 20:12:44.596614 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 20:12:44.596688 ==
8348 20:12:44.599908 Dram Type= 6, Freq= 0, CH_1, rank 1
8349 20:12:44.603398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 20:12:44.606845 ==
8351 20:12:44.609958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8352 20:12:44.613404 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8353 20:12:44.620323 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8354 20:12:44.622989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8355 20:12:44.633443 [CA 0] Center 42 (13~72) winsize 60
8356 20:12:44.636697 [CA 1] Center 42 (13~72) winsize 60
8357 20:12:44.640390 [CA 2] Center 38 (9~68) winsize 60
8358 20:12:44.643618 [CA 3] Center 37 (8~67) winsize 60
8359 20:12:44.646668 [CA 4] Center 38 (9~68) winsize 60
8360 20:12:44.650185 [CA 5] Center 37 (8~67) winsize 60
8361 20:12:44.650259
8362 20:12:44.653646 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8363 20:12:44.653748
8364 20:12:44.656893 [CATrainingPosCal] consider 2 rank data
8365 20:12:44.659904 u2DelayCellTimex100 = 290/100 ps
8366 20:12:44.663302 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8367 20:12:44.670027 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8368 20:12:44.673142 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8369 20:12:44.676445 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8370 20:12:44.680041 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8371 20:12:44.683115 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8372 20:12:44.683187
8373 20:12:44.686711 CA PerBit enable=1, Macro0, CA PI delay=37
8374 20:12:44.686778
8375 20:12:44.689841 [CBTSetCACLKResult] CA Dly = 37
8376 20:12:44.693073 CS Dly: 9 (0~41)
8377 20:12:44.696443 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8378 20:12:44.700195 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8379 20:12:44.700265
8380 20:12:44.703111 ----->DramcWriteLeveling(PI) begin...
8381 20:12:44.703180 ==
8382 20:12:44.706558 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 20:12:44.709844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 20:12:44.713263 ==
8385 20:12:44.713330 Write leveling (Byte 0): 25 => 25
8386 20:12:44.716678 Write leveling (Byte 1): 26 => 26
8387 20:12:44.719857 DramcWriteLeveling(PI) end<-----
8388 20:12:44.719926
8389 20:12:44.719984 ==
8390 20:12:44.723305 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 20:12:44.730030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 20:12:44.730108 ==
8393 20:12:44.730172 [Gating] SW mode calibration
8394 20:12:44.740061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8395 20:12:44.743302 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8396 20:12:44.746832 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 20:12:44.753184 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 20:12:44.756532 1 4 8 | B1->B0 | 2525 2828 | 0 1 | (0 0) (0 0)
8399 20:12:44.759889 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 20:12:44.766382 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 20:12:44.769871 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 20:12:44.773093 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 20:12:44.779984 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 20:12:44.782996 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 20:12:44.786386 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8406 20:12:44.792884 1 5 8 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 1)
8407 20:12:44.796336 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8408 20:12:44.799966 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8409 20:12:44.805997 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 20:12:44.809481 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 20:12:44.812766 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 20:12:44.819839 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 20:12:44.822709 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 20:12:44.826067 1 6 8 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
8415 20:12:44.832801 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 20:12:44.835970 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 20:12:44.839348 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 20:12:44.845858 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 20:12:44.849200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 20:12:44.852680 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 20:12:44.859380 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8422 20:12:44.862398 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8423 20:12:44.865991 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8424 20:12:44.872687 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 20:12:44.875853 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 20:12:44.879240 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 20:12:44.885750 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 20:12:44.889307 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 20:12:44.892191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 20:12:44.899197 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 20:12:44.902793 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 20:12:44.905846 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 20:12:44.912536 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 20:12:44.915491 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 20:12:44.919115 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 20:12:44.922525 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 20:12:44.928926 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8438 20:12:44.932508 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 20:12:44.935713 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8440 20:12:44.942365 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 20:12:44.945913 Total UI for P1: 0, mck2ui 16
8442 20:12:44.949046 best dqsien dly found for B0: ( 1, 9, 8)
8443 20:12:44.952233 Total UI for P1: 0, mck2ui 16
8444 20:12:44.955602 best dqsien dly found for B1: ( 1, 9, 10)
8445 20:12:44.958851 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8446 20:12:44.962056 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8447 20:12:44.962135
8448 20:12:44.965517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8449 20:12:44.969020 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8450 20:12:44.971936 [Gating] SW calibration Done
8451 20:12:44.972007 ==
8452 20:12:44.975675 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 20:12:44.978744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 20:12:44.978813 ==
8455 20:12:44.982103 RX Vref Scan: 0
8456 20:12:44.982176
8457 20:12:44.982237 RX Vref 0 -> 0, step: 1
8458 20:12:44.985395
8459 20:12:44.985464 RX Delay 0 -> 252, step: 8
8460 20:12:44.988714 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8461 20:12:44.995215 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8462 20:12:44.998437 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8463 20:12:45.001749 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8464 20:12:45.005457 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8465 20:12:45.008695 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8466 20:12:45.015092 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8467 20:12:45.018620 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8468 20:12:45.021835 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8469 20:12:45.025500 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8470 20:12:45.028482 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8471 20:12:45.032108 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8472 20:12:45.038917 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8473 20:12:45.041828 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8474 20:12:45.045207 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8475 20:12:45.048650 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8476 20:12:45.048725 ==
8477 20:12:45.051678 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 20:12:45.058369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 20:12:45.058456 ==
8480 20:12:45.058524 DQS Delay:
8481 20:12:45.061789 DQS0 = 0, DQS1 = 0
8482 20:12:45.061868 DQM Delay:
8483 20:12:45.065069 DQM0 = 137, DQM1 = 130
8484 20:12:45.065152 DQ Delay:
8485 20:12:45.068357 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8486 20:12:45.071615 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8487 20:12:45.075223 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8488 20:12:45.078233 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8489 20:12:45.078317
8490 20:12:45.078383
8491 20:12:45.078445 ==
8492 20:12:45.081542 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 20:12:45.088629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 20:12:45.088714 ==
8495 20:12:45.088781
8496 20:12:45.088842
8497 20:12:45.088901 TX Vref Scan disable
8498 20:12:45.092021 == TX Byte 0 ==
8499 20:12:45.095279 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8500 20:12:45.098645 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 20:12:45.101844 == TX Byte 1 ==
8502 20:12:45.105224 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8503 20:12:45.111989 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8504 20:12:45.112074 ==
8505 20:12:45.114959 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 20:12:45.118168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 20:12:45.118253 ==
8508 20:12:45.130452
8509 20:12:45.133888 TX Vref early break, caculate TX vref
8510 20:12:45.137222 TX Vref=16, minBit 10, minWin=22, winSum=378
8511 20:12:45.140503 TX Vref=18, minBit 10, minWin=22, winSum=388
8512 20:12:45.143829 TX Vref=20, minBit 0, minWin=24, winSum=399
8513 20:12:45.147158 TX Vref=22, minBit 10, minWin=24, winSum=407
8514 20:12:45.150358 TX Vref=24, minBit 1, minWin=25, winSum=417
8515 20:12:45.157360 TX Vref=26, minBit 0, minWin=26, winSum=429
8516 20:12:45.160503 TX Vref=28, minBit 0, minWin=26, winSum=430
8517 20:12:45.164139 TX Vref=30, minBit 8, minWin=25, winSum=425
8518 20:12:45.167427 TX Vref=32, minBit 9, minWin=24, winSum=412
8519 20:12:45.171115 TX Vref=34, minBit 14, minWin=24, winSum=405
8520 20:12:45.177320 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8521 20:12:45.177405
8522 20:12:45.180472 Final TX Range 0 Vref 28
8523 20:12:45.180556
8524 20:12:45.180623 ==
8525 20:12:45.184291 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 20:12:45.187336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 20:12:45.187420 ==
8528 20:12:45.187486
8529 20:12:45.187546
8530 20:12:45.190912 TX Vref Scan disable
8531 20:12:45.197122 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8532 20:12:45.197207 == TX Byte 0 ==
8533 20:12:45.200679 u2DelayCellOfst[0]=13 cells (4 PI)
8534 20:12:45.204068 u2DelayCellOfst[1]=10 cells (3 PI)
8535 20:12:45.207129 u2DelayCellOfst[2]=0 cells (0 PI)
8536 20:12:45.210602 u2DelayCellOfst[3]=3 cells (1 PI)
8537 20:12:45.214117 u2DelayCellOfst[4]=6 cells (2 PI)
8538 20:12:45.217574 u2DelayCellOfst[5]=16 cells (5 PI)
8539 20:12:45.217658 u2DelayCellOfst[6]=16 cells (5 PI)
8540 20:12:45.220507 u2DelayCellOfst[7]=3 cells (1 PI)
8541 20:12:45.227374 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8542 20:12:45.230746 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8543 20:12:45.230830 == TX Byte 1 ==
8544 20:12:45.233752 u2DelayCellOfst[8]=0 cells (0 PI)
8545 20:12:45.237283 u2DelayCellOfst[9]=3 cells (1 PI)
8546 20:12:45.240570 u2DelayCellOfst[10]=10 cells (3 PI)
8547 20:12:45.243732 u2DelayCellOfst[11]=3 cells (1 PI)
8548 20:12:45.247099 u2DelayCellOfst[12]=13 cells (4 PI)
8549 20:12:45.250240 u2DelayCellOfst[13]=16 cells (5 PI)
8550 20:12:45.253561 u2DelayCellOfst[14]=16 cells (5 PI)
8551 20:12:45.256892 u2DelayCellOfst[15]=16 cells (5 PI)
8552 20:12:45.260124 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8553 20:12:45.266846 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8554 20:12:45.266929 DramC Write-DBI on
8555 20:12:45.267011 ==
8556 20:12:45.270547 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 20:12:45.273791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 20:12:45.273890 ==
8559 20:12:45.273994
8560 20:12:45.276994
8561 20:12:45.277093 TX Vref Scan disable
8562 20:12:45.280555 == TX Byte 0 ==
8563 20:12:45.283609 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8564 20:12:45.286920 == TX Byte 1 ==
8565 20:12:45.290470 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8566 20:12:45.290553 DramC Write-DBI off
8567 20:12:45.290618
8568 20:12:45.293922 [DATLAT]
8569 20:12:45.294030 Freq=1600, CH1 RK0
8570 20:12:45.294094
8571 20:12:45.297053 DATLAT Default: 0xf
8572 20:12:45.297123 0, 0xFFFF, sum = 0
8573 20:12:45.300401 1, 0xFFFF, sum = 0
8574 20:12:45.300477 2, 0xFFFF, sum = 0
8575 20:12:45.303639 3, 0xFFFF, sum = 0
8576 20:12:45.303708 4, 0xFFFF, sum = 0
8577 20:12:45.307083 5, 0xFFFF, sum = 0
8578 20:12:45.307151 6, 0xFFFF, sum = 0
8579 20:12:45.310393 7, 0xFFFF, sum = 0
8580 20:12:45.310460 8, 0xFFFF, sum = 0
8581 20:12:45.313888 9, 0xFFFF, sum = 0
8582 20:12:45.317010 10, 0xFFFF, sum = 0
8583 20:12:45.317084 11, 0xFFFF, sum = 0
8584 20:12:45.320513 12, 0xFFFF, sum = 0
8585 20:12:45.320614 13, 0xFFFF, sum = 0
8586 20:12:45.323637 14, 0x0, sum = 1
8587 20:12:45.323714 15, 0x0, sum = 2
8588 20:12:45.327523 16, 0x0, sum = 3
8589 20:12:45.327597 17, 0x0, sum = 4
8590 20:12:45.327659 best_step = 15
8591 20:12:45.327727
8592 20:12:45.330111 ==
8593 20:12:45.333602 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 20:12:45.336920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 20:12:45.337013 ==
8596 20:12:45.337077 RX Vref Scan: 1
8597 20:12:45.337137
8598 20:12:45.340398 Set Vref Range= 24 -> 127
8599 20:12:45.340502
8600 20:12:45.343516 RX Vref 24 -> 127, step: 1
8601 20:12:45.343588
8602 20:12:45.347372 RX Delay 19 -> 252, step: 4
8603 20:12:45.347452
8604 20:12:45.350721 Set Vref, RX VrefLevel [Byte0]: 24
8605 20:12:45.353546 [Byte1]: 24
8606 20:12:45.353614
8607 20:12:45.357109 Set Vref, RX VrefLevel [Byte0]: 25
8608 20:12:45.360242 [Byte1]: 25
8609 20:12:45.360325
8610 20:12:45.363686 Set Vref, RX VrefLevel [Byte0]: 26
8611 20:12:45.366942 [Byte1]: 26
8612 20:12:45.370584
8613 20:12:45.370666 Set Vref, RX VrefLevel [Byte0]: 27
8614 20:12:45.373909 [Byte1]: 27
8615 20:12:45.378075
8616 20:12:45.378157 Set Vref, RX VrefLevel [Byte0]: 28
8617 20:12:45.381243 [Byte1]: 28
8618 20:12:45.385184
8619 20:12:45.385265 Set Vref, RX VrefLevel [Byte0]: 29
8620 20:12:45.388659 [Byte1]: 29
8621 20:12:45.392902
8622 20:12:45.392985 Set Vref, RX VrefLevel [Byte0]: 30
8623 20:12:45.396510 [Byte1]: 30
8624 20:12:45.400676
8625 20:12:45.400758 Set Vref, RX VrefLevel [Byte0]: 31
8626 20:12:45.403903 [Byte1]: 31
8627 20:12:45.408367
8628 20:12:45.408449 Set Vref, RX VrefLevel [Byte0]: 32
8629 20:12:45.411345 [Byte1]: 32
8630 20:12:45.415753
8631 20:12:45.415835 Set Vref, RX VrefLevel [Byte0]: 33
8632 20:12:45.418993 [Byte1]: 33
8633 20:12:45.423232
8634 20:12:45.423314 Set Vref, RX VrefLevel [Byte0]: 34
8635 20:12:45.426367 [Byte1]: 34
8636 20:12:45.431029
8637 20:12:45.431111 Set Vref, RX VrefLevel [Byte0]: 35
8638 20:12:45.434113 [Byte1]: 35
8639 20:12:45.438667
8640 20:12:45.438749 Set Vref, RX VrefLevel [Byte0]: 36
8641 20:12:45.441495 [Byte1]: 36
8642 20:12:45.445821
8643 20:12:45.445902 Set Vref, RX VrefLevel [Byte0]: 37
8644 20:12:45.449653 [Byte1]: 37
8645 20:12:45.453735
8646 20:12:45.453870 Set Vref, RX VrefLevel [Byte0]: 38
8647 20:12:45.456789 [Byte1]: 38
8648 20:12:45.461119
8649 20:12:45.461202 Set Vref, RX VrefLevel [Byte0]: 39
8650 20:12:45.464607 [Byte1]: 39
8651 20:12:45.468814
8652 20:12:45.468897 Set Vref, RX VrefLevel [Byte0]: 40
8653 20:12:45.471904 [Byte1]: 40
8654 20:12:45.476233
8655 20:12:45.476316 Set Vref, RX VrefLevel [Byte0]: 41
8656 20:12:45.479586 [Byte1]: 41
8657 20:12:45.484219
8658 20:12:45.484302 Set Vref, RX VrefLevel [Byte0]: 42
8659 20:12:45.487230 [Byte1]: 42
8660 20:12:45.491608
8661 20:12:45.491693 Set Vref, RX VrefLevel [Byte0]: 43
8662 20:12:45.494689 [Byte1]: 43
8663 20:12:45.499191
8664 20:12:45.499275 Set Vref, RX VrefLevel [Byte0]: 44
8665 20:12:45.502172 [Byte1]: 44
8666 20:12:45.506765
8667 20:12:45.506848 Set Vref, RX VrefLevel [Byte0]: 45
8668 20:12:45.509798 [Byte1]: 45
8669 20:12:45.514025
8670 20:12:45.514108 Set Vref, RX VrefLevel [Byte0]: 46
8671 20:12:45.517398 [Byte1]: 46
8672 20:12:45.521688
8673 20:12:45.521772 Set Vref, RX VrefLevel [Byte0]: 47
8674 20:12:45.524870 [Byte1]: 47
8675 20:12:45.529153
8676 20:12:45.529236 Set Vref, RX VrefLevel [Byte0]: 48
8677 20:12:45.532751 [Byte1]: 48
8678 20:12:45.536663
8679 20:12:45.536747 Set Vref, RX VrefLevel [Byte0]: 49
8680 20:12:45.540004 [Byte1]: 49
8681 20:12:45.544399
8682 20:12:45.544483 Set Vref, RX VrefLevel [Byte0]: 50
8683 20:12:45.547777 [Byte1]: 50
8684 20:12:45.551848
8685 20:12:45.551931 Set Vref, RX VrefLevel [Byte0]: 51
8686 20:12:45.555417 [Byte1]: 51
8687 20:12:45.559582
8688 20:12:45.559665 Set Vref, RX VrefLevel [Byte0]: 52
8689 20:12:45.565901 [Byte1]: 52
8690 20:12:45.565992
8691 20:12:45.569212 Set Vref, RX VrefLevel [Byte0]: 53
8692 20:12:45.572646 [Byte1]: 53
8693 20:12:45.572749
8694 20:12:45.575840 Set Vref, RX VrefLevel [Byte0]: 54
8695 20:12:45.578989 [Byte1]: 54
8696 20:12:45.579073
8697 20:12:45.582466 Set Vref, RX VrefLevel [Byte0]: 55
8698 20:12:45.586178 [Byte1]: 55
8699 20:12:45.589964
8700 20:12:45.590049 Set Vref, RX VrefLevel [Byte0]: 56
8701 20:12:45.593342 [Byte1]: 56
8702 20:12:45.597480
8703 20:12:45.597577 Set Vref, RX VrefLevel [Byte0]: 57
8704 20:12:45.601344 [Byte1]: 57
8705 20:12:45.605453
8706 20:12:45.605640 Set Vref, RX VrefLevel [Byte0]: 58
8707 20:12:45.608611 [Byte1]: 58
8708 20:12:45.612439
8709 20:12:45.612645 Set Vref, RX VrefLevel [Byte0]: 59
8710 20:12:45.616352 [Byte1]: 59
8711 20:12:45.620113
8712 20:12:45.620252 Set Vref, RX VrefLevel [Byte0]: 60
8713 20:12:45.623634 [Byte1]: 60
8714 20:12:45.627702
8715 20:12:45.627878 Set Vref, RX VrefLevel [Byte0]: 61
8716 20:12:45.631706 [Byte1]: 61
8717 20:12:45.635948
8718 20:12:45.636282 Set Vref, RX VrefLevel [Byte0]: 62
8719 20:12:45.638991 [Byte1]: 62
8720 20:12:45.643231
8721 20:12:45.643631 Set Vref, RX VrefLevel [Byte0]: 63
8722 20:12:45.646520 [Byte1]: 63
8723 20:12:45.651307
8724 20:12:45.651890 Set Vref, RX VrefLevel [Byte0]: 64
8725 20:12:45.654098 [Byte1]: 64
8726 20:12:45.658524
8727 20:12:45.658996 Set Vref, RX VrefLevel [Byte0]: 65
8728 20:12:45.661620 [Byte1]: 65
8729 20:12:45.666027
8730 20:12:45.666502 Set Vref, RX VrefLevel [Byte0]: 66
8731 20:12:45.669262 [Byte1]: 66
8732 20:12:45.673860
8733 20:12:45.674460 Set Vref, RX VrefLevel [Byte0]: 67
8734 20:12:45.677085 [Byte1]: 67
8735 20:12:45.681556
8736 20:12:45.682175 Set Vref, RX VrefLevel [Byte0]: 68
8737 20:12:45.684648 [Byte1]: 68
8738 20:12:45.688921
8739 20:12:45.689508 Set Vref, RX VrefLevel [Byte0]: 69
8740 20:12:45.691787 [Byte1]: 69
8741 20:12:45.696164
8742 20:12:45.696633 Set Vref, RX VrefLevel [Byte0]: 70
8743 20:12:45.699516 [Byte1]: 70
8744 20:12:45.704009
8745 20:12:45.704576 Set Vref, RX VrefLevel [Byte0]: 71
8746 20:12:45.707265 [Byte1]: 71
8747 20:12:45.711541
8748 20:12:45.712015 Set Vref, RX VrefLevel [Byte0]: 72
8749 20:12:45.714943 [Byte1]: 72
8750 20:12:45.719017
8751 20:12:45.719558 Set Vref, RX VrefLevel [Byte0]: 73
8752 20:12:45.722427 [Byte1]: 73
8753 20:12:45.726670
8754 20:12:45.727144 Set Vref, RX VrefLevel [Byte0]: 74
8755 20:12:45.729689 [Byte1]: 74
8756 20:12:45.734297
8757 20:12:45.734848 Set Vref, RX VrefLevel [Byte0]: 75
8758 20:12:45.737557 [Byte1]: 75
8759 20:12:45.742150
8760 20:12:45.742723 Set Vref, RX VrefLevel [Byte0]: 76
8761 20:12:45.745108 [Byte1]: 76
8762 20:12:45.749428
8763 20:12:45.750034 Set Vref, RX VrefLevel [Byte0]: 77
8764 20:12:45.752872 [Byte1]: 77
8765 20:12:45.757091
8766 20:12:45.757572 Set Vref, RX VrefLevel [Byte0]: 78
8767 20:12:45.760285 [Byte1]: 78
8768 20:12:45.764277
8769 20:12:45.764959 Final RX Vref Byte 0 = 57 to rank0
8770 20:12:45.767611 Final RX Vref Byte 1 = 62 to rank0
8771 20:12:45.770831 Final RX Vref Byte 0 = 57 to rank1
8772 20:12:45.774491 Final RX Vref Byte 1 = 62 to rank1==
8773 20:12:45.777815 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 20:12:45.784356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 20:12:45.784990 ==
8776 20:12:45.785590 DQS Delay:
8777 20:12:45.786152 DQS0 = 0, DQS1 = 0
8778 20:12:45.787254 DQM Delay:
8779 20:12:45.787653 DQM0 = 134, DQM1 = 129
8780 20:12:45.790983 DQ Delay:
8781 20:12:45.794115 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8782 20:12:45.797714 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8783 20:12:45.800989 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8784 20:12:45.804308 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8785 20:12:45.804570
8786 20:12:45.804762
8787 20:12:45.804941
8788 20:12:45.807912 [DramC_TX_OE_Calibration] TA2
8789 20:12:45.811174 Original DQ_B0 (3 6) =30, OEN = 27
8790 20:12:45.814331 Original DQ_B1 (3 6) =30, OEN = 27
8791 20:12:45.817885 24, 0x0, End_B0=24 End_B1=24
8792 20:12:45.818246 25, 0x0, End_B0=25 End_B1=25
8793 20:12:45.821050 26, 0x0, End_B0=26 End_B1=26
8794 20:12:45.824663 27, 0x0, End_B0=27 End_B1=27
8795 20:12:45.827718 28, 0x0, End_B0=28 End_B1=28
8796 20:12:45.828059 29, 0x0, End_B0=29 End_B1=29
8797 20:12:45.831325 30, 0x0, End_B0=30 End_B1=30
8798 20:12:45.834201 31, 0x4141, End_B0=30 End_B1=30
8799 20:12:45.837663 Byte0 end_step=30 best_step=27
8800 20:12:45.841217 Byte1 end_step=30 best_step=27
8801 20:12:45.844503 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 20:12:45.844910 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 20:12:45.845224
8804 20:12:45.845520
8805 20:12:45.854522 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8806 20:12:45.857648 CH1 RK0: MR19=303, MR18=1A28
8807 20:12:45.864322 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8808 20:12:45.864816
8809 20:12:45.867606 ----->DramcWriteLeveling(PI) begin...
8810 20:12:45.868260 ==
8811 20:12:45.871321 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 20:12:45.874499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 20:12:45.874971 ==
8814 20:12:45.877799 Write leveling (Byte 0): 27 => 27
8815 20:12:45.880935 Write leveling (Byte 1): 29 => 29
8816 20:12:45.884437 DramcWriteLeveling(PI) end<-----
8817 20:12:45.885006
8818 20:12:45.885378 ==
8819 20:12:45.887915 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 20:12:45.891210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 20:12:45.891687 ==
8822 20:12:45.894179 [Gating] SW mode calibration
8823 20:12:45.901176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 20:12:45.907699 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 20:12:45.911119 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 20:12:45.914016 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 20:12:45.920998 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
8828 20:12:45.923923 1 4 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 1)
8829 20:12:45.927309 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 20:12:45.934011 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 20:12:45.937317 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 20:12:45.940448 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 20:12:45.947481 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 20:12:45.950591 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 20:12:45.954181 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8836 20:12:45.960538 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
8837 20:12:45.964244 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 20:12:45.967256 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 20:12:45.973610 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 20:12:45.977114 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 20:12:45.980326 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 20:12:45.986878 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 20:12:45.990076 1 6 8 | B1->B0 | 4646 2929 | 0 1 | (0 0) (0 0)
8844 20:12:45.993618 1 6 12 | B1->B0 | 4646 403f | 0 1 | (0 0) (0 0)
8845 20:12:45.997214 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 20:12:46.003833 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 20:12:46.007026 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 20:12:46.010279 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 20:12:46.017510 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 20:12:46.020520 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 20:12:46.023935 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 20:12:46.030407 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8853 20:12:46.034171 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 20:12:46.036991 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 20:12:46.043551 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 20:12:46.046902 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 20:12:46.050603 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 20:12:46.057087 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 20:12:46.060228 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 20:12:46.063514 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 20:12:46.070287 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 20:12:46.073407 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 20:12:46.076682 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 20:12:46.083776 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 20:12:46.086915 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 20:12:46.090464 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 20:12:46.097046 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8868 20:12:46.100905 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 20:12:46.103640 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 20:12:46.107485 Total UI for P1: 0, mck2ui 16
8871 20:12:46.110150 best dqsien dly found for B0: ( 1, 9, 10)
8872 20:12:46.113651 Total UI for P1: 0, mck2ui 16
8873 20:12:46.117524 best dqsien dly found for B1: ( 1, 9, 12)
8874 20:12:46.120554 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8875 20:12:46.123507 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8876 20:12:46.123931
8877 20:12:46.127181 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8878 20:12:46.133646 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8879 20:12:46.133884 [Gating] SW calibration Done
8880 20:12:46.134114 ==
8881 20:12:46.136644 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 20:12:46.143056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 20:12:46.143242 ==
8884 20:12:46.143392 RX Vref Scan: 0
8885 20:12:46.143527
8886 20:12:46.146457 RX Vref 0 -> 0, step: 1
8887 20:12:46.146639
8888 20:12:46.149649 RX Delay 0 -> 252, step: 8
8889 20:12:46.153113 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8890 20:12:46.156521 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8891 20:12:46.160019 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8892 20:12:46.163235 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8893 20:12:46.170148 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8894 20:12:46.173562 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8895 20:12:46.176513 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8896 20:12:46.179930 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8897 20:12:46.183504 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8898 20:12:46.190145 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8899 20:12:46.193325 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8900 20:12:46.196458 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8901 20:12:46.200100 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8902 20:12:46.203355 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8903 20:12:46.209768 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8904 20:12:46.213272 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8905 20:12:46.213533 ==
8906 20:12:46.216165 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 20:12:46.219710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 20:12:46.219972 ==
8909 20:12:46.223249 DQS Delay:
8910 20:12:46.223518 DQS0 = 0, DQS1 = 0
8911 20:12:46.223738 DQM Delay:
8912 20:12:46.226721 DQM0 = 137, DQM1 = 133
8913 20:12:46.227050 DQ Delay:
8914 20:12:46.229994 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8915 20:12:46.233133 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8916 20:12:46.239671 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8917 20:12:46.242827 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8918 20:12:46.243192
8919 20:12:46.243496
8920 20:12:46.243793 ==
8921 20:12:46.246292 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 20:12:46.249664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 20:12:46.249927 ==
8924 20:12:46.250165
8925 20:12:46.250360
8926 20:12:46.252985 TX Vref Scan disable
8927 20:12:46.256526 == TX Byte 0 ==
8928 20:12:46.259597 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8929 20:12:46.263008 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8930 20:12:46.266329 == TX Byte 1 ==
8931 20:12:46.269570 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8932 20:12:46.273107 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8933 20:12:46.273397 ==
8934 20:12:46.276083 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 20:12:46.279440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 20:12:46.282417 ==
8937 20:12:46.293720
8938 20:12:46.297020 TX Vref early break, caculate TX vref
8939 20:12:46.300121 TX Vref=16, minBit 11, minWin=21, winSum=379
8940 20:12:46.303639 TX Vref=18, minBit 9, minWin=22, winSum=383
8941 20:12:46.306970 TX Vref=20, minBit 8, minWin=23, winSum=394
8942 20:12:46.310559 TX Vref=22, minBit 11, minWin=23, winSum=404
8943 20:12:46.313138 TX Vref=24, minBit 9, minWin=24, winSum=410
8944 20:12:46.319927 TX Vref=26, minBit 9, minWin=24, winSum=413
8945 20:12:46.323231 TX Vref=28, minBit 10, minWin=24, winSum=415
8946 20:12:46.326706 TX Vref=30, minBit 8, minWin=24, winSum=414
8947 20:12:46.329933 TX Vref=32, minBit 8, minWin=24, winSum=403
8948 20:12:46.333204 TX Vref=34, minBit 9, minWin=22, winSum=393
8949 20:12:46.339971 [TxChooseVref] Worse bit 10, Min win 24, Win sum 415, Final Vref 28
8950 20:12:46.340178
8951 20:12:46.343299 Final TX Range 0 Vref 28
8952 20:12:46.343502
8953 20:12:46.343662 ==
8954 20:12:46.346981 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 20:12:46.349776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 20:12:46.350091 ==
8957 20:12:46.350272
8958 20:12:46.350431
8959 20:12:46.353488 TX Vref Scan disable
8960 20:12:46.359729 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8961 20:12:46.360017 == TX Byte 0 ==
8962 20:12:46.362994 u2DelayCellOfst[0]=13 cells (4 PI)
8963 20:12:46.366413 u2DelayCellOfst[1]=6 cells (2 PI)
8964 20:12:46.369986 u2DelayCellOfst[2]=0 cells (0 PI)
8965 20:12:46.373160 u2DelayCellOfst[3]=3 cells (1 PI)
8966 20:12:46.376085 u2DelayCellOfst[4]=6 cells (2 PI)
8967 20:12:46.379518 u2DelayCellOfst[5]=16 cells (5 PI)
8968 20:12:46.383189 u2DelayCellOfst[6]=16 cells (5 PI)
8969 20:12:46.386559 u2DelayCellOfst[7]=3 cells (1 PI)
8970 20:12:46.389616 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8971 20:12:46.393122 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8972 20:12:46.396458 == TX Byte 1 ==
8973 20:12:46.399566 u2DelayCellOfst[8]=0 cells (0 PI)
8974 20:12:46.399962 u2DelayCellOfst[9]=3 cells (1 PI)
8975 20:12:46.402982 u2DelayCellOfst[10]=10 cells (3 PI)
8976 20:12:46.406587 u2DelayCellOfst[11]=0 cells (0 PI)
8977 20:12:46.409538 u2DelayCellOfst[12]=13 cells (4 PI)
8978 20:12:46.412853 u2DelayCellOfst[13]=13 cells (4 PI)
8979 20:12:46.416183 u2DelayCellOfst[14]=16 cells (5 PI)
8980 20:12:46.419535 u2DelayCellOfst[15]=16 cells (5 PI)
8981 20:12:46.423084 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8982 20:12:46.429989 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8983 20:12:46.430486 DramC Write-DBI on
8984 20:12:46.430803 ==
8985 20:12:46.433409 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 20:12:46.439969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 20:12:46.440461 ==
8988 20:12:46.440773
8989 20:12:46.441059
8990 20:12:46.441334 TX Vref Scan disable
8991 20:12:46.443533 == TX Byte 0 ==
8992 20:12:46.446952 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8993 20:12:46.450027 == TX Byte 1 ==
8994 20:12:46.453418 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8995 20:12:46.456709 DramC Write-DBI off
8996 20:12:46.457101
8997 20:12:46.457411 [DATLAT]
8998 20:12:46.457700 Freq=1600, CH1 RK1
8999 20:12:46.458037
9000 20:12:46.460032 DATLAT Default: 0xf
9001 20:12:46.460431 0, 0xFFFF, sum = 0
9002 20:12:46.463116 1, 0xFFFF, sum = 0
9003 20:12:46.466813 2, 0xFFFF, sum = 0
9004 20:12:46.467319 3, 0xFFFF, sum = 0
9005 20:12:46.469780 4, 0xFFFF, sum = 0
9006 20:12:46.470203 5, 0xFFFF, sum = 0
9007 20:12:46.473188 6, 0xFFFF, sum = 0
9008 20:12:46.473583 7, 0xFFFF, sum = 0
9009 20:12:46.476369 8, 0xFFFF, sum = 0
9010 20:12:46.476871 9, 0xFFFF, sum = 0
9011 20:12:46.480002 10, 0xFFFF, sum = 0
9012 20:12:46.480503 11, 0xFFFF, sum = 0
9013 20:12:46.483203 12, 0xFFFF, sum = 0
9014 20:12:46.483601 13, 0xFFFF, sum = 0
9015 20:12:46.486914 14, 0x0, sum = 1
9016 20:12:46.487418 15, 0x0, sum = 2
9017 20:12:46.490321 16, 0x0, sum = 3
9018 20:12:46.490819 17, 0x0, sum = 4
9019 20:12:46.493122 best_step = 15
9020 20:12:46.493511
9021 20:12:46.493823 ==
9022 20:12:46.496882 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 20:12:46.500343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 20:12:46.500843 ==
9025 20:12:46.501158 RX Vref Scan: 0
9026 20:12:46.503516
9027 20:12:46.504003 RX Vref 0 -> 0, step: 1
9028 20:12:46.504316
9029 20:12:46.506390 RX Delay 19 -> 252, step: 4
9030 20:12:46.510088 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9031 20:12:46.516470 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9032 20:12:46.519997 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9033 20:12:46.523343 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9034 20:12:46.527009 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9035 20:12:46.530272 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9036 20:12:46.533210 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9037 20:12:46.540428 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9038 20:12:46.543224 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9039 20:12:46.546846 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9040 20:12:46.549975 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9041 20:12:46.553324 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9042 20:12:46.559598 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
9043 20:12:46.562867 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9044 20:12:46.566414 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9045 20:12:46.569858 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9046 20:12:46.570394 ==
9047 20:12:46.573207 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 20:12:46.579924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 20:12:46.580495 ==
9050 20:12:46.580870 DQS Delay:
9051 20:12:46.581218 DQS0 = 0, DQS1 = 0
9052 20:12:46.583002 DQM Delay:
9053 20:12:46.583472 DQM0 = 133, DQM1 = 130
9054 20:12:46.586721 DQ Delay:
9055 20:12:46.589475 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
9056 20:12:46.592767 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9057 20:12:46.596102 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =126
9058 20:12:46.600009 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
9059 20:12:46.600583
9060 20:12:46.600956
9061 20:12:46.601300
9062 20:12:46.602959 [DramC_TX_OE_Calibration] TA2
9063 20:12:46.606032 Original DQ_B0 (3 6) =30, OEN = 27
9064 20:12:46.609734 Original DQ_B1 (3 6) =30, OEN = 27
9065 20:12:46.613226 24, 0x0, End_B0=24 End_B1=24
9066 20:12:46.613803 25, 0x0, End_B0=25 End_B1=25
9067 20:12:46.616278 26, 0x0, End_B0=26 End_B1=26
9068 20:12:46.619859 27, 0x0, End_B0=27 End_B1=27
9069 20:12:46.622869 28, 0x0, End_B0=28 End_B1=28
9070 20:12:46.626449 29, 0x0, End_B0=29 End_B1=29
9071 20:12:46.627029 30, 0x0, End_B0=30 End_B1=30
9072 20:12:46.629718 31, 0x4141, End_B0=30 End_B1=30
9073 20:12:46.633158 Byte0 end_step=30 best_step=27
9074 20:12:46.636183 Byte1 end_step=30 best_step=27
9075 20:12:46.639688 Byte0 TX OE(2T, 0.5T) = (3, 3)
9076 20:12:46.642876 Byte1 TX OE(2T, 0.5T) = (3, 3)
9077 20:12:46.643448
9078 20:12:46.643820
9079 20:12:46.649588 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9080 20:12:46.653042 CH1 RK1: MR19=303, MR18=1C07
9081 20:12:46.659119 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9082 20:12:46.662694 [RxdqsGatingPostProcess] freq 1600
9083 20:12:46.665990 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9084 20:12:46.669363 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 20:12:46.672862 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 20:12:46.676587 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 20:12:46.679301 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 20:12:46.682658 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 20:12:46.686319 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 20:12:46.689340 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 20:12:46.693099 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 20:12:46.695824 Pre-setting of DQS Precalculation
9093 20:12:46.699100 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9094 20:12:46.706025 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9095 20:12:46.712896 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 20:12:46.713496
9097 20:12:46.713867
9098 20:12:46.715956 [Calibration Summary] 3200 Mbps
9099 20:12:46.719340 CH 0, Rank 0
9100 20:12:46.719919 SW Impedance : PASS
9101 20:12:46.722649 DUTY Scan : NO K
9102 20:12:46.725907 ZQ Calibration : PASS
9103 20:12:46.726652 Jitter Meter : NO K
9104 20:12:46.729722 CBT Training : PASS
9105 20:12:46.732788 Write leveling : PASS
9106 20:12:46.733363 RX DQS gating : PASS
9107 20:12:46.735943 RX DQ/DQS(RDDQC) : PASS
9108 20:12:46.739589 TX DQ/DQS : PASS
9109 20:12:46.740171 RX DATLAT : PASS
9110 20:12:46.742713 RX DQ/DQS(Engine): PASS
9111 20:12:46.743181 TX OE : PASS
9112 20:12:46.745878 All Pass.
9113 20:12:46.746377
9114 20:12:46.746750 CH 0, Rank 1
9115 20:12:46.749563 SW Impedance : PASS
9116 20:12:46.750209 DUTY Scan : NO K
9117 20:12:46.752869 ZQ Calibration : PASS
9118 20:12:46.755745 Jitter Meter : NO K
9119 20:12:46.756401 CBT Training : PASS
9120 20:12:46.759343 Write leveling : PASS
9121 20:12:46.762449 RX DQS gating : PASS
9122 20:12:46.762957 RX DQ/DQS(RDDQC) : PASS
9123 20:12:46.766041 TX DQ/DQS : PASS
9124 20:12:46.769245 RX DATLAT : PASS
9125 20:12:46.769838 RX DQ/DQS(Engine): PASS
9126 20:12:46.772799 TX OE : PASS
9127 20:12:46.773371 All Pass.
9128 20:12:46.773745
9129 20:12:46.776186 CH 1, Rank 0
9130 20:12:46.776752 SW Impedance : PASS
9131 20:12:46.779230 DUTY Scan : NO K
9132 20:12:46.782511 ZQ Calibration : PASS
9133 20:12:46.783077 Jitter Meter : NO K
9134 20:12:46.785786 CBT Training : PASS
9135 20:12:46.789483 Write leveling : PASS
9136 20:12:46.790118 RX DQS gating : PASS
9137 20:12:46.792256 RX DQ/DQS(RDDQC) : PASS
9138 20:12:46.792758 TX DQ/DQS : PASS
9139 20:12:46.795737 RX DATLAT : PASS
9140 20:12:46.798933 RX DQ/DQS(Engine): PASS
9141 20:12:46.799408 TX OE : PASS
9142 20:12:46.802621 All Pass.
9143 20:12:46.803186
9144 20:12:46.803562 CH 1, Rank 1
9145 20:12:46.805877 SW Impedance : PASS
9146 20:12:46.806487 DUTY Scan : NO K
9147 20:12:46.809008 ZQ Calibration : PASS
9148 20:12:46.812362 Jitter Meter : NO K
9149 20:12:46.812933 CBT Training : PASS
9150 20:12:46.815670 Write leveling : PASS
9151 20:12:46.818897 RX DQS gating : PASS
9152 20:12:46.819463 RX DQ/DQS(RDDQC) : PASS
9153 20:12:46.822302 TX DQ/DQS : PASS
9154 20:12:46.826031 RX DATLAT : PASS
9155 20:12:46.826616 RX DQ/DQS(Engine): PASS
9156 20:12:46.828853 TX OE : PASS
9157 20:12:46.829426 All Pass.
9158 20:12:46.829801
9159 20:12:46.832422 DramC Write-DBI on
9160 20:12:46.836161 PER_BANK_REFRESH: Hybrid Mode
9161 20:12:46.836730 TX_TRACKING: ON
9162 20:12:46.845727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9163 20:12:46.852304 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9164 20:12:46.858760 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9165 20:12:46.862188 [FAST_K] Save calibration result to emmc
9166 20:12:46.865882 sync common calibartion params.
9167 20:12:46.868732 sync cbt_mode0:1, 1:1
9168 20:12:46.872570 dram_init: ddr_geometry: 2
9169 20:12:46.873164 dram_init: ddr_geometry: 2
9170 20:12:46.875687 dram_init: ddr_geometry: 2
9171 20:12:46.878810 0:dram_rank_size:100000000
9172 20:12:46.879502 1:dram_rank_size:100000000
9173 20:12:46.885320 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9174 20:12:46.888686 DFS_SHUFFLE_HW_MODE: ON
9175 20:12:46.892212 dramc_set_vcore_voltage set vcore to 725000
9176 20:12:46.895190 Read voltage for 1600, 0
9177 20:12:46.895870 Vio18 = 0
9178 20:12:46.896257 Vcore = 725000
9179 20:12:46.898598 Vdram = 0
9180 20:12:46.899112 Vddq = 0
9181 20:12:46.899486 Vmddr = 0
9182 20:12:46.902081 switch to 3200 Mbps bootup
9183 20:12:46.902673 [DramcRunTimeConfig]
9184 20:12:46.905403 PHYPLL
9185 20:12:46.905869 DPM_CONTROL_AFTERK: ON
9186 20:12:46.908496 PER_BANK_REFRESH: ON
9187 20:12:46.912249 REFRESH_OVERHEAD_REDUCTION: ON
9188 20:12:46.912819 CMD_PICG_NEW_MODE: OFF
9189 20:12:46.915661 XRTWTW_NEW_MODE: ON
9190 20:12:46.916231 XRTRTR_NEW_MODE: ON
9191 20:12:46.918651 TX_TRACKING: ON
9192 20:12:46.919120 RDSEL_TRACKING: OFF
9193 20:12:46.921779 DQS Precalculation for DVFS: ON
9194 20:12:46.925566 RX_TRACKING: OFF
9195 20:12:46.926201 HW_GATING DBG: ON
9196 20:12:46.928815 ZQCS_ENABLE_LP4: ON
9197 20:12:46.929386 RX_PICG_NEW_MODE: ON
9198 20:12:46.932032 TX_PICG_NEW_MODE: ON
9199 20:12:46.935370 ENABLE_RX_DCM_DPHY: ON
9200 20:12:46.935940 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9201 20:12:46.938735 DUMMY_READ_FOR_TRACKING: OFF
9202 20:12:46.942107 !!! SPM_CONTROL_AFTERK: OFF
9203 20:12:46.945447 !!! SPM could not control APHY
9204 20:12:46.946068 IMPEDANCE_TRACKING: ON
9205 20:12:46.948713 TEMP_SENSOR: ON
9206 20:12:46.949181 HW_SAVE_FOR_SR: OFF
9207 20:12:46.952017 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9208 20:12:46.955347 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9209 20:12:46.958486 Read ODT Tracking: ON
9210 20:12:46.961604 Refresh Rate DeBounce: ON
9211 20:12:46.962113 DFS_NO_QUEUE_FLUSH: ON
9212 20:12:46.965145 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9213 20:12:46.968629 ENABLE_DFS_RUNTIME_MRW: OFF
9214 20:12:46.972347 DDR_RESERVE_NEW_MODE: ON
9215 20:12:46.972917 MR_CBT_SWITCH_FREQ: ON
9216 20:12:46.974891 =========================
9217 20:12:46.994310 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9218 20:12:46.997583 dram_init: ddr_geometry: 2
9219 20:12:47.015768 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9220 20:12:47.019020 dram_init: dram init end (result: 0)
9221 20:12:47.025996 DRAM-K: Full calibration passed in 24510 msecs
9222 20:12:47.029099 MRC: failed to locate region type 0.
9223 20:12:47.029674 DRAM rank0 size:0x100000000,
9224 20:12:47.032324 DRAM rank1 size=0x100000000
9225 20:12:47.042266 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9226 20:12:47.049207 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9227 20:12:47.055795 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9228 20:12:47.062105 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9229 20:12:47.065396 DRAM rank0 size:0x100000000,
9230 20:12:47.068988 DRAM rank1 size=0x100000000
9231 20:12:47.069459 CBMEM:
9232 20:12:47.072244 IMD: root @ 0xfffff000 254 entries.
9233 20:12:47.075520 IMD: root @ 0xffffec00 62 entries.
9234 20:12:47.078868 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9235 20:12:47.082149 WARNING: RO_VPD is uninitialized or empty.
9236 20:12:47.089031 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9237 20:12:47.095993 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9238 20:12:47.108506 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9239 20:12:47.120297 BS: romstage times (exec / console): total (unknown) / 24007 ms
9240 20:12:47.120873
9241 20:12:47.121239
9242 20:12:47.129529 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9243 20:12:47.133122 ARM64: Exception handlers installed.
9244 20:12:47.136559 ARM64: Testing exception
9245 20:12:47.139554 ARM64: Done test exception
9246 20:12:47.140156 Enumerating buses...
9247 20:12:47.143083 Show all devs... Before device enumeration.
9248 20:12:47.146637 Root Device: enabled 1
9249 20:12:47.149818 CPU_CLUSTER: 0: enabled 1
9250 20:12:47.150333 CPU: 00: enabled 1
9251 20:12:47.153324 Compare with tree...
9252 20:12:47.153786 Root Device: enabled 1
9253 20:12:47.156707 CPU_CLUSTER: 0: enabled 1
9254 20:12:47.159783 CPU: 00: enabled 1
9255 20:12:47.160246 Root Device scanning...
9256 20:12:47.163233 scan_static_bus for Root Device
9257 20:12:47.166630 CPU_CLUSTER: 0 enabled
9258 20:12:47.169846 scan_static_bus for Root Device done
9259 20:12:47.173637 scan_bus: bus Root Device finished in 8 msecs
9260 20:12:47.174268 done
9261 20:12:47.179784 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9262 20:12:47.183389 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9263 20:12:47.190082 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9264 20:12:47.192922 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9265 20:12:47.196382 Allocating resources...
9266 20:12:47.199557 Reading resources...
9267 20:12:47.202605 Root Device read_resources bus 0 link: 0
9268 20:12:47.203074 DRAM rank0 size:0x100000000,
9269 20:12:47.206351 DRAM rank1 size=0x100000000
9270 20:12:47.209489 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9271 20:12:47.212946 CPU: 00 missing read_resources
9272 20:12:47.216366 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9273 20:12:47.223145 Root Device read_resources bus 0 link: 0 done
9274 20:12:47.223720 Done reading resources.
9275 20:12:47.229710 Show resources in subtree (Root Device)...After reading.
9276 20:12:47.232700 Root Device child on link 0 CPU_CLUSTER: 0
9277 20:12:47.235799 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 20:12:47.246315 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 20:12:47.246895 CPU: 00
9280 20:12:47.249578 Root Device assign_resources, bus 0 link: 0
9281 20:12:47.252693 CPU_CLUSTER: 0 missing set_resources
9282 20:12:47.259316 Root Device assign_resources, bus 0 link: 0 done
9283 20:12:47.259883 Done setting resources.
9284 20:12:47.266040 Show resources in subtree (Root Device)...After assigning values.
9285 20:12:47.269762 Root Device child on link 0 CPU_CLUSTER: 0
9286 20:12:47.272506 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 20:12:47.282671 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 20:12:47.283254 CPU: 00
9289 20:12:47.286097 Done allocating resources.
9290 20:12:47.290026 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9291 20:12:47.292543 Enabling resources...
9292 20:12:47.293009 done.
9293 20:12:47.299093 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9294 20:12:47.299661 Initializing devices...
9295 20:12:47.302639 Root Device init
9296 20:12:47.303103 init hardware done!
9297 20:12:47.305890 0x00000018: ctrlr->caps
9298 20:12:47.309099 52.000 MHz: ctrlr->f_max
9299 20:12:47.309696 0.400 MHz: ctrlr->f_min
9300 20:12:47.312676 0x40ff8080: ctrlr->voltages
9301 20:12:47.313283 sclk: 390625
9302 20:12:47.315872 Bus Width = 1
9303 20:12:47.316512 sclk: 390625
9304 20:12:47.318885 Bus Width = 1
9305 20:12:47.319355 Early init status = 3
9306 20:12:47.325688 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9307 20:12:47.328980 in-header: 03 fc 00 00 01 00 00 00
9308 20:12:47.329558 in-data: 00
9309 20:12:47.335904 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9310 20:12:47.338880 in-header: 03 fd 00 00 00 00 00 00
9311 20:12:47.342490 in-data:
9312 20:12:47.345665 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9313 20:12:47.349342 in-header: 03 fc 00 00 01 00 00 00
9314 20:12:47.352536 in-data: 00
9315 20:12:47.355888 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9316 20:12:47.361310 in-header: 03 fd 00 00 00 00 00 00
9317 20:12:47.365202 in-data:
9318 20:12:47.368006 [SSUSB] Setting up USB HOST controller...
9319 20:12:47.371747 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9320 20:12:47.374521 [SSUSB] phy power-on done.
9321 20:12:47.378400 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9322 20:12:47.385340 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9323 20:12:47.388393 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9324 20:12:47.394495 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9325 20:12:47.401381 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9326 20:12:47.407788 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9327 20:12:47.414768 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9328 20:12:47.421492 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9329 20:12:47.424957 SPM: binary array size = 0x9dc
9330 20:12:47.428063 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9331 20:12:47.434900 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9332 20:12:47.441672 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9333 20:12:47.444931 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9334 20:12:47.451022 configure_display: Starting display init
9335 20:12:47.485121 anx7625_power_on_init: Init interface.
9336 20:12:47.487893 anx7625_disable_pd_protocol: Disabled PD feature.
9337 20:12:47.491610 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9338 20:12:47.519175 anx7625_start_dp_work: Secure OCM version=00
9339 20:12:47.522603 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9340 20:12:47.537626 sp_tx_get_edid_block: EDID Block = 1
9341 20:12:47.640282 Extracted contents:
9342 20:12:47.643355 header: 00 ff ff ff ff ff ff 00
9343 20:12:47.646807 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9344 20:12:47.650284 version: 01 04
9345 20:12:47.653293 basic params: 95 1f 11 78 0a
9346 20:12:47.656766 chroma info: 76 90 94 55 54 90 27 21 50 54
9347 20:12:47.659554 established: 00 00 00
9348 20:12:47.665928 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9349 20:12:47.669319 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9350 20:12:47.676295 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 20:12:47.682639 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9352 20:12:47.689331 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9353 20:12:47.692432 extensions: 00
9354 20:12:47.692917 checksum: fb
9355 20:12:47.693347
9356 20:12:47.695918 Manufacturer: IVO Model 57d Serial Number 0
9357 20:12:47.699248 Made week 0 of 2020
9358 20:12:47.699771 EDID version: 1.4
9359 20:12:47.702560 Digital display
9360 20:12:47.705859 6 bits per primary color channel
9361 20:12:47.706343 DisplayPort interface
9362 20:12:47.709167 Maximum image size: 31 cm x 17 cm
9363 20:12:47.713165 Gamma: 220%
9364 20:12:47.713499 Check DPMS levels
9365 20:12:47.715737 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9366 20:12:47.719060 First detailed timing is preferred timing
9367 20:12:47.722143 Established timings supported:
9368 20:12:47.725501 Standard timings supported:
9369 20:12:47.729137 Detailed timings
9370 20:12:47.732261 Hex of detail: 383680a07038204018303c0035ae10000019
9371 20:12:47.735981 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9372 20:12:47.742209 0780 0798 07c8 0820 hborder 0
9373 20:12:47.745563 0438 043b 0447 0458 vborder 0
9374 20:12:47.749408 -hsync -vsync
9375 20:12:47.749827 Did detailed timing
9376 20:12:47.752824 Hex of detail: 000000000000000000000000000000000000
9377 20:12:47.755684 Manufacturer-specified data, tag 0
9378 20:12:47.762516 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9379 20:12:47.762935 ASCII string: InfoVision
9380 20:12:47.769461 Hex of detail: 000000fe00523134304e574635205248200a
9381 20:12:47.772775 ASCII string: R140NWF5 RH
9382 20:12:47.773200 Checksum
9383 20:12:47.773612 Checksum: 0xfb (valid)
9384 20:12:47.778958 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9385 20:12:47.782843 DSI data_rate: 832800000 bps
9386 20:12:47.785970 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9387 20:12:47.792679 anx7625_parse_edid: pixelclock(138800).
9388 20:12:47.796449 hactive(1920), hsync(48), hfp(24), hbp(88)
9389 20:12:47.799236 vactive(1080), vsync(12), vfp(3), vbp(17)
9390 20:12:47.802534 anx7625_dsi_config: config dsi.
9391 20:12:47.809140 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9392 20:12:47.821755 anx7625_dsi_config: success to config DSI
9393 20:12:47.825541 anx7625_dp_start: MIPI phy setup OK.
9394 20:12:47.828839 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9395 20:12:47.831556 mtk_ddp_mode_set invalid vrefresh 60
9396 20:12:47.835123 main_disp_path_setup
9397 20:12:47.835595 ovl_layer_smi_id_en
9398 20:12:47.839132 ovl_layer_smi_id_en
9399 20:12:47.839891 ccorr_config
9400 20:12:47.840289 aal_config
9401 20:12:47.841844 gamma_config
9402 20:12:47.842435 postmask_config
9403 20:12:47.845325 dither_config
9404 20:12:47.848817 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9405 20:12:47.855466 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9406 20:12:47.858921 Root Device init finished in 553 msecs
9407 20:12:47.859494 CPU_CLUSTER: 0 init
9408 20:12:47.868498 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9409 20:12:47.871997 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9410 20:12:47.875839 APU_MBOX 0x190000b0 = 0x10001
9411 20:12:47.878168 APU_MBOX 0x190001b0 = 0x10001
9412 20:12:47.882088 APU_MBOX 0x190005b0 = 0x10001
9413 20:12:47.885704 APU_MBOX 0x190006b0 = 0x10001
9414 20:12:47.888459 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9415 20:12:47.900623 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9416 20:12:47.913003 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9417 20:12:47.919943 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9418 20:12:47.931437 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9419 20:12:47.940649 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9420 20:12:47.944430 CPU_CLUSTER: 0 init finished in 81 msecs
9421 20:12:47.947026 Devices initialized
9422 20:12:47.950666 Show all devs... After init.
9423 20:12:47.951132 Root Device: enabled 1
9424 20:12:47.953603 CPU_CLUSTER: 0: enabled 1
9425 20:12:47.957140 CPU: 00: enabled 1
9426 20:12:47.960395 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9427 20:12:47.963519 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9428 20:12:47.966940 ELOG: NV offset 0x57f000 size 0x1000
9429 20:12:47.973612 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9430 20:12:47.980387 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9431 20:12:47.983554 ELOG: Event(17) added with size 13 at 2024-03-03 20:12:11 UTC
9432 20:12:47.987064 out: cmd=0x121: 03 db 21 01 00 00 00 00
9433 20:12:47.990670 in-header: 03 2b 00 00 2c 00 00 00
9434 20:12:48.004152 in-data: 34 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9435 20:12:48.010550 ELOG: Event(A1) added with size 10 at 2024-03-03 20:12:11 UTC
9436 20:12:48.017407 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9437 20:12:48.023899 ELOG: Event(A0) added with size 9 at 2024-03-03 20:12:11 UTC
9438 20:12:48.027175 elog_add_boot_reason: Logged dev mode boot
9439 20:12:48.030556 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9440 20:12:48.034084 Finalize devices...
9441 20:12:48.034674 Devices finalized
9442 20:12:48.040229 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9443 20:12:48.043578 Writing coreboot table at 0xffe64000
9444 20:12:48.047311 0. 000000000010a000-0000000000113fff: RAMSTAGE
9445 20:12:48.050713 1. 0000000040000000-00000000400fffff: RAM
9446 20:12:48.056962 2. 0000000040100000-000000004032afff: RAMSTAGE
9447 20:12:48.060261 3. 000000004032b000-00000000545fffff: RAM
9448 20:12:48.063797 4. 0000000054600000-000000005465ffff: BL31
9449 20:12:48.066953 5. 0000000054660000-00000000ffe63fff: RAM
9450 20:12:48.073995 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9451 20:12:48.076936 7. 0000000100000000-000000023fffffff: RAM
9452 20:12:48.080221 Passing 5 GPIOs to payload:
9453 20:12:48.083695 NAME | PORT | POLARITY | VALUE
9454 20:12:48.087011 EC in RW | 0x000000aa | low | undefined
9455 20:12:48.093527 EC interrupt | 0x00000005 | low | undefined
9456 20:12:48.097137 TPM interrupt | 0x000000ab | high | undefined
9457 20:12:48.103380 SD card detect | 0x00000011 | high | undefined
9458 20:12:48.106504 speaker enable | 0x00000093 | high | undefined
9459 20:12:48.109770 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9460 20:12:48.113531 in-header: 03 f9 00 00 02 00 00 00
9461 20:12:48.116798 in-data: 02 00
9462 20:12:48.117569 ADC[4]: Raw value=901770 ID=7
9463 20:12:48.120088 ADC[3]: Raw value=213179 ID=1
9464 20:12:48.123394 RAM Code: 0x71
9465 20:12:48.123879 ADC[6]: Raw value=74502 ID=0
9466 20:12:48.127012 ADC[5]: Raw value=212072 ID=1
9467 20:12:48.129681 SKU Code: 0x1
9468 20:12:48.133045 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5082
9469 20:12:48.136462 coreboot table: 964 bytes.
9470 20:12:48.139793 IMD ROOT 0. 0xfffff000 0x00001000
9471 20:12:48.143274 IMD SMALL 1. 0xffffe000 0x00001000
9472 20:12:48.146613 RO MCACHE 2. 0xffffc000 0x00001104
9473 20:12:48.149982 CONSOLE 3. 0xfff7c000 0x00080000
9474 20:12:48.153211 FMAP 4. 0xfff7b000 0x00000452
9475 20:12:48.156585 TIME STAMP 5. 0xfff7a000 0x00000910
9476 20:12:48.159251 VBOOT WORK 6. 0xfff66000 0x00014000
9477 20:12:48.162866 RAMOOPS 7. 0xffe66000 0x00100000
9478 20:12:48.166255 COREBOOT 8. 0xffe64000 0x00002000
9479 20:12:48.166728 IMD small region:
9480 20:12:48.169302 IMD ROOT 0. 0xffffec00 0x00000400
9481 20:12:48.172613 VPD 1. 0xffffeb80 0x0000006c
9482 20:12:48.179382 MMC STATUS 2. 0xffffeb60 0x00000004
9483 20:12:48.183074 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9484 20:12:48.185956 Probing TPM: done!
9485 20:12:48.189241 Connected to device vid:did:rid of 1ae0:0028:00
9486 20:12:48.199202 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9487 20:12:48.202707 Initialized TPM device CR50 revision 0
9488 20:12:48.206235 Checking cr50 for pending updates
9489 20:12:48.210140 Reading cr50 TPM mode
9490 20:12:48.218762 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9491 20:12:48.225583 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9492 20:12:48.265716 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9493 20:12:48.268738 Checking segment from ROM address 0x40100000
9494 20:12:48.272027 Checking segment from ROM address 0x4010001c
9495 20:12:48.279169 Loading segment from ROM address 0x40100000
9496 20:12:48.279701 code (compression=0)
9497 20:12:48.288868 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9498 20:12:48.295305 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9499 20:12:48.295751 it's not compressed!
9500 20:12:48.302450 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9501 20:12:48.305783 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9502 20:12:48.326013 Loading segment from ROM address 0x4010001c
9503 20:12:48.326575 Entry Point 0x80000000
9504 20:12:48.329429 Loaded segments
9505 20:12:48.332907 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9506 20:12:48.339765 Jumping to boot code at 0x80000000(0xffe64000)
9507 20:12:48.346293 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9508 20:12:48.352791 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9509 20:12:48.360379 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9510 20:12:48.363722 Checking segment from ROM address 0x40100000
9511 20:12:48.367302 Checking segment from ROM address 0x4010001c
9512 20:12:48.370812 Loading segment from ROM address 0x40100000
9513 20:12:48.374371 code (compression=1)
9514 20:12:48.380611 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9515 20:12:48.390526 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9516 20:12:48.391064 using LZMA
9517 20:12:48.399331 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9518 20:12:48.405465 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9519 20:12:48.408802 Loading segment from ROM address 0x4010001c
9520 20:12:48.409406 Entry Point 0x54601000
9521 20:12:48.412212 Loaded segments
9522 20:12:48.415976 NOTICE: MT8192 bl31_setup
9523 20:12:48.422574 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9524 20:12:48.425788 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9525 20:12:48.429354 WARNING: region 0:
9526 20:12:48.432721 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 20:12:48.433462 WARNING: region 1:
9528 20:12:48.439171 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9529 20:12:48.442812 WARNING: region 2:
9530 20:12:48.445806 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9531 20:12:48.449102 WARNING: region 3:
9532 20:12:48.452642 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9533 20:12:48.455938 WARNING: region 4:
9534 20:12:48.459437 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 20:12:48.462236 WARNING: region 5:
9536 20:12:48.465588 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 20:12:48.469442 WARNING: region 6:
9538 20:12:48.472573 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 20:12:48.473050 WARNING: region 7:
9540 20:12:48.479383 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 20:12:48.486323 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9542 20:12:48.489442 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9543 20:12:48.492859 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9544 20:12:48.499273 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9545 20:12:48.502471 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9546 20:12:48.505816 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9547 20:12:48.512576 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9548 20:12:48.516362 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9549 20:12:48.519248 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9550 20:12:48.526084 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9551 20:12:48.530018 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9552 20:12:48.536490 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9553 20:12:48.539325 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9554 20:12:48.542519 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9555 20:12:48.549598 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9556 20:12:48.552811 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9557 20:12:48.556109 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9558 20:12:48.562646 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9559 20:12:48.566254 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9560 20:12:48.569349 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9561 20:12:48.576143 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9562 20:12:48.579674 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9563 20:12:48.586200 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9564 20:12:48.589389 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9565 20:12:48.593238 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9566 20:12:48.600046 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9567 20:12:48.602976 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9568 20:12:48.609674 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9569 20:12:48.612708 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9570 20:12:48.616326 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9571 20:12:48.622650 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9572 20:12:48.626249 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9573 20:12:48.629779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9574 20:12:48.636440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9575 20:12:48.639923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9576 20:12:48.643009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9577 20:12:48.646561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9578 20:12:48.652953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9579 20:12:48.656053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9580 20:12:48.660044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9581 20:12:48.663177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9582 20:12:48.669629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9583 20:12:48.673016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9584 20:12:48.676451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9585 20:12:48.679504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9586 20:12:48.686167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9587 20:12:48.689474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9588 20:12:48.693204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9589 20:12:48.699666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9590 20:12:48.702884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9591 20:12:48.706516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9592 20:12:48.713005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9593 20:12:48.716296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9594 20:12:48.723210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9595 20:12:48.726562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9596 20:12:48.729667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9597 20:12:48.736096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9598 20:12:48.739553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9599 20:12:48.746433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9600 20:12:48.749531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9601 20:12:48.756640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9602 20:12:48.759830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9603 20:12:48.766508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9604 20:12:48.769703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9605 20:12:48.773085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9606 20:12:48.779447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9607 20:12:48.783303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9608 20:12:48.789740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9609 20:12:48.793417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9610 20:12:48.800203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9611 20:12:48.802802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9612 20:12:48.806486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9613 20:12:48.813256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9614 20:12:48.816545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9615 20:12:48.823257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9616 20:12:48.826528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9617 20:12:48.833792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9618 20:12:48.836652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9619 20:12:48.840238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9620 20:12:48.846463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9621 20:12:48.849863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9622 20:12:48.856811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9623 20:12:48.859824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9624 20:12:48.866709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9625 20:12:48.870008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9626 20:12:48.873089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9627 20:12:48.879920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9628 20:12:48.883631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9629 20:12:48.889743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9630 20:12:48.893390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9631 20:12:48.899907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9632 20:12:48.903155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9633 20:12:48.906488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9634 20:12:48.913440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9635 20:12:48.916479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9636 20:12:48.923319 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9637 20:12:48.926541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9638 20:12:48.929889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9639 20:12:48.933518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9640 20:12:48.940137 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9641 20:12:48.943268 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9642 20:12:48.946668 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9643 20:12:48.953065 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9644 20:12:48.956510 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9645 20:12:48.963300 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9646 20:12:48.966881 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9647 20:12:48.969856 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9648 20:12:48.977504 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9649 20:12:48.980374 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9650 20:12:48.983370 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9651 20:12:48.990621 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9652 20:12:48.993501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9653 20:12:49.000599 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9654 20:12:49.003877 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9655 20:12:49.007345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9656 20:12:49.014017 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9657 20:12:49.017346 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9658 20:12:49.020930 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9659 20:12:49.027464 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9660 20:12:49.030565 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9661 20:12:49.034068 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9662 20:12:49.037661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9663 20:12:49.040580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9664 20:12:49.047031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9665 20:12:49.050532 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9666 20:12:49.057475 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9667 20:12:49.060722 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9668 20:12:49.063901 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9669 20:12:49.070716 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9670 20:12:49.074353 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9671 20:12:49.077589 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9672 20:12:49.084042 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9673 20:12:49.087448 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9674 20:12:49.094160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9675 20:12:49.097547 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9676 20:12:49.101049 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9677 20:12:49.107706 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9678 20:12:49.110931 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9679 20:12:49.114505 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9680 20:12:49.120753 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9681 20:12:49.124204 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9682 20:12:49.131018 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9683 20:12:49.134072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9684 20:12:49.140640 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9685 20:12:49.144218 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9686 20:12:49.147855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9687 20:12:49.154112 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9688 20:12:49.157207 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9689 20:12:49.160593 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9690 20:12:49.167312 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9691 20:12:49.170546 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9692 20:12:49.177440 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9693 20:12:49.180658 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9694 20:12:49.183688 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9695 20:12:49.190450 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9696 20:12:49.193660 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9697 20:12:49.200584 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9698 20:12:49.203782 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9699 20:12:49.207253 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9700 20:12:49.213812 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9701 20:12:49.217330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9702 20:12:49.220395 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9703 20:12:49.226882 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9704 20:12:49.230321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9705 20:12:49.237060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9706 20:12:49.240614 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9707 20:12:49.244286 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9708 20:12:49.250644 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9709 20:12:49.253780 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9710 20:12:49.260400 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9711 20:12:49.263709 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9712 20:12:49.267027 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9713 20:12:49.274147 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9714 20:12:49.276965 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9715 20:12:49.283950 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9716 20:12:49.287199 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9717 20:12:49.290532 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9718 20:12:49.296901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9719 20:12:49.300212 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9720 20:12:49.303527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9721 20:12:49.310064 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9722 20:12:49.313233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9723 20:12:49.320233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9724 20:12:49.323570 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9725 20:12:49.326594 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9726 20:12:49.333659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9727 20:12:49.336868 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9728 20:12:49.343460 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9729 20:12:49.346612 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9730 20:12:49.350248 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9731 20:12:49.356971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9732 20:12:49.360157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9733 20:12:49.366392 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9734 20:12:49.369883 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9735 20:12:49.376920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9736 20:12:49.380299 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9737 20:12:49.383496 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9738 20:12:49.390255 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9739 20:12:49.393518 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9740 20:12:49.400099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9741 20:12:49.403425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9742 20:12:49.406578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9743 20:12:49.413195 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9744 20:12:49.416786 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9745 20:12:49.423181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9746 20:12:49.426419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9747 20:12:49.433284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9748 20:12:49.436395 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9749 20:12:49.440021 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9750 20:12:49.446770 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9751 20:12:49.449352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9752 20:12:49.456560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9753 20:12:49.459535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9754 20:12:49.466284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9755 20:12:49.469287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9756 20:12:49.472919 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9757 20:12:49.479848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9758 20:12:49.482764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9759 20:12:49.489512 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9760 20:12:49.492690 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9761 20:12:49.496306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9762 20:12:49.502497 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9763 20:12:49.506017 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9764 20:12:49.512514 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9765 20:12:49.516045 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9766 20:12:49.519473 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9767 20:12:49.525797 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9768 20:12:49.529492 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9769 20:12:49.536142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9770 20:12:49.539223 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9771 20:12:49.542699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9772 20:12:49.546126 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9773 20:12:49.552515 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9774 20:12:49.555843 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9775 20:12:49.559250 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9776 20:12:49.565885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9777 20:12:49.569442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9778 20:12:49.572550 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9779 20:12:49.579299 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9780 20:12:49.582567 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9781 20:12:49.585705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9782 20:12:49.592701 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9783 20:12:49.595820 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9784 20:12:49.599320 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9785 20:12:49.605720 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9786 20:12:49.609051 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9787 20:12:49.616160 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9788 20:12:49.618680 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9789 20:12:49.622194 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9790 20:12:49.629053 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9791 20:12:49.632315 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9792 20:12:49.635538 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9793 20:12:49.642099 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9794 20:12:49.645663 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9795 20:12:49.649018 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9796 20:12:49.655200 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9797 20:12:49.658688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9798 20:12:49.665457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9799 20:12:49.668236 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9800 20:12:49.671616 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9801 20:12:49.678335 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9802 20:12:49.681713 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9803 20:12:49.688625 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9804 20:12:49.691996 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9805 20:12:49.695143 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9806 20:12:49.701856 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9807 20:12:49.705638 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9808 20:12:49.708564 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9809 20:12:49.715022 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9810 20:12:49.718351 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9811 20:12:49.721799 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9812 20:12:49.724983 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9813 20:12:49.731577 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9814 20:12:49.734942 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9815 20:12:49.738188 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9816 20:12:49.741342 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9817 20:12:49.748261 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9818 20:12:49.751234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9819 20:12:49.754533 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9820 20:12:49.757913 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9821 20:12:49.764489 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9822 20:12:49.767795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9823 20:12:49.771294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9824 20:12:49.777916 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9825 20:12:49.781262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9826 20:12:49.787859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9827 20:12:49.791140 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9828 20:12:49.794430 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9829 20:12:49.801503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9830 20:12:49.804327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9831 20:12:49.810930 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9832 20:12:49.814615 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9833 20:12:49.817875 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9834 20:12:49.824877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9835 20:12:49.827815 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9836 20:12:49.834085 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9837 20:12:49.837347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9838 20:12:49.840911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9839 20:12:49.847567 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9840 20:12:49.851092 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9841 20:12:49.857478 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9842 20:12:49.860648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9843 20:12:49.867277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9844 20:12:49.870732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9845 20:12:49.873758 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9846 20:12:49.880717 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9847 20:12:49.883853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9848 20:12:49.890809 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9849 20:12:49.893801 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9850 20:12:49.897298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9851 20:12:49.903756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9852 20:12:49.907233 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9853 20:12:49.913772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9854 20:12:49.916842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9855 20:12:49.920262 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9856 20:12:49.927107 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9857 20:12:49.930349 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9858 20:12:49.936818 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9859 20:12:49.940137 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9860 20:12:49.946599 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9861 20:12:49.950318 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9862 20:12:49.953356 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9863 20:12:49.960176 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9864 20:12:49.963209 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9865 20:12:49.969826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9866 20:12:49.973243 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9867 20:12:49.976763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9868 20:12:49.983287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9869 20:12:49.986466 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9870 20:12:49.993345 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9871 20:12:49.996685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9872 20:12:49.999537 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9873 20:12:50.006510 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9874 20:12:50.009706 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9875 20:12:50.016835 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9876 20:12:50.019768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9877 20:12:50.026337 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9878 20:12:50.029611 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9879 20:12:50.033113 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9880 20:12:50.039527 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9881 20:12:50.042835 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9882 20:12:50.049525 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9883 20:12:50.052754 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9884 20:12:50.056179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9885 20:12:50.062742 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9886 20:12:50.066279 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9887 20:12:50.072551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9888 20:12:50.076227 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9889 20:12:50.079490 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9890 20:12:50.086386 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9891 20:12:50.089450 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9892 20:12:50.096452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9893 20:12:50.099369 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9894 20:12:50.102798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9895 20:12:50.109309 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9896 20:12:50.112557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9897 20:12:50.119215 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9898 20:12:50.122237 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9899 20:12:50.129529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9900 20:12:50.132596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9901 20:12:50.139186 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9902 20:12:50.142243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9903 20:12:50.146055 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9904 20:12:50.152738 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9905 20:12:50.155719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9906 20:12:50.162397 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9907 20:12:50.165718 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9908 20:12:50.171979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9909 20:12:50.175589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9910 20:12:50.178579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9911 20:12:50.185695 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9912 20:12:50.189173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9913 20:12:50.195433 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9914 20:12:50.198763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9915 20:12:50.205560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9916 20:12:50.208892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9917 20:12:50.215407 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9918 20:12:50.218465 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9919 20:12:50.222364 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9920 20:12:50.228855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9921 20:12:50.232052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9922 20:12:50.238570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9923 20:12:50.241909 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9924 20:12:50.248733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9925 20:12:50.252124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9926 20:12:50.255074 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9927 20:12:50.262044 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9928 20:12:50.265313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9929 20:12:50.271596 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9930 20:12:50.275029 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9931 20:12:50.282038 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9932 20:12:50.285204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9933 20:12:50.291794 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9934 20:12:50.294960 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9935 20:12:50.298486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9936 20:12:50.305397 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9937 20:12:50.307953 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9938 20:12:50.314734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9939 20:12:50.318258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9940 20:12:50.325013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9941 20:12:50.328470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9942 20:12:50.331512 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9943 20:12:50.338174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9944 20:12:50.341518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9945 20:12:50.348147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9946 20:12:50.351568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9947 20:12:50.358161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9948 20:12:50.361361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9949 20:12:50.368265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9950 20:12:50.371000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9951 20:12:50.374512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9952 20:12:50.381410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9953 20:12:50.384696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9954 20:12:50.391579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9955 20:12:50.394252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9956 20:12:50.401108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9957 20:12:50.404821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9958 20:12:50.410949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9959 20:12:50.414230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9960 20:12:50.421258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9961 20:12:50.424400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9962 20:12:50.430708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9963 20:12:50.434362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9964 20:12:50.440911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9965 20:12:50.444583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9966 20:12:50.450869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9967 20:12:50.454116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9968 20:12:50.461345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9969 20:12:50.464134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9970 20:12:50.470486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9971 20:12:50.474098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9972 20:12:50.480614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9973 20:12:50.484143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9974 20:12:50.490739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9975 20:12:50.494013 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9976 20:12:50.496877 INFO: [APUAPC] vio 0
9977 20:12:50.500914 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9978 20:12:50.507191 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9979 20:12:50.510700 INFO: [APUAPC] D0_APC_0: 0x400510
9980 20:12:50.513514 INFO: [APUAPC] D0_APC_1: 0x0
9981 20:12:50.514117 INFO: [APUAPC] D0_APC_2: 0x1540
9982 20:12:50.517300 INFO: [APUAPC] D0_APC_3: 0x0
9983 20:12:50.520206 INFO: [APUAPC] D1_APC_0: 0xffffffff
9984 20:12:50.523843 INFO: [APUAPC] D1_APC_1: 0xffffffff
9985 20:12:50.527142 INFO: [APUAPC] D1_APC_2: 0x3fffff
9986 20:12:50.529816 INFO: [APUAPC] D1_APC_3: 0x0
9987 20:12:50.533683 INFO: [APUAPC] D2_APC_0: 0xffffffff
9988 20:12:50.537038 INFO: [APUAPC] D2_APC_1: 0xffffffff
9989 20:12:50.540248 INFO: [APUAPC] D2_APC_2: 0x3fffff
9990 20:12:50.543221 INFO: [APUAPC] D2_APC_3: 0x0
9991 20:12:50.546712 INFO: [APUAPC] D3_APC_0: 0xffffffff
9992 20:12:50.550125 INFO: [APUAPC] D3_APC_1: 0xffffffff
9993 20:12:50.553567 INFO: [APUAPC] D3_APC_2: 0x3fffff
9994 20:12:50.556564 INFO: [APUAPC] D3_APC_3: 0x0
9995 20:12:50.560055 INFO: [APUAPC] D4_APC_0: 0xffffffff
9996 20:12:50.563048 INFO: [APUAPC] D4_APC_1: 0xffffffff
9997 20:12:50.566582 INFO: [APUAPC] D4_APC_2: 0x3fffff
9998 20:12:50.569802 INFO: [APUAPC] D4_APC_3: 0x0
9999 20:12:50.573276 INFO: [APUAPC] D5_APC_0: 0xffffffff
10000 20:12:50.576578 INFO: [APUAPC] D5_APC_1: 0xffffffff
10001 20:12:50.579915 INFO: [APUAPC] D5_APC_2: 0x3fffff
10002 20:12:50.582808 INFO: [APUAPC] D5_APC_3: 0x0
10003 20:12:50.586583 INFO: [APUAPC] D6_APC_0: 0xffffffff
10004 20:12:50.589568 INFO: [APUAPC] D6_APC_1: 0xffffffff
10005 20:12:50.593077 INFO: [APUAPC] D6_APC_2: 0x3fffff
10006 20:12:50.595969 INFO: [APUAPC] D6_APC_3: 0x0
10007 20:12:50.599909 INFO: [APUAPC] D7_APC_0: 0xffffffff
10008 20:12:50.603023 INFO: [APUAPC] D7_APC_1: 0xffffffff
10009 20:12:50.606047 INFO: [APUAPC] D7_APC_2: 0x3fffff
10010 20:12:50.609263 INFO: [APUAPC] D7_APC_3: 0x0
10011 20:12:50.612503 INFO: [APUAPC] D8_APC_0: 0xffffffff
10012 20:12:50.615765 INFO: [APUAPC] D8_APC_1: 0xffffffff
10013 20:12:50.619250 INFO: [APUAPC] D8_APC_2: 0x3fffff
10014 20:12:50.622478 INFO: [APUAPC] D8_APC_3: 0x0
10015 20:12:50.626146 INFO: [APUAPC] D9_APC_0: 0xffffffff
10016 20:12:50.629430 INFO: [APUAPC] D9_APC_1: 0xffffffff
10017 20:12:50.633058 INFO: [APUAPC] D9_APC_2: 0x3fffff
10018 20:12:50.635799 INFO: [APUAPC] D9_APC_3: 0x0
10019 20:12:50.639262 INFO: [APUAPC] D10_APC_0: 0xffffffff
10020 20:12:50.642607 INFO: [APUAPC] D10_APC_1: 0xffffffff
10021 20:12:50.646147 INFO: [APUAPC] D10_APC_2: 0x3fffff
10022 20:12:50.649045 INFO: [APUAPC] D10_APC_3: 0x0
10023 20:12:50.652797 INFO: [APUAPC] D11_APC_0: 0xffffffff
10024 20:12:50.655893 INFO: [APUAPC] D11_APC_1: 0xffffffff
10025 20:12:50.659336 INFO: [APUAPC] D11_APC_2: 0x3fffff
10026 20:12:50.662211 INFO: [APUAPC] D11_APC_3: 0x0
10027 20:12:50.665785 INFO: [APUAPC] D12_APC_0: 0xffffffff
10028 20:12:50.668597 INFO: [APUAPC] D12_APC_1: 0xffffffff
10029 20:12:50.672147 INFO: [APUAPC] D12_APC_2: 0x3fffff
10030 20:12:50.675418 INFO: [APUAPC] D12_APC_3: 0x0
10031 20:12:50.678829 INFO: [APUAPC] D13_APC_0: 0xffffffff
10032 20:12:50.682348 INFO: [APUAPC] D13_APC_1: 0xffffffff
10033 20:12:50.685553 INFO: [APUAPC] D13_APC_2: 0x3fffff
10034 20:12:50.688861 INFO: [APUAPC] D13_APC_3: 0x0
10035 20:12:50.692090 INFO: [APUAPC] D14_APC_0: 0xffffffff
10036 20:12:50.695338 INFO: [APUAPC] D14_APC_1: 0xffffffff
10037 20:12:50.698614 INFO: [APUAPC] D14_APC_2: 0x3fffff
10038 20:12:50.702288 INFO: [APUAPC] D14_APC_3: 0x0
10039 20:12:50.705199 INFO: [APUAPC] D15_APC_0: 0xffffffff
10040 20:12:50.708743 INFO: [APUAPC] D15_APC_1: 0xffffffff
10041 20:12:50.712101 INFO: [APUAPC] D15_APC_2: 0x3fffff
10042 20:12:50.715355 INFO: [APUAPC] D15_APC_3: 0x0
10043 20:12:50.718465 INFO: [APUAPC] APC_CON: 0x4
10044 20:12:50.721839 INFO: [NOCDAPC] D0_APC_0: 0x0
10045 20:12:50.725161 INFO: [NOCDAPC] D0_APC_1: 0x0
10046 20:12:50.728723 INFO: [NOCDAPC] D1_APC_0: 0x0
10047 20:12:50.729292 INFO: [NOCDAPC] D1_APC_1: 0xfff
10048 20:12:50.732010 INFO: [NOCDAPC] D2_APC_0: 0x0
10049 20:12:50.734769 INFO: [NOCDAPC] D2_APC_1: 0xfff
10050 20:12:50.738376 INFO: [NOCDAPC] D3_APC_0: 0x0
10051 20:12:50.741841 INFO: [NOCDAPC] D3_APC_1: 0xfff
10052 20:12:50.745129 INFO: [NOCDAPC] D4_APC_0: 0x0
10053 20:12:50.748044 INFO: [NOCDAPC] D4_APC_1: 0xfff
10054 20:12:50.751536 INFO: [NOCDAPC] D5_APC_0: 0x0
10055 20:12:50.754974 INFO: [NOCDAPC] D5_APC_1: 0xfff
10056 20:12:50.758574 INFO: [NOCDAPC] D6_APC_0: 0x0
10057 20:12:50.761608 INFO: [NOCDAPC] D6_APC_1: 0xfff
10058 20:12:50.762200 INFO: [NOCDAPC] D7_APC_0: 0x0
10059 20:12:50.765103 INFO: [NOCDAPC] D7_APC_1: 0xfff
10060 20:12:50.768062 INFO: [NOCDAPC] D8_APC_0: 0x0
10061 20:12:50.771307 INFO: [NOCDAPC] D8_APC_1: 0xfff
10062 20:12:50.774809 INFO: [NOCDAPC] D9_APC_0: 0x0
10063 20:12:50.778526 INFO: [NOCDAPC] D9_APC_1: 0xfff
10064 20:12:50.781070 INFO: [NOCDAPC] D10_APC_0: 0x0
10065 20:12:50.784592 INFO: [NOCDAPC] D10_APC_1: 0xfff
10066 20:12:50.787985 INFO: [NOCDAPC] D11_APC_0: 0x0
10067 20:12:50.791689 INFO: [NOCDAPC] D11_APC_1: 0xfff
10068 20:12:50.794462 INFO: [NOCDAPC] D12_APC_0: 0x0
10069 20:12:50.797836 INFO: [NOCDAPC] D12_APC_1: 0xfff
10070 20:12:50.801166 INFO: [NOCDAPC] D13_APC_0: 0x0
10071 20:12:50.803958 INFO: [NOCDAPC] D13_APC_1: 0xfff
10072 20:12:50.807613 INFO: [NOCDAPC] D14_APC_0: 0x0
10073 20:12:50.808089 INFO: [NOCDAPC] D14_APC_1: 0xfff
10074 20:12:50.811155 INFO: [NOCDAPC] D15_APC_0: 0x0
10075 20:12:50.814387 INFO: [NOCDAPC] D15_APC_1: 0xfff
10076 20:12:50.817365 INFO: [NOCDAPC] APC_CON: 0x4
10077 20:12:50.820941 INFO: [APUAPC] set_apusys_apc done
10078 20:12:50.824418 INFO: [DEVAPC] devapc_init done
10079 20:12:50.827892 INFO: GICv3 without legacy support detected.
10080 20:12:50.834197 INFO: ARM GICv3 driver initialized in EL3
10081 20:12:50.837215 INFO: Maximum SPI INTID supported: 639
10082 20:12:50.840695 INFO: BL31: Initializing runtime services
10083 20:12:50.847263 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10084 20:12:50.850683 INFO: SPM: enable CPC mode
10085 20:12:50.854176 INFO: mcdi ready for mcusys-off-idle and system suspend
10086 20:12:50.858254 INFO: BL31: Preparing for EL3 exit to normal world
10087 20:12:50.864127 INFO: Entry point address = 0x80000000
10088 20:12:50.864742 INFO: SPSR = 0x8
10089 20:12:50.870360
10090 20:12:50.870926
10091 20:12:50.871303
10092 20:12:50.873979 Starting depthcharge on Spherion...
10093 20:12:50.874554
10094 20:12:50.874933 Wipe memory regions:
10095 20:12:50.875281
10096 20:12:50.877746 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10097 20:12:50.878333 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10098 20:12:50.878770 Setting prompt string to ['asurada:']
10099 20:12:50.879215 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10100 20:12:50.879935 [0x00000040000000, 0x00000054600000)
10101 20:12:50.998826
10102 20:12:50.999466 [0x00000054660000, 0x00000080000000)
10103 20:12:51.259831
10104 20:12:51.260399 [0x000000821a7280, 0x000000ffe64000)
10105 20:12:52.004806
10106 20:12:52.005373 [0x00000100000000, 0x00000240000000)
10107 20:12:53.894676
10108 20:12:53.897767 Initializing XHCI USB controller at 0x11200000.
10109 20:12:54.935734
10110 20:12:54.939014 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10111 20:12:54.939527
10112 20:12:54.939896
10113 20:12:54.940237
10114 20:12:54.941055 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 20:12:55.042532 asurada: tftpboot 192.168.201.1 12928082/tftp-deploy-uyoxvert/kernel/image.itb 12928082/tftp-deploy-uyoxvert/kernel/cmdline
10117 20:12:55.043216 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 20:12:55.043734 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10119 20:12:55.048266 tftpboot 192.168.201.1 12928082/tftp-deploy-uyoxvert/kernel/image.ittp-deploy-uyoxvert/kernel/cmdline
10120 20:12:55.048798
10121 20:12:55.049163 Waiting for link
10122 20:12:55.209103
10123 20:12:55.209721 R8152: Initializing
10124 20:12:55.210147
10125 20:12:55.212105 Version 9 (ocp_data = 6010)
10126 20:12:55.212570
10127 20:12:55.215648 R8152: Done initializing
10128 20:12:55.216280
10129 20:12:55.216653 Adding net device
10130 20:12:57.083672
10131 20:12:57.084238 done.
10132 20:12:57.084611
10133 20:12:57.084974 MAC: 00:e0:4c:72:2d:d6
10134 20:12:57.085333
10135 20:12:57.087030 Sending DHCP discover... done.
10136 20:12:57.087495
10137 20:12:57.090197 Waiting for reply... done.
10138 20:12:57.090666
10139 20:12:57.093542 Sending DHCP request... done.
10140 20:12:57.094159
10141 20:12:57.094539 Waiting for reply... done.
10142 20:12:57.094889
10143 20:12:57.097325 My ip is 192.168.201.21
10144 20:12:57.097792
10145 20:12:57.100682 The DHCP server ip is 192.168.201.1
10146 20:12:57.101262
10147 20:12:57.103802 TFTP server IP predefined by user: 192.168.201.1
10148 20:12:57.104387
10149 20:12:57.110834 Bootfile predefined by user: 12928082/tftp-deploy-uyoxvert/kernel/image.itb
10150 20:12:57.111436
10151 20:12:57.113479 Sending tftp read request... done.
10152 20:12:57.113985
10153 20:12:57.116738 Waiting for the transfer...
10154 20:12:57.116822
10155 20:12:57.381814 00000000 ################################################################
10156 20:12:57.382000
10157 20:12:57.669360 00080000 ################################################################
10158 20:12:57.669495
10159 20:12:57.936185 00100000 ################################################################
10160 20:12:57.936314
10161 20:12:58.215383 00180000 ################################################################
10162 20:12:58.215569
10163 20:12:58.469594 00200000 ################################################################
10164 20:12:58.469740
10165 20:12:58.724991 00280000 ################################################################
10166 20:12:58.725126
10167 20:12:58.978692 00300000 ################################################################
10168 20:12:58.978836
10169 20:12:59.227638 00380000 ################################################################
10170 20:12:59.227775
10171 20:12:59.518690 00400000 ################################################################
10172 20:12:59.518834
10173 20:12:59.795581 00480000 ################################################################
10174 20:12:59.795748
10175 20:13:00.091827 00500000 ################################################################
10176 20:13:00.091957
10177 20:13:00.342511 00580000 ################################################################
10178 20:13:00.342665
10179 20:13:00.623173 00600000 ################################################################
10180 20:13:00.623356
10181 20:13:00.910899 00680000 ################################################################
10182 20:13:00.911051
10183 20:13:01.197027 00700000 ################################################################
10184 20:13:01.197180
10185 20:13:01.464119 00780000 ################################################################
10186 20:13:01.464286
10187 20:13:01.723434 00800000 ################################################################
10188 20:13:01.723564
10189 20:13:01.989245 00880000 ################################################################
10190 20:13:01.989374
10191 20:13:02.256131 00900000 ################################################################
10192 20:13:02.256263
10193 20:13:02.527798 00980000 ################################################################
10194 20:13:02.527945
10195 20:13:02.825307 00a00000 ################################################################
10196 20:13:02.825444
10197 20:13:03.123005 00a80000 ################################################################
10198 20:13:03.123136
10199 20:13:03.416284 00b00000 ################################################################
10200 20:13:03.416419
10201 20:13:03.711947 00b80000 ################################################################
10202 20:13:03.712082
10203 20:13:04.008402 00c00000 ################################################################
10204 20:13:04.008530
10205 20:13:04.284211 00c80000 ################################################################
10206 20:13:04.284340
10207 20:13:04.536418 00d00000 ################################################################
10208 20:13:04.536553
10209 20:13:04.785115 00d80000 ################################################################
10210 20:13:04.785241
10211 20:13:05.041503 00e00000 ################################################################
10212 20:13:05.041622
10213 20:13:05.337843 00e80000 ################################################################
10214 20:13:05.338000
10215 20:13:05.596483 00f00000 ################################################################
10216 20:13:05.596613
10217 20:13:05.855257 00f80000 ################################################################
10218 20:13:05.855383
10219 20:13:06.144907 01000000 ################################################################
10220 20:13:06.145038
10221 20:13:06.439592 01080000 ################################################################
10222 20:13:06.439798
10223 20:13:06.711594 01100000 ################################################################
10224 20:13:06.711728
10225 20:13:07.008302 01180000 ################################################################
10226 20:13:07.008435
10227 20:13:07.288105 01200000 ################################################################
10228 20:13:07.288239
10229 20:13:07.551232 01280000 ################################################################
10230 20:13:07.551358
10231 20:13:07.834652 01300000 ################################################################
10232 20:13:07.834807
10233 20:13:08.128234 01380000 ################################################################
10234 20:13:08.128371
10235 20:13:08.422575 01400000 ################################################################
10236 20:13:08.422703
10237 20:13:08.716469 01480000 ################################################################
10238 20:13:08.716607
10239 20:13:09.015138 01500000 ################################################################
10240 20:13:09.015273
10241 20:13:09.269763 01580000 ################################################################
10242 20:13:09.269894
10243 20:13:09.522315 01600000 ################################################################
10244 20:13:09.522453
10245 20:13:09.789394 01680000 ################################################################
10246 20:13:09.789527
10247 20:13:10.086103 01700000 ################################################################
10248 20:13:10.086230
10249 20:13:10.361148 01780000 ################################################################
10250 20:13:10.361275
10251 20:13:10.636377 01800000 ################################################################
10252 20:13:10.636532
10253 20:13:10.896006 01880000 ################################################################
10254 20:13:10.896162
10255 20:13:11.170329 01900000 ################################################################
10256 20:13:11.170479
10257 20:13:11.458355 01980000 ################################################################
10258 20:13:11.458483
10259 20:13:11.728202 01a00000 ################################################################
10260 20:13:11.728334
10261 20:13:11.993792 01a80000 ################################################################
10262 20:13:11.993948
10263 20:13:12.261330 01b00000 ################################################################
10264 20:13:12.261458
10265 20:13:12.540482 01b80000 ################################################################
10266 20:13:12.540613
10267 20:13:12.817821 01c00000 ################################################################
10268 20:13:12.817984
10269 20:13:12.837399 01c80000 ##### done.
10270 20:13:12.837483
10271 20:13:12.840582 The bootfile was 29917758 bytes long.
10272 20:13:12.840673
10273 20:13:12.844334 Sending tftp read request... done.
10274 20:13:12.844512
10275 20:13:12.844605 Waiting for the transfer...
10276 20:13:12.847553
10277 20:13:12.847727 00000000 # done.
10278 20:13:12.847813
10279 20:13:12.854154 Command line loaded dynamically from TFTP file: 12928082/tftp-deploy-uyoxvert/kernel/cmdline
10280 20:13:12.854340
10281 20:13:12.877280 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10282 20:13:12.877555
10283 20:13:12.877727 Loading FIT.
10284 20:13:12.877868
10285 20:13:12.880883 Image ramdisk-1 has 17808406 bytes.
10286 20:13:12.881087
10287 20:13:12.883857 Image fdt-1 has 47278 bytes.
10288 20:13:12.884058
10289 20:13:12.888333 Image kernel-1 has 12060038 bytes.
10290 20:13:12.888693
10291 20:13:12.897541 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10292 20:13:12.898130
10293 20:13:12.914289 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10294 20:13:12.914900
10295 20:13:12.920894 Choosing best match conf-1 for compat google,spherion-rev2.
10296 20:13:12.921465
10297 20:13:12.928737 Connected to device vid:did:rid of 1ae0:0028:00
10298 20:13:12.936561
10299 20:13:12.940564 tpm_get_response: command 0x17b, return code 0x0
10300 20:13:12.941156
10301 20:13:12.942760 ec_init: CrosEC protocol v3 supported (256, 248)
10302 20:13:12.947415
10303 20:13:12.950939 tpm_cleanup: add release locality here.
10304 20:13:12.951526
10305 20:13:12.952012 Shutting down all USB controllers.
10306 20:13:12.954006
10307 20:13:12.954484 Removing current net device
10308 20:13:12.954957
10309 20:13:12.960754 Exiting depthcharge with code 4 at timestamp: 51396275
10310 20:13:12.961343
10311 20:13:12.963671 LZMA decompressing kernel-1 to 0x821a6718
10312 20:13:12.964164
10313 20:13:12.967639 LZMA decompressing kernel-1 to 0x40000000
10314 20:13:14.466647
10315 20:13:14.467225 jumping to kernel
10316 20:13:14.468932 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10317 20:13:14.469477 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10318 20:13:14.469879 Setting prompt string to ['Linux version [0-9]']
10319 20:13:14.470287 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10320 20:13:14.470663 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10321 20:13:14.547880
10322 20:13:14.551024 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10323 20:13:14.555293 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10324 20:13:14.555845 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10325 20:13:14.556250 Setting prompt string to []
10326 20:13:14.556672 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10327 20:13:14.557077 Using line separator: #'\n'#
10328 20:13:14.557419 No login prompt set.
10329 20:13:14.557763 Parsing kernel messages
10330 20:13:14.558124 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10331 20:13:14.558688 [login-action] Waiting for messages, (timeout 00:04:02)
10332 20:13:14.559052 Waiting using forced prompt support (timeout 00:02:01)
10333 20:13:14.574777 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10334 20:13:14.577882 [ 0.000000] random: crng init done
10335 20:13:14.584458 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10336 20:13:14.587842 [ 0.000000] efi: UEFI not found.
10337 20:13:14.595217 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10338 20:13:14.601698 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10339 20:13:14.611309 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10340 20:13:14.621236 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10341 20:13:14.628452 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10342 20:13:14.634513 [ 0.000000] printk: bootconsole [mtk8250] enabled
10343 20:13:14.637974 [ 0.000000] NUMA: No NUMA configuration found
10344 20:13:14.647901 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10345 20:13:14.652237 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10346 20:13:14.654240 [ 0.000000] Zone ranges:
10347 20:13:14.661410 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10348 20:13:14.664464 [ 0.000000] DMA32 empty
10349 20:13:14.671616 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10350 20:13:14.675466 [ 0.000000] Movable zone start for each node
10351 20:13:14.678104 [ 0.000000] Early memory node ranges
10352 20:13:14.684593 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10353 20:13:14.690928 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10354 20:13:14.698009 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10355 20:13:14.701439 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10356 20:13:14.708164 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10357 20:13:14.714718 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10358 20:13:14.772903 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10359 20:13:14.779895 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10360 20:13:14.786395 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10361 20:13:14.789708 [ 0.000000] psci: probing for conduit method from DT.
10362 20:13:14.796371 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10363 20:13:14.799982 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10364 20:13:14.806380 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10365 20:13:14.809563 [ 0.000000] psci: SMC Calling Convention v1.2
10366 20:13:14.816151 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10367 20:13:14.819085 [ 0.000000] Detected VIPT I-cache on CPU0
10368 20:13:14.826069 [ 0.000000] CPU features: detected: GIC system register CPU interface
10369 20:13:14.832574 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10370 20:13:14.839107 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10371 20:13:14.846283 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10372 20:13:14.852450 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10373 20:13:14.862194 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10374 20:13:14.865638 [ 0.000000] alternatives: applying boot alternatives
10375 20:13:14.872288 [ 0.000000] Fallback order for Node 0: 0
10376 20:13:14.879124 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10377 20:13:14.882379 [ 0.000000] Policy zone: Normal
10378 20:13:14.905158 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10379 20:13:14.915263 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10380 20:13:14.926186 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10381 20:13:14.936120 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10382 20:13:14.942475 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10383 20:13:14.945772 <6>[ 0.000000] software IO TLB: area num 8.
10384 20:13:15.003489 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10385 20:13:15.152666 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10386 20:13:15.159978 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10387 20:13:15.166307 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10388 20:13:15.169406 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10389 20:13:15.176270 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10390 20:13:15.182787 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10391 20:13:15.186101 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10392 20:13:15.196046 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10393 20:13:15.202490 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10394 20:13:15.209295 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10395 20:13:15.216143 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10396 20:13:15.219013 <6>[ 0.000000] GICv3: 608 SPIs implemented
10397 20:13:15.222802 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10398 20:13:15.229751 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10399 20:13:15.232600 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10400 20:13:15.239182 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10401 20:13:15.252546 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10402 20:13:15.262533 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10403 20:13:15.272177 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10404 20:13:15.279413 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10405 20:13:15.292529 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10406 20:13:15.299140 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10407 20:13:15.305739 <6>[ 0.009184] Console: colour dummy device 80x25
10408 20:13:15.315647 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10409 20:13:15.322420 <6>[ 0.024378] pid_max: default: 32768 minimum: 301
10410 20:13:15.325572 <6>[ 0.029281] LSM: Security Framework initializing
10411 20:13:15.332392 <6>[ 0.034248] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 20:13:15.342353 <6>[ 0.042062] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 20:13:15.348716 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10414 20:13:15.355640 <6>[ 0.058910] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 20:13:15.365845 <6>[ 0.065249] cblist_init_generic: Setting adjustable number of callback queues.
10416 20:13:15.372299 <6>[ 0.072721] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 20:13:15.375290 <6>[ 0.079164] rcu: Hierarchical SRCU implementation.
10418 20:13:15.382195 <6>[ 0.079166] rcu: Max phase no-delay instances is 1000.
10419 20:13:15.388784 <6>[ 0.079191] printk: bootconsole [mtk8250] printing thread started
10420 20:13:15.395160 <6>[ 0.097542] EFI services will not be available.
10421 20:13:15.398262 <6>[ 0.097746] smp: Bringing up secondary CPUs ...
10422 20:13:15.401611 <6>[ 0.098058] Detected VIPT I-cache on CPU1
10423 20:13:15.412197 <6>[ 0.098128] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 20:13:15.418217 <6>[ 0.098159] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 20:13:15.427563 <6>[ 0.126035] Detected VIPT I-cache on CPU2
10426 20:13:15.437840 <6>[ 0.126083] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 20:13:15.444099 <6>[ 0.126098] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 20:13:15.447553 <6>[ 0.126356] Detected VIPT I-cache on CPU3
10429 20:13:15.454230 <6>[ 0.126403] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 20:13:15.460859 <6>[ 0.126416] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 20:13:15.464241 <6>[ 0.126729] CPU features: detected: Spectre-v4
10432 20:13:15.470587 <6>[ 0.126736] CPU features: detected: Spectre-BHB
10433 20:13:15.474043 <6>[ 0.126741] Detected PIPT I-cache on CPU4
10434 20:13:15.480811 <6>[ 0.126798] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 20:13:15.487156 <6>[ 0.126815] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 20:13:15.493694 <6>[ 0.127111] Detected PIPT I-cache on CPU5
10437 20:13:15.500447 <6>[ 0.127171] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 20:13:15.507206 <6>[ 0.127187] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 20:13:15.510484 <6>[ 0.127459] Detected PIPT I-cache on CPU6
10440 20:13:15.517042 <6>[ 0.127524] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 20:13:15.523582 <6>[ 0.127540] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 20:13:15.530492 <6>[ 0.127829] Detected PIPT I-cache on CPU7
10443 20:13:15.537236 <6>[ 0.127893] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 20:13:15.543933 <6>[ 0.127908] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 20:13:15.547477 <6>[ 0.127956] smp: Brought up 1 node, 8 CPUs
10446 20:13:15.553397 <6>[ 0.127961] SMP: Total of 8 processors activated.
10447 20:13:15.557105 <6>[ 0.127964] CPU features: detected: 32-bit EL0 Support
10448 20:13:15.566680 <6>[ 0.127966] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 20:13:15.573440 <6>[ 0.127968] CPU features: detected: Common not Private translations
10450 20:13:15.580128 <6>[ 0.127970] CPU features: detected: CRC32 instructions
10451 20:13:15.583662 <6>[ 0.127973] CPU features: detected: RCpc load-acquire (LDAPR)
10452 20:13:15.590082 <6>[ 0.127975] CPU features: detected: LSE atomic instructions
10453 20:13:15.596799 <6>[ 0.127976] CPU features: detected: Privileged Access Never
10454 20:13:15.603093 <6>[ 0.127978] CPU features: detected: RAS Extension Support
10455 20:13:15.610156 <6>[ 0.127981] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 20:13:15.613151 <6>[ 0.128046] CPU: All CPU(s) started at EL2
10457 20:13:15.641847 �íͽ�ɍ���ɍ�}���}��չѕ�5)�<6>[ 0.344<427] printk: console [ttyS0] printing thread started
10458 20:13:15.645435 5<6>[ 0.344471] printk: console [ttyS0] enabled
10459 20:13:15.651877 >[ 0.225599] VFS: Disk quotas dquot_6.6.0
10460 20:13:15.658474 <6>[ 0.344475] printk: bootconsole [mtk8250] disabled
10461 20:13:15.664712 <6>[ 0.358888] printk: bootconsole [mtk8250] printing thread stopped
10462 20:13:15.668199 <6>[ 0.360206] SuperH (H)SCI(F) driver initialized
10463 20:13:15.675213 <6>[ 0.360694] msm_serial: driver initialized
10464 20:13:15.681465 <6>[ 0.365280] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10465 20:13:15.691588 <6>[ 0.365311] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10466 20:13:15.697868 <6>[ 0.365340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10467 20:13:15.707682 <6>[ 0.365370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10468 20:13:15.720420 <6>[ 0.365391] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10469 20:13:15.726581 <6>[ 0.365418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10470 20:13:15.742725 <6>[ 0.365446] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10471 20:13:15.744154 <6>[ 0.365568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10472 20:13:15.752517 <6>[ 0.365597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10473 20:13:15.756996 <6>[ 0.376322] loop: module loaded
10474 20:13:15.763924 <6>[ 0.378912] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10475 20:13:15.767325 <4>[ 0.395836] mtk-pmic-keys: Failed to locate of_node [id: -1]
10476 20:13:15.770646 <6>[ 0.396793] megasas: 07.719.03.00-rc1
10477 20:13:15.777598 <6>[ 0.408916] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10478 20:13:15.780755 <6>[ 0.409061] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10479 20:13:15.787173 <6>[ 0.421154] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10480 20:13:15.800852 <6>[ 0.474979] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10481 20:13:16.262085 <6>[ 0.963270] Freeing initrd memory: 17384K
10482 20:13:16.269040 <6>[ 0.969555] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10483 20:13:16.272340 <6>[ 0.974154] tun: Universal TUN/TAP device driver, 1.6
10484 20:13:16.275680 <6>[ 0.974899] thunder_xcv, ver 1.0
10485 20:13:16.278761 <6>[ 0.974917] thunder_bgx, ver 1.0
10486 20:13:16.282110 <6>[ 0.974932] nicpf, ver 1.0
10487 20:13:16.288908 <6>[ 0.975969] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10488 20:13:16.295209 <6>[ 0.975972] hns3: Copyright (c) 2017 Huawei Corporation.
10489 20:13:16.298628 <6>[ 0.975997] hclge is initializing
10490 20:13:16.305227 <6>[ 0.976014] e1000: Intel(R) PRO/1000 Network Driver
10491 20:13:16.312258 <6>[ 0.976016] e1000: Copyright (c) 1999-2006 Intel Corporation.
10492 20:13:16.316156 <6>[ 0.976035] e1000e: Intel(R) PRO/1000 Network Driver
10493 20:13:16.322973 <6>[ 0.976037] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10494 20:13:16.326621 <6>[ 0.976054] igb: Intel(R) Gigabit Ethernet Network Driver
10495 20:13:16.333560 <6>[ 0.976056] igb: Copyright (c) 2007-2014 Intel Corporation.
10496 20:13:16.340682 <6>[ 0.976070] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10497 20:13:16.346979 <6>[ 0.976072] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10498 20:13:16.350656 <6>[ 0.976363] sky2: driver version 1.30
10499 20:13:16.357244 <6>[ 0.977416] VFIO - User Level meta-driver version: 0.3
10500 20:13:16.360342 <6>[ 0.980212] usbcore: registered new interface driver usb-storage
10501 20:13:16.367207 <6>[ 0.980392] usbcore: registered new device driver onboard-usb-hub
10502 20:13:16.373508 <6>[ 0.983182] mt6397-rtc mt6359-rtc: registered as rtc0
10503 20:13:16.383718 <6>[ 0.983336] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:12:39 UTC (1709496759)
10504 20:13:16.386935 <6>[ 0.983944] i2c_dev: i2c /dev entries driver
10505 20:13:16.393539 <6>[ 0.991075] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10506 20:13:16.400049 <6>[ 1.006059] cpu cpu0: EM: created perf domain
10507 20:13:16.403686 <6>[ 1.006373] cpu cpu4: EM: created perf domain
10508 20:13:16.409657 <6>[ 1.008016] sdhci: Secure Digital Host Controller Interface driver
10509 20:13:16.413136 <6>[ 1.008017] sdhci: Copyright(c) Pierre Ossman
10510 20:13:16.419971 <6>[ 1.008366] Synopsys Designware Multimedia Card Interface Driver
10511 20:13:16.426562 <6>[ 1.008733] sdhci-pltfm: SDHCI platform and OF driver helper
10512 20:13:16.433583 <6>[ 1.012988] ledtrig-cpu: registered to indicate activity on CPUs
10513 20:13:16.436812 <6>[ 1.013564] mmc0: CQHCI version 5.10
10514 20:13:16.443636 <6>[ 1.013617] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10515 20:13:16.450727 <6>[ 1.013892] usbcore: registered new interface driver usbhid
10516 20:13:16.453700 <6>[ 1.013894] usbhid: USB HID core driver
10517 20:13:16.459733 <6>[ 1.014020] spi_master spi0: will run message pump with realtime priority
10518 20:13:16.473924 <6>[ 1.042722] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10519 20:13:16.486443 <6>[ 1.044491] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10520 20:13:16.493256 <6>[ 1.046527] cros-ec-spi spi0.0: Chrome EC device registered
10521 20:13:16.502694 <6>[ 1.058832] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10522 20:13:16.506200 <6>[ 1.059797] NET: Registered PF_PACKET protocol family
10523 20:13:16.513137 <6>[ 1.059868] 9pnet: Installing 9P2000 support
10524 20:13:16.516039 <5>[ 1.059902] Key type dns_resolver registered
10525 20:13:16.519523 <6>[ 1.060176] registered taskstats version 1
10526 20:13:16.526297 <5>[ 1.060191] Loading compiled-in X.509 certificates
10527 20:13:16.536535 <4>[ 1.076324] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 20:13:16.546315 <4>[ 1.076591] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 20:13:16.553004 <3>[ 1.076612] debugfs: File 'uA_load' in directory '/' already present!
10530 20:13:16.559860 <3>[ 1.076624] debugfs: File 'min_uV' in directory '/' already present!
10531 20:13:16.566495 <3>[ 1.076631] debugfs: File 'max_uV' in directory '/' already present!
10532 20:13:16.573211 <3>[ 1.076637] debugfs: File 'constraint_flags' in directory '/' already present!
10533 20:13:16.583790 <3>[ 1.080390] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10534 20:13:16.589994 <6>[ 1.088046] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10535 20:13:16.593412 <6>[ 1.088679] xhci-mtk 11200000.usb: xHCI Host Controller
10536 20:13:16.602808 <6>[ 1.088701] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10537 20:13:16.612559 <6>[ 1.088919] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10538 20:13:16.616493 <6>[ 1.088971] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10539 20:13:16.622880 <6>[ 1.089066] xhci-mtk 11200000.usb: xHCI Host Controller
10540 20:13:16.629714 <6>[ 1.089075] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10541 20:13:16.636491 <6>[ 1.089084] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10542 20:13:16.643361 <6>[ 1.089718] hub 1-0:1.0: USB hub found
10543 20:13:16.646439 <6>[ 1.089747] hub 1-0:1.0: 1 port detected
10544 20:13:16.653103 <6>[ 1.090335] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10545 20:13:16.659834 <6>[ 1.090900] hub 2-0:1.0: USB hub found
10546 20:13:16.663030 <6>[ 1.090966] hub 2-0:1.0: 1 port detected
10547 20:13:16.666551 <6>[ 1.093727] mtk-msdc 11f70000.mmc: Got CD GPIO
10548 20:13:16.676738 <6>[ 1.100702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10549 20:13:16.682838 <6>[ 1.100709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10550 20:13:16.692961 <4>[ 1.100791] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10551 20:13:16.699685 <6>[ 1.101283] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10552 20:13:16.706407 <6>[ 1.101285] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10553 20:13:16.716261 <6>[ 1.101667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10554 20:13:16.723229 <6>[ 1.101677] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10555 20:13:16.729744 <6>[ 1.101679] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10556 20:13:16.740088 <6>[ 1.101683] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10557 20:13:16.750291 <6>[ 1.102997] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10558 20:13:16.757285 <6>[ 1.103008] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10559 20:13:16.766701 <6>[ 1.103011] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10560 20:13:16.773269 <6>[ 1.103013] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10561 20:13:16.783293 <6>[ 1.103016] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10562 20:13:16.789878 <6>[ 1.103019] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10563 20:13:16.799670 <6>[ 1.103021] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10564 20:13:16.806334 <6>[ 1.103023] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10565 20:13:16.816123 <6>[ 1.103026] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10566 20:13:16.822632 <6>[ 1.103028] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10567 20:13:16.833070 <6>[ 1.103031] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10568 20:13:16.839263 <6>[ 1.103034] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10569 20:13:16.849508 <6>[ 1.103037] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10570 20:13:16.856258 <6>[ 1.103039] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10571 20:13:16.865793 <6>[ 1.103041] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10572 20:13:16.872532 <6>[ 1.103399] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10573 20:13:16.878789 <6>[ 1.103995] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10574 20:13:16.885562 <6>[ 1.104232] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10575 20:13:16.892431 <6>[ 1.104468] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10576 20:13:16.898866 <6>[ 1.104717] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10577 20:13:16.908829 <6>[ 1.104877] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10578 20:13:16.915211 <6>[ 1.104887] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10579 20:13:16.925318 <6>[ 1.104889] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10580 20:13:16.934853 <6>[ 1.104893] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10581 20:13:16.944952 <6>[ 1.104897] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10582 20:13:16.954832 <6>[ 1.104901] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10583 20:13:16.964541 <6>[ 1.104904] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10584 20:13:16.971348 <6>[ 1.104906] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10585 20:13:16.981302 <6>[ 1.104909] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10586 20:13:16.991626 <6>[ 1.104914] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10587 20:13:17.001123 <6>[ 1.104917] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10588 20:13:17.011055 <6>[ 1.105293] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10589 20:13:17.014158 <6>[ 1.107902] mmc0: Command Queue Engine enabled
10590 20:13:17.021077 <6>[ 1.107916] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 20:13:17.027859 <6>[ 1.108456] mmcblk0: mmc0:0001 DA4128 116 GiB
10592 20:13:17.031036 <6>[ 1.111658] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10593 20:13:17.037629 <6>[ 1.112607] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 20:13:17.044158 <6>[ 1.113174] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10595 20:13:17.050669 <6>[ 1.113809] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10596 20:13:17.054033 <6>[ 1.128710] Trying to probe devices needed for running init ...
10597 20:13:17.063692 <6>[ 1.473843] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10598 20:13:17.067159 <6>[ 1.501313] hub 2-1:1.0: USB hub found
10599 20:13:17.070676 <6>[ 1.501748] hub 2-1:1.0: 3 ports detected
10600 20:13:17.073504 <6>[ 1.504831] hub 2-1:1.0: USB hub found
10601 20:13:17.080728 <6>[ 1.505172] hub 2-1:1.0: 3 ports detected
10602 20:13:17.087181 <6>[ 1.621643] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10603 20:13:17.090234 <6>[ 1.774408] hub 1-1:1.0: USB hub found
10604 20:13:17.093651 <6>[ 1.774801] hub 1-1:1.0: 4 ports detected
10605 20:13:17.096991 <6>[ 1.778415] hub 1-1:1.0: USB hub found
10606 20:13:17.103125 <6>[ 1.778687] hub 1-1:1.0: 4 ports detected
10607 20:13:17.161335 <6>[ 1.857898] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10608 20:13:17.393431 <6>[ 2.089770] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10609 20:13:17.514147 <6>[ 2.217272] hub 1-1.4:1.0: USB hub found
10610 20:13:17.516920 <6>[ 2.217691] hub 1-1.4:1.0: 2 ports detected
10611 20:13:17.520563 <6>[ 2.221091] hub 1-1.4:1.0: USB hub found
10612 20:13:17.527031 <6>[ 2.221405] hub 1-1.4:1.0: 2 ports detected
10613 20:13:17.813322 <6>[ 2.509763] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10614 20:13:17.997753 <6>[ 2.693753] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10615 20:13:28.705480 <6>[ 13.410771] ALSA device list:
10616 20:13:28.712369 <6>[ 13.410791] No soundcards found.
10617 20:13:28.715410 <6>[ 13.415081] Freeing unused kernel memory: 8448K
10618 20:13:28.718717 <6>[ 13.415231] Run /init as init process
10619 20:13:28.722593 Loading, please wait...
10620 20:13:28.737482 Starting version 247.3-7+deb11u4
10621 20:13:28.947878 <6>[ 13.647166] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10622 20:13:28.954227 <3>[ 13.651586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 20:13:28.964442 <3>[ 13.651659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 20:13:28.974302 <3>[ 13.651689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 20:13:28.981500 <3>[ 13.652215] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 20:13:28.991251 <3>[ 13.652230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 20:13:28.997993 <3>[ 13.652239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 20:13:29.007901 <3>[ 13.652254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 20:13:29.015131 <3>[ 13.652261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 20:13:29.025296 <3>[ 13.652312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 20:13:29.031656 <3>[ 13.658615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10632 20:13:29.038492 <3>[ 13.658638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 20:13:29.048395 <3>[ 13.658645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 20:13:29.055114 <3>[ 13.669332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 20:13:29.064833 <3>[ 13.669352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 20:13:29.071875 <3>[ 13.669356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 20:13:29.078768 <3>[ 13.669361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 20:13:29.088825 <3>[ 13.669364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 20:13:29.095083 <3>[ 13.669400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 20:13:29.101673 <6>[ 13.671796] remoteproc remoteproc0: scp is available
10641 20:13:29.105165 <6>[ 13.671905] remoteproc remoteproc0: powering up scp
10642 20:13:29.114898 <6>[ 13.671913] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10643 20:13:29.121829 <6>[ 13.671963] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10644 20:13:29.128190 <6>[ 13.677616] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10645 20:13:29.134759 <6>[ 13.680841] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10646 20:13:29.144733 <6>[ 13.680881] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10647 20:13:29.155106 <6>[ 13.680892] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10648 20:13:29.157898 <6>[ 13.681893] usbcore: registered new device driver r8152-cfgselector
10649 20:13:29.167943 <4>[ 13.703654] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10650 20:13:29.174421 <4>[ 13.703991] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10651 20:13:29.184662 <4>[ 13.704385] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10652 20:13:29.187937 <4>[ 13.704385] Fallback method does not support PEC.
10653 20:13:29.191170 <6>[ 13.719027] mc: Linux media interface: v0.10
10654 20:13:29.201057 <3>[ 13.721428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10655 20:13:29.211115 <3>[ 13.742333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 20:13:29.217299 <6>[ 13.786027] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10657 20:13:29.224142 <6>[ 13.797815] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10658 20:13:29.233929 <6>[ 13.797846] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10659 20:13:29.240613 <6>[ 13.797854] remoteproc remoteproc0: remote processor scp is now up
10660 20:13:29.247121 <6>[ 13.807677] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10661 20:13:29.256986 <6>[ 13.808329] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10662 20:13:29.267162 <6>[ 13.810514] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10663 20:13:29.276498 <6>[ 13.810717] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10664 20:13:29.283668 <6>[ 13.811364] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10665 20:13:29.293805 <4>[ 13.819146] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10666 20:13:29.303126 <4>[ 13.819162] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10667 20:13:29.310111 <6>[ 13.822885] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10668 20:13:29.313285 <6>[ 13.822894] pci_bus 0000:00: root bus resource [bus 00-ff]
10669 20:13:29.323423 <6>[ 13.822903] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10670 20:13:29.333070 <6>[ 13.822911] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10671 20:13:29.336454 <6>[ 13.822950] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10672 20:13:29.346484 <6>[ 13.822975] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10673 20:13:29.349635 <6>[ 13.823065] pci 0000:00:00.0: supports D1 D2
10674 20:13:29.356219 <6>[ 13.823070] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10675 20:13:29.362767 <6>[ 13.825119] videodev: Linux video capture interface: v2.00
10676 20:13:29.369282 <6>[ 13.825960] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10677 20:13:29.376041 <6>[ 13.826235] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10678 20:13:29.385767 <6>[ 13.826280] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10679 20:13:29.392625 <6>[ 13.826303] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10680 20:13:29.399384 <6>[ 13.826322] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10681 20:13:29.402784 <6>[ 13.826446] pci 0000:01:00.0: supports D1 D2
10682 20:13:29.412294 <6>[ 13.826449] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10683 20:13:29.419044 <6>[ 13.841640] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10684 20:13:29.425834 <6>[ 13.841684] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10685 20:13:29.432099 <6>[ 13.841690] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10686 20:13:29.441838 <6>[ 13.841703] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10687 20:13:29.448864 <6>[ 13.841719] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10688 20:13:29.458784 <6>[ 13.841734] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10689 20:13:29.462382 <6>[ 13.841750] pci 0000:00:00.0: PCI bridge to [bus 01]
10690 20:13:29.471975 <6>[ 13.841759] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10691 20:13:29.478364 <6>[ 13.841941] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10692 20:13:29.481485 <6>[ 13.842907] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10693 20:13:29.488557 <6>[ 13.843187] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10694 20:13:29.492168 <6>[ 13.846305] Bluetooth: Core ver 2.22
10695 20:13:29.498296 <6>[ 13.846442] NET: Registered PF_BLUETOOTH protocol family
10696 20:13:29.504864 <6>[ 13.846450] Bluetooth: HCI device and connection manager initialized
10697 20:13:29.512203 <6>[ 13.846483] Bluetooth: HCI socket layer initialized
10698 20:13:29.515111 <6>[ 13.846501] Bluetooth: L2CAP socket layer initialized
10699 20:13:29.521781 <6>[ 13.846516] Bluetooth: SCO socket layer initialized
10700 20:13:29.528285 <5>[ 13.865930] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10701 20:13:29.534902 <5>[ 13.877495] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10702 20:13:29.545046 <5>[ 13.878115] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10703 20:13:29.551095 <6>[ 13.878132] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10704 20:13:29.561114 <4>[ 13.878224] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10705 20:13:29.564882 <6>[ 13.878239] cfg80211: failed to load regulatory.db
10706 20:13:29.577660 <6>[ 13.879462] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10707 20:13:29.584361 <6>[ 13.879572] usbcore: registered new interface driver uvcvideo
10708 20:13:29.587844 <6>[ 13.886098] r8152 2-1.3:1.0 eth0: v1.12.13
10709 20:13:29.594087 <6>[ 13.886417] usbcore: registered new interface driver r8152
10710 20:13:29.597597 <6>[ 13.904409] usbcore: registered new interface driver btusb
10711 20:13:29.610805 <4>[ 13.911018] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10712 20:13:29.614178 <3>[ 13.911042] Bluetooth: hci0: Failed to load firmware file (-2)
10713 20:13:29.620781 <3>[ 13.911046] Bluetooth: hci0: Failed to set up firmware (-2)
10714 20:13:29.630860 <4>[ 13.911049] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10715 20:13:29.637378 <6>[ 13.920318] usbcore: registered new interface driver cdc_ether
10716 20:13:29.644114 <6>[ 13.928646] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10717 20:13:29.650756 <6>[ 13.935584] usbcore: registered new interface driver r8153_ecm
10718 20:13:29.657056 <6>[ 13.944360] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10719 20:13:29.663816 <6>[ 13.985172] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10720 20:13:29.670503 <6>[ 13.985272] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10721 20:13:29.677105 <6>[ 14.005656] mt7921e 0000:01:00.0: ASIC revision: 79610010
10722 20:13:29.683642 <6>[ 14.106157] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10723 20:13:29.687198 <6>[ 14.106157]
10724 20:13:29.693787 <6>[ 14.364084] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10725 20:13:29.697156 Begin: Loading essential drivers ... done.
10726 20:13:29.703528 Begin: Running /scripts/init-premount ... done.
10727 20:13:29.710294 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10728 20:13:29.720203 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10729 20:13:29.723611 Device /sys/class/net/enx00e04c722dd6 found
10730 20:13:29.724199 done.
10731 20:13:29.730251 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10732 20:13:30.500545 <6>[ 15.204640] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10733 20:13:30.744594 <6>[ 15.446182] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10734 20:13:30.778638 IP-Config: no response after 2 secs - giving up
10735 20:13:30.821221 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10736 20:13:31.551936 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10737 20:13:31.555142 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10738 20:13:31.561593 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10739 20:13:31.568297 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10740 20:13:31.574899 host : mt8192-asurada-spherion-r0-cbg-1
10741 20:13:31.581532 domain : lava-rack
10742 20:13:31.588449 rootserver: 192.168.201.1 rootpath:
10743 20:13:31.589204 filename :
10744 20:13:31.702055 done.
10745 20:13:31.709565 Begin: Running /scripts/nfs-bottom ... done.
10746 20:13:31.729254 Begin: Running /scripts/init-bottom ... done.
10747 20:13:32.944222 <6>[ 17.648471] NET: Registered PF_INET6 protocol family
10748 20:13:32.947202 <6>[ 17.652457] Segment Routing with IPv6
10749 20:13:32.953917 <6>[ 17.652470] In-situ OAM (IOAM) with IPv6
10750 20:13:33.084703 <30>[ 17.771805] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10751 20:13:33.091659 <30>[ 17.772804] systemd[1]: Detected architecture arm64.
10752 20:13:33.092235
10753 20:13:33.097900 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10754 20:13:33.098421
10755 20:13:33.116113 <30>[ 17.820568] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10756 20:13:34.023519 <30>[ 18.723476] systemd[1]: Queued start job for default target Graphical Interface.
10757 20:13:34.038585 [[0;32m OK [<30>[ 18.740211] systemd[1]: Created slice system-getty.slice.
10758 20:13:34.041717 0m] Created slice [0;1;39msystem-getty.slice[0m.
10759 20:13:34.060733 [[0;32m OK [0m] Created slic<30>[ 18.763123] systemd[1]: Created slice system-modprobe.slice.
10760 20:13:34.064385 e [0;1;39msystem-modprobe.slice[0m.
10761 20:13:34.084797 [[0;32m OK [0m] Created slic<30>[ 18.786965] systemd[1]: Created slice system-serial\x2dgetty.slice.
10762 20:13:34.092171 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10763 20:13:34.109070 [[0;32m OK [0m] Created slic<30>[ 18.810787] systemd[1]: Created slice User and Session Slice.
10764 20:13:34.111716 e [0;1;39mUser and Session Slice[0m.
10765 20:13:34.136050 [[0;32m OK [0m] Started [0;<30>[ 18.834597] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10766 20:13:34.139233 1;39mDispatch Password …ts to Console Directory Watch[0m.
10767 20:13:34.163383 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.861952] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10768 20:13:34.166479 sword R…uests to Wall Directory Watch[0m.
10769 20:13:34.190834 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.885906] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10770 20:13:34.197013 <30>[ 18.886088] systemd[1]: Reached target Local Encrypted Volumes.
10771 20:13:34.200263 l Encrypted Volumes[0m.
10772 20:13:34.219804 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.921885] systemd[1]: Reached target Paths.
10773 20:13:34.220613 s[0m.
10774 20:13:34.243194 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.941758] systemd[1]: Reached target Remote File Systems.
10775 20:13:34.243786 te File Systems[0m.
10776 20:13:34.264661 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 18.966078] systemd[1]: Reached target Slices.
10777 20:13:34.265250 es[0m.
10778 20:13:34.283695 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 18.985788] systemd[1]: Reached target Swap.
10779 20:13:34.284280 [0m.
10780 20:13:34.308156 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.006261] systemd[1]: Listening on initctl Compatibility Named Pipe.
10781 20:13:34.310812 l Compatibility Named Pipe[0m.
10782 20:13:34.321043 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.022464] systemd[1]: Listening on Journal Audit Socket.
10783 20:13:34.324593 l Audit Socket[0m.
10784 20:13:34.345576 [[0;32m OK [0m] Listening on<30>[ 19.047395] systemd[1]: Listening on Journal Socket (/dev/log).
10785 20:13:34.348759 [0;1;39mJournal Socket (/dev/log)[0m.
10786 20:13:34.369621 [[0;32m OK [0m] Listening on<30>[ 19.071106] systemd[1]: Listening on Journal Socket.
10787 20:13:34.373020 [0;1;39mJournal Socket[0m.
10788 20:13:34.389818 [[0;32m OK [0m] Listening on<30>[ 19.091849] systemd[1]: Listening on Network Service Netlink Socket.
10789 20:13:34.396532 [0;1;39mNetwork Service Netlink Socket[0m.
10790 20:13:34.415397 [[0;32m OK [<30>[ 19.116718] systemd[1]: Listening on udev Control Socket.
10791 20:13:34.418214 0m] Listening on [0;1;39mudev Control Socket[0m.
10792 20:13:34.438036 [[0;32m OK [0m] Listening on<30>[ 19.138874] systemd[1]: Listening on udev Kernel Socket.
10793 20:13:34.440813 [0;1;39mudev Kernel Socket[0m.
10794 20:13:34.484525 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.186166] systemd[1]: Mounting Huge Pages File System...
10795 20:13:34.487185 m[0m...
10796 20:13:34.508761 Mounting [0;1;39mPOSIX<30>[ 19.210769] systemd[1]: Mounting POSIX Message Queue File System...
10797 20:13:34.511901 Message Queue File System[0m...
10798 20:13:34.539217 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.238208] systemd[1]: Mounting Kernel Debug File System...
10799 20:13:34.539700 tem[0m...
10800 20:13:34.559055 <30>[ 19.258217] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10801 20:13:34.568986 <30>[ 19.265777] systemd[1]: Starting Create list of static device nodes for the current kernel...
10802 20:13:34.575670 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10803 20:13:34.600733 Starting [0;1;39mLoad <30>[ 19.302600] systemd[1]: Starting Load Kernel Module configfs...
10804 20:13:34.604098 Kernel Module configfs[0m...
10805 20:13:34.625001 Starting [0;1;39mLoad <30>[ 19.326707] systemd[1]: Starting Load Kernel Module drm...
10806 20:13:34.627867 Kernel Module drm[0m...
10807 20:13:34.664748 Starting [0;1;39mLoad <30>[ 19.366620] systemd[1]: Starting Load Kernel Module fuse...
10808 20:13:34.667723 Kernel Module fuse[0m...
10809 20:13:34.704507 <6>[ 19.406272] fuse: init (API version 7.37)
10810 20:13:34.713743 <30>[ 19.406565] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10811 20:13:34.740763 Starting [0;1;39mJourn<30>[ 19.442620] systemd[1]: Starting Journal Service...
10812 20:13:34.741341 al Service[0m...
10813 20:13:34.767867 <30>[ 19.473341] systemd[1]: Starting Load Kernel Modules...
10814 20:13:34.774340 Starting [0;1;39mLoad Kernel Modules[0m...
10815 20:13:34.796719 Starting [0;1;39mRemou<30>[ 19.498784] systemd[1]: Starting Remount Root and Kernel File Systems...
10816 20:13:34.800312 nt Root and Kernel File Systems[0m...
10817 20:13:34.824920 Starting [0;1;39mColdp<30>[ 19.527371] systemd[1]: Starting Coldplug All udev Devices...
10818 20:13:34.828099 lug All udev Devices[0m...
10819 20:13:34.852143 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 19.554529] systemd[1]: Mounted Huge Pages File System.
10820 20:13:34.855164 File System[0m.
10821 20:13:34.870950 <3>[ 19.572054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 20:13:34.881750 [[0;32m OK [0m] Mounted [0;<30>[ 19.583095] systemd[1]: Mounted POSIX Message Queue File System.
10823 20:13:34.884987 1;39mPOSIX Message Queue File System[0m.
10824 20:13:34.894475 <3>[ 19.593780] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 20:13:34.907542 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.610351] systemd[1]: Mounted Kernel Debug File System.
10826 20:13:34.911180 g File System[0m.
10827 20:13:34.935019 <3>[ 19.635021] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 20:13:34.945761 <30>[ 19.638422] systemd[1]: Finished Create list of static device nodes for the current kernel.
10829 20:13:34.955702 [[0;32m OK [0m] Finished [0<3>[ 19.655392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 20:13:34.963154 ;1;39mCreate list of st… nodes for the current kernel[0m.
10831 20:13:34.975125 <3>[ 19.676840] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 20:13:34.986875 [[0;32m OK [<30>[ 19.687505] systemd[1]: modprobe@configfs.service: Succeeded.
10833 20:13:34.993571 0m] Finished [0<30>[ 19.688236] systemd[1]: Finished Load Kernel Module configfs.
10834 20:13:35.003421 ;1;39mLoad Kernel Module configf<3>[ 19.704202] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 20:13:35.003990 s[0m.
10836 20:13:35.023176 <3>[ 19.725144] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 20:13:35.034387 [[0;32m OK [<30>[ 19.735623] systemd[1]: modprobe@drm.service: Succeeded.
10838 20:13:35.042099 0m] Finished [0<30>[ 19.736499] systemd[1]: Finished Load Kernel Module drm.
10839 20:13:35.045121 ;1;39mLoad Kernel Module drm[0m.
10840 20:13:35.058957 <3>[ 19.757636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 20:13:35.067154 [[0;32m OK [<30>[ 19.771560] systemd[1]: modprobe@fuse.service: Succeeded.
10842 20:13:35.077703 0m] Finished [0<30>[ 19.772318] systemd[1]: Finished Load Kernel Module fuse.
10843 20:13:35.087456 ;1;39mLoad Kerne<3>[ 19.779520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 20:13:35.088143 l Module fuse[0m.
10845 20:13:35.099350 <3>[ 19.799831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 20:13:35.109401 [[0;32m OK [0m] Finished [0<30>[ 19.811354] systemd[1]: Finished Load Kernel Modules.
10847 20:13:35.112897 ;1;39mLoad Kernel Modules[0m.
10848 20:13:35.129812 [[0;32m OK [0m] Finished [0<30>[ 19.831466] systemd[1]: Finished Remount Root and Kernel File Systems.
10849 20:13:35.133424 ;1;39mRemount Root and Kernel File Systems[0m.
10850 20:13:35.152337 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 19.854486] systemd[1]: Started Journal Service.
10851 20:13:35.155995 vice[0m.
10852 20:13:35.215965 Mounting [0;1;39mFUSE Control File System[0m...
10853 20:13:35.239902 Mounting [0;1;39mKernel Configuration File System[0m...
10854 20:13:35.262996 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10855 20:13:35.283471 Starting [0;1;39mLoad/Save Random Seed[0m...
10856 20:13:35.306808 <46>[ 20.008960] systemd-journald[309]: Received client request to flush runtime journal.
10857 20:13:35.313337 Starting [0;1;39mApply Kernel Variables[0m...
10858 20:13:35.334771 Starting [0;1;39mCreate System Users[0m...
10859 20:13:35.350148 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10860 20:13:35.368428 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10861 20:13:35.385708 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10862 20:13:35.401723 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10863 20:13:35.418535 <4>[ 20.110572] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10864 20:13:35.425015 <3>[ 20.110585] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10865 20:13:35.431619 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10866 20:13:35.447638 See 'systemctl status systemd-udev-trigger.service' for details.
10867 20:13:36.758855 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10868 20:13:36.800341 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10869 20:13:36.836709 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10870 20:13:36.933151 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10871 20:13:36.952099 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10872 20:13:36.968028 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10873 20:13:37.032653 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10874 20:13:37.059752 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10875 20:13:37.219115 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10876 20:13:37.277765 Starting [0;1;39mNetwork Service[0m...
10877 20:13:37.338577 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10878 20:13:37.409493 Starting [0;1;39mNetwork Time Synchronization[0m...
10879 20:13:37.429866 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10880 20:13:37.594341 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10881 20:13:37.614837 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10882 20:13:37.667728 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10883 20:13:37.970609 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10884 20:13:37.984047 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10885 20:13:38.004060 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10886 20:13:38.032774 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10887 20:13:38.054325 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10888 20:13:38.067291 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10889 20:13:38.090944 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10890 20:13:38.107431 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10891 20:13:38.128163 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10892 20:13:38.845123 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10893 20:13:39.185611 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10894 20:13:39.203909 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10895 20:13:39.224551 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10896 20:13:39.239330 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10897 20:13:39.260287 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10898 20:13:39.271413 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10899 20:13:39.287281 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10900 20:13:39.307139 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10901 20:13:39.344040 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10902 20:13:39.394616 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10903 20:13:39.484136 Starting [0;1;39mUser Login Management[0m...
10904 20:13:39.587718 Starting [0;1;39mNetwork Name Resolution[0m...
10905 20:13:39.616726 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10906 20:13:39.709056 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10907 20:13:39.729562 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10908 20:13:39.769681 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10909 20:13:40.324754 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10910 20:13:40.344911 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10911 20:13:40.367212 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10912 20:13:40.421529 Starting [0;1;39mPermit User Sessions[0m...
10913 20:13:40.449654 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10914 20:13:40.504950 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10915 20:13:40.531984 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10916 20:13:40.553789 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10917 20:13:40.573298 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10918 20:13:40.596926 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10919 20:13:40.641390 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10920 20:13:40.687977 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10921 20:13:40.780752
10922 20:13:40.780929
10923 20:13:40.783689 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10924 20:13:40.783800
10925 20:13:40.787349 debian-bullseye-arm64 login: root (automatic login)
10926 20:13:40.787451
10927 20:13:40.787536
10928 20:13:41.115359 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10929 20:13:41.115533
10930 20:13:41.121932 The programs included with the Debian GNU/Linux system are free software;
10931 20:13:41.129297 the exact distribution terms for each program are described in the
10932 20:13:41.131997 individual files in /usr/share/doc/*/copyright.
10933 20:13:41.132104
10934 20:13:41.138875 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10935 20:13:41.141746 permitted by applicable law.
10936 20:13:41.961808 Matched prompt #10: / #
10938 20:13:41.962156 Setting prompt string to ['/ #']
10939 20:13:41.962283 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10941 20:13:41.962540 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10942 20:13:41.962629 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10943 20:13:41.962701 Setting prompt string to ['/ #']
10944 20:13:41.962763 Forcing a shell prompt, looking for ['/ #']
10946 20:13:42.012989 / #
10947 20:13:42.013157 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10948 20:13:42.013289 Waiting using forced prompt support (timeout 00:02:30)
10949 20:13:42.017757
10950 20:13:42.018049 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10951 20:13:42.018145 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10953 20:13:42.118467 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy'
10954 20:13:42.124570 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928082/extract-nfsrootfs-5er4w0xy'
10956 20:13:42.225149 / # export NFS_SERVER_IP='192.168.201.1'
10957 20:13:42.231525 export NFS_SERVER_IP='192.168.201.1'
10958 20:13:42.231826 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10959 20:13:42.231935 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10960 20:13:42.232078 end: 2 depthcharge-action (duration 00:01:26) [common]
10961 20:13:42.232172 start: 3 lava-test-retry (timeout 00:07:54) [common]
10962 20:13:42.232264 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
10963 20:13:42.232338 Using namespace: common
10965 20:13:42.332726 / # #
10966 20:13:42.332910 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10967 20:13:42.339424 #
10968 20:13:42.339700 Using /lava-12928082
10970 20:13:42.440120 / # export SHELL=/bin/bash
10971 20:13:42.446404 export SHELL=/bin/bash
10973 20:13:42.547014 / # . /lava-12928082/environment
10974 20:13:42.552664 . /lava-12928082/environment
10976 20:13:42.657542 / # /lava-12928082/bin/lava-test-runner /lava-12928082/0
10977 20:13:42.657765 Test shell timeout: 10s (minimum of the action and connection timeout)
10978 20:13:42.662856 /lava-12928082/bin/lava-test-runner /lava-12928082/0
10979 20:13:42.904362 + export TESTRUN_ID=0_timesync-off
10980 20:13:42.907478 + TESTRUN_ID=0_timesync-off
10981 20:13:42.910906 + cd /lava-12928082/0/tests/0_timesync-off
10982 20:13:42.913921 ++ cat uuid
10983 20:13:42.917378 + UUID=12928082_1.6.2.3.1
10984 20:13:42.917491 + set +x
10985 20:13:42.920654 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12928082_1.6.2.3.1>
10986 20:13:42.920932 Received signal: <STARTRUN> 0_timesync-off 12928082_1.6.2.3.1
10987 20:13:42.921016 Starting test lava.0_timesync-off (12928082_1.6.2.3.1)
10988 20:13:42.921106 Skipping test definition patterns.
10989 20:13:42.924103 + systemctl stop systemd-timesyncd
10990 20:13:42.967920 + set +x
10991 20:13:42.971206 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12928082_1.6.2.3.1>
10992 20:13:42.971477 Received signal: <ENDRUN> 0_timesync-off 12928082_1.6.2.3.1
10993 20:13:42.971564 Ending use of test pattern.
10994 20:13:42.971629 Ending test lava.0_timesync-off (12928082_1.6.2.3.1), duration 0.05
10996 20:13:43.039508 + export TESTRUN_ID=1_kselftest-arm64
10997 20:13:43.039659 + TESTRUN_ID=1_kselftest-arm64
10998 20:13:43.046124 + cd /lava-12928082/0/tests/1_kselftest-arm64
10999 20:13:43.046211 ++ cat uuid
11000 20:13:43.049415 + UUID=12928082_1.6.2.3.5
11001 20:13:43.049492 + set +x
11002 20:13:43.052995 Received signal: <STARTRUN> 1_kselftest-arm64 12928082_1.6.2.3.5
11003 20:13:43.053073 Starting test lava.1_kselftest-arm64 (12928082_1.6.2.3.5)
11004 20:13:43.053157 Skipping test definition patterns.
11005 20:13:43.055951 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12928082_1.6.2.3.5>
11006 20:13:43.056028 + cd ./automated/linux/kselftest/
11007 20:13:43.085928 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11008 20:13:43.110874 INFO: install_deps skipped
11009 20:13:43.225142 --2024-03-03 20:13:05-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11010 20:13:43.238213 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11011 20:13:43.371209 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11012 20:13:43.504407 HTTP request sent, awaiting response... 200 OK
11013 20:13:43.507839 Length: 1746752 (1.7M) [application/octet-stream]
11014 20:13:43.510896 Saving to: 'kselftest.tar.xz'
11015 20:13:43.510981
11016 20:13:43.511047
11017 20:13:43.770500 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11018 20:13:44.036671 kselftest.tar.xz 2%[ ] 47.81K 181KB/s
11019 20:13:44.485165 kselftest.tar.xz 12%[=> ] 217.50K 410KB/s
11020 20:13:44.571788 kselftest.tar.xz 48%[========> ] 826.47K 844KB/s
11021 20:13:44.578248 kselftest.tar.xz 100%[===================>] 1.67M 1.56MB/s in 1.1s
11022 20:13:44.578343
11023 20:13:44.732394 2024-03-03 20:13:07 (1.56 MB/s) - 'kselftest.tar.xz' saved [1746752/1746752]
11024 20:13:44.732553
11025 20:13:49.820689 skiplist:
11026 20:13:49.823780 ========================================
11027 20:13:49.826923 ========================================
11028 20:13:49.867896 arm64:tags_test
11029 20:13:49.870953 arm64:run_tags_test.sh
11030 20:13:49.871047 arm64:fake_sigreturn_bad_magic
11031 20:13:49.874096 arm64:fake_sigreturn_bad_size
11032 20:13:49.877303 arm64:fake_sigreturn_bad_size_for_magic0
11033 20:13:49.881073 arm64:fake_sigreturn_duplicated_fpsimd
11034 20:13:49.883987 arm64:fake_sigreturn_misaligned_sp
11035 20:13:49.887279 arm64:fake_sigreturn_missing_fpsimd
11036 20:13:49.890756 arm64:fake_sigreturn_sme_change_vl
11037 20:13:49.893907 arm64:fake_sigreturn_sve_change_vl
11038 20:13:49.897281 arm64:mangle_pstate_invalid_compat_toggle
11039 20:13:49.900873 arm64:mangle_pstate_invalid_daif_bits
11040 20:13:49.904013 arm64:mangle_pstate_invalid_mode_el1h
11041 20:13:49.907273 arm64:mangle_pstate_invalid_mode_el1t
11042 20:13:49.910706 arm64:mangle_pstate_invalid_mode_el2h
11043 20:13:49.913837 arm64:mangle_pstate_invalid_mode_el2t
11044 20:13:49.917790 arm64:mangle_pstate_invalid_mode_el3h
11045 20:13:49.920350 arm64:mangle_pstate_invalid_mode_el3t
11046 20:13:49.924055 arm64:sme_trap_no_sm
11047 20:13:49.927158 arm64:sme_trap_non_streaming
11048 20:13:49.927250 arm64:sme_trap_za
11049 20:13:49.930402 arm64:sme_vl
11050 20:13:49.930485 arm64:ssve_regs
11051 20:13:49.933525 arm64:sve_regs
11052 20:13:49.933611 arm64:sve_vl
11053 20:13:49.933677 arm64:za_no_regs
11054 20:13:49.936969 arm64:za_regs
11055 20:13:49.937052 arm64:pac
11056 20:13:49.940379 arm64:fp-stress
11057 20:13:49.940463 arm64:sve-ptrace
11058 20:13:49.943639 arm64:sve-probe-vls
11059 20:13:49.943723 arm64:vec-syscfg
11060 20:13:49.943789 arm64:za-fork
11061 20:13:49.946699 arm64:za-ptrace
11062 20:13:49.950168 arm64:check_buffer_fill
11063 20:13:49.950252 arm64:check_child_memory
11064 20:13:49.953482 arm64:check_gcr_el1_cswitch
11065 20:13:49.957378 arm64:check_ksm_options
11066 20:13:49.957461 arm64:check_mmap_options
11067 20:13:49.959844 arm64:check_prctl
11068 20:13:49.963476 arm64:check_tags_inclusion
11069 20:13:49.963560 arm64:check_user_mem
11070 20:13:49.966541 arm64:btitest
11071 20:13:49.966624 arm64:nobtitest
11072 20:13:49.966690 arm64:hwcap
11073 20:13:49.969889 arm64:ptrace
11074 20:13:49.970009 arm64:syscall-abi
11075 20:13:49.973192 arm64:tpidr2
11076 20:13:49.976540 ============== Tests to run ===============
11077 20:13:49.976624 arm64:tags_test
11078 20:13:49.979725 arm64:run_tags_test.sh
11079 20:13:49.982890 arm64:fake_sigreturn_bad_magic
11080 20:13:49.982974 arm64:fake_sigreturn_bad_size
11081 20:13:49.989626 arm64:fake_sigreturn_bad_size_for_magic0
11082 20:13:49.993153 arm64:fake_sigreturn_duplicated_fpsimd
11083 20:13:49.996385 arm64:fake_sigreturn_misaligned_sp
11084 20:13:49.999833 arm64:fake_sigreturn_missing_fpsimd
11085 20:13:49.999916 arm64:fake_sigreturn_sme_change_vl
11086 20:13:50.003034 arm64:fake_sigreturn_sve_change_vl
11087 20:13:50.009737 arm64:mangle_pstate_invalid_compat_toggle
11088 20:13:50.012990 arm64:mangle_pstate_invalid_daif_bits
11089 20:13:50.016317 arm64:mangle_pstate_invalid_mode_el1h
11090 20:13:50.019897 arm64:mangle_pstate_invalid_mode_el1t
11091 20:13:50.023049 arm64:mangle_pstate_invalid_mode_el2h
11092 20:13:50.026244 arm64:mangle_pstate_invalid_mode_el2t
11093 20:13:50.030204 arm64:mangle_pstate_invalid_mode_el3h
11094 20:13:50.032798 arm64:mangle_pstate_invalid_mode_el3t
11095 20:13:50.032906 arm64:sme_trap_no_sm
11096 20:13:50.036399 arm64:sme_trap_non_streaming
11097 20:13:50.039432 arm64:sme_trap_za
11098 20:13:50.039508 arm64:sme_vl
11099 20:13:50.039573 arm64:ssve_regs
11100 20:13:50.043193 arm64:sve_regs
11101 20:13:50.043264 arm64:sve_vl
11102 20:13:50.046162 arm64:za_no_regs
11103 20:13:50.046237 arm64:za_regs
11104 20:13:50.046301 arm64:pac
11105 20:13:50.049365 arm64:fp-stress
11106 20:13:50.049437 arm64:sve-ptrace
11107 20:13:50.053074 arm64:sve-probe-vls
11108 20:13:50.053148 arm64:vec-syscfg
11109 20:13:50.056029 arm64:za-fork
11110 20:13:50.056101 arm64:za-ptrace
11111 20:13:50.059311 arm64:check_buffer_fill
11112 20:13:50.059384 arm64:check_child_memory
11113 20:13:50.062598 arm64:check_gcr_el1_cswitch
11114 20:13:50.066001 arm64:check_ksm_options
11115 20:13:50.069127 arm64:check_mmap_options
11116 20:13:50.069197 arm64:check_prctl
11117 20:13:50.072561 arm64:check_tags_inclusion
11118 20:13:50.072637 arm64:check_user_mem
11119 20:13:50.075916 arm64:btitest
11120 20:13:50.075987 arm64:nobtitest
11121 20:13:50.079396 arm64:hwcap
11122 20:13:50.079468 arm64:ptrace
11123 20:13:50.079529 arm64:syscall-abi
11124 20:13:50.082528 arm64:tpidr2
11125 20:13:50.085856 ===========End Tests to run ===============
11126 20:13:50.085952 shardfile-arm64 pass
11127 20:13:50.253458 <12>[ 34.958999] kselftest: Running tests in arm64
11128 20:13:50.259967 TAP version 13
11129 20:13:50.270899 1..48
11130 20:13:50.285035 # selftests: arm64: tags_test
11131 20:13:50.716878 ok 1 selftests: arm64: tags_test
11132 20:13:50.731559 # selftests: arm64: run_tags_test.sh
11133 20:13:50.772418 # --------------------
11134 20:13:50.775533 # running tags test
11135 20:13:50.775645 # --------------------
11136 20:13:50.779060 # [PASS]
11137 20:13:50.781863 ok 2 selftests: arm64: run_tags_test.sh
11138 20:13:50.793558 # selftests: arm64: fake_sigreturn_bad_magic
11139 20:13:50.912785 # Registered handlers for all signals.
11140 20:13:50.913008 # Detected MINSTKSIGSZ:4720
11141 20:13:50.913144 # Testcase initialized.
11142 20:13:50.913258 # uc context validated.
11143 20:13:50.913370 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11144 20:13:50.913482 # Handled SIG_COPYCTX
11145 20:13:50.913589 # Available space:3568
11146 20:13:50.913698 # Using badly built context - ERR: BAD MAGIC !
11147 20:13:50.913809 # SIG_OK -- SP:0xFFFFFA09D5F0 si_addr@:0xfffffa09d5f0 si_code:2 token@:0xfffffa09c390 offset:-4704
11148 20:13:50.913920 # ==>> completed. PASS(1)
11149 20:13:50.914052 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11150 20:13:50.914164 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA09C390
11151 20:13:50.914260 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11152 20:13:50.914350 # selftests: arm64: fake_sigreturn_bad_size
11153 20:13:50.920134 # Registered handlers for all signals.
11154 20:13:50.920245 # Detected MINSTKSIGSZ:4720
11155 20:13:50.923049 # Testcase initialized.
11156 20:13:50.926807 # uc context validated.
11157 20:13:50.929498 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11158 20:13:50.933017 # Handled SIG_COPYCTX
11159 20:13:50.933143 # Available space:3568
11160 20:13:50.936241 # uc context validated.
11161 20:13:50.942805 # Using badly built context - ERR: Bad size for esr_context
11162 20:13:50.949390 # SIG_OK -- SP:0xFFFFEB4E84E0 si_addr@:0xffffeb4e84e0 si_code:2 token@:0xffffeb4e7280 offset:-4704
11163 20:13:50.952729 # ==>> completed. PASS(1)
11164 20:13:50.959609 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11165 20:13:50.965934 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEB4E7280
11166 20:13:50.969222 ok 4 selftests: arm64: fake_sigreturn_bad_size
11167 20:13:50.976452 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11168 20:13:51.002139 # Registered handlers for all signals.
11169 20:13:51.002244 # Detected MINSTKSIGSZ:4720
11170 20:13:51.005332 # Testcase initialized.
11171 20:13:51.008604 # uc context validated.
11172 20:13:51.012123 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11173 20:13:51.015251 # Handled SIG_COPYCTX
11174 20:13:51.015357 # Available space:3568
11175 20:13:51.021804 # Using badly built context - ERR: Bad size for terminator
11176 20:13:51.032170 # SIG_OK -- SP:0xFFFFD7F26C00 si_addr@:0xffffd7f26c00 si_code:2 token@:0xffffd7f259a0 offset:-4704
11177 20:13:51.032316 # ==>> completed. PASS(1)
11178 20:13:51.041824 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11179 20:13:51.048444 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD7F259A0
11180 20:13:51.051728 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11181 20:13:51.058694 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11182 20:13:51.081119 # Registered handlers for all signals.
11183 20:13:51.081260 # Detected MINSTKSIGSZ:4720
11184 20:13:51.084282 # Testcase initialized.
11185 20:13:51.087465 # uc context validated.
11186 20:13:51.091219 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11187 20:13:51.094194 # Handled SIG_COPYCTX
11188 20:13:51.094285 # Available space:3568
11189 20:13:51.101096 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11190 20:13:51.111007 # SIG_OK -- SP:0xFFFFC65ED190 si_addr@:0xffffc65ed190 si_code:2 token@:0xffffc65ebf30 offset:-4704
11191 20:13:51.111107 # ==>> completed. PASS(1)
11192 20:13:51.120738 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11193 20:13:51.127399 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC65EBF30
11194 20:13:51.130738 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11195 20:13:51.133848 # selftests: arm64: fake_sigreturn_misaligned_sp
11196 20:13:51.150114 # Registered handlers for all signals.
11197 20:13:51.150270 # Detected MINSTKSIGSZ:4720
11198 20:13:51.153189 # Testcase initialized.
11199 20:13:51.156412 # uc context validated.
11200 20:13:51.160203 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11201 20:13:51.163547 # Handled SIG_COPYCTX
11202 20:13:51.169570 # SIG_OK -- SP:0xFFFFF9A5A273 si_addr@:0xfffff9a5a273 si_code:2 token@:0xfffff9a5a273 offset:0
11203 20:13:51.172888 # ==>> completed. PASS(1)
11204 20:13:51.179833 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11205 20:13:51.186297 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF9A5A273
11206 20:13:51.193103 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11207 20:13:51.196476 # selftests: arm64: fake_sigreturn_missing_fpsimd
11208 20:13:51.219876 # Registered handlers for all signals.
11209 20:13:51.220020 # Detected MINSTKSIGSZ:4720
11210 20:13:51.223143 # Testcase initialized.
11211 20:13:51.226585 # uc context validated.
11212 20:13:51.229806 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11213 20:13:51.233028 # Handled SIG_COPYCTX
11214 20:13:51.236306 # Mangling template header. Spare space:4096
11215 20:13:51.239968 # Using badly built context - ERR: Missing FPSIMD
11216 20:13:51.250160 # SIG_OK -- SP:0xFFFFE4742340 si_addr@:0xffffe4742340 si_code:2 token@:0xffffe47410e0 offset:-4704
11217 20:13:51.253029 # ==>> completed. PASS(1)
11218 20:13:51.259387 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11219 20:13:51.266271 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE47410E0
11220 20:13:51.269559 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11221 20:13:51.275906 # selftests: arm64: fake_sigreturn_sme_change_vl
11222 20:13:51.296754 # Registered handlers for all signals.
11223 20:13:51.296862 # Detected MINSTKSIGSZ:4720
11224 20:13:51.300137 # ==>> completed. SKIP.
11225 20:13:51.306903 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11226 20:13:51.310098 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11227 20:13:51.316616 # selftests: arm64: fake_sigreturn_sve_change_vl
11228 20:13:51.371049 # Registered handlers for all signals.
11229 20:13:51.371168 # Detected MINSTKSIGSZ:4720
11230 20:13:51.374893 # ==>> completed. SKIP.
11231 20:13:51.377795 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11232 20:13:51.384304 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11233 20:13:51.391707 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11234 20:13:51.450740 # Registered handlers for all signals.
11235 20:13:51.450888 # Detected MINSTKSIGSZ:4720
11236 20:13:51.453868 # Testcase initialized.
11237 20:13:51.457160 # uc context validated.
11238 20:13:51.457236 # Handled SIG_TRIG
11239 20:13:51.466854 # SIG_OK -- SP:0xFFFFE01A9750 si_addr@:0xffffe01a9750 si_code:2 token@:(nil) offset:-281474441582416
11240 20:13:51.470322 # ==>> completed. PASS(1)
11241 20:13:51.477283 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11242 20:13:51.483850 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11243 20:13:51.486785 # selftests: arm64: mangle_pstate_invalid_daif_bits
11244 20:13:51.531864 # Registered handlers for all signals.
11245 20:13:51.531994 # Detected MINSTKSIGSZ:4720
11246 20:13:51.534932 # Testcase initialized.
11247 20:13:51.538372 # uc context validated.
11248 20:13:51.538453 # Handled SIG_TRIG
11249 20:13:51.548249 # SIG_OK -- SP:0xFFFFF084AA80 si_addr@:0xfffff084aa80 si_code:2 token@:(nil) offset:-281474716969600
11250 20:13:51.551400 # ==>> completed. PASS(1)
11251 20:13:51.558054 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11252 20:13:51.561283 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11253 20:13:51.567883 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11254 20:13:51.602407 # Registered handlers for all signals.
11255 20:13:51.602528 # Detected MINSTKSIGSZ:4720
11256 20:13:51.605467 # Testcase initialized.
11257 20:13:51.608871 # uc context validated.
11258 20:13:51.608996 # Handled SIG_TRIG
11259 20:13:51.618623 # SIG_OK -- SP:0xFFFFD2196E20 si_addr@:0xffffd2196e20 si_code:2 token@:(nil) offset:-281474206625312
11260 20:13:51.622298 # ==>> completed. PASS(1)
11261 20:13:51.628818 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11262 20:13:51.632076 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11263 20:13:51.638565 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11264 20:13:51.680441 # Registered handlers for all signals.
11265 20:13:51.680550 # Detected MINSTKSIGSZ:4720
11266 20:13:51.684243 # Testcase initialized.
11267 20:13:51.687239 # uc context validated.
11268 20:13:51.687324 # Handled SIG_TRIG
11269 20:13:51.696886 # SIG_OK -- SP:0xFFFFF6640100 si_addr@:0xfffff6640100 si_code:2 token@:(nil) offset:-281474815492352
11270 20:13:51.700417 # ==>> completed. PASS(1)
11271 20:13:51.706737 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11272 20:13:51.710146 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11273 20:13:51.716871 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11274 20:13:51.764191 # Registered handlers for all signals.
11275 20:13:51.764353 # Detected MINSTKSIGSZ:4720
11276 20:13:51.767496 # Testcase initialized.
11277 20:13:51.770955 # uc context validated.
11278 20:13:51.771040 # Handled SIG_TRIG
11279 20:13:51.780708 # SIG_OK -- SP:0xFFFFF28A50E0 si_addr@:0xfffff28a50e0 si_code:2 token@:(nil) offset:-281474750894304
11280 20:13:51.784119 # ==>> completed. PASS(1)
11281 20:13:51.791023 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11282 20:13:51.793876 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11283 20:13:51.800717 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11284 20:13:51.832326 # Registered handlers for all signals.
11285 20:13:51.832430 # Detected MINSTKSIGSZ:4720
11286 20:13:51.835977 # Testcase initialized.
11287 20:13:51.839268 # uc context validated.
11288 20:13:51.839355 # Handled SIG_TRIG
11289 20:13:51.848923 # SIG_OK -- SP:0xFFFFD420F0D0 si_addr@:0xffffd420f0d0 si_code:2 token@:(nil) offset:-281474240671952
11290 20:13:51.852207 # ==>> completed. PASS(1)
11291 20:13:51.858963 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11292 20:13:51.862173 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11293 20:13:51.869174 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11294 20:13:51.910002 # Registered handlers for all signals.
11295 20:13:51.910118 # Detected MINSTKSIGSZ:4720
11296 20:13:51.913416 # Testcase initialized.
11297 20:13:51.916721 # uc context validated.
11298 20:13:51.916808 # Handled SIG_TRIG
11299 20:13:51.926419 # SIG_OK -- SP:0xFFFFE4F1B490 si_addr@:0xffffe4f1b490 si_code:2 token@:(nil) offset:-281474522789008
11300 20:13:51.929831 # ==>> completed. PASS(1)
11301 20:13:51.936467 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11302 20:13:51.939659 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11303 20:13:51.946334 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11304 20:13:51.986932 # Registered handlers for all signals.
11305 20:13:51.987114 # Detected MINSTKSIGSZ:4720
11306 20:13:51.990130 # Testcase initialized.
11307 20:13:51.993632 # uc context validated.
11308 20:13:51.993775 # Handled SIG_TRIG
11309 20:13:52.003522 # SIG_OK -- SP:0xFFFFCFDD0EB0 si_addr@:0xffffcfdd0eb0 si_code:2 token@:(nil) offset:-281474169114288
11310 20:13:52.006715 # ==>> completed. PASS(1)
11311 20:13:52.013800 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11312 20:13:52.016936 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11313 20:13:52.020480 # selftests: arm64: sme_trap_no_sm
11314 20:13:52.059591 # Registered handlers for all signals.
11315 20:13:52.059792 # Detected MINSTKSIGSZ:4720
11316 20:13:52.063075 # ==>> completed. SKIP.
11317 20:13:52.072680 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11318 20:13:52.076310 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11319 20:13:52.079141 # selftests: arm64: sme_trap_non_streaming
11320 20:13:52.139533 # Registered handlers for all signals.
11321 20:13:52.139730 # Detected MINSTKSIGSZ:4720
11322 20:13:52.142927 # ==>> completed. SKIP.
11323 20:13:52.152901 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11324 20:13:52.159303 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11325 20:13:52.162729 # selftests: arm64: sme_trap_za
11326 20:13:52.216112 # Registered handlers for all signals.
11327 20:13:52.216264 # Detected MINSTKSIGSZ:4720
11328 20:13:52.219390 # Testcase initialized.
11329 20:13:52.229357 # SIG_OK -- SP:0xFFFFFDD4D2F0 si_addr@:0xaaaac04a2510 si_code:1 token@:(nil) offset:-187650347246864
11330 20:13:52.229458 # ==>> completed. PASS(1)
11331 20:13:52.239228 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11332 20:13:52.239345 ok 21 selftests: arm64: sme_trap_za
11333 20:13:52.242595 # selftests: arm64: sme_vl
11334 20:13:52.294148 # Registered handlers for all signals.
11335 20:13:52.294300 # Detected MINSTKSIGSZ:4720
11336 20:13:52.297266 # ==>> completed. SKIP.
11337 20:13:52.304095 # # SME VL :: Check that we get the right SME VL reported
11338 20:13:52.307172 ok 22 selftests: arm64: sme_vl # SKIP
11339 20:13:52.310432 # selftests: arm64: ssve_regs
11340 20:13:52.358804 # Registered handlers for all signals.
11341 20:13:52.358952 # Detected MINSTKSIGSZ:4720
11342 20:13:52.362713 # ==>> completed. SKIP.
11343 20:13:52.368876 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11344 20:13:52.372454 ok 23 selftests: arm64: ssve_regs # SKIP
11345 20:13:52.375249 # selftests: arm64: sve_regs
11346 20:13:52.425083 # Registered handlers for all signals.
11347 20:13:52.425194 # Detected MINSTKSIGSZ:4720
11348 20:13:52.428377 # ==>> completed. SKIP.
11349 20:13:52.435058 # # SVE registers :: Check that we get the right SVE registers reported
11350 20:13:52.438589 ok 24 selftests: arm64: sve_regs # SKIP
11351 20:13:52.441558 # selftests: arm64: sve_vl
11352 20:13:52.490218 # Registered handlers for all signals.
11353 20:13:52.490352 # Detected MINSTKSIGSZ:4720
11354 20:13:52.493555 # ==>> completed. SKIP.
11355 20:13:52.496665 # # SVE VL :: Check that we get the right SVE VL reported
11356 20:13:52.503481 ok 25 selftests: arm64: sve_vl # SKIP
11357 20:13:52.506806 # selftests: arm64: za_no_regs
11358 20:13:52.565691 # Registered handlers for all signals.
11359 20:13:52.565799 # Detected MINSTKSIGSZ:4720
11360 20:13:52.568846 # ==>> completed. SKIP.
11361 20:13:52.575576 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11362 20:13:52.578780 ok 26 selftests: arm64: za_no_regs # SKIP
11363 20:13:52.581886 # selftests: arm64: za_regs
11364 20:13:52.630740 # Registered handlers for all signals.
11365 20:13:52.630846 # Detected MINSTKSIGSZ:4720
11366 20:13:52.634563 # ==>> completed. SKIP.
11367 20:13:52.640781 # # ZA register :: Check that we get the right ZA registers reported
11368 20:13:52.644745 ok 27 selftests: arm64: za_regs # SKIP
11369 20:13:52.647333 # selftests: arm64: pac
11370 20:13:52.692220 # TAP version 13
11371 20:13:52.692317 # 1..7
11372 20:13:52.695541 # # Starting 7 tests from 1 test cases.
11373 20:13:52.698860 # # RUN global.corrupt_pac ...
11374 20:13:52.702080 # # SKIP PAUTH not enabled
11375 20:13:52.705332 # # OK global.corrupt_pac
11376 20:13:52.708840 # ok 1 # SKIP PAUTH not enabled
11377 20:13:52.715632 # # RUN global.pac_instructions_not_nop ...
11378 20:13:52.718738 # # SKIP PAUTH not enabled
11379 20:13:52.722330 # # OK global.pac_instructions_not_nop
11380 20:13:52.725314 # ok 2 # SKIP PAUTH not enabled
11381 20:13:52.731788 # # RUN global.pac_instructions_not_nop_generic ...
11382 20:13:52.735273 # # SKIP Generic PAUTH not enabled
11383 20:13:52.738521 # # OK global.pac_instructions_not_nop_generic
11384 20:13:52.745308 # ok 3 # SKIP Generic PAUTH not enabled
11385 20:13:52.748269 # # RUN global.single_thread_different_keys ...
11386 20:13:52.751993 # # SKIP PAUTH not enabled
11387 20:13:52.758122 # # OK global.single_thread_different_keys
11388 20:13:52.758208 # ok 4 # SKIP PAUTH not enabled
11389 20:13:52.765218 # # RUN global.exec_changed_keys ...
11390 20:13:52.768140 # # SKIP PAUTH not enabled
11391 20:13:52.771732 # # OK global.exec_changed_keys
11392 20:13:52.775550 # ok 5 # SKIP PAUTH not enabled
11393 20:13:52.778409 # # RUN global.context_switch_keep_keys ...
11394 20:13:52.781936 # # SKIP PAUTH not enabled
11395 20:13:52.787994 # # OK global.context_switch_keep_keys
11396 20:13:52.788079 # ok 6 # SKIP PAUTH not enabled
11397 20:13:52.794736 # # RUN global.context_switch_keep_keys_generic ...
11398 20:13:52.797898 # # SKIP Generic PAUTH not enabled
11399 20:13:52.804752 # # OK global.context_switch_keep_keys_generic
11400 20:13:52.807875 # ok 7 # SKIP Generic PAUTH not enabled
11401 20:13:52.811115 # # PASSED: 7 / 7 tests passed.
11402 20:13:52.814834 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11403 20:13:52.818168 ok 28 selftests: arm64: pac
11404 20:13:52.821153 # selftests: arm64: fp-stress
11405 20:13:59.325291 <6>[ 44.033568] vpu: disabling
11406 20:13:59.328723 <6>[ 44.033654] vproc2: disabling
11407 20:13:59.331702 <6>[ 44.033691] vproc1: disabling
11408 20:13:59.335014 <6>[ 44.033730] vaud18: disabling
11409 20:13:59.338254 <6>[ 44.033910] vsram_others: disabling
11410 20:13:59.341562 <6>[ 44.034038] va09: disabling
11411 20:13:59.345058 <6>[ 44.034093] vsram_md: disabling
11412 20:13:59.348714 <6>[ 44.034190] Vgpu: disabling
11413 20:14:02.760331 # TAP version 13
11414 20:14:02.760502 # 1..16
11415 20:14:02.763074 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11416 20:14:02.766593 # # Will run for 10s
11417 20:14:02.766685 # # Started FPSIMD-0-0
11418 20:14:02.769916 # # Started FPSIMD-0-1
11419 20:14:02.773824 # # Started FPSIMD-1-0
11420 20:14:02.773919 # # Started FPSIMD-1-1
11421 20:14:02.776434 # # Started FPSIMD-2-0
11422 20:14:02.776524 # # Started FPSIMD-2-1
11423 20:14:02.780466 # # Started FPSIMD-3-0
11424 20:14:02.783216 # # Started FPSIMD-3-1
11425 20:14:02.783306 # # Started FPSIMD-4-0
11426 20:14:02.786499 # # Started FPSIMD-4-1
11427 20:14:02.789520 # # Started FPSIMD-5-0
11428 20:14:02.789642 # # Started FPSIMD-5-1
11429 20:14:02.793007 # # Started FPSIMD-6-0
11430 20:14:02.793140 # # Started FPSIMD-6-1
11431 20:14:02.796543 # # Started FPSIMD-7-0
11432 20:14:02.799492 # # Started FPSIMD-7-1
11433 20:14:02.803466 # # FPSIMD-0-0: Vector length: 128 bits
11434 20:14:02.806240 # # FPSIMD-0-0: PID: 1172
11435 20:14:02.809418 # # FPSIMD-0-1: Vector length: 128 bits
11436 20:14:02.809511 # # FPSIMD-0-1: PID: 1173
11437 20:14:02.812723 # # FPSIMD-1-1: Vector length: 128 bits
11438 20:14:02.816428 # # FPSIMD-1-1: PID: 1175
11439 20:14:02.819660 # # FPSIMD-1-0: Vector length: 128 bits
11440 20:14:02.823137 # # FPSIMD-1-0: PID: 1174
11441 20:14:02.826137 # # FPSIMD-2-1: Vector length: 128 bits
11442 20:14:02.829687 # # FPSIMD-2-1: PID: 1177
11443 20:14:02.832781 # # FPSIMD-2-0: Vector length: 128 bits
11444 20:14:02.832870 # # FPSIMD-2-0: PID: 1176
11445 20:14:02.839325 # # FPSIMD-6-0: Vector length: 128 bits
11446 20:14:02.839417 # # FPSIMD-6-0: PID: 1184
11447 20:14:02.842981 # # FPSIMD-5-1: Vector length: 128 bits
11448 20:14:02.845912 # # FPSIMD-5-1: PID: 1183
11449 20:14:02.849192 # # FPSIMD-3-0: Vector length: 128 bits
11450 20:14:02.852579 # # FPSIMD-3-0: PID: 1178
11451 20:14:02.855927 # # FPSIMD-7-1: Vector length: 128 bits
11452 20:14:02.859125 # # FPSIMD-7-1: PID: 1187
11453 20:14:02.862433 # # FPSIMD-3-1: Vector length: 128 bits
11454 20:14:02.862524 # # FPSIMD-3-1: PID: 1179
11455 20:14:02.865873 # # FPSIMD-4-1: Vector length: 128 bits
11456 20:14:02.869629 # # FPSIMD-4-1: PID: 1181
11457 20:14:02.872611 # # FPSIMD-7-0: Vector length: 128 bits
11458 20:14:02.875809 # # FPSIMD-7-0: PID: 1186
11459 20:14:02.879123 # # FPSIMD-5-0: Vector length: 128 bits
11460 20:14:02.882557 # # FPSIMD-5-0: PID: 1182
11461 20:14:02.885790 # # FPSIMD-4-0: Vector length: 128 bits
11462 20:14:02.885884 # # FPSIMD-4-0: PID: 1180
11463 20:14:02.892326 # # FPSIMD-6-1: Vector length: 128 bits
11464 20:14:02.892433 # # FPSIMD-6-1: PID: 1185
11465 20:14:02.895679 # # Finishing up...
11466 20:14:02.902396 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1024467, signals=10
11467 20:14:02.909272 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1334627, signals=10
11468 20:14:02.915536 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1412521, signals=10
11469 20:14:02.925574 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1450115, signals=10
11470 20:14:02.931960 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=994494, signals=10
11471 20:14:02.939062 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=957167, signals=10
11472 20:14:02.945365 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1541845, signals=10
11473 20:14:02.945477 # ok 1 FPSIMD-0-0
11474 20:14:02.948716 # ok 2 FPSIMD-0-1
11475 20:14:02.948808 # ok 3 FPSIMD-1-0
11476 20:14:02.951881 # ok 4 FPSIMD-1-1
11477 20:14:02.951973 # ok 5 FPSIMD-2-0
11478 20:14:02.955414 # ok 6 FPSIMD-2-1
11479 20:14:02.955507 # ok 7 FPSIMD-3-0
11480 20:14:02.959138 # ok 8 FPSIMD-3-1
11481 20:14:02.959257 # ok 9 FPSIMD-4-0
11482 20:14:02.962494 # ok 10 FPSIMD-4-1
11483 20:14:02.962583 # ok 11 FPSIMD-5-0
11484 20:14:02.965330 # ok 12 FPSIMD-5-1
11485 20:14:02.969134 # ok 13 FPSIMD-6-0
11486 20:14:02.969225 # ok 14 FPSIMD-6-1
11487 20:14:02.972020 # ok 15 FPSIMD-7-0
11488 20:14:02.972105 # ok 16 FPSIMD-7-1
11489 20:14:02.979167 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1252611, signals=9
11490 20:14:02.985267 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1336890, signals=9
11491 20:14:02.995432 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1253748, signals=10
11492 20:14:03.001733 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=951643, signals=10
11493 20:14:03.008004 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1332526, signals=10
11494 20:14:03.014769 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1434137, signals=10
11495 20:14:03.021491 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1504945, signals=10
11496 20:14:03.031121 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1291672, signals=10
11497 20:14:03.037713 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1176067, signals=9
11498 20:14:03.041240 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11499 20:14:03.044532 ok 29 selftests: arm64: fp-stress
11500 20:14:03.047645 # selftests: arm64: sve-ptrace
11501 20:14:03.047745 # TAP version 13
11502 20:14:03.051126 # 1..4104
11503 20:14:03.054321 # ok 2 # SKIP SVE not available
11504 20:14:03.057788 # # Planned tests != run tests (4104 != 1)
11505 20:14:03.061072 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11506 20:14:03.064237 ok 30 selftests: arm64: sve-ptrace # SKIP
11507 20:14:03.067781 # selftests: arm64: sve-probe-vls
11508 20:14:03.070858 # TAP version 13
11509 20:14:03.070953 # 1..2
11510 20:14:03.074205 # ok 2 # SKIP SVE not available
11511 20:14:03.077498 # # Planned tests != run tests (2 != 1)
11512 20:14:03.081168 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11513 20:14:03.087469 ok 31 selftests: arm64: sve-probe-vls # SKIP
11514 20:14:03.087586 # selftests: arm64: vec-syscfg
11515 20:14:03.091005 # TAP version 13
11516 20:14:03.091095 # 1..20
11517 20:14:03.094066 # ok 1 # SKIP SVE not supported
11518 20:14:03.097408 # ok 2 # SKIP SVE not supported
11519 20:14:03.101002 # ok 3 # SKIP SVE not supported
11520 20:14:03.103979 # ok 4 # SKIP SVE not supported
11521 20:14:03.107600 # ok 5 # SKIP SVE not supported
11522 20:14:03.107692 # ok 6 # SKIP SVE not supported
11523 20:14:03.111100 # ok 7 # SKIP SVE not supported
11524 20:14:03.114579 # ok 8 # SKIP SVE not supported
11525 20:14:03.117844 # ok 9 # SKIP SVE not supported
11526 20:14:03.120982 # ok 10 # SKIP SVE not supported
11527 20:14:03.124396 # ok 11 # SKIP SME not supported
11528 20:14:03.127654 # ok 12 # SKIP SME not supported
11529 20:14:03.127745 # ok 13 # SKIP SME not supported
11530 20:14:03.131150 # ok 14 # SKIP SME not supported
11531 20:14:03.134038 # ok 15 # SKIP SME not supported
11532 20:14:03.137675 # ok 16 # SKIP SME not supported
11533 20:14:03.140964 # ok 17 # SKIP SME not supported
11534 20:14:03.144061 # ok 18 # SKIP SME not supported
11535 20:14:03.147455 # ok 19 # SKIP SME not supported
11536 20:14:03.150901 # ok 20 # SKIP SME not supported
11537 20:14:03.154343 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11538 20:14:03.157121 ok 32 selftests: arm64: vec-syscfg
11539 20:14:03.160470 # selftests: arm64: za-fork
11540 20:14:03.160564 # TAP version 13
11541 20:14:03.163784 # 1..1
11542 20:14:03.163873 # # PID: 1262
11543 20:14:03.167430 # # SME support not present
11544 20:14:03.167525 # ok 0 skipped
11545 20:14:03.174476 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11546 20:14:03.177381 ok 33 selftests: arm64: za-fork
11547 20:14:03.177471 # selftests: arm64: za-ptrace
11548 20:14:03.180354 # TAP version 13
11549 20:14:03.180439 # 1..1
11550 20:14:03.183690 # ok 2 # SKIP SME not available
11551 20:14:03.187002 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11552 20:14:03.193655 ok 34 selftests: arm64: za-ptrace # SKIP
11553 20:14:03.197035 # selftests: arm64: check_buffer_fill
11554 20:14:03.209151 # # SKIP: MTE features unavailable
11555 20:14:03.216326 ok 35 selftests: arm64: check_buffer_fill # SKIP
11556 20:14:03.230278 # selftests: arm64: check_child_memory
11557 20:14:03.262288 # # SKIP: MTE features unavailable
11558 20:14:03.268945 ok 36 selftests: arm64: check_child_memory # SKIP
11559 20:14:03.285042 # selftests: arm64: check_gcr_el1_cswitch
11560 20:14:03.329518 # # SKIP: MTE features unavailable
11561 20:14:03.335700 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11562 20:14:03.349457 # selftests: arm64: check_ksm_options
11563 20:14:03.388725 # # SKIP: MTE features unavailable
11564 20:14:03.395582 ok 38 selftests: arm64: check_ksm_options # SKIP
11565 20:14:03.409826 # selftests: arm64: check_mmap_options
11566 20:14:03.466778 # # SKIP: MTE features unavailable
11567 20:14:03.474677 ok 39 selftests: arm64: check_mmap_options # SKIP
11568 20:14:03.486764 # selftests: arm64: check_prctl
11569 20:14:03.541743 # TAP version 13
11570 20:14:03.541911 # 1..5
11571 20:14:03.544843 # ok 1 check_basic_read
11572 20:14:03.544951 # ok 2 NONE
11573 20:14:03.548221 # ok 3 # SKIP SYNC
11574 20:14:03.548321 # ok 4 # SKIP ASYNC
11575 20:14:03.551962 # ok 5 # SKIP SYNC+ASYNC
11576 20:14:03.555101 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11577 20:14:03.558094 ok 40 selftests: arm64: check_prctl
11578 20:14:03.564967 # selftests: arm64: check_tags_inclusion
11579 20:14:03.594263 # # SKIP: MTE features unavailable
11580 20:14:03.601159 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11581 20:14:03.614532 # selftests: arm64: check_user_mem
11582 20:14:03.663130 # # SKIP: MTE features unavailable
11583 20:14:03.670647 ok 42 selftests: arm64: check_user_mem # SKIP
11584 20:14:03.681539 # selftests: arm64: btitest
11585 20:14:03.737924 # TAP version 13
11586 20:14:03.738095 # 1..18
11587 20:14:03.741040 # # HWCAP_PACA not present
11588 20:14:03.744637 # # HWCAP2_BTI not present
11589 20:14:03.744744 # # Test binary built for BTI
11590 20:14:03.750844 # ok 1 nohint_func/call_using_br_x0 # SKIP
11591 20:14:03.753907 # ok 1 nohint_func/call_using_br_x16 # SKIP
11592 20:14:03.758202 # ok 1 nohint_func/call_using_blr # SKIP
11593 20:14:03.760650 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11594 20:14:03.764101 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11595 20:14:03.770781 # ok 1 bti_none_func/call_using_blr # SKIP
11596 20:14:03.774408 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11597 20:14:03.777268 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11598 20:14:03.780519 # ok 1 bti_c_func/call_using_blr # SKIP
11599 20:14:03.784052 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11600 20:14:03.787612 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11601 20:14:03.790512 # ok 1 bti_j_func/call_using_blr # SKIP
11602 20:14:03.793885 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11603 20:14:03.800761 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11604 20:14:03.803898 # ok 1 bti_jc_func/call_using_blr # SKIP
11605 20:14:03.807045 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11606 20:14:03.810678 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11607 20:14:03.814309 # ok 1 paciasp_func/call_using_blr # SKIP
11608 20:14:03.820162 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11609 20:14:03.823419 # # WARNING - EXPECTED TEST COUNT WRONG
11610 20:14:03.826893 ok 43 selftests: arm64: btitest
11611 20:14:03.827006 # selftests: arm64: nobtitest
11612 20:14:03.830141 # TAP version 13
11613 20:14:03.830242 # 1..18
11614 20:14:03.833804 # # HWCAP_PACA not present
11615 20:14:03.837018 # # HWCAP2_BTI not present
11616 20:14:03.840497 # # Test binary not built for BTI
11617 20:14:03.843569 # ok 1 nohint_func/call_using_br_x0 # SKIP
11618 20:14:03.846710 # ok 1 nohint_func/call_using_br_x16 # SKIP
11619 20:14:03.850019 # ok 1 nohint_func/call_using_blr # SKIP
11620 20:14:03.853261 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11621 20:14:03.856892 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11622 20:14:03.863612 # ok 1 bti_none_func/call_using_blr # SKIP
11623 20:14:03.866767 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11624 20:14:03.869881 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11625 20:14:03.873350 # ok 1 bti_c_func/call_using_blr # SKIP
11626 20:14:03.876795 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11627 20:14:03.879836 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11628 20:14:03.883344 # ok 1 bti_j_func/call_using_blr # SKIP
11629 20:14:03.886777 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11630 20:14:03.893320 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11631 20:14:03.896976 # ok 1 bti_jc_func/call_using_blr # SKIP
11632 20:14:03.899820 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11633 20:14:03.903071 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11634 20:14:03.906483 # ok 1 paciasp_func/call_using_blr # SKIP
11635 20:14:03.913305 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11636 20:14:03.916292 # # WARNING - EXPECTED TEST COUNT WRONG
11637 20:14:03.919514 ok 44 selftests: arm64: nobtitest
11638 20:14:03.919679 # selftests: arm64: hwcap
11639 20:14:03.923143 # TAP version 13
11640 20:14:03.923266 # 1..28
11641 20:14:03.926414 # ok 1 cpuinfo_match_RNG
11642 20:14:03.929635 # # SIGILL reported for RNG
11643 20:14:03.929782 # ok 2 # SKIP sigill_RNG
11644 20:14:03.933193 # ok 3 cpuinfo_match_SME
11645 20:14:03.933289 # ok 4 sigill_SME
11646 20:14:03.936239 # ok 5 cpuinfo_match_SVE
11647 20:14:03.939875 # ok 6 sigill_SVE
11648 20:14:03.939980 # ok 7 cpuinfo_match_SVE 2
11649 20:14:03.942938 # # SIGILL reported for SVE 2
11650 20:14:03.946436 # ok 8 # SKIP sigill_SVE 2
11651 20:14:03.949754 # ok 9 cpuinfo_match_SVE AES
11652 20:14:03.952955 # # SIGILL reported for SVE AES
11653 20:14:03.953065 # ok 10 # SKIP sigill_SVE AES
11654 20:14:03.956213 # ok 11 cpuinfo_match_SVE2 PMULL
11655 20:14:03.959730 # # SIGILL reported for SVE2 PMULL
11656 20:14:03.962889 # ok 12 # SKIP sigill_SVE2 PMULL
11657 20:14:03.966083 # ok 13 cpuinfo_match_SVE2 BITPERM
11658 20:14:03.969638 # # SIGILL reported for SVE2 BITPERM
11659 20:14:03.972639 # ok 14 # SKIP sigill_SVE2 BITPERM
11660 20:14:03.976014 # ok 15 cpuinfo_match_SVE2 SHA3
11661 20:14:03.979581 # # SIGILL reported for SVE2 SHA3
11662 20:14:03.982951 # ok 16 # SKIP sigill_SVE2 SHA3
11663 20:14:03.983060 # ok 17 cpuinfo_match_SVE2 SM4
11664 20:14:03.986135 # # SIGILL reported for SVE2 SM4
11665 20:14:03.989483 # ok 18 # SKIP sigill_SVE2 SM4
11666 20:14:03.992485 # ok 19 cpuinfo_match_SVE2 I8MM
11667 20:14:03.996154 # # SIGILL reported for SVE2 I8MM
11668 20:14:03.999350 # ok 20 # SKIP sigill_SVE2 I8MM
11669 20:14:04.002479 # ok 21 cpuinfo_match_SVE2 F32MM
11670 20:14:04.005788 # # SIGILL reported for SVE2 F32MM
11671 20:14:04.009564 # ok 22 # SKIP sigill_SVE2 F32MM
11672 20:14:04.009697 # ok 23 cpuinfo_match_SVE2 F64MM
11673 20:14:04.012644 # # SIGILL reported for SVE2 F64MM
11674 20:14:04.015813 # ok 24 # SKIP sigill_SVE2 F64MM
11675 20:14:04.019010 # ok 25 cpuinfo_match_SVE2 BF16
11676 20:14:04.022308 # # SIGILL reported for SVE2 BF16
11677 20:14:04.025854 # ok 26 # SKIP sigill_SVE2 BF16
11678 20:14:04.029536 # ok 27 cpuinfo_match_SVE2 EBF16
11679 20:14:04.032594 # ok 28 # SKIP sigill_SVE2 EBF16
11680 20:14:04.035982 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11681 20:14:04.039206 ok 45 selftests: arm64: hwcap
11682 20:14:04.042416 # selftests: arm64: ptrace
11683 20:14:04.042531 # TAP version 13
11684 20:14:04.045642 # 1..7
11685 20:14:04.045741 # # Parent is 1504, child is 1505
11686 20:14:04.048782 # ok 1 read_tpidr_one
11687 20:14:04.052131 # ok 2 write_tpidr_one
11688 20:14:04.052241 # ok 3 verify_tpidr_one
11689 20:14:04.055857 # ok 4 count_tpidrs
11690 20:14:04.055962 # ok 5 tpidr2_write
11691 20:14:04.058698 # ok 6 tpidr2_read
11692 20:14:04.061970 # ok 7 write_tpidr_only
11693 20:14:04.065483 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11694 20:14:04.068780 ok 46 selftests: arm64: ptrace
11695 20:14:04.072214 # selftests: arm64: syscall-abi
11696 20:14:04.072337 # TAP version 13
11697 20:14:04.075456 # 1..2
11698 20:14:04.075557 # ok 1 getpid() FPSIMD
11699 20:14:04.078717 # ok 2 sched_yield() FPSIMD
11700 20:14:04.081803 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11701 20:14:04.085372 ok 47 selftests: arm64: syscall-abi
11702 20:14:04.088657 # selftests: arm64: tpidr2
11703 20:14:04.103427 # TAP version 13
11704 20:14:04.103598 # 1..5
11705 20:14:04.107322 # # PID: 1541
11706 20:14:04.107441 # # SME support not present
11707 20:14:04.109843 # ok 0 skipped, TPIDR2 not supported
11708 20:14:04.113113 # ok 1 skipped, TPIDR2 not supported
11709 20:14:04.116498 # ok 2 skipped, TPIDR2 not supported
11710 20:14:04.119787 # ok 3 skipped, TPIDR2 not supported
11711 20:14:04.123274 # ok 4 skipped, TPIDR2 not supported
11712 20:14:04.129678 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11713 20:14:04.132783 ok 48 selftests: arm64: tpidr2
11714 20:14:04.669053 Traceback (most recent call last):
11715 20:14:04.678846 File "/lava-12928082/0/tests/1_kselftest-arm64/automated/linux/kselftest/./parse-output.py", line 4, in <module>
11716 20:14:04.682500 from tap import parser
11717 20:14:04.685731 ModuleNotFoundError: No module named 'tap'
11718 20:14:04.700946 + ../../utils/send-to-lava.sh ./output/result.txt
11719 20:14:04.762303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11720 20:14:04.762458 + set +x
11721 20:14:04.762737 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11723 20:14:04.768526 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12928082_1.6.2.3.5>
11724 20:14:04.768840 Received signal: <ENDRUN> 1_kselftest-arm64 12928082_1.6.2.3.5
11725 20:14:04.768926 Ending use of test pattern.
11726 20:14:04.768991 Ending test lava.1_kselftest-arm64 (12928082_1.6.2.3.5), duration 21.72
11728 20:14:04.772034 <LAVA_TEST_RUNNER EXIT>
11729 20:14:04.772304 ok: lava_test_shell seems to have completed
11730 20:14:04.772408 shardfile-arm64: pass
11731 20:14:04.772527 end: 3.1 lava-test-shell (duration 00:00:23) [common]
11732 20:14:04.772638 end: 3 lava-test-retry (duration 00:00:23) [common]
11733 20:14:04.772729 start: 4 finalize (timeout 00:07:32) [common]
11734 20:14:04.772823 start: 4.1 power-off (timeout 00:00:30) [common]
11735 20:14:04.772979 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11736 20:14:04.853126 >> Command sent successfully.
11737 20:14:04.855622 Returned 0 in 0 seconds
11738 20:14:04.956080 end: 4.1 power-off (duration 00:00:00) [common]
11740 20:14:04.956423 start: 4.2 read-feedback (timeout 00:07:32) [common]
11741 20:14:04.956685 Listened to connection for namespace 'common' for up to 1s
11742 20:14:05.957354 Finalising connection for namespace 'common'
11743 20:14:05.957581 Disconnecting from shell: Finalise
11744 20:14:05.957672 / #
11745 20:14:06.058070 end: 4.2 read-feedback (duration 00:00:01) [common]
11746 20:14:06.058265 end: 4 finalize (duration 00:00:01) [common]
11747 20:14:06.058381 Cleaning after the job
11748 20:14:06.058483 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/ramdisk
11749 20:14:06.060889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/kernel
11750 20:14:06.071023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/dtb
11751 20:14:06.071280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/nfsrootfs
11752 20:14:06.139123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928082/tftp-deploy-uyoxvert/modules
11753 20:14:06.144737 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928082
11754 20:14:06.676449 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928082
11755 20:14:06.676644 Job finished correctly