Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 36
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 14
1 20:13:15.500538 lava-dispatcher, installed at version: 2024.01
2 20:13:15.500738 start: 0 validate
3 20:13:15.500866 Start time: 2024-03-03 20:13:15.500858+00:00 (UTC)
4 20:13:15.500987 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:13:15.501118 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 20:13:15.503849 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:13:15.503966 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:13:35.277561 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:13:35.277776 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:13:35.547499 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:13:35.547668 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:13:35.812069 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:13:35.812335 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:13:41.316412 validate duration: 25.82
16 20:13:41.316774 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:13:41.316917 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:13:41.317055 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:13:41.317216 Not decompressing ramdisk as can be used compressed.
20 20:13:41.317341 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 20:13:41.317444 saving as /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/ramdisk/initrd.cpio.gz
22 20:13:41.317551 total size: 4663047 (4 MB)
23 20:13:41.318937 progress 0 % (0 MB)
24 20:13:41.320502 progress 5 % (0 MB)
25 20:13:41.321792 progress 10 % (0 MB)
26 20:13:41.323082 progress 15 % (0 MB)
27 20:13:41.324373 progress 20 % (0 MB)
28 20:13:41.325683 progress 25 % (1 MB)
29 20:13:41.326929 progress 30 % (1 MB)
30 20:13:41.328229 progress 35 % (1 MB)
31 20:13:41.329568 progress 40 % (1 MB)
32 20:13:41.330967 progress 45 % (2 MB)
33 20:13:41.332196 progress 50 % (2 MB)
34 20:13:41.333478 progress 55 % (2 MB)
35 20:13:41.334748 progress 60 % (2 MB)
36 20:13:41.335982 progress 65 % (2 MB)
37 20:13:41.337265 progress 70 % (3 MB)
38 20:13:41.338499 progress 75 % (3 MB)
39 20:13:41.339766 progress 80 % (3 MB)
40 20:13:41.341055 progress 85 % (3 MB)
41 20:13:41.342454 progress 90 % (4 MB)
42 20:13:41.343711 progress 95 % (4 MB)
43 20:13:41.345003 progress 100 % (4 MB)
44 20:13:41.345148 4 MB downloaded in 0.03 s (161.13 MB/s)
45 20:13:41.345299 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:13:41.345543 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:13:41.345630 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:13:41.345716 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:13:41.345853 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:13:41.345936 saving as /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/kernel/Image
52 20:13:41.346011 total size: 51601920 (49 MB)
53 20:13:41.346072 No compression specified
54 20:13:41.347233 progress 0 % (0 MB)
55 20:13:41.360855 progress 5 % (2 MB)
56 20:13:41.377537 progress 10 % (4 MB)
57 20:13:41.392129 progress 15 % (7 MB)
58 20:13:41.406764 progress 20 % (9 MB)
59 20:13:41.422213 progress 25 % (12 MB)
60 20:13:41.437813 progress 30 % (14 MB)
61 20:13:41.452732 progress 35 % (17 MB)
62 20:13:41.470986 progress 40 % (19 MB)
63 20:13:41.489647 progress 45 % (22 MB)
64 20:13:41.509108 progress 50 % (24 MB)
65 20:13:41.529197 progress 55 % (27 MB)
66 20:13:41.544552 progress 60 % (29 MB)
67 20:13:41.559312 progress 65 % (32 MB)
68 20:13:41.573845 progress 70 % (34 MB)
69 20:13:41.588201 progress 75 % (36 MB)
70 20:13:41.602522 progress 80 % (39 MB)
71 20:13:41.617726 progress 85 % (41 MB)
72 20:13:41.633699 progress 90 % (44 MB)
73 20:13:41.652960 progress 95 % (46 MB)
74 20:13:41.671831 progress 100 % (49 MB)
75 20:13:41.672236 49 MB downloaded in 0.33 s (150.86 MB/s)
76 20:13:41.672499 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:13:41.672926 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:13:41.673080 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:13:41.673230 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:13:41.673448 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:13:41.673578 saving as /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/dtb/mt8192-asurada-spherion-r0.dtb
83 20:13:41.673690 total size: 47278 (0 MB)
84 20:13:41.673810 No compression specified
85 20:13:41.675650 progress 69 % (0 MB)
86 20:13:41.675992 progress 100 % (0 MB)
87 20:13:41.676229 0 MB downloaded in 0.00 s (17.79 MB/s)
88 20:13:41.676451 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:13:41.676865 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:13:41.677014 start: 1.4 download-retry (timeout 00:10:00) [common]
92 20:13:41.677157 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 20:13:41.677350 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 20:13:41.677468 saving as /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/nfsrootfs/full.rootfs.tar
95 20:13:41.677577 total size: 200856304 (191 MB)
96 20:13:41.677690 Using unxz to decompress xz
97 20:13:41.683352 progress 0 % (0 MB)
98 20:13:42.269485 progress 5 % (9 MB)
99 20:13:42.849530 progress 10 % (19 MB)
100 20:13:43.554278 progress 15 % (28 MB)
101 20:13:43.958809 progress 20 % (38 MB)
102 20:13:44.355279 progress 25 % (47 MB)
103 20:13:45.071787 progress 30 % (57 MB)
104 20:13:45.689404 progress 35 % (67 MB)
105 20:13:46.380780 progress 40 % (76 MB)
106 20:13:47.033707 progress 45 % (86 MB)
107 20:13:47.787549 progress 50 % (95 MB)
108 20:13:48.572607 progress 55 % (105 MB)
109 20:13:49.349053 progress 60 % (114 MB)
110 20:13:49.479169 progress 65 % (124 MB)
111 20:13:49.648523 progress 70 % (134 MB)
112 20:13:49.756090 progress 75 % (143 MB)
113 20:13:49.835796 progress 80 % (153 MB)
114 20:13:49.921457 progress 85 % (162 MB)
115 20:13:50.049353 progress 90 % (172 MB)
116 20:13:50.421050 progress 95 % (182 MB)
117 20:13:51.055109 progress 100 % (191 MB)
118 20:13:51.061266 191 MB downloaded in 9.38 s (20.41 MB/s)
119 20:13:51.061576 end: 1.4.1 http-download (duration 00:00:09) [common]
121 20:13:51.061863 end: 1.4 download-retry (duration 00:00:09) [common]
122 20:13:51.061957 start: 1.5 download-retry (timeout 00:09:50) [common]
123 20:13:51.062047 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 20:13:51.062200 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:13:51.062273 saving as /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/modules/modules.tar
126 20:13:51.062336 total size: 8632284 (8 MB)
127 20:13:51.062402 Using unxz to decompress xz
128 20:13:51.067122 progress 0 % (0 MB)
129 20:13:51.088949 progress 5 % (0 MB)
130 20:13:51.115779 progress 10 % (0 MB)
131 20:13:51.142248 progress 15 % (1 MB)
132 20:13:51.166652 progress 20 % (1 MB)
133 20:13:51.193435 progress 25 % (2 MB)
134 20:13:51.221622 progress 30 % (2 MB)
135 20:13:51.250381 progress 35 % (2 MB)
136 20:13:51.277726 progress 40 % (3 MB)
137 20:13:51.303261 progress 45 % (3 MB)
138 20:13:51.329831 progress 50 % (4 MB)
139 20:13:51.357220 progress 55 % (4 MB)
140 20:13:51.384458 progress 60 % (4 MB)
141 20:13:51.411556 progress 65 % (5 MB)
142 20:13:51.440740 progress 70 % (5 MB)
143 20:13:51.477140 progress 75 % (6 MB)
144 20:13:51.512051 progress 80 % (6 MB)
145 20:13:51.537806 progress 85 % (7 MB)
146 20:13:51.565380 progress 90 % (7 MB)
147 20:13:51.596180 progress 95 % (7 MB)
148 20:13:51.627048 progress 100 % (8 MB)
149 20:13:51.632902 8 MB downloaded in 0.57 s (14.43 MB/s)
150 20:13:51.633390 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:13:51.633958 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:13:51.634131 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 20:13:51.634313 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 20:13:55.753905 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo
156 20:13:55.754203 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 20:13:55.754371 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 20:13:55.754630 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1
159 20:13:55.754834 makedir: /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin
160 20:13:55.755000 makedir: /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/tests
161 20:13:55.755163 makedir: /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/results
162 20:13:55.755328 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-add-keys
163 20:13:55.755564 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-add-sources
164 20:13:55.755776 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-background-process-start
165 20:13:55.755987 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-background-process-stop
166 20:13:55.756193 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-common-functions
167 20:13:55.756403 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-echo-ipv4
168 20:13:55.756611 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-install-packages
169 20:13:55.756818 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-installed-packages
170 20:13:55.757024 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-os-build
171 20:13:55.757232 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-probe-channel
172 20:13:55.757442 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-probe-ip
173 20:13:55.757650 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-target-ip
174 20:13:55.757858 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-target-mac
175 20:13:55.758064 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-target-storage
176 20:13:55.758270 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-case
177 20:13:55.758476 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-event
178 20:13:55.758679 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-feedback
179 20:13:55.758883 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-raise
180 20:13:55.759088 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-reference
181 20:13:55.759293 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-runner
182 20:13:55.759499 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-set
183 20:13:55.759708 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-test-shell
184 20:13:55.759919 Updating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-add-keys (debian)
185 20:13:55.760165 Updating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-add-sources (debian)
186 20:13:55.760656 Updating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-install-packages (debian)
187 20:13:55.760878 Updating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-installed-packages (debian)
188 20:13:55.761160 Updating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/bin/lava-os-build (debian)
189 20:13:55.761388 Creating /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/environment
190 20:13:55.761601 LAVA metadata
191 20:13:55.761760 - LAVA_JOB_ID=12928080
192 20:13:55.761909 - LAVA_DISPATCHER_IP=192.168.201.1
193 20:13:55.762137 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 20:13:55.762268 skipped lava-vland-overlay
195 20:13:55.762427 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 20:13:55.762604 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 20:13:55.762712 skipped lava-multinode-overlay
198 20:13:55.762837 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 20:13:55.762981 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 20:13:55.763114 Loading test definitions
201 20:13:55.763271 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 20:13:55.763398 Using /lava-12928080 at stage 0
203 20:13:55.763914 uuid=12928080_1.6.2.3.1 testdef=None
204 20:13:55.764053 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 20:13:55.764230 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 20:13:55.765073 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 20:13:55.765477 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 20:13:55.766437 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 20:13:55.766891 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 20:13:55.767922 runner path: /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/0/tests/0_timesync-off test_uuid 12928080_1.6.2.3.1
213 20:13:55.768174 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 20:13:55.768741 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 20:13:55.768868 Using /lava-12928080 at stage 0
217 20:13:55.769027 Fetching tests from https://github.com/kernelci/test-definitions.git
218 20:13:55.769172 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/0/tests/1_kselftest-dt'
219 20:13:59.113403 Running '/usr/bin/git checkout kernelci.org
220 20:13:59.200518 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 20:13:59.201724 uuid=12928080_1.6.2.3.5 testdef=None
222 20:13:59.202022 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 20:13:59.202503 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 20:13:59.203962 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 20:13:59.204411 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 20:13:59.206349 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 20:13:59.206813 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 20:13:59.208702 runner path: /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/0/tests/1_kselftest-dt test_uuid 12928080_1.6.2.3.5
232 20:13:59.208866 BOARD='mt8192-asurada-spherion-r0'
233 20:13:59.209007 BRANCH='cip-gitlab'
234 20:13:59.209149 SKIPFILE='/dev/null'
235 20:13:59.209284 SKIP_INSTALL='True'
236 20:13:59.209422 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 20:13:59.209569 TST_CASENAME=''
238 20:13:59.209708 TST_CMDFILES='dt'
239 20:13:59.209965 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 20:13:59.210373 Creating lava-test-runner.conf files
242 20:13:59.210490 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928080/lava-overlay-m16apvc1/lava-12928080/0 for stage 0
243 20:13:59.210651 - 0_timesync-off
244 20:13:59.210777 - 1_kselftest-dt
245 20:13:59.210988 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 20:13:59.211151 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 20:14:07.436045 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 20:14:07.436202 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 20:14:07.436303 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 20:14:07.436405 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 20:14:07.436497 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 20:14:07.562619 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 20:14:07.563105 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 20:14:07.563334 extracting modules file /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo
255 20:14:07.962587 extracting modules file /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928080/extract-overlay-ramdisk-0c2qs7v6/ramdisk
256 20:14:08.240553 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 20:14:08.240710 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 20:14:08.240816 [common] Applying overlay to NFS
259 20:14:08.240883 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928080/compress-overlay-7lsz0pqs/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo
260 20:14:09.313949 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 20:14:09.314123 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 20:14:09.314223 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 20:14:09.314315 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 20:14:09.314398 Building ramdisk /var/lib/lava/dispatcher/tmp/12928080/extract-overlay-ramdisk-0c2qs7v6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928080/extract-overlay-ramdisk-0c2qs7v6/ramdisk
265 20:14:09.686238 >> 119447 blocks
266 20:14:11.807360 rename /var/lib/lava/dispatcher/tmp/12928080/extract-overlay-ramdisk-0c2qs7v6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/ramdisk/ramdisk.cpio.gz
267 20:14:11.807989 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 20:14:11.808184 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 20:14:11.808387 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 20:14:11.808576 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/kernel/Image'
271 20:14:26.692449 Returned 0 in 14 seconds
272 20:14:26.793216 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/kernel/image.itb
273 20:14:27.234861 output: FIT description: Kernel Image image with one or more FDT blobs
274 20:14:27.235370 output: Created: Sun Mar 3 20:14:27 2024
275 20:14:27.235497 output: Image 0 (kernel-1)
276 20:14:27.235617 output: Description:
277 20:14:27.235726 output: Created: Sun Mar 3 20:14:27 2024
278 20:14:27.235846 output: Type: Kernel Image
279 20:14:27.235958 output: Compression: lzma compressed
280 20:14:27.236075 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
281 20:14:27.236192 output: Architecture: AArch64
282 20:14:27.236318 output: OS: Linux
283 20:14:27.236436 output: Load Address: 0x00000000
284 20:14:27.236554 output: Entry Point: 0x00000000
285 20:14:27.236669 output: Hash algo: crc32
286 20:14:27.236788 output: Hash value: 91cb1a17
287 20:14:27.236909 output: Image 1 (fdt-1)
288 20:14:27.237014 output: Description: mt8192-asurada-spherion-r0
289 20:14:27.237124 output: Created: Sun Mar 3 20:14:27 2024
290 20:14:27.237235 output: Type: Flat Device Tree
291 20:14:27.237342 output: Compression: uncompressed
292 20:14:27.237448 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 20:14:27.237559 output: Architecture: AArch64
294 20:14:27.237671 output: Hash algo: crc32
295 20:14:27.237780 output: Hash value: cc4352de
296 20:14:27.237891 output: Image 2 (ramdisk-1)
297 20:14:27.238002 output: Description: unavailable
298 20:14:27.238112 output: Created: Sun Mar 3 20:14:27 2024
299 20:14:27.238222 output: Type: RAMDisk Image
300 20:14:27.238327 output: Compression: Unknown Compression
301 20:14:27.238437 output: Data Size: 17803460 Bytes = 17386.19 KiB = 16.98 MiB
302 20:14:27.238545 output: Architecture: AArch64
303 20:14:27.238655 output: OS: Linux
304 20:14:27.238758 output: Load Address: unavailable
305 20:14:27.238868 output: Entry Point: unavailable
306 20:14:27.238976 output: Hash algo: crc32
307 20:14:27.239086 output: Hash value: 2c9deba9
308 20:14:27.239192 output: Default Configuration: 'conf-1'
309 20:14:27.239303 output: Configuration 0 (conf-1)
310 20:14:27.239413 output: Description: mt8192-asurada-spherion-r0
311 20:14:27.239524 output: Kernel: kernel-1
312 20:14:27.239627 output: Init Ramdisk: ramdisk-1
313 20:14:27.239736 output: FDT: fdt-1
314 20:14:27.239846 output: Loadables: kernel-1
315 20:14:27.239949 output:
316 20:14:27.240265 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 20:14:27.240442 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 20:14:27.240622 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 20:14:27.240787 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 20:14:27.240936 No LXC device requested
321 20:14:27.241083 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 20:14:27.241240 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 20:14:27.241383 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 20:14:27.241507 Checking files for TFTP limit of 4294967296 bytes.
325 20:14:27.242345 end: 1 tftp-deploy (duration 00:00:46) [common]
326 20:14:27.242523 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 20:14:27.242684 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 20:14:27.242896 substitutions:
329 20:14:27.243021 - {DTB}: 12928080/tftp-deploy-c59hqd2v/dtb/mt8192-asurada-spherion-r0.dtb
330 20:14:27.243141 - {INITRD}: 12928080/tftp-deploy-c59hqd2v/ramdisk/ramdisk.cpio.gz
331 20:14:27.243255 - {KERNEL}: 12928080/tftp-deploy-c59hqd2v/kernel/Image
332 20:14:27.243366 - {LAVA_MAC}: None
333 20:14:27.243482 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo
334 20:14:27.243594 - {NFS_SERVER_IP}: 192.168.201.1
335 20:14:27.243706 - {PRESEED_CONFIG}: None
336 20:14:27.243819 - {PRESEED_LOCAL}: None
337 20:14:27.243932 - {RAMDISK}: 12928080/tftp-deploy-c59hqd2v/ramdisk/ramdisk.cpio.gz
338 20:14:27.244042 - {ROOT_PART}: None
339 20:14:27.244153 - {ROOT}: None
340 20:14:27.244265 - {SERVER_IP}: 192.168.201.1
341 20:14:27.244381 - {TEE}: None
342 20:14:27.244493 Parsed boot commands:
343 20:14:27.244602 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 20:14:27.244898 Parsed boot commands: tftpboot 192.168.201.1 12928080/tftp-deploy-c59hqd2v/kernel/image.itb 12928080/tftp-deploy-c59hqd2v/kernel/cmdline
345 20:14:27.245043 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 20:14:27.245196 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 20:14:27.245358 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 20:14:27.245512 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 20:14:27.245644 Not connected, no need to disconnect.
350 20:14:27.245780 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 20:14:27.245927 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 20:14:27.246055 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 20:14:27.251109 Setting prompt string to ['lava-test: # ']
354 20:14:27.251650 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 20:14:27.251838 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 20:14:27.252010 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 20:14:27.252173 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 20:14:27.252548 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 20:14:32.379066 >> Command sent successfully.
360 20:14:32.382623 Returned 0 in 5 seconds
361 20:14:32.483043 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 20:14:32.483375 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 20:14:32.483477 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 20:14:32.483574 Setting prompt string to 'Starting depthcharge on Spherion...'
366 20:14:32.483657 Changing prompt to 'Starting depthcharge on Spherion...'
367 20:14:32.483754 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 20:14:32.484039 [Enter `^Ec?' for help]
369 20:14:32.655117
370 20:14:32.655269
371 20:14:32.655358 F0: 102B 0000
372 20:14:32.655441
373 20:14:32.655504 F3: 1001 0000 [0200]
374 20:14:32.658346
375 20:14:32.658429 F3: 1001 0000
376 20:14:32.658496
377 20:14:32.658559 F7: 102D 0000
378 20:14:32.658618
379 20:14:32.661349 F1: 0000 0000
380 20:14:32.661433
381 20:14:32.661500 V0: 0000 0000 [0001]
382 20:14:32.661613
383 20:14:32.664962 00: 0007 8000
384 20:14:32.665050
385 20:14:32.665116 01: 0000 0000
386 20:14:32.665180
387 20:14:32.668182 BP: 0C00 0209 [0000]
388 20:14:32.668306
389 20:14:32.668390 G0: 1182 0000
390 20:14:32.668452
391 20:14:32.672073 EC: 0000 0021 [4000]
392 20:14:32.672155
393 20:14:32.672221 S7: 0000 0000 [0000]
394 20:14:32.672282
395 20:14:32.675792 CC: 0000 0000 [0001]
396 20:14:32.675873
397 20:14:32.675938 T0: 0000 0040 [010F]
398 20:14:32.676008
399 20:14:32.676077 Jump to BL
400 20:14:32.676136
401 20:14:32.702023
402 20:14:32.702176
403 20:14:32.702276
404 20:14:32.709946 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 20:14:32.713701 ARM64: Exception handlers installed.
406 20:14:32.717434 ARM64: Testing exception
407 20:14:32.717559 ARM64: Done test exception
408 20:14:32.727594 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 20:14:32.737704 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 20:14:32.744262 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 20:14:32.754455 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 20:14:32.761231 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 20:14:32.767849 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 20:14:32.778865 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 20:14:32.785531 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 20:14:32.804729 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 20:14:32.808257 WDT: Last reset was cold boot
418 20:14:32.811450 SPI1(PAD0) initialized at 2873684 Hz
419 20:14:32.815006 SPI5(PAD0) initialized at 992727 Hz
420 20:14:32.818761 VBOOT: Loading verstage.
421 20:14:32.824792 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:14:32.828514 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:14:32.831529 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:14:32.835129 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:14:32.842523 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:14:32.848869 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:14:32.860353 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 20:14:32.860439
429 20:14:32.860506
430 20:14:32.870110 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:14:32.873767 ARM64: Exception handlers installed.
432 20:14:32.877175 ARM64: Testing exception
433 20:14:32.877290 ARM64: Done test exception
434 20:14:32.883667 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:14:32.887406 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:14:32.900778 Probing TPM: . done!
437 20:14:32.900862 TPM ready after 0 ms
438 20:14:32.907849 Connected to device vid:did:rid of 1ae0:0028:00
439 20:14:32.914975 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 20:14:32.974278 Initialized TPM device CR50 revision 0
441 20:14:32.986475 tlcl_send_startup: Startup return code is 0
442 20:14:32.986628 TPM: setup succeeded
443 20:14:32.997642 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:14:33.006830 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:14:33.018443 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:14:33.028714 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:14:33.032023 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:14:33.035826 in-header: 03 07 00 00 08 00 00 00
449 20:14:33.039467 in-data: aa e4 47 04 13 02 00 00
450 20:14:33.043222 Chrome EC: UHEPI supported
451 20:14:33.047097 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:14:33.052105 in-header: 03 95 00 00 08 00 00 00
453 20:14:33.055840 in-data: 18 20 20 08 00 00 00 00
454 20:14:33.055964 Phase 1
455 20:14:33.062800 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:14:33.066466 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:14:33.074047 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:14:33.074184 Recovery requested (1009000e)
459 20:14:33.086634 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:14:33.090737 tlcl_extend: response is 0
461 20:14:33.101508 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:14:33.104966 tlcl_extend: response is 0
463 20:14:33.112075 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:14:33.131975 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 20:14:33.138576 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 20:14:33.138680
467 20:14:33.138749
468 20:14:33.148515 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:14:33.151578 ARM64: Exception handlers installed.
470 20:14:33.155236 ARM64: Testing exception
471 20:14:33.155361 ARM64: Done test exception
472 20:14:33.177597 pmic_efuse_setting: Set efuses in 11 msecs
473 20:14:33.180826 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:14:33.187557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:14:33.191368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:14:33.194896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:14:33.202587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:14:33.206326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:14:33.209977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:14:33.217810 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:14:33.221521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:14:33.225170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:14:33.229046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:14:33.235956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:14:33.239957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:14:33.244120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:14:33.250840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:14:33.255195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:14:33.262168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:14:33.266033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:14:33.273387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:14:33.277170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:14:33.284877 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:14:33.288059 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:14:33.295259 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:14:33.298867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:14:33.306654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:14:33.310457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:14:33.317981 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:14:33.321692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:14:33.325424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:14:33.332238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:14:33.336359 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:14:33.339926 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:14:33.347540 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:14:33.351237 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:14:33.358379 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:14:33.362271 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:14:33.365720 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:14:33.373946 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:14:33.377358 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:14:33.381155 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:14:33.384875 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:14:33.388624 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:14:33.396180 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:14:33.400501 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:14:33.404131 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:14:33.407350 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:14:33.411006 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:14:33.415146 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:14:33.418826 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:14:33.426336 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:14:33.430156 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:14:33.433887 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:14:33.440832 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:14:33.448611 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:14:33.451529 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:14:33.462684 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:14:33.470217 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:14:33.473847 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:14:33.477856 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:14:33.485136 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:14:33.489046 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
534 20:14:33.496568 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:14:33.500486 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 20:14:33.503369 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:14:33.515403 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 20:14:33.524216 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 20:14:33.533876 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 20:14:33.543442 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 20:14:33.552768 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 20:14:33.562398 [RTC]rtc_get_frequency_meter,154: input=16, output=783
543 20:14:33.573415 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 20:14:33.576632 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 20:14:33.580590 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 20:14:33.584380 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 20:14:33.587601 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 20:14:33.595801 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 20:14:33.598973 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 20:14:33.599063 ADC[4]: Raw value=906203 ID=7
551 20:14:33.602815 ADC[3]: Raw value=213441 ID=1
552 20:14:33.606364 RAM Code: 0x71
553 20:14:33.610346 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 20:14:33.614005 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 20:14:33.621220 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 20:14:33.629482 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 20:14:33.632803 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 20:14:33.636485 in-header: 03 07 00 00 08 00 00 00
559 20:14:33.640457 in-data: aa e4 47 04 13 02 00 00
560 20:14:33.644244 Chrome EC: UHEPI supported
561 20:14:33.647516 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 20:14:33.651375 in-header: 03 95 00 00 08 00 00 00
563 20:14:33.655152 in-data: 18 20 20 08 00 00 00 00
564 20:14:33.658850 MRC: failed to locate region type 0.
565 20:14:33.666764 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 20:14:33.666883 DRAM-K: Running full calibration
567 20:14:33.674236 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 20:14:33.677940 header.status = 0x0
569 20:14:33.678027 header.version = 0x6 (expected: 0x6)
570 20:14:33.681361 header.size = 0xd00 (expected: 0xd00)
571 20:14:33.685228 header.flags = 0x0
572 20:14:33.692344 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 20:14:33.708856 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 20:14:33.716535 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 20:14:33.716638 dram_init: ddr_geometry: 2
576 20:14:33.720921 [EMI] MDL number = 2
577 20:14:33.720998 [EMI] Get MDL freq = 0
578 20:14:33.724390 dram_init: ddr_type: 0
579 20:14:33.727918 is_discrete_lpddr4: 1
580 20:14:33.727998 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 20:14:33.731646
582 20:14:33.731749
583 20:14:33.731820 [Bian_co] ETT version 0.0.0.1
584 20:14:33.739350 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 20:14:33.739440
586 20:14:33.743178 dramc_set_vcore_voltage set vcore to 650000
587 20:14:33.743265 Read voltage for 800, 4
588 20:14:33.743335 Vio18 = 0
589 20:14:33.746491 Vcore = 650000
590 20:14:33.746574 Vdram = 0
591 20:14:33.746654 Vddq = 0
592 20:14:33.746722 Vmddr = 0
593 20:14:33.750240 dram_init: config_dvfs: 1
594 20:14:33.754221 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 20:14:33.761755 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 20:14:33.765281 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 20:14:33.769375 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 20:14:33.773143 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 20:14:33.776633 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 20:14:33.780275 MEM_TYPE=3, freq_sel=18
601 20:14:33.780366 sv_algorithm_assistance_LP4_1600
602 20:14:33.786627 ============ PULL DRAM RESETB DOWN ============
603 20:14:33.790329 ========== PULL DRAM RESETB DOWN end =========
604 20:14:33.793485 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 20:14:33.797215 ===================================
606 20:14:33.800941 LPDDR4 DRAM CONFIGURATION
607 20:14:33.804849 ===================================
608 20:14:33.804936 EX_ROW_EN[0] = 0x0
609 20:14:33.808604 EX_ROW_EN[1] = 0x0
610 20:14:33.808690 LP4Y_EN = 0x0
611 20:14:33.811628 WORK_FSP = 0x0
612 20:14:33.811715 WL = 0x2
613 20:14:33.815481 RL = 0x2
614 20:14:33.815561 BL = 0x2
615 20:14:33.819202 RPST = 0x0
616 20:14:33.819278 RD_PRE = 0x0
617 20:14:33.822376 WR_PRE = 0x1
618 20:14:33.822455 WR_PST = 0x0
619 20:14:33.825466 DBI_WR = 0x0
620 20:14:33.825545 DBI_RD = 0x0
621 20:14:33.829112 OTF = 0x1
622 20:14:33.832095 ===================================
623 20:14:33.835777 ===================================
624 20:14:33.835857 ANA top config
625 20:14:33.838869 ===================================
626 20:14:33.842097 DLL_ASYNC_EN = 0
627 20:14:33.845860 ALL_SLAVE_EN = 1
628 20:14:33.845949 NEW_RANK_MODE = 1
629 20:14:33.849264 DLL_IDLE_MODE = 1
630 20:14:33.852133 LP45_APHY_COMB_EN = 1
631 20:14:33.856091 TX_ODT_DIS = 1
632 20:14:33.856205 NEW_8X_MODE = 1
633 20:14:33.859837 ===================================
634 20:14:33.862760 ===================================
635 20:14:33.866286 data_rate = 1600
636 20:14:33.869684 CKR = 1
637 20:14:33.872818 DQ_P2S_RATIO = 8
638 20:14:33.876584 ===================================
639 20:14:33.879580 CA_P2S_RATIO = 8
640 20:14:33.879685 DQ_CA_OPEN = 0
641 20:14:33.883031 DQ_SEMI_OPEN = 0
642 20:14:33.886545 CA_SEMI_OPEN = 0
643 20:14:33.889539 CA_FULL_RATE = 0
644 20:14:33.893131 DQ_CKDIV4_EN = 1
645 20:14:33.896255 CA_CKDIV4_EN = 1
646 20:14:33.896377 CA_PREDIV_EN = 0
647 20:14:33.900028 PH8_DLY = 0
648 20:14:33.903130 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 20:14:33.906747 DQ_AAMCK_DIV = 4
650 20:14:33.909849 CA_AAMCK_DIV = 4
651 20:14:33.913082 CA_ADMCK_DIV = 4
652 20:14:33.913197 DQ_TRACK_CA_EN = 0
653 20:14:33.916139 CA_PICK = 800
654 20:14:33.919848 CA_MCKIO = 800
655 20:14:33.923806 MCKIO_SEMI = 0
656 20:14:33.927106 PLL_FREQ = 3068
657 20:14:33.927218 DQ_UI_PI_RATIO = 32
658 20:14:33.930364 CA_UI_PI_RATIO = 0
659 20:14:33.934173 ===================================
660 20:14:33.938355 ===================================
661 20:14:33.941985 memory_type:LPDDR4
662 20:14:33.942076 GP_NUM : 10
663 20:14:33.945239 SRAM_EN : 1
664 20:14:33.945328 MD32_EN : 0
665 20:14:33.949027 ===================================
666 20:14:33.952196 [ANA_INIT] >>>>>>>>>>>>>>
667 20:14:33.956154 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 20:14:33.959491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 20:14:33.963016 ===================================
670 20:14:33.963125 data_rate = 1600,PCW = 0X7600
671 20:14:33.966097 ===================================
672 20:14:33.969895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 20:14:33.976410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 20:14:33.983232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 20:14:33.986289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 20:14:33.989932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 20:14:33.993534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 20:14:33.996416 [ANA_INIT] flow start
679 20:14:33.999811 [ANA_INIT] PLL >>>>>>>>
680 20:14:33.999938 [ANA_INIT] PLL <<<<<<<<
681 20:14:34.002943 [ANA_INIT] MIDPI >>>>>>>>
682 20:14:34.006644 [ANA_INIT] MIDPI <<<<<<<<
683 20:14:34.006770 [ANA_INIT] DLL >>>>>>>>
684 20:14:34.009962 [ANA_INIT] flow end
685 20:14:34.013188 ============ LP4 DIFF to SE enter ============
686 20:14:34.016224 ============ LP4 DIFF to SE exit ============
687 20:14:34.019873 [ANA_INIT] <<<<<<<<<<<<<
688 20:14:34.023177 [Flow] Enable top DCM control >>>>>
689 20:14:34.026582 [Flow] Enable top DCM control <<<<<
690 20:14:34.030151 Enable DLL master slave shuffle
691 20:14:34.036333 ==============================================================
692 20:14:34.036457 Gating Mode config
693 20:14:34.043105 ==============================================================
694 20:14:34.043232 Config description:
695 20:14:34.053456 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 20:14:34.060294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 20:14:34.066627 SELPH_MODE 0: By rank 1: By Phase
698 20:14:34.070035 ==============================================================
699 20:14:34.073464 GAT_TRACK_EN = 1
700 20:14:34.076884 RX_GATING_MODE = 2
701 20:14:34.080104 RX_GATING_TRACK_MODE = 2
702 20:14:34.083736 SELPH_MODE = 1
703 20:14:34.086918 PICG_EARLY_EN = 1
704 20:14:34.090534 VALID_LAT_VALUE = 1
705 20:14:34.093709 ==============================================================
706 20:14:34.096825 Enter into Gating configuration >>>>
707 20:14:34.099890 Exit from Gating configuration <<<<
708 20:14:34.103581 Enter into DVFS_PRE_config >>>>>
709 20:14:34.117025 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 20:14:34.117124 Exit from DVFS_PRE_config <<<<<
711 20:14:34.120135 Enter into PICG configuration >>>>
712 20:14:34.123179 Exit from PICG configuration <<<<
713 20:14:34.126688 [RX_INPUT] configuration >>>>>
714 20:14:34.130241 [RX_INPUT] configuration <<<<<
715 20:14:34.136593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 20:14:34.139802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 20:14:34.146627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 20:14:34.153377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 20:14:34.159878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 20:14:34.166718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 20:14:34.169784 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 20:14:34.173215 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 20:14:34.177057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 20:14:34.183549 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 20:14:34.187099 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 20:14:34.190125 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 20:14:34.193448 ===================================
728 20:14:34.196666 LPDDR4 DRAM CONFIGURATION
729 20:14:34.200492 ===================================
730 20:14:34.200578 EX_ROW_EN[0] = 0x0
731 20:14:34.203458 EX_ROW_EN[1] = 0x0
732 20:14:34.203543 LP4Y_EN = 0x0
733 20:14:34.206499 WORK_FSP = 0x0
734 20:14:34.210441 WL = 0x2
735 20:14:34.210527 RL = 0x2
736 20:14:34.213738 BL = 0x2
737 20:14:34.213845 RPST = 0x0
738 20:14:34.217075 RD_PRE = 0x0
739 20:14:34.217186 WR_PRE = 0x1
740 20:14:34.220144 WR_PST = 0x0
741 20:14:34.220251 DBI_WR = 0x0
742 20:14:34.223372 DBI_RD = 0x0
743 20:14:34.223447 OTF = 0x1
744 20:14:34.226997 ===================================
745 20:14:34.230000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 20:14:34.236805 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 20:14:34.239956 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 20:14:34.243267 ===================================
749 20:14:34.247101 LPDDR4 DRAM CONFIGURATION
750 20:14:34.250388 ===================================
751 20:14:34.250468 EX_ROW_EN[0] = 0x10
752 20:14:34.253489 EX_ROW_EN[1] = 0x0
753 20:14:34.253591 LP4Y_EN = 0x0
754 20:14:34.257294 WORK_FSP = 0x0
755 20:14:34.257367 WL = 0x2
756 20:14:34.260095 RL = 0x2
757 20:14:34.260195 BL = 0x2
758 20:14:34.263262 RPST = 0x0
759 20:14:34.263371 RD_PRE = 0x0
760 20:14:34.266987 WR_PRE = 0x1
761 20:14:34.267094 WR_PST = 0x0
762 20:14:34.270100 DBI_WR = 0x0
763 20:14:34.273249 DBI_RD = 0x0
764 20:14:34.273332 OTF = 0x1
765 20:14:34.277013 ===================================
766 20:14:34.283512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 20:14:34.286711 nWR fixed to 40
768 20:14:34.290329 [ModeRegInit_LP4] CH0 RK0
769 20:14:34.290409 [ModeRegInit_LP4] CH0 RK1
770 20:14:34.293543 [ModeRegInit_LP4] CH1 RK0
771 20:14:34.296818 [ModeRegInit_LP4] CH1 RK1
772 20:14:34.296900 match AC timing 13
773 20:14:34.303257 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 20:14:34.307058 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 20:14:34.309954 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 20:14:34.316898 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 20:14:34.320087 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 20:14:34.320194 [EMI DOE] emi_dcm 0
779 20:14:34.326542 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 20:14:34.326651 ==
781 20:14:34.329818 Dram Type= 6, Freq= 0, CH_0, rank 0
782 20:14:34.333713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 20:14:34.333823 ==
784 20:14:34.340180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 20:14:34.346719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 20:14:34.354434 [CA 0] Center 36 (6~67) winsize 62
787 20:14:34.357544 [CA 1] Center 36 (6~67) winsize 62
788 20:14:34.360666 [CA 2] Center 34 (4~65) winsize 62
789 20:14:34.363957 [CA 3] Center 33 (3~64) winsize 62
790 20:14:34.367547 [CA 4] Center 33 (3~63) winsize 61
791 20:14:34.371206 [CA 5] Center 32 (3~62) winsize 60
792 20:14:34.371314
793 20:14:34.374358 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 20:14:34.374465
795 20:14:34.377730 [CATrainingPosCal] consider 1 rank data
796 20:14:34.381474 u2DelayCellTimex100 = 270/100 ps
797 20:14:34.384722 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 20:14:34.387781 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 20:14:34.391037 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 20:14:34.397900 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 20:14:34.400900 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 20:14:34.404718 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 20:14:34.404817
804 20:14:34.407972 CA PerBit enable=1, Macro0, CA PI delay=32
805 20:14:34.408078
806 20:14:34.411190 [CBTSetCACLKResult] CA Dly = 32
807 20:14:34.411294 CS Dly: 4 (0~35)
808 20:14:34.411404 ==
809 20:14:34.414401 Dram Type= 6, Freq= 0, CH_0, rank 1
810 20:14:34.421219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 20:14:34.421328 ==
812 20:14:34.424383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 20:14:34.431469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 20:14:34.440421 [CA 0] Center 36 (6~67) winsize 62
815 20:14:34.443880 [CA 1] Center 36 (6~67) winsize 62
816 20:14:34.446809 [CA 2] Center 34 (4~65) winsize 62
817 20:14:34.450740 [CA 3] Center 33 (3~64) winsize 62
818 20:14:34.454077 [CA 4] Center 33 (3~63) winsize 61
819 20:14:34.457241 [CA 5] Center 32 (2~63) winsize 62
820 20:14:34.457327
821 20:14:34.460578 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 20:14:34.460693
823 20:14:34.463553 [CATrainingPosCal] consider 2 rank data
824 20:14:34.467372 u2DelayCellTimex100 = 270/100 ps
825 20:14:34.470554 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 20:14:34.473743 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 20:14:34.480249 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 20:14:34.483990 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 20:14:34.487352 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 20:14:34.490575 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 20:14:34.490696
832 20:14:34.493751 CA PerBit enable=1, Macro0, CA PI delay=32
833 20:14:34.493828
834 20:14:34.497106 [CBTSetCACLKResult] CA Dly = 32
835 20:14:34.497184 CS Dly: 5 (0~37)
836 20:14:34.497247
837 20:14:34.500828 ----->DramcWriteLeveling(PI) begin...
838 20:14:34.500921 ==
839 20:14:34.504648 Dram Type= 6, Freq= 0, CH_0, rank 0
840 20:14:34.507796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 20:14:34.511923 ==
842 20:14:34.512028 Write leveling (Byte 0): 34 => 34
843 20:14:34.515080 Write leveling (Byte 1): 29 => 29
844 20:14:34.518849 DramcWriteLeveling(PI) end<-----
845 20:14:34.518961
846 20:14:34.519056 ==
847 20:14:34.522494 Dram Type= 6, Freq= 0, CH_0, rank 0
848 20:14:34.525982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 20:14:34.526088 ==
850 20:14:34.528954 [Gating] SW mode calibration
851 20:14:34.536568 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 20:14:34.543552 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 20:14:34.546876 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 20:14:34.550072 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 20:14:34.553489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 20:14:34.560620 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 20:14:34.563744 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:14:34.567012 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:14:34.573475 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:14:34.576742 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:14:34.580339 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:14:34.587205 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:14:34.590306 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 20:14:34.593292 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 20:14:34.600251 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 20:14:34.603389 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 20:14:34.607006 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 20:14:34.613459 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 20:14:34.617139 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 20:14:34.620266 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 20:14:34.623401 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 20:14:34.630283 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 20:14:34.633926 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 20:14:34.636948 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 20:14:34.643752 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 20:14:34.647465 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 20:14:34.650295 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 20:14:34.656979 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 20:14:34.660612 0 9 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 0)
880 20:14:34.664270 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
881 20:14:34.670754 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 20:14:34.674021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 20:14:34.677237 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 20:14:34.683665 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 20:14:34.687311 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 20:14:34.690800 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
887 20:14:34.693814 0 10 8 | B1->B0 | 2f2f 2b2b | 1 0 | (1 1) (1 0)
888 20:14:34.700853 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 20:14:34.704243 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 20:14:34.707312 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 20:14:34.714176 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 20:14:34.717301 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 20:14:34.720925 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 20:14:34.727213 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 20:14:34.730898 0 11 8 | B1->B0 | 2d2d 3d3d | 1 1 | (0 0) (0 0)
896 20:14:34.734096 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
897 20:14:34.740765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 20:14:34.743882 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 20:14:34.747551 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 20:14:34.754450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 20:14:34.757418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 20:14:34.761017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 20:14:34.767614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 20:14:34.771213 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 20:14:34.774339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 20:14:34.777471 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 20:14:34.784064 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 20:14:34.787658 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 20:14:34.790801 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 20:14:34.797472 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 20:14:34.801022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 20:14:34.804457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 20:14:34.810672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 20:14:34.814185 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 20:14:34.817596 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 20:14:34.824246 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 20:14:34.827330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 20:14:34.831125 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 20:14:34.837538 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 20:14:34.837627 Total UI for P1: 0, mck2ui 16
921 20:14:34.844655 best dqsien dly found for B0: ( 0, 14, 6)
922 20:14:34.847586 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 20:14:34.850825 Total UI for P1: 0, mck2ui 16
924 20:14:34.854790 best dqsien dly found for B1: ( 0, 14, 8)
925 20:14:34.858017 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 20:14:34.861083 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 20:14:34.861208
928 20:14:34.864845 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 20:14:34.868058 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 20:14:34.871115 [Gating] SW calibration Done
931 20:14:34.871196 ==
932 20:14:34.874735 Dram Type= 6, Freq= 0, CH_0, rank 0
933 20:14:34.878414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 20:14:34.878514 ==
935 20:14:34.881632 RX Vref Scan: 0
936 20:14:34.881735
937 20:14:34.881866 RX Vref 0 -> 0, step: 1
938 20:14:34.881993
939 20:14:34.884898 RX Delay -130 -> 252, step: 16
940 20:14:34.888015 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
941 20:14:34.895107 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 20:14:34.898328 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
943 20:14:34.901464 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
944 20:14:34.904579 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 20:14:34.907809 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 20:14:34.914833 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
947 20:14:34.918215 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
948 20:14:34.921743 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
949 20:14:34.924640 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
950 20:14:34.928073 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
951 20:14:34.934757 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
952 20:14:34.938017 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
953 20:14:34.941715 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
954 20:14:34.944768 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 20:14:34.948387 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
956 20:14:34.951651 ==
957 20:14:34.951749 Dram Type= 6, Freq= 0, CH_0, rank 0
958 20:14:34.958189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 20:14:34.958303 ==
960 20:14:34.958399 DQS Delay:
961 20:14:34.961326 DQS0 = 0, DQS1 = 0
962 20:14:34.961427 DQM Delay:
963 20:14:34.964545 DQM0 = 93, DQM1 = 83
964 20:14:34.964658 DQ Delay:
965 20:14:34.968240 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 20:14:34.971301 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
967 20:14:34.974499 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
968 20:14:34.978179 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 20:14:34.978264
970 20:14:34.978331
971 20:14:34.978393 ==
972 20:14:34.981386 Dram Type= 6, Freq= 0, CH_0, rank 0
973 20:14:34.984917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 20:14:34.985016 ==
975 20:14:34.985084
976 20:14:34.985146
977 20:14:34.988039 TX Vref Scan disable
978 20:14:34.991231 == TX Byte 0 ==
979 20:14:34.994320 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
980 20:14:34.998136 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
981 20:14:35.001155 == TX Byte 1 ==
982 20:14:35.004766 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 20:14:35.007757 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 20:14:35.007872 ==
985 20:14:35.011319 Dram Type= 6, Freq= 0, CH_0, rank 0
986 20:14:35.014610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 20:14:35.017745 ==
988 20:14:35.029757 TX Vref=22, minBit 8, minWin=27, winSum=445
989 20:14:35.033471 TX Vref=24, minBit 9, minWin=27, winSum=452
990 20:14:35.036513 TX Vref=26, minBit 5, minWin=28, winSum=456
991 20:14:35.039704 TX Vref=28, minBit 8, minWin=28, winSum=458
992 20:14:35.043360 TX Vref=30, minBit 5, minWin=28, winSum=458
993 20:14:35.046489 TX Vref=32, minBit 10, minWin=27, winSum=452
994 20:14:35.053289 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
995 20:14:35.053422
996 20:14:35.056520 Final TX Range 1 Vref 28
997 20:14:35.056630
998 20:14:35.056740 ==
999 20:14:35.059722 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 20:14:35.063050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 20:14:35.063164 ==
1002 20:14:35.063264
1003 20:14:35.066223
1004 20:14:35.066331 TX Vref Scan disable
1005 20:14:35.070052 == TX Byte 0 ==
1006 20:14:35.073342 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1007 20:14:35.076459 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1008 20:14:35.080000 == TX Byte 1 ==
1009 20:14:35.083328 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 20:14:35.086444 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 20:14:35.089737
1012 20:14:35.089845 [DATLAT]
1013 20:14:35.089948 Freq=800, CH0 RK0
1014 20:14:35.090048
1015 20:14:35.092888 DATLAT Default: 0xa
1016 20:14:35.092972 0, 0xFFFF, sum = 0
1017 20:14:35.096103 1, 0xFFFF, sum = 0
1018 20:14:35.096223 2, 0xFFFF, sum = 0
1019 20:14:35.099900 3, 0xFFFF, sum = 0
1020 20:14:35.103093 4, 0xFFFF, sum = 0
1021 20:14:35.103224 5, 0xFFFF, sum = 0
1022 20:14:35.106305 6, 0xFFFF, sum = 0
1023 20:14:35.106395 7, 0xFFFF, sum = 0
1024 20:14:35.109578 8, 0xFFFF, sum = 0
1025 20:14:35.109671 9, 0x0, sum = 1
1026 20:14:35.109777 10, 0x0, sum = 2
1027 20:14:35.113028 11, 0x0, sum = 3
1028 20:14:35.113109 12, 0x0, sum = 4
1029 20:14:35.116475 best_step = 10
1030 20:14:35.116577
1031 20:14:35.116674 ==
1032 20:14:35.120008 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 20:14:35.123184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 20:14:35.123289 ==
1035 20:14:35.126491 RX Vref Scan: 1
1036 20:14:35.126593
1037 20:14:35.126684 Set Vref Range= 32 -> 127
1038 20:14:35.126775
1039 20:14:35.129741 RX Vref 32 -> 127, step: 1
1040 20:14:35.129841
1041 20:14:35.132954 RX Delay -95 -> 252, step: 8
1042 20:14:35.133030
1043 20:14:35.136746 Set Vref, RX VrefLevel [Byte0]: 32
1044 20:14:35.139694 [Byte1]: 32
1045 20:14:35.139798
1046 20:14:35.143500 Set Vref, RX VrefLevel [Byte0]: 33
1047 20:14:35.146732 [Byte1]: 33
1048 20:14:35.149906
1049 20:14:35.149989 Set Vref, RX VrefLevel [Byte0]: 34
1050 20:14:35.153292 [Byte1]: 34
1051 20:14:35.157774
1052 20:14:35.157883 Set Vref, RX VrefLevel [Byte0]: 35
1053 20:14:35.161175 [Byte1]: 35
1054 20:14:35.165109
1055 20:14:35.165199 Set Vref, RX VrefLevel [Byte0]: 36
1056 20:14:35.168664 [Byte1]: 36
1057 20:14:35.173443
1058 20:14:35.173528 Set Vref, RX VrefLevel [Byte0]: 37
1059 20:14:35.176908 [Byte1]: 37
1060 20:14:35.180769
1061 20:14:35.180851 Set Vref, RX VrefLevel [Byte0]: 38
1062 20:14:35.184643 [Byte1]: 38
1063 20:14:35.188783
1064 20:14:35.188866 Set Vref, RX VrefLevel [Byte0]: 39
1065 20:14:35.192262 [Byte1]: 39
1066 20:14:35.195841
1067 20:14:35.195946 Set Vref, RX VrefLevel [Byte0]: 40
1068 20:14:35.199645 [Byte1]: 40
1069 20:14:35.203928
1070 20:14:35.204035 Set Vref, RX VrefLevel [Byte0]: 41
1071 20:14:35.206953 [Byte1]: 41
1072 20:14:35.210808
1073 20:14:35.210915 Set Vref, RX VrefLevel [Byte0]: 42
1074 20:14:35.214551 [Byte1]: 42
1075 20:14:35.218966
1076 20:14:35.219069 Set Vref, RX VrefLevel [Byte0]: 43
1077 20:14:35.221913 [Byte1]: 43
1078 20:14:35.226231
1079 20:14:35.226334 Set Vref, RX VrefLevel [Byte0]: 44
1080 20:14:35.229593 [Byte1]: 44
1081 20:14:35.233599
1082 20:14:35.233702 Set Vref, RX VrefLevel [Byte0]: 45
1083 20:14:35.237315 [Byte1]: 45
1084 20:14:35.241669
1085 20:14:35.241744 Set Vref, RX VrefLevel [Byte0]: 46
1086 20:14:35.244757 [Byte1]: 46
1087 20:14:35.249129
1088 20:14:35.249204 Set Vref, RX VrefLevel [Byte0]: 47
1089 20:14:35.252379 [Byte1]: 47
1090 20:14:35.256230
1091 20:14:35.256333 Set Vref, RX VrefLevel [Byte0]: 48
1092 20:14:35.260095 [Byte1]: 48
1093 20:14:35.263934
1094 20:14:35.264041 Set Vref, RX VrefLevel [Byte0]: 49
1095 20:14:35.267765 [Byte1]: 49
1096 20:14:35.271952
1097 20:14:35.272029 Set Vref, RX VrefLevel [Byte0]: 50
1098 20:14:35.274986 [Byte1]: 50
1099 20:14:35.279412
1100 20:14:35.279496 Set Vref, RX VrefLevel [Byte0]: 51
1101 20:14:35.282484 [Byte1]: 51
1102 20:14:35.286900
1103 20:14:35.287005 Set Vref, RX VrefLevel [Byte0]: 52
1104 20:14:35.290088 [Byte1]: 52
1105 20:14:35.294740
1106 20:14:35.294854 Set Vref, RX VrefLevel [Byte0]: 53
1107 20:14:35.297976 [Byte1]: 53
1108 20:14:35.302098
1109 20:14:35.302246 Set Vref, RX VrefLevel [Byte0]: 54
1110 20:14:35.305508 [Byte1]: 54
1111 20:14:35.310163
1112 20:14:35.310283 Set Vref, RX VrefLevel [Byte0]: 55
1113 20:14:35.313220 [Byte1]: 55
1114 20:14:35.317307
1115 20:14:35.317392 Set Vref, RX VrefLevel [Byte0]: 56
1116 20:14:35.320540 [Byte1]: 56
1117 20:14:35.325081
1118 20:14:35.325189 Set Vref, RX VrefLevel [Byte0]: 57
1119 20:14:35.328140 [Byte1]: 57
1120 20:14:35.332414
1121 20:14:35.332525 Set Vref, RX VrefLevel [Byte0]: 58
1122 20:14:35.335974 [Byte1]: 58
1123 20:14:35.340063
1124 20:14:35.340166 Set Vref, RX VrefLevel [Byte0]: 59
1125 20:14:35.343839 [Byte1]: 59
1126 20:14:35.347691
1127 20:14:35.347782 Set Vref, RX VrefLevel [Byte0]: 60
1128 20:14:35.351213 [Byte1]: 60
1129 20:14:35.355093
1130 20:14:35.355198 Set Vref, RX VrefLevel [Byte0]: 61
1131 20:14:35.358879 [Byte1]: 61
1132 20:14:35.362836
1133 20:14:35.362926 Set Vref, RX VrefLevel [Byte0]: 62
1134 20:14:35.366065 [Byte1]: 62
1135 20:14:35.370388
1136 20:14:35.370489 Set Vref, RX VrefLevel [Byte0]: 63
1137 20:14:35.373631 [Byte1]: 63
1138 20:14:35.378087
1139 20:14:35.378188 Set Vref, RX VrefLevel [Byte0]: 64
1140 20:14:35.381519 [Byte1]: 64
1141 20:14:35.385783
1142 20:14:35.385859 Set Vref, RX VrefLevel [Byte0]: 65
1143 20:14:35.388830 [Byte1]: 65
1144 20:14:35.393195
1145 20:14:35.393283 Set Vref, RX VrefLevel [Byte0]: 66
1146 20:14:35.396972 [Byte1]: 66
1147 20:14:35.400823
1148 20:14:35.400898 Set Vref, RX VrefLevel [Byte0]: 67
1149 20:14:35.403931 [Byte1]: 67
1150 20:14:35.408904
1151 20:14:35.408992 Set Vref, RX VrefLevel [Byte0]: 68
1152 20:14:35.411642 [Byte1]: 68
1153 20:14:35.416194
1154 20:14:35.416309 Set Vref, RX VrefLevel [Byte0]: 69
1155 20:14:35.419235 [Byte1]: 69
1156 20:14:35.423752
1157 20:14:35.423866 Set Vref, RX VrefLevel [Byte0]: 70
1158 20:14:35.427310 [Byte1]: 70
1159 20:14:35.431596
1160 20:14:35.431693 Set Vref, RX VrefLevel [Byte0]: 71
1161 20:14:35.434636 [Byte1]: 71
1162 20:14:35.439141
1163 20:14:35.439233 Set Vref, RX VrefLevel [Byte0]: 72
1164 20:14:35.442042 [Byte1]: 72
1165 20:14:35.446648
1166 20:14:35.446753 Set Vref, RX VrefLevel [Byte0]: 73
1167 20:14:35.449663 [Byte1]: 73
1168 20:14:35.454272
1169 20:14:35.454361 Set Vref, RX VrefLevel [Byte0]: 74
1170 20:14:35.457812 [Byte1]: 74
1171 20:14:35.461501
1172 20:14:35.461604 Set Vref, RX VrefLevel [Byte0]: 75
1173 20:14:35.465283 [Byte1]: 75
1174 20:14:35.469552
1175 20:14:35.469653 Set Vref, RX VrefLevel [Byte0]: 76
1176 20:14:35.472679 [Byte1]: 76
1177 20:14:35.476953
1178 20:14:35.477039 Set Vref, RX VrefLevel [Byte0]: 77
1179 20:14:35.479999 [Byte1]: 77
1180 20:14:35.484247
1181 20:14:35.484355 Final RX Vref Byte 0 = 56 to rank0
1182 20:14:35.487635 Final RX Vref Byte 1 = 60 to rank0
1183 20:14:35.491319 Final RX Vref Byte 0 = 56 to rank1
1184 20:14:35.494480 Final RX Vref Byte 1 = 60 to rank1==
1185 20:14:35.498193 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 20:14:35.504539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 20:14:35.504617 ==
1188 20:14:35.504680 DQS Delay:
1189 20:14:35.504742 DQS0 = 0, DQS1 = 0
1190 20:14:35.507694 DQM Delay:
1191 20:14:35.507793 DQM0 = 91, DQM1 = 87
1192 20:14:35.511467 DQ Delay:
1193 20:14:35.514555 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1194 20:14:35.517749 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1195 20:14:35.520789 DQ8 =80, DQ9 =80, DQ10 =84, DQ11 =80
1196 20:14:35.524433 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1197 20:14:35.524509
1198 20:14:35.524574
1199 20:14:35.531352 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1200 20:14:35.534151 CH0 RK0: MR19=606, MR18=4A41
1201 20:14:35.541087 CH0_RK0: MR19=0x606, MR18=0x4A41, DQSOSC=391, MR23=63, INC=96, DEC=64
1202 20:14:35.541192
1203 20:14:35.544475 ----->DramcWriteLeveling(PI) begin...
1204 20:14:35.544547 ==
1205 20:14:35.547882 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 20:14:35.551108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 20:14:35.551206 ==
1208 20:14:35.554524 Write leveling (Byte 0): 32 => 32
1209 20:14:35.557794 Write leveling (Byte 1): 31 => 31
1210 20:14:35.561030 DramcWriteLeveling(PI) end<-----
1211 20:14:35.561109
1212 20:14:35.561173 ==
1213 20:14:35.564820 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 20:14:35.567766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 20:14:35.567856 ==
1216 20:14:35.570860 [Gating] SW mode calibration
1217 20:14:35.618307 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 20:14:35.618966 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 20:14:35.619244 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 20:14:35.619345 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 20:14:35.619449 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1222 20:14:35.619551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 20:14:35.619647 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 20:14:35.620246 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 20:14:35.620342 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 20:14:35.620586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 20:14:35.662313 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 20:14:35.662659 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 20:14:35.662763 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 20:14:35.662855 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 20:14:35.662951 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 20:14:35.663046 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 20:14:35.663148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 20:14:35.663236 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 20:14:35.663334 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 20:14:35.663422 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 20:14:35.690960 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1238 20:14:35.691520 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 20:14:35.691818 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 20:14:35.691889 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 20:14:35.691950 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 20:14:35.692255 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 20:14:35.695638 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 20:14:35.698739 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 20:14:35.701742 0 9 8 | B1->B0 | 3030 2a2a | 0 1 | (0 0) (1 1)
1246 20:14:35.705578 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 20:14:35.711914 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 20:14:35.715531 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 20:14:35.718829 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 20:14:35.725661 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 20:14:35.728793 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 20:14:35.731814 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1253 20:14:35.738641 0 10 8 | B1->B0 | 2c2c 2727 | 0 0 | (1 0) (0 0)
1254 20:14:35.742327 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 20:14:35.745453 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 20:14:35.749170 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 20:14:35.757356 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 20:14:35.761020 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 20:14:35.764850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 20:14:35.767943 0 11 4 | B1->B0 | 2727 2625 | 0 1 | (0 0) (0 0)
1261 20:14:35.770932 0 11 8 | B1->B0 | 3e3e 3c3c | 0 1 | (0 0) (0 0)
1262 20:14:35.777961 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 20:14:35.781618 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 20:14:35.785254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 20:14:35.791880 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 20:14:35.794869 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 20:14:35.798269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 20:14:35.804830 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 20:14:35.808547 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 20:14:35.811756 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 20:14:35.814965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 20:14:35.822094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 20:14:35.825180 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 20:14:35.828853 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 20:14:35.835188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 20:14:35.838306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 20:14:35.842063 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 20:14:35.848213 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 20:14:35.852014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 20:14:35.855285 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 20:14:35.861834 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 20:14:35.864939 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 20:14:35.868211 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 20:14:35.875506 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 20:14:35.878394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1286 20:14:35.881969 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 20:14:35.885297 Total UI for P1: 0, mck2ui 16
1288 20:14:35.888998 best dqsien dly found for B0: ( 0, 14, 10)
1289 20:14:35.891915 Total UI for P1: 0, mck2ui 16
1290 20:14:35.895309 best dqsien dly found for B1: ( 0, 14, 8)
1291 20:14:35.898461 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1292 20:14:35.902109 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 20:14:35.902203
1294 20:14:35.905154 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1295 20:14:35.908948 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 20:14:35.912058 [Gating] SW calibration Done
1297 20:14:35.912138 ==
1298 20:14:35.915121 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 20:14:35.922125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 20:14:35.922210 ==
1301 20:14:35.922274 RX Vref Scan: 0
1302 20:14:35.922335
1303 20:14:35.924947 RX Vref 0 -> 0, step: 1
1304 20:14:35.925041
1305 20:14:35.928489 RX Delay -130 -> 252, step: 16
1306 20:14:35.931654 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1307 20:14:35.935529 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1308 20:14:35.938607 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1309 20:14:35.941813 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1310 20:14:35.948875 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1311 20:14:35.951913 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1312 20:14:35.955018 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1313 20:14:35.958821 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1314 20:14:35.962014 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1315 20:14:35.968460 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1316 20:14:35.972064 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1317 20:14:35.975030 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1318 20:14:35.978402 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1319 20:14:35.981824 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1320 20:14:35.988912 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1321 20:14:35.991946 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1322 20:14:35.992056 ==
1323 20:14:35.994958 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 20:14:35.998399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 20:14:35.998486 ==
1326 20:14:36.001934 DQS Delay:
1327 20:14:36.002040 DQS0 = 0, DQS1 = 0
1328 20:14:36.002148 DQM Delay:
1329 20:14:36.005172 DQM0 = 96, DQM1 = 83
1330 20:14:36.005278 DQ Delay:
1331 20:14:36.008598 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1332 20:14:36.011817 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =109
1333 20:14:36.015441 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1334 20:14:36.018409 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1335 20:14:36.018491
1336 20:14:36.018555
1337 20:14:36.018615 ==
1338 20:14:36.021645 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 20:14:36.028660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 20:14:36.028742 ==
1341 20:14:36.028807
1342 20:14:36.028866
1343 20:14:36.028923 TX Vref Scan disable
1344 20:14:36.032386 == TX Byte 0 ==
1345 20:14:36.035452 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1346 20:14:36.039115 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1347 20:14:36.042172 == TX Byte 1 ==
1348 20:14:36.045255 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1349 20:14:36.048911 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1350 20:14:36.052558 ==
1351 20:14:36.055434 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 20:14:36.058894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 20:14:36.058977 ==
1354 20:14:36.071185 TX Vref=22, minBit 1, minWin=28, winSum=450
1355 20:14:36.074476 TX Vref=24, minBit 1, minWin=28, winSum=452
1356 20:14:36.078145 TX Vref=26, minBit 1, minWin=28, winSum=455
1357 20:14:36.081373 TX Vref=28, minBit 11, minWin=27, winSum=456
1358 20:14:36.084420 TX Vref=30, minBit 12, minWin=27, winSum=453
1359 20:14:36.091239 TX Vref=32, minBit 10, minWin=27, winSum=453
1360 20:14:36.094571 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 26
1361 20:14:36.094660
1362 20:14:36.098030 Final TX Range 1 Vref 26
1363 20:14:36.098109
1364 20:14:36.098173 ==
1365 20:14:36.101580 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 20:14:36.104624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 20:14:36.104729 ==
1368 20:14:36.108116
1369 20:14:36.108189
1370 20:14:36.108251 TX Vref Scan disable
1371 20:14:36.111550 == TX Byte 0 ==
1372 20:14:36.114804 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1373 20:14:36.121348 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1374 20:14:36.121431 == TX Byte 1 ==
1375 20:14:36.124797 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1376 20:14:36.128053 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1377 20:14:36.131647
1378 20:14:36.131735 [DATLAT]
1379 20:14:36.131828 Freq=800, CH0 RK1
1380 20:14:36.131916
1381 20:14:36.134872 DATLAT Default: 0xa
1382 20:14:36.134979 0, 0xFFFF, sum = 0
1383 20:14:36.138185 1, 0xFFFF, sum = 0
1384 20:14:36.138295 2, 0xFFFF, sum = 0
1385 20:14:36.141809 3, 0xFFFF, sum = 0
1386 20:14:36.141910 4, 0xFFFF, sum = 0
1387 20:14:36.144935 5, 0xFFFF, sum = 0
1388 20:14:36.147957 6, 0xFFFF, sum = 0
1389 20:14:36.148056 7, 0xFFFF, sum = 0
1390 20:14:36.151644 8, 0xFFFF, sum = 0
1391 20:14:36.151716 9, 0x0, sum = 1
1392 20:14:36.151777 10, 0x0, sum = 2
1393 20:14:36.154756 11, 0x0, sum = 3
1394 20:14:36.154828 12, 0x0, sum = 4
1395 20:14:36.157856 best_step = 10
1396 20:14:36.157932
1397 20:14:36.157990 ==
1398 20:14:36.161640 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 20:14:36.164613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 20:14:36.164685 ==
1401 20:14:36.168067 RX Vref Scan: 0
1402 20:14:36.168171
1403 20:14:36.168260 RX Vref 0 -> 0, step: 1
1404 20:14:36.168350
1405 20:14:36.171408 RX Delay -95 -> 252, step: 8
1406 20:14:36.178357 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1407 20:14:36.181451 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1408 20:14:36.184638 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1409 20:14:36.188096 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1410 20:14:36.191285 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1411 20:14:36.198589 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1412 20:14:36.201867 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1413 20:14:36.205188 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1414 20:14:36.208139 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1415 20:14:36.211585 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1416 20:14:36.218219 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1417 20:14:36.221401 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1418 20:14:36.224900 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1419 20:14:36.228542 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1420 20:14:36.231516 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1421 20:14:36.238311 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1422 20:14:36.238442 ==
1423 20:14:36.241255 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 20:14:36.245056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 20:14:36.245135 ==
1426 20:14:36.245199 DQS Delay:
1427 20:14:36.248455 DQS0 = 0, DQS1 = 0
1428 20:14:36.248562 DQM Delay:
1429 20:14:36.251783 DQM0 = 93, DQM1 = 83
1430 20:14:36.251881 DQ Delay:
1431 20:14:36.255070 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1432 20:14:36.258184 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1433 20:14:36.261469 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1434 20:14:36.264782 DQ12 =88, DQ13 =84, DQ14 =96, DQ15 =92
1435 20:14:36.264873
1436 20:14:36.264938
1437 20:14:36.271916 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1438 20:14:36.275052 CH0 RK1: MR19=606, MR18=4112
1439 20:14:36.281636 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1440 20:14:36.284988 [RxdqsGatingPostProcess] freq 800
1441 20:14:36.291858 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 20:14:36.294835 Pre-setting of DQS Precalculation
1443 20:14:36.298597 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 20:14:36.298681 ==
1445 20:14:36.301638 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 20:14:36.304886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 20:14:36.304969 ==
1448 20:14:36.311821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 20:14:36.318409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 20:14:36.326517 [CA 0] Center 36 (6~67) winsize 62
1451 20:14:36.330259 [CA 1] Center 36 (6~67) winsize 62
1452 20:14:36.333253 [CA 2] Center 34 (4~65) winsize 62
1453 20:14:36.336702 [CA 3] Center 34 (4~65) winsize 62
1454 20:14:36.340279 [CA 4] Center 34 (4~65) winsize 62
1455 20:14:36.343296 [CA 5] Center 34 (4~65) winsize 62
1456 20:14:36.343378
1457 20:14:36.346830 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 20:14:36.346917
1459 20:14:36.349937 [CATrainingPosCal] consider 1 rank data
1460 20:14:36.353176 u2DelayCellTimex100 = 270/100 ps
1461 20:14:36.356252 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 20:14:36.359905 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 20:14:36.366838 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 20:14:36.370040 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 20:14:36.373009 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 20:14:36.376737 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 20:14:36.376820
1468 20:14:36.379695 CA PerBit enable=1, Macro0, CA PI delay=34
1469 20:14:36.379778
1470 20:14:36.382938 [CBTSetCACLKResult] CA Dly = 34
1471 20:14:36.383021 CS Dly: 6 (0~37)
1472 20:14:36.386140 ==
1473 20:14:36.386223 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 20:14:36.393106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 20:14:36.393216 ==
1476 20:14:36.396689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 20:14:36.402978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 20:14:36.413018 [CA 0] Center 36 (6~67) winsize 62
1479 20:14:36.416761 [CA 1] Center 36 (6~67) winsize 62
1480 20:14:36.420590 [CA 2] Center 35 (4~66) winsize 63
1481 20:14:36.424157 [CA 3] Center 34 (4~65) winsize 62
1482 20:14:36.427885 [CA 4] Center 35 (5~66) winsize 62
1483 20:14:36.431503 [CA 5] Center 34 (4~65) winsize 62
1484 20:14:36.431583
1485 20:14:36.435030 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1486 20:14:36.435112
1487 20:14:36.439161 [CATrainingPosCal] consider 2 rank data
1488 20:14:36.439241 u2DelayCellTimex100 = 270/100 ps
1489 20:14:36.442910 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 20:14:36.447038 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 20:14:36.450186 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 20:14:36.453387 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 20:14:36.456806 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1494 20:14:36.463571 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 20:14:36.463648
1496 20:14:36.467028 CA PerBit enable=1, Macro0, CA PI delay=34
1497 20:14:36.467167
1498 20:14:36.470308 [CBTSetCACLKResult] CA Dly = 34
1499 20:14:36.470383 CS Dly: 6 (0~38)
1500 20:14:36.470444
1501 20:14:36.473315 ----->DramcWriteLeveling(PI) begin...
1502 20:14:36.473390 ==
1503 20:14:36.477118 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 20:14:36.480243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 20:14:36.483532 ==
1506 20:14:36.483620 Write leveling (Byte 0): 27 => 27
1507 20:14:36.486643 Write leveling (Byte 1): 28 => 28
1508 20:14:36.490425 DramcWriteLeveling(PI) end<-----
1509 20:14:36.490505
1510 20:14:36.490569 ==
1511 20:14:36.493448 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 20:14:36.500300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 20:14:36.500398 ==
1514 20:14:36.500462 [Gating] SW mode calibration
1515 20:14:36.510568 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 20:14:36.513513 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 20:14:36.516887 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1518 20:14:36.523547 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1519 20:14:36.526953 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 20:14:36.530675 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 20:14:36.537384 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 20:14:36.540426 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 20:14:36.543964 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 20:14:36.550622 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 20:14:36.553694 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 20:14:36.557350 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 20:14:36.563560 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 20:14:36.567215 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 20:14:36.570816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 20:14:36.577247 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 20:14:36.580728 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 20:14:36.583843 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 20:14:36.587043 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1534 20:14:36.594008 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1535 20:14:36.597735 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 20:14:36.600850 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 20:14:36.607594 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 20:14:36.610626 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 20:14:36.613871 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 20:14:36.620849 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 20:14:36.624215 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 20:14:36.627093 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1543 20:14:36.634084 0 9 8 | B1->B0 | 3030 3333 | 1 1 | (0 0) (1 1)
1544 20:14:36.637082 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 20:14:36.640825 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 20:14:36.647492 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 20:14:36.650752 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 20:14:36.653741 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 20:14:36.660405 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 20:14:36.663964 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1551 20:14:36.667543 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1552 20:14:36.670621 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 20:14:36.677257 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 20:14:36.680823 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 20:14:36.683970 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 20:14:36.690849 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 20:14:36.693936 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1558 20:14:36.697670 0 11 4 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (1 1)
1559 20:14:36.703964 0 11 8 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
1560 20:14:36.707155 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 20:14:36.710809 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 20:14:36.717752 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 20:14:36.720872 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 20:14:36.723954 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 20:14:36.730884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 20:14:36.733985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1567 20:14:36.737617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 20:14:36.743916 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 20:14:36.747130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 20:14:36.750727 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 20:14:36.753895 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 20:14:36.760537 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 20:14:36.763867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 20:14:36.767370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 20:14:36.774007 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 20:14:36.777420 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 20:14:36.780988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 20:14:36.787720 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 20:14:36.791225 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 20:14:36.794358 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 20:14:36.801186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 20:14:36.804408 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1583 20:14:36.807450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 20:14:36.810589 Total UI for P1: 0, mck2ui 16
1585 20:14:36.814251 best dqsien dly found for B0: ( 0, 14, 6)
1586 20:14:36.817729 Total UI for P1: 0, mck2ui 16
1587 20:14:36.820976 best dqsien dly found for B1: ( 0, 14, 4)
1588 20:14:36.824034 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1589 20:14:36.827750 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1590 20:14:36.827823
1591 20:14:36.830972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 20:14:36.837850 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 20:14:36.837926 [Gating] SW calibration Done
1594 20:14:36.837989 ==
1595 20:14:36.841009 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 20:14:36.847864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 20:14:36.847939 ==
1598 20:14:36.848001 RX Vref Scan: 0
1599 20:14:36.848059
1600 20:14:36.851064 RX Vref 0 -> 0, step: 1
1601 20:14:36.851177
1602 20:14:36.854188 RX Delay -130 -> 252, step: 16
1603 20:14:36.857698 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1604 20:14:36.861055 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1605 20:14:36.864430 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1606 20:14:36.870897 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1607 20:14:36.873934 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1608 20:14:36.877565 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1609 20:14:36.880551 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1610 20:14:36.884069 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1611 20:14:36.887511 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1612 20:14:36.894125 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1613 20:14:36.897484 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1614 20:14:36.900924 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1615 20:14:36.904048 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1616 20:14:36.911281 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1617 20:14:36.914196 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1618 20:14:36.917994 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1619 20:14:36.918067 ==
1620 20:14:36.920981 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 20:14:36.924562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 20:14:36.924633 ==
1623 20:14:36.927834 DQS Delay:
1624 20:14:36.927905 DQS0 = 0, DQS1 = 0
1625 20:14:36.927986 DQM Delay:
1626 20:14:36.930987 DQM0 = 93, DQM1 = 87
1627 20:14:36.931060 DQ Delay:
1628 20:14:36.934835 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1629 20:14:36.937937 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1630 20:14:36.941062 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1631 20:14:36.944236 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1632 20:14:36.944334
1633 20:14:36.944430
1634 20:14:36.944527 ==
1635 20:14:36.947944 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 20:14:36.954285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 20:14:36.954362 ==
1638 20:14:36.954443
1639 20:14:36.954522
1640 20:14:36.954599 TX Vref Scan disable
1641 20:14:36.958009 == TX Byte 0 ==
1642 20:14:36.961811 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 20:14:36.964905 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 20:14:36.968028 == TX Byte 1 ==
1645 20:14:36.971624 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1646 20:14:36.974856 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1647 20:14:36.977871 ==
1648 20:14:36.981538 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 20:14:36.984471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 20:14:36.984550 ==
1651 20:14:36.994558 TX Vref=22, minBit 1, minWin=26, winSum=438
1652 20:14:37.001498 TX Vref=24, minBit 1, minWin=27, winSum=444
1653 20:14:37.004556 TX Vref=26, minBit 1, minWin=27, winSum=445
1654 20:14:37.007694 TX Vref=28, minBit 2, minWin=27, winSum=449
1655 20:14:37.010998 TX Vref=30, minBit 1, minWin=27, winSum=451
1656 20:14:37.014623 TX Vref=32, minBit 0, minWin=27, winSum=449
1657 20:14:37.020990 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1658 20:14:37.021095
1659 20:14:37.024680 Final TX Range 1 Vref 30
1660 20:14:37.024761
1661 20:14:37.024824 ==
1662 20:14:37.027889 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 20:14:37.031241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 20:14:37.031330 ==
1665 20:14:37.031394
1666 20:14:37.031452
1667 20:14:37.034271 TX Vref Scan disable
1668 20:14:37.037934 == TX Byte 0 ==
1669 20:14:37.041438 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1670 20:14:37.044552 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1671 20:14:37.048264 == TX Byte 1 ==
1672 20:14:37.051388 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1673 20:14:37.054586 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1674 20:14:37.054666
1675 20:14:37.057547 [DATLAT]
1676 20:14:37.057627 Freq=800, CH1 RK0
1677 20:14:37.057734
1678 20:14:37.060971 DATLAT Default: 0xa
1679 20:14:37.061051 0, 0xFFFF, sum = 0
1680 20:14:37.064636 1, 0xFFFF, sum = 0
1681 20:14:37.064745 2, 0xFFFF, sum = 0
1682 20:14:37.067730 3, 0xFFFF, sum = 0
1683 20:14:37.067811 4, 0xFFFF, sum = 0
1684 20:14:37.071478 5, 0xFFFF, sum = 0
1685 20:14:37.071567 6, 0xFFFF, sum = 0
1686 20:14:37.074470 7, 0xFFFF, sum = 0
1687 20:14:37.074551 8, 0xFFFF, sum = 0
1688 20:14:37.077909 9, 0x0, sum = 1
1689 20:14:37.077990 10, 0x0, sum = 2
1690 20:14:37.081638 11, 0x0, sum = 3
1691 20:14:37.081719 12, 0x0, sum = 4
1692 20:14:37.081783 best_step = 10
1693 20:14:37.084886
1694 20:14:37.084966 ==
1695 20:14:37.087934 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 20:14:37.091067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 20:14:37.091152 ==
1698 20:14:37.091215 RX Vref Scan: 1
1699 20:14:37.091274
1700 20:14:37.094766 Set Vref Range= 32 -> 127
1701 20:14:37.094846
1702 20:14:37.097937 RX Vref 32 -> 127, step: 1
1703 20:14:37.098018
1704 20:14:37.101458 RX Delay -79 -> 252, step: 8
1705 20:14:37.101538
1706 20:14:37.104713 Set Vref, RX VrefLevel [Byte0]: 32
1707 20:14:37.108149 [Byte1]: 32
1708 20:14:37.108254
1709 20:14:37.111268 Set Vref, RX VrefLevel [Byte0]: 33
1710 20:14:37.114503 [Byte1]: 33
1711 20:14:37.114598
1712 20:14:37.117906 Set Vref, RX VrefLevel [Byte0]: 34
1713 20:14:37.120973 [Byte1]: 34
1714 20:14:37.124559
1715 20:14:37.124664 Set Vref, RX VrefLevel [Byte0]: 35
1716 20:14:37.127863 [Byte1]: 35
1717 20:14:37.132227
1718 20:14:37.132352 Set Vref, RX VrefLevel [Byte0]: 36
1719 20:14:37.136161 [Byte1]: 36
1720 20:14:37.139499
1721 20:14:37.139610 Set Vref, RX VrefLevel [Byte0]: 37
1722 20:14:37.143110 [Byte1]: 37
1723 20:14:37.147144
1724 20:14:37.147251 Set Vref, RX VrefLevel [Byte0]: 38
1725 20:14:37.150872 [Byte1]: 38
1726 20:14:37.154925
1727 20:14:37.155035 Set Vref, RX VrefLevel [Byte0]: 39
1728 20:14:37.157895 [Byte1]: 39
1729 20:14:37.162323
1730 20:14:37.162443 Set Vref, RX VrefLevel [Byte0]: 40
1731 20:14:37.165568 [Byte1]: 40
1732 20:14:37.170141
1733 20:14:37.170224 Set Vref, RX VrefLevel [Byte0]: 41
1734 20:14:37.173236 [Byte1]: 41
1735 20:14:37.177701
1736 20:14:37.177782 Set Vref, RX VrefLevel [Byte0]: 42
1737 20:14:37.180652 [Byte1]: 42
1738 20:14:37.184923
1739 20:14:37.185027 Set Vref, RX VrefLevel [Byte0]: 43
1740 20:14:37.188711 [Byte1]: 43
1741 20:14:37.192420
1742 20:14:37.192500 Set Vref, RX VrefLevel [Byte0]: 44
1743 20:14:37.196168 [Byte1]: 44
1744 20:14:37.200048
1745 20:14:37.200128 Set Vref, RX VrefLevel [Byte0]: 45
1746 20:14:37.203192 [Byte1]: 45
1747 20:14:37.207564
1748 20:14:37.207644 Set Vref, RX VrefLevel [Byte0]: 46
1749 20:14:37.210820 [Byte1]: 46
1750 20:14:37.215368
1751 20:14:37.215450 Set Vref, RX VrefLevel [Byte0]: 47
1752 20:14:37.218309 [Byte1]: 47
1753 20:14:37.223124
1754 20:14:37.223206 Set Vref, RX VrefLevel [Byte0]: 48
1755 20:14:37.226284 [Byte1]: 48
1756 20:14:37.230640
1757 20:14:37.230723 Set Vref, RX VrefLevel [Byte0]: 49
1758 20:14:37.233478 [Byte1]: 49
1759 20:14:37.237935
1760 20:14:37.238043 Set Vref, RX VrefLevel [Byte0]: 50
1761 20:14:37.244280 [Byte1]: 50
1762 20:14:37.244370
1763 20:14:37.247892 Set Vref, RX VrefLevel [Byte0]: 51
1764 20:14:37.251019 [Byte1]: 51
1765 20:14:37.251104
1766 20:14:37.254188 Set Vref, RX VrefLevel [Byte0]: 52
1767 20:14:37.257703 [Byte1]: 52
1768 20:14:37.257784
1769 20:14:37.261294 Set Vref, RX VrefLevel [Byte0]: 53
1770 20:14:37.264435 [Byte1]: 53
1771 20:14:37.268019
1772 20:14:37.268122 Set Vref, RX VrefLevel [Byte0]: 54
1773 20:14:37.271220 [Byte1]: 54
1774 20:14:37.275710
1775 20:14:37.275837 Set Vref, RX VrefLevel [Byte0]: 55
1776 20:14:37.278896 [Byte1]: 55
1777 20:14:37.283324
1778 20:14:37.283450 Set Vref, RX VrefLevel [Byte0]: 56
1779 20:14:37.286318 [Byte1]: 56
1780 20:14:37.290404
1781 20:14:37.290514 Set Vref, RX VrefLevel [Byte0]: 57
1782 20:14:37.294197 [Byte1]: 57
1783 20:14:37.298446
1784 20:14:37.298530 Set Vref, RX VrefLevel [Byte0]: 58
1785 20:14:37.301572 [Byte1]: 58
1786 20:14:37.306000
1787 20:14:37.306082 Set Vref, RX VrefLevel [Byte0]: 59
1788 20:14:37.309142 [Byte1]: 59
1789 20:14:37.313551
1790 20:14:37.313623 Set Vref, RX VrefLevel [Byte0]: 60
1791 20:14:37.316817 [Byte1]: 60
1792 20:14:37.321018
1793 20:14:37.321093 Set Vref, RX VrefLevel [Byte0]: 61
1794 20:14:37.324079 [Byte1]: 61
1795 20:14:37.328405
1796 20:14:37.328481 Set Vref, RX VrefLevel [Byte0]: 62
1797 20:14:37.331449 [Byte1]: 62
1798 20:14:37.335687
1799 20:14:37.335769 Set Vref, RX VrefLevel [Byte0]: 63
1800 20:14:37.339514 [Byte1]: 63
1801 20:14:37.343397
1802 20:14:37.343473 Set Vref, RX VrefLevel [Byte0]: 64
1803 20:14:37.346539 [Byte1]: 64
1804 20:14:37.351263
1805 20:14:37.351343 Set Vref, RX VrefLevel [Byte0]: 65
1806 20:14:37.354176 [Byte1]: 65
1807 20:14:37.358872
1808 20:14:37.358957 Set Vref, RX VrefLevel [Byte0]: 66
1809 20:14:37.361973 [Byte1]: 66
1810 20:14:37.366068
1811 20:14:37.366169 Set Vref, RX VrefLevel [Byte0]: 67
1812 20:14:37.369340 [Byte1]: 67
1813 20:14:37.373581
1814 20:14:37.373685 Set Vref, RX VrefLevel [Byte0]: 68
1815 20:14:37.376927 [Byte1]: 68
1816 20:14:37.381152
1817 20:14:37.381252 Set Vref, RX VrefLevel [Byte0]: 69
1818 20:14:37.384721 [Byte1]: 69
1819 20:14:37.388828
1820 20:14:37.388904 Set Vref, RX VrefLevel [Byte0]: 70
1821 20:14:37.392134 [Byte1]: 70
1822 20:14:37.396227
1823 20:14:37.396341 Set Vref, RX VrefLevel [Byte0]: 71
1824 20:14:37.399673 [Byte1]: 71
1825 20:14:37.404170
1826 20:14:37.404271 Set Vref, RX VrefLevel [Byte0]: 72
1827 20:14:37.407286 [Byte1]: 72
1828 20:14:37.411668
1829 20:14:37.411767 Set Vref, RX VrefLevel [Byte0]: 73
1830 20:14:37.414837 [Byte1]: 73
1831 20:14:37.418690
1832 20:14:37.418791 Final RX Vref Byte 0 = 56 to rank0
1833 20:14:37.422477 Final RX Vref Byte 1 = 56 to rank0
1834 20:14:37.425656 Final RX Vref Byte 0 = 56 to rank1
1835 20:14:37.428713 Final RX Vref Byte 1 = 56 to rank1==
1836 20:14:37.432225 Dram Type= 6, Freq= 0, CH_1, rank 0
1837 20:14:37.439160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 20:14:37.439264 ==
1839 20:14:37.439368 DQS Delay:
1840 20:14:37.439466 DQS0 = 0, DQS1 = 0
1841 20:14:37.442232 DQM Delay:
1842 20:14:37.442334 DQM0 = 95, DQM1 = 89
1843 20:14:37.445498 DQ Delay:
1844 20:14:37.448743 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1845 20:14:37.452458 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1846 20:14:37.452540 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1847 20:14:37.458664 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1848 20:14:37.458768
1849 20:14:37.458870
1850 20:14:37.465552 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1851 20:14:37.469048 CH1 RK0: MR19=606, MR18=2B47
1852 20:14:37.475820 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1853 20:14:37.475924
1854 20:14:37.478765 ----->DramcWriteLeveling(PI) begin...
1855 20:14:37.478867 ==
1856 20:14:37.482520 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 20:14:37.485364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 20:14:37.485440 ==
1859 20:14:37.488754 Write leveling (Byte 0): 26 => 26
1860 20:14:37.492458 Write leveling (Byte 1): 31 => 31
1861 20:14:37.495666 DramcWriteLeveling(PI) end<-----
1862 20:14:37.495771
1863 20:14:37.495873 ==
1864 20:14:37.498819 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 20:14:37.502346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 20:14:37.502449 ==
1867 20:14:37.505931 [Gating] SW mode calibration
1868 20:14:37.512159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1869 20:14:37.519043 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1870 20:14:37.522959 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1871 20:14:37.526106 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1872 20:14:37.532770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 20:14:37.535929 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 20:14:37.539102 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 20:14:37.545935 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 20:14:37.549044 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 20:14:37.552658 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 20:14:37.559022 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 20:14:37.562409 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 20:14:37.566293 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 20:14:37.569484 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 20:14:37.575610 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 20:14:37.578981 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 20:14:37.582565 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 20:14:37.589209 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 20:14:37.592755 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 20:14:37.595588 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1888 20:14:37.602823 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 20:14:37.606048 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 20:14:37.609126 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 20:14:37.615965 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 20:14:37.619095 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 20:14:37.622593 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 20:14:37.629170 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 20:14:37.632394 0 9 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1896 20:14:37.636187 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
1897 20:14:37.642760 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 20:14:37.645853 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 20:14:37.649384 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 20:14:37.656123 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 20:14:37.659095 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 20:14:37.662987 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (1 0) (1 1)
1903 20:14:37.666127 0 10 4 | B1->B0 | 2929 3030 | 0 0 | (0 0) (1 1)
1904 20:14:37.672946 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 20:14:37.676157 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 20:14:37.679211 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 20:14:37.686048 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 20:14:37.689464 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 20:14:37.692834 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 20:14:37.699240 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 20:14:37.702698 0 11 4 | B1->B0 | 3d3d 3030 | 0 0 | (0 0) (0 0)
1912 20:14:37.706295 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1913 20:14:37.713067 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 20:14:37.716176 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 20:14:37.719460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 20:14:37.725939 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 20:14:37.729762 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 20:14:37.732900 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 20:14:37.735963 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1920 20:14:37.743022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1921 20:14:37.746051 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 20:14:37.749558 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 20:14:37.756241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 20:14:37.759529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 20:14:37.762597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 20:14:37.769627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 20:14:37.772760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 20:14:37.776464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 20:14:37.782731 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 20:14:37.786443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 20:14:37.789498 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 20:14:37.796221 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 20:14:37.799777 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 20:14:37.803091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 20:14:37.809394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1936 20:14:37.812756 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 20:14:37.816459 Total UI for P1: 0, mck2ui 16
1938 20:14:37.819809 best dqsien dly found for B0: ( 0, 14, 4)
1939 20:14:37.822782 Total UI for P1: 0, mck2ui 16
1940 20:14:37.826511 best dqsien dly found for B1: ( 0, 14, 4)
1941 20:14:37.830060 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1942 20:14:37.833027 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1943 20:14:37.833132
1944 20:14:37.836096 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1945 20:14:37.839929 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1946 20:14:37.843141 [Gating] SW calibration Done
1947 20:14:37.843214 ==
1948 20:14:37.846275 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 20:14:37.849362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 20:14:37.849453 ==
1951 20:14:37.853135 RX Vref Scan: 0
1952 20:14:37.853279
1953 20:14:37.853358 RX Vref 0 -> 0, step: 1
1954 20:14:37.856169
1955 20:14:37.856249 RX Delay -130 -> 252, step: 16
1956 20:14:37.863168 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1957 20:14:37.866469 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1958 20:14:37.870120 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1959 20:14:37.873153 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1960 20:14:37.876650 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1961 20:14:37.879866 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1962 20:14:37.886670 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1963 20:14:37.889855 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1964 20:14:37.893100 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1965 20:14:37.896767 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1966 20:14:37.899954 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1967 20:14:37.906257 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1968 20:14:37.910159 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1969 20:14:37.913065 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1970 20:14:37.916582 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1971 20:14:37.920164 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1972 20:14:37.923480 ==
1973 20:14:37.926760 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 20:14:37.929993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 20:14:37.930085 ==
1976 20:14:37.930158 DQS Delay:
1977 20:14:37.933177 DQS0 = 0, DQS1 = 0
1978 20:14:37.933253 DQM Delay:
1979 20:14:37.936957 DQM0 = 92, DQM1 = 87
1980 20:14:37.937033 DQ Delay:
1981 20:14:37.939984 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1982 20:14:37.942924 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1983 20:14:37.946724 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1984 20:14:37.949893 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1985 20:14:37.949976
1986 20:14:37.950061
1987 20:14:37.950125 ==
1988 20:14:37.952980 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 20:14:37.956725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 20:14:37.956816 ==
1991 20:14:37.956882
1992 20:14:37.956943
1993 20:14:37.959846 TX Vref Scan disable
1994 20:14:37.963207 == TX Byte 0 ==
1995 20:14:37.966902 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1996 20:14:37.970082 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1997 20:14:37.973204 == TX Byte 1 ==
1998 20:14:37.976399 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1999 20:14:37.980187 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2000 20:14:37.980270 ==
2001 20:14:37.983204 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 20:14:37.987044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 20:14:37.990224 ==
2004 20:14:38.001431 TX Vref=22, minBit 0, minWin=27, winSum=439
2005 20:14:38.004976 TX Vref=24, minBit 0, minWin=27, winSum=439
2006 20:14:38.008061 TX Vref=26, minBit 2, minWin=27, winSum=447
2007 20:14:38.011471 TX Vref=28, minBit 2, minWin=27, winSum=451
2008 20:14:38.015261 TX Vref=30, minBit 2, minWin=27, winSum=449
2009 20:14:38.018317 TX Vref=32, minBit 0, minWin=27, winSum=447
2010 20:14:38.025101 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
2011 20:14:38.025227
2012 20:14:38.028337 Final TX Range 1 Vref 28
2013 20:14:38.028462
2014 20:14:38.028583 ==
2015 20:14:38.031771 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 20:14:38.035165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 20:14:38.035289 ==
2018 20:14:38.035411
2019 20:14:38.035524
2020 20:14:38.038543 TX Vref Scan disable
2021 20:14:38.041474 == TX Byte 0 ==
2022 20:14:38.044884 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2023 20:14:38.048198 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2024 20:14:38.051958 == TX Byte 1 ==
2025 20:14:38.055241 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2026 20:14:38.058170 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2027 20:14:38.058257
2028 20:14:38.062115 [DATLAT]
2029 20:14:38.062221 Freq=800, CH1 RK1
2030 20:14:38.062316
2031 20:14:38.065106 DATLAT Default: 0xa
2032 20:14:38.065183 0, 0xFFFF, sum = 0
2033 20:14:38.068240 1, 0xFFFF, sum = 0
2034 20:14:38.068347 2, 0xFFFF, sum = 0
2035 20:14:38.072034 3, 0xFFFF, sum = 0
2036 20:14:38.072119 4, 0xFFFF, sum = 0
2037 20:14:38.075148 5, 0xFFFF, sum = 0
2038 20:14:38.075227 6, 0xFFFF, sum = 0
2039 20:14:38.078317 7, 0xFFFF, sum = 0
2040 20:14:38.078396 8, 0xFFFF, sum = 0
2041 20:14:38.082004 9, 0x0, sum = 1
2042 20:14:38.082092 10, 0x0, sum = 2
2043 20:14:38.085157 11, 0x0, sum = 3
2044 20:14:38.085235 12, 0x0, sum = 4
2045 20:14:38.088321 best_step = 10
2046 20:14:38.088403
2047 20:14:38.088467 ==
2048 20:14:38.092102 Dram Type= 6, Freq= 0, CH_1, rank 1
2049 20:14:38.095145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2050 20:14:38.095221 ==
2051 20:14:38.098862 RX Vref Scan: 0
2052 20:14:38.098938
2053 20:14:38.099007 RX Vref 0 -> 0, step: 1
2054 20:14:38.099070
2055 20:14:38.102017 RX Delay -79 -> 252, step: 8
2056 20:14:38.108659 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2057 20:14:38.111598 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2058 20:14:38.115231 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2059 20:14:38.118549 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2060 20:14:38.121937 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2061 20:14:38.125330 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2062 20:14:38.131920 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2063 20:14:38.135117 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2064 20:14:38.138695 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2065 20:14:38.141654 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2066 20:14:38.145049 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2067 20:14:38.148722 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2068 20:14:38.155464 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2069 20:14:38.158492 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2070 20:14:38.161897 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2071 20:14:38.165062 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2072 20:14:38.165146 ==
2073 20:14:38.168406 Dram Type= 6, Freq= 0, CH_1, rank 1
2074 20:14:38.175318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2075 20:14:38.175404 ==
2076 20:14:38.175470 DQS Delay:
2077 20:14:38.175553 DQS0 = 0, DQS1 = 0
2078 20:14:38.178884 DQM Delay:
2079 20:14:38.178994 DQM0 = 97, DQM1 = 91
2080 20:14:38.181852 DQ Delay:
2081 20:14:38.184969 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2082 20:14:38.188695 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2083 20:14:38.191832 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2084 20:14:38.195529 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2085 20:14:38.195642
2086 20:14:38.195711
2087 20:14:38.201816 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2088 20:14:38.205690 CH1 RK1: MR19=606, MR18=440E
2089 20:14:38.211816 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2090 20:14:38.215426 [RxdqsGatingPostProcess] freq 800
2091 20:14:38.218548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2092 20:14:38.222224 Pre-setting of DQS Precalculation
2093 20:14:38.228368 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2094 20:14:38.235130 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2095 20:14:38.242207 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2096 20:14:38.242288
2097 20:14:38.242360
2098 20:14:38.245164 [Calibration Summary] 1600 Mbps
2099 20:14:38.245244 CH 0, Rank 0
2100 20:14:38.248846 SW Impedance : PASS
2101 20:14:38.252169 DUTY Scan : NO K
2102 20:14:38.252246 ZQ Calibration : PASS
2103 20:14:38.255101 Jitter Meter : NO K
2104 20:14:38.258737 CBT Training : PASS
2105 20:14:38.258820 Write leveling : PASS
2106 20:14:38.261861 RX DQS gating : PASS
2107 20:14:38.261947 RX DQ/DQS(RDDQC) : PASS
2108 20:14:38.265590 TX DQ/DQS : PASS
2109 20:14:38.268598 RX DATLAT : PASS
2110 20:14:38.268680 RX DQ/DQS(Engine): PASS
2111 20:14:38.272190 TX OE : NO K
2112 20:14:38.272274 All Pass.
2113 20:14:38.272348
2114 20:14:38.275591 CH 0, Rank 1
2115 20:14:38.275674 SW Impedance : PASS
2116 20:14:38.279043 DUTY Scan : NO K
2117 20:14:38.281821 ZQ Calibration : PASS
2118 20:14:38.281899 Jitter Meter : NO K
2119 20:14:38.285348 CBT Training : PASS
2120 20:14:38.288779 Write leveling : PASS
2121 20:14:38.288855 RX DQS gating : PASS
2122 20:14:38.291811 RX DQ/DQS(RDDQC) : PASS
2123 20:14:38.295535 TX DQ/DQS : PASS
2124 20:14:38.295615 RX DATLAT : PASS
2125 20:14:38.298790 RX DQ/DQS(Engine): PASS
2126 20:14:38.301844 TX OE : NO K
2127 20:14:38.301946 All Pass.
2128 20:14:38.302011
2129 20:14:38.302075 CH 1, Rank 0
2130 20:14:38.305483 SW Impedance : PASS
2131 20:14:38.308739 DUTY Scan : NO K
2132 20:14:38.308826 ZQ Calibration : PASS
2133 20:14:38.312313 Jitter Meter : NO K
2134 20:14:38.312391 CBT Training : PASS
2135 20:14:38.315266 Write leveling : PASS
2136 20:14:38.318761 RX DQS gating : PASS
2137 20:14:38.318843 RX DQ/DQS(RDDQC) : PASS
2138 20:14:38.321869 TX DQ/DQS : PASS
2139 20:14:38.325606 RX DATLAT : PASS
2140 20:14:38.325699 RX DQ/DQS(Engine): PASS
2141 20:14:38.328712 TX OE : NO K
2142 20:14:38.328795 All Pass.
2143 20:14:38.328866
2144 20:14:38.332502 CH 1, Rank 1
2145 20:14:38.332602 SW Impedance : PASS
2146 20:14:38.335530 DUTY Scan : NO K
2147 20:14:38.338785 ZQ Calibration : PASS
2148 20:14:38.338870 Jitter Meter : NO K
2149 20:14:38.341857 CBT Training : PASS
2150 20:14:38.345468 Write leveling : PASS
2151 20:14:38.345555 RX DQS gating : PASS
2152 20:14:38.348457 RX DQ/DQS(RDDQC) : PASS
2153 20:14:38.348542 TX DQ/DQS : PASS
2154 20:14:38.351803 RX DATLAT : PASS
2155 20:14:38.355555 RX DQ/DQS(Engine): PASS
2156 20:14:38.355658 TX OE : NO K
2157 20:14:38.358849 All Pass.
2158 20:14:38.358934
2159 20:14:38.359020 DramC Write-DBI off
2160 20:14:38.362092 PER_BANK_REFRESH: Hybrid Mode
2161 20:14:38.365192 TX_TRACKING: ON
2162 20:14:38.369111 [GetDramInforAfterCalByMRR] Vendor 6.
2163 20:14:38.372513 [GetDramInforAfterCalByMRR] Revision 606.
2164 20:14:38.375474 [GetDramInforAfterCalByMRR] Revision 2 0.
2165 20:14:38.375560 MR0 0x3b3b
2166 20:14:38.375646 MR8 0x5151
2167 20:14:38.382269 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 20:14:38.382382
2169 20:14:38.382476 MR0 0x3b3b
2170 20:14:38.382570 MR8 0x5151
2171 20:14:38.385368 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 20:14:38.385456
2173 20:14:38.395482 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2174 20:14:38.398994 [FAST_K] Save calibration result to emmc
2175 20:14:38.401875 [FAST_K] Save calibration result to emmc
2176 20:14:38.405557 dram_init: config_dvfs: 1
2177 20:14:38.408820 dramc_set_vcore_voltage set vcore to 662500
2178 20:14:38.412485 Read voltage for 1200, 2
2179 20:14:38.412566 Vio18 = 0
2180 20:14:38.412630 Vcore = 662500
2181 20:14:38.415565 Vdram = 0
2182 20:14:38.415646 Vddq = 0
2183 20:14:38.415710 Vmddr = 0
2184 20:14:38.422372 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2185 20:14:38.425355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2186 20:14:38.428794 MEM_TYPE=3, freq_sel=15
2187 20:14:38.432446 sv_algorithm_assistance_LP4_1600
2188 20:14:38.435576 ============ PULL DRAM RESETB DOWN ============
2189 20:14:38.438676 ========== PULL DRAM RESETB DOWN end =========
2190 20:14:38.445536 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2191 20:14:38.449209 ===================================
2192 20:14:38.449325 LPDDR4 DRAM CONFIGURATION
2193 20:14:38.452421 ===================================
2194 20:14:38.455566 EX_ROW_EN[0] = 0x0
2195 20:14:38.459247 EX_ROW_EN[1] = 0x0
2196 20:14:38.459333 LP4Y_EN = 0x0
2197 20:14:38.462410 WORK_FSP = 0x0
2198 20:14:38.462485 WL = 0x4
2199 20:14:38.466061 RL = 0x4
2200 20:14:38.466174 BL = 0x2
2201 20:14:38.468847 RPST = 0x0
2202 20:14:38.468929 RD_PRE = 0x0
2203 20:14:38.472178 WR_PRE = 0x1
2204 20:14:38.472260 WR_PST = 0x0
2205 20:14:38.475852 DBI_WR = 0x0
2206 20:14:38.475933 DBI_RD = 0x0
2207 20:14:38.478891 OTF = 0x1
2208 20:14:38.482297 ===================================
2209 20:14:38.486002 ===================================
2210 20:14:38.486085 ANA top config
2211 20:14:38.489087 ===================================
2212 20:14:38.492509 DLL_ASYNC_EN = 0
2213 20:14:38.496196 ALL_SLAVE_EN = 0
2214 20:14:38.496310 NEW_RANK_MODE = 1
2215 20:14:38.499393 DLL_IDLE_MODE = 1
2216 20:14:38.502341 LP45_APHY_COMB_EN = 1
2217 20:14:38.505816 TX_ODT_DIS = 1
2218 20:14:38.509079 NEW_8X_MODE = 1
2219 20:14:38.509163 ===================================
2220 20:14:38.512380 ===================================
2221 20:14:38.516035 data_rate = 2400
2222 20:14:38.519100 CKR = 1
2223 20:14:38.522934 DQ_P2S_RATIO = 8
2224 20:14:38.526192 ===================================
2225 20:14:38.529280 CA_P2S_RATIO = 8
2226 20:14:38.532662 DQ_CA_OPEN = 0
2227 20:14:38.535652 DQ_SEMI_OPEN = 0
2228 20:14:38.535744 CA_SEMI_OPEN = 0
2229 20:14:38.539378 CA_FULL_RATE = 0
2230 20:14:38.542480 DQ_CKDIV4_EN = 0
2231 20:14:38.546087 CA_CKDIV4_EN = 0
2232 20:14:38.549267 CA_PREDIV_EN = 0
2233 20:14:38.549352 PH8_DLY = 17
2234 20:14:38.552489 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2235 20:14:38.555662 DQ_AAMCK_DIV = 4
2236 20:14:38.558849 CA_AAMCK_DIV = 4
2237 20:14:38.562532 CA_ADMCK_DIV = 4
2238 20:14:38.565568 DQ_TRACK_CA_EN = 0
2239 20:14:38.569370 CA_PICK = 1200
2240 20:14:38.569480 CA_MCKIO = 1200
2241 20:14:38.572513 MCKIO_SEMI = 0
2242 20:14:38.575597 PLL_FREQ = 2366
2243 20:14:38.579457 DQ_UI_PI_RATIO = 32
2244 20:14:38.582339 CA_UI_PI_RATIO = 0
2245 20:14:38.585987 ===================================
2246 20:14:38.589225 ===================================
2247 20:14:38.592200 memory_type:LPDDR4
2248 20:14:38.592282 GP_NUM : 10
2249 20:14:38.595688 SRAM_EN : 1
2250 20:14:38.595832 MD32_EN : 0
2251 20:14:38.599148 ===================================
2252 20:14:38.602399 [ANA_INIT] >>>>>>>>>>>>>>
2253 20:14:38.606135 <<<<<< [CONFIGURE PHASE]: ANA_TX
2254 20:14:38.609532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2255 20:14:38.612877 ===================================
2256 20:14:38.615701 data_rate = 2400,PCW = 0X5b00
2257 20:14:38.619051 ===================================
2258 20:14:38.622797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2259 20:14:38.625892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 20:14:38.632471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 20:14:38.636137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2262 20:14:38.639359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2263 20:14:38.642909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2264 20:14:38.646326 [ANA_INIT] flow start
2265 20:14:38.649295 [ANA_INIT] PLL >>>>>>>>
2266 20:14:38.649425 [ANA_INIT] PLL <<<<<<<<
2267 20:14:38.653014 [ANA_INIT] MIDPI >>>>>>>>
2268 20:14:38.656159 [ANA_INIT] MIDPI <<<<<<<<
2269 20:14:38.659460 [ANA_INIT] DLL >>>>>>>>
2270 20:14:38.659594 [ANA_INIT] DLL <<<<<<<<
2271 20:14:38.663166 [ANA_INIT] flow end
2272 20:14:38.666095 ============ LP4 DIFF to SE enter ============
2273 20:14:38.669644 ============ LP4 DIFF to SE exit ============
2274 20:14:38.672722 [ANA_INIT] <<<<<<<<<<<<<
2275 20:14:38.675898 [Flow] Enable top DCM control >>>>>
2276 20:14:38.679749 [Flow] Enable top DCM control <<<<<
2277 20:14:38.682824 Enable DLL master slave shuffle
2278 20:14:38.686083 ==============================================================
2279 20:14:38.689741 Gating Mode config
2280 20:14:38.696415 ==============================================================
2281 20:14:38.696543 Config description:
2282 20:14:38.706262 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2283 20:14:38.713109 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2284 20:14:38.716546 SELPH_MODE 0: By rank 1: By Phase
2285 20:14:38.723100 ==============================================================
2286 20:14:38.726934 GAT_TRACK_EN = 1
2287 20:14:38.729971 RX_GATING_MODE = 2
2288 20:14:38.733280 RX_GATING_TRACK_MODE = 2
2289 20:14:38.736673 SELPH_MODE = 1
2290 20:14:38.739784 PICG_EARLY_EN = 1
2291 20:14:38.739870 VALID_LAT_VALUE = 1
2292 20:14:38.746486 ==============================================================
2293 20:14:38.749875 Enter into Gating configuration >>>>
2294 20:14:38.752939 Exit from Gating configuration <<<<
2295 20:14:38.756390 Enter into DVFS_PRE_config >>>>>
2296 20:14:38.766655 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2297 20:14:38.769849 Exit from DVFS_PRE_config <<<<<
2298 20:14:38.772979 Enter into PICG configuration >>>>
2299 20:14:38.776727 Exit from PICG configuration <<<<
2300 20:14:38.780041 [RX_INPUT] configuration >>>>>
2301 20:14:38.783318 [RX_INPUT] configuration <<<<<
2302 20:14:38.789764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2303 20:14:38.792947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2304 20:14:38.799820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 20:14:38.806249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 20:14:38.813066 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 20:14:38.819374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 20:14:38.823160 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2309 20:14:38.826181 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2310 20:14:38.829680 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2311 20:14:38.833017 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2312 20:14:38.840148 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2313 20:14:38.843290 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2314 20:14:38.846432 ===================================
2315 20:14:38.849973 LPDDR4 DRAM CONFIGURATION
2316 20:14:38.853412 ===================================
2317 20:14:38.853541 EX_ROW_EN[0] = 0x0
2318 20:14:38.856514 EX_ROW_EN[1] = 0x0
2319 20:14:38.856638 LP4Y_EN = 0x0
2320 20:14:38.859733 WORK_FSP = 0x0
2321 20:14:38.859858 WL = 0x4
2322 20:14:38.863298 RL = 0x4
2323 20:14:38.863423 BL = 0x2
2324 20:14:38.866586 RPST = 0x0
2325 20:14:38.866709 RD_PRE = 0x0
2326 20:14:38.869849 WR_PRE = 0x1
2327 20:14:38.872932 WR_PST = 0x0
2328 20:14:38.873057 DBI_WR = 0x0
2329 20:14:38.876383 DBI_RD = 0x0
2330 20:14:38.876507 OTF = 0x1
2331 20:14:38.880040 ===================================
2332 20:14:38.883257 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2333 20:14:38.886432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2334 20:14:38.893249 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2335 20:14:38.896653 ===================================
2336 20:14:38.899808 LPDDR4 DRAM CONFIGURATION
2337 20:14:38.899912 ===================================
2338 20:14:38.903496 EX_ROW_EN[0] = 0x10
2339 20:14:38.906759 EX_ROW_EN[1] = 0x0
2340 20:14:38.906882 LP4Y_EN = 0x0
2341 20:14:38.910024 WORK_FSP = 0x0
2342 20:14:38.910131 WL = 0x4
2343 20:14:38.913316 RL = 0x4
2344 20:14:38.913423 BL = 0x2
2345 20:14:38.916401 RPST = 0x0
2346 20:14:38.916499 RD_PRE = 0x0
2347 20:14:38.919590 WR_PRE = 0x1
2348 20:14:38.919687 WR_PST = 0x0
2349 20:14:38.923355 DBI_WR = 0x0
2350 20:14:38.923462 DBI_RD = 0x0
2351 20:14:38.926500 OTF = 0x1
2352 20:14:38.929767 ===================================
2353 20:14:38.936432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2354 20:14:38.936553 ==
2355 20:14:38.939579 Dram Type= 6, Freq= 0, CH_0, rank 0
2356 20:14:38.942775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 20:14:38.942900 ==
2358 20:14:38.946627 [Duty_Offset_Calibration]
2359 20:14:38.946755 B0:2 B1:1 CA:1
2360 20:14:38.946871
2361 20:14:38.949879 [DutyScan_Calibration_Flow] k_type=0
2362 20:14:38.960065
2363 20:14:38.960199 ==CLK 0==
2364 20:14:38.963521 Final CLK duty delay cell = 0
2365 20:14:38.967115 [0] MAX Duty = 5218%(X100), DQS PI = 24
2366 20:14:38.970003 [0] MIN Duty = 4875%(X100), DQS PI = 0
2367 20:14:38.970129 [0] AVG Duty = 5046%(X100)
2368 20:14:38.970245
2369 20:14:38.973631 CH0 CLK Duty spec in!! Max-Min= 343%
2370 20:14:38.980217 [DutyScan_Calibration_Flow] ====Done====
2371 20:14:38.980354
2372 20:14:38.983554 [DutyScan_Calibration_Flow] k_type=1
2373 20:14:38.998574
2374 20:14:38.998710 ==DQS 0 ==
2375 20:14:39.001751 Final DQS duty delay cell = -4
2376 20:14:39.005707 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2377 20:14:39.008897 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2378 20:14:39.011982 [-4] AVG Duty = 4937%(X100)
2379 20:14:39.012106
2380 20:14:39.012219 ==DQS 1 ==
2381 20:14:39.015772 Final DQS duty delay cell = 0
2382 20:14:39.019013 [0] MAX Duty = 5156%(X100), DQS PI = 62
2383 20:14:39.022124 [0] MIN Duty = 5000%(X100), DQS PI = 32
2384 20:14:39.025345 [0] AVG Duty = 5078%(X100)
2385 20:14:39.025465
2386 20:14:39.028961 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2387 20:14:39.029084
2388 20:14:39.031887 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2389 20:14:39.035676 [DutyScan_Calibration_Flow] ====Done====
2390 20:14:39.035797
2391 20:14:39.038716 [DutyScan_Calibration_Flow] k_type=3
2392 20:14:39.055708
2393 20:14:39.055830 ==DQM 0 ==
2394 20:14:39.059290 Final DQM duty delay cell = 0
2395 20:14:39.062289 [0] MAX Duty = 5156%(X100), DQS PI = 30
2396 20:14:39.065419 [0] MIN Duty = 4875%(X100), DQS PI = 58
2397 20:14:39.069145 [0] AVG Duty = 5015%(X100)
2398 20:14:39.069273
2399 20:14:39.069386 ==DQM 1 ==
2400 20:14:39.072219 Final DQM duty delay cell = 0
2401 20:14:39.075797 [0] MAX Duty = 5125%(X100), DQS PI = 60
2402 20:14:39.079020 [0] MIN Duty = 5031%(X100), DQS PI = 14
2403 20:14:39.082306 [0] AVG Duty = 5078%(X100)
2404 20:14:39.082427
2405 20:14:39.085949 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2406 20:14:39.086073
2407 20:14:39.089093 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2408 20:14:39.092202 [DutyScan_Calibration_Flow] ====Done====
2409 20:14:39.092325
2410 20:14:39.095534 [DutyScan_Calibration_Flow] k_type=2
2411 20:14:39.112192
2412 20:14:39.112331 ==DQ 0 ==
2413 20:14:39.115158 Final DQ duty delay cell = 0
2414 20:14:39.118781 [0] MAX Duty = 5062%(X100), DQS PI = 32
2415 20:14:39.121883 [0] MIN Duty = 4875%(X100), DQS PI = 0
2416 20:14:39.121964 [0] AVG Duty = 4968%(X100)
2417 20:14:39.122030
2418 20:14:39.125756 ==DQ 1 ==
2419 20:14:39.128955 Final DQ duty delay cell = 0
2420 20:14:39.132083 [0] MAX Duty = 5093%(X100), DQS PI = 24
2421 20:14:39.135302 [0] MIN Duty = 4938%(X100), DQS PI = 36
2422 20:14:39.135386 [0] AVG Duty = 5015%(X100)
2423 20:14:39.135451
2424 20:14:39.138488 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2425 20:14:39.138592
2426 20:14:39.142222 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2427 20:14:39.149181 [DutyScan_Calibration_Flow] ====Done====
2428 20:14:39.149291 ==
2429 20:14:39.152035 Dram Type= 6, Freq= 0, CH_1, rank 0
2430 20:14:39.155371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2431 20:14:39.155498 ==
2432 20:14:39.159073 [Duty_Offset_Calibration]
2433 20:14:39.159179 B0:1 B1:0 CA:0
2434 20:14:39.159274
2435 20:14:39.161737 [DutyScan_Calibration_Flow] k_type=0
2436 20:14:39.171193
2437 20:14:39.171322 ==CLK 0==
2438 20:14:39.174424 Final CLK duty delay cell = -4
2439 20:14:39.177966 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2440 20:14:39.181025 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2441 20:14:39.184840 [-4] AVG Duty = 4953%(X100)
2442 20:14:39.184921
2443 20:14:39.188088 CH1 CLK Duty spec in!! Max-Min= 156%
2444 20:14:39.191115 [DutyScan_Calibration_Flow] ====Done====
2445 20:14:39.191236
2446 20:14:39.194920 [DutyScan_Calibration_Flow] k_type=1
2447 20:14:39.211046
2448 20:14:39.211158 ==DQS 0 ==
2449 20:14:39.214087 Final DQS duty delay cell = 0
2450 20:14:39.217544 [0] MAX Duty = 5094%(X100), DQS PI = 24
2451 20:14:39.220982 [0] MIN Duty = 4875%(X100), DQS PI = 0
2452 20:14:39.221061 [0] AVG Duty = 4984%(X100)
2453 20:14:39.224028
2454 20:14:39.224109 ==DQS 1 ==
2455 20:14:39.227683 Final DQS duty delay cell = 0
2456 20:14:39.230730 [0] MAX Duty = 5187%(X100), DQS PI = 20
2457 20:14:39.234335 [0] MIN Duty = 4969%(X100), DQS PI = 8
2458 20:14:39.234450 [0] AVG Duty = 5078%(X100)
2459 20:14:39.237622
2460 20:14:39.240749 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2461 20:14:39.240839
2462 20:14:39.244492 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2463 20:14:39.247653 [DutyScan_Calibration_Flow] ====Done====
2464 20:14:39.247738
2465 20:14:39.250886 [DutyScan_Calibration_Flow] k_type=3
2466 20:14:39.267635
2467 20:14:39.267720 ==DQM 0 ==
2468 20:14:39.270725 Final DQM duty delay cell = 0
2469 20:14:39.274538 [0] MAX Duty = 5187%(X100), DQS PI = 10
2470 20:14:39.277673 [0] MIN Duty = 5031%(X100), DQS PI = 46
2471 20:14:39.277748 [0] AVG Duty = 5109%(X100)
2472 20:14:39.280714
2473 20:14:39.280797 ==DQM 1 ==
2474 20:14:39.284217 Final DQM duty delay cell = 0
2475 20:14:39.287669 [0] MAX Duty = 5031%(X100), DQS PI = 26
2476 20:14:39.290966 [0] MIN Duty = 4907%(X100), DQS PI = 36
2477 20:14:39.291072 [0] AVG Duty = 4969%(X100)
2478 20:14:39.294649
2479 20:14:39.297499 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2480 20:14:39.297585
2481 20:14:39.301289 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2482 20:14:39.304308 [DutyScan_Calibration_Flow] ====Done====
2483 20:14:39.304393
2484 20:14:39.307385 [DutyScan_Calibration_Flow] k_type=2
2485 20:14:39.323273
2486 20:14:39.323416 ==DQ 0 ==
2487 20:14:39.326812 Final DQ duty delay cell = -4
2488 20:14:39.329949 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2489 20:14:39.333617 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2490 20:14:39.336516 [-4] AVG Duty = 4984%(X100)
2491 20:14:39.336599
2492 20:14:39.336666 ==DQ 1 ==
2493 20:14:39.340047 Final DQ duty delay cell = 0
2494 20:14:39.343320 [0] MAX Duty = 5125%(X100), DQS PI = 20
2495 20:14:39.346976 [0] MIN Duty = 4969%(X100), DQS PI = 10
2496 20:14:39.347059 [0] AVG Duty = 5047%(X100)
2497 20:14:39.347124
2498 20:14:39.353464 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2499 20:14:39.353547
2500 20:14:39.356665 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2501 20:14:39.360314 [DutyScan_Calibration_Flow] ====Done====
2502 20:14:39.363376 nWR fixed to 30
2503 20:14:39.363466 [ModeRegInit_LP4] CH0 RK0
2504 20:14:39.367057 [ModeRegInit_LP4] CH0 RK1
2505 20:14:39.370361 [ModeRegInit_LP4] CH1 RK0
2506 20:14:39.370451 [ModeRegInit_LP4] CH1 RK1
2507 20:14:39.373701 match AC timing 7
2508 20:14:39.376778 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2509 20:14:39.380569 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2510 20:14:39.387039 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2511 20:14:39.390019 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2512 20:14:39.396876 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2513 20:14:39.396963 ==
2514 20:14:39.400147 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 20:14:39.403763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 20:14:39.403840 ==
2517 20:14:39.410238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2518 20:14:39.413586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2519 20:14:39.423899 [CA 0] Center 39 (8~70) winsize 63
2520 20:14:39.426951 [CA 1] Center 39 (8~70) winsize 63
2521 20:14:39.430524 [CA 2] Center 35 (5~66) winsize 62
2522 20:14:39.433553 [CA 3] Center 34 (4~65) winsize 62
2523 20:14:39.436619 [CA 4] Center 33 (3~64) winsize 62
2524 20:14:39.440547 [CA 5] Center 32 (3~62) winsize 60
2525 20:14:39.440648
2526 20:14:39.443827 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2527 20:14:39.443927
2528 20:14:39.446860 [CATrainingPosCal] consider 1 rank data
2529 20:14:39.450591 u2DelayCellTimex100 = 270/100 ps
2530 20:14:39.453395 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2531 20:14:39.457053 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2532 20:14:39.463801 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2533 20:14:39.466997 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2534 20:14:39.470106 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2535 20:14:39.473768 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2536 20:14:39.473901
2537 20:14:39.476810 CA PerBit enable=1, Macro0, CA PI delay=32
2538 20:14:39.476934
2539 20:14:39.480600 [CBTSetCACLKResult] CA Dly = 32
2540 20:14:39.480728 CS Dly: 6 (0~37)
2541 20:14:39.480839 ==
2542 20:14:39.483649 Dram Type= 6, Freq= 0, CH_0, rank 1
2543 20:14:39.490213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2544 20:14:39.490346 ==
2545 20:14:39.493636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2546 20:14:39.500307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2547 20:14:39.509204 [CA 0] Center 38 (8~69) winsize 62
2548 20:14:39.512762 [CA 1] Center 38 (8~69) winsize 62
2549 20:14:39.515955 [CA 2] Center 35 (5~66) winsize 62
2550 20:14:39.519156 [CA 3] Center 34 (4~65) winsize 62
2551 20:14:39.523011 [CA 4] Center 33 (3~64) winsize 62
2552 20:14:39.526386 [CA 5] Center 32 (3~62) winsize 60
2553 20:14:39.526490
2554 20:14:39.529460 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2555 20:14:39.529564
2556 20:14:39.532534 [CATrainingPosCal] consider 2 rank data
2557 20:14:39.536166 u2DelayCellTimex100 = 270/100 ps
2558 20:14:39.539228 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2559 20:14:39.542668 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2560 20:14:39.549627 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2561 20:14:39.552895 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2562 20:14:39.556115 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2563 20:14:39.559805 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2564 20:14:39.559919
2565 20:14:39.562821 CA PerBit enable=1, Macro0, CA PI delay=32
2566 20:14:39.562901
2567 20:14:39.566031 [CBTSetCACLKResult] CA Dly = 32
2568 20:14:39.566133 CS Dly: 6 (0~38)
2569 20:14:39.566234
2570 20:14:39.569782 ----->DramcWriteLeveling(PI) begin...
2571 20:14:39.569893 ==
2572 20:14:39.572839 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 20:14:39.579643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 20:14:39.579728 ==
2575 20:14:39.582712 Write leveling (Byte 0): 31 => 31
2576 20:14:39.586166 Write leveling (Byte 1): 30 => 30
2577 20:14:39.586275 DramcWriteLeveling(PI) end<-----
2578 20:14:39.589539
2579 20:14:39.589622 ==
2580 20:14:39.592660 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 20:14:39.596330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 20:14:39.596415 ==
2583 20:14:39.599694 [Gating] SW mode calibration
2584 20:14:39.606535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2585 20:14:39.609857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2586 20:14:39.616597 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2587 20:14:39.619738 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2588 20:14:39.623234 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 20:14:39.629707 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 20:14:39.633555 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 20:14:39.636746 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 20:14:39.639886 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2593 20:14:39.646525 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2594 20:14:39.649973 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2595 20:14:39.653254 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 20:14:39.659741 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 20:14:39.662935 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 20:14:39.666720 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 20:14:39.673098 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 20:14:39.677074 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2601 20:14:39.680157 1 0 28 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
2602 20:14:39.686387 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2603 20:14:39.690045 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 20:14:39.693067 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 20:14:39.700116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 20:14:39.703625 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 20:14:39.707078 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 20:14:39.713437 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 20:14:39.716344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2610 20:14:39.720037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2611 20:14:39.726503 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 20:14:39.730159 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 20:14:39.733201 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 20:14:39.740276 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 20:14:39.743451 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 20:14:39.746557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 20:14:39.749758 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 20:14:39.756985 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 20:14:39.760073 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 20:14:39.763280 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 20:14:39.769849 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 20:14:39.773407 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 20:14:39.776789 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 20:14:39.783785 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 20:14:39.787027 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2626 20:14:39.790268 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2627 20:14:39.793616 Total UI for P1: 0, mck2ui 16
2628 20:14:39.797114 best dqsien dly found for B0: ( 1, 3, 28)
2629 20:14:39.800172 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 20:14:39.803832 Total UI for P1: 0, mck2ui 16
2631 20:14:39.807036 best dqsien dly found for B1: ( 1, 4, 0)
2632 20:14:39.810147 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2633 20:14:39.816816 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2634 20:14:39.816921
2635 20:14:39.820369 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2636 20:14:39.823704 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2637 20:14:39.826773 [Gating] SW calibration Done
2638 20:14:39.826857 ==
2639 20:14:39.830297 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 20:14:39.833960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 20:14:39.834043 ==
2642 20:14:39.834109 RX Vref Scan: 0
2643 20:14:39.836828
2644 20:14:39.836910 RX Vref 0 -> 0, step: 1
2645 20:14:39.836977
2646 20:14:39.840412 RX Delay -40 -> 252, step: 8
2647 20:14:39.844008 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2648 20:14:39.847176 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2649 20:14:39.853556 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2650 20:14:39.856807 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2651 20:14:39.860578 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2652 20:14:39.863623 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2653 20:14:39.866904 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2654 20:14:39.873443 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2655 20:14:39.877352 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2656 20:14:39.880172 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2657 20:14:39.883890 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2658 20:14:39.887203 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2659 20:14:39.893522 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2660 20:14:39.897350 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2661 20:14:39.900294 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2662 20:14:39.903402 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2663 20:14:39.903485 ==
2664 20:14:39.906897 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 20:14:39.910475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 20:14:39.913689 ==
2667 20:14:39.913773 DQS Delay:
2668 20:14:39.913840 DQS0 = 0, DQS1 = 0
2669 20:14:39.916883 DQM Delay:
2670 20:14:39.916960 DQM0 = 121, DQM1 = 113
2671 20:14:39.920580 DQ Delay:
2672 20:14:39.923674 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2673 20:14:39.926802 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2674 20:14:39.930347 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2675 20:14:39.933852 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2676 20:14:39.933937
2677 20:14:39.934003
2678 20:14:39.934063 ==
2679 20:14:39.936826 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 20:14:39.940246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 20:14:39.940344 ==
2682 20:14:39.940408
2683 20:14:39.940467
2684 20:14:39.943668 TX Vref Scan disable
2685 20:14:39.946973 == TX Byte 0 ==
2686 20:14:39.950332 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2687 20:14:39.954329 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2688 20:14:39.957135 == TX Byte 1 ==
2689 20:14:39.960446 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2690 20:14:39.963518 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2691 20:14:39.963598 ==
2692 20:14:39.967353 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 20:14:39.970376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 20:14:39.973843 ==
2695 20:14:39.983849 TX Vref=22, minBit 12, minWin=24, winSum=407
2696 20:14:39.986845 TX Vref=24, minBit 0, minWin=25, winSum=409
2697 20:14:39.990556 TX Vref=26, minBit 7, minWin=25, winSum=421
2698 20:14:39.993665 TX Vref=28, minBit 1, minWin=26, winSum=426
2699 20:14:39.996834 TX Vref=30, minBit 13, minWin=25, winSum=427
2700 20:14:40.003732 TX Vref=32, minBit 0, minWin=26, winSum=424
2701 20:14:40.007056 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
2702 20:14:40.007168
2703 20:14:40.010708 Final TX Range 1 Vref 28
2704 20:14:40.010822
2705 20:14:40.010910 ==
2706 20:14:40.013581 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 20:14:40.016911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 20:14:40.016991 ==
2709 20:14:40.020245
2710 20:14:40.020355
2711 20:14:40.020448 TX Vref Scan disable
2712 20:14:40.023934 == TX Byte 0 ==
2713 20:14:40.027086 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2714 20:14:40.030284 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2715 20:14:40.033868 == TX Byte 1 ==
2716 20:14:40.037098 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2717 20:14:40.040248 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2718 20:14:40.040362
2719 20:14:40.043751 [DATLAT]
2720 20:14:40.043860 Freq=1200, CH0 RK0
2721 20:14:40.043958
2722 20:14:40.046991 DATLAT Default: 0xd
2723 20:14:40.047098 0, 0xFFFF, sum = 0
2724 20:14:40.050658 1, 0xFFFF, sum = 0
2725 20:14:40.050763 2, 0xFFFF, sum = 0
2726 20:14:40.053736 3, 0xFFFF, sum = 0
2727 20:14:40.053846 4, 0xFFFF, sum = 0
2728 20:14:40.057352 5, 0xFFFF, sum = 0
2729 20:14:40.057458 6, 0xFFFF, sum = 0
2730 20:14:40.060372 7, 0xFFFF, sum = 0
2731 20:14:40.060448 8, 0xFFFF, sum = 0
2732 20:14:40.063880 9, 0xFFFF, sum = 0
2733 20:14:40.067290 10, 0xFFFF, sum = 0
2734 20:14:40.067374 11, 0xFFFF, sum = 0
2735 20:14:40.070580 12, 0x0, sum = 1
2736 20:14:40.070666 13, 0x0, sum = 2
2737 20:14:40.070732 14, 0x0, sum = 3
2738 20:14:40.074085 15, 0x0, sum = 4
2739 20:14:40.074216 best_step = 13
2740 20:14:40.074328
2741 20:14:40.074438 ==
2742 20:14:40.077106 Dram Type= 6, Freq= 0, CH_0, rank 0
2743 20:14:40.083761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2744 20:14:40.083865 ==
2745 20:14:40.083958 RX Vref Scan: 1
2746 20:14:40.084047
2747 20:14:40.087416 Set Vref Range= 32 -> 127
2748 20:14:40.087518
2749 20:14:40.090516 RX Vref 32 -> 127, step: 1
2750 20:14:40.090632
2751 20:14:40.093705 RX Delay -13 -> 252, step: 4
2752 20:14:40.093803
2753 20:14:40.096998 Set Vref, RX VrefLevel [Byte0]: 32
2754 20:14:40.100756 [Byte1]: 32
2755 20:14:40.100843
2756 20:14:40.103956 Set Vref, RX VrefLevel [Byte0]: 33
2757 20:14:40.107124 [Byte1]: 33
2758 20:14:40.107198
2759 20:14:40.111020 Set Vref, RX VrefLevel [Byte0]: 34
2760 20:14:40.114195 [Byte1]: 34
2761 20:14:40.118080
2762 20:14:40.118194 Set Vref, RX VrefLevel [Byte0]: 35
2763 20:14:40.120996 [Byte1]: 35
2764 20:14:40.125738
2765 20:14:40.125865 Set Vref, RX VrefLevel [Byte0]: 36
2766 20:14:40.128954 [Byte1]: 36
2767 20:14:40.134131
2768 20:14:40.134238 Set Vref, RX VrefLevel [Byte0]: 37
2769 20:14:40.137084 [Byte1]: 37
2770 20:14:40.141372
2771 20:14:40.141477 Set Vref, RX VrefLevel [Byte0]: 38
2772 20:14:40.144706 [Byte1]: 38
2773 20:14:40.149593
2774 20:14:40.149696 Set Vref, RX VrefLevel [Byte0]: 39
2775 20:14:40.152589 [Byte1]: 39
2776 20:14:40.157443
2777 20:14:40.157567 Set Vref, RX VrefLevel [Byte0]: 40
2778 20:14:40.160532 [Byte1]: 40
2779 20:14:40.165239
2780 20:14:40.165367 Set Vref, RX VrefLevel [Byte0]: 41
2781 20:14:40.168337 [Byte1]: 41
2782 20:14:40.173346
2783 20:14:40.173468 Set Vref, RX VrefLevel [Byte0]: 42
2784 20:14:40.176592 [Byte1]: 42
2785 20:14:40.181074
2786 20:14:40.181191 Set Vref, RX VrefLevel [Byte0]: 43
2787 20:14:40.184475 [Byte1]: 43
2788 20:14:40.188900
2789 20:14:40.188983 Set Vref, RX VrefLevel [Byte0]: 44
2790 20:14:40.192076 [Byte1]: 44
2791 20:14:40.196941
2792 20:14:40.197032 Set Vref, RX VrefLevel [Byte0]: 45
2793 20:14:40.200129 [Byte1]: 45
2794 20:14:40.204415
2795 20:14:40.204497 Set Vref, RX VrefLevel [Byte0]: 46
2796 20:14:40.208059 [Byte1]: 46
2797 20:14:40.212622
2798 20:14:40.212703 Set Vref, RX VrefLevel [Byte0]: 47
2799 20:14:40.215914 [Byte1]: 47
2800 20:14:40.220381
2801 20:14:40.220481 Set Vref, RX VrefLevel [Byte0]: 48
2802 20:14:40.223625 [Byte1]: 48
2803 20:14:40.228516
2804 20:14:40.228625 Set Vref, RX VrefLevel [Byte0]: 49
2805 20:14:40.231438 [Byte1]: 49
2806 20:14:40.236182
2807 20:14:40.236291 Set Vref, RX VrefLevel [Byte0]: 50
2808 20:14:40.239417 [Byte1]: 50
2809 20:14:40.244354
2810 20:14:40.244455 Set Vref, RX VrefLevel [Byte0]: 51
2811 20:14:40.247591 [Byte1]: 51
2812 20:14:40.252016
2813 20:14:40.252129 Set Vref, RX VrefLevel [Byte0]: 52
2814 20:14:40.255140 [Byte1]: 52
2815 20:14:40.259986
2816 20:14:40.260113 Set Vref, RX VrefLevel [Byte0]: 53
2817 20:14:40.263137 [Byte1]: 53
2818 20:14:40.268031
2819 20:14:40.268155 Set Vref, RX VrefLevel [Byte0]: 54
2820 20:14:40.271288 [Byte1]: 54
2821 20:14:40.275682
2822 20:14:40.275809 Set Vref, RX VrefLevel [Byte0]: 55
2823 20:14:40.279007 [Byte1]: 55
2824 20:14:40.283926
2825 20:14:40.284051 Set Vref, RX VrefLevel [Byte0]: 56
2826 20:14:40.286932 [Byte1]: 56
2827 20:14:40.291280
2828 20:14:40.291388 Set Vref, RX VrefLevel [Byte0]: 57
2829 20:14:40.294519 [Byte1]: 57
2830 20:14:40.299377
2831 20:14:40.299489 Set Vref, RX VrefLevel [Byte0]: 58
2832 20:14:40.302901 [Byte1]: 58
2833 20:14:40.307369
2834 20:14:40.307497 Set Vref, RX VrefLevel [Byte0]: 59
2835 20:14:40.310511 [Byte1]: 59
2836 20:14:40.315279
2837 20:14:40.315385 Set Vref, RX VrefLevel [Byte0]: 60
2838 20:14:40.318181 [Byte1]: 60
2839 20:14:40.323262
2840 20:14:40.323344 Set Vref, RX VrefLevel [Byte0]: 61
2841 20:14:40.326518 [Byte1]: 61
2842 20:14:40.331082
2843 20:14:40.331194 Set Vref, RX VrefLevel [Byte0]: 62
2844 20:14:40.334151 [Byte1]: 62
2845 20:14:40.339074
2846 20:14:40.339190 Set Vref, RX VrefLevel [Byte0]: 63
2847 20:14:40.341905 [Byte1]: 63
2848 20:14:40.346858
2849 20:14:40.346962 Set Vref, RX VrefLevel [Byte0]: 64
2850 20:14:40.349791 [Byte1]: 64
2851 20:14:40.354615
2852 20:14:40.354722 Set Vref, RX VrefLevel [Byte0]: 65
2853 20:14:40.357914 [Byte1]: 65
2854 20:14:40.362342
2855 20:14:40.362466 Set Vref, RX VrefLevel [Byte0]: 66
2856 20:14:40.366006 [Byte1]: 66
2857 20:14:40.370404
2858 20:14:40.370520 Set Vref, RX VrefLevel [Byte0]: 67
2859 20:14:40.373470 [Byte1]: 67
2860 20:14:40.378419
2861 20:14:40.378545 Set Vref, RX VrefLevel [Byte0]: 68
2862 20:14:40.381553 [Byte1]: 68
2863 20:14:40.386122
2864 20:14:40.386247 Set Vref, RX VrefLevel [Byte0]: 69
2865 20:14:40.389494 [Byte1]: 69
2866 20:14:40.394307
2867 20:14:40.394390 Final RX Vref Byte 0 = 57 to rank0
2868 20:14:40.397243 Final RX Vref Byte 1 = 46 to rank0
2869 20:14:40.400781 Final RX Vref Byte 0 = 57 to rank1
2870 20:14:40.404113 Final RX Vref Byte 1 = 46 to rank1==
2871 20:14:40.407160 Dram Type= 6, Freq= 0, CH_0, rank 0
2872 20:14:40.414239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 20:14:40.414323 ==
2874 20:14:40.414394 DQS Delay:
2875 20:14:40.414455 DQS0 = 0, DQS1 = 0
2876 20:14:40.417245 DQM Delay:
2877 20:14:40.417331 DQM0 = 120, DQM1 = 110
2878 20:14:40.420863 DQ Delay:
2879 20:14:40.424238 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2880 20:14:40.427417 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2881 20:14:40.430777 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2882 20:14:40.434352 DQ12 =116, DQ13 =114, DQ14 =124, DQ15 =118
2883 20:14:40.434457
2884 20:14:40.434553
2885 20:14:40.441322 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2886 20:14:40.444459 CH0 RK0: MR19=404, MR18=1710
2887 20:14:40.450805 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2888 20:14:40.450909
2889 20:14:40.454273 ----->DramcWriteLeveling(PI) begin...
2890 20:14:40.454378 ==
2891 20:14:40.457250 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 20:14:40.460807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 20:14:40.463842 ==
2894 20:14:40.463949 Write leveling (Byte 0): 36 => 36
2895 20:14:40.467155 Write leveling (Byte 1): 28 => 28
2896 20:14:40.470861 DramcWriteLeveling(PI) end<-----
2897 20:14:40.470974
2898 20:14:40.471068 ==
2899 20:14:40.474371 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 20:14:40.480674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 20:14:40.480802 ==
2902 20:14:40.480920 [Gating] SW mode calibration
2903 20:14:40.490784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2904 20:14:40.494031 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2905 20:14:40.497152 0 15 0 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 0)
2906 20:14:40.503914 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 20:14:40.507456 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 20:14:40.510530 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 20:14:40.517147 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 20:14:40.520863 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 20:14:40.524084 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2912 20:14:40.530933 0 15 28 | B1->B0 | 3232 2d2d | 1 1 | (1 0) (1 0)
2913 20:14:40.533747 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2914 20:14:40.537264 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 20:14:40.544064 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 20:14:40.547652 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 20:14:40.550872 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 20:14:40.557221 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 20:14:40.560757 1 0 24 | B1->B0 | 2626 2626 | 0 0 | (1 1) (0 0)
2920 20:14:40.564208 1 0 28 | B1->B0 | 3d3d 4141 | 0 1 | (0 0) (1 1)
2921 20:14:40.570929 1 1 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
2922 20:14:40.573992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 20:14:40.577628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 20:14:40.581187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 20:14:40.587880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 20:14:40.590982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 20:14:40.594109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 20:14:40.601117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2929 20:14:40.604231 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2930 20:14:40.607435 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 20:14:40.614262 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 20:14:40.617779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 20:14:40.621085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 20:14:40.627453 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 20:14:40.631218 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 20:14:40.634460 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 20:14:40.638187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 20:14:40.644606 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 20:14:40.647919 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 20:14:40.650812 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 20:14:40.657769 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 20:14:40.661150 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 20:14:40.664255 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 20:14:40.671373 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2945 20:14:40.674441 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 20:14:40.677808 Total UI for P1: 0, mck2ui 16
2947 20:14:40.681046 best dqsien dly found for B0: ( 1, 3, 28)
2948 20:14:40.684451 Total UI for P1: 0, mck2ui 16
2949 20:14:40.687822 best dqsien dly found for B1: ( 1, 3, 28)
2950 20:14:40.690905 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2951 20:14:40.694727 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2952 20:14:40.694811
2953 20:14:40.697691 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2954 20:14:40.701379 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2955 20:14:40.704719 [Gating] SW calibration Done
2956 20:14:40.704851 ==
2957 20:14:40.707812 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 20:14:40.710880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 20:14:40.714829 ==
2960 20:14:40.714952 RX Vref Scan: 0
2961 20:14:40.715052
2962 20:14:40.718069 RX Vref 0 -> 0, step: 1
2963 20:14:40.718182
2964 20:14:40.718276 RX Delay -40 -> 252, step: 8
2965 20:14:40.724924 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2966 20:14:40.728001 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2967 20:14:40.731215 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2968 20:14:40.734956 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2969 20:14:40.738146 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2970 20:14:40.745062 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2971 20:14:40.748106 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2972 20:14:40.751759 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2973 20:14:40.754837 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2974 20:14:40.757949 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2975 20:14:40.764867 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2976 20:14:40.768205 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2977 20:14:40.771471 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2978 20:14:40.774886 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2979 20:14:40.778146 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2980 20:14:40.785217 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2981 20:14:40.785303 ==
2982 20:14:40.788182 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 20:14:40.791518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 20:14:40.791601 ==
2985 20:14:40.791692 DQS Delay:
2986 20:14:40.795090 DQS0 = 0, DQS1 = 0
2987 20:14:40.795213 DQM Delay:
2988 20:14:40.798256 DQM0 = 122, DQM1 = 112
2989 20:14:40.798376 DQ Delay:
2990 20:14:40.801644 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2991 20:14:40.805014 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2992 20:14:40.807939 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2993 20:14:40.811715 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2994 20:14:40.811800
2995 20:14:40.811866
2996 20:14:40.814873 ==
2997 20:14:40.814984 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 20:14:40.821938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 20:14:40.822024 ==
3000 20:14:40.822090
3001 20:14:40.822151
3002 20:14:40.825180 TX Vref Scan disable
3003 20:14:40.825290 == TX Byte 0 ==
3004 20:14:40.828214 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3005 20:14:40.835120 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3006 20:14:40.835227 == TX Byte 1 ==
3007 20:14:40.838297 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3008 20:14:40.844541 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3009 20:14:40.844622 ==
3010 20:14:40.848374 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 20:14:40.851485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 20:14:40.851559 ==
3013 20:14:40.864351 TX Vref=22, minBit 1, minWin=25, winSum=419
3014 20:14:40.867030 TX Vref=24, minBit 0, minWin=26, winSum=421
3015 20:14:40.870823 TX Vref=26, minBit 4, minWin=26, winSum=427
3016 20:14:40.874036 TX Vref=28, minBit 12, minWin=26, winSum=432
3017 20:14:40.877638 TX Vref=30, minBit 5, minWin=25, winSum=430
3018 20:14:40.880542 TX Vref=32, minBit 1, minWin=26, winSum=430
3019 20:14:40.887422 [TxChooseVref] Worse bit 12, Min win 26, Win sum 432, Final Vref 28
3020 20:14:40.887529
3021 20:14:40.890745 Final TX Range 1 Vref 28
3022 20:14:40.890852
3023 20:14:40.890956 ==
3024 20:14:40.894543 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 20:14:40.897573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 20:14:40.897680 ==
3027 20:14:40.897784
3028 20:14:40.901150
3029 20:14:40.901257 TX Vref Scan disable
3030 20:14:40.903910 == TX Byte 0 ==
3031 20:14:40.907909 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3032 20:14:40.911027 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3033 20:14:40.914034 == TX Byte 1 ==
3034 20:14:40.917464 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3035 20:14:40.920814 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3036 20:14:40.920922
3037 20:14:40.923885 [DATLAT]
3038 20:14:40.923986 Freq=1200, CH0 RK1
3039 20:14:40.924089
3040 20:14:40.927414 DATLAT Default: 0xd
3041 20:14:40.927517 0, 0xFFFF, sum = 0
3042 20:14:40.930600 1, 0xFFFF, sum = 0
3043 20:14:40.930731 2, 0xFFFF, sum = 0
3044 20:14:40.934140 3, 0xFFFF, sum = 0
3045 20:14:40.934267 4, 0xFFFF, sum = 0
3046 20:14:40.937702 5, 0xFFFF, sum = 0
3047 20:14:40.937811 6, 0xFFFF, sum = 0
3048 20:14:40.940781 7, 0xFFFF, sum = 0
3049 20:14:40.944093 8, 0xFFFF, sum = 0
3050 20:14:40.944199 9, 0xFFFF, sum = 0
3051 20:14:40.948055 10, 0xFFFF, sum = 0
3052 20:14:40.948159 11, 0xFFFF, sum = 0
3053 20:14:40.951255 12, 0x0, sum = 1
3054 20:14:40.951362 13, 0x0, sum = 2
3055 20:14:40.951466 14, 0x0, sum = 3
3056 20:14:40.954493 15, 0x0, sum = 4
3057 20:14:40.954601 best_step = 13
3058 20:14:40.954702
3059 20:14:40.957666 ==
3060 20:14:40.957767 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 20:14:40.964369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 20:14:40.964472 ==
3063 20:14:40.964569 RX Vref Scan: 0
3064 20:14:40.964659
3065 20:14:40.967449 RX Vref 0 -> 0, step: 1
3066 20:14:40.967548
3067 20:14:40.970583 RX Delay -13 -> 252, step: 4
3068 20:14:40.974587 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3069 20:14:40.977879 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3070 20:14:40.983997 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3071 20:14:40.987893 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3072 20:14:40.990959 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3073 20:14:40.994325 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3074 20:14:40.997553 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3075 20:14:41.004375 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3076 20:14:41.007709 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3077 20:14:41.011221 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3078 20:14:41.014133 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3079 20:14:41.017444 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3080 20:14:41.024190 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3081 20:14:41.027942 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3082 20:14:41.031000 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3083 20:14:41.034460 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3084 20:14:41.034543 ==
3085 20:14:41.037746 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 20:14:41.041103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 20:14:41.044277 ==
3088 20:14:41.044360 DQS Delay:
3089 20:14:41.044423 DQS0 = 0, DQS1 = 0
3090 20:14:41.047581 DQM Delay:
3091 20:14:41.047707 DQM0 = 120, DQM1 = 109
3092 20:14:41.051232 DQ Delay:
3093 20:14:41.054382 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3094 20:14:41.057641 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3095 20:14:41.061451 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3096 20:14:41.064554 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =118
3097 20:14:41.064664
3098 20:14:41.064756
3099 20:14:41.071351 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3100 20:14:41.074355 CH0 RK1: MR19=403, MR18=FEF
3101 20:14:41.081385 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3102 20:14:41.084521 [RxdqsGatingPostProcess] freq 1200
3103 20:14:41.091612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3104 20:14:41.091736 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 20:14:41.094813 best DQS1 dly(2T, 0.5T) = (0, 12)
3106 20:14:41.097952 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 20:14:41.101731 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3108 20:14:41.104824 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 20:14:41.108144 best DQS1 dly(2T, 0.5T) = (0, 11)
3110 20:14:41.111432 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 20:14:41.114609 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3112 20:14:41.117917 Pre-setting of DQS Precalculation
3113 20:14:41.121298 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3114 20:14:41.121412 ==
3115 20:14:41.124954 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 20:14:41.131442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 20:14:41.131549 ==
3118 20:14:41.135229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3119 20:14:41.141290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3120 20:14:41.150219 [CA 0] Center 37 (7~68) winsize 62
3121 20:14:41.153794 [CA 1] Center 37 (7~68) winsize 62
3122 20:14:41.157054 [CA 2] Center 35 (5~65) winsize 61
3123 20:14:41.160290 [CA 3] Center 34 (4~64) winsize 61
3124 20:14:41.163896 [CA 4] Center 34 (4~64) winsize 61
3125 20:14:41.167101 [CA 5] Center 33 (3~63) winsize 61
3126 20:14:41.167184
3127 20:14:41.170972 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3128 20:14:41.171055
3129 20:14:41.173995 [CATrainingPosCal] consider 1 rank data
3130 20:14:41.177311 u2DelayCellTimex100 = 270/100 ps
3131 20:14:41.180936 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 20:14:41.183817 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 20:14:41.187433 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3134 20:14:41.190690 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 20:14:41.197779 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 20:14:41.200969 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3137 20:14:41.201077
3138 20:14:41.204132 CA PerBit enable=1, Macro0, CA PI delay=33
3139 20:14:41.204215
3140 20:14:41.207989 [CBTSetCACLKResult] CA Dly = 33
3141 20:14:41.208073 CS Dly: 8 (0~39)
3142 20:14:41.208139 ==
3143 20:14:41.211007 Dram Type= 6, Freq= 0, CH_1, rank 1
3144 20:14:41.306374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 20:14:41.306514 ==
3146 20:14:41.306611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 20:14:41.306696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3148 20:14:41.306778 [CA 0] Center 37 (7~68) winsize 62
3149 20:14:41.306859 [CA 1] Center 37 (7~68) winsize 62
3150 20:14:41.306937 [CA 2] Center 35 (5~65) winsize 61
3151 20:14:41.307016 [CA 3] Center 34 (4~65) winsize 62
3152 20:14:41.307112 [CA 4] Center 34 (4~65) winsize 62
3153 20:14:41.307209 [CA 5] Center 33 (4~63) winsize 60
3154 20:14:41.307306
3155 20:14:41.307401 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3156 20:14:41.307497
3157 20:14:41.307593 [CATrainingPosCal] consider 2 rank data
3158 20:14:41.307688 u2DelayCellTimex100 = 270/100 ps
3159 20:14:41.307783 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 20:14:41.307878 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 20:14:41.307973 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3162 20:14:41.308067 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 20:14:41.308161 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 20:14:41.308256 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3165 20:14:41.308359
3166 20:14:41.308455 CA PerBit enable=1, Macro0, CA PI delay=33
3167 20:14:41.308551
3168 20:14:41.308648 [CBTSetCACLKResult] CA Dly = 33
3169 20:14:41.308743 CS Dly: 9 (0~41)
3170 20:14:41.308838
3171 20:14:41.308931 ----->DramcWriteLeveling(PI) begin...
3172 20:14:41.309028 ==
3173 20:14:41.309123 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 20:14:41.309218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 20:14:41.309313 ==
3176 20:14:41.309602 Write leveling (Byte 0): 26 => 26
3177 20:14:41.312708 Write leveling (Byte 1): 27 => 27
3178 20:14:41.312798 DramcWriteLeveling(PI) end<-----
3179 20:14:41.316467
3180 20:14:41.316563 ==
3181 20:14:41.319590 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 20:14:41.322801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 20:14:41.322891 ==
3184 20:14:41.325776 [Gating] SW mode calibration
3185 20:14:41.332875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3186 20:14:41.336190 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3187 20:14:41.342570 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 20:14:41.346301 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 20:14:41.349779 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 20:14:41.356352 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 20:14:41.359479 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 20:14:41.363002 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 20:14:41.369363 0 15 24 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (0 0)
3194 20:14:41.373102 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3195 20:14:41.376147 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 20:14:41.382690 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 20:14:41.386116 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 20:14:41.389596 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 20:14:41.392605 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 20:14:41.399413 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 20:14:41.403131 1 0 24 | B1->B0 | 3434 4040 | 0 0 | (1 1) (0 0)
3202 20:14:41.406035 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 20:14:41.413228 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 20:14:41.416302 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 20:14:41.419522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 20:14:41.426646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 20:14:41.429679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 20:14:41.433393 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 20:14:41.439419 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 20:14:41.442886 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3211 20:14:41.446670 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 20:14:41.453054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 20:14:41.456829 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 20:14:41.459911 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 20:14:41.463418 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 20:14:41.470069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 20:14:41.473140 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 20:14:41.476618 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 20:14:41.482971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 20:14:41.486773 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 20:14:41.489922 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 20:14:41.496310 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 20:14:41.499786 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 20:14:41.503226 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 20:14:41.510292 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 20:14:41.513040 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3227 20:14:41.516835 Total UI for P1: 0, mck2ui 16
3228 20:14:41.520037 best dqsien dly found for B0: ( 1, 3, 24)
3229 20:14:41.523289 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 20:14:41.526465 Total UI for P1: 0, mck2ui 16
3231 20:14:41.530369 best dqsien dly found for B1: ( 1, 3, 26)
3232 20:14:41.533408 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3233 20:14:41.536431 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3234 20:14:41.536521
3235 20:14:41.539969 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3236 20:14:41.546861 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3237 20:14:41.546970 [Gating] SW calibration Done
3238 20:14:41.547071 ==
3239 20:14:41.549895 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 20:14:41.556700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 20:14:41.556784 ==
3242 20:14:41.556849 RX Vref Scan: 0
3243 20:14:41.556910
3244 20:14:41.559947 RX Vref 0 -> 0, step: 1
3245 20:14:41.560060
3246 20:14:41.563647 RX Delay -40 -> 252, step: 8
3247 20:14:41.566884 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3248 20:14:41.569990 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3249 20:14:41.573889 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3250 20:14:41.576966 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3251 20:14:41.583530 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3252 20:14:41.587210 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3253 20:14:41.590253 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3254 20:14:41.593547 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3255 20:14:41.597215 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3256 20:14:41.603647 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3257 20:14:41.607192 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3258 20:14:41.610154 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3259 20:14:41.613601 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3260 20:14:41.616960 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3261 20:14:41.623422 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3262 20:14:41.627109 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3263 20:14:41.627217 ==
3264 20:14:41.630217 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 20:14:41.633404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 20:14:41.633491 ==
3267 20:14:41.636709 DQS Delay:
3268 20:14:41.636788 DQS0 = 0, DQS1 = 0
3269 20:14:41.636853 DQM Delay:
3270 20:14:41.640481 DQM0 = 120, DQM1 = 116
3271 20:14:41.640556 DQ Delay:
3272 20:14:41.643474 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3273 20:14:41.647145 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3274 20:14:41.650032 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3275 20:14:41.656795 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3276 20:14:41.656918
3277 20:14:41.657018
3278 20:14:41.657112 ==
3279 20:14:41.660699 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 20:14:41.663866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 20:14:41.663973 ==
3282 20:14:41.664077
3283 20:14:41.664174
3284 20:14:41.666992 TX Vref Scan disable
3285 20:14:41.667106 == TX Byte 0 ==
3286 20:14:41.673804 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3287 20:14:41.676885 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3288 20:14:41.677012 == TX Byte 1 ==
3289 20:14:41.683733 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3290 20:14:41.686915 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3291 20:14:41.687045 ==
3292 20:14:41.690596 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 20:14:41.693471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 20:14:41.693597 ==
3295 20:14:41.706014 TX Vref=22, minBit 9, minWin=24, winSum=412
3296 20:14:41.709460 TX Vref=24, minBit 1, minWin=25, winSum=417
3297 20:14:41.712524 TX Vref=26, minBit 10, minWin=25, winSum=422
3298 20:14:41.715802 TX Vref=28, minBit 9, minWin=25, winSum=426
3299 20:14:41.719582 TX Vref=30, minBit 10, minWin=26, winSum=431
3300 20:14:41.726206 TX Vref=32, minBit 9, minWin=25, winSum=427
3301 20:14:41.729328 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
3302 20:14:41.729452
3303 20:14:41.732705 Final TX Range 1 Vref 30
3304 20:14:41.732818
3305 20:14:41.732912 ==
3306 20:14:41.736188 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 20:14:41.739303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 20:14:41.739412 ==
3309 20:14:41.743000
3310 20:14:41.743126
3311 20:14:41.743222 TX Vref Scan disable
3312 20:14:41.746170 == TX Byte 0 ==
3313 20:14:41.749257 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3314 20:14:41.752813 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3315 20:14:41.756282 == TX Byte 1 ==
3316 20:14:41.759737 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3317 20:14:41.762814 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3318 20:14:41.762918
3319 20:14:41.766435 [DATLAT]
3320 20:14:41.766540 Freq=1200, CH1 RK0
3321 20:14:41.766642
3322 20:14:41.769743 DATLAT Default: 0xd
3323 20:14:41.769823 0, 0xFFFF, sum = 0
3324 20:14:41.772942 1, 0xFFFF, sum = 0
3325 20:14:41.773021 2, 0xFFFF, sum = 0
3326 20:14:41.775972 3, 0xFFFF, sum = 0
3327 20:14:41.776051 4, 0xFFFF, sum = 0
3328 20:14:41.779764 5, 0xFFFF, sum = 0
3329 20:14:41.779850 6, 0xFFFF, sum = 0
3330 20:14:41.782873 7, 0xFFFF, sum = 0
3331 20:14:41.782980 8, 0xFFFF, sum = 0
3332 20:14:41.786125 9, 0xFFFF, sum = 0
3333 20:14:41.789290 10, 0xFFFF, sum = 0
3334 20:14:41.789373 11, 0xFFFF, sum = 0
3335 20:14:41.793082 12, 0x0, sum = 1
3336 20:14:41.793161 13, 0x0, sum = 2
3337 20:14:41.793227 14, 0x0, sum = 3
3338 20:14:41.796533 15, 0x0, sum = 4
3339 20:14:41.796611 best_step = 13
3340 20:14:41.796675
3341 20:14:41.796735 ==
3342 20:14:41.799360 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 20:14:41.806215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 20:14:41.806346 ==
3345 20:14:41.806459 RX Vref Scan: 1
3346 20:14:41.806570
3347 20:14:41.809811 Set Vref Range= 32 -> 127
3348 20:14:41.809932
3349 20:14:41.813135 RX Vref 32 -> 127, step: 1
3350 20:14:41.813222
3351 20:14:41.816275 RX Delay -5 -> 252, step: 4
3352 20:14:41.816372
3353 20:14:41.819382 Set Vref, RX VrefLevel [Byte0]: 32
3354 20:14:41.822805 [Byte1]: 32
3355 20:14:41.822889
3356 20:14:41.826475 Set Vref, RX VrefLevel [Byte0]: 33
3357 20:14:41.829860 [Byte1]: 33
3358 20:14:41.829957
3359 20:14:41.832814 Set Vref, RX VrefLevel [Byte0]: 34
3360 20:14:41.836380 [Byte1]: 34
3361 20:14:41.839910
3362 20:14:41.840027 Set Vref, RX VrefLevel [Byte0]: 35
3363 20:14:41.843388 [Byte1]: 35
3364 20:14:41.848173
3365 20:14:41.848261 Set Vref, RX VrefLevel [Byte0]: 36
3366 20:14:41.850985 [Byte1]: 36
3367 20:14:41.855885
3368 20:14:41.855977 Set Vref, RX VrefLevel [Byte0]: 37
3369 20:14:41.859058 [Byte1]: 37
3370 20:14:41.863747
3371 20:14:41.863833 Set Vref, RX VrefLevel [Byte0]: 38
3372 20:14:41.867042 [Byte1]: 38
3373 20:14:41.871882
3374 20:14:41.871973 Set Vref, RX VrefLevel [Byte0]: 39
3375 20:14:41.874605 [Byte1]: 39
3376 20:14:41.879492
3377 20:14:41.879589 Set Vref, RX VrefLevel [Byte0]: 40
3378 20:14:41.882623 [Byte1]: 40
3379 20:14:41.887021
3380 20:14:41.887160 Set Vref, RX VrefLevel [Byte0]: 41
3381 20:14:41.890210 [Byte1]: 41
3382 20:14:41.895141
3383 20:14:41.895269 Set Vref, RX VrefLevel [Byte0]: 42
3384 20:14:41.898207 [Byte1]: 42
3385 20:14:41.903240
3386 20:14:41.903365 Set Vref, RX VrefLevel [Byte0]: 43
3387 20:14:41.906320 [Byte1]: 43
3388 20:14:41.910670
3389 20:14:41.910770 Set Vref, RX VrefLevel [Byte0]: 44
3390 20:14:41.913707 [Byte1]: 44
3391 20:14:41.918798
3392 20:14:41.918919 Set Vref, RX VrefLevel [Byte0]: 45
3393 20:14:41.921849 [Byte1]: 45
3394 20:14:41.926232
3395 20:14:41.926316 Set Vref, RX VrefLevel [Byte0]: 46
3396 20:14:41.930115 [Byte1]: 46
3397 20:14:41.934095
3398 20:14:41.934179 Set Vref, RX VrefLevel [Byte0]: 47
3399 20:14:41.937831 [Byte1]: 47
3400 20:14:41.942346
3401 20:14:41.942429 Set Vref, RX VrefLevel [Byte0]: 48
3402 20:14:41.945331 [Byte1]: 48
3403 20:14:41.949708
3404 20:14:41.949790 Set Vref, RX VrefLevel [Byte0]: 49
3405 20:14:41.953312 [Byte1]: 49
3406 20:14:41.958150
3407 20:14:41.958239 Set Vref, RX VrefLevel [Byte0]: 50
3408 20:14:41.960925 [Byte1]: 50
3409 20:14:41.965821
3410 20:14:41.965949 Set Vref, RX VrefLevel [Byte0]: 51
3411 20:14:41.968919 [Byte1]: 51
3412 20:14:41.973263
3413 20:14:41.973349 Set Vref, RX VrefLevel [Byte0]: 52
3414 20:14:41.976878 [Byte1]: 52
3415 20:14:41.981503
3416 20:14:41.981646 Set Vref, RX VrefLevel [Byte0]: 53
3417 20:14:41.984755 [Byte1]: 53
3418 20:14:41.989139
3419 20:14:41.989249 Set Vref, RX VrefLevel [Byte0]: 54
3420 20:14:41.992522 [Byte1]: 54
3421 20:14:41.997303
3422 20:14:41.997448 Set Vref, RX VrefLevel [Byte0]: 55
3423 20:14:42.000432 [Byte1]: 55
3424 20:14:42.004922
3425 20:14:42.005061 Set Vref, RX VrefLevel [Byte0]: 56
3426 20:14:42.008573 [Byte1]: 56
3427 20:14:42.012808
3428 20:14:42.012945 Set Vref, RX VrefLevel [Byte0]: 57
3429 20:14:42.016613 [Byte1]: 57
3430 20:14:42.020782
3431 20:14:42.020907 Set Vref, RX VrefLevel [Byte0]: 58
3432 20:14:42.023817 [Byte1]: 58
3433 20:14:42.028387
3434 20:14:42.028511 Set Vref, RX VrefLevel [Byte0]: 59
3435 20:14:42.031599 [Byte1]: 59
3436 20:14:42.036788
3437 20:14:42.036912 Set Vref, RX VrefLevel [Byte0]: 60
3438 20:14:42.039958 [Byte1]: 60
3439 20:14:42.044260
3440 20:14:42.044380 Set Vref, RX VrefLevel [Byte0]: 61
3441 20:14:42.047528 [Byte1]: 61
3442 20:14:42.051795
3443 20:14:42.051904 Set Vref, RX VrefLevel [Byte0]: 62
3444 20:14:42.055560 [Byte1]: 62
3445 20:14:42.059925
3446 20:14:42.060032 Set Vref, RX VrefLevel [Byte0]: 63
3447 20:14:42.063418 [Byte1]: 63
3448 20:14:42.067552
3449 20:14:42.067668 Set Vref, RX VrefLevel [Byte0]: 64
3450 20:14:42.071251 [Byte1]: 64
3451 20:14:42.075332
3452 20:14:42.075444 Set Vref, RX VrefLevel [Byte0]: 65
3453 20:14:42.078861 [Byte1]: 65
3454 20:14:42.083498
3455 20:14:42.083609 Set Vref, RX VrefLevel [Byte0]: 66
3456 20:14:42.086847 [Byte1]: 66
3457 20:14:42.091024
3458 20:14:42.091130 Set Vref, RX VrefLevel [Byte0]: 67
3459 20:14:42.094368 [Byte1]: 67
3460 20:14:42.099147
3461 20:14:42.099266 Set Vref, RX VrefLevel [Byte0]: 68
3462 20:14:42.102588 [Byte1]: 68
3463 20:14:42.107030
3464 20:14:42.107138 Final RX Vref Byte 0 = 54 to rank0
3465 20:14:42.110187 Final RX Vref Byte 1 = 54 to rank0
3466 20:14:42.113909 Final RX Vref Byte 0 = 54 to rank1
3467 20:14:42.117107 Final RX Vref Byte 1 = 54 to rank1==
3468 20:14:42.120180 Dram Type= 6, Freq= 0, CH_1, rank 0
3469 20:14:42.123919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 20:14:42.127331 ==
3471 20:14:42.127449 DQS Delay:
3472 20:14:42.127553 DQS0 = 0, DQS1 = 0
3473 20:14:42.130519 DQM Delay:
3474 20:14:42.130634 DQM0 = 120, DQM1 = 117
3475 20:14:42.133714 DQ Delay:
3476 20:14:42.136878 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3477 20:14:42.140603 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3478 20:14:42.143935 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3479 20:14:42.147033 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3480 20:14:42.147150
3481 20:14:42.147256
3482 20:14:42.153975 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3483 20:14:42.157404 CH1 RK0: MR19=404, MR18=13
3484 20:14:42.163592 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3485 20:14:42.163715
3486 20:14:42.167474 ----->DramcWriteLeveling(PI) begin...
3487 20:14:42.167586 ==
3488 20:14:42.170327 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 20:14:42.174031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 20:14:42.174141 ==
3491 20:14:42.176978 Write leveling (Byte 0): 26 => 26
3492 20:14:42.180636 Write leveling (Byte 1): 28 => 28
3493 20:14:42.183605 DramcWriteLeveling(PI) end<-----
3494 20:14:42.183728
3495 20:14:42.183842 ==
3496 20:14:42.187314 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 20:14:42.190526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 20:14:42.190632 ==
3499 20:14:42.193780 [Gating] SW mode calibration
3500 20:14:42.201087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3501 20:14:42.207249 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3502 20:14:42.210402 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 20:14:42.217497 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 20:14:42.220441 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 20:14:42.223763 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 20:14:42.230953 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 20:14:42.233915 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3508 20:14:42.237199 0 15 24 | B1->B0 | 2b2b 3333 | 0 1 | (0 1) (1 1)
3509 20:14:42.240321 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3510 20:14:42.247414 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 20:14:42.250700 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 20:14:42.254012 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 20:14:42.260396 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 20:14:42.264204 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 20:14:42.267247 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3516 20:14:42.273964 1 0 24 | B1->B0 | 4242 2c2c | 0 0 | (0 0) (0 0)
3517 20:14:42.277451 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
3518 20:14:42.280647 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 20:14:42.287280 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 20:14:42.290185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 20:14:42.293743 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 20:14:42.300884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 20:14:42.303879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3524 20:14:42.306979 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3525 20:14:42.313812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3526 20:14:42.317564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 20:14:42.320143 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 20:14:42.327214 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 20:14:42.330246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 20:14:42.333839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 20:14:42.340478 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 20:14:42.343629 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 20:14:42.347257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 20:14:42.353750 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 20:14:42.356925 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 20:14:42.360178 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 20:14:42.367026 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 20:14:42.370082 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 20:14:42.373858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3540 20:14:42.377078 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3541 20:14:42.383783 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3542 20:14:42.386758 Total UI for P1: 0, mck2ui 16
3543 20:14:42.389946 best dqsien dly found for B1: ( 1, 3, 22)
3544 20:14:42.393520 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 20:14:42.396699 Total UI for P1: 0, mck2ui 16
3546 20:14:42.400216 best dqsien dly found for B0: ( 1, 3, 26)
3547 20:14:42.403430 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3548 20:14:42.406599 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3549 20:14:42.406712
3550 20:14:42.409806 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3551 20:14:42.413393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3552 20:14:42.416473 [Gating] SW calibration Done
3553 20:14:42.416551 ==
3554 20:14:42.420206 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 20:14:42.426487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 20:14:42.426608 ==
3557 20:14:42.426704 RX Vref Scan: 0
3558 20:14:42.426795
3559 20:14:42.430193 RX Vref 0 -> 0, step: 1
3560 20:14:42.430304
3561 20:14:42.433291 RX Delay -40 -> 252, step: 8
3562 20:14:42.436552 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3563 20:14:42.440298 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3564 20:14:42.443258 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3565 20:14:42.446925 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3566 20:14:42.453327 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3567 20:14:42.456845 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3568 20:14:42.460095 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3569 20:14:42.463304 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3570 20:14:42.467199 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3571 20:14:42.473600 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3572 20:14:42.476600 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3573 20:14:42.480367 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3574 20:14:42.483551 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3575 20:14:42.486623 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3576 20:14:42.493266 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3577 20:14:42.496506 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3578 20:14:42.496590 ==
3579 20:14:42.499642 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 20:14:42.503199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 20:14:42.503283 ==
3582 20:14:42.506727 DQS Delay:
3583 20:14:42.506810 DQS0 = 0, DQS1 = 0
3584 20:14:42.506875 DQM Delay:
3585 20:14:42.510225 DQM0 = 120, DQM1 = 117
3586 20:14:42.510309 DQ Delay:
3587 20:14:42.513390 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =115
3588 20:14:42.516592 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3589 20:14:42.523356 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3590 20:14:42.526309 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3591 20:14:42.526396
3592 20:14:42.526462
3593 20:14:42.526522 ==
3594 20:14:42.529529 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 20:14:42.533399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 20:14:42.533482 ==
3597 20:14:42.533546
3598 20:14:42.533607
3599 20:14:42.536006 TX Vref Scan disable
3600 20:14:42.539822 == TX Byte 0 ==
3601 20:14:42.542801 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3602 20:14:42.546502 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3603 20:14:42.549784 == TX Byte 1 ==
3604 20:14:42.552792 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3605 20:14:42.556054 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3606 20:14:42.556126 ==
3607 20:14:42.559830 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 20:14:42.562631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 20:14:42.562713 ==
3610 20:14:42.575637 TX Vref=22, minBit 10, minWin=25, winSum=420
3611 20:14:42.579267 TX Vref=24, minBit 1, minWin=26, winSum=425
3612 20:14:42.582402 TX Vref=26, minBit 1, minWin=26, winSum=429
3613 20:14:42.585551 TX Vref=28, minBit 0, minWin=26, winSum=432
3614 20:14:42.589412 TX Vref=30, minBit 9, minWin=26, winSum=437
3615 20:14:42.595784 TX Vref=32, minBit 9, minWin=26, winSum=433
3616 20:14:42.598833 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3617 20:14:42.598936
3618 20:14:42.602819 Final TX Range 1 Vref 30
3619 20:14:42.602901
3620 20:14:42.602966 ==
3621 20:14:42.605986 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 20:14:42.609061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 20:14:42.612025 ==
3624 20:14:42.612138
3625 20:14:42.612243
3626 20:14:42.612354 TX Vref Scan disable
3627 20:14:42.615386 == TX Byte 0 ==
3628 20:14:42.618960 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3629 20:14:42.622059 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3630 20:14:42.625702 == TX Byte 1 ==
3631 20:14:42.629276 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3632 20:14:42.632326 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3633 20:14:42.635361
3634 20:14:42.635465 [DATLAT]
3635 20:14:42.635569 Freq=1200, CH1 RK1
3636 20:14:42.635671
3637 20:14:42.639178 DATLAT Default: 0xd
3638 20:14:42.639261 0, 0xFFFF, sum = 0
3639 20:14:42.642467 1, 0xFFFF, sum = 0
3640 20:14:42.642553 2, 0xFFFF, sum = 0
3641 20:14:42.645616 3, 0xFFFF, sum = 0
3642 20:14:42.648929 4, 0xFFFF, sum = 0
3643 20:14:42.649041 5, 0xFFFF, sum = 0
3644 20:14:42.651925 6, 0xFFFF, sum = 0
3645 20:14:42.652008 7, 0xFFFF, sum = 0
3646 20:14:42.655569 8, 0xFFFF, sum = 0
3647 20:14:42.655669 9, 0xFFFF, sum = 0
3648 20:14:42.658721 10, 0xFFFF, sum = 0
3649 20:14:42.658806 11, 0xFFFF, sum = 0
3650 20:14:42.662081 12, 0x0, sum = 1
3651 20:14:42.662194 13, 0x0, sum = 2
3652 20:14:42.665203 14, 0x0, sum = 3
3653 20:14:42.665314 15, 0x0, sum = 4
3654 20:14:42.665422 best_step = 13
3655 20:14:42.668443
3656 20:14:42.668528 ==
3657 20:14:42.672161 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 20:14:42.675736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 20:14:42.675844 ==
3660 20:14:42.675949 RX Vref Scan: 0
3661 20:14:42.676052
3662 20:14:42.678897 RX Vref 0 -> 0, step: 1
3663 20:14:42.679006
3664 20:14:42.682228 RX Delay -5 -> 252, step: 4
3665 20:14:42.685338 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3666 20:14:42.692012 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3667 20:14:42.695137 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3668 20:14:42.698274 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3669 20:14:42.701938 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3670 20:14:42.705403 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3671 20:14:42.711694 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3672 20:14:42.714884 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3673 20:14:42.718695 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3674 20:14:42.721835 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3675 20:14:42.724894 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3676 20:14:42.732052 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3677 20:14:42.735026 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3678 20:14:42.738467 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3679 20:14:42.741899 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3680 20:14:42.744767 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3681 20:14:42.748457 ==
3682 20:14:42.751708 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 20:14:42.754800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 20:14:42.754917 ==
3685 20:14:42.755025 DQS Delay:
3686 20:14:42.758700 DQS0 = 0, DQS1 = 0
3687 20:14:42.758816 DQM Delay:
3688 20:14:42.761885 DQM0 = 120, DQM1 = 118
3689 20:14:42.761993 DQ Delay:
3690 20:14:42.765087 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3691 20:14:42.768326 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3692 20:14:42.771579 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3693 20:14:42.774861 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3694 20:14:42.774971
3695 20:14:42.775078
3696 20:14:42.785169 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3697 20:14:42.785270 CH1 RK1: MR19=403, MR18=FEC
3698 20:14:42.791567 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3699 20:14:42.794811 [RxdqsGatingPostProcess] freq 1200
3700 20:14:42.801643 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3701 20:14:42.804703 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 20:14:42.808282 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 20:14:42.811747 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 20:14:42.814909 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 20:14:42.818043 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 20:14:42.822051 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 20:14:42.822156 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 20:14:42.825155 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 20:14:42.828270 Pre-setting of DQS Precalculation
3710 20:14:42.834829 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3711 20:14:42.841418 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3712 20:14:42.848177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3713 20:14:42.848310
3714 20:14:42.848501
3715 20:14:42.851600 [Calibration Summary] 2400 Mbps
3716 20:14:42.855034 CH 0, Rank 0
3717 20:14:42.855170 SW Impedance : PASS
3718 20:14:42.857993 DUTY Scan : NO K
3719 20:14:42.861309 ZQ Calibration : PASS
3720 20:14:42.861416 Jitter Meter : NO K
3721 20:14:42.864424 CBT Training : PASS
3722 20:14:42.864533 Write leveling : PASS
3723 20:14:42.868433 RX DQS gating : PASS
3724 20:14:42.871523 RX DQ/DQS(RDDQC) : PASS
3725 20:14:42.871628 TX DQ/DQS : PASS
3726 20:14:42.874752 RX DATLAT : PASS
3727 20:14:42.877995 RX DQ/DQS(Engine): PASS
3728 20:14:42.878105 TX OE : NO K
3729 20:14:42.881218 All Pass.
3730 20:14:42.881335
3731 20:14:42.881441 CH 0, Rank 1
3732 20:14:42.884981 SW Impedance : PASS
3733 20:14:42.885086 DUTY Scan : NO K
3734 20:14:42.888221 ZQ Calibration : PASS
3735 20:14:42.891393 Jitter Meter : NO K
3736 20:14:42.891481 CBT Training : PASS
3737 20:14:42.894749 Write leveling : PASS
3738 20:14:42.897871 RX DQS gating : PASS
3739 20:14:42.897977 RX DQ/DQS(RDDQC) : PASS
3740 20:14:42.901567 TX DQ/DQS : PASS
3741 20:14:42.901679 RX DATLAT : PASS
3742 20:14:42.904724 RX DQ/DQS(Engine): PASS
3743 20:14:42.908061 TX OE : NO K
3744 20:14:42.908169 All Pass.
3745 20:14:42.908276
3746 20:14:42.908386 CH 1, Rank 0
3747 20:14:42.911220 SW Impedance : PASS
3748 20:14:42.914893 DUTY Scan : NO K
3749 20:14:42.915009 ZQ Calibration : PASS
3750 20:14:42.918019 Jitter Meter : NO K
3751 20:14:42.921240 CBT Training : PASS
3752 20:14:42.921352 Write leveling : PASS
3753 20:14:42.925076 RX DQS gating : PASS
3754 20:14:42.928147 RX DQ/DQS(RDDQC) : PASS
3755 20:14:42.928273 TX DQ/DQS : PASS
3756 20:14:42.931769 RX DATLAT : PASS
3757 20:14:42.934919 RX DQ/DQS(Engine): PASS
3758 20:14:42.935001 TX OE : NO K
3759 20:14:42.938042 All Pass.
3760 20:14:42.938120
3761 20:14:42.938185 CH 1, Rank 1
3762 20:14:42.941630 SW Impedance : PASS
3763 20:14:42.941709 DUTY Scan : NO K
3764 20:14:42.944774 ZQ Calibration : PASS
3765 20:14:42.947969 Jitter Meter : NO K
3766 20:14:42.948074 CBT Training : PASS
3767 20:14:42.951138 Write leveling : PASS
3768 20:14:42.951242 RX DQS gating : PASS
3769 20:14:42.954470 RX DQ/DQS(RDDQC) : PASS
3770 20:14:42.958038 TX DQ/DQS : PASS
3771 20:14:42.958123 RX DATLAT : PASS
3772 20:14:42.961727 RX DQ/DQS(Engine): PASS
3773 20:14:42.964758 TX OE : NO K
3774 20:14:42.964836 All Pass.
3775 20:14:42.964900
3776 20:14:42.968313 DramC Write-DBI off
3777 20:14:42.968400 PER_BANK_REFRESH: Hybrid Mode
3778 20:14:42.971115 TX_TRACKING: ON
3779 20:14:42.980921 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3780 20:14:42.984212 [FAST_K] Save calibration result to emmc
3781 20:14:42.988090 dramc_set_vcore_voltage set vcore to 650000
3782 20:14:42.988203 Read voltage for 600, 5
3783 20:14:42.991291 Vio18 = 0
3784 20:14:42.991421 Vcore = 650000
3785 20:14:42.991537 Vdram = 0
3786 20:14:42.994533 Vddq = 0
3787 20:14:42.994654 Vmddr = 0
3788 20:14:42.998277 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3789 20:14:43.004664 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3790 20:14:43.007880 MEM_TYPE=3, freq_sel=19
3791 20:14:43.011099 sv_algorithm_assistance_LP4_1600
3792 20:14:43.014376 ============ PULL DRAM RESETB DOWN ============
3793 20:14:43.017431 ========== PULL DRAM RESETB DOWN end =========
3794 20:14:43.024280 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3795 20:14:43.027825 ===================================
3796 20:14:43.027933 LPDDR4 DRAM CONFIGURATION
3797 20:14:43.030768 ===================================
3798 20:14:43.034051 EX_ROW_EN[0] = 0x0
3799 20:14:43.034160 EX_ROW_EN[1] = 0x0
3800 20:14:43.037886 LP4Y_EN = 0x0
3801 20:14:43.041002 WORK_FSP = 0x0
3802 20:14:43.041112 WL = 0x2
3803 20:14:43.044539 RL = 0x2
3804 20:14:43.044645 BL = 0x2
3805 20:14:43.047746 RPST = 0x0
3806 20:14:43.047853 RD_PRE = 0x0
3807 20:14:43.050977 WR_PRE = 0x1
3808 20:14:43.051081 WR_PST = 0x0
3809 20:14:43.054408 DBI_WR = 0x0
3810 20:14:43.054513 DBI_RD = 0x0
3811 20:14:43.057720 OTF = 0x1
3812 20:14:43.060839 ===================================
3813 20:14:43.064417 ===================================
3814 20:14:43.064523 ANA top config
3815 20:14:43.067585 ===================================
3816 20:14:43.070624 DLL_ASYNC_EN = 0
3817 20:14:43.074239 ALL_SLAVE_EN = 1
3818 20:14:43.074348 NEW_RANK_MODE = 1
3819 20:14:43.077715 DLL_IDLE_MODE = 1
3820 20:14:43.080641 LP45_APHY_COMB_EN = 1
3821 20:14:43.083998 TX_ODT_DIS = 1
3822 20:14:43.087629 NEW_8X_MODE = 1
3823 20:14:43.090619 ===================================
3824 20:14:43.093789 ===================================
3825 20:14:43.093904 data_rate = 1200
3826 20:14:43.097057 CKR = 1
3827 20:14:43.100427 DQ_P2S_RATIO = 8
3828 20:14:43.104318 ===================================
3829 20:14:43.107394 CA_P2S_RATIO = 8
3830 20:14:43.110492 DQ_CA_OPEN = 0
3831 20:14:43.113642 DQ_SEMI_OPEN = 0
3832 20:14:43.113754 CA_SEMI_OPEN = 0
3833 20:14:43.117469 CA_FULL_RATE = 0
3834 20:14:43.120535 DQ_CKDIV4_EN = 1
3835 20:14:43.123719 CA_CKDIV4_EN = 1
3836 20:14:43.127510 CA_PREDIV_EN = 0
3837 20:14:43.130695 PH8_DLY = 0
3838 20:14:43.130789 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3839 20:14:43.133916 DQ_AAMCK_DIV = 4
3840 20:14:43.137015 CA_AAMCK_DIV = 4
3841 20:14:43.140600 CA_ADMCK_DIV = 4
3842 20:14:43.143857 DQ_TRACK_CA_EN = 0
3843 20:14:43.147397 CA_PICK = 600
3844 20:14:43.147508 CA_MCKIO = 600
3845 20:14:43.150712 MCKIO_SEMI = 0
3846 20:14:43.153802 PLL_FREQ = 2288
3847 20:14:43.157006 DQ_UI_PI_RATIO = 32
3848 20:14:43.160406 CA_UI_PI_RATIO = 0
3849 20:14:43.163820 ===================================
3850 20:14:43.166559 ===================================
3851 20:14:43.170486 memory_type:LPDDR4
3852 20:14:43.170565 GP_NUM : 10
3853 20:14:43.173560 SRAM_EN : 1
3854 20:14:43.173678 MD32_EN : 0
3855 20:14:43.176612 ===================================
3856 20:14:43.179926 [ANA_INIT] >>>>>>>>>>>>>>
3857 20:14:43.183424 <<<<<< [CONFIGURE PHASE]: ANA_TX
3858 20:14:43.187017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3859 20:14:43.190293 ===================================
3860 20:14:43.193417 data_rate = 1200,PCW = 0X5800
3861 20:14:43.196724 ===================================
3862 20:14:43.200190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3863 20:14:43.206369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 20:14:43.210224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 20:14:43.216487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3866 20:14:43.219744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3867 20:14:43.223567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3868 20:14:43.223647 [ANA_INIT] flow start
3869 20:14:43.226820 [ANA_INIT] PLL >>>>>>>>
3870 20:14:43.229933 [ANA_INIT] PLL <<<<<<<<
3871 20:14:43.230052 [ANA_INIT] MIDPI >>>>>>>>
3872 20:14:43.233816 [ANA_INIT] MIDPI <<<<<<<<
3873 20:14:43.236943 [ANA_INIT] DLL >>>>>>>>
3874 20:14:43.237069 [ANA_INIT] flow end
3875 20:14:43.243333 ============ LP4 DIFF to SE enter ============
3876 20:14:43.246733 ============ LP4 DIFF to SE exit ============
3877 20:14:43.250054 [ANA_INIT] <<<<<<<<<<<<<
3878 20:14:43.250182 [Flow] Enable top DCM control >>>>>
3879 20:14:43.253626 [Flow] Enable top DCM control <<<<<
3880 20:14:43.256583 Enable DLL master slave shuffle
3881 20:14:43.263846 ==============================================================
3882 20:14:43.266868 Gating Mode config
3883 20:14:43.270190 ==============================================================
3884 20:14:43.273217 Config description:
3885 20:14:43.283469 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 20:14:43.289743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 20:14:43.293372 SELPH_MODE 0: By rank 1: By Phase
3888 20:14:43.299762 ==============================================================
3889 20:14:43.303166 GAT_TRACK_EN = 1
3890 20:14:43.306696 RX_GATING_MODE = 2
3891 20:14:43.310053 RX_GATING_TRACK_MODE = 2
3892 20:14:43.310137 SELPH_MODE = 1
3893 20:14:43.312830 PICG_EARLY_EN = 1
3894 20:14:43.316369 VALID_LAT_VALUE = 1
3895 20:14:43.323252 ==============================================================
3896 20:14:43.326531 Enter into Gating configuration >>>>
3897 20:14:43.329763 Exit from Gating configuration <<<<
3898 20:14:43.333145 Enter into DVFS_PRE_config >>>>>
3899 20:14:43.343572 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 20:14:43.346674 Exit from DVFS_PRE_config <<<<<
3901 20:14:43.349894 Enter into PICG configuration >>>>
3902 20:14:43.352917 Exit from PICG configuration <<<<
3903 20:14:43.356539 [RX_INPUT] configuration >>>>>
3904 20:14:43.360155 [RX_INPUT] configuration <<<<<
3905 20:14:43.362975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 20:14:43.369722 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 20:14:43.376449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 20:14:43.382747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 20:14:43.386535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 20:14:43.392969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 20:14:43.399413 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 20:14:43.402643 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 20:14:43.406361 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 20:14:43.409453 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 20:14:43.413200 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 20:14:43.419252 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 20:14:43.422810 ===================================
3918 20:14:43.426149 LPDDR4 DRAM CONFIGURATION
3919 20:14:43.426230 ===================================
3920 20:14:43.429821 EX_ROW_EN[0] = 0x0
3921 20:14:43.432780 EX_ROW_EN[1] = 0x0
3922 20:14:43.432862 LP4Y_EN = 0x0
3923 20:14:43.436106 WORK_FSP = 0x0
3924 20:14:43.436215 WL = 0x2
3925 20:14:43.439878 RL = 0x2
3926 20:14:43.439952 BL = 0x2
3927 20:14:43.443150 RPST = 0x0
3928 20:14:43.443226 RD_PRE = 0x0
3929 20:14:43.446180 WR_PRE = 0x1
3930 20:14:43.446251 WR_PST = 0x0
3931 20:14:43.449960 DBI_WR = 0x0
3932 20:14:43.450061 DBI_RD = 0x0
3933 20:14:43.453249 OTF = 0x1
3934 20:14:43.456534 ===================================
3935 20:14:43.459646 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 20:14:43.462828 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 20:14:43.469842 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 20:14:43.472787 ===================================
3939 20:14:43.472890 LPDDR4 DRAM CONFIGURATION
3940 20:14:43.476315 ===================================
3941 20:14:43.479454 EX_ROW_EN[0] = 0x10
3942 20:14:43.483254 EX_ROW_EN[1] = 0x0
3943 20:14:43.483367 LP4Y_EN = 0x0
3944 20:14:43.486228 WORK_FSP = 0x0
3945 20:14:43.486329 WL = 0x2
3946 20:14:43.489433 RL = 0x2
3947 20:14:43.489537 BL = 0x2
3948 20:14:43.493254 RPST = 0x0
3949 20:14:43.493367 RD_PRE = 0x0
3950 20:14:43.496388 WR_PRE = 0x1
3951 20:14:43.496492 WR_PST = 0x0
3952 20:14:43.499311 DBI_WR = 0x0
3953 20:14:43.499413 DBI_RD = 0x0
3954 20:14:43.502588 OTF = 0x1
3955 20:14:43.506172 ===================================
3956 20:14:43.512605 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 20:14:43.516339 nWR fixed to 30
3958 20:14:43.516446 [ModeRegInit_LP4] CH0 RK0
3959 20:14:43.519313 [ModeRegInit_LP4] CH0 RK1
3960 20:14:43.522510 [ModeRegInit_LP4] CH1 RK0
3961 20:14:43.526394 [ModeRegInit_LP4] CH1 RK1
3962 20:14:43.526478 match AC timing 17
3963 20:14:43.529445 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 20:14:43.535847 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 20:14:43.538894 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 20:14:43.542627 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 20:14:43.549476 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 20:14:43.549558 ==
3969 20:14:43.552796 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 20:14:43.555958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 20:14:43.556042 ==
3972 20:14:43.562324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 20:14:43.568920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3974 20:14:43.572171 [CA 0] Center 36 (5~67) winsize 63
3975 20:14:43.575955 [CA 1] Center 36 (5~67) winsize 63
3976 20:14:43.579333 [CA 2] Center 33 (3~64) winsize 62
3977 20:14:43.582333 [CA 3] Center 33 (2~64) winsize 63
3978 20:14:43.586108 [CA 4] Center 33 (2~64) winsize 63
3979 20:14:43.588856 [CA 5] Center 32 (2~63) winsize 62
3980 20:14:43.588975
3981 20:14:43.592116 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3982 20:14:43.592237
3983 20:14:43.595359 [CATrainingPosCal] consider 1 rank data
3984 20:14:43.599219 u2DelayCellTimex100 = 270/100 ps
3985 20:14:43.602472 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3986 20:14:43.605554 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3987 20:14:43.608541 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3988 20:14:43.611909 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3989 20:14:43.615442 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3990 20:14:43.618524 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3991 20:14:43.618646
3992 20:14:43.625385 CA PerBit enable=1, Macro0, CA PI delay=32
3993 20:14:43.625508
3994 20:14:43.625623 [CBTSetCACLKResult] CA Dly = 32
3995 20:14:43.628656 CS Dly: 5 (0~36)
3996 20:14:43.628761 ==
3997 20:14:43.632193 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 20:14:43.635654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 20:14:43.635761 ==
4000 20:14:43.641876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 20:14:43.648509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4002 20:14:43.651732 [CA 0] Center 35 (5~66) winsize 62
4003 20:14:43.655515 [CA 1] Center 36 (5~67) winsize 63
4004 20:14:43.658806 [CA 2] Center 34 (3~65) winsize 63
4005 20:14:43.661990 [CA 3] Center 33 (2~64) winsize 63
4006 20:14:43.665112 [CA 4] Center 33 (2~64) winsize 63
4007 20:14:43.668929 [CA 5] Center 32 (2~63) winsize 62
4008 20:14:43.669053
4009 20:14:43.671957 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4010 20:14:43.672085
4011 20:14:43.675262 [CATrainingPosCal] consider 2 rank data
4012 20:14:43.678556 u2DelayCellTimex100 = 270/100 ps
4013 20:14:43.681843 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4014 20:14:43.684991 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4015 20:14:43.688699 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4016 20:14:43.691825 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
4017 20:14:43.694999 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4018 20:14:43.698159 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4019 20:14:43.701724
4020 20:14:43.704888 CA PerBit enable=1, Macro0, CA PI delay=32
4021 20:14:43.704972
4022 20:14:43.708831 [CBTSetCACLKResult] CA Dly = 32
4023 20:14:43.708914 CS Dly: 5 (0~36)
4024 20:14:43.708981
4025 20:14:43.711422 ----->DramcWriteLeveling(PI) begin...
4026 20:14:43.711507 ==
4027 20:14:43.714976 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 20:14:43.718462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 20:14:43.721800 ==
4030 20:14:43.721886 Write leveling (Byte 0): 34 => 34
4031 20:14:43.725075 Write leveling (Byte 1): 30 => 30
4032 20:14:43.728500 DramcWriteLeveling(PI) end<-----
4033 20:14:43.728609
4034 20:14:43.728705 ==
4035 20:14:43.731484 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 20:14:43.738161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 20:14:43.738273 ==
4038 20:14:43.738368 [Gating] SW mode calibration
4039 20:14:43.748192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 20:14:43.752058 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 20:14:43.755000 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 20:14:43.761476 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 20:14:43.765095 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 20:14:43.768302 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
4045 20:14:43.774546 0 9 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
4046 20:14:43.778323 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 20:14:43.781508 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 20:14:43.788192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 20:14:43.791301 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 20:14:43.794556 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 20:14:43.801412 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 20:14:43.804755 0 10 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
4053 20:14:43.808542 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
4054 20:14:43.814520 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 20:14:43.818237 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 20:14:43.821549 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 20:14:43.828323 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 20:14:43.831571 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 20:14:43.834885 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 20:14:43.838307 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 20:14:43.845175 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 20:14:43.848266 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 20:14:43.851717 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 20:14:43.857888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 20:14:43.861454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 20:14:43.868015 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 20:14:43.870936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 20:14:43.874573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 20:14:43.880778 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 20:14:43.884094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 20:14:43.887818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 20:14:43.891144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 20:14:43.897574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 20:14:43.900722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 20:14:43.907596 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 20:14:43.910808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4077 20:14:43.913876 Total UI for P1: 0, mck2ui 16
4078 20:14:43.917547 best dqsien dly found for B0: ( 0, 13, 10)
4079 20:14:43.920735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4080 20:14:43.923861 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 20:14:43.927603 Total UI for P1: 0, mck2ui 16
4082 20:14:43.930444 best dqsien dly found for B1: ( 0, 13, 16)
4083 20:14:43.936996 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4084 20:14:43.940759 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4085 20:14:43.940850
4086 20:14:43.943805 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4087 20:14:43.947018 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4088 20:14:43.951117 [Gating] SW calibration Done
4089 20:14:43.951252 ==
4090 20:14:43.953947 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 20:14:43.957032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 20:14:43.957116 ==
4093 20:14:43.960609 RX Vref Scan: 0
4094 20:14:43.960688
4095 20:14:43.960753 RX Vref 0 -> 0, step: 1
4096 20:14:43.960817
4097 20:14:43.963966 RX Delay -230 -> 252, step: 16
4098 20:14:43.967163 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4099 20:14:43.974018 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4100 20:14:43.976931 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4101 20:14:43.980241 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4102 20:14:43.983482 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4103 20:14:43.986994 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4104 20:14:43.993812 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4105 20:14:43.996888 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4106 20:14:44.000112 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4107 20:14:44.004047 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4108 20:14:44.010452 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4109 20:14:44.013586 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4110 20:14:44.016811 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4111 20:14:44.020087 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4112 20:14:44.027074 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4113 20:14:44.030171 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4114 20:14:44.030248 ==
4115 20:14:44.033342 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 20:14:44.037004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 20:14:44.037135 ==
4118 20:14:44.040204 DQS Delay:
4119 20:14:44.040325 DQS0 = 0, DQS1 = 0
4120 20:14:44.040447 DQM Delay:
4121 20:14:44.043697 DQM0 = 50, DQM1 = 46
4122 20:14:44.043804 DQ Delay:
4123 20:14:44.047227 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4124 20:14:44.050356 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4125 20:14:44.053861 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4126 20:14:44.056725 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4127 20:14:44.056849
4128 20:14:44.056967
4129 20:14:44.057082 ==
4130 20:14:44.060041 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 20:14:44.063610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 20:14:44.066688 ==
4133 20:14:44.066818
4134 20:14:44.066928
4135 20:14:44.067040 TX Vref Scan disable
4136 20:14:44.070212 == TX Byte 0 ==
4137 20:14:44.073629 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4138 20:14:44.080041 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4139 20:14:44.080169 == TX Byte 1 ==
4140 20:14:44.083153 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4141 20:14:44.089781 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4142 20:14:44.089894 ==
4143 20:14:44.093285 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 20:14:44.096382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 20:14:44.096467 ==
4146 20:14:44.096533
4147 20:14:44.096637
4148 20:14:44.099835 TX Vref Scan disable
4149 20:14:44.103255 == TX Byte 0 ==
4150 20:14:44.106390 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4151 20:14:44.109610 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4152 20:14:44.112822 == TX Byte 1 ==
4153 20:14:44.116632 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4154 20:14:44.120018 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4155 20:14:44.120128
4156 20:14:44.120220 [DATLAT]
4157 20:14:44.123196 Freq=600, CH0 RK0
4158 20:14:44.123296
4159 20:14:44.126290 DATLAT Default: 0x9
4160 20:14:44.126397 0, 0xFFFF, sum = 0
4161 20:14:44.129449 1, 0xFFFF, sum = 0
4162 20:14:44.129560 2, 0xFFFF, sum = 0
4163 20:14:44.132689 3, 0xFFFF, sum = 0
4164 20:14:44.132776 4, 0xFFFF, sum = 0
4165 20:14:44.135964 5, 0xFFFF, sum = 0
4166 20:14:44.136068 6, 0xFFFF, sum = 0
4167 20:14:44.139917 7, 0xFFFF, sum = 0
4168 20:14:44.140029 8, 0x0, sum = 1
4169 20:14:44.143014 9, 0x0, sum = 2
4170 20:14:44.143146 10, 0x0, sum = 3
4171 20:14:44.146312 11, 0x0, sum = 4
4172 20:14:44.146439 best_step = 9
4173 20:14:44.146547
4174 20:14:44.146655 ==
4175 20:14:44.149391 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 20:14:44.153007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 20:14:44.153132 ==
4178 20:14:44.155931 RX Vref Scan: 1
4179 20:14:44.156056
4180 20:14:44.159328 RX Vref 0 -> 0, step: 1
4181 20:14:44.159411
4182 20:14:44.159487 RX Delay -163 -> 252, step: 8
4183 20:14:44.159587
4184 20:14:44.162855 Set Vref, RX VrefLevel [Byte0]: 57
4185 20:14:44.165748 [Byte1]: 46
4186 20:14:44.170244
4187 20:14:44.170354 Final RX Vref Byte 0 = 57 to rank0
4188 20:14:44.173724 Final RX Vref Byte 1 = 46 to rank0
4189 20:14:44.177423 Final RX Vref Byte 0 = 57 to rank1
4190 20:14:44.180602 Final RX Vref Byte 1 = 46 to rank1==
4191 20:14:44.184115 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 20:14:44.190650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 20:14:44.190762 ==
4194 20:14:44.190859 DQS Delay:
4195 20:14:44.190960 DQS0 = 0, DQS1 = 0
4196 20:14:44.193881 DQM Delay:
4197 20:14:44.193985 DQM0 = 53, DQM1 = 46
4198 20:14:44.197147 DQ Delay:
4199 20:14:44.200339 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4200 20:14:44.200451 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4201 20:14:44.203770 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4202 20:14:44.210556 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4203 20:14:44.210684
4204 20:14:44.210801
4205 20:14:44.216963 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4206 20:14:44.220046 CH0 RK0: MR19=808, MR18=6D60
4207 20:14:44.227118 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4208 20:14:44.227204
4209 20:14:44.230233 ----->DramcWriteLeveling(PI) begin...
4210 20:14:44.230344 ==
4211 20:14:44.233436 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 20:14:44.237089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 20:14:44.237170 ==
4214 20:14:44.240443 Write leveling (Byte 0): 35 => 35
4215 20:14:44.243621 Write leveling (Byte 1): 31 => 31
4216 20:14:44.246818 DramcWriteLeveling(PI) end<-----
4217 20:14:44.246928
4218 20:14:44.247022 ==
4219 20:14:44.250007 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 20:14:44.253792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 20:14:44.253896 ==
4222 20:14:44.256855 [Gating] SW mode calibration
4223 20:14:44.263783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4224 20:14:44.270427 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4225 20:14:44.273265 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 20:14:44.276728 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 20:14:44.283636 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 20:14:44.286640 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1)
4229 20:14:44.290139 0 9 16 | B1->B0 | 2929 2424 | 1 0 | (1 0) (1 0)
4230 20:14:44.296884 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 20:14:44.300011 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 20:14:44.303201 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 20:14:44.310309 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 20:14:44.313456 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 20:14:44.316749 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 20:14:44.323420 0 10 12 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
4237 20:14:44.326847 0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
4238 20:14:44.330234 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 20:14:44.336538 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 20:14:44.340368 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 20:14:44.343516 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 20:14:44.349909 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 20:14:44.353033 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 20:14:44.356361 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4245 20:14:44.363440 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4246 20:14:44.366580 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 20:14:44.369730 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 20:14:44.376628 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 20:14:44.379865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 20:14:44.383484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 20:14:44.389724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 20:14:44.393278 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 20:14:44.396207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 20:14:44.402850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 20:14:44.406332 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 20:14:44.410111 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 20:14:44.413169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 20:14:44.419420 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 20:14:44.423358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 20:14:44.426522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4261 20:14:44.433082 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 20:14:44.436189 Total UI for P1: 0, mck2ui 16
4263 20:14:44.439848 best dqsien dly found for B0: ( 0, 13, 12)
4264 20:14:44.439961 Total UI for P1: 0, mck2ui 16
4265 20:14:44.446680 best dqsien dly found for B1: ( 0, 13, 14)
4266 20:14:44.449854 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4267 20:14:44.452913 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4268 20:14:44.453015
4269 20:14:44.456502 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4270 20:14:44.459702 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4271 20:14:44.462895 [Gating] SW calibration Done
4272 20:14:44.463009 ==
4273 20:14:44.466235 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 20:14:44.469431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 20:14:44.469535 ==
4276 20:14:44.472642 RX Vref Scan: 0
4277 20:14:44.472729
4278 20:14:44.472800 RX Vref 0 -> 0, step: 1
4279 20:14:44.476453
4280 20:14:44.476537 RX Delay -230 -> 252, step: 16
4281 20:14:44.483116 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4282 20:14:44.486331 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4283 20:14:44.489559 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4284 20:14:44.492813 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4285 20:14:44.496508 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4286 20:14:44.502854 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4287 20:14:44.506184 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4288 20:14:44.509564 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4289 20:14:44.512967 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4290 20:14:44.519575 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4291 20:14:44.522724 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4292 20:14:44.526117 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4293 20:14:44.529874 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4294 20:14:44.536411 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4295 20:14:44.539779 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4296 20:14:44.543010 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4297 20:14:44.543114 ==
4298 20:14:44.546129 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 20:14:44.549247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 20:14:44.549355 ==
4301 20:14:44.553057 DQS Delay:
4302 20:14:44.553157 DQS0 = 0, DQS1 = 0
4303 20:14:44.556222 DQM Delay:
4304 20:14:44.556332 DQM0 = 51, DQM1 = 43
4305 20:14:44.556424 DQ Delay:
4306 20:14:44.559271 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4307 20:14:44.562935 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4308 20:14:44.566151 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4309 20:14:44.569393 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4310 20:14:44.569505
4311 20:14:44.569600
4312 20:14:44.572741 ==
4313 20:14:44.572844 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 20:14:44.579134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 20:14:44.579246 ==
4316 20:14:44.579343
4317 20:14:44.579436
4318 20:14:44.582901 TX Vref Scan disable
4319 20:14:44.583006 == TX Byte 0 ==
4320 20:14:44.585730 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4321 20:14:44.592524 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4322 20:14:44.592627 == TX Byte 1 ==
4323 20:14:44.596402 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4324 20:14:44.602773 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4325 20:14:44.602880 ==
4326 20:14:44.605896 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 20:14:44.609628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 20:14:44.609713 ==
4329 20:14:44.609779
4330 20:14:44.609840
4331 20:14:44.612612 TX Vref Scan disable
4332 20:14:44.615942 == TX Byte 0 ==
4333 20:14:44.619137 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4334 20:14:44.622661 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4335 20:14:44.625810 == TX Byte 1 ==
4336 20:14:44.629052 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4337 20:14:44.632491 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4338 20:14:44.632601
4339 20:14:44.635787 [DATLAT]
4340 20:14:44.635893 Freq=600, CH0 RK1
4341 20:14:44.635989
4342 20:14:44.639483 DATLAT Default: 0x9
4343 20:14:44.639589 0, 0xFFFF, sum = 0
4344 20:14:44.642663 1, 0xFFFF, sum = 0
4345 20:14:44.642768 2, 0xFFFF, sum = 0
4346 20:14:44.645789 3, 0xFFFF, sum = 0
4347 20:14:44.645895 4, 0xFFFF, sum = 0
4348 20:14:44.649002 5, 0xFFFF, sum = 0
4349 20:14:44.649108 6, 0xFFFF, sum = 0
4350 20:14:44.653060 7, 0xFFFF, sum = 0
4351 20:14:44.653166 8, 0x0, sum = 1
4352 20:14:44.656061 9, 0x0, sum = 2
4353 20:14:44.656162 10, 0x0, sum = 3
4354 20:14:44.659189 11, 0x0, sum = 4
4355 20:14:44.659303 best_step = 9
4356 20:14:44.659403
4357 20:14:44.659511 ==
4358 20:14:44.662526 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 20:14:44.666235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 20:14:44.666345 ==
4361 20:14:44.669542 RX Vref Scan: 0
4362 20:14:44.669653
4363 20:14:44.672630 RX Vref 0 -> 0, step: 1
4364 20:14:44.672745
4365 20:14:44.672840 RX Delay -163 -> 252, step: 8
4366 20:14:44.680659 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4367 20:14:44.684057 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4368 20:14:44.687451 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4369 20:14:44.690922 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4370 20:14:44.694022 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4371 20:14:44.700941 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4372 20:14:44.704143 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4373 20:14:44.707450 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4374 20:14:44.710552 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4375 20:14:44.714351 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4376 20:14:44.720646 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4377 20:14:44.723684 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4378 20:14:44.727413 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4379 20:14:44.730699 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4380 20:14:44.733840 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4381 20:14:44.740664 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4382 20:14:44.740750 ==
4383 20:14:44.744004 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 20:14:44.747264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 20:14:44.747350 ==
4386 20:14:44.747417 DQS Delay:
4387 20:14:44.750513 DQS0 = 0, DQS1 = 0
4388 20:14:44.750620 DQM Delay:
4389 20:14:44.754381 DQM0 = 54, DQM1 = 46
4390 20:14:44.754458 DQ Delay:
4391 20:14:44.757153 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4392 20:14:44.760337 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4393 20:14:44.764060 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4394 20:14:44.767238 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4395 20:14:44.767362
4396 20:14:44.767477
4397 20:14:44.777380 [DQSOSCAuto] RK1, (LSB)MR18= 0x6628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4398 20:14:44.777511 CH0 RK1: MR19=808, MR18=6628
4399 20:14:44.783600 CH0_RK1: MR19=0x808, MR18=0x6628, DQSOSC=390, MR23=63, INC=172, DEC=114
4400 20:14:44.787499 [RxdqsGatingPostProcess] freq 600
4401 20:14:44.793716 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 20:14:44.797341 Pre-setting of DQS Precalculation
4403 20:14:44.800275 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 20:14:44.800367 ==
4405 20:14:44.803587 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 20:14:44.806892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 20:14:44.807003 ==
4408 20:14:44.813712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 20:14:44.820300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4410 20:14:44.823864 [CA 0] Center 36 (5~67) winsize 63
4411 20:14:44.827015 [CA 1] Center 36 (5~67) winsize 63
4412 20:14:44.830816 [CA 2] Center 34 (4~65) winsize 62
4413 20:14:44.834070 [CA 3] Center 34 (4~65) winsize 62
4414 20:14:44.837347 [CA 4] Center 34 (4~65) winsize 62
4415 20:14:44.840526 [CA 5] Center 33 (3~64) winsize 62
4416 20:14:44.840648
4417 20:14:44.843925 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4418 20:14:44.844049
4419 20:14:44.846931 [CATrainingPosCal] consider 1 rank data
4420 20:14:44.850612 u2DelayCellTimex100 = 270/100 ps
4421 20:14:44.853822 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4422 20:14:44.857484 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4423 20:14:44.860790 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 20:14:44.863567 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 20:14:44.866813 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 20:14:44.874096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 20:14:44.874225
4428 20:14:44.876935 CA PerBit enable=1, Macro0, CA PI delay=33
4429 20:14:44.877062
4430 20:14:44.880768 [CBTSetCACLKResult] CA Dly = 33
4431 20:14:44.880889 CS Dly: 5 (0~36)
4432 20:14:44.881001 ==
4433 20:14:44.883920 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 20:14:44.886821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 20:14:44.889962 ==
4436 20:14:44.893807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 20:14:44.900061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4438 20:14:44.903339 [CA 0] Center 36 (5~67) winsize 63
4439 20:14:44.907135 [CA 1] Center 36 (5~67) winsize 63
4440 20:14:44.910217 [CA 2] Center 34 (4~65) winsize 62
4441 20:14:44.913324 [CA 3] Center 34 (4~65) winsize 62
4442 20:14:44.916901 [CA 4] Center 35 (4~66) winsize 63
4443 20:14:44.920344 [CA 5] Center 34 (4~64) winsize 61
4444 20:14:44.920473
4445 20:14:44.923438 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4446 20:14:44.923557
4447 20:14:44.926661 [CATrainingPosCal] consider 2 rank data
4448 20:14:44.930169 u2DelayCellTimex100 = 270/100 ps
4449 20:14:44.933500 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4450 20:14:44.936987 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4451 20:14:44.940241 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4452 20:14:44.943370 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4453 20:14:44.950319 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4454 20:14:44.953563 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4455 20:14:44.953669
4456 20:14:44.956751 CA PerBit enable=1, Macro0, CA PI delay=34
4457 20:14:44.956875
4458 20:14:44.959933 [CBTSetCACLKResult] CA Dly = 34
4459 20:14:44.960058 CS Dly: 6 (0~38)
4460 20:14:44.960173
4461 20:14:44.963629 ----->DramcWriteLeveling(PI) begin...
4462 20:14:44.963757 ==
4463 20:14:44.966485 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 20:14:44.973422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 20:14:44.973552 ==
4466 20:14:44.976515 Write leveling (Byte 0): 30 => 30
4467 20:14:44.979984 Write leveling (Byte 1): 33 => 33
4468 20:14:44.980109 DramcWriteLeveling(PI) end<-----
4469 20:14:44.980224
4470 20:14:44.983150 ==
4471 20:14:44.986844 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 20:14:44.989809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 20:14:44.989935 ==
4474 20:14:44.993213 [Gating] SW mode calibration
4475 20:14:45.000033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 20:14:45.003210 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 20:14:45.010141 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 20:14:45.013443 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 20:14:45.016720 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 20:14:45.023542 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
4481 20:14:45.026818 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 20:14:45.030119 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 20:14:45.036739 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 20:14:45.040029 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 20:14:45.043253 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 20:14:45.049666 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 20:14:45.053016 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4488 20:14:45.056594 0 10 12 | B1->B0 | 3838 3636 | 0 0 | (1 1) (0 0)
4489 20:14:45.063160 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 20:14:45.066271 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 20:14:45.069425 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 20:14:45.076374 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 20:14:45.079566 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 20:14:45.082724 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 20:14:45.086466 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 20:14:45.092811 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4497 20:14:45.095900 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 20:14:45.099643 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 20:14:45.106024 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 20:14:45.109575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 20:14:45.112721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 20:14:45.119211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 20:14:45.122975 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 20:14:45.126377 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 20:14:45.132834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 20:14:45.136043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 20:14:45.139296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 20:14:45.146140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 20:14:45.149381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 20:14:45.153092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 20:14:45.159866 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 20:14:45.163269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 20:14:45.166013 Total UI for P1: 0, mck2ui 16
4514 20:14:45.169312 best dqsien dly found for B0: ( 0, 13, 10)
4515 20:14:45.172787 Total UI for P1: 0, mck2ui 16
4516 20:14:45.176102 best dqsien dly found for B1: ( 0, 13, 10)
4517 20:14:45.179317 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4518 20:14:45.182768 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4519 20:14:45.182884
4520 20:14:45.186133 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4521 20:14:45.189333 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4522 20:14:45.192530 [Gating] SW calibration Done
4523 20:14:45.192631 ==
4524 20:14:45.195732 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 20:14:45.199561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 20:14:45.202734 ==
4527 20:14:45.202838 RX Vref Scan: 0
4528 20:14:45.202942
4529 20:14:45.205941 RX Vref 0 -> 0, step: 1
4530 20:14:45.206049
4531 20:14:45.209690 RX Delay -230 -> 252, step: 16
4532 20:14:45.212813 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4533 20:14:45.215996 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4534 20:14:45.219086 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4535 20:14:45.222681 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4536 20:14:45.229478 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4537 20:14:45.232787 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4538 20:14:45.235973 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4539 20:14:45.238942 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4540 20:14:45.245777 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4541 20:14:45.249056 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4542 20:14:45.252339 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4543 20:14:45.255407 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4544 20:14:45.262231 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4545 20:14:45.265292 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4546 20:14:45.268409 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4547 20:14:45.272229 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4548 20:14:45.272333 ==
4549 20:14:45.275200 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 20:14:45.281990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 20:14:45.282100 ==
4552 20:14:45.282202 DQS Delay:
4553 20:14:45.282294 DQS0 = 0, DQS1 = 0
4554 20:14:45.285724 DQM Delay:
4555 20:14:45.285827 DQM0 = 49, DQM1 = 50
4556 20:14:45.288496 DQ Delay:
4557 20:14:45.292257 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4558 20:14:45.292371 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4559 20:14:45.295128 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4560 20:14:45.298836 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4561 20:14:45.301859
4562 20:14:45.301962
4563 20:14:45.302055 ==
4564 20:14:45.305813 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 20:14:45.308916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 20:14:45.309016 ==
4567 20:14:45.309112
4568 20:14:45.309190
4569 20:14:45.312325 TX Vref Scan disable
4570 20:14:45.312400 == TX Byte 0 ==
4571 20:14:45.318606 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4572 20:14:45.321848 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4573 20:14:45.321925 == TX Byte 1 ==
4574 20:14:45.328497 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4575 20:14:45.332129 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4576 20:14:45.332211 ==
4577 20:14:45.335267 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 20:14:45.338446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 20:14:45.338577 ==
4580 20:14:45.338686
4581 20:14:45.338791
4582 20:14:45.342182 TX Vref Scan disable
4583 20:14:45.345189 == TX Byte 0 ==
4584 20:14:45.348641 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 20:14:45.351962 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 20:14:45.355325 == TX Byte 1 ==
4587 20:14:45.358463 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4588 20:14:45.362030 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4589 20:14:45.365215
4590 20:14:45.365318 [DATLAT]
4591 20:14:45.365419 Freq=600, CH1 RK0
4592 20:14:45.365510
4593 20:14:45.368129 DATLAT Default: 0x9
4594 20:14:45.368238 0, 0xFFFF, sum = 0
4595 20:14:45.371693 1, 0xFFFF, sum = 0
4596 20:14:45.371800 2, 0xFFFF, sum = 0
4597 20:14:45.374835 3, 0xFFFF, sum = 0
4598 20:14:45.374958 4, 0xFFFF, sum = 0
4599 20:14:45.378698 5, 0xFFFF, sum = 0
4600 20:14:45.378804 6, 0xFFFF, sum = 0
4601 20:14:45.381547 7, 0xFFFF, sum = 0
4602 20:14:45.381663 8, 0x0, sum = 1
4603 20:14:45.385396 9, 0x0, sum = 2
4604 20:14:45.385503 10, 0x0, sum = 3
4605 20:14:45.388421 11, 0x0, sum = 4
4606 20:14:45.388499 best_step = 9
4607 20:14:45.388598
4608 20:14:45.388695 ==
4609 20:14:45.391477 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 20:14:45.398423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 20:14:45.398531 ==
4612 20:14:45.398631 RX Vref Scan: 1
4613 20:14:45.398730
4614 20:14:45.402116 RX Vref 0 -> 0, step: 1
4615 20:14:45.402202
4616 20:14:45.404997 RX Delay -163 -> 252, step: 8
4617 20:14:45.405071
4618 20:14:45.408647 Set Vref, RX VrefLevel [Byte0]: 54
4619 20:14:45.412034 [Byte1]: 54
4620 20:14:45.412113
4621 20:14:45.414771 Final RX Vref Byte 0 = 54 to rank0
4622 20:14:45.418135 Final RX Vref Byte 1 = 54 to rank0
4623 20:14:45.421739 Final RX Vref Byte 0 = 54 to rank1
4624 20:14:45.424903 Final RX Vref Byte 1 = 54 to rank1==
4625 20:14:45.428174 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 20:14:45.432025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 20:14:45.432139 ==
4628 20:14:45.435267 DQS Delay:
4629 20:14:45.435370 DQS0 = 0, DQS1 = 0
4630 20:14:45.435471 DQM Delay:
4631 20:14:45.438367 DQM0 = 48, DQM1 = 44
4632 20:14:45.438473 DQ Delay:
4633 20:14:45.442193 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4634 20:14:45.445385 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4635 20:14:45.448550 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4636 20:14:45.451751 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4637 20:14:45.451862
4638 20:14:45.451957
4639 20:14:45.461968 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4640 20:14:45.462075 CH1 RK0: MR19=808, MR18=496E
4641 20:14:45.468218 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4642 20:14:45.468331
4643 20:14:45.471713 ----->DramcWriteLeveling(PI) begin...
4644 20:14:45.471798 ==
4645 20:14:45.474905 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 20:14:45.481561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 20:14:45.481680 ==
4648 20:14:45.485089 Write leveling (Byte 0): 32 => 32
4649 20:14:45.488537 Write leveling (Byte 1): 30 => 30
4650 20:14:45.488642 DramcWriteLeveling(PI) end<-----
4651 20:14:45.488727
4652 20:14:45.491564 ==
4653 20:14:45.494806 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 20:14:45.498529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 20:14:45.498636 ==
4656 20:14:45.501740 [Gating] SW mode calibration
4657 20:14:45.508455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4658 20:14:45.511740 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4659 20:14:45.517951 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 20:14:45.521723 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 20:14:45.524560 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 20:14:45.531271 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4663 20:14:45.534813 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 20:14:45.538008 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 20:14:45.544914 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 20:14:45.547992 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 20:14:45.551153 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 20:14:45.558210 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 20:14:45.561434 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 20:14:45.564710 0 10 12 | B1->B0 | 3737 3535 | 0 0 | (0 0) (0 0)
4671 20:14:45.571667 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 20:14:45.574816 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 20:14:45.577925 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 20:14:45.584594 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 20:14:45.588036 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 20:14:45.591349 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 20:14:45.597737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4678 20:14:45.601129 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 20:14:45.604609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 20:14:45.610798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 20:14:45.614470 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 20:14:45.618090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 20:14:45.624391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 20:14:45.627655 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 20:14:45.631410 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 20:14:45.634384 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 20:14:45.640977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 20:14:45.644465 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 20:14:45.647476 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 20:14:45.654124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 20:14:45.657249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 20:14:45.661060 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 20:14:45.667545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 20:14:45.670773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4695 20:14:45.674145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4696 20:14:45.677342 Total UI for P1: 0, mck2ui 16
4697 20:14:45.680268 best dqsien dly found for B1: ( 0, 13, 12)
4698 20:14:45.687553 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 20:14:45.690746 Total UI for P1: 0, mck2ui 16
4700 20:14:45.693880 best dqsien dly found for B0: ( 0, 13, 14)
4701 20:14:45.697138 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4702 20:14:45.700415 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4703 20:14:45.700519
4704 20:14:45.703668 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4705 20:14:45.707071 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4706 20:14:45.710445 [Gating] SW calibration Done
4707 20:14:45.710539 ==
4708 20:14:45.713793 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 20:14:45.716768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 20:14:45.716871 ==
4711 20:14:45.720305 RX Vref Scan: 0
4712 20:14:45.720386
4713 20:14:45.723354 RX Vref 0 -> 0, step: 1
4714 20:14:45.723456
4715 20:14:45.723551 RX Delay -230 -> 252, step: 16
4716 20:14:45.729882 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4717 20:14:45.733307 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4718 20:14:45.736658 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4719 20:14:45.740312 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4720 20:14:45.746631 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4721 20:14:45.750194 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4722 20:14:45.753458 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4723 20:14:45.757064 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4724 20:14:45.759867 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4725 20:14:45.766993 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4726 20:14:45.770317 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4727 20:14:45.773422 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4728 20:14:45.776673 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4729 20:14:45.783611 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4730 20:14:45.786724 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4731 20:14:45.790033 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4732 20:14:45.790124 ==
4733 20:14:45.793113 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 20:14:45.799571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 20:14:45.799688 ==
4736 20:14:45.799781 DQS Delay:
4737 20:14:45.799870 DQS0 = 0, DQS1 = 0
4738 20:14:45.802770 DQM Delay:
4739 20:14:45.802852 DQM0 = 50, DQM1 = 49
4740 20:14:45.806590 DQ Delay:
4741 20:14:45.809724 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4742 20:14:45.809806 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4743 20:14:45.812963 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4744 20:14:45.819908 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4745 20:14:45.820005
4746 20:14:45.820072
4747 20:14:45.820132 ==
4748 20:14:45.823313 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 20:14:45.826430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 20:14:45.826519 ==
4751 20:14:45.826601
4752 20:14:45.826676
4753 20:14:45.829508 TX Vref Scan disable
4754 20:14:45.829625 == TX Byte 0 ==
4755 20:14:45.836568 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4756 20:14:45.839862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4757 20:14:45.839992 == TX Byte 1 ==
4758 20:14:45.846308 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 20:14:45.849693 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 20:14:45.849805 ==
4761 20:14:45.853052 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 20:14:45.856160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 20:14:45.856260 ==
4764 20:14:45.856367
4765 20:14:45.856458
4766 20:14:45.859408 TX Vref Scan disable
4767 20:14:45.863140 == TX Byte 0 ==
4768 20:14:45.866003 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4769 20:14:45.869633 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4770 20:14:45.872635 == TX Byte 1 ==
4771 20:14:45.876356 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4772 20:14:45.879741 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4773 20:14:45.882651
4774 20:14:45.882735 [DATLAT]
4775 20:14:45.882800 Freq=600, CH1 RK1
4776 20:14:45.882862
4777 20:14:45.886271 DATLAT Default: 0x9
4778 20:14:45.886354 0, 0xFFFF, sum = 0
4779 20:14:45.889356 1, 0xFFFF, sum = 0
4780 20:14:45.889440 2, 0xFFFF, sum = 0
4781 20:14:45.892664 3, 0xFFFF, sum = 0
4782 20:14:45.896235 4, 0xFFFF, sum = 0
4783 20:14:45.896331 5, 0xFFFF, sum = 0
4784 20:14:45.899382 6, 0xFFFF, sum = 0
4785 20:14:45.899465 7, 0xFFFF, sum = 0
4786 20:14:45.902530 8, 0x0, sum = 1
4787 20:14:45.902615 9, 0x0, sum = 2
4788 20:14:45.902682 10, 0x0, sum = 3
4789 20:14:45.905788 11, 0x0, sum = 4
4790 20:14:45.905900 best_step = 9
4791 20:14:45.905993
4792 20:14:45.906082 ==
4793 20:14:45.909537 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 20:14:45.915944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 20:14:45.916053 ==
4796 20:14:45.916147 RX Vref Scan: 0
4797 20:14:45.916237
4798 20:14:45.919207 RX Vref 0 -> 0, step: 1
4799 20:14:45.919289
4800 20:14:45.922392 RX Delay -163 -> 252, step: 8
4801 20:14:45.925741 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4802 20:14:45.932790 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4803 20:14:45.935952 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4804 20:14:45.939154 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4805 20:14:45.942490 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4806 20:14:45.945526 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4807 20:14:45.952350 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4808 20:14:45.955915 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4809 20:14:45.958882 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4810 20:14:45.962478 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4811 20:14:45.965833 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4812 20:14:45.972582 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4813 20:14:45.975737 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4814 20:14:45.978757 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4815 20:14:45.982257 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4816 20:14:45.989113 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4817 20:14:45.989197 ==
4818 20:14:45.992059 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 20:14:45.995537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 20:14:45.995618 ==
4821 20:14:45.995683 DQS Delay:
4822 20:14:45.998606 DQS0 = 0, DQS1 = 0
4823 20:14:45.998683 DQM Delay:
4824 20:14:46.002493 DQM0 = 48, DQM1 = 45
4825 20:14:46.002594 DQ Delay:
4826 20:14:46.005624 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4827 20:14:46.008727 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4828 20:14:46.012128 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4829 20:14:46.015306 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4830 20:14:46.015409
4831 20:14:46.015511
4832 20:14:46.022404 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4833 20:14:46.025569 CH1 RK1: MR19=808, MR18=6A22
4834 20:14:46.032002 CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115
4835 20:14:46.035187 [RxdqsGatingPostProcess] freq 600
4836 20:14:46.042154 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4837 20:14:46.045430 Pre-setting of DQS Precalculation
4838 20:14:46.048588 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4839 20:14:46.055030 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4840 20:14:46.062054 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4841 20:14:46.062166
4842 20:14:46.062261
4843 20:14:46.065105 [Calibration Summary] 1200 Mbps
4844 20:14:46.068592 CH 0, Rank 0
4845 20:14:46.068702 SW Impedance : PASS
4846 20:14:46.071843 DUTY Scan : NO K
4847 20:14:46.074896 ZQ Calibration : PASS
4848 20:14:46.074977 Jitter Meter : NO K
4849 20:14:46.078441 CBT Training : PASS
4850 20:14:46.081653 Write leveling : PASS
4851 20:14:46.081736 RX DQS gating : PASS
4852 20:14:46.085314 RX DQ/DQS(RDDQC) : PASS
4853 20:14:46.085397 TX DQ/DQS : PASS
4854 20:14:46.088354 RX DATLAT : PASS
4855 20:14:46.091570 RX DQ/DQS(Engine): PASS
4856 20:14:46.091685 TX OE : NO K
4857 20:14:46.095401 All Pass.
4858 20:14:46.095500
4859 20:14:46.095594 CH 0, Rank 1
4860 20:14:46.098544 SW Impedance : PASS
4861 20:14:46.098627 DUTY Scan : NO K
4862 20:14:46.101698 ZQ Calibration : PASS
4863 20:14:46.104877 Jitter Meter : NO K
4864 20:14:46.104969 CBT Training : PASS
4865 20:14:46.108776 Write leveling : PASS
4866 20:14:46.111853 RX DQS gating : PASS
4867 20:14:46.111965 RX DQ/DQS(RDDQC) : PASS
4868 20:14:46.114822 TX DQ/DQS : PASS
4869 20:14:46.118247 RX DATLAT : PASS
4870 20:14:46.118332 RX DQ/DQS(Engine): PASS
4871 20:14:46.121383 TX OE : NO K
4872 20:14:46.121461 All Pass.
4873 20:14:46.121525
4874 20:14:46.124965 CH 1, Rank 0
4875 20:14:46.125042 SW Impedance : PASS
4876 20:14:46.128034 DUTY Scan : NO K
4877 20:14:46.131265 ZQ Calibration : PASS
4878 20:14:46.131342 Jitter Meter : NO K
4879 20:14:46.135291 CBT Training : PASS
4880 20:14:46.138619 Write leveling : PASS
4881 20:14:46.138700 RX DQS gating : PASS
4882 20:14:46.141509 RX DQ/DQS(RDDQC) : PASS
4883 20:14:46.141582 TX DQ/DQS : PASS
4884 20:14:46.144917 RX DATLAT : PASS
4885 20:14:46.148152 RX DQ/DQS(Engine): PASS
4886 20:14:46.148261 TX OE : NO K
4887 20:14:46.151510 All Pass.
4888 20:14:46.151591
4889 20:14:46.151666 CH 1, Rank 1
4890 20:14:46.154774 SW Impedance : PASS
4891 20:14:46.154864 DUTY Scan : NO K
4892 20:14:46.157936 ZQ Calibration : PASS
4893 20:14:46.161175 Jitter Meter : NO K
4894 20:14:46.161254 CBT Training : PASS
4895 20:14:46.164907 Write leveling : PASS
4896 20:14:46.168163 RX DQS gating : PASS
4897 20:14:46.168240 RX DQ/DQS(RDDQC) : PASS
4898 20:14:46.171412 TX DQ/DQS : PASS
4899 20:14:46.175054 RX DATLAT : PASS
4900 20:14:46.175133 RX DQ/DQS(Engine): PASS
4901 20:14:46.178165 TX OE : NO K
4902 20:14:46.178283 All Pass.
4903 20:14:46.178369
4904 20:14:46.181804 DramC Write-DBI off
4905 20:14:46.185021 PER_BANK_REFRESH: Hybrid Mode
4906 20:14:46.185103 TX_TRACKING: ON
4907 20:14:46.194619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4908 20:14:46.197689 [FAST_K] Save calibration result to emmc
4909 20:14:46.201129 dramc_set_vcore_voltage set vcore to 662500
4910 20:14:46.204489 Read voltage for 933, 3
4911 20:14:46.204572 Vio18 = 0
4912 20:14:46.204643 Vcore = 662500
4913 20:14:46.207900 Vdram = 0
4914 20:14:46.208000 Vddq = 0
4915 20:14:46.208099 Vmddr = 0
4916 20:14:46.214224 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4917 20:14:46.217938 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4918 20:14:46.221133 MEM_TYPE=3, freq_sel=17
4919 20:14:46.224393 sv_algorithm_assistance_LP4_1600
4920 20:14:46.227518 ============ PULL DRAM RESETB DOWN ============
4921 20:14:46.231205 ========== PULL DRAM RESETB DOWN end =========
4922 20:14:46.237798 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4923 20:14:46.240880 ===================================
4924 20:14:46.240994 LPDDR4 DRAM CONFIGURATION
4925 20:14:46.244013 ===================================
4926 20:14:46.247735 EX_ROW_EN[0] = 0x0
4927 20:14:46.250773 EX_ROW_EN[1] = 0x0
4928 20:14:46.250879 LP4Y_EN = 0x0
4929 20:14:46.254054 WORK_FSP = 0x0
4930 20:14:46.254177 WL = 0x3
4931 20:14:46.257379 RL = 0x3
4932 20:14:46.257485 BL = 0x2
4933 20:14:46.260642 RPST = 0x0
4934 20:14:46.260757 RD_PRE = 0x0
4935 20:14:46.264196 WR_PRE = 0x1
4936 20:14:46.264310 WR_PST = 0x0
4937 20:14:46.267251 DBI_WR = 0x0
4938 20:14:46.267349 DBI_RD = 0x0
4939 20:14:46.270715 OTF = 0x1
4940 20:14:46.273842 ===================================
4941 20:14:46.277168 ===================================
4942 20:14:46.277286 ANA top config
4943 20:14:46.280947 ===================================
4944 20:14:46.284323 DLL_ASYNC_EN = 0
4945 20:14:46.287214 ALL_SLAVE_EN = 1
4946 20:14:46.290934 NEW_RANK_MODE = 1
4947 20:14:46.291046 DLL_IDLE_MODE = 1
4948 20:14:46.293924 LP45_APHY_COMB_EN = 1
4949 20:14:46.297370 TX_ODT_DIS = 1
4950 20:14:46.300639 NEW_8X_MODE = 1
4951 20:14:46.303642 ===================================
4952 20:14:46.307399 ===================================
4953 20:14:46.310518 data_rate = 1866
4954 20:14:46.310624 CKR = 1
4955 20:14:46.314183 DQ_P2S_RATIO = 8
4956 20:14:46.317325 ===================================
4957 20:14:46.320455 CA_P2S_RATIO = 8
4958 20:14:46.323799 DQ_CA_OPEN = 0
4959 20:14:46.326931 DQ_SEMI_OPEN = 0
4960 20:14:46.330174 CA_SEMI_OPEN = 0
4961 20:14:46.330253 CA_FULL_RATE = 0
4962 20:14:46.333420 DQ_CKDIV4_EN = 1
4963 20:14:46.337239 CA_CKDIV4_EN = 1
4964 20:14:46.340181 CA_PREDIV_EN = 0
4965 20:14:46.343579 PH8_DLY = 0
4966 20:14:46.347255 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4967 20:14:46.347336 DQ_AAMCK_DIV = 4
4968 20:14:46.350360 CA_AAMCK_DIV = 4
4969 20:14:46.353543 CA_ADMCK_DIV = 4
4970 20:14:46.357420 DQ_TRACK_CA_EN = 0
4971 20:14:46.360474 CA_PICK = 933
4972 20:14:46.363769 CA_MCKIO = 933
4973 20:14:46.363847 MCKIO_SEMI = 0
4974 20:14:46.367369 PLL_FREQ = 3732
4975 20:14:46.370437 DQ_UI_PI_RATIO = 32
4976 20:14:46.373470 CA_UI_PI_RATIO = 0
4977 20:14:46.376927 ===================================
4978 20:14:46.380544 ===================================
4979 20:14:46.383777 memory_type:LPDDR4
4980 20:14:46.383860 GP_NUM : 10
4981 20:14:46.386942 SRAM_EN : 1
4982 20:14:46.390597 MD32_EN : 0
4983 20:14:46.393699 ===================================
4984 20:14:46.393786 [ANA_INIT] >>>>>>>>>>>>>>
4985 20:14:46.397016 <<<<<< [CONFIGURE PHASE]: ANA_TX
4986 20:14:46.400154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4987 20:14:46.403873 ===================================
4988 20:14:46.406903 data_rate = 1866,PCW = 0X8f00
4989 20:14:46.410233 ===================================
4990 20:14:46.413444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4991 20:14:46.419986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 20:14:46.423211 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 20:14:46.430231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4994 20:14:46.433488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4995 20:14:46.436591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4996 20:14:46.436682 [ANA_INIT] flow start
4997 20:14:46.440341 [ANA_INIT] PLL >>>>>>>>
4998 20:14:46.443542 [ANA_INIT] PLL <<<<<<<<
4999 20:14:46.443645 [ANA_INIT] MIDPI >>>>>>>>
5000 20:14:46.446779 [ANA_INIT] MIDPI <<<<<<<<
5001 20:14:46.450468 [ANA_INIT] DLL >>>>>>>>
5002 20:14:46.450576 [ANA_INIT] flow end
5003 20:14:46.457131 ============ LP4 DIFF to SE enter ============
5004 20:14:46.460335 ============ LP4 DIFF to SE exit ============
5005 20:14:46.463587 [ANA_INIT] <<<<<<<<<<<<<
5006 20:14:46.466748 [Flow] Enable top DCM control >>>>>
5007 20:14:46.470086 [Flow] Enable top DCM control <<<<<
5008 20:14:46.470178 Enable DLL master slave shuffle
5009 20:14:46.476917 ==============================================================
5010 20:14:46.479994 Gating Mode config
5011 20:14:46.483212 ==============================================================
5012 20:14:46.487049 Config description:
5013 20:14:46.496445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5014 20:14:46.503327 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5015 20:14:46.506297 SELPH_MODE 0: By rank 1: By Phase
5016 20:14:46.513245 ==============================================================
5017 20:14:46.516283 GAT_TRACK_EN = 1
5018 20:14:46.519383 RX_GATING_MODE = 2
5019 20:14:46.522916 RX_GATING_TRACK_MODE = 2
5020 20:14:46.526537 SELPH_MODE = 1
5021 20:14:46.529423 PICG_EARLY_EN = 1
5022 20:14:46.529502 VALID_LAT_VALUE = 1
5023 20:14:46.536541 ==============================================================
5024 20:14:46.539721 Enter into Gating configuration >>>>
5025 20:14:46.542848 Exit from Gating configuration <<<<
5026 20:14:46.546059 Enter into DVFS_PRE_config >>>>>
5027 20:14:46.556181 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5028 20:14:46.559285 Exit from DVFS_PRE_config <<<<<
5029 20:14:46.562849 Enter into PICG configuration >>>>
5030 20:14:46.565927 Exit from PICG configuration <<<<
5031 20:14:46.569783 [RX_INPUT] configuration >>>>>
5032 20:14:46.572961 [RX_INPUT] configuration <<<<<
5033 20:14:46.576029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5034 20:14:46.583088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5035 20:14:46.589895 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 20:14:46.596168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 20:14:46.602734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 20:14:46.609266 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 20:14:46.613005 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5040 20:14:46.615954 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5041 20:14:46.619421 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5042 20:14:46.622817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5043 20:14:46.629705 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5044 20:14:46.632561 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 20:14:46.636170 ===================================
5046 20:14:46.639308 LPDDR4 DRAM CONFIGURATION
5047 20:14:46.642745 ===================================
5048 20:14:46.642829 EX_ROW_EN[0] = 0x0
5049 20:14:46.645831 EX_ROW_EN[1] = 0x0
5050 20:14:46.645949 LP4Y_EN = 0x0
5051 20:14:46.649250 WORK_FSP = 0x0
5052 20:14:46.649337 WL = 0x3
5053 20:14:46.652493 RL = 0x3
5054 20:14:46.652602 BL = 0x2
5055 20:14:46.656244 RPST = 0x0
5056 20:14:46.656334 RD_PRE = 0x0
5057 20:14:46.659253 WR_PRE = 0x1
5058 20:14:46.663046 WR_PST = 0x0
5059 20:14:46.663131 DBI_WR = 0x0
5060 20:14:46.666189 DBI_RD = 0x0
5061 20:14:46.666272 OTF = 0x1
5062 20:14:46.669183 ===================================
5063 20:14:46.672620 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5064 20:14:46.678906 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5065 20:14:46.682637 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5066 20:14:46.685904 ===================================
5067 20:14:46.689110 LPDDR4 DRAM CONFIGURATION
5068 20:14:46.692381 ===================================
5069 20:14:46.692507 EX_ROW_EN[0] = 0x10
5070 20:14:46.696015 EX_ROW_EN[1] = 0x0
5071 20:14:46.696136 LP4Y_EN = 0x0
5072 20:14:46.699132 WORK_FSP = 0x0
5073 20:14:46.699253 WL = 0x3
5074 20:14:46.702361 RL = 0x3
5075 20:14:46.702480 BL = 0x2
5076 20:14:46.705526 RPST = 0x0
5077 20:14:46.705650 RD_PRE = 0x0
5078 20:14:46.709349 WR_PRE = 0x1
5079 20:14:46.709476 WR_PST = 0x0
5080 20:14:46.712556 DBI_WR = 0x0
5081 20:14:46.712675 DBI_RD = 0x0
5082 20:14:46.715701 OTF = 0x1
5083 20:14:46.718921 ===================================
5084 20:14:46.725434 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5085 20:14:46.729277 nWR fixed to 30
5086 20:14:46.732400 [ModeRegInit_LP4] CH0 RK0
5087 20:14:46.732479 [ModeRegInit_LP4] CH0 RK1
5088 20:14:46.735686 [ModeRegInit_LP4] CH1 RK0
5089 20:14:46.739376 [ModeRegInit_LP4] CH1 RK1
5090 20:14:46.739482 match AC timing 9
5091 20:14:46.745734 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5092 20:14:46.748812 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5093 20:14:46.752440 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5094 20:14:46.758920 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5095 20:14:46.762037 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5096 20:14:46.762120 ==
5097 20:14:46.765569 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 20:14:46.768606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 20:14:46.768686 ==
5100 20:14:46.775245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 20:14:46.782112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5102 20:14:46.785277 [CA 0] Center 37 (6~68) winsize 63
5103 20:14:46.788853 [CA 1] Center 37 (7~68) winsize 62
5104 20:14:46.791779 [CA 2] Center 34 (4~65) winsize 62
5105 20:14:46.795165 [CA 3] Center 34 (3~65) winsize 63
5106 20:14:46.798501 [CA 4] Center 33 (3~64) winsize 62
5107 20:14:46.802091 [CA 5] Center 32 (2~62) winsize 61
5108 20:14:46.802175
5109 20:14:46.805131 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5110 20:14:46.805214
5111 20:14:46.808427 [CATrainingPosCal] consider 1 rank data
5112 20:14:46.812196 u2DelayCellTimex100 = 270/100 ps
5113 20:14:46.815281 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5114 20:14:46.818563 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5115 20:14:46.821815 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5116 20:14:46.825430 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5117 20:14:46.828710 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5118 20:14:46.835132 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5119 20:14:46.835215
5120 20:14:46.838311 CA PerBit enable=1, Macro0, CA PI delay=32
5121 20:14:46.838397
5122 20:14:46.842108 [CBTSetCACLKResult] CA Dly = 32
5123 20:14:46.842223 CS Dly: 5 (0~36)
5124 20:14:46.842319 ==
5125 20:14:46.845248 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 20:14:46.848421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 20:14:46.851738 ==
5128 20:14:46.854993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 20:14:46.861733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5130 20:14:46.864909 [CA 0] Center 37 (6~68) winsize 63
5131 20:14:46.868177 [CA 1] Center 37 (6~68) winsize 63
5132 20:14:46.871726 [CA 2] Center 34 (4~65) winsize 62
5133 20:14:46.875169 [CA 3] Center 34 (4~65) winsize 62
5134 20:14:46.878632 [CA 4] Center 33 (2~64) winsize 63
5135 20:14:46.881649 [CA 5] Center 32 (2~62) winsize 61
5136 20:14:46.881733
5137 20:14:46.885147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5138 20:14:46.885254
5139 20:14:46.888238 [CATrainingPosCal] consider 2 rank data
5140 20:14:46.891774 u2DelayCellTimex100 = 270/100 ps
5141 20:14:46.894904 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5142 20:14:46.898775 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5143 20:14:46.901735 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5144 20:14:46.905432 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5145 20:14:46.911979 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5146 20:14:46.915077 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5147 20:14:46.915195
5148 20:14:46.918154 CA PerBit enable=1, Macro0, CA PI delay=32
5149 20:14:46.918264
5150 20:14:46.921763 [CBTSetCACLKResult] CA Dly = 32
5151 20:14:46.921869 CS Dly: 5 (0~37)
5152 20:14:46.921962
5153 20:14:46.924695 ----->DramcWriteLeveling(PI) begin...
5154 20:14:46.924782 ==
5155 20:14:46.928459 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 20:14:46.934927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 20:14:46.935037 ==
5158 20:14:46.938099 Write leveling (Byte 0): 32 => 32
5159 20:14:46.938183 Write leveling (Byte 1): 28 => 28
5160 20:14:46.941899 DramcWriteLeveling(PI) end<-----
5161 20:14:46.942010
5162 20:14:46.942107 ==
5163 20:14:46.945019 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 20:14:46.951347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 20:14:46.951484 ==
5166 20:14:46.955320 [Gating] SW mode calibration
5167 20:14:46.961659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 20:14:46.964726 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5169 20:14:46.971585 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5170 20:14:46.974930 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 20:14:46.978213 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 20:14:46.984542 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 20:14:46.987743 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 20:14:46.991541 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 20:14:46.998108 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5176 20:14:47.001360 0 14 28 | B1->B0 | 3434 2929 | 0 0 | (1 0) (0 0)
5177 20:14:47.004502 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5178 20:14:47.011416 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 20:14:47.014703 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 20:14:47.018172 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 20:14:47.024404 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 20:14:47.027712 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 20:14:47.031154 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5184 20:14:47.034589 0 15 28 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
5185 20:14:47.040933 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5186 20:14:47.044936 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 20:14:47.047997 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 20:14:47.054338 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 20:14:47.057575 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 20:14:47.060793 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 20:14:47.067824 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5192 20:14:47.070994 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5193 20:14:47.074086 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5194 20:14:47.081081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 20:14:47.084302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 20:14:47.087468 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 20:14:47.094510 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 20:14:47.097845 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 20:14:47.101034 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 20:14:47.107971 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 20:14:47.111274 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 20:14:47.114323 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 20:14:47.120987 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 20:14:47.124515 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 20:14:47.127509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 20:14:47.133989 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 20:14:47.137713 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5208 20:14:47.141235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5209 20:14:47.147413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5210 20:14:47.147522 Total UI for P1: 0, mck2ui 16
5211 20:14:47.154379 best dqsien dly found for B0: ( 1, 2, 26)
5212 20:14:47.157494 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 20:14:47.160919 Total UI for P1: 0, mck2ui 16
5214 20:14:47.164171 best dqsien dly found for B1: ( 1, 3, 0)
5215 20:14:47.167076 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5216 20:14:47.170736 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5217 20:14:47.170840
5218 20:14:47.173959 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5219 20:14:47.177247 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5220 20:14:47.180879 [Gating] SW calibration Done
5221 20:14:47.181006 ==
5222 20:14:47.183953 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 20:14:47.187175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 20:14:47.187304 ==
5225 20:14:47.190370 RX Vref Scan: 0
5226 20:14:47.190453
5227 20:14:47.193539 RX Vref 0 -> 0, step: 1
5228 20:14:47.193618
5229 20:14:47.193681 RX Delay -80 -> 252, step: 8
5230 20:14:47.200215 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5231 20:14:47.204098 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5232 20:14:47.207182 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5233 20:14:47.210503 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5234 20:14:47.213603 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5235 20:14:47.217204 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5236 20:14:47.223764 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5237 20:14:47.227211 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5238 20:14:47.230312 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5239 20:14:47.233819 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5240 20:14:47.236805 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5241 20:14:47.243794 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5242 20:14:47.247152 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5243 20:14:47.250393 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5244 20:14:47.253319 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5245 20:14:47.257198 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5246 20:14:47.257296 ==
5247 20:14:47.260461 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 20:14:47.267163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 20:14:47.267272 ==
5250 20:14:47.267366 DQS Delay:
5251 20:14:47.269967 DQS0 = 0, DQS1 = 0
5252 20:14:47.270075 DQM Delay:
5253 20:14:47.270148 DQM0 = 104, DQM1 = 94
5254 20:14:47.273795 DQ Delay:
5255 20:14:47.276979 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5256 20:14:47.280053 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5257 20:14:47.283518 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5258 20:14:47.286828 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5259 20:14:47.286935
5260 20:14:47.287028
5261 20:14:47.287117 ==
5262 20:14:47.289914 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 20:14:47.293761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 20:14:47.293850 ==
5265 20:14:47.293916
5266 20:14:47.293976
5267 20:14:47.296811 TX Vref Scan disable
5268 20:14:47.300068 == TX Byte 0 ==
5269 20:14:47.303228 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5270 20:14:47.306414 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5271 20:14:47.310169 == TX Byte 1 ==
5272 20:14:47.313363 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5273 20:14:47.316449 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5274 20:14:47.316556 ==
5275 20:14:47.319722 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 20:14:47.326442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 20:14:47.326573 ==
5278 20:14:47.326695
5279 20:14:47.326815
5280 20:14:47.326931 TX Vref Scan disable
5281 20:14:47.330611 == TX Byte 0 ==
5282 20:14:47.333657 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5283 20:14:47.340272 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5284 20:14:47.340389 == TX Byte 1 ==
5285 20:14:47.343617 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5286 20:14:47.350191 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5287 20:14:47.350290
5288 20:14:47.350358 [DATLAT]
5289 20:14:47.350419 Freq=933, CH0 RK0
5290 20:14:47.350479
5291 20:14:47.353842 DATLAT Default: 0xd
5292 20:14:47.353945 0, 0xFFFF, sum = 0
5293 20:14:47.356737 1, 0xFFFF, sum = 0
5294 20:14:47.356839 2, 0xFFFF, sum = 0
5295 20:14:47.360130 3, 0xFFFF, sum = 0
5296 20:14:47.363403 4, 0xFFFF, sum = 0
5297 20:14:47.363484 5, 0xFFFF, sum = 0
5298 20:14:47.367264 6, 0xFFFF, sum = 0
5299 20:14:47.367346 7, 0xFFFF, sum = 0
5300 20:14:47.370383 8, 0xFFFF, sum = 0
5301 20:14:47.370462 9, 0xFFFF, sum = 0
5302 20:14:47.373471 10, 0x0, sum = 1
5303 20:14:47.373574 11, 0x0, sum = 2
5304 20:14:47.377200 12, 0x0, sum = 3
5305 20:14:47.377306 13, 0x0, sum = 4
5306 20:14:47.377401 best_step = 11
5307 20:14:47.377490
5308 20:14:47.380410 ==
5309 20:14:47.383861 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 20:14:47.386677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 20:14:47.386784 ==
5312 20:14:47.386878 RX Vref Scan: 1
5313 20:14:47.386968
5314 20:14:47.390448 RX Vref 0 -> 0, step: 1
5315 20:14:47.390558
5316 20:14:47.393893 RX Delay -53 -> 252, step: 4
5317 20:14:47.393999
5318 20:14:47.396949 Set Vref, RX VrefLevel [Byte0]: 57
5319 20:14:47.399926 [Byte1]: 46
5320 20:14:47.400035
5321 20:14:47.403850 Final RX Vref Byte 0 = 57 to rank0
5322 20:14:47.407160 Final RX Vref Byte 1 = 46 to rank0
5323 20:14:47.410204 Final RX Vref Byte 0 = 57 to rank1
5324 20:14:47.413526 Final RX Vref Byte 1 = 46 to rank1==
5325 20:14:47.416648 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 20:14:47.420420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 20:14:47.420513 ==
5328 20:14:47.423717 DQS Delay:
5329 20:14:47.423805 DQS0 = 0, DQS1 = 0
5330 20:14:47.426549 DQM Delay:
5331 20:14:47.426657 DQM0 = 105, DQM1 = 95
5332 20:14:47.426751 DQ Delay:
5333 20:14:47.433599 DQ0 =104, DQ1 =108, DQ2 =104, DQ3 =102
5334 20:14:47.436762 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5335 20:14:47.440398 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =90
5336 20:14:47.443407 DQ12 =102, DQ13 =100, DQ14 =108, DQ15 =100
5337 20:14:47.443492
5338 20:14:47.443567
5339 20:14:47.450271 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5340 20:14:47.453167 CH0 RK0: MR19=505, MR18=2E26
5341 20:14:47.459922 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5342 20:14:47.460034
5343 20:14:47.463194 ----->DramcWriteLeveling(PI) begin...
5344 20:14:47.463297 ==
5345 20:14:47.466830 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 20:14:47.470353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 20:14:47.470469 ==
5348 20:14:47.473979 Write leveling (Byte 0): 33 => 33
5349 20:14:47.476774 Write leveling (Byte 1): 29 => 29
5350 20:14:47.480325 DramcWriteLeveling(PI) end<-----
5351 20:14:47.480442
5352 20:14:47.480548 ==
5353 20:14:47.483415 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 20:14:47.486601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 20:14:47.486711 ==
5356 20:14:47.490393 [Gating] SW mode calibration
5357 20:14:47.496748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 20:14:47.503546 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5359 20:14:47.506842 0 14 0 | B1->B0 | 3231 3131 | 1 0 | (0 0) (0 0)
5360 20:14:47.513821 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 20:14:47.516902 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 20:14:47.520205 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 20:14:47.526581 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 20:14:47.530263 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 20:14:47.533427 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5366 20:14:47.539672 0 14 28 | B1->B0 | 2b2b 2e2e | 1 0 | (1 1) (0 0)
5367 20:14:47.543383 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5368 20:14:47.546543 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 20:14:47.549816 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 20:14:47.556692 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 20:14:47.559729 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 20:14:47.562972 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 20:14:47.569881 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5374 20:14:47.572938 0 15 28 | B1->B0 | 3737 3938 | 1 1 | (0 0) (0 0)
5375 20:14:47.576326 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 20:14:47.583104 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 20:14:47.586199 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 20:14:47.589743 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 20:14:47.596545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 20:14:47.599762 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 20:14:47.603269 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 20:14:47.609447 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5383 20:14:47.613201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5384 20:14:47.616165 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 20:14:47.622680 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 20:14:47.625904 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 20:14:47.629482 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 20:14:47.635798 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 20:14:47.639711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 20:14:47.642787 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 20:14:47.649426 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 20:14:47.652588 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 20:14:47.655708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 20:14:47.662843 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 20:14:47.665972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 20:14:47.669096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 20:14:47.675959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 20:14:47.679493 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 20:14:47.682553 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 20:14:47.686130 Total UI for P1: 0, mck2ui 16
5401 20:14:47.689301 best dqsien dly found for B0: ( 1, 2, 26)
5402 20:14:47.692470 Total UI for P1: 0, mck2ui 16
5403 20:14:47.696081 best dqsien dly found for B1: ( 1, 2, 28)
5404 20:14:47.699126 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5405 20:14:47.702202 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5406 20:14:47.702307
5407 20:14:47.706041 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5408 20:14:47.712281 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5409 20:14:47.712399 [Gating] SW calibration Done
5410 20:14:47.712488 ==
5411 20:14:47.715556 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 20:14:47.722658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 20:14:47.722743 ==
5414 20:14:47.722839 RX Vref Scan: 0
5415 20:14:47.722927
5416 20:14:47.725822 RX Vref 0 -> 0, step: 1
5417 20:14:47.725914
5418 20:14:47.728820 RX Delay -80 -> 252, step: 8
5419 20:14:47.732215 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5420 20:14:47.735735 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5421 20:14:47.738663 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5422 20:14:47.745515 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5423 20:14:47.749044 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5424 20:14:47.752148 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5425 20:14:47.755822 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5426 20:14:47.758683 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5427 20:14:47.762461 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5428 20:14:47.768637 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5429 20:14:47.772345 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5430 20:14:47.775492 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5431 20:14:47.778761 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5432 20:14:47.781935 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5433 20:14:47.788808 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5434 20:14:47.791791 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5435 20:14:47.791902 ==
5436 20:14:47.795405 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 20:14:47.798592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 20:14:47.798698 ==
5439 20:14:47.798808 DQS Delay:
5440 20:14:47.801728 DQS0 = 0, DQS1 = 0
5441 20:14:47.801835 DQM Delay:
5442 20:14:47.805513 DQM0 = 105, DQM1 = 95
5443 20:14:47.805616 DQ Delay:
5444 20:14:47.808612 DQ0 =103, DQ1 =107, DQ2 =107, DQ3 =99
5445 20:14:47.811825 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5446 20:14:47.815605 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5447 20:14:47.818882 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5448 20:14:47.818985
5449 20:14:47.819085
5450 20:14:47.819182 ==
5451 20:14:47.822061 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 20:14:47.828360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 20:14:47.828446 ==
5454 20:14:47.828514
5455 20:14:47.828575
5456 20:14:47.828633 TX Vref Scan disable
5457 20:14:47.832309 == TX Byte 0 ==
5458 20:14:47.835511 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5459 20:14:47.842601 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5460 20:14:47.842713 == TX Byte 1 ==
5461 20:14:47.845994 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5462 20:14:47.849004 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5463 20:14:47.852538 ==
5464 20:14:47.855732 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 20:14:47.858974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 20:14:47.859084 ==
5467 20:14:47.859184
5468 20:14:47.859282
5469 20:14:47.862113 TX Vref Scan disable
5470 20:14:47.862220 == TX Byte 0 ==
5471 20:14:47.868769 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5472 20:14:47.872509 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5473 20:14:47.872638 == TX Byte 1 ==
5474 20:14:47.878869 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5475 20:14:47.881980 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5476 20:14:47.882107
5477 20:14:47.882219 [DATLAT]
5478 20:14:47.885524 Freq=933, CH0 RK1
5479 20:14:47.885642
5480 20:14:47.885738 DATLAT Default: 0xb
5481 20:14:47.888576 0, 0xFFFF, sum = 0
5482 20:14:47.888713 1, 0xFFFF, sum = 0
5483 20:14:47.892012 2, 0xFFFF, sum = 0
5484 20:14:47.894982 3, 0xFFFF, sum = 0
5485 20:14:47.895069 4, 0xFFFF, sum = 0
5486 20:14:47.898665 5, 0xFFFF, sum = 0
5487 20:14:47.898783 6, 0xFFFF, sum = 0
5488 20:14:47.901828 7, 0xFFFF, sum = 0
5489 20:14:47.901924 8, 0xFFFF, sum = 0
5490 20:14:47.905725 9, 0xFFFF, sum = 0
5491 20:14:47.905851 10, 0x0, sum = 1
5492 20:14:47.908894 11, 0x0, sum = 2
5493 20:14:47.908977 12, 0x0, sum = 3
5494 20:14:47.909044 13, 0x0, sum = 4
5495 20:14:47.911999 best_step = 11
5496 20:14:47.912101
5497 20:14:47.912191 ==
5498 20:14:47.915470 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 20:14:47.918732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 20:14:47.918848 ==
5501 20:14:47.921860 RX Vref Scan: 0
5502 20:14:47.921964
5503 20:14:47.924938 RX Vref 0 -> 0, step: 1
5504 20:14:47.925015
5505 20:14:47.925080 RX Delay -45 -> 252, step: 4
5506 20:14:47.932701 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5507 20:14:47.935837 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5508 20:14:47.939188 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5509 20:14:47.942498 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5510 20:14:47.946349 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5511 20:14:47.952748 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5512 20:14:47.956004 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5513 20:14:47.959485 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5514 20:14:47.962724 iDelay=199, Bit 8, Center 82 (-1 ~ 166) 168
5515 20:14:47.966036 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5516 20:14:47.972433 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5517 20:14:47.976018 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5518 20:14:47.978855 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5519 20:14:47.982290 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5520 20:14:47.985692 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5521 20:14:47.992512 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5522 20:14:47.992599 ==
5523 20:14:47.995799 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 20:14:47.999271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 20:14:47.999382 ==
5526 20:14:47.999484 DQS Delay:
5527 20:14:48.002359 DQS0 = 0, DQS1 = 0
5528 20:14:48.002464 DQM Delay:
5529 20:14:48.005925 DQM0 = 104, DQM1 = 93
5530 20:14:48.006012 DQ Delay:
5531 20:14:48.008993 DQ0 =102, DQ1 =104, DQ2 =100, DQ3 =100
5532 20:14:48.012366 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5533 20:14:48.015853 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =88
5534 20:14:48.019117 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =100
5535 20:14:48.019222
5536 20:14:48.019325
5537 20:14:48.028773 [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5538 20:14:48.028868 CH0 RK1: MR19=505, MR18=2700
5539 20:14:48.035624 CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43
5540 20:14:48.038839 [RxdqsGatingPostProcess] freq 933
5541 20:14:48.045819 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5542 20:14:48.049090 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 20:14:48.052303 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 20:14:48.055455 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 20:14:48.058724 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 20:14:48.062407 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 20:14:48.062496 best DQS1 dly(2T, 0.5T) = (0, 10)
5548 20:14:48.065479 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 20:14:48.068639 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5550 20:14:48.072403 Pre-setting of DQS Precalculation
5551 20:14:48.078651 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5552 20:14:48.078740 ==
5553 20:14:48.082478 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 20:14:48.085697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 20:14:48.085805 ==
5556 20:14:48.092083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 20:14:48.098632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 20:14:48.102424 [CA 0] Center 36 (6~67) winsize 62
5559 20:14:48.105513 [CA 1] Center 36 (6~67) winsize 62
5560 20:14:48.108562 [CA 2] Center 34 (4~65) winsize 62
5561 20:14:48.112005 [CA 3] Center 34 (4~65) winsize 62
5562 20:14:48.115188 [CA 4] Center 34 (4~65) winsize 62
5563 20:14:48.119008 [CA 5] Center 33 (3~64) winsize 62
5564 20:14:48.119091
5565 20:14:48.121994 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 20:14:48.122075
5567 20:14:48.125503 [CATrainingPosCal] consider 1 rank data
5568 20:14:48.128724 u2DelayCellTimex100 = 270/100 ps
5569 20:14:48.132215 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 20:14:48.135583 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 20:14:48.138486 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 20:14:48.142038 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5573 20:14:48.145393 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 20:14:48.148939 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 20:14:48.149024
5576 20:14:48.152248 CA PerBit enable=1, Macro0, CA PI delay=33
5577 20:14:48.155363
5578 20:14:48.155453 [CBTSetCACLKResult] CA Dly = 33
5579 20:14:48.158476 CS Dly: 6 (0~37)
5580 20:14:48.158555 ==
5581 20:14:48.161760 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 20:14:48.165190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 20:14:48.165314 ==
5584 20:14:48.171770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 20:14:48.178751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5586 20:14:48.181880 [CA 0] Center 36 (6~67) winsize 62
5587 20:14:48.185060 [CA 1] Center 37 (6~68) winsize 63
5588 20:14:48.188345 [CA 2] Center 35 (5~65) winsize 61
5589 20:14:48.192107 [CA 3] Center 34 (4~65) winsize 62
5590 20:14:48.195402 [CA 4] Center 34 (4~65) winsize 62
5591 20:14:48.198669 [CA 5] Center 33 (3~64) winsize 62
5592 20:14:48.198780
5593 20:14:48.201649 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5594 20:14:48.201757
5595 20:14:48.205272 [CATrainingPosCal] consider 2 rank data
5596 20:14:48.208623 u2DelayCellTimex100 = 270/100 ps
5597 20:14:48.211697 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5598 20:14:48.214826 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5599 20:14:48.218454 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5600 20:14:48.221690 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5601 20:14:48.224839 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5602 20:14:48.228283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5603 20:14:48.228370
5604 20:14:48.235319 CA PerBit enable=1, Macro0, CA PI delay=33
5605 20:14:48.235423
5606 20:14:48.238454 [CBTSetCACLKResult] CA Dly = 33
5607 20:14:48.238556 CS Dly: 7 (0~40)
5608 20:14:48.238661
5609 20:14:48.241863 ----->DramcWriteLeveling(PI) begin...
5610 20:14:48.241967 ==
5611 20:14:48.244854 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 20:14:48.248457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 20:14:48.248570 ==
5614 20:14:48.251443 Write leveling (Byte 0): 26 => 26
5615 20:14:48.255013 Write leveling (Byte 1): 27 => 27
5616 20:14:48.258045 DramcWriteLeveling(PI) end<-----
5617 20:14:48.258169
5618 20:14:48.258283 ==
5619 20:14:48.261317 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 20:14:48.267767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 20:14:48.267908 ==
5622 20:14:48.268027 [Gating] SW mode calibration
5623 20:14:48.277745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 20:14:48.281067 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5625 20:14:48.288129 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 20:14:48.291315 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 20:14:48.294498 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 20:14:48.301318 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 20:14:48.304465 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 20:14:48.307620 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 20:14:48.311421 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5632 20:14:48.318056 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 20:14:48.320894 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 20:14:48.324228 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 20:14:48.331276 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 20:14:48.334489 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 20:14:48.337770 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 20:14:48.344180 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 20:14:48.347945 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
5640 20:14:48.351115 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5641 20:14:48.357358 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 20:14:48.361178 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 20:14:48.364207 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 20:14:48.371007 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 20:14:48.374055 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 20:14:48.377676 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5647 20:14:48.384244 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5648 20:14:48.387484 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 20:14:48.390592 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 20:14:48.397351 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 20:14:48.400891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 20:14:48.403933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 20:14:48.410942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 20:14:48.414161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 20:14:48.417356 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 20:14:48.420796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 20:14:48.427730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 20:14:48.430786 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 20:14:48.434278 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 20:14:48.440601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 20:14:48.443771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 20:14:48.447136 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 20:14:48.453881 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5664 20:14:48.457641 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5665 20:14:48.460706 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 20:14:48.463973 Total UI for P1: 0, mck2ui 16
5667 20:14:48.467244 best dqsien dly found for B0: ( 1, 2, 26)
5668 20:14:48.470937 Total UI for P1: 0, mck2ui 16
5669 20:14:48.473916 best dqsien dly found for B1: ( 1, 2, 26)
5670 20:14:48.477159 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5671 20:14:48.480422 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5672 20:14:48.480506
5673 20:14:48.487449 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5674 20:14:48.490521 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5675 20:14:48.493891 [Gating] SW calibration Done
5676 20:14:48.493996 ==
5677 20:14:48.496923 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 20:14:48.500490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 20:14:48.500601 ==
5680 20:14:48.500694 RX Vref Scan: 0
5681 20:14:48.500792
5682 20:14:48.503882 RX Vref 0 -> 0, step: 1
5683 20:14:48.503982
5684 20:14:48.506771 RX Delay -80 -> 252, step: 8
5685 20:14:48.510424 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5686 20:14:48.513930 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5687 20:14:48.520178 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5688 20:14:48.523425 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5689 20:14:48.526812 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5690 20:14:48.530574 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5691 20:14:48.533186 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5692 20:14:48.537032 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5693 20:14:48.543357 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5694 20:14:48.546805 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5695 20:14:48.550114 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5696 20:14:48.553511 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5697 20:14:48.557019 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5698 20:14:48.559869 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5699 20:14:48.566972 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5700 20:14:48.570133 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5701 20:14:48.570213 ==
5702 20:14:48.573366 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 20:14:48.576748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 20:14:48.576834 ==
5705 20:14:48.579901 DQS Delay:
5706 20:14:48.579988 DQS0 = 0, DQS1 = 0
5707 20:14:48.580077 DQM Delay:
5708 20:14:48.583095 DQM0 = 102, DQM1 = 98
5709 20:14:48.583183 DQ Delay:
5710 20:14:48.586825 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5711 20:14:48.590161 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5712 20:14:48.593336 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5713 20:14:48.596496 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5714 20:14:48.596590
5715 20:14:48.600041
5716 20:14:48.600124 ==
5717 20:14:48.603111 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 20:14:48.606877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 20:14:48.606987 ==
5720 20:14:48.607092
5721 20:14:48.607184
5722 20:14:48.610196 TX Vref Scan disable
5723 20:14:48.610312 == TX Byte 0 ==
5724 20:14:48.616644 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5725 20:14:48.619724 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5726 20:14:48.619831 == TX Byte 1 ==
5727 20:14:48.626372 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5728 20:14:48.629579 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5729 20:14:48.629689 ==
5730 20:14:48.633260 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 20:14:48.636476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 20:14:48.636569 ==
5733 20:14:48.636637
5734 20:14:48.636702
5735 20:14:48.639425 TX Vref Scan disable
5736 20:14:48.643423 == TX Byte 0 ==
5737 20:14:48.646554 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5738 20:14:48.649651 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5739 20:14:48.653401 == TX Byte 1 ==
5740 20:14:48.656524 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 20:14:48.659546 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 20:14:48.659656
5743 20:14:48.662967 [DATLAT]
5744 20:14:48.663081 Freq=933, CH1 RK0
5745 20:14:48.663188
5746 20:14:48.666506 DATLAT Default: 0xd
5747 20:14:48.666615 0, 0xFFFF, sum = 0
5748 20:14:48.670003 1, 0xFFFF, sum = 0
5749 20:14:48.670116 2, 0xFFFF, sum = 0
5750 20:14:48.672812 3, 0xFFFF, sum = 0
5751 20:14:48.672924 4, 0xFFFF, sum = 0
5752 20:14:48.676492 5, 0xFFFF, sum = 0
5753 20:14:48.676620 6, 0xFFFF, sum = 0
5754 20:14:48.679402 7, 0xFFFF, sum = 0
5755 20:14:48.679504 8, 0xFFFF, sum = 0
5756 20:14:48.683274 9, 0xFFFF, sum = 0
5757 20:14:48.683387 10, 0x0, sum = 1
5758 20:14:48.686247 11, 0x0, sum = 2
5759 20:14:48.686372 12, 0x0, sum = 3
5760 20:14:48.689467 13, 0x0, sum = 4
5761 20:14:48.689553 best_step = 11
5762 20:14:48.689619
5763 20:14:48.689687 ==
5764 20:14:48.692753 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 20:14:48.699830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 20:14:48.699941 ==
5767 20:14:48.700049 RX Vref Scan: 1
5768 20:14:48.700142
5769 20:14:48.702860 RX Vref 0 -> 0, step: 1
5770 20:14:48.702939
5771 20:14:48.705879 RX Delay -45 -> 252, step: 4
5772 20:14:48.705961
5773 20:14:48.709343 Set Vref, RX VrefLevel [Byte0]: 54
5774 20:14:48.712467 [Byte1]: 54
5775 20:14:48.712547
5776 20:14:48.715738 Final RX Vref Byte 0 = 54 to rank0
5777 20:14:48.719484 Final RX Vref Byte 1 = 54 to rank0
5778 20:14:48.722404 Final RX Vref Byte 0 = 54 to rank1
5779 20:14:48.725972 Final RX Vref Byte 1 = 54 to rank1==
5780 20:14:48.729339 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 20:14:48.732411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 20:14:48.732543 ==
5783 20:14:48.736282 DQS Delay:
5784 20:14:48.736405 DQS0 = 0, DQS1 = 0
5785 20:14:48.736515 DQM Delay:
5786 20:14:48.739356 DQM0 = 103, DQM1 = 99
5787 20:14:48.739468 DQ Delay:
5788 20:14:48.742381 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5789 20:14:48.746100 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5790 20:14:48.749214 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5791 20:14:48.752659 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =106
5792 20:14:48.755938
5793 20:14:48.756020
5794 20:14:48.762212 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5795 20:14:48.765847 CH1 RK0: MR19=505, MR18=1B32
5796 20:14:48.772324 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5797 20:14:48.772404
5798 20:14:48.775381 ----->DramcWriteLeveling(PI) begin...
5799 20:14:48.775470 ==
5800 20:14:48.778957 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 20:14:48.782449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 20:14:48.782528 ==
5803 20:14:48.785354 Write leveling (Byte 0): 26 => 26
5804 20:14:48.789115 Write leveling (Byte 1): 25 => 25
5805 20:14:48.792179 DramcWriteLeveling(PI) end<-----
5806 20:14:48.792282
5807 20:14:48.792360 ==
5808 20:14:48.795301 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 20:14:48.799103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 20:14:48.799183 ==
5811 20:14:48.802217 [Gating] SW mode calibration
5812 20:14:48.808818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5813 20:14:48.815456 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5814 20:14:48.818533 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 20:14:48.821838 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 20:14:48.828810 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 20:14:48.831900 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 20:14:48.835044 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 20:14:48.842086 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 20:14:48.845142 0 14 24 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 0)
5821 20:14:48.848495 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5822 20:14:48.855505 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 20:14:48.858807 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 20:14:48.861934 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 20:14:48.868589 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 20:14:48.871737 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 20:14:48.875386 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 20:14:48.882051 0 15 24 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (0 0)
5829 20:14:48.885222 0 15 28 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (0 0)
5830 20:14:48.888403 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 20:14:48.895605 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 20:14:48.898585 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 20:14:48.901885 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 20:14:48.908346 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 20:14:48.912097 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 20:14:48.915459 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 20:14:48.921640 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5838 20:14:48.925169 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 20:14:48.928440 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 20:14:48.931692 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 20:14:48.938758 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 20:14:48.941814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 20:14:48.945265 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 20:14:48.951828 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 20:14:48.955114 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 20:14:48.958419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 20:14:48.964772 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 20:14:48.968547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 20:14:48.971759 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 20:14:48.978302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 20:14:48.981593 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5852 20:14:48.984772 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 20:14:48.991912 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 20:14:48.992000 Total UI for P1: 0, mck2ui 16
5855 20:14:48.998447 best dqsien dly found for B0: ( 1, 2, 26)
5856 20:14:48.998533 Total UI for P1: 0, mck2ui 16
5857 20:14:49.002009 best dqsien dly found for B1: ( 1, 2, 26)
5858 20:14:49.008641 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5859 20:14:49.011816 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5860 20:14:49.011900
5861 20:14:49.014929 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5862 20:14:49.018281 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5863 20:14:49.021340 [Gating] SW calibration Done
5864 20:14:49.021469 ==
5865 20:14:49.025105 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 20:14:49.028265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 20:14:49.028361 ==
5868 20:14:49.031987 RX Vref Scan: 0
5869 20:14:49.032069
5870 20:14:49.032134 RX Vref 0 -> 0, step: 1
5871 20:14:49.032194
5872 20:14:49.034583 RX Delay -80 -> 252, step: 8
5873 20:14:49.038376 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5874 20:14:49.044757 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5875 20:14:49.048553 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5876 20:14:49.051600 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5877 20:14:49.054781 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5878 20:14:49.058397 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5879 20:14:49.061854 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5880 20:14:49.065043 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5881 20:14:49.071301 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5882 20:14:49.075071 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5883 20:14:49.078316 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5884 20:14:49.081472 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5885 20:14:49.084725 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5886 20:14:49.091273 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5887 20:14:49.095055 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5888 20:14:49.098162 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5889 20:14:49.098275 ==
5890 20:14:49.101381 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 20:14:49.104754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 20:14:49.104863 ==
5893 20:14:49.107839 DQS Delay:
5894 20:14:49.107948 DQS0 = 0, DQS1 = 0
5895 20:14:49.111382 DQM Delay:
5896 20:14:49.111490 DQM0 = 102, DQM1 = 99
5897 20:14:49.111582 DQ Delay:
5898 20:14:49.114692 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5899 20:14:49.118005 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5900 20:14:49.121459 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5901 20:14:49.124543 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5902 20:14:49.127818
5903 20:14:49.127941
5904 20:14:49.128061 ==
5905 20:14:49.131118 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 20:14:49.134813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 20:14:49.134929 ==
5908 20:14:49.135025
5909 20:14:49.135115
5910 20:14:49.137906 TX Vref Scan disable
5911 20:14:49.137982 == TX Byte 0 ==
5912 20:14:49.144942 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 20:14:49.148015 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 20:14:49.148120 == TX Byte 1 ==
5915 20:14:49.154890 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5916 20:14:49.157942 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5917 20:14:49.158020 ==
5918 20:14:49.160913 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 20:14:49.164714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 20:14:49.164819 ==
5921 20:14:49.164920
5922 20:14:49.165016
5923 20:14:49.168061 TX Vref Scan disable
5924 20:14:49.171251 == TX Byte 0 ==
5925 20:14:49.174556 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 20:14:49.177718 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 20:14:49.180913 == TX Byte 1 ==
5928 20:14:49.184597 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5929 20:14:49.187822 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5930 20:14:49.187902
5931 20:14:49.191067 [DATLAT]
5932 20:14:49.191150 Freq=933, CH1 RK1
5933 20:14:49.191217
5934 20:14:49.194207 DATLAT Default: 0xb
5935 20:14:49.194287 0, 0xFFFF, sum = 0
5936 20:14:49.197400 1, 0xFFFF, sum = 0
5937 20:14:49.197525 2, 0xFFFF, sum = 0
5938 20:14:49.201258 3, 0xFFFF, sum = 0
5939 20:14:49.201354 4, 0xFFFF, sum = 0
5940 20:14:49.204298 5, 0xFFFF, sum = 0
5941 20:14:49.204405 6, 0xFFFF, sum = 0
5942 20:14:49.207374 7, 0xFFFF, sum = 0
5943 20:14:49.207482 8, 0xFFFF, sum = 0
5944 20:14:49.210797 9, 0xFFFF, sum = 0
5945 20:14:49.210906 10, 0x0, sum = 1
5946 20:14:49.214414 11, 0x0, sum = 2
5947 20:14:49.214519 12, 0x0, sum = 3
5948 20:14:49.217472 13, 0x0, sum = 4
5949 20:14:49.217584 best_step = 11
5950 20:14:49.217688
5951 20:14:49.217793 ==
5952 20:14:49.221256 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 20:14:49.227935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 20:14:49.228041 ==
5955 20:14:49.228142 RX Vref Scan: 0
5956 20:14:49.228241
5957 20:14:49.230764 RX Vref 0 -> 0, step: 1
5958 20:14:49.230862
5959 20:14:49.234237 RX Delay -45 -> 252, step: 4
5960 20:14:49.237891 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5961 20:14:49.240751 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5962 20:14:49.247788 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5963 20:14:49.250707 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5964 20:14:49.254039 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5965 20:14:49.257271 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5966 20:14:49.261025 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5967 20:14:49.267355 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5968 20:14:49.270427 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5969 20:14:49.274174 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5970 20:14:49.277383 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5971 20:14:49.280598 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5972 20:14:49.283876 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5973 20:14:49.290838 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5974 20:14:49.293989 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5975 20:14:49.297139 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5976 20:14:49.297225 ==
5977 20:14:49.300376 Dram Type= 6, Freq= 0, CH_1, rank 1
5978 20:14:49.303593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5979 20:14:49.307505 ==
5980 20:14:49.307587 DQS Delay:
5981 20:14:49.307671 DQS0 = 0, DQS1 = 0
5982 20:14:49.310505 DQM Delay:
5983 20:14:49.310587 DQM0 = 104, DQM1 = 99
5984 20:14:49.313624 DQ Delay:
5985 20:14:49.317285 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5986 20:14:49.320683 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5987 20:14:49.323739 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5988 20:14:49.327129 DQ12 =108, DQ13 =108, DQ14 =102, DQ15 =110
5989 20:14:49.327252
5990 20:14:49.327367
5991 20:14:49.333608 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5992 20:14:49.337101 CH1 RK1: MR19=505, MR18=2D01
5993 20:14:49.343833 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5994 20:14:49.346790 [RxdqsGatingPostProcess] freq 933
5995 20:14:49.353838 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5996 20:14:49.353954 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 20:14:49.356749 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 20:14:49.360358 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 20:14:49.363805 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 20:14:49.366942 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 20:14:49.370430 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 20:14:49.373334 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 20:14:49.377006 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 20:14:49.379997 Pre-setting of DQS Precalculation
6005 20:14:49.386705 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6006 20:14:49.393651 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6007 20:14:49.399964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6008 20:14:49.400073
6009 20:14:49.400166
6010 20:14:49.403818 [Calibration Summary] 1866 Mbps
6011 20:14:49.403900 CH 0, Rank 0
6012 20:14:49.406992 SW Impedance : PASS
6013 20:14:49.407066 DUTY Scan : NO K
6014 20:14:49.410116 ZQ Calibration : PASS
6015 20:14:49.413386 Jitter Meter : NO K
6016 20:14:49.413460 CBT Training : PASS
6017 20:14:49.416497 Write leveling : PASS
6018 20:14:49.419734 RX DQS gating : PASS
6019 20:14:49.419842 RX DQ/DQS(RDDQC) : PASS
6020 20:14:49.423422 TX DQ/DQS : PASS
6021 20:14:49.426478 RX DATLAT : PASS
6022 20:14:49.426554 RX DQ/DQS(Engine): PASS
6023 20:14:49.430262 TX OE : NO K
6024 20:14:49.430391 All Pass.
6025 20:14:49.430508
6026 20:14:49.433475 CH 0, Rank 1
6027 20:14:49.433595 SW Impedance : PASS
6028 20:14:49.436886 DUTY Scan : NO K
6029 20:14:49.439913 ZQ Calibration : PASS
6030 20:14:49.439993 Jitter Meter : NO K
6031 20:14:49.443495 CBT Training : PASS
6032 20:14:49.446554 Write leveling : PASS
6033 20:14:49.446631 RX DQS gating : PASS
6034 20:14:49.450238 RX DQ/DQS(RDDQC) : PASS
6035 20:14:49.453188 TX DQ/DQS : PASS
6036 20:14:49.453297 RX DATLAT : PASS
6037 20:14:49.456295 RX DQ/DQS(Engine): PASS
6038 20:14:49.456384 TX OE : NO K
6039 20:14:49.459582 All Pass.
6040 20:14:49.459706
6041 20:14:49.459817 CH 1, Rank 0
6042 20:14:49.462866 SW Impedance : PASS
6043 20:14:49.462988 DUTY Scan : NO K
6044 20:14:49.466678 ZQ Calibration : PASS
6045 20:14:49.469840 Jitter Meter : NO K
6046 20:14:49.469945 CBT Training : PASS
6047 20:14:49.473073 Write leveling : PASS
6048 20:14:49.476225 RX DQS gating : PASS
6049 20:14:49.476311 RX DQ/DQS(RDDQC) : PASS
6050 20:14:49.479924 TX DQ/DQS : PASS
6051 20:14:49.483104 RX DATLAT : PASS
6052 20:14:49.483181 RX DQ/DQS(Engine): PASS
6053 20:14:49.486564 TX OE : NO K
6054 20:14:49.486641 All Pass.
6055 20:14:49.486704
6056 20:14:49.489972 CH 1, Rank 1
6057 20:14:49.490063 SW Impedance : PASS
6058 20:14:49.493296 DUTY Scan : NO K
6059 20:14:49.496444 ZQ Calibration : PASS
6060 20:14:49.496569 Jitter Meter : NO K
6061 20:14:49.499603 CBT Training : PASS
6062 20:14:49.503183 Write leveling : PASS
6063 20:14:49.503307 RX DQS gating : PASS
6064 20:14:49.506413 RX DQ/DQS(RDDQC) : PASS
6065 20:14:49.506539 TX DQ/DQS : PASS
6066 20:14:49.509571 RX DATLAT : PASS
6067 20:14:49.512820 RX DQ/DQS(Engine): PASS
6068 20:14:49.512944 TX OE : NO K
6069 20:14:49.516746 All Pass.
6070 20:14:49.516828
6071 20:14:49.516913 DramC Write-DBI off
6072 20:14:49.519450 PER_BANK_REFRESH: Hybrid Mode
6073 20:14:49.523301 TX_TRACKING: ON
6074 20:14:49.529624 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6075 20:14:49.532720 [FAST_K] Save calibration result to emmc
6076 20:14:49.539721 dramc_set_vcore_voltage set vcore to 650000
6077 20:14:49.539822 Read voltage for 400, 6
6078 20:14:49.539893 Vio18 = 0
6079 20:14:49.542735 Vcore = 650000
6080 20:14:49.542812 Vdram = 0
6081 20:14:49.542911 Vddq = 0
6082 20:14:49.546181 Vmddr = 0
6083 20:14:49.549654 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6084 20:14:49.556091 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6085 20:14:49.556204 MEM_TYPE=3, freq_sel=20
6086 20:14:49.559645 sv_algorithm_assistance_LP4_800
6087 20:14:49.566177 ============ PULL DRAM RESETB DOWN ============
6088 20:14:49.569899 ========== PULL DRAM RESETB DOWN end =========
6089 20:14:49.572975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6090 20:14:49.576071 ===================================
6091 20:14:49.579852 LPDDR4 DRAM CONFIGURATION
6092 20:14:49.583034 ===================================
6093 20:14:49.583140 EX_ROW_EN[0] = 0x0
6094 20:14:49.586070 EX_ROW_EN[1] = 0x0
6095 20:14:49.589200 LP4Y_EN = 0x0
6096 20:14:49.589327 WORK_FSP = 0x0
6097 20:14:49.593052 WL = 0x2
6098 20:14:49.593158 RL = 0x2
6099 20:14:49.595988 BL = 0x2
6100 20:14:49.596111 RPST = 0x0
6101 20:14:49.599384 RD_PRE = 0x0
6102 20:14:49.599508 WR_PRE = 0x1
6103 20:14:49.602763 WR_PST = 0x0
6104 20:14:49.602887 DBI_WR = 0x0
6105 20:14:49.605882 DBI_RD = 0x0
6106 20:14:49.606002 OTF = 0x1
6107 20:14:49.608982 ===================================
6108 20:14:49.612503 ===================================
6109 20:14:49.615919 ANA top config
6110 20:14:49.619195 ===================================
6111 20:14:49.622825 DLL_ASYNC_EN = 0
6112 20:14:49.622950 ALL_SLAVE_EN = 1
6113 20:14:49.625930 NEW_RANK_MODE = 1
6114 20:14:49.629383 DLL_IDLE_MODE = 1
6115 20:14:49.632511 LP45_APHY_COMB_EN = 1
6116 20:14:49.632633 TX_ODT_DIS = 1
6117 20:14:49.636175 NEW_8X_MODE = 1
6118 20:14:49.639268 ===================================
6119 20:14:49.642453 ===================================
6120 20:14:49.645568 data_rate = 800
6121 20:14:49.649165 CKR = 1
6122 20:14:49.652227 DQ_P2S_RATIO = 4
6123 20:14:49.656054 ===================================
6124 20:14:49.659118 CA_P2S_RATIO = 4
6125 20:14:49.659233 DQ_CA_OPEN = 0
6126 20:14:49.662065 DQ_SEMI_OPEN = 1
6127 20:14:49.665682 CA_SEMI_OPEN = 1
6128 20:14:49.669054 CA_FULL_RATE = 0
6129 20:14:49.672065 DQ_CKDIV4_EN = 0
6130 20:14:49.675813 CA_CKDIV4_EN = 1
6131 20:14:49.675899 CA_PREDIV_EN = 0
6132 20:14:49.678945 PH8_DLY = 0
6133 20:14:49.682081 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6134 20:14:49.685969 DQ_AAMCK_DIV = 0
6135 20:14:49.689026 CA_AAMCK_DIV = 0
6136 20:14:49.692113 CA_ADMCK_DIV = 4
6137 20:14:49.692214 DQ_TRACK_CA_EN = 0
6138 20:14:49.695297 CA_PICK = 800
6139 20:14:49.699005 CA_MCKIO = 400
6140 20:14:49.702100 MCKIO_SEMI = 400
6141 20:14:49.705789 PLL_FREQ = 3016
6142 20:14:49.708807 DQ_UI_PI_RATIO = 32
6143 20:14:49.712164 CA_UI_PI_RATIO = 32
6144 20:14:49.715339 ===================================
6145 20:14:49.718441 ===================================
6146 20:14:49.718565 memory_type:LPDDR4
6147 20:14:49.722190 GP_NUM : 10
6148 20:14:49.725222 SRAM_EN : 1
6149 20:14:49.725305 MD32_EN : 0
6150 20:14:49.728309 ===================================
6151 20:14:49.731952 [ANA_INIT] >>>>>>>>>>>>>>
6152 20:14:49.735309 <<<<<< [CONFIGURE PHASE]: ANA_TX
6153 20:14:49.738524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6154 20:14:49.741580 ===================================
6155 20:14:49.745258 data_rate = 800,PCW = 0X7400
6156 20:14:49.748368 ===================================
6157 20:14:49.751517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6158 20:14:49.755139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 20:14:49.768364 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 20:14:49.771485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6161 20:14:49.774974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6162 20:14:49.778554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6163 20:14:49.781564 [ANA_INIT] flow start
6164 20:14:49.785238 [ANA_INIT] PLL >>>>>>>>
6165 20:14:49.785315 [ANA_INIT] PLL <<<<<<<<
6166 20:14:49.787982 [ANA_INIT] MIDPI >>>>>>>>
6167 20:14:49.791464 [ANA_INIT] MIDPI <<<<<<<<
6168 20:14:49.791547 [ANA_INIT] DLL >>>>>>>>
6169 20:14:49.795008 [ANA_INIT] flow end
6170 20:14:49.798063 ============ LP4 DIFF to SE enter ============
6171 20:14:49.801793 ============ LP4 DIFF to SE exit ============
6172 20:14:49.804856 [ANA_INIT] <<<<<<<<<<<<<
6173 20:14:49.808151 [Flow] Enable top DCM control >>>>>
6174 20:14:49.811887 [Flow] Enable top DCM control <<<<<
6175 20:14:49.814728 Enable DLL master slave shuffle
6176 20:14:49.821239 ==============================================================
6177 20:14:49.821350 Gating Mode config
6178 20:14:49.827984 ==============================================================
6179 20:14:49.828099 Config description:
6180 20:14:49.837983 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6181 20:14:49.844369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6182 20:14:49.851385 SELPH_MODE 0: By rank 1: By Phase
6183 20:14:49.854752 ==============================================================
6184 20:14:49.857807 GAT_TRACK_EN = 0
6185 20:14:49.861053 RX_GATING_MODE = 2
6186 20:14:49.864474 RX_GATING_TRACK_MODE = 2
6187 20:14:49.867634 SELPH_MODE = 1
6188 20:14:49.871355 PICG_EARLY_EN = 1
6189 20:14:49.874510 VALID_LAT_VALUE = 1
6190 20:14:49.880920 ==============================================================
6191 20:14:49.884651 Enter into Gating configuration >>>>
6192 20:14:49.887822 Exit from Gating configuration <<<<
6193 20:14:49.890846 Enter into DVFS_PRE_config >>>>>
6194 20:14:49.900892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6195 20:14:49.904170 Exit from DVFS_PRE_config <<<<<
6196 20:14:49.907599 Enter into PICG configuration >>>>
6197 20:14:49.910868 Exit from PICG configuration <<<<
6198 20:14:49.914550 [RX_INPUT] configuration >>>>>
6199 20:14:49.914655 [RX_INPUT] configuration <<<<<
6200 20:14:49.920623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6201 20:14:49.927211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6202 20:14:49.931058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 20:14:49.937149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 20:14:49.944080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 20:14:49.950459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 20:14:49.954211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6207 20:14:49.957277 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6208 20:14:49.964245 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6209 20:14:49.967279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6210 20:14:49.970375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6211 20:14:49.977117 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 20:14:49.977195 ===================================
6213 20:14:49.980429 LPDDR4 DRAM CONFIGURATION
6214 20:14:49.984064 ===================================
6215 20:14:49.987121 EX_ROW_EN[0] = 0x0
6216 20:14:49.987200 EX_ROW_EN[1] = 0x0
6217 20:14:49.990714 LP4Y_EN = 0x0
6218 20:14:49.990797 WORK_FSP = 0x0
6219 20:14:49.994007 WL = 0x2
6220 20:14:49.994088 RL = 0x2
6221 20:14:49.997216 BL = 0x2
6222 20:14:49.997298 RPST = 0x0
6223 20:14:50.000644 RD_PRE = 0x0
6224 20:14:50.003621 WR_PRE = 0x1
6225 20:14:50.003703 WR_PST = 0x0
6226 20:14:50.007037 DBI_WR = 0x0
6227 20:14:50.007119 DBI_RD = 0x0
6228 20:14:50.010630 OTF = 0x1
6229 20:14:50.013995 ===================================
6230 20:14:50.016820 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6231 20:14:50.020155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6232 20:14:50.023641 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 20:14:50.027191 ===================================
6234 20:14:50.030259 LPDDR4 DRAM CONFIGURATION
6235 20:14:50.033825 ===================================
6236 20:14:50.036826 EX_ROW_EN[0] = 0x10
6237 20:14:50.036910 EX_ROW_EN[1] = 0x0
6238 20:14:50.039996 LP4Y_EN = 0x0
6239 20:14:50.040079 WORK_FSP = 0x0
6240 20:14:50.043685 WL = 0x2
6241 20:14:50.043768 RL = 0x2
6242 20:14:50.046848 BL = 0x2
6243 20:14:50.046960 RPST = 0x0
6244 20:14:50.050044 RD_PRE = 0x0
6245 20:14:50.053183 WR_PRE = 0x1
6246 20:14:50.053271 WR_PST = 0x0
6247 20:14:50.056930 DBI_WR = 0x0
6248 20:14:50.057007 DBI_RD = 0x0
6249 20:14:50.060136 OTF = 0x1
6250 20:14:50.063253 ===================================
6251 20:14:50.066962 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6252 20:14:50.072000 nWR fixed to 30
6253 20:14:50.075164 [ModeRegInit_LP4] CH0 RK0
6254 20:14:50.075255 [ModeRegInit_LP4] CH0 RK1
6255 20:14:50.078924 [ModeRegInit_LP4] CH1 RK0
6256 20:14:50.082077 [ModeRegInit_LP4] CH1 RK1
6257 20:14:50.082153 match AC timing 19
6258 20:14:50.088843 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6259 20:14:50.091872 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6260 20:14:50.095117 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6261 20:14:50.101782 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6262 20:14:50.105302 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6263 20:14:50.105386 ==
6264 20:14:50.108518 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 20:14:50.111835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 20:14:50.111960 ==
6267 20:14:50.118392 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 20:14:50.125007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6269 20:14:50.128188 [CA 0] Center 36 (8~64) winsize 57
6270 20:14:50.131375 [CA 1] Center 36 (8~64) winsize 57
6271 20:14:50.135088 [CA 2] Center 36 (8~64) winsize 57
6272 20:14:50.138094 [CA 3] Center 36 (8~64) winsize 57
6273 20:14:50.138205 [CA 4] Center 36 (8~64) winsize 57
6274 20:14:50.141906 [CA 5] Center 36 (8~64) winsize 57
6275 20:14:50.142015
6276 20:14:50.148435 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6277 20:14:50.148543
6278 20:14:50.151552 [CATrainingPosCal] consider 1 rank data
6279 20:14:50.154490 u2DelayCellTimex100 = 270/100 ps
6280 20:14:50.158271 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 20:14:50.161437 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 20:14:50.165171 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 20:14:50.168258 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 20:14:50.171394 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 20:14:50.174537 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 20:14:50.174639
6287 20:14:50.178375 CA PerBit enable=1, Macro0, CA PI delay=36
6288 20:14:50.178492
6289 20:14:50.181379 [CBTSetCACLKResult] CA Dly = 36
6290 20:14:50.184502 CS Dly: 1 (0~32)
6291 20:14:50.184610 ==
6292 20:14:50.188186 Dram Type= 6, Freq= 0, CH_0, rank 1
6293 20:14:50.191186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 20:14:50.191303 ==
6295 20:14:50.198262 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 20:14:50.204408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6297 20:14:50.204517 [CA 0] Center 36 (8~64) winsize 57
6298 20:14:50.207579 [CA 1] Center 36 (8~64) winsize 57
6299 20:14:50.211398 [CA 2] Center 36 (8~64) winsize 57
6300 20:14:50.214481 [CA 3] Center 36 (8~64) winsize 57
6301 20:14:50.217792 [CA 4] Center 36 (8~64) winsize 57
6302 20:14:50.221227 [CA 5] Center 36 (8~64) winsize 57
6303 20:14:50.221338
6304 20:14:50.224298 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6305 20:14:50.224376
6306 20:14:50.227418 [CATrainingPosCal] consider 2 rank data
6307 20:14:50.231198 u2DelayCellTimex100 = 270/100 ps
6308 20:14:50.234145 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 20:14:50.240953 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 20:14:50.244233 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 20:14:50.247537 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 20:14:50.250918 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 20:14:50.254375 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 20:14:50.254497
6315 20:14:50.257807 CA PerBit enable=1, Macro0, CA PI delay=36
6316 20:14:50.257930
6317 20:14:50.261239 [CBTSetCACLKResult] CA Dly = 36
6318 20:14:50.261361 CS Dly: 1 (0~32)
6319 20:14:50.261473
6320 20:14:50.267310 ----->DramcWriteLeveling(PI) begin...
6321 20:14:50.267437 ==
6322 20:14:50.270870 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 20:14:50.274185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 20:14:50.274289 ==
6325 20:14:50.277242 Write leveling (Byte 0): 40 => 8
6326 20:14:50.280522 Write leveling (Byte 1): 40 => 8
6327 20:14:50.284227 DramcWriteLeveling(PI) end<-----
6328 20:14:50.284337
6329 20:14:50.284440 ==
6330 20:14:50.287472 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 20:14:50.290536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 20:14:50.290641 ==
6333 20:14:50.294171 [Gating] SW mode calibration
6334 20:14:50.300568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6335 20:14:50.307298 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6336 20:14:50.310346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 20:14:50.314150 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 20:14:50.320424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 20:14:50.324009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 20:14:50.327013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 20:14:50.333724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 20:14:50.336852 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 20:14:50.340548 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 20:14:50.343653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 20:14:50.346806 Total UI for P1: 0, mck2ui 16
6346 20:14:50.350453 best dqsien dly found for B0: ( 0, 14, 24)
6347 20:14:50.353473 Total UI for P1: 0, mck2ui 16
6348 20:14:50.357191 best dqsien dly found for B1: ( 0, 14, 24)
6349 20:14:50.360168 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6350 20:14:50.366946 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6351 20:14:50.367029
6352 20:14:50.370520 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 20:14:50.373672 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 20:14:50.377399 [Gating] SW calibration Done
6355 20:14:50.377508 ==
6356 20:14:50.380271 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 20:14:50.383842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 20:14:50.383945 ==
6359 20:14:50.386806 RX Vref Scan: 0
6360 20:14:50.386910
6361 20:14:50.387006 RX Vref 0 -> 0, step: 1
6362 20:14:50.387097
6363 20:14:50.390337 RX Delay -410 -> 252, step: 16
6364 20:14:50.393598 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6365 20:14:50.400415 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6366 20:14:50.403543 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6367 20:14:50.406948 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6368 20:14:50.409926 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6369 20:14:50.416781 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6370 20:14:50.419993 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6371 20:14:50.423760 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6372 20:14:50.426957 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6373 20:14:50.433624 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6374 20:14:50.436641 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6375 20:14:50.440260 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6376 20:14:50.443390 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6377 20:14:50.449989 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6378 20:14:50.453650 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6379 20:14:50.456589 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6380 20:14:50.456693 ==
6381 20:14:50.460345 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 20:14:50.466991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 20:14:50.467098 ==
6384 20:14:50.467190 DQS Delay:
6385 20:14:50.469776 DQS0 = 27, DQS1 = 35
6386 20:14:50.469881 DQM Delay:
6387 20:14:50.469977 DQM0 = 8, DQM1 = 11
6388 20:14:50.473337 DQ Delay:
6389 20:14:50.477026 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6390 20:14:50.477130 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6391 20:14:50.480076 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6392 20:14:50.483065 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6393 20:14:50.483194
6394 20:14:50.483310
6395 20:14:50.486790 ==
6396 20:14:50.489947 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 20:14:50.493080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 20:14:50.493208 ==
6399 20:14:50.493321
6400 20:14:50.493433
6401 20:14:50.496360 TX Vref Scan disable
6402 20:14:50.496483 == TX Byte 0 ==
6403 20:14:50.499973 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 20:14:50.506685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 20:14:50.506811 == TX Byte 1 ==
6406 20:14:50.509952 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 20:14:50.513050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 20:14:50.516483 ==
6409 20:14:50.519922 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 20:14:50.523330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 20:14:50.523413 ==
6412 20:14:50.523478
6413 20:14:50.523538
6414 20:14:50.526493 TX Vref Scan disable
6415 20:14:50.526574 == TX Byte 0 ==
6416 20:14:50.529540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 20:14:50.536472 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 20:14:50.536555 == TX Byte 1 ==
6419 20:14:50.539471 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 20:14:50.546501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 20:14:50.546584
6422 20:14:50.546648 [DATLAT]
6423 20:14:50.546709 Freq=400, CH0 RK0
6424 20:14:50.546767
6425 20:14:50.549594 DATLAT Default: 0xf
6426 20:14:50.549675 0, 0xFFFF, sum = 0
6427 20:14:50.553287 1, 0xFFFF, sum = 0
6428 20:14:50.556605 2, 0xFFFF, sum = 0
6429 20:14:50.556698 3, 0xFFFF, sum = 0
6430 20:14:50.559581 4, 0xFFFF, sum = 0
6431 20:14:50.559704 5, 0xFFFF, sum = 0
6432 20:14:50.562666 6, 0xFFFF, sum = 0
6433 20:14:50.562772 7, 0xFFFF, sum = 0
6434 20:14:50.566480 8, 0xFFFF, sum = 0
6435 20:14:50.566590 9, 0xFFFF, sum = 0
6436 20:14:50.569604 10, 0xFFFF, sum = 0
6437 20:14:50.569681 11, 0xFFFF, sum = 0
6438 20:14:50.572635 12, 0xFFFF, sum = 0
6439 20:14:50.572723 13, 0x0, sum = 1
6440 20:14:50.575987 14, 0x0, sum = 2
6441 20:14:50.576099 15, 0x0, sum = 3
6442 20:14:50.579471 16, 0x0, sum = 4
6443 20:14:50.579576 best_step = 14
6444 20:14:50.579674
6445 20:14:50.579764 ==
6446 20:14:50.583008 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 20:14:50.586499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 20:14:50.586608 ==
6449 20:14:50.589589 RX Vref Scan: 1
6450 20:14:50.589670
6451 20:14:50.592818 RX Vref 0 -> 0, step: 1
6452 20:14:50.592897
6453 20:14:50.592959 RX Delay -311 -> 252, step: 8
6454 20:14:50.596614
6455 20:14:50.596714 Set Vref, RX VrefLevel [Byte0]: 57
6456 20:14:50.599715 [Byte1]: 46
6457 20:14:50.605309
6458 20:14:50.605384 Final RX Vref Byte 0 = 57 to rank0
6459 20:14:50.608481 Final RX Vref Byte 1 = 46 to rank0
6460 20:14:50.611706 Final RX Vref Byte 0 = 57 to rank1
6461 20:14:50.614891 Final RX Vref Byte 1 = 46 to rank1==
6462 20:14:50.618612 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 20:14:50.625487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 20:14:50.625599 ==
6465 20:14:50.625701 DQS Delay:
6466 20:14:50.628415 DQS0 = 28, DQS1 = 36
6467 20:14:50.628489 DQM Delay:
6468 20:14:50.628552 DQM0 = 11, DQM1 = 13
6469 20:14:50.631792 DQ Delay:
6470 20:14:50.634999 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6471 20:14:50.635140 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6472 20:14:50.638370 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6473 20:14:50.641954 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6474 20:14:50.642043
6475 20:14:50.645179
6476 20:14:50.651652 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6477 20:14:50.655067 CH0 RK0: MR19=C0C, MR18=CDBA
6478 20:14:50.661727 CH0_RK0: MR19=0xC0C, MR18=0xCDBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6479 20:14:50.661859 ==
6480 20:14:50.664599 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 20:14:50.668177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 20:14:50.668320 ==
6483 20:14:50.671279 [Gating] SW mode calibration
6484 20:14:50.678149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6485 20:14:50.684603 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6486 20:14:50.688052 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 20:14:50.691221 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 20:14:50.694694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 20:14:50.701277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 20:14:50.705076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 20:14:50.708215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 20:14:50.715102 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 20:14:50.718105 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 20:14:50.721702 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 20:14:50.724839 Total UI for P1: 0, mck2ui 16
6496 20:14:50.727978 best dqsien dly found for B0: ( 0, 14, 24)
6497 20:14:50.731651 Total UI for P1: 0, mck2ui 16
6498 20:14:50.734776 best dqsien dly found for B1: ( 0, 14, 24)
6499 20:14:50.738418 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6500 20:14:50.741658 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6501 20:14:50.744756
6502 20:14:50.748453 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 20:14:50.751214 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 20:14:50.754882 [Gating] SW calibration Done
6505 20:14:50.754990 ==
6506 20:14:50.758125 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 20:14:50.761444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 20:14:50.761528 ==
6509 20:14:50.761594 RX Vref Scan: 0
6510 20:14:50.764571
6511 20:14:50.764647 RX Vref 0 -> 0, step: 1
6512 20:14:50.764710
6513 20:14:50.767951 RX Delay -410 -> 252, step: 16
6514 20:14:50.771260 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6515 20:14:50.777985 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6516 20:14:50.781045 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6517 20:14:50.784737 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6518 20:14:50.788212 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6519 20:14:50.794883 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6520 20:14:50.798044 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6521 20:14:50.801230 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6522 20:14:50.804819 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6523 20:14:50.807788 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6524 20:14:50.814554 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6525 20:14:50.817758 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6526 20:14:50.821482 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6527 20:14:50.827859 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6528 20:14:50.830987 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6529 20:14:50.834764 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6530 20:14:50.834872 ==
6531 20:14:50.837820 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 20:14:50.840997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 20:14:50.841075 ==
6534 20:14:50.844667 DQS Delay:
6535 20:14:50.844813 DQS0 = 19, DQS1 = 35
6536 20:14:50.847647 DQM Delay:
6537 20:14:50.847775 DQM0 = 10, DQM1 = 16
6538 20:14:50.851249 DQ Delay:
6539 20:14:50.851374 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6540 20:14:50.854234 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6541 20:14:50.857565 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6542 20:14:50.861339 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6543 20:14:50.861466
6544 20:14:50.861597
6545 20:14:50.861712 ==
6546 20:14:50.864595 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 20:14:50.871275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 20:14:50.871407 ==
6549 20:14:50.871521
6550 20:14:50.871644
6551 20:14:50.871764 TX Vref Scan disable
6552 20:14:50.874388 == TX Byte 0 ==
6553 20:14:50.877663 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6554 20:14:50.880905 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6555 20:14:50.884104 == TX Byte 1 ==
6556 20:14:50.887524 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6557 20:14:50.890918 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6558 20:14:50.894401 ==
6559 20:14:50.894508 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 20:14:50.900713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 20:14:50.900796 ==
6562 20:14:50.900898
6563 20:14:50.900998
6564 20:14:50.903995 TX Vref Scan disable
6565 20:14:50.904116 == TX Byte 0 ==
6566 20:14:50.907476 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6567 20:14:50.910934 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6568 20:14:50.913927 == TX Byte 1 ==
6569 20:14:50.917281 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6570 20:14:50.920600 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6571 20:14:50.924396
6572 20:14:50.924478 [DATLAT]
6573 20:14:50.924553 Freq=400, CH0 RK1
6574 20:14:50.924617
6575 20:14:50.927539 DATLAT Default: 0xe
6576 20:14:50.927620 0, 0xFFFF, sum = 0
6577 20:14:50.930760 1, 0xFFFF, sum = 0
6578 20:14:50.930844 2, 0xFFFF, sum = 0
6579 20:14:50.933885 3, 0xFFFF, sum = 0
6580 20:14:50.934014 4, 0xFFFF, sum = 0
6581 20:14:50.937674 5, 0xFFFF, sum = 0
6582 20:14:50.937802 6, 0xFFFF, sum = 0
6583 20:14:50.940747 7, 0xFFFF, sum = 0
6584 20:14:50.943696 8, 0xFFFF, sum = 0
6585 20:14:50.943821 9, 0xFFFF, sum = 0
6586 20:14:50.947536 10, 0xFFFF, sum = 0
6587 20:14:50.947661 11, 0xFFFF, sum = 0
6588 20:14:50.950813 12, 0xFFFF, sum = 0
6589 20:14:50.950936 13, 0x0, sum = 1
6590 20:14:50.953920 14, 0x0, sum = 2
6591 20:14:50.954043 15, 0x0, sum = 3
6592 20:14:50.957328 16, 0x0, sum = 4
6593 20:14:50.957450 best_step = 14
6594 20:14:50.957563
6595 20:14:50.957673 ==
6596 20:14:50.960497 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 20:14:50.963655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 20:14:50.963775 ==
6599 20:14:50.967275 RX Vref Scan: 0
6600 20:14:50.967396
6601 20:14:50.970479 RX Vref 0 -> 0, step: 1
6602 20:14:50.970600
6603 20:14:50.970711 RX Delay -311 -> 252, step: 8
6604 20:14:50.979434 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6605 20:14:50.982437 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6606 20:14:50.985686 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6607 20:14:50.989097 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6608 20:14:50.995547 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6609 20:14:50.999281 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6610 20:14:51.002408 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6611 20:14:51.005563 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6612 20:14:51.012163 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6613 20:14:51.015142 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6614 20:14:51.018537 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6615 20:14:51.025058 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6616 20:14:51.028373 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6617 20:14:51.031923 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6618 20:14:51.035359 iDelay=217, Bit 14, Center -16 (-231 ~ 200) 432
6619 20:14:51.041853 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6620 20:14:51.041937 ==
6621 20:14:51.045439 Dram Type= 6, Freq= 0, CH_0, rank 1
6622 20:14:51.048785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 20:14:51.048869 ==
6624 20:14:51.048936 DQS Delay:
6625 20:14:51.051769 DQS0 = 24, DQS1 = 36
6626 20:14:51.051851 DQM Delay:
6627 20:14:51.055068 DQM0 = 8, DQM1 = 12
6628 20:14:51.055151 DQ Delay:
6629 20:14:51.058530 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6630 20:14:51.061557 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6631 20:14:51.065227 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6632 20:14:51.068247 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6633 20:14:51.068336
6634 20:14:51.068403
6635 20:14:51.075164 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6636 20:14:51.078420 CH0 RK1: MR19=C0C, MR18=B959
6637 20:14:51.085211 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6638 20:14:51.088320 [RxdqsGatingPostProcess] freq 400
6639 20:14:51.095200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6640 20:14:51.095285 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 20:14:51.098202 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 20:14:51.101538 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 20:14:51.104844 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 20:14:51.108240 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 20:14:51.111492 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 20:14:51.114648 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 20:14:51.118438 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 20:14:51.121382 Pre-setting of DQS Precalculation
6649 20:14:51.128398 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6650 20:14:51.128490 ==
6651 20:14:51.131429 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 20:14:51.134787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 20:14:51.134871 ==
6654 20:14:51.141836 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 20:14:51.144986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6656 20:14:51.148211 [CA 0] Center 36 (8~64) winsize 57
6657 20:14:51.151363 [CA 1] Center 36 (8~64) winsize 57
6658 20:14:51.154848 [CA 2] Center 36 (8~64) winsize 57
6659 20:14:51.158130 [CA 3] Center 36 (8~64) winsize 57
6660 20:14:51.161651 [CA 4] Center 36 (8~64) winsize 57
6661 20:14:51.165220 [CA 5] Center 36 (8~64) winsize 57
6662 20:14:51.165302
6663 20:14:51.167979 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6664 20:14:51.168062
6665 20:14:51.171683 [CATrainingPosCal] consider 1 rank data
6666 20:14:51.174633 u2DelayCellTimex100 = 270/100 ps
6667 20:14:51.177918 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 20:14:51.181237 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 20:14:51.184719 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 20:14:51.191111 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 20:14:51.194284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 20:14:51.197520 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 20:14:51.197604
6674 20:14:51.201294 CA PerBit enable=1, Macro0, CA PI delay=36
6675 20:14:51.201378
6676 20:14:51.204446 [CBTSetCACLKResult] CA Dly = 36
6677 20:14:51.204528 CS Dly: 1 (0~32)
6678 20:14:51.204594 ==
6679 20:14:51.207527 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 20:14:51.214330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 20:14:51.214414 ==
6682 20:14:51.217753 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 20:14:51.224470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6684 20:14:51.227594 [CA 0] Center 36 (8~64) winsize 57
6685 20:14:51.230616 [CA 1] Center 36 (8~64) winsize 57
6686 20:14:51.234401 [CA 2] Center 36 (8~64) winsize 57
6687 20:14:51.237622 [CA 3] Center 36 (8~64) winsize 57
6688 20:14:51.241299 [CA 4] Center 36 (8~64) winsize 57
6689 20:14:51.244138 [CA 5] Center 36 (8~64) winsize 57
6690 20:14:51.244252
6691 20:14:51.247570 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6692 20:14:51.247678
6693 20:14:51.250568 [CATrainingPosCal] consider 2 rank data
6694 20:14:51.254218 u2DelayCellTimex100 = 270/100 ps
6695 20:14:51.257808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 20:14:51.260712 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 20:14:51.264297 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 20:14:51.267198 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 20:14:51.270719 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 20:14:51.273991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 20:14:51.274098
6702 20:14:51.280757 CA PerBit enable=1, Macro0, CA PI delay=36
6703 20:14:51.280843
6704 20:14:51.284451 [CBTSetCACLKResult] CA Dly = 36
6705 20:14:51.284546 CS Dly: 1 (0~32)
6706 20:14:51.284612
6707 20:14:51.287353 ----->DramcWriteLeveling(PI) begin...
6708 20:14:51.287464 ==
6709 20:14:51.290612 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 20:14:51.294168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 20:14:51.294248 ==
6712 20:14:51.297290 Write leveling (Byte 0): 40 => 8
6713 20:14:51.300503 Write leveling (Byte 1): 40 => 8
6714 20:14:51.304091 DramcWriteLeveling(PI) end<-----
6715 20:14:51.304197
6716 20:14:51.304294 ==
6717 20:14:51.307398 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 20:14:51.310547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 20:14:51.313740 ==
6720 20:14:51.313815 [Gating] SW mode calibration
6721 20:14:51.324315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6722 20:14:51.327169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6723 20:14:51.330506 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 20:14:51.337202 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 20:14:51.340418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 20:14:51.343549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 20:14:51.350381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 20:14:51.353914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 20:14:51.357282 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 20:14:51.363922 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 20:14:51.367067 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 20:14:51.370623 Total UI for P1: 0, mck2ui 16
6733 20:14:51.373533 best dqsien dly found for B0: ( 0, 14, 24)
6734 20:14:51.376916 Total UI for P1: 0, mck2ui 16
6735 20:14:51.380527 best dqsien dly found for B1: ( 0, 14, 24)
6736 20:14:51.383586 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6737 20:14:51.386790 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6738 20:14:51.386921
6739 20:14:51.390057 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 20:14:51.393866 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 20:14:51.396870 [Gating] SW calibration Done
6742 20:14:51.396948 ==
6743 20:14:51.400430 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 20:14:51.406735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 20:14:51.406812 ==
6746 20:14:51.406875 RX Vref Scan: 0
6747 20:14:51.406936
6748 20:14:51.410385 RX Vref 0 -> 0, step: 1
6749 20:14:51.410482
6750 20:14:51.413397 RX Delay -410 -> 252, step: 16
6751 20:14:51.416667 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6752 20:14:51.419868 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6753 20:14:51.423321 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6754 20:14:51.430055 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6755 20:14:51.433257 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6756 20:14:51.436714 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6757 20:14:51.440294 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6758 20:14:51.447285 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6759 20:14:51.450378 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6760 20:14:51.453520 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6761 20:14:51.456798 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6762 20:14:51.463243 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6763 20:14:51.466669 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6764 20:14:51.470054 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6765 20:14:51.473758 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6766 20:14:51.480045 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6767 20:14:51.480161 ==
6768 20:14:51.483078 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 20:14:51.486506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 20:14:51.486607 ==
6771 20:14:51.489510 DQS Delay:
6772 20:14:51.489609 DQS0 = 27, DQS1 = 35
6773 20:14:51.489706 DQM Delay:
6774 20:14:51.493358 DQM0 = 10, DQM1 = 13
6775 20:14:51.493463 DQ Delay:
6776 20:14:51.496452 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6777 20:14:51.499550 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6778 20:14:51.503317 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6779 20:14:51.506371 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6780 20:14:51.506476
6781 20:14:51.506571
6782 20:14:51.506664 ==
6783 20:14:51.510011 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 20:14:51.513224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 20:14:51.513348 ==
6786 20:14:51.516256
6787 20:14:51.516387
6788 20:14:51.516504 TX Vref Scan disable
6789 20:14:51.520064 == TX Byte 0 ==
6790 20:14:51.523212 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 20:14:51.526269 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 20:14:51.529949 == TX Byte 1 ==
6793 20:14:51.533229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 20:14:51.536062 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 20:14:51.536169 ==
6796 20:14:51.539762 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 20:14:51.542801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 20:14:51.546316 ==
6799 20:14:51.546421
6800 20:14:51.546524
6801 20:14:51.546623 TX Vref Scan disable
6802 20:14:51.549356 == TX Byte 0 ==
6803 20:14:51.552669 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 20:14:51.555929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 20:14:51.559499 == TX Byte 1 ==
6806 20:14:51.562719 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 20:14:51.565867 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 20:14:51.565988
6809 20:14:51.566103 [DATLAT]
6810 20:14:51.569514 Freq=400, CH1 RK0
6811 20:14:51.569639
6812 20:14:51.573078 DATLAT Default: 0xf
6813 20:14:51.573203 0, 0xFFFF, sum = 0
6814 20:14:51.576461 1, 0xFFFF, sum = 0
6815 20:14:51.576590 2, 0xFFFF, sum = 0
6816 20:14:51.579743 3, 0xFFFF, sum = 0
6817 20:14:51.579850 4, 0xFFFF, sum = 0
6818 20:14:51.582598 5, 0xFFFF, sum = 0
6819 20:14:51.582716 6, 0xFFFF, sum = 0
6820 20:14:51.586148 7, 0xFFFF, sum = 0
6821 20:14:51.586268 8, 0xFFFF, sum = 0
6822 20:14:51.589264 9, 0xFFFF, sum = 0
6823 20:14:51.589389 10, 0xFFFF, sum = 0
6824 20:14:51.592788 11, 0xFFFF, sum = 0
6825 20:14:51.592910 12, 0xFFFF, sum = 0
6826 20:14:51.595795 13, 0x0, sum = 1
6827 20:14:51.595915 14, 0x0, sum = 2
6828 20:14:51.599432 15, 0x0, sum = 3
6829 20:14:51.599570 16, 0x0, sum = 4
6830 20:14:51.602624 best_step = 14
6831 20:14:51.602741
6832 20:14:51.602847 ==
6833 20:14:51.605860 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 20:14:51.609369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 20:14:51.609492 ==
6836 20:14:51.612430 RX Vref Scan: 1
6837 20:14:51.612551
6838 20:14:51.612663 RX Vref 0 -> 0, step: 1
6839 20:14:51.612774
6840 20:14:51.615939 RX Delay -311 -> 252, step: 8
6841 20:14:51.616062
6842 20:14:51.619079 Set Vref, RX VrefLevel [Byte0]: 54
6843 20:14:51.622258 [Byte1]: 54
6844 20:14:51.626769
6845 20:14:51.626892 Final RX Vref Byte 0 = 54 to rank0
6846 20:14:51.630023 Final RX Vref Byte 1 = 54 to rank0
6847 20:14:51.633834 Final RX Vref Byte 0 = 54 to rank1
6848 20:14:51.636892 Final RX Vref Byte 1 = 54 to rank1==
6849 20:14:51.640032 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 20:14:51.646699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 20:14:51.646805 ==
6852 20:14:51.646901 DQS Delay:
6853 20:14:51.650132 DQS0 = 28, DQS1 = 32
6854 20:14:51.650236 DQM Delay:
6855 20:14:51.650328 DQM0 = 9, DQM1 = 9
6856 20:14:51.653348 DQ Delay:
6857 20:14:51.656453 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6858 20:14:51.656531 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6859 20:14:51.660002 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6860 20:14:51.663348 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6861 20:14:51.663456
6862 20:14:51.663547
6863 20:14:51.673095 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6864 20:14:51.676548 CH1 RK0: MR19=C0C, MR18=8FC8
6865 20:14:51.683178 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6866 20:14:51.683307 ==
6867 20:14:51.686819 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 20:14:51.689954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 20:14:51.690073 ==
6870 20:14:51.693124 [Gating] SW mode calibration
6871 20:14:51.699609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6872 20:14:51.702932 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6873 20:14:51.709703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 20:14:51.712838 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 20:14:51.716508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 20:14:51.723108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 20:14:51.726200 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 20:14:51.729494 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 20:14:51.736109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 20:14:51.739930 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 20:14:51.743053 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 20:14:51.746224 Total UI for P1: 0, mck2ui 16
6883 20:14:51.749366 best dqsien dly found for B0: ( 0, 14, 24)
6884 20:14:51.753089 Total UI for P1: 0, mck2ui 16
6885 20:14:51.756192 best dqsien dly found for B1: ( 0, 14, 24)
6886 20:14:51.759262 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6887 20:14:51.762990 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6888 20:14:51.766140
6889 20:14:51.769270 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 20:14:51.772713 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 20:14:51.776234 [Gating] SW calibration Done
6892 20:14:51.776335 ==
6893 20:14:51.779455 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 20:14:51.782601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 20:14:51.782708 ==
6896 20:14:51.782802 RX Vref Scan: 0
6897 20:14:51.782892
6898 20:14:51.786135 RX Vref 0 -> 0, step: 1
6899 20:14:51.786240
6900 20:14:51.789377 RX Delay -410 -> 252, step: 16
6901 20:14:51.792623 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6902 20:14:51.799162 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6903 20:14:51.802382 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6904 20:14:51.806272 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6905 20:14:51.809131 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6906 20:14:51.816018 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6907 20:14:51.819577 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6908 20:14:51.822759 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6909 20:14:51.826021 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6910 20:14:51.829459 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6911 20:14:51.836367 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6912 20:14:51.839397 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6913 20:14:51.842549 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6914 20:14:51.849409 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6915 20:14:51.852533 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6916 20:14:51.855660 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6917 20:14:51.855778 ==
6918 20:14:51.858905 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 20:14:51.862524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 20:14:51.865775 ==
6921 20:14:51.865894 DQS Delay:
6922 20:14:51.866005 DQS0 = 35, DQS1 = 35
6923 20:14:51.869441 DQM Delay:
6924 20:14:51.869569 DQM0 = 18, DQM1 = 15
6925 20:14:51.872516 DQ Delay:
6926 20:14:51.875555 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6927 20:14:51.875684 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6928 20:14:51.879343 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6929 20:14:51.882504 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6930 20:14:51.882602
6931 20:14:51.882691
6932 20:14:51.885445 ==
6933 20:14:51.889393 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 20:14:51.892446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 20:14:51.892594 ==
6936 20:14:51.892714
6937 20:14:51.892821
6938 20:14:51.895755 TX Vref Scan disable
6939 20:14:51.895873 == TX Byte 0 ==
6940 20:14:51.899110 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6941 20:14:51.905413 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6942 20:14:51.905535 == TX Byte 1 ==
6943 20:14:51.908629 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6944 20:14:51.915740 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6945 20:14:51.915865 ==
6946 20:14:51.918920 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 20:14:51.922288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 20:14:51.922373 ==
6949 20:14:51.922454
6950 20:14:51.922545
6951 20:14:51.925773 TX Vref Scan disable
6952 20:14:51.925855 == TX Byte 0 ==
6953 20:14:51.928859 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6954 20:14:51.935676 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6955 20:14:51.935759 == TX Byte 1 ==
6956 20:14:51.938821 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6957 20:14:51.945208 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6958 20:14:51.945335
6959 20:14:51.945445 [DATLAT]
6960 20:14:51.945556 Freq=400, CH1 RK1
6961 20:14:51.945668
6962 20:14:51.948593 DATLAT Default: 0xe
6963 20:14:51.948676 0, 0xFFFF, sum = 0
6964 20:14:51.952264 1, 0xFFFF, sum = 0
6965 20:14:51.955215 2, 0xFFFF, sum = 0
6966 20:14:51.955298 3, 0xFFFF, sum = 0
6967 20:14:51.959141 4, 0xFFFF, sum = 0
6968 20:14:51.959224 5, 0xFFFF, sum = 0
6969 20:14:51.962159 6, 0xFFFF, sum = 0
6970 20:14:51.962243 7, 0xFFFF, sum = 0
6971 20:14:51.965197 8, 0xFFFF, sum = 0
6972 20:14:51.965281 9, 0xFFFF, sum = 0
6973 20:14:51.969043 10, 0xFFFF, sum = 0
6974 20:14:51.969138 11, 0xFFFF, sum = 0
6975 20:14:51.972169 12, 0xFFFF, sum = 0
6976 20:14:51.972310 13, 0x0, sum = 1
6977 20:14:51.975526 14, 0x0, sum = 2
6978 20:14:51.975616 15, 0x0, sum = 3
6979 20:14:51.978780 16, 0x0, sum = 4
6980 20:14:51.978920 best_step = 14
6981 20:14:51.979007
6982 20:14:51.979069 ==
6983 20:14:51.982057 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 20:14:51.985278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 20:14:51.988596 ==
6986 20:14:51.988696 RX Vref Scan: 0
6987 20:14:51.988775
6988 20:14:51.991601 RX Vref 0 -> 0, step: 1
6989 20:14:51.991698
6990 20:14:51.995337 RX Delay -311 -> 252, step: 8
6991 20:14:51.998682 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6992 20:14:52.005154 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6993 20:14:52.008193 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6994 20:14:52.011392 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6995 20:14:52.015201 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6996 20:14:52.021686 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6997 20:14:52.024717 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6998 20:14:52.028134 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6999 20:14:52.031825 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7000 20:14:52.038227 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7001 20:14:52.041545 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7002 20:14:52.044640 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7003 20:14:52.051349 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7004 20:14:52.054826 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7005 20:14:52.058367 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7006 20:14:52.061225 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7007 20:14:52.061301 ==
7008 20:14:52.064766 Dram Type= 6, Freq= 0, CH_1, rank 1
7009 20:14:52.071305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7010 20:14:52.071386 ==
7011 20:14:52.071449 DQS Delay:
7012 20:14:52.074479 DQS0 = 28, DQS1 = 36
7013 20:14:52.074555 DQM Delay:
7014 20:14:52.074627 DQM0 = 10, DQM1 = 14
7015 20:14:52.077814 DQ Delay:
7016 20:14:52.081710 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7017 20:14:52.084764 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7018 20:14:52.084839 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7019 20:14:52.087891 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7020 20:14:52.087962
7021 20:14:52.091630
7022 20:14:52.097895 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7023 20:14:52.101747 CH1 RK1: MR19=C0C, MR18=C455
7024 20:14:52.107995 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
7025 20:14:52.111604 [RxdqsGatingPostProcess] freq 400
7026 20:14:52.114599 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7027 20:14:52.118196 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 20:14:52.121293 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 20:14:52.125008 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 20:14:52.128175 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 20:14:52.131174 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 20:14:52.134652 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 20:14:52.138099 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 20:14:52.141102 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 20:14:52.145148 Pre-setting of DQS Precalculation
7036 20:14:52.147920 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7037 20:14:52.154783 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7038 20:14:52.161446 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7039 20:14:52.164628
7040 20:14:52.164711
7041 20:14:52.164776 [Calibration Summary] 800 Mbps
7042 20:14:52.168387 CH 0, Rank 0
7043 20:14:52.168470 SW Impedance : PASS
7044 20:14:52.171488 DUTY Scan : NO K
7045 20:14:52.174376 ZQ Calibration : PASS
7046 20:14:52.174486 Jitter Meter : NO K
7047 20:14:52.177886 CBT Training : PASS
7048 20:14:52.181177 Write leveling : PASS
7049 20:14:52.181261 RX DQS gating : PASS
7050 20:14:52.184529 RX DQ/DQS(RDDQC) : PASS
7051 20:14:52.187785 TX DQ/DQS : PASS
7052 20:14:52.187896 RX DATLAT : PASS
7053 20:14:52.191581 RX DQ/DQS(Engine): PASS
7054 20:14:52.194376 TX OE : NO K
7055 20:14:52.194458 All Pass.
7056 20:14:52.194523
7057 20:14:52.194583 CH 0, Rank 1
7058 20:14:52.198043 SW Impedance : PASS
7059 20:14:52.201238 DUTY Scan : NO K
7060 20:14:52.201321 ZQ Calibration : PASS
7061 20:14:52.204408 Jitter Meter : NO K
7062 20:14:52.208190 CBT Training : PASS
7063 20:14:52.208266 Write leveling : NO K
7064 20:14:52.211267 RX DQS gating : PASS
7065 20:14:52.211344 RX DQ/DQS(RDDQC) : PASS
7066 20:14:52.214325 TX DQ/DQS : PASS
7067 20:14:52.218036 RX DATLAT : PASS
7068 20:14:52.218111 RX DQ/DQS(Engine): PASS
7069 20:14:52.220995 TX OE : NO K
7070 20:14:52.221073 All Pass.
7071 20:14:52.221137
7072 20:14:52.224837 CH 1, Rank 0
7073 20:14:52.224913 SW Impedance : PASS
7074 20:14:52.227824 DUTY Scan : NO K
7075 20:14:52.230930 ZQ Calibration : PASS
7076 20:14:52.231004 Jitter Meter : NO K
7077 20:14:52.234619 CBT Training : PASS
7078 20:14:52.238204 Write leveling : PASS
7079 20:14:52.238283 RX DQS gating : PASS
7080 20:14:52.241510 RX DQ/DQS(RDDQC) : PASS
7081 20:14:52.244567 TX DQ/DQS : PASS
7082 20:14:52.244645 RX DATLAT : PASS
7083 20:14:52.247627 RX DQ/DQS(Engine): PASS
7084 20:14:52.247705 TX OE : NO K
7085 20:14:52.251325 All Pass.
7086 20:14:52.251398
7087 20:14:52.251459 CH 1, Rank 1
7088 20:14:52.254912 SW Impedance : PASS
7089 20:14:52.254984 DUTY Scan : NO K
7090 20:14:52.258095 ZQ Calibration : PASS
7091 20:14:52.261425 Jitter Meter : NO K
7092 20:14:52.261496 CBT Training : PASS
7093 20:14:52.264689 Write leveling : NO K
7094 20:14:52.268061 RX DQS gating : PASS
7095 20:14:52.268134 RX DQ/DQS(RDDQC) : PASS
7096 20:14:52.271644 TX DQ/DQS : PASS
7097 20:14:52.274775 RX DATLAT : PASS
7098 20:14:52.274849 RX DQ/DQS(Engine): PASS
7099 20:14:52.277782 TX OE : NO K
7100 20:14:52.277858 All Pass.
7101 20:14:52.277918
7102 20:14:52.281435 DramC Write-DBI off
7103 20:14:52.284497 PER_BANK_REFRESH: Hybrid Mode
7104 20:14:52.284570 TX_TRACKING: ON
7105 20:14:52.294473 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7106 20:14:52.297839 [FAST_K] Save calibration result to emmc
7107 20:14:52.301183 dramc_set_vcore_voltage set vcore to 725000
7108 20:14:52.304669 Read voltage for 1600, 0
7109 20:14:52.304747 Vio18 = 0
7110 20:14:52.304811 Vcore = 725000
7111 20:14:52.308131 Vdram = 0
7112 20:14:52.308211 Vddq = 0
7113 20:14:52.308274 Vmddr = 0
7114 20:14:52.314404 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7115 20:14:52.317479 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7116 20:14:52.321257 MEM_TYPE=3, freq_sel=13
7117 20:14:52.324354 sv_algorithm_assistance_LP4_3733
7118 20:14:52.327830 ============ PULL DRAM RESETB DOWN ============
7119 20:14:52.330796 ========== PULL DRAM RESETB DOWN end =========
7120 20:14:52.337680 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7121 20:14:52.340888 ===================================
7122 20:14:52.343943 LPDDR4 DRAM CONFIGURATION
7123 20:14:52.347600 ===================================
7124 20:14:52.347703 EX_ROW_EN[0] = 0x0
7125 20:14:52.351134 EX_ROW_EN[1] = 0x0
7126 20:14:52.351212 LP4Y_EN = 0x0
7127 20:14:52.354005 WORK_FSP = 0x1
7128 20:14:52.354084 WL = 0x5
7129 20:14:52.357182 RL = 0x5
7130 20:14:52.357256 BL = 0x2
7131 20:14:52.360897 RPST = 0x0
7132 20:14:52.360970 RD_PRE = 0x0
7133 20:14:52.364038 WR_PRE = 0x1
7134 20:14:52.364113 WR_PST = 0x1
7135 20:14:52.367249 DBI_WR = 0x0
7136 20:14:52.367326 DBI_RD = 0x0
7137 20:14:52.370725 OTF = 0x1
7138 20:14:52.373812 ===================================
7139 20:14:52.377519 ===================================
7140 20:14:52.377592 ANA top config
7141 20:14:52.380755 ===================================
7142 20:14:52.384198 DLL_ASYNC_EN = 0
7143 20:14:52.387244 ALL_SLAVE_EN = 0
7144 20:14:52.391024 NEW_RANK_MODE = 1
7145 20:14:52.391140 DLL_IDLE_MODE = 1
7146 20:14:52.394041 LP45_APHY_COMB_EN = 1
7147 20:14:52.397214 TX_ODT_DIS = 0
7148 20:14:52.400576 NEW_8X_MODE = 1
7149 20:14:52.404209 ===================================
7150 20:14:52.407357 ===================================
7151 20:14:52.410282 data_rate = 3200
7152 20:14:52.410387 CKR = 1
7153 20:14:52.413794 DQ_P2S_RATIO = 8
7154 20:14:52.417150 ===================================
7155 20:14:52.420590 CA_P2S_RATIO = 8
7156 20:14:52.423913 DQ_CA_OPEN = 0
7157 20:14:52.427133 DQ_SEMI_OPEN = 0
7158 20:14:52.430662 CA_SEMI_OPEN = 0
7159 20:14:52.430777 CA_FULL_RATE = 0
7160 20:14:52.433633 DQ_CKDIV4_EN = 0
7161 20:14:52.437363 CA_CKDIV4_EN = 0
7162 20:14:52.440393 CA_PREDIV_EN = 0
7163 20:14:52.443485 PH8_DLY = 12
7164 20:14:52.447272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7165 20:14:52.447378 DQ_AAMCK_DIV = 4
7166 20:14:52.450375 CA_AAMCK_DIV = 4
7167 20:14:52.453396 CA_ADMCK_DIV = 4
7168 20:14:52.456818 DQ_TRACK_CA_EN = 0
7169 20:14:52.460249 CA_PICK = 1600
7170 20:14:52.464104 CA_MCKIO = 1600
7171 20:14:52.467148 MCKIO_SEMI = 0
7172 20:14:52.467231 PLL_FREQ = 3068
7173 20:14:52.470121 DQ_UI_PI_RATIO = 32
7174 20:14:52.473890 CA_UI_PI_RATIO = 0
7175 20:14:52.477122 ===================================
7176 20:14:52.480182 ===================================
7177 20:14:52.483933 memory_type:LPDDR4
7178 20:14:52.484033 GP_NUM : 10
7179 20:14:52.487286 SRAM_EN : 1
7180 20:14:52.490593 MD32_EN : 0
7181 20:14:52.493832 ===================================
7182 20:14:52.493929 [ANA_INIT] >>>>>>>>>>>>>>
7183 20:14:52.497029 <<<<<< [CONFIGURE PHASE]: ANA_TX
7184 20:14:52.500369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7185 20:14:52.503527 ===================================
7186 20:14:52.507099 data_rate = 3200,PCW = 0X7600
7187 20:14:52.510589 ===================================
7188 20:14:52.513750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7189 20:14:52.520185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 20:14:52.523831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 20:14:52.530200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7192 20:14:52.533890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7193 20:14:52.536963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7194 20:14:52.540483 [ANA_INIT] flow start
7195 20:14:52.540590 [ANA_INIT] PLL >>>>>>>>
7196 20:14:52.543539 [ANA_INIT] PLL <<<<<<<<
7197 20:14:52.546742 [ANA_INIT] MIDPI >>>>>>>>
7198 20:14:52.546824 [ANA_INIT] MIDPI <<<<<<<<
7199 20:14:52.550530 [ANA_INIT] DLL >>>>>>>>
7200 20:14:52.553585 [ANA_INIT] DLL <<<<<<<<
7201 20:14:52.553668 [ANA_INIT] flow end
7202 20:14:52.557281 ============ LP4 DIFF to SE enter ============
7203 20:14:52.563990 ============ LP4 DIFF to SE exit ============
7204 20:14:52.564073 [ANA_INIT] <<<<<<<<<<<<<
7205 20:14:52.566734 [Flow] Enable top DCM control >>>>>
7206 20:14:52.570142 [Flow] Enable top DCM control <<<<<
7207 20:14:52.573737 Enable DLL master slave shuffle
7208 20:14:52.580090 ==============================================================
7209 20:14:52.580217 Gating Mode config
7210 20:14:52.586811 ==============================================================
7211 20:14:52.590504 Config description:
7212 20:14:52.600410 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7213 20:14:52.606847 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7214 20:14:52.610419 SELPH_MODE 0: By rank 1: By Phase
7215 20:14:52.617342 ==============================================================
7216 20:14:52.620265 GAT_TRACK_EN = 1
7217 20:14:52.620425 RX_GATING_MODE = 2
7218 20:14:52.623420 RX_GATING_TRACK_MODE = 2
7219 20:14:52.626974 SELPH_MODE = 1
7220 20:14:52.629999 PICG_EARLY_EN = 1
7221 20:14:52.633723 VALID_LAT_VALUE = 1
7222 20:14:52.640233 ==============================================================
7223 20:14:52.643385 Enter into Gating configuration >>>>
7224 20:14:52.646907 Exit from Gating configuration <<<<
7225 20:14:52.649869 Enter into DVFS_PRE_config >>>>>
7226 20:14:52.659942 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7227 20:14:52.663093 Exit from DVFS_PRE_config <<<<<
7228 20:14:52.666805 Enter into PICG configuration >>>>
7229 20:14:52.669757 Exit from PICG configuration <<<<
7230 20:14:52.673178 [RX_INPUT] configuration >>>>>
7231 20:14:52.676629 [RX_INPUT] configuration <<<<<
7232 20:14:52.679499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7233 20:14:52.686000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7234 20:14:52.692818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 20:14:52.699638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 20:14:52.703282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 20:14:52.709819 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 20:14:52.713024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7239 20:14:52.719907 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7240 20:14:52.723007 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7241 20:14:52.725979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7242 20:14:52.729665 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7243 20:14:52.735798 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 20:14:52.739539 ===================================
7245 20:14:52.739622 LPDDR4 DRAM CONFIGURATION
7246 20:14:52.742627 ===================================
7247 20:14:52.746390 EX_ROW_EN[0] = 0x0
7248 20:14:52.749729 EX_ROW_EN[1] = 0x0
7249 20:14:52.749812 LP4Y_EN = 0x0
7250 20:14:52.753032 WORK_FSP = 0x1
7251 20:14:52.753143 WL = 0x5
7252 20:14:52.755923 RL = 0x5
7253 20:14:52.756027 BL = 0x2
7254 20:14:52.759320 RPST = 0x0
7255 20:14:52.759425 RD_PRE = 0x0
7256 20:14:52.763193 WR_PRE = 0x1
7257 20:14:52.763275 WR_PST = 0x1
7258 20:14:52.766215 DBI_WR = 0x0
7259 20:14:52.766284 DBI_RD = 0x0
7260 20:14:52.769437 OTF = 0x1
7261 20:14:52.772613 ===================================
7262 20:14:52.776438 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7263 20:14:52.779400 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7264 20:14:52.785928 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 20:14:52.789278 ===================================
7266 20:14:52.789361 LPDDR4 DRAM CONFIGURATION
7267 20:14:52.792763 ===================================
7268 20:14:52.795792 EX_ROW_EN[0] = 0x10
7269 20:14:52.799625 EX_ROW_EN[1] = 0x0
7270 20:14:52.799752 LP4Y_EN = 0x0
7271 20:14:52.802737 WORK_FSP = 0x1
7272 20:14:52.802864 WL = 0x5
7273 20:14:52.806305 RL = 0x5
7274 20:14:52.806390 BL = 0x2
7275 20:14:52.809495 RPST = 0x0
7276 20:14:52.809578 RD_PRE = 0x0
7277 20:14:52.812492 WR_PRE = 0x1
7278 20:14:52.812575 WR_PST = 0x1
7279 20:14:52.815997 DBI_WR = 0x0
7280 20:14:52.816079 DBI_RD = 0x0
7281 20:14:52.819066 OTF = 0x1
7282 20:14:52.822883 ===================================
7283 20:14:52.829074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7284 20:14:52.829158 ==
7285 20:14:52.832850 Dram Type= 6, Freq= 0, CH_0, rank 0
7286 20:14:52.835954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 20:14:52.836066 ==
7288 20:14:52.839129 [Duty_Offset_Calibration]
7289 20:14:52.839212 B0:2 B1:1 CA:1
7290 20:14:52.839278
7291 20:14:52.842661 [DutyScan_Calibration_Flow] k_type=0
7292 20:14:52.852842
7293 20:14:52.852932 ==CLK 0==
7294 20:14:52.856198 Final CLK duty delay cell = 0
7295 20:14:52.859475 [0] MAX Duty = 5156%(X100), DQS PI = 22
7296 20:14:52.862803 [0] MIN Duty = 4876%(X100), DQS PI = 48
7297 20:14:52.862887 [0] AVG Duty = 5016%(X100)
7298 20:14:52.866174
7299 20:14:52.869434 CH0 CLK Duty spec in!! Max-Min= 280%
7300 20:14:52.872938 [DutyScan_Calibration_Flow] ====Done====
7301 20:14:52.873062
7302 20:14:52.876375 [DutyScan_Calibration_Flow] k_type=1
7303 20:14:52.892275
7304 20:14:52.892406 ==DQS 0 ==
7305 20:14:52.895353 Final DQS duty delay cell = -4
7306 20:14:52.898962 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7307 20:14:52.902046 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7308 20:14:52.905242 [-4] AVG Duty = 4891%(X100)
7309 20:14:52.905324
7310 20:14:52.905390 ==DQS 1 ==
7311 20:14:52.908718 Final DQS duty delay cell = 0
7312 20:14:52.911891 [0] MAX Duty = 5187%(X100), DQS PI = 20
7313 20:14:52.915161 [0] MIN Duty = 5031%(X100), DQS PI = 52
7314 20:14:52.918270 [0] AVG Duty = 5109%(X100)
7315 20:14:52.918353
7316 20:14:52.921883 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7317 20:14:52.921966
7318 20:14:52.924890 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7319 20:14:52.928388 [DutyScan_Calibration_Flow] ====Done====
7320 20:14:52.928471
7321 20:14:52.931470 [DutyScan_Calibration_Flow] k_type=3
7322 20:14:52.949545
7323 20:14:52.949629 ==DQM 0 ==
7324 20:14:52.952715 Final DQM duty delay cell = 0
7325 20:14:52.955911 [0] MAX Duty = 5218%(X100), DQS PI = 34
7326 20:14:52.959555 [0] MIN Duty = 4876%(X100), DQS PI = 60
7327 20:14:52.959663 [0] AVG Duty = 5047%(X100)
7328 20:14:52.963207
7329 20:14:52.963290 ==DQM 1 ==
7330 20:14:52.966326 Final DQM duty delay cell = 0
7331 20:14:52.969460 [0] MAX Duty = 5187%(X100), DQS PI = 4
7332 20:14:52.972870 [0] MIN Duty = 5062%(X100), DQS PI = 12
7333 20:14:52.972995 [0] AVG Duty = 5124%(X100)
7334 20:14:52.976447
7335 20:14:52.979313 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7336 20:14:52.979436
7337 20:14:52.982584 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7338 20:14:52.986087 [DutyScan_Calibration_Flow] ====Done====
7339 20:14:52.986187
7340 20:14:52.989373 [DutyScan_Calibration_Flow] k_type=2
7341 20:14:53.006525
7342 20:14:53.006653 ==DQ 0 ==
7343 20:14:53.010233 Final DQ duty delay cell = 0
7344 20:14:53.013278 [0] MAX Duty = 5062%(X100), DQS PI = 26
7345 20:14:53.016484 [0] MIN Duty = 4907%(X100), DQS PI = 0
7346 20:14:53.016607 [0] AVG Duty = 4984%(X100)
7347 20:14:53.020175
7348 20:14:53.020279 ==DQ 1 ==
7349 20:14:53.023348 Final DQ duty delay cell = 0
7350 20:14:53.026384 [0] MAX Duty = 5093%(X100), DQS PI = 20
7351 20:14:53.029533 [0] MIN Duty = 4938%(X100), DQS PI = 34
7352 20:14:53.029654 [0] AVG Duty = 5015%(X100)
7353 20:14:53.029764
7354 20:14:53.036625 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7355 20:14:53.036746
7356 20:14:53.039588 CH0 DQ 1 Duty spec in!! Max-Min= 155%
7357 20:14:53.042741 [DutyScan_Calibration_Flow] ====Done====
7358 20:14:53.042852 ==
7359 20:14:53.046372 Dram Type= 6, Freq= 0, CH_1, rank 0
7360 20:14:53.049943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7361 20:14:53.050042 ==
7362 20:14:53.053171 [Duty_Offset_Calibration]
7363 20:14:53.053287 B0:1 B1:0 CA:0
7364 20:14:53.053384
7365 20:14:53.056280 [DutyScan_Calibration_Flow] k_type=0
7366 20:14:53.066221
7367 20:14:53.066355 ==CLK 0==
7368 20:14:53.069563 Final CLK duty delay cell = -4
7369 20:14:53.072789 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7370 20:14:53.075887 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7371 20:14:53.079434 [-4] AVG Duty = 4906%(X100)
7372 20:14:53.079517
7373 20:14:53.083113 CH1 CLK Duty spec in!! Max-Min= 125%
7374 20:14:53.086131 [DutyScan_Calibration_Flow] ====Done====
7375 20:14:53.086242
7376 20:14:53.089063 [DutyScan_Calibration_Flow] k_type=1
7377 20:14:53.105806
7378 20:14:53.105890 ==DQS 0 ==
7379 20:14:53.109085 Final DQS duty delay cell = 0
7380 20:14:53.112771 [0] MAX Duty = 5094%(X100), DQS PI = 24
7381 20:14:53.116258 [0] MIN Duty = 4875%(X100), DQS PI = 14
7382 20:14:53.119215 [0] AVG Duty = 4984%(X100)
7383 20:14:53.119315
7384 20:14:53.119385 ==DQS 1 ==
7385 20:14:53.122777 Final DQS duty delay cell = 0
7386 20:14:53.125921 [0] MAX Duty = 5249%(X100), DQS PI = 50
7387 20:14:53.128976 [0] MIN Duty = 4876%(X100), DQS PI = 40
7388 20:14:53.132766 [0] AVG Duty = 5062%(X100)
7389 20:14:53.132847
7390 20:14:53.135837 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7391 20:14:53.135938
7392 20:14:53.139451 CH1 DQS 1 Duty spec in!! Max-Min= 373%
7393 20:14:53.142154 [DutyScan_Calibration_Flow] ====Done====
7394 20:14:53.142229
7395 20:14:53.145625 [DutyScan_Calibration_Flow] k_type=3
7396 20:14:53.162945
7397 20:14:53.163022 ==DQM 0 ==
7398 20:14:53.166274 Final DQM duty delay cell = 0
7399 20:14:53.169885 [0] MAX Duty = 5187%(X100), DQS PI = 40
7400 20:14:53.172994 [0] MIN Duty = 5000%(X100), DQS PI = 16
7401 20:14:53.173064 [0] AVG Duty = 5093%(X100)
7402 20:14:53.176585
7403 20:14:53.176690 ==DQM 1 ==
7404 20:14:53.179558 Final DQM duty delay cell = 0
7405 20:14:53.183176 [0] MAX Duty = 5093%(X100), DQS PI = 10
7406 20:14:53.186240 [0] MIN Duty = 4907%(X100), DQS PI = 0
7407 20:14:53.186317 [0] AVG Duty = 5000%(X100)
7408 20:14:53.189956
7409 20:14:53.192992 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7410 20:14:53.193093
7411 20:14:53.196548 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7412 20:14:53.199651 [DutyScan_Calibration_Flow] ====Done====
7413 20:14:53.199746
7414 20:14:53.202847 [DutyScan_Calibration_Flow] k_type=2
7415 20:14:53.218687
7416 20:14:53.218785 ==DQ 0 ==
7417 20:14:53.222519 Final DQ duty delay cell = -4
7418 20:14:53.225805 [-4] MAX Duty = 5062%(X100), DQS PI = 26
7419 20:14:53.228741 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7420 20:14:53.232057 [-4] AVG Duty = 4968%(X100)
7421 20:14:53.232161
7422 20:14:53.232263 ==DQ 1 ==
7423 20:14:53.235400 Final DQ duty delay cell = 0
7424 20:14:53.238683 [0] MAX Duty = 5093%(X100), DQS PI = 8
7425 20:14:53.242512 [0] MIN Duty = 4938%(X100), DQS PI = 0
7426 20:14:53.242619 [0] AVG Duty = 5015%(X100)
7427 20:14:53.245696
7428 20:14:53.248851 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7429 20:14:53.248943
7430 20:14:53.252460 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7431 20:14:53.255309 [DutyScan_Calibration_Flow] ====Done====
7432 20:14:53.258817 nWR fixed to 30
7433 20:14:53.258953 [ModeRegInit_LP4] CH0 RK0
7434 20:14:53.262414 [ModeRegInit_LP4] CH0 RK1
7435 20:14:53.265530 [ModeRegInit_LP4] CH1 RK0
7436 20:14:53.268770 [ModeRegInit_LP4] CH1 RK1
7437 20:14:53.268862 match AC timing 5
7438 20:14:53.272023 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7439 20:14:53.279055 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7440 20:14:53.282164 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7441 20:14:53.288438 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7442 20:14:53.292393 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7443 20:14:53.292503 [MiockJmeterHQA]
7444 20:14:53.292598
7445 20:14:53.295551 [DramcMiockJmeter] u1RxGatingPI = 0
7446 20:14:53.298623 0 : 4255, 4027
7447 20:14:53.298746 4 : 4254, 4026
7448 20:14:53.302306 8 : 4255, 4029
7449 20:14:53.302438 12 : 4254, 4029
7450 20:14:53.302566 16 : 4363, 4138
7451 20:14:53.305430 20 : 4252, 4027
7452 20:14:53.305507 24 : 4252, 4027
7453 20:14:53.308614 28 : 4253, 4027
7454 20:14:53.308689 32 : 4255, 4029
7455 20:14:53.311682 36 : 4363, 4138
7456 20:14:53.311758 40 : 4252, 4026
7457 20:14:53.311859 44 : 4252, 4027
7458 20:14:53.315513 48 : 4249, 4027
7459 20:14:53.315599 52 : 4255, 4029
7460 20:14:53.318517 56 : 4250, 4027
7461 20:14:53.318622 60 : 4361, 4137
7462 20:14:53.321664 64 : 4361, 4137
7463 20:14:53.321772 68 : 4249, 4027
7464 20:14:53.325277 72 : 4250, 4026
7465 20:14:53.325381 76 : 4250, 4027
7466 20:14:53.325480 80 : 4253, 4027
7467 20:14:53.328890 84 : 4253, 4028
7468 20:14:53.328970 88 : 4360, 88
7469 20:14:53.331766 92 : 4363, 0
7470 20:14:53.331869 96 : 4361, 0
7471 20:14:53.331962 100 : 4250, 0
7472 20:14:53.335416 104 : 4360, 0
7473 20:14:53.335521 108 : 4250, 0
7474 20:14:53.338569 112 : 4250, 0
7475 20:14:53.338675 116 : 4249, 0
7476 20:14:53.338773 120 : 4250, 0
7477 20:14:53.342117 124 : 4253, 0
7478 20:14:53.342197 128 : 4250, 0
7479 20:14:53.345400 132 : 4250, 0
7480 20:14:53.345503 136 : 4253, 0
7481 20:14:53.345597 140 : 4360, 0
7482 20:14:53.348856 144 : 4253, 0
7483 20:14:53.348960 148 : 4250, 0
7484 20:14:53.349058 152 : 4250, 0
7485 20:14:53.352184 156 : 4360, 0
7486 20:14:53.352298 160 : 4250, 0
7487 20:14:53.355446 164 : 4250, 0
7488 20:14:53.355551 168 : 4250, 0
7489 20:14:53.355642 172 : 4250, 0
7490 20:14:53.358388 176 : 4363, 0
7491 20:14:53.358466 180 : 4250, 0
7492 20:14:53.362022 184 : 4250, 0
7493 20:14:53.362130 188 : 4250, 0
7494 20:14:53.362224 192 : 4360, 0
7495 20:14:53.365378 196 : 4250, 0
7496 20:14:53.365453 200 : 4250, 0
7497 20:14:53.368390 204 : 4250, 1220
7498 20:14:53.368464 208 : 4253, 3979
7499 20:14:53.372162 212 : 4250, 4027
7500 20:14:53.372266 216 : 4250, 4027
7501 20:14:53.372346 220 : 4361, 4137
7502 20:14:53.375178 224 : 4250, 4026
7503 20:14:53.375274 228 : 4250, 4027
7504 20:14:53.378233 232 : 4360, 4138
7505 20:14:53.378340 236 : 4249, 4027
7506 20:14:53.382056 240 : 4250, 4026
7507 20:14:53.382163 244 : 4363, 4139
7508 20:14:53.385003 248 : 4250, 4027
7509 20:14:53.385080 252 : 4249, 4027
7510 20:14:53.388230 256 : 4250, 4026
7511 20:14:53.388341 260 : 4253, 4029
7512 20:14:53.391888 264 : 4250, 4027
7513 20:14:53.391997 268 : 4249, 4027
7514 20:14:53.394806 272 : 4363, 4137
7515 20:14:53.394913 276 : 4250, 4026
7516 20:14:53.395013 280 : 4250, 4027
7517 20:14:53.398207 284 : 4360, 4138
7518 20:14:53.398313 288 : 4252, 4027
7519 20:14:53.401646 292 : 4250, 4026
7520 20:14:53.401754 296 : 4363, 4139
7521 20:14:53.404772 300 : 4250, 4027
7522 20:14:53.404879 304 : 4249, 4027
7523 20:14:53.408303 308 : 4250, 3979
7524 20:14:53.408407 312 : 4253, 1857
7525 20:14:53.408504
7526 20:14:53.411484 MIOCK jitter meter ch=0
7527 20:14:53.411584
7528 20:14:53.414676 1T = (312-88) = 224 dly cells
7529 20:14:53.421509 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7530 20:14:53.421617 ==
7531 20:14:53.425185 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 20:14:53.428221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 20:14:53.428333 ==
7534 20:14:53.434826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 20:14:53.437774 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 20:14:53.441569 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 20:14:53.447644 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 20:14:53.456506 [CA 0] Center 42 (12~73) winsize 62
7539 20:14:53.459997 [CA 1] Center 42 (12~73) winsize 62
7540 20:14:53.463219 [CA 2] Center 37 (8~67) winsize 60
7541 20:14:53.466469 [CA 3] Center 37 (7~67) winsize 61
7542 20:14:53.470149 [CA 4] Center 36 (6~66) winsize 61
7543 20:14:53.473558 [CA 5] Center 35 (6~64) winsize 59
7544 20:14:53.473639
7545 20:14:53.476976 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 20:14:53.477073
7547 20:14:53.480034 [CATrainingPosCal] consider 1 rank data
7548 20:14:53.483129 u2DelayCellTimex100 = 290/100 ps
7549 20:14:53.486335 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7550 20:14:53.493345 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7551 20:14:53.496549 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7552 20:14:53.500088 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7553 20:14:53.503143 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 20:14:53.506653 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7555 20:14:53.506753
7556 20:14:53.509775 CA PerBit enable=1, Macro0, CA PI delay=35
7557 20:14:53.509878
7558 20:14:53.513134 [CBTSetCACLKResult] CA Dly = 35
7559 20:14:53.513240 CS Dly: 9 (0~40)
7560 20:14:53.519757 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 20:14:53.522807 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 20:14:53.522911 ==
7563 20:14:53.526670 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 20:14:53.529615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 20:14:53.529718 ==
7566 20:14:53.536291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 20:14:53.539379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 20:14:53.546597 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 20:14:53.549503 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 20:14:53.559962 [CA 0] Center 43 (13~73) winsize 61
7571 20:14:53.563085 [CA 1] Center 43 (13~73) winsize 61
7572 20:14:53.566324 [CA 2] Center 38 (8~68) winsize 61
7573 20:14:53.569906 [CA 3] Center 38 (8~68) winsize 61
7574 20:14:53.573305 [CA 4] Center 36 (6~66) winsize 61
7575 20:14:53.576201 [CA 5] Center 35 (6~65) winsize 60
7576 20:14:53.576310
7577 20:14:53.579860 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7578 20:14:53.579964
7579 20:14:53.583145 [CATrainingPosCal] consider 2 rank data
7580 20:14:53.586322 u2DelayCellTimex100 = 290/100 ps
7581 20:14:53.589504 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7582 20:14:53.596410 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7583 20:14:53.599632 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7584 20:14:53.603290 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7585 20:14:53.606449 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7586 20:14:53.609535 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7587 20:14:53.609643
7588 20:14:53.612850 CA PerBit enable=1, Macro0, CA PI delay=35
7589 20:14:53.612943
7590 20:14:53.616510 [CBTSetCACLKResult] CA Dly = 35
7591 20:14:53.619753 CS Dly: 10 (0~42)
7592 20:14:53.623158 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 20:14:53.626180 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 20:14:53.626284
7595 20:14:53.629782 ----->DramcWriteLeveling(PI) begin...
7596 20:14:53.629884 ==
7597 20:14:53.632958 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 20:14:53.636591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 20:14:53.639524 ==
7600 20:14:53.639631 Write leveling (Byte 0): 35 => 35
7601 20:14:53.643223 Write leveling (Byte 1): 27 => 27
7602 20:14:53.646226 DramcWriteLeveling(PI) end<-----
7603 20:14:53.646328
7604 20:14:53.646419 ==
7605 20:14:53.649650 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 20:14:53.656448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 20:14:53.656531 ==
7608 20:14:53.656595 [Gating] SW mode calibration
7609 20:14:53.666134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 20:14:53.669930 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 20:14:53.673200 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7612 20:14:53.679954 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7613 20:14:53.682993 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7614 20:14:53.686508 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7615 20:14:53.692987 1 4 16 | B1->B0 | 2323 3333 | 1 1 | (0 0) (0 0)
7616 20:14:53.696529 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7617 20:14:53.699438 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7618 20:14:53.706647 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7619 20:14:53.709421 1 5 0 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7620 20:14:53.713161 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7621 20:14:53.719463 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7622 20:14:53.722642 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7623 20:14:53.726289 1 5 16 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (0 0)
7624 20:14:53.732884 1 5 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
7625 20:14:53.736269 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7626 20:14:53.739336 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7627 20:14:53.745940 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7628 20:14:53.749221 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7629 20:14:53.752830 1 6 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
7630 20:14:53.759093 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (1 1)
7631 20:14:53.762741 1 6 16 | B1->B0 | 2c2b 4646 | 1 0 | (0 0) (0 0)
7632 20:14:53.766230 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 20:14:53.772524 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 20:14:53.776113 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 20:14:53.779378 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 20:14:53.785609 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 20:14:53.789329 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 20:14:53.792419 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 20:14:53.795873 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7640 20:14:53.802838 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 20:14:53.805932 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 20:14:53.808981 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 20:14:53.815508 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 20:14:53.818847 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 20:14:53.822591 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 20:14:53.828751 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 20:14:53.832457 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 20:14:53.835416 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 20:14:53.842330 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 20:14:53.845774 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 20:14:53.849329 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 20:14:53.855324 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 20:14:53.858655 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 20:14:53.861986 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 20:14:53.868670 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 20:14:53.868779 Total UI for P1: 0, mck2ui 16
7657 20:14:53.875447 best dqsien dly found for B0: ( 1, 9, 12)
7658 20:14:53.878906 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 20:14:53.882018 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 20:14:53.885226 Total UI for P1: 0, mck2ui 16
7661 20:14:53.888359 best dqsien dly found for B1: ( 1, 9, 18)
7662 20:14:53.892156 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7663 20:14:53.895256 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7664 20:14:53.895402
7665 20:14:53.901802 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7666 20:14:53.905333 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7667 20:14:53.908721 [Gating] SW calibration Done
7668 20:14:53.908809 ==
7669 20:14:53.912087 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 20:14:53.914954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 20:14:53.915054 ==
7672 20:14:53.915145 RX Vref Scan: 0
7673 20:14:53.915232
7674 20:14:53.918838 RX Vref 0 -> 0, step: 1
7675 20:14:53.918933
7676 20:14:53.921844 RX Delay 0 -> 252, step: 8
7677 20:14:53.925361 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7678 20:14:53.928807 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7679 20:14:53.932174 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7680 20:14:53.938289 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7681 20:14:53.942026 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7682 20:14:53.945149 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7683 20:14:53.948641 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7684 20:14:53.951758 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7685 20:14:53.958316 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7686 20:14:53.961960 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7687 20:14:53.964978 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7688 20:14:53.968558 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7689 20:14:53.971918 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7690 20:14:53.978185 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7691 20:14:53.981681 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7692 20:14:53.985124 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7693 20:14:53.985246 ==
7694 20:14:53.988651 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 20:14:53.991468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 20:14:53.995009 ==
7697 20:14:53.995108 DQS Delay:
7698 20:14:53.995199 DQS0 = 0, DQS1 = 0
7699 20:14:53.998357 DQM Delay:
7700 20:14:53.998514 DQM0 = 136, DQM1 = 130
7701 20:14:54.001981 DQ Delay:
7702 20:14:54.005087 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7703 20:14:54.008261 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7704 20:14:54.011339 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7705 20:14:54.014777 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7706 20:14:54.014904
7707 20:14:54.015014
7708 20:14:54.015121 ==
7709 20:14:54.018152 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 20:14:54.021432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 20:14:54.021552 ==
7712 20:14:54.021662
7713 20:14:54.021779
7714 20:14:54.025057 TX Vref Scan disable
7715 20:14:54.028171 == TX Byte 0 ==
7716 20:14:54.031319 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7717 20:14:54.034939 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7718 20:14:54.038275 == TX Byte 1 ==
7719 20:14:54.041551 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7720 20:14:54.044869 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7721 20:14:54.045059 ==
7722 20:14:54.048074 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 20:14:54.054879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 20:14:54.055013 ==
7725 20:14:54.067059
7726 20:14:54.070009 TX Vref early break, caculate TX vref
7727 20:14:54.073861 TX Vref=16, minBit 0, minWin=23, winSum=380
7728 20:14:54.076936 TX Vref=18, minBit 7, minWin=23, winSum=388
7729 20:14:54.080324 TX Vref=20, minBit 0, minWin=24, winSum=398
7730 20:14:54.083592 TX Vref=22, minBit 7, minWin=24, winSum=408
7731 20:14:54.086644 TX Vref=24, minBit 2, minWin=25, winSum=417
7732 20:14:54.093855 TX Vref=26, minBit 2, minWin=25, winSum=424
7733 20:14:54.096768 TX Vref=28, minBit 1, minWin=25, winSum=421
7734 20:14:54.100438 TX Vref=30, minBit 1, minWin=25, winSum=417
7735 20:14:54.103730 TX Vref=32, minBit 6, minWin=23, winSum=406
7736 20:14:54.106723 TX Vref=34, minBit 6, minWin=23, winSum=395
7737 20:14:54.113652 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 26
7738 20:14:54.113733
7739 20:14:54.116878 Final TX Range 0 Vref 26
7740 20:14:54.116958
7741 20:14:54.117022 ==
7742 20:14:54.119828 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 20:14:54.123425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 20:14:54.123510 ==
7745 20:14:54.123579
7746 20:14:54.123638
7747 20:14:54.126912 TX Vref Scan disable
7748 20:14:54.133333 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7749 20:14:54.133416 == TX Byte 0 ==
7750 20:14:54.136503 u2DelayCellOfst[0]=10 cells (3 PI)
7751 20:14:54.140308 u2DelayCellOfst[1]=13 cells (4 PI)
7752 20:14:54.143456 u2DelayCellOfst[2]=10 cells (3 PI)
7753 20:14:54.146615 u2DelayCellOfst[3]=10 cells (3 PI)
7754 20:14:54.150081 u2DelayCellOfst[4]=6 cells (2 PI)
7755 20:14:54.153691 u2DelayCellOfst[5]=0 cells (0 PI)
7756 20:14:54.156873 u2DelayCellOfst[6]=16 cells (5 PI)
7757 20:14:54.156970 u2DelayCellOfst[7]=13 cells (4 PI)
7758 20:14:54.163465 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7759 20:14:54.166978 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7760 20:14:54.167058 == TX Byte 1 ==
7761 20:14:54.170038 u2DelayCellOfst[8]=3 cells (1 PI)
7762 20:14:54.173173 u2DelayCellOfst[9]=0 cells (0 PI)
7763 20:14:54.176859 u2DelayCellOfst[10]=10 cells (3 PI)
7764 20:14:54.179959 u2DelayCellOfst[11]=3 cells (1 PI)
7765 20:14:54.183125 u2DelayCellOfst[12]=10 cells (3 PI)
7766 20:14:54.186802 u2DelayCellOfst[13]=13 cells (4 PI)
7767 20:14:54.189829 u2DelayCellOfst[14]=13 cells (4 PI)
7768 20:14:54.193262 u2DelayCellOfst[15]=10 cells (3 PI)
7769 20:14:54.196855 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7770 20:14:54.203198 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7771 20:14:54.203300 DramC Write-DBI on
7772 20:14:54.203379 ==
7773 20:14:54.206319 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 20:14:54.209842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 20:14:54.213201 ==
7776 20:14:54.213327
7777 20:14:54.213422
7778 20:14:54.213512 TX Vref Scan disable
7779 20:14:54.216682 == TX Byte 0 ==
7780 20:14:54.219947 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7781 20:14:54.223568 == TX Byte 1 ==
7782 20:14:54.226724 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7783 20:14:54.229935 DramC Write-DBI off
7784 20:14:54.230089
7785 20:14:54.230212 [DATLAT]
7786 20:14:54.230316 Freq=1600, CH0 RK0
7787 20:14:54.230403
7788 20:14:54.233486 DATLAT Default: 0xf
7789 20:14:54.233581 0, 0xFFFF, sum = 0
7790 20:14:54.236671 1, 0xFFFF, sum = 0
7791 20:14:54.240200 2, 0xFFFF, sum = 0
7792 20:14:54.240292 3, 0xFFFF, sum = 0
7793 20:14:54.243468 4, 0xFFFF, sum = 0
7794 20:14:54.243552 5, 0xFFFF, sum = 0
7795 20:14:54.246705 6, 0xFFFF, sum = 0
7796 20:14:54.246788 7, 0xFFFF, sum = 0
7797 20:14:54.249843 8, 0xFFFF, sum = 0
7798 20:14:54.249946 9, 0xFFFF, sum = 0
7799 20:14:54.252994 10, 0xFFFF, sum = 0
7800 20:14:54.253093 11, 0xFFFF, sum = 0
7801 20:14:54.256343 12, 0xFFFF, sum = 0
7802 20:14:54.256469 13, 0xFFFF, sum = 0
7803 20:14:54.260332 14, 0x0, sum = 1
7804 20:14:54.260466 15, 0x0, sum = 2
7805 20:14:54.263223 16, 0x0, sum = 3
7806 20:14:54.263349 17, 0x0, sum = 4
7807 20:14:54.266483 best_step = 15
7808 20:14:54.266599
7809 20:14:54.266750 ==
7810 20:14:54.269592 Dram Type= 6, Freq= 0, CH_0, rank 0
7811 20:14:54.273289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7812 20:14:54.273431 ==
7813 20:14:54.276535 RX Vref Scan: 1
7814 20:14:54.276673
7815 20:14:54.276785 Set Vref Range= 24 -> 127
7816 20:14:54.276940
7817 20:14:54.279704 RX Vref 24 -> 127, step: 1
7818 20:14:54.279827
7819 20:14:54.283197 RX Delay 27 -> 252, step: 4
7820 20:14:54.283351
7821 20:14:54.286420 Set Vref, RX VrefLevel [Byte0]: 24
7822 20:14:54.289698 [Byte1]: 24
7823 20:14:54.289820
7824 20:14:54.292778 Set Vref, RX VrefLevel [Byte0]: 25
7825 20:14:54.295924 [Byte1]: 25
7826 20:14:54.296076
7827 20:14:54.299572 Set Vref, RX VrefLevel [Byte0]: 26
7828 20:14:54.302643 [Byte1]: 26
7829 20:14:54.306877
7830 20:14:54.307000 Set Vref, RX VrefLevel [Byte0]: 27
7831 20:14:54.310175 [Byte1]: 27
7832 20:14:54.314602
7833 20:14:54.314725 Set Vref, RX VrefLevel [Byte0]: 28
7834 20:14:54.317810 [Byte1]: 28
7835 20:14:54.321577
7836 20:14:54.321699 Set Vref, RX VrefLevel [Byte0]: 29
7837 20:14:54.325074 [Byte1]: 29
7838 20:14:54.329659
7839 20:14:54.329744 Set Vref, RX VrefLevel [Byte0]: 30
7840 20:14:54.332516 [Byte1]: 30
7841 20:14:54.336937
7842 20:14:54.337020 Set Vref, RX VrefLevel [Byte0]: 31
7843 20:14:54.339955 [Byte1]: 31
7844 20:14:54.344691
7845 20:14:54.344775 Set Vref, RX VrefLevel [Byte0]: 32
7846 20:14:54.347630 [Byte1]: 32
7847 20:14:54.352054
7848 20:14:54.352136 Set Vref, RX VrefLevel [Byte0]: 33
7849 20:14:54.355157 [Byte1]: 33
7850 20:14:54.359589
7851 20:14:54.359670 Set Vref, RX VrefLevel [Byte0]: 34
7852 20:14:54.362994 [Byte1]: 34
7853 20:14:54.367299
7854 20:14:54.367382 Set Vref, RX VrefLevel [Byte0]: 35
7855 20:14:54.370565 [Byte1]: 35
7856 20:14:54.374432
7857 20:14:54.374553 Set Vref, RX VrefLevel [Byte0]: 36
7858 20:14:54.378146 [Byte1]: 36
7859 20:14:54.381781
7860 20:14:54.381905 Set Vref, RX VrefLevel [Byte0]: 37
7861 20:14:54.385159 [Byte1]: 37
7862 20:14:54.389511
7863 20:14:54.389636 Set Vref, RX VrefLevel [Byte0]: 38
7864 20:14:54.392850 [Byte1]: 38
7865 20:14:54.397165
7866 20:14:54.397272 Set Vref, RX VrefLevel [Byte0]: 39
7867 20:14:54.400227 [Byte1]: 39
7868 20:14:54.404939
7869 20:14:54.405034 Set Vref, RX VrefLevel [Byte0]: 40
7870 20:14:54.408015 [Byte1]: 40
7871 20:14:54.412230
7872 20:14:54.412322 Set Vref, RX VrefLevel [Byte0]: 41
7873 20:14:54.415389 [Byte1]: 41
7874 20:14:54.419812
7875 20:14:54.419929 Set Vref, RX VrefLevel [Byte0]: 42
7876 20:14:54.422811 [Byte1]: 42
7877 20:14:54.427302
7878 20:14:54.427412 Set Vref, RX VrefLevel [Byte0]: 43
7879 20:14:54.430437 [Byte1]: 43
7880 20:14:54.434895
7881 20:14:54.434977 Set Vref, RX VrefLevel [Byte0]: 44
7882 20:14:54.437813 [Byte1]: 44
7883 20:14:54.442450
7884 20:14:54.442533 Set Vref, RX VrefLevel [Byte0]: 45
7885 20:14:54.445443 [Byte1]: 45
7886 20:14:54.450134
7887 20:14:54.450217 Set Vref, RX VrefLevel [Byte0]: 46
7888 20:14:54.453370 [Byte1]: 46
7889 20:14:54.457532
7890 20:14:54.457615 Set Vref, RX VrefLevel [Byte0]: 47
7891 20:14:54.460850 [Byte1]: 47
7892 20:14:54.464713
7893 20:14:54.464796 Set Vref, RX VrefLevel [Byte0]: 48
7894 20:14:54.468583 [Byte1]: 48
7895 20:14:54.472337
7896 20:14:54.472420 Set Vref, RX VrefLevel [Byte0]: 49
7897 20:14:54.475564 [Byte1]: 49
7898 20:14:54.479921
7899 20:14:54.480003 Set Vref, RX VrefLevel [Byte0]: 50
7900 20:14:54.483196 [Byte1]: 50
7901 20:14:54.487504
7902 20:14:54.487587 Set Vref, RX VrefLevel [Byte0]: 51
7903 20:14:54.490738 [Byte1]: 51
7904 20:14:54.495200
7905 20:14:54.495283 Set Vref, RX VrefLevel [Byte0]: 52
7906 20:14:54.498360 [Byte1]: 52
7907 20:14:54.502645
7908 20:14:54.502727 Set Vref, RX VrefLevel [Byte0]: 53
7909 20:14:54.506297 [Byte1]: 53
7910 20:14:54.509983
7911 20:14:54.510065 Set Vref, RX VrefLevel [Byte0]: 54
7912 20:14:54.513800 [Byte1]: 54
7913 20:14:54.517698
7914 20:14:54.517781 Set Vref, RX VrefLevel [Byte0]: 55
7915 20:14:54.520781 [Byte1]: 55
7916 20:14:54.525391
7917 20:14:54.525474 Set Vref, RX VrefLevel [Byte0]: 56
7918 20:14:54.528304 [Byte1]: 56
7919 20:14:54.532499
7920 20:14:54.532583 Set Vref, RX VrefLevel [Byte0]: 57
7921 20:14:54.536052 [Byte1]: 57
7922 20:14:54.540282
7923 20:14:54.540375 Set Vref, RX VrefLevel [Byte0]: 58
7924 20:14:54.543406 [Byte1]: 58
7925 20:14:54.547537
7926 20:14:54.547619 Set Vref, RX VrefLevel [Byte0]: 59
7927 20:14:54.551132 [Byte1]: 59
7928 20:14:54.555344
7929 20:14:54.555426 Set Vref, RX VrefLevel [Byte0]: 60
7930 20:14:54.558903 [Byte1]: 60
7931 20:14:54.562581
7932 20:14:54.562664 Set Vref, RX VrefLevel [Byte0]: 61
7933 20:14:54.566335 [Byte1]: 61
7934 20:14:54.570531
7935 20:14:54.570613 Set Vref, RX VrefLevel [Byte0]: 62
7936 20:14:54.573840 [Byte1]: 62
7937 20:14:54.577715
7938 20:14:54.577806 Set Vref, RX VrefLevel [Byte0]: 63
7939 20:14:54.581357 [Byte1]: 63
7940 20:14:54.585234
7941 20:14:54.585354 Set Vref, RX VrefLevel [Byte0]: 64
7942 20:14:54.588557 [Byte1]: 64
7943 20:14:54.592726
7944 20:14:54.592809 Set Vref, RX VrefLevel [Byte0]: 65
7945 20:14:54.596157 [Byte1]: 65
7946 20:14:54.600729
7947 20:14:54.600824 Set Vref, RX VrefLevel [Byte0]: 66
7948 20:14:54.603881 [Byte1]: 66
7949 20:14:54.607819
7950 20:14:54.607894 Set Vref, RX VrefLevel [Byte0]: 67
7951 20:14:54.611070 [Byte1]: 67
7952 20:14:54.615750
7953 20:14:54.615873 Set Vref, RX VrefLevel [Byte0]: 68
7954 20:14:54.618666 [Byte1]: 68
7955 20:14:54.622934
7956 20:14:54.623050 Set Vref, RX VrefLevel [Byte0]: 69
7957 20:14:54.626216 [Byte1]: 69
7958 20:14:54.630626
7959 20:14:54.630709 Set Vref, RX VrefLevel [Byte0]: 70
7960 20:14:54.634180 [Byte1]: 70
7961 20:14:54.638116
7962 20:14:54.638227 Set Vref, RX VrefLevel [Byte0]: 71
7963 20:14:54.641561 [Byte1]: 71
7964 20:14:54.645702
7965 20:14:54.645811 Set Vref, RX VrefLevel [Byte0]: 72
7966 20:14:54.649132 [Byte1]: 72
7967 20:14:54.653079
7968 20:14:54.653186 Set Vref, RX VrefLevel [Byte0]: 73
7969 20:14:54.656439 [Byte1]: 73
7970 20:14:54.660906
7971 20:14:54.660982 Set Vref, RX VrefLevel [Byte0]: 74
7972 20:14:54.663992 [Byte1]: 74
7973 20:14:54.668261
7974 20:14:54.668357 Final RX Vref Byte 0 = 56 to rank0
7975 20:14:54.671336 Final RX Vref Byte 1 = 62 to rank0
7976 20:14:54.674929 Final RX Vref Byte 0 = 56 to rank1
7977 20:14:54.678278 Final RX Vref Byte 1 = 62 to rank1==
7978 20:14:54.681292 Dram Type= 6, Freq= 0, CH_0, rank 0
7979 20:14:54.687909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 20:14:54.687993 ==
7981 20:14:54.688059 DQS Delay:
7982 20:14:54.691575 DQS0 = 0, DQS1 = 0
7983 20:14:54.691657 DQM Delay:
7984 20:14:54.691723 DQM0 = 133, DQM1 = 128
7985 20:14:54.694687 DQ Delay:
7986 20:14:54.698042 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7987 20:14:54.701189 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7988 20:14:54.704973 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7989 20:14:54.708211 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7990 20:14:54.708317
7991 20:14:54.708415
7992 20:14:54.708497
7993 20:14:54.711442 [DramC_TX_OE_Calibration] TA2
7994 20:14:54.714532 Original DQ_B0 (3 6) =30, OEN = 27
7995 20:14:54.717891 Original DQ_B1 (3 6) =30, OEN = 27
7996 20:14:54.721194 24, 0x0, End_B0=24 End_B1=24
7997 20:14:54.721278 25, 0x0, End_B0=25 End_B1=25
7998 20:14:54.724938 26, 0x0, End_B0=26 End_B1=26
7999 20:14:54.728126 27, 0x0, End_B0=27 End_B1=27
8000 20:14:54.731098 28, 0x0, End_B0=28 End_B1=28
8001 20:14:54.734330 29, 0x0, End_B0=29 End_B1=29
8002 20:14:54.734440 30, 0x0, End_B0=30 End_B1=30
8003 20:14:54.738256 31, 0x4545, End_B0=30 End_B1=30
8004 20:14:54.741501 Byte0 end_step=30 best_step=27
8005 20:14:54.744556 Byte1 end_step=30 best_step=27
8006 20:14:54.747884 Byte0 TX OE(2T, 0.5T) = (3, 3)
8007 20:14:54.751013 Byte1 TX OE(2T, 0.5T) = (3, 3)
8008 20:14:54.751134
8009 20:14:54.751229
8010 20:14:54.757491 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8011 20:14:54.761471 CH0 RK0: MR19=303, MR18=231F
8012 20:14:54.767895 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
8013 20:14:54.767983
8014 20:14:54.771216 ----->DramcWriteLeveling(PI) begin...
8015 20:14:54.771327 ==
8016 20:14:54.774902 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 20:14:54.778114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 20:14:54.778225 ==
8019 20:14:54.781313 Write leveling (Byte 0): 35 => 35
8020 20:14:54.784816 Write leveling (Byte 1): 29 => 29
8021 20:14:54.787880 DramcWriteLeveling(PI) end<-----
8022 20:14:54.787963
8023 20:14:54.788027 ==
8024 20:14:54.791181 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 20:14:54.794874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 20:14:54.794982 ==
8027 20:14:54.798482 [Gating] SW mode calibration
8028 20:14:54.804578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8029 20:14:54.811099 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8030 20:14:54.814868 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 20:14:54.818022 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 20:14:54.824321 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 20:14:54.828187 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8034 20:14:54.831380 1 4 16 | B1->B0 | 2e2e 3636 | 1 0 | (1 1) (1 1)
8035 20:14:54.837473 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8036 20:14:54.840741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 20:14:54.844483 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 20:14:54.851314 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 20:14:54.854577 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8040 20:14:54.857644 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 20:14:54.864640 1 5 12 | B1->B0 | 3434 3736 | 1 1 | (1 0) (1 0)
8042 20:14:54.867805 1 5 16 | B1->B0 | 2c2c 2928 | 1 1 | (1 0) (1 0)
8043 20:14:54.871147 1 5 20 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
8044 20:14:54.877618 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8045 20:14:54.881072 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8046 20:14:54.884147 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8047 20:14:54.890985 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8048 20:14:54.894609 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8049 20:14:54.897590 1 6 12 | B1->B0 | 2929 3837 | 0 1 | (0 0) (0 0)
8050 20:14:54.904368 1 6 16 | B1->B0 | 3c3c 4443 | 1 1 | (0 0) (0 0)
8051 20:14:54.907782 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 20:14:54.911114 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 20:14:54.914356 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 20:14:54.920842 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 20:14:54.924215 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 20:14:54.927394 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 20:14:54.934027 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8058 20:14:54.937795 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8059 20:14:54.940690 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 20:14:54.947570 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 20:14:54.950703 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 20:14:54.954527 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 20:14:54.960780 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 20:14:54.964534 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 20:14:54.967804 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 20:14:54.974404 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 20:14:54.977728 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 20:14:54.980765 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 20:14:54.987555 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 20:14:54.991426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 20:14:54.994548 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 20:14:55.000714 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 20:14:55.004576 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8074 20:14:55.007445 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8075 20:14:55.011091 Total UI for P1: 0, mck2ui 16
8076 20:14:55.014081 best dqsien dly found for B0: ( 1, 9, 12)
8077 20:14:55.017473 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 20:14:55.021022 Total UI for P1: 0, mck2ui 16
8079 20:14:55.024430 best dqsien dly found for B1: ( 1, 9, 14)
8080 20:14:55.027466 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8081 20:14:55.031066 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8082 20:14:55.033995
8083 20:14:55.037735 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8084 20:14:55.040928 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8085 20:14:55.044263 [Gating] SW calibration Done
8086 20:14:55.044404 ==
8087 20:14:55.047367 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 20:14:55.050925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 20:14:55.051052 ==
8090 20:14:55.051177 RX Vref Scan: 0
8091 20:14:55.054195
8092 20:14:55.054321 RX Vref 0 -> 0, step: 1
8093 20:14:55.054446
8094 20:14:55.057467 RX Delay 0 -> 252, step: 8
8095 20:14:55.061029 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8096 20:14:55.064621 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8097 20:14:55.067637 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8098 20:14:55.074790 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8099 20:14:55.077857 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8100 20:14:55.081083 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8101 20:14:55.084470 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8102 20:14:55.087853 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8103 20:14:55.094068 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8104 20:14:55.097912 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8105 20:14:55.100707 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8106 20:14:55.103948 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8107 20:14:55.110858 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8108 20:14:55.114176 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8109 20:14:55.117503 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8110 20:14:55.120878 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8111 20:14:55.120996 ==
8112 20:14:55.123967 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 20:14:55.127447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 20:14:55.130884 ==
8115 20:14:55.131012 DQS Delay:
8116 20:14:55.131135 DQS0 = 0, DQS1 = 0
8117 20:14:55.134204 DQM Delay:
8118 20:14:55.134340 DQM0 = 136, DQM1 = 129
8119 20:14:55.137383 DQ Delay:
8120 20:14:55.140996 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8121 20:14:55.144076 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8122 20:14:55.147075 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8123 20:14:55.150842 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8124 20:14:55.150966
8125 20:14:55.151088
8126 20:14:55.151202 ==
8127 20:14:55.153999 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 20:14:55.157019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 20:14:55.160717 ==
8130 20:14:55.160841
8131 20:14:55.160966
8132 20:14:55.161078 TX Vref Scan disable
8133 20:14:55.164013 == TX Byte 0 ==
8134 20:14:55.166841 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8135 20:14:55.170415 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8136 20:14:55.173700 == TX Byte 1 ==
8137 20:14:55.176681 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8138 20:14:55.179922 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8139 20:14:55.183382 ==
8140 20:14:55.186607 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 20:14:55.189852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 20:14:55.190034 ==
8143 20:14:55.202876
8144 20:14:55.206539 TX Vref early break, caculate TX vref
8145 20:14:55.209675 TX Vref=16, minBit 1, minWin=23, winSum=386
8146 20:14:55.212858 TX Vref=18, minBit 2, minWin=23, winSum=396
8147 20:14:55.216575 TX Vref=20, minBit 1, minWin=24, winSum=404
8148 20:14:55.219866 TX Vref=22, minBit 1, minWin=24, winSum=411
8149 20:14:55.223170 TX Vref=24, minBit 1, minWin=25, winSum=418
8150 20:14:55.229516 TX Vref=26, minBit 0, minWin=25, winSum=424
8151 20:14:55.232524 TX Vref=28, minBit 1, minWin=25, winSum=421
8152 20:14:55.235975 TX Vref=30, minBit 0, minWin=25, winSum=416
8153 20:14:55.239739 TX Vref=32, minBit 7, minWin=24, winSum=411
8154 20:14:55.242781 TX Vref=34, minBit 0, minWin=23, winSum=395
8155 20:14:55.249578 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8156 20:14:55.249661
8157 20:14:55.252771 Final TX Range 0 Vref 26
8158 20:14:55.252855
8159 20:14:55.252920 ==
8160 20:14:55.255797 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 20:14:55.258995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 20:14:55.259078 ==
8163 20:14:55.259143
8164 20:14:55.259203
8165 20:14:55.262241 TX Vref Scan disable
8166 20:14:55.269111 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8167 20:14:55.269195 == TX Byte 0 ==
8168 20:14:55.272870 u2DelayCellOfst[0]=10 cells (3 PI)
8169 20:14:55.275990 u2DelayCellOfst[1]=16 cells (5 PI)
8170 20:14:55.279169 u2DelayCellOfst[2]=10 cells (3 PI)
8171 20:14:55.282414 u2DelayCellOfst[3]=6 cells (2 PI)
8172 20:14:55.286049 u2DelayCellOfst[4]=10 cells (3 PI)
8173 20:14:55.289065 u2DelayCellOfst[5]=0 cells (0 PI)
8174 20:14:55.292438 u2DelayCellOfst[6]=16 cells (5 PI)
8175 20:14:55.295626 u2DelayCellOfst[7]=13 cells (4 PI)
8176 20:14:55.299311 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8177 20:14:55.302235 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8178 20:14:55.305922 == TX Byte 1 ==
8179 20:14:55.306048 u2DelayCellOfst[8]=0 cells (0 PI)
8180 20:14:55.308980 u2DelayCellOfst[9]=0 cells (0 PI)
8181 20:14:55.312061 u2DelayCellOfst[10]=6 cells (2 PI)
8182 20:14:55.315319 u2DelayCellOfst[11]=3 cells (1 PI)
8183 20:14:55.319027 u2DelayCellOfst[12]=10 cells (3 PI)
8184 20:14:55.322198 u2DelayCellOfst[13]=10 cells (3 PI)
8185 20:14:55.325748 u2DelayCellOfst[14]=13 cells (4 PI)
8186 20:14:55.328801 u2DelayCellOfst[15]=10 cells (3 PI)
8187 20:14:55.332454 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8188 20:14:55.338671 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8189 20:14:55.338800 DramC Write-DBI on
8190 20:14:55.338920 ==
8191 20:14:55.342610 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 20:14:55.345482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 20:14:55.348599 ==
8194 20:14:55.348718
8195 20:14:55.348838
8196 20:14:55.348944 TX Vref Scan disable
8197 20:14:55.352862 == TX Byte 0 ==
8198 20:14:55.356089 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8199 20:14:55.359219 == TX Byte 1 ==
8200 20:14:55.362380 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8201 20:14:55.365506 DramC Write-DBI off
8202 20:14:55.365627
8203 20:14:55.365741 [DATLAT]
8204 20:14:55.365859 Freq=1600, CH0 RK1
8205 20:14:55.365968
8206 20:14:55.369217 DATLAT Default: 0xf
8207 20:14:55.369375 0, 0xFFFF, sum = 0
8208 20:14:55.372249 1, 0xFFFF, sum = 0
8209 20:14:55.375530 2, 0xFFFF, sum = 0
8210 20:14:55.375651 3, 0xFFFF, sum = 0
8211 20:14:55.379327 4, 0xFFFF, sum = 0
8212 20:14:55.379449 5, 0xFFFF, sum = 0
8213 20:14:55.382425 6, 0xFFFF, sum = 0
8214 20:14:55.382555 7, 0xFFFF, sum = 0
8215 20:14:55.385599 8, 0xFFFF, sum = 0
8216 20:14:55.385719 9, 0xFFFF, sum = 0
8217 20:14:55.388897 10, 0xFFFF, sum = 0
8218 20:14:55.389019 11, 0xFFFF, sum = 0
8219 20:14:55.392198 12, 0xFFFF, sum = 0
8220 20:14:55.392339 13, 0xFFFF, sum = 0
8221 20:14:55.395412 14, 0x0, sum = 1
8222 20:14:55.395545 15, 0x0, sum = 2
8223 20:14:55.399131 16, 0x0, sum = 3
8224 20:14:55.399254 17, 0x0, sum = 4
8225 20:14:55.402296 best_step = 15
8226 20:14:55.402420
8227 20:14:55.402534 ==
8228 20:14:55.405910 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 20:14:55.408988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 20:14:55.409119 ==
8231 20:14:55.412139 RX Vref Scan: 0
8232 20:14:55.412276
8233 20:14:55.412410 RX Vref 0 -> 0, step: 1
8234 20:14:55.412523
8235 20:14:55.415729 RX Delay 19 -> 252, step: 4
8236 20:14:55.419109 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8237 20:14:55.425585 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8238 20:14:55.428992 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8239 20:14:55.432197 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8240 20:14:55.435600 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8241 20:14:55.438958 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8242 20:14:55.445875 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8243 20:14:55.448967 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8244 20:14:55.452244 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8245 20:14:55.455525 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8246 20:14:55.458484 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8247 20:14:55.465229 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8248 20:14:55.468616 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8249 20:14:55.472223 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8250 20:14:55.475503 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8251 20:14:55.478794 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8252 20:14:55.481875 ==
8253 20:14:55.485606 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 20:14:55.488788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 20:14:55.488871 ==
8256 20:14:55.488936 DQS Delay:
8257 20:14:55.492102 DQS0 = 0, DQS1 = 0
8258 20:14:55.492183 DQM Delay:
8259 20:14:55.495236 DQM0 = 133, DQM1 = 127
8260 20:14:55.495317 DQ Delay:
8261 20:14:55.498976 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =132
8262 20:14:55.501981 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8263 20:14:55.505233 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8264 20:14:55.508385 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8265 20:14:55.508468
8266 20:14:55.508532
8267 20:14:55.508592
8268 20:14:55.512026 [DramC_TX_OE_Calibration] TA2
8269 20:14:55.515092 Original DQ_B0 (3 6) =30, OEN = 27
8270 20:14:55.518805 Original DQ_B1 (3 6) =30, OEN = 27
8271 20:14:55.521880 24, 0x0, End_B0=24 End_B1=24
8272 20:14:55.525448 25, 0x0, End_B0=25 End_B1=25
8273 20:14:55.525531 26, 0x0, End_B0=26 End_B1=26
8274 20:14:55.528539 27, 0x0, End_B0=27 End_B1=27
8275 20:14:55.532180 28, 0x0, End_B0=28 End_B1=28
8276 20:14:55.535562 29, 0x0, End_B0=29 End_B1=29
8277 20:14:55.535672 30, 0x0, End_B0=30 End_B1=30
8278 20:14:55.538468 31, 0x4141, End_B0=30 End_B1=30
8279 20:14:55.542197 Byte0 end_step=30 best_step=27
8280 20:14:55.545263 Byte1 end_step=30 best_step=27
8281 20:14:55.548484 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 20:14:55.552169 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 20:14:55.552253
8284 20:14:55.552346
8285 20:14:55.558471 [DQSOSCAuto] RK1, (LSB)MR18= 0x230a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8286 20:14:55.561465 CH0 RK1: MR19=303, MR18=230A
8287 20:14:55.568241 CH0_RK1: MR19=0x303, MR18=0x230A, DQSOSC=392, MR23=63, INC=24, DEC=16
8288 20:14:55.571506 [RxdqsGatingPostProcess] freq 1600
8289 20:14:55.578435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 20:14:55.578559 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 20:14:55.581282 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 20:14:55.584908 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 20:14:55.588282 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 20:14:55.591538 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 20:14:55.595291 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 20:14:55.598451 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 20:14:55.601484 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 20:14:55.604785 Pre-setting of DQS Precalculation
8299 20:14:55.608696 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 20:14:55.608807 ==
8301 20:14:55.611736 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 20:14:55.618064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 20:14:55.618152 ==
8304 20:14:55.621302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 20:14:55.628132 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 20:14:55.631253 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 20:14:55.637727 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 20:14:55.645243 [CA 0] Center 42 (13~72) winsize 60
8309 20:14:55.648627 [CA 1] Center 42 (12~72) winsize 61
8310 20:14:55.652206 [CA 2] Center 38 (9~68) winsize 60
8311 20:14:55.655462 [CA 3] Center 38 (9~67) winsize 59
8312 20:14:55.658894 [CA 4] Center 38 (9~68) winsize 60
8313 20:14:55.662057 [CA 5] Center 37 (7~67) winsize 61
8314 20:14:55.662158
8315 20:14:55.665337 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 20:14:55.665422
8317 20:14:55.668552 [CATrainingPosCal] consider 1 rank data
8318 20:14:55.672143 u2DelayCellTimex100 = 290/100 ps
8319 20:14:55.675334 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8320 20:14:55.681901 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8321 20:14:55.685151 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8322 20:14:55.688421 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8323 20:14:55.692171 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8324 20:14:55.695157 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8325 20:14:55.695267
8326 20:14:55.698565 CA PerBit enable=1, Macro0, CA PI delay=37
8327 20:14:55.698672
8328 20:14:55.701936 [CBTSetCACLKResult] CA Dly = 37
8329 20:14:55.705558 CS Dly: 10 (0~41)
8330 20:14:55.708432 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 20:14:55.712016 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 20:14:55.712100 ==
8333 20:14:55.715402 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 20:14:55.718452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 20:14:55.718551 ==
8336 20:14:55.725707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 20:14:55.728740 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 20:14:55.735141 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 20:14:55.738478 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 20:14:55.748896 [CA 0] Center 42 (12~72) winsize 61
8341 20:14:55.751914 [CA 1] Center 42 (13~72) winsize 60
8342 20:14:55.755504 [CA 2] Center 39 (9~69) winsize 61
8343 20:14:55.759039 [CA 3] Center 38 (9~68) winsize 60
8344 20:14:55.762185 [CA 4] Center 39 (9~69) winsize 61
8345 20:14:55.765219 [CA 5] Center 37 (8~67) winsize 60
8346 20:14:55.765322
8347 20:14:55.768335 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 20:14:55.768476
8349 20:14:55.772123 [CATrainingPosCal] consider 2 rank data
8350 20:14:55.775113 u2DelayCellTimex100 = 290/100 ps
8351 20:14:55.778454 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8352 20:14:55.785489 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8353 20:14:55.788932 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8354 20:14:55.792023 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8355 20:14:55.795319 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8356 20:14:55.798821 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 20:14:55.798936
8358 20:14:55.801931 CA PerBit enable=1, Macro0, CA PI delay=37
8359 20:14:55.802010
8360 20:14:55.804993 [CBTSetCACLKResult] CA Dly = 37
8361 20:14:55.808210 CS Dly: 11 (0~44)
8362 20:14:55.811668 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 20:14:55.814866 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 20:14:55.814974
8365 20:14:55.818297 ----->DramcWriteLeveling(PI) begin...
8366 20:14:55.818410 ==
8367 20:14:55.821442 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 20:14:55.825105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 20:14:55.828388 ==
8370 20:14:55.828507 Write leveling (Byte 0): 27 => 27
8371 20:14:55.831753 Write leveling (Byte 1): 28 => 28
8372 20:14:55.834799 DramcWriteLeveling(PI) end<-----
8373 20:14:55.834906
8374 20:14:55.834999 ==
8375 20:14:55.838127 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 20:14:55.845227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 20:14:55.845352 ==
8378 20:14:55.848218 [Gating] SW mode calibration
8379 20:14:55.855047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 20:14:55.858551 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 20:14:55.864754 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 20:14:55.868609 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 20:14:55.871637 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (1 1) (0 0)
8384 20:14:55.878201 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8385 20:14:55.881188 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 20:14:55.884528 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 20:14:55.891705 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 20:14:55.894930 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 20:14:55.898254 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 20:14:55.904839 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 20:14:55.907948 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8392 20:14:55.911109 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8393 20:14:55.914944 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 20:14:55.921523 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 20:14:55.924737 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 20:14:55.927876 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 20:14:55.934433 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 20:14:55.937786 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 20:14:55.941206 1 6 8 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
8400 20:14:55.947545 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8401 20:14:55.950785 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 20:14:55.954614 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 20:14:55.960773 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 20:14:55.964547 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 20:14:55.967992 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 20:14:55.974492 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 20:14:55.977865 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8408 20:14:55.981191 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 20:14:55.987768 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 20:14:55.990625 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 20:14:55.993975 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 20:14:56.000743 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 20:14:56.003900 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 20:14:56.007730 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 20:14:56.014116 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 20:14:56.017216 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 20:14:56.021093 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 20:14:56.027288 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 20:14:56.030412 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 20:14:56.034206 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 20:14:56.040529 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 20:14:56.044022 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 20:14:56.047400 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8424 20:14:56.053775 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 20:14:56.057392 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 20:14:56.060539 Total UI for P1: 0, mck2ui 16
8427 20:14:56.064121 best dqsien dly found for B0: ( 1, 9, 10)
8428 20:14:56.067170 Total UI for P1: 0, mck2ui 16
8429 20:14:56.070286 best dqsien dly found for B1: ( 1, 9, 10)
8430 20:14:56.073673 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8431 20:14:56.076892 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8432 20:14:56.076973
8433 20:14:56.080418 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8434 20:14:56.083954 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8435 20:14:56.086933 [Gating] SW calibration Done
8436 20:14:56.087049 ==
8437 20:14:56.090798 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 20:14:56.093947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 20:14:56.094058 ==
8440 20:14:56.097204 RX Vref Scan: 0
8441 20:14:56.097285
8442 20:14:56.100669 RX Vref 0 -> 0, step: 1
8443 20:14:56.100776
8444 20:14:56.100870 RX Delay 0 -> 252, step: 8
8445 20:14:56.107204 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8446 20:14:56.110747 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8447 20:14:56.113612 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8448 20:14:56.117237 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8449 20:14:56.120529 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8450 20:14:56.127179 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8451 20:14:56.130287 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8452 20:14:56.133905 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8453 20:14:56.137012 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8454 20:14:56.140100 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8455 20:14:56.146858 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8456 20:14:56.150003 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8457 20:14:56.153584 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8458 20:14:56.156920 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8459 20:14:56.160102 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8460 20:14:56.166863 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8461 20:14:56.166943 ==
8462 20:14:56.170435 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 20:14:56.173573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 20:14:56.173650 ==
8465 20:14:56.173714 DQS Delay:
8466 20:14:56.176690 DQS0 = 0, DQS1 = 0
8467 20:14:56.176760 DQM Delay:
8468 20:14:56.180235 DQM0 = 136, DQM1 = 133
8469 20:14:56.180316 DQ Delay:
8470 20:14:56.183859 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8471 20:14:56.187000 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8472 20:14:56.190017 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8473 20:14:56.193726 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8474 20:14:56.193804
8475 20:14:56.193866
8476 20:14:56.196844 ==
8477 20:14:56.199954 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 20:14:56.203060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 20:14:56.203134 ==
8480 20:14:56.203196
8481 20:14:56.203254
8482 20:14:56.206682 TX Vref Scan disable
8483 20:14:56.206753 == TX Byte 0 ==
8484 20:14:56.209679 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8485 20:14:56.216395 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8486 20:14:56.216483 == TX Byte 1 ==
8487 20:14:56.219463 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8488 20:14:56.226325 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8489 20:14:56.226436 ==
8490 20:14:56.229680 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 20:14:56.232971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 20:14:56.233054 ==
8493 20:14:56.245746
8494 20:14:56.249576 TX Vref early break, caculate TX vref
8495 20:14:56.252689 TX Vref=16, minBit 1, minWin=23, winSum=377
8496 20:14:56.255739 TX Vref=18, minBit 1, minWin=23, winSum=381
8497 20:14:56.258835 TX Vref=20, minBit 1, minWin=23, winSum=395
8498 20:14:56.262518 TX Vref=22, minBit 0, minWin=24, winSum=404
8499 20:14:56.265550 TX Vref=24, minBit 0, minWin=25, winSum=412
8500 20:14:56.272034 TX Vref=26, minBit 0, minWin=25, winSum=421
8501 20:14:56.275868 TX Vref=28, minBit 0, minWin=25, winSum=422
8502 20:14:56.278981 TX Vref=30, minBit 0, minWin=25, winSum=417
8503 20:14:56.282192 TX Vref=32, minBit 0, minWin=24, winSum=409
8504 20:14:56.285876 TX Vref=34, minBit 0, minWin=23, winSum=397
8505 20:14:56.292083 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8506 20:14:56.292164
8507 20:14:56.295745 Final TX Range 0 Vref 28
8508 20:14:56.295819
8509 20:14:56.295881 ==
8510 20:14:56.299177 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 20:14:56.302343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 20:14:56.302415 ==
8513 20:14:56.302480
8514 20:14:56.302539
8515 20:14:56.305500 TX Vref Scan disable
8516 20:14:56.312306 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8517 20:14:56.312380 == TX Byte 0 ==
8518 20:14:56.315570 u2DelayCellOfst[0]=16 cells (5 PI)
8519 20:14:56.318593 u2DelayCellOfst[1]=10 cells (3 PI)
8520 20:14:56.322359 u2DelayCellOfst[2]=0 cells (0 PI)
8521 20:14:56.325303 u2DelayCellOfst[3]=6 cells (2 PI)
8522 20:14:56.329229 u2DelayCellOfst[4]=10 cells (3 PI)
8523 20:14:56.332514 u2DelayCellOfst[5]=16 cells (5 PI)
8524 20:14:56.335784 u2DelayCellOfst[6]=16 cells (5 PI)
8525 20:14:56.335928 u2DelayCellOfst[7]=3 cells (1 PI)
8526 20:14:56.341975 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8527 20:14:56.345687 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8528 20:14:56.345792 == TX Byte 1 ==
8529 20:14:56.348860 u2DelayCellOfst[8]=0 cells (0 PI)
8530 20:14:56.351965 u2DelayCellOfst[9]=3 cells (1 PI)
8531 20:14:56.355574 u2DelayCellOfst[10]=10 cells (3 PI)
8532 20:14:56.359081 u2DelayCellOfst[11]=3 cells (1 PI)
8533 20:14:56.362260 u2DelayCellOfst[12]=13 cells (4 PI)
8534 20:14:56.365824 u2DelayCellOfst[13]=13 cells (4 PI)
8535 20:14:56.368917 u2DelayCellOfst[14]=13 cells (4 PI)
8536 20:14:56.371988 u2DelayCellOfst[15]=13 cells (4 PI)
8537 20:14:56.375283 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8538 20:14:56.381957 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8539 20:14:56.382039 DramC Write-DBI on
8540 20:14:56.382134 ==
8541 20:14:56.385693 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 20:14:56.388927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 20:14:56.389048 ==
8544 20:14:56.392132
8545 20:14:56.392243
8546 20:14:56.392346 TX Vref Scan disable
8547 20:14:56.395379 == TX Byte 0 ==
8548 20:14:56.398639 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8549 20:14:56.402479 == TX Byte 1 ==
8550 20:14:56.405247 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8551 20:14:56.405359 DramC Write-DBI off
8552 20:14:56.405475
8553 20:14:56.408387 [DATLAT]
8554 20:14:56.408497 Freq=1600, CH1 RK0
8555 20:14:56.408631
8556 20:14:56.412081 DATLAT Default: 0xf
8557 20:14:56.412184 0, 0xFFFF, sum = 0
8558 20:14:56.415200 1, 0xFFFF, sum = 0
8559 20:14:56.415311 2, 0xFFFF, sum = 0
8560 20:14:56.418460 3, 0xFFFF, sum = 0
8561 20:14:56.418544 4, 0xFFFF, sum = 0
8562 20:14:56.421948 5, 0xFFFF, sum = 0
8563 20:14:56.425330 6, 0xFFFF, sum = 0
8564 20:14:56.425413 7, 0xFFFF, sum = 0
8565 20:14:56.428639 8, 0xFFFF, sum = 0
8566 20:14:56.428719 9, 0xFFFF, sum = 0
8567 20:14:56.431720 10, 0xFFFF, sum = 0
8568 20:14:56.431805 11, 0xFFFF, sum = 0
8569 20:14:56.435223 12, 0xFFFF, sum = 0
8570 20:14:56.435306 13, 0xFFFF, sum = 0
8571 20:14:56.438376 14, 0x0, sum = 1
8572 20:14:56.438486 15, 0x0, sum = 2
8573 20:14:56.441714 16, 0x0, sum = 3
8574 20:14:56.441797 17, 0x0, sum = 4
8575 20:14:56.444921 best_step = 15
8576 20:14:56.445029
8577 20:14:56.445122 ==
8578 20:14:56.448071 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 20:14:56.451412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 20:14:56.451541 ==
8581 20:14:56.454984 RX Vref Scan: 1
8582 20:14:56.455108
8583 20:14:56.455223 Set Vref Range= 24 -> 127
8584 20:14:56.455338
8585 20:14:56.458257 RX Vref 24 -> 127, step: 1
8586 20:14:56.458383
8587 20:14:56.461489 RX Delay 27 -> 252, step: 4
8588 20:14:56.461610
8589 20:14:56.464920 Set Vref, RX VrefLevel [Byte0]: 24
8590 20:14:56.468004 [Byte1]: 24
8591 20:14:56.468130
8592 20:14:56.471614 Set Vref, RX VrefLevel [Byte0]: 25
8593 20:14:56.474578 [Byte1]: 25
8594 20:14:56.474687
8595 20:14:56.478330 Set Vref, RX VrefLevel [Byte0]: 26
8596 20:14:56.481148 [Byte1]: 26
8597 20:14:56.485048
8598 20:14:56.485160 Set Vref, RX VrefLevel [Byte0]: 27
8599 20:14:56.488508 [Byte1]: 27
8600 20:14:56.492694
8601 20:14:56.492807 Set Vref, RX VrefLevel [Byte0]: 28
8602 20:14:56.496212 [Byte1]: 28
8603 20:14:56.500430
8604 20:14:56.500538 Set Vref, RX VrefLevel [Byte0]: 29
8605 20:14:56.503783 [Byte1]: 29
8606 20:14:56.508108
8607 20:14:56.508217 Set Vref, RX VrefLevel [Byte0]: 30
8608 20:14:56.511003 [Byte1]: 30
8609 20:14:56.515104
8610 20:14:56.515217 Set Vref, RX VrefLevel [Byte0]: 31
8611 20:14:56.518469 [Byte1]: 31
8612 20:14:56.523259
8613 20:14:56.523340 Set Vref, RX VrefLevel [Byte0]: 32
8614 20:14:56.525967 [Byte1]: 32
8615 20:14:56.530610
8616 20:14:56.530728 Set Vref, RX VrefLevel [Byte0]: 33
8617 20:14:56.533977 [Byte1]: 33
8618 20:14:56.538090
8619 20:14:56.538199 Set Vref, RX VrefLevel [Byte0]: 34
8620 20:14:56.541369 [Byte1]: 34
8621 20:14:56.545319
8622 20:14:56.545439 Set Vref, RX VrefLevel [Byte0]: 35
8623 20:14:56.548592 [Byte1]: 35
8624 20:14:56.553078
8625 20:14:56.553160 Set Vref, RX VrefLevel [Byte0]: 36
8626 20:14:56.556381 [Byte1]: 36
8627 20:14:56.560467
8628 20:14:56.560550 Set Vref, RX VrefLevel [Byte0]: 37
8629 20:14:56.563780 [Byte1]: 37
8630 20:14:56.568360
8631 20:14:56.568443 Set Vref, RX VrefLevel [Byte0]: 38
8632 20:14:56.571672 [Byte1]: 38
8633 20:14:56.575510
8634 20:14:56.575585 Set Vref, RX VrefLevel [Byte0]: 39
8635 20:14:56.578659 [Byte1]: 39
8636 20:14:56.583534
8637 20:14:56.583639 Set Vref, RX VrefLevel [Byte0]: 40
8638 20:14:56.586539 [Byte1]: 40
8639 20:14:56.590918
8640 20:14:56.591027 Set Vref, RX VrefLevel [Byte0]: 41
8641 20:14:56.594034 [Byte1]: 41
8642 20:14:56.598440
8643 20:14:56.598532 Set Vref, RX VrefLevel [Byte0]: 42
8644 20:14:56.601776 [Byte1]: 42
8645 20:14:56.605797
8646 20:14:56.605883 Set Vref, RX VrefLevel [Byte0]: 43
8647 20:14:56.608822 [Byte1]: 43
8648 20:14:56.613159
8649 20:14:56.613237 Set Vref, RX VrefLevel [Byte0]: 44
8650 20:14:56.619993 [Byte1]: 44
8651 20:14:56.620102
8652 20:14:56.623192 Set Vref, RX VrefLevel [Byte0]: 45
8653 20:14:56.626123 [Byte1]: 45
8654 20:14:56.626203
8655 20:14:56.629466 Set Vref, RX VrefLevel [Byte0]: 46
8656 20:14:56.633086 [Byte1]: 46
8657 20:14:56.633169
8658 20:14:56.636544 Set Vref, RX VrefLevel [Byte0]: 47
8659 20:14:56.639720 [Byte1]: 47
8660 20:14:56.643383
8661 20:14:56.643459 Set Vref, RX VrefLevel [Byte0]: 48
8662 20:14:56.646484 [Byte1]: 48
8663 20:14:56.650885
8664 20:14:56.650962 Set Vref, RX VrefLevel [Byte0]: 49
8665 20:14:56.654104 [Byte1]: 49
8666 20:14:56.658715
8667 20:14:56.658793 Set Vref, RX VrefLevel [Byte0]: 50
8668 20:14:56.662197 [Byte1]: 50
8669 20:14:56.666033
8670 20:14:56.666109 Set Vref, RX VrefLevel [Byte0]: 51
8671 20:14:56.669485 [Byte1]: 51
8672 20:14:56.673466
8673 20:14:56.673544 Set Vref, RX VrefLevel [Byte0]: 52
8674 20:14:56.676831 [Byte1]: 52
8675 20:14:56.680891
8676 20:14:56.680968 Set Vref, RX VrefLevel [Byte0]: 53
8677 20:14:56.684083 [Byte1]: 53
8678 20:14:56.688283
8679 20:14:56.688396 Set Vref, RX VrefLevel [Byte0]: 54
8680 20:14:56.691991 [Byte1]: 54
8681 20:14:56.696124
8682 20:14:56.696227 Set Vref, RX VrefLevel [Byte0]: 55
8683 20:14:56.699086 [Byte1]: 55
8684 20:14:56.703587
8685 20:14:56.703717 Set Vref, RX VrefLevel [Byte0]: 56
8686 20:14:56.706782 [Byte1]: 56
8687 20:14:56.711348
8688 20:14:56.711467 Set Vref, RX VrefLevel [Byte0]: 57
8689 20:14:56.714733 [Byte1]: 57
8690 20:14:56.718462
8691 20:14:56.718586 Set Vref, RX VrefLevel [Byte0]: 58
8692 20:14:56.721830 [Byte1]: 58
8693 20:14:56.726397
8694 20:14:56.726515 Set Vref, RX VrefLevel [Byte0]: 59
8695 20:14:56.729589 [Byte1]: 59
8696 20:14:56.734194
8697 20:14:56.734316 Set Vref, RX VrefLevel [Byte0]: 60
8698 20:14:56.737547 [Byte1]: 60
8699 20:14:56.741456
8700 20:14:56.741572 Set Vref, RX VrefLevel [Byte0]: 61
8701 20:14:56.744555 [Byte1]: 61
8702 20:14:56.749086
8703 20:14:56.749196 Set Vref, RX VrefLevel [Byte0]: 62
8704 20:14:56.752506 [Byte1]: 62
8705 20:14:56.756771
8706 20:14:56.756854 Set Vref, RX VrefLevel [Byte0]: 63
8707 20:14:56.759689 [Byte1]: 63
8708 20:14:56.763757
8709 20:14:56.763883 Set Vref, RX VrefLevel [Byte0]: 64
8710 20:14:56.767234 [Byte1]: 64
8711 20:14:56.771250
8712 20:14:56.771332 Set Vref, RX VrefLevel [Byte0]: 65
8713 20:14:56.774454 [Byte1]: 65
8714 20:14:56.779153
8715 20:14:56.779284 Set Vref, RX VrefLevel [Byte0]: 66
8716 20:14:56.782529 [Byte1]: 66
8717 20:14:56.786608
8718 20:14:56.786733 Set Vref, RX VrefLevel [Byte0]: 67
8719 20:14:56.789882 [Byte1]: 67
8720 20:14:56.794259
8721 20:14:56.794384 Set Vref, RX VrefLevel [Byte0]: 68
8722 20:14:56.797262 [Byte1]: 68
8723 20:14:56.801566
8724 20:14:56.801691 Set Vref, RX VrefLevel [Byte0]: 69
8725 20:14:56.804695 [Byte1]: 69
8726 20:14:56.809513
8727 20:14:56.809637 Set Vref, RX VrefLevel [Byte0]: 70
8728 20:14:56.812426 [Byte1]: 70
8729 20:14:56.817028
8730 20:14:56.817156 Set Vref, RX VrefLevel [Byte0]: 71
8731 20:14:56.820194 [Byte1]: 71
8732 20:14:56.824162
8733 20:14:56.824292 Set Vref, RX VrefLevel [Byte0]: 72
8734 20:14:56.827503 [Byte1]: 72
8735 20:14:56.831413
8736 20:14:56.831532 Set Vref, RX VrefLevel [Byte0]: 73
8737 20:14:56.835498 [Byte1]: 73
8738 20:14:56.839321
8739 20:14:56.839446 Final RX Vref Byte 0 = 57 to rank0
8740 20:14:56.842529 Final RX Vref Byte 1 = 57 to rank0
8741 20:14:56.845739 Final RX Vref Byte 0 = 57 to rank1
8742 20:14:56.849385 Final RX Vref Byte 1 = 57 to rank1==
8743 20:14:56.852300 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 20:14:56.858897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 20:14:56.859023 ==
8746 20:14:56.859140 DQS Delay:
8747 20:14:56.859254 DQS0 = 0, DQS1 = 0
8748 20:14:56.862302 DQM Delay:
8749 20:14:56.862425 DQM0 = 133, DQM1 = 131
8750 20:14:56.865756 DQ Delay:
8751 20:14:56.869404 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8752 20:14:56.872765 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8753 20:14:56.875840 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8754 20:14:56.879334 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8755 20:14:56.879461
8756 20:14:56.879574
8757 20:14:56.879689
8758 20:14:56.882290 [DramC_TX_OE_Calibration] TA2
8759 20:14:56.885662 Original DQ_B0 (3 6) =30, OEN = 27
8760 20:14:56.889478 Original DQ_B1 (3 6) =30, OEN = 27
8761 20:14:56.892798 24, 0x0, End_B0=24 End_B1=24
8762 20:14:56.892928 25, 0x0, End_B0=25 End_B1=25
8763 20:14:56.896168 26, 0x0, End_B0=26 End_B1=26
8764 20:14:56.898991 27, 0x0, End_B0=27 End_B1=27
8765 20:14:56.902510 28, 0x0, End_B0=28 End_B1=28
8766 20:14:56.902640 29, 0x0, End_B0=29 End_B1=29
8767 20:14:56.905802 30, 0x0, End_B0=30 End_B1=30
8768 20:14:56.908995 31, 0x5151, End_B0=30 End_B1=30
8769 20:14:56.912658 Byte0 end_step=30 best_step=27
8770 20:14:56.915989 Byte1 end_step=30 best_step=27
8771 20:14:56.919136 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 20:14:56.919238 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 20:14:56.922201
8774 20:14:56.922311
8775 20:14:56.928690 [DQSOSCAuto] RK0, (LSB)MR18= 0x1522, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8776 20:14:56.932599 CH1 RK0: MR19=303, MR18=1522
8777 20:14:56.938739 CH1_RK0: MR19=0x303, MR18=0x1522, DQSOSC=392, MR23=63, INC=24, DEC=16
8778 20:14:56.938849
8779 20:14:56.941982 ----->DramcWriteLeveling(PI) begin...
8780 20:14:56.942093 ==
8781 20:14:56.945880 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 20:14:56.949085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 20:14:56.949196 ==
8784 20:14:56.952279 Write leveling (Byte 0): 25 => 25
8785 20:14:56.955454 Write leveling (Byte 1): 31 => 31
8786 20:14:56.958718 DramcWriteLeveling(PI) end<-----
8787 20:14:56.958843
8788 20:14:56.958960 ==
8789 20:14:56.962377 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 20:14:56.965437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 20:14:56.965563 ==
8792 20:14:56.968979 [Gating] SW mode calibration
8793 20:14:56.975549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 20:14:56.982082 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 20:14:56.985631 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 20:14:56.989071 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 20:14:56.995342 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8798 20:14:56.998790 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 20:14:57.001711 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 20:14:57.008678 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 20:14:57.011634 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 20:14:57.015455 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 20:14:57.021641 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 20:14:57.025393 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 20:14:57.028217 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8806 20:14:57.035069 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8807 20:14:57.038267 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 20:14:57.041372 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 20:14:57.048305 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 20:14:57.051496 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 20:14:57.054660 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 20:14:57.061641 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 20:14:57.064779 1 6 8 | B1->B0 | 4040 2323 | 0 0 | (0 0) (0 0)
8814 20:14:57.067870 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
8815 20:14:57.074651 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 20:14:57.077693 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 20:14:57.081256 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 20:14:57.087957 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 20:14:57.091232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 20:14:57.094425 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 20:14:57.101452 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 20:14:57.104540 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8823 20:14:57.107710 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8824 20:14:57.114591 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 20:14:57.117672 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 20:14:57.121440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 20:14:57.127990 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 20:14:57.130931 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 20:14:57.134513 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 20:14:57.140971 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 20:14:57.144327 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 20:14:57.147630 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 20:14:57.154481 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 20:14:57.157507 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 20:14:57.161436 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 20:14:57.164419 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 20:14:57.171317 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 20:14:57.174499 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8839 20:14:57.177578 Total UI for P1: 0, mck2ui 16
8840 20:14:57.180819 best dqsien dly found for B1: ( 1, 9, 8)
8841 20:14:57.184398 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 20:14:57.187585 Total UI for P1: 0, mck2ui 16
8843 20:14:57.191222 best dqsien dly found for B0: ( 1, 9, 12)
8844 20:14:57.194130 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8845 20:14:57.197827 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8846 20:14:57.197948
8847 20:14:57.204244 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8848 20:14:57.207966 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8849 20:14:57.211124 [Gating] SW calibration Done
8850 20:14:57.211204 ==
8851 20:14:57.214859 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 20:14:57.217919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 20:14:57.218000 ==
8854 20:14:57.218064 RX Vref Scan: 0
8855 20:14:57.218123
8856 20:14:57.221030 RX Vref 0 -> 0, step: 1
8857 20:14:57.221110
8858 20:14:57.224575 RX Delay 0 -> 252, step: 8
8859 20:14:57.227480 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8860 20:14:57.230996 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8861 20:14:57.237677 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8862 20:14:57.240870 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8863 20:14:57.243879 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8864 20:14:57.247371 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8865 20:14:57.250424 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8866 20:14:57.257200 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8867 20:14:57.260523 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8868 20:14:57.263861 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8869 20:14:57.267314 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8870 20:14:57.270683 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8871 20:14:57.277055 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8872 20:14:57.280249 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8873 20:14:57.284006 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8874 20:14:57.287067 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8875 20:14:57.287148 ==
8876 20:14:57.290790 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 20:14:57.297125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 20:14:57.297206 ==
8879 20:14:57.297269 DQS Delay:
8880 20:14:57.297327 DQS0 = 0, DQS1 = 0
8881 20:14:57.300616 DQM Delay:
8882 20:14:57.300712 DQM0 = 136, DQM1 = 134
8883 20:14:57.303778 DQ Delay:
8884 20:14:57.306861 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8885 20:14:57.310615 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8886 20:14:57.313802 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =131
8887 20:14:57.317013 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8888 20:14:57.317093
8889 20:14:57.317156
8890 20:14:57.317215 ==
8891 20:14:57.320716 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 20:14:57.323850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 20:14:57.323930 ==
8894 20:14:57.327020
8895 20:14:57.327100
8896 20:14:57.327165 TX Vref Scan disable
8897 20:14:57.330687 == TX Byte 0 ==
8898 20:14:57.333660 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 20:14:57.337305 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 20:14:57.340196 == TX Byte 1 ==
8901 20:14:57.343718 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8902 20:14:57.347247 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8903 20:14:57.347328 ==
8904 20:14:57.350478 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 20:14:57.357189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 20:14:57.357280 ==
8907 20:14:57.369359
8908 20:14:57.372333 TX Vref early break, caculate TX vref
8909 20:14:57.375848 TX Vref=16, minBit 0, minWin=23, winSum=384
8910 20:14:57.378841 TX Vref=18, minBit 0, minWin=23, winSum=396
8911 20:14:57.382747 TX Vref=20, minBit 0, minWin=23, winSum=399
8912 20:14:57.386005 TX Vref=22, minBit 1, minWin=24, winSum=413
8913 20:14:57.389253 TX Vref=24, minBit 0, minWin=25, winSum=418
8914 20:14:57.395552 TX Vref=26, minBit 0, minWin=25, winSum=424
8915 20:14:57.398853 TX Vref=28, minBit 0, minWin=25, winSum=423
8916 20:14:57.402124 TX Vref=30, minBit 0, minWin=25, winSum=421
8917 20:14:57.405846 TX Vref=32, minBit 0, minWin=25, winSum=412
8918 20:14:57.409450 TX Vref=34, minBit 0, minWin=23, winSum=399
8919 20:14:57.415600 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8920 20:14:57.415685
8921 20:14:57.418823 Final TX Range 0 Vref 26
8922 20:14:57.418906
8923 20:14:57.418990 ==
8924 20:14:57.422514 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 20:14:57.425662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 20:14:57.425746 ==
8927 20:14:57.425831
8928 20:14:57.425910
8929 20:14:57.428889 TX Vref Scan disable
8930 20:14:57.435655 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8931 20:14:57.435739 == TX Byte 0 ==
8932 20:14:57.439370 u2DelayCellOfst[0]=16 cells (5 PI)
8933 20:14:57.442344 u2DelayCellOfst[1]=10 cells (3 PI)
8934 20:14:57.445525 u2DelayCellOfst[2]=0 cells (0 PI)
8935 20:14:57.448942 u2DelayCellOfst[3]=6 cells (2 PI)
8936 20:14:57.452507 u2DelayCellOfst[4]=10 cells (3 PI)
8937 20:14:57.456003 u2DelayCellOfst[5]=16 cells (5 PI)
8938 20:14:57.459170 u2DelayCellOfst[6]=16 cells (5 PI)
8939 20:14:57.459253 u2DelayCellOfst[7]=6 cells (2 PI)
8940 20:14:57.465279 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8941 20:14:57.469007 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8942 20:14:57.472087 == TX Byte 1 ==
8943 20:14:57.472170 u2DelayCellOfst[8]=0 cells (0 PI)
8944 20:14:57.475256 u2DelayCellOfst[9]=3 cells (1 PI)
8945 20:14:57.479062 u2DelayCellOfst[10]=10 cells (3 PI)
8946 20:14:57.482100 u2DelayCellOfst[11]=6 cells (2 PI)
8947 20:14:57.485237 u2DelayCellOfst[12]=13 cells (4 PI)
8948 20:14:57.488663 u2DelayCellOfst[13]=16 cells (5 PI)
8949 20:14:57.491862 u2DelayCellOfst[14]=16 cells (5 PI)
8950 20:14:57.495594 u2DelayCellOfst[15]=20 cells (6 PI)
8951 20:14:57.498411 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8952 20:14:57.505522 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8953 20:14:57.505606 DramC Write-DBI on
8954 20:14:57.505690 ==
8955 20:14:57.508472 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 20:14:57.511887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 20:14:57.515154 ==
8958 20:14:57.515237
8959 20:14:57.515322
8960 20:14:57.515401 TX Vref Scan disable
8961 20:14:57.518376 == TX Byte 0 ==
8962 20:14:57.521859 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8963 20:14:57.525495 == TX Byte 1 ==
8964 20:14:57.528444 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8965 20:14:57.528524 DramC Write-DBI off
8966 20:14:57.531985
8967 20:14:57.532095 [DATLAT]
8968 20:14:57.532187 Freq=1600, CH1 RK1
8969 20:14:57.532275
8970 20:14:57.535281 DATLAT Default: 0xf
8971 20:14:57.535361 0, 0xFFFF, sum = 0
8972 20:14:57.538346 1, 0xFFFF, sum = 0
8973 20:14:57.538429 2, 0xFFFF, sum = 0
8974 20:14:57.541907 3, 0xFFFF, sum = 0
8975 20:14:57.541999 4, 0xFFFF, sum = 0
8976 20:14:57.544989 5, 0xFFFF, sum = 0
8977 20:14:57.548528 6, 0xFFFF, sum = 0
8978 20:14:57.548613 7, 0xFFFF, sum = 0
8979 20:14:57.551631 8, 0xFFFF, sum = 0
8980 20:14:57.551716 9, 0xFFFF, sum = 0
8981 20:14:57.555305 10, 0xFFFF, sum = 0
8982 20:14:57.555390 11, 0xFFFF, sum = 0
8983 20:14:57.558914 12, 0xFFFF, sum = 0
8984 20:14:57.558998 13, 0xFFFF, sum = 0
8985 20:14:57.561724 14, 0x0, sum = 1
8986 20:14:57.561808 15, 0x0, sum = 2
8987 20:14:57.565168 16, 0x0, sum = 3
8988 20:14:57.565278 17, 0x0, sum = 4
8989 20:14:57.568442 best_step = 15
8990 20:14:57.568525
8991 20:14:57.568611 ==
8992 20:14:57.571943 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 20:14:57.575401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 20:14:57.575485 ==
8995 20:14:57.575607 RX Vref Scan: 0
8996 20:14:57.578492
8997 20:14:57.578575 RX Vref 0 -> 0, step: 1
8998 20:14:57.578660
8999 20:14:57.581585 RX Delay 19 -> 252, step: 4
9000 20:14:57.585266 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9001 20:14:57.591927 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9002 20:14:57.595035 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9003 20:14:57.598179 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9004 20:14:57.602043 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9005 20:14:57.605132 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9006 20:14:57.608761 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9007 20:14:57.615347 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9008 20:14:57.618491 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9009 20:14:57.621548 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9010 20:14:57.624847 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9011 20:14:57.628490 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9012 20:14:57.634745 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9013 20:14:57.638156 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9014 20:14:57.641287 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9015 20:14:57.644965 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9016 20:14:57.645045 ==
9017 20:14:57.648335 Dram Type= 6, Freq= 0, CH_1, rank 1
9018 20:14:57.654629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9019 20:14:57.654714 ==
9020 20:14:57.654799 DQS Delay:
9021 20:14:57.658200 DQS0 = 0, DQS1 = 0
9022 20:14:57.658283 DQM Delay:
9023 20:14:57.661113 DQM0 = 134, DQM1 = 130
9024 20:14:57.661196 DQ Delay:
9025 20:14:57.664746 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9026 20:14:57.668407 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9027 20:14:57.671221 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9028 20:14:57.674214 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9029 20:14:57.674297
9030 20:14:57.674396
9031 20:14:57.674493
9032 20:14:57.677940 [DramC_TX_OE_Calibration] TA2
9033 20:14:57.681026 Original DQ_B0 (3 6) =30, OEN = 27
9034 20:14:57.684522 Original DQ_B1 (3 6) =30, OEN = 27
9035 20:14:57.687611 24, 0x0, End_B0=24 End_B1=24
9036 20:14:57.691463 25, 0x0, End_B0=25 End_B1=25
9037 20:14:57.691545 26, 0x0, End_B0=26 End_B1=26
9038 20:14:57.694425 27, 0x0, End_B0=27 End_B1=27
9039 20:14:57.697540 28, 0x0, End_B0=28 End_B1=28
9040 20:14:57.700829 29, 0x0, End_B0=29 End_B1=29
9041 20:14:57.700915 30, 0x0, End_B0=30 End_B1=30
9042 20:14:57.704061 31, 0x4141, End_B0=30 End_B1=30
9043 20:14:57.707819 Byte0 end_step=30 best_step=27
9044 20:14:57.710947 Byte1 end_step=30 best_step=27
9045 20:14:57.714010 Byte0 TX OE(2T, 0.5T) = (3, 3)
9046 20:14:57.717845 Byte1 TX OE(2T, 0.5T) = (3, 3)
9047 20:14:57.717952
9048 20:14:57.718019
9049 20:14:57.724274 [DQSOSCAuto] RK1, (LSB)MR18= 0x240a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9050 20:14:57.727350 CH1 RK1: MR19=303, MR18=240A
9051 20:14:57.734501 CH1_RK1: MR19=0x303, MR18=0x240A, DQSOSC=391, MR23=63, INC=24, DEC=16
9052 20:14:57.737583 [RxdqsGatingPostProcess] freq 1600
9053 20:14:57.744421 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9054 20:14:57.744503 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 20:14:57.747353 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 20:14:57.750673 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 20:14:57.754042 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 20:14:57.757683 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 20:14:57.760772 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 20:14:57.764012 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 20:14:57.767557 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 20:14:57.770765 Pre-setting of DQS Precalculation
9063 20:14:57.774263 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9064 20:14:57.780853 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9065 20:14:57.790583 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9066 20:14:57.790665
9067 20:14:57.790730
9068 20:14:57.794080 [Calibration Summary] 3200 Mbps
9069 20:14:57.794161 CH 0, Rank 0
9070 20:14:57.797174 SW Impedance : PASS
9071 20:14:57.797255 DUTY Scan : NO K
9072 20:14:57.800780 ZQ Calibration : PASS
9073 20:14:57.803820 Jitter Meter : NO K
9074 20:14:57.803900 CBT Training : PASS
9075 20:14:57.807650 Write leveling : PASS
9076 20:14:57.807731 RX DQS gating : PASS
9077 20:14:57.810747 RX DQ/DQS(RDDQC) : PASS
9078 20:14:57.813839 TX DQ/DQS : PASS
9079 20:14:57.813920 RX DATLAT : PASS
9080 20:14:57.817393 RX DQ/DQS(Engine): PASS
9081 20:14:57.820317 TX OE : PASS
9082 20:14:57.820413 All Pass.
9083 20:14:57.820477
9084 20:14:57.820536 CH 0, Rank 1
9085 20:14:57.823950 SW Impedance : PASS
9086 20:14:57.827587 DUTY Scan : NO K
9087 20:14:57.827668 ZQ Calibration : PASS
9088 20:14:57.830685 Jitter Meter : NO K
9089 20:14:57.833864 CBT Training : PASS
9090 20:14:57.833944 Write leveling : PASS
9091 20:14:57.836980 RX DQS gating : PASS
9092 20:14:57.840628 RX DQ/DQS(RDDQC) : PASS
9093 20:14:57.840708 TX DQ/DQS : PASS
9094 20:14:57.843773 RX DATLAT : PASS
9095 20:14:57.846952 RX DQ/DQS(Engine): PASS
9096 20:14:57.847050 TX OE : PASS
9097 20:14:57.847146 All Pass.
9098 20:14:57.850183
9099 20:14:57.850264 CH 1, Rank 0
9100 20:14:57.853953 SW Impedance : PASS
9101 20:14:57.854034 DUTY Scan : NO K
9102 20:14:57.856978 ZQ Calibration : PASS
9103 20:14:57.860083 Jitter Meter : NO K
9104 20:14:57.860164 CBT Training : PASS
9105 20:14:57.863738 Write leveling : PASS
9106 20:14:57.866955 RX DQS gating : PASS
9107 20:14:57.867036 RX DQ/DQS(RDDQC) : PASS
9108 20:14:57.870110 TX DQ/DQS : PASS
9109 20:14:57.870192 RX DATLAT : PASS
9110 20:14:57.873684 RX DQ/DQS(Engine): PASS
9111 20:14:57.877207 TX OE : PASS
9112 20:14:57.877288 All Pass.
9113 20:14:57.877353
9114 20:14:57.877412 CH 1, Rank 1
9115 20:14:57.880152 SW Impedance : PASS
9116 20:14:57.883690 DUTY Scan : NO K
9117 20:14:57.883771 ZQ Calibration : PASS
9118 20:14:57.887121 Jitter Meter : NO K
9119 20:14:57.890462 CBT Training : PASS
9120 20:14:57.890543 Write leveling : PASS
9121 20:14:57.893561 RX DQS gating : PASS
9122 20:14:57.896667 RX DQ/DQS(RDDQC) : PASS
9123 20:14:57.896768 TX DQ/DQS : PASS
9124 20:14:57.900228 RX DATLAT : PASS
9125 20:14:57.903239 RX DQ/DQS(Engine): PASS
9126 20:14:57.903346 TX OE : PASS
9127 20:14:57.906789 All Pass.
9128 20:14:57.906869
9129 20:14:57.906932 DramC Write-DBI on
9130 20:14:57.910335 PER_BANK_REFRESH: Hybrid Mode
9131 20:14:57.910416 TX_TRACKING: ON
9132 20:14:57.920089 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9133 20:14:57.926490 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9134 20:14:57.936977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 20:14:57.940177 [FAST_K] Save calibration result to emmc
9136 20:14:57.943260 sync common calibartion params.
9137 20:14:57.943341 sync cbt_mode0:1, 1:1
9138 20:14:57.946962 dram_init: ddr_geometry: 2
9139 20:14:57.950216 dram_init: ddr_geometry: 2
9140 20:14:57.950296 dram_init: ddr_geometry: 2
9141 20:14:57.953281 0:dram_rank_size:100000000
9142 20:14:57.956335 1:dram_rank_size:100000000
9143 20:14:57.960148 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9144 20:14:57.963186 DFS_SHUFFLE_HW_MODE: ON
9145 20:14:57.966877 dramc_set_vcore_voltage set vcore to 725000
9146 20:14:57.970130 Read voltage for 1600, 0
9147 20:14:57.970210 Vio18 = 0
9148 20:14:57.973255 Vcore = 725000
9149 20:14:57.973335 Vdram = 0
9150 20:14:57.973399 Vddq = 0
9151 20:14:57.973458 Vmddr = 0
9152 20:14:57.976901 switch to 3200 Mbps bootup
9153 20:14:57.979772 [DramcRunTimeConfig]
9154 20:14:57.979855 PHYPLL
9155 20:14:57.982956 DPM_CONTROL_AFTERK: ON
9156 20:14:57.983038 PER_BANK_REFRESH: ON
9157 20:14:57.986530 REFRESH_OVERHEAD_REDUCTION: ON
9158 20:14:57.989639 CMD_PICG_NEW_MODE: OFF
9159 20:14:57.989722 XRTWTW_NEW_MODE: ON
9160 20:14:57.993434 XRTRTR_NEW_MODE: ON
9161 20:14:57.993517 TX_TRACKING: ON
9162 20:14:57.996471 RDSEL_TRACKING: OFF
9163 20:14:57.999595 DQS Precalculation for DVFS: ON
9164 20:14:57.999677 RX_TRACKING: OFF
9165 20:14:58.003208 HW_GATING DBG: ON
9166 20:14:58.003288 ZQCS_ENABLE_LP4: ON
9167 20:14:58.006584 RX_PICG_NEW_MODE: ON
9168 20:14:58.006664 TX_PICG_NEW_MODE: ON
9169 20:14:58.009915 ENABLE_RX_DCM_DPHY: ON
9170 20:14:58.013278 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9171 20:14:58.016160 DUMMY_READ_FOR_TRACKING: OFF
9172 20:14:58.016293 !!! SPM_CONTROL_AFTERK: OFF
9173 20:14:58.019521 !!! SPM could not control APHY
9174 20:14:58.022823 IMPEDANCE_TRACKING: ON
9175 20:14:58.022904 TEMP_SENSOR: ON
9176 20:14:58.026346 HW_SAVE_FOR_SR: OFF
9177 20:14:58.029652 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9178 20:14:58.032801 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9179 20:14:58.032882 Read ODT Tracking: ON
9180 20:14:58.036061 Refresh Rate DeBounce: ON
9181 20:14:58.039426 DFS_NO_QUEUE_FLUSH: ON
9182 20:14:58.042898 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9183 20:14:58.043005 ENABLE_DFS_RUNTIME_MRW: OFF
9184 20:14:58.046300 DDR_RESERVE_NEW_MODE: ON
9185 20:14:58.049584 MR_CBT_SWITCH_FREQ: ON
9186 20:14:58.049667 =========================
9187 20:14:58.069508 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9188 20:14:58.073183 dram_init: ddr_geometry: 2
9189 20:14:58.091250 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9190 20:14:58.094337 dram_init: dram init end (result: 0)
9191 20:14:58.101186 DRAM-K: Full calibration passed in 24421 msecs
9192 20:14:58.104473 MRC: failed to locate region type 0.
9193 20:14:58.104557 DRAM rank0 size:0x100000000,
9194 20:14:58.108173 DRAM rank1 size=0x100000000
9195 20:14:58.117992 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9196 20:14:58.124438 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9197 20:14:58.131432 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9198 20:14:58.138009 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9199 20:14:58.141135 DRAM rank0 size:0x100000000,
9200 20:14:58.144170 DRAM rank1 size=0x100000000
9201 20:14:58.144277 CBMEM:
9202 20:14:58.147688 IMD: root @ 0xfffff000 254 entries.
9203 20:14:58.151159 IMD: root @ 0xffffec00 62 entries.
9204 20:14:58.154667 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9205 20:14:58.157350 WARNING: RO_VPD is uninitialized or empty.
9206 20:14:58.164258 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9207 20:14:58.171705 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9208 20:14:58.183895 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9209 20:14:58.195348 BS: romstage times (exec / console): total (unknown) / 23957 ms
9210 20:14:58.195480
9211 20:14:58.195599
9212 20:14:58.205158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9213 20:14:58.209092 ARM64: Exception handlers installed.
9214 20:14:58.212207 ARM64: Testing exception
9215 20:14:58.215340 ARM64: Done test exception
9216 20:14:58.215422 Enumerating buses...
9217 20:14:58.219119 Show all devs... Before device enumeration.
9218 20:14:58.222219 Root Device: enabled 1
9219 20:14:58.225326 CPU_CLUSTER: 0: enabled 1
9220 20:14:58.225409 CPU: 00: enabled 1
9221 20:14:58.228848 Compare with tree...
9222 20:14:58.228930 Root Device: enabled 1
9223 20:14:58.232204 CPU_CLUSTER: 0: enabled 1
9224 20:14:58.235741 CPU: 00: enabled 1
9225 20:14:58.235824 Root Device scanning...
9226 20:14:58.239086 scan_static_bus for Root Device
9227 20:14:58.242031 CPU_CLUSTER: 0 enabled
9228 20:14:58.245821 scan_static_bus for Root Device done
9229 20:14:58.248881 scan_bus: bus Root Device finished in 8 msecs
9230 20:14:58.248964 done
9231 20:14:58.255692 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9232 20:14:58.258793 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9233 20:14:58.265663 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9234 20:14:58.268780 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9235 20:14:58.272031 Allocating resources...
9236 20:14:58.272127 Reading resources...
9237 20:14:58.278974 Root Device read_resources bus 0 link: 0
9238 20:14:58.279056 DRAM rank0 size:0x100000000,
9239 20:14:58.281898 DRAM rank1 size=0x100000000
9240 20:14:58.285581 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9241 20:14:58.288762 CPU: 00 missing read_resources
9242 20:14:58.292415 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9243 20:14:58.298599 Root Device read_resources bus 0 link: 0 done
9244 20:14:58.298680 Done reading resources.
9245 20:14:58.305943 Show resources in subtree (Root Device)...After reading.
9246 20:14:58.309018 Root Device child on link 0 CPU_CLUSTER: 0
9247 20:14:58.312092 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 20:14:58.321902 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 20:14:58.321986 CPU: 00
9250 20:14:58.325606 Root Device assign_resources, bus 0 link: 0
9251 20:14:58.328571 CPU_CLUSTER: 0 missing set_resources
9252 20:14:58.332252 Root Device assign_resources, bus 0 link: 0 done
9253 20:14:58.335382 Done setting resources.
9254 20:14:58.342008 Show resources in subtree (Root Device)...After assigning values.
9255 20:14:58.345660 Root Device child on link 0 CPU_CLUSTER: 0
9256 20:14:58.348580 CPU_CLUSTER: 0 child on link 0 CPU: 00
9257 20:14:58.358843 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9258 20:14:58.358927 CPU: 00
9259 20:14:58.361805 Done allocating resources.
9260 20:14:58.365515 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9261 20:14:58.368484 Enabling resources...
9262 20:14:58.368589 done.
9263 20:14:58.372193 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9264 20:14:58.375348 Initializing devices...
9265 20:14:58.378463 Root Device init
9266 20:14:58.378543 init hardware done!
9267 20:14:58.382108 0x00000018: ctrlr->caps
9268 20:14:58.382261 52.000 MHz: ctrlr->f_max
9269 20:14:58.385103 0.400 MHz: ctrlr->f_min
9270 20:14:58.388548 0x40ff8080: ctrlr->voltages
9271 20:14:58.388631 sclk: 390625
9272 20:14:58.391722 Bus Width = 1
9273 20:14:58.391805 sclk: 390625
9274 20:14:58.391890 Bus Width = 1
9275 20:14:58.394884 Early init status = 3
9276 20:14:58.398194 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9277 20:14:58.403323 in-header: 03 fc 00 00 01 00 00 00
9278 20:14:58.406703 in-data: 00
9279 20:14:58.409719 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9280 20:14:58.415305 in-header: 03 fd 00 00 00 00 00 00
9281 20:14:58.418375 in-data:
9282 20:14:58.421566 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9283 20:14:58.425968 in-header: 03 fc 00 00 01 00 00 00
9284 20:14:58.429163 in-data: 00
9285 20:14:58.432283 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9286 20:14:58.437906 in-header: 03 fd 00 00 00 00 00 00
9287 20:14:58.441609 in-data:
9288 20:14:58.444659 [SSUSB] Setting up USB HOST controller...
9289 20:14:58.447645 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9290 20:14:58.451448 [SSUSB] phy power-on done.
9291 20:14:58.454628 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9292 20:14:58.461501 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9293 20:14:58.464833 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9294 20:14:58.471170 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9295 20:14:58.478086 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9296 20:14:58.484430 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9297 20:14:58.491069 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9298 20:14:58.497852 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9299 20:14:58.501482 SPM: binary array size = 0x9dc
9300 20:14:58.504803 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9301 20:14:58.511436 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9302 20:14:58.517884 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9303 20:14:58.521688 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9304 20:14:58.527637 configure_display: Starting display init
9305 20:14:58.561112 anx7625_power_on_init: Init interface.
9306 20:14:58.564631 anx7625_disable_pd_protocol: Disabled PD feature.
9307 20:14:58.567787 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9308 20:14:58.595694 anx7625_start_dp_work: Secure OCM version=00
9309 20:14:58.599393 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9310 20:14:58.613953 sp_tx_get_edid_block: EDID Block = 1
9311 20:14:58.716600 Extracted contents:
9312 20:14:58.719674 header: 00 ff ff ff ff ff ff 00
9313 20:14:58.722711 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9314 20:14:58.726493 version: 01 04
9315 20:14:58.729442 basic params: 95 1f 11 78 0a
9316 20:14:58.733222 chroma info: 76 90 94 55 54 90 27 21 50 54
9317 20:14:58.736311 established: 00 00 00
9318 20:14:58.743094 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9319 20:14:58.746267 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9320 20:14:58.753032 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9321 20:14:58.759492 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9322 20:14:58.766148 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9323 20:14:58.769199 extensions: 00
9324 20:14:58.769283 checksum: fb
9325 20:14:58.769366
9326 20:14:58.772343 Manufacturer: IVO Model 57d Serial Number 0
9327 20:14:58.775925 Made week 0 of 2020
9328 20:14:58.776028 EDID version: 1.4
9329 20:14:58.779381 Digital display
9330 20:14:58.782533 6 bits per primary color channel
9331 20:14:58.782618 DisplayPort interface
9332 20:14:58.786042 Maximum image size: 31 cm x 17 cm
9333 20:14:58.789287 Gamma: 220%
9334 20:14:58.789370 Check DPMS levels
9335 20:14:58.792427 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9336 20:14:58.798828 First detailed timing is preferred timing
9337 20:14:58.798913 Established timings supported:
9338 20:14:58.802365 Standard timings supported:
9339 20:14:58.805970 Detailed timings
9340 20:14:58.808970 Hex of detail: 383680a07038204018303c0035ae10000019
9341 20:14:58.812280 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9342 20:14:58.819077 0780 0798 07c8 0820 hborder 0
9343 20:14:58.822205 0438 043b 0447 0458 vborder 0
9344 20:14:58.825916 -hsync -vsync
9345 20:14:58.825999 Did detailed timing
9346 20:14:58.832083 Hex of detail: 000000000000000000000000000000000000
9347 20:14:58.835679 Manufacturer-specified data, tag 0
9348 20:14:58.839183 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9349 20:14:58.842258 ASCII string: InfoVision
9350 20:14:58.845419 Hex of detail: 000000fe00523134304e574635205248200a
9351 20:14:58.849242 ASCII string: R140NWF5 RH
9352 20:14:58.849325 Checksum
9353 20:14:58.852322 Checksum: 0xfb (valid)
9354 20:14:58.855530 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9355 20:14:58.859190 DSI data_rate: 832800000 bps
9356 20:14:58.865844 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9357 20:14:58.868984 anx7625_parse_edid: pixelclock(138800).
9358 20:14:58.872101 hactive(1920), hsync(48), hfp(24), hbp(88)
9359 20:14:58.875605 vactive(1080), vsync(12), vfp(3), vbp(17)
9360 20:14:58.878988 anx7625_dsi_config: config dsi.
9361 20:14:58.885804 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9362 20:14:58.898388 anx7625_dsi_config: success to config DSI
9363 20:14:58.902030 anx7625_dp_start: MIPI phy setup OK.
9364 20:14:58.905152 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9365 20:14:58.908072 mtk_ddp_mode_set invalid vrefresh 60
9366 20:14:58.911504 main_disp_path_setup
9367 20:14:58.911587 ovl_layer_smi_id_en
9368 20:14:58.914929 ovl_layer_smi_id_en
9369 20:14:58.915035 ccorr_config
9370 20:14:58.915126 aal_config
9371 20:14:58.918487 gamma_config
9372 20:14:58.918571 postmask_config
9373 20:14:58.921698 dither_config
9374 20:14:58.925101 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9375 20:14:58.931330 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9376 20:14:58.934507 Root Device init finished in 554 msecs
9377 20:14:58.938365 CPU_CLUSTER: 0 init
9378 20:14:58.945025 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9379 20:14:58.948138 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9380 20:14:58.951377 APU_MBOX 0x190000b0 = 0x10001
9381 20:14:58.955054 APU_MBOX 0x190001b0 = 0x10001
9382 20:14:58.958261 APU_MBOX 0x190005b0 = 0x10001
9383 20:14:58.961402 APU_MBOX 0x190006b0 = 0x10001
9384 20:14:58.964398 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9385 20:14:58.977064 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9386 20:14:58.989545 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9387 20:14:58.996538 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9388 20:14:59.008335 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9389 20:14:59.017364 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9390 20:14:59.020683 CPU_CLUSTER: 0 init finished in 81 msecs
9391 20:14:59.023754 Devices initialized
9392 20:14:59.027170 Show all devs... After init.
9393 20:14:59.027290 Root Device: enabled 1
9394 20:14:59.030340 CPU_CLUSTER: 0: enabled 1
9395 20:14:59.033788 CPU: 00: enabled 1
9396 20:14:59.037235 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9397 20:14:59.040315 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9398 20:14:59.043511 ELOG: NV offset 0x57f000 size 0x1000
9399 20:14:59.050580 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9400 20:14:59.056915 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9401 20:14:59.060582 ELOG: Event(17) added with size 13 at 2024-03-03 20:12:10 UTC
9402 20:14:59.063715 out: cmd=0x121: 03 db 21 01 00 00 00 00
9403 20:14:59.067453 in-header: 03 fe 00 00 2c 00 00 00
9404 20:14:59.080440 in-data: 61 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9405 20:14:59.087343 ELOG: Event(A1) added with size 10 at 2024-03-03 20:12:10 UTC
9406 20:14:59.093752 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9407 20:14:59.100798 ELOG: Event(A0) added with size 9 at 2024-03-03 20:12:10 UTC
9408 20:14:59.103922 elog_add_boot_reason: Logged dev mode boot
9409 20:14:59.107451 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9410 20:14:59.110479 Finalize devices...
9411 20:14:59.110601 Devices finalized
9412 20:14:59.117016 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9413 20:14:59.120780 Writing coreboot table at 0xffe64000
9414 20:14:59.123824 0. 000000000010a000-0000000000113fff: RAMSTAGE
9415 20:14:59.126910 1. 0000000040000000-00000000400fffff: RAM
9416 20:14:59.130454 2. 0000000040100000-000000004032afff: RAMSTAGE
9417 20:14:59.136949 3. 000000004032b000-00000000545fffff: RAM
9418 20:14:59.140575 4. 0000000054600000-000000005465ffff: BL31
9419 20:14:59.144004 5. 0000000054660000-00000000ffe63fff: RAM
9420 20:14:59.150244 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9421 20:14:59.153920 7. 0000000100000000-000000023fffffff: RAM
9422 20:14:59.154000 Passing 5 GPIOs to payload:
9423 20:14:59.160201 NAME | PORT | POLARITY | VALUE
9424 20:14:59.163917 EC in RW | 0x000000aa | low | undefined
9425 20:14:59.170206 EC interrupt | 0x00000005 | low | undefined
9426 20:14:59.173921 TPM interrupt | 0x000000ab | high | undefined
9427 20:14:59.177065 SD card detect | 0x00000011 | high | undefined
9428 20:14:59.183753 speaker enable | 0x00000093 | high | undefined
9429 20:14:59.186913 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9430 20:14:59.190271 in-header: 03 f9 00 00 02 00 00 00
9431 20:14:59.190393 in-data: 02 00
9432 20:14:59.193232 ADC[4]: Raw value=904357 ID=7
9433 20:14:59.196705 ADC[3]: Raw value=213810 ID=1
9434 20:14:59.200220 RAM Code: 0x71
9435 20:14:59.200370 ADC[6]: Raw value=75701 ID=0
9436 20:14:59.203254 ADC[5]: Raw value=213072 ID=1
9437 20:14:59.203338 SKU Code: 0x1
9438 20:14:59.210072 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5b3f
9439 20:14:59.213512 coreboot table: 964 bytes.
9440 20:14:59.216472 IMD ROOT 0. 0xfffff000 0x00001000
9441 20:14:59.220435 IMD SMALL 1. 0xffffe000 0x00001000
9442 20:14:59.223387 RO MCACHE 2. 0xffffc000 0x00001104
9443 20:14:59.227219 CONSOLE 3. 0xfff7c000 0x00080000
9444 20:14:59.230325 FMAP 4. 0xfff7b000 0x00000452
9445 20:14:59.233440 TIME STAMP 5. 0xfff7a000 0x00000910
9446 20:14:59.236564 VBOOT WORK 6. 0xfff66000 0x00014000
9447 20:14:59.240196 RAMOOPS 7. 0xffe66000 0x00100000
9448 20:14:59.243606 COREBOOT 8. 0xffe64000 0x00002000
9449 20:14:59.243691 IMD small region:
9450 20:14:59.246748 IMD ROOT 0. 0xffffec00 0x00000400
9451 20:14:59.250428 VPD 1. 0xffffeb80 0x0000006c
9452 20:14:59.253568 MMC STATUS 2. 0xffffeb60 0x00000004
9453 20:14:59.259742 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9454 20:14:59.263573 Probing TPM: done!
9455 20:14:59.266926 Connected to device vid:did:rid of 1ae0:0028:00
9456 20:14:59.276667 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9457 20:14:59.280188 Initialized TPM device CR50 revision 0
9458 20:14:59.283825 Checking cr50 for pending updates
9459 20:14:59.287592 Reading cr50 TPM mode
9460 20:14:59.295813 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9461 20:14:59.302076 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9462 20:14:59.342593 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9463 20:14:59.345655 Checking segment from ROM address 0x40100000
9464 20:14:59.349173 Checking segment from ROM address 0x4010001c
9465 20:14:59.355811 Loading segment from ROM address 0x40100000
9466 20:14:59.355892 code (compression=0)
9467 20:14:59.362293 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9468 20:14:59.372349 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9469 20:14:59.372431 it's not compressed!
9470 20:14:59.379150 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9471 20:14:59.382304 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9472 20:14:59.403026 Loading segment from ROM address 0x4010001c
9473 20:14:59.403111 Entry Point 0x80000000
9474 20:14:59.406206 Loaded segments
9475 20:14:59.409325 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9476 20:14:59.416232 Jumping to boot code at 0x80000000(0xffe64000)
9477 20:14:59.422968 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9478 20:14:59.429896 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9479 20:14:59.437049 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9480 20:14:59.440203 Checking segment from ROM address 0x40100000
9481 20:14:59.444115 Checking segment from ROM address 0x4010001c
9482 20:14:59.450532 Loading segment from ROM address 0x40100000
9483 20:14:59.450615 code (compression=1)
9484 20:14:59.457415 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9485 20:14:59.467051 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9486 20:14:59.467135 using LZMA
9487 20:14:59.475674 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9488 20:14:59.482305 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9489 20:14:59.485947 Loading segment from ROM address 0x4010001c
9490 20:14:59.486076 Entry Point 0x54601000
9491 20:14:59.488992 Loaded segments
9492 20:14:59.492048 NOTICE: MT8192 bl31_setup
9493 20:14:59.499081 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9494 20:14:59.502355 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9495 20:14:59.505948 WARNING: region 0:
9496 20:14:59.509089 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 20:14:59.509171 WARNING: region 1:
9498 20:14:59.515960 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9499 20:14:59.519539 WARNING: region 2:
9500 20:14:59.522600 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9501 20:14:59.525793 WARNING: region 3:
9502 20:14:59.529292 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 20:14:59.532758 WARNING: region 4:
9504 20:14:59.536011 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 20:14:59.539273 WARNING: region 5:
9506 20:14:59.542581 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 20:14:59.546229 WARNING: region 6:
9508 20:14:59.549404 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 20:14:59.549528 WARNING: region 7:
9510 20:14:59.556142 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 20:14:59.562817 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9512 20:14:59.565958 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9513 20:14:59.569020 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9514 20:14:59.576070 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9515 20:14:59.579141 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9516 20:14:59.582859 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9517 20:14:59.589334 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9518 20:14:59.592509 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9519 20:14:59.599352 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9520 20:14:59.602367 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9521 20:14:59.606322 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9522 20:14:59.612710 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9523 20:14:59.616410 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9524 20:14:59.619679 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9525 20:14:59.626413 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9526 20:14:59.629775 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9527 20:14:59.632627 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9528 20:14:59.639375 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9529 20:14:59.643093 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9530 20:14:59.645956 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9531 20:14:59.652976 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9532 20:14:59.655994 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9533 20:14:59.662835 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9534 20:14:59.666299 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9535 20:14:59.669855 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9536 20:14:59.676212 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9537 20:14:59.679287 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9538 20:14:59.686305 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9539 20:14:59.689426 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9540 20:14:59.692916 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9541 20:14:59.699405 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9542 20:14:59.703050 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9543 20:14:59.706353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9544 20:14:59.713277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9545 20:14:59.716320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9546 20:14:59.719855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9547 20:14:59.722906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9548 20:14:59.729627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9549 20:14:59.732724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9550 20:14:59.736391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9551 20:14:59.739568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9552 20:14:59.746367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9553 20:14:59.749537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9554 20:14:59.752698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9555 20:14:59.755954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9556 20:14:59.762985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9557 20:14:59.766335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9558 20:14:59.769501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9559 20:14:59.776455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9560 20:14:59.779828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9561 20:14:59.783023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9562 20:14:59.789901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9563 20:14:59.792898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9564 20:14:59.799704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9565 20:14:59.803089 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9566 20:14:59.809915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9567 20:14:59.812938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9568 20:14:59.816120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9569 20:14:59.822725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9570 20:14:59.826286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9571 20:14:59.832992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9572 20:14:59.836544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9573 20:14:59.842904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9574 20:14:59.846615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9575 20:14:59.849574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9576 20:14:59.856264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9577 20:14:59.859620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9578 20:14:59.866602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9579 20:14:59.869901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9580 20:14:59.876472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9581 20:14:59.879449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9582 20:14:59.882977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9583 20:14:59.889659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9584 20:14:59.893207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9585 20:14:59.900111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9586 20:14:59.903118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9587 20:14:59.909648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9588 20:14:59.913250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9589 20:14:59.919416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9590 20:14:59.923121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9591 20:14:59.926166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9592 20:14:59.933414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9593 20:14:59.936536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9594 20:14:59.943184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9595 20:14:59.946358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9596 20:14:59.949905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9597 20:14:59.956556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9598 20:14:59.959607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9599 20:14:59.966509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9600 20:14:59.969579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9601 20:14:59.976577 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9602 20:14:59.979533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9603 20:14:59.983180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9604 20:14:59.989898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9605 20:14:59.993506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9606 20:15:00.000267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9607 20:15:00.003079 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9608 20:15:00.006599 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9609 20:15:00.013426 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9610 20:15:00.016349 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9611 20:15:00.019773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9612 20:15:00.022938 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9613 20:15:00.029737 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9614 20:15:00.033471 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9615 20:15:00.040125 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9616 20:15:00.043332 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9617 20:15:00.046721 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9618 20:15:00.053202 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9619 20:15:00.056314 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9620 20:15:00.063045 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9621 20:15:00.066732 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9622 20:15:00.069869 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9623 20:15:00.076617 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9624 20:15:00.079760 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9625 20:15:00.086752 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9626 20:15:00.089825 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9627 20:15:00.093032 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9628 20:15:00.096874 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9629 20:15:00.103270 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9630 20:15:00.106467 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9631 20:15:00.109584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9632 20:15:00.113249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9633 20:15:00.120031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9634 20:15:00.123220 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9635 20:15:00.126845 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9636 20:15:00.133449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9637 20:15:00.136570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9638 20:15:00.143140 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9639 20:15:00.146871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9640 20:15:00.150053 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9641 20:15:00.156801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9642 20:15:00.159884 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9643 20:15:00.163568 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9644 20:15:00.169864 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9645 20:15:00.173621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9646 20:15:00.179937 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9647 20:15:00.183692 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9648 20:15:00.186658 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9649 20:15:00.193151 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9650 20:15:00.196785 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9651 20:15:00.203661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9652 20:15:00.207182 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9653 20:15:00.210108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9654 20:15:00.216999 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9655 20:15:00.220200 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9656 20:15:00.223333 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9657 20:15:00.230173 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9658 20:15:00.233672 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9659 20:15:00.240157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9660 20:15:00.243121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9661 20:15:00.246581 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9662 20:15:00.253212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9663 20:15:00.256866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9664 20:15:00.263584 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9665 20:15:00.267170 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9666 20:15:00.270214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9667 20:15:00.277167 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9668 20:15:00.280233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9669 20:15:00.283351 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9670 20:15:00.290124 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9671 20:15:00.293147 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9672 20:15:00.300346 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9673 20:15:00.303388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9674 20:15:00.306984 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9675 20:15:00.313289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9676 20:15:00.316849 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9677 20:15:00.323264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9678 20:15:00.326875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9679 20:15:00.330066 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9680 20:15:00.336900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9681 20:15:00.339969 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9682 20:15:00.346804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9683 20:15:00.349855 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9684 20:15:00.353318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9685 20:15:00.359958 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9686 20:15:00.363085 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9687 20:15:00.366593 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9688 20:15:00.373379 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9689 20:15:00.376416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9690 20:15:00.383178 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9691 20:15:00.386277 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9692 20:15:00.390133 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9693 20:15:00.396317 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9694 20:15:00.399984 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9695 20:15:00.406733 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9696 20:15:00.409836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9697 20:15:00.413032 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9698 20:15:00.420070 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9699 20:15:00.422955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9700 20:15:00.429714 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9701 20:15:00.432864 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9702 20:15:00.436526 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9703 20:15:00.442793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9704 20:15:00.446513 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9705 20:15:00.452859 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9706 20:15:00.456535 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9707 20:15:00.459591 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9708 20:15:00.466156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9709 20:15:00.469929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9710 20:15:00.476104 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9711 20:15:00.479854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9712 20:15:00.485973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9713 20:15:00.489430 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9714 20:15:00.492937 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9715 20:15:00.499730 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9716 20:15:00.502674 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9717 20:15:00.509516 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9718 20:15:00.512626 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9719 20:15:00.515850 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9720 20:15:00.523091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9721 20:15:00.525970 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9722 20:15:00.532921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9723 20:15:00.535927 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9724 20:15:00.542640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9725 20:15:00.545989 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9726 20:15:00.549126 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9727 20:15:00.556028 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9728 20:15:00.559184 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9729 20:15:00.566006 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9730 20:15:00.569633 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9731 20:15:00.572751 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9732 20:15:00.579347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9733 20:15:00.582418 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9734 20:15:00.589313 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9735 20:15:00.592472 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9736 20:15:00.599343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9737 20:15:00.602425 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9738 20:15:00.606201 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9739 20:15:00.613011 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9740 20:15:00.616012 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9741 20:15:00.619020 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9742 20:15:00.622455 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9743 20:15:00.628858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9744 20:15:00.632094 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9745 20:15:00.635836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9746 20:15:00.642219 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9747 20:15:00.645846 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9748 20:15:00.649020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9749 20:15:00.655617 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9750 20:15:00.658887 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9751 20:15:00.662457 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9752 20:15:00.668850 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9753 20:15:00.672483 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9754 20:15:00.675561 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9755 20:15:00.682267 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9756 20:15:00.685435 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9757 20:15:00.692233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9758 20:15:00.695452 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9759 20:15:00.699247 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9760 20:15:00.705318 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9761 20:15:00.709120 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9762 20:15:00.715341 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9763 20:15:00.718967 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9764 20:15:00.722197 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9765 20:15:00.728816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9766 20:15:00.731902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9767 20:15:00.735566 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9768 20:15:00.741888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9769 20:15:00.745311 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9770 20:15:00.748572 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9771 20:15:00.754997 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9772 20:15:00.758593 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9773 20:15:00.765499 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9774 20:15:00.768367 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9775 20:15:00.771875 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9776 20:15:00.778614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9777 20:15:00.782042 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9778 20:15:00.785336 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9779 20:15:00.791586 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9780 20:15:00.795058 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9781 20:15:00.798470 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9782 20:15:00.801525 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9783 20:15:00.805250 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9784 20:15:00.811700 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9785 20:15:00.814857 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9786 20:15:00.818136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9787 20:15:00.821712 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9788 20:15:00.828620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9789 20:15:00.831739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9790 20:15:00.835327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9791 20:15:00.841923 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9792 20:15:00.844991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9793 20:15:00.848196 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9794 20:15:00.855011 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9795 20:15:00.858348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9796 20:15:00.864681 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9797 20:15:00.867733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9798 20:15:00.871306 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9799 20:15:00.878186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9800 20:15:00.881438 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9801 20:15:00.888075 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9802 20:15:00.891105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9803 20:15:00.894493 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9804 20:15:00.901419 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9805 20:15:00.904221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9806 20:15:00.911009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9807 20:15:00.914326 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9808 20:15:00.917940 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9809 20:15:00.924485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9810 20:15:00.927972 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9811 20:15:00.934310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9812 20:15:00.937505 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9813 20:15:00.944098 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9814 20:15:00.947911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9815 20:15:00.951124 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9816 20:15:00.957958 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9817 20:15:00.961131 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9818 20:15:00.964257 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9819 20:15:00.970909 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9820 20:15:00.974245 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9821 20:15:00.981234 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9822 20:15:00.984481 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9823 20:15:00.990765 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9824 20:15:00.994376 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9825 20:15:00.997899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9826 20:15:01.004513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9827 20:15:01.007647 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9828 20:15:01.014417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9829 20:15:01.017411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9830 20:15:01.021059 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9831 20:15:01.027566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9832 20:15:01.030941 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9833 20:15:01.037878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9834 20:15:01.041065 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9835 20:15:01.044258 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9836 20:15:01.050774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9837 20:15:01.054318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9838 20:15:01.060617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9839 20:15:01.064220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9840 20:15:01.067408 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9841 20:15:01.074296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9842 20:15:01.077461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9843 20:15:01.084198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9844 20:15:01.087135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9845 20:15:01.094279 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9846 20:15:01.097565 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9847 20:15:01.100600 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9848 20:15:01.107548 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9849 20:15:01.110497 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9850 20:15:01.114246 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9851 20:15:01.120275 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9852 20:15:01.123940 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9853 20:15:01.130373 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9854 20:15:01.134046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9855 20:15:01.140850 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9856 20:15:01.143720 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9857 20:15:01.147078 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9858 20:15:01.153596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9859 20:15:01.156902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9860 20:15:01.163574 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9861 20:15:01.167206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9862 20:15:01.170228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9863 20:15:01.176709 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9864 20:15:01.180485 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9865 20:15:01.186859 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9866 20:15:01.190049 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9867 20:15:01.196862 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9868 20:15:01.200510 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9869 20:15:01.203587 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9870 20:15:01.210320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9871 20:15:01.213643 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9872 20:15:01.219961 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9873 20:15:01.223260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9874 20:15:01.230160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9875 20:15:01.233521 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9876 20:15:01.236612 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9877 20:15:01.243547 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9878 20:15:01.246798 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9879 20:15:01.253154 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9880 20:15:01.256839 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9881 20:15:01.263170 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9882 20:15:01.266853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9883 20:15:01.270015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9884 20:15:01.276563 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9885 20:15:01.280252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9886 20:15:01.286565 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9887 20:15:01.289749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9888 20:15:01.296606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9889 20:15:01.299718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9890 20:15:01.303334 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9891 20:15:01.309640 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9892 20:15:01.313110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9893 20:15:01.319933 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9894 20:15:01.323125 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9895 20:15:01.329855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9896 20:15:01.333146 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9897 20:15:01.336638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9898 20:15:01.342972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9899 20:15:01.346523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9900 20:15:01.353189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9901 20:15:01.356144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9902 20:15:01.362876 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9903 20:15:01.366048 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9904 20:15:01.373210 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9905 20:15:01.376404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9906 20:15:01.379604 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9907 20:15:01.386358 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9908 20:15:01.389233 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9909 20:15:01.396231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9910 20:15:01.399513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9911 20:15:01.406344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9912 20:15:01.409591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9913 20:15:01.412612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9914 20:15:01.419296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9915 20:15:01.422406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9916 20:15:01.429266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9917 20:15:01.432864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9918 20:15:01.439012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9919 20:15:01.442771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9920 20:15:01.448965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9921 20:15:01.452602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9922 20:15:01.458909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9923 20:15:01.462444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9924 20:15:01.468912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9925 20:15:01.472605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9926 20:15:01.475713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9927 20:15:01.482194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9928 20:15:01.485782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9929 20:15:01.492252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9930 20:15:01.496056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9931 20:15:01.502159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9932 20:15:01.505753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9933 20:15:01.512492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9934 20:15:01.515592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9935 20:15:01.522394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9936 20:15:01.525862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9937 20:15:01.532076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9938 20:15:01.535192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9939 20:15:01.542292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9940 20:15:01.545317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9941 20:15:01.551672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9942 20:15:01.555359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9943 20:15:01.561744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9944 20:15:01.565503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9945 20:15:01.571874 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9946 20:15:01.571955 INFO: [APUAPC] vio 0
9947 20:15:01.578759 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9948 20:15:01.582373 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9949 20:15:01.585872 INFO: [APUAPC] D0_APC_0: 0x400510
9950 20:15:01.589055 INFO: [APUAPC] D0_APC_1: 0x0
9951 20:15:01.592127 INFO: [APUAPC] D0_APC_2: 0x1540
9952 20:15:01.595566 INFO: [APUAPC] D0_APC_3: 0x0
9953 20:15:01.598761 INFO: [APUAPC] D1_APC_0: 0xffffffff
9954 20:15:01.602465 INFO: [APUAPC] D1_APC_1: 0xffffffff
9955 20:15:01.605401 INFO: [APUAPC] D1_APC_2: 0x3fffff
9956 20:15:01.608841 INFO: [APUAPC] D1_APC_3: 0x0
9957 20:15:01.611950 INFO: [APUAPC] D2_APC_0: 0xffffffff
9958 20:15:01.615237 INFO: [APUAPC] D2_APC_1: 0xffffffff
9959 20:15:01.619389 INFO: [APUAPC] D2_APC_2: 0x3fffff
9960 20:15:01.622423 INFO: [APUAPC] D2_APC_3: 0x0
9961 20:15:01.625602 INFO: [APUAPC] D3_APC_0: 0xffffffff
9962 20:15:01.628878 INFO: [APUAPC] D3_APC_1: 0xffffffff
9963 20:15:01.632076 INFO: [APUAPC] D3_APC_2: 0x3fffff
9964 20:15:01.632156 INFO: [APUAPC] D3_APC_3: 0x0
9965 20:15:01.635356 INFO: [APUAPC] D4_APC_0: 0xffffffff
9966 20:15:01.642452 INFO: [APUAPC] D4_APC_1: 0xffffffff
9967 20:15:01.645501 INFO: [APUAPC] D4_APC_2: 0x3fffff
9968 20:15:01.645582 INFO: [APUAPC] D4_APC_3: 0x0
9969 20:15:01.648799 INFO: [APUAPC] D5_APC_0: 0xffffffff
9970 20:15:01.651973 INFO: [APUAPC] D5_APC_1: 0xffffffff
9971 20:15:01.655895 INFO: [APUAPC] D5_APC_2: 0x3fffff
9972 20:15:01.658979 INFO: [APUAPC] D5_APC_3: 0x0
9973 20:15:01.661928 INFO: [APUAPC] D6_APC_0: 0xffffffff
9974 20:15:01.665077 INFO: [APUAPC] D6_APC_1: 0xffffffff
9975 20:15:01.668868 INFO: [APUAPC] D6_APC_2: 0x3fffff
9976 20:15:01.671909 INFO: [APUAPC] D6_APC_3: 0x0
9977 20:15:01.675095 INFO: [APUAPC] D7_APC_0: 0xffffffff
9978 20:15:01.678705 INFO: [APUAPC] D7_APC_1: 0xffffffff
9979 20:15:01.681736 INFO: [APUAPC] D7_APC_2: 0x3fffff
9980 20:15:01.685624 INFO: [APUAPC] D7_APC_3: 0x0
9981 20:15:01.688659 INFO: [APUAPC] D8_APC_0: 0xffffffff
9982 20:15:01.691609 INFO: [APUAPC] D8_APC_1: 0xffffffff
9983 20:15:01.695437 INFO: [APUAPC] D8_APC_2: 0x3fffff
9984 20:15:01.698508 INFO: [APUAPC] D8_APC_3: 0x0
9985 20:15:01.702252 INFO: [APUAPC] D9_APC_0: 0xffffffff
9986 20:15:01.705256 INFO: [APUAPC] D9_APC_1: 0xffffffff
9987 20:15:01.708322 INFO: [APUAPC] D9_APC_2: 0x3fffff
9988 20:15:01.712084 INFO: [APUAPC] D9_APC_3: 0x0
9989 20:15:01.715077 INFO: [APUAPC] D10_APC_0: 0xffffffff
9990 20:15:01.718581 INFO: [APUAPC] D10_APC_1: 0xffffffff
9991 20:15:01.721927 INFO: [APUAPC] D10_APC_2: 0x3fffff
9992 20:15:01.724927 INFO: [APUAPC] D10_APC_3: 0x0
9993 20:15:01.728268 INFO: [APUAPC] D11_APC_0: 0xffffffff
9994 20:15:01.731810 INFO: [APUAPC] D11_APC_1: 0xffffffff
9995 20:15:01.735098 INFO: [APUAPC] D11_APC_2: 0x3fffff
9996 20:15:01.738352 INFO: [APUAPC] D11_APC_3: 0x0
9997 20:15:01.741417 INFO: [APUAPC] D12_APC_0: 0xffffffff
9998 20:15:01.744904 INFO: [APUAPC] D12_APC_1: 0xffffffff
9999 20:15:01.748436 INFO: [APUAPC] D12_APC_2: 0x3fffff
10000 20:15:01.751425 INFO: [APUAPC] D12_APC_3: 0x0
10001 20:15:01.755167 INFO: [APUAPC] D13_APC_0: 0xffffffff
10002 20:15:01.758289 INFO: [APUAPC] D13_APC_1: 0xffffffff
10003 20:15:01.761239 INFO: [APUAPC] D13_APC_2: 0x3fffff
10004 20:15:01.764828 INFO: [APUAPC] D13_APC_3: 0x0
10005 20:15:01.768241 INFO: [APUAPC] D14_APC_0: 0xffffffff
10006 20:15:01.771425 INFO: [APUAPC] D14_APC_1: 0xffffffff
10007 20:15:01.775012 INFO: [APUAPC] D14_APC_2: 0x3fffff
10008 20:15:01.778144 INFO: [APUAPC] D14_APC_3: 0x0
10009 20:15:01.781282 INFO: [APUAPC] D15_APC_0: 0xffffffff
10010 20:15:01.785010 INFO: [APUAPC] D15_APC_1: 0xffffffff
10011 20:15:01.788119 INFO: [APUAPC] D15_APC_2: 0x3fffff
10012 20:15:01.791244 INFO: [APUAPC] D15_APC_3: 0x0
10013 20:15:01.794842 INFO: [APUAPC] APC_CON: 0x4
10014 20:15:01.797972 INFO: [NOCDAPC] D0_APC_0: 0x0
10015 20:15:01.801709 INFO: [NOCDAPC] D0_APC_1: 0x0
10016 20:15:01.804846 INFO: [NOCDAPC] D1_APC_0: 0x0
10017 20:15:01.807868 INFO: [NOCDAPC] D1_APC_1: 0xfff
10018 20:15:01.807988 INFO: [NOCDAPC] D2_APC_0: 0x0
10019 20:15:01.811584 INFO: [NOCDAPC] D2_APC_1: 0xfff
10020 20:15:01.814803 INFO: [NOCDAPC] D3_APC_0: 0x0
10021 20:15:01.817967 INFO: [NOCDAPC] D3_APC_1: 0xfff
10022 20:15:01.821540 INFO: [NOCDAPC] D4_APC_0: 0x0
10023 20:15:01.824728 INFO: [NOCDAPC] D4_APC_1: 0xfff
10024 20:15:01.827696 INFO: [NOCDAPC] D5_APC_0: 0x0
10025 20:15:01.831029 INFO: [NOCDAPC] D5_APC_1: 0xfff
10026 20:15:01.834462 INFO: [NOCDAPC] D6_APC_0: 0x0
10027 20:15:01.838081 INFO: [NOCDAPC] D6_APC_1: 0xfff
10028 20:15:01.841226 INFO: [NOCDAPC] D7_APC_0: 0x0
10029 20:15:01.844182 INFO: [NOCDAPC] D7_APC_1: 0xfff
10030 20:15:01.844264 INFO: [NOCDAPC] D8_APC_0: 0x0
10031 20:15:01.847864 INFO: [NOCDAPC] D8_APC_1: 0xfff
10032 20:15:01.851025 INFO: [NOCDAPC] D9_APC_0: 0x0
10033 20:15:01.854309 INFO: [NOCDAPC] D9_APC_1: 0xfff
10034 20:15:01.857456 INFO: [NOCDAPC] D10_APC_0: 0x0
10035 20:15:01.861038 INFO: [NOCDAPC] D10_APC_1: 0xfff
10036 20:15:01.864238 INFO: [NOCDAPC] D11_APC_0: 0x0
10037 20:15:01.867356 INFO: [NOCDAPC] D11_APC_1: 0xfff
10038 20:15:01.870704 INFO: [NOCDAPC] D12_APC_0: 0x0
10039 20:15:01.874056 INFO: [NOCDAPC] D12_APC_1: 0xfff
10040 20:15:01.877285 INFO: [NOCDAPC] D13_APC_0: 0x0
10041 20:15:01.880685 INFO: [NOCDAPC] D13_APC_1: 0xfff
10042 20:15:01.884231 INFO: [NOCDAPC] D14_APC_0: 0x0
10043 20:15:01.887181 INFO: [NOCDAPC] D14_APC_1: 0xfff
10044 20:15:01.887262 INFO: [NOCDAPC] D15_APC_0: 0x0
10045 20:15:01.890964 INFO: [NOCDAPC] D15_APC_1: 0xfff
10046 20:15:01.894156 INFO: [NOCDAPC] APC_CON: 0x4
10047 20:15:01.897201 INFO: [APUAPC] set_apusys_apc done
10048 20:15:01.900734 INFO: [DEVAPC] devapc_init done
10049 20:15:01.904218 INFO: GICv3 without legacy support detected.
10050 20:15:01.910515 INFO: ARM GICv3 driver initialized in EL3
10051 20:15:01.914281 INFO: Maximum SPI INTID supported: 639
10052 20:15:01.917601 INFO: BL31: Initializing runtime services
10053 20:15:01.923939 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10054 20:15:01.927199 INFO: SPM: enable CPC mode
10055 20:15:01.930950 INFO: mcdi ready for mcusys-off-idle and system suspend
10056 20:15:01.934124 INFO: BL31: Preparing for EL3 exit to normal world
10057 20:15:01.940267 INFO: Entry point address = 0x80000000
10058 20:15:01.940374 INFO: SPSR = 0x8
10059 20:15:01.947077
10060 20:15:01.947157
10061 20:15:01.947219
10062 20:15:01.950140 Starting depthcharge on Spherion...
10063 20:15:01.950220
10064 20:15:01.950308 Wipe memory regions:
10065 20:15:01.950383
10066 20:15:01.951047 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10067 20:15:01.951151 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10068 20:15:01.951234 Setting prompt string to ['asurada:']
10069 20:15:01.951316 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10070 20:15:01.953774 [0x00000040000000, 0x00000054600000)
10071 20:15:02.075786
10072 20:15:02.075935 [0x00000054660000, 0x00000080000000)
10073 20:15:02.336523
10074 20:15:02.336716 [0x000000821a7280, 0x000000ffe64000)
10075 20:15:03.081701
10076 20:15:03.081950 [0x00000100000000, 0x00000240000000)
10077 20:15:04.971740
10078 20:15:04.974826 Initializing XHCI USB controller at 0x11200000.
10079 20:15:06.013638
10080 20:15:06.017179 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10081 20:15:06.017264
10082 20:15:06.017329
10083 20:15:06.017389
10084 20:15:06.017693 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 20:15:06.118045 asurada: tftpboot 192.168.201.1 12928080/tftp-deploy-c59hqd2v/kernel/image.itb 12928080/tftp-deploy-c59hqd2v/kernel/cmdline
10087 20:15:06.118161 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 20:15:06.118240 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 20:15:06.122584 tftpboot 192.168.201.1 12928080/tftp-deploy-c59hqd2v/kernel/image.ittp-deploy-c59hqd2v/kernel/cmdline
10090 20:15:06.122667
10091 20:15:06.122731 Waiting for link
10092 20:15:06.283120
10093 20:15:06.283257 R8152: Initializing
10094 20:15:06.283340
10095 20:15:06.286290 Version 9 (ocp_data = 6010)
10096 20:15:06.286373
10097 20:15:06.290048 R8152: Done initializing
10098 20:15:06.290131
10099 20:15:06.290197 Adding net device
10100 20:15:08.162443
10101 20:15:08.162599 done.
10102 20:15:08.162666
10103 20:15:08.162727 MAC: 00:e0:4c:78:7a:aa
10104 20:15:08.162785
10105 20:15:08.165430 Sending DHCP discover... done.
10106 20:15:08.165559
10107 20:15:08.168828 Waiting for reply... done.
10108 20:15:08.168951
10109 20:15:08.172010 Sending DHCP request... done.
10110 20:15:08.172130
10111 20:15:08.177654 Waiting for reply... done.
10112 20:15:08.177777
10113 20:15:08.177888 My ip is 192.168.201.12
10114 20:15:08.177994
10115 20:15:08.181069 The DHCP server ip is 192.168.201.1
10116 20:15:08.181186
10117 20:15:08.187707 TFTP server IP predefined by user: 192.168.201.1
10118 20:15:08.187832
10119 20:15:08.194428 Bootfile predefined by user: 12928080/tftp-deploy-c59hqd2v/kernel/image.itb
10120 20:15:08.194549
10121 20:15:08.194663 Sending tftp read request... done.
10122 20:15:08.197775
10123 20:15:08.200941 Waiting for the transfer...
10124 20:15:08.201055
10125 20:15:08.490061 00000000 ################################################################
10126 20:15:08.490220
10127 20:15:08.753111 00080000 ################################################################
10128 20:15:08.753259
10129 20:15:09.045947 00100000 ################################################################
10130 20:15:09.046109
10131 20:15:09.325827 00180000 ################################################################
10132 20:15:09.325972
10133 20:15:09.607733 00200000 ################################################################
10134 20:15:09.607896
10135 20:15:09.905818 00280000 ################################################################
10136 20:15:09.905978
10137 20:15:10.171389 00300000 ################################################################
10138 20:15:10.171528
10139 20:15:10.436511 00380000 ################################################################
10140 20:15:10.436704
10141 20:15:10.698330 00400000 ################################################################
10142 20:15:10.698510
10143 20:15:10.951627 00480000 ################################################################
10144 20:15:10.951794
10145 20:15:11.222231 00500000 ################################################################
10146 20:15:11.222425
10147 20:15:11.479219 00580000 ################################################################
10148 20:15:11.479355
10149 20:15:11.733910 00600000 ################################################################
10150 20:15:11.734062
10151 20:15:11.988442 00680000 ################################################################
10152 20:15:11.988605
10153 20:15:12.255981 00700000 ################################################################
10154 20:15:12.256166
10155 20:15:12.516058 00780000 ################################################################
10156 20:15:12.516201
10157 20:15:12.772025 00800000 ################################################################
10158 20:15:12.772194
10159 20:15:13.035830 00880000 ################################################################
10160 20:15:13.035973
10161 20:15:13.295943 00900000 ################################################################
10162 20:15:13.296109
10163 20:15:13.571643 00980000 ################################################################
10164 20:15:13.571774
10165 20:15:13.827849 00a00000 ################################################################
10166 20:15:13.828018
10167 20:15:14.095443 00a80000 ################################################################
10168 20:15:14.095578
10169 20:15:14.359810 00b00000 ################################################################
10170 20:15:14.359951
10171 20:15:14.618108 00b80000 ################################################################
10172 20:15:14.618324
10173 20:15:14.887976 00c00000 ################################################################
10174 20:15:14.888153
10175 20:15:15.170050 00c80000 ################################################################
10176 20:15:15.170223
10177 20:15:15.461732 00d00000 ################################################################
10178 20:15:15.461873
10179 20:15:15.734043 00d80000 ################################################################
10180 20:15:15.734193
10181 20:15:15.989222 00e00000 ################################################################
10182 20:15:15.989378
10183 20:15:16.241119 00e80000 ################################################################
10184 20:15:16.241268
10185 20:15:16.490972 00f00000 ################################################################
10186 20:15:16.491147
10187 20:15:16.750408 00f80000 ################################################################
10188 20:15:16.750602
10189 20:15:17.033661 01000000 ################################################################
10190 20:15:17.033858
10191 20:15:17.303977 01080000 ################################################################
10192 20:15:17.304117
10193 20:15:17.584307 01100000 ################################################################
10194 20:15:17.584439
10195 20:15:17.855762 01180000 ################################################################
10196 20:15:17.855903
10197 20:15:18.112246 01200000 ################################################################
10198 20:15:18.112479
10199 20:15:18.366166 01280000 ################################################################
10200 20:15:18.366361
10201 20:15:18.623129 01300000 ################################################################
10202 20:15:18.623280
10203 20:15:18.879687 01380000 ################################################################
10204 20:15:18.879821
10205 20:15:19.133746 01400000 ################################################################
10206 20:15:19.133912
10207 20:15:19.389134 01480000 ################################################################
10208 20:15:19.389343
10209 20:15:19.660522 01500000 ################################################################
10210 20:15:19.660664
10211 20:15:19.909512 01580000 ################################################################
10212 20:15:19.909645
10213 20:15:20.186531 01600000 ################################################################
10214 20:15:20.186668
10215 20:15:20.452781 01680000 ################################################################
10216 20:15:20.452919
10217 20:15:20.713779 01700000 ################################################################
10218 20:15:20.713947
10219 20:15:20.975639 01780000 ################################################################
10220 20:15:20.975840
10221 20:15:21.239018 01800000 ################################################################
10222 20:15:21.239183
10223 20:15:21.500923 01880000 ################################################################
10224 20:15:21.501090
10225 20:15:21.762264 01900000 ################################################################
10226 20:15:21.762425
10227 20:15:22.025027 01980000 ################################################################
10228 20:15:22.025223
10229 20:15:22.308962 01a00000 ################################################################
10230 20:15:22.309103
10231 20:15:22.588344 01a80000 ################################################################
10232 20:15:22.588504
10233 20:15:22.849656 01b00000 ################################################################
10234 20:15:22.849797
10235 20:15:23.116396 01b80000 ################################################################
10236 20:15:23.116534
10237 20:15:23.391351 01c00000 ################################################################
10238 20:15:23.391492
10239 20:15:23.405581 01c80000 #### done.
10240 20:15:23.405672
10241 20:15:23.408597 The bootfile was 29912810 bytes long.
10242 20:15:23.408684
10243 20:15:23.412269 Sending tftp read request... done.
10244 20:15:23.412376
10245 20:15:23.414978 Waiting for the transfer...
10246 20:15:23.415089
10247 20:15:23.415195 00000000 # done.
10248 20:15:23.415301
10249 20:15:23.424966 Command line loaded dynamically from TFTP file: 12928080/tftp-deploy-c59hqd2v/kernel/cmdline
10250 20:15:23.425055
10251 20:15:23.445187 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10252 20:15:23.445284
10253 20:15:23.448200 Loading FIT.
10254 20:15:23.448317
10255 20:15:23.451888 Image ramdisk-1 has 17803460 bytes.
10256 20:15:23.452004
10257 20:15:23.455095 Image fdt-1 has 47278 bytes.
10258 20:15:23.455182
10259 20:15:23.455286 Image kernel-1 has 12060038 bytes.
10260 20:15:23.458656
10261 20:15:23.465255 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10262 20:15:23.465343
10263 20:15:23.481785 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10264 20:15:23.485164
10265 20:15:23.488505 Choosing best match conf-1 for compat google,spherion-rev2.
10266 20:15:23.492940
10267 20:15:23.497732 Connected to device vid:did:rid of 1ae0:0028:00
10268 20:15:23.505160
10269 20:15:23.508789 tpm_get_response: command 0x17b, return code 0x0
10270 20:15:23.508877
10271 20:15:23.511905 ec_init: CrosEC protocol v3 supported (256, 248)
10272 20:15:23.516105
10273 20:15:23.519735 tpm_cleanup: add release locality here.
10274 20:15:23.519823
10275 20:15:23.519910 Shutting down all USB controllers.
10276 20:15:23.522884
10277 20:15:23.522970 Removing current net device
10278 20:15:23.523058
10279 20:15:23.530057 Exiting depthcharge with code 4 at timestamp: 50823828
10280 20:15:23.530144
10281 20:15:23.532873 LZMA decompressing kernel-1 to 0x821a6718
10282 20:15:23.532960
10283 20:15:23.536220 LZMA decompressing kernel-1 to 0x40000000
10284 20:15:25.035719
10285 20:15:25.035863 jumping to kernel
10286 20:15:25.036461 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10287 20:15:25.036573 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10288 20:15:25.036666 Setting prompt string to ['Linux version [0-9]']
10289 20:15:25.036753 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10290 20:15:25.036841 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10291 20:15:25.117765
10292 20:15:25.120887 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10293 20:15:25.124696 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10294 20:15:25.124835 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10295 20:15:25.124920 Setting prompt string to []
10296 20:15:25.125023 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10297 20:15:25.125112 Using line separator: #'\n'#
10298 20:15:25.125186 No login prompt set.
10299 20:15:25.125266 Parsing kernel messages
10300 20:15:25.125360 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10301 20:15:25.125546 [login-action] Waiting for messages, (timeout 00:04:02)
10302 20:15:25.125649 Waiting using forced prompt support (timeout 00:02:01)
10303 20:15:25.144089 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10304 20:15:25.147504 [ 0.000000] random: crng init done
10305 20:15:25.154172 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10306 20:15:25.157336 [ 0.000000] efi: UEFI not found.
10307 20:15:25.164159 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10308 20:15:25.173753 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10309 20:15:25.183762 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10310 20:15:25.190520 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10311 20:15:25.197156 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10312 20:15:25.203655 [ 0.000000] printk: bootconsole [mtk8250] enabled
10313 20:15:25.210244 [ 0.000000] NUMA: No NUMA configuration found
10314 20:15:25.216907 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10315 20:15:25.223782 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10316 20:15:25.223868 [ 0.000000] Zone ranges:
10317 20:15:25.230197 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10318 20:15:25.233759 [ 0.000000] DMA32 empty
10319 20:15:25.240634 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10320 20:15:25.243607 [ 0.000000] Movable zone start for each node
10321 20:15:25.247133 [ 0.000000] Early memory node ranges
10322 20:15:25.253859 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10323 20:15:25.260344 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10324 20:15:25.266672 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10325 20:15:25.273469 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10326 20:15:25.280165 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10327 20:15:25.286926 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10328 20:15:25.343062 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10329 20:15:25.349222 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10330 20:15:25.356258 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10331 20:15:25.359545 [ 0.000000] psci: probing for conduit method from DT.
10332 20:15:25.366302 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10333 20:15:25.369433 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10334 20:15:25.375801 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10335 20:15:25.379471 [ 0.000000] psci: SMC Calling Convention v1.2
10336 20:15:25.385811 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10337 20:15:25.388975 [ 0.000000] Detected VIPT I-cache on CPU0
10338 20:15:25.396106 [ 0.000000] CPU features: detected: GIC system register CPU interface
10339 20:15:25.402538 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10340 20:15:25.409124 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10341 20:15:25.415873 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10342 20:15:25.422070 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10343 20:15:25.432539 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10344 20:15:25.435709 [ 0.000000] alternatives: applying boot alternatives
10345 20:15:25.441803 [ 0.000000] Fallback order for Node 0: 0
10346 20:15:25.448802 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10347 20:15:25.452006 [ 0.000000] Policy zone: Normal
10348 20:15:25.475272 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10349 20:15:25.485222 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10350 20:15:25.494905 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10351 20:15:25.505258 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10352 20:15:25.511777 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10353 20:15:25.514933 <6>[ 0.000000] software IO TLB: area num 8.
10354 20:15:25.570828 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10355 20:15:25.719892 <6>[ 0.000000] Memory: 7949808K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 402960K reserved, 32768K cma-reserved)
10356 20:15:25.726911 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10357 20:15:25.733169 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10358 20:15:25.736534 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10359 20:15:25.743250 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10360 20:15:25.749989 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10361 20:15:25.753192 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10362 20:15:25.763158 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10363 20:15:25.769936 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10364 20:15:25.776729 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10365 20:15:25.783453 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10366 20:15:25.786431 <6>[ 0.000000] GICv3: 608 SPIs implemented
10367 20:15:25.789924 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10368 20:15:25.796507 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10369 20:15:25.799524 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10370 20:15:25.806102 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10371 20:15:25.819509 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10372 20:15:25.829816 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10373 20:15:25.839640 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10374 20:15:25.846883 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10375 20:15:25.859932 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10376 20:15:25.866874 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10377 20:15:25.873699 <6>[ 0.009185] Console: colour dummy device 80x25
10378 20:15:25.883575 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10379 20:15:25.886717 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10380 20:15:25.893439 <6>[ 0.029227] LSM: Security Framework initializing
10381 20:15:25.900097 <6>[ 0.034195] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 20:15:25.909941 <6>[ 0.042009] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10383 20:15:25.916868 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10384 20:15:25.923130 <6>[ 0.058957] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 20:15:25.933318 <6>[ 0.065298] cblist_init_generic: Setting adjustable number of callback queues.
10386 20:15:25.939735 <6>[ 0.072771] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 20:15:25.942853 <6>[ 0.079239] rcu: Hierarchical SRCU implementation.
10388 20:15:25.949958 <6>[ 0.079241] rcu: Max phase no-delay instances is 1000.
10389 20:15:25.956172 <6>[ 0.079266] printk: bootconsole [mtk8250] printing thread started
10390 20:15:25.962781 <6>[ 0.097605] EFI services will not be available.
10391 20:15:25.966124 <6>[ 0.097808] smp: Bringing up secondary CPUs ...
10392 20:15:25.969560 <6>[ 0.098115] Detected VIPT I-cache on CPU1
10393 20:15:25.979563 <6>[ 0.098182] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10394 20:15:25.985994 <6>[ 0.098213] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10395 20:15:25.995144 <6>[ 0.126064] Detected VIPT I-cache on CPU2
10396 20:15:26.001878 <6>[ 0.126110] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10397 20:15:26.012279 <6>[ 0.126124] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10398 20:15:26.015415 <6>[ 0.126385] Detected VIPT I-cache on CPU3
10399 20:15:26.021775 <6>[ 0.126432] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10400 20:15:26.028668 <6>[ 0.126445] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10401 20:15:26.031634 <6>[ 0.126757] CPU features: detected: Spectre-v4
10402 20:15:26.038300 <6>[ 0.126762] CPU features: detected: Spectre-BHB
10403 20:15:26.041987 <6>[ 0.126768] Detected PIPT I-cache on CPU4
10404 20:15:26.048016 <6>[ 0.126825] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10405 20:15:26.054779 <6>[ 0.126843] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10406 20:15:26.061445 <6>[ 0.127137] Detected PIPT I-cache on CPU5
10407 20:15:26.068062 <6>[ 0.127196] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10408 20:15:26.074938 <6>[ 0.127212] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10409 20:15:26.077944 <6>[ 0.127488] Detected PIPT I-cache on CPU6
10410 20:15:26.084791 <6>[ 0.127551] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10411 20:15:26.091359 <6>[ 0.127567] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10412 20:15:26.098181 <6>[ 0.127862] Detected PIPT I-cache on CPU7
10413 20:15:26.104452 <6>[ 0.127925] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10414 20:15:26.111416 <6>[ 0.127941] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10415 20:15:26.114559 <6>[ 0.127988] smp: Brought up 1 node, 8 CPUs
10416 20:15:26.121374 <6>[ 0.127993] SMP: Total of 8 processors activated.
10417 20:15:26.124860 <6>[ 0.127996] CPU features: detected: 32-bit EL0 Support
10418 20:15:26.134309 <6>[ 0.127998] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10419 20:15:26.141272 <6>[ 0.128000] CPU features: detected: Common not Private translations
10420 20:15:26.147935 <6>[ 0.128002] CPU features: detected: CRC32 instructions
10421 20:15:26.151413 <6>[ 0.128005] CPU features: detected: RCpc load-acquire (LDAPR)
10422 20:15:26.157934 <6>[ 0.128006] CPU features: detected: LSE atomic instructions
10423 20:15:26.164582 <6>[ 0.128008] CPU features: detected: Privileged Access Never
10424 20:15:26.171206 <6>[ 0.128009] CPU features: detected: RAS Extension Support
10425 20:15:26.177834 <6>[ 0.128012] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10426 20:15:26.180940 <6>[ 0.128080] CPU: All CPU(s) started at EL2
10427 20:15:26.209322 ��������,�,Z5��}��չѕ�5R�<6>[ 0.344<439] printk: console [ttyS0] printing thread started
10428 20:15:26.212587 5<6>[ 0.344467] printk: console [ttyS0] enabled
10429 20:15:26.219490 >[ 0.225590] VFS: Disk quotas dquot_6.6.0
10430 20:15:26.226103 <6>[ 0.344471] printk: bootconsole [mtk8250] disabled
10431 20:15:26.232501 <6>[ 0.358896] printk: bootconsole [mtk8250] printing thread stopped
10432 20:15:26.236044 <6>[ 0.359915] SuperH (H)SCI(F) driver initialized
10433 20:15:26.242929 <6>[ 0.360384] msm_serial: driver initialized
10434 20:15:26.249414 <6>[ 0.364911] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10435 20:15:26.258974 <6>[ 0.364940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10436 20:15:26.265712 <6>[ 0.364969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10437 20:15:26.281900 <6>[ 0.364998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10438 20:15:26.289346 <6>[ 0.365020] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10439 20:15:26.294526 <6>[ 0.365047] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10440 20:15:26.312968 <6>[ 0.365075] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10441 20:15:26.313337 <6>[ 0.365188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10442 20:15:26.325052 <6>[ 0.365217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10443 20:15:26.325139 <6>[ 0.376427] loop: module loaded
10444 20:15:26.331794 <6>[ 0.379014] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10445 20:15:26.338810 <4>[ 0.395874] mtk-pmic-keys: Failed to locate of_node [id: -1]
10446 20:15:26.338894 <6>[ 0.396690] megasas: 07.719.03.00-rc1
10447 20:15:26.345304 <6>[ 0.408916] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10448 20:15:26.348892 <6>[ 0.409061] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10449 20:15:26.355386 <6>[ 0.421177] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10450 20:15:26.368460 <6>[ 0.475164] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10451 20:15:26.841626 <6>[ 0.973810] Freeing initrd memory: 17380K
10452 20:15:26.848470 <6>[ 0.980045] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10453 20:15:26.851467 <6>[ 0.984639] tun: Universal TUN/TAP device driver, 1.6
10454 20:15:26.855195 <6>[ 0.985378] thunder_xcv, ver 1.0
10455 20:15:26.858333 <6>[ 0.985395] thunder_bgx, ver 1.0
10456 20:15:26.861523 <6>[ 0.985408] nicpf, ver 1.0
10457 20:15:26.868089 <6>[ 0.986458] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10458 20:15:26.874918 <6>[ 0.986461] hns3: Copyright (c) 2017 Huawei Corporation.
10459 20:15:26.878758 <6>[ 0.986485] hclge is initializing
10460 20:15:26.885302 <6>[ 0.986499] e1000: Intel(R) PRO/1000 Network Driver
10461 20:15:26.888652 <6>[ 0.986501] e1000: Copyright (c) 1999-2006 Intel Corporation.
10462 20:15:26.895983 <6>[ 0.986519] e1000e: Intel(R) PRO/1000 Network Driver
10463 20:15:26.903821 <6>[ 0.986520] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10464 20:15:26.906850 <6>[ 0.986540] igb: Intel(R) Gigabit Ethernet Network Driver
10465 20:15:26.913313 <6>[ 0.986542] igb: Copyright (c) 2007-2014 Intel Corporation.
10466 20:15:26.921120 <6>[ 0.986556] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10467 20:15:26.923767 <6>[ 0.986558] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10468 20:15:26.930571 <6>[ 0.986844] sky2: driver version 1.30
10469 20:15:26.933899 <6>[ 0.987902] VFIO - User Level meta-driver version: 0.3
10470 20:15:26.940689 <6>[ 0.990722] usbcore: registered new interface driver usb-storage
10471 20:15:26.947540 <6>[ 0.990900] usbcore: registered new device driver onboard-usb-hub
10472 20:15:26.953853 <6>[ 0.993660] mt6397-rtc mt6359-rtc: registered as rtc0
10473 20:15:26.960775 <6>[ 0.993813] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:12:38 UTC (1709496758)
10474 20:15:26.967481 <6>[ 0.994432] i2c_dev: i2c /dev entries driver
10475 20:15:26.974133 <6>[ 1.001526] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10476 20:15:26.977175 <6>[ 1.016505] cpu cpu0: EM: created perf domain
10477 20:15:26.983977 <6>[ 1.016829] cpu cpu4: EM: created perf domain
10478 20:15:26.990768 <6>[ 1.019949] sdhci: Secure Digital Host Controller Interface driver
10479 20:15:26.993579 <6>[ 1.019951] sdhci: Copyright(c) Pierre Ossman
10480 20:15:27.000154 <6>[ 1.020301] Synopsys Designware Multimedia Card Interface Driver
10481 20:15:27.007210 <6>[ 1.020696] sdhci-pltfm: SDHCI platform and OF driver helper
10482 20:15:27.013680 <6>[ 1.024949] ledtrig-cpu: registered to indicate activity on CPUs
10483 20:15:27.017349 <6>[ 1.025657] mmc0: CQHCI version 5.10
10484 20:15:27.024083 <6>[ 1.025691] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10485 20:15:27.030612 <6>[ 1.025964] usbcore: registered new interface driver usbhid
10486 20:15:27.033542 <6>[ 1.025967] usbhid: USB HID core driver
10487 20:15:27.040222 <6>[ 1.026078] spi_master spi0: will run message pump with realtime priority
10488 20:15:27.053993 <6>[ 1.055976] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10489 20:15:27.066992 <6>[ 1.058646] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10490 20:15:27.074046 <6>[ 1.059745] cros-ec-spi spi0.0: Chrome EC device registered
10491 20:15:27.080720 <6>[ 1.071786] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10492 20:15:27.086894 <6>[ 1.072733] NET: Registered PF_PACKET protocol family
10493 20:15:27.090708 <6>[ 1.072800] 9pnet: Installing 9P2000 support
10494 20:15:27.096905 <5>[ 1.072838] Key type dns_resolver registered
10495 20:15:27.100438 <6>[ 1.073134] registered taskstats version 1
10496 20:15:27.103803 <5>[ 1.073147] Loading compiled-in X.509 certificates
10497 20:15:27.117117 <4>[ 1.089411] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10498 20:15:27.127095 <4>[ 1.089628] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10499 20:15:27.133877 <3>[ 1.089638] debugfs: File 'uA_load' in directory '/' already present!
10500 20:15:27.140744 <3>[ 1.089645] debugfs: File 'min_uV' in directory '/' already present!
10501 20:15:27.147232 <3>[ 1.089648] debugfs: File 'max_uV' in directory '/' already present!
10502 20:15:27.153789 <3>[ 1.089651] debugfs: File 'constraint_flags' in directory '/' already present!
10503 20:15:27.160425 <3>[ 1.092120] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10504 20:15:27.167322 <6>[ 1.100683] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10505 20:15:27.173902 <6>[ 1.101276] xhci-mtk 11200000.usb: xHCI Host Controller
10506 20:15:27.180742 <6>[ 1.101292] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10507 20:15:27.190719 <6>[ 1.101495] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10508 20:15:27.197378 <6>[ 1.101542] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10509 20:15:27.204087 <6>[ 1.101648] xhci-mtk 11200000.usb: xHCI Host Controller
10510 20:15:27.210604 <6>[ 1.101655] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10511 20:15:27.217156 <6>[ 1.101662] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10512 20:15:27.220246 <6>[ 1.102125] hub 1-0:1.0: USB hub found
10513 20:15:27.223754 <6>[ 1.102152] hub 1-0:1.0: 1 port detected
10514 20:15:27.234357 <6>[ 1.102377] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10515 20:15:27.237336 <6>[ 1.102665] hub 2-0:1.0: USB hub found
10516 20:15:27.240774 <6>[ 1.102686] hub 2-0:1.0: 1 port detected
10517 20:15:27.246912 <6>[ 1.105731] mtk-msdc 11f70000.mmc: Got CD GPIO
10518 20:15:27.253566 <6>[ 1.120668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10519 20:15:27.263748 <6>[ 1.120676] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10520 20:15:27.270214 <4>[ 1.120902] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10521 20:15:27.280010 <6>[ 1.121577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10522 20:15:27.286706 <6>[ 1.121581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10523 20:15:27.297305 <6>[ 1.121792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10524 20:15:27.303675 <6>[ 1.121804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10525 20:15:27.310046 <6>[ 1.121808] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10526 20:15:27.320020 <6>[ 1.121813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10527 20:15:27.326552 <6>[ 1.123352] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10528 20:15:27.336434 <6>[ 1.123369] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10529 20:15:27.346849 <6>[ 1.123375] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10530 20:15:27.353286 <6>[ 1.123380] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10531 20:15:27.363016 <6>[ 1.123385] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10532 20:15:27.369725 <6>[ 1.123390] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10533 20:15:27.380051 <6>[ 1.123395] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10534 20:15:27.386897 <6>[ 1.123401] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10535 20:15:27.396162 <6>[ 1.123406] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10536 20:15:27.402688 <6>[ 1.123411] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10537 20:15:27.412918 <6>[ 1.123416] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10538 20:15:27.419863 <6>[ 1.123421] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10539 20:15:27.429600 <6>[ 1.123426] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10540 20:15:27.436396 <6>[ 1.123432] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10541 20:15:27.445985 <6>[ 1.123437] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10542 20:15:27.452811 <6>[ 1.123940] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10543 20:15:27.456184 <6>[ 1.124411] mmc0: Command Queue Engine enabled
10544 20:15:27.462814 <6>[ 1.124420] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10545 20:15:27.469325 <6>[ 1.124945] mmcblk0: mmc0:0001 DA4128 116 GiB
10546 20:15:27.472416 <6>[ 1.126232] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10547 20:15:27.479169 <6>[ 1.126869] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10548 20:15:27.486141 <6>[ 1.127179] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10549 20:15:27.492624 <6>[ 1.127441] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10550 20:15:27.502196 <6>[ 1.127607] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10551 20:15:27.512732 <6>[ 1.127621] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10552 20:15:27.522506 <6>[ 1.127623] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10553 20:15:27.532206 <6>[ 1.127628] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10554 20:15:27.539225 <6>[ 1.127631] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10555 20:15:27.549214 <6>[ 1.127635] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10556 20:15:27.559018 <6>[ 1.127639] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10557 20:15:27.568767 <6>[ 1.127641] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10558 20:15:27.578629 <6>[ 1.127644] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10559 20:15:27.588651 <6>[ 1.127650] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10560 20:15:27.598402 <6>[ 1.127654] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10561 20:15:27.605189 <6>[ 1.128278] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10562 20:15:27.611722 <6>[ 1.128820] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10563 20:15:27.618418 <6>[ 1.129977] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10564 20:15:27.621851 <6>[ 1.130561] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10565 20:15:27.628386 <6>[ 1.131075] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10566 20:15:27.634915 <6>[ 1.140702] Trying to probe devices needed for running init ...
10567 20:15:27.641817 <6>[ 1.489866] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10568 20:15:27.645019 <6>[ 1.520294] hub 2-1:1.0: USB hub found
10569 20:15:27.651459 <6>[ 1.520586] hub 2-1:1.0: 3 ports detected
10570 20:15:27.654725 <6>[ 1.522283] hub 2-1:1.0: USB hub found
10571 20:15:27.658393 <6>[ 1.522585] hub 2-1:1.0: 3 ports detected
10572 20:15:27.664830 <6>[ 1.645638] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10573 20:15:27.668247 <6>[ 1.802276] hub 1-1:1.0: USB hub found
10574 20:15:27.674990 <6>[ 1.802660] hub 1-1:1.0: 4 ports detected
10575 20:15:27.677800 <6>[ 1.805630] hub 1-1:1.0: USB hub found
10576 20:15:27.681380 <6>[ 1.806040] hub 1-1:1.0: 4 ports detected
10577 20:15:27.753211 <6>[ 1.882013] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10578 20:15:27.989038 <6>[ 2.117789] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10579 20:15:28.113408 <6>[ 2.245770] hub 1-1.4:1.0: USB hub found
10580 20:15:28.116964 <6>[ 2.246231] hub 1-1.4:1.0: 2 ports detected
10581 20:15:28.120558 <6>[ 2.249790] hub 1-1.4:1.0: USB hub found
10582 20:15:28.126984 <6>[ 2.250120] hub 1-1.4:1.0: 2 ports detected
10583 20:15:28.409134 <6>[ 2.537760] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10584 20:15:28.592707 <6>[ 2.721758] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10585 20:15:39.273082 <6>[ 13.410839] ALSA device list:
10586 20:15:39.279595 <6>[ 13.410861] No soundcards found.
10587 20:15:39.283149 <6>[ 13.415227] Freeing unused kernel memory: 8448K
10588 20:15:39.286656 <6>[ 13.415382] Run /init as init process
10589 20:15:39.289637 Loading, please wait...
10590 20:15:39.310579 Starting version 247.3-7+deb11u4
10591 20:15:39.504069 <6>[ 13.635584] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10592 20:15:39.510442 <6>[ 13.635699] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10593 20:15:39.520637 <6>[ 13.635705] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10594 20:15:39.531808 <6>[ 13.664972] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10595 20:15:39.534905 <6>[ 13.669304] remoteproc remoteproc0: scp is available
10596 20:15:39.541938 <6>[ 13.669400] remoteproc remoteproc0: powering up scp
10597 20:15:39.548309 <6>[ 13.669404] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10598 20:15:39.554942 <6>[ 13.669434] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10599 20:15:39.575274 <3>[ 13.705590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 20:15:39.582025 <3>[ 13.705623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10601 20:15:39.592321 <3>[ 13.705633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 20:15:39.598467 <4>[ 13.711791] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10603 20:15:39.608535 <3>[ 13.712033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10604 20:15:39.615188 <3>[ 13.712053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10605 20:15:39.623110 <3>[ 13.712057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10606 20:15:39.632841 <3>[ 13.712062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 20:15:39.639295 <3>[ 13.712066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10608 20:15:39.645969 <4>[ 13.715345] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10609 20:15:39.653209 <6>[ 13.715512] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10610 20:15:39.663504 <3>[ 13.725489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 20:15:39.670147 <3>[ 13.738656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 20:15:39.679834 <3>[ 13.738736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 20:15:39.686461 <3>[ 13.738746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 20:15:39.690069 <6>[ 13.739355] mc: Linux media interface: v0.10
10615 20:15:39.699758 <3>[ 13.741212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 20:15:39.706166 <3>[ 13.741232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10617 20:15:39.716411 <3>[ 13.741235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10618 20:15:39.723007 <3>[ 13.741242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10619 20:15:39.732736 <3>[ 13.741246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10620 20:15:39.739302 <3>[ 13.741632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10621 20:15:39.745819 <6>[ 13.743450] usbcore: registered new device driver r8152-cfgselector
10622 20:15:39.755992 <4>[ 13.744227] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10623 20:15:39.759312 <4>[ 13.744227] Fallback method does not support PEC.
10624 20:15:39.765848 <6>[ 13.761724] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10625 20:15:39.772496 <6>[ 13.761743] pci_bus 0000:00: root bus resource [bus 00-ff]
10626 20:15:39.779236 <6>[ 13.761749] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10627 20:15:39.789198 <6>[ 13.761752] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10628 20:15:39.795994 <6>[ 13.761796] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10629 20:15:39.802540 <6>[ 13.761812] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10630 20:15:39.809204 <6>[ 13.761887] pci 0000:00:00.0: supports D1 D2
10631 20:15:39.815826 <6>[ 13.761890] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10632 20:15:39.821928 <3>[ 13.762968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 20:15:39.828783 <6>[ 13.763557] videodev: Linux video capture interface: v2.00
10634 20:15:39.838613 <6>[ 13.764951] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10635 20:15:39.842051 <6>[ 13.768373] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10636 20:15:39.851908 <6>[ 13.768423] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10637 20:15:39.858671 <6>[ 13.768446] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10638 20:15:39.864965 <6>[ 13.768466] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10639 20:15:39.871648 <6>[ 13.768593] pci 0000:01:00.0: supports D1 D2
10640 20:15:39.878560 <6>[ 13.768596] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10641 20:15:39.885266 <6>[ 13.785877] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10642 20:15:39.891934 <6>[ 13.785974] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10643 20:15:39.898684 <6>[ 13.785981] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10644 20:15:39.908692 <6>[ 13.785994] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10645 20:15:39.914818 <6>[ 13.786010] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10646 20:15:39.924882 <6>[ 13.786027] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10647 20:15:39.928569 <6>[ 13.786045] pci 0000:00:00.0: PCI bridge to [bus 01]
10648 20:15:39.938642 <6>[ 13.786058] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10649 20:15:39.944895 <6>[ 13.787376] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10650 20:15:39.948448 <6>[ 13.792923] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10651 20:15:39.955050 <6>[ 13.793716] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10652 20:15:39.964732 <6>[ 13.794769] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10653 20:15:39.971443 <6>[ 13.794788] remoteproc remoteproc0: remote processor scp is now up
10654 20:15:39.978166 <6>[ 13.794789] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10655 20:15:39.984564 <3>[ 13.798489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 20:15:39.994944 <6>[ 13.814951] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10657 20:15:40.001265 <6>[ 13.817865] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10658 20:15:40.011380 <6>[ 13.824014] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10659 20:15:40.021408 <6>[ 13.858005] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10660 20:15:40.031535 <6>[ 13.875237] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10661 20:15:40.037755 <6>[ 13.875624] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10662 20:15:40.047675 <4>[ 13.884016] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10663 20:15:40.057669 <4>[ 13.884034] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10664 20:15:40.064362 <5>[ 13.907600] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10665 20:15:40.070933 <5>[ 13.920730] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10666 20:15:40.081366 <5>[ 13.920967] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10667 20:15:40.087433 <4>[ 13.921026] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10668 20:15:40.094106 <6>[ 13.921034] cfg80211: failed to load regulatory.db
10669 20:15:40.097781 <6>[ 13.922528] Bluetooth: Core ver 2.22
10670 20:15:40.104263 <6>[ 13.922662] NET: Registered PF_BLUETOOTH protocol family
10671 20:15:40.110891 <6>[ 13.922673] Bluetooth: HCI device and connection manager initialized
10672 20:15:40.113787 <6>[ 13.922722] Bluetooth: HCI socket layer initialized
10673 20:15:40.120892 <6>[ 13.922742] Bluetooth: L2CAP socket layer initialized
10674 20:15:40.123900 <6>[ 13.922757] Bluetooth: SCO socket layer initialized
10675 20:15:40.130487 <6>[ 13.937629] r8152 2-1.3:1.0 eth0: v1.12.13
10676 20:15:40.133916 <6>[ 13.937721] usbcore: registered new interface driver r8152
10677 20:15:40.143503 <6>[ 13.951792] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10678 20:15:40.154306 <6>[ 13.953095] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10679 20:15:40.160277 <6>[ 13.953311] usbcore: registered new interface driver uvcvideo
10680 20:15:40.166838 <6>[ 13.966292] usbcore: registered new interface driver cdc_ether
10681 20:15:40.173536 <6>[ 13.980013] usbcore: registered new interface driver r8153_ecm
10682 20:15:40.176783 <6>[ 13.986657] usbcore: registered new interface driver btusb
10683 20:15:40.190651 <4>[ 13.987773] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10684 20:15:40.193487 <3>[ 13.987820] Bluetooth: hci0: Failed to load firmware file (-2)
10685 20:15:40.200146 <3>[ 13.987836] Bluetooth: hci0: Failed to set up firmware (-2)
10686 20:15:40.210178 <4>[ 13.987848] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10687 20:15:40.216722 <6>[ 13.994674] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10688 20:15:40.223115 <6>[ 14.001908] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10689 20:15:40.229918 <6>[ 14.014747] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10690 20:15:40.236930 <6>[ 14.014848] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10691 20:15:40.243421 <6>[ 14.033651] mt7921e 0000:01:00.0: ASIC revision: 79610010
10692 20:15:40.253212 <6>[ 14.128338] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10693 20:15:40.253336 <6>[ 14.128338]
10694 20:15:40.262997 <6>[ 14.388142] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10695 20:15:40.266593 Begin: Loading essential drivers ... done.
10696 20:15:40.269619 Begin: Running /scripts/init-premount ... done.
10697 20:15:40.276215 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10698 20:15:40.286206 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10699 20:15:40.289787 Device /sys/class/net/enx00e04c787aaa found
10700 20:15:40.289912 done.
10701 20:15:40.351376 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10702 20:15:41.095993 <6>[ 15.231093] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10703 20:15:41.356201 IP-Config: no response after 2 secs - giving up
10704 20:15:41.371973 <6>[ 15.507507] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10705 20:15:41.424270 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10706 20:15:42.151139 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10707 20:15:42.157845 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10708 20:15:42.164300 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10709 20:15:42.170962 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10710 20:15:42.177724 host : mt8192-asurada-spherion-r0-cbg-0
10711 20:15:42.184461 domain : lava-rack
10712 20:15:42.187508 rootserver: 192.168.201.1 rootpath:
10713 20:15:42.187614 filename :
10714 20:15:42.321306 done.
10715 20:15:42.324551 Begin: Running /scripts/nfs-bottom ... done.
10716 20:15:42.349235 Begin: Running /scripts/init-bottom ... done.
10717 20:15:43.497096 <6>[ 17.631073] NET: Registered PF_INET6 protocol family
10718 20:15:43.500653 <6>[ 17.633235] Segment Routing with IPv6
10719 20:15:43.507135 <6>[ 17.633261] In-situ OAM (IOAM) with IPv6
10720 20:15:43.619943 <30>[ 17.733612] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10721 20:15:43.622921 <30>[ 17.734507] systemd[1]: Detected architecture arm64.
10722 20:15:43.633106
10723 20:15:43.636081 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10724 20:15:43.636162
10725 20:15:43.655875 <30>[ 17.791875] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10726 20:15:44.371060 <30>[ 18.502357] systemd[1]: Queued start job for default target Graphical Interface.
10727 20:15:44.398295 [[0;32m OK [<30>[ 18.532250] systemd[1]: Created slice system-getty.slice.
10728 20:15:44.401133 0m] Created slice [0;1;39msystem-getty.slice[0m.
10729 20:15:44.421167 [[0;32m OK [0m] Created slic<30>[ 18.555031] systemd[1]: Created slice system-modprobe.slice.
10730 20:15:44.423932 e [0;1;39msystem-modprobe.slice[0m.
10731 20:15:44.444724 [[0;32m OK [0m] Created slic<30>[ 18.578946] systemd[1]: Created slice system-serial\x2dgetty.slice.
10732 20:15:44.451095 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10733 20:15:44.469687 [[0;32m OK [0m] Created slic<30>[ 18.603664] systemd[1]: Created slice User and Session Slice.
10734 20:15:44.472955 e [0;1;39mUser and Session Slice[0m.
10735 20:15:44.495973 [[0;32m OK [0m] Started [0;<30>[ 18.626726] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10736 20:15:44.499301 1;39mDispatch Password …ts to Console Directory Watch[0m.
10737 20:15:44.523110 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.653984] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10738 20:15:44.525858 sword R…uests to Wall Directory Watch[0m.
10739 20:15:44.550384 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.677935] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10740 20:15:44.557052 <30>[ 18.678113] systemd[1]: Reached target Local Encrypted Volumes.
10741 20:15:44.560553 l Encrypted Volumes[0m.
10742 20:15:44.579407 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.713952] systemd[1]: Reached target Paths.
10743 20:15:44.579551 s[0m.
10744 20:15:44.602987 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.733963] systemd[1]: Reached target Remote File Systems.
10745 20:15:44.603154 te File Systems[0m.
10746 20:15:44.623252 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 18.757729] systemd[1]: Reached target Slices.
10747 20:15:44.623447 es[0m.
10748 20:15:44.643398 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 18.777785] systemd[1]: Reached target Swap.
10749 20:15:44.643595 [0m.
10750 20:15:44.666958 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 18.798152] systemd[1]: Listening on initctl Compatibility Named Pipe.
10751 20:15:44.670208 l Compatibility Named Pipe[0m.
10752 20:15:44.680538 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 18.814146] systemd[1]: Listening on Journal Audit Socket.
10753 20:15:44.683732 l Audit Socket[0m.
10754 20:15:44.704336 [[0;32m OK [0m] Listening on<30>[ 18.838894] systemd[1]: Listening on Journal Socket (/dev/log).
10755 20:15:44.708043 [0;1;39mJournal Socket (/dev/log)[0m.
10756 20:15:44.728694 [[0;32m OK [0m] Listening on<30>[ 18.863057] systemd[1]: Listening on Journal Socket.
10757 20:15:44.732079 [0;1;39mJournal Socket[0m.
10758 20:15:44.748759 [[0;32m OK [0m] Listening on<30>[ 18.883369] systemd[1]: Listening on Network Service Netlink Socket.
10759 20:15:44.755259 [0;1;39mNetwork Service Netlink Socket[0m.
10760 20:15:44.775044 [[0;32m OK [<30>[ 18.909047] systemd[1]: Listening on udev Control Socket.
10761 20:15:44.777890 0m] Listening on [0;1;39mudev Control Socket[0m.
10762 20:15:44.795476 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 18.930205] systemd[1]: Listening on udev Kernel Socket.
10763 20:15:44.798811 ernel Socket[0m.
10764 20:15:44.854935 Mounting [0;1;39mHuge Pages File Syste<30>[ 18.986175] systemd[1]: Mounting Huge Pages File System...
10765 20:15:44.855141 m[0m...
10766 20:15:44.874008 Mounting [0;1;39mPOSIX<30>[ 19.008078] systemd[1]: Mounting POSIX Message Queue File System...
10767 20:15:44.877342 Message Queue File System[0m...
10768 20:15:44.898357 Mountin<30>[ 19.032773] systemd[1]: Mounting Kernel Debug File System...
10769 20:15:44.901793 g [0;1;39mKernel Debug File System[0m...
10770 20:15:44.923050 <30>[ 19.054241] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10771 20:15:44.936362 Starting [0;1;39mCreat<30>[ 19.067134] systemd[1]: Starting Create list of static device nodes for the current kernel...
10772 20:15:44.939897 e list of st…odes for the current kernel[0m...
10773 20:15:44.967229 Starting [0;1;39mLoad Kernel Module co<30>[ 19.098159] systemd[1]: Starting Load Kernel Module configfs...
10774 20:15:44.967400 nfigfs[0m...
10775 20:15:44.988163 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.122461] systemd[1]: Starting Load Kernel Module drm...
10776 20:15:44.991598 m[0m...
10777 20:15:45.012587 Starting [0;1;39mLoad <30>[ 19.146739] systemd[1]: Starting Load Kernel Module fuse...
10778 20:15:45.016017 Kernel Module fuse[0m...
10779 20:15:45.047987 <6>[ 19.181992] fuse: init (API version 7.37)
10780 20:15:45.057631 <30>[ 19.182816] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10781 20:15:45.068208 Starting [0;1;39mJournal Service[0m..<30>[ 19.202525] systemd[1]: Starting Journal Service...
10782 20:15:45.068366 .
10783 20:15:45.121266 Starting [0;1;39mLoad <30>[ 19.255272] systemd[1]: Starting Load Kernel Modules...
10784 20:15:45.124266 Kernel Modules[0m...
10785 20:15:45.146249 Startin<30>[ 19.280629] systemd[1]: Starting Remount Root and Kernel File Systems...
10786 20:15:45.152806 g [0;1;39mRemount Root and Kernel File Systems[0m...
10787 20:15:45.174855 Startin<30>[ 19.308689] systemd[1]: Starting Coldplug All udev Devices...
10788 20:15:45.177898 g [0;1;39mColdplug All udev Devices[0m...
10789 20:15:45.190789 <3>[ 19.322809] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 20:15:45.208950 [[0;32m OK [0m] Mounted [0;<30>[ 19.343257] systemd[1]: Mounted Huge Pages File System.
10791 20:15:45.212263 1;39mHuge Pages File System[0m.
10792 20:15:45.227060 <3>[ 19.361084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10793 20:15:45.236842 [[0;32m OK [0m] Mounted [0;<30>[ 19.371158] systemd[1]: Mounted POSIX Message Queue File System.
10794 20:15:45.240092 1;39mPOSIX Message Queue File System[0m.
10795 20:15:45.260570 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.394259] systemd[1]: Mounted Kernel Debug File System.
10796 20:15:45.270939 g File System[0<3>[ 19.401458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10797 20:15:45.271093 m.
10798 20:15:45.299617 [[0;32m OK [0m] Finished [0;1;39mCreate lis<30>[ 19.430518] systemd[1]: Finished Create list of static device nodes for the current kernel.
10799 20:15:45.302990 t of st… nodes for the current kernel[0m.
10800 20:15:45.315038 <3>[ 19.447989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 20:15:45.330689 [[0;32m OK [<30>[ 19.463536] systemd[1]: modprobe@configfs.service: Succeeded.
10802 20:15:45.337191 0m] Finished [0<30>[ 19.464513] systemd[1]: Finished Load Kernel Module configfs.
10803 20:15:45.347313 ;1;39mLoad Kerne<3>[ 19.468356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10804 20:15:45.350332 l Module configfs[0m.
10805 20:15:45.366809 <3>[ 19.498069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 20:15:45.379273 [[0;32m OK [<30>[ 19.511787] systemd[1]: modprobe@drm.service: Succeeded.
10807 20:15:45.385539 0m] Finished [0<30>[ 19.512883] systemd[1]: Finished Load Kernel Module drm.
10808 20:15:45.385664 ;1;39mLoad Kernel Module drm[0m.
10809 20:15:45.398879 <3>[ 19.531906] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 20:15:45.412300 [[0;32m OK [<30>[ 19.547748] systemd[1]: modprobe@fuse.service: Succeeded.
10811 20:15:45.422012 0m] Finished [0<30>[ 19.548905] systemd[1]: Finished Load Kernel Module fuse.
10812 20:15:45.428349 <3>[ 19.552106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10813 20:15:45.431979 ;1;39mLoad Kernel Module fuse[0m.
10814 20:15:45.447047 <3>[ 19.581125] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 20:15:45.457433 [[0;32m OK [0m] Finished [0<30>[ 19.591433] systemd[1]: Finished Load Kernel Modules.
10816 20:15:45.460602 ;1;39mLoad Kernel Modules[0m.
10817 20:15:45.471166 <3>[ 19.603458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 20:15:45.481941 [[0;32m OK [0m] Finished [0<30>[ 19.615196] systemd[1]: Finished Remount Root and Kernel File Systems.
10819 20:15:45.485330 ;1;39mRemount Root and Kernel File Systems[0m.
10820 20:15:45.537003 [[0;32m OK [0m] Started [0;<30>[ 19.671457] systemd[1]: Started Journal Service.
10821 20:15:45.540078 1;39mJournal Service[0m.
10822 20:15:45.561210 Mounting [0;1;39mFUSE Control File System[0m...
10823 20:15:45.585495 Mounting [0;1;39mKernel Configuration File System[0m...
10824 20:15:45.613483 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10825 20:15:45.636886 Starting [0;1;39mLoad/Save Random Seed[0m...
10826 20:15:45.651017 <46>[ 19.784703] systemd-journald[306]: Received client request to flush runtime journal.
10827 20:15:45.667141 Starting [0;1;39mApply Kernel Variables[0m...
10828 20:15:45.693677 <4>[ 19.819481] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10829 20:15:45.703676 <3>[ 19.819497] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10830 20:15:45.800579 Starting [0;1;39mCreate System Users[0m...
10831 20:15:45.826173 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10832 20:15:45.839932 See 'systemctl status systemd-udev-trigger.service' for details.
10833 20:15:45.856746 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10834 20:15:45.872500 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10835 20:15:45.889487 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10836 20:15:46.759310 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10837 20:15:47.080190 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10838 20:15:47.095425 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10839 20:15:47.136749 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10840 20:15:47.201010 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10841 20:15:47.216230 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10842 20:15:47.231719 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10843 20:15:47.292661 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10844 20:15:47.319460 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10845 20:15:47.469559 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10846 20:15:47.509290 Starting [0;1;39mNetwork Service[0m...
10847 20:15:47.553879 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10848 20:15:47.643053 Starting [0;1;39mNetwork Time Synchronization[0m...
10849 20:15:47.670566 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10850 20:15:47.820529 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10851 20:15:47.847074 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10852 20:15:47.908937 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10853 20:15:48.219264 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10854 20:15:48.239873 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10855 20:15:48.262532 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10856 20:15:48.276904 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10857 20:15:48.295908 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10858 20:15:48.380684 Starting [0;1;39mNetwork Name Resolution[0m...
10859 20:15:48.400337 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10860 20:15:48.422515 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10861 20:15:48.440883 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10862 20:15:48.456481 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10863 20:15:48.475365 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10864 20:15:48.488061 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10865 20:15:48.503780 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10866 20:15:48.523257 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10867 20:15:48.551624 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10868 20:15:48.573819 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10869 20:15:49.112569 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10870 20:15:49.123208 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10871 20:15:49.296542 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10872 20:15:49.307853 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10873 20:15:49.323708 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10874 20:15:49.372721 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10875 20:15:49.723840 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10876 20:15:49.876538 Starting [0;1;39mUser Login Management[0m...
10877 20:15:50.309350 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10878 20:15:50.342777 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10879 20:15:50.357039 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10880 20:15:50.378791 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10881 20:15:50.420294 Starting [0;1;39mPermit User Sessions[0m...
10882 20:15:50.436552 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10883 20:15:50.453965 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10884 20:15:50.494598 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10885 20:15:50.516175 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10886 20:15:50.534406 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10887 20:15:50.549493 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10888 20:15:50.565486 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10889 20:15:50.606216 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10890 20:15:50.656121 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10891 20:15:50.728665
10892 20:15:50.728827
10893 20:15:50.731654 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10894 20:15:50.731742
10895 20:15:50.734996 debian-bullseye-arm64 login: root (automatic login)
10896 20:15:50.735087
10897 20:15:50.735206
10898 20:15:51.062651 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10899 20:15:51.062839
10900 20:15:51.069277 The programs included with the Debian GNU/Linux system are free software;
10901 20:15:51.075887 the exact distribution terms for each program are described in the
10902 20:15:51.079398 individual files in /usr/share/doc/*/copyright.
10903 20:15:51.079501
10904 20:15:51.085885 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10905 20:15:51.089103 permitted by applicable law.
10906 20:15:51.833170 Matched prompt #10: / #
10908 20:15:51.833494 Setting prompt string to ['/ #']
10909 20:15:51.833610 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10911 20:15:51.833838 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10912 20:15:51.833941 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10913 20:15:51.834018 Setting prompt string to ['/ #']
10914 20:15:51.834116 Forcing a shell prompt, looking for ['/ #']
10916 20:15:51.884378 / #
10917 20:15:51.884617 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10918 20:15:51.884728 Waiting using forced prompt support (timeout 00:02:30)
10919 20:15:51.889780
10920 20:15:51.890070 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10921 20:15:51.890176 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10923 20:15:51.990618 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo'
10924 20:15:51.995979 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928080/extract-nfsrootfs-x12fwpwo'
10926 20:15:52.096595 / # export NFS_SERVER_IP='192.168.201.1'
10927 20:15:52.101786 export NFS_SERVER_IP='192.168.201.1'
10928 20:15:52.102126 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10929 20:15:52.102245 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
10930 20:15:52.102380 end: 2 depthcharge-action (duration 00:01:25) [common]
10931 20:15:52.102516 start: 3 lava-test-retry (timeout 00:07:49) [common]
10932 20:15:52.102644 start: 3.1 lava-test-shell (timeout 00:07:49) [common]
10933 20:15:52.102762 Using namespace: common
10935 20:15:52.203188 / # #
10936 20:15:52.203380 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10937 20:15:52.208677 #
10938 20:15:52.208956 Using /lava-12928080
10940 20:15:52.309359 / # export SHELL=/bin/bash
10941 20:15:52.314332 export SHELL=/bin/bash
10943 20:15:52.414905 / # . /lava-12928080/environment
10944 20:15:52.421040 . /lava-12928080/environment
10946 20:15:52.525934 / # /lava-12928080/bin/lava-test-runner /lava-12928080/0
10947 20:15:52.526115 Test shell timeout: 10s (minimum of the action and connection timeout)
10948 20:15:52.531530 /lava-12928080/bin/lava-test-runner /lava-12928080/0
10949 20:15:52.749019 + export TESTRUN_ID=0_timesync-off
10950 20:15:52.752037 + TESTRUN_ID=0_timesync-off
10951 20:15:52.755449 + cd /lava-12928080/0/tests/0_timesync-off
10952 20:15:52.758888 ++ cat uuid
10953 20:15:52.758992 + UUID=12928080_1.6.2.3.1
10954 20:15:52.762436 + set +x
10955 20:15:52.765494 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12928080_1.6.2.3.1>
10956 20:15:52.765775 Received signal: <STARTRUN> 0_timesync-off 12928080_1.6.2.3.1
10957 20:15:52.765867 Starting test lava.0_timesync-off (12928080_1.6.2.3.1)
10958 20:15:52.765985 Skipping test definition patterns.
10959 20:15:52.768480 + systemctl stop systemd-timesyncd
10960 20:15:52.815804 + set +x
10961 20:15:52.818860 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12928080_1.6.2.3.1>
10962 20:15:52.819150 Received signal: <ENDRUN> 0_timesync-off 12928080_1.6.2.3.1
10963 20:15:52.819263 Ending use of test pattern.
10964 20:15:52.819354 Ending test lava.0_timesync-off (12928080_1.6.2.3.1), duration 0.05
10966 20:15:52.867601 + export TESTRUN_ID=1_kselftest-dt
10967 20:15:52.870331 + TESTRUN_ID=1_kselftest-dt
10968 20:15:52.873778 + cd /lava-12928080/0/tests/1_kselftest-dt
10969 20:15:52.877346 ++ cat uuid
10970 20:15:52.877433 + UUID=12928080_1.6.2.3.5
10971 20:15:52.880462 + set +x
10972 20:15:52.883440 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12928080_1.6.2.3.5>
10973 20:15:52.883704 Received signal: <STARTRUN> 1_kselftest-dt 12928080_1.6.2.3.5
10974 20:15:52.883785 Starting test lava.1_kselftest-dt (12928080_1.6.2.3.5)
10975 20:15:52.883895 Skipping test definition patterns.
10976 20:15:52.887083 + cd ./automated/linux/kselftest/
10977 20:15:52.917032 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10978 20:15:52.936911 INFO: install_deps skipped
10979 20:15:53.047170 --2024-03-03 20:13:04-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10980 20:15:53.053760 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10981 20:15:53.182090 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10982 20:15:53.314510 HTTP request sent, awaiting response... 200 OK
10983 20:15:53.317989 Length: 1746752 (1.7M) [application/octet-stream]
10984 20:15:53.321190 Saving to: 'kselftest.tar.xz'
10985 20:15:53.321316
10986 20:15:53.321429
10987 20:15:53.579921 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10988 20:15:53.845363 kselftest.tar.xz 2%[ ] 49.22K 187KB/s
10989 20:15:54.294205 kselftest.tar.xz 12%[=> ] 217.50K 411KB/s
10990 20:15:54.385879 kselftest.tar.xz 48%[========> ] 821.30K 840KB/s
10991 20:15:54.392665 kselftest.tar.xz 100%[===================>] 1.67M 1.56MB/s in 1.1s
10992 20:15:54.392813
10993 20:15:54.545859 2024-03-03 20:13:05 (1.56 MB/s) - 'kselftest.tar.xz' saved [1746752/1746752]
10994 20:15:54.546013
10995 20:15:58.332964 skiplist:
10996 20:15:58.336491 ========================================
10997 20:15:58.339413 ========================================
10998 20:15:58.391891 ============== Tests to run ===============
10999 20:15:58.395173 ===========End Tests to run ===============
11000 20:15:58.398391 shardfile-dt fail
11001 20:15:58.417925 ./kselftest.sh: 131: cannot open /lava-12928080/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11002 20:15:58.421191 + ../../utils/send-to-lava.sh ./output/result.txt
11003 20:15:58.471362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11004 20:15:58.471506 + set +x
11005 20:15:58.471755 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11007 20:15:58.477705 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12928080_1.6.2.3.5>
11008 20:15:58.477802 <LAVA_TEST_RUNNER EXIT>
11009 20:15:58.478036 Received signal: <ENDRUN> 1_kselftest-dt 12928080_1.6.2.3.5
11010 20:15:58.478106 Ending use of test pattern.
11011 20:15:58.478166 Ending test lava.1_kselftest-dt (12928080_1.6.2.3.5), duration 5.59
11013 20:15:58.478381 ok: lava_test_shell seems to have completed
11014 20:15:58.478469 shardfile-dt: fail
11015 20:15:58.478554 end: 3.1 lava-test-shell (duration 00:00:06) [common]
11016 20:15:58.478633 end: 3 lava-test-retry (duration 00:00:06) [common]
11017 20:15:58.478719 start: 4 finalize (timeout 00:07:43) [common]
11018 20:15:58.478811 start: 4.1 power-off (timeout 00:00:30) [common]
11019 20:15:58.478964 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11020 20:15:58.556769 >> Command sent successfully.
11021 20:15:58.559464 Returned 0 in 0 seconds
11022 20:15:58.659871 end: 4.1 power-off (duration 00:00:00) [common]
11024 20:15:58.660254 start: 4.2 read-feedback (timeout 00:07:43) [common]
11025 20:15:58.660560 Listened to connection for namespace 'common' for up to 1s
11026 20:15:58.660846 Listened to connection for namespace 'common' for up to 1s
11027 20:15:59.661507 Finalising connection for namespace 'common'
11028 20:15:59.661688 Disconnecting from shell: Finalise
11029 20:15:59.661769 / #
11030 20:15:59.762126 end: 4.2 read-feedback (duration 00:00:01) [common]
11031 20:15:59.762307 end: 4 finalize (duration 00:00:01) [common]
11032 20:15:59.762423 Cleaning after the job
11033 20:15:59.762521 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/ramdisk
11034 20:15:59.765530 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/kernel
11035 20:15:59.781140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/dtb
11036 20:15:59.781437 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/nfsrootfs
11037 20:15:59.879082 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928080/tftp-deploy-c59hqd2v/modules
11038 20:15:59.886833 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928080
11039 20:16:00.553608 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928080
11040 20:16:00.553798 Job finished correctly