Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 13
1 20:14:09.016485 lava-dispatcher, installed at version: 2024.01
2 20:14:09.016712 start: 0 validate
3 20:14:09.016850 Start time: 2024-03-03 20:14:09.016842+00:00 (UTC)
4 20:14:09.016980 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:14:09.017109 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 20:14:09.297681 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:14:09.297858 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:14:09.555573 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:14:09.555751 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:14:09.824732 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:14:09.825433 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:14:10.095958 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:14:10.096868 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:14:10.371680 validate duration: 1.35
16 20:14:10.372266 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:14:10.372508 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:14:10.372736 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:14:10.373023 Not decompressing ramdisk as can be used compressed.
20 20:14:10.373240 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 20:14:10.373401 saving as /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/ramdisk/initrd.cpio.gz
22 20:14:10.373594 total size: 4663047 (4 MB)
23 20:14:10.375966 progress 0 % (0 MB)
24 20:14:10.379134 progress 5 % (0 MB)
25 20:14:10.381315 progress 10 % (0 MB)
26 20:14:10.383517 progress 15 % (0 MB)
27 20:14:10.385602 progress 20 % (0 MB)
28 20:14:10.387495 progress 25 % (1 MB)
29 20:14:10.389397 progress 30 % (1 MB)
30 20:14:10.391094 progress 35 % (1 MB)
31 20:14:10.392797 progress 40 % (1 MB)
32 20:14:10.394659 progress 45 % (2 MB)
33 20:14:10.396240 progress 50 % (2 MB)
34 20:14:10.397809 progress 55 % (2 MB)
35 20:14:10.399342 progress 60 % (2 MB)
36 20:14:10.400729 progress 65 % (2 MB)
37 20:14:10.402088 progress 70 % (3 MB)
38 20:14:10.403434 progress 75 % (3 MB)
39 20:14:10.404811 progress 80 % (3 MB)
40 20:14:10.406127 progress 85 % (3 MB)
41 20:14:10.407511 progress 90 % (4 MB)
42 20:14:10.408732 progress 95 % (4 MB)
43 20:14:10.410015 progress 100 % (4 MB)
44 20:14:10.410166 4 MB downloaded in 0.04 s (121.57 MB/s)
45 20:14:10.410318 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:14:10.410560 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:14:10.410646 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:14:10.410730 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:14:10.410867 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:14:10.410934 saving as /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/kernel/Image
52 20:14:10.410993 total size: 51601920 (49 MB)
53 20:14:10.411053 No compression specified
54 20:14:10.412429 progress 0 % (0 MB)
55 20:14:10.426074 progress 5 % (2 MB)
56 20:14:10.439626 progress 10 % (4 MB)
57 20:14:10.453255 progress 15 % (7 MB)
58 20:14:10.466806 progress 20 % (9 MB)
59 20:14:10.480311 progress 25 % (12 MB)
60 20:14:10.494176 progress 30 % (14 MB)
61 20:14:10.508177 progress 35 % (17 MB)
62 20:14:10.521700 progress 40 % (19 MB)
63 20:14:10.535304 progress 45 % (22 MB)
64 20:14:10.548797 progress 50 % (24 MB)
65 20:14:10.562519 progress 55 % (27 MB)
66 20:14:10.575909 progress 60 % (29 MB)
67 20:14:10.589580 progress 65 % (32 MB)
68 20:14:10.603410 progress 70 % (34 MB)
69 20:14:10.617086 progress 75 % (36 MB)
70 20:14:10.630549 progress 80 % (39 MB)
71 20:14:10.644142 progress 85 % (41 MB)
72 20:14:10.657531 progress 90 % (44 MB)
73 20:14:10.670602 progress 95 % (46 MB)
74 20:14:10.683514 progress 100 % (49 MB)
75 20:14:10.683754 49 MB downloaded in 0.27 s (180.42 MB/s)
76 20:14:10.683908 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:14:10.684142 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:14:10.684234 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:14:10.684318 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:14:10.684457 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:14:10.684533 saving as /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/dtb/mt8192-asurada-spherion-r0.dtb
83 20:14:10.684594 total size: 47278 (0 MB)
84 20:14:10.684654 No compression specified
85 20:14:10.685797 progress 69 % (0 MB)
86 20:14:10.686070 progress 100 % (0 MB)
87 20:14:10.686226 0 MB downloaded in 0.00 s (27.66 MB/s)
88 20:14:10.686348 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:14:10.686568 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:14:10.686651 start: 1.4 download-retry (timeout 00:10:00) [common]
92 20:14:10.686732 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 20:14:10.686842 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 20:14:10.686914 saving as /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/nfsrootfs/full.rootfs.tar
95 20:14:10.686973 total size: 200856304 (191 MB)
96 20:14:10.687033 Using unxz to decompress xz
97 20:14:10.691247 progress 0 % (0 MB)
98 20:14:11.222859 progress 5 % (9 MB)
99 20:14:11.757924 progress 10 % (19 MB)
100 20:14:12.349222 progress 15 % (28 MB)
101 20:14:12.715918 progress 20 % (38 MB)
102 20:14:13.039603 progress 25 % (47 MB)
103 20:14:13.644552 progress 30 % (57 MB)
104 20:14:14.212910 progress 35 % (67 MB)
105 20:14:14.838478 progress 40 % (76 MB)
106 20:14:15.425043 progress 45 % (86 MB)
107 20:14:16.036006 progress 50 % (95 MB)
108 20:14:16.686156 progress 55 % (105 MB)
109 20:14:17.364689 progress 60 % (114 MB)
110 20:14:17.483230 progress 65 % (124 MB)
111 20:14:17.630632 progress 70 % (134 MB)
112 20:14:17.727799 progress 75 % (143 MB)
113 20:14:17.803158 progress 80 % (153 MB)
114 20:14:17.884409 progress 85 % (162 MB)
115 20:14:17.988133 progress 90 % (172 MB)
116 20:14:18.282331 progress 95 % (182 MB)
117 20:14:18.873939 progress 100 % (191 MB)
118 20:14:18.879799 191 MB downloaded in 8.19 s (23.38 MB/s)
119 20:14:18.880099 end: 1.4.1 http-download (duration 00:00:08) [common]
121 20:14:18.880503 end: 1.4 download-retry (duration 00:00:08) [common]
122 20:14:18.880623 start: 1.5 download-retry (timeout 00:09:51) [common]
123 20:14:18.880741 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 20:14:18.880929 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:14:18.881027 saving as /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/modules/modules.tar
126 20:14:18.881117 total size: 8632284 (8 MB)
127 20:14:18.881209 Using unxz to decompress xz
128 20:14:18.886001 progress 0 % (0 MB)
129 20:14:18.906192 progress 5 % (0 MB)
130 20:14:18.930414 progress 10 % (0 MB)
131 20:14:18.954440 progress 15 % (1 MB)
132 20:14:18.976936 progress 20 % (1 MB)
133 20:14:19.001105 progress 25 % (2 MB)
134 20:14:19.027511 progress 30 % (2 MB)
135 20:14:19.053720 progress 35 % (2 MB)
136 20:14:19.078529 progress 40 % (3 MB)
137 20:14:19.102296 progress 45 % (3 MB)
138 20:14:19.127001 progress 50 % (4 MB)
139 20:14:19.151608 progress 55 % (4 MB)
140 20:14:19.176707 progress 60 % (4 MB)
141 20:14:19.200947 progress 65 % (5 MB)
142 20:14:19.225938 progress 70 % (5 MB)
143 20:14:19.251011 progress 75 % (6 MB)
144 20:14:19.277232 progress 80 % (6 MB)
145 20:14:19.301758 progress 85 % (7 MB)
146 20:14:19.328219 progress 90 % (7 MB)
147 20:14:19.356892 progress 95 % (7 MB)
148 20:14:19.385215 progress 100 % (8 MB)
149 20:14:19.390675 8 MB downloaded in 0.51 s (16.16 MB/s)
150 20:14:19.390937 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:14:19.391212 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:14:19.391306 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 20:14:19.391406 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 20:14:22.895065 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0
156 20:14:22.895267 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 20:14:22.895367 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 20:14:22.895536 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3
159 20:14:22.895665 makedir: /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin
160 20:14:22.895765 makedir: /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/tests
161 20:14:22.895861 makedir: /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/results
162 20:14:22.895960 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-add-keys
163 20:14:22.896101 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-add-sources
164 20:14:22.896231 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-background-process-start
165 20:14:22.896357 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-background-process-stop
166 20:14:22.896484 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-common-functions
167 20:14:22.896609 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-echo-ipv4
168 20:14:22.896733 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-install-packages
169 20:14:22.896859 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-installed-packages
170 20:14:22.896980 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-os-build
171 20:14:22.897105 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-probe-channel
172 20:14:22.897229 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-probe-ip
173 20:14:22.897352 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-target-ip
174 20:14:22.897478 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-target-mac
175 20:14:22.897633 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-target-storage
176 20:14:22.897759 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-case
177 20:14:22.897884 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-event
178 20:14:22.898007 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-feedback
179 20:14:22.898130 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-raise
180 20:14:22.898253 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-reference
181 20:14:22.898376 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-runner
182 20:14:22.898499 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-set
183 20:14:22.898623 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-test-shell
184 20:14:22.898749 Updating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-add-keys (debian)
185 20:14:22.898900 Updating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-add-sources (debian)
186 20:14:22.899040 Updating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-install-packages (debian)
187 20:14:22.899176 Updating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-installed-packages (debian)
188 20:14:22.899311 Updating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/bin/lava-os-build (debian)
189 20:14:22.899430 Creating /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/environment
190 20:14:22.899523 LAVA metadata
191 20:14:22.899590 - LAVA_JOB_ID=12928144
192 20:14:22.899651 - LAVA_DISPATCHER_IP=192.168.201.1
193 20:14:22.899749 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 20:14:22.899812 skipped lava-vland-overlay
195 20:14:22.899882 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 20:14:22.899957 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 20:14:22.900016 skipped lava-multinode-overlay
198 20:14:22.900085 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 20:14:22.900201 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 20:14:22.900275 Loading test definitions
201 20:14:22.900360 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 20:14:22.900428 Using /lava-12928144 at stage 0
203 20:14:22.900703 uuid=12928144_1.6.2.3.1 testdef=None
204 20:14:22.900789 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 20:14:22.900870 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 20:14:22.901321 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 20:14:22.901787 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 20:14:22.902338 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 20:14:22.902561 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 20:14:22.903086 runner path: /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/0/tests/0_timesync-off test_uuid 12928144_1.6.2.3.1
213 20:14:22.903270 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 20:14:22.903486 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 20:14:22.903560 Using /lava-12928144 at stage 0
217 20:14:22.903653 Fetching tests from https://github.com/kernelci/test-definitions.git
218 20:14:22.903736 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/0/tests/1_kselftest-rtc'
219 20:14:25.406048 Running '/usr/bin/git checkout kernelci.org
220 20:14:25.554894 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 20:14:25.555842 uuid=12928144_1.6.2.3.5 testdef=None
222 20:14:25.556032 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 20:14:25.556403 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 20:14:25.557671 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 20:14:25.558033 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 20:14:25.559661 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 20:14:25.560034 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 20:14:25.561571 runner path: /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/0/tests/1_kselftest-rtc test_uuid 12928144_1.6.2.3.5
232 20:14:25.561661 BOARD='mt8192-asurada-spherion-r0'
233 20:14:25.561725 BRANCH='cip-gitlab'
234 20:14:25.561784 SKIPFILE='/dev/null'
235 20:14:25.561841 SKIP_INSTALL='True'
236 20:14:25.561896 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 20:14:25.561954 TST_CASENAME=''
238 20:14:25.562009 TST_CMDFILES='rtc'
239 20:14:25.562151 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 20:14:25.562371 Creating lava-test-runner.conf files
242 20:14:25.562435 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928144/lava-overlay-rjz96gi3/lava-12928144/0 for stage 0
243 20:14:25.562528 - 0_timesync-off
244 20:14:25.562594 - 1_kselftest-rtc
245 20:14:25.562687 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 20:14:25.562773 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 20:14:33.437380 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 20:14:33.437630 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 20:14:33.437726 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 20:14:33.437825 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 20:14:33.437917 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 20:14:33.560185 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 20:14:33.560579 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 20:14:33.560696 extracting modules file /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0
255 20:14:33.784194 extracting modules file /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928144/extract-overlay-ramdisk-ru1p86j0/ramdisk
256 20:14:34.018060 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 20:14:34.018232 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 20:14:34.018324 [common] Applying overlay to NFS
259 20:14:34.018395 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928144/compress-overlay-n779zn8p/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0
260 20:14:34.943037 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 20:14:34.943214 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 20:14:34.943313 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 20:14:34.943408 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 20:14:34.943496 Building ramdisk /var/lib/lava/dispatcher/tmp/12928144/extract-overlay-ramdisk-ru1p86j0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928144/extract-overlay-ramdisk-ru1p86j0/ramdisk
265 20:14:35.280160 >> 119447 blocks
266 20:14:37.228358 rename /var/lib/lava/dispatcher/tmp/12928144/extract-overlay-ramdisk-ru1p86j0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/ramdisk/ramdisk.cpio.gz
267 20:14:37.228835 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 20:14:37.228963 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 20:14:37.229061 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 20:14:37.229170 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/kernel/Image'
271 20:14:50.074150 Returned 0 in 12 seconds
272 20:14:50.175314 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/kernel/image.itb
273 20:14:50.581180 output: FIT description: Kernel Image image with one or more FDT blobs
274 20:14:50.581609 output: Created: Sun Mar 3 20:14:50 2024
275 20:14:50.581682 output: Image 0 (kernel-1)
276 20:14:50.581749 output: Description:
277 20:14:50.581811 output: Created: Sun Mar 3 20:14:50 2024
278 20:14:50.581871 output: Type: Kernel Image
279 20:14:50.581931 output: Compression: lzma compressed
280 20:14:50.581993 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
281 20:14:50.582071 output: Architecture: AArch64
282 20:14:50.582168 output: OS: Linux
283 20:14:50.582252 output: Load Address: 0x00000000
284 20:14:50.582313 output: Entry Point: 0x00000000
285 20:14:50.582370 output: Hash algo: crc32
286 20:14:50.582426 output: Hash value: 91cb1a17
287 20:14:50.582481 output: Image 1 (fdt-1)
288 20:14:50.582533 output: Description: mt8192-asurada-spherion-r0
289 20:14:50.582584 output: Created: Sun Mar 3 20:14:50 2024
290 20:14:50.582637 output: Type: Flat Device Tree
291 20:14:50.582688 output: Compression: uncompressed
292 20:14:50.582739 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 20:14:50.582791 output: Architecture: AArch64
294 20:14:50.582842 output: Hash algo: crc32
295 20:14:50.582894 output: Hash value: cc4352de
296 20:14:50.582945 output: Image 2 (ramdisk-1)
297 20:14:50.582996 output: Description: unavailable
298 20:14:50.583047 output: Created: Sun Mar 3 20:14:50 2024
299 20:14:50.583098 output: Type: RAMDisk Image
300 20:14:50.583149 output: Compression: Unknown Compression
301 20:14:50.583200 output: Data Size: 17805849 Bytes = 17388.52 KiB = 16.98 MiB
302 20:14:50.583252 output: Architecture: AArch64
303 20:14:50.583303 output: OS: Linux
304 20:14:50.583354 output: Load Address: unavailable
305 20:14:50.583403 output: Entry Point: unavailable
306 20:14:50.583454 output: Hash algo: crc32
307 20:14:50.583505 output: Hash value: 8b6c1966
308 20:14:50.583555 output: Default Configuration: 'conf-1'
309 20:14:50.583606 output: Configuration 0 (conf-1)
310 20:14:50.583656 output: Description: mt8192-asurada-spherion-r0
311 20:14:50.583707 output: Kernel: kernel-1
312 20:14:50.583758 output: Init Ramdisk: ramdisk-1
313 20:14:50.583809 output: FDT: fdt-1
314 20:14:50.583860 output: Loadables: kernel-1
315 20:14:50.583911 output:
316 20:14:50.584134 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 20:14:50.584234 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 20:14:50.584333 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 20:14:50.584422 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 20:14:50.584503 No LXC device requested
321 20:14:50.584581 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 20:14:50.584668 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 20:14:50.584745 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 20:14:50.584812 Checking files for TFTP limit of 4294967296 bytes.
325 20:14:50.585313 end: 1 tftp-deploy (duration 00:00:40) [common]
326 20:14:50.585417 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 20:14:50.585555 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 20:14:50.585686 substitutions:
329 20:14:50.585756 - {DTB}: 12928144/tftp-deploy-p_3bgsc4/dtb/mt8192-asurada-spherion-r0.dtb
330 20:14:50.585822 - {INITRD}: 12928144/tftp-deploy-p_3bgsc4/ramdisk/ramdisk.cpio.gz
331 20:14:50.585880 - {KERNEL}: 12928144/tftp-deploy-p_3bgsc4/kernel/Image
332 20:14:50.585935 - {LAVA_MAC}: None
333 20:14:50.585991 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0
334 20:14:50.586057 - {NFS_SERVER_IP}: 192.168.201.1
335 20:14:50.586119 - {PRESEED_CONFIG}: None
336 20:14:50.586174 - {PRESEED_LOCAL}: None
337 20:14:50.586228 - {RAMDISK}: 12928144/tftp-deploy-p_3bgsc4/ramdisk/ramdisk.cpio.gz
338 20:14:50.586282 - {ROOT_PART}: None
339 20:14:50.586335 - {ROOT}: None
340 20:14:50.586387 - {SERVER_IP}: 192.168.201.1
341 20:14:50.586440 - {TEE}: None
342 20:14:50.586492 Parsed boot commands:
343 20:14:50.586544 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 20:14:50.586730 Parsed boot commands: tftpboot 192.168.201.1 12928144/tftp-deploy-p_3bgsc4/kernel/image.itb 12928144/tftp-deploy-p_3bgsc4/kernel/cmdline
345 20:14:50.586819 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 20:14:50.586903 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 20:14:50.586992 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 20:14:50.587085 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 20:14:50.587158 Not connected, no need to disconnect.
350 20:14:50.587232 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 20:14:50.587310 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 20:14:50.587379 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 20:14:50.591471 Setting prompt string to ['lava-test: # ']
354 20:14:50.591846 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 20:14:50.591953 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 20:14:50.592051 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 20:14:50.592146 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 20:14:50.592356 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 20:14:55.722236 >> Command sent successfully.
360 20:14:55.724631 Returned 0 in 5 seconds
361 20:14:55.825064 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 20:14:55.825403 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 20:14:55.825550 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 20:14:55.825649 Setting prompt string to 'Starting depthcharge on Spherion...'
366 20:14:55.825729 Changing prompt to 'Starting depthcharge on Spherion...'
367 20:14:55.825822 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 20:14:55.826118 [Enter `^Ec?' for help]
369 20:14:55.999277
370 20:14:55.999473
371 20:14:55.999615 F0: 102B 0000
372 20:14:55.999744
373 20:14:55.999883 F3: 1001 0000 [0200]
374 20:14:56.000012
375 20:14:56.002729 F3: 1001 0000
376 20:14:56.002871
377 20:14:56.003015 F7: 102D 0000
378 20:14:56.003151
379 20:14:56.006243 F1: 0000 0000
380 20:14:56.006403
381 20:14:56.006565 V0: 0000 0000 [0001]
382 20:14:56.006720
383 20:14:56.009254 00: 0007 8000
384 20:14:56.009420
385 20:14:56.009592 01: 0000 0000
386 20:14:56.009784
387 20:14:56.010010 BP: 0C00 0209 [0000]
388 20:14:56.012643
389 20:14:56.012822 G0: 1182 0000
390 20:14:56.013007
391 20:14:56.013215 EC: 0000 0021 [4000]
392 20:14:56.016637
393 20:14:56.016846 S7: 0000 0000 [0000]
394 20:14:56.017060
395 20:14:56.017305 CC: 0000 0000 [0001]
396 20:14:56.019973
397 20:14:56.020224 T0: 0000 0040 [010F]
398 20:14:56.020486
399 20:14:56.020724 Jump to BL
400 20:14:56.020959
401 20:14:56.046470
402 20:14:56.046999
403 20:14:56.047455
404 20:14:56.053612 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 20:14:56.057405 ARM64: Exception handlers installed.
406 20:14:56.060663 ARM64: Testing exception
407 20:14:56.064000 ARM64: Done test exception
408 20:14:56.070447 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 20:14:56.080925 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 20:14:56.087799 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 20:14:56.097850 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 20:14:56.104545 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 20:14:56.111049 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 20:14:56.123026 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 20:14:56.129606 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 20:14:56.148923 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 20:14:56.152331 WDT: Last reset was cold boot
418 20:14:56.155449 SPI1(PAD0) initialized at 2873684 Hz
419 20:14:56.158765 SPI5(PAD0) initialized at 992727 Hz
420 20:14:56.162506 VBOOT: Loading verstage.
421 20:14:56.168781 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:14:56.172104 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:14:56.175745 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:14:56.178672 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:14:56.186344 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:14:56.192818 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:14:56.203618 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 20:14:56.203756
429 20:14:56.203828
430 20:14:56.213763 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:14:56.217071 ARM64: Exception handlers installed.
432 20:14:56.220453 ARM64: Testing exception
433 20:14:56.220559 ARM64: Done test exception
434 20:14:56.226876 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:14:56.230393 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:14:56.244941 Probing TPM: . done!
437 20:14:56.245024 TPM ready after 0 ms
438 20:14:56.251380 Connected to device vid:did:rid of 1ae0:0028:00
439 20:14:56.258710 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 20:14:56.297715 Initialized TPM device CR50 revision 0
441 20:14:56.309172 tlcl_send_startup: Startup return code is 0
442 20:14:56.309296 TPM: setup succeeded
443 20:14:56.320612 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:14:56.329374 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:14:56.340974 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:14:56.350287 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:14:56.353641 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:14:56.358892 in-header: 03 07 00 00 08 00 00 00
449 20:14:56.362292 in-data: aa e4 47 04 13 02 00 00
450 20:14:56.365828 Chrome EC: UHEPI supported
451 20:14:56.372852 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:14:56.376847 in-header: 03 9d 00 00 08 00 00 00
453 20:14:56.380176 in-data: 10 20 20 08 00 00 00 00
454 20:14:56.380288 Phase 1
455 20:14:56.384069 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:14:56.391603 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:14:56.398838 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:14:56.398985 Recovery requested (1009000e)
459 20:14:56.409034 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:14:56.413117 tlcl_extend: response is 0
461 20:14:56.421172 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:14:56.426737 tlcl_extend: response is 0
463 20:14:56.433453 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:14:56.454359 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
465 20:14:56.461698 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 20:14:56.461794
467 20:14:56.461881
468 20:14:56.472952 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:14:56.473065 ARM64: Exception handlers installed.
470 20:14:56.476370 ARM64: Testing exception
471 20:14:56.479471 ARM64: Done test exception
472 20:14:56.500121 pmic_efuse_setting: Set efuses in 11 msecs
473 20:14:56.503508 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:14:56.510124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:14:56.513645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:14:56.517163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:14:56.524513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:14:56.528247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:14:56.531573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:14:56.538868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:14:56.542451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:14:56.545681 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:14:56.552565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:14:56.555871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:14:56.559200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:14:56.565804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:14:56.572644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:14:56.575599 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:14:56.582321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:14:56.588883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:14:56.595973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:14:56.599770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:14:56.607090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:14:56.610585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:14:56.617890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:14:56.621282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:14:56.628446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:14:56.632268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:14:56.638813 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:14:56.642393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:14:56.649863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:14:56.652840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:14:56.659786 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:14:56.662969 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:14:56.666778 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:14:56.674230 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:14:56.677953 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:14:56.682000 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:14:56.689409 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:14:56.692894 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:14:56.699381 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:14:56.702720 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:14:56.706064 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:14:56.712969 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:14:56.715970 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:14:56.719631 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:14:56.725804 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:14:56.729222 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:14:56.732607 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:14:56.738928 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:14:56.742438 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:14:56.745863 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:14:56.749357 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:14:56.755885 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:14:56.762133 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:14:56.769116 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:14:56.775915 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:14:56.782508 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:14:56.792369 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:14:56.795713 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:14:56.802529 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:14:56.805816 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:14:56.812480 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xe
534 20:14:56.819039 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:14:56.822430 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 20:14:56.825713 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:14:56.836712 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 20:14:56.839794 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 20:14:56.846626 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 20:14:56.849745 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 20:14:56.853264 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 20:14:56.856637 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 20:14:56.860172 ADC[4]: Raw value=899630 ID=7
544 20:14:56.863153 ADC[3]: Raw value=212700 ID=1
545 20:14:56.866689 RAM Code: 0x71
546 20:14:56.869775 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 20:14:56.873245 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 20:14:56.883697 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 20:14:56.890499 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 20:14:56.893697 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 20:14:56.897005 in-header: 03 07 00 00 08 00 00 00
552 20:14:56.900531 in-data: aa e4 47 04 13 02 00 00
553 20:14:56.904028 Chrome EC: UHEPI supported
554 20:14:56.907777 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 20:14:56.911107 in-header: 03 d5 00 00 08 00 00 00
556 20:14:56.914996 in-data: 98 20 60 08 00 00 00 00
557 20:14:56.918504 MRC: failed to locate region type 0.
558 20:14:56.925687 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 20:14:56.929110 DRAM-K: Running full calibration
560 20:14:56.935956 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 20:14:56.936059 header.status = 0x0
562 20:14:56.939508 header.version = 0x6 (expected: 0x6)
563 20:14:56.943347 header.size = 0xd00 (expected: 0xd00)
564 20:14:56.946657 header.flags = 0x0
565 20:14:56.949895 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 20:14:56.968567 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
567 20:14:56.975462 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 20:14:56.978757 dram_init: ddr_geometry: 2
569 20:14:56.982375 [EMI] MDL number = 2
570 20:14:56.982446 [EMI] Get MDL freq = 0
571 20:14:56.985461 dram_init: ddr_type: 0
572 20:14:56.985538 is_discrete_lpddr4: 1
573 20:14:56.988819 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 20:14:56.988887
575 20:14:56.988946
576 20:14:56.992097 [Bian_co] ETT version 0.0.0.1
577 20:14:56.998820 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 20:14:56.998896
579 20:14:57.001877 dramc_set_vcore_voltage set vcore to 650000
580 20:14:57.001948 Read voltage for 800, 4
581 20:14:57.005323 Vio18 = 0
582 20:14:57.005419 Vcore = 650000
583 20:14:57.005539 Vdram = 0
584 20:14:57.008624 Vddq = 0
585 20:14:57.008691 Vmddr = 0
586 20:14:57.011887 dram_init: config_dvfs: 1
587 20:14:57.015522 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 20:14:57.022000 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 20:14:57.025209 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 20:14:57.028571 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 20:14:57.032133 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 20:14:57.035236 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 20:14:57.038518 MEM_TYPE=3, freq_sel=18
594 20:14:57.041605 sv_algorithm_assistance_LP4_1600
595 20:14:57.045269 ============ PULL DRAM RESETB DOWN ============
596 20:14:57.051722 ========== PULL DRAM RESETB DOWN end =========
597 20:14:57.055297 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 20:14:57.058404 ===================================
599 20:14:57.062066 LPDDR4 DRAM CONFIGURATION
600 20:14:57.065459 ===================================
601 20:14:57.065966 EX_ROW_EN[0] = 0x0
602 20:14:57.068779 EX_ROW_EN[1] = 0x0
603 20:14:57.069144 LP4Y_EN = 0x0
604 20:14:57.072126 WORK_FSP = 0x0
605 20:14:57.072672 WL = 0x2
606 20:14:57.075457 RL = 0x2
607 20:14:57.075902 BL = 0x2
608 20:14:57.078936 RPST = 0x0
609 20:14:57.079363 RD_PRE = 0x0
610 20:14:57.082050 WR_PRE = 0x1
611 20:14:57.082788 WR_PST = 0x0
612 20:14:57.085463 DBI_WR = 0x0
613 20:14:57.085946 DBI_RD = 0x0
614 20:14:57.088787 OTF = 0x1
615 20:14:57.091800 ===================================
616 20:14:57.095271 ===================================
617 20:14:57.095759 ANA top config
618 20:14:57.098537 ===================================
619 20:14:57.102013 DLL_ASYNC_EN = 0
620 20:14:57.105215 ALL_SLAVE_EN = 1
621 20:14:57.108663 NEW_RANK_MODE = 1
622 20:14:57.109131 DLL_IDLE_MODE = 1
623 20:14:57.111738 LP45_APHY_COMB_EN = 1
624 20:14:57.115363 TX_ODT_DIS = 1
625 20:14:57.118788 NEW_8X_MODE = 1
626 20:14:57.121920 ===================================
627 20:14:57.125021 ===================================
628 20:14:57.128677 data_rate = 1600
629 20:14:57.131870 CKR = 1
630 20:14:57.132388 DQ_P2S_RATIO = 8
631 20:14:57.135016 ===================================
632 20:14:57.138447 CA_P2S_RATIO = 8
633 20:14:57.142108 DQ_CA_OPEN = 0
634 20:14:57.144937 DQ_SEMI_OPEN = 0
635 20:14:57.148579 CA_SEMI_OPEN = 0
636 20:14:57.149017 CA_FULL_RATE = 0
637 20:14:57.151676 DQ_CKDIV4_EN = 1
638 20:14:57.155456 CA_CKDIV4_EN = 1
639 20:14:57.158443 CA_PREDIV_EN = 0
640 20:14:57.161809 PH8_DLY = 0
641 20:14:57.165259 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 20:14:57.165807 DQ_AAMCK_DIV = 4
643 20:14:57.168676 CA_AAMCK_DIV = 4
644 20:14:57.172158 CA_ADMCK_DIV = 4
645 20:14:57.175317 DQ_TRACK_CA_EN = 0
646 20:14:57.178811 CA_PICK = 800
647 20:14:57.182051 CA_MCKIO = 800
648 20:14:57.182503 MCKIO_SEMI = 0
649 20:14:57.185371 PLL_FREQ = 3068
650 20:14:57.188798 DQ_UI_PI_RATIO = 32
651 20:14:57.192261 CA_UI_PI_RATIO = 0
652 20:14:57.195134 ===================================
653 20:14:57.198792 ===================================
654 20:14:57.202175 memory_type:LPDDR4
655 20:14:57.202617 GP_NUM : 10
656 20:14:57.205527 SRAM_EN : 1
657 20:14:57.209134 MD32_EN : 0
658 20:14:57.209620 ===================================
659 20:14:57.212795 [ANA_INIT] >>>>>>>>>>>>>>
660 20:14:57.216752 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 20:14:57.220361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 20:14:57.224020 ===================================
663 20:14:57.224555 data_rate = 1600,PCW = 0X7600
664 20:14:57.228093 ===================================
665 20:14:57.231843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 20:14:57.239057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 20:14:57.243121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 20:14:57.246300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 20:14:57.250243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 20:14:57.254091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 20:14:57.258260 [ANA_INIT] flow start
672 20:14:57.258795 [ANA_INIT] PLL >>>>>>>>
673 20:14:57.262116 [ANA_INIT] PLL <<<<<<<<
674 20:14:57.262652 [ANA_INIT] MIDPI >>>>>>>>
675 20:14:57.265657 [ANA_INIT] MIDPI <<<<<<<<
676 20:14:57.269186 [ANA_INIT] DLL >>>>>>>>
677 20:14:57.269692 [ANA_INIT] flow end
678 20:14:57.272550 ============ LP4 DIFF to SE enter ============
679 20:14:57.280161 ============ LP4 DIFF to SE exit ============
680 20:14:57.280638 [ANA_INIT] <<<<<<<<<<<<<
681 20:14:57.283933 [Flow] Enable top DCM control >>>>>
682 20:14:57.287880 [Flow] Enable top DCM control <<<<<
683 20:14:57.291205 Enable DLL master slave shuffle
684 20:14:57.295287 ==============================================================
685 20:14:57.298930 Gating Mode config
686 20:14:57.302701 ==============================================================
687 20:14:57.306129 Config description:
688 20:14:57.313296 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 20:14:57.321028 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 20:14:57.324695 SELPH_MODE 0: By rank 1: By Phase
691 20:14:57.332187 ==============================================================
692 20:14:57.336042 GAT_TRACK_EN = 1
693 20:14:57.336655 RX_GATING_MODE = 2
694 20:14:57.339318 RX_GATING_TRACK_MODE = 2
695 20:14:57.342849 SELPH_MODE = 1
696 20:14:57.346072 PICG_EARLY_EN = 1
697 20:14:57.349427 VALID_LAT_VALUE = 1
698 20:14:57.356259 ==============================================================
699 20:14:57.359419 Enter into Gating configuration >>>>
700 20:14:57.362846 Exit from Gating configuration <<<<
701 20:14:57.366316 Enter into DVFS_PRE_config >>>>>
702 20:14:57.376382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 20:14:57.379571 Exit from DVFS_PRE_config <<<<<
704 20:14:57.383329 Enter into PICG configuration >>>>
705 20:14:57.386234 Exit from PICG configuration <<<<
706 20:14:57.389935 [RX_INPUT] configuration >>>>>
707 20:14:57.390392 [RX_INPUT] configuration <<<<<
708 20:14:57.396329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 20:14:57.402900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 20:14:57.406414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 20:14:57.412889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 20:14:57.420047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 20:14:57.426451 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 20:14:57.430097 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 20:14:57.433304 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 20:14:57.440013 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 20:14:57.443206 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 20:14:57.446295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 20:14:57.449954 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 20:14:57.453124 ===================================
721 20:14:57.456528 LPDDR4 DRAM CONFIGURATION
722 20:14:57.459629 ===================================
723 20:14:57.463287 EX_ROW_EN[0] = 0x0
724 20:14:57.463895 EX_ROW_EN[1] = 0x0
725 20:14:57.466574 LP4Y_EN = 0x0
726 20:14:57.467074 WORK_FSP = 0x0
727 20:14:57.469925 WL = 0x2
728 20:14:57.470522 RL = 0x2
729 20:14:57.472910 BL = 0x2
730 20:14:57.473399 RPST = 0x0
731 20:14:57.476298 RD_PRE = 0x0
732 20:14:57.476788 WR_PRE = 0x1
733 20:14:57.479755 WR_PST = 0x0
734 20:14:57.480244 DBI_WR = 0x0
735 20:14:57.483010 DBI_RD = 0x0
736 20:14:57.483509 OTF = 0x1
737 20:14:57.486341 ===================================
738 20:14:57.493017 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 20:14:57.496295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 20:14:57.499888 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 20:14:57.503160 ===================================
742 20:14:57.506564 LPDDR4 DRAM CONFIGURATION
743 20:14:57.509719 ===================================
744 20:14:57.513145 EX_ROW_EN[0] = 0x10
745 20:14:57.513636 EX_ROW_EN[1] = 0x0
746 20:14:57.516555 LP4Y_EN = 0x0
747 20:14:57.517006 WORK_FSP = 0x0
748 20:14:57.519820 WL = 0x2
749 20:14:57.520359 RL = 0x2
750 20:14:57.523575 BL = 0x2
751 20:14:57.524105 RPST = 0x0
752 20:14:57.526683 RD_PRE = 0x0
753 20:14:57.527134 WR_PRE = 0x1
754 20:14:57.529851 WR_PST = 0x0
755 20:14:57.530298 DBI_WR = 0x0
756 20:14:57.533430 DBI_RD = 0x0
757 20:14:57.533919 OTF = 0x1
758 20:14:57.536541 ===================================
759 20:14:57.542952 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 20:14:57.547464 nWR fixed to 40
761 20:14:57.550800 [ModeRegInit_LP4] CH0 RK0
762 20:14:57.551263 [ModeRegInit_LP4] CH0 RK1
763 20:14:57.554281 [ModeRegInit_LP4] CH1 RK0
764 20:14:57.557540 [ModeRegInit_LP4] CH1 RK1
765 20:14:57.557992 match AC timing 13
766 20:14:57.564603 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 20:14:57.567381 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 20:14:57.571008 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 20:14:57.577618 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 20:14:57.580572 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 20:14:57.581019 [EMI DOE] emi_dcm 0
772 20:14:57.587468 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 20:14:57.587947 ==
774 20:14:57.591014 Dram Type= 6, Freq= 0, CH_0, rank 0
775 20:14:57.594221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 20:14:57.594673 ==
777 20:14:57.600976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 20:14:57.607509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 20:14:57.614961 [CA 0] Center 38 (7~69) winsize 63
780 20:14:57.618471 [CA 1] Center 37 (7~68) winsize 62
781 20:14:57.621627 [CA 2] Center 35 (5~66) winsize 62
782 20:14:57.624922 [CA 3] Center 35 (5~66) winsize 62
783 20:14:57.628219 [CA 4] Center 34 (4~65) winsize 62
784 20:14:57.631694 [CA 5] Center 34 (3~65) winsize 63
785 20:14:57.632133
786 20:14:57.635063 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 20:14:57.635658
788 20:14:57.638287 [CATrainingPosCal] consider 1 rank data
789 20:14:57.641802 u2DelayCellTimex100 = 270/100 ps
790 20:14:57.644964 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 20:14:57.648453 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 20:14:57.654930 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 20:14:57.659077 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 20:14:57.662380 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 20:14:57.665975 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 20:14:57.666431
797 20:14:57.669676 CA PerBit enable=1, Macro0, CA PI delay=34
798 20:14:57.670120
799 20:14:57.670465 [CBTSetCACLKResult] CA Dly = 34
800 20:14:57.673210 CS Dly: 6 (0~37)
801 20:14:57.673780 ==
802 20:14:57.676796 Dram Type= 6, Freq= 0, CH_0, rank 1
803 20:14:57.680854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 20:14:57.681299 ==
805 20:14:57.687978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 20:14:57.691139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 20:14:57.701538 [CA 0] Center 38 (7~69) winsize 63
808 20:14:57.705738 [CA 1] Center 38 (7~69) winsize 63
809 20:14:57.709208 [CA 2] Center 35 (5~66) winsize 62
810 20:14:57.712796 [CA 3] Center 35 (5~66) winsize 62
811 20:14:57.716695 [CA 4] Center 34 (4~65) winsize 62
812 20:14:57.717188 [CA 5] Center 34 (4~65) winsize 62
813 20:14:57.717646
814 20:14:57.724098 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 20:14:57.724555
816 20:14:57.724923 [CATrainingPosCal] consider 2 rank data
817 20:14:57.727906 u2DelayCellTimex100 = 270/100 ps
818 20:14:57.731504 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 20:14:57.735262 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 20:14:57.739039 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 20:14:57.742560 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 20:14:57.746595 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 20:14:57.750162 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 20:14:57.750634
825 20:14:57.754132 CA PerBit enable=1, Macro0, CA PI delay=34
826 20:14:57.754768
827 20:14:57.757745 [CBTSetCACLKResult] CA Dly = 34
828 20:14:57.758192 CS Dly: 6 (0~38)
829 20:14:57.758541
830 20:14:57.761351 ----->DramcWriteLeveling(PI) begin...
831 20:14:57.761847 ==
832 20:14:57.765569 Dram Type= 6, Freq= 0, CH_0, rank 0
833 20:14:57.768834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 20:14:57.772608 ==
835 20:14:57.773078 Write leveling (Byte 0): 33 => 33
836 20:14:57.776212 Write leveling (Byte 1): 29 => 29
837 20:14:57.780176 DramcWriteLeveling(PI) end<-----
838 20:14:57.780631
839 20:14:57.780988 ==
840 20:14:57.783605 Dram Type= 6, Freq= 0, CH_0, rank 0
841 20:14:57.787502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 20:14:57.787960 ==
843 20:14:57.790868 [Gating] SW mode calibration
844 20:14:57.798287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 20:14:57.801923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 20:14:57.805585 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 20:14:57.813225 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 20:14:57.817297 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
849 20:14:57.820531 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 20:14:57.824307 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 20:14:57.827864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 20:14:57.831907 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 20:14:57.839454 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 20:14:57.843228 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 20:14:57.846986 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 20:14:57.850198 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 20:14:57.854077 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:14:57.861880 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:14:57.865831 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:14:57.869228 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:14:57.873031 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:14:57.876781 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:14:57.880477 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 20:14:57.888416 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
865 20:14:57.891937 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
866 20:14:57.895556 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
867 20:14:57.898916 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 20:14:57.902463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 20:14:57.909799 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 20:14:57.913892 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 20:14:57.917395 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 20:14:57.921453 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 20:14:57.924571 0 9 12 | B1->B0 | 2828 3333 | 1 0 | (1 1) (0 0)
874 20:14:57.931842 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 20:14:57.935487 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 20:14:57.938976 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 20:14:57.942917 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 20:14:57.946503 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 20:14:57.953689 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 20:14:57.957643 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
881 20:14:57.961106 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
882 20:14:57.964759 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 20:14:57.968411 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 20:14:57.975845 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 20:14:57.979722 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 20:14:57.983055 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 20:14:57.986211 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 20:14:57.993006 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
889 20:14:57.996505 0 11 12 | B1->B0 | 3333 4444 | 0 1 | (0 0) (0 0)
890 20:14:57.999531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 20:14:58.006380 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 20:14:58.009610 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 20:14:58.013057 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 20:14:58.019765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 20:14:58.023330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 20:14:58.026683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 20:14:58.029607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 20:14:58.036427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 20:14:58.039412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 20:14:58.043105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 20:14:58.049575 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 20:14:58.052944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 20:14:58.056364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 20:14:58.062802 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 20:14:58.066393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 20:14:58.069513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 20:14:58.076382 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 20:14:58.079615 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 20:14:58.082810 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 20:14:58.089723 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 20:14:58.093187 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
912 20:14:58.096132 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 20:14:58.103060 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
914 20:14:58.106317 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
915 20:14:58.109551 Total UI for P1: 0, mck2ui 16
916 20:14:58.112854 best dqsien dly found for B0: ( 0, 14, 8)
917 20:14:58.116167 Total UI for P1: 0, mck2ui 16
918 20:14:58.119743 best dqsien dly found for B1: ( 0, 14, 14)
919 20:14:58.122776 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 20:14:58.126297 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
921 20:14:58.126746
922 20:14:58.129666 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 20:14:58.132935 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
924 20:14:58.136234 [Gating] SW calibration Done
925 20:14:58.136680 ==
926 20:14:58.139397 Dram Type= 6, Freq= 0, CH_0, rank 0
927 20:14:58.142694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 20:14:58.143145 ==
929 20:14:58.146033 RX Vref Scan: 0
930 20:14:58.146483
931 20:14:58.149441 RX Vref 0 -> 0, step: 1
932 20:14:58.149914
933 20:14:58.150270 RX Delay -130 -> 252, step: 16
934 20:14:58.155857 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
935 20:14:58.159367 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 20:14:58.162830 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 20:14:58.166275 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 20:14:58.169761 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 20:14:58.175927 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 20:14:58.179678 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 20:14:58.182647 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 20:14:58.186009 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 20:14:58.189442 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 20:14:58.195999 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 20:14:58.199743 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 20:14:58.202716 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 20:14:58.206173 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 20:14:58.209419 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 20:14:58.216327 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 20:14:58.216837 ==
951 20:14:58.219379 Dram Type= 6, Freq= 0, CH_0, rank 0
952 20:14:58.222896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 20:14:58.223380 ==
954 20:14:58.223774 DQS Delay:
955 20:14:58.226419 DQS0 = 0, DQS1 = 0
956 20:14:58.226862 DQM Delay:
957 20:14:58.229556 DQM0 = 82, DQM1 = 69
958 20:14:58.230006 DQ Delay:
959 20:14:58.233207 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
960 20:14:58.236289 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
961 20:14:58.239605 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
962 20:14:58.242999 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 20:14:58.243432
964 20:14:58.243836
965 20:14:58.244181 ==
966 20:14:58.246771 Dram Type= 6, Freq= 0, CH_0, rank 0
967 20:14:58.250217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 20:14:58.250781 ==
969 20:14:58.251152
970 20:14:58.251515
971 20:14:58.253762 TX Vref Scan disable
972 20:14:58.256863 == TX Byte 0 ==
973 20:14:58.260035 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
974 20:14:58.263190 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
975 20:14:58.266579 == TX Byte 1 ==
976 20:14:58.270206 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 20:14:58.273333 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 20:14:58.273872 ==
979 20:14:58.276535 Dram Type= 6, Freq= 0, CH_0, rank 0
980 20:14:58.279826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 20:14:58.282946 ==
982 20:14:58.294964 TX Vref=22, minBit 11, minWin=26, winSum=438
983 20:14:58.298319 TX Vref=24, minBit 5, minWin=27, winSum=440
984 20:14:58.301394 TX Vref=26, minBit 0, minWin=27, winSum=440
985 20:14:58.305009 TX Vref=28, minBit 12, minWin=27, winSum=445
986 20:14:58.308168 TX Vref=30, minBit 9, minWin=26, winSum=442
987 20:14:58.314747 TX Vref=32, minBit 9, minWin=26, winSum=441
988 20:14:58.318131 [TxChooseVref] Worse bit 12, Min win 27, Win sum 445, Final Vref 28
989 20:14:58.318572
990 20:14:58.321707 Final TX Range 1 Vref 28
991 20:14:58.322282
992 20:14:58.322767 ==
993 20:14:58.324865 Dram Type= 6, Freq= 0, CH_0, rank 0
994 20:14:58.328218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 20:14:58.328907 ==
996 20:14:58.331584
997 20:14:58.332051
998 20:14:58.332484 TX Vref Scan disable
999 20:14:58.335197 == TX Byte 0 ==
1000 20:14:58.338557 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1001 20:14:58.344809 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1002 20:14:58.345284 == TX Byte 1 ==
1003 20:14:58.348279 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1004 20:14:58.355066 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1005 20:14:58.355845
1006 20:14:58.356241 [DATLAT]
1007 20:14:58.356587 Freq=800, CH0 RK0
1008 20:14:58.356902
1009 20:14:58.358341 DATLAT Default: 0xa
1010 20:14:58.358805 0, 0xFFFF, sum = 0
1011 20:14:58.361775 1, 0xFFFF, sum = 0
1012 20:14:58.362249 2, 0xFFFF, sum = 0
1013 20:14:58.365049 3, 0xFFFF, sum = 0
1014 20:14:58.365539 4, 0xFFFF, sum = 0
1015 20:14:58.368472 5, 0xFFFF, sum = 0
1016 20:14:58.371941 6, 0xFFFF, sum = 0
1017 20:14:58.372367 7, 0xFFFF, sum = 0
1018 20:14:58.374904 8, 0xFFFF, sum = 0
1019 20:14:58.375386 9, 0x0, sum = 1
1020 20:14:58.375856 10, 0x0, sum = 2
1021 20:14:58.378526 11, 0x0, sum = 3
1022 20:14:58.379090 12, 0x0, sum = 4
1023 20:14:58.381589 best_step = 10
1024 20:14:58.382042
1025 20:14:58.382433 ==
1026 20:14:58.384913 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 20:14:58.388689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 20:14:58.389147 ==
1029 20:14:58.391780 RX Vref Scan: 1
1030 20:14:58.392223
1031 20:14:58.392589 Set Vref Range= 32 -> 127
1032 20:14:58.392910
1033 20:14:58.395224 RX Vref 32 -> 127, step: 1
1034 20:14:58.395677
1035 20:14:58.398512 RX Delay -111 -> 252, step: 8
1036 20:14:58.398960
1037 20:14:58.401823 Set Vref, RX VrefLevel [Byte0]: 32
1038 20:14:58.405037 [Byte1]: 32
1039 20:14:58.405517
1040 20:14:58.408424 Set Vref, RX VrefLevel [Byte0]: 33
1041 20:14:58.411759 [Byte1]: 33
1042 20:14:58.415502
1043 20:14:58.415953 Set Vref, RX VrefLevel [Byte0]: 34
1044 20:14:58.419220 [Byte1]: 34
1045 20:14:58.423161
1046 20:14:58.423694 Set Vref, RX VrefLevel [Byte0]: 35
1047 20:14:58.426348 [Byte1]: 35
1048 20:14:58.430749
1049 20:14:58.431203 Set Vref, RX VrefLevel [Byte0]: 36
1050 20:14:58.434170 [Byte1]: 36
1051 20:14:58.438574
1052 20:14:58.438987 Set Vref, RX VrefLevel [Byte0]: 37
1053 20:14:58.441973 [Byte1]: 37
1054 20:14:58.446167
1055 20:14:58.446621 Set Vref, RX VrefLevel [Byte0]: 38
1056 20:14:58.449291 [Byte1]: 38
1057 20:14:58.453889
1058 20:14:58.454343 Set Vref, RX VrefLevel [Byte0]: 39
1059 20:14:58.457352 [Byte1]: 39
1060 20:14:58.461527
1061 20:14:58.461978 Set Vref, RX VrefLevel [Byte0]: 40
1062 20:14:58.464791 [Byte1]: 40
1063 20:14:58.469282
1064 20:14:58.469867 Set Vref, RX VrefLevel [Byte0]: 41
1065 20:14:58.472228 [Byte1]: 41
1066 20:14:58.476811
1067 20:14:58.477251 Set Vref, RX VrefLevel [Byte0]: 42
1068 20:14:58.480104 [Byte1]: 42
1069 20:14:58.484343
1070 20:14:58.484904 Set Vref, RX VrefLevel [Byte0]: 43
1071 20:14:58.487797 [Byte1]: 43
1072 20:14:58.491791
1073 20:14:58.492235 Set Vref, RX VrefLevel [Byte0]: 44
1074 20:14:58.495243 [Byte1]: 44
1075 20:14:58.499602
1076 20:14:58.500214 Set Vref, RX VrefLevel [Byte0]: 45
1077 20:14:58.502944 [Byte1]: 45
1078 20:14:58.507786
1079 20:14:58.508234 Set Vref, RX VrefLevel [Byte0]: 46
1080 20:14:58.511074 [Byte1]: 46
1081 20:14:58.515259
1082 20:14:58.515715 Set Vref, RX VrefLevel [Byte0]: 47
1083 20:14:58.518731 [Byte1]: 47
1084 20:14:58.522837
1085 20:14:58.523249 Set Vref, RX VrefLevel [Byte0]: 48
1086 20:14:58.525911 [Byte1]: 48
1087 20:14:58.530279
1088 20:14:58.530689 Set Vref, RX VrefLevel [Byte0]: 49
1089 20:14:58.533691 [Byte1]: 49
1090 20:14:58.537579
1091 20:14:58.541200 Set Vref, RX VrefLevel [Byte0]: 50
1092 20:14:58.541657 [Byte1]: 50
1093 20:14:58.545357
1094 20:14:58.545813 Set Vref, RX VrefLevel [Byte0]: 51
1095 20:14:58.549067 [Byte1]: 51
1096 20:14:58.553117
1097 20:14:58.553572 Set Vref, RX VrefLevel [Byte0]: 52
1098 20:14:58.556186 [Byte1]: 52
1099 20:14:58.560759
1100 20:14:58.561179 Set Vref, RX VrefLevel [Byte0]: 53
1101 20:14:58.564226 [Byte1]: 53
1102 20:14:58.568456
1103 20:14:58.568874 Set Vref, RX VrefLevel [Byte0]: 54
1104 20:14:58.571863 [Byte1]: 54
1105 20:14:58.576292
1106 20:14:58.576709 Set Vref, RX VrefLevel [Byte0]: 55
1107 20:14:58.579616 [Byte1]: 55
1108 20:14:58.583795
1109 20:14:58.584215 Set Vref, RX VrefLevel [Byte0]: 56
1110 20:14:58.587196 [Byte1]: 56
1111 20:14:58.591485
1112 20:14:58.591902 Set Vref, RX VrefLevel [Byte0]: 57
1113 20:14:58.594515 [Byte1]: 57
1114 20:14:58.598935
1115 20:14:58.599353 Set Vref, RX VrefLevel [Byte0]: 58
1116 20:14:58.602315 [Byte1]: 58
1117 20:14:58.606708
1118 20:14:58.607127 Set Vref, RX VrefLevel [Byte0]: 59
1119 20:14:58.610223 [Byte1]: 59
1120 20:14:58.614191
1121 20:14:58.614610 Set Vref, RX VrefLevel [Byte0]: 60
1122 20:14:58.617570 [Byte1]: 60
1123 20:14:58.621968
1124 20:14:58.622388 Set Vref, RX VrefLevel [Byte0]: 61
1125 20:14:58.625440 [Byte1]: 61
1126 20:14:58.629555
1127 20:14:58.629977 Set Vref, RX VrefLevel [Byte0]: 62
1128 20:14:58.633056 [Byte1]: 62
1129 20:14:58.637122
1130 20:14:58.637582 Set Vref, RX VrefLevel [Byte0]: 63
1131 20:14:58.640552 [Byte1]: 63
1132 20:14:58.645047
1133 20:14:58.645620 Set Vref, RX VrefLevel [Byte0]: 64
1134 20:14:58.648221 [Byte1]: 64
1135 20:14:58.652682
1136 20:14:58.653205 Set Vref, RX VrefLevel [Byte0]: 65
1137 20:14:58.656085 [Byte1]: 65
1138 20:14:58.660304
1139 20:14:58.660867 Set Vref, RX VrefLevel [Byte0]: 66
1140 20:14:58.663445 [Byte1]: 66
1141 20:14:58.667947
1142 20:14:58.668500 Set Vref, RX VrefLevel [Byte0]: 67
1143 20:14:58.671074 [Byte1]: 67
1144 20:14:58.675409
1145 20:14:58.675832 Set Vref, RX VrefLevel [Byte0]: 68
1146 20:14:58.678853 [Byte1]: 68
1147 20:14:58.683280
1148 20:14:58.683699 Set Vref, RX VrefLevel [Byte0]: 69
1149 20:14:58.686607 [Byte1]: 69
1150 20:14:58.690998
1151 20:14:58.691417 Set Vref, RX VrefLevel [Byte0]: 70
1152 20:14:58.694168 [Byte1]: 70
1153 20:14:58.698244
1154 20:14:58.698665 Set Vref, RX VrefLevel [Byte0]: 71
1155 20:14:58.701617 [Byte1]: 71
1156 20:14:58.705945
1157 20:14:58.706365 Set Vref, RX VrefLevel [Byte0]: 72
1158 20:14:58.709329 [Byte1]: 72
1159 20:14:58.713961
1160 20:14:58.714380 Set Vref, RX VrefLevel [Byte0]: 73
1161 20:14:58.717208 [Byte1]: 73
1162 20:14:58.721370
1163 20:14:58.721876 Set Vref, RX VrefLevel [Byte0]: 74
1164 20:14:58.724655 [Byte1]: 74
1165 20:14:58.728921
1166 20:14:58.729361 Set Vref, RX VrefLevel [Byte0]: 75
1167 20:14:58.732151 [Byte1]: 75
1168 20:14:58.736552
1169 20:14:58.736989 Set Vref, RX VrefLevel [Byte0]: 76
1170 20:14:58.739868 [Byte1]: 76
1171 20:14:58.744360
1172 20:14:58.744802 Set Vref, RX VrefLevel [Byte0]: 77
1173 20:14:58.747782 [Byte1]: 77
1174 20:14:58.752052
1175 20:14:58.752494 Set Vref, RX VrefLevel [Byte0]: 78
1176 20:14:58.755259 [Byte1]: 78
1177 20:14:58.759664
1178 20:14:58.760101 Set Vref, RX VrefLevel [Byte0]: 79
1179 20:14:58.762694 [Byte1]: 79
1180 20:14:58.767335
1181 20:14:58.767772 Final RX Vref Byte 0 = 60 to rank0
1182 20:14:58.770325 Final RX Vref Byte 1 = 60 to rank0
1183 20:14:58.774039 Final RX Vref Byte 0 = 60 to rank1
1184 20:14:58.777222 Final RX Vref Byte 1 = 60 to rank1==
1185 20:14:58.780319 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 20:14:58.787300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 20:14:58.787886 ==
1188 20:14:58.788256 DQS Delay:
1189 20:14:58.788585 DQS0 = 0, DQS1 = 0
1190 20:14:58.790349 DQM Delay:
1191 20:14:58.790800 DQM0 = 81, DQM1 = 68
1192 20:14:58.793911 DQ Delay:
1193 20:14:58.797045 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 20:14:58.797536 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1195 20:14:58.800486 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1196 20:14:58.807328 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1197 20:14:58.807784
1198 20:14:58.808116
1199 20:14:58.813842 [DQSOSCAuto] RK0, (LSB)MR18= 0x2725, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1200 20:14:58.817216 CH0 RK0: MR19=606, MR18=2725
1201 20:14:58.823613 CH0_RK0: MR19=0x606, MR18=0x2725, DQSOSC=400, MR23=63, INC=92, DEC=61
1202 20:14:58.824120
1203 20:14:58.827071 ----->DramcWriteLeveling(PI) begin...
1204 20:14:58.827552 ==
1205 20:14:58.830582 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 20:14:58.833863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 20:14:58.834342 ==
1208 20:14:58.837237 Write leveling (Byte 0): 34 => 34
1209 20:14:58.840478 Write leveling (Byte 1): 31 => 31
1210 20:14:58.843869 DramcWriteLeveling(PI) end<-----
1211 20:14:58.844340
1212 20:14:58.844742 ==
1213 20:14:58.847585 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 20:14:58.850408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 20:14:58.850890 ==
1216 20:14:58.853958 [Gating] SW mode calibration
1217 20:14:58.860311 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 20:14:58.867292 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 20:14:58.870666 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 20:14:58.873829 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 20:14:58.880398 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1222 20:14:58.883903 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 20:14:58.887281 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 20:14:58.893768 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 20:14:58.897179 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 20:14:58.900495 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 20:14:58.907018 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 20:14:58.910693 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 20:14:58.913825 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 20:14:58.917328 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 20:14:58.964599 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 20:14:58.965198 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 20:14:58.966029 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 20:14:58.966377 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 20:14:58.966691 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 20:14:58.966990 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 20:14:58.967280 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1238 20:14:58.967564 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1239 20:14:58.967847 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 20:14:58.968126 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 20:14:58.972066 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 20:14:58.972489 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 20:14:58.975195 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 20:14:58.981781 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 20:14:58.985385 0 9 8 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
1246 20:14:58.988839 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 20:14:58.991972 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 20:14:58.998681 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 20:14:59.002017 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 20:14:59.005341 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 20:14:59.011980 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 20:14:59.015142 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1253 20:14:59.018603 0 10 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (0 1)
1254 20:14:59.025458 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1255 20:14:59.028591 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 20:14:59.031988 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 20:14:59.038989 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 20:14:59.041917 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 20:14:59.045341 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 20:14:59.052040 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1261 20:14:59.055418 0 11 8 | B1->B0 | 2e2e 3a3a | 1 1 | (0 0) (0 0)
1262 20:14:59.058775 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1263 20:14:59.065107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 20:14:59.068750 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 20:14:59.071762 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 20:14:59.078778 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 20:14:59.081908 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 20:14:59.086044 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 20:14:59.089806 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 20:14:59.093851 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 20:14:59.097911 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 20:14:59.104307 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 20:14:59.107977 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 20:14:59.111583 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 20:14:59.118106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 20:14:59.121625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 20:14:59.125051 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 20:14:59.131340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 20:14:59.134919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 20:14:59.137983 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 20:14:59.144790 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 20:14:59.147888 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 20:14:59.151392 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 20:14:59.154792 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 20:14:59.161284 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 20:14:59.164459 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1287 20:14:59.168039 Total UI for P1: 0, mck2ui 16
1288 20:14:59.171135 best dqsien dly found for B0: ( 0, 14, 6)
1289 20:14:59.175047 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 20:14:59.177912 Total UI for P1: 0, mck2ui 16
1291 20:14:59.181232 best dqsien dly found for B1: ( 0, 14, 10)
1292 20:14:59.184586 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1293 20:14:59.188093 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1294 20:14:59.191172
1295 20:14:59.194317 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1296 20:14:59.197703 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1297 20:14:59.201166 [Gating] SW calibration Done
1298 20:14:59.201761 ==
1299 20:14:59.204527 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 20:14:59.207697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 20:14:59.208136 ==
1302 20:14:59.208472 RX Vref Scan: 0
1303 20:14:59.208800
1304 20:14:59.211186 RX Vref 0 -> 0, step: 1
1305 20:14:59.211621
1306 20:14:59.214395 RX Delay -130 -> 252, step: 16
1307 20:14:59.218159 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1308 20:14:59.221180 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1309 20:14:59.227835 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1310 20:14:59.231222 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1311 20:14:59.234480 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1312 20:14:59.237920 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1313 20:14:59.241385 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1314 20:14:59.244362 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1315 20:14:59.251209 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1316 20:14:59.254669 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1317 20:14:59.258145 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1318 20:14:59.261150 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1319 20:14:59.267991 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1320 20:14:59.271055 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1321 20:14:59.274564 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1322 20:14:59.278051 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1323 20:14:59.278494 ==
1324 20:14:59.281118 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 20:14:59.284437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 20:14:59.288143 ==
1327 20:14:59.288592 DQS Delay:
1328 20:14:59.289064 DQS0 = 0, DQS1 = 0
1329 20:14:59.290905 DQM Delay:
1330 20:14:59.291476 DQM0 = 78, DQM1 = 69
1331 20:14:59.294217 DQ Delay:
1332 20:14:59.297606 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1333 20:14:59.298046 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
1334 20:14:59.301530 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1335 20:14:59.304233 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1336 20:14:59.307760
1337 20:14:59.308208
1338 20:14:59.308561 ==
1339 20:14:59.311111 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 20:14:59.314539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 20:14:59.315001 ==
1342 20:14:59.315342
1343 20:14:59.315656
1344 20:14:59.317809 TX Vref Scan disable
1345 20:14:59.318227 == TX Byte 0 ==
1346 20:14:59.324301 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1347 20:14:59.327745 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1348 20:14:59.328168 == TX Byte 1 ==
1349 20:14:59.334535 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1350 20:14:59.338162 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1351 20:14:59.338613 ==
1352 20:14:59.341026 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 20:14:59.344361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 20:14:59.344783 ==
1355 20:14:59.358066 TX Vref=22, minBit 11, minWin=26, winSum=433
1356 20:14:59.361435 TX Vref=24, minBit 11, minWin=26, winSum=438
1357 20:14:59.365015 TX Vref=26, minBit 1, minWin=27, winSum=438
1358 20:14:59.367991 TX Vref=28, minBit 2, minWin=27, winSum=441
1359 20:14:59.371490 TX Vref=30, minBit 2, minWin=27, winSum=443
1360 20:14:59.378053 TX Vref=32, minBit 9, minWin=26, winSum=436
1361 20:14:59.381664 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 30
1362 20:14:59.382107
1363 20:14:59.384695 Final TX Range 1 Vref 30
1364 20:14:59.385141
1365 20:14:59.385594 ==
1366 20:14:59.388189 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 20:14:59.391186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 20:14:59.394763 ==
1369 20:14:59.395105
1370 20:14:59.395343
1371 20:14:59.395572 TX Vref Scan disable
1372 20:14:59.398218 == TX Byte 0 ==
1373 20:14:59.401388 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1374 20:14:59.407881 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1375 20:14:59.408198 == TX Byte 1 ==
1376 20:14:59.411245 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1377 20:14:59.418035 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1378 20:14:59.418352
1379 20:14:59.418585 [DATLAT]
1380 20:14:59.418813 Freq=800, CH0 RK1
1381 20:14:59.419023
1382 20:14:59.421407 DATLAT Default: 0xa
1383 20:14:59.421746 0, 0xFFFF, sum = 0
1384 20:14:59.424634 1, 0xFFFF, sum = 0
1385 20:14:59.424937 2, 0xFFFF, sum = 0
1386 20:14:59.427950 3, 0xFFFF, sum = 0
1387 20:14:59.431327 4, 0xFFFF, sum = 0
1388 20:14:59.431628 5, 0xFFFF, sum = 0
1389 20:14:59.434556 6, 0xFFFF, sum = 0
1390 20:14:59.434854 7, 0xFFFF, sum = 0
1391 20:14:59.437829 8, 0xFFFF, sum = 0
1392 20:14:59.438250 9, 0x0, sum = 1
1393 20:14:59.438539 10, 0x0, sum = 2
1394 20:14:59.441290 11, 0x0, sum = 3
1395 20:14:59.441661 12, 0x0, sum = 4
1396 20:14:59.444719 best_step = 10
1397 20:14:59.445041
1398 20:14:59.445278 ==
1399 20:14:59.447758 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 20:14:59.451227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 20:14:59.451525 ==
1402 20:14:59.454366 RX Vref Scan: 0
1403 20:14:59.454683
1404 20:14:59.454936 RX Vref 0 -> 0, step: 1
1405 20:14:59.457614
1406 20:14:59.458101 RX Delay -111 -> 252, step: 8
1407 20:14:59.464945 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1408 20:14:59.468125 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1409 20:14:59.471669 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1410 20:14:59.474994 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1411 20:14:59.478196 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1412 20:14:59.484802 iDelay=209, Bit 5, Center 68 (-47 ~ 184) 232
1413 20:14:59.488146 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1414 20:14:59.491670 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1415 20:14:59.494764 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1416 20:14:59.498204 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1417 20:14:59.505004 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1418 20:14:59.508354 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1419 20:14:59.511528 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1420 20:14:59.515047 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1421 20:14:59.518425 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1422 20:14:59.524912 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1423 20:14:59.525345 ==
1424 20:14:59.528491 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 20:14:59.531662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 20:14:59.532187 ==
1427 20:14:59.532662 DQS Delay:
1428 20:14:59.534798 DQS0 = 0, DQS1 = 0
1429 20:14:59.535230 DQM Delay:
1430 20:14:59.538409 DQM0 = 79, DQM1 = 71
1431 20:14:59.538822 DQ Delay:
1432 20:14:59.541720 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1433 20:14:59.544977 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =88
1434 20:14:59.548183 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1435 20:14:59.551412 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1436 20:14:59.551845
1437 20:14:59.552223
1438 20:14:59.561789 [DQSOSCAuto] RK1, (LSB)MR18= 0x4823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1439 20:14:59.562247 CH0 RK1: MR19=606, MR18=4823
1440 20:14:59.568105 CH0_RK1: MR19=0x606, MR18=0x4823, DQSOSC=391, MR23=63, INC=96, DEC=64
1441 20:14:59.571638 [RxdqsGatingPostProcess] freq 800
1442 20:14:59.578215 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 20:14:59.581723 Pre-setting of DQS Precalculation
1444 20:14:59.585033 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 20:14:59.585447 ==
1446 20:14:59.588515 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 20:14:59.591806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 20:14:59.592249 ==
1449 20:14:59.598267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 20:14:59.604782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 20:14:59.613201 [CA 0] Center 36 (6~67) winsize 62
1452 20:14:59.616787 [CA 1] Center 36 (6~67) winsize 62
1453 20:14:59.619804 [CA 2] Center 34 (4~65) winsize 62
1454 20:14:59.623310 [CA 3] Center 34 (4~64) winsize 61
1455 20:14:59.627029 [CA 4] Center 34 (4~64) winsize 61
1456 20:14:59.630004 [CA 5] Center 34 (4~64) winsize 61
1457 20:14:59.630463
1458 20:14:59.633167 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 20:14:59.633651
1460 20:14:59.636403 [CATrainingPosCal] consider 1 rank data
1461 20:14:59.639882 u2DelayCellTimex100 = 270/100 ps
1462 20:14:59.643291 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 20:14:59.646690 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 20:14:59.653006 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 20:14:59.656225 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 20:14:59.659415 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 20:14:59.662820 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 20:14:59.662908
1469 20:14:59.665956 CA PerBit enable=1, Macro0, CA PI delay=34
1470 20:14:59.666051
1471 20:14:59.669440 [CBTSetCACLKResult] CA Dly = 34
1472 20:14:59.669533 CS Dly: 5 (0~36)
1473 20:14:59.672779 ==
1474 20:14:59.672868 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 20:14:59.679704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 20:14:59.679820 ==
1477 20:14:59.682837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 20:14:59.689467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 20:14:59.699068 [CA 0] Center 36 (6~67) winsize 62
1480 20:14:59.702650 [CA 1] Center 36 (6~67) winsize 62
1481 20:14:59.705789 [CA 2] Center 34 (4~65) winsize 62
1482 20:14:59.708950 [CA 3] Center 33 (3~64) winsize 62
1483 20:14:59.712502 [CA 4] Center 34 (4~65) winsize 62
1484 20:14:59.715902 [CA 5] Center 33 (3~64) winsize 62
1485 20:14:59.716182
1486 20:14:59.719423 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1487 20:14:59.719721
1488 20:14:59.722850 [CATrainingPosCal] consider 2 rank data
1489 20:14:59.726538 u2DelayCellTimex100 = 270/100 ps
1490 20:14:59.729408 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 20:14:59.733002 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 20:14:59.739536 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 20:14:59.743161 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 20:14:59.746961 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 20:14:59.750583 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 20:14:59.751039
1497 20:14:59.754419 CA PerBit enable=1, Macro0, CA PI delay=34
1498 20:14:59.754834
1499 20:14:59.755219 [CBTSetCACLKResult] CA Dly = 34
1500 20:14:59.758026 CS Dly: 6 (0~38)
1501 20:14:59.758697
1502 20:14:59.761893 ----->DramcWriteLeveling(PI) begin...
1503 20:14:59.762340 ==
1504 20:14:59.765105 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 20:14:59.768777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 20:14:59.769230 ==
1507 20:14:59.772383 Write leveling (Byte 0): 26 => 26
1508 20:14:59.776246 Write leveling (Byte 1): 32 => 32
1509 20:14:59.776686 DramcWriteLeveling(PI) end<-----
1510 20:14:59.779822
1511 20:14:59.780236 ==
1512 20:14:59.780567 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 20:14:59.786926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 20:14:59.787479 ==
1515 20:14:59.789892 [Gating] SW mode calibration
1516 20:14:59.796716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 20:14:59.799862 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 20:14:59.806476 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 20:14:59.809845 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 20:14:59.813426 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 20:14:59.819918 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 20:14:59.823393 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 20:14:59.826422 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 20:14:59.833216 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 20:14:59.836224 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 20:14:59.839790 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 20:14:59.846666 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 20:14:59.849528 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 20:14:59.852835 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 20:14:59.860017 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 20:14:59.862962 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 20:14:59.865998 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 20:14:59.869243 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 20:14:59.876113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 20:14:59.879415 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 20:14:59.882807 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 20:14:59.889413 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 20:14:59.892477 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 20:14:59.896075 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 20:14:59.902845 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 20:14:59.905942 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 20:14:59.909607 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 20:14:59.915949 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 20:14:59.919600 0 9 8 | B1->B0 | 2525 2828 | 1 1 | (1 1) (1 1)
1545 20:14:59.922799 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 20:14:59.929572 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 20:14:59.932982 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 20:14:59.936212 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 20:14:59.939720 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 20:14:59.946328 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 20:14:59.949428 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1552 20:14:59.952820 0 10 8 | B1->B0 | 2f2f 2e2e | 0 1 | (0 0) (1 0)
1553 20:14:59.959445 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 20:14:59.962959 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 20:14:59.966326 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 20:14:59.972924 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 20:14:59.976518 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 20:14:59.979376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 20:14:59.986412 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1560 20:14:59.989398 0 11 8 | B1->B0 | 3636 3737 | 0 1 | (0 0) (0 0)
1561 20:14:59.992627 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 20:14:59.999480 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 20:15:00.002827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 20:15:00.006272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 20:15:00.012732 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 20:15:00.016219 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 20:15:00.019542 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 20:15:00.026273 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 20:15:00.029512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 20:15:00.032728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 20:15:00.036327 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 20:15:00.042850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 20:15:00.046354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 20:15:00.049654 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 20:15:00.056242 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 20:15:00.059407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 20:15:00.062721 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 20:15:00.069559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 20:15:00.072717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 20:15:00.076182 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 20:15:00.082797 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 20:15:00.086130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 20:15:00.089793 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 20:15:00.096175 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 20:15:00.096254 Total UI for P1: 0, mck2ui 16
1586 20:15:00.102766 best dqsien dly found for B0: ( 0, 14, 6)
1587 20:15:00.102848 Total UI for P1: 0, mck2ui 16
1588 20:15:00.106099 best dqsien dly found for B1: ( 0, 14, 6)
1589 20:15:00.112732 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1590 20:15:00.116373 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1591 20:15:00.116447
1592 20:15:00.119654 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 20:15:00.122922 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1594 20:15:00.126248 [Gating] SW calibration Done
1595 20:15:00.126321 ==
1596 20:15:00.129429 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 20:15:00.132671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 20:15:00.132743 ==
1599 20:15:00.136072 RX Vref Scan: 0
1600 20:15:00.136142
1601 20:15:00.136202 RX Vref 0 -> 0, step: 1
1602 20:15:00.136268
1603 20:15:00.139198 RX Delay -130 -> 252, step: 16
1604 20:15:00.142605 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1605 20:15:00.149181 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1606 20:15:00.152754 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1607 20:15:00.155886 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1608 20:15:00.159444 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1609 20:15:00.162739 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1610 20:15:00.166119 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1611 20:15:00.172750 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1612 20:15:00.175915 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1613 20:15:00.179287 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1614 20:15:00.182713 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1615 20:15:00.186109 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1616 20:15:00.192607 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1617 20:15:00.195743 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1618 20:15:00.199240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1619 20:15:00.202676 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1620 20:15:00.202749 ==
1621 20:15:00.205648 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 20:15:00.212514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 20:15:00.212617 ==
1624 20:15:00.212707 DQS Delay:
1625 20:15:00.215958 DQS0 = 0, DQS1 = 0
1626 20:15:00.216055 DQM Delay:
1627 20:15:00.216144 DQM0 = 82, DQM1 = 76
1628 20:15:00.219007 DQ Delay:
1629 20:15:00.222437 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1630 20:15:00.225968 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1631 20:15:00.229241 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1632 20:15:00.232546 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1633 20:15:00.232629
1634 20:15:00.232713
1635 20:15:00.232791 ==
1636 20:15:00.235991 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 20:15:00.239245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 20:15:00.239353 ==
1639 20:15:00.239437
1640 20:15:00.239516
1641 20:15:00.242382 TX Vref Scan disable
1642 20:15:00.242465 == TX Byte 0 ==
1643 20:15:00.249360 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 20:15:00.252521 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 20:15:00.252629 == TX Byte 1 ==
1646 20:15:00.259006 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1647 20:15:00.262386 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1648 20:15:00.262469 ==
1649 20:15:00.265745 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 20:15:00.269124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 20:15:00.269232 ==
1652 20:15:00.283762 TX Vref=22, minBit 1, minWin=27, winSum=444
1653 20:15:00.287206 TX Vref=24, minBit 6, minWin=27, winSum=444
1654 20:15:00.290274 TX Vref=26, minBit 1, minWin=27, winSum=446
1655 20:15:00.293728 TX Vref=28, minBit 8, minWin=27, winSum=451
1656 20:15:00.297150 TX Vref=30, minBit 5, minWin=27, winSum=447
1657 20:15:00.303795 TX Vref=32, minBit 5, minWin=27, winSum=447
1658 20:15:00.307334 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1659 20:15:00.307446
1660 20:15:00.310381 Final TX Range 1 Vref 28
1661 20:15:00.310467
1662 20:15:00.310551 ==
1663 20:15:00.313470 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 20:15:00.316921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 20:15:00.317004 ==
1666 20:15:00.320627
1667 20:15:00.320709
1668 20:15:00.320793 TX Vref Scan disable
1669 20:15:00.324116 == TX Byte 0 ==
1670 20:15:00.327421 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 20:15:00.330831 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 20:15:00.333854 == TX Byte 1 ==
1673 20:15:00.337421 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1674 20:15:00.340682 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1675 20:15:00.340783
1676 20:15:00.343924 [DATLAT]
1677 20:15:00.344018 Freq=800, CH1 RK0
1678 20:15:00.344102
1679 20:15:00.347472 DATLAT Default: 0xa
1680 20:15:00.347555 0, 0xFFFF, sum = 0
1681 20:15:00.350477 1, 0xFFFF, sum = 0
1682 20:15:00.350562 2, 0xFFFF, sum = 0
1683 20:15:00.353892 3, 0xFFFF, sum = 0
1684 20:15:00.353977 4, 0xFFFF, sum = 0
1685 20:15:00.357184 5, 0xFFFF, sum = 0
1686 20:15:00.357294 6, 0xFFFF, sum = 0
1687 20:15:00.360763 7, 0xFFFF, sum = 0
1688 20:15:00.360847 8, 0xFFFF, sum = 0
1689 20:15:00.364094 9, 0x0, sum = 1
1690 20:15:00.364179 10, 0x0, sum = 2
1691 20:15:00.367423 11, 0x0, sum = 3
1692 20:15:00.367508 12, 0x0, sum = 4
1693 20:15:00.370580 best_step = 10
1694 20:15:00.370662
1695 20:15:00.370746 ==
1696 20:15:00.373989 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 20:15:00.377237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 20:15:00.377328 ==
1699 20:15:00.380604 RX Vref Scan: 1
1700 20:15:00.380679
1701 20:15:00.380763 Set Vref Range= 32 -> 127
1702 20:15:00.380842
1703 20:15:00.383869 RX Vref 32 -> 127, step: 1
1704 20:15:00.383953
1705 20:15:00.387534 RX Delay -111 -> 252, step: 8
1706 20:15:00.387617
1707 20:15:00.390931 Set Vref, RX VrefLevel [Byte0]: 32
1708 20:15:00.394224 [Byte1]: 32
1709 20:15:00.394307
1710 20:15:00.397275 Set Vref, RX VrefLevel [Byte0]: 33
1711 20:15:00.400934 [Byte1]: 33
1712 20:15:00.404330
1713 20:15:00.404404 Set Vref, RX VrefLevel [Byte0]: 34
1714 20:15:00.407491 [Byte1]: 34
1715 20:15:00.411906
1716 20:15:00.412003 Set Vref, RX VrefLevel [Byte0]: 35
1717 20:15:00.415353 [Byte1]: 35
1718 20:15:00.419618
1719 20:15:00.419722 Set Vref, RX VrefLevel [Byte0]: 36
1720 20:15:00.426272 [Byte1]: 36
1721 20:15:00.426395
1722 20:15:00.429489 Set Vref, RX VrefLevel [Byte0]: 37
1723 20:15:00.432795 [Byte1]: 37
1724 20:15:00.432974
1725 20:15:00.436114 Set Vref, RX VrefLevel [Byte0]: 38
1726 20:15:00.439721 [Byte1]: 38
1727 20:15:00.442910
1728 20:15:00.443098 Set Vref, RX VrefLevel [Byte0]: 39
1729 20:15:00.446176 [Byte1]: 39
1730 20:15:00.450301
1731 20:15:00.450542 Set Vref, RX VrefLevel [Byte0]: 40
1732 20:15:00.453523 [Byte1]: 40
1733 20:15:00.457889
1734 20:15:00.458192 Set Vref, RX VrefLevel [Byte0]: 41
1735 20:15:00.461393 [Byte1]: 41
1736 20:15:00.465845
1737 20:15:00.466271 Set Vref, RX VrefLevel [Byte0]: 42
1738 20:15:00.468936 [Byte1]: 42
1739 20:15:00.473277
1740 20:15:00.473806 Set Vref, RX VrefLevel [Byte0]: 43
1741 20:15:00.476734 [Byte1]: 43
1742 20:15:00.481076
1743 20:15:00.481776 Set Vref, RX VrefLevel [Byte0]: 44
1744 20:15:00.484261 [Byte1]: 44
1745 20:15:00.488781
1746 20:15:00.489234 Set Vref, RX VrefLevel [Byte0]: 45
1747 20:15:00.492108 [Byte1]: 45
1748 20:15:00.496520
1749 20:15:00.496935 Set Vref, RX VrefLevel [Byte0]: 46
1750 20:15:00.500030 [Byte1]: 46
1751 20:15:00.504347
1752 20:15:00.504757 Set Vref, RX VrefLevel [Byte0]: 47
1753 20:15:00.507219 [Byte1]: 47
1754 20:15:00.511657
1755 20:15:00.512066 Set Vref, RX VrefLevel [Byte0]: 48
1756 20:15:00.514951 [Byte1]: 48
1757 20:15:00.519220
1758 20:15:00.519635 Set Vref, RX VrefLevel [Byte0]: 49
1759 20:15:00.522872 [Byte1]: 49
1760 20:15:00.527121
1761 20:15:00.527655 Set Vref, RX VrefLevel [Byte0]: 50
1762 20:15:00.530571 [Byte1]: 50
1763 20:15:00.534668
1764 20:15:00.535078 Set Vref, RX VrefLevel [Byte0]: 51
1765 20:15:00.537881 [Byte1]: 51
1766 20:15:00.542158
1767 20:15:00.542539 Set Vref, RX VrefLevel [Byte0]: 52
1768 20:15:00.545885 [Byte1]: 52
1769 20:15:00.549987
1770 20:15:00.550435 Set Vref, RX VrefLevel [Byte0]: 53
1771 20:15:00.553323 [Byte1]: 53
1772 20:15:00.557530
1773 20:15:00.558196 Set Vref, RX VrefLevel [Byte0]: 54
1774 20:15:00.561048 [Byte1]: 54
1775 20:15:00.565338
1776 20:15:00.565955 Set Vref, RX VrefLevel [Byte0]: 55
1777 20:15:00.568668 [Byte1]: 55
1778 20:15:00.573158
1779 20:15:00.573785 Set Vref, RX VrefLevel [Byte0]: 56
1780 20:15:00.576236 [Byte1]: 56
1781 20:15:00.580526
1782 20:15:00.581058 Set Vref, RX VrefLevel [Byte0]: 57
1783 20:15:00.583776 [Byte1]: 57
1784 20:15:00.588086
1785 20:15:00.588538 Set Vref, RX VrefLevel [Byte0]: 58
1786 20:15:00.591467 [Byte1]: 58
1787 20:15:00.595984
1788 20:15:00.596436 Set Vref, RX VrefLevel [Byte0]: 59
1789 20:15:00.599166 [Byte1]: 59
1790 20:15:00.603340
1791 20:15:00.603834 Set Vref, RX VrefLevel [Byte0]: 60
1792 20:15:00.606873 [Byte1]: 60
1793 20:15:00.611258
1794 20:15:00.611800 Set Vref, RX VrefLevel [Byte0]: 61
1795 20:15:00.614682 [Byte1]: 61
1796 20:15:00.618952
1797 20:15:00.619402 Set Vref, RX VrefLevel [Byte0]: 62
1798 20:15:00.622318 [Byte1]: 62
1799 20:15:00.626522
1800 20:15:00.627000 Set Vref, RX VrefLevel [Byte0]: 63
1801 20:15:00.629731 [Byte1]: 63
1802 20:15:00.634291
1803 20:15:00.634765 Set Vref, RX VrefLevel [Byte0]: 64
1804 20:15:00.637689 [Byte1]: 64
1805 20:15:00.641898
1806 20:15:00.642507 Set Vref, RX VrefLevel [Byte0]: 65
1807 20:15:00.645131 [Byte1]: 65
1808 20:15:00.649607
1809 20:15:00.650114 Set Vref, RX VrefLevel [Byte0]: 66
1810 20:15:00.652684 [Byte1]: 66
1811 20:15:00.656828
1812 20:15:00.657275 Set Vref, RX VrefLevel [Byte0]: 67
1813 20:15:00.660150 [Byte1]: 67
1814 20:15:00.664555
1815 20:15:00.664959 Set Vref, RX VrefLevel [Byte0]: 68
1816 20:15:00.667726 [Byte1]: 68
1817 20:15:00.672337
1818 20:15:00.672765 Set Vref, RX VrefLevel [Byte0]: 69
1819 20:15:00.675757 [Byte1]: 69
1820 20:15:00.679886
1821 20:15:00.680315 Set Vref, RX VrefLevel [Byte0]: 70
1822 20:15:00.683254 [Byte1]: 70
1823 20:15:00.687487
1824 20:15:00.687984 Set Vref, RX VrefLevel [Byte0]: 71
1825 20:15:00.690741 [Byte1]: 71
1826 20:15:00.695081
1827 20:15:00.695522 Set Vref, RX VrefLevel [Byte0]: 72
1828 20:15:00.698620 [Byte1]: 72
1829 20:15:00.702855
1830 20:15:00.703280 Set Vref, RX VrefLevel [Byte0]: 73
1831 20:15:00.706150 [Byte1]: 73
1832 20:15:00.710756
1833 20:15:00.711186 Set Vref, RX VrefLevel [Byte0]: 74
1834 20:15:00.713962 [Byte1]: 74
1835 20:15:00.718070
1836 20:15:00.718577 Set Vref, RX VrefLevel [Byte0]: 75
1837 20:15:00.721871 [Byte1]: 75
1838 20:15:00.726002
1839 20:15:00.726429 Set Vref, RX VrefLevel [Byte0]: 76
1840 20:15:00.729058 [Byte1]: 76
1841 20:15:00.733593
1842 20:15:00.734026 Final RX Vref Byte 0 = 58 to rank0
1843 20:15:00.736863 Final RX Vref Byte 1 = 56 to rank0
1844 20:15:00.740252 Final RX Vref Byte 0 = 58 to rank1
1845 20:15:00.743609 Final RX Vref Byte 1 = 56 to rank1==
1846 20:15:00.746863 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 20:15:00.753602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 20:15:00.754052 ==
1849 20:15:00.754399 DQS Delay:
1850 20:15:00.754735 DQS0 = 0, DQS1 = 0
1851 20:15:00.756602 DQM Delay:
1852 20:15:00.757041 DQM0 = 81, DQM1 = 71
1853 20:15:00.760098 DQ Delay:
1854 20:15:00.763714 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1855 20:15:00.766602 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1856 20:15:00.767021 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1857 20:15:00.773639 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1858 20:15:00.774055
1859 20:15:00.774385
1860 20:15:00.779982 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1861 20:15:00.783250 CH1 RK0: MR19=606, MR18=E18
1862 20:15:00.790094 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1863 20:15:00.790604
1864 20:15:00.793211 ----->DramcWriteLeveling(PI) begin...
1865 20:15:00.793830 ==
1866 20:15:00.796618 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 20:15:00.799972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 20:15:00.800392 ==
1869 20:15:00.803330 Write leveling (Byte 0): 27 => 27
1870 20:15:00.806603 Write leveling (Byte 1): 32 => 32
1871 20:15:00.809846 DramcWriteLeveling(PI) end<-----
1872 20:15:00.810265
1873 20:15:00.810595 ==
1874 20:15:00.813183 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 20:15:00.816345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 20:15:00.816766 ==
1877 20:15:00.819769 [Gating] SW mode calibration
1878 20:15:00.826502 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 20:15:00.833260 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 20:15:00.836750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1881 20:15:00.839877 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1882 20:15:00.846679 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 20:15:00.850099 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 20:15:00.853175 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 20:15:00.860075 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 20:15:00.863491 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 20:15:00.866650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 20:15:00.874839 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 20:15:00.876413 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 20:15:00.879688 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 20:15:00.886338 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 20:15:00.890356 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 20:15:00.893234 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 20:15:00.896601 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 20:15:00.903163 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 20:15:00.906552 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 20:15:00.909992 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1898 20:15:00.916587 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 20:15:00.919879 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 20:15:00.923169 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 20:15:00.929738 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 20:15:00.933105 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 20:15:00.936396 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 20:15:00.942976 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 20:15:00.946519 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1906 20:15:00.949800 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1907 20:15:00.956243 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 20:15:00.959576 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 20:15:00.962825 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 20:15:00.969639 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 20:15:00.972897 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 20:15:00.976085 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 20:15:00.983063 0 10 4 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (0 1)
1914 20:15:00.986143 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1915 20:15:00.989695 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 20:15:00.996270 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 20:15:00.999579 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 20:15:01.003059 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 20:15:01.006444 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 20:15:01.012877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 20:15:01.016439 0 11 4 | B1->B0 | 2727 3434 | 0 0 | (0 0) (1 1)
1922 20:15:01.019562 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1923 20:15:01.026542 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 20:15:01.029948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 20:15:01.032999 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 20:15:01.039822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 20:15:01.042977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 20:15:01.046438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 20:15:01.053194 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1930 20:15:01.056377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1931 20:15:01.059850 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 20:15:01.066855 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 20:15:01.069825 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 20:15:01.073422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 20:15:01.079847 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 20:15:01.082857 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 20:15:01.086411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 20:15:01.093005 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 20:15:01.096320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 20:15:01.099765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 20:15:01.103177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 20:15:01.110017 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 20:15:01.113215 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 20:15:01.116246 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1945 20:15:01.122916 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 20:15:01.126388 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1947 20:15:01.129426 Total UI for P1: 0, mck2ui 16
1948 20:15:01.132914 best dqsien dly found for B0: ( 0, 14, 2)
1949 20:15:01.136074 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1950 20:15:01.139098 Total UI for P1: 0, mck2ui 16
1951 20:15:01.142631 best dqsien dly found for B1: ( 0, 14, 6)
1952 20:15:01.145689 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1953 20:15:01.149180 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1954 20:15:01.149267
1955 20:15:01.155816 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1956 20:15:01.159216 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1957 20:15:01.159299 [Gating] SW calibration Done
1958 20:15:01.162618 ==
1959 20:15:01.165797 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 20:15:01.168966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 20:15:01.169048 ==
1962 20:15:01.169114 RX Vref Scan: 0
1963 20:15:01.169175
1964 20:15:01.172668 RX Vref 0 -> 0, step: 1
1965 20:15:01.172750
1966 20:15:01.175846 RX Delay -130 -> 252, step: 16
1967 20:15:01.179153 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1968 20:15:01.182738 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1969 20:15:01.186110 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1970 20:15:01.192702 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1971 20:15:01.195810 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1972 20:15:01.199400 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1973 20:15:01.202409 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1974 20:15:01.205840 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1975 20:15:01.212749 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1976 20:15:01.216114 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1977 20:15:01.219362 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1978 20:15:01.222729 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1979 20:15:01.225778 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1980 20:15:01.232660 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1981 20:15:01.235774 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1982 20:15:01.239115 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1983 20:15:01.239197 ==
1984 20:15:01.242557 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 20:15:01.245885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 20:15:01.249179 ==
1987 20:15:01.249261 DQS Delay:
1988 20:15:01.249326 DQS0 = 0, DQS1 = 0
1989 20:15:01.252471 DQM Delay:
1990 20:15:01.252553 DQM0 = 78, DQM1 = 71
1991 20:15:01.255854 DQ Delay:
1992 20:15:01.255936 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1993 20:15:01.259171 DQ4 =69, DQ5 =93, DQ6 =93, DQ7 =77
1994 20:15:01.262215 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1995 20:15:01.265723 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1996 20:15:01.265806
1997 20:15:01.269099
1998 20:15:01.269181 ==
1999 20:15:01.272322 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 20:15:01.275847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 20:15:01.275929 ==
2002 20:15:01.275993
2003 20:15:01.276054
2004 20:15:01.279062 TX Vref Scan disable
2005 20:15:01.279144 == TX Byte 0 ==
2006 20:15:01.285869 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 20:15:01.289047 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 20:15:01.289129 == TX Byte 1 ==
2009 20:15:01.295763 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2010 20:15:01.298859 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2011 20:15:01.298942 ==
2012 20:15:01.302426 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 20:15:01.305757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 20:15:01.305839 ==
2015 20:15:01.319611 TX Vref=22, minBit 2, minWin=27, winSum=447
2016 20:15:01.322848 TX Vref=24, minBit 1, minWin=28, winSum=453
2017 20:15:01.326412 TX Vref=26, minBit 1, minWin=28, winSum=457
2018 20:15:01.329539 TX Vref=28, minBit 0, minWin=28, winSum=457
2019 20:15:01.332641 TX Vref=30, minBit 5, minWin=27, winSum=458
2020 20:15:01.339854 TX Vref=32, minBit 1, minWin=27, winSum=456
2021 20:15:01.342777 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
2022 20:15:01.342859
2023 20:15:01.346209 Final TX Range 1 Vref 26
2024 20:15:01.346291
2025 20:15:01.346357 ==
2026 20:15:01.349414 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 20:15:01.352630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 20:15:01.352713 ==
2029 20:15:01.356154
2030 20:15:01.356234
2031 20:15:01.356300 TX Vref Scan disable
2032 20:15:01.359566 == TX Byte 0 ==
2033 20:15:01.362751 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 20:15:01.369497 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 20:15:01.369583 == TX Byte 1 ==
2036 20:15:01.372598 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2037 20:15:01.379527 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2038 20:15:01.379610
2039 20:15:01.379675 [DATLAT]
2040 20:15:01.379735 Freq=800, CH1 RK1
2041 20:15:01.379794
2042 20:15:01.382868 DATLAT Default: 0xa
2043 20:15:01.382950 0, 0xFFFF, sum = 0
2044 20:15:01.386106 1, 0xFFFF, sum = 0
2045 20:15:01.386189 2, 0xFFFF, sum = 0
2046 20:15:01.389392 3, 0xFFFF, sum = 0
2047 20:15:01.389497 4, 0xFFFF, sum = 0
2048 20:15:01.392722 5, 0xFFFF, sum = 0
2049 20:15:01.396396 6, 0xFFFF, sum = 0
2050 20:15:01.396479 7, 0xFFFF, sum = 0
2051 20:15:01.399582 8, 0xFFFF, sum = 0
2052 20:15:01.399665 9, 0x0, sum = 1
2053 20:15:01.399731 10, 0x0, sum = 2
2054 20:15:01.402705 11, 0x0, sum = 3
2055 20:15:01.402788 12, 0x0, sum = 4
2056 20:15:01.406232 best_step = 10
2057 20:15:01.406322
2058 20:15:01.406388 ==
2059 20:15:01.409447 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 20:15:01.412836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 20:15:01.412918 ==
2062 20:15:01.416017 RX Vref Scan: 0
2063 20:15:01.416099
2064 20:15:01.416164 RX Vref 0 -> 0, step: 1
2065 20:15:01.416224
2066 20:15:01.419220 RX Delay -111 -> 252, step: 8
2067 20:15:01.426517 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2068 20:15:01.429895 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2069 20:15:01.433142 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2070 20:15:01.436198 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2071 20:15:01.439453 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2072 20:15:01.446389 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2073 20:15:01.449524 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2074 20:15:01.453101 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2075 20:15:01.456091 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2076 20:15:01.459501 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2077 20:15:01.466172 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2078 20:15:01.469597 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2079 20:15:01.473198 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2080 20:15:01.476255 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2081 20:15:01.479631 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2082 20:15:01.486566 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2083 20:15:01.486649 ==
2084 20:15:01.489430 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 20:15:01.493065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 20:15:01.493147 ==
2087 20:15:01.493213 DQS Delay:
2088 20:15:01.496333 DQS0 = 0, DQS1 = 0
2089 20:15:01.496414 DQM Delay:
2090 20:15:01.499581 DQM0 = 77, DQM1 = 73
2091 20:15:01.499663 DQ Delay:
2092 20:15:01.502838 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2093 20:15:01.506390 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2094 20:15:01.509472 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2095 20:15:01.513018 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2096 20:15:01.513099
2097 20:15:01.513163
2098 20:15:01.519519 [DQSOSCAuto] RK1, (LSB)MR18= 0x233b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2099 20:15:01.522907 CH1 RK1: MR19=606, MR18=233B
2100 20:15:01.529514 CH1_RK1: MR19=0x606, MR18=0x233B, DQSOSC=394, MR23=63, INC=95, DEC=63
2101 20:15:01.533030 [RxdqsGatingPostProcess] freq 800
2102 20:15:01.539584 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 20:15:01.542862 Pre-setting of DQS Precalculation
2104 20:15:01.545965 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 20:15:01.552923 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 20:15:01.559577 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 20:15:01.559659
2108 20:15:01.562657
2109 20:15:01.562739 [Calibration Summary] 1600 Mbps
2110 20:15:01.566152 CH 0, Rank 0
2111 20:15:01.566233 SW Impedance : PASS
2112 20:15:01.569452 DUTY Scan : NO K
2113 20:15:01.572996 ZQ Calibration : PASS
2114 20:15:01.573078 Jitter Meter : NO K
2115 20:15:01.576029 CBT Training : PASS
2116 20:15:01.579227 Write leveling : PASS
2117 20:15:01.579309 RX DQS gating : PASS
2118 20:15:01.582620 RX DQ/DQS(RDDQC) : PASS
2119 20:15:01.585882 TX DQ/DQS : PASS
2120 20:15:01.585965 RX DATLAT : PASS
2121 20:15:01.589460 RX DQ/DQS(Engine): PASS
2122 20:15:01.592540 TX OE : NO K
2123 20:15:01.592621 All Pass.
2124 20:15:01.592686
2125 20:15:01.592746 CH 0, Rank 1
2126 20:15:01.595917 SW Impedance : PASS
2127 20:15:01.599230 DUTY Scan : NO K
2128 20:15:01.599313 ZQ Calibration : PASS
2129 20:15:01.602468 Jitter Meter : NO K
2130 20:15:01.602550 CBT Training : PASS
2131 20:15:01.605908 Write leveling : PASS
2132 20:15:01.609189 RX DQS gating : PASS
2133 20:15:01.609271 RX DQ/DQS(RDDQC) : PASS
2134 20:15:01.612659 TX DQ/DQS : PASS
2135 20:15:01.615951 RX DATLAT : PASS
2136 20:15:01.616033 RX DQ/DQS(Engine): PASS
2137 20:15:01.619352 TX OE : NO K
2138 20:15:01.619467 All Pass.
2139 20:15:01.619534
2140 20:15:01.622650 CH 1, Rank 0
2141 20:15:01.622732 SW Impedance : PASS
2142 20:15:01.625885 DUTY Scan : NO K
2143 20:15:01.629383 ZQ Calibration : PASS
2144 20:15:01.629464 Jitter Meter : NO K
2145 20:15:01.632646 CBT Training : PASS
2146 20:15:01.635839 Write leveling : PASS
2147 20:15:01.635921 RX DQS gating : PASS
2148 20:15:01.639373 RX DQ/DQS(RDDQC) : PASS
2149 20:15:01.639454 TX DQ/DQS : PASS
2150 20:15:01.642536 RX DATLAT : PASS
2151 20:15:01.645959 RX DQ/DQS(Engine): PASS
2152 20:15:01.646041 TX OE : NO K
2153 20:15:01.649408 All Pass.
2154 20:15:01.649530
2155 20:15:01.649595 CH 1, Rank 1
2156 20:15:01.652909 SW Impedance : PASS
2157 20:15:01.652990 DUTY Scan : NO K
2158 20:15:01.655930 ZQ Calibration : PASS
2159 20:15:01.659177 Jitter Meter : NO K
2160 20:15:01.659260 CBT Training : PASS
2161 20:15:01.662582 Write leveling : PASS
2162 20:15:01.665963 RX DQS gating : PASS
2163 20:15:01.666046 RX DQ/DQS(RDDQC) : PASS
2164 20:15:01.669090 TX DQ/DQS : PASS
2165 20:15:01.672712 RX DATLAT : PASS
2166 20:15:01.672795 RX DQ/DQS(Engine): PASS
2167 20:15:01.676158 TX OE : NO K
2168 20:15:01.676241 All Pass.
2169 20:15:01.676306
2170 20:15:01.679435 DramC Write-DBI off
2171 20:15:01.682602 PER_BANK_REFRESH: Hybrid Mode
2172 20:15:01.682684 TX_TRACKING: ON
2173 20:15:01.685957 [GetDramInforAfterCalByMRR] Vendor 6.
2174 20:15:01.689334 [GetDramInforAfterCalByMRR] Revision 606.
2175 20:15:01.692714 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 20:15:01.696189 MR0 0x3b3b
2177 20:15:01.696270 MR8 0x5151
2178 20:15:01.699143 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 20:15:01.699225
2180 20:15:01.699290 MR0 0x3b3b
2181 20:15:01.702523 MR8 0x5151
2182 20:15:01.706046 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 20:15:01.706128
2184 20:15:01.712779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 20:15:01.719655 [FAST_K] Save calibration result to emmc
2186 20:15:01.722555 [FAST_K] Save calibration result to emmc
2187 20:15:01.722637 dram_init: config_dvfs: 1
2188 20:15:01.726146 dramc_set_vcore_voltage set vcore to 662500
2189 20:15:01.729192 Read voltage for 1200, 2
2190 20:15:01.729274 Vio18 = 0
2191 20:15:01.732600 Vcore = 662500
2192 20:15:01.732682 Vdram = 0
2193 20:15:01.732747 Vddq = 0
2194 20:15:01.736325 Vmddr = 0
2195 20:15:01.739566 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 20:15:01.745823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 20:15:01.745905 MEM_TYPE=3, freq_sel=15
2198 20:15:01.749419 sv_algorithm_assistance_LP4_1600
2199 20:15:01.755933 ============ PULL DRAM RESETB DOWN ============
2200 20:15:01.759018 ========== PULL DRAM RESETB DOWN end =========
2201 20:15:01.762393 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 20:15:01.765901 ===================================
2203 20:15:01.769166 LPDDR4 DRAM CONFIGURATION
2204 20:15:01.772714 ===================================
2205 20:15:01.775691 EX_ROW_EN[0] = 0x0
2206 20:15:01.775773 EX_ROW_EN[1] = 0x0
2207 20:15:01.779331 LP4Y_EN = 0x0
2208 20:15:01.779413 WORK_FSP = 0x0
2209 20:15:01.782632 WL = 0x4
2210 20:15:01.782713 RL = 0x4
2211 20:15:01.785684 BL = 0x2
2212 20:15:01.785766 RPST = 0x0
2213 20:15:01.788950 RD_PRE = 0x0
2214 20:15:01.789035 WR_PRE = 0x1
2215 20:15:01.792634 WR_PST = 0x0
2216 20:15:01.792716 DBI_WR = 0x0
2217 20:15:01.795647 DBI_RD = 0x0
2218 20:15:01.795729 OTF = 0x1
2219 20:15:01.799292 ===================================
2220 20:15:01.802261 ===================================
2221 20:15:01.806089 ANA top config
2222 20:15:01.809060 ===================================
2223 20:15:01.812448 DLL_ASYNC_EN = 0
2224 20:15:01.812565 ALL_SLAVE_EN = 0
2225 20:15:01.815885 NEW_RANK_MODE = 1
2226 20:15:01.819162 DLL_IDLE_MODE = 1
2227 20:15:01.822366 LP45_APHY_COMB_EN = 1
2228 20:15:01.822447 TX_ODT_DIS = 1
2229 20:15:01.825863 NEW_8X_MODE = 1
2230 20:15:01.829251 ===================================
2231 20:15:01.832680 ===================================
2232 20:15:01.835696 data_rate = 2400
2233 20:15:01.839430 CKR = 1
2234 20:15:01.842473 DQ_P2S_RATIO = 8
2235 20:15:01.845940 ===================================
2236 20:15:01.846022 CA_P2S_RATIO = 8
2237 20:15:01.849197 DQ_CA_OPEN = 0
2238 20:15:01.852725 DQ_SEMI_OPEN = 0
2239 20:15:01.856086 CA_SEMI_OPEN = 0
2240 20:15:01.859294 CA_FULL_RATE = 0
2241 20:15:01.862640 DQ_CKDIV4_EN = 0
2242 20:15:01.862733 CA_CKDIV4_EN = 0
2243 20:15:01.866053 CA_PREDIV_EN = 0
2244 20:15:01.869212 PH8_DLY = 17
2245 20:15:01.872705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 20:15:01.876104 DQ_AAMCK_DIV = 4
2247 20:15:01.879202 CA_AAMCK_DIV = 4
2248 20:15:01.879323 CA_ADMCK_DIV = 4
2249 20:15:01.882518 DQ_TRACK_CA_EN = 0
2250 20:15:01.886132 CA_PICK = 1200
2251 20:15:01.889466 CA_MCKIO = 1200
2252 20:15:01.892574 MCKIO_SEMI = 0
2253 20:15:01.896090 PLL_FREQ = 2366
2254 20:15:01.899208 DQ_UI_PI_RATIO = 32
2255 20:15:01.899289 CA_UI_PI_RATIO = 0
2256 20:15:01.902759 ===================================
2257 20:15:01.905978 ===================================
2258 20:15:01.909577 memory_type:LPDDR4
2259 20:15:01.912574 GP_NUM : 10
2260 20:15:01.912715 SRAM_EN : 1
2261 20:15:01.916087 MD32_EN : 0
2262 20:15:01.919443 ===================================
2263 20:15:01.922422 [ANA_INIT] >>>>>>>>>>>>>>
2264 20:15:01.925997 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 20:15:01.929407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 20:15:01.932622 ===================================
2267 20:15:01.932703 data_rate = 2400,PCW = 0X5b00
2268 20:15:01.936049 ===================================
2269 20:15:01.939450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 20:15:01.945926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 20:15:01.952405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 20:15:01.955885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 20:15:01.959285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 20:15:01.962454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 20:15:01.965784 [ANA_INIT] flow start
2276 20:15:01.965866 [ANA_INIT] PLL >>>>>>>>
2277 20:15:01.969126 [ANA_INIT] PLL <<<<<<<<
2278 20:15:01.972522 [ANA_INIT] MIDPI >>>>>>>>
2279 20:15:01.975969 [ANA_INIT] MIDPI <<<<<<<<
2280 20:15:01.976050 [ANA_INIT] DLL >>>>>>>>
2281 20:15:01.979101 [ANA_INIT] DLL <<<<<<<<
2282 20:15:01.979182 [ANA_INIT] flow end
2283 20:15:01.985781 ============ LP4 DIFF to SE enter ============
2284 20:15:01.989187 ============ LP4 DIFF to SE exit ============
2285 20:15:01.992493 [ANA_INIT] <<<<<<<<<<<<<
2286 20:15:01.995928 [Flow] Enable top DCM control >>>>>
2287 20:15:01.999102 [Flow] Enable top DCM control <<<<<
2288 20:15:02.002603 Enable DLL master slave shuffle
2289 20:15:02.006032 ==============================================================
2290 20:15:02.009278 Gating Mode config
2291 20:15:02.012304 ==============================================================
2292 20:15:02.016102 Config description:
2293 20:15:02.025712 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 20:15:02.032467 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 20:15:02.035986 SELPH_MODE 0: By rank 1: By Phase
2296 20:15:02.042591 ==============================================================
2297 20:15:02.045981 GAT_TRACK_EN = 1
2298 20:15:02.049463 RX_GATING_MODE = 2
2299 20:15:02.052494 RX_GATING_TRACK_MODE = 2
2300 20:15:02.055908 SELPH_MODE = 1
2301 20:15:02.055990 PICG_EARLY_EN = 1
2302 20:15:02.059104 VALID_LAT_VALUE = 1
2303 20:15:02.065946 ==============================================================
2304 20:15:02.069353 Enter into Gating configuration >>>>
2305 20:15:02.072562 Exit from Gating configuration <<<<
2306 20:15:02.075944 Enter into DVFS_PRE_config >>>>>
2307 20:15:02.085892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 20:15:02.088972 Exit from DVFS_PRE_config <<<<<
2309 20:15:02.092450 Enter into PICG configuration >>>>
2310 20:15:02.095741 Exit from PICG configuration <<<<
2311 20:15:02.099214 [RX_INPUT] configuration >>>>>
2312 20:15:02.102481 [RX_INPUT] configuration <<<<<
2313 20:15:02.105984 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 20:15:02.112156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 20:15:02.119190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 20:15:02.125769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 20:15:02.132528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 20:15:02.135661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 20:15:02.142566 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 20:15:02.145516 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 20:15:02.149159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 20:15:02.152288 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 20:15:02.158955 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 20:15:02.162369 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 20:15:02.165525 ===================================
2326 20:15:02.168943 LPDDR4 DRAM CONFIGURATION
2327 20:15:02.172575 ===================================
2328 20:15:02.172657 EX_ROW_EN[0] = 0x0
2329 20:15:02.175550 EX_ROW_EN[1] = 0x0
2330 20:15:02.175632 LP4Y_EN = 0x0
2331 20:15:02.179034 WORK_FSP = 0x0
2332 20:15:02.179140 WL = 0x4
2333 20:15:02.182303 RL = 0x4
2334 20:15:02.182390 BL = 0x2
2335 20:15:02.185498 RPST = 0x0
2336 20:15:02.185592 RD_PRE = 0x0
2337 20:15:02.189131 WR_PRE = 0x1
2338 20:15:02.189224 WR_PST = 0x0
2339 20:15:02.192434 DBI_WR = 0x0
2340 20:15:02.192536 DBI_RD = 0x0
2341 20:15:02.195669 OTF = 0x1
2342 20:15:02.199124 ===================================
2343 20:15:02.202583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 20:15:02.205812 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 20:15:02.212256 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 20:15:02.215838 ===================================
2347 20:15:02.216043 LPDDR4 DRAM CONFIGURATION
2348 20:15:02.219086 ===================================
2349 20:15:02.222824 EX_ROW_EN[0] = 0x10
2350 20:15:02.225729 EX_ROW_EN[1] = 0x0
2351 20:15:02.225970 LP4Y_EN = 0x0
2352 20:15:02.229009 WORK_FSP = 0x0
2353 20:15:02.229258 WL = 0x4
2354 20:15:02.232277 RL = 0x4
2355 20:15:02.232578 BL = 0x2
2356 20:15:02.235851 RPST = 0x0
2357 20:15:02.236241 RD_PRE = 0x0
2358 20:15:02.239065 WR_PRE = 0x1
2359 20:15:02.239452 WR_PST = 0x0
2360 20:15:02.242458 DBI_WR = 0x0
2361 20:15:02.242875 DBI_RD = 0x0
2362 20:15:02.245415 OTF = 0x1
2363 20:15:02.248739 ===================================
2364 20:15:02.255621 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 20:15:02.255714 ==
2366 20:15:02.258729 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 20:15:02.262310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 20:15:02.262413 ==
2369 20:15:02.265627 [Duty_Offset_Calibration]
2370 20:15:02.265711 B0:2 B1:0 CA:3
2371 20:15:02.265779
2372 20:15:02.268695 [DutyScan_Calibration_Flow] k_type=0
2373 20:15:02.279268
2374 20:15:02.279348 ==CLK 0==
2375 20:15:02.282240 Final CLK duty delay cell = 0
2376 20:15:02.285832 [0] MAX Duty = 5031%(X100), DQS PI = 12
2377 20:15:02.288896 [0] MIN Duty = 4906%(X100), DQS PI = 54
2378 20:15:02.289003 [0] AVG Duty = 4968%(X100)
2379 20:15:02.292348
2380 20:15:02.295514 CH0 CLK Duty spec in!! Max-Min= 125%
2381 20:15:02.299226 [DutyScan_Calibration_Flow] ====Done====
2382 20:15:02.299319
2383 20:15:02.302352 [DutyScan_Calibration_Flow] k_type=1
2384 20:15:02.317428
2385 20:15:02.317585 ==DQS 0 ==
2386 20:15:02.320736 Final DQS duty delay cell = 0
2387 20:15:02.324173 [0] MAX Duty = 5062%(X100), DQS PI = 14
2388 20:15:02.327714 [0] MIN Duty = 4907%(X100), DQS PI = 2
2389 20:15:02.327886 [0] AVG Duty = 4984%(X100)
2390 20:15:02.331028
2391 20:15:02.331226 ==DQS 1 ==
2392 20:15:02.334351 Final DQS duty delay cell = -4
2393 20:15:02.337513 [-4] MAX Duty = 5000%(X100), DQS PI = 34
2394 20:15:02.340925 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2395 20:15:02.344286 [-4] AVG Duty = 4953%(X100)
2396 20:15:02.344584
2397 20:15:02.347701 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2398 20:15:02.348085
2399 20:15:02.351194 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2400 20:15:02.354419 [DutyScan_Calibration_Flow] ====Done====
2401 20:15:02.354838
2402 20:15:02.357503 [DutyScan_Calibration_Flow] k_type=3
2403 20:15:02.375338
2404 20:15:02.375750 ==DQM 0 ==
2405 20:15:02.378842 Final DQM duty delay cell = 0
2406 20:15:02.381970 [0] MAX Duty = 5124%(X100), DQS PI = 28
2407 20:15:02.385386 [0] MIN Duty = 4876%(X100), DQS PI = 0
2408 20:15:02.385838 [0] AVG Duty = 5000%(X100)
2409 20:15:02.388811
2410 20:15:02.389224 ==DQM 1 ==
2411 20:15:02.391859 Final DQM duty delay cell = 4
2412 20:15:02.395376 [4] MAX Duty = 5124%(X100), DQS PI = 50
2413 20:15:02.398633 [4] MIN Duty = 5000%(X100), DQS PI = 14
2414 20:15:02.399050 [4] AVG Duty = 5062%(X100)
2415 20:15:02.401955
2416 20:15:02.405292 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2417 20:15:02.405738
2418 20:15:02.408561 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2419 20:15:02.411852 [DutyScan_Calibration_Flow] ====Done====
2420 20:15:02.412275
2421 20:15:02.415016 [DutyScan_Calibration_Flow] k_type=2
2422 20:15:02.431051
2423 20:15:02.431466 ==DQ 0 ==
2424 20:15:02.434081 Final DQ duty delay cell = -4
2425 20:15:02.437723 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2426 20:15:02.440768 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2427 20:15:02.444094 [-4] AVG Duty = 4969%(X100)
2428 20:15:02.444511
2429 20:15:02.444841 ==DQ 1 ==
2430 20:15:02.447506 Final DQ duty delay cell = 0
2431 20:15:02.450885 [0] MAX Duty = 5125%(X100), DQS PI = 0
2432 20:15:02.454286 [0] MIN Duty = 5000%(X100), DQS PI = 20
2433 20:15:02.457252 [0] AVG Duty = 5062%(X100)
2434 20:15:02.457693
2435 20:15:02.460860 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2436 20:15:02.461311
2437 20:15:02.464043 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2438 20:15:02.467419 [DutyScan_Calibration_Flow] ====Done====
2439 20:15:02.467836 ==
2440 20:15:02.470864 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 20:15:02.474257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 20:15:02.474677 ==
2443 20:15:02.477515 [Duty_Offset_Calibration]
2444 20:15:02.478099 B0:1 B1:-2 CA:0
2445 20:15:02.478463
2446 20:15:02.480686 [DutyScan_Calibration_Flow] k_type=0
2447 20:15:02.491141
2448 20:15:02.491556 ==CLK 0==
2449 20:15:02.494459 Final CLK duty delay cell = 0
2450 20:15:02.497873 [0] MAX Duty = 5031%(X100), DQS PI = 18
2451 20:15:02.501335 [0] MIN Duty = 4875%(X100), DQS PI = 2
2452 20:15:02.501787 [0] AVG Duty = 4953%(X100)
2453 20:15:02.504459
2454 20:15:02.504870 CH1 CLK Duty spec in!! Max-Min= 156%
2455 20:15:02.511387 [DutyScan_Calibration_Flow] ====Done====
2456 20:15:02.511806
2457 20:15:02.514380 [DutyScan_Calibration_Flow] k_type=1
2458 20:15:02.529592
2459 20:15:02.530024 ==DQS 0 ==
2460 20:15:02.533112 Final DQS duty delay cell = -4
2461 20:15:02.536182 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2462 20:15:02.539517 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2463 20:15:02.542782 [-4] AVG Duty = 4953%(X100)
2464 20:15:02.543202
2465 20:15:02.543531 ==DQS 1 ==
2466 20:15:02.546138 Final DQS duty delay cell = 0
2467 20:15:02.549592 [0] MAX Duty = 5093%(X100), DQS PI = 0
2468 20:15:02.552982 [0] MIN Duty = 4875%(X100), DQS PI = 26
2469 20:15:02.556467 [0] AVG Duty = 4984%(X100)
2470 20:15:02.556884
2471 20:15:02.559603 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2472 20:15:02.560019
2473 20:15:02.562770 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2474 20:15:02.566125 [DutyScan_Calibration_Flow] ====Done====
2475 20:15:02.566427
2476 20:15:02.569343 [DutyScan_Calibration_Flow] k_type=3
2477 20:15:02.586152
2478 20:15:02.586510 ==DQM 0 ==
2479 20:15:02.589531 Final DQM duty delay cell = 0
2480 20:15:02.592769 [0] MAX Duty = 5000%(X100), DQS PI = 22
2481 20:15:02.596133 [0] MIN Duty = 4844%(X100), DQS PI = 52
2482 20:15:02.599354 [0] AVG Duty = 4922%(X100)
2483 20:15:02.599710
2484 20:15:02.599994 ==DQM 1 ==
2485 20:15:02.602810 Final DQM duty delay cell = 0
2486 20:15:02.606255 [0] MAX Duty = 5031%(X100), DQS PI = 36
2487 20:15:02.609363 [0] MIN Duty = 4907%(X100), DQS PI = 4
2488 20:15:02.612873 [0] AVG Duty = 4969%(X100)
2489 20:15:02.613218
2490 20:15:02.616282 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2491 20:15:02.616694
2492 20:15:02.619295 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2493 20:15:02.622862 [DutyScan_Calibration_Flow] ====Done====
2494 20:15:02.623188
2495 20:15:02.625951 [DutyScan_Calibration_Flow] k_type=2
2496 20:15:02.642739
2497 20:15:02.643085 ==DQ 0 ==
2498 20:15:02.645926 Final DQ duty delay cell = 0
2499 20:15:02.649202 [0] MAX Duty = 5093%(X100), DQS PI = 20
2500 20:15:02.652472 [0] MIN Duty = 4938%(X100), DQS PI = 56
2501 20:15:02.652886 [0] AVG Duty = 5015%(X100)
2502 20:15:02.656196
2503 20:15:02.656505 ==DQ 1 ==
2504 20:15:02.659405 Final DQ duty delay cell = 0
2505 20:15:02.662718 [0] MAX Duty = 5125%(X100), DQS PI = 36
2506 20:15:02.666103 [0] MIN Duty = 4969%(X100), DQS PI = 26
2507 20:15:02.666428 [0] AVG Duty = 5047%(X100)
2508 20:15:02.666726
2509 20:15:02.669218 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2510 20:15:02.672848
2511 20:15:02.676090 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2512 20:15:02.679005 [DutyScan_Calibration_Flow] ====Done====
2513 20:15:02.682448 nWR fixed to 30
2514 20:15:02.682767 [ModeRegInit_LP4] CH0 RK0
2515 20:15:02.685946 [ModeRegInit_LP4] CH0 RK1
2516 20:15:02.689077 [ModeRegInit_LP4] CH1 RK0
2517 20:15:02.689506 [ModeRegInit_LP4] CH1 RK1
2518 20:15:02.692342 match AC timing 7
2519 20:15:02.695715 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 20:15:02.699326 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 20:15:02.705755 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 20:15:02.709145 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 20:15:02.715916 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 20:15:02.716216 ==
2525 20:15:02.719197 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 20:15:02.722355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 20:15:02.722667 ==
2528 20:15:02.729370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 20:15:02.732673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 20:15:02.742850 [CA 0] Center 40 (10~71) winsize 62
2531 20:15:02.746272 [CA 1] Center 39 (9~70) winsize 62
2532 20:15:02.749371 [CA 2] Center 36 (6~66) winsize 61
2533 20:15:02.752795 [CA 3] Center 35 (5~66) winsize 62
2534 20:15:02.756071 [CA 4] Center 34 (4~65) winsize 62
2535 20:15:02.759500 [CA 5] Center 33 (3~63) winsize 61
2536 20:15:02.759934
2537 20:15:02.762934 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 20:15:02.763424
2539 20:15:02.766044 [CATrainingPosCal] consider 1 rank data
2540 20:15:02.769531 u2DelayCellTimex100 = 270/100 ps
2541 20:15:02.772965 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2542 20:15:02.779382 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2543 20:15:02.782588 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2544 20:15:02.785828 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 20:15:02.789278 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2546 20:15:02.792884 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 20:15:02.793345
2548 20:15:02.796003 CA PerBit enable=1, Macro0, CA PI delay=33
2549 20:15:02.796423
2550 20:15:02.799121 [CBTSetCACLKResult] CA Dly = 33
2551 20:15:02.799540 CS Dly: 7 (0~38)
2552 20:15:02.802921 ==
2553 20:15:02.805885 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 20:15:02.809361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 20:15:02.809808 ==
2556 20:15:02.812825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 20:15:02.819404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2558 20:15:02.828733 [CA 0] Center 40 (10~70) winsize 61
2559 20:15:02.832085 [CA 1] Center 40 (10~70) winsize 61
2560 20:15:02.835511 [CA 2] Center 35 (5~66) winsize 62
2561 20:15:02.838834 [CA 3] Center 35 (5~66) winsize 62
2562 20:15:02.842027 [CA 4] Center 34 (4~65) winsize 62
2563 20:15:02.845562 [CA 5] Center 33 (3~64) winsize 62
2564 20:15:02.845985
2565 20:15:02.849113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2566 20:15:02.849799
2567 20:15:02.852160 [CATrainingPosCal] consider 2 rank data
2568 20:15:02.855610 u2DelayCellTimex100 = 270/100 ps
2569 20:15:02.858771 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2570 20:15:02.865587 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2571 20:15:02.868794 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2572 20:15:02.872073 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2573 20:15:02.875434 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2574 20:15:02.878867 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2575 20:15:02.879331
2576 20:15:02.882281 CA PerBit enable=1, Macro0, CA PI delay=33
2577 20:15:02.882703
2578 20:15:02.885769 [CBTSetCACLKResult] CA Dly = 33
2579 20:15:02.886188 CS Dly: 8 (0~40)
2580 20:15:02.889213
2581 20:15:02.892176 ----->DramcWriteLeveling(PI) begin...
2582 20:15:02.892600 ==
2583 20:15:02.895436 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 20:15:02.898994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 20:15:02.899417 ==
2586 20:15:02.902304 Write leveling (Byte 0): 33 => 33
2587 20:15:02.905800 Write leveling (Byte 1): 30 => 30
2588 20:15:02.908863 DramcWriteLeveling(PI) end<-----
2589 20:15:02.909285
2590 20:15:02.909742 ==
2591 20:15:02.912485 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 20:15:02.915685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 20:15:02.916243 ==
2594 20:15:02.919232 [Gating] SW mode calibration
2595 20:15:02.925825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 20:15:02.932293 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 20:15:02.935636 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 20:15:02.938989 0 15 4 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
2599 20:15:02.942375 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 20:15:02.949141 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 20:15:02.952229 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 20:15:02.955684 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 20:15:02.962391 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 20:15:02.965890 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2605 20:15:02.969213 1 0 0 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (1 0)
2606 20:15:02.975575 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2607 20:15:02.978936 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 20:15:02.982354 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 20:15:02.989226 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 20:15:02.992240 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 20:15:02.995788 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 20:15:03.002268 1 0 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2613 20:15:03.005723 1 1 0 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (0 0)
2614 20:15:03.008857 1 1 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2615 20:15:03.015369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 20:15:03.018850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 20:15:03.022072 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 20:15:03.028803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 20:15:03.032160 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 20:15:03.035750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 20:15:03.042222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2622 20:15:03.045540 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2623 20:15:03.048946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 20:15:03.052150 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 20:15:03.058617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 20:15:03.062354 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 20:15:03.065721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 20:15:03.072195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 20:15:03.075595 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 20:15:03.078884 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 20:15:03.085573 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 20:15:03.089076 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 20:15:03.092134 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 20:15:03.098801 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 20:15:03.102325 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 20:15:03.105517 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 20:15:03.112249 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2638 20:15:03.115372 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2639 20:15:03.118819 Total UI for P1: 0, mck2ui 16
2640 20:15:03.122160 best dqsien dly found for B0: ( 1, 3, 30)
2641 20:15:03.125447 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 20:15:03.128414 Total UI for P1: 0, mck2ui 16
2643 20:15:03.131687 best dqsien dly found for B1: ( 1, 4, 2)
2644 20:15:03.135127 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2645 20:15:03.138575 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2646 20:15:03.138997
2647 20:15:03.145212 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2648 20:15:03.148570 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2649 20:15:03.148992 [Gating] SW calibration Done
2650 20:15:03.151915 ==
2651 20:15:03.152335 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 20:15:03.158521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 20:15:03.158948 ==
2654 20:15:03.159282 RX Vref Scan: 0
2655 20:15:03.159594
2656 20:15:03.161659 RX Vref 0 -> 0, step: 1
2657 20:15:03.162077
2658 20:15:03.164664 RX Delay -40 -> 252, step: 8
2659 20:15:03.168195 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2660 20:15:03.171674 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2661 20:15:03.175047 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2662 20:15:03.181602 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2663 20:15:03.185010 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2664 20:15:03.188096 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2665 20:15:03.191769 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2666 20:15:03.194708 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2667 20:15:03.201225 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2668 20:15:03.204120 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2669 20:15:03.207564 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2670 20:15:03.210803 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2671 20:15:03.214451 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2672 20:15:03.220876 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2673 20:15:03.224297 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2674 20:15:03.227371 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2675 20:15:03.227453 ==
2676 20:15:03.230825 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 20:15:03.234176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 20:15:03.234258 ==
2679 20:15:03.237389 DQS Delay:
2680 20:15:03.237482 DQS0 = 0, DQS1 = 0
2681 20:15:03.240761 DQM Delay:
2682 20:15:03.240854 DQM0 = 112, DQM1 = 103
2683 20:15:03.244377 DQ Delay:
2684 20:15:03.247645 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2685 20:15:03.250940 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2686 20:15:03.254223 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2687 20:15:03.257531 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2688 20:15:03.257652
2689 20:15:03.257749
2690 20:15:03.257838 ==
2691 20:15:03.261084 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 20:15:03.264211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 20:15:03.264375 ==
2694 20:15:03.264485
2695 20:15:03.264584
2696 20:15:03.267690 TX Vref Scan disable
2697 20:15:03.270887 == TX Byte 0 ==
2698 20:15:03.274211 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2699 20:15:03.277504 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2700 20:15:03.280834 == TX Byte 1 ==
2701 20:15:03.284209 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2702 20:15:03.287521 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2703 20:15:03.287613 ==
2704 20:15:03.290826 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 20:15:03.294070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 20:15:03.294152 ==
2707 20:15:03.307472 TX Vref=22, minBit 0, minWin=25, winSum=417
2708 20:15:03.311061 TX Vref=24, minBit 3, minWin=26, winSum=421
2709 20:15:03.314004 TX Vref=26, minBit 1, minWin=26, winSum=427
2710 20:15:03.317492 TX Vref=28, minBit 14, minWin=25, winSum=427
2711 20:15:03.320890 TX Vref=30, minBit 13, minWin=25, winSum=425
2712 20:15:03.327664 TX Vref=32, minBit 10, minWin=25, winSum=424
2713 20:15:03.330694 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26
2714 20:15:03.330776
2715 20:15:03.333881 Final TX Range 1 Vref 26
2716 20:15:03.333963
2717 20:15:03.334028 ==
2718 20:15:03.337269 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 20:15:03.340768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 20:15:03.340850 ==
2721 20:15:03.343860
2722 20:15:03.343941
2723 20:15:03.344005 TX Vref Scan disable
2724 20:15:03.347281 == TX Byte 0 ==
2725 20:15:03.350786 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2726 20:15:03.354198 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2727 20:15:03.357397 == TX Byte 1 ==
2728 20:15:03.360627 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2729 20:15:03.367259 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2730 20:15:03.367342
2731 20:15:03.367406 [DATLAT]
2732 20:15:03.367466 Freq=1200, CH0 RK0
2733 20:15:03.367526
2734 20:15:03.370599 DATLAT Default: 0xd
2735 20:15:03.370680 0, 0xFFFF, sum = 0
2736 20:15:03.374030 1, 0xFFFF, sum = 0
2737 20:15:03.374113 2, 0xFFFF, sum = 0
2738 20:15:03.377223 3, 0xFFFF, sum = 0
2739 20:15:03.380556 4, 0xFFFF, sum = 0
2740 20:15:03.380638 5, 0xFFFF, sum = 0
2741 20:15:03.383992 6, 0xFFFF, sum = 0
2742 20:15:03.384075 7, 0xFFFF, sum = 0
2743 20:15:03.387471 8, 0xFFFF, sum = 0
2744 20:15:03.387559 9, 0xFFFF, sum = 0
2745 20:15:03.390481 10, 0xFFFF, sum = 0
2746 20:15:03.390564 11, 0xFFFF, sum = 0
2747 20:15:03.393681 12, 0x0, sum = 1
2748 20:15:03.393764 13, 0x0, sum = 2
2749 20:15:03.397043 14, 0x0, sum = 3
2750 20:15:03.397125 15, 0x0, sum = 4
2751 20:15:03.397191 best_step = 13
2752 20:15:03.400731
2753 20:15:03.400812 ==
2754 20:15:03.403763 Dram Type= 6, Freq= 0, CH_0, rank 0
2755 20:15:03.407113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2756 20:15:03.407196 ==
2757 20:15:03.407261 RX Vref Scan: 1
2758 20:15:03.407322
2759 20:15:03.410643 Set Vref Range= 32 -> 127
2760 20:15:03.410725
2761 20:15:03.413757 RX Vref 32 -> 127, step: 1
2762 20:15:03.413840
2763 20:15:03.417250 RX Delay -37 -> 252, step: 4
2764 20:15:03.417368
2765 20:15:03.420516 Set Vref, RX VrefLevel [Byte0]: 32
2766 20:15:03.423910 [Byte1]: 32
2767 20:15:03.423992
2768 20:15:03.427040 Set Vref, RX VrefLevel [Byte0]: 33
2769 20:15:03.430473 [Byte1]: 33
2770 20:15:03.434288
2771 20:15:03.434381 Set Vref, RX VrefLevel [Byte0]: 34
2772 20:15:03.437466 [Byte1]: 34
2773 20:15:03.442136
2774 20:15:03.442216 Set Vref, RX VrefLevel [Byte0]: 35
2775 20:15:03.445114 [Byte1]: 35
2776 20:15:03.450236
2777 20:15:03.450317 Set Vref, RX VrefLevel [Byte0]: 36
2778 20:15:03.453237 [Byte1]: 36
2779 20:15:03.458182
2780 20:15:03.458263 Set Vref, RX VrefLevel [Byte0]: 37
2781 20:15:03.461212 [Byte1]: 37
2782 20:15:03.465916
2783 20:15:03.465997 Set Vref, RX VrefLevel [Byte0]: 38
2784 20:15:03.469149 [Byte1]: 38
2785 20:15:03.474378
2786 20:15:03.474460 Set Vref, RX VrefLevel [Byte0]: 39
2787 20:15:03.477313 [Byte1]: 39
2788 20:15:03.481869
2789 20:15:03.481950 Set Vref, RX VrefLevel [Byte0]: 40
2790 20:15:03.485375 [Byte1]: 40
2791 20:15:03.489862
2792 20:15:03.489943 Set Vref, RX VrefLevel [Byte0]: 41
2793 20:15:03.493428 [Byte1]: 41
2794 20:15:03.497992
2795 20:15:03.498073 Set Vref, RX VrefLevel [Byte0]: 42
2796 20:15:03.501229 [Byte1]: 42
2797 20:15:03.505834
2798 20:15:03.505915 Set Vref, RX VrefLevel [Byte0]: 43
2799 20:15:03.509411 [Byte1]: 43
2800 20:15:03.514005
2801 20:15:03.514086 Set Vref, RX VrefLevel [Byte0]: 44
2802 20:15:03.517369 [Byte1]: 44
2803 20:15:03.522149
2804 20:15:03.522240 Set Vref, RX VrefLevel [Byte0]: 45
2805 20:15:03.525185 [Byte1]: 45
2806 20:15:03.530023
2807 20:15:03.530104 Set Vref, RX VrefLevel [Byte0]: 46
2808 20:15:03.533220 [Byte1]: 46
2809 20:15:03.537963
2810 20:15:03.538044 Set Vref, RX VrefLevel [Byte0]: 47
2811 20:15:03.541209 [Byte1]: 47
2812 20:15:03.546258
2813 20:15:03.546339 Set Vref, RX VrefLevel [Byte0]: 48
2814 20:15:03.549248 [Byte1]: 48
2815 20:15:03.553764
2816 20:15:03.553845 Set Vref, RX VrefLevel [Byte0]: 49
2817 20:15:03.557352 [Byte1]: 49
2818 20:15:03.561897
2819 20:15:03.561978 Set Vref, RX VrefLevel [Byte0]: 50
2820 20:15:03.565350 [Byte1]: 50
2821 20:15:03.570091
2822 20:15:03.570172 Set Vref, RX VrefLevel [Byte0]: 51
2823 20:15:03.573368 [Byte1]: 51
2824 20:15:03.578039
2825 20:15:03.578119 Set Vref, RX VrefLevel [Byte0]: 52
2826 20:15:03.581497 [Byte1]: 52
2827 20:15:03.586222
2828 20:15:03.586303 Set Vref, RX VrefLevel [Byte0]: 53
2829 20:15:03.589136 [Byte1]: 53
2830 20:15:03.594154
2831 20:15:03.594234 Set Vref, RX VrefLevel [Byte0]: 54
2832 20:15:03.597198 [Byte1]: 54
2833 20:15:03.601969
2834 20:15:03.602051 Set Vref, RX VrefLevel [Byte0]: 55
2835 20:15:03.605367 [Byte1]: 55
2836 20:15:03.609941
2837 20:15:03.610022 Set Vref, RX VrefLevel [Byte0]: 56
2838 20:15:03.613090 [Byte1]: 56
2839 20:15:03.617819
2840 20:15:03.617901 Set Vref, RX VrefLevel [Byte0]: 57
2841 20:15:03.621170 [Byte1]: 57
2842 20:15:03.625863
2843 20:15:03.625970 Set Vref, RX VrefLevel [Byte0]: 58
2844 20:15:03.629250 [Byte1]: 58
2845 20:15:03.633897
2846 20:15:03.633979 Set Vref, RX VrefLevel [Byte0]: 59
2847 20:15:03.637186 [Byte1]: 59
2848 20:15:03.642128
2849 20:15:03.642209 Set Vref, RX VrefLevel [Byte0]: 60
2850 20:15:03.645165 [Byte1]: 60
2851 20:15:03.650109
2852 20:15:03.650191 Set Vref, RX VrefLevel [Byte0]: 61
2853 20:15:03.653147 [Byte1]: 61
2854 20:15:03.658083
2855 20:15:03.658164 Set Vref, RX VrefLevel [Byte0]: 62
2856 20:15:03.661248 [Byte1]: 62
2857 20:15:03.665860
2858 20:15:03.665941 Set Vref, RX VrefLevel [Byte0]: 63
2859 20:15:03.669393 [Byte1]: 63
2860 20:15:03.673769
2861 20:15:03.673877 Set Vref, RX VrefLevel [Byte0]: 64
2862 20:15:03.677161 [Byte1]: 64
2863 20:15:03.681894
2864 20:15:03.681975 Set Vref, RX VrefLevel [Byte0]: 65
2865 20:15:03.685196 [Byte1]: 65
2866 20:15:03.690025
2867 20:15:03.690107 Set Vref, RX VrefLevel [Byte0]: 66
2868 20:15:03.693359 [Byte1]: 66
2869 20:15:03.697848
2870 20:15:03.697930 Set Vref, RX VrefLevel [Byte0]: 67
2871 20:15:03.701378 [Byte1]: 67
2872 20:15:03.705929
2873 20:15:03.706010 Set Vref, RX VrefLevel [Byte0]: 68
2874 20:15:03.709352 [Byte1]: 68
2875 20:15:03.713928
2876 20:15:03.714010 Set Vref, RX VrefLevel [Byte0]: 69
2877 20:15:03.717407 [Byte1]: 69
2878 20:15:03.722120
2879 20:15:03.722202 Set Vref, RX VrefLevel [Byte0]: 70
2880 20:15:03.725240 [Byte1]: 70
2881 20:15:03.729806
2882 20:15:03.729887 Set Vref, RX VrefLevel [Byte0]: 71
2883 20:15:03.733164 [Byte1]: 71
2884 20:15:03.737907
2885 20:15:03.737988 Set Vref, RX VrefLevel [Byte0]: 72
2886 20:15:03.741410 [Byte1]: 72
2887 20:15:03.746164
2888 20:15:03.746245 Set Vref, RX VrefLevel [Byte0]: 73
2889 20:15:03.749120 [Byte1]: 73
2890 20:15:03.754070
2891 20:15:03.754151 Set Vref, RX VrefLevel [Byte0]: 74
2892 20:15:03.757116 [Byte1]: 74
2893 20:15:03.762040
2894 20:15:03.762121 Final RX Vref Byte 0 = 61 to rank0
2895 20:15:03.765282 Final RX Vref Byte 1 = 45 to rank0
2896 20:15:03.768585 Final RX Vref Byte 0 = 61 to rank1
2897 20:15:03.772009 Final RX Vref Byte 1 = 45 to rank1==
2898 20:15:03.775220 Dram Type= 6, Freq= 0, CH_0, rank 0
2899 20:15:03.781935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 20:15:03.782018 ==
2901 20:15:03.782083 DQS Delay:
2902 20:15:03.782143 DQS0 = 0, DQS1 = 0
2903 20:15:03.785450 DQM Delay:
2904 20:15:03.785567 DQM0 = 111, DQM1 = 98
2905 20:15:03.788353 DQ Delay:
2906 20:15:03.791787 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2907 20:15:03.795048 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2908 20:15:03.798651 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2909 20:15:03.801936 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2910 20:15:03.802017
2911 20:15:03.802081
2912 20:15:03.808388 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2913 20:15:03.811738 CH0 RK0: MR19=403, MR18=FF
2914 20:15:03.818300 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2915 20:15:03.818385
2916 20:15:03.821778 ----->DramcWriteLeveling(PI) begin...
2917 20:15:03.821860 ==
2918 20:15:03.825283 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 20:15:03.828397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 20:15:03.828479 ==
2921 20:15:03.831870 Write leveling (Byte 0): 31 => 31
2922 20:15:03.835226 Write leveling (Byte 1): 30 => 30
2923 20:15:03.838420 DramcWriteLeveling(PI) end<-----
2924 20:15:03.838502
2925 20:15:03.838566 ==
2926 20:15:03.842070 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 20:15:03.845024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 20:15:03.848185 ==
2929 20:15:03.848266 [Gating] SW mode calibration
2930 20:15:03.858193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2931 20:15:03.861703 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2932 20:15:03.864941 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2933 20:15:03.871720 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 20:15:03.874948 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 20:15:03.878173 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 20:15:03.884917 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 20:15:03.888267 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 20:15:03.891669 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2939 20:15:03.898331 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2940 20:15:03.901660 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2941 20:15:03.904815 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 20:15:03.911591 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 20:15:03.914842 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 20:15:03.918112 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 20:15:03.924664 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 20:15:03.927991 1 0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2947 20:15:03.931353 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2948 20:15:03.934802 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2949 20:15:03.941647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 20:15:03.944920 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 20:15:03.948299 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 20:15:03.954836 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 20:15:03.958045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 20:15:03.961622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2955 20:15:03.968041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2956 20:15:03.971493 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2957 20:15:03.974811 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 20:15:03.981193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 20:15:03.985012 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 20:15:03.988256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 20:15:03.995155 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 20:15:03.997888 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 20:15:04.001424 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 20:15:04.008306 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 20:15:04.011140 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 20:15:04.014576 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 20:15:04.021324 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 20:15:04.024795 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 20:15:04.028161 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 20:15:04.034561 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 20:15:04.038007 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2972 20:15:04.041435 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2973 20:15:04.044659 Total UI for P1: 0, mck2ui 16
2974 20:15:04.047896 best dqsien dly found for B0: ( 1, 3, 28)
2975 20:15:04.051408 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 20:15:04.054681 Total UI for P1: 0, mck2ui 16
2977 20:15:04.057960 best dqsien dly found for B1: ( 1, 4, 0)
2978 20:15:04.061391 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2979 20:15:04.064797 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2980 20:15:04.064879
2981 20:15:04.071259 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2982 20:15:04.074850 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2983 20:15:04.077864 [Gating] SW calibration Done
2984 20:15:04.077945 ==
2985 20:15:04.081487 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 20:15:04.084776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 20:15:04.084858 ==
2988 20:15:04.084922 RX Vref Scan: 0
2989 20:15:04.084982
2990 20:15:04.088029 RX Vref 0 -> 0, step: 1
2991 20:15:04.088110
2992 20:15:04.091594 RX Delay -40 -> 252, step: 8
2993 20:15:04.094685 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2994 20:15:04.098011 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2995 20:15:04.101482 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2996 20:15:04.108101 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2997 20:15:04.111540 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2998 20:15:04.114888 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2999 20:15:04.117980 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3000 20:15:04.121292 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
3001 20:15:04.128013 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3002 20:15:04.131263 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3003 20:15:04.134745 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3004 20:15:04.138013 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
3005 20:15:04.141426 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3006 20:15:04.148167 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
3007 20:15:04.151441 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3008 20:15:04.154857 iDelay=200, Bit 15, Center 107 (40 ~ 175) 136
3009 20:15:04.154938 ==
3010 20:15:04.157963 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 20:15:04.161243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 20:15:04.161325 ==
3013 20:15:04.164529 DQS Delay:
3014 20:15:04.164611 DQS0 = 0, DQS1 = 0
3015 20:15:04.168094 DQM Delay:
3016 20:15:04.168175 DQM0 = 111, DQM1 = 99
3017 20:15:04.168240 DQ Delay:
3018 20:15:04.171125 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3019 20:15:04.174490 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
3020 20:15:04.178028 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
3021 20:15:04.184478 DQ12 =107, DQ13 =103, DQ14 =111, DQ15 =107
3022 20:15:04.184560
3023 20:15:04.184624
3024 20:15:04.184685 ==
3025 20:15:04.187849 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 20:15:04.191060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 20:15:04.191142 ==
3028 20:15:04.191206
3029 20:15:04.191264
3030 20:15:04.194518 TX Vref Scan disable
3031 20:15:04.194599 == TX Byte 0 ==
3032 20:15:04.201074 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3033 20:15:04.204600 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3034 20:15:04.204682 == TX Byte 1 ==
3035 20:15:04.211161 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3036 20:15:04.214285 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3037 20:15:04.214367 ==
3038 20:15:04.217768 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 20:15:04.220879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 20:15:04.220961 ==
3041 20:15:04.234144 TX Vref=22, minBit 2, minWin=26, winSum=429
3042 20:15:04.237443 TX Vref=24, minBit 5, minWin=26, winSum=434
3043 20:15:04.240681 TX Vref=26, minBit 12, minWin=26, winSum=436
3044 20:15:04.243927 TX Vref=28, minBit 5, minWin=27, winSum=440
3045 20:15:04.247441 TX Vref=30, minBit 1, minWin=27, winSum=436
3046 20:15:04.253706 TX Vref=32, minBit 14, minWin=25, winSum=436
3047 20:15:04.256994 [TxChooseVref] Worse bit 5, Min win 27, Win sum 440, Final Vref 28
3048 20:15:04.257076
3049 20:15:04.260505 Final TX Range 1 Vref 28
3050 20:15:04.260586
3051 20:15:04.260699 ==
3052 20:15:04.263695 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 20:15:04.267396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 20:15:04.270449 ==
3055 20:15:04.270531
3056 20:15:04.270595
3057 20:15:04.270663 TX Vref Scan disable
3058 20:15:04.273838 == TX Byte 0 ==
3059 20:15:04.277135 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3060 20:15:04.283918 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3061 20:15:04.284000 == TX Byte 1 ==
3062 20:15:04.287186 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3063 20:15:04.293783 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3064 20:15:04.293865
3065 20:15:04.293930 [DATLAT]
3066 20:15:04.293990 Freq=1200, CH0 RK1
3067 20:15:04.294049
3068 20:15:04.297011 DATLAT Default: 0xd
3069 20:15:04.297091 0, 0xFFFF, sum = 0
3070 20:15:04.300469 1, 0xFFFF, sum = 0
3071 20:15:04.303896 2, 0xFFFF, sum = 0
3072 20:15:04.303979 3, 0xFFFF, sum = 0
3073 20:15:04.306964 4, 0xFFFF, sum = 0
3074 20:15:04.307047 5, 0xFFFF, sum = 0
3075 20:15:04.310426 6, 0xFFFF, sum = 0
3076 20:15:04.310508 7, 0xFFFF, sum = 0
3077 20:15:04.313491 8, 0xFFFF, sum = 0
3078 20:15:04.313573 9, 0xFFFF, sum = 0
3079 20:15:04.317033 10, 0xFFFF, sum = 0
3080 20:15:04.317116 11, 0xFFFF, sum = 0
3081 20:15:04.320278 12, 0x0, sum = 1
3082 20:15:04.320361 13, 0x0, sum = 2
3083 20:15:04.323484 14, 0x0, sum = 3
3084 20:15:04.323568 15, 0x0, sum = 4
3085 20:15:04.327012 best_step = 13
3086 20:15:04.327094
3087 20:15:04.327158 ==
3088 20:15:04.330322 Dram Type= 6, Freq= 0, CH_0, rank 1
3089 20:15:04.333755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 20:15:04.333838 ==
3091 20:15:04.333902 RX Vref Scan: 0
3092 20:15:04.333962
3093 20:15:04.336798 RX Vref 0 -> 0, step: 1
3094 20:15:04.336879
3095 20:15:04.340204 RX Delay -37 -> 252, step: 4
3096 20:15:04.343503 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3097 20:15:04.350469 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3098 20:15:04.353435 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3099 20:15:04.356798 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3100 20:15:04.360277 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3101 20:15:04.363533 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3102 20:15:04.370476 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3103 20:15:04.373380 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3104 20:15:04.376976 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3105 20:15:04.380403 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3106 20:15:04.383673 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3107 20:15:04.390395 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3108 20:15:04.393633 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3109 20:15:04.396850 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3110 20:15:04.400244 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3111 20:15:04.403629 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3112 20:15:04.403725 ==
3113 20:15:04.407051 Dram Type= 6, Freq= 0, CH_0, rank 1
3114 20:15:04.413703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 20:15:04.413802 ==
3116 20:15:04.413892 DQS Delay:
3117 20:15:04.416811 DQS0 = 0, DQS1 = 0
3118 20:15:04.416914 DQM Delay:
3119 20:15:04.420070 DQM0 = 110, DQM1 = 98
3120 20:15:04.420174 DQ Delay:
3121 20:15:04.423683 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3122 20:15:04.426813 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3123 20:15:04.430310 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3124 20:15:04.433382 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3125 20:15:04.433482
3126 20:15:04.433577
3127 20:15:04.443657 [DQSOSCAuto] RK1, (LSB)MR18= 0xff7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3128 20:15:04.443759 CH0 RK1: MR19=403, MR18=FF7
3129 20:15:04.450069 CH0_RK1: MR19=0x403, MR18=0xFF7, DQSOSC=404, MR23=63, INC=40, DEC=26
3130 20:15:04.453645 [RxdqsGatingPostProcess] freq 1200
3131 20:15:04.460202 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3132 20:15:04.463866 best DQS0 dly(2T, 0.5T) = (0, 11)
3133 20:15:04.467058 best DQS1 dly(2T, 0.5T) = (0, 12)
3134 20:15:04.467131 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3135 20:15:04.470105 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3136 20:15:04.473579 best DQS0 dly(2T, 0.5T) = (0, 11)
3137 20:15:04.476989 best DQS1 dly(2T, 0.5T) = (0, 12)
3138 20:15:04.480191 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3139 20:15:04.483680 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3140 20:15:04.487005 Pre-setting of DQS Precalculation
3141 20:15:04.493445 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3142 20:15:04.493548 ==
3143 20:15:04.497134 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 20:15:04.500197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 20:15:04.500294 ==
3146 20:15:04.506819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 20:15:04.510208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3148 20:15:04.519565 [CA 0] Center 37 (7~67) winsize 61
3149 20:15:04.523020 [CA 1] Center 37 (7~68) winsize 62
3150 20:15:04.526435 [CA 2] Center 34 (4~64) winsize 61
3151 20:15:04.529804 [CA 3] Center 33 (3~64) winsize 62
3152 20:15:04.533111 [CA 4] Center 34 (4~64) winsize 61
3153 20:15:04.536286 [CA 5] Center 33 (3~63) winsize 61
3154 20:15:04.536379
3155 20:15:04.539898 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3156 20:15:04.539999
3157 20:15:04.543228 [CATrainingPosCal] consider 1 rank data
3158 20:15:04.546342 u2DelayCellTimex100 = 270/100 ps
3159 20:15:04.549576 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3160 20:15:04.552999 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 20:15:04.559484 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 20:15:04.563000 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3163 20:15:04.566220 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 20:15:04.569707 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3165 20:15:04.569776
3166 20:15:04.572788 CA PerBit enable=1, Macro0, CA PI delay=33
3167 20:15:04.572853
3168 20:15:04.576272 [CBTSetCACLKResult] CA Dly = 33
3169 20:15:04.576341 CS Dly: 5 (0~36)
3170 20:15:04.576404 ==
3171 20:15:04.579579 Dram Type= 6, Freq= 0, CH_1, rank 1
3172 20:15:04.586295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 20:15:04.586392 ==
3174 20:15:04.589449 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3175 20:15:04.596142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3176 20:15:04.605428 [CA 0] Center 37 (7~67) winsize 61
3177 20:15:04.608507 [CA 1] Center 37 (7~68) winsize 62
3178 20:15:04.612260 [CA 2] Center 34 (4~65) winsize 62
3179 20:15:04.615595 [CA 3] Center 33 (3~64) winsize 62
3180 20:15:04.618636 [CA 4] Center 34 (4~65) winsize 62
3181 20:15:04.622331 [CA 5] Center 33 (3~63) winsize 61
3182 20:15:04.622413
3183 20:15:04.625189 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3184 20:15:04.625294
3185 20:15:04.628634 [CATrainingPosCal] consider 2 rank data
3186 20:15:04.632055 u2DelayCellTimex100 = 270/100 ps
3187 20:15:04.635174 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3188 20:15:04.638774 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3189 20:15:04.645327 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3190 20:15:04.648735 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3191 20:15:04.651924 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3192 20:15:04.655338 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3193 20:15:04.655433
3194 20:15:04.658473 CA PerBit enable=1, Macro0, CA PI delay=33
3195 20:15:04.658543
3196 20:15:04.661956 [CBTSetCACLKResult] CA Dly = 33
3197 20:15:04.662028 CS Dly: 6 (0~39)
3198 20:15:04.662088
3199 20:15:04.665256 ----->DramcWriteLeveling(PI) begin...
3200 20:15:04.668669 ==
3201 20:15:04.668743 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 20:15:04.675332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 20:15:04.675412 ==
3204 20:15:04.678928 Write leveling (Byte 0): 25 => 25
3205 20:15:04.681853 Write leveling (Byte 1): 29 => 29
3206 20:15:04.685337 DramcWriteLeveling(PI) end<-----
3207 20:15:04.685406
3208 20:15:04.685466 ==
3209 20:15:04.688437 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 20:15:04.691997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 20:15:04.692098 ==
3212 20:15:04.695060 [Gating] SW mode calibration
3213 20:15:04.702017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3214 20:15:04.705188 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3215 20:15:04.712178 0 15 0 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
3216 20:15:04.715096 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 20:15:04.718437 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 20:15:04.725453 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 20:15:04.728626 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 20:15:04.731937 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 20:15:04.738428 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3222 20:15:04.741896 0 15 28 | B1->B0 | 2f2f 2f2f | 0 1 | (0 1) (1 0)
3223 20:15:04.745414 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 20:15:04.752147 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 20:15:04.755667 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 20:15:04.759023 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 20:15:04.765743 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 20:15:04.769161 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 20:15:04.772409 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3230 20:15:04.779031 1 0 28 | B1->B0 | 3e3e 4040 | 0 1 | (0 0) (0 0)
3231 20:15:04.782250 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3232 20:15:04.785773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 20:15:04.792319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 20:15:04.795838 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 20:15:04.798907 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 20:15:04.802294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 20:15:04.809027 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 20:15:04.812259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 20:15:04.815625 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3240 20:15:04.822125 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 20:15:04.825696 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 20:15:04.828814 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 20:15:04.835801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 20:15:04.839143 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 20:15:04.842210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 20:15:04.848993 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 20:15:04.852551 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 20:15:04.855645 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 20:15:04.862144 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 20:15:04.865879 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 20:15:04.868834 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 20:15:04.875657 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 20:15:04.879090 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 20:15:04.882504 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3255 20:15:04.889281 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3256 20:15:04.889877 Total UI for P1: 0, mck2ui 16
3257 20:15:04.892356 best dqsien dly found for B1: ( 1, 3, 28)
3258 20:15:04.898862 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 20:15:04.902208 Total UI for P1: 0, mck2ui 16
3260 20:15:04.905720 best dqsien dly found for B0: ( 1, 3, 30)
3261 20:15:04.908995 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3262 20:15:04.912373 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3263 20:15:04.912811
3264 20:15:04.915451 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3265 20:15:04.919251 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3266 20:15:04.922415 [Gating] SW calibration Done
3267 20:15:04.922875 ==
3268 20:15:04.925877 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 20:15:04.929036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 20:15:04.929459 ==
3271 20:15:04.932388 RX Vref Scan: 0
3272 20:15:04.932808
3273 20:15:04.933139 RX Vref 0 -> 0, step: 1
3274 20:15:04.933447
3275 20:15:04.935980 RX Delay -40 -> 252, step: 8
3276 20:15:04.942499 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3277 20:15:04.945450 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3278 20:15:04.949019 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3279 20:15:04.952557 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3280 20:15:04.955525 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3281 20:15:04.959215 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3282 20:15:04.965816 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3283 20:15:04.968927 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3284 20:15:04.972231 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3285 20:15:04.975664 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3286 20:15:04.978811 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3287 20:15:04.985533 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3288 20:15:04.989016 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3289 20:15:04.992203 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3290 20:15:04.995604 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3291 20:15:04.998835 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3292 20:15:05.002158 ==
3293 20:15:05.005334 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 20:15:05.008946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 20:15:05.009368 ==
3296 20:15:05.009738 DQS Delay:
3297 20:15:05.012066 DQS0 = 0, DQS1 = 0
3298 20:15:05.012487 DQM Delay:
3299 20:15:05.015520 DQM0 = 113, DQM1 = 106
3300 20:15:05.015939 DQ Delay:
3301 20:15:05.019030 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3302 20:15:05.022182 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3303 20:15:05.025593 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3304 20:15:05.028913 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3305 20:15:05.029403
3306 20:15:05.029869
3307 20:15:05.030255 ==
3308 20:15:05.032319 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 20:15:05.039054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 20:15:05.039481 ==
3311 20:15:05.039813
3312 20:15:05.040119
3313 20:15:05.040415 TX Vref Scan disable
3314 20:15:05.042178 == TX Byte 0 ==
3315 20:15:05.045532 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 20:15:05.048930 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 20:15:05.052214 == TX Byte 1 ==
3318 20:15:05.055454 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3319 20:15:05.062226 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3320 20:15:05.062650 ==
3321 20:15:05.065400 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 20:15:05.068602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 20:15:05.069027 ==
3324 20:15:05.080196 TX Vref=22, minBit 8, minWin=24, winSum=408
3325 20:15:05.083505 TX Vref=24, minBit 8, minWin=24, winSum=416
3326 20:15:05.086567 TX Vref=26, minBit 8, minWin=25, winSum=422
3327 20:15:05.090398 TX Vref=28, minBit 9, minWin=25, winSum=423
3328 20:15:05.093442 TX Vref=30, minBit 10, minWin=25, winSum=428
3329 20:15:05.100089 TX Vref=32, minBit 9, minWin=25, winSum=423
3330 20:15:05.103608 [TxChooseVref] Worse bit 10, Min win 25, Win sum 428, Final Vref 30
3331 20:15:05.104030
3332 20:15:05.106608 Final TX Range 1 Vref 30
3333 20:15:05.107030
3334 20:15:05.107361 ==
3335 20:15:05.109897 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 20:15:05.113309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 20:15:05.116660 ==
3338 20:15:05.117077
3339 20:15:05.117414
3340 20:15:05.117782 TX Vref Scan disable
3341 20:15:05.119864 == TX Byte 0 ==
3342 20:15:05.123329 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3343 20:15:05.130197 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3344 20:15:05.130620 == TX Byte 1 ==
3345 20:15:05.133359 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3346 20:15:05.136605 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3347 20:15:05.140139
3348 20:15:05.140560 [DATLAT]
3349 20:15:05.140897 Freq=1200, CH1 RK0
3350 20:15:05.141208
3351 20:15:05.143392 DATLAT Default: 0xd
3352 20:15:05.143811 0, 0xFFFF, sum = 0
3353 20:15:05.146714 1, 0xFFFF, sum = 0
3354 20:15:05.147144 2, 0xFFFF, sum = 0
3355 20:15:05.150106 3, 0xFFFF, sum = 0
3356 20:15:05.153304 4, 0xFFFF, sum = 0
3357 20:15:05.153781 5, 0xFFFF, sum = 0
3358 20:15:05.156452 6, 0xFFFF, sum = 0
3359 20:15:05.156877 7, 0xFFFF, sum = 0
3360 20:15:05.160154 8, 0xFFFF, sum = 0
3361 20:15:05.160578 9, 0xFFFF, sum = 0
3362 20:15:05.163123 10, 0xFFFF, sum = 0
3363 20:15:05.163547 11, 0xFFFF, sum = 0
3364 20:15:05.166739 12, 0x0, sum = 1
3365 20:15:05.167246 13, 0x0, sum = 2
3366 20:15:05.169933 14, 0x0, sum = 3
3367 20:15:05.170355 15, 0x0, sum = 4
3368 20:15:05.170691 best_step = 13
3369 20:15:05.173308
3370 20:15:05.173756 ==
3371 20:15:05.176468 Dram Type= 6, Freq= 0, CH_1, rank 0
3372 20:15:05.179963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3373 20:15:05.180385 ==
3374 20:15:05.180713 RX Vref Scan: 1
3375 20:15:05.181019
3376 20:15:05.183244 Set Vref Range= 32 -> 127
3377 20:15:05.183665
3378 20:15:05.186551 RX Vref 32 -> 127, step: 1
3379 20:15:05.186969
3380 20:15:05.189930 RX Delay -21 -> 252, step: 4
3381 20:15:05.190349
3382 20:15:05.193419 Set Vref, RX VrefLevel [Byte0]: 32
3383 20:15:05.197009 [Byte1]: 32
3384 20:15:05.197562
3385 20:15:05.199864 Set Vref, RX VrefLevel [Byte0]: 33
3386 20:15:05.203001 [Byte1]: 33
3387 20:15:05.206341
3388 20:15:05.206892 Set Vref, RX VrefLevel [Byte0]: 34
3389 20:15:05.209878 [Byte1]: 34
3390 20:15:05.214162
3391 20:15:05.214615 Set Vref, RX VrefLevel [Byte0]: 35
3392 20:15:05.217743 [Byte1]: 35
3393 20:15:05.222312
3394 20:15:05.222727 Set Vref, RX VrefLevel [Byte0]: 36
3395 20:15:05.225856 [Byte1]: 36
3396 20:15:05.230322
3397 20:15:05.230736 Set Vref, RX VrefLevel [Byte0]: 37
3398 20:15:05.233318 [Byte1]: 37
3399 20:15:05.238236
3400 20:15:05.238650 Set Vref, RX VrefLevel [Byte0]: 38
3401 20:15:05.241389 [Byte1]: 38
3402 20:15:05.246140
3403 20:15:05.246556 Set Vref, RX VrefLevel [Byte0]: 39
3404 20:15:05.249952 [Byte1]: 39
3405 20:15:05.253931
3406 20:15:05.254344 Set Vref, RX VrefLevel [Byte0]: 40
3407 20:15:05.257294 [Byte1]: 40
3408 20:15:05.261642
3409 20:15:05.262060 Set Vref, RX VrefLevel [Byte0]: 41
3410 20:15:05.265208 [Byte1]: 41
3411 20:15:05.270001
3412 20:15:05.270416 Set Vref, RX VrefLevel [Byte0]: 42
3413 20:15:05.273249 [Byte1]: 42
3414 20:15:05.277903
3415 20:15:05.278506 Set Vref, RX VrefLevel [Byte0]: 43
3416 20:15:05.281126 [Byte1]: 43
3417 20:15:05.285747
3418 20:15:05.286220 Set Vref, RX VrefLevel [Byte0]: 44
3419 20:15:05.288762 [Byte1]: 44
3420 20:15:05.293553
3421 20:15:05.293970 Set Vref, RX VrefLevel [Byte0]: 45
3422 20:15:05.296996 [Byte1]: 45
3423 20:15:05.301646
3424 20:15:05.302151 Set Vref, RX VrefLevel [Byte0]: 46
3425 20:15:05.304825 [Byte1]: 46
3426 20:15:05.309706
3427 20:15:05.310217 Set Vref, RX VrefLevel [Byte0]: 47
3428 20:15:05.312527 [Byte1]: 47
3429 20:15:05.317309
3430 20:15:05.317882 Set Vref, RX VrefLevel [Byte0]: 48
3431 20:15:05.320767 [Byte1]: 48
3432 20:15:05.325433
3433 20:15:05.325913 Set Vref, RX VrefLevel [Byte0]: 49
3434 20:15:05.328387 [Byte1]: 49
3435 20:15:05.333183
3436 20:15:05.333643 Set Vref, RX VrefLevel [Byte0]: 50
3437 20:15:05.336741 [Byte1]: 50
3438 20:15:05.340897
3439 20:15:05.341313 Set Vref, RX VrefLevel [Byte0]: 51
3440 20:15:05.344142 [Byte1]: 51
3441 20:15:05.349037
3442 20:15:05.349644 Set Vref, RX VrefLevel [Byte0]: 52
3443 20:15:05.352277 [Byte1]: 52
3444 20:15:05.356924
3445 20:15:05.357338 Set Vref, RX VrefLevel [Byte0]: 53
3446 20:15:05.360086 [Byte1]: 53
3447 20:15:05.364767
3448 20:15:05.365195 Set Vref, RX VrefLevel [Byte0]: 54
3449 20:15:05.368219 [Byte1]: 54
3450 20:15:05.372698
3451 20:15:05.375707 Set Vref, RX VrefLevel [Byte0]: 55
3452 20:15:05.379325 [Byte1]: 55
3453 20:15:05.379746
3454 20:15:05.382679 Set Vref, RX VrefLevel [Byte0]: 56
3455 20:15:05.386195 [Byte1]: 56
3456 20:15:05.386665
3457 20:15:05.389250 Set Vref, RX VrefLevel [Byte0]: 57
3458 20:15:05.392639 [Byte1]: 57
3459 20:15:05.396709
3460 20:15:05.397137 Set Vref, RX VrefLevel [Byte0]: 58
3461 20:15:05.399862 [Byte1]: 58
3462 20:15:05.404401
3463 20:15:05.404823 Set Vref, RX VrefLevel [Byte0]: 59
3464 20:15:05.407639 [Byte1]: 59
3465 20:15:05.412673
3466 20:15:05.413235 Set Vref, RX VrefLevel [Byte0]: 60
3467 20:15:05.415619 [Byte1]: 60
3468 20:15:05.420326
3469 20:15:05.420792 Set Vref, RX VrefLevel [Byte0]: 61
3470 20:15:05.423924 [Byte1]: 61
3471 20:15:05.428583
3472 20:15:05.429045 Set Vref, RX VrefLevel [Byte0]: 62
3473 20:15:05.431556 [Byte1]: 62
3474 20:15:05.436374
3475 20:15:05.436836 Set Vref, RX VrefLevel [Byte0]: 63
3476 20:15:05.439291 [Byte1]: 63
3477 20:15:05.444305
3478 20:15:05.444725 Set Vref, RX VrefLevel [Byte0]: 64
3479 20:15:05.447116 [Byte1]: 64
3480 20:15:05.451877
3481 20:15:05.452291 Set Vref, RX VrefLevel [Byte0]: 65
3482 20:15:05.455355 [Byte1]: 65
3483 20:15:05.459698
3484 20:15:05.460118 Set Vref, RX VrefLevel [Byte0]: 66
3485 20:15:05.463233 [Byte1]: 66
3486 20:15:05.467900
3487 20:15:05.468361 Set Vref, RX VrefLevel [Byte0]: 67
3488 20:15:05.471091 [Byte1]: 67
3489 20:15:05.475842
3490 20:15:05.476263 Final RX Vref Byte 0 = 55 to rank0
3491 20:15:05.479484 Final RX Vref Byte 1 = 48 to rank0
3492 20:15:05.482313 Final RX Vref Byte 0 = 55 to rank1
3493 20:15:05.486047 Final RX Vref Byte 1 = 48 to rank1==
3494 20:15:05.489210 Dram Type= 6, Freq= 0, CH_1, rank 0
3495 20:15:05.495655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 20:15:05.496361 ==
3497 20:15:05.496871 DQS Delay:
3498 20:15:05.497383 DQS0 = 0, DQS1 = 0
3499 20:15:05.499032 DQM Delay:
3500 20:15:05.499458 DQM0 = 114, DQM1 = 105
3501 20:15:05.502362 DQ Delay:
3502 20:15:05.505818 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3503 20:15:05.509161 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3504 20:15:05.512231 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3505 20:15:05.515648 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3506 20:15:05.516154
3507 20:15:05.516636
3508 20:15:05.525583 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3509 20:15:05.526172 CH1 RK0: MR19=303, MR18=F0F7
3510 20:15:05.532317 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3511 20:15:05.532741
3512 20:15:05.535420 ----->DramcWriteLeveling(PI) begin...
3513 20:15:05.535848 ==
3514 20:15:05.538958 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 20:15:05.545531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 20:15:05.545959 ==
3517 20:15:05.548656 Write leveling (Byte 0): 24 => 24
3518 20:15:05.549077 Write leveling (Byte 1): 26 => 26
3519 20:15:05.552302 DramcWriteLeveling(PI) end<-----
3520 20:15:05.552724
3521 20:15:05.553058 ==
3522 20:15:05.555304 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 20:15:05.562206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 20:15:05.562675 ==
3525 20:15:05.565395 [Gating] SW mode calibration
3526 20:15:05.572169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3527 20:15:05.575536 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3528 20:15:05.581826 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 20:15:05.585198 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 20:15:05.588858 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 20:15:05.595383 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 20:15:05.598642 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 20:15:05.601819 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 20:15:05.608472 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 0)
3535 20:15:05.611821 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3536 20:15:05.615146 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 20:15:05.618550 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 20:15:05.625089 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 20:15:05.628614 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 20:15:05.632004 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 20:15:05.638490 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3542 20:15:05.641932 1 0 24 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
3543 20:15:05.645090 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3544 20:15:05.651839 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 20:15:05.655190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 20:15:05.658330 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 20:15:05.664958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 20:15:05.668502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 20:15:05.671619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 20:15:05.678200 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3551 20:15:05.681766 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3552 20:15:05.685080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 20:15:05.691687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 20:15:05.694937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 20:15:05.698253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 20:15:05.705120 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 20:15:05.708093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 20:15:05.711700 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 20:15:05.718158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 20:15:05.721227 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 20:15:05.724860 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 20:15:05.731006 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 20:15:05.734592 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 20:15:05.738077 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 20:15:05.744818 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 20:15:05.747778 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3567 20:15:05.750953 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3568 20:15:05.754521 Total UI for P1: 0, mck2ui 16
3569 20:15:05.757586 best dqsien dly found for B0: ( 1, 3, 24)
3570 20:15:05.764345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 20:15:05.764784 Total UI for P1: 0, mck2ui 16
3572 20:15:05.767701 best dqsien dly found for B1: ( 1, 3, 26)
3573 20:15:05.774180 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3574 20:15:05.777417 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3575 20:15:05.777878
3576 20:15:05.780891 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3577 20:15:05.784221 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3578 20:15:05.787459 [Gating] SW calibration Done
3579 20:15:05.787976 ==
3580 20:15:05.790894 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 20:15:05.793965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 20:15:05.794388 ==
3583 20:15:05.797512 RX Vref Scan: 0
3584 20:15:05.797938
3585 20:15:05.798269 RX Vref 0 -> 0, step: 1
3586 20:15:05.798581
3587 20:15:05.800566 RX Delay -40 -> 252, step: 8
3588 20:15:05.804041 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3589 20:15:05.810478 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3590 20:15:05.813937 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3591 20:15:05.817405 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3592 20:15:05.820917 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3593 20:15:05.824080 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3594 20:15:05.830846 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3595 20:15:05.834053 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3596 20:15:05.837304 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3597 20:15:05.840567 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3598 20:15:05.844006 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3599 20:15:05.850620 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3600 20:15:05.853658 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3601 20:15:05.857022 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3602 20:15:05.860445 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3603 20:15:05.863793 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3604 20:15:05.867085 ==
3605 20:15:05.867537 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 20:15:05.873851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 20:15:05.874318 ==
3608 20:15:05.874673 DQS Delay:
3609 20:15:05.876999 DQS0 = 0, DQS1 = 0
3610 20:15:05.877445 DQM Delay:
3611 20:15:05.880369 DQM0 = 110, DQM1 = 107
3612 20:15:05.880808 DQ Delay:
3613 20:15:05.883608 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3614 20:15:05.887129 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3615 20:15:05.890372 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3616 20:15:05.893840 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3617 20:15:05.894271
3618 20:15:05.894601
3619 20:15:05.894934 ==
3620 20:15:05.896888 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 20:15:05.900306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 20:15:05.903602 ==
3623 20:15:05.904140
3624 20:15:05.904476
3625 20:15:05.904805 TX Vref Scan disable
3626 20:15:05.907004 == TX Byte 0 ==
3627 20:15:05.910095 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3628 20:15:05.913719 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3629 20:15:05.916784 == TX Byte 1 ==
3630 20:15:05.920094 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3631 20:15:05.923223 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3632 20:15:05.926830 ==
3633 20:15:05.929832 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 20:15:05.933436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 20:15:05.933889 ==
3636 20:15:05.944271 TX Vref=22, minBit 9, minWin=25, winSum=420
3637 20:15:05.947943 TX Vref=24, minBit 9, minWin=25, winSum=426
3638 20:15:05.950890 TX Vref=26, minBit 1, minWin=26, winSum=428
3639 20:15:05.954705 TX Vref=28, minBit 1, minWin=26, winSum=430
3640 20:15:05.957580 TX Vref=30, minBit 0, minWin=26, winSum=430
3641 20:15:05.964444 TX Vref=32, minBit 8, minWin=26, winSum=428
3642 20:15:05.967493 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3643 20:15:05.967919
3644 20:15:05.970938 Final TX Range 1 Vref 28
3645 20:15:05.971327
3646 20:15:05.971662 ==
3647 20:15:05.974042 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 20:15:05.977685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 20:15:05.978111 ==
3650 20:15:05.980907
3651 20:15:05.981323
3652 20:15:05.981692 TX Vref Scan disable
3653 20:15:05.983883 == TX Byte 0 ==
3654 20:15:05.987673 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3655 20:15:05.993908 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3656 20:15:05.994424 == TX Byte 1 ==
3657 20:15:05.997387 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3658 20:15:06.004254 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3659 20:15:06.004679
3660 20:15:06.005010 [DATLAT]
3661 20:15:06.005322 Freq=1200, CH1 RK1
3662 20:15:06.005689
3663 20:15:06.007448 DATLAT Default: 0xd
3664 20:15:06.007866 0, 0xFFFF, sum = 0
3665 20:15:06.010769 1, 0xFFFF, sum = 0
3666 20:15:06.014112 2, 0xFFFF, sum = 0
3667 20:15:06.014555 3, 0xFFFF, sum = 0
3668 20:15:06.017104 4, 0xFFFF, sum = 0
3669 20:15:06.017537 5, 0xFFFF, sum = 0
3670 20:15:06.020498 6, 0xFFFF, sum = 0
3671 20:15:06.020883 7, 0xFFFF, sum = 0
3672 20:15:06.023974 8, 0xFFFF, sum = 0
3673 20:15:06.024450 9, 0xFFFF, sum = 0
3674 20:15:06.027067 10, 0xFFFF, sum = 0
3675 20:15:06.027521 11, 0xFFFF, sum = 0
3676 20:15:06.030728 12, 0x0, sum = 1
3677 20:15:06.031178 13, 0x0, sum = 2
3678 20:15:06.034099 14, 0x0, sum = 3
3679 20:15:06.034539 15, 0x0, sum = 4
3680 20:15:06.037084 best_step = 13
3681 20:15:06.037557
3682 20:15:06.037919 ==
3683 20:15:06.040504 Dram Type= 6, Freq= 0, CH_1, rank 1
3684 20:15:06.044029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3685 20:15:06.044473 ==
3686 20:15:06.044824 RX Vref Scan: 0
3687 20:15:06.045132
3688 20:15:06.047158 RX Vref 0 -> 0, step: 1
3689 20:15:06.047586
3690 20:15:06.050407 RX Delay -21 -> 252, step: 4
3691 20:15:06.053755 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3692 20:15:06.060550 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3693 20:15:06.063968 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3694 20:15:06.067082 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3695 20:15:06.070578 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3696 20:15:06.073686 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3697 20:15:06.080433 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3698 20:15:06.083526 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3699 20:15:06.086889 iDelay=195, Bit 8, Center 96 (35 ~ 158) 124
3700 20:15:06.090206 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3701 20:15:06.093553 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3702 20:15:06.100252 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3703 20:15:06.103450 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3704 20:15:06.106811 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3705 20:15:06.110480 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3706 20:15:06.116575 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3707 20:15:06.116961 ==
3708 20:15:06.119903 Dram Type= 6, Freq= 0, CH_1, rank 1
3709 20:15:06.123127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3710 20:15:06.123501 ==
3711 20:15:06.123839 DQS Delay:
3712 20:15:06.126423 DQS0 = 0, DQS1 = 0
3713 20:15:06.126909 DQM Delay:
3714 20:15:06.129936 DQM0 = 111, DQM1 = 108
3715 20:15:06.130296 DQ Delay:
3716 20:15:06.133227 DQ0 =114, DQ1 =110, DQ2 =102, DQ3 =108
3717 20:15:06.136550 DQ4 =108, DQ5 =118, DQ6 =120, DQ7 =110
3718 20:15:06.139984 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =102
3719 20:15:06.143428 DQ12 =116, DQ13 =112, DQ14 =114, DQ15 =116
3720 20:15:06.143831
3721 20:15:06.144151
3722 20:15:06.153029 [DQSOSCAuto] RK1, (LSB)MR18= 0xf606, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3723 20:15:06.156438 CH1 RK1: MR19=304, MR18=F606
3724 20:15:06.162740 CH1_RK1: MR19=0x304, MR18=0xF606, DQSOSC=407, MR23=63, INC=39, DEC=26
3725 20:15:06.163151 [RxdqsGatingPostProcess] freq 1200
3726 20:15:06.169581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3727 20:15:06.173081 best DQS0 dly(2T, 0.5T) = (0, 11)
3728 20:15:06.176351 best DQS1 dly(2T, 0.5T) = (0, 11)
3729 20:15:06.179739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3730 20:15:06.182913 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3731 20:15:06.186476 best DQS0 dly(2T, 0.5T) = (0, 11)
3732 20:15:06.189422 best DQS1 dly(2T, 0.5T) = (0, 11)
3733 20:15:06.192911 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3734 20:15:06.196196 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3735 20:15:06.199271 Pre-setting of DQS Precalculation
3736 20:15:06.202735 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3737 20:15:06.209147 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3738 20:15:06.219025 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3739 20:15:06.219436
3740 20:15:06.219756
3741 20:15:06.222381 [Calibration Summary] 2400 Mbps
3742 20:15:06.222833 CH 0, Rank 0
3743 20:15:06.225777 SW Impedance : PASS
3744 20:15:06.226349 DUTY Scan : NO K
3745 20:15:06.229156 ZQ Calibration : PASS
3746 20:15:06.232200 Jitter Meter : NO K
3747 20:15:06.232624 CBT Training : PASS
3748 20:15:06.235448 Write leveling : PASS
3749 20:15:06.235875 RX DQS gating : PASS
3750 20:15:06.238766 RX DQ/DQS(RDDQC) : PASS
3751 20:15:06.242274 TX DQ/DQS : PASS
3752 20:15:06.242703 RX DATLAT : PASS
3753 20:15:06.245427 RX DQ/DQS(Engine): PASS
3754 20:15:06.248908 TX OE : NO K
3755 20:15:06.249342 All Pass.
3756 20:15:06.249801
3757 20:15:06.250205 CH 0, Rank 1
3758 20:15:06.252258 SW Impedance : PASS
3759 20:15:06.255768 DUTY Scan : NO K
3760 20:15:06.256196 ZQ Calibration : PASS
3761 20:15:06.258705 Jitter Meter : NO K
3762 20:15:06.262142 CBT Training : PASS
3763 20:15:06.262568 Write leveling : PASS
3764 20:15:06.265546 RX DQS gating : PASS
3765 20:15:06.268993 RX DQ/DQS(RDDQC) : PASS
3766 20:15:06.269460 TX DQ/DQS : PASS
3767 20:15:06.272482 RX DATLAT : PASS
3768 20:15:06.275477 RX DQ/DQS(Engine): PASS
3769 20:15:06.275891 TX OE : NO K
3770 20:15:06.278711 All Pass.
3771 20:15:06.279121
3772 20:15:06.279446 CH 1, Rank 0
3773 20:15:06.282043 SW Impedance : PASS
3774 20:15:06.282455 DUTY Scan : NO K
3775 20:15:06.285582 ZQ Calibration : PASS
3776 20:15:06.288811 Jitter Meter : NO K
3777 20:15:06.289222 CBT Training : PASS
3778 20:15:06.292230 Write leveling : PASS
3779 20:15:06.292640 RX DQS gating : PASS
3780 20:15:06.295424 RX DQ/DQS(RDDQC) : PASS
3781 20:15:06.298825 TX DQ/DQS : PASS
3782 20:15:06.299239 RX DATLAT : PASS
3783 20:15:06.301941 RX DQ/DQS(Engine): PASS
3784 20:15:06.305423 TX OE : NO K
3785 20:15:06.305905 All Pass.
3786 20:15:06.306409
3787 20:15:06.306874 CH 1, Rank 1
3788 20:15:06.308689 SW Impedance : PASS
3789 20:15:06.311957 DUTY Scan : NO K
3790 20:15:06.312423 ZQ Calibration : PASS
3791 20:15:06.315174 Jitter Meter : NO K
3792 20:15:06.318725 CBT Training : PASS
3793 20:15:06.319151 Write leveling : PASS
3794 20:15:06.321791 RX DQS gating : PASS
3795 20:15:06.325141 RX DQ/DQS(RDDQC) : PASS
3796 20:15:06.325625 TX DQ/DQS : PASS
3797 20:15:06.328448 RX DATLAT : PASS
3798 20:15:06.332024 RX DQ/DQS(Engine): PASS
3799 20:15:06.332436 TX OE : NO K
3800 20:15:06.332766 All Pass.
3801 20:15:06.335112
3802 20:15:06.335537 DramC Write-DBI off
3803 20:15:06.338519 PER_BANK_REFRESH: Hybrid Mode
3804 20:15:06.338946 TX_TRACKING: ON
3805 20:15:06.348553 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3806 20:15:06.351729 [FAST_K] Save calibration result to emmc
3807 20:15:06.354917 dramc_set_vcore_voltage set vcore to 650000
3808 20:15:06.358292 Read voltage for 600, 5
3809 20:15:06.358757 Vio18 = 0
3810 20:15:06.361767 Vcore = 650000
3811 20:15:06.362190 Vdram = 0
3812 20:15:06.362617 Vddq = 0
3813 20:15:06.363021 Vmddr = 0
3814 20:15:06.368492 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3815 20:15:06.374862 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3816 20:15:06.375303 MEM_TYPE=3, freq_sel=19
3817 20:15:06.378525 sv_algorithm_assistance_LP4_1600
3818 20:15:06.381541 ============ PULL DRAM RESETB DOWN ============
3819 20:15:06.388480 ========== PULL DRAM RESETB DOWN end =========
3820 20:15:06.391699 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3821 20:15:06.395085 ===================================
3822 20:15:06.398188 LPDDR4 DRAM CONFIGURATION
3823 20:15:06.401852 ===================================
3824 20:15:06.402277 EX_ROW_EN[0] = 0x0
3825 20:15:06.404863 EX_ROW_EN[1] = 0x0
3826 20:15:06.405286 LP4Y_EN = 0x0
3827 20:15:06.408289 WORK_FSP = 0x0
3828 20:15:06.408784 WL = 0x2
3829 20:15:06.411423 RL = 0x2
3830 20:15:06.415103 BL = 0x2
3831 20:15:06.415531 RPST = 0x0
3832 20:15:06.418167 RD_PRE = 0x0
3833 20:15:06.418594 WR_PRE = 0x1
3834 20:15:06.421525 WR_PST = 0x0
3835 20:15:06.421973 DBI_WR = 0x0
3836 20:15:06.424826 DBI_RD = 0x0
3837 20:15:06.425256 OTF = 0x1
3838 20:15:06.428177 ===================================
3839 20:15:06.431504 ===================================
3840 20:15:06.434665 ANA top config
3841 20:15:06.437785 ===================================
3842 20:15:06.438211 DLL_ASYNC_EN = 0
3843 20:15:06.441582 ALL_SLAVE_EN = 1
3844 20:15:06.444814 NEW_RANK_MODE = 1
3845 20:15:06.448177 DLL_IDLE_MODE = 1
3846 20:15:06.448590 LP45_APHY_COMB_EN = 1
3847 20:15:06.451301 TX_ODT_DIS = 1
3848 20:15:06.454797 NEW_8X_MODE = 1
3849 20:15:06.457852 ===================================
3850 20:15:06.461256 ===================================
3851 20:15:06.464341 data_rate = 1200
3852 20:15:06.467904 CKR = 1
3853 20:15:06.470959 DQ_P2S_RATIO = 8
3854 20:15:06.474379 ===================================
3855 20:15:06.474797 CA_P2S_RATIO = 8
3856 20:15:06.477803 DQ_CA_OPEN = 0
3857 20:15:06.481080 DQ_SEMI_OPEN = 0
3858 20:15:06.484134 CA_SEMI_OPEN = 0
3859 20:15:06.487717 CA_FULL_RATE = 0
3860 20:15:06.490837 DQ_CKDIV4_EN = 1
3861 20:15:06.491359 CA_CKDIV4_EN = 1
3862 20:15:06.494111 CA_PREDIV_EN = 0
3863 20:15:06.497382 PH8_DLY = 0
3864 20:15:06.500920 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3865 20:15:06.503936 DQ_AAMCK_DIV = 4
3866 20:15:06.507505 CA_AAMCK_DIV = 4
3867 20:15:06.507918 CA_ADMCK_DIV = 4
3868 20:15:06.510562 DQ_TRACK_CA_EN = 0
3869 20:15:06.513985 CA_PICK = 600
3870 20:15:06.517249 CA_MCKIO = 600
3871 20:15:06.521422 MCKIO_SEMI = 0
3872 20:15:06.523784 PLL_FREQ = 2288
3873 20:15:06.527005 DQ_UI_PI_RATIO = 32
3874 20:15:06.527564 CA_UI_PI_RATIO = 0
3875 20:15:06.530500 ===================================
3876 20:15:06.533760 ===================================
3877 20:15:06.537121 memory_type:LPDDR4
3878 20:15:06.540248 GP_NUM : 10
3879 20:15:06.540656 SRAM_EN : 1
3880 20:15:06.543582 MD32_EN : 0
3881 20:15:06.547100 ===================================
3882 20:15:06.550370 [ANA_INIT] >>>>>>>>>>>>>>
3883 20:15:06.553575 <<<<<< [CONFIGURE PHASE]: ANA_TX
3884 20:15:06.556997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3885 20:15:06.559866 ===================================
3886 20:15:06.563399 data_rate = 1200,PCW = 0X5800
3887 20:15:06.566800 ===================================
3888 20:15:06.569887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3889 20:15:06.573245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3890 20:15:06.579838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3891 20:15:06.583263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3892 20:15:06.586513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3893 20:15:06.589897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3894 20:15:06.593185 [ANA_INIT] flow start
3895 20:15:06.596594 [ANA_INIT] PLL >>>>>>>>
3896 20:15:06.597026 [ANA_INIT] PLL <<<<<<<<
3897 20:15:06.599907 [ANA_INIT] MIDPI >>>>>>>>
3898 20:15:06.603155 [ANA_INIT] MIDPI <<<<<<<<
3899 20:15:06.605872 [ANA_INIT] DLL >>>>>>>>
3900 20:15:06.605952 [ANA_INIT] flow end
3901 20:15:06.609459 ============ LP4 DIFF to SE enter ============
3902 20:15:06.615616 ============ LP4 DIFF to SE exit ============
3903 20:15:06.615697 [ANA_INIT] <<<<<<<<<<<<<
3904 20:15:06.619062 [Flow] Enable top DCM control >>>>>
3905 20:15:06.622533 [Flow] Enable top DCM control <<<<<
3906 20:15:06.625768 Enable DLL master slave shuffle
3907 20:15:06.632301 ==============================================================
3908 20:15:06.632383 Gating Mode config
3909 20:15:06.638695 ==============================================================
3910 20:15:06.642327 Config description:
3911 20:15:06.652002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3912 20:15:06.658617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3913 20:15:06.662246 SELPH_MODE 0: By rank 1: By Phase
3914 20:15:06.668765 ==============================================================
3915 20:15:06.671901 GAT_TRACK_EN = 1
3916 20:15:06.675360 RX_GATING_MODE = 2
3917 20:15:06.675440 RX_GATING_TRACK_MODE = 2
3918 20:15:06.678593 SELPH_MODE = 1
3919 20:15:06.681964 PICG_EARLY_EN = 1
3920 20:15:06.685192 VALID_LAT_VALUE = 1
3921 20:15:06.691696 ==============================================================
3922 20:15:06.694831 Enter into Gating configuration >>>>
3923 20:15:06.698205 Exit from Gating configuration <<<<
3924 20:15:06.701463 Enter into DVFS_PRE_config >>>>>
3925 20:15:06.711411 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3926 20:15:06.714482 Exit from DVFS_PRE_config <<<<<
3927 20:15:06.717920 Enter into PICG configuration >>>>
3928 20:15:06.721349 Exit from PICG configuration <<<<
3929 20:15:06.724478 [RX_INPUT] configuration >>>>>
3930 20:15:06.727849 [RX_INPUT] configuration <<<<<
3931 20:15:06.731202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3932 20:15:06.737912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3933 20:15:06.744146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3934 20:15:06.750825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3935 20:15:06.757802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3936 20:15:06.760877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3937 20:15:06.767431 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3938 20:15:06.770937 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3939 20:15:06.774017 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3940 20:15:06.777389 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3941 20:15:06.783905 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3942 20:15:06.787514 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 20:15:06.790399 ===================================
3944 20:15:06.793982 LPDDR4 DRAM CONFIGURATION
3945 20:15:06.797050 ===================================
3946 20:15:06.797176 EX_ROW_EN[0] = 0x0
3947 20:15:06.800457 EX_ROW_EN[1] = 0x0
3948 20:15:06.800592 LP4Y_EN = 0x0
3949 20:15:06.803797 WORK_FSP = 0x0
3950 20:15:06.803900 WL = 0x2
3951 20:15:06.806891 RL = 0x2
3952 20:15:06.810463 BL = 0x2
3953 20:15:06.810610 RPST = 0x0
3954 20:15:06.813667 RD_PRE = 0x0
3955 20:15:06.813800 WR_PRE = 0x1
3956 20:15:06.816924 WR_PST = 0x0
3957 20:15:06.817105 DBI_WR = 0x0
3958 20:15:06.820222 DBI_RD = 0x0
3959 20:15:06.820322 OTF = 0x1
3960 20:15:06.823618 ===================================
3961 20:15:06.826707 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3962 20:15:06.833633 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3963 20:15:06.836794 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3964 20:15:06.840007 ===================================
3965 20:15:06.843705 LPDDR4 DRAM CONFIGURATION
3966 20:15:06.846774 ===================================
3967 20:15:06.846876 EX_ROW_EN[0] = 0x10
3968 20:15:06.850239 EX_ROW_EN[1] = 0x0
3969 20:15:06.850370 LP4Y_EN = 0x0
3970 20:15:06.853462 WORK_FSP = 0x0
3971 20:15:06.853654 WL = 0x2
3972 20:15:06.856552 RL = 0x2
3973 20:15:06.856692 BL = 0x2
3974 20:15:06.860167 RPST = 0x0
3975 20:15:06.863459 RD_PRE = 0x0
3976 20:15:06.863565 WR_PRE = 0x1
3977 20:15:06.866639 WR_PST = 0x0
3978 20:15:06.866740 DBI_WR = 0x0
3979 20:15:06.870113 DBI_RD = 0x0
3980 20:15:06.870216 OTF = 0x1
3981 20:15:06.873081 ===================================
3982 20:15:06.879695 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3983 20:15:06.883478 nWR fixed to 30
3984 20:15:06.886687 [ModeRegInit_LP4] CH0 RK0
3985 20:15:06.886768 [ModeRegInit_LP4] CH0 RK1
3986 20:15:06.890267 [ModeRegInit_LP4] CH1 RK0
3987 20:15:06.893632 [ModeRegInit_LP4] CH1 RK1
3988 20:15:06.893720 match AC timing 17
3989 20:15:06.900011 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3990 20:15:06.903675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3991 20:15:06.906855 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3992 20:15:06.913413 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3993 20:15:06.916897 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3994 20:15:06.917007 ==
3995 20:15:06.920289 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 20:15:06.923419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 20:15:06.923501 ==
3998 20:15:06.929929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 20:15:06.936713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4000 20:15:06.939792 [CA 0] Center 37 (7~67) winsize 61
4001 20:15:06.943509 [CA 1] Center 36 (6~67) winsize 62
4002 20:15:06.946807 [CA 2] Center 35 (5~65) winsize 61
4003 20:15:06.949742 [CA 3] Center 35 (5~65) winsize 61
4004 20:15:06.953342 [CA 4] Center 34 (4~65) winsize 62
4005 20:15:06.956684 [CA 5] Center 33 (3~64) winsize 62
4006 20:15:06.956764
4007 20:15:06.959944 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4008 20:15:06.960016
4009 20:15:06.962917 [CATrainingPosCal] consider 1 rank data
4010 20:15:06.966669 u2DelayCellTimex100 = 270/100 ps
4011 20:15:06.969814 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4012 20:15:06.973026 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4013 20:15:06.976496 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4014 20:15:06.979727 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4015 20:15:06.986410 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4016 20:15:06.989479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4017 20:15:06.989550
4018 20:15:06.992946 CA PerBit enable=1, Macro0, CA PI delay=33
4019 20:15:06.993017
4020 20:15:06.996261 [CBTSetCACLKResult] CA Dly = 33
4021 20:15:06.996334 CS Dly: 4 (0~35)
4022 20:15:06.996403 ==
4023 20:15:06.999385 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 20:15:07.006087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 20:15:07.006170 ==
4026 20:15:07.009447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4027 20:15:07.016116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4028 20:15:07.019424 [CA 0] Center 37 (7~67) winsize 61
4029 20:15:07.022500 [CA 1] Center 36 (6~67) winsize 62
4030 20:15:07.026086 [CA 2] Center 35 (5~65) winsize 61
4031 20:15:07.029127 [CA 3] Center 34 (4~65) winsize 62
4032 20:15:07.032722 [CA 4] Center 33 (3~64) winsize 62
4033 20:15:07.035734 [CA 5] Center 34 (4~64) winsize 61
4034 20:15:07.035811
4035 20:15:07.039109 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4036 20:15:07.039190
4037 20:15:07.042563 [CATrainingPosCal] consider 2 rank data
4038 20:15:07.045967 u2DelayCellTimex100 = 270/100 ps
4039 20:15:07.049246 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4040 20:15:07.052291 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4041 20:15:07.058858 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4042 20:15:07.062508 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4043 20:15:07.065760 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4044 20:15:07.068988 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4045 20:15:07.069086
4046 20:15:07.072433 CA PerBit enable=1, Macro0, CA PI delay=34
4047 20:15:07.072523
4048 20:15:07.075651 [CBTSetCACLKResult] CA Dly = 34
4049 20:15:07.075747 CS Dly: 5 (0~37)
4050 20:15:07.075834
4051 20:15:07.078962 ----->DramcWriteLeveling(PI) begin...
4052 20:15:07.082587 ==
4053 20:15:07.085539 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 20:15:07.088938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 20:15:07.089019 ==
4056 20:15:07.092463 Write leveling (Byte 0): 35 => 35
4057 20:15:07.095649 Write leveling (Byte 1): 31 => 31
4058 20:15:07.098906 DramcWriteLeveling(PI) end<-----
4059 20:15:07.098999
4060 20:15:07.099074 ==
4061 20:15:07.102650 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 20:15:07.105402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 20:15:07.105543 ==
4064 20:15:07.108898 [Gating] SW mode calibration
4065 20:15:07.115566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4066 20:15:07.122276 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4067 20:15:07.125233 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 20:15:07.129022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4069 20:15:07.135577 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4070 20:15:07.138822 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (0 0) (1 0)
4071 20:15:07.142093 0 9 16 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4072 20:15:07.148533 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 20:15:07.151873 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 20:15:07.155282 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 20:15:07.162020 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 20:15:07.165414 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 20:15:07.168615 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 20:15:07.175169 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4079 20:15:07.178780 0 10 16 | B1->B0 | 3232 3c3c | 1 0 | (0 0) (0 0)
4080 20:15:07.181778 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 20:15:07.185253 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 20:15:07.191767 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 20:15:07.195359 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 20:15:07.198450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 20:15:07.205194 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 20:15:07.208574 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 20:15:07.211697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4088 20:15:07.218631 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 20:15:07.221791 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 20:15:07.225084 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 20:15:07.231818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 20:15:07.234891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 20:15:07.238392 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 20:15:07.244996 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 20:15:07.248204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 20:15:07.251555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 20:15:07.258070 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 20:15:07.261376 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 20:15:07.264397 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 20:15:07.271231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 20:15:07.274422 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 20:15:07.277783 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4103 20:15:07.284574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4104 20:15:07.287729 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 20:15:07.291171 Total UI for P1: 0, mck2ui 16
4106 20:15:07.294255 best dqsien dly found for B0: ( 0, 13, 14)
4107 20:15:07.297596 Total UI for P1: 0, mck2ui 16
4108 20:15:07.301111 best dqsien dly found for B1: ( 0, 13, 18)
4109 20:15:07.304552 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4110 20:15:07.307522 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4111 20:15:07.307603
4112 20:15:07.311016 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4113 20:15:07.314086 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4114 20:15:07.317466 [Gating] SW calibration Done
4115 20:15:07.317587 ==
4116 20:15:07.321062 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 20:15:07.324105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 20:15:07.327539 ==
4119 20:15:07.327633 RX Vref Scan: 0
4120 20:15:07.327697
4121 20:15:07.330730 RX Vref 0 -> 0, step: 1
4122 20:15:07.330839
4123 20:15:07.334104 RX Delay -230 -> 252, step: 16
4124 20:15:07.337388 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4125 20:15:07.340801 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4126 20:15:07.343949 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4127 20:15:07.350435 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4128 20:15:07.353678 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4129 20:15:07.357299 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4130 20:15:07.360360 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4131 20:15:07.364018 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4132 20:15:07.370611 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4133 20:15:07.373898 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4134 20:15:07.377009 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4135 20:15:07.380472 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4136 20:15:07.387143 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4137 20:15:07.390579 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4138 20:15:07.393748 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4139 20:15:07.397051 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4140 20:15:07.400455 ==
4141 20:15:07.403756 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 20:15:07.407125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 20:15:07.407543 ==
4144 20:15:07.407874 DQS Delay:
4145 20:15:07.410101 DQS0 = 0, DQS1 = 0
4146 20:15:07.410518 DQM Delay:
4147 20:15:07.413824 DQM0 = 36, DQM1 = 29
4148 20:15:07.414395 DQ Delay:
4149 20:15:07.417047 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4150 20:15:07.420450 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4151 20:15:07.423840 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4152 20:15:07.426855 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4153 20:15:07.427270
4154 20:15:07.427674
4155 20:15:07.428249 ==
4156 20:15:07.430403 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 20:15:07.433746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 20:15:07.434165 ==
4159 20:15:07.434497
4160 20:15:07.434803
4161 20:15:07.436853 TX Vref Scan disable
4162 20:15:07.440134 == TX Byte 0 ==
4163 20:15:07.443665 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4164 20:15:07.446783 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4165 20:15:07.450169 == TX Byte 1 ==
4166 20:15:07.453898 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4167 20:15:07.456880 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4168 20:15:07.457298 ==
4169 20:15:07.460255 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 20:15:07.466746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 20:15:07.467169 ==
4172 20:15:07.467526
4173 20:15:07.467831
4174 20:15:07.468186 TX Vref Scan disable
4175 20:15:07.470954 == TX Byte 0 ==
4176 20:15:07.474418 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4177 20:15:07.481083 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4178 20:15:07.481517 == TX Byte 1 ==
4179 20:15:07.484251 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4180 20:15:07.491046 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4181 20:15:07.491503
4182 20:15:07.491859 [DATLAT]
4183 20:15:07.492196 Freq=600, CH0 RK0
4184 20:15:07.492497
4185 20:15:07.494275 DATLAT Default: 0x9
4186 20:15:07.494717 0, 0xFFFF, sum = 0
4187 20:15:07.497617 1, 0xFFFF, sum = 0
4188 20:15:07.500814 2, 0xFFFF, sum = 0
4189 20:15:07.501247 3, 0xFFFF, sum = 0
4190 20:15:07.503987 4, 0xFFFF, sum = 0
4191 20:15:07.504409 5, 0xFFFF, sum = 0
4192 20:15:07.507382 6, 0xFFFF, sum = 0
4193 20:15:07.507803 7, 0xFFFF, sum = 0
4194 20:15:07.510736 8, 0x0, sum = 1
4195 20:15:07.511156 9, 0x0, sum = 2
4196 20:15:07.511488 10, 0x0, sum = 3
4197 20:15:07.513934 11, 0x0, sum = 4
4198 20:15:07.514354 best_step = 9
4199 20:15:07.514683
4200 20:15:07.517253 ==
4201 20:15:07.517719 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 20:15:07.523817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 20:15:07.524330 ==
4204 20:15:07.524664 RX Vref Scan: 1
4205 20:15:07.524975
4206 20:15:07.527250 RX Vref 0 -> 0, step: 1
4207 20:15:07.527671
4208 20:15:07.530281 RX Delay -195 -> 252, step: 8
4209 20:15:07.530702
4210 20:15:07.533780 Set Vref, RX VrefLevel [Byte0]: 61
4211 20:15:07.537251 [Byte1]: 45
4212 20:15:07.537718
4213 20:15:07.540255 Final RX Vref Byte 0 = 61 to rank0
4214 20:15:07.543553 Final RX Vref Byte 1 = 45 to rank0
4215 20:15:07.547023 Final RX Vref Byte 0 = 61 to rank1
4216 20:15:07.550280 Final RX Vref Byte 1 = 45 to rank1==
4217 20:15:07.553407 Dram Type= 6, Freq= 0, CH_0, rank 0
4218 20:15:07.556995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 20:15:07.560100 ==
4220 20:15:07.560553 DQS Delay:
4221 20:15:07.560888 DQS0 = 0, DQS1 = 0
4222 20:15:07.563441 DQM Delay:
4223 20:15:07.563855 DQM0 = 36, DQM1 = 28
4224 20:15:07.566954 DQ Delay:
4225 20:15:07.567369 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4226 20:15:07.569921 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =48
4227 20:15:07.573441 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4228 20:15:07.576577 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4229 20:15:07.576993
4230 20:15:07.580289
4231 20:15:07.586758 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4232 20:15:07.590140 CH0 RK0: MR19=808, MR18=4140
4233 20:15:07.596647 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4234 20:15:07.597065
4235 20:15:07.600054 ----->DramcWriteLeveling(PI) begin...
4236 20:15:07.600476 ==
4237 20:15:07.603422 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 20:15:07.606300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 20:15:07.606719 ==
4240 20:15:07.609801 Write leveling (Byte 0): 34 => 34
4241 20:15:07.613206 Write leveling (Byte 1): 30 => 30
4242 20:15:07.616310 DramcWriteLeveling(PI) end<-----
4243 20:15:07.616724
4244 20:15:07.617052 ==
4245 20:15:07.619843 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 20:15:07.622977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 20:15:07.623390 ==
4248 20:15:07.626316 [Gating] SW mode calibration
4249 20:15:07.633318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4250 20:15:07.639669 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4251 20:15:07.643080 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 20:15:07.646141 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4253 20:15:07.652745 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4254 20:15:07.656232 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4255 20:15:07.659517 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4256 20:15:07.666155 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 20:15:07.669254 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 20:15:07.672750 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 20:15:07.679188 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 20:15:07.682813 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 20:15:07.685767 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 20:15:07.692383 0 10 12 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
4263 20:15:07.695809 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4264 20:15:07.699248 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 20:15:07.705889 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 20:15:07.708911 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 20:15:07.712323 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 20:15:07.719016 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 20:15:07.722190 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 20:15:07.725389 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4271 20:15:07.731969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 20:15:07.735546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 20:15:07.738721 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 20:15:07.745272 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 20:15:07.748745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 20:15:07.752017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 20:15:07.758640 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 20:15:07.762211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 20:15:07.765197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 20:15:07.771787 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 20:15:07.775391 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 20:15:07.778441 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 20:15:07.785316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 20:15:07.788360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 20:15:07.792041 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 20:15:07.798606 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4287 20:15:07.801826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4288 20:15:07.805202 Total UI for P1: 0, mck2ui 16
4289 20:15:07.808370 best dqsien dly found for B0: ( 0, 13, 12)
4290 20:15:07.811785 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 20:15:07.814947 Total UI for P1: 0, mck2ui 16
4292 20:15:07.818495 best dqsien dly found for B1: ( 0, 13, 16)
4293 20:15:07.821773 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4294 20:15:07.824705 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4295 20:15:07.825136
4296 20:15:07.831750 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4297 20:15:07.834712 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4298 20:15:07.837889 [Gating] SW calibration Done
4299 20:15:07.838362 ==
4300 20:15:07.841583 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 20:15:07.844783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 20:15:07.845260 ==
4303 20:15:07.845762 RX Vref Scan: 0
4304 20:15:07.846085
4305 20:15:07.847896 RX Vref 0 -> 0, step: 1
4306 20:15:07.848347
4307 20:15:07.851159 RX Delay -230 -> 252, step: 16
4308 20:15:07.854389 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4309 20:15:07.857943 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4310 20:15:07.864507 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4311 20:15:07.868018 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4312 20:15:07.871119 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4313 20:15:07.874500 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4314 20:15:07.881031 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4315 20:15:07.884221 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4316 20:15:07.887862 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4317 20:15:07.891307 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4318 20:15:07.894658 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4319 20:15:07.901346 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4320 20:15:07.904474 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4321 20:15:07.907741 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4322 20:15:07.911271 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4323 20:15:07.917929 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4324 20:15:07.918506 ==
4325 20:15:07.921124 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 20:15:07.924232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 20:15:07.924684 ==
4328 20:15:07.925047 DQS Delay:
4329 20:15:07.927726 DQS0 = 0, DQS1 = 0
4330 20:15:07.928117 DQM Delay:
4331 20:15:07.931326 DQM0 = 34, DQM1 = 29
4332 20:15:07.931776 DQ Delay:
4333 20:15:07.934347 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4334 20:15:07.937509 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4335 20:15:07.941071 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4336 20:15:07.944149 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4337 20:15:07.944592
4338 20:15:07.944921
4339 20:15:07.945255 ==
4340 20:15:07.947283 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 20:15:07.950842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 20:15:07.951295 ==
4343 20:15:07.954034
4344 20:15:07.954582
4345 20:15:07.954944 TX Vref Scan disable
4346 20:15:07.957339 == TX Byte 0 ==
4347 20:15:07.960991 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4348 20:15:07.964084 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4349 20:15:07.967378 == TX Byte 1 ==
4350 20:15:07.970841 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4351 20:15:07.974081 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4352 20:15:07.977578 ==
4353 20:15:07.980566 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 20:15:07.983770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 20:15:07.984202 ==
4356 20:15:07.984534
4357 20:15:07.984978
4358 20:15:07.987181 TX Vref Scan disable
4359 20:15:07.990235 == TX Byte 0 ==
4360 20:15:07.993636 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4361 20:15:07.997381 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4362 20:15:07.997856 == TX Byte 1 ==
4363 20:15:08.003678 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4364 20:15:08.007209 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4365 20:15:08.007627
4366 20:15:08.007954 [DATLAT]
4367 20:15:08.010119 Freq=600, CH0 RK1
4368 20:15:08.010611
4369 20:15:08.010966 DATLAT Default: 0x9
4370 20:15:08.013576 0, 0xFFFF, sum = 0
4371 20:15:08.016753 1, 0xFFFF, sum = 0
4372 20:15:08.017062 2, 0xFFFF, sum = 0
4373 20:15:08.020141 3, 0xFFFF, sum = 0
4374 20:15:08.020368 4, 0xFFFF, sum = 0
4375 20:15:08.023360 5, 0xFFFF, sum = 0
4376 20:15:08.023596 6, 0xFFFF, sum = 0
4377 20:15:08.026341 7, 0xFFFF, sum = 0
4378 20:15:08.026450 8, 0x0, sum = 1
4379 20:15:08.029777 9, 0x0, sum = 2
4380 20:15:08.029859 10, 0x0, sum = 3
4381 20:15:08.029924 11, 0x0, sum = 4
4382 20:15:08.033126 best_step = 9
4383 20:15:08.033207
4384 20:15:08.033271 ==
4385 20:15:08.036164 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 20:15:08.039765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 20:15:08.039847 ==
4388 20:15:08.042727 RX Vref Scan: 0
4389 20:15:08.042807
4390 20:15:08.046064 RX Vref 0 -> 0, step: 1
4391 20:15:08.046145
4392 20:15:08.046208 RX Delay -195 -> 252, step: 8
4393 20:15:08.054209 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4394 20:15:08.057081 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4395 20:15:08.060578 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4396 20:15:08.063697 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4397 20:15:08.070567 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4398 20:15:08.073706 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4399 20:15:08.077125 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4400 20:15:08.080372 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4401 20:15:08.083770 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4402 20:15:08.090310 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4403 20:15:08.093792 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4404 20:15:08.097016 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4405 20:15:08.100307 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4406 20:15:08.106912 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4407 20:15:08.110404 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4408 20:15:08.113772 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4409 20:15:08.113853 ==
4410 20:15:08.117111 Dram Type= 6, Freq= 0, CH_0, rank 1
4411 20:15:08.120329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 20:15:08.123773 ==
4413 20:15:08.123854 DQS Delay:
4414 20:15:08.123918 DQS0 = 0, DQS1 = 0
4415 20:15:08.127427 DQM Delay:
4416 20:15:08.127508 DQM0 = 33, DQM1 = 28
4417 20:15:08.130343 DQ Delay:
4418 20:15:08.130428 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4419 20:15:08.133687 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4420 20:15:08.136934 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =16
4421 20:15:08.140439 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4422 20:15:08.140520
4423 20:15:08.143581
4424 20:15:08.150526 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4425 20:15:08.153637 CH0 RK1: MR19=808, MR18=6836
4426 20:15:08.160216 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4427 20:15:08.163422 [RxdqsGatingPostProcess] freq 600
4428 20:15:08.166957 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4429 20:15:08.170082 Pre-setting of DQS Precalculation
4430 20:15:08.176912 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4431 20:15:08.176995 ==
4432 20:15:08.179907 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 20:15:08.183459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 20:15:08.183545 ==
4435 20:15:08.190064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 20:15:08.193336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4437 20:15:08.197417 [CA 0] Center 35 (5~66) winsize 62
4438 20:15:08.200802 [CA 1] Center 36 (6~66) winsize 61
4439 20:15:08.204095 [CA 2] Center 34 (4~65) winsize 62
4440 20:15:08.207683 [CA 3] Center 34 (3~65) winsize 63
4441 20:15:08.210866 [CA 4] Center 34 (4~65) winsize 62
4442 20:15:08.214143 [CA 5] Center 33 (3~64) winsize 62
4443 20:15:08.214225
4444 20:15:08.217336 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4445 20:15:08.217418
4446 20:15:08.220454 [CATrainingPosCal] consider 1 rank data
4447 20:15:08.223922 u2DelayCellTimex100 = 270/100 ps
4448 20:15:08.227180 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4449 20:15:08.233810 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4450 20:15:08.237213 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 20:15:08.240388 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4452 20:15:08.243874 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 20:15:08.246960 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 20:15:08.247042
4455 20:15:08.250362 CA PerBit enable=1, Macro0, CA PI delay=33
4456 20:15:08.250444
4457 20:15:08.253834 [CBTSetCACLKResult] CA Dly = 33
4458 20:15:08.256987 CS Dly: 4 (0~35)
4459 20:15:08.257069 ==
4460 20:15:08.260404 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 20:15:08.263782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 20:15:08.263864 ==
4463 20:15:08.270126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4464 20:15:08.273517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4465 20:15:08.277686 [CA 0] Center 36 (6~66) winsize 61
4466 20:15:08.280949 [CA 1] Center 36 (5~67) winsize 63
4467 20:15:08.284119 [CA 2] Center 34 (4~65) winsize 62
4468 20:15:08.287347 [CA 3] Center 34 (3~65) winsize 63
4469 20:15:08.290912 [CA 4] Center 34 (4~65) winsize 62
4470 20:15:08.294140 [CA 5] Center 33 (3~64) winsize 62
4471 20:15:08.294221
4472 20:15:08.297316 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4473 20:15:08.297422
4474 20:15:08.300868 [CATrainingPosCal] consider 2 rank data
4475 20:15:08.304042 u2DelayCellTimex100 = 270/100 ps
4476 20:15:08.307521 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4477 20:15:08.313862 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4478 20:15:08.317395 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4479 20:15:08.320374 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4480 20:15:08.323759 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4481 20:15:08.327027 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 20:15:08.327107
4483 20:15:08.330400 CA PerBit enable=1, Macro0, CA PI delay=33
4484 20:15:08.330480
4485 20:15:08.333721 [CBTSetCACLKResult] CA Dly = 33
4486 20:15:08.337206 CS Dly: 5 (0~37)
4487 20:15:08.337289
4488 20:15:08.340232 ----->DramcWriteLeveling(PI) begin...
4489 20:15:08.340317 ==
4490 20:15:08.343829 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 20:15:08.346862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 20:15:08.346946 ==
4493 20:15:08.350293 Write leveling (Byte 0): 28 => 28
4494 20:15:08.353436 Write leveling (Byte 1): 29 => 29
4495 20:15:08.356842 DramcWriteLeveling(PI) end<-----
4496 20:15:08.356925
4497 20:15:08.357009 ==
4498 20:15:08.360316 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 20:15:08.363460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 20:15:08.363543 ==
4501 20:15:08.366853 [Gating] SW mode calibration
4502 20:15:08.373326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4503 20:15:08.380065 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4504 20:15:08.383621 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 20:15:08.386717 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4506 20:15:08.393282 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4507 20:15:08.396539 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4508 20:15:08.400021 0 9 16 | B1->B0 | 2828 2626 | 1 0 | (1 0) (1 0)
4509 20:15:08.406454 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 20:15:08.409881 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 20:15:08.413471 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 20:15:08.420105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 20:15:08.423480 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 20:15:08.426551 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 20:15:08.433144 0 10 12 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
4516 20:15:08.436519 0 10 16 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
4517 20:15:08.439812 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 20:15:08.446415 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 20:15:08.449692 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 20:15:08.453111 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 20:15:08.459853 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 20:15:08.462975 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 20:15:08.466399 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4524 20:15:08.472934 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4525 20:15:08.476182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 20:15:08.479556 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 20:15:08.483000 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 20:15:08.489354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 20:15:08.493032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 20:15:08.496354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 20:15:08.502601 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 20:15:08.506313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 20:15:08.509411 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 20:15:08.516296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 20:15:08.519315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 20:15:08.522672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 20:15:08.529295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 20:15:08.532452 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 20:15:08.535919 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4540 20:15:08.542394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4541 20:15:08.545734 Total UI for P1: 0, mck2ui 16
4542 20:15:08.549235 best dqsien dly found for B0: ( 0, 13, 14)
4543 20:15:08.552194 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 20:15:08.555684 Total UI for P1: 0, mck2ui 16
4545 20:15:08.558941 best dqsien dly found for B1: ( 0, 13, 14)
4546 20:15:08.562380 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4547 20:15:08.565798 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4548 20:15:08.565871
4549 20:15:08.569049 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4550 20:15:08.572314 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4551 20:15:08.575797 [Gating] SW calibration Done
4552 20:15:08.575888 ==
4553 20:15:08.579001 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 20:15:08.585386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 20:15:08.585501 ==
4556 20:15:08.585568 RX Vref Scan: 0
4557 20:15:08.585629
4558 20:15:08.588924 RX Vref 0 -> 0, step: 1
4559 20:15:08.588997
4560 20:15:08.592431 RX Delay -230 -> 252, step: 16
4561 20:15:08.595318 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4562 20:15:08.598703 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4563 20:15:08.602260 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4564 20:15:08.608450 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4565 20:15:08.612019 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4566 20:15:08.615165 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4567 20:15:08.618667 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4568 20:15:08.625086 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4569 20:15:08.628511 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4570 20:15:08.631686 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4571 20:15:08.635196 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4572 20:15:08.641673 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4573 20:15:08.644958 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4574 20:15:08.648130 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4575 20:15:08.651480 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4576 20:15:08.658095 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4577 20:15:08.658216 ==
4578 20:15:08.661659 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 20:15:08.665036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 20:15:08.665117 ==
4581 20:15:08.665181 DQS Delay:
4582 20:15:08.668037 DQS0 = 0, DQS1 = 0
4583 20:15:08.668117 DQM Delay:
4584 20:15:08.671478 DQM0 = 37, DQM1 = 28
4585 20:15:08.671558 DQ Delay:
4586 20:15:08.674819 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4587 20:15:08.678160 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4588 20:15:08.681180 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4589 20:15:08.684904 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4590 20:15:08.684984
4591 20:15:08.685047
4592 20:15:08.685106 ==
4593 20:15:08.688118 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 20:15:08.691656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 20:15:08.691737 ==
4596 20:15:08.691800
4597 20:15:08.691859
4598 20:15:08.694829 TX Vref Scan disable
4599 20:15:08.697839 == TX Byte 0 ==
4600 20:15:08.701387 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4601 20:15:08.704389 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4602 20:15:08.707730 == TX Byte 1 ==
4603 20:15:08.710912 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4604 20:15:08.714360 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4605 20:15:08.714442 ==
4606 20:15:08.717890 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 20:15:08.724461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 20:15:08.724542 ==
4609 20:15:08.724605
4610 20:15:08.724664
4611 20:15:08.724720 TX Vref Scan disable
4612 20:15:08.728908 == TX Byte 0 ==
4613 20:15:08.732189 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4614 20:15:08.738857 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4615 20:15:08.738939 == TX Byte 1 ==
4616 20:15:08.741965 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4617 20:15:08.748576 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4618 20:15:08.748657
4619 20:15:08.748721 [DATLAT]
4620 20:15:08.748781 Freq=600, CH1 RK0
4621 20:15:08.748840
4622 20:15:08.751778 DATLAT Default: 0x9
4623 20:15:08.755144 0, 0xFFFF, sum = 0
4624 20:15:08.755226 1, 0xFFFF, sum = 0
4625 20:15:08.758514 2, 0xFFFF, sum = 0
4626 20:15:08.758596 3, 0xFFFF, sum = 0
4627 20:15:08.761901 4, 0xFFFF, sum = 0
4628 20:15:08.761983 5, 0xFFFF, sum = 0
4629 20:15:08.765072 6, 0xFFFF, sum = 0
4630 20:15:08.765154 7, 0xFFFF, sum = 0
4631 20:15:08.768735 8, 0x0, sum = 1
4632 20:15:08.768818 9, 0x0, sum = 2
4633 20:15:08.768883 10, 0x0, sum = 3
4634 20:15:08.771896 11, 0x0, sum = 4
4635 20:15:08.771977 best_step = 9
4636 20:15:08.772040
4637 20:15:08.772100 ==
4638 20:15:08.775318 Dram Type= 6, Freq= 0, CH_1, rank 0
4639 20:15:08.781812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 20:15:08.781920 ==
4641 20:15:08.781985 RX Vref Scan: 1
4642 20:15:08.782118
4643 20:15:08.785032 RX Vref 0 -> 0, step: 1
4644 20:15:08.785112
4645 20:15:08.788212 RX Delay -195 -> 252, step: 8
4646 20:15:08.788323
4647 20:15:08.791813 Set Vref, RX VrefLevel [Byte0]: 55
4648 20:15:08.794965 [Byte1]: 48
4649 20:15:08.795046
4650 20:15:08.798121 Final RX Vref Byte 0 = 55 to rank0
4651 20:15:08.801753 Final RX Vref Byte 1 = 48 to rank0
4652 20:15:08.804793 Final RX Vref Byte 0 = 55 to rank1
4653 20:15:08.808343 Final RX Vref Byte 1 = 48 to rank1==
4654 20:15:08.811541 Dram Type= 6, Freq= 0, CH_1, rank 0
4655 20:15:08.814794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 20:15:08.814876 ==
4657 20:15:08.818162 DQS Delay:
4658 20:15:08.818244 DQS0 = 0, DQS1 = 0
4659 20:15:08.821400 DQM Delay:
4660 20:15:08.821490 DQM0 = 39, DQM1 = 28
4661 20:15:08.821556 DQ Delay:
4662 20:15:08.824818 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4663 20:15:08.827980 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4664 20:15:08.831650 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4665 20:15:08.834638 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4666 20:15:08.834720
4667 20:15:08.838044
4668 20:15:08.844573 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4669 20:15:08.848083 CH1 RK0: MR19=808, MR18=1C2A
4670 20:15:08.854344 CH1_RK0: MR19=0x808, MR18=0x1C2A, DQSOSC=401, MR23=63, INC=163, DEC=108
4671 20:15:08.854426
4672 20:15:08.857781 ----->DramcWriteLeveling(PI) begin...
4673 20:15:08.857864 ==
4674 20:15:08.861079 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 20:15:08.864287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 20:15:08.864370 ==
4677 20:15:08.867940 Write leveling (Byte 0): 30 => 30
4678 20:15:08.870821 Write leveling (Byte 1): 30 => 30
4679 20:15:08.874436 DramcWriteLeveling(PI) end<-----
4680 20:15:08.874517
4681 20:15:08.874597 ==
4682 20:15:08.877527 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 20:15:08.880899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 20:15:08.880981 ==
4685 20:15:08.884357 [Gating] SW mode calibration
4686 20:15:08.890683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4687 20:15:08.897415 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4688 20:15:08.900890 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4689 20:15:08.904294 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4690 20:15:08.910855 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4691 20:15:08.914327 0 9 12 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (0 0)
4692 20:15:08.917416 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4693 20:15:08.924062 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 20:15:08.927329 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 20:15:08.930733 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 20:15:08.937369 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 20:15:08.940728 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 20:15:08.943796 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4699 20:15:08.950923 0 10 12 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
4700 20:15:08.953810 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 20:15:08.957449 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 20:15:08.964014 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 20:15:08.967149 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 20:15:08.970185 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 20:15:08.976861 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 20:15:08.980296 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 20:15:08.983629 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4708 20:15:08.990638 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 20:15:08.993456 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 20:15:08.997022 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 20:15:09.003692 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 20:15:09.007063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 20:15:09.010049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 20:15:09.016797 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 20:15:09.020039 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 20:15:09.023599 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 20:15:09.030078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 20:15:09.033454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 20:15:09.036775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 20:15:09.043323 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 20:15:09.046806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 20:15:09.050152 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4723 20:15:09.053427 Total UI for P1: 0, mck2ui 16
4724 20:15:09.056492 best dqsien dly found for B0: ( 0, 13, 6)
4725 20:15:09.060231 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4726 20:15:09.066688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 20:15:09.069797 Total UI for P1: 0, mck2ui 16
4728 20:15:09.073225 best dqsien dly found for B1: ( 0, 13, 14)
4729 20:15:09.076350 best DQS0 dly(MCK, UI, PI) = (0, 13, 6)
4730 20:15:09.079693 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4731 20:15:09.079775
4732 20:15:09.083398 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 6)
4733 20:15:09.086442 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4734 20:15:09.089763 [Gating] SW calibration Done
4735 20:15:09.089844 ==
4736 20:15:09.093137 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 20:15:09.096489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 20:15:09.096571 ==
4739 20:15:09.099716 RX Vref Scan: 0
4740 20:15:09.099796
4741 20:15:09.103198 RX Vref 0 -> 0, step: 1
4742 20:15:09.103280
4743 20:15:09.103345 RX Delay -230 -> 252, step: 16
4744 20:15:09.109887 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4745 20:15:09.113008 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4746 20:15:09.116350 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4747 20:15:09.119480 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4748 20:15:09.125957 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4749 20:15:09.129331 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4750 20:15:09.132547 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4751 20:15:09.135897 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4752 20:15:09.142686 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4753 20:15:09.145913 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4754 20:15:09.149496 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4755 20:15:09.152514 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4756 20:15:09.156024 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4757 20:15:09.162474 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4758 20:15:09.165950 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4759 20:15:09.169398 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4760 20:15:09.169540 ==
4761 20:15:09.172439 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 20:15:09.179087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 20:15:09.179170 ==
4764 20:15:09.179234 DQS Delay:
4765 20:15:09.179295 DQS0 = 0, DQS1 = 0
4766 20:15:09.182486 DQM Delay:
4767 20:15:09.182567 DQM0 = 35, DQM1 = 29
4768 20:15:09.185824 DQ Delay:
4769 20:15:09.189310 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4770 20:15:09.192525 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4771 20:15:09.195758 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4772 20:15:09.199229 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4773 20:15:09.199310
4774 20:15:09.199374
4775 20:15:09.199433 ==
4776 20:15:09.202325 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 20:15:09.206082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 20:15:09.206165 ==
4779 20:15:09.206229
4780 20:15:09.206289
4781 20:15:09.209275 TX Vref Scan disable
4782 20:15:09.209357 == TX Byte 0 ==
4783 20:15:09.215936 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4784 20:15:09.219197 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4785 20:15:09.219279 == TX Byte 1 ==
4786 20:15:09.225971 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4787 20:15:09.229069 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4788 20:15:09.229152 ==
4789 20:15:09.232537 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 20:15:09.235699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 20:15:09.235782 ==
4792 20:15:09.235846
4793 20:15:09.235906
4794 20:15:09.239048 TX Vref Scan disable
4795 20:15:09.242431 == TX Byte 0 ==
4796 20:15:09.245454 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4797 20:15:09.248923 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4798 20:15:09.252421 == TX Byte 1 ==
4799 20:15:09.255543 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4800 20:15:09.262081 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4801 20:15:09.262163
4802 20:15:09.262227 [DATLAT]
4803 20:15:09.262287 Freq=600, CH1 RK1
4804 20:15:09.262345
4805 20:15:09.265081 DATLAT Default: 0x9
4806 20:15:09.268354 0, 0xFFFF, sum = 0
4807 20:15:09.268438 1, 0xFFFF, sum = 0
4808 20:15:09.271740 2, 0xFFFF, sum = 0
4809 20:15:09.271822 3, 0xFFFF, sum = 0
4810 20:15:09.274880 4, 0xFFFF, sum = 0
4811 20:15:09.274990 5, 0xFFFF, sum = 0
4812 20:15:09.278595 6, 0xFFFF, sum = 0
4813 20:15:09.278678 7, 0xFFFF, sum = 0
4814 20:15:09.281751 8, 0x0, sum = 1
4815 20:15:09.281834 9, 0x0, sum = 2
4816 20:15:09.281900 10, 0x0, sum = 3
4817 20:15:09.285218 11, 0x0, sum = 4
4818 20:15:09.285300 best_step = 9
4819 20:15:09.285365
4820 20:15:09.288322 ==
4821 20:15:09.288403 Dram Type= 6, Freq= 0, CH_1, rank 1
4822 20:15:09.294827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4823 20:15:09.294910 ==
4824 20:15:09.294975 RX Vref Scan: 0
4825 20:15:09.295035
4826 20:15:09.298078 RX Vref 0 -> 0, step: 1
4827 20:15:09.298160
4828 20:15:09.301379 RX Delay -195 -> 252, step: 8
4829 20:15:09.308205 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4830 20:15:09.311444 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4831 20:15:09.314801 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4832 20:15:09.317904 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4833 20:15:09.321293 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4834 20:15:09.328072 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4835 20:15:09.331200 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4836 20:15:09.334411 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4837 20:15:09.337809 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4838 20:15:09.344497 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4839 20:15:09.347704 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4840 20:15:09.350892 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4841 20:15:09.354421 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4842 20:15:09.361074 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4843 20:15:09.364285 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4844 20:15:09.367493 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4845 20:15:09.367575 ==
4846 20:15:09.370927 Dram Type= 6, Freq= 0, CH_1, rank 1
4847 20:15:09.374272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4848 20:15:09.377315 ==
4849 20:15:09.377391 DQS Delay:
4850 20:15:09.377473 DQS0 = 0, DQS1 = 0
4851 20:15:09.380688 DQM Delay:
4852 20:15:09.380769 DQM0 = 36, DQM1 = 30
4853 20:15:09.384340 DQ Delay:
4854 20:15:09.384421 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4855 20:15:09.387311 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4856 20:15:09.390543 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4857 20:15:09.393836 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4858 20:15:09.397287
4859 20:15:09.397367
4860 20:15:09.403673 [DQSOSCAuto] RK1, (LSB)MR18= 0x3757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4861 20:15:09.407465 CH1 RK1: MR19=808, MR18=3757
4862 20:15:09.413789 CH1_RK1: MR19=0x808, MR18=0x3757, DQSOSC=393, MR23=63, INC=169, DEC=113
4863 20:15:09.417009 [RxdqsGatingPostProcess] freq 600
4864 20:15:09.420675 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4865 20:15:09.423659 Pre-setting of DQS Precalculation
4866 20:15:09.430180 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4867 20:15:09.436689 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4868 20:15:09.443359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4869 20:15:09.443441
4870 20:15:09.443505
4871 20:15:09.446711 [Calibration Summary] 1200 Mbps
4872 20:15:09.446791 CH 0, Rank 0
4873 20:15:09.450115 SW Impedance : PASS
4874 20:15:09.453502 DUTY Scan : NO K
4875 20:15:09.453597 ZQ Calibration : PASS
4876 20:15:09.456629 Jitter Meter : NO K
4877 20:15:09.460189 CBT Training : PASS
4878 20:15:09.460269 Write leveling : PASS
4879 20:15:09.463406 RX DQS gating : PASS
4880 20:15:09.466870 RX DQ/DQS(RDDQC) : PASS
4881 20:15:09.466951 TX DQ/DQS : PASS
4882 20:15:09.470116 RX DATLAT : PASS
4883 20:15:09.470196 RX DQ/DQS(Engine): PASS
4884 20:15:09.473255 TX OE : NO K
4885 20:15:09.473336 All Pass.
4886 20:15:09.473400
4887 20:15:09.476888 CH 0, Rank 1
4888 20:15:09.476969 SW Impedance : PASS
4889 20:15:09.480100 DUTY Scan : NO K
4890 20:15:09.483319 ZQ Calibration : PASS
4891 20:15:09.483399 Jitter Meter : NO K
4892 20:15:09.486628 CBT Training : PASS
4893 20:15:09.489957 Write leveling : PASS
4894 20:15:09.490037 RX DQS gating : PASS
4895 20:15:09.493225 RX DQ/DQS(RDDQC) : PASS
4896 20:15:09.496155 TX DQ/DQS : PASS
4897 20:15:09.496236 RX DATLAT : PASS
4898 20:15:09.499741 RX DQ/DQS(Engine): PASS
4899 20:15:09.503092 TX OE : NO K
4900 20:15:09.503173 All Pass.
4901 20:15:09.503237
4902 20:15:09.503296 CH 1, Rank 0
4903 20:15:09.506166 SW Impedance : PASS
4904 20:15:09.509495 DUTY Scan : NO K
4905 20:15:09.509591 ZQ Calibration : PASS
4906 20:15:09.512902 Jitter Meter : NO K
4907 20:15:09.516211 CBT Training : PASS
4908 20:15:09.516292 Write leveling : PASS
4909 20:15:09.519381 RX DQS gating : PASS
4910 20:15:09.522795 RX DQ/DQS(RDDQC) : PASS
4911 20:15:09.522875 TX DQ/DQS : PASS
4912 20:15:09.526200 RX DATLAT : PASS
4913 20:15:09.529523 RX DQ/DQS(Engine): PASS
4914 20:15:09.529603 TX OE : NO K
4915 20:15:09.532545 All Pass.
4916 20:15:09.532625
4917 20:15:09.532688 CH 1, Rank 1
4918 20:15:09.535766 SW Impedance : PASS
4919 20:15:09.535847 DUTY Scan : NO K
4920 20:15:09.539378 ZQ Calibration : PASS
4921 20:15:09.542510 Jitter Meter : NO K
4922 20:15:09.542591 CBT Training : PASS
4923 20:15:09.545958 Write leveling : PASS
4924 20:15:09.546038 RX DQS gating : PASS
4925 20:15:09.548981 RX DQ/DQS(RDDQC) : PASS
4926 20:15:09.552384 TX DQ/DQS : PASS
4927 20:15:09.552464 RX DATLAT : PASS
4928 20:15:09.555907 RX DQ/DQS(Engine): PASS
4929 20:15:09.559156 TX OE : NO K
4930 20:15:09.559237 All Pass.
4931 20:15:09.559301
4932 20:15:09.562320 DramC Write-DBI off
4933 20:15:09.562401 PER_BANK_REFRESH: Hybrid Mode
4934 20:15:09.565820 TX_TRACKING: ON
4935 20:15:09.575454 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4936 20:15:09.578846 [FAST_K] Save calibration result to emmc
4937 20:15:09.582268 dramc_set_vcore_voltage set vcore to 662500
4938 20:15:09.582348 Read voltage for 933, 3
4939 20:15:09.585568 Vio18 = 0
4940 20:15:09.585648 Vcore = 662500
4941 20:15:09.585712 Vdram = 0
4942 20:15:09.588673 Vddq = 0
4943 20:15:09.588753 Vmddr = 0
4944 20:15:09.595334 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4945 20:15:09.598822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4946 20:15:09.601847 MEM_TYPE=3, freq_sel=17
4947 20:15:09.605333 sv_algorithm_assistance_LP4_1600
4948 20:15:09.608593 ============ PULL DRAM RESETB DOWN ============
4949 20:15:09.612090 ========== PULL DRAM RESETB DOWN end =========
4950 20:15:09.618741 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4951 20:15:09.622077 ===================================
4952 20:15:09.622159 LPDDR4 DRAM CONFIGURATION
4953 20:15:09.625351 ===================================
4954 20:15:09.628570 EX_ROW_EN[0] = 0x0
4955 20:15:09.631660 EX_ROW_EN[1] = 0x0
4956 20:15:09.631742 LP4Y_EN = 0x0
4957 20:15:09.634999 WORK_FSP = 0x0
4958 20:15:09.635081 WL = 0x3
4959 20:15:09.638409 RL = 0x3
4960 20:15:09.638491 BL = 0x2
4961 20:15:09.641720 RPST = 0x0
4962 20:15:09.641801 RD_PRE = 0x0
4963 20:15:09.645089 WR_PRE = 0x1
4964 20:15:09.645171 WR_PST = 0x0
4965 20:15:09.648381 DBI_WR = 0x0
4966 20:15:09.648463 DBI_RD = 0x0
4967 20:15:09.651694 OTF = 0x1
4968 20:15:09.655036 ===================================
4969 20:15:09.658388 ===================================
4970 20:15:09.658470 ANA top config
4971 20:15:09.661367 ===================================
4972 20:15:09.664908 DLL_ASYNC_EN = 0
4973 20:15:09.668040 ALL_SLAVE_EN = 1
4974 20:15:09.671455 NEW_RANK_MODE = 1
4975 20:15:09.671538 DLL_IDLE_MODE = 1
4976 20:15:09.674840 LP45_APHY_COMB_EN = 1
4977 20:15:09.678123 TX_ODT_DIS = 1
4978 20:15:09.681314 NEW_8X_MODE = 1
4979 20:15:09.684652 ===================================
4980 20:15:09.688042 ===================================
4981 20:15:09.691222 data_rate = 1866
4982 20:15:09.691304 CKR = 1
4983 20:15:09.694316 DQ_P2S_RATIO = 8
4984 20:15:09.697640 ===================================
4985 20:15:09.701185 CA_P2S_RATIO = 8
4986 20:15:09.704384 DQ_CA_OPEN = 0
4987 20:15:09.707563 DQ_SEMI_OPEN = 0
4988 20:15:09.710858 CA_SEMI_OPEN = 0
4989 20:15:09.710939 CA_FULL_RATE = 0
4990 20:15:09.714229 DQ_CKDIV4_EN = 1
4991 20:15:09.717563 CA_CKDIV4_EN = 1
4992 20:15:09.720968 CA_PREDIV_EN = 0
4993 20:15:09.724471 PH8_DLY = 0
4994 20:15:09.727428 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4995 20:15:09.727509 DQ_AAMCK_DIV = 4
4996 20:15:09.730880 CA_AAMCK_DIV = 4
4997 20:15:09.734184 CA_ADMCK_DIV = 4
4998 20:15:09.737366 DQ_TRACK_CA_EN = 0
4999 20:15:09.740621 CA_PICK = 933
5000 20:15:09.743927 CA_MCKIO = 933
5001 20:15:09.747232 MCKIO_SEMI = 0
5002 20:15:09.747313 PLL_FREQ = 3732
5003 20:15:09.750705 DQ_UI_PI_RATIO = 32
5004 20:15:09.753804 CA_UI_PI_RATIO = 0
5005 20:15:09.757117 ===================================
5006 20:15:09.760378 ===================================
5007 20:15:09.763629 memory_type:LPDDR4
5008 20:15:09.767043 GP_NUM : 10
5009 20:15:09.767125 SRAM_EN : 1
5010 20:15:09.770171 MD32_EN : 0
5011 20:15:09.773659 ===================================
5012 20:15:09.773741 [ANA_INIT] >>>>>>>>>>>>>>
5013 20:15:09.776770 <<<<<< [CONFIGURE PHASE]: ANA_TX
5014 20:15:09.780218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5015 20:15:09.783572 ===================================
5016 20:15:09.786820 data_rate = 1866,PCW = 0X8f00
5017 20:15:09.789950 ===================================
5018 20:15:09.793352 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5019 20:15:09.799856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5020 20:15:09.806818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5021 20:15:09.810080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5022 20:15:09.813114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5023 20:15:09.816444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5024 20:15:09.819746 [ANA_INIT] flow start
5025 20:15:09.819828 [ANA_INIT] PLL >>>>>>>>
5026 20:15:09.823284 [ANA_INIT] PLL <<<<<<<<
5027 20:15:09.826470 [ANA_INIT] MIDPI >>>>>>>>
5028 20:15:09.826552 [ANA_INIT] MIDPI <<<<<<<<
5029 20:15:09.829872 [ANA_INIT] DLL >>>>>>>>
5030 20:15:09.833146 [ANA_INIT] flow end
5031 20:15:09.836511 ============ LP4 DIFF to SE enter ============
5032 20:15:09.839789 ============ LP4 DIFF to SE exit ============
5033 20:15:09.843206 [ANA_INIT] <<<<<<<<<<<<<
5034 20:15:09.846399 [Flow] Enable top DCM control >>>>>
5035 20:15:09.849643 [Flow] Enable top DCM control <<<<<
5036 20:15:09.852997 Enable DLL master slave shuffle
5037 20:15:09.856365 ==============================================================
5038 20:15:09.859603 Gating Mode config
5039 20:15:09.865982 ==============================================================
5040 20:15:09.866066 Config description:
5041 20:15:09.876097 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5042 20:15:09.882685 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5043 20:15:09.889168 SELPH_MODE 0: By rank 1: By Phase
5044 20:15:09.892318 ==============================================================
5045 20:15:09.895972 GAT_TRACK_EN = 1
5046 20:15:09.898868 RX_GATING_MODE = 2
5047 20:15:09.902496 RX_GATING_TRACK_MODE = 2
5048 20:15:09.905592 SELPH_MODE = 1
5049 20:15:09.909081 PICG_EARLY_EN = 1
5050 20:15:09.912440 VALID_LAT_VALUE = 1
5051 20:15:09.918820 ==============================================================
5052 20:15:09.922039 Enter into Gating configuration >>>>
5053 20:15:09.925526 Exit from Gating configuration <<<<
5054 20:15:09.925637 Enter into DVFS_PRE_config >>>>>
5055 20:15:09.938551 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5056 20:15:09.942082 Exit from DVFS_PRE_config <<<<<
5057 20:15:09.945214 Enter into PICG configuration >>>>
5058 20:15:09.948863 Exit from PICG configuration <<<<
5059 20:15:09.948946 [RX_INPUT] configuration >>>>>
5060 20:15:09.952111 [RX_INPUT] configuration <<<<<
5061 20:15:09.958350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5062 20:15:09.965017 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5063 20:15:09.968380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5064 20:15:09.975147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5065 20:15:09.981443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5066 20:15:09.988344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5067 20:15:09.991368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5068 20:15:09.994846 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5069 20:15:10.001499 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5070 20:15:10.004654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5071 20:15:10.008181 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5072 20:15:10.014888 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5073 20:15:10.017890 ===================================
5074 20:15:10.017974 LPDDR4 DRAM CONFIGURATION
5075 20:15:10.021416 ===================================
5076 20:15:10.024714 EX_ROW_EN[0] = 0x0
5077 20:15:10.024797 EX_ROW_EN[1] = 0x0
5078 20:15:10.028152 LP4Y_EN = 0x0
5079 20:15:10.028235 WORK_FSP = 0x0
5080 20:15:10.031362 WL = 0x3
5081 20:15:10.034501 RL = 0x3
5082 20:15:10.034585 BL = 0x2
5083 20:15:10.038011 RPST = 0x0
5084 20:15:10.038095 RD_PRE = 0x0
5085 20:15:10.041451 WR_PRE = 0x1
5086 20:15:10.041567 WR_PST = 0x0
5087 20:15:10.044500 DBI_WR = 0x0
5088 20:15:10.044583 DBI_RD = 0x0
5089 20:15:10.048059 OTF = 0x1
5090 20:15:10.051107 ===================================
5091 20:15:10.054579 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5092 20:15:10.057858 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5093 20:15:10.061158 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5094 20:15:10.064644 ===================================
5095 20:15:10.067923 LPDDR4 DRAM CONFIGURATION
5096 20:15:10.071129 ===================================
5097 20:15:10.074519 EX_ROW_EN[0] = 0x10
5098 20:15:10.074657 EX_ROW_EN[1] = 0x0
5099 20:15:10.077757 LP4Y_EN = 0x0
5100 20:15:10.077912 WORK_FSP = 0x0
5101 20:15:10.081302 WL = 0x3
5102 20:15:10.081492 RL = 0x3
5103 20:15:10.084287 BL = 0x2
5104 20:15:10.087748 RPST = 0x0
5105 20:15:10.087954 RD_PRE = 0x0
5106 20:15:10.091235 WR_PRE = 0x1
5107 20:15:10.091481 WR_PST = 0x0
5108 20:15:10.094312 DBI_WR = 0x0
5109 20:15:10.094565 DBI_RD = 0x0
5110 20:15:10.097797 OTF = 0x1
5111 20:15:10.101106 ===================================
5112 20:15:10.107535 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5113 20:15:10.111244 nWR fixed to 30
5114 20:15:10.111676 [ModeRegInit_LP4] CH0 RK0
5115 20:15:10.114159 [ModeRegInit_LP4] CH0 RK1
5116 20:15:10.117778 [ModeRegInit_LP4] CH1 RK0
5117 20:15:10.118200 [ModeRegInit_LP4] CH1 RK1
5118 20:15:10.120863 match AC timing 9
5119 20:15:10.124268 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5120 20:15:10.127309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5121 20:15:10.134199 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5122 20:15:10.137455 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5123 20:15:10.143863 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5124 20:15:10.144323 ==
5125 20:15:10.147177 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 20:15:10.150520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 20:15:10.150933 ==
5128 20:15:10.157159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 20:15:10.163730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5130 20:15:10.166856 [CA 0] Center 38 (8~69) winsize 62
5131 20:15:10.170092 [CA 1] Center 38 (7~69) winsize 63
5132 20:15:10.173571 [CA 2] Center 35 (5~66) winsize 62
5133 20:15:10.176855 [CA 3] Center 35 (5~66) winsize 62
5134 20:15:10.180198 [CA 4] Center 34 (4~64) winsize 61
5135 20:15:10.183575 [CA 5] Center 33 (3~64) winsize 62
5136 20:15:10.183990
5137 20:15:10.186745 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5138 20:15:10.187161
5139 20:15:10.189856 [CATrainingPosCal] consider 1 rank data
5140 20:15:10.193158 u2DelayCellTimex100 = 270/100 ps
5141 20:15:10.196718 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5142 20:15:10.199708 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5143 20:15:10.203218 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5144 20:15:10.206702 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5145 20:15:10.209695 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5146 20:15:10.213319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5147 20:15:10.216485
5148 20:15:10.219498 CA PerBit enable=1, Macro0, CA PI delay=33
5149 20:15:10.219961
5150 20:15:10.223000 [CBTSetCACLKResult] CA Dly = 33
5151 20:15:10.223557 CS Dly: 7 (0~38)
5152 20:15:10.223948 ==
5153 20:15:10.226197 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 20:15:10.229573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 20:15:10.230239 ==
5156 20:15:10.236033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5157 20:15:10.242900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5158 20:15:10.246113 [CA 0] Center 38 (8~69) winsize 62
5159 20:15:10.249269 [CA 1] Center 38 (8~69) winsize 62
5160 20:15:10.252182 [CA 2] Center 35 (5~66) winsize 62
5161 20:15:10.255496 [CA 3] Center 35 (4~66) winsize 63
5162 20:15:10.258846 [CA 4] Center 34 (4~65) winsize 62
5163 20:15:10.262235 [CA 5] Center 33 (3~64) winsize 62
5164 20:15:10.262318
5165 20:15:10.265511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5166 20:15:10.265594
5167 20:15:10.268886 [CATrainingPosCal] consider 2 rank data
5168 20:15:10.271988 u2DelayCellTimex100 = 270/100 ps
5169 20:15:10.275332 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5170 20:15:10.278675 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5171 20:15:10.282128 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5172 20:15:10.288802 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5173 20:15:10.291816 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5174 20:15:10.295365 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5175 20:15:10.295446
5176 20:15:10.298382 CA PerBit enable=1, Macro0, CA PI delay=33
5177 20:15:10.298463
5178 20:15:10.301603 [CBTSetCACLKResult] CA Dly = 33
5179 20:15:10.301684 CS Dly: 7 (0~39)
5180 20:15:10.301749
5181 20:15:10.304954 ----->DramcWriteLeveling(PI) begin...
5182 20:15:10.308501 ==
5183 20:15:10.311593 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 20:15:10.315117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 20:15:10.315199 ==
5186 20:15:10.318237 Write leveling (Byte 0): 31 => 31
5187 20:15:10.321467 Write leveling (Byte 1): 29 => 29
5188 20:15:10.324941 DramcWriteLeveling(PI) end<-----
5189 20:15:10.325034
5190 20:15:10.325113 ==
5191 20:15:10.328332 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 20:15:10.331337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 20:15:10.331448 ==
5194 20:15:10.334734 [Gating] SW mode calibration
5195 20:15:10.341161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5196 20:15:10.348092 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5197 20:15:10.351443 0 14 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5198 20:15:10.354521 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5199 20:15:10.361432 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 20:15:10.364557 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 20:15:10.367883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 20:15:10.374617 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 20:15:10.378034 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 20:15:10.381278 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5205 20:15:10.387888 0 15 0 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (1 1)
5206 20:15:10.391256 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5207 20:15:10.394334 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 20:15:10.401263 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 20:15:10.404306 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 20:15:10.407746 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 20:15:10.414066 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 20:15:10.417448 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5213 20:15:10.420630 1 0 0 | B1->B0 | 2d2d 3d3d | 0 0 | (1 1) (0 0)
5214 20:15:10.427300 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5215 20:15:10.430355 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 20:15:10.433769 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 20:15:10.440446 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 20:15:10.443754 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 20:15:10.446845 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 20:15:10.453430 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 20:15:10.456835 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5222 20:15:10.460142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 20:15:10.466759 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 20:15:10.470089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 20:15:10.473451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 20:15:10.476663 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 20:15:10.483425 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 20:15:10.486494 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 20:15:10.493370 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 20:15:10.496550 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 20:15:10.499782 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 20:15:10.506277 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 20:15:10.509780 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 20:15:10.513161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 20:15:10.516538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 20:15:10.523138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 20:15:10.526174 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5238 20:15:10.529623 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5239 20:15:10.532706 Total UI for P1: 0, mck2ui 16
5240 20:15:10.536437 best dqsien dly found for B0: ( 1, 3, 0)
5241 20:15:10.542887 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 20:15:10.546405 Total UI for P1: 0, mck2ui 16
5243 20:15:10.549535 best dqsien dly found for B1: ( 1, 3, 4)
5244 20:15:10.553048 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5245 20:15:10.556210 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5246 20:15:10.556686
5247 20:15:10.559776 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5248 20:15:10.562588 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5249 20:15:10.565990 [Gating] SW calibration Done
5250 20:15:10.566486 ==
5251 20:15:10.569364 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 20:15:10.572999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 20:15:10.573677 ==
5254 20:15:10.575806 RX Vref Scan: 0
5255 20:15:10.576324
5256 20:15:10.579161 RX Vref 0 -> 0, step: 1
5257 20:15:10.579666
5258 20:15:10.580096 RX Delay -80 -> 252, step: 8
5259 20:15:10.585704 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5260 20:15:10.588947 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5261 20:15:10.592205 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5262 20:15:10.595496 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5263 20:15:10.598770 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5264 20:15:10.602193 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5265 20:15:10.608626 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5266 20:15:10.612250 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5267 20:15:10.615294 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5268 20:15:10.618867 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5269 20:15:10.622127 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5270 20:15:10.628980 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5271 20:15:10.632115 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5272 20:15:10.635673 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5273 20:15:10.638682 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5274 20:15:10.642018 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5275 20:15:10.645423 ==
5276 20:15:10.645948 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 20:15:10.652006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 20:15:10.652389 ==
5279 20:15:10.652716 DQS Delay:
5280 20:15:10.654996 DQS0 = 0, DQS1 = 0
5281 20:15:10.655357 DQM Delay:
5282 20:15:10.658525 DQM0 = 95, DQM1 = 83
5283 20:15:10.658902 DQ Delay:
5284 20:15:10.661865 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5285 20:15:10.665342 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5286 20:15:10.668301 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5287 20:15:10.671832 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5288 20:15:10.672265
5289 20:15:10.672612
5290 20:15:10.672933 ==
5291 20:15:10.674881 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 20:15:10.678256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 20:15:10.678697 ==
5294 20:15:10.679047
5295 20:15:10.679351
5296 20:15:10.681742 TX Vref Scan disable
5297 20:15:10.685049 == TX Byte 0 ==
5298 20:15:10.688426 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5299 20:15:10.691576 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5300 20:15:10.694766 == TX Byte 1 ==
5301 20:15:10.698385 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5302 20:15:10.701775 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5303 20:15:10.702236 ==
5304 20:15:10.704766 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 20:15:10.711416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 20:15:10.711849 ==
5307 20:15:10.712346
5308 20:15:10.712696
5309 20:15:10.713013 TX Vref Scan disable
5310 20:15:10.715263 == TX Byte 0 ==
5311 20:15:10.718727 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5312 20:15:10.725371 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5313 20:15:10.725893 == TX Byte 1 ==
5314 20:15:10.728764 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5315 20:15:10.732097 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5316 20:15:10.735445
5317 20:15:10.735871 [DATLAT]
5318 20:15:10.736210 Freq=933, CH0 RK0
5319 20:15:10.736531
5320 20:15:10.738693 DATLAT Default: 0xd
5321 20:15:10.739114 0, 0xFFFF, sum = 0
5322 20:15:10.742147 1, 0xFFFF, sum = 0
5323 20:15:10.742587 2, 0xFFFF, sum = 0
5324 20:15:10.745428 3, 0xFFFF, sum = 0
5325 20:15:10.748562 4, 0xFFFF, sum = 0
5326 20:15:10.749015 5, 0xFFFF, sum = 0
5327 20:15:10.751863 6, 0xFFFF, sum = 0
5328 20:15:10.752305 7, 0xFFFF, sum = 0
5329 20:15:10.755197 8, 0xFFFF, sum = 0
5330 20:15:10.755643 9, 0xFFFF, sum = 0
5331 20:15:10.758467 10, 0x0, sum = 1
5332 20:15:10.758908 11, 0x0, sum = 2
5333 20:15:10.761983 12, 0x0, sum = 3
5334 20:15:10.762427 13, 0x0, sum = 4
5335 20:15:10.762783 best_step = 11
5336 20:15:10.763094
5337 20:15:10.765145 ==
5338 20:15:10.768626 Dram Type= 6, Freq= 0, CH_0, rank 0
5339 20:15:10.771913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 20:15:10.772353 ==
5341 20:15:10.772700 RX Vref Scan: 1
5342 20:15:10.773013
5343 20:15:10.775164 RX Vref 0 -> 0, step: 1
5344 20:15:10.775598
5345 20:15:10.778674 RX Delay -69 -> 252, step: 4
5346 20:15:10.779126
5347 20:15:10.781688 Set Vref, RX VrefLevel [Byte0]: 61
5348 20:15:10.785174 [Byte1]: 45
5349 20:15:10.785655
5350 20:15:10.788424 Final RX Vref Byte 0 = 61 to rank0
5351 20:15:10.791770 Final RX Vref Byte 1 = 45 to rank0
5352 20:15:10.795073 Final RX Vref Byte 0 = 61 to rank1
5353 20:15:10.798358 Final RX Vref Byte 1 = 45 to rank1==
5354 20:15:10.801587 Dram Type= 6, Freq= 0, CH_0, rank 0
5355 20:15:10.804744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 20:15:10.808062 ==
5357 20:15:10.808500 DQS Delay:
5358 20:15:10.808847 DQS0 = 0, DQS1 = 0
5359 20:15:10.811482 DQM Delay:
5360 20:15:10.811918 DQM0 = 95, DQM1 = 82
5361 20:15:10.814754 DQ Delay:
5362 20:15:10.815256 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5363 20:15:10.818134 DQ4 =96, DQ5 =86, DQ6 =102, DQ7 =106
5364 20:15:10.821223 DQ8 =72, DQ9 =68, DQ10 =82, DQ11 =76
5365 20:15:10.827825 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5366 20:15:10.828245
5367 20:15:10.828612
5368 20:15:10.834565 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5369 20:15:10.838217 CH0 RK0: MR19=505, MR18=1616
5370 20:15:10.844466 CH0_RK0: MR19=0x505, MR18=0x1616, DQSOSC=414, MR23=63, INC=63, DEC=42
5371 20:15:10.845004
5372 20:15:10.847820 ----->DramcWriteLeveling(PI) begin...
5373 20:15:10.848120 ==
5374 20:15:10.851281 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 20:15:10.854409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 20:15:10.854761 ==
5377 20:15:10.857696 Write leveling (Byte 0): 32 => 32
5378 20:15:10.861124 Write leveling (Byte 1): 31 => 31
5379 20:15:10.864368 DramcWriteLeveling(PI) end<-----
5380 20:15:10.864692
5381 20:15:10.864988 ==
5382 20:15:10.867796 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 20:15:10.870875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 20:15:10.871306 ==
5385 20:15:10.875704 [Gating] SW mode calibration
5386 20:15:10.880841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5387 20:15:10.887658 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5388 20:15:10.890774 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5389 20:15:10.897779 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5390 20:15:10.900776 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 20:15:10.904233 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 20:15:10.910701 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 20:15:10.913961 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 20:15:10.917259 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5395 20:15:10.924025 0 14 28 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (0 0)
5396 20:15:10.927379 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (0 1) (0 0)
5397 20:15:10.930756 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 20:15:10.933821 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 20:15:10.940464 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 20:15:10.943900 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 20:15:10.947521 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 20:15:10.954009 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 20:15:10.957313 0 15 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
5404 20:15:10.960908 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5405 20:15:10.967287 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 20:15:10.970368 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 20:15:10.973638 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 20:15:10.980320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 20:15:10.983780 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 20:15:10.986986 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 20:15:10.993429 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5412 20:15:10.996957 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5413 20:15:11.000026 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 20:15:11.006730 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 20:15:11.010226 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 20:15:11.013341 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 20:15:11.019951 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 20:15:11.023184 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 20:15:11.026724 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 20:15:11.032862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 20:15:11.036296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 20:15:11.039757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 20:15:11.046651 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 20:15:11.049950 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 20:15:11.053187 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 20:15:11.059592 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 20:15:11.063132 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5428 20:15:11.066076 Total UI for P1: 0, mck2ui 16
5429 20:15:11.069547 best dqsien dly found for B0: ( 1, 2, 26)
5430 20:15:11.073013 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 20:15:11.076315 Total UI for P1: 0, mck2ui 16
5432 20:15:11.079690 best dqsien dly found for B1: ( 1, 2, 28)
5433 20:15:11.082819 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5434 20:15:11.086101 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5435 20:15:11.086639
5436 20:15:11.092876 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5437 20:15:11.096214 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5438 20:15:11.096779 [Gating] SW calibration Done
5439 20:15:11.099541 ==
5440 20:15:11.102564 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 20:15:11.105944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 20:15:11.106443 ==
5443 20:15:11.106829 RX Vref Scan: 0
5444 20:15:11.107172
5445 20:15:11.109287 RX Vref 0 -> 0, step: 1
5446 20:15:11.109873
5447 20:15:11.112841 RX Delay -80 -> 252, step: 8
5448 20:15:11.115768 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5449 20:15:11.119226 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5450 20:15:11.122351 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5451 20:15:11.129160 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5452 20:15:11.132282 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5453 20:15:11.135709 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5454 20:15:11.139077 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5455 20:15:11.142156 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5456 20:15:11.148798 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5457 20:15:11.152127 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5458 20:15:11.155464 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5459 20:15:11.159025 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5460 20:15:11.162162 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5461 20:15:11.168635 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5462 20:15:11.172107 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5463 20:15:11.175239 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5464 20:15:11.175796 ==
5465 20:15:11.178892 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 20:15:11.182028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 20:15:11.182468 ==
5468 20:15:11.185242 DQS Delay:
5469 20:15:11.185811 DQS0 = 0, DQS1 = 0
5470 20:15:11.188787 DQM Delay:
5471 20:15:11.189207 DQM0 = 91, DQM1 = 81
5472 20:15:11.189577 DQ Delay:
5473 20:15:11.191923 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5474 20:15:11.195375 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5475 20:15:11.198610 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5476 20:15:11.201755 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =87
5477 20:15:11.202183
5478 20:15:11.202514
5479 20:15:11.205063 ==
5480 20:15:11.209021 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 20:15:11.211831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 20:15:11.212270 ==
5483 20:15:11.212607
5484 20:15:11.212917
5485 20:15:11.214995 TX Vref Scan disable
5486 20:15:11.215579 == TX Byte 0 ==
5487 20:15:11.218384 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5488 20:15:11.224893 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5489 20:15:11.225412 == TX Byte 1 ==
5490 20:15:11.231806 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5491 20:15:11.234949 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5492 20:15:11.235374 ==
5493 20:15:11.238431 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 20:15:11.241720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 20:15:11.242248 ==
5496 20:15:11.242593
5497 20:15:11.242908
5498 20:15:11.244752 TX Vref Scan disable
5499 20:15:11.248090 == TX Byte 0 ==
5500 20:15:11.251220 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5501 20:15:11.254799 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5502 20:15:11.258147 == TX Byte 1 ==
5503 20:15:11.261575 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5504 20:15:11.265108 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5505 20:15:11.265739
5506 20:15:11.268458 [DATLAT]
5507 20:15:11.268928 Freq=933, CH0 RK1
5508 20:15:11.269528
5509 20:15:11.271279 DATLAT Default: 0xb
5510 20:15:11.271901 0, 0xFFFF, sum = 0
5511 20:15:11.274746 1, 0xFFFF, sum = 0
5512 20:15:11.275314 2, 0xFFFF, sum = 0
5513 20:15:11.278163 3, 0xFFFF, sum = 0
5514 20:15:11.278588 4, 0xFFFF, sum = 0
5515 20:15:11.281546 5, 0xFFFF, sum = 0
5516 20:15:11.281848 6, 0xFFFF, sum = 0
5517 20:15:11.284687 7, 0xFFFF, sum = 0
5518 20:15:11.285015 8, 0xFFFF, sum = 0
5519 20:15:11.288178 9, 0xFFFF, sum = 0
5520 20:15:11.288478 10, 0x0, sum = 1
5521 20:15:11.291231 11, 0x0, sum = 2
5522 20:15:11.291531 12, 0x0, sum = 3
5523 20:15:11.294884 13, 0x0, sum = 4
5524 20:15:11.295248 best_step = 11
5525 20:15:11.295525
5526 20:15:11.295782 ==
5527 20:15:11.297895 Dram Type= 6, Freq= 0, CH_0, rank 1
5528 20:15:11.301267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 20:15:11.304645 ==
5530 20:15:11.304950 RX Vref Scan: 0
5531 20:15:11.305249
5532 20:15:11.307933 RX Vref 0 -> 0, step: 1
5533 20:15:11.308233
5534 20:15:11.311001 RX Delay -77 -> 252, step: 4
5535 20:15:11.314332 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5536 20:15:11.317599 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5537 20:15:11.324054 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5538 20:15:11.327339 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5539 20:15:11.331039 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5540 20:15:11.334175 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5541 20:15:11.337327 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5542 20:15:11.340966 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5543 20:15:11.347264 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5544 20:15:11.350521 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5545 20:15:11.353939 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5546 20:15:11.357124 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5547 20:15:11.363604 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5548 20:15:11.367065 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5549 20:15:11.370524 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5550 20:15:11.373761 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5551 20:15:11.373872 ==
5552 20:15:11.376934 Dram Type= 6, Freq= 0, CH_0, rank 1
5553 20:15:11.380214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 20:15:11.383486 ==
5555 20:15:11.383589 DQS Delay:
5556 20:15:11.383695 DQS0 = 0, DQS1 = 0
5557 20:15:11.386660 DQM Delay:
5558 20:15:11.386739 DQM0 = 92, DQM1 = 84
5559 20:15:11.390136 DQ Delay:
5560 20:15:11.390207 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =86
5561 20:15:11.393611 DQ4 =92, DQ5 =82, DQ6 =106, DQ7 =104
5562 20:15:11.396843 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5563 20:15:11.400186 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5564 20:15:11.403229
5565 20:15:11.403357
5566 20:15:11.410257 [DQSOSCAuto] RK1, (LSB)MR18= 0x3111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5567 20:15:11.413591 CH0 RK1: MR19=505, MR18=3111
5568 20:15:11.419771 CH0_RK1: MR19=0x505, MR18=0x3111, DQSOSC=406, MR23=63, INC=65, DEC=43
5569 20:15:11.423273 [RxdqsGatingPostProcess] freq 933
5570 20:15:11.426569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5571 20:15:11.429876 best DQS0 dly(2T, 0.5T) = (0, 11)
5572 20:15:11.433250 best DQS1 dly(2T, 0.5T) = (0, 11)
5573 20:15:11.436448 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5574 20:15:11.439743 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5575 20:15:11.442762 best DQS0 dly(2T, 0.5T) = (0, 10)
5576 20:15:11.446492 best DQS1 dly(2T, 0.5T) = (0, 10)
5577 20:15:11.449709 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5578 20:15:11.453521 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5579 20:15:11.456055 Pre-setting of DQS Precalculation
5580 20:15:11.459663 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5581 20:15:11.459745 ==
5582 20:15:11.462816 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 20:15:11.469351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 20:15:11.469482 ==
5585 20:15:11.472711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 20:15:11.478972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5587 20:15:11.482713 [CA 0] Center 37 (7~67) winsize 61
5588 20:15:11.485897 [CA 1] Center 37 (7~68) winsize 62
5589 20:15:11.489040 [CA 2] Center 34 (5~64) winsize 60
5590 20:15:11.492694 [CA 3] Center 34 (5~64) winsize 60
5591 20:15:11.495863 [CA 4] Center 34 (5~64) winsize 60
5592 20:15:11.499029 [CA 5] Center 33 (4~63) winsize 60
5593 20:15:11.499111
5594 20:15:11.502512 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5595 20:15:11.502597
5596 20:15:11.505769 [CATrainingPosCal] consider 1 rank data
5597 20:15:11.509164 u2DelayCellTimex100 = 270/100 ps
5598 20:15:11.512355 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5599 20:15:11.518695 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5600 20:15:11.522309 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5601 20:15:11.525746 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5602 20:15:11.528781 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5603 20:15:11.532012 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5604 20:15:11.532124
5605 20:15:11.535454 CA PerBit enable=1, Macro0, CA PI delay=33
5606 20:15:11.535563
5607 20:15:11.538530 [CBTSetCACLKResult] CA Dly = 33
5608 20:15:11.541727 CS Dly: 5 (0~36)
5609 20:15:11.541835 ==
5610 20:15:11.545078 Dram Type= 6, Freq= 0, CH_1, rank 1
5611 20:15:11.548602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 20:15:11.548685 ==
5613 20:15:11.555326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5614 20:15:11.558312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5615 20:15:11.562492 [CA 0] Center 37 (7~68) winsize 62
5616 20:15:11.565670 [CA 1] Center 37 (7~68) winsize 62
5617 20:15:11.569222 [CA 2] Center 35 (5~65) winsize 61
5618 20:15:11.572668 [CA 3] Center 34 (4~64) winsize 61
5619 20:15:11.575693 [CA 4] Center 34 (4~65) winsize 62
5620 20:15:11.579111 [CA 5] Center 33 (3~64) winsize 62
5621 20:15:11.579219
5622 20:15:11.582083 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5623 20:15:11.582185
5624 20:15:11.585450 [CATrainingPosCal] consider 2 rank data
5625 20:15:11.588756 u2DelayCellTimex100 = 270/100 ps
5626 20:15:11.592287 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5627 20:15:11.598771 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5628 20:15:11.602165 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5629 20:15:11.605444 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5630 20:15:11.608700 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5631 20:15:11.612280 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5632 20:15:11.612362
5633 20:15:11.615300 CA PerBit enable=1, Macro0, CA PI delay=33
5634 20:15:11.615382
5635 20:15:11.618752 [CBTSetCACLKResult] CA Dly = 33
5636 20:15:11.622164 CS Dly: 6 (0~38)
5637 20:15:11.622273
5638 20:15:11.625391 ----->DramcWriteLeveling(PI) begin...
5639 20:15:11.625541 ==
5640 20:15:11.628877 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 20:15:11.631907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 20:15:11.632021 ==
5643 20:15:11.635299 Write leveling (Byte 0): 24 => 24
5644 20:15:11.638851 Write leveling (Byte 1): 25 => 25
5645 20:15:11.641917 DramcWriteLeveling(PI) end<-----
5646 20:15:11.642002
5647 20:15:11.642065 ==
5648 20:15:11.645120 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 20:15:11.648486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 20:15:11.648568 ==
5651 20:15:11.651732 [Gating] SW mode calibration
5652 20:15:11.658536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5653 20:15:11.665238 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5654 20:15:11.668253 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 1)
5655 20:15:11.671706 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 20:15:11.678465 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 20:15:11.681622 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 20:15:11.685092 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 20:15:11.691615 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 20:15:11.695487 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 20:15:11.698456 0 14 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5662 20:15:11.704957 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5663 20:15:11.708351 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 20:15:11.711511 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 20:15:11.718194 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 20:15:11.721708 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 20:15:11.724966 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 20:15:11.731790 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 20:15:11.734765 0 15 28 | B1->B0 | 3636 3838 | 0 0 | (0 0) (0 0)
5670 20:15:11.738082 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5671 20:15:11.744758 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 20:15:11.747893 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 20:15:11.751489 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 20:15:11.757945 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 20:15:11.761158 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 20:15:11.764526 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 20:15:11.771141 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5678 20:15:11.774620 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5679 20:15:11.777787 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 20:15:11.781333 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 20:15:11.787542 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 20:15:11.790871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 20:15:11.794359 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 20:15:11.800949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 20:15:11.804338 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 20:15:11.807518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 20:15:11.814320 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 20:15:11.817451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 20:15:11.820819 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 20:15:11.827329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 20:15:11.830504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 20:15:11.833918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5693 20:15:11.840650 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5694 20:15:11.844024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5695 20:15:11.847530 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 20:15:11.850600 Total UI for P1: 0, mck2ui 16
5697 20:15:11.854048 best dqsien dly found for B0: ( 1, 2, 28)
5698 20:15:11.857035 Total UI for P1: 0, mck2ui 16
5699 20:15:11.860615 best dqsien dly found for B1: ( 1, 2, 28)
5700 20:15:11.863976 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5701 20:15:11.867457 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5702 20:15:11.867535
5703 20:15:11.873800 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5704 20:15:11.876994 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5705 20:15:11.880508 [Gating] SW calibration Done
5706 20:15:11.880580 ==
5707 20:15:11.884168 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 20:15:11.887026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 20:15:11.887097 ==
5710 20:15:11.887160 RX Vref Scan: 0
5711 20:15:11.887218
5712 20:15:11.890432 RX Vref 0 -> 0, step: 1
5713 20:15:11.890499
5714 20:15:11.893728 RX Delay -80 -> 252, step: 8
5715 20:15:11.897428 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5716 20:15:11.900496 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5717 20:15:11.903756 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5718 20:15:11.910262 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5719 20:15:11.913727 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5720 20:15:11.917180 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5721 20:15:11.920290 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5722 20:15:11.923513 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5723 20:15:11.930445 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5724 20:15:11.933434 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5725 20:15:11.936850 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5726 20:15:11.940703 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5727 20:15:11.943385 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5728 20:15:11.946949 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5729 20:15:11.953348 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5730 20:15:11.956883 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5731 20:15:11.956965 ==
5732 20:15:11.959986 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 20:15:11.963510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 20:15:11.963593 ==
5735 20:15:11.966655 DQS Delay:
5736 20:15:11.966739 DQS0 = 0, DQS1 = 0
5737 20:15:11.966806 DQM Delay:
5738 20:15:11.970341 DQM0 = 94, DQM1 = 87
5739 20:15:11.970429 DQ Delay:
5740 20:15:11.973659 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5741 20:15:11.976941 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5742 20:15:11.980330 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5743 20:15:11.983613 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5744 20:15:11.983695
5745 20:15:11.983760
5746 20:15:11.983819 ==
5747 20:15:11.986655 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 20:15:11.993426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 20:15:11.993547 ==
5750 20:15:11.993612
5751 20:15:11.993672
5752 20:15:11.993729 TX Vref Scan disable
5753 20:15:11.997020 == TX Byte 0 ==
5754 20:15:12.000176 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5755 20:15:12.006618 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5756 20:15:12.006728 == TX Byte 1 ==
5757 20:15:12.010371 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5758 20:15:12.016927 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5759 20:15:12.017010 ==
5760 20:15:12.019938 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 20:15:12.023385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 20:15:12.023502 ==
5763 20:15:12.023604
5764 20:15:12.023692
5765 20:15:12.026918 TX Vref Scan disable
5766 20:15:12.027032 == TX Byte 0 ==
5767 20:15:12.033269 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5768 20:15:12.036413 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5769 20:15:12.039888 == TX Byte 1 ==
5770 20:15:12.043017 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5771 20:15:12.046673 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5772 20:15:12.046755
5773 20:15:12.046819 [DATLAT]
5774 20:15:12.049635 Freq=933, CH1 RK0
5775 20:15:12.049745
5776 20:15:12.049866 DATLAT Default: 0xd
5777 20:15:12.053154 0, 0xFFFF, sum = 0
5778 20:15:12.056340 1, 0xFFFF, sum = 0
5779 20:15:12.056468 2, 0xFFFF, sum = 0
5780 20:15:12.059848 3, 0xFFFF, sum = 0
5781 20:15:12.059931 4, 0xFFFF, sum = 0
5782 20:15:12.063139 5, 0xFFFF, sum = 0
5783 20:15:12.063223 6, 0xFFFF, sum = 0
5784 20:15:12.066495 7, 0xFFFF, sum = 0
5785 20:15:12.066581 8, 0xFFFF, sum = 0
5786 20:15:12.069706 9, 0xFFFF, sum = 0
5787 20:15:12.069789 10, 0x0, sum = 1
5788 20:15:12.073127 11, 0x0, sum = 2
5789 20:15:12.073225 12, 0x0, sum = 3
5790 20:15:12.076256 13, 0x0, sum = 4
5791 20:15:12.076379 best_step = 11
5792 20:15:12.076503
5793 20:15:12.076624 ==
5794 20:15:12.079613 Dram Type= 6, Freq= 0, CH_1, rank 0
5795 20:15:12.082939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 20:15:12.083022 ==
5797 20:15:12.086413 RX Vref Scan: 1
5798 20:15:12.086548
5799 20:15:12.089486 RX Vref 0 -> 0, step: 1
5800 20:15:12.089582
5801 20:15:12.089647 RX Delay -61 -> 252, step: 4
5802 20:15:12.089707
5803 20:15:12.092824 Set Vref, RX VrefLevel [Byte0]: 55
5804 20:15:12.096340 [Byte1]: 48
5805 20:15:12.100886
5806 20:15:12.100957 Final RX Vref Byte 0 = 55 to rank0
5807 20:15:12.104072 Final RX Vref Byte 1 = 48 to rank0
5808 20:15:12.107494 Final RX Vref Byte 0 = 55 to rank1
5809 20:15:12.111039 Final RX Vref Byte 1 = 48 to rank1==
5810 20:15:12.113989 Dram Type= 6, Freq= 0, CH_1, rank 0
5811 20:15:12.120567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 20:15:12.120655 ==
5813 20:15:12.120722 DQS Delay:
5814 20:15:12.123927 DQS0 = 0, DQS1 = 0
5815 20:15:12.124009 DQM Delay:
5816 20:15:12.124114 DQM0 = 96, DQM1 = 87
5817 20:15:12.127362 DQ Delay:
5818 20:15:12.130417 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =94
5819 20:15:12.133906 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5820 20:15:12.137349 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =80
5821 20:15:12.140466 DQ12 =94, DQ13 =92, DQ14 =94, DQ15 =96
5822 20:15:12.140565
5823 20:15:12.140654
5824 20:15:12.147246 [DQSOSCAuto] RK0, (LSB)MR18= 0x30c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5825 20:15:12.150815 CH1 RK0: MR19=505, MR18=30C
5826 20:15:12.156964 CH1_RK0: MR19=0x505, MR18=0x30C, DQSOSC=418, MR23=63, INC=62, DEC=41
5827 20:15:12.157042
5828 20:15:12.160497 ----->DramcWriteLeveling(PI) begin...
5829 20:15:12.160611 ==
5830 20:15:12.163713 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 20:15:12.167226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 20:15:12.167308 ==
5833 20:15:12.170503 Write leveling (Byte 0): 25 => 25
5834 20:15:12.173855 Write leveling (Byte 1): 27 => 27
5835 20:15:12.176973 DramcWriteLeveling(PI) end<-----
5836 20:15:12.177077
5837 20:15:12.177173 ==
5838 20:15:12.180251 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 20:15:12.183862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 20:15:12.183944 ==
5841 20:15:12.186800 [Gating] SW mode calibration
5842 20:15:12.193626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5843 20:15:12.200436 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5844 20:15:12.203691 0 14 0 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
5845 20:15:12.210098 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 20:15:12.213410 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 20:15:12.216652 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 20:15:12.223370 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 20:15:12.226872 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 20:15:12.230103 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5851 20:15:12.236796 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5852 20:15:12.240133 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 20:15:12.243355 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 20:15:12.249955 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 20:15:12.253171 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 20:15:12.256556 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 20:15:12.263257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 20:15:12.266304 0 15 24 | B1->B0 | 2727 3030 | 1 0 | (0 0) (0 0)
5859 20:15:12.269870 0 15 28 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5860 20:15:12.273057 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 20:15:12.279401 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 20:15:12.282757 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 20:15:12.286148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 20:15:12.292994 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 20:15:12.296048 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 20:15:12.299495 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5867 20:15:12.305996 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5868 20:15:12.309528 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 20:15:12.312786 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 20:15:12.319490 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 20:15:12.322440 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 20:15:12.325987 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 20:15:12.332525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 20:15:12.335734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 20:15:12.339070 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 20:15:12.345813 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 20:15:12.348875 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 20:15:12.352267 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 20:15:12.359245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 20:15:12.362248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 20:15:12.365680 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5882 20:15:12.372592 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5883 20:15:12.375498 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 20:15:12.379069 Total UI for P1: 0, mck2ui 16
5885 20:15:12.382369 best dqsien dly found for B0: ( 1, 2, 22)
5886 20:15:12.385696 Total UI for P1: 0, mck2ui 16
5887 20:15:12.388917 best dqsien dly found for B1: ( 1, 2, 24)
5888 20:15:12.392207 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5889 20:15:12.395565 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5890 20:15:12.395690
5891 20:15:12.398757 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5892 20:15:12.402361 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5893 20:15:12.405468 [Gating] SW calibration Done
5894 20:15:12.405576 ==
5895 20:15:12.408665 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 20:15:12.412017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 20:15:12.415523 ==
5898 20:15:12.415603 RX Vref Scan: 0
5899 20:15:12.415667
5900 20:15:12.418778 RX Vref 0 -> 0, step: 1
5901 20:15:12.418858
5902 20:15:12.422209 RX Delay -80 -> 252, step: 8
5903 20:15:12.425257 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5904 20:15:12.428680 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5905 20:15:12.431982 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5906 20:15:12.435235 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5907 20:15:12.441596 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5908 20:15:12.445282 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5909 20:15:12.448178 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5910 20:15:12.451659 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5911 20:15:12.454977 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5912 20:15:12.461321 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5913 20:15:12.464721 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5914 20:15:12.468291 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5915 20:15:12.471466 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5916 20:15:12.474862 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5917 20:15:12.478059 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5918 20:15:12.484536 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5919 20:15:12.484616 ==
5920 20:15:12.488047 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 20:15:12.491138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 20:15:12.491211 ==
5923 20:15:12.491272 DQS Delay:
5924 20:15:12.494785 DQS0 = 0, DQS1 = 0
5925 20:15:12.494856 DQM Delay:
5926 20:15:12.497942 DQM0 = 93, DQM1 = 88
5927 20:15:12.498007 DQ Delay:
5928 20:15:12.501092 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5929 20:15:12.504368 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5930 20:15:12.507898 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =87
5931 20:15:12.511272 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5932 20:15:12.511344
5933 20:15:12.511404
5934 20:15:12.511462 ==
5935 20:15:12.514400 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 20:15:12.517660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 20:15:12.520947 ==
5938 20:15:12.521014
5939 20:15:12.521071
5940 20:15:12.521127 TX Vref Scan disable
5941 20:15:12.524576 == TX Byte 0 ==
5942 20:15:12.527926 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5943 20:15:12.531158 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5944 20:15:12.534152 == TX Byte 1 ==
5945 20:15:12.537818 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5946 20:15:12.540960 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5947 20:15:12.544349 ==
5948 20:15:12.544457 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 20:15:12.550873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 20:15:12.550946 ==
5951 20:15:12.551011
5952 20:15:12.551071
5953 20:15:12.554007 TX Vref Scan disable
5954 20:15:12.554074 == TX Byte 0 ==
5955 20:15:12.560702 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5956 20:15:12.564298 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5957 20:15:12.564404 == TX Byte 1 ==
5958 20:15:12.570778 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5959 20:15:12.574040 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5960 20:15:12.574146
5961 20:15:12.574238 [DATLAT]
5962 20:15:12.577412 Freq=933, CH1 RK1
5963 20:15:12.577553
5964 20:15:12.577649 DATLAT Default: 0xb
5965 20:15:12.580782 0, 0xFFFF, sum = 0
5966 20:15:12.580864 1, 0xFFFF, sum = 0
5967 20:15:12.583942 2, 0xFFFF, sum = 0
5968 20:15:12.584015 3, 0xFFFF, sum = 0
5969 20:15:12.587560 4, 0xFFFF, sum = 0
5970 20:15:12.587632 5, 0xFFFF, sum = 0
5971 20:15:12.590618 6, 0xFFFF, sum = 0
5972 20:15:12.590716 7, 0xFFFF, sum = 0
5973 20:15:12.594183 8, 0xFFFF, sum = 0
5974 20:15:12.594256 9, 0xFFFF, sum = 0
5975 20:15:12.597361 10, 0x0, sum = 1
5976 20:15:12.597467 11, 0x0, sum = 2
5977 20:15:12.600694 12, 0x0, sum = 3
5978 20:15:12.600798 13, 0x0, sum = 4
5979 20:15:12.604048 best_step = 11
5980 20:15:12.604118
5981 20:15:12.604177 ==
5982 20:15:12.607169 Dram Type= 6, Freq= 0, CH_1, rank 1
5983 20:15:12.610937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5984 20:15:12.611036 ==
5985 20:15:12.614058 RX Vref Scan: 0
5986 20:15:12.614127
5987 20:15:12.614186 RX Vref 0 -> 0, step: 1
5988 20:15:12.614242
5989 20:15:12.617435 RX Delay -69 -> 252, step: 4
5990 20:15:12.624398 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5991 20:15:12.627929 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5992 20:15:12.631019 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5993 20:15:12.634518 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5994 20:15:12.637702 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5995 20:15:12.644513 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5996 20:15:12.647722 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5997 20:15:12.650808 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5998 20:15:12.654295 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5999 20:15:12.657793 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
6000 20:15:12.660816 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
6001 20:15:12.667595 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
6002 20:15:12.670749 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
6003 20:15:12.674129 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
6004 20:15:12.677413 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
6005 20:15:12.680669 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
6006 20:15:12.683918 ==
6007 20:15:12.687342 Dram Type= 6, Freq= 0, CH_1, rank 1
6008 20:15:12.690450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6009 20:15:12.690554 ==
6010 20:15:12.690647 DQS Delay:
6011 20:15:12.693814 DQS0 = 0, DQS1 = 0
6012 20:15:12.693910 DQM Delay:
6013 20:15:12.697300 DQM0 = 91, DQM1 = 91
6014 20:15:12.697392 DQ Delay:
6015 20:15:12.700375 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
6016 20:15:12.703817 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
6017 20:15:12.707119 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
6018 20:15:12.710459 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
6019 20:15:12.710526
6020 20:15:12.710587
6021 20:15:12.716931 [DQSOSCAuto] RK1, (LSB)MR18= 0xc21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
6022 20:15:12.720272 CH1 RK1: MR19=505, MR18=C21
6023 20:15:12.727079 CH1_RK1: MR19=0x505, MR18=0xC21, DQSOSC=411, MR23=63, INC=64, DEC=42
6024 20:15:12.730261 [RxdqsGatingPostProcess] freq 933
6025 20:15:12.736894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6026 20:15:12.740101 best DQS0 dly(2T, 0.5T) = (0, 10)
6027 20:15:12.740170 best DQS1 dly(2T, 0.5T) = (0, 10)
6028 20:15:12.743391 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6029 20:15:12.746754 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6030 20:15:12.750187 best DQS0 dly(2T, 0.5T) = (0, 10)
6031 20:15:12.753378 best DQS1 dly(2T, 0.5T) = (0, 10)
6032 20:15:12.756930 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6033 20:15:12.760063 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6034 20:15:12.763554 Pre-setting of DQS Precalculation
6035 20:15:12.770087 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6036 20:15:12.776509 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6037 20:15:12.783429 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6038 20:15:12.783512
6039 20:15:12.783577
6040 20:15:12.786600 [Calibration Summary] 1866 Mbps
6041 20:15:12.786716 CH 0, Rank 0
6042 20:15:12.789971 SW Impedance : PASS
6043 20:15:12.793300 DUTY Scan : NO K
6044 20:15:12.793432 ZQ Calibration : PASS
6045 20:15:12.796439 Jitter Meter : NO K
6046 20:15:12.799921 CBT Training : PASS
6047 20:15:12.800041 Write leveling : PASS
6048 20:15:12.803203 RX DQS gating : PASS
6049 20:15:12.806577 RX DQ/DQS(RDDQC) : PASS
6050 20:15:12.806717 TX DQ/DQS : PASS
6051 20:15:12.809492 RX DATLAT : PASS
6052 20:15:12.812935 RX DQ/DQS(Engine): PASS
6053 20:15:12.813015 TX OE : NO K
6054 20:15:12.813079 All Pass.
6055 20:15:12.816314
6056 20:15:12.816394 CH 0, Rank 1
6057 20:15:12.819746 SW Impedance : PASS
6058 20:15:12.819835 DUTY Scan : NO K
6059 20:15:12.822782 ZQ Calibration : PASS
6060 20:15:12.822861 Jitter Meter : NO K
6061 20:15:12.826337 CBT Training : PASS
6062 20:15:12.829317 Write leveling : PASS
6063 20:15:12.829387 RX DQS gating : PASS
6064 20:15:12.833048 RX DQ/DQS(RDDQC) : PASS
6065 20:15:12.836360 TX DQ/DQS : PASS
6066 20:15:12.836432 RX DATLAT : PASS
6067 20:15:12.839615 RX DQ/DQS(Engine): PASS
6068 20:15:12.842939 TX OE : NO K
6069 20:15:12.843054 All Pass.
6070 20:15:12.843186
6071 20:15:12.843248 CH 1, Rank 0
6072 20:15:12.846278 SW Impedance : PASS
6073 20:15:12.849287 DUTY Scan : NO K
6074 20:15:12.849392 ZQ Calibration : PASS
6075 20:15:12.852458 Jitter Meter : NO K
6076 20:15:12.855726 CBT Training : PASS
6077 20:15:12.855801 Write leveling : PASS
6078 20:15:12.859429 RX DQS gating : PASS
6079 20:15:12.862384 RX DQ/DQS(RDDQC) : PASS
6080 20:15:12.862455 TX DQ/DQS : PASS
6081 20:15:12.865877 RX DATLAT : PASS
6082 20:15:12.868995 RX DQ/DQS(Engine): PASS
6083 20:15:12.869075 TX OE : NO K
6084 20:15:12.872420 All Pass.
6085 20:15:12.872492
6086 20:15:12.872561 CH 1, Rank 1
6087 20:15:12.875900 SW Impedance : PASS
6088 20:15:12.875970 DUTY Scan : NO K
6089 20:15:12.879029 ZQ Calibration : PASS
6090 20:15:12.882331 Jitter Meter : NO K
6091 20:15:12.882403 CBT Training : PASS
6092 20:15:12.885793 Write leveling : PASS
6093 20:15:12.885896 RX DQS gating : PASS
6094 20:15:12.888789 RX DQ/DQS(RDDQC) : PASS
6095 20:15:12.892112 TX DQ/DQS : PASS
6096 20:15:12.892187 RX DATLAT : PASS
6097 20:15:12.895572 RX DQ/DQS(Engine): PASS
6098 20:15:12.898863 TX OE : NO K
6099 20:15:12.898942 All Pass.
6100 20:15:12.899023
6101 20:15:12.902198 DramC Write-DBI off
6102 20:15:12.902276 PER_BANK_REFRESH: Hybrid Mode
6103 20:15:12.905538 TX_TRACKING: ON
6104 20:15:12.915336 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6105 20:15:12.918653 [FAST_K] Save calibration result to emmc
6106 20:15:12.922096 dramc_set_vcore_voltage set vcore to 650000
6107 20:15:12.922177 Read voltage for 400, 6
6108 20:15:12.925294 Vio18 = 0
6109 20:15:12.925397 Vcore = 650000
6110 20:15:12.925491 Vdram = 0
6111 20:15:12.929170 Vddq = 0
6112 20:15:12.929238 Vmddr = 0
6113 20:15:12.935316 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6114 20:15:12.938851 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6115 20:15:12.941765 MEM_TYPE=3, freq_sel=20
6116 20:15:12.945284 sv_algorithm_assistance_LP4_800
6117 20:15:12.948512 ============ PULL DRAM RESETB DOWN ============
6118 20:15:12.951806 ========== PULL DRAM RESETB DOWN end =========
6119 20:15:12.958586 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6120 20:15:12.962064 ===================================
6121 20:15:12.962160 LPDDR4 DRAM CONFIGURATION
6122 20:15:12.965217 ===================================
6123 20:15:12.968660 EX_ROW_EN[0] = 0x0
6124 20:15:12.968734 EX_ROW_EN[1] = 0x0
6125 20:15:12.971816 LP4Y_EN = 0x0
6126 20:15:12.971892 WORK_FSP = 0x0
6127 20:15:12.975262 WL = 0x2
6128 20:15:12.978267 RL = 0x2
6129 20:15:12.978336 BL = 0x2
6130 20:15:12.981750 RPST = 0x0
6131 20:15:12.981825 RD_PRE = 0x0
6132 20:15:12.985295 WR_PRE = 0x1
6133 20:15:12.985400 WR_PST = 0x0
6134 20:15:12.988333 DBI_WR = 0x0
6135 20:15:12.988412 DBI_RD = 0x0
6136 20:15:12.991764 OTF = 0x1
6137 20:15:12.994903 ===================================
6138 20:15:12.998366 ===================================
6139 20:15:12.998445 ANA top config
6140 20:15:13.001798 ===================================
6141 20:15:13.005028 DLL_ASYNC_EN = 0
6142 20:15:13.008229 ALL_SLAVE_EN = 1
6143 20:15:13.008302 NEW_RANK_MODE = 1
6144 20:15:13.011431 DLL_IDLE_MODE = 1
6145 20:15:13.014771 LP45_APHY_COMB_EN = 1
6146 20:15:13.018068 TX_ODT_DIS = 1
6147 20:15:13.021307 NEW_8X_MODE = 1
6148 20:15:13.024754 ===================================
6149 20:15:13.028023 ===================================
6150 20:15:13.028099 data_rate = 800
6151 20:15:13.031565 CKR = 1
6152 20:15:13.034922 DQ_P2S_RATIO = 4
6153 20:15:13.038073 ===================================
6154 20:15:13.041329 CA_P2S_RATIO = 4
6155 20:15:13.044848 DQ_CA_OPEN = 0
6156 20:15:13.047980 DQ_SEMI_OPEN = 1
6157 20:15:13.048089 CA_SEMI_OPEN = 1
6158 20:15:13.051118 CA_FULL_RATE = 0
6159 20:15:13.054633 DQ_CKDIV4_EN = 0
6160 20:15:13.058035 CA_CKDIV4_EN = 1
6161 20:15:13.061084 CA_PREDIV_EN = 0
6162 20:15:13.064607 PH8_DLY = 0
6163 20:15:13.064689 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6164 20:15:13.067665 DQ_AAMCK_DIV = 0
6165 20:15:13.071143 CA_AAMCK_DIV = 0
6166 20:15:13.074304 CA_ADMCK_DIV = 4
6167 20:15:13.077710 DQ_TRACK_CA_EN = 0
6168 20:15:13.081013 CA_PICK = 800
6169 20:15:13.084269 CA_MCKIO = 400
6170 20:15:13.084350 MCKIO_SEMI = 400
6171 20:15:13.087764 PLL_FREQ = 3016
6172 20:15:13.091000 DQ_UI_PI_RATIO = 32
6173 20:15:13.094570 CA_UI_PI_RATIO = 32
6174 20:15:13.097592 ===================================
6175 20:15:13.101046 ===================================
6176 20:15:13.104041 memory_type:LPDDR4
6177 20:15:13.104123 GP_NUM : 10
6178 20:15:13.107443 SRAM_EN : 1
6179 20:15:13.110812 MD32_EN : 0
6180 20:15:13.114249 ===================================
6181 20:15:13.114338 [ANA_INIT] >>>>>>>>>>>>>>
6182 20:15:13.117385 <<<<<< [CONFIGURE PHASE]: ANA_TX
6183 20:15:13.120632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6184 20:15:13.124300 ===================================
6185 20:15:13.127562 data_rate = 800,PCW = 0X7400
6186 20:15:13.130788 ===================================
6187 20:15:13.134167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6188 20:15:13.140656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6189 20:15:13.150528 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6190 20:15:13.157378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6191 20:15:13.160458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6192 20:15:13.163920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6193 20:15:13.163995 [ANA_INIT] flow start
6194 20:15:13.167160 [ANA_INIT] PLL >>>>>>>>
6195 20:15:13.170447 [ANA_INIT] PLL <<<<<<<<
6196 20:15:13.170548 [ANA_INIT] MIDPI >>>>>>>>
6197 20:15:13.173765 [ANA_INIT] MIDPI <<<<<<<<
6198 20:15:13.177080 [ANA_INIT] DLL >>>>>>>>
6199 20:15:13.177159 [ANA_INIT] flow end
6200 20:15:13.183675 ============ LP4 DIFF to SE enter ============
6201 20:15:13.187145 ============ LP4 DIFF to SE exit ============
6202 20:15:13.187218 [ANA_INIT] <<<<<<<<<<<<<
6203 20:15:13.190412 [Flow] Enable top DCM control >>>>>
6204 20:15:13.193695 [Flow] Enable top DCM control <<<<<
6205 20:15:13.196889 Enable DLL master slave shuffle
6206 20:15:13.203825 ==============================================================
6207 20:15:13.207292 Gating Mode config
6208 20:15:13.210320 ==============================================================
6209 20:15:13.213407 Config description:
6210 20:15:13.223398 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6211 20:15:13.230457 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6212 20:15:13.233624 SELPH_MODE 0: By rank 1: By Phase
6213 20:15:13.240143 ==============================================================
6214 20:15:13.243594 GAT_TRACK_EN = 0
6215 20:15:13.246606 RX_GATING_MODE = 2
6216 20:15:13.249958 RX_GATING_TRACK_MODE = 2
6217 20:15:13.250033 SELPH_MODE = 1
6218 20:15:13.253246 PICG_EARLY_EN = 1
6219 20:15:13.256592 VALID_LAT_VALUE = 1
6220 20:15:13.263290 ==============================================================
6221 20:15:13.266349 Enter into Gating configuration >>>>
6222 20:15:13.269956 Exit from Gating configuration <<<<
6223 20:15:13.273197 Enter into DVFS_PRE_config >>>>>
6224 20:15:13.283055 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6225 20:15:13.286399 Exit from DVFS_PRE_config <<<<<
6226 20:15:13.289957 Enter into PICG configuration >>>>
6227 20:15:13.292947 Exit from PICG configuration <<<<
6228 20:15:13.296432 [RX_INPUT] configuration >>>>>
6229 20:15:13.299992 [RX_INPUT] configuration <<<<<
6230 20:15:13.302895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6231 20:15:13.309458 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6232 20:15:13.316508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6233 20:15:13.322761 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6234 20:15:13.329643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6235 20:15:13.336219 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6236 20:15:13.339447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6237 20:15:13.343129 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6238 20:15:13.346180 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6239 20:15:13.352815 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6240 20:15:13.356218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6241 20:15:13.359415 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6242 20:15:13.362616 ===================================
6243 20:15:13.366127 LPDDR4 DRAM CONFIGURATION
6244 20:15:13.369437 ===================================
6245 20:15:13.369885 EX_ROW_EN[0] = 0x0
6246 20:15:13.372475 EX_ROW_EN[1] = 0x0
6247 20:15:13.372861 LP4Y_EN = 0x0
6248 20:15:13.375773 WORK_FSP = 0x0
6249 20:15:13.379229 WL = 0x2
6250 20:15:13.379720 RL = 0x2
6251 20:15:13.382221 BL = 0x2
6252 20:15:13.382610 RPST = 0x0
6253 20:15:13.385733 RD_PRE = 0x0
6254 20:15:13.386056 WR_PRE = 0x1
6255 20:15:13.389076 WR_PST = 0x0
6256 20:15:13.389368 DBI_WR = 0x0
6257 20:15:13.392734 DBI_RD = 0x0
6258 20:15:13.393030 OTF = 0x1
6259 20:15:13.395720 ===================================
6260 20:15:13.398898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6261 20:15:13.405651 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6262 20:15:13.408725 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6263 20:15:13.412102 ===================================
6264 20:15:13.415597 LPDDR4 DRAM CONFIGURATION
6265 20:15:13.419079 ===================================
6266 20:15:13.419377 EX_ROW_EN[0] = 0x10
6267 20:15:13.421945 EX_ROW_EN[1] = 0x0
6268 20:15:13.422223 LP4Y_EN = 0x0
6269 20:15:13.425313 WORK_FSP = 0x0
6270 20:15:13.425657 WL = 0x2
6271 20:15:13.428736 RL = 0x2
6272 20:15:13.431983 BL = 0x2
6273 20:15:13.432206 RPST = 0x0
6274 20:15:13.435084 RD_PRE = 0x0
6275 20:15:13.435294 WR_PRE = 0x1
6276 20:15:13.438567 WR_PST = 0x0
6277 20:15:13.438746 DBI_WR = 0x0
6278 20:15:13.441781 DBI_RD = 0x0
6279 20:15:13.441863 OTF = 0x1
6280 20:15:13.444984 ===================================
6281 20:15:13.451320 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6282 20:15:13.455603 nWR fixed to 30
6283 20:15:13.458797 [ModeRegInit_LP4] CH0 RK0
6284 20:15:13.458881 [ModeRegInit_LP4] CH0 RK1
6285 20:15:13.462348 [ModeRegInit_LP4] CH1 RK0
6286 20:15:13.465488 [ModeRegInit_LP4] CH1 RK1
6287 20:15:13.465572 match AC timing 19
6288 20:15:13.472077 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6289 20:15:13.475402 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6290 20:15:13.478616 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6291 20:15:13.485423 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6292 20:15:13.488750 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6293 20:15:13.488837 ==
6294 20:15:13.491971 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 20:15:13.495109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 20:15:13.495195 ==
6297 20:15:13.501999 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 20:15:13.508551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6299 20:15:13.511902 [CA 0] Center 36 (8~64) winsize 57
6300 20:15:13.515227 [CA 1] Center 36 (8~64) winsize 57
6301 20:15:13.518378 [CA 2] Center 36 (8~64) winsize 57
6302 20:15:13.522062 [CA 3] Center 36 (8~64) winsize 57
6303 20:15:13.522136 [CA 4] Center 36 (8~64) winsize 57
6304 20:15:13.525317 [CA 5] Center 36 (8~64) winsize 57
6305 20:15:13.525414
6306 20:15:13.531858 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6307 20:15:13.531932
6308 20:15:13.535093 [CATrainingPosCal] consider 1 rank data
6309 20:15:13.538212 u2DelayCellTimex100 = 270/100 ps
6310 20:15:13.541617 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 20:15:13.544991 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 20:15:13.548303 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 20:15:13.551623 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 20:15:13.554838 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 20:15:13.558296 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 20:15:13.558396
6317 20:15:13.561414 CA PerBit enable=1, Macro0, CA PI delay=36
6318 20:15:13.561560
6319 20:15:13.564736 [CBTSetCACLKResult] CA Dly = 36
6320 20:15:13.568201 CS Dly: 1 (0~32)
6321 20:15:13.568299 ==
6322 20:15:13.571623 Dram Type= 6, Freq= 0, CH_0, rank 1
6323 20:15:13.574689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 20:15:13.574767 ==
6325 20:15:13.581405 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6326 20:15:13.588134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6327 20:15:13.588232 [CA 0] Center 36 (8~64) winsize 57
6328 20:15:13.591252 [CA 1] Center 36 (8~64) winsize 57
6329 20:15:13.594823 [CA 2] Center 36 (8~64) winsize 57
6330 20:15:13.598306 [CA 3] Center 36 (8~64) winsize 57
6331 20:15:13.601665 [CA 4] Center 36 (8~64) winsize 57
6332 20:15:13.604605 [CA 5] Center 36 (8~64) winsize 57
6333 20:15:13.604704
6334 20:15:13.608001 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6335 20:15:13.608082
6336 20:15:13.611350 [CATrainingPosCal] consider 2 rank data
6337 20:15:13.614818 u2DelayCellTimex100 = 270/100 ps
6338 20:15:13.618125 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 20:15:13.621213 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 20:15:13.627997 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 20:15:13.631479 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 20:15:13.634913 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 20:15:13.638027 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 20:15:13.638108
6345 20:15:13.641439 CA PerBit enable=1, Macro0, CA PI delay=36
6346 20:15:13.641557
6347 20:15:13.644463 [CBTSetCACLKResult] CA Dly = 36
6348 20:15:13.644575 CS Dly: 1 (0~32)
6349 20:15:13.644684
6350 20:15:13.647787 ----->DramcWriteLeveling(PI) begin...
6351 20:15:13.651405 ==
6352 20:15:13.654485 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 20:15:13.657713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 20:15:13.657820 ==
6355 20:15:13.661193 Write leveling (Byte 0): 40 => 8
6356 20:15:13.664584 Write leveling (Byte 1): 40 => 8
6357 20:15:13.667984 DramcWriteLeveling(PI) end<-----
6358 20:15:13.668109
6359 20:15:13.668200 ==
6360 20:15:13.671154 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 20:15:13.674432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 20:15:13.674516 ==
6363 20:15:13.677604 [Gating] SW mode calibration
6364 20:15:13.684433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6365 20:15:13.690939 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6366 20:15:13.694272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6367 20:15:13.697432 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6368 20:15:13.704083 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6369 20:15:13.707705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6370 20:15:13.711230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 20:15:13.714352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 20:15:13.721045 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 20:15:13.724071 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 20:15:13.727547 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6375 20:15:13.731104 Total UI for P1: 0, mck2ui 16
6376 20:15:13.734116 best dqsien dly found for B0: ( 0, 14, 24)
6377 20:15:13.737514 Total UI for P1: 0, mck2ui 16
6378 20:15:13.740643 best dqsien dly found for B1: ( 0, 14, 24)
6379 20:15:13.747443 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6380 20:15:13.750837 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6381 20:15:13.751073
6382 20:15:13.753888 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6383 20:15:13.757468 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6384 20:15:13.760521 [Gating] SW calibration Done
6385 20:15:13.760898 ==
6386 20:15:13.764059 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 20:15:13.767276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 20:15:13.767752 ==
6389 20:15:13.770600 RX Vref Scan: 0
6390 20:15:13.771086
6391 20:15:13.771465 RX Vref 0 -> 0, step: 1
6392 20:15:13.771924
6393 20:15:13.774198 RX Delay -410 -> 252, step: 16
6394 20:15:13.780409 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6395 20:15:13.783862 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6396 20:15:13.787223 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6397 20:15:13.790493 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6398 20:15:13.796833 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6399 20:15:13.800294 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6400 20:15:13.803428 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6401 20:15:13.806993 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6402 20:15:13.813740 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6403 20:15:13.816995 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6404 20:15:13.820130 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6405 20:15:13.823531 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6406 20:15:13.830282 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6407 20:15:13.833761 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6408 20:15:13.836809 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6409 20:15:13.840334 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6410 20:15:13.843560 ==
6411 20:15:13.844195 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 20:15:13.850527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 20:15:13.851014 ==
6414 20:15:13.851417 DQS Delay:
6415 20:15:13.853315 DQS0 = 59, DQS1 = 59
6416 20:15:13.853900 DQM Delay:
6417 20:15:13.856604 DQM0 = 17, DQM1 = 10
6418 20:15:13.857170 DQ Delay:
6419 20:15:13.860093 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6420 20:15:13.863563 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6421 20:15:13.866695 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6422 20:15:13.869968 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6423 20:15:13.870465
6424 20:15:13.870882
6425 20:15:13.871295 ==
6426 20:15:13.873207 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 20:15:13.876578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 20:15:13.877076 ==
6429 20:15:13.877665
6430 20:15:13.878066
6431 20:15:13.879889 TX Vref Scan disable
6432 20:15:13.880430 == TX Byte 0 ==
6433 20:15:13.886377 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 20:15:13.889767 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 20:15:13.890175 == TX Byte 1 ==
6436 20:15:13.896281 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 20:15:13.899616 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 20:15:13.900142 ==
6439 20:15:13.903389 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 20:15:13.906403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 20:15:13.906837 ==
6442 20:15:13.907187
6443 20:15:13.907507
6444 20:15:13.909987 TX Vref Scan disable
6445 20:15:13.910572 == TX Byte 0 ==
6446 20:15:13.916391 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6447 20:15:13.919752 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6448 20:15:13.920171 == TX Byte 1 ==
6449 20:15:13.926280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6450 20:15:13.929411 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6451 20:15:13.930043
6452 20:15:13.930570 [DATLAT]
6453 20:15:13.932717 Freq=400, CH0 RK0
6454 20:15:13.933154
6455 20:15:13.933531 DATLAT Default: 0xf
6456 20:15:13.936199 0, 0xFFFF, sum = 0
6457 20:15:13.936647 1, 0xFFFF, sum = 0
6458 20:15:13.939249 2, 0xFFFF, sum = 0
6459 20:15:13.939638 3, 0xFFFF, sum = 0
6460 20:15:13.942808 4, 0xFFFF, sum = 0
6461 20:15:13.943360 5, 0xFFFF, sum = 0
6462 20:15:13.946127 6, 0xFFFF, sum = 0
6463 20:15:13.949445 7, 0xFFFF, sum = 0
6464 20:15:13.949925 8, 0xFFFF, sum = 0
6465 20:15:13.952901 9, 0xFFFF, sum = 0
6466 20:15:13.953334 10, 0xFFFF, sum = 0
6467 20:15:13.955991 11, 0xFFFF, sum = 0
6468 20:15:13.956412 12, 0xFFFF, sum = 0
6469 20:15:13.959262 13, 0x0, sum = 1
6470 20:15:13.959699 14, 0x0, sum = 2
6471 20:15:13.962887 15, 0x0, sum = 3
6472 20:15:13.963312 16, 0x0, sum = 4
6473 20:15:13.963665 best_step = 14
6474 20:15:13.965957
6475 20:15:13.966508 ==
6476 20:15:13.969172 Dram Type= 6, Freq= 0, CH_0, rank 0
6477 20:15:13.972407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 20:15:13.972952 ==
6479 20:15:13.973441 RX Vref Scan: 1
6480 20:15:13.973939
6481 20:15:13.975717 RX Vref 0 -> 0, step: 1
6482 20:15:13.976147
6483 20:15:13.979448 RX Delay -359 -> 252, step: 8
6484 20:15:13.979883
6485 20:15:13.982466 Set Vref, RX VrefLevel [Byte0]: 61
6486 20:15:13.986061 [Byte1]: 45
6487 20:15:13.989874
6488 20:15:13.990298 Final RX Vref Byte 0 = 61 to rank0
6489 20:15:13.993468 Final RX Vref Byte 1 = 45 to rank0
6490 20:15:13.996229 Final RX Vref Byte 0 = 61 to rank1
6491 20:15:13.999943 Final RX Vref Byte 1 = 45 to rank1==
6492 20:15:14.003111 Dram Type= 6, Freq= 0, CH_0, rank 0
6493 20:15:14.009571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 20:15:14.010207 ==
6495 20:15:14.010773 DQS Delay:
6496 20:15:14.012939 DQS0 = 60, DQS1 = 64
6497 20:15:14.013556 DQM Delay:
6498 20:15:14.014076 DQM0 = 15, DQM1 = 10
6499 20:15:14.015927 DQ Delay:
6500 20:15:14.019565 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =16
6501 20:15:14.022770 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6502 20:15:14.025866 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6503 20:15:14.029244 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6504 20:15:14.029714
6505 20:15:14.030063
6506 20:15:14.036252 [DQSOSCAuto] RK0, (LSB)MR18= 0x807e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6507 20:15:14.039343 CH0 RK0: MR19=C0C, MR18=807E
6508 20:15:14.045975 CH0_RK0: MR19=0xC0C, MR18=0x807E, DQSOSC=393, MR23=63, INC=382, DEC=254
6509 20:15:14.046444 ==
6510 20:15:14.049145 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 20:15:14.052569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 20:15:14.052996 ==
6513 20:15:14.055841 [Gating] SW mode calibration
6514 20:15:14.062227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6515 20:15:14.068720 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6516 20:15:14.072236 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6517 20:15:14.075709 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6518 20:15:14.082237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 20:15:14.085467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6520 20:15:14.088644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 20:15:14.095611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 20:15:14.099179 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 20:15:14.102451 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 20:15:14.108660 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6525 20:15:14.108963 Total UI for P1: 0, mck2ui 16
6526 20:15:14.115428 best dqsien dly found for B0: ( 0, 14, 24)
6527 20:15:14.115728 Total UI for P1: 0, mck2ui 16
6528 20:15:14.121675 best dqsien dly found for B1: ( 0, 14, 24)
6529 20:15:14.125243 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6530 20:15:14.128455 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6531 20:15:14.128754
6532 20:15:14.131778 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6533 20:15:14.135197 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6534 20:15:14.138576 [Gating] SW calibration Done
6535 20:15:14.138875 ==
6536 20:15:14.141646 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 20:15:14.145014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 20:15:14.145317 ==
6539 20:15:14.148308 RX Vref Scan: 0
6540 20:15:14.148728
6541 20:15:14.149082 RX Vref 0 -> 0, step: 1
6542 20:15:14.151821
6543 20:15:14.152121 RX Delay -410 -> 252, step: 16
6544 20:15:14.158441 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6545 20:15:14.161421 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6546 20:15:14.164851 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6547 20:15:14.168402 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6548 20:15:14.175255 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6549 20:15:14.178275 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6550 20:15:14.181327 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6551 20:15:14.184516 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6552 20:15:14.191197 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6553 20:15:14.194350 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6554 20:15:14.197924 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6555 20:15:14.204520 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6556 20:15:14.207855 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6557 20:15:14.211013 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6558 20:15:14.214528 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6559 20:15:14.220973 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6560 20:15:14.221396 ==
6561 20:15:14.224403 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 20:15:14.227686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 20:15:14.228110 ==
6564 20:15:14.228445 DQS Delay:
6565 20:15:14.231083 DQS0 = 59, DQS1 = 59
6566 20:15:14.231503 DQM Delay:
6567 20:15:14.234409 DQM0 = 17, DQM1 = 10
6568 20:15:14.234831 DQ Delay:
6569 20:15:14.237831 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6570 20:15:14.241088 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6571 20:15:14.244520 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6572 20:15:14.247663 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6573 20:15:14.248085
6574 20:15:14.248430
6575 20:15:14.248737 ==
6576 20:15:14.250895 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 20:15:14.254490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 20:15:14.255032 ==
6579 20:15:14.255399
6580 20:15:14.257942
6581 20:15:14.258432 TX Vref Scan disable
6582 20:15:14.260870 == TX Byte 0 ==
6583 20:15:14.264213 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6584 20:15:14.267204 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6585 20:15:14.270581 == TX Byte 1 ==
6586 20:15:14.274191 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6587 20:15:14.277547 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6588 20:15:14.277970 ==
6589 20:15:14.280890 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 20:15:14.284085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 20:15:14.284507 ==
6592 20:15:14.287518
6593 20:15:14.287934
6594 20:15:14.288262 TX Vref Scan disable
6595 20:15:14.290731 == TX Byte 0 ==
6596 20:15:14.294030 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6597 20:15:14.297260 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6598 20:15:14.300775 == TX Byte 1 ==
6599 20:15:14.304028 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6600 20:15:14.307526 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6601 20:15:14.308126
6602 20:15:14.308628 [DATLAT]
6603 20:15:14.310578 Freq=400, CH0 RK1
6604 20:15:14.311076
6605 20:15:14.313981 DATLAT Default: 0xe
6606 20:15:14.314470 0, 0xFFFF, sum = 0
6607 20:15:14.317346 1, 0xFFFF, sum = 0
6608 20:15:14.317908 2, 0xFFFF, sum = 0
6609 20:15:14.320801 3, 0xFFFF, sum = 0
6610 20:15:14.321285 4, 0xFFFF, sum = 0
6611 20:15:14.323886 5, 0xFFFF, sum = 0
6612 20:15:14.324559 6, 0xFFFF, sum = 0
6613 20:15:14.327317 7, 0xFFFF, sum = 0
6614 20:15:14.327765 8, 0xFFFF, sum = 0
6615 20:15:14.330456 9, 0xFFFF, sum = 0
6616 20:15:14.330904 10, 0xFFFF, sum = 0
6617 20:15:14.333889 11, 0xFFFF, sum = 0
6618 20:15:14.334386 12, 0xFFFF, sum = 0
6619 20:15:14.337025 13, 0x0, sum = 1
6620 20:15:14.337468 14, 0x0, sum = 2
6621 20:15:14.340282 15, 0x0, sum = 3
6622 20:15:14.340810 16, 0x0, sum = 4
6623 20:15:14.343479 best_step = 14
6624 20:15:14.343923
6625 20:15:14.344446 ==
6626 20:15:14.346895 Dram Type= 6, Freq= 0, CH_0, rank 1
6627 20:15:14.350218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 20:15:14.350646 ==
6629 20:15:14.353588 RX Vref Scan: 0
6630 20:15:14.354014
6631 20:15:14.354358 RX Vref 0 -> 0, step: 1
6632 20:15:14.354681
6633 20:15:14.356707 RX Delay -359 -> 252, step: 8
6634 20:15:14.364758 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6635 20:15:14.368337 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6636 20:15:14.371278 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6637 20:15:14.374917 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6638 20:15:14.381572 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6639 20:15:14.384504 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6640 20:15:14.388129 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6641 20:15:14.391362 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6642 20:15:14.397632 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6643 20:15:14.400950 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6644 20:15:14.404526 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6645 20:15:14.411039 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6646 20:15:14.414261 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6647 20:15:14.417750 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6648 20:15:14.420720 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6649 20:15:14.427824 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6650 20:15:14.428364 ==
6651 20:15:14.430810 Dram Type= 6, Freq= 0, CH_0, rank 1
6652 20:15:14.434357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 20:15:14.434777 ==
6654 20:15:14.435249 DQS Delay:
6655 20:15:14.437332 DQS0 = 60, DQS1 = 72
6656 20:15:14.437847 DQM Delay:
6657 20:15:14.440933 DQM0 = 12, DQM1 = 17
6658 20:15:14.441361 DQ Delay:
6659 20:15:14.444472 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6660 20:15:14.447749 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6661 20:15:14.450852 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6662 20:15:14.453999 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6663 20:15:14.454429
6664 20:15:14.454761
6665 20:15:14.460927 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6666 20:15:14.463958 CH0 RK1: MR19=C0C, MR18=CB81
6667 20:15:14.470710 CH0_RK1: MR19=0xC0C, MR18=0xCB81, DQSOSC=384, MR23=63, INC=400, DEC=267
6668 20:15:14.474132 [RxdqsGatingPostProcess] freq 400
6669 20:15:14.480642 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6670 20:15:14.483870 best DQS0 dly(2T, 0.5T) = (0, 10)
6671 20:15:14.487262 best DQS1 dly(2T, 0.5T) = (0, 10)
6672 20:15:14.490499 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6673 20:15:14.493538 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6674 20:15:14.493971 best DQS0 dly(2T, 0.5T) = (0, 10)
6675 20:15:14.497161 best DQS1 dly(2T, 0.5T) = (0, 10)
6676 20:15:14.500239 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6677 20:15:14.503678 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6678 20:15:14.507183 Pre-setting of DQS Precalculation
6679 20:15:14.513417 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6680 20:15:14.513867 ==
6681 20:15:14.516957 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 20:15:14.520242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 20:15:14.520885 ==
6684 20:15:14.526950 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 20:15:14.533303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6686 20:15:14.533788 [CA 0] Center 36 (8~64) winsize 57
6687 20:15:14.536768 [CA 1] Center 36 (8~64) winsize 57
6688 20:15:14.540204 [CA 2] Center 36 (8~64) winsize 57
6689 20:15:14.543410 [CA 3] Center 36 (8~64) winsize 57
6690 20:15:14.546790 [CA 4] Center 36 (8~64) winsize 57
6691 20:15:14.550261 [CA 5] Center 36 (8~64) winsize 57
6692 20:15:14.550683
6693 20:15:14.553603 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6694 20:15:14.554052
6695 20:15:14.556694 [CATrainingPosCal] consider 1 rank data
6696 20:15:14.560096 u2DelayCellTimex100 = 270/100 ps
6697 20:15:14.563434 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 20:15:14.567063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 20:15:14.573568 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 20:15:14.576511 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 20:15:14.580005 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 20:15:14.583219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 20:15:14.583646
6704 20:15:14.586487 CA PerBit enable=1, Macro0, CA PI delay=36
6705 20:15:14.586989
6706 20:15:14.589892 [CBTSetCACLKResult] CA Dly = 36
6707 20:15:14.590315 CS Dly: 1 (0~32)
6708 20:15:14.593019 ==
6709 20:15:14.596416 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 20:15:14.599963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 20:15:14.600389 ==
6712 20:15:14.603134 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6713 20:15:14.609963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6714 20:15:14.612923 [CA 0] Center 36 (8~64) winsize 57
6715 20:15:14.616354 [CA 1] Center 36 (8~64) winsize 57
6716 20:15:14.619759 [CA 2] Center 36 (8~64) winsize 57
6717 20:15:14.622910 [CA 3] Center 36 (8~64) winsize 57
6718 20:15:14.626313 [CA 4] Center 36 (8~64) winsize 57
6719 20:15:14.629456 [CA 5] Center 36 (8~64) winsize 57
6720 20:15:14.630091
6721 20:15:14.632956 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6722 20:15:14.633599
6723 20:15:14.636075 [CATrainingPosCal] consider 2 rank data
6724 20:15:14.639347 u2DelayCellTimex100 = 270/100 ps
6725 20:15:14.642955 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 20:15:14.645960 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 20:15:14.649310 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 20:15:14.656210 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 20:15:14.659269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 20:15:14.662729 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 20:15:14.663359
6732 20:15:14.666022 CA PerBit enable=1, Macro0, CA PI delay=36
6733 20:15:14.666659
6734 20:15:14.669215 [CBTSetCACLKResult] CA Dly = 36
6735 20:15:14.669841 CS Dly: 1 (0~32)
6736 20:15:14.670279
6737 20:15:14.672601 ----->DramcWriteLeveling(PI) begin...
6738 20:15:14.673154 ==
6739 20:15:14.675792 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 20:15:14.682682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 20:15:14.683188 ==
6742 20:15:14.685579 Write leveling (Byte 0): 40 => 8
6743 20:15:14.689057 Write leveling (Byte 1): 40 => 8
6744 20:15:14.689447 DramcWriteLeveling(PI) end<-----
6745 20:15:14.689858
6746 20:15:14.692276 ==
6747 20:15:14.696027 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 20:15:14.698851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 20:15:14.699356 ==
6750 20:15:14.702418 [Gating] SW mode calibration
6751 20:15:14.708979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6752 20:15:14.712176 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6753 20:15:14.718794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6754 20:15:14.722214 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6755 20:15:14.725764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6756 20:15:14.732300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6757 20:15:14.735385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 20:15:14.738841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 20:15:14.745200 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 20:15:14.748676 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 20:15:14.751616 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6762 20:15:14.755484 Total UI for P1: 0, mck2ui 16
6763 20:15:14.759025 best dqsien dly found for B0: ( 0, 14, 24)
6764 20:15:14.761832 Total UI for P1: 0, mck2ui 16
6765 20:15:14.765006 best dqsien dly found for B1: ( 0, 14, 24)
6766 20:15:14.768658 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6767 20:15:14.771810 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6768 20:15:14.775011
6769 20:15:14.777870 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6770 20:15:14.781338 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6771 20:15:14.784874 [Gating] SW calibration Done
6772 20:15:14.784956 ==
6773 20:15:14.788086 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 20:15:14.791240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 20:15:14.791327 ==
6776 20:15:14.791391 RX Vref Scan: 0
6777 20:15:14.794470
6778 20:15:14.794552 RX Vref 0 -> 0, step: 1
6779 20:15:14.794617
6780 20:15:14.797869 RX Delay -410 -> 252, step: 16
6781 20:15:14.801034 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6782 20:15:14.807660 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6783 20:15:14.811117 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6784 20:15:14.814373 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6785 20:15:14.817768 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6786 20:15:14.824163 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6787 20:15:14.827488 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6788 20:15:14.830910 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6789 20:15:14.834213 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6790 20:15:14.840761 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6791 20:15:14.844281 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6792 20:15:14.847357 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6793 20:15:14.850814 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6794 20:15:14.857208 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6795 20:15:14.860942 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6796 20:15:14.864150 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6797 20:15:14.864239 ==
6798 20:15:14.867440 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 20:15:14.873957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 20:15:14.874062 ==
6801 20:15:14.874147 DQS Delay:
6802 20:15:14.877261 DQS0 = 51, DQS1 = 67
6803 20:15:14.877372 DQM Delay:
6804 20:15:14.877460 DQM0 = 13, DQM1 = 19
6805 20:15:14.880829 DQ Delay:
6806 20:15:14.883769 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6807 20:15:14.883890 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6808 20:15:14.887130 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6809 20:15:14.890496 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6810 20:15:14.894094
6811 20:15:14.894253
6812 20:15:14.894378 ==
6813 20:15:14.897208 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 20:15:14.900481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 20:15:14.900682 ==
6816 20:15:14.900876
6817 20:15:14.901041
6818 20:15:14.903889 TX Vref Scan disable
6819 20:15:14.904104 == TX Byte 0 ==
6820 20:15:14.907089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 20:15:14.913961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 20:15:14.914321 == TX Byte 1 ==
6823 20:15:14.917186 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 20:15:14.923969 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 20:15:14.924412 ==
6826 20:15:14.926969 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 20:15:14.930405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 20:15:14.930887 ==
6829 20:15:14.931223
6830 20:15:14.931557
6831 20:15:14.934009 TX Vref Scan disable
6832 20:15:14.934452 == TX Byte 0 ==
6833 20:15:14.940004 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6834 20:15:14.943538 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6835 20:15:14.944142 == TX Byte 1 ==
6836 20:15:14.950091 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 20:15:14.953319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 20:15:14.953827
6839 20:15:14.954192 [DATLAT]
6840 20:15:14.956901 Freq=400, CH1 RK0
6841 20:15:14.957338
6842 20:15:14.957734 DATLAT Default: 0xf
6843 20:15:14.959762 0, 0xFFFF, sum = 0
6844 20:15:14.960388 1, 0xFFFF, sum = 0
6845 20:15:14.963514 2, 0xFFFF, sum = 0
6846 20:15:14.963974 3, 0xFFFF, sum = 0
6847 20:15:14.966523 4, 0xFFFF, sum = 0
6848 20:15:14.967053 5, 0xFFFF, sum = 0
6849 20:15:14.969846 6, 0xFFFF, sum = 0
6850 20:15:14.970327 7, 0xFFFF, sum = 0
6851 20:15:14.973129 8, 0xFFFF, sum = 0
6852 20:15:14.973638 9, 0xFFFF, sum = 0
6853 20:15:14.976508 10, 0xFFFF, sum = 0
6854 20:15:14.980013 11, 0xFFFF, sum = 0
6855 20:15:14.980463 12, 0xFFFF, sum = 0
6856 20:15:14.983140 13, 0x0, sum = 1
6857 20:15:14.983571 14, 0x0, sum = 2
6858 20:15:14.984095 15, 0x0, sum = 3
6859 20:15:14.986541 16, 0x0, sum = 4
6860 20:15:14.987001 best_step = 14
6861 20:15:14.987361
6862 20:15:14.989751 ==
6863 20:15:14.993007 Dram Type= 6, Freq= 0, CH_1, rank 0
6864 20:15:14.996659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 20:15:14.997235 ==
6866 20:15:14.997766 RX Vref Scan: 1
6867 20:15:14.998216
6868 20:15:14.999666 RX Vref 0 -> 0, step: 1
6869 20:15:15.000172
6870 20:15:15.002590 RX Delay -375 -> 252, step: 8
6871 20:15:15.003096
6872 20:15:15.006089 Set Vref, RX VrefLevel [Byte0]: 55
6873 20:15:15.009123 [Byte1]: 48
6874 20:15:15.013305
6875 20:15:15.013798 Final RX Vref Byte 0 = 55 to rank0
6876 20:15:15.016536 Final RX Vref Byte 1 = 48 to rank0
6877 20:15:15.019917 Final RX Vref Byte 0 = 55 to rank1
6878 20:15:15.023094 Final RX Vref Byte 1 = 48 to rank1==
6879 20:15:15.026652 Dram Type= 6, Freq= 0, CH_1, rank 0
6880 20:15:15.033031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 20:15:15.033454 ==
6882 20:15:15.034005 DQS Delay:
6883 20:15:15.036441 DQS0 = 52, DQS1 = 68
6884 20:15:15.036859 DQM Delay:
6885 20:15:15.037186 DQM0 = 9, DQM1 = 14
6886 20:15:15.039959 DQ Delay:
6887 20:15:15.043112 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6888 20:15:15.043534 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6889 20:15:15.046370 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6890 20:15:15.049720 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6891 20:15:15.050143
6892 20:15:15.050475
6893 20:15:15.059541 [DQSOSCAuto] RK0, (LSB)MR18= 0x5669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6894 20:15:15.062954 CH1 RK0: MR19=C0C, MR18=5669
6895 20:15:15.069756 CH1_RK0: MR19=0xC0C, MR18=0x5669, DQSOSC=396, MR23=63, INC=376, DEC=251
6896 20:15:15.070328 ==
6897 20:15:15.072859 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 20:15:15.076381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 20:15:15.076924 ==
6900 20:15:15.079512 [Gating] SW mode calibration
6901 20:15:15.086281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6902 20:15:15.092893 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6903 20:15:15.096421 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6904 20:15:15.099691 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6905 20:15:15.102833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6906 20:15:15.109227 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6907 20:15:15.112641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 20:15:15.115956 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 20:15:15.122635 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 20:15:15.125907 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 20:15:15.129099 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6912 20:15:15.132399 Total UI for P1: 0, mck2ui 16
6913 20:15:15.135784 best dqsien dly found for B0: ( 0, 14, 24)
6914 20:15:15.139206 Total UI for P1: 0, mck2ui 16
6915 20:15:15.142308 best dqsien dly found for B1: ( 0, 14, 24)
6916 20:15:15.148704 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6917 20:15:15.152139 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6918 20:15:15.152574
6919 20:15:15.155529 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6920 20:15:15.158919 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6921 20:15:15.162327 [Gating] SW calibration Done
6922 20:15:15.162746 ==
6923 20:15:15.165580 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 20:15:15.168959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 20:15:15.169379 ==
6926 20:15:15.171995 RX Vref Scan: 0
6927 20:15:15.172413
6928 20:15:15.172747 RX Vref 0 -> 0, step: 1
6929 20:15:15.173061
6930 20:15:15.175397 RX Delay -410 -> 252, step: 16
6931 20:15:15.182191 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6932 20:15:15.185621 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6933 20:15:15.188540 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6934 20:15:15.191946 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6935 20:15:15.198439 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6936 20:15:15.201972 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6937 20:15:15.204948 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6938 20:15:15.208505 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6939 20:15:15.215059 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6940 20:15:15.218289 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6941 20:15:15.221616 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6942 20:15:15.224812 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6943 20:15:15.231832 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6944 20:15:15.235005 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6945 20:15:15.238303 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6946 20:15:15.241682 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6947 20:15:15.244901 ==
6948 20:15:15.248355 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 20:15:15.251453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 20:15:15.251884 ==
6951 20:15:15.252220 DQS Delay:
6952 20:15:15.254829 DQS0 = 59, DQS1 = 59
6953 20:15:15.255249 DQM Delay:
6954 20:15:15.258080 DQM0 = 19, DQM1 = 12
6955 20:15:15.258501 DQ Delay:
6956 20:15:15.261402 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6957 20:15:15.264756 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6958 20:15:15.268106 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6959 20:15:15.271339 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6960 20:15:15.271760
6961 20:15:15.272089
6962 20:15:15.272396 ==
6963 20:15:15.274744 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 20:15:15.277984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 20:15:15.278408 ==
6966 20:15:15.278740
6967 20:15:15.279046
6968 20:15:15.281308 TX Vref Scan disable
6969 20:15:15.281776 == TX Byte 0 ==
6970 20:15:15.287763 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6971 20:15:15.291133 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6972 20:15:15.291555 == TX Byte 1 ==
6973 20:15:15.297747 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6974 20:15:15.301125 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6975 20:15:15.301579 ==
6976 20:15:15.304386 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 20:15:15.307769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 20:15:15.308193 ==
6979 20:15:15.308526
6980 20:15:15.308834
6981 20:15:15.310876 TX Vref Scan disable
6982 20:15:15.314452 == TX Byte 0 ==
6983 20:15:15.317715 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6984 20:15:15.321018 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6985 20:15:15.321439 == TX Byte 1 ==
6986 20:15:15.327497 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6987 20:15:15.330863 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6988 20:15:15.331282
6989 20:15:15.331611 [DATLAT]
6990 20:15:15.334126 Freq=400, CH1 RK1
6991 20:15:15.334548
6992 20:15:15.334878 DATLAT Default: 0xe
6993 20:15:15.337742 0, 0xFFFF, sum = 0
6994 20:15:15.338171 1, 0xFFFF, sum = 0
6995 20:15:15.340870 2, 0xFFFF, sum = 0
6996 20:15:15.341294 3, 0xFFFF, sum = 0
6997 20:15:15.343888 4, 0xFFFF, sum = 0
6998 20:15:15.347263 5, 0xFFFF, sum = 0
6999 20:15:15.347783 6, 0xFFFF, sum = 0
7000 20:15:15.350741 7, 0xFFFF, sum = 0
7001 20:15:15.351169 8, 0xFFFF, sum = 0
7002 20:15:15.353641 9, 0xFFFF, sum = 0
7003 20:15:15.354247 10, 0xFFFF, sum = 0
7004 20:15:15.357263 11, 0xFFFF, sum = 0
7005 20:15:15.357717 12, 0xFFFF, sum = 0
7006 20:15:15.360360 13, 0x0, sum = 1
7007 20:15:15.360838 14, 0x0, sum = 2
7008 20:15:15.363984 15, 0x0, sum = 3
7009 20:15:15.364408 16, 0x0, sum = 4
7010 20:15:15.367034 best_step = 14
7011 20:15:15.367453
7012 20:15:15.367788 ==
7013 20:15:15.370447 Dram Type= 6, Freq= 0, CH_1, rank 1
7014 20:15:15.373812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7015 20:15:15.374432 ==
7016 20:15:15.374793 RX Vref Scan: 0
7017 20:15:15.377123
7018 20:15:15.377729 RX Vref 0 -> 0, step: 1
7019 20:15:15.378206
7020 20:15:15.380450 RX Delay -359 -> 252, step: 8
7021 20:15:15.388011 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7022 20:15:15.391335 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7023 20:15:15.394509 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7024 20:15:15.400964 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7025 20:15:15.404426 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7026 20:15:15.407873 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7027 20:15:15.411229 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7028 20:15:15.417751 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7029 20:15:15.420871 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7030 20:15:15.424323 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
7031 20:15:15.427550 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7032 20:15:15.434004 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7033 20:15:15.437408 iDelay=217, Bit 12, Center -44 (-295 ~ 208) 504
7034 20:15:15.440851 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7035 20:15:15.444389 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7036 20:15:15.450876 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7037 20:15:15.451343 ==
7038 20:15:15.454115 Dram Type= 6, Freq= 0, CH_1, rank 1
7039 20:15:15.457539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7040 20:15:15.457992 ==
7041 20:15:15.458321 DQS Delay:
7042 20:15:15.460454 DQS0 = 60, DQS1 = 64
7043 20:15:15.460894 DQM Delay:
7044 20:15:15.463960 DQM0 = 13, DQM1 = 11
7045 20:15:15.464413 DQ Delay:
7046 20:15:15.467442 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7047 20:15:15.470771 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7048 20:15:15.473880 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7049 20:15:15.477131 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7050 20:15:15.477627
7051 20:15:15.477992
7052 20:15:15.483767 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7053 20:15:15.487203 CH1 RK1: MR19=C0C, MR18=7CAC
7054 20:15:15.493752 CH1_RK1: MR19=0xC0C, MR18=0x7CAC, DQSOSC=388, MR23=63, INC=392, DEC=261
7055 20:15:15.497068 [RxdqsGatingPostProcess] freq 400
7056 20:15:15.503672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7057 20:15:15.507212 best DQS0 dly(2T, 0.5T) = (0, 10)
7058 20:15:15.507731 best DQS1 dly(2T, 0.5T) = (0, 10)
7059 20:15:15.510236 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7060 20:15:15.513808 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7061 20:15:15.516929 best DQS0 dly(2T, 0.5T) = (0, 10)
7062 20:15:15.520355 best DQS1 dly(2T, 0.5T) = (0, 10)
7063 20:15:15.523725 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7064 20:15:15.526833 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7065 20:15:15.530435 Pre-setting of DQS Precalculation
7066 20:15:15.536873 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7067 20:15:15.543608 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7068 20:15:15.550023 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7069 20:15:15.550447
7070 20:15:15.550776
7071 20:15:15.553127 [Calibration Summary] 800 Mbps
7072 20:15:15.553209 CH 0, Rank 0
7073 20:15:15.556464 SW Impedance : PASS
7074 20:15:15.559892 DUTY Scan : NO K
7075 20:15:15.560008 ZQ Calibration : PASS
7076 20:15:15.563087 Jitter Meter : NO K
7077 20:15:15.566399 CBT Training : PASS
7078 20:15:15.566503 Write leveling : PASS
7079 20:15:15.569713 RX DQS gating : PASS
7080 20:15:15.569829 RX DQ/DQS(RDDQC) : PASS
7081 20:15:15.573087 TX DQ/DQS : PASS
7082 20:15:15.576518 RX DATLAT : PASS
7083 20:15:15.576664 RX DQ/DQS(Engine): PASS
7084 20:15:15.579886 TX OE : NO K
7085 20:15:15.580008 All Pass.
7086 20:15:15.580104
7087 20:15:15.582874 CH 0, Rank 1
7088 20:15:15.583045 SW Impedance : PASS
7089 20:15:15.586606 DUTY Scan : NO K
7090 20:15:15.589533 ZQ Calibration : PASS
7091 20:15:15.589668 Jitter Meter : NO K
7092 20:15:15.593075 CBT Training : PASS
7093 20:15:15.596370 Write leveling : NO K
7094 20:15:15.596451 RX DQS gating : PASS
7095 20:15:15.599498 RX DQ/DQS(RDDQC) : PASS
7096 20:15:15.602762 TX DQ/DQS : PASS
7097 20:15:15.602844 RX DATLAT : PASS
7098 20:15:15.605933 RX DQ/DQS(Engine): PASS
7099 20:15:15.609424 TX OE : NO K
7100 20:15:15.609544 All Pass.
7101 20:15:15.609609
7102 20:15:15.609669 CH 1, Rank 0
7103 20:15:15.612901 SW Impedance : PASS
7104 20:15:15.616139 DUTY Scan : NO K
7105 20:15:15.616226 ZQ Calibration : PASS
7106 20:15:15.619493 Jitter Meter : NO K
7107 20:15:15.622858 CBT Training : PASS
7108 20:15:15.622961 Write leveling : PASS
7109 20:15:15.625898 RX DQS gating : PASS
7110 20:15:15.629374 RX DQ/DQS(RDDQC) : PASS
7111 20:15:15.629468 TX DQ/DQS : PASS
7112 20:15:15.632580 RX DATLAT : PASS
7113 20:15:15.632714 RX DQ/DQS(Engine): PASS
7114 20:15:15.635860 TX OE : NO K
7115 20:15:15.635980 All Pass.
7116 20:15:15.636080
7117 20:15:15.639310 CH 1, Rank 1
7118 20:15:15.639456 SW Impedance : PASS
7119 20:15:15.642805 DUTY Scan : NO K
7120 20:15:15.645845 ZQ Calibration : PASS
7121 20:15:15.645941 Jitter Meter : NO K
7122 20:15:15.649023 CBT Training : PASS
7123 20:15:15.652535 Write leveling : NO K
7124 20:15:15.652612 RX DQS gating : PASS
7125 20:15:15.655883 RX DQ/DQS(RDDQC) : PASS
7126 20:15:15.658998 TX DQ/DQS : PASS
7127 20:15:15.659069 RX DATLAT : PASS
7128 20:15:15.662518 RX DQ/DQS(Engine): PASS
7129 20:15:15.665616 TX OE : NO K
7130 20:15:15.665696 All Pass.
7131 20:15:15.665764
7132 20:15:15.665828 DramC Write-DBI off
7133 20:15:15.669122 PER_BANK_REFRESH: Hybrid Mode
7134 20:15:15.672578 TX_TRACKING: ON
7135 20:15:15.678947 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7136 20:15:15.685679 [FAST_K] Save calibration result to emmc
7137 20:15:15.688739 dramc_set_vcore_voltage set vcore to 725000
7138 20:15:15.688890 Read voltage for 1600, 0
7139 20:15:15.692092 Vio18 = 0
7140 20:15:15.692253 Vcore = 725000
7141 20:15:15.692370 Vdram = 0
7142 20:15:15.695464 Vddq = 0
7143 20:15:15.695618 Vmddr = 0
7144 20:15:15.698940 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7145 20:15:15.705607 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7146 20:15:15.708759 MEM_TYPE=3, freq_sel=13
7147 20:15:15.712293 sv_algorithm_assistance_LP4_3733
7148 20:15:15.715355 ============ PULL DRAM RESETB DOWN ============
7149 20:15:15.718718 ========== PULL DRAM RESETB DOWN end =========
7150 20:15:15.725597 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7151 20:15:15.728949 ===================================
7152 20:15:15.729427 LPDDR4 DRAM CONFIGURATION
7153 20:15:15.732050 ===================================
7154 20:15:15.735428 EX_ROW_EN[0] = 0x0
7155 20:15:15.738491 EX_ROW_EN[1] = 0x0
7156 20:15:15.739134 LP4Y_EN = 0x0
7157 20:15:15.741957 WORK_FSP = 0x1
7158 20:15:15.742427 WL = 0x5
7159 20:15:15.745421 RL = 0x5
7160 20:15:15.745900 BL = 0x2
7161 20:15:15.748478 RPST = 0x0
7162 20:15:15.748953 RD_PRE = 0x0
7163 20:15:15.751888 WR_PRE = 0x1
7164 20:15:15.752575 WR_PST = 0x1
7165 20:15:15.755152 DBI_WR = 0x0
7166 20:15:15.755654 DBI_RD = 0x0
7167 20:15:15.758571 OTF = 0x1
7168 20:15:15.761762 ===================================
7169 20:15:15.765169 ===================================
7170 20:15:15.765820 ANA top config
7171 20:15:15.768316 ===================================
7172 20:15:15.771840 DLL_ASYNC_EN = 0
7173 20:15:15.775177 ALL_SLAVE_EN = 0
7174 20:15:15.778123 NEW_RANK_MODE = 1
7175 20:15:15.778613 DLL_IDLE_MODE = 1
7176 20:15:15.781465 LP45_APHY_COMB_EN = 1
7177 20:15:15.785084 TX_ODT_DIS = 0
7178 20:15:15.788348 NEW_8X_MODE = 1
7179 20:15:15.791710 ===================================
7180 20:15:15.794887 ===================================
7181 20:15:15.795338 data_rate = 3200
7182 20:15:15.798428 CKR = 1
7183 20:15:15.801839 DQ_P2S_RATIO = 8
7184 20:15:15.805148 ===================================
7185 20:15:15.808221 CA_P2S_RATIO = 8
7186 20:15:15.811695 DQ_CA_OPEN = 0
7187 20:15:15.815151 DQ_SEMI_OPEN = 0
7188 20:15:15.815604 CA_SEMI_OPEN = 0
7189 20:15:15.818481 CA_FULL_RATE = 0
7190 20:15:15.821546 DQ_CKDIV4_EN = 0
7191 20:15:15.825019 CA_CKDIV4_EN = 0
7192 20:15:15.828217 CA_PREDIV_EN = 0
7193 20:15:15.831495 PH8_DLY = 12
7194 20:15:15.831938 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7195 20:15:15.835095 DQ_AAMCK_DIV = 4
7196 20:15:15.838238 CA_AAMCK_DIV = 4
7197 20:15:15.841309 CA_ADMCK_DIV = 4
7198 20:15:15.844869 DQ_TRACK_CA_EN = 0
7199 20:15:15.848127 CA_PICK = 1600
7200 20:15:15.851318 CA_MCKIO = 1600
7201 20:15:15.851771 MCKIO_SEMI = 0
7202 20:15:15.854617 PLL_FREQ = 3068
7203 20:15:15.858076 DQ_UI_PI_RATIO = 32
7204 20:15:15.861362 CA_UI_PI_RATIO = 0
7205 20:15:15.864614 ===================================
7206 20:15:15.867753 ===================================
7207 20:15:15.873301 memory_type:LPDDR4
7208 20:15:15.873770 GP_NUM : 10
7209 20:15:15.874466 SRAM_EN : 1
7210 20:15:15.877790 MD32_EN : 0
7211 20:15:15.881254 ===================================
7212 20:15:15.881732 [ANA_INIT] >>>>>>>>>>>>>>
7213 20:15:15.884452 <<<<<< [CONFIGURE PHASE]: ANA_TX
7214 20:15:15.887460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7215 20:15:15.890701 ===================================
7216 20:15:15.894404 data_rate = 3200,PCW = 0X7600
7217 20:15:15.897721 ===================================
7218 20:15:15.900971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7219 20:15:15.907354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7220 20:15:15.910833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7221 20:15:15.917365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7222 20:15:15.920790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7223 20:15:15.924021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7224 20:15:15.927579 [ANA_INIT] flow start
7225 20:15:15.928053 [ANA_INIT] PLL >>>>>>>>
7226 20:15:15.930968 [ANA_INIT] PLL <<<<<<<<
7227 20:15:15.934286 [ANA_INIT] MIDPI >>>>>>>>
7228 20:15:15.934708 [ANA_INIT] MIDPI <<<<<<<<
7229 20:15:15.937270 [ANA_INIT] DLL >>>>>>>>
7230 20:15:15.940683 [ANA_INIT] DLL <<<<<<<<
7231 20:15:15.941101 [ANA_INIT] flow end
7232 20:15:15.947263 ============ LP4 DIFF to SE enter ============
7233 20:15:15.950684 ============ LP4 DIFF to SE exit ============
7234 20:15:15.951109 [ANA_INIT] <<<<<<<<<<<<<
7235 20:15:15.953650 [Flow] Enable top DCM control >>>>>
7236 20:15:15.957101 [Flow] Enable top DCM control <<<<<
7237 20:15:15.960578 Enable DLL master slave shuffle
7238 20:15:15.967302 ==============================================================
7239 20:15:15.970643 Gating Mode config
7240 20:15:15.973846 ==============================================================
7241 20:15:15.977234 Config description:
7242 20:15:15.987132 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7243 20:15:15.993957 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7244 20:15:15.996827 SELPH_MODE 0: By rank 1: By Phase
7245 20:15:16.003749 ==============================================================
7246 20:15:16.007154 GAT_TRACK_EN = 1
7247 20:15:16.010133 RX_GATING_MODE = 2
7248 20:15:16.013694 RX_GATING_TRACK_MODE = 2
7249 20:15:16.014116 SELPH_MODE = 1
7250 20:15:16.017020 PICG_EARLY_EN = 1
7251 20:15:16.020122 VALID_LAT_VALUE = 1
7252 20:15:16.026866 ==============================================================
7253 20:15:16.030179 Enter into Gating configuration >>>>
7254 20:15:16.033511 Exit from Gating configuration <<<<
7255 20:15:16.036901 Enter into DVFS_PRE_config >>>>>
7256 20:15:16.046799 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7257 20:15:16.049821 Exit from DVFS_PRE_config <<<<<
7258 20:15:16.053356 Enter into PICG configuration >>>>
7259 20:15:16.056682 Exit from PICG configuration <<<<
7260 20:15:16.060083 [RX_INPUT] configuration >>>>>
7261 20:15:16.063341 [RX_INPUT] configuration <<<<<
7262 20:15:16.066697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7263 20:15:16.073393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7264 20:15:16.079722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7265 20:15:16.086061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7266 20:15:16.092957 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7267 20:15:16.096361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7268 20:15:16.102726 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7269 20:15:16.106125 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7270 20:15:16.109708 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7271 20:15:16.112642 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7272 20:15:16.119293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7273 20:15:16.122570 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7274 20:15:16.126050 ===================================
7275 20:15:16.129182 LPDDR4 DRAM CONFIGURATION
7276 20:15:16.132733 ===================================
7277 20:15:16.133153 EX_ROW_EN[0] = 0x0
7278 20:15:16.136070 EX_ROW_EN[1] = 0x0
7279 20:15:16.136488 LP4Y_EN = 0x0
7280 20:15:16.139235 WORK_FSP = 0x1
7281 20:15:16.139837 WL = 0x5
7282 20:15:16.142532 RL = 0x5
7283 20:15:16.142953 BL = 0x2
7284 20:15:16.145842 RPST = 0x0
7285 20:15:16.146261 RD_PRE = 0x0
7286 20:15:16.149142 WR_PRE = 0x1
7287 20:15:16.152597 WR_PST = 0x1
7288 20:15:16.153016 DBI_WR = 0x0
7289 20:15:16.155910 DBI_RD = 0x0
7290 20:15:16.156398 OTF = 0x1
7291 20:15:16.158959 ===================================
7292 20:15:16.162594 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7293 20:15:16.165699 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7294 20:15:16.172339 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7295 20:15:16.175763 ===================================
7296 20:15:16.178717 LPDDR4 DRAM CONFIGURATION
7297 20:15:16.182074 ===================================
7298 20:15:16.182495 EX_ROW_EN[0] = 0x10
7299 20:15:16.185389 EX_ROW_EN[1] = 0x0
7300 20:15:16.185953 LP4Y_EN = 0x0
7301 20:15:16.188871 WORK_FSP = 0x1
7302 20:15:16.189373 WL = 0x5
7303 20:15:16.192187 RL = 0x5
7304 20:15:16.192686 BL = 0x2
7305 20:15:16.195713 RPST = 0x0
7306 20:15:16.196233 RD_PRE = 0x0
7307 20:15:16.198734 WR_PRE = 0x1
7308 20:15:16.199211 WR_PST = 0x1
7309 20:15:16.202081 DBI_WR = 0x0
7310 20:15:16.205828 DBI_RD = 0x0
7311 20:15:16.206420 OTF = 0x1
7312 20:15:16.208756 ===================================
7313 20:15:16.215275 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7314 20:15:16.215807 ==
7315 20:15:16.218746 Dram Type= 6, Freq= 0, CH_0, rank 0
7316 20:15:16.222236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 20:15:16.222732 ==
7318 20:15:16.225206 [Duty_Offset_Calibration]
7319 20:15:16.225733 B0:2 B1:0 CA:3
7320 20:15:16.228761
7321 20:15:16.229234 [DutyScan_Calibration_Flow] k_type=0
7322 20:15:16.240135
7323 20:15:16.240683 ==CLK 0==
7324 20:15:16.243112 Final CLK duty delay cell = 0
7325 20:15:16.246530 [0] MAX Duty = 5031%(X100), DQS PI = 12
7326 20:15:16.249715 [0] MIN Duty = 4875%(X100), DQS PI = 54
7327 20:15:16.253072 [0] AVG Duty = 4953%(X100)
7328 20:15:16.253525
7329 20:15:16.256423 CH0 CLK Duty spec in!! Max-Min= 156%
7330 20:15:16.259741 [DutyScan_Calibration_Flow] ====Done====
7331 20:15:16.260163
7332 20:15:16.263009 [DutyScan_Calibration_Flow] k_type=1
7333 20:15:16.279670
7334 20:15:16.280086 ==DQS 0 ==
7335 20:15:16.283158 Final DQS duty delay cell = 0
7336 20:15:16.286148 [0] MAX Duty = 5094%(X100), DQS PI = 12
7337 20:15:16.289639 [0] MIN Duty = 4875%(X100), DQS PI = 50
7338 20:15:16.293121 [0] AVG Duty = 4984%(X100)
7339 20:15:16.293600
7340 20:15:16.293950 ==DQS 1 ==
7341 20:15:16.296490 Final DQS duty delay cell = 0
7342 20:15:16.299702 [0] MAX Duty = 5156%(X100), DQS PI = 32
7343 20:15:16.302735 [0] MIN Duty = 5062%(X100), DQS PI = 8
7344 20:15:16.306094 [0] AVG Duty = 5109%(X100)
7345 20:15:16.306517
7346 20:15:16.309541 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7347 20:15:16.309965
7348 20:15:16.312887 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7349 20:15:16.316280 [DutyScan_Calibration_Flow] ====Done====
7350 20:15:16.316701
7351 20:15:16.319562 [DutyScan_Calibration_Flow] k_type=3
7352 20:15:16.337605
7353 20:15:16.338026 ==DQM 0 ==
7354 20:15:16.340560 Final DQM duty delay cell = 0
7355 20:15:16.343991 [0] MAX Duty = 5156%(X100), DQS PI = 14
7356 20:15:16.347441 [0] MIN Duty = 4875%(X100), DQS PI = 0
7357 20:15:16.350914 [0] AVG Duty = 5015%(X100)
7358 20:15:16.351332
7359 20:15:16.351662 ==DQM 1 ==
7360 20:15:16.353904 Final DQM duty delay cell = 4
7361 20:15:16.357319 [4] MAX Duty = 5187%(X100), DQS PI = 60
7362 20:15:16.360364 [4] MIN Duty = 5031%(X100), DQS PI = 12
7363 20:15:16.363892 [4] AVG Duty = 5109%(X100)
7364 20:15:16.364311
7365 20:15:16.367180 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7366 20:15:16.367600
7367 20:15:16.370653 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7368 20:15:16.373796 [DutyScan_Calibration_Flow] ====Done====
7369 20:15:16.374303
7370 20:15:16.377283 [DutyScan_Calibration_Flow] k_type=2
7371 20:15:16.393730
7372 20:15:16.394158 ==DQ 0 ==
7373 20:15:16.396782 Final DQ duty delay cell = -4
7374 20:15:16.400122 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7375 20:15:16.403760 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7376 20:15:16.406827 [-4] AVG Duty = 4938%(X100)
7377 20:15:16.407326
7378 20:15:16.407752 ==DQ 1 ==
7379 20:15:16.410148 Final DQ duty delay cell = 0
7380 20:15:16.413359 [0] MAX Duty = 5156%(X100), DQS PI = 60
7381 20:15:16.416732 [0] MIN Duty = 5000%(X100), DQS PI = 16
7382 20:15:16.420230 [0] AVG Duty = 5078%(X100)
7383 20:15:16.420712
7384 20:15:16.423521 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7385 20:15:16.424022
7386 20:15:16.426801 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7387 20:15:16.430155 [DutyScan_Calibration_Flow] ====Done====
7388 20:15:16.430660 ==
7389 20:15:16.433614 Dram Type= 6, Freq= 0, CH_1, rank 0
7390 20:15:16.436612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7391 20:15:16.437085 ==
7392 20:15:16.439962 [Duty_Offset_Calibration]
7393 20:15:16.440499 B0:1 B1:-2 CA:0
7394 20:15:16.440904
7395 20:15:16.443425 [DutyScan_Calibration_Flow] k_type=0
7396 20:15:16.454198
7397 20:15:16.454688 ==CLK 0==
7398 20:15:16.457609 Final CLK duty delay cell = 0
7399 20:15:16.460475 [0] MAX Duty = 5093%(X100), DQS PI = 22
7400 20:15:16.463864 [0] MIN Duty = 4844%(X100), DQS PI = 58
7401 20:15:16.467297 [0] AVG Duty = 4968%(X100)
7402 20:15:16.467820
7403 20:15:16.470520 CH1 CLK Duty spec in!! Max-Min= 249%
7404 20:15:16.473838 [DutyScan_Calibration_Flow] ====Done====
7405 20:15:16.474319
7406 20:15:16.477266 [DutyScan_Calibration_Flow] k_type=1
7407 20:15:16.492804
7408 20:15:16.493221 ==DQS 0 ==
7409 20:15:16.496269 Final DQS duty delay cell = -4
7410 20:15:16.499781 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7411 20:15:16.502906 [-4] MIN Duty = 4844%(X100), DQS PI = 44
7412 20:15:16.506036 [-4] AVG Duty = 4906%(X100)
7413 20:15:16.506539
7414 20:15:16.506965 ==DQS 1 ==
7415 20:15:16.509385 Final DQS duty delay cell = 0
7416 20:15:16.512644 [0] MAX Duty = 5093%(X100), DQS PI = 60
7417 20:15:16.516170 [0] MIN Duty = 4844%(X100), DQS PI = 24
7418 20:15:16.519590 [0] AVG Duty = 4968%(X100)
7419 20:15:16.520081
7420 20:15:16.522511 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7421 20:15:16.522991
7422 20:15:16.525762 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7423 20:15:16.529412 [DutyScan_Calibration_Flow] ====Done====
7424 20:15:16.529938
7425 20:15:16.532446 [DutyScan_Calibration_Flow] k_type=3
7426 20:15:16.549996
7427 20:15:16.550458 ==DQM 0 ==
7428 20:15:16.553451 Final DQM duty delay cell = 0
7429 20:15:16.556586 [0] MAX Duty = 5031%(X100), DQS PI = 24
7430 20:15:16.559903 [0] MIN Duty = 4813%(X100), DQS PI = 56
7431 20:15:16.563338 [0] AVG Duty = 4922%(X100)
7432 20:15:16.563754
7433 20:15:16.564082 ==DQM 1 ==
7434 20:15:16.566734 Final DQM duty delay cell = 0
7435 20:15:16.570131 [0] MAX Duty = 5062%(X100), DQS PI = 34
7436 20:15:16.573438 [0] MIN Duty = 4875%(X100), DQS PI = 26
7437 20:15:16.576476 [0] AVG Duty = 4968%(X100)
7438 20:15:16.576947
7439 20:15:16.579834 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7440 20:15:16.580377
7441 20:15:16.583286 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7442 20:15:16.586628 [DutyScan_Calibration_Flow] ====Done====
7443 20:15:16.587182
7444 20:15:16.589770 [DutyScan_Calibration_Flow] k_type=2
7445 20:15:16.606957
7446 20:15:16.607480 ==DQ 0 ==
7447 20:15:16.610029 Final DQ duty delay cell = 0
7448 20:15:16.613429 [0] MAX Duty = 5093%(X100), DQS PI = 22
7449 20:15:16.616776 [0] MIN Duty = 4907%(X100), DQS PI = 62
7450 20:15:16.617281 [0] AVG Duty = 5000%(X100)
7451 20:15:16.620043
7452 20:15:16.620536 ==DQ 1 ==
7453 20:15:16.623576 Final DQ duty delay cell = 0
7454 20:15:16.626861 [0] MAX Duty = 5125%(X100), DQS PI = 34
7455 20:15:16.630288 [0] MIN Duty = 4938%(X100), DQS PI = 24
7456 20:15:16.630785 [0] AVG Duty = 5031%(X100)
7457 20:15:16.631187
7458 20:15:16.633575 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7459 20:15:16.636805
7460 20:15:16.640125 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7461 20:15:16.643445 [DutyScan_Calibration_Flow] ====Done====
7462 20:15:16.647002 nWR fixed to 30
7463 20:15:16.647481 [ModeRegInit_LP4] CH0 RK0
7464 20:15:16.650205 [ModeRegInit_LP4] CH0 RK1
7465 20:15:16.653569 [ModeRegInit_LP4] CH1 RK0
7466 20:15:16.654064 [ModeRegInit_LP4] CH1 RK1
7467 20:15:16.656638 match AC timing 5
7468 20:15:16.660213 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7469 20:15:16.666779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7470 20:15:16.669950 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7471 20:15:16.676759 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7472 20:15:16.679760 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7473 20:15:16.680206 [MiockJmeterHQA]
7474 20:15:16.680564
7475 20:15:16.683083 [DramcMiockJmeter] u1RxGatingPI = 0
7476 20:15:16.686497 0 : 4263, 4032
7477 20:15:16.686965 4 : 4255, 4029
7478 20:15:16.687371 8 : 4255, 4029
7479 20:15:16.690048 12 : 4260, 4032
7480 20:15:16.690495 16 : 4366, 4139
7481 20:15:16.693428 20 : 4255, 4030
7482 20:15:16.693918 24 : 4257, 4029
7483 20:15:16.696488 28 : 4258, 4030
7484 20:15:16.696947 32 : 4260, 4034
7485 20:15:16.700108 36 : 4257, 4029
7486 20:15:16.700557 40 : 4257, 4029
7487 20:15:16.700900 44 : 4368, 4142
7488 20:15:16.702966 48 : 4254, 4029
7489 20:15:16.703433 52 : 4260, 4032
7490 20:15:16.706468 56 : 4255, 4030
7491 20:15:16.706930 60 : 4253, 4029
7492 20:15:16.709716 64 : 4258, 4032
7493 20:15:16.710174 68 : 4360, 4138
7494 20:15:16.713295 72 : 4252, 4029
7495 20:15:16.713784 76 : 4255, 4029
7496 20:15:16.714150 80 : 4252, 4029
7497 20:15:16.716350 84 : 4258, 4032
7498 20:15:16.716798 88 : 4255, 4029
7499 20:15:16.719733 92 : 4253, 4029
7500 20:15:16.720342 96 : 4365, 4142
7501 20:15:16.723012 100 : 4253, 4029
7502 20:15:16.723532 104 : 4253, 3746
7503 20:15:16.726436 108 : 4258, 6
7504 20:15:16.726891 112 : 4253, 0
7505 20:15:16.727270 116 : 4253, 0
7506 20:15:16.729584 120 : 4258, 0
7507 20:15:16.730112 124 : 4253, 0
7508 20:15:16.733087 128 : 4253, 0
7509 20:15:16.733734 132 : 4257, 0
7510 20:15:16.734146 136 : 4253, 0
7511 20:15:16.736240 140 : 4253, 0
7512 20:15:16.736742 144 : 4252, 0
7513 20:15:16.737182 148 : 4258, 0
7514 20:15:16.739639 152 : 4363, 0
7515 20:15:16.740148 156 : 4363, 0
7516 20:15:16.742548 160 : 4250, 0
7517 20:15:16.743059 164 : 4252, 0
7518 20:15:16.743511 168 : 4363, 0
7519 20:15:16.746242 172 : 4253, 0
7520 20:15:16.746744 176 : 4253, 0
7521 20:15:16.749286 180 : 4252, 0
7522 20:15:16.749814 184 : 4363, 0
7523 20:15:16.750249 188 : 4253, 0
7524 20:15:16.752614 192 : 4252, 0
7525 20:15:16.753117 196 : 4364, 0
7526 20:15:16.756096 200 : 4253, 0
7527 20:15:16.756570 204 : 4252, 0
7528 20:15:16.757083 208 : 4252, 0
7529 20:15:16.759509 212 : 4253, 0
7530 20:15:16.760046 216 : 4253, 0
7531 20:15:16.760392 220 : 4255, 0
7532 20:15:16.762757 224 : 4253, 0
7533 20:15:16.763182 228 : 4363, 0
7534 20:15:16.766112 232 : 4366, 0
7535 20:15:16.766670 236 : 4363, 827
7536 20:15:16.769587 240 : 4255, 4030
7537 20:15:16.770017 244 : 4253, 4029
7538 20:15:16.770357 248 : 4253, 4029
7539 20:15:16.772683 252 : 4255, 4029
7540 20:15:16.773154 256 : 4252, 4030
7541 20:15:16.775880 260 : 4363, 4140
7542 20:15:16.776283 264 : 4252, 4029
7543 20:15:16.778731 268 : 4363, 4140
7544 20:15:16.778819 272 : 4255, 4029
7545 20:15:16.782360 276 : 4257, 4032
7546 20:15:16.782441 280 : 4255, 4030
7547 20:15:16.785402 284 : 4255, 4029
7548 20:15:16.785529 288 : 4253, 4029
7549 20:15:16.788877 292 : 4252, 4029
7550 20:15:16.788965 296 : 4253, 4029
7551 20:15:16.792239 300 : 4255, 4029
7552 20:15:16.792327 304 : 4255, 4029
7553 20:15:16.795576 308 : 4363, 4140
7554 20:15:16.795656 312 : 4253, 4029
7555 20:15:16.795720 316 : 4252, 4029
7556 20:15:16.798758 320 : 4250, 4027
7557 20:15:16.798850 324 : 4366, 4140
7558 20:15:16.802311 328 : 4252, 4029
7559 20:15:16.802392 332 : 4253, 4029
7560 20:15:16.805354 336 : 4255, 4029
7561 20:15:16.805470 340 : 4255, 4029
7562 20:15:16.808687 344 : 4252, 4030
7563 20:15:16.808769 348 : 4252, 4029
7564 20:15:16.811829 352 : 4255, 4028
7565 20:15:16.811910 356 : 4255, 2845
7566 20:15:16.815207 360 : 4361, 6
7567 20:15:16.815288
7568 20:15:16.815360 MIOCK jitter meter ch=0
7569 20:15:16.815419
7570 20:15:16.818487 1T = (360-108) = 252 dly cells
7571 20:15:16.825115 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7572 20:15:16.825196 ==
7573 20:15:16.828407 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 20:15:16.831602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 20:15:16.831675 ==
7576 20:15:16.838336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7577 20:15:16.841730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7578 20:15:16.844946 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7579 20:15:16.851232 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7580 20:15:16.861283 [CA 0] Center 44 (14~75) winsize 62
7581 20:15:16.864717 [CA 1] Center 43 (13~74) winsize 62
7582 20:15:16.867976 [CA 2] Center 40 (11~69) winsize 59
7583 20:15:16.871228 [CA 3] Center 39 (10~68) winsize 59
7584 20:15:16.874456 [CA 4] Center 37 (8~67) winsize 60
7585 20:15:16.877870 [CA 5] Center 37 (7~67) winsize 61
7586 20:15:16.877950
7587 20:15:16.881327 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7588 20:15:16.881397
7589 20:15:16.887846 [CATrainingPosCal] consider 1 rank data
7590 20:15:16.887920 u2DelayCellTimex100 = 258/100 ps
7591 20:15:16.894420 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7592 20:15:16.897572 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7593 20:15:16.900853 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7594 20:15:16.904152 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7595 20:15:16.907433 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7596 20:15:16.910833 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7597 20:15:16.910935
7598 20:15:16.914044 CA PerBit enable=1, Macro0, CA PI delay=37
7599 20:15:16.914119
7600 20:15:16.917464 [CBTSetCACLKResult] CA Dly = 37
7601 20:15:16.921054 CS Dly: 11 (0~42)
7602 20:15:16.924396 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7603 20:15:16.927389 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7604 20:15:16.927483 ==
7605 20:15:16.930956 Dram Type= 6, Freq= 0, CH_0, rank 1
7606 20:15:16.937463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 20:15:16.937600 ==
7608 20:15:16.941102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7609 20:15:16.947736 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7610 20:15:16.950930 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7611 20:15:16.957525 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7612 20:15:16.965619 [CA 0] Center 44 (14~75) winsize 62
7613 20:15:16.968897 [CA 1] Center 43 (13~74) winsize 62
7614 20:15:16.972121 [CA 2] Center 39 (10~69) winsize 60
7615 20:15:16.975581 [CA 3] Center 39 (10~69) winsize 60
7616 20:15:16.979066 [CA 4] Center 37 (8~67) winsize 60
7617 20:15:16.981866 [CA 5] Center 37 (7~67) winsize 61
7618 20:15:16.982313
7619 20:15:16.985757 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7620 20:15:16.986169
7621 20:15:16.988889 [CATrainingPosCal] consider 2 rank data
7622 20:15:16.992279 u2DelayCellTimex100 = 258/100 ps
7623 20:15:16.998894 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7624 20:15:17.002048 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7625 20:15:17.005392 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7626 20:15:17.009077 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7627 20:15:17.012172 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7628 20:15:17.015549 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7629 20:15:17.016055
7630 20:15:17.018890 CA PerBit enable=1, Macro0, CA PI delay=37
7631 20:15:17.019390
7632 20:15:17.022113 [CBTSetCACLKResult] CA Dly = 37
7633 20:15:17.025339 CS Dly: 11 (0~43)
7634 20:15:17.028822 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7635 20:15:17.032221 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7636 20:15:17.032711
7637 20:15:17.035321 ----->DramcWriteLeveling(PI) begin...
7638 20:15:17.035812 ==
7639 20:15:17.038480 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 20:15:17.045587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 20:15:17.046055 ==
7642 20:15:17.048576 Write leveling (Byte 0): 35 => 35
7643 20:15:17.051873 Write leveling (Byte 1): 30 => 30
7644 20:15:17.052328 DramcWriteLeveling(PI) end<-----
7645 20:15:17.054994
7646 20:15:17.055436 ==
7647 20:15:17.058287 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 20:15:17.061686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 20:15:17.062142 ==
7650 20:15:17.065221 [Gating] SW mode calibration
7651 20:15:17.071866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7652 20:15:17.074937 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7653 20:15:17.081782 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 20:15:17.084845 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 20:15:17.088080 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 20:15:17.094853 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 20:15:17.098332 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7658 20:15:17.101330 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7659 20:15:17.108024 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7660 20:15:17.111245 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 20:15:17.114859 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 20:15:17.121387 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 20:15:17.124461 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 20:15:17.127787 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7665 20:15:17.134667 1 5 16 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7666 20:15:17.137855 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7667 20:15:17.141252 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7668 20:15:17.147580 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 20:15:17.150821 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 20:15:17.154365 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 20:15:17.160853 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 20:15:17.164006 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 20:15:17.167515 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7674 20:15:17.174090 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
7675 20:15:17.177277 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7676 20:15:17.180477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 20:15:17.187301 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 20:15:17.190450 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 20:15:17.193741 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 20:15:17.200565 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7681 20:15:17.203854 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7682 20:15:17.207256 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 20:15:17.213823 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7684 20:15:17.216870 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 20:15:17.220342 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 20:15:17.227176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 20:15:17.230177 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 20:15:17.233537 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 20:15:17.240108 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 20:15:17.243420 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 20:15:17.246804 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 20:15:17.253358 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 20:15:17.256905 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 20:15:17.260146 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 20:15:17.266740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 20:15:17.270000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7697 20:15:17.273274 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7698 20:15:17.279978 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7699 20:15:17.280403 Total UI for P1: 0, mck2ui 16
7700 20:15:17.286394 best dqsien dly found for B0: ( 1, 9, 14)
7701 20:15:17.289621 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7702 20:15:17.293011 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7703 20:15:17.296457 Total UI for P1: 0, mck2ui 16
7704 20:15:17.299870 best dqsien dly found for B1: ( 1, 9, 24)
7705 20:15:17.303126 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7706 20:15:17.306316 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7707 20:15:17.306734
7708 20:15:17.309686 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7709 20:15:17.316873 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7710 20:15:17.317292 [Gating] SW calibration Done
7711 20:15:17.319797 ==
7712 20:15:17.320218 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 20:15:17.326490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 20:15:17.327003 ==
7715 20:15:17.327339 RX Vref Scan: 0
7716 20:15:17.327650
7717 20:15:17.329725 RX Vref 0 -> 0, step: 1
7718 20:15:17.330147
7719 20:15:17.332839 RX Delay 0 -> 252, step: 8
7720 20:15:17.336280 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7721 20:15:17.339780 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7722 20:15:17.342793 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7723 20:15:17.349462 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7724 20:15:17.352695 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7725 20:15:17.356147 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7726 20:15:17.359461 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7727 20:15:17.362705 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7728 20:15:17.369438 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7729 20:15:17.372937 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7730 20:15:17.375861 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7731 20:15:17.379112 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7732 20:15:17.382632 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7733 20:15:17.389084 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7734 20:15:17.392319 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7735 20:15:17.396066 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7736 20:15:17.396492 ==
7737 20:15:17.399201 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 20:15:17.402293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 20:15:17.406087 ==
7740 20:15:17.406512 DQS Delay:
7741 20:15:17.406842 DQS0 = 0, DQS1 = 0
7742 20:15:17.409080 DQM Delay:
7743 20:15:17.409541 DQM0 = 127, DQM1 = 124
7744 20:15:17.412217 DQ Delay:
7745 20:15:17.415904 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7746 20:15:17.419274 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7747 20:15:17.422096 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7748 20:15:17.425590 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7749 20:15:17.426082
7750 20:15:17.426487
7751 20:15:17.426875 ==
7752 20:15:17.429075 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 20:15:17.432063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 20:15:17.432578 ==
7755 20:15:17.435232
7756 20:15:17.435753
7757 20:15:17.436184 TX Vref Scan disable
7758 20:15:17.438739 == TX Byte 0 ==
7759 20:15:17.442104 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7760 20:15:17.445298 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7761 20:15:17.448854 == TX Byte 1 ==
7762 20:15:17.451992 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7763 20:15:17.455324 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7764 20:15:17.455798 ==
7765 20:15:17.458701 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 20:15:17.465409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 20:15:17.465894 ==
7768 20:15:17.477624
7769 20:15:17.480657 TX Vref early break, caculate TX vref
7770 20:15:17.484030 TX Vref=16, minBit 4, minWin=22, winSum=366
7771 20:15:17.487357 TX Vref=18, minBit 0, minWin=23, winSum=375
7772 20:15:17.490720 TX Vref=20, minBit 0, minWin=23, winSum=387
7773 20:15:17.494217 TX Vref=22, minBit 0, minWin=24, winSum=395
7774 20:15:17.497517 TX Vref=24, minBit 7, minWin=24, winSum=403
7775 20:15:17.503996 TX Vref=26, minBit 0, minWin=25, winSum=411
7776 20:15:17.507336 TX Vref=28, minBit 4, minWin=25, winSum=416
7777 20:15:17.510762 TX Vref=30, minBit 8, minWin=24, winSum=408
7778 20:15:17.514049 TX Vref=32, minBit 4, minWin=24, winSum=399
7779 20:15:17.517211 TX Vref=34, minBit 8, minWin=23, winSum=390
7780 20:15:17.523972 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7781 20:15:17.524551
7782 20:15:17.527351 Final TX Range 0 Vref 28
7783 20:15:17.528071
7784 20:15:17.528434 ==
7785 20:15:17.530560 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 20:15:17.533750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 20:15:17.534167 ==
7788 20:15:17.534495
7789 20:15:17.534797
7790 20:15:17.537129 TX Vref Scan disable
7791 20:15:17.543838 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7792 20:15:17.544254 == TX Byte 0 ==
7793 20:15:17.546900 u2DelayCellOfst[0]=15 cells (4 PI)
7794 20:15:17.550270 u2DelayCellOfst[1]=18 cells (5 PI)
7795 20:15:17.553336 u2DelayCellOfst[2]=11 cells (3 PI)
7796 20:15:17.556795 u2DelayCellOfst[3]=15 cells (4 PI)
7797 20:15:17.560305 u2DelayCellOfst[4]=11 cells (3 PI)
7798 20:15:17.563338 u2DelayCellOfst[5]=0 cells (0 PI)
7799 20:15:17.566857 u2DelayCellOfst[6]=22 cells (6 PI)
7800 20:15:17.569917 u2DelayCellOfst[7]=18 cells (5 PI)
7801 20:15:17.573439 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7802 20:15:17.576430 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7803 20:15:17.579812 == TX Byte 1 ==
7804 20:15:17.583183 u2DelayCellOfst[8]=0 cells (0 PI)
7805 20:15:17.586360 u2DelayCellOfst[9]=3 cells (1 PI)
7806 20:15:17.586775 u2DelayCellOfst[10]=7 cells (2 PI)
7807 20:15:17.589985 u2DelayCellOfst[11]=3 cells (1 PI)
7808 20:15:17.593174 u2DelayCellOfst[12]=11 cells (3 PI)
7809 20:15:17.596438 u2DelayCellOfst[13]=11 cells (3 PI)
7810 20:15:17.599824 u2DelayCellOfst[14]=18 cells (5 PI)
7811 20:15:17.602896 u2DelayCellOfst[15]=11 cells (3 PI)
7812 20:15:17.609510 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7813 20:15:17.612863 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7814 20:15:17.613332 DramC Write-DBI on
7815 20:15:17.613830 ==
7816 20:15:17.616476 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 20:15:17.623006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 20:15:17.623446 ==
7819 20:15:17.623886
7820 20:15:17.624301
7821 20:15:17.626187 TX Vref Scan disable
7822 20:15:17.626689 == TX Byte 0 ==
7823 20:15:17.632522 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7824 20:15:17.632957 == TX Byte 1 ==
7825 20:15:17.635738 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7826 20:15:17.639547 DramC Write-DBI off
7827 20:15:17.639979
7828 20:15:17.640420 [DATLAT]
7829 20:15:17.642739 Freq=1600, CH0 RK0
7830 20:15:17.643174
7831 20:15:17.643615 DATLAT Default: 0xf
7832 20:15:17.645983 0, 0xFFFF, sum = 0
7833 20:15:17.646542 1, 0xFFFF, sum = 0
7834 20:15:17.649178 2, 0xFFFF, sum = 0
7835 20:15:17.649638 3, 0xFFFF, sum = 0
7836 20:15:17.652541 4, 0xFFFF, sum = 0
7837 20:15:17.652967 5, 0xFFFF, sum = 0
7838 20:15:17.655900 6, 0xFFFF, sum = 0
7839 20:15:17.656328 7, 0xFFFF, sum = 0
7840 20:15:17.658960 8, 0xFFFF, sum = 0
7841 20:15:17.659388 9, 0xFFFF, sum = 0
7842 20:15:17.662561 10, 0xFFFF, sum = 0
7843 20:15:17.665740 11, 0xFFFF, sum = 0
7844 20:15:17.666206 12, 0xFFFF, sum = 0
7845 20:15:17.669287 13, 0xEFFF, sum = 0
7846 20:15:17.669886 14, 0x0, sum = 1
7847 20:15:17.672340 15, 0x0, sum = 2
7848 20:15:17.672823 16, 0x0, sum = 3
7849 20:15:17.675910 17, 0x0, sum = 4
7850 20:15:17.676510 best_step = 15
7851 20:15:17.676997
7852 20:15:17.677435 ==
7853 20:15:17.679113 Dram Type= 6, Freq= 0, CH_0, rank 0
7854 20:15:17.682668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7855 20:15:17.683134 ==
7856 20:15:17.685587 RX Vref Scan: 1
7857 20:15:17.686054
7858 20:15:17.688770 Set Vref Range= 24 -> 127
7859 20:15:17.689268
7860 20:15:17.689778 RX Vref 24 -> 127, step: 1
7861 20:15:17.690110
7862 20:15:17.692221 RX Delay 11 -> 252, step: 4
7863 20:15:17.692782
7864 20:15:17.695511 Set Vref, RX VrefLevel [Byte0]: 24
7865 20:15:17.699035 [Byte1]: 24
7866 20:15:17.702412
7867 20:15:17.702881 Set Vref, RX VrefLevel [Byte0]: 25
7868 20:15:17.705700 [Byte1]: 25
7869 20:15:17.709901
7870 20:15:17.710470 Set Vref, RX VrefLevel [Byte0]: 26
7871 20:15:17.713094 [Byte1]: 26
7872 20:15:17.717471
7873 20:15:17.717951 Set Vref, RX VrefLevel [Byte0]: 27
7874 20:15:17.720808 [Byte1]: 27
7875 20:15:17.725056
7876 20:15:17.725793 Set Vref, RX VrefLevel [Byte0]: 28
7877 20:15:17.728329 [Byte1]: 28
7878 20:15:17.732692
7879 20:15:17.733212 Set Vref, RX VrefLevel [Byte0]: 29
7880 20:15:17.736014 [Byte1]: 29
7881 20:15:17.740407
7882 20:15:17.740823 Set Vref, RX VrefLevel [Byte0]: 30
7883 20:15:17.743581 [Byte1]: 30
7884 20:15:17.747893
7885 20:15:17.748314 Set Vref, RX VrefLevel [Byte0]: 31
7886 20:15:17.751186 [Byte1]: 31
7887 20:15:17.755471
7888 20:15:17.755903 Set Vref, RX VrefLevel [Byte0]: 32
7889 20:15:17.758671 [Byte1]: 32
7890 20:15:17.762964
7891 20:15:17.763508 Set Vref, RX VrefLevel [Byte0]: 33
7892 20:15:17.766384 [Byte1]: 33
7893 20:15:17.770778
7894 20:15:17.771189 Set Vref, RX VrefLevel [Byte0]: 34
7895 20:15:17.773913 [Byte1]: 34
7896 20:15:17.778107
7897 20:15:17.778514 Set Vref, RX VrefLevel [Byte0]: 35
7898 20:15:17.781539 [Byte1]: 35
7899 20:15:17.785756
7900 20:15:17.785836 Set Vref, RX VrefLevel [Byte0]: 36
7901 20:15:17.788807 [Byte1]: 36
7902 20:15:17.793246
7903 20:15:17.793351 Set Vref, RX VrefLevel [Byte0]: 37
7904 20:15:17.796431 [Byte1]: 37
7905 20:15:17.800718
7906 20:15:17.800798 Set Vref, RX VrefLevel [Byte0]: 38
7907 20:15:17.804303 [Byte1]: 38
7908 20:15:17.808529
7909 20:15:17.808608 Set Vref, RX VrefLevel [Byte0]: 39
7910 20:15:17.811858 [Byte1]: 39
7911 20:15:17.816072
7912 20:15:17.816160 Set Vref, RX VrefLevel [Byte0]: 40
7913 20:15:17.819309 [Byte1]: 40
7914 20:15:17.823801
7915 20:15:17.823886 Set Vref, RX VrefLevel [Byte0]: 41
7916 20:15:17.827097 [Byte1]: 41
7917 20:15:17.831185
7918 20:15:17.831265 Set Vref, RX VrefLevel [Byte0]: 42
7919 20:15:17.834658 [Byte1]: 42
7920 20:15:17.838613
7921 20:15:17.838694 Set Vref, RX VrefLevel [Byte0]: 43
7922 20:15:17.842173 [Byte1]: 43
7923 20:15:17.846511
7924 20:15:17.846597 Set Vref, RX VrefLevel [Byte0]: 44
7925 20:15:17.849779 [Byte1]: 44
7926 20:15:17.854204
7927 20:15:17.854283 Set Vref, RX VrefLevel [Byte0]: 45
7928 20:15:17.857486 [Byte1]: 45
7929 20:15:17.861739
7930 20:15:17.861819 Set Vref, RX VrefLevel [Byte0]: 46
7931 20:15:17.865127 [Byte1]: 46
7932 20:15:17.869160
7933 20:15:17.869265 Set Vref, RX VrefLevel [Byte0]: 47
7934 20:15:17.872621 [Byte1]: 47
7935 20:15:17.876994
7936 20:15:17.877155 Set Vref, RX VrefLevel [Byte0]: 48
7937 20:15:17.880265 [Byte1]: 48
7938 20:15:17.884679
7939 20:15:17.884759 Set Vref, RX VrefLevel [Byte0]: 49
7940 20:15:17.887766 [Byte1]: 49
7941 20:15:17.892003
7942 20:15:17.892083 Set Vref, RX VrefLevel [Byte0]: 50
7943 20:15:17.895495 [Byte1]: 50
7944 20:15:17.899859
7945 20:15:17.899938 Set Vref, RX VrefLevel [Byte0]: 51
7946 20:15:17.902874 [Byte1]: 51
7947 20:15:17.907408
7948 20:15:17.907488 Set Vref, RX VrefLevel [Byte0]: 52
7949 20:15:17.910636 [Byte1]: 52
7950 20:15:17.915073
7951 20:15:17.915153 Set Vref, RX VrefLevel [Byte0]: 53
7952 20:15:17.918396 [Byte1]: 53
7953 20:15:17.922654
7954 20:15:17.922734 Set Vref, RX VrefLevel [Byte0]: 54
7955 20:15:17.926067 [Byte1]: 54
7956 20:15:17.930183
7957 20:15:17.930263 Set Vref, RX VrefLevel [Byte0]: 55
7958 20:15:17.933687 [Byte1]: 55
7959 20:15:17.937855
7960 20:15:17.937935 Set Vref, RX VrefLevel [Byte0]: 56
7961 20:15:17.940996 [Byte1]: 56
7962 20:15:17.945434
7963 20:15:17.945541 Set Vref, RX VrefLevel [Byte0]: 57
7964 20:15:17.948864 [Byte1]: 57
7965 20:15:17.953087
7966 20:15:17.953202 Set Vref, RX VrefLevel [Byte0]: 58
7967 20:15:17.956562 [Byte1]: 58
7968 20:15:17.960632
7969 20:15:17.960712 Set Vref, RX VrefLevel [Byte0]: 59
7970 20:15:17.964273 [Byte1]: 59
7971 20:15:17.968400
7972 20:15:17.968480 Set Vref, RX VrefLevel [Byte0]: 60
7973 20:15:17.971713 [Byte1]: 60
7974 20:15:17.975878
7975 20:15:17.975957 Set Vref, RX VrefLevel [Byte0]: 61
7976 20:15:17.979223 [Byte1]: 61
7977 20:15:17.983446
7978 20:15:17.983526 Set Vref, RX VrefLevel [Byte0]: 62
7979 20:15:17.986831 [Byte1]: 62
7980 20:15:17.990935
7981 20:15:17.991021 Set Vref, RX VrefLevel [Byte0]: 63
7982 20:15:17.994504 [Byte1]: 63
7983 20:15:17.998628
7984 20:15:17.998707 Set Vref, RX VrefLevel [Byte0]: 64
7985 20:15:18.002091 [Byte1]: 64
7986 20:15:18.006467
7987 20:15:18.006547 Set Vref, RX VrefLevel [Byte0]: 65
7988 20:15:18.009450 [Byte1]: 65
7989 20:15:18.014166
7990 20:15:18.014262 Set Vref, RX VrefLevel [Byte0]: 66
7991 20:15:18.017426 [Byte1]: 66
7992 20:15:18.021388
7993 20:15:18.021500 Set Vref, RX VrefLevel [Byte0]: 67
7994 20:15:18.025008 [Byte1]: 67
7995 20:15:18.029375
7996 20:15:18.029454 Set Vref, RX VrefLevel [Byte0]: 68
7997 20:15:18.032480 [Byte1]: 68
7998 20:15:18.036939
7999 20:15:18.037019 Set Vref, RX VrefLevel [Byte0]: 69
8000 20:15:18.039940 [Byte1]: 69
8001 20:15:18.044456
8002 20:15:18.044535 Set Vref, RX VrefLevel [Byte0]: 70
8003 20:15:18.047640 [Byte1]: 70
8004 20:15:18.051969
8005 20:15:18.052048 Set Vref, RX VrefLevel [Byte0]: 71
8006 20:15:18.055136 [Byte1]: 71
8007 20:15:18.059678
8008 20:15:18.059757 Set Vref, RX VrefLevel [Byte0]: 72
8009 20:15:18.062975 [Byte1]: 72
8010 20:15:18.067481
8011 20:15:18.067567 Set Vref, RX VrefLevel [Byte0]: 73
8012 20:15:18.070500 [Byte1]: 73
8013 20:15:18.074675
8014 20:15:18.074754 Set Vref, RX VrefLevel [Byte0]: 74
8015 20:15:18.078216 [Byte1]: 74
8016 20:15:18.082559
8017 20:15:18.082638 Set Vref, RX VrefLevel [Byte0]: 75
8018 20:15:18.085497 [Byte1]: 75
8019 20:15:18.090112
8020 20:15:18.090192 Set Vref, RX VrefLevel [Byte0]: 76
8021 20:15:18.093429 [Byte1]: 76
8022 20:15:18.097784
8023 20:15:18.097890 Final RX Vref Byte 0 = 66 to rank0
8024 20:15:18.100778 Final RX Vref Byte 1 = 59 to rank0
8025 20:15:18.104310 Final RX Vref Byte 0 = 66 to rank1
8026 20:15:18.107543 Final RX Vref Byte 1 = 59 to rank1==
8027 20:15:18.110862 Dram Type= 6, Freq= 0, CH_0, rank 0
8028 20:15:18.117431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 20:15:18.117562 ==
8030 20:15:18.117627 DQS Delay:
8031 20:15:18.120824 DQS0 = 0, DQS1 = 0
8032 20:15:18.120904 DQM Delay:
8033 20:15:18.120967 DQM0 = 126, DQM1 = 120
8034 20:15:18.124146 DQ Delay:
8035 20:15:18.127496 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8036 20:15:18.131178 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8037 20:15:18.134020 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8038 20:15:18.137674 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
8039 20:15:18.137758
8040 20:15:18.137821
8041 20:15:18.137879
8042 20:15:18.140822 [DramC_TX_OE_Calibration] TA2
8043 20:15:18.144406 Original DQ_B0 (3 6) =30, OEN = 27
8044 20:15:18.147496 Original DQ_B1 (3 6) =30, OEN = 27
8045 20:15:18.150835 24, 0x0, End_B0=24 End_B1=24
8046 20:15:18.150943 25, 0x0, End_B0=25 End_B1=25
8047 20:15:18.153957 26, 0x0, End_B0=26 End_B1=26
8048 20:15:18.157616 27, 0x0, End_B0=27 End_B1=27
8049 20:15:18.160693 28, 0x0, End_B0=28 End_B1=28
8050 20:15:18.164044 29, 0x0, End_B0=29 End_B1=29
8051 20:15:18.164125 30, 0x0, End_B0=30 End_B1=30
8052 20:15:18.167230 31, 0x4141, End_B0=30 End_B1=30
8053 20:15:18.170555 Byte0 end_step=30 best_step=27
8054 20:15:18.173933 Byte1 end_step=30 best_step=27
8055 20:15:18.177205 Byte0 TX OE(2T, 0.5T) = (3, 3)
8056 20:15:18.180644 Byte1 TX OE(2T, 0.5T) = (3, 3)
8057 20:15:18.180717
8058 20:15:18.180778
8059 20:15:18.187359 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8060 20:15:18.190420 CH0 RK0: MR19=303, MR18=1212
8061 20:15:18.196972 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8062 20:15:18.197052
8063 20:15:18.200353 ----->DramcWriteLeveling(PI) begin...
8064 20:15:18.200434 ==
8065 20:15:18.203671 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 20:15:18.207147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 20:15:18.207230 ==
8068 20:15:18.210535 Write leveling (Byte 0): 35 => 35
8069 20:15:18.213761 Write leveling (Byte 1): 28 => 28
8070 20:15:18.217053 DramcWriteLeveling(PI) end<-----
8071 20:15:18.217134
8072 20:15:18.217196 ==
8073 20:15:18.220267 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 20:15:18.223981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 20:15:18.224063 ==
8076 20:15:18.226779 [Gating] SW mode calibration
8077 20:15:18.233689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8078 20:15:18.240159 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8079 20:15:18.243442 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 20:15:18.250404 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 20:15:18.253296 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 20:15:18.256690 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8083 20:15:18.260361 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8084 20:15:18.266928 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8085 20:15:18.270051 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 20:15:18.273235 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 20:15:18.280116 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 20:15:18.283392 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 20:15:18.286562 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8090 20:15:18.293317 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8091 20:15:18.296440 1 5 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8092 20:15:18.299902 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8093 20:15:18.306630 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 20:15:18.309742 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 20:15:18.313412 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 20:15:18.319885 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 20:15:18.323260 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8098 20:15:18.326797 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8099 20:15:18.332943 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8100 20:15:18.336357 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 20:15:18.339787 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 20:15:18.346189 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 20:15:18.349955 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 20:15:18.353050 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8105 20:15:18.359652 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8106 20:15:18.363176 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8107 20:15:18.366185 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 20:15:18.373067 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8109 20:15:18.376173 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 20:15:18.379532 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 20:15:18.386230 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 20:15:18.389486 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 20:15:18.392707 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 20:15:18.399344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 20:15:18.402814 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 20:15:18.405791 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 20:15:18.412907 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 20:15:18.416135 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 20:15:18.419470 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 20:15:18.425748 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 20:15:18.429109 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8122 20:15:18.432677 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8123 20:15:18.435705 Total UI for P1: 0, mck2ui 16
8124 20:15:18.439258 best dqsien dly found for B0: ( 1, 9, 8)
8125 20:15:18.442588 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8126 20:15:18.449186 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8127 20:15:18.452399 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 20:15:18.455921 Total UI for P1: 0, mck2ui 16
8129 20:15:18.459035 best dqsien dly found for B1: ( 1, 9, 18)
8130 20:15:18.462306 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8131 20:15:18.465747 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8132 20:15:18.465828
8133 20:15:18.468832 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8134 20:15:18.475853 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8135 20:15:18.475934 [Gating] SW calibration Done
8136 20:15:18.475997 ==
8137 20:15:18.478785 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 20:15:18.485927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 20:15:18.486008 ==
8140 20:15:18.486071 RX Vref Scan: 0
8141 20:15:18.486130
8142 20:15:18.488867 RX Vref 0 -> 0, step: 1
8143 20:15:18.488947
8144 20:15:18.492089 RX Delay 0 -> 252, step: 8
8145 20:15:18.495464 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8146 20:15:18.498783 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8147 20:15:18.502059 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8148 20:15:18.505557 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8149 20:15:18.512047 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8150 20:15:18.515650 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8151 20:15:18.519092 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8152 20:15:18.522192 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8153 20:15:18.525728 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8154 20:15:18.532146 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8155 20:15:18.535750 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8156 20:15:18.539008 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8157 20:15:18.542146 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8158 20:15:18.545601 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8159 20:15:18.552452 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8160 20:15:18.555562 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8161 20:15:18.555645 ==
8162 20:15:18.558753 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 20:15:18.562344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 20:15:18.562462 ==
8165 20:15:18.565801 DQS Delay:
8166 20:15:18.565880 DQS0 = 0, DQS1 = 0
8167 20:15:18.565959 DQM Delay:
8168 20:15:18.568825 DQM0 = 128, DQM1 = 122
8169 20:15:18.568905 DQ Delay:
8170 20:15:18.572015 DQ0 =127, DQ1 =127, DQ2 =127, DQ3 =123
8171 20:15:18.575548 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8172 20:15:18.578823 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8173 20:15:18.585426 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8174 20:15:18.585541
8175 20:15:18.585604
8176 20:15:18.585662 ==
8177 20:15:18.588810 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 20:15:18.591837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 20:15:18.591917 ==
8180 20:15:18.591980
8181 20:15:18.592038
8182 20:15:18.595296 TX Vref Scan disable
8183 20:15:18.595376 == TX Byte 0 ==
8184 20:15:18.601839 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8185 20:15:18.605008 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8186 20:15:18.608513 == TX Byte 1 ==
8187 20:15:18.611679 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8188 20:15:18.615369 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8189 20:15:18.615450 ==
8190 20:15:18.618409 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 20:15:18.621915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 20:15:18.621995 ==
8193 20:15:18.636616
8194 20:15:18.640114 TX Vref early break, caculate TX vref
8195 20:15:18.643499 TX Vref=16, minBit 8, minWin=22, winSum=370
8196 20:15:18.646466 TX Vref=18, minBit 8, minWin=22, winSum=377
8197 20:15:18.650110 TX Vref=20, minBit 1, minWin=23, winSum=383
8198 20:15:18.653346 TX Vref=22, minBit 1, minWin=24, winSum=394
8199 20:15:18.656681 TX Vref=24, minBit 9, minWin=24, winSum=402
8200 20:15:18.663208 TX Vref=26, minBit 8, minWin=24, winSum=406
8201 20:15:18.666501 TX Vref=28, minBit 8, minWin=24, winSum=413
8202 20:15:18.669939 TX Vref=30, minBit 8, minWin=23, winSum=405
8203 20:15:18.673038 TX Vref=32, minBit 8, minWin=24, winSum=405
8204 20:15:18.676415 TX Vref=34, minBit 8, minWin=22, winSum=390
8205 20:15:18.682946 [TxChooseVref] Worse bit 8, Min win 24, Win sum 413, Final Vref 28
8206 20:15:18.683028
8207 20:15:18.686284 Final TX Range 0 Vref 28
8208 20:15:18.686365
8209 20:15:18.686429 ==
8210 20:15:18.689776 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 20:15:18.693017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 20:15:18.693098 ==
8213 20:15:18.693162
8214 20:15:18.693220
8215 20:15:18.696087 TX Vref Scan disable
8216 20:15:18.702813 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8217 20:15:18.702894 == TX Byte 0 ==
8218 20:15:18.706324 u2DelayCellOfst[0]=11 cells (3 PI)
8219 20:15:18.709542 u2DelayCellOfst[1]=18 cells (5 PI)
8220 20:15:18.712784 u2DelayCellOfst[2]=11 cells (3 PI)
8221 20:15:18.716040 u2DelayCellOfst[3]=15 cells (4 PI)
8222 20:15:18.719397 u2DelayCellOfst[4]=7 cells (2 PI)
8223 20:15:18.722578 u2DelayCellOfst[5]=0 cells (0 PI)
8224 20:15:18.726087 u2DelayCellOfst[6]=18 cells (5 PI)
8225 20:15:18.729129 u2DelayCellOfst[7]=18 cells (5 PI)
8226 20:15:18.732497 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8227 20:15:18.735891 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8228 20:15:18.739357 == TX Byte 1 ==
8229 20:15:18.742361 u2DelayCellOfst[8]=0 cells (0 PI)
8230 20:15:18.742441 u2DelayCellOfst[9]=3 cells (1 PI)
8231 20:15:18.745932 u2DelayCellOfst[10]=7 cells (2 PI)
8232 20:15:18.749103 u2DelayCellOfst[11]=7 cells (2 PI)
8233 20:15:18.752300 u2DelayCellOfst[12]=15 cells (4 PI)
8234 20:15:18.755817 u2DelayCellOfst[13]=11 cells (3 PI)
8235 20:15:18.759023 u2DelayCellOfst[14]=15 cells (4 PI)
8236 20:15:18.762376 u2DelayCellOfst[15]=11 cells (3 PI)
8237 20:15:18.765400 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8238 20:15:18.772193 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8239 20:15:18.772274 DramC Write-DBI on
8240 20:15:18.772338 ==
8241 20:15:18.775446 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 20:15:18.781831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 20:15:18.781912 ==
8244 20:15:18.781976
8245 20:15:18.782035
8246 20:15:18.782091 TX Vref Scan disable
8247 20:15:18.786289 == TX Byte 0 ==
8248 20:15:18.789671 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8249 20:15:18.792812 == TX Byte 1 ==
8250 20:15:18.796130 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8251 20:15:18.799156 DramC Write-DBI off
8252 20:15:18.799239
8253 20:15:18.799304 [DATLAT]
8254 20:15:18.799362 Freq=1600, CH0 RK1
8255 20:15:18.799421
8256 20:15:18.802588 DATLAT Default: 0xf
8257 20:15:18.806013 0, 0xFFFF, sum = 0
8258 20:15:18.806095 1, 0xFFFF, sum = 0
8259 20:15:18.809046 2, 0xFFFF, sum = 0
8260 20:15:18.809128 3, 0xFFFF, sum = 0
8261 20:15:18.812469 4, 0xFFFF, sum = 0
8262 20:15:18.812552 5, 0xFFFF, sum = 0
8263 20:15:18.815864 6, 0xFFFF, sum = 0
8264 20:15:18.815945 7, 0xFFFF, sum = 0
8265 20:15:18.819191 8, 0xFFFF, sum = 0
8266 20:15:18.819274 9, 0xFFFF, sum = 0
8267 20:15:18.822286 10, 0xFFFF, sum = 0
8268 20:15:18.822368 11, 0xFFFF, sum = 0
8269 20:15:18.825529 12, 0xFFFF, sum = 0
8270 20:15:18.825611 13, 0xCFFF, sum = 0
8271 20:15:18.829018 14, 0x0, sum = 1
8272 20:15:18.829100 15, 0x0, sum = 2
8273 20:15:18.832135 16, 0x0, sum = 3
8274 20:15:18.832217 17, 0x0, sum = 4
8275 20:15:18.835572 best_step = 15
8276 20:15:18.835653
8277 20:15:18.835716 ==
8278 20:15:18.838983 Dram Type= 6, Freq= 0, CH_0, rank 1
8279 20:15:18.842392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 20:15:18.842473 ==
8281 20:15:18.845453 RX Vref Scan: 0
8282 20:15:18.845558
8283 20:15:18.845623 RX Vref 0 -> 0, step: 1
8284 20:15:18.845682
8285 20:15:18.848950 RX Delay 3 -> 252, step: 4
8286 20:15:18.855380 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8287 20:15:18.858774 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8288 20:15:18.862127 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8289 20:15:18.865449 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8290 20:15:18.868613 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8291 20:15:18.875323 iDelay=195, Bit 5, Center 112 (59 ~ 166) 108
8292 20:15:18.878619 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8293 20:15:18.881783 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8294 20:15:18.885223 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8295 20:15:18.888727 iDelay=195, Bit 9, Center 104 (47 ~ 162) 116
8296 20:15:18.895034 iDelay=195, Bit 10, Center 120 (63 ~ 178) 116
8297 20:15:18.898236 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8298 20:15:18.901908 iDelay=195, Bit 12, Center 124 (67 ~ 182) 116
8299 20:15:18.905240 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
8300 20:15:18.908249 iDelay=195, Bit 14, Center 128 (71 ~ 186) 116
8301 20:15:18.914819 iDelay=195, Bit 15, Center 124 (67 ~ 182) 116
8302 20:15:18.914900 ==
8303 20:15:18.918309 Dram Type= 6, Freq= 0, CH_0, rank 1
8304 20:15:18.921618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 20:15:18.921699 ==
8306 20:15:18.921763 DQS Delay:
8307 20:15:18.924968 DQS0 = 0, DQS1 = 0
8308 20:15:18.925048 DQM Delay:
8309 20:15:18.927992 DQM0 = 125, DQM1 = 118
8310 20:15:18.928073 DQ Delay:
8311 20:15:18.931385 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8312 20:15:18.934805 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =136
8313 20:15:18.938332 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8314 20:15:18.944636 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8315 20:15:18.944759
8316 20:15:18.944823
8317 20:15:18.944882
8318 20:15:18.944938 [DramC_TX_OE_Calibration] TA2
8319 20:15:18.948126 Original DQ_B0 (3 6) =30, OEN = 27
8320 20:15:18.951514 Original DQ_B1 (3 6) =30, OEN = 27
8321 20:15:18.954574 24, 0x0, End_B0=24 End_B1=24
8322 20:15:18.958157 25, 0x0, End_B0=25 End_B1=25
8323 20:15:18.961352 26, 0x0, End_B0=26 End_B1=26
8324 20:15:18.961433 27, 0x0, End_B0=27 End_B1=27
8325 20:15:18.964771 28, 0x0, End_B0=28 End_B1=28
8326 20:15:18.967963 29, 0x0, End_B0=29 End_B1=29
8327 20:15:18.971313 30, 0x0, End_B0=30 End_B1=30
8328 20:15:18.974644 31, 0x4141, End_B0=30 End_B1=30
8329 20:15:18.974728 Byte0 end_step=30 best_step=27
8330 20:15:18.978221 Byte1 end_step=30 best_step=27
8331 20:15:18.981369 Byte0 TX OE(2T, 0.5T) = (3, 3)
8332 20:15:18.984437 Byte1 TX OE(2T, 0.5T) = (3, 3)
8333 20:15:18.984519
8334 20:15:18.984584
8335 20:15:18.994432 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8336 20:15:18.994516 CH0 RK1: MR19=303, MR18=210F
8337 20:15:19.001014 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8338 20:15:19.004389 [RxdqsGatingPostProcess] freq 1600
8339 20:15:19.010775 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8340 20:15:19.014081 best DQS0 dly(2T, 0.5T) = (1, 1)
8341 20:15:19.017406 best DQS1 dly(2T, 0.5T) = (1, 1)
8342 20:15:19.020817 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8343 20:15:19.023856 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8344 20:15:19.023937 best DQS0 dly(2T, 0.5T) = (1, 1)
8345 20:15:19.027472 best DQS1 dly(2T, 0.5T) = (1, 1)
8346 20:15:19.030540 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8347 20:15:19.034001 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8348 20:15:19.037423 Pre-setting of DQS Precalculation
8349 20:15:19.044086 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8350 20:15:19.044167 ==
8351 20:15:19.047343 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 20:15:19.050620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 20:15:19.050701 ==
8354 20:15:19.057389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8355 20:15:19.060700 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8356 20:15:19.063822 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8357 20:15:19.070248 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8358 20:15:19.079241 [CA 0] Center 42 (13~72) winsize 60
8359 20:15:19.082834 [CA 1] Center 43 (13~73) winsize 61
8360 20:15:19.086139 [CA 2] Center 38 (9~67) winsize 59
8361 20:15:19.089460 [CA 3] Center 37 (8~67) winsize 60
8362 20:15:19.092628 [CA 4] Center 37 (8~67) winsize 60
8363 20:15:19.096436 [CA 5] Center 37 (8~66) winsize 59
8364 20:15:19.096528
8365 20:15:19.099362 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8366 20:15:19.099455
8367 20:15:19.102629 [CATrainingPosCal] consider 1 rank data
8368 20:15:19.105866 u2DelayCellTimex100 = 258/100 ps
8369 20:15:19.109403 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8370 20:15:19.116079 CA1 delay=43 (13~73),Diff = 6 PI (22 cell)
8371 20:15:19.119583 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8372 20:15:19.122555 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8373 20:15:19.125696 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8374 20:15:19.129032 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8375 20:15:19.129205
8376 20:15:19.132548 CA PerBit enable=1, Macro0, CA PI delay=37
8377 20:15:19.132748
8378 20:15:19.135690 [CBTSetCACLKResult] CA Dly = 37
8379 20:15:19.139245 CS Dly: 9 (0~40)
8380 20:15:19.142277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8381 20:15:19.145824 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8382 20:15:19.146204 ==
8383 20:15:19.149220 Dram Type= 6, Freq= 0, CH_1, rank 1
8384 20:15:19.152384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 20:15:19.156060 ==
8386 20:15:19.159313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8387 20:15:19.162615 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8388 20:15:19.169133 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8389 20:15:19.172485 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8390 20:15:19.182874 [CA 0] Center 42 (13~71) winsize 59
8391 20:15:19.185972 [CA 1] Center 42 (13~72) winsize 60
8392 20:15:19.189588 [CA 2] Center 37 (8~67) winsize 60
8393 20:15:19.192864 [CA 3] Center 36 (7~66) winsize 60
8394 20:15:19.196160 [CA 4] Center 38 (8~68) winsize 61
8395 20:15:19.199457 [CA 5] Center 37 (7~67) winsize 61
8396 20:15:19.199925
8397 20:15:19.202587 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8398 20:15:19.203074
8399 20:15:19.205967 [CATrainingPosCal] consider 2 rank data
8400 20:15:19.209352 u2DelayCellTimex100 = 258/100 ps
8401 20:15:19.215828 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8402 20:15:19.219077 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8403 20:15:19.222626 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8404 20:15:19.225799 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8405 20:15:19.228867 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8406 20:15:19.232509 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8407 20:15:19.233002
8408 20:15:19.235603 CA PerBit enable=1, Macro0, CA PI delay=37
8409 20:15:19.236100
8410 20:15:19.238993 [CBTSetCACLKResult] CA Dly = 37
8411 20:15:19.242476 CS Dly: 10 (0~43)
8412 20:15:19.245584 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8413 20:15:19.248940 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8414 20:15:19.249361
8415 20:15:19.252237 ----->DramcWriteLeveling(PI) begin...
8416 20:15:19.252862 ==
8417 20:15:19.255680 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 20:15:19.262193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 20:15:19.262786 ==
8420 20:15:19.265239 Write leveling (Byte 0): 24 => 24
8421 20:15:19.268691 Write leveling (Byte 1): 28 => 28
8422 20:15:19.269227 DramcWriteLeveling(PI) end<-----
8423 20:15:19.269711
8424 20:15:19.272221 ==
8425 20:15:19.275347 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 20:15:19.278433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 20:15:19.278958 ==
8428 20:15:19.281773 [Gating] SW mode calibration
8429 20:15:19.288650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8430 20:15:19.291969 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8431 20:15:19.298587 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 20:15:19.301747 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 20:15:19.305090 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 20:15:19.311739 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 20:15:19.315017 1 4 16 | B1->B0 | 3333 3030 | 1 0 | (1 1) (1 1)
8436 20:15:19.318091 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 20:15:19.324884 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 20:15:19.328172 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 20:15:19.331554 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 20:15:19.338083 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 20:15:19.341352 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 20:15:19.344857 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8443 20:15:19.351455 1 5 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 0)
8444 20:15:19.354676 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 20:15:19.358113 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 20:15:19.364361 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 20:15:19.367518 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 20:15:19.371088 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 20:15:19.377622 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 20:15:19.380983 1 6 12 | B1->B0 | 2f2f 2d2d | 1 0 | (0 0) (0 0)
8451 20:15:19.384193 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8452 20:15:19.390641 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 20:15:19.393968 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 20:15:19.397318 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 20:15:19.403952 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 20:15:19.407184 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 20:15:19.410541 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 20:15:19.417119 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 20:15:19.420457 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8460 20:15:19.423883 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 20:15:19.430304 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 20:15:19.433942 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 20:15:19.436925 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 20:15:19.443528 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 20:15:19.446684 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 20:15:19.450132 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 20:15:19.456675 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 20:15:19.460035 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 20:15:19.463394 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 20:15:19.470024 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 20:15:19.473339 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 20:15:19.476843 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 20:15:19.483119 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 20:15:19.486573 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 20:15:19.489682 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8476 20:15:19.496383 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 20:15:19.496879 Total UI for P1: 0, mck2ui 16
8478 20:15:19.503307 best dqsien dly found for B0: ( 1, 9, 16)
8479 20:15:19.503779 Total UI for P1: 0, mck2ui 16
8480 20:15:19.509688 best dqsien dly found for B1: ( 1, 9, 16)
8481 20:15:19.513193 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8482 20:15:19.516424 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8483 20:15:19.516907
8484 20:15:19.519711 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8485 20:15:19.522978 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8486 20:15:19.526161 [Gating] SW calibration Done
8487 20:15:19.526706 ==
8488 20:15:19.529624 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 20:15:19.532974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 20:15:19.533413 ==
8491 20:15:19.536512 RX Vref Scan: 0
8492 20:15:19.536932
8493 20:15:19.537268 RX Vref 0 -> 0, step: 1
8494 20:15:19.537643
8495 20:15:19.539800 RX Delay 0 -> 252, step: 8
8496 20:15:19.542880 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8497 20:15:19.549777 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8498 20:15:19.553095 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8499 20:15:19.556327 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8500 20:15:19.559561 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8501 20:15:19.562746 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8502 20:15:19.569770 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8503 20:15:19.572737 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8504 20:15:19.576134 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8505 20:15:19.579308 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8506 20:15:19.582677 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8507 20:15:19.589213 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8508 20:15:19.592485 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8509 20:15:19.595763 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8510 20:15:19.599321 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8511 20:15:19.605853 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8512 20:15:19.606281 ==
8513 20:15:19.609014 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 20:15:19.612326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 20:15:19.612752 ==
8516 20:15:19.613087 DQS Delay:
8517 20:15:19.615775 DQS0 = 0, DQS1 = 0
8518 20:15:19.616194 DQM Delay:
8519 20:15:19.618742 DQM0 = 132, DQM1 = 126
8520 20:15:19.619181 DQ Delay:
8521 20:15:19.622174 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8522 20:15:19.625641 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8523 20:15:19.629069 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8524 20:15:19.632116 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8525 20:15:19.632496
8526 20:15:19.632843
8527 20:15:19.635428 ==
8528 20:15:19.638602 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 20:15:19.642141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 20:15:19.642534 ==
8531 20:15:19.642849
8532 20:15:19.643168
8533 20:15:19.645348 TX Vref Scan disable
8534 20:15:19.645783 == TX Byte 0 ==
8535 20:15:19.648657 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8536 20:15:19.655357 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8537 20:15:19.655798 == TX Byte 1 ==
8538 20:15:19.658505 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8539 20:15:19.665221 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8540 20:15:19.665713 ==
8541 20:15:19.668529 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 20:15:19.671987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 20:15:19.672571 ==
8544 20:15:19.685269
8545 20:15:19.688270 TX Vref early break, caculate TX vref
8546 20:15:19.691705 TX Vref=16, minBit 11, minWin=21, winSum=365
8547 20:15:19.695150 TX Vref=18, minBit 10, minWin=22, winSum=376
8548 20:15:19.698543 TX Vref=20, minBit 1, minWin=23, winSum=380
8549 20:15:19.701552 TX Vref=22, minBit 12, minWin=23, winSum=391
8550 20:15:19.705011 TX Vref=24, minBit 0, minWin=24, winSum=406
8551 20:15:19.711902 TX Vref=26, minBit 0, minWin=25, winSum=413
8552 20:15:19.714721 TX Vref=28, minBit 0, minWin=25, winSum=415
8553 20:15:19.718387 TX Vref=30, minBit 1, minWin=24, winSum=412
8554 20:15:19.721342 TX Vref=32, minBit 9, minWin=23, winSum=401
8555 20:15:19.724933 TX Vref=34, minBit 6, minWin=23, winSum=392
8556 20:15:19.731301 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8557 20:15:19.731747
8558 20:15:19.734918 Final TX Range 0 Vref 28
8559 20:15:19.735359
8560 20:15:19.735715 ==
8561 20:15:19.737931 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 20:15:19.741152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 20:15:19.741629 ==
8564 20:15:19.742003
8565 20:15:19.742333
8566 20:15:19.744617 TX Vref Scan disable
8567 20:15:19.751452 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8568 20:15:19.751902 == TX Byte 0 ==
8569 20:15:19.754433 u2DelayCellOfst[0]=22 cells (6 PI)
8570 20:15:19.757842 u2DelayCellOfst[1]=15 cells (4 PI)
8571 20:15:19.761045 u2DelayCellOfst[2]=0 cells (0 PI)
8572 20:15:19.764713 u2DelayCellOfst[3]=7 cells (2 PI)
8573 20:15:19.767856 u2DelayCellOfst[4]=11 cells (3 PI)
8574 20:15:19.770981 u2DelayCellOfst[5]=22 cells (6 PI)
8575 20:15:19.774495 u2DelayCellOfst[6]=22 cells (6 PI)
8576 20:15:19.777903 u2DelayCellOfst[7]=7 cells (2 PI)
8577 20:15:19.781110 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8578 20:15:19.784223 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8579 20:15:19.787713 == TX Byte 1 ==
8580 20:15:19.791041 u2DelayCellOfst[8]=0 cells (0 PI)
8581 20:15:19.791580 u2DelayCellOfst[9]=7 cells (2 PI)
8582 20:15:19.794460 u2DelayCellOfst[10]=15 cells (4 PI)
8583 20:15:19.797715 u2DelayCellOfst[11]=11 cells (3 PI)
8584 20:15:19.800948 u2DelayCellOfst[12]=18 cells (5 PI)
8585 20:15:19.804212 u2DelayCellOfst[13]=22 cells (6 PI)
8586 20:15:19.807532 u2DelayCellOfst[14]=22 cells (6 PI)
8587 20:15:19.811138 u2DelayCellOfst[15]=22 cells (6 PI)
8588 20:15:19.817823 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8589 20:15:19.820854 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8590 20:15:19.821300 DramC Write-DBI on
8591 20:15:19.821718 ==
8592 20:15:19.824386 Dram Type= 6, Freq= 0, CH_1, rank 0
8593 20:15:19.830839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8594 20:15:19.831288 ==
8595 20:15:19.831638
8596 20:15:19.831946
8597 20:15:19.832265 TX Vref Scan disable
8598 20:15:19.834726 == TX Byte 0 ==
8599 20:15:19.838130 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8600 20:15:19.841354 == TX Byte 1 ==
8601 20:15:19.844682 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8602 20:15:19.847714 DramC Write-DBI off
8603 20:15:19.848160
8604 20:15:19.848507 [DATLAT]
8605 20:15:19.848843 Freq=1600, CH1 RK0
8606 20:15:19.849147
8607 20:15:19.851412 DATLAT Default: 0xf
8608 20:15:19.854570 0, 0xFFFF, sum = 0
8609 20:15:19.855008 1, 0xFFFF, sum = 0
8610 20:15:19.857879 2, 0xFFFF, sum = 0
8611 20:15:19.858320 3, 0xFFFF, sum = 0
8612 20:15:19.861361 4, 0xFFFF, sum = 0
8613 20:15:19.861826 5, 0xFFFF, sum = 0
8614 20:15:19.864520 6, 0xFFFF, sum = 0
8615 20:15:19.864974 7, 0xFFFF, sum = 0
8616 20:15:19.867725 8, 0xFFFF, sum = 0
8617 20:15:19.868120 9, 0xFFFF, sum = 0
8618 20:15:19.871287 10, 0xFFFF, sum = 0
8619 20:15:19.871803 11, 0xFFFF, sum = 0
8620 20:15:19.874497 12, 0xFFFF, sum = 0
8621 20:15:19.874954 13, 0x8FFF, sum = 0
8622 20:15:19.877974 14, 0x0, sum = 1
8623 20:15:19.878428 15, 0x0, sum = 2
8624 20:15:19.881159 16, 0x0, sum = 3
8625 20:15:19.881651 17, 0x0, sum = 4
8626 20:15:19.884469 best_step = 15
8627 20:15:19.884867
8628 20:15:19.885201 ==
8629 20:15:19.887733 Dram Type= 6, Freq= 0, CH_1, rank 0
8630 20:15:19.890998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8631 20:15:19.891591 ==
8632 20:15:19.894359 RX Vref Scan: 1
8633 20:15:19.894777
8634 20:15:19.895130 Set Vref Range= 24 -> 127
8635 20:15:19.895453
8636 20:15:19.897619 RX Vref 24 -> 127, step: 1
8637 20:15:19.898064
8638 20:15:19.901020 RX Delay 11 -> 252, step: 4
8639 20:15:19.901461
8640 20:15:19.904382 Set Vref, RX VrefLevel [Byte0]: 24
8641 20:15:19.907656 [Byte1]: 24
8642 20:15:19.908112
8643 20:15:19.911054 Set Vref, RX VrefLevel [Byte0]: 25
8644 20:15:19.914099 [Byte1]: 25
8645 20:15:19.917426
8646 20:15:19.917895 Set Vref, RX VrefLevel [Byte0]: 26
8647 20:15:19.920859 [Byte1]: 26
8648 20:15:19.925057
8649 20:15:19.925551 Set Vref, RX VrefLevel [Byte0]: 27
8650 20:15:19.928506 [Byte1]: 27
8651 20:15:19.932937
8652 20:15:19.933372 Set Vref, RX VrefLevel [Byte0]: 28
8653 20:15:19.936131 [Byte1]: 28
8654 20:15:19.940352
8655 20:15:19.940798 Set Vref, RX VrefLevel [Byte0]: 29
8656 20:15:19.943476 [Byte1]: 29
8657 20:15:19.947997
8658 20:15:19.948431 Set Vref, RX VrefLevel [Byte0]: 30
8659 20:15:19.951142 [Byte1]: 30
8660 20:15:19.955722
8661 20:15:19.956168 Set Vref, RX VrefLevel [Byte0]: 31
8662 20:15:19.958689 [Byte1]: 31
8663 20:15:19.963109
8664 20:15:19.963653 Set Vref, RX VrefLevel [Byte0]: 32
8665 20:15:19.966563 [Byte1]: 32
8666 20:15:19.970933
8667 20:15:19.971371 Set Vref, RX VrefLevel [Byte0]: 33
8668 20:15:19.974106 [Byte1]: 33
8669 20:15:19.978313
8670 20:15:19.978745 Set Vref, RX VrefLevel [Byte0]: 34
8671 20:15:19.981751 [Byte1]: 34
8672 20:15:19.985936
8673 20:15:19.986368 Set Vref, RX VrefLevel [Byte0]: 35
8674 20:15:19.989388 [Byte1]: 35
8675 20:15:19.993637
8676 20:15:19.994339 Set Vref, RX VrefLevel [Byte0]: 36
8677 20:15:19.996977 [Byte1]: 36
8678 20:15:20.001189
8679 20:15:20.001830 Set Vref, RX VrefLevel [Byte0]: 37
8680 20:15:20.004309 [Byte1]: 37
8681 20:15:20.008842
8682 20:15:20.009547 Set Vref, RX VrefLevel [Byte0]: 38
8683 20:15:20.012300 [Byte1]: 38
8684 20:15:20.016307
8685 20:15:20.016853 Set Vref, RX VrefLevel [Byte0]: 39
8686 20:15:20.019781 [Byte1]: 39
8687 20:15:20.024029
8688 20:15:20.024602 Set Vref, RX VrefLevel [Byte0]: 40
8689 20:15:20.027505 [Byte1]: 40
8690 20:15:20.031531
8691 20:15:20.032133 Set Vref, RX VrefLevel [Byte0]: 41
8692 20:15:20.035158 [Byte1]: 41
8693 20:15:20.039435
8694 20:15:20.039989 Set Vref, RX VrefLevel [Byte0]: 42
8695 20:15:20.042483 [Byte1]: 42
8696 20:15:20.047004
8697 20:15:20.047557 Set Vref, RX VrefLevel [Byte0]: 43
8698 20:15:20.050060 [Byte1]: 43
8699 20:15:20.054472
8700 20:15:20.054907 Set Vref, RX VrefLevel [Byte0]: 44
8701 20:15:20.057870 [Byte1]: 44
8702 20:15:20.062224
8703 20:15:20.062659 Set Vref, RX VrefLevel [Byte0]: 45
8704 20:15:20.065452 [Byte1]: 45
8705 20:15:20.069685
8706 20:15:20.070134 Set Vref, RX VrefLevel [Byte0]: 46
8707 20:15:20.072900 [Byte1]: 46
8708 20:15:20.077293
8709 20:15:20.077793 Set Vref, RX VrefLevel [Byte0]: 47
8710 20:15:20.080657 [Byte1]: 47
8711 20:15:20.084935
8712 20:15:20.085370 Set Vref, RX VrefLevel [Byte0]: 48
8713 20:15:20.088365 [Byte1]: 48
8714 20:15:20.092600
8715 20:15:20.093037 Set Vref, RX VrefLevel [Byte0]: 49
8716 20:15:20.095555 [Byte1]: 49
8717 20:15:20.100310
8718 20:15:20.100746 Set Vref, RX VrefLevel [Byte0]: 50
8719 20:15:20.103472 [Byte1]: 50
8720 20:15:20.107759
8721 20:15:20.108195 Set Vref, RX VrefLevel [Byte0]: 51
8722 20:15:20.111193 [Byte1]: 51
8723 20:15:20.115218
8724 20:15:20.115662 Set Vref, RX VrefLevel [Byte0]: 52
8725 20:15:20.118757 [Byte1]: 52
8726 20:15:20.123331
8727 20:15:20.123735 Set Vref, RX VrefLevel [Byte0]: 53
8728 20:15:20.126247 [Byte1]: 53
8729 20:15:20.130758
8730 20:15:20.131217 Set Vref, RX VrefLevel [Byte0]: 54
8731 20:15:20.133845 [Byte1]: 54
8732 20:15:20.138171
8733 20:15:20.138610 Set Vref, RX VrefLevel [Byte0]: 55
8734 20:15:20.141514 [Byte1]: 55
8735 20:15:20.145872
8736 20:15:20.146308 Set Vref, RX VrefLevel [Byte0]: 56
8737 20:15:20.148974 [Byte1]: 56
8738 20:15:20.153418
8739 20:15:20.153908 Set Vref, RX VrefLevel [Byte0]: 57
8740 20:15:20.156636 [Byte1]: 57
8741 20:15:20.161201
8742 20:15:20.161709 Set Vref, RX VrefLevel [Byte0]: 58
8743 20:15:20.164513 [Byte1]: 58
8744 20:15:20.168512
8745 20:15:20.169157 Set Vref, RX VrefLevel [Byte0]: 59
8746 20:15:20.172049 [Byte1]: 59
8747 20:15:20.176112
8748 20:15:20.176547 Set Vref, RX VrefLevel [Byte0]: 60
8749 20:15:20.179550 [Byte1]: 60
8750 20:15:20.183879
8751 20:15:20.184322 Set Vref, RX VrefLevel [Byte0]: 61
8752 20:15:20.187229 [Byte1]: 61
8753 20:15:20.191503
8754 20:15:20.192043 Set Vref, RX VrefLevel [Byte0]: 62
8755 20:15:20.194843 [Byte1]: 62
8756 20:15:20.199349
8757 20:15:20.199787 Set Vref, RX VrefLevel [Byte0]: 63
8758 20:15:20.202455 [Byte1]: 63
8759 20:15:20.206769
8760 20:15:20.207207 Set Vref, RX VrefLevel [Byte0]: 64
8761 20:15:20.210156 [Byte1]: 64
8762 20:15:20.214323
8763 20:15:20.214762 Set Vref, RX VrefLevel [Byte0]: 65
8764 20:15:20.217742 [Byte1]: 65
8765 20:15:20.222244
8766 20:15:20.222688 Set Vref, RX VrefLevel [Byte0]: 66
8767 20:15:20.225545 [Byte1]: 66
8768 20:15:20.229727
8769 20:15:20.230159 Set Vref, RX VrefLevel [Byte0]: 67
8770 20:15:20.232737 [Byte1]: 67
8771 20:15:20.237373
8772 20:15:20.237945 Set Vref, RX VrefLevel [Byte0]: 68
8773 20:15:20.240567 [Byte1]: 68
8774 20:15:20.244667
8775 20:15:20.245097 Set Vref, RX VrefLevel [Byte0]: 69
8776 20:15:20.248135 [Byte1]: 69
8777 20:15:20.252405
8778 20:15:20.252840 Set Vref, RX VrefLevel [Byte0]: 70
8779 20:15:20.255806 [Byte1]: 70
8780 20:15:20.259846
8781 20:15:20.260280 Set Vref, RX VrefLevel [Byte0]: 71
8782 20:15:20.263218 [Byte1]: 71
8783 20:15:20.267922
8784 20:15:20.268356 Final RX Vref Byte 0 = 57 to rank0
8785 20:15:20.270825 Final RX Vref Byte 1 = 55 to rank0
8786 20:15:20.274247 Final RX Vref Byte 0 = 57 to rank1
8787 20:15:20.277706 Final RX Vref Byte 1 = 55 to rank1==
8788 20:15:20.280865 Dram Type= 6, Freq= 0, CH_1, rank 0
8789 20:15:20.287640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 20:15:20.288054 ==
8791 20:15:20.288403 DQS Delay:
8792 20:15:20.288728 DQS0 = 0, DQS1 = 0
8793 20:15:20.291077 DQM Delay:
8794 20:15:20.291526 DQM0 = 131, DQM1 = 123
8795 20:15:20.294294 DQ Delay:
8796 20:15:20.297347 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8797 20:15:20.300688 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8798 20:15:20.304160 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8799 20:15:20.307272 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8800 20:15:20.307708
8801 20:15:20.308045
8802 20:15:20.308365
8803 20:15:20.310823 [DramC_TX_OE_Calibration] TA2
8804 20:15:20.314301 Original DQ_B0 (3 6) =30, OEN = 27
8805 20:15:20.317447 Original DQ_B1 (3 6) =30, OEN = 27
8806 20:15:20.320785 24, 0x0, End_B0=24 End_B1=24
8807 20:15:20.321230 25, 0x0, End_B0=25 End_B1=25
8808 20:15:20.324022 26, 0x0, End_B0=26 End_B1=26
8809 20:15:20.327298 27, 0x0, End_B0=27 End_B1=27
8810 20:15:20.330516 28, 0x0, End_B0=28 End_B1=28
8811 20:15:20.333943 29, 0x0, End_B0=29 End_B1=29
8812 20:15:20.334400 30, 0x0, End_B0=30 End_B1=30
8813 20:15:20.337177 31, 0x4545, End_B0=30 End_B1=30
8814 20:15:20.340529 Byte0 end_step=30 best_step=27
8815 20:15:20.343787 Byte1 end_step=30 best_step=27
8816 20:15:20.347069 Byte0 TX OE(2T, 0.5T) = (3, 3)
8817 20:15:20.350463 Byte1 TX OE(2T, 0.5T) = (3, 3)
8818 20:15:20.350940
8819 20:15:20.351271
8820 20:15:20.356816 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8821 20:15:20.360374 CH1 RK0: MR19=303, MR18=70B
8822 20:15:20.366941 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8823 20:15:20.367404
8824 20:15:20.370161 ----->DramcWriteLeveling(PI) begin...
8825 20:15:20.370614 ==
8826 20:15:20.373663 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 20:15:20.376691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 20:15:20.377139 ==
8829 20:15:20.380087 Write leveling (Byte 0): 25 => 25
8830 20:15:20.383706 Write leveling (Byte 1): 28 => 28
8831 20:15:20.386802 DramcWriteLeveling(PI) end<-----
8832 20:15:20.387215
8833 20:15:20.387576 ==
8834 20:15:20.389848 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 20:15:20.393350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 20:15:20.393850 ==
8837 20:15:20.396881 [Gating] SW mode calibration
8838 20:15:20.403375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8839 20:15:20.409886 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8840 20:15:20.413372 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 20:15:20.419747 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 20:15:20.423008 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8843 20:15:20.426564 1 4 12 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
8844 20:15:20.432976 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 20:15:20.436530 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 20:15:20.440167 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 20:15:20.446224 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 20:15:20.449603 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 20:15:20.453086 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 20:15:20.456085 1 5 8 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8851 20:15:20.462849 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8852 20:15:20.466205 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 20:15:20.469204 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 20:15:20.476092 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 20:15:20.479531 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 20:15:20.482830 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 20:15:20.489745 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8858 20:15:20.492769 1 6 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8859 20:15:20.496187 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8860 20:15:20.502818 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 20:15:20.505855 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 20:15:20.509281 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 20:15:20.515662 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 20:15:20.519019 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 20:15:20.522383 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8866 20:15:20.528951 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8867 20:15:20.532145 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8868 20:15:20.535658 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 20:15:20.542122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 20:15:20.545453 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 20:15:20.548479 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 20:15:20.555456 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 20:15:20.558525 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 20:15:20.562143 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 20:15:20.568895 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 20:15:20.572146 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 20:15:20.575368 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 20:15:20.581631 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 20:15:20.585183 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 20:15:20.588416 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 20:15:20.594849 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 20:15:20.598200 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8883 20:15:20.601600 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8884 20:15:20.607954 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 20:15:20.611773 Total UI for P1: 0, mck2ui 16
8886 20:15:20.614869 best dqsien dly found for B0: ( 1, 9, 10)
8887 20:15:20.615404 Total UI for P1: 0, mck2ui 16
8888 20:15:20.621683 best dqsien dly found for B1: ( 1, 9, 10)
8889 20:15:20.624889 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8890 20:15:20.627908 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8891 20:15:20.628343
8892 20:15:20.631396 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8893 20:15:20.634475 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8894 20:15:20.637912 [Gating] SW calibration Done
8895 20:15:20.638348 ==
8896 20:15:20.641189 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 20:15:20.644468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 20:15:20.644897 ==
8899 20:15:20.647776 RX Vref Scan: 0
8900 20:15:20.648212
8901 20:15:20.651264 RX Vref 0 -> 0, step: 1
8902 20:15:20.651801
8903 20:15:20.652155 RX Delay 0 -> 252, step: 8
8904 20:15:20.657640 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8905 20:15:20.661053 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8906 20:15:20.664339 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8907 20:15:20.667785 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8908 20:15:20.671043 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8909 20:15:20.677462 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8910 20:15:20.680822 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8911 20:15:20.684178 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8912 20:15:20.687738 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8913 20:15:20.690720 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8914 20:15:20.697262 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8915 20:15:20.700832 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8916 20:15:20.704321 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8917 20:15:20.707372 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8918 20:15:20.710842 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8919 20:15:20.717445 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8920 20:15:20.717919 ==
8921 20:15:20.720591 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 20:15:20.724129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 20:15:20.724573 ==
8924 20:15:20.724924 DQS Delay:
8925 20:15:20.727184 DQS0 = 0, DQS1 = 0
8926 20:15:20.727624 DQM Delay:
8927 20:15:20.730502 DQM0 = 133, DQM1 = 128
8928 20:15:20.730938 DQ Delay:
8929 20:15:20.733993 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8930 20:15:20.737061 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8931 20:15:20.740574 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8932 20:15:20.743965 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8933 20:15:20.744421
8934 20:15:20.747226
8935 20:15:20.747643 ==
8936 20:15:20.750714 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 20:15:20.753940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 20:15:20.754380 ==
8939 20:15:20.754728
8940 20:15:20.755033
8941 20:15:20.757064 TX Vref Scan disable
8942 20:15:20.757546 == TX Byte 0 ==
8943 20:15:20.763829 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8944 20:15:20.767235 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8945 20:15:20.767691 == TX Byte 1 ==
8946 20:15:20.773506 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8947 20:15:20.776813 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 20:15:20.777264 ==
8949 20:15:20.780242 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 20:15:20.783528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 20:15:20.783977 ==
8952 20:15:20.798124
8953 20:15:20.801436 TX Vref early break, caculate TX vref
8954 20:15:20.804735 TX Vref=16, minBit 0, minWin=23, winSum=383
8955 20:15:20.808008 TX Vref=18, minBit 0, minWin=23, winSum=392
8956 20:15:20.811783 TX Vref=20, minBit 0, minWin=23, winSum=398
8957 20:15:20.814872 TX Vref=22, minBit 0, minWin=23, winSum=407
8958 20:15:20.818175 TX Vref=24, minBit 0, minWin=24, winSum=421
8959 20:15:20.824899 TX Vref=26, minBit 0, minWin=25, winSum=425
8960 20:15:20.828129 TX Vref=28, minBit 1, minWin=25, winSum=427
8961 20:15:20.831491 TX Vref=30, minBit 0, minWin=25, winSum=421
8962 20:15:20.834592 TX Vref=32, minBit 1, minWin=24, winSum=411
8963 20:15:20.838182 TX Vref=34, minBit 1, minWin=24, winSum=406
8964 20:15:20.841094 TX Vref=36, minBit 9, minWin=22, winSum=394
8965 20:15:20.847754 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
8966 20:15:20.848194
8967 20:15:20.851331 Final TX Range 0 Vref 28
8968 20:15:20.851873
8969 20:15:20.852219 ==
8970 20:15:20.854410 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 20:15:20.857874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 20:15:20.858309 ==
8973 20:15:20.858642
8974 20:15:20.860955
8975 20:15:20.861387 TX Vref Scan disable
8976 20:15:20.867685 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8977 20:15:20.868140 == TX Byte 0 ==
8978 20:15:20.871008 u2DelayCellOfst[0]=18 cells (5 PI)
8979 20:15:20.874311 u2DelayCellOfst[1]=18 cells (5 PI)
8980 20:15:20.877562 u2DelayCellOfst[2]=0 cells (0 PI)
8981 20:15:20.880726 u2DelayCellOfst[3]=7 cells (2 PI)
8982 20:15:20.884206 u2DelayCellOfst[4]=11 cells (3 PI)
8983 20:15:20.887677 u2DelayCellOfst[5]=22 cells (6 PI)
8984 20:15:20.890849 u2DelayCellOfst[6]=18 cells (5 PI)
8985 20:15:20.893923 u2DelayCellOfst[7]=7 cells (2 PI)
8986 20:15:20.897593 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8987 20:15:20.900620 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8988 20:15:20.904090 == TX Byte 1 ==
8989 20:15:20.907147 u2DelayCellOfst[8]=0 cells (0 PI)
8990 20:15:20.910499 u2DelayCellOfst[9]=7 cells (2 PI)
8991 20:15:20.913688 u2DelayCellOfst[10]=11 cells (3 PI)
8992 20:15:20.917135 u2DelayCellOfst[11]=7 cells (2 PI)
8993 20:15:20.917613 u2DelayCellOfst[12]=18 cells (5 PI)
8994 20:15:20.920593 u2DelayCellOfst[13]=18 cells (5 PI)
8995 20:15:20.923879 u2DelayCellOfst[14]=22 cells (6 PI)
8996 20:15:20.927107 u2DelayCellOfst[15]=22 cells (6 PI)
8997 20:15:20.934024 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8998 20:15:20.937335 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8999 20:15:20.937930 DramC Write-DBI on
9000 20:15:20.940435 ==
9001 20:15:20.943790 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 20:15:20.947237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 20:15:20.947736 ==
9004 20:15:20.948076
9005 20:15:20.948442
9006 20:15:20.950171 TX Vref Scan disable
9007 20:15:20.950623 == TX Byte 0 ==
9008 20:15:20.956987 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9009 20:15:20.957443 == TX Byte 1 ==
9010 20:15:20.960398 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9011 20:15:20.963608 DramC Write-DBI off
9012 20:15:20.964069
9013 20:15:20.964466 [DATLAT]
9014 20:15:20.966845 Freq=1600, CH1 RK1
9015 20:15:20.967293
9016 20:15:20.967655 DATLAT Default: 0xf
9017 20:15:20.970068 0, 0xFFFF, sum = 0
9018 20:15:20.970517 1, 0xFFFF, sum = 0
9019 20:15:20.973368 2, 0xFFFF, sum = 0
9020 20:15:20.973882 3, 0xFFFF, sum = 0
9021 20:15:20.976811 4, 0xFFFF, sum = 0
9022 20:15:20.977228 5, 0xFFFF, sum = 0
9023 20:15:20.980020 6, 0xFFFF, sum = 0
9024 20:15:20.980513 7, 0xFFFF, sum = 0
9025 20:15:20.983174 8, 0xFFFF, sum = 0
9026 20:15:20.986450 9, 0xFFFF, sum = 0
9027 20:15:20.987037 10, 0xFFFF, sum = 0
9028 20:15:20.990040 11, 0xFFFF, sum = 0
9029 20:15:20.990491 12, 0xFFFF, sum = 0
9030 20:15:20.993095 13, 0x8FFF, sum = 0
9031 20:15:20.993656 14, 0x0, sum = 1
9032 20:15:20.996838 15, 0x0, sum = 2
9033 20:15:20.997295 16, 0x0, sum = 3
9034 20:15:20.999894 17, 0x0, sum = 4
9035 20:15:21.000354 best_step = 15
9036 20:15:21.000714
9037 20:15:21.001267 ==
9038 20:15:21.002968 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 20:15:21.006355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 20:15:21.006811 ==
9041 20:15:21.009824 RX Vref Scan: 0
9042 20:15:21.010235
9043 20:15:21.012837 RX Vref 0 -> 0, step: 1
9044 20:15:21.013273
9045 20:15:21.013682 RX Delay 11 -> 252, step: 4
9046 20:15:21.020285 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9047 20:15:21.023636 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9048 20:15:21.026882 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9049 20:15:21.030460 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9050 20:15:21.033574 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9051 20:15:21.040688 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9052 20:15:21.043414 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9053 20:15:21.046989 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9054 20:15:21.050056 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9055 20:15:21.053308 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9056 20:15:21.059866 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9057 20:15:21.063399 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9058 20:15:21.066722 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9059 20:15:21.070012 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9060 20:15:21.076471 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9061 20:15:21.079530 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9062 20:15:21.079944 ==
9063 20:15:21.083004 Dram Type= 6, Freq= 0, CH_1, rank 1
9064 20:15:21.086477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9065 20:15:21.086913 ==
9066 20:15:21.089865 DQS Delay:
9067 20:15:21.090279 DQS0 = 0, DQS1 = 0
9068 20:15:21.090718 DQM Delay:
9069 20:15:21.093093 DQM0 = 130, DQM1 = 124
9070 20:15:21.093587 DQ Delay:
9071 20:15:21.096243 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =128
9072 20:15:21.099449 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9073 20:15:21.106185 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9074 20:15:21.109630 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9075 20:15:21.110070
9076 20:15:21.110420
9077 20:15:21.110743
9078 20:15:21.112680 [DramC_TX_OE_Calibration] TA2
9079 20:15:21.116142 Original DQ_B0 (3 6) =30, OEN = 27
9080 20:15:21.116582 Original DQ_B1 (3 6) =30, OEN = 27
9081 20:15:21.119588 24, 0x0, End_B0=24 End_B1=24
9082 20:15:21.123075 25, 0x0, End_B0=25 End_B1=25
9083 20:15:21.126184 26, 0x0, End_B0=26 End_B1=26
9084 20:15:21.129422 27, 0x0, End_B0=27 End_B1=27
9085 20:15:21.130089 28, 0x0, End_B0=28 End_B1=28
9086 20:15:21.132931 29, 0x0, End_B0=29 End_B1=29
9087 20:15:21.136304 30, 0x0, End_B0=30 End_B1=30
9088 20:15:21.139533 31, 0x4141, End_B0=30 End_B1=30
9089 20:15:21.142546 Byte0 end_step=30 best_step=27
9090 20:15:21.145930 Byte1 end_step=30 best_step=27
9091 20:15:21.146707 Byte0 TX OE(2T, 0.5T) = (3, 3)
9092 20:15:21.149470 Byte1 TX OE(2T, 0.5T) = (3, 3)
9093 20:15:21.149937
9094 20:15:21.150267
9095 20:15:21.159588 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9096 20:15:21.160011 CH1 RK1: MR19=303, MR18=F1A
9097 20:15:21.165897 CH1_RK1: MR19=0x303, MR18=0xF1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9098 20:15:21.169424 [RxdqsGatingPostProcess] freq 1600
9099 20:15:21.175765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9100 20:15:21.179523 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 20:15:21.182471 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 20:15:21.185631 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 20:15:21.189111 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 20:15:21.189595 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 20:15:21.192415 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 20:15:21.195461 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 20:15:21.198921 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 20:15:21.202095 Pre-setting of DQS Precalculation
9109 20:15:21.208602 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9110 20:15:21.215292 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9111 20:15:21.222346 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 20:15:21.222920
9113 20:15:21.223263
9114 20:15:21.225228 [Calibration Summary] 3200 Mbps
9115 20:15:21.225671 CH 0, Rank 0
9116 20:15:21.228810 SW Impedance : PASS
9117 20:15:21.231875 DUTY Scan : NO K
9118 20:15:21.232313 ZQ Calibration : PASS
9119 20:15:21.235263 Jitter Meter : NO K
9120 20:15:21.238448 CBT Training : PASS
9121 20:15:21.238886 Write leveling : PASS
9122 20:15:21.241866 RX DQS gating : PASS
9123 20:15:21.245200 RX DQ/DQS(RDDQC) : PASS
9124 20:15:21.245697 TX DQ/DQS : PASS
9125 20:15:21.248593 RX DATLAT : PASS
9126 20:15:21.251572 RX DQ/DQS(Engine): PASS
9127 20:15:21.252011 TX OE : PASS
9128 20:15:21.255370 All Pass.
9129 20:15:21.255810
9130 20:15:21.256165 CH 0, Rank 1
9131 20:15:21.258584 SW Impedance : PASS
9132 20:15:21.259194 DUTY Scan : NO K
9133 20:15:21.261792 ZQ Calibration : PASS
9134 20:15:21.264914 Jitter Meter : NO K
9135 20:15:21.265531 CBT Training : PASS
9136 20:15:21.268291 Write leveling : PASS
9137 20:15:21.268727 RX DQS gating : PASS
9138 20:15:21.271572 RX DQ/DQS(RDDQC) : PASS
9139 20:15:21.274858 TX DQ/DQS : PASS
9140 20:15:21.275291 RX DATLAT : PASS
9141 20:15:21.278400 RX DQ/DQS(Engine): PASS
9142 20:15:21.281601 TX OE : PASS
9143 20:15:21.282042 All Pass.
9144 20:15:21.282392
9145 20:15:21.282715 CH 1, Rank 0
9146 20:15:21.284975 SW Impedance : PASS
9147 20:15:21.288382 DUTY Scan : NO K
9148 20:15:21.288819 ZQ Calibration : PASS
9149 20:15:21.291428 Jitter Meter : NO K
9150 20:15:21.294849 CBT Training : PASS
9151 20:15:21.295267 Write leveling : PASS
9152 20:15:21.298687 RX DQS gating : PASS
9153 20:15:21.301621 RX DQ/DQS(RDDQC) : PASS
9154 20:15:21.302057 TX DQ/DQS : PASS
9155 20:15:21.304933 RX DATLAT : PASS
9156 20:15:21.307992 RX DQ/DQS(Engine): PASS
9157 20:15:21.308419 TX OE : PASS
9158 20:15:21.311185 All Pass.
9159 20:15:21.311617
9160 20:15:21.312061 CH 1, Rank 1
9161 20:15:21.314344 SW Impedance : PASS
9162 20:15:21.314779 DUTY Scan : NO K
9163 20:15:21.317800 ZQ Calibration : PASS
9164 20:15:21.321046 Jitter Meter : NO K
9165 20:15:21.321517 CBT Training : PASS
9166 20:15:21.324473 Write leveling : PASS
9167 20:15:21.327977 RX DQS gating : PASS
9168 20:15:21.328463 RX DQ/DQS(RDDQC) : PASS
9169 20:15:21.331225 TX DQ/DQS : PASS
9170 20:15:21.334416 RX DATLAT : PASS
9171 20:15:21.334831 RX DQ/DQS(Engine): PASS
9172 20:15:21.337952 TX OE : PASS
9173 20:15:21.338369 All Pass.
9174 20:15:21.338697
9175 20:15:21.340964 DramC Write-DBI on
9176 20:15:21.344302 PER_BANK_REFRESH: Hybrid Mode
9177 20:15:21.344716 TX_TRACKING: ON
9178 20:15:21.354242 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9179 20:15:21.360997 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9180 20:15:21.367629 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9181 20:15:21.370628 [FAST_K] Save calibration result to emmc
9182 20:15:21.374078 sync common calibartion params.
9183 20:15:21.377458 sync cbt_mode0:1, 1:1
9184 20:15:21.380615 dram_init: ddr_geometry: 2
9185 20:15:21.381071 dram_init: ddr_geometry: 2
9186 20:15:21.384053 dram_init: ddr_geometry: 2
9187 20:15:21.387433 0:dram_rank_size:100000000
9188 20:15:21.387879 1:dram_rank_size:100000000
9189 20:15:21.393988 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9190 20:15:21.397578 DFS_SHUFFLE_HW_MODE: ON
9191 20:15:21.400495 dramc_set_vcore_voltage set vcore to 725000
9192 20:15:21.403938 Read voltage for 1600, 0
9193 20:15:21.404353 Vio18 = 0
9194 20:15:21.404680 Vcore = 725000
9195 20:15:21.407330 Vdram = 0
9196 20:15:21.407743 Vddq = 0
9197 20:15:21.408072 Vmddr = 0
9198 20:15:21.410437 switch to 3200 Mbps bootup
9199 20:15:21.410852 [DramcRunTimeConfig]
9200 20:15:21.413978 PHYPLL
9201 20:15:21.414393 DPM_CONTROL_AFTERK: ON
9202 20:15:21.417208 PER_BANK_REFRESH: ON
9203 20:15:21.420696 REFRESH_OVERHEAD_REDUCTION: ON
9204 20:15:21.421112 CMD_PICG_NEW_MODE: OFF
9205 20:15:21.423688 XRTWTW_NEW_MODE: ON
9206 20:15:21.424105 XRTRTR_NEW_MODE: ON
9207 20:15:21.427066 TX_TRACKING: ON
9208 20:15:21.427484 RDSEL_TRACKING: OFF
9209 20:15:21.430152 DQS Precalculation for DVFS: ON
9210 20:15:21.433633 RX_TRACKING: OFF
9211 20:15:21.434051 HW_GATING DBG: ON
9212 20:15:21.436784 ZQCS_ENABLE_LP4: ON
9213 20:15:21.437198 RX_PICG_NEW_MODE: ON
9214 20:15:21.440053 TX_PICG_NEW_MODE: ON
9215 20:15:21.443829 ENABLE_RX_DCM_DPHY: ON
9216 20:15:21.444245 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9217 20:15:21.446832 DUMMY_READ_FOR_TRACKING: OFF
9218 20:15:21.450165 !!! SPM_CONTROL_AFTERK: OFF
9219 20:15:21.453738 !!! SPM could not control APHY
9220 20:15:21.454156 IMPEDANCE_TRACKING: ON
9221 20:15:21.456875 TEMP_SENSOR: ON
9222 20:15:21.457289 HW_SAVE_FOR_SR: OFF
9223 20:15:21.460537 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9224 20:15:21.463786 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9225 20:15:21.466975 Read ODT Tracking: ON
9226 20:15:21.470127 Refresh Rate DeBounce: ON
9227 20:15:21.470541 DFS_NO_QUEUE_FLUSH: ON
9228 20:15:21.473432 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9229 20:15:21.476899 ENABLE_DFS_RUNTIME_MRW: OFF
9230 20:15:21.480204 DDR_RESERVE_NEW_MODE: ON
9231 20:15:21.480618 MR_CBT_SWITCH_FREQ: ON
9232 20:15:21.483695 =========================
9233 20:15:21.502631 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9234 20:15:21.505890 dram_init: ddr_geometry: 2
9235 20:15:21.524347 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9236 20:15:21.527712 dram_init: dram init end (result: 0)
9237 20:15:21.534330 DRAM-K: Full calibration passed in 24593 msecs
9238 20:15:21.537657 MRC: failed to locate region type 0.
9239 20:15:21.538075 DRAM rank0 size:0x100000000,
9240 20:15:21.540739 DRAM rank1 size=0x100000000
9241 20:15:21.550786 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9242 20:15:21.557302 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9243 20:15:21.563950 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9244 20:15:21.570765 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9245 20:15:21.574043 DRAM rank0 size:0x100000000,
9246 20:15:21.577239 DRAM rank1 size=0x100000000
9247 20:15:21.577847 CBMEM:
9248 20:15:21.580420 IMD: root @ 0xfffff000 254 entries.
9249 20:15:21.583807 IMD: root @ 0xffffec00 62 entries.
9250 20:15:21.587227 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9251 20:15:21.590651 WARNING: RO_VPD is uninitialized or empty.
9252 20:15:21.597168 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9253 20:15:21.604449 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9254 20:15:21.617222 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9255 20:15:21.628549 BS: romstage times (exec / console): total (unknown) / 24055 ms
9256 20:15:21.629139
9257 20:15:21.629684
9258 20:15:21.638304 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9259 20:15:21.641749 ARM64: Exception handlers installed.
9260 20:15:21.645034 ARM64: Testing exception
9261 20:15:21.648542 ARM64: Done test exception
9262 20:15:21.648973 Enumerating buses...
9263 20:15:21.651733 Show all devs... Before device enumeration.
9264 20:15:21.655063 Root Device: enabled 1
9265 20:15:21.658545 CPU_CLUSTER: 0: enabled 1
9266 20:15:21.658959 CPU: 00: enabled 1
9267 20:15:21.661579 Compare with tree...
9268 20:15:21.662000 Root Device: enabled 1
9269 20:15:21.664691 CPU_CLUSTER: 0: enabled 1
9270 20:15:21.667896 CPU: 00: enabled 1
9271 20:15:21.668312 Root Device scanning...
9272 20:15:21.671202 scan_static_bus for Root Device
9273 20:15:21.674581 CPU_CLUSTER: 0 enabled
9274 20:15:21.677974 scan_static_bus for Root Device done
9275 20:15:21.681270 scan_bus: bus Root Device finished in 8 msecs
9276 20:15:21.681721 done
9277 20:15:21.687935 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9278 20:15:21.691100 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9279 20:15:21.697917 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9280 20:15:21.701375 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9281 20:15:21.704500 Allocating resources...
9282 20:15:21.707617 Reading resources...
9283 20:15:21.710907 Root Device read_resources bus 0 link: 0
9284 20:15:21.714449 DRAM rank0 size:0x100000000,
9285 20:15:21.714881 DRAM rank1 size=0x100000000
9286 20:15:21.717877 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9287 20:15:21.721064 CPU: 00 missing read_resources
9288 20:15:21.727546 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9289 20:15:21.730758 Root Device read_resources bus 0 link: 0 done
9290 20:15:21.731361 Done reading resources.
9291 20:15:21.737613 Show resources in subtree (Root Device)...After reading.
9292 20:15:21.740830 Root Device child on link 0 CPU_CLUSTER: 0
9293 20:15:21.744401 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 20:15:21.754157 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 20:15:21.754597 CPU: 00
9296 20:15:21.757424 Root Device assign_resources, bus 0 link: 0
9297 20:15:21.760713 CPU_CLUSTER: 0 missing set_resources
9298 20:15:21.767416 Root Device assign_resources, bus 0 link: 0 done
9299 20:15:21.768066 Done setting resources.
9300 20:15:21.774036 Show resources in subtree (Root Device)...After assigning values.
9301 20:15:21.777135 Root Device child on link 0 CPU_CLUSTER: 0
9302 20:15:21.780580 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 20:15:21.790306 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 20:15:21.790761 CPU: 00
9305 20:15:21.793686 Done allocating resources.
9306 20:15:21.800388 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9307 20:15:21.800826 Enabling resources...
9308 20:15:21.801173 done.
9309 20:15:21.807098 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9310 20:15:21.807533 Initializing devices...
9311 20:15:21.810447 Root Device init
9312 20:15:21.810966 init hardware done!
9313 20:15:21.813573 0x00000018: ctrlr->caps
9314 20:15:21.816930 52.000 MHz: ctrlr->f_max
9315 20:15:21.817371 0.400 MHz: ctrlr->f_min
9316 20:15:21.820491 0x40ff8080: ctrlr->voltages
9317 20:15:21.823607 sclk: 390625
9318 20:15:21.824035 Bus Width = 1
9319 20:15:21.824380 sclk: 390625
9320 20:15:21.827025 Bus Width = 1
9321 20:15:21.827460 Early init status = 3
9322 20:15:21.833714 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9323 20:15:21.836950 in-header: 03 fc 00 00 01 00 00 00
9324 20:15:21.840307 in-data: 00
9325 20:15:21.843595 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9326 20:15:21.848742 in-header: 03 fd 00 00 00 00 00 00
9327 20:15:21.852158 in-data:
9328 20:15:21.855532 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9329 20:15:21.859935 in-header: 03 fc 00 00 01 00 00 00
9330 20:15:21.863253 in-data: 00
9331 20:15:21.866095 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9332 20:15:21.872209 in-header: 03 fd 00 00 00 00 00 00
9333 20:15:21.875351 in-data:
9334 20:15:21.878683 [SSUSB] Setting up USB HOST controller...
9335 20:15:21.881894 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9336 20:15:21.885314 [SSUSB] phy power-on done.
9337 20:15:21.888309 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9338 20:15:21.895128 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9339 20:15:21.898551 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9340 20:15:21.904938 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9341 20:15:21.911620 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9342 20:15:21.918383 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9343 20:15:21.924706 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9344 20:15:21.931838 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9345 20:15:21.934889 SPM: binary array size = 0x9dc
9346 20:15:21.938228 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9347 20:15:21.944980 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9348 20:15:21.951990 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9349 20:15:21.954942 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9350 20:15:21.961318 configure_display: Starting display init
9351 20:15:21.995179 anx7625_power_on_init: Init interface.
9352 20:15:21.998542 anx7625_disable_pd_protocol: Disabled PD feature.
9353 20:15:22.001832 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9354 20:15:22.029511 anx7625_start_dp_work: Secure OCM version=00
9355 20:15:22.033065 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9356 20:15:22.047796 sp_tx_get_edid_block: EDID Block = 1
9357 20:15:22.150218 Extracted contents:
9358 20:15:22.153359 header: 00 ff ff ff ff ff ff 00
9359 20:15:22.156945 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9360 20:15:22.160131 version: 01 04
9361 20:15:22.163485 basic params: 95 1f 11 78 0a
9362 20:15:22.166483 chroma info: 76 90 94 55 54 90 27 21 50 54
9363 20:15:22.170060 established: 00 00 00
9364 20:15:22.176677 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9365 20:15:22.180021 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9366 20:15:22.186661 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 20:15:22.193058 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9368 20:15:22.199904 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9369 20:15:22.203245 extensions: 00
9370 20:15:22.203660 checksum: fb
9371 20:15:22.203991
9372 20:15:22.206378 Manufacturer: IVO Model 57d Serial Number 0
9373 20:15:22.209740 Made week 0 of 2020
9374 20:15:22.212823 EDID version: 1.4
9375 20:15:22.213372 Digital display
9376 20:15:22.216419 6 bits per primary color channel
9377 20:15:22.216840 DisplayPort interface
9378 20:15:22.219496 Maximum image size: 31 cm x 17 cm
9379 20:15:22.222916 Gamma: 220%
9380 20:15:22.223331 Check DPMS levels
9381 20:15:22.225938 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9382 20:15:22.232819 First detailed timing is preferred timing
9383 20:15:22.233341 Established timings supported:
9384 20:15:22.235867 Standard timings supported:
9385 20:15:22.239241 Detailed timings
9386 20:15:22.242868 Hex of detail: 383680a07038204018303c0035ae10000019
9387 20:15:22.249359 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9388 20:15:22.252569 0780 0798 07c8 0820 hborder 0
9389 20:15:22.255885 0438 043b 0447 0458 vborder 0
9390 20:15:22.259492 -hsync -vsync
9391 20:15:22.259911 Did detailed timing
9392 20:15:22.265540 Hex of detail: 000000000000000000000000000000000000
9393 20:15:22.269073 Manufacturer-specified data, tag 0
9394 20:15:22.272247 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9395 20:15:22.275840 ASCII string: InfoVision
9396 20:15:22.278905 Hex of detail: 000000fe00523134304e574635205248200a
9397 20:15:22.282201 ASCII string: R140NWF5 RH
9398 20:15:22.282619 Checksum
9399 20:15:22.285792 Checksum: 0xfb (valid)
9400 20:15:22.289034 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9401 20:15:22.292552 DSI data_rate: 832800000 bps
9402 20:15:22.298812 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9403 20:15:22.302216 anx7625_parse_edid: pixelclock(138800).
9404 20:15:22.305753 hactive(1920), hsync(48), hfp(24), hbp(88)
9405 20:15:22.308890 vactive(1080), vsync(12), vfp(3), vbp(17)
9406 20:15:22.312155 anx7625_dsi_config: config dsi.
9407 20:15:22.318824 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9408 20:15:22.332333 anx7625_dsi_config: success to config DSI
9409 20:15:22.335696 anx7625_dp_start: MIPI phy setup OK.
9410 20:15:22.338726 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9411 20:15:22.342169 mtk_ddp_mode_set invalid vrefresh 60
9412 20:15:22.345201 main_disp_path_setup
9413 20:15:22.345663 ovl_layer_smi_id_en
9414 20:15:22.349074 ovl_layer_smi_id_en
9415 20:15:22.349719 ccorr_config
9416 20:15:22.350267 aal_config
9417 20:15:22.352147 gamma_config
9418 20:15:22.352736 postmask_config
9419 20:15:22.355478 dither_config
9420 20:15:22.358457 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9421 20:15:22.365394 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9422 20:15:22.368397 Root Device init finished in 555 msecs
9423 20:15:22.371867 CPU_CLUSTER: 0 init
9424 20:15:22.378565 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9425 20:15:22.385018 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9426 20:15:22.385454 APU_MBOX 0x190000b0 = 0x10001
9427 20:15:22.388428 APU_MBOX 0x190001b0 = 0x10001
9428 20:15:22.391599 APU_MBOX 0x190005b0 = 0x10001
9429 20:15:22.395050 APU_MBOX 0x190006b0 = 0x10001
9430 20:15:22.401664 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9431 20:15:22.411136 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9432 20:15:22.423856 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9433 20:15:22.430272 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9434 20:15:22.441761 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9435 20:15:22.450902 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9436 20:15:22.454367 CPU_CLUSTER: 0 init finished in 81 msecs
9437 20:15:22.457595 Devices initialized
9438 20:15:22.461165 Show all devs... After init.
9439 20:15:22.461634 Root Device: enabled 1
9440 20:15:22.464374 CPU_CLUSTER: 0: enabled 1
9441 20:15:22.467764 CPU: 00: enabled 1
9442 20:15:22.470825 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9443 20:15:22.474299 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9444 20:15:22.477377 ELOG: NV offset 0x57f000 size 0x1000
9445 20:15:22.484150 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9446 20:15:22.490596 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9447 20:15:22.494100 ELOG: Event(17) added with size 13 at 2024-03-03 20:15:23 UTC
9448 20:15:22.500716 out: cmd=0x121: 03 db 21 01 00 00 00 00
9449 20:15:22.503704 in-header: 03 44 00 00 2c 00 00 00
9450 20:15:22.516972 in-data: 1a 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9451 20:15:22.520337 ELOG: Event(A1) added with size 10 at 2024-03-03 20:15:23 UTC
9452 20:15:22.526758 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9453 20:15:22.533074 ELOG: Event(A0) added with size 9 at 2024-03-03 20:15:23 UTC
9454 20:15:22.536440 elog_add_boot_reason: Logged dev mode boot
9455 20:15:22.543225 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9456 20:15:22.543305 Finalize devices...
9457 20:15:22.546340 Devices finalized
9458 20:15:22.549855 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9459 20:15:22.552937 Writing coreboot table at 0xffe64000
9460 20:15:22.556207 0. 000000000010a000-0000000000113fff: RAMSTAGE
9461 20:15:22.563088 1. 0000000040000000-00000000400fffff: RAM
9462 20:15:22.566407 2. 0000000040100000-000000004032afff: RAMSTAGE
9463 20:15:22.569442 3. 000000004032b000-00000000545fffff: RAM
9464 20:15:22.573080 4. 0000000054600000-000000005465ffff: BL31
9465 20:15:22.576305 5. 0000000054660000-00000000ffe63fff: RAM
9466 20:15:22.582844 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9467 20:15:22.586241 7. 0000000100000000-000000023fffffff: RAM
9468 20:15:22.589512 Passing 5 GPIOs to payload:
9469 20:15:22.592917 NAME | PORT | POLARITY | VALUE
9470 20:15:22.599422 EC in RW | 0x000000aa | low | undefined
9471 20:15:22.602688 EC interrupt | 0x00000005 | low | undefined
9472 20:15:22.606049 TPM interrupt | 0x000000ab | high | undefined
9473 20:15:22.612841 SD card detect | 0x00000011 | high | undefined
9474 20:15:22.616153 speaker enable | 0x00000093 | high | undefined
9475 20:15:22.619349 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9476 20:15:22.622723 in-header: 03 f9 00 00 02 00 00 00
9477 20:15:22.625732 in-data: 02 00
9478 20:15:22.629027 ADC[4]: Raw value=894081 ID=7
9479 20:15:22.629096 ADC[3]: Raw value=212700 ID=1
9480 20:15:22.632246 RAM Code: 0x71
9481 20:15:22.635536 ADC[6]: Raw value=74722 ID=0
9482 20:15:22.635616 ADC[5]: Raw value=211590 ID=1
9483 20:15:22.639049 SKU Code: 0x1
9484 20:15:22.645389 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 18ab
9485 20:15:22.645519 coreboot table: 964 bytes.
9486 20:15:22.649050 IMD ROOT 0. 0xfffff000 0x00001000
9487 20:15:22.652146 IMD SMALL 1. 0xffffe000 0x00001000
9488 20:15:22.655585 RO MCACHE 2. 0xffffc000 0x00001104
9489 20:15:22.658983 CONSOLE 3. 0xfff7c000 0x00080000
9490 20:15:22.662088 FMAP 4. 0xfff7b000 0x00000452
9491 20:15:22.665585 TIME STAMP 5. 0xfff7a000 0x00000910
9492 20:15:22.668673 VBOOT WORK 6. 0xfff66000 0x00014000
9493 20:15:22.672102 RAMOOPS 7. 0xffe66000 0x00100000
9494 20:15:22.675384 COREBOOT 8. 0xffe64000 0x00002000
9495 20:15:22.678653 IMD small region:
9496 20:15:22.681934 IMD ROOT 0. 0xffffec00 0x00000400
9497 20:15:22.685273 VPD 1. 0xffffeb80 0x0000006c
9498 20:15:22.688647 MMC STATUS 2. 0xffffeb60 0x00000004
9499 20:15:22.691744 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9500 20:15:22.694999 Probing TPM: done!
9501 20:15:22.698739 Connected to device vid:did:rid of 1ae0:0028:00
9502 20:15:22.709800 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9503 20:15:22.713105 Initialized TPM device CR50 revision 0
9504 20:15:22.716924 Checking cr50 for pending updates
9505 20:15:22.720749 Reading cr50 TPM mode
9506 20:15:22.728906 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9507 20:15:22.735618 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9508 20:15:22.775629 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9509 20:15:22.779185 Checking segment from ROM address 0x40100000
9510 20:15:22.782682 Checking segment from ROM address 0x4010001c
9511 20:15:22.788914 Loading segment from ROM address 0x40100000
9512 20:15:22.788996 code (compression=0)
9513 20:15:22.798994 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9514 20:15:22.805663 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9515 20:15:22.805745 it's not compressed!
9516 20:15:22.812432 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9517 20:15:22.819033 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9518 20:15:22.836258 Loading segment from ROM address 0x4010001c
9519 20:15:22.836342 Entry Point 0x80000000
9520 20:15:22.839568 Loaded segments
9521 20:15:22.842895 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9522 20:15:22.849731 Jumping to boot code at 0x80000000(0xffe64000)
9523 20:15:22.856241 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9524 20:15:22.862719 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9525 20:15:22.870759 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9526 20:15:22.874256 Checking segment from ROM address 0x40100000
9527 20:15:22.877184 Checking segment from ROM address 0x4010001c
9528 20:15:22.884146 Loading segment from ROM address 0x40100000
9529 20:15:22.884227 code (compression=1)
9530 20:15:22.890929 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9531 20:15:22.900773 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9532 20:15:22.900887 using LZMA
9533 20:15:22.909269 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9534 20:15:22.915763 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9535 20:15:22.919219 Loading segment from ROM address 0x4010001c
9536 20:15:22.919306 Entry Point 0x54601000
9537 20:15:22.922725 Loaded segments
9538 20:15:22.925778 NOTICE: MT8192 bl31_setup
9539 20:15:22.932654 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9540 20:15:22.935887 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9541 20:15:22.939452 WARNING: region 0:
9542 20:15:22.942943 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 20:15:22.943136 WARNING: region 1:
9544 20:15:22.949545 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9545 20:15:22.952922 WARNING: region 2:
9546 20:15:22.956060 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9547 20:15:22.959498 WARNING: region 3:
9548 20:15:22.962875 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9549 20:15:22.966259 WARNING: region 4:
9550 20:15:22.972957 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9551 20:15:22.973341 WARNING: region 5:
9552 20:15:22.976533 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 20:15:22.980013 WARNING: region 6:
9554 20:15:22.982862 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 20:15:22.986421 WARNING: region 7:
9556 20:15:22.989548 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 20:15:22.996204 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9558 20:15:22.999820 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9559 20:15:23.002740 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9560 20:15:23.009458 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9561 20:15:23.012976 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9562 20:15:23.016425 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9563 20:15:23.023045 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9564 20:15:23.026163 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9565 20:15:23.032917 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9566 20:15:23.036212 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9567 20:15:23.039708 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9568 20:15:23.046214 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9569 20:15:23.049655 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9570 20:15:23.052972 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9571 20:15:23.059697 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9572 20:15:23.062870 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9573 20:15:23.069320 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9574 20:15:23.072789 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9575 20:15:23.076134 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9576 20:15:23.082875 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9577 20:15:23.086210 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9578 20:15:23.089627 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9579 20:15:23.096355 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9580 20:15:23.099479 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9581 20:15:23.105982 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9582 20:15:23.109394 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9583 20:15:23.112732 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9584 20:15:23.119478 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9585 20:15:23.122856 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9586 20:15:23.129357 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9587 20:15:23.132843 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9588 20:15:23.136388 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9589 20:15:23.142594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9590 20:15:23.146168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9591 20:15:23.149532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9592 20:15:23.152690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9593 20:15:23.159299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9594 20:15:23.162971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9595 20:15:23.166350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9596 20:15:23.169546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9597 20:15:23.176155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9598 20:15:23.179281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9599 20:15:23.182688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9600 20:15:23.186018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9601 20:15:23.192667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9602 20:15:23.195864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9603 20:15:23.199442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9604 20:15:23.202789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9605 20:15:23.209629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9606 20:15:23.212723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9607 20:15:23.219529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9608 20:15:23.222643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9609 20:15:23.229223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9610 20:15:23.232776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9611 20:15:23.236225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9612 20:15:23.242897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9613 20:15:23.246148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9614 20:15:23.252908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9615 20:15:23.256158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9616 20:15:23.262773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9617 20:15:23.266232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9618 20:15:23.269413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9619 20:15:23.276079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9620 20:15:23.279480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9621 20:15:23.286279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9622 20:15:23.289431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9623 20:15:23.295890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9624 20:15:23.299372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9625 20:15:23.302844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9626 20:15:23.309425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9627 20:15:23.312638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9628 20:15:23.319255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9629 20:15:23.322910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9630 20:15:23.329432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9631 20:15:23.332708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9632 20:15:23.335760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9633 20:15:23.342360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9634 20:15:23.346030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9635 20:15:23.352512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9636 20:15:23.356041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9637 20:15:23.362486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9638 20:15:23.365938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9639 20:15:23.372688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9640 20:15:23.375888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9641 20:15:23.379265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9642 20:15:23.385955 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9643 20:15:23.389001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9644 20:15:23.395769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9645 20:15:23.399099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9646 20:15:23.405906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9647 20:15:23.409082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9648 20:15:23.412245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9649 20:15:23.418798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9650 20:15:23.421978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9651 20:15:23.428914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9652 20:15:23.432316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9653 20:15:23.435508 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9654 20:15:23.441960 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9655 20:15:23.445392 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9656 20:15:23.448417 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9657 20:15:23.451927 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9658 20:15:23.458501 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9659 20:15:23.461701 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9660 20:15:23.468520 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9661 20:15:23.471728 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9662 20:15:23.475452 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9663 20:15:23.481796 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9664 20:15:23.485249 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9665 20:15:23.491701 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9666 20:15:23.495080 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9667 20:15:23.498237 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9668 20:15:23.505225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9669 20:15:23.508289 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9670 20:15:23.515262 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9671 20:15:23.518352 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9672 20:15:23.521763 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9673 20:15:23.528327 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9674 20:15:23.531597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9675 20:15:23.534986 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9676 20:15:23.541742 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9677 20:15:23.545041 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9678 20:15:23.548472 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9679 20:15:23.551709 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9680 20:15:23.558188 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9681 20:15:23.561874 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9682 20:15:23.565417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9683 20:15:23.571993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9684 20:15:23.575298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9685 20:15:23.582042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9686 20:15:23.585308 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9687 20:15:23.588697 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9688 20:15:23.595100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9689 20:15:23.598477 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9690 20:15:23.605274 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9691 20:15:23.608494 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9692 20:15:23.611882 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9693 20:15:23.618450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9694 20:15:23.621705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9695 20:15:23.624931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9696 20:15:23.631618 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9697 20:15:23.634919 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9698 20:15:23.641938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9699 20:15:23.645204 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9700 20:15:23.648485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9701 20:15:23.655291 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9702 20:15:23.658442 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9703 20:15:23.665138 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9704 20:15:23.668472 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9705 20:15:23.672128 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9706 20:15:23.678622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9707 20:15:23.681789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9708 20:15:23.685073 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9709 20:15:23.692074 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9710 20:15:23.695213 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9711 20:15:23.702011 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9712 20:15:23.705544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9713 20:15:23.708832 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9714 20:15:23.715591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9715 20:15:23.718572 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9716 20:15:23.721869 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9717 20:15:23.728735 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9718 20:15:23.732146 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9719 20:15:23.738407 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9720 20:15:23.741852 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9721 20:15:23.745454 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9722 20:15:23.751675 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9723 20:15:23.755647 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9724 20:15:23.761606 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9725 20:15:23.764927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9726 20:15:23.768292 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9727 20:15:23.774956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9728 20:15:23.778505 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9729 20:15:23.784915 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9730 20:15:23.788481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9731 20:15:23.791465 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9732 20:15:23.798239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9733 20:15:23.801546 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9734 20:15:23.808079 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9735 20:15:23.811519 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9736 20:15:23.814668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9737 20:15:23.821232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9738 20:15:23.824835 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9739 20:15:23.831291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9740 20:15:23.834822 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9741 20:15:23.837673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9742 20:15:23.844244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9743 20:15:23.847587 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9744 20:15:23.853941 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9745 20:15:23.857548 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9746 20:15:23.860701 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9747 20:15:23.867545 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9748 20:15:23.870616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9749 20:15:23.877228 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9750 20:15:23.880485 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9751 20:15:23.887226 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9752 20:15:23.890734 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9753 20:15:23.893796 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9754 20:15:23.900796 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9755 20:15:23.903851 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9756 20:15:23.910713 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9757 20:15:23.913755 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9758 20:15:23.917062 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9759 20:15:23.923832 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9760 20:15:23.927267 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9761 20:15:23.933968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9762 20:15:23.936800 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9763 20:15:23.943893 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9764 20:15:23.946984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9765 20:15:23.950252 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9766 20:15:23.957175 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9767 20:15:23.960439 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9768 20:15:23.966924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9769 20:15:23.970085 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9770 20:15:23.976950 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9771 20:15:23.980152 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9772 20:15:23.983335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9773 20:15:23.989964 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9774 20:15:23.993282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9775 20:15:24.000338 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9776 20:15:24.003246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9777 20:15:24.006551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9778 20:15:24.013179 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9779 20:15:24.016810 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9780 20:15:24.023433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9781 20:15:24.026552 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9782 20:15:24.030162 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9783 20:15:24.036661 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9784 20:15:24.040097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9785 20:15:24.046766 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9786 20:15:24.050032 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9787 20:15:24.053298 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9788 20:15:24.056565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9789 20:15:24.062980 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9790 20:15:24.066324 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9791 20:15:24.069581 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9792 20:15:24.076699 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9793 20:15:24.079877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9794 20:15:24.083320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9795 20:15:24.089798 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9796 20:15:24.093184 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9797 20:15:24.096346 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9798 20:15:24.103110 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9799 20:15:24.106381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9800 20:15:24.109539 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9801 20:15:24.116281 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9802 20:15:24.119784 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9803 20:15:24.126430 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9804 20:15:24.129696 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9805 20:15:24.132822 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9806 20:15:24.139288 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9807 20:15:24.142805 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9808 20:15:24.149320 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9809 20:15:24.152611 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9810 20:15:24.156180 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9811 20:15:24.162600 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9812 20:15:24.165833 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9813 20:15:24.169441 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9814 20:15:24.175776 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9815 20:15:24.179126 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9816 20:15:24.182534 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9817 20:15:24.189011 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9818 20:15:24.192402 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9819 20:15:24.198852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9820 20:15:24.202366 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9821 20:15:24.205766 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9822 20:15:24.212495 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9823 20:15:24.215933 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9824 20:15:24.219081 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9825 20:15:24.225678 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9826 20:15:24.229012 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9827 20:15:24.232260 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9828 20:15:24.235607 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9829 20:15:24.242168 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9830 20:15:24.245427 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9831 20:15:24.249004 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9832 20:15:24.252215 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9833 20:15:24.258744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9834 20:15:24.261948 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9835 20:15:24.265363 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9836 20:15:24.268856 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9837 20:15:24.275136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9838 20:15:24.278405 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9839 20:15:24.281789 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9840 20:15:24.288543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9841 20:15:24.291940 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9842 20:15:24.298457 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9843 20:15:24.301953 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9844 20:15:24.308552 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9845 20:15:24.311479 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9846 20:15:24.314904 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9847 20:15:24.321459 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9848 20:15:24.324974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9849 20:15:24.331936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9850 20:15:24.334925 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9851 20:15:24.338397 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9852 20:15:24.345007 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9853 20:15:24.348287 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9854 20:15:24.351473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9855 20:15:24.358137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9856 20:15:24.361518 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9857 20:15:24.367996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9858 20:15:24.371344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9859 20:15:24.377923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9860 20:15:24.381587 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9861 20:15:24.384727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9862 20:15:24.391520 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9863 20:15:24.394941 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9864 20:15:24.401354 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9865 20:15:24.404648 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9866 20:15:24.407812 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9867 20:15:24.414581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9868 20:15:24.418129 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9869 20:15:24.424632 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9870 20:15:24.427691 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9871 20:15:24.431186 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9872 20:15:24.437729 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9873 20:15:24.440795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9874 20:15:24.447662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9875 20:15:24.451000 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9876 20:15:24.457573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9877 20:15:24.460625 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9878 20:15:24.464116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9879 20:15:24.470810 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9880 20:15:24.474131 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9881 20:15:24.480696 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9882 20:15:24.484056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9883 20:15:24.490443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9884 20:15:24.494061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9885 20:15:24.497233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9886 20:15:24.503691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9887 20:15:24.507108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9888 20:15:24.513624 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9889 20:15:24.516729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9890 20:15:24.520115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9891 20:15:24.526985 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9892 20:15:24.530162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9893 20:15:24.537105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9894 20:15:24.540200 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9895 20:15:24.543453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9896 20:15:24.550089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9897 20:15:24.553151 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9898 20:15:24.559979 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9899 20:15:24.563413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9900 20:15:24.569972 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9901 20:15:24.573058 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9902 20:15:24.576478 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9903 20:15:24.583257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9904 20:15:24.586445 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9905 20:15:24.592905 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9906 20:15:24.596526 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9907 20:15:24.599583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9908 20:15:24.606315 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9909 20:15:24.609537 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9910 20:15:24.616181 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9911 20:15:24.619330 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9912 20:15:24.626043 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9913 20:15:24.629316 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9914 20:15:24.632738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9915 20:15:24.639699 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9916 20:15:24.642517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9917 20:15:24.649365 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9918 20:15:24.653002 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9919 20:15:24.659483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9920 20:15:24.662660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9921 20:15:24.666183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9922 20:15:24.673054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9923 20:15:24.675877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9924 20:15:24.682811 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9925 20:15:24.685834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9926 20:15:24.692775 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9927 20:15:24.695763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9928 20:15:24.699078 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9929 20:15:24.705731 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9930 20:15:24.709231 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9931 20:15:24.715894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9932 20:15:24.719050 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9933 20:15:24.725705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9934 20:15:24.729164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9935 20:15:24.732211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9936 20:15:24.738979 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9937 20:15:24.742515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9938 20:15:24.749060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9939 20:15:24.752333 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9940 20:15:24.758780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9941 20:15:24.762103 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9942 20:15:24.765955 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9943 20:15:24.772416 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9944 20:15:24.775421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9945 20:15:24.782033 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9946 20:15:24.785610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9947 20:15:24.792213 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9948 20:15:24.795621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9949 20:15:24.802403 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9950 20:15:24.805389 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9951 20:15:24.808787 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9952 20:15:24.815646 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9953 20:15:24.818890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9954 20:15:24.825271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9955 20:15:24.828454 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9956 20:15:24.835214 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9957 20:15:24.838455 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9958 20:15:24.842006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9959 20:15:24.848500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9960 20:15:24.852012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9961 20:15:24.858434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9962 20:15:24.861872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9963 20:15:24.868236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9964 20:15:24.871840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9965 20:15:24.878446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9966 20:15:24.881804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9967 20:15:24.888346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9968 20:15:24.891732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9969 20:15:24.898171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9970 20:15:24.901450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9971 20:15:24.908062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9972 20:15:24.911539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9973 20:15:24.918340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9974 20:15:24.921273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9975 20:15:24.924716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9976 20:15:24.931440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9977 20:15:24.934547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9978 20:15:24.941307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9979 20:15:24.944447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9980 20:15:24.951044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9981 20:15:24.954303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9982 20:15:24.960933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9983 20:15:24.967726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9984 20:15:24.971166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9985 20:15:24.977990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9986 20:15:24.981020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9987 20:15:24.987707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9988 20:15:24.990558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9989 20:15:24.997584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9990 20:15:25.002246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9991 20:15:25.004239 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9992 20:15:25.007252 INFO: [APUAPC] vio 0
9993 20:15:25.010664 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9994 20:15:25.017811 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9995 20:15:25.020785 INFO: [APUAPC] D0_APC_0: 0x400510
9996 20:15:25.024262 INFO: [APUAPC] D0_APC_1: 0x0
9997 20:15:25.027445 INFO: [APUAPC] D0_APC_2: 0x1540
9998 20:15:25.027885 INFO: [APUAPC] D0_APC_3: 0x0
9999 20:15:25.030963 INFO: [APUAPC] D1_APC_0: 0xffffffff
10000 20:15:25.037392 INFO: [APUAPC] D1_APC_1: 0xffffffff
10001 20:15:25.037874 INFO: [APUAPC] D1_APC_2: 0x3fffff
10002 20:15:25.040731 INFO: [APUAPC] D1_APC_3: 0x0
10003 20:15:25.044015 INFO: [APUAPC] D2_APC_0: 0xffffffff
10004 20:15:25.047257 INFO: [APUAPC] D2_APC_1: 0xffffffff
10005 20:15:25.050962 INFO: [APUAPC] D2_APC_2: 0x3fffff
10006 20:15:25.054118 INFO: [APUAPC] D2_APC_3: 0x0
10007 20:15:25.057516 INFO: [APUAPC] D3_APC_0: 0xffffffff
10008 20:15:25.060596 INFO: [APUAPC] D3_APC_1: 0xffffffff
10009 20:15:25.063981 INFO: [APUAPC] D3_APC_2: 0x3fffff
10010 20:15:25.067424 INFO: [APUAPC] D3_APC_3: 0x0
10011 20:15:25.070441 INFO: [APUAPC] D4_APC_0: 0xffffffff
10012 20:15:25.074041 INFO: [APUAPC] D4_APC_1: 0xffffffff
10013 20:15:25.077097 INFO: [APUAPC] D4_APC_2: 0x3fffff
10014 20:15:25.080781 INFO: [APUAPC] D4_APC_3: 0x0
10015 20:15:25.083682 INFO: [APUAPC] D5_APC_0: 0xffffffff
10016 20:15:25.087229 INFO: [APUAPC] D5_APC_1: 0xffffffff
10017 20:15:25.090604 INFO: [APUAPC] D5_APC_2: 0x3fffff
10018 20:15:25.093666 INFO: [APUAPC] D5_APC_3: 0x0
10019 20:15:25.097297 INFO: [APUAPC] D6_APC_0: 0xffffffff
10020 20:15:25.100220 INFO: [APUAPC] D6_APC_1: 0xffffffff
10021 20:15:25.103673 INFO: [APUAPC] D6_APC_2: 0x3fffff
10022 20:15:25.106817 INFO: [APUAPC] D6_APC_3: 0x0
10023 20:15:25.110191 INFO: [APUAPC] D7_APC_0: 0xffffffff
10024 20:15:25.113583 INFO: [APUAPC] D7_APC_1: 0xffffffff
10025 20:15:25.117305 INFO: [APUAPC] D7_APC_2: 0x3fffff
10026 20:15:25.120409 INFO: [APUAPC] D7_APC_3: 0x0
10027 20:15:25.123911 INFO: [APUAPC] D8_APC_0: 0xffffffff
10028 20:15:25.127405 INFO: [APUAPC] D8_APC_1: 0xffffffff
10029 20:15:25.130420 INFO: [APUAPC] D8_APC_2: 0x3fffff
10030 20:15:25.133547 INFO: [APUAPC] D8_APC_3: 0x0
10031 20:15:25.136937 INFO: [APUAPC] D9_APC_0: 0xffffffff
10032 20:15:25.140334 INFO: [APUAPC] D9_APC_1: 0xffffffff
10033 20:15:25.143338 INFO: [APUAPC] D9_APC_2: 0x3fffff
10034 20:15:25.146898 INFO: [APUAPC] D9_APC_3: 0x0
10035 20:15:25.150184 INFO: [APUAPC] D10_APC_0: 0xffffffff
10036 20:15:25.153316 INFO: [APUAPC] D10_APC_1: 0xffffffff
10037 20:15:25.156640 INFO: [APUAPC] D10_APC_2: 0x3fffff
10038 20:15:25.159911 INFO: [APUAPC] D10_APC_3: 0x0
10039 20:15:25.163309 INFO: [APUAPC] D11_APC_0: 0xffffffff
10040 20:15:25.166805 INFO: [APUAPC] D11_APC_1: 0xffffffff
10041 20:15:25.169763 INFO: [APUAPC] D11_APC_2: 0x3fffff
10042 20:15:25.173084 INFO: [APUAPC] D11_APC_3: 0x0
10043 20:15:25.176665 INFO: [APUAPC] D12_APC_0: 0xffffffff
10044 20:15:25.179809 INFO: [APUAPC] D12_APC_1: 0xffffffff
10045 20:15:25.183301 INFO: [APUAPC] D12_APC_2: 0x3fffff
10046 20:15:25.186525 INFO: [APUAPC] D12_APC_3: 0x0
10047 20:15:25.189803 INFO: [APUAPC] D13_APC_0: 0xffffffff
10048 20:15:25.193257 INFO: [APUAPC] D13_APC_1: 0xffffffff
10049 20:15:25.196503 INFO: [APUAPC] D13_APC_2: 0x3fffff
10050 20:15:25.199732 INFO: [APUAPC] D13_APC_3: 0x0
10051 20:15:25.203245 INFO: [APUAPC] D14_APC_0: 0xffffffff
10052 20:15:25.206441 INFO: [APUAPC] D14_APC_1: 0xffffffff
10053 20:15:25.209690 INFO: [APUAPC] D14_APC_2: 0x3fffff
10054 20:15:25.212974 INFO: [APUAPC] D14_APC_3: 0x0
10055 20:15:25.216085 INFO: [APUAPC] D15_APC_0: 0xffffffff
10056 20:15:25.219599 INFO: [APUAPC] D15_APC_1: 0xffffffff
10057 20:15:25.223079 INFO: [APUAPC] D15_APC_2: 0x3fffff
10058 20:15:25.226347 INFO: [APUAPC] D15_APC_3: 0x0
10059 20:15:25.229322 INFO: [APUAPC] APC_CON: 0x4
10060 20:15:25.232925 INFO: [NOCDAPC] D0_APC_0: 0x0
10061 20:15:25.236312 INFO: [NOCDAPC] D0_APC_1: 0x0
10062 20:15:25.236725 INFO: [NOCDAPC] D1_APC_0: 0x0
10063 20:15:25.239774 INFO: [NOCDAPC] D1_APC_1: 0xfff
10064 20:15:25.242672 INFO: [NOCDAPC] D2_APC_0: 0x0
10065 20:15:25.246333 INFO: [NOCDAPC] D2_APC_1: 0xfff
10066 20:15:25.249171 INFO: [NOCDAPC] D3_APC_0: 0x0
10067 20:15:25.252696 INFO: [NOCDAPC] D3_APC_1: 0xfff
10068 20:15:25.256023 INFO: [NOCDAPC] D4_APC_0: 0x0
10069 20:15:25.259379 INFO: [NOCDAPC] D4_APC_1: 0xfff
10070 20:15:25.262635 INFO: [NOCDAPC] D5_APC_0: 0x0
10071 20:15:25.266149 INFO: [NOCDAPC] D5_APC_1: 0xfff
10072 20:15:25.269251 INFO: [NOCDAPC] D6_APC_0: 0x0
10073 20:15:25.269711 INFO: [NOCDAPC] D6_APC_1: 0xfff
10074 20:15:25.272777 INFO: [NOCDAPC] D7_APC_0: 0x0
10075 20:15:25.275772 INFO: [NOCDAPC] D7_APC_1: 0xfff
10076 20:15:25.279220 INFO: [NOCDAPC] D8_APC_0: 0x0
10077 20:15:25.282383 INFO: [NOCDAPC] D8_APC_1: 0xfff
10078 20:15:25.286118 INFO: [NOCDAPC] D9_APC_0: 0x0
10079 20:15:25.288924 INFO: [NOCDAPC] D9_APC_1: 0xfff
10080 20:15:25.292302 INFO: [NOCDAPC] D10_APC_0: 0x0
10081 20:15:25.295587 INFO: [NOCDAPC] D10_APC_1: 0xfff
10082 20:15:25.299050 INFO: [NOCDAPC] D11_APC_0: 0x0
10083 20:15:25.302532 INFO: [NOCDAPC] D11_APC_1: 0xfff
10084 20:15:25.305597 INFO: [NOCDAPC] D12_APC_0: 0x0
10085 20:15:25.309013 INFO: [NOCDAPC] D12_APC_1: 0xfff
10086 20:15:25.312358 INFO: [NOCDAPC] D13_APC_0: 0x0
10087 20:15:25.312766 INFO: [NOCDAPC] D13_APC_1: 0xfff
10088 20:15:25.315650 INFO: [NOCDAPC] D14_APC_0: 0x0
10089 20:15:25.318876 INFO: [NOCDAPC] D14_APC_1: 0xfff
10090 20:15:25.322132 INFO: [NOCDAPC] D15_APC_0: 0x0
10091 20:15:25.325657 INFO: [NOCDAPC] D15_APC_1: 0xfff
10092 20:15:25.329154 INFO: [NOCDAPC] APC_CON: 0x4
10093 20:15:25.332456 INFO: [APUAPC] set_apusys_apc done
10094 20:15:25.335467 INFO: [DEVAPC] devapc_init done
10095 20:15:25.338852 INFO: GICv3 without legacy support detected.
10096 20:15:25.341951 INFO: ARM GICv3 driver initialized in EL3
10097 20:15:25.348703 INFO: Maximum SPI INTID supported: 639
10098 20:15:25.352299 INFO: BL31: Initializing runtime services
10099 20:15:25.358666 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10100 20:15:25.359125 INFO: SPM: enable CPC mode
10101 20:15:25.365076 INFO: mcdi ready for mcusys-off-idle and system suspend
10102 20:15:25.368571 INFO: BL31: Preparing for EL3 exit to normal world
10103 20:15:25.375129 INFO: Entry point address = 0x80000000
10104 20:15:25.375543 INFO: SPSR = 0x8
10105 20:15:25.381107
10106 20:15:25.381556
10107 20:15:25.381897
10108 20:15:25.384450 Starting depthcharge on Spherion...
10109 20:15:25.384864
10110 20:15:25.385191 Wipe memory regions:
10111 20:15:25.385539
10112 20:15:25.388060 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10113 20:15:25.388560 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10114 20:15:25.388959 Setting prompt string to ['asurada:']
10115 20:15:25.389380 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10116 20:15:25.390119 [0x00000040000000, 0x00000054600000)
10117 20:15:25.510290
10118 20:15:25.510765 [0x00000054660000, 0x00000080000000)
10119 20:15:25.770468
10120 20:15:25.770974 [0x000000821a7280, 0x000000ffe64000)
10121 20:15:26.514424
10122 20:15:26.514583 [0x00000100000000, 0x00000240000000)
10123 20:15:28.403332
10124 20:15:28.406197 Initializing XHCI USB controller at 0x11200000.
10125 20:15:29.444090
10126 20:15:29.446929 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10127 20:15:29.447387
10128 20:15:29.447736
10129 20:15:29.448052
10130 20:15:29.448823 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10132 20:15:29.549954 asurada: tftpboot 192.168.201.1 12928144/tftp-deploy-p_3bgsc4/kernel/image.itb 12928144/tftp-deploy-p_3bgsc4/kernel/cmdline
10133 20:15:29.550530 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10134 20:15:29.551096 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10135 20:15:29.555150 tftpboot 192.168.201.1 12928144/tftp-deploy-p_3bgsc4/kernel/image.itp-deploy-p_3bgsc4/kernel/cmdline
10136 20:15:29.555561
10137 20:15:29.555885 Waiting for link
10138 20:15:29.715616
10139 20:15:29.716079 R8152: Initializing
10140 20:15:29.716417
10141 20:15:29.718878 Version 6 (ocp_data = 5c30)
10142 20:15:29.719295
10143 20:15:29.722292 R8152: Done initializing
10144 20:15:29.722839
10145 20:15:29.723298 Adding net device
10146 20:15:31.623473
10147 20:15:31.624022 done.
10148 20:15:31.624438
10149 20:15:31.624934 MAC: 00:24:32:30:78:ff
10150 20:15:31.625350
10151 20:15:31.626644 Sending DHCP discover... done.
10152 20:15:31.627116
10153 20:15:31.629911 Waiting for reply... done.
10154 20:15:31.630375
10155 20:15:31.633381 Sending DHCP request... done.
10156 20:15:31.633883
10157 20:15:31.636898 Waiting for reply... done.
10158 20:15:31.637354
10159 20:15:31.637786 My ip is 192.168.201.21
10160 20:15:31.638165
10161 20:15:31.639884 The DHCP server ip is 192.168.201.1
10162 20:15:31.640343
10163 20:15:31.643265 TFTP server IP predefined by user: 192.168.201.1
10164 20:15:31.646582
10165 20:15:31.649827 Bootfile predefined by user: 12928144/tftp-deploy-p_3bgsc4/kernel/image.itb
10166 20:15:31.653199
10167 20:15:31.653708 Sending tftp read request... done.
10168 20:15:31.654091
10169 20:15:31.663014 Waiting for the transfer...
10170 20:15:31.663564
10171 20:15:32.347489 00000000 ################################################################
10172 20:15:32.347983
10173 20:15:32.978163 00080000 ################################################################
10174 20:15:32.978309
10175 20:15:33.551012 00100000 ################################################################
10176 20:15:33.551148
10177 20:15:34.120676 00180000 ################################################################
10178 20:15:34.120822
10179 20:15:34.763392 00200000 ################################################################
10180 20:15:34.764060
10181 20:15:35.358789 00280000 ################################################################
10182 20:15:35.358933
10183 20:15:35.983026 00300000 ################################################################
10184 20:15:35.983550
10185 20:15:36.664189 00380000 ################################################################
10186 20:15:36.664733
10187 20:15:37.361999 00400000 ################################################################
10188 20:15:37.362517
10189 20:15:38.045301 00480000 ################################################################
10190 20:15:38.045846
10191 20:15:38.654228 00500000 ################################################################
10192 20:15:38.654361
10193 20:15:39.314558 00580000 ################################################################
10194 20:15:39.315080
10195 20:15:40.011582 00600000 ################################################################
10196 20:15:40.012206
10197 20:15:40.695602 00680000 ################################################################
10198 20:15:40.696118
10199 20:15:41.382443 00700000 ################################################################
10200 20:15:41.382941
10201 20:15:41.998829 00780000 ################################################################
10202 20:15:41.998974
10203 20:15:42.556066 00800000 ################################################################
10204 20:15:42.556237
10205 20:15:43.115932 00880000 ################################################################
10206 20:15:43.116071
10207 20:15:43.752344 00900000 ################################################################
10208 20:15:43.753024
10209 20:15:44.439624 00980000 ################################################################
10210 20:15:44.440224
10211 20:15:45.046568 00a00000 ################################################################
10212 20:15:45.046718
10213 20:15:45.665386 00a80000 ################################################################
10214 20:15:45.666014
10215 20:15:46.368488 00b00000 ################################################################
10216 20:15:46.369051
10217 20:15:47.048362 00b80000 ################################################################
10218 20:15:47.048881
10219 20:15:47.736408 00c00000 ################################################################
10220 20:15:47.736546
10221 20:15:48.317454 00c80000 ################################################################
10222 20:15:48.317607
10223 20:15:48.918305 00d00000 ################################################################
10224 20:15:48.918476
10225 20:15:49.562991 00d80000 ################################################################
10226 20:15:49.563589
10227 20:15:50.157609 00e00000 ################################################################
10228 20:15:50.157754
10229 20:15:50.738374 00e80000 ################################################################
10230 20:15:50.738508
10231 20:15:51.299903 00f00000 ################################################################
10232 20:15:51.300059
10233 20:15:51.875769 00f80000 ################################################################
10234 20:15:51.875912
10235 20:15:52.439310 01000000 ################################################################
10236 20:15:52.439465
10237 20:15:52.987791 01080000 ################################################################
10238 20:15:52.987996
10239 20:15:53.533660 01100000 ################################################################
10240 20:15:53.533809
10241 20:15:54.085919 01180000 ################################################################
10242 20:15:54.086075
10243 20:15:54.623618 01200000 ################################################################
10244 20:15:54.623760
10245 20:15:55.155726 01280000 ################################################################
10246 20:15:55.155862
10247 20:15:55.679784 01300000 ################################################################
10248 20:15:55.679930
10249 20:15:56.211825 01380000 ################################################################
10250 20:15:56.211968
10251 20:15:56.747896 01400000 ################################################################
10252 20:15:56.748047
10253 20:15:57.284145 01480000 ################################################################
10254 20:15:57.284289
10255 20:15:57.808860 01500000 ################################################################
10256 20:15:57.809012
10257 20:15:58.335074 01580000 ################################################################
10258 20:15:58.335228
10259 20:15:58.892604 01600000 ################################################################
10260 20:15:58.892753
10261 20:15:59.441999 01680000 ################################################################
10262 20:15:59.442152
10263 20:16:00.015428 01700000 ################################################################
10264 20:16:00.015574
10265 20:16:00.593355 01780000 ################################################################
10266 20:16:00.593554
10267 20:16:01.152775 01800000 ################################################################
10268 20:16:01.152925
10269 20:16:01.713362 01880000 ################################################################
10270 20:16:01.713573
10271 20:16:02.262982 01900000 ################################################################
10272 20:16:02.263144
10273 20:16:02.823275 01980000 ################################################################
10274 20:16:02.823486
10275 20:16:03.387929 01a00000 ################################################################
10276 20:16:03.388086
10277 20:16:03.939528 01a80000 ################################################################
10278 20:16:03.939692
10279 20:16:04.508065 01b00000 ################################################################
10280 20:16:04.508222
10281 20:16:05.064830 01b80000 ################################################################
10282 20:16:05.065006
10283 20:16:05.618146 01c00000 ################################################################
10284 20:16:05.618336
10285 20:16:05.653161 01c80000 #### done.
10286 20:16:05.653309
10287 20:16:05.656733 The bootfile was 29915202 bytes long.
10288 20:16:05.656836
10289 20:16:05.659824 Sending tftp read request... done.
10290 20:16:05.659903
10291 20:16:05.659966 Waiting for the transfer...
10292 20:16:05.660031
10293 20:16:05.663086 00000000 # done.
10294 20:16:05.663171
10295 20:16:05.670047 Command line loaded dynamically from TFTP file: 12928144/tftp-deploy-p_3bgsc4/kernel/cmdline
10296 20:16:05.670188
10297 20:16:05.693022 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10298 20:16:05.693178
10299 20:16:05.693279 Loading FIT.
10300 20:16:05.693379
10301 20:16:05.696399 Image ramdisk-1 has 17805849 bytes.
10302 20:16:05.696505
10303 20:16:05.699729 Image fdt-1 has 47278 bytes.
10304 20:16:05.699833
10305 20:16:05.703032 Image kernel-1 has 12060038 bytes.
10306 20:16:05.703145
10307 20:16:05.712936 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10308 20:16:05.713061
10309 20:16:05.729568 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10310 20:16:05.729719
10311 20:16:05.736208 Choosing best match conf-1 for compat google,spherion-rev2.
10312 20:16:05.736324
10313 20:16:05.743542 Connected to device vid:did:rid of 1ae0:0028:00
10314 20:16:05.751945
10315 20:16:05.755384 tpm_get_response: command 0x17b, return code 0x0
10316 20:16:05.755484
10317 20:16:05.758526 ec_init: CrosEC protocol v3 supported (256, 248)
10318 20:16:05.762399
10319 20:16:05.765713 tpm_cleanup: add release locality here.
10320 20:16:05.765804
10321 20:16:05.765887 Shutting down all USB controllers.
10322 20:16:05.769193
10323 20:16:05.769274 Removing current net device
10324 20:16:05.769374
10325 20:16:05.775852 Exiting depthcharge with code 4 at timestamp: 69726185
10326 20:16:05.775975
10327 20:16:05.779031 LZMA decompressing kernel-1 to 0x821a6718
10328 20:16:05.779117
10329 20:16:05.782676 LZMA decompressing kernel-1 to 0x40000000
10330 20:16:07.282011
10331 20:16:07.282162 jumping to kernel
10332 20:16:07.282652 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10333 20:16:07.282764 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10334 20:16:07.282876 Setting prompt string to ['Linux version [0-9]']
10335 20:16:07.282984 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10336 20:16:07.283089 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10337 20:16:07.364728
10338 20:16:07.367740 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10339 20:16:07.371282 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10340 20:16:07.371416 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10341 20:16:07.371524 Setting prompt string to []
10342 20:16:07.371645 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10343 20:16:07.371752 Using line separator: #'\n'#
10344 20:16:07.371845 No login prompt set.
10345 20:16:07.371947 Parsing kernel messages
10346 20:16:07.372041 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10347 20:16:07.372220 [login-action] Waiting for messages, (timeout 00:03:43)
10348 20:16:07.372323 Waiting using forced prompt support (timeout 00:01:52)
10349 20:16:07.391014 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10350 20:16:07.394477 [ 0.000000] random: crng init done
10351 20:16:07.401075 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10352 20:16:07.404223 [ 0.000000] efi: UEFI not found.
10353 20:16:07.410900 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10354 20:16:07.417741 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10355 20:16:07.427573 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10356 20:16:07.437563 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10357 20:16:07.443931 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10358 20:16:07.450623 [ 0.000000] printk: bootconsole [mtk8250] enabled
10359 20:16:07.457269 [ 0.000000] NUMA: No NUMA configuration found
10360 20:16:07.463907 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10361 20:16:07.466866 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10362 20:16:07.470524 [ 0.000000] Zone ranges:
10363 20:16:07.477036 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10364 20:16:07.480255 [ 0.000000] DMA32 empty
10365 20:16:07.487099 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10366 20:16:07.490457 [ 0.000000] Movable zone start for each node
10367 20:16:07.493547 [ 0.000000] Early memory node ranges
10368 20:16:07.500214 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10369 20:16:07.507090 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10370 20:16:07.513389 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10371 20:16:07.519869 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10372 20:16:07.526760 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10373 20:16:07.533075 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10374 20:16:07.589462 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10375 20:16:07.595856 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10376 20:16:07.602615 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10377 20:16:07.605658 [ 0.000000] psci: probing for conduit method from DT.
10378 20:16:07.612373 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10379 20:16:07.615811 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10380 20:16:07.622212 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10381 20:16:07.625424 [ 0.000000] psci: SMC Calling Convention v1.2
10382 20:16:07.632251 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10383 20:16:07.635299 [ 0.000000] Detected VIPT I-cache on CPU0
10384 20:16:07.642209 [ 0.000000] CPU features: detected: GIC system register CPU interface
10385 20:16:07.648672 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10386 20:16:07.655399 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10387 20:16:07.662180 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10388 20:16:07.671892 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10389 20:16:07.678406 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10390 20:16:07.681410 [ 0.000000] alternatives: applying boot alternatives
10391 20:16:07.688131 [ 0.000000] Fallback order for Node 0: 0
10392 20:16:07.694979 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10393 20:16:07.698382 [ 0.000000] Policy zone: Normal
10394 20:16:07.721562 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10395 20:16:07.731432 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10396 20:16:07.742010 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10397 20:16:07.752231 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10398 20:16:07.758820 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10399 20:16:07.761800 <6>[ 0.000000] software IO TLB: area num 8.
10400 20:16:07.818657 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10401 20:16:07.968409 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10402 20:16:07.974750 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10403 20:16:07.981437 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10404 20:16:07.984874 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10405 20:16:07.991251 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10406 20:16:07.998035 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10407 20:16:08.001421 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10408 20:16:08.011231 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10409 20:16:08.017788 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10410 20:16:08.024510 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10411 20:16:08.030951 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10412 20:16:08.034262 <6>[ 0.000000] GICv3: 608 SPIs implemented
10413 20:16:08.037513 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10414 20:16:08.044050 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10415 20:16:08.047761 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10416 20:16:08.054132 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10417 20:16:08.067501 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10418 20:16:08.080526 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10419 20:16:08.087263 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10420 20:16:08.094667 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10421 20:16:08.108173 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10422 20:16:08.114725 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10423 20:16:08.121216 <6>[ 0.009181] Console: colour dummy device 80x25
10424 20:16:08.131195 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10425 20:16:08.138048 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10426 20:16:08.141371 <6>[ 0.029221] LSM: Security Framework initializing
10427 20:16:08.147724 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 20:16:08.157876 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10429 20:16:08.164513 <6>[ 0.051372] cblist_init_generic: Setting adjustable number of callback queues.
10430 20:16:08.171094 <6>[ 0.058815] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 20:16:08.180778 <6>[ 0.065194] cblist_init_generic: Setting adjustable number of callback queues.
10432 20:16:08.187702 <6>[ 0.072622] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 20:16:08.190618 <6>[ 0.079059] rcu: Hierarchical SRCU implementation.
10434 20:16:08.197199 <6>[ 0.079061] rcu: Max phase no-delay instances is 1000.
10435 20:16:08.204100 <6>[ 0.079086] printk: bootconsole [mtk8250] printing thread started
10436 20:16:08.210447 <6>[ 0.097426] EFI services will not be available.
10437 20:16:08.213905 <6>[ 0.097630] smp: Bringing up secondary CPUs ...
10438 20:16:08.217025 <6>[ 0.097943] Detected VIPT I-cache on CPU1
10439 20:16:08.227095 <6>[ 0.098011] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10440 20:16:08.233492 <6>[ 0.098042] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10441 20:16:08.242875 <6>[ 0.125938] Detected VIPT I-cache on CPU2
10442 20:16:08.253006 <6>[ 0.125984] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10443 20:16:08.259256 <6>[ 0.125997] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10444 20:16:08.262816 <6>[ 0.126253] Detected VIPT I-cache on CPU3
10445 20:16:08.269388 <6>[ 0.126299] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10446 20:16:08.275937 <6>[ 0.126312] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10447 20:16:08.282471 <6>[ 0.126621] CPU features: detected: Spectre-v4
10448 20:16:08.285679 <6>[ 0.126628] CPU features: detected: Spectre-BHB
10449 20:16:08.289105 <6>[ 0.126633] Detected PIPT I-cache on CPU4
10450 20:16:08.295603 <6>[ 0.126691] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10451 20:16:08.305309 <6>[ 0.126708] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10452 20:16:08.309014 <6>[ 0.126999] Detected PIPT I-cache on CPU5
10453 20:16:08.315331 <6>[ 0.127059] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10454 20:16:08.321889 <6>[ 0.127075] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10455 20:16:08.325408 <6>[ 0.127348] Detected PIPT I-cache on CPU6
10456 20:16:08.335187 <6>[ 0.127412] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10457 20:16:08.341511 <6>[ 0.127428] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10458 20:16:08.344861 <6>[ 0.127720] Detected PIPT I-cache on CPU7
10459 20:16:08.351602 <6>[ 0.127784] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10460 20:16:08.358033 <6>[ 0.127800] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10461 20:16:08.364587 <6>[ 0.127847] smp: Brought up 1 node, 8 CPUs
10462 20:16:08.368015 <6>[ 0.127851] SMP: Total of 8 processors activated.
10463 20:16:08.374668 <6>[ 0.127855] CPU features: detected: 32-bit EL0 Support
10464 20:16:08.381241 <6>[ 0.127856] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10465 20:16:08.388059 <6>[ 0.127859] CPU features: detected: Common not Private translations
10466 20:16:08.394330 <6>[ 0.127861] CPU features: detected: CRC32 instructions
10467 20:16:08.401093 <6>[ 0.127864] CPU features: detected: RCpc load-acquire (LDAPR)
10468 20:16:08.404408 <6>[ 0.127865] CPU features: detected: LSE atomic instructions
10469 20:16:08.411084 <6>[ 0.127867] CPU features: detected: Privileged Access Never
10470 20:16:08.417318 <6>[ 0.127868] CPU features: detected: RAS Extension Support
10471 20:16:08.424089 <6>[ 0.127871] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10472 20:16:08.427537 <6>[ 0.127937] CPU: All CPU(s) started at EL2
10473 20:16:08.433981 <6>[ 0.127938] alternatives: applying system-wide alternatives
10474 20:16:08.437304 <6>[ 0.141044] devtmpfs: initialized
10475 20:16:08.463461 �FX,ZY��ash table entries: 512 (order 0, 4096 bytes)
10476 20:16:08.469852 <6>[ 0.355845] p<rintk: console [ttyS0] printing thread started
10477 20:16:08.473157 6><6>[ 0.355874] printk: console [ttyS0] enabled
10478 20:16:08.476587 [ 0.225615] pnp: PnP ACPI: disabled
10479 20:16:08.485504 <6>[ 0.355878] printk: bootconsole [mtk8250] disabled
10480 20:16:08.492075 <6>[ 0.369858] printk: bootconsole [mtk8250] printing thread stopped
10481 20:16:08.495367 <6>[ 0.370893] SuperH (H)SCI(F) driver initialized
10482 20:16:08.502091 <6>[ 0.371377] msm_serial: driver initialized
10483 20:16:08.508887 <6>[ 0.375920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10484 20:16:08.518631 <6>[ 0.375952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10485 20:16:08.525569 <6>[ 0.375981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10486 20:16:08.534946 <6>[ 0.376010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10487 20:16:08.553249 <6>[ 0.376032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10488 20:16:08.553758 <6>[ 0.376059] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10489 20:16:08.569354 <6>[ 0.376087] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10490 20:16:08.569564 <6>[ 0.376199] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10491 20:16:08.582459 <6>[ 0.376228] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10492 20:16:08.588095 <6>[ 0.388389] loop: module loaded
10493 20:16:08.591823 <6>[ 0.390980] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10494 20:16:08.595216 <4>[ 0.407632] mtk-pmic-keys: Failed to locate of_node [id: -1]
10495 20:16:08.598512 <6>[ 0.408466] megasas: 07.719.03.00-rc1
10496 20:16:08.604871 <6>[ 0.420776] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10497 20:16:08.608172 <6>[ 0.420946] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10498 20:16:08.614851 <6>[ 0.432603] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10499 20:16:08.627960 <6>[ 0.484911] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10500 20:16:09.069414 <6>[ 0.955848] Freeing initrd memory: 17384K
10501 20:16:09.077417 <6>[ 0.962050] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10502 20:16:09.084342 <6>[ 0.966619] tun: Universal TUN/TAP device driver, 1.6
10503 20:16:09.087294 <6>[ 0.967358] thunder_xcv, ver 1.0
10504 20:16:09.090875 <6>[ 0.967378] thunder_bgx, ver 1.0
10505 20:16:09.094105 <6>[ 0.967391] nicpf, ver 1.0
10506 20:16:09.100609 <6>[ 0.968434] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10507 20:16:09.107239 <6>[ 0.968437] hns3: Copyright (c) 2017 Huawei Corporation.
10508 20:16:09.110558 <6>[ 0.968464] hclge is initializing
10509 20:16:09.113978 <6>[ 0.968478] e1000: Intel(R) PRO/1000 Network Driver
10510 20:16:09.121072 <6>[ 0.968480] e1000: Copyright (c) 1999-2006 Intel Corporation.
10511 20:16:09.128206 <6>[ 0.968497] e1000e: Intel(R) PRO/1000 Network Driver
10512 20:16:09.131235 <6>[ 0.968498] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10513 20:16:09.138550 <6>[ 0.968515] igb: Intel(R) Gigabit Ethernet Network Driver
10514 20:16:09.144962 <6>[ 0.968517] igb: Copyright (c) 2007-2014 Intel Corporation.
10515 20:16:09.151964 <6>[ 0.968531] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10516 20:16:09.155611 <6>[ 0.968533] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10517 20:16:09.162335 <6>[ 0.968823] sky2: driver version 1.30
10518 20:16:09.165596 <6>[ 0.969893] VFIO - User Level meta-driver version: 0.3
10519 20:16:09.172129 <6>[ 0.972709] usbcore: registered new interface driver usb-storage
10520 20:16:09.178783 <6>[ 0.972907] usbcore: registered new device driver onboard-usb-hub
10521 20:16:09.185247 <6>[ 0.975677] mt6397-rtc mt6359-rtc: registered as rtc0
10522 20:16:09.192350 <6>[ 0.975829] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:16:09 UTC (1709496969)
10523 20:16:09.198639 <6>[ 0.976436] i2c_dev: i2c /dev entries driver
10524 20:16:09.205156 <6>[ 0.983501] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10525 20:16:09.211938 <6>[ 0.999484] cpu cpu0: EM: created perf domain
10526 20:16:09.215007 <6>[ 0.999794] cpu cpu4: EM: created perf domain
10527 20:16:09.221787 <6>[ 1.003579] sdhci: Secure Digital Host Controller Interface driver
10528 20:16:09.224909 <6>[ 1.003581] sdhci: Copyright(c) Pierre Ossman
10529 20:16:09.231778 <6>[ 1.003929] Synopsys Designware Multimedia Card Interface Driver
10530 20:16:09.238149 <6>[ 1.004316] sdhci-pltfm: SDHCI platform and OF driver helper
10531 20:16:09.244707 <6>[ 1.008591] ledtrig-cpu: registered to indicate activity on CPUs
10532 20:16:09.248105 <6>[ 1.009212] mmc0: CQHCI version 5.10
10533 20:16:09.254728 <6>[ 1.009281] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10534 20:16:09.261369 <6>[ 1.009582] usbcore: registered new interface driver usbhid
10535 20:16:09.264551 <6>[ 1.009584] usbhid: USB HID core driver
10536 20:16:09.271192 <6>[ 1.009709] spi_master spi0: will run message pump with realtime priority
10537 20:16:09.284652 <6>[ 1.042134] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10538 20:16:09.297828 <6>[ 1.044677] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10539 20:16:09.304425 <6>[ 1.045656] cros-ec-spi spi0.0: Chrome EC device registered
10540 20:16:09.314535 <6>[ 1.059820] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10541 20:16:09.318009 <6>[ 1.062119] NET: Registered PF_PACKET protocol family
10542 20:16:09.324511 <6>[ 1.062215] 9pnet: Installing 9P2000 support
10543 20:16:09.327860 <5>[ 1.062262] Key type dns_resolver registered
10544 20:16:09.330831 <6>[ 1.062614] registered taskstats version 1
10545 20:16:09.337646 <5>[ 1.062633] Loading compiled-in X.509 certificates
10546 20:16:09.347849 <4>[ 1.077707] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 20:16:09.357392 <4>[ 1.077871] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10548 20:16:09.364081 <3>[ 1.077883] debugfs: File 'uA_load' in directory '/' already present!
10549 20:16:09.370949 <3>[ 1.077892] debugfs: File 'min_uV' in directory '/' already present!
10550 20:16:09.377394 <3>[ 1.077896] debugfs: File 'max_uV' in directory '/' already present!
10551 20:16:09.384131 <3>[ 1.077900] debugfs: File 'constraint_flags' in directory '/' already present!
10552 20:16:09.394152 <3>[ 1.081684] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10553 20:16:09.400765 <6>[ 1.092416] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10554 20:16:09.404021 <6>[ 1.093023] xhci-mtk 11200000.usb: xHCI Host Controller
10555 20:16:09.414075 <6>[ 1.093043] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10556 20:16:09.423941 <6>[ 1.093265] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10557 20:16:09.427331 <6>[ 1.093311] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10558 20:16:09.433955 <6>[ 1.093443] xhci-mtk 11200000.usb: xHCI Host Controller
10559 20:16:09.440466 <6>[ 1.093451] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10560 20:16:09.447178 <6>[ 1.093461] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10561 20:16:09.453890 <6>[ 1.094099] hub 1-0:1.0: USB hub found
10562 20:16:09.457133 <6>[ 1.094127] hub 1-0:1.0: 1 port detected
10563 20:16:09.463590 <6>[ 1.094510] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10564 20:16:09.470277 <6>[ 1.094826] hub 2-0:1.0: USB hub found
10565 20:16:09.473647 <6>[ 1.094848] hub 2-0:1.0: 1 port detected
10566 20:16:09.477051 <6>[ 1.097877] mtk-msdc 11f70000.mmc: Got CD GPIO
10567 20:16:09.483719 <6>[ 1.108126] mmc0: Command Queue Engine enabled
10568 20:16:09.490267 <6>[ 1.108138] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10569 20:16:09.493725 <6>[ 1.108782] mmcblk0: mmc0:0001 DA4128 116 GiB
10570 20:16:09.500372 <6>[ 1.112283] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10571 20:16:09.506951 <6>[ 1.113041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10572 20:16:09.517000 <6>[ 1.113048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10573 20:16:09.523677 <4>[ 1.113205] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10574 20:16:09.530310 <6>[ 1.113489] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10575 20:16:09.536659 <6>[ 1.113856] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10576 20:16:09.546670 <6>[ 1.113860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10577 20:16:09.553423 <6>[ 1.113999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10578 20:16:09.563365 <6>[ 1.114011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10579 20:16:09.569814 <6>[ 1.114016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10580 20:16:09.579721 <6>[ 1.114021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10581 20:16:09.582833 <6>[ 1.114172] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10582 20:16:09.589608 <6>[ 1.115069] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10583 20:16:09.599313 <6>[ 1.116351] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10584 20:16:09.606038 <6>[ 1.116367] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10585 20:16:09.615814 <6>[ 1.116372] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10586 20:16:09.622438 <6>[ 1.116378] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10587 20:16:09.632842 <6>[ 1.116384] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10588 20:16:09.639429 <6>[ 1.116389] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10589 20:16:09.649350 <6>[ 1.116395] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10590 20:16:09.655487 <6>[ 1.116400] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10591 20:16:09.665621 <6>[ 1.116405] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10592 20:16:09.672032 <6>[ 1.116410] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10593 20:16:09.682120 <6>[ 1.116416] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10594 20:16:09.692253 <6>[ 1.116421] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10595 20:16:09.698483 <6>[ 1.116426] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10596 20:16:09.708319 <6>[ 1.116431] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10597 20:16:09.714965 <6>[ 1.116437] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10598 20:16:09.721892 <6>[ 1.117021] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10599 20:16:09.728582 <6>[ 1.118037] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10600 20:16:09.734733 <6>[ 1.118593] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10601 20:16:09.741640 <6>[ 1.119210] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10602 20:16:09.748125 <6>[ 1.119846] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10603 20:16:09.757982 <6>[ 1.120039] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10604 20:16:09.767858 <6>[ 1.120055] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10605 20:16:09.774607 <6>[ 1.120061] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10606 20:16:09.784540 <6>[ 1.120067] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10607 20:16:09.794169 <6>[ 1.120073] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10608 20:16:09.804257 <6>[ 1.120079] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10609 20:16:09.813893 <6>[ 1.120084] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10610 20:16:09.823804 <6>[ 1.120090] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10611 20:16:09.830465 <6>[ 1.120095] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10612 20:16:09.840429 <6>[ 1.120102] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10613 20:16:09.853644 <6>[ 1.120106] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10614 20:16:09.860251 <6>[ 1.120830] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10615 20:16:09.866681 <6>[ 1.130233] Trying to probe devices needed for running init ...
10616 20:16:09.873341 <6>[ 1.517455] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10617 20:16:09.876850 <6>[ 1.670028] hub 1-1:1.0: USB hub found
10618 20:16:09.880029 <6>[ 1.670422] hub 1-1:1.0: 4 ports detected
10619 20:16:09.886543 <6>[ 1.673938] hub 1-1:1.0: USB hub found
10620 20:16:09.889990 <6>[ 1.674246] hub 1-1:1.0: 4 ports detected
10621 20:16:09.912547 <6>[ 1.793673] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10622 20:16:09.933500 <6>[ 1.819118] hub 2-1:1.0: USB hub found
10623 20:16:09.936609 <6>[ 1.819564] hub 2-1:1.0: 3 ports detected
10624 20:16:09.939916 <6>[ 1.822528] hub 2-1:1.0: USB hub found
10625 20:16:09.943351 <6>[ 1.822929] hub 2-1:1.0: 3 ports detected
10626 20:16:10.108886 <6>[ 1.989688] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10627 20:16:10.229453 <6>[ 2.116483] hub 1-1.4:1.0: USB hub found
10628 20:16:10.232916 <6>[ 2.116798] hub 1-1.4:1.0: 2 ports detected
10629 20:16:10.236021 <6>[ 2.120071] hub 1-1.4:1.0: USB hub found
10630 20:16:10.242651 <6>[ 2.120380] hub 1-1.4:1.0: 2 ports detected
10631 20:16:10.312779 <6>[ 2.193795] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10632 20:16:10.528668 <6>[ 2.409654] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10633 20:16:10.712495 <6>[ 2.593660] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10634 20:16:21.521047 <6>[ 13.411015] ALSA device list:
10635 20:16:21.527486 <6>[ 13.411040] No soundcards found.
10636 20:16:21.530763 <6>[ 13.415056] Freeing unused kernel memory: 8448K
10637 20:16:21.534114 <6>[ 13.415147] Run /init as init process
10638 20:16:21.537311 Loading, please wait...
10639 20:16:21.552061 Starting version 247.3-7+deb11u4
10640 20:16:21.727225 <6>[ 13.612999] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10641 20:16:21.730687 <6>[ 13.616913] remoteproc remoteproc0: scp is available
10642 20:16:21.737142 <6>[ 13.617037] remoteproc remoteproc0: powering up scp
10643 20:16:21.743845 <6>[ 13.617054] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10644 20:16:21.750362 <6>[ 13.617115] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10645 20:16:21.763492 <6>[ 13.627956] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10646 20:16:21.770170 <6>[ 13.627981] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10647 20:16:21.780077 <6>[ 13.627986] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10648 20:16:21.791112 <6>[ 13.677269] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10649 20:16:21.798179 <6>[ 13.677562] usbcore: registered new device driver r8152-cfgselector
10650 20:16:21.804688 <3>[ 13.679921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 20:16:21.814530 <3>[ 13.679956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 20:16:21.821070 <3>[ 13.679964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 20:16:21.831427 <3>[ 13.680122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 20:16:21.837764 <3>[ 13.680131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 20:16:21.844297 <3>[ 13.680139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 20:16:21.854522 <3>[ 13.680155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 20:16:21.861355 <3>[ 13.680163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 20:16:21.868284 <3>[ 13.680242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 20:16:21.878435 <3>[ 13.680325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10660 20:16:21.884799 <3>[ 13.680332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 20:16:21.894803 <3>[ 13.680340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10662 20:16:21.901152 <3>[ 13.680391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 20:16:21.911155 <3>[ 13.680399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 20:16:21.917918 <3>[ 13.680406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 20:16:21.927750 <3>[ 13.680414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 20:16:21.934387 <3>[ 13.680421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 20:16:21.944192 <3>[ 13.680470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 20:16:21.947554 <6>[ 13.685848] mc: Linux media interface: v0.10
10669 20:16:21.954601 <6>[ 13.709286] videodev: Linux video capture interface: v2.00
10670 20:16:21.960935 <4>[ 13.711420] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10671 20:16:21.967527 <4>[ 13.712830] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10672 20:16:21.974154 <4>[ 13.712830] Fallback method does not support PEC.
10673 20:16:21.980598 <4>[ 13.718829] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10674 20:16:21.990431 <3>[ 13.731018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 20:16:21.997020 <6>[ 13.746767] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10676 20:16:22.006993 <6>[ 13.746775] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10677 20:16:22.010596 <6>[ 13.746780] remoteproc remoteproc0: remote processor scp is now up
10678 20:16:22.020243 <6>[ 13.750689] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10679 20:16:22.023659 <6>[ 13.750694] pci_bus 0000:00: root bus resource [bus 00-ff]
10680 20:16:22.029954 <6>[ 13.750700] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10681 20:16:22.040105 <6>[ 13.750703] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10682 20:16:22.046889 <6>[ 13.750726] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10683 20:16:22.056437 <6>[ 13.750739] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10684 20:16:22.059962 <6>[ 13.750802] pci 0000:00:00.0: supports D1 D2
10685 20:16:22.066526 <6>[ 13.750804] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10686 20:16:22.076323 <6>[ 13.751692] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10687 20:16:22.079806 <6>[ 13.751764] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10688 20:16:22.089854 <6>[ 13.751789] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10689 20:16:22.096451 <6>[ 13.751805] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10690 20:16:22.102915 <6>[ 13.751820] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10691 20:16:22.109584 <6>[ 13.751921] pci 0000:01:00.0: supports D1 D2
10692 20:16:22.116030 <6>[ 13.751922] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10693 20:16:22.123059 <3>[ 13.753176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 20:16:22.129659 <6>[ 13.761465] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10695 20:16:22.139146 <6>[ 13.761523] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10696 20:16:22.145728 <6>[ 13.761529] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10697 20:16:22.155900 <6>[ 13.761541] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10698 20:16:22.162690 <6>[ 13.761553] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10699 20:16:22.169453 <6>[ 13.761567] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10700 20:16:22.175613 <6>[ 13.761579] pci 0000:00:00.0: PCI bridge to [bus 01]
10701 20:16:22.182542 <6>[ 13.761584] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10702 20:16:22.188855 <6>[ 13.761815] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10703 20:16:22.199006 <6>[ 13.761911] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10704 20:16:22.205212 <6>[ 13.764544] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10705 20:16:22.211947 <6>[ 13.765060] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10706 20:16:22.218560 <6>[ 13.773982] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10707 20:16:22.228531 <6>[ 13.776441] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10708 20:16:22.235288 <4>[ 13.785699] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10709 20:16:22.245251 <4>[ 13.785768] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10710 20:16:22.254960 <6>[ 13.810478] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10711 20:16:22.261817 <6>[ 13.810813] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10712 20:16:22.271649 <6>[ 13.828148] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10713 20:16:22.278570 <6>[ 13.845516] r8152 2-1.3:1.0 eth0: v1.12.13
10714 20:16:22.281391 <6>[ 13.845617] usbcore: registered new interface driver r8152
10715 20:16:22.288240 <6>[ 13.847924] Bluetooth: Core ver 2.22
10716 20:16:22.291695 <6>[ 13.847984] NET: Registered PF_BLUETOOTH protocol family
10717 20:16:22.298146 <6>[ 13.847985] Bluetooth: HCI device and connection manager initialized
10718 20:16:22.305041 <6>[ 13.848001] Bluetooth: HCI socket layer initialized
10719 20:16:22.307731 <6>[ 13.848006] Bluetooth: L2CAP socket layer initialized
10720 20:16:22.314516 <6>[ 13.848013] Bluetooth: SCO socket layer initialized
10721 20:16:22.321072 <5>[ 13.857533] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10722 20:16:22.327686 <5>[ 13.868079] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10723 20:16:22.337592 <5>[ 13.868545] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10724 20:16:22.347419 <4>[ 13.868697] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10725 20:16:22.350926 <6>[ 13.868713] cfg80211: failed to load regulatory.db
10726 20:16:22.357677 <6>[ 13.868778] usbcore: registered new interface driver cdc_ether
10727 20:16:22.364193 <6>[ 13.885173] usbcore: registered new interface driver r8153_ecm
10728 20:16:22.370794 <6>[ 13.886066] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10729 20:16:22.383725 <6>[ 13.888236] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10730 20:16:22.390514 <6>[ 13.888357] usbcore: registered new interface driver uvcvideo
10731 20:16:22.393777 <6>[ 13.895851] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10732 20:16:22.400324 <6>[ 13.906869] usbcore: registered new interface driver btusb
10733 20:16:22.410409 <4>[ 13.907753] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10734 20:16:22.417323 <3>[ 13.907764] Bluetooth: hci0: Failed to load firmware file (-2)
10735 20:16:22.423657 <3>[ 13.907767] Bluetooth: hci0: Failed to set up firmware (-2)
10736 20:16:22.433570 <4>[ 13.907769] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10737 20:16:22.440173 <6>[ 13.914005] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10738 20:16:22.446856 <6>[ 14.243855] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10739 20:16:22.453446 <6>[ 14.243966] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10740 20:16:22.459969 <6>[ 14.261605] mt7921e 0000:01:00.0: ASIC revision: 79610010
10741 20:16:22.471426 <6>[ 14.357085] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10742 20:16:22.474685 <6>[ 14.357085]
10743 20:16:22.478254 Begin: Loading essential drivers ... done.
10744 20:16:22.481314 Begin: Running /scripts/init-premount ... done.
10745 20:16:22.487976 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10746 20:16:22.498286 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10747 20:16:22.501347 Device /sys/class/net/enx0024323078ff found
10748 20:16:22.501616 done.
10749 20:16:22.579606 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10750 20:16:22.731125 <6>[ 14.614252] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10751 20:16:23.512199 <6>[ 15.400945] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10752 20:16:23.571985 <6>[ 15.457558] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10753 20:16:23.586426 IP-Config: no response after 2 secs - giving up
10754 20:16:23.592795 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10755 20:16:23.628094 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10756 20:16:24.284349 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10757 20:16:24.290942 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10758 20:16:24.297512 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10759 20:16:24.304202 host : mt8192-asurada-spherion-r0-cbg-8
10760 20:16:24.310966 domain : lava-rack
10761 20:16:24.314226 rootserver: 192.168.201.1 rootpath:
10762 20:16:24.317444 filename :
10763 20:16:24.428366 done.
10764 20:16:24.435890 Begin: Running /scripts/nfs-bottom ... done.
10765 20:16:24.452777 Begin: Running /scripts/init-bottom ... done.
10766 20:16:25.659887 <6>[ 17.545723] NET: Registered PF_INET6 protocol family
10767 20:16:25.662979 <6>[ 17.547997] Segment Routing with IPv6
10768 20:16:25.669643 <6>[ 17.548021] In-situ OAM (IOAM) with IPv6
10769 20:16:25.799352 <30>[ 17.665629] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10770 20:16:25.799482
10771 20:16:25.805953 Welcome to [1<30>[ 17.666559] systemd[1]: Detected architecture arm64.
10772 20:16:25.809148 mDebian GNU/Linux 11 (bullseye)[0m!
10773 20:16:25.809251
10774 20:16:25.827346 <30>[ 17.716004] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10775 20:16:26.702756 <30>[ 18.588945] systemd[1]: Queued start job for default target Graphical Interface.
10776 20:16:26.729853 [[0;32m OK [<30>[ 18.616038] systemd[1]: Created slice system-getty.slice.
10777 20:16:26.732921 0m] Created slice [0;1;39msystem-getty.slice[0m.
10778 20:16:26.752452 [[0;32m OK [0m] Created slic<30>[ 18.638929] systemd[1]: Created slice system-modprobe.slice.
10779 20:16:26.755708 e [0;1;39msystem-modprobe.slice[0m.
10780 20:16:26.776503 [[0;32m OK [0m] Created slic<30>[ 18.662899] systemd[1]: Created slice system-serial\x2dgetty.slice.
10781 20:16:26.782726 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10782 20:16:26.801144 [[0;32m OK [0m] Created slic<30>[ 18.687472] systemd[1]: Created slice User and Session Slice.
10783 20:16:26.804503 e [0;1;39mUser and Session Slice[0m.
10784 20:16:26.826901 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 18.710089] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10785 20:16:26.830381 ssword …ts to Console Directory Watch[0m.
10786 20:16:26.854657 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.737879] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10787 20:16:26.857962 sword R…uests to Wall Directory Watch[0m.
10788 20:16:26.882229 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.761808] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10789 20:16:26.888629 <30>[ 18.762010] systemd[1]: Reached target Local Encrypted Volumes.
10790 20:16:26.892123 l Encrypted Volumes[0m.
10791 20:16:26.911773 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.798205] systemd[1]: Reached target Paths.
10792 20:16:26.911859 s[0m.
10793 20:16:26.934306 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.817647] systemd[1]: Reached target Remote File Systems.
10794 20:16:26.934395 te File Systems[0m.
10795 20:16:26.955798 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 18.842062] systemd[1]: Reached target Slices.
10796 20:16:26.955911 es[0m.
10797 20:16:26.975214 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 18.861659] systemd[1]: Reached target Swap.
10798 20:16:26.975305 [0m.
10799 20:16:26.999015 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 18.882183] systemd[1]: Listening on initctl Compatibility Named Pipe.
10800 20:16:27.002228 l Compatibility Named Pipe[0m.
10801 20:16:27.012292 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 18.898353] systemd[1]: Listening on Journal Audit Socket.
10802 20:16:27.015378 l Audit Socket[0m.
10803 20:16:27.036308 [[0;32m OK [0m] Listening on<30>[ 18.923039] systemd[1]: Listening on Journal Socket (/dev/log).
10804 20:16:27.039744 [0;1;39mJournal Socket (/dev/log)[0m.
10805 20:16:27.060319 [[0;32m OK [0m] Listening on<30>[ 18.946979] systemd[1]: Listening on Journal Socket.
10806 20:16:27.063602 [0;1;39mJournal Socket[0m.
10807 20:16:27.081138 [[0;32m OK [0m] Listening on<30>[ 18.967518] systemd[1]: Listening on Network Service Netlink Socket.
10808 20:16:27.087257 [0;1;39mNetwork Service Netlink Socket[0m.
10809 20:16:27.107083 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 18.993627] systemd[1]: Listening on udev Control Socket.
10810 20:16:27.110200 ontrol Socket[0m.
10811 20:16:27.127419 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.014120] systemd[1]: Listening on udev Kernel Socket.
10812 20:16:27.130729 ernel Socket[0m.
10813 20:16:27.178510 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.061727] systemd[1]: Mounting Huge Pages File System...
10814 20:16:27.178608 m[0m...
10815 20:16:27.203143 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.086053] systemd[1]: Mounting POSIX Message Queue File System...
10816 20:16:27.203262 ile System[0m...
10817 20:16:27.230907 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.114185] systemd[1]: Mounting Kernel Debug File System...
10818 20:16:27.231033 tem[0m...
10819 20:16:27.250860 <30>[ 19.134169] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10820 20:16:27.268009 Starting [0;1;39mCreat<30>[ 19.151124] systemd[1]: Starting Create list of static device nodes for the current kernel...
10821 20:16:27.271319 e list of st…odes for the current kernel[0m...
10822 20:16:27.293993 Startin<30>[ 19.180365] systemd[1]: Starting Load Kernel Module configfs...
10823 20:16:27.297012 g [0;1;39mLoad Kernel Module configfs[0m...
10824 20:16:27.320117 Starting [0;1;39mLoad <30>[ 19.206618] systemd[1]: Starting Load Kernel Module drm...
10825 20:16:27.323421 Kernel Module drm[0m...
10826 20:16:27.347080 Starting [0;1;39mLoad Kernel Module fu<30>[ 19.230174] systemd[1]: Starting Load Kernel Module fuse...
10827 20:16:27.347186 se[0m...
10828 20:16:27.386686 <30>[ 19.270762] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10829 20:16:27.393185 <6>[ 19.272069] fuse: init (API version 7.37)
10830 20:16:27.431763 Starting [0;1;39mJourn<30>[ 19.318467] systemd[1]: Starting Journal Service...
10831 20:16:27.431885 al Service[0m...
10832 20:16:27.461949 Startin<30>[ 19.348361] systemd[1]: Starting Load Kernel Modules...
10833 20:16:27.465047 g [0;1;39mLoad Kernel Modules[0m...
10834 20:16:27.491236 Starting [0;1;39mRemount Root and Kern<30>[ 19.374464] systemd[1]: Starting Remount Root and Kernel File Systems...
10835 20:16:27.494553 el File Systems[0m...
10836 20:16:27.555086 Starting [0;1;39mColdplug All udev Dev<30>[ 19.438465] systemd[1]: Starting Coldplug All udev Devices...
10837 20:16:27.555198 ices[0m...
10838 20:16:27.570553 <3>[ 19.456207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 20:16:27.583259 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 19.469583] systemd[1]: Mounted Huge Pages File System.
10840 20:16:27.586346 File System[0m.
10841 20:16:27.602484 <3>[ 19.486591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 20:16:27.612493 [[0;32m OK [0m] Mounted [0;<30>[ 19.498843] systemd[1]: Mounted POSIX Message Queue File System.
10843 20:16:27.615621 1;39mPOSIX Message Queue File System[0m.
10844 20:16:27.635633 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.522051] systemd[1]: Mounted Kernel Debug File System.
10845 20:16:27.645727 g File System[0<3>[ 19.525554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 20:16:27.645812 m.
10847 20:16:27.662381 <3>[ 19.545693] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10848 20:16:27.676372 [[0;32m OK [0m] Finished [0<30>[ 19.559149] systemd[1]: Finished Create list of static device nodes for the current kernel.
10849 20:16:27.686567 ;1;39mCreate lis<3>[ 19.567158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 20:16:27.689976 t of st… nodes for the current kernel[0m.
10851 20:16:27.702665 <3>[ 19.587242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 20:16:27.713922 [[0;32m OK [0m] Finished [0<30>[ 19.599187] systemd[1]: modprobe@configfs.service: Succeeded.
10853 20:16:27.720640 ;1;39mLoad Kerne<30>[ 19.599801] systemd[1]: Finished Load Kernel Module configfs.
10854 20:16:27.730345 l Module configf<3>[ 19.608965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 20:16:27.730427 s[0m.
10856 20:16:27.742633 <3>[ 19.628961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 20:16:27.753924 [[0;32m OK [0m] Finished [0<30>[ 19.639259] systemd[1]: modprobe@drm.service: Succeeded.
10858 20:16:27.760239 ;1;39mLoad Kerne<30>[ 19.639867] systemd[1]: Finished Load Kernel Module drm.
10859 20:16:27.770266 l Module drm[0m<3>[ 19.650397] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 20:16:27.770365 .
10861 20:16:27.786771 <3>[ 19.671290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 20:16:27.798921 [[0;32m OK [<30>[ 19.683956] systemd[1]: modprobe@fuse.service: Succeeded.
10863 20:16:27.805558 0m] Finished [0<30>[ 19.685073] systemd[1]: Finished Load Kernel Module fuse.
10864 20:16:27.808760 ;1;39mLoad Kernel Module fuse[0m.
10865 20:16:27.829235 [[0;32m OK [<30>[ 19.716162] systemd[1]: Finished Load Kernel Modules.
10866 20:16:27.832599 0m] Finished [0;1;39mLoad Kernel Modules[0m.
10867 20:16:27.851682 [[0;32m OK [0m] Started [0;<30>[ 19.738522] systemd[1]: Started Journal Service.
10868 20:16:27.855200 1;39mJournal Service[0m.
10869 20:16:27.873987 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10870 20:16:27.912962 Mounting [0;1;39mFUSE Control File System[0m...
10871 20:16:27.936664 Mounting [0;1;39mKernel Configuration File System[0m...
10872 20:16:27.964846 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10873 20:16:27.983209 Starting [0;1;39mLoad/Save Random Seed[0m...
10874 20:16:28.008914 Starting [0;1;39mApply Kernel Variables[0m...
10875 20:16:28.030625 <46>[ 19.917194] systemd-journald[305]: Received client request to flush runtime journal.
10876 20:16:28.034027 Starting [0;1;39mCreate System Users[0m...
10877 20:16:28.054519 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10878 20:16:28.072473 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10879 20:16:28.102742 [[0;32m OK [0m] Finished [0<4>[ 19.980776] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10880 20:16:28.109612 <3>[ 19.980787] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10881 20:16:28.112791 ;1;39mLoad/Save Random Seed[0m.
10882 20:16:28.134365 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10883 20:16:28.147710 See 'systemctl status systemd-udev-trigger.service' for details.
10884 20:16:28.791477 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10885 20:16:29.435884 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10886 20:16:29.469226 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10887 20:16:29.520724 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10888 20:16:29.610652 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10889 20:16:29.624085 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10890 20:16:29.639228 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10891 20:16:29.679563 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10892 20:16:29.707099 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10893 20:16:29.892341 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10894 20:16:29.954191 Starting [0;1;39mNetwork Service[0m...
10895 20:16:30.065362 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10896 20:16:30.133669 Starting [0;1;39mNetwork Time Synchronization[0m...
10897 20:16:30.151860 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10898 20:16:30.277620 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10899 20:16:30.306304 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10900 20:16:30.376507 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10901 20:16:30.640729 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10902 20:16:30.659280 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10903 20:16:30.683482 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10904 20:16:30.740042 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10905 20:16:30.760020 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10906 20:16:30.783560 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10907 20:16:30.832205 Starting [0;1;39mNetwork Name Resolution[0m...
10908 20:16:30.852272 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10909 20:16:30.883632 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10910 20:16:30.900037 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10911 20:16:30.919117 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10912 20:16:30.931884 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10913 20:16:30.947768 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10914 20:16:30.996255 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10915 20:16:31.018259 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10916 20:16:31.481238 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10917 20:16:31.757099 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10918 20:16:31.771310 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10919 20:16:31.792158 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10920 20:16:31.803421 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10921 20:16:31.819567 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10922 20:16:31.876567 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10923 20:16:32.191940 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10924 20:16:32.292665 Starting [0;1;39mUser Login Management[0m...
10925 20:16:32.815285 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10926 20:16:32.837236 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10927 20:16:32.852727 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10928 20:16:32.870477 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10929 20:16:32.904192 Starting [0;1;39mPermit User Sessions[0m...
10930 20:16:32.920037 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10931 20:16:32.983403 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10932 20:16:33.043999 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10933 20:16:33.065189 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10934 20:16:33.084303 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10935 20:16:33.099829 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10936 20:16:33.115786 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10937 20:16:33.167930 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10938 20:16:33.214689 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10939 20:16:33.279465
10940 20:16:33.279579
10941 20:16:33.282826 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10942 20:16:33.282970
10943 20:16:33.286003 debian-bullseye-arm64 login: root (automatic login)
10944 20:16:33.286085
10945 20:16:33.286148
10946 20:16:33.668202 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10947 20:16:33.668368
10948 20:16:33.674768 The programs included with the Debian GNU/Linux system are free software;
10949 20:16:33.681350 the exact distribution terms for each program are described in the
10950 20:16:33.684769 individual files in /usr/share/doc/*/copyright.
10951 20:16:33.684854
10952 20:16:33.691404 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10953 20:16:33.694498 permitted by applicable law.
10954 20:16:34.577344 Matched prompt #10: / #
10956 20:16:34.577693 Setting prompt string to ['/ #']
10957 20:16:34.577806 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10959 20:16:34.578100 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10960 20:16:34.578202 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
10961 20:16:34.578307 Setting prompt string to ['/ #']
10962 20:16:34.578380 Forcing a shell prompt, looking for ['/ #']
10964 20:16:34.628670 / #
10965 20:16:34.628786 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10966 20:16:34.628870 Waiting using forced prompt support (timeout 00:02:30)
10967 20:16:34.633263
10968 20:16:34.633532 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10969 20:16:34.633653 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
10971 20:16:34.734026 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0'
10972 20:16:34.739021 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928144/extract-nfsrootfs-e00ht0b0'
10974 20:16:34.839551 / # export NFS_SERVER_IP='192.168.201.1'
10975 20:16:34.844517 export NFS_SERVER_IP='192.168.201.1'
10976 20:16:34.844801 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10977 20:16:34.844899 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
10978 20:16:34.844994 end: 2 depthcharge-action (duration 00:01:44) [common]
10979 20:16:34.845086 start: 3 lava-test-retry (timeout 00:07:36) [common]
10980 20:16:34.845172 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
10981 20:16:34.845249 Using namespace: common
10983 20:16:34.945586 / # #
10984 20:16:34.945699 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10985 20:16:34.950718 #
10986 20:16:34.950987 Using /lava-12928144
10988 20:16:35.051333 / # export SHELL=/bin/bash
10989 20:16:35.056997 export SHELL=/bin/bash
10991 20:16:35.157538 / # . /lava-12928144/environment
10992 20:16:35.162629 . /lava-12928144/environment
10994 20:16:35.268783 / # /lava-12928144/bin/lava-test-runner /lava-12928144/0
10995 20:16:35.268899 Test shell timeout: 10s (minimum of the action and connection timeout)
10996 20:16:35.274087 /lava-12928144/bin/lava-test-runner /lava-12928144/0
10997 20:16:35.584434 + export TESTRUN_ID=0_timesync-off
10998 20:16:35.587701 + TESTRUN_ID=0_timesync-off
10999 20:16:35.591066 + cd /lava-12928144/0/tests/0_timesync-off
11000 20:16:35.594319 ++ cat uuid
11001 20:16:35.599873 + UUID=12928144_1.6.2.3.1
11002 20:16:35.599956 + set +x
11003 20:16:35.606258 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12928144_1.6.2.3.1>
11004 20:16:35.606523 Received signal: <STARTRUN> 0_timesync-off 12928144_1.6.2.3.1
11005 20:16:35.606601 Starting test lava.0_timesync-off (12928144_1.6.2.3.1)
11006 20:16:35.606688 Skipping test definition patterns.
11007 20:16:35.609756 + systemctl stop systemd-timesyncd
11008 20:16:35.670321 + set +x
11009 20:16:35.673783 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12928144_1.6.2.3.1>
11010 20:16:35.674043 Received signal: <ENDRUN> 0_timesync-off 12928144_1.6.2.3.1
11011 20:16:35.674124 Ending use of test pattern.
11012 20:16:35.674187 Ending test lava.0_timesync-off (12928144_1.6.2.3.1), duration 0.07
11014 20:16:35.754323 + export TESTRUN_ID=1_kselftest-rtc
11015 20:16:35.757800 + TESTRUN_ID=1_kselftest-rtc
11016 20:16:35.760727 + cd /lava-12928144/0/tests/1_kselftest-rtc
11017 20:16:35.764101 ++ cat uuid
11018 20:16:35.772067 + UUID=12928144_1.6.2.3.5
11019 20:16:35.772152 + set +x
11020 20:16:35.778393 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12928144_1.6.2.3.5>
11021 20:16:35.778653 Received signal: <STARTRUN> 1_kselftest-rtc 12928144_1.6.2.3.5
11022 20:16:35.778726 Starting test lava.1_kselftest-rtc (12928144_1.6.2.3.5)
11023 20:16:35.778808 Skipping test definition patterns.
11024 20:16:35.781965 + cd ./automated/linux/kselftest/
11025 20:16:35.808176 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11026 20:16:35.852413 INFO: install_deps skipped
11027 20:16:35.976739 --2024-03-03 20:16:35-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11028 20:16:35.987529 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11029 20:16:36.120741 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11030 20:16:36.254021 HTTP request sent, awaiting response... 200 OK
11031 20:16:36.257148 Length: 1746752 (1.7M) [application/octet-stream]
11032 20:16:36.260491 Saving to: 'kselftest.tar.xz'
11033 20:16:36.260600
11034 20:16:36.260668
11035 20:16:36.520317 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11036 20:16:36.786990 kselftest.tar.xz 2%[ ] 47.81K 180KB/s
11037 20:16:37.052486 kselftest.tar.xz 12%[=> ] 217.50K 409KB/s
11038 20:16:37.360401 kselftest.tar.xz 52%[=========> ] 896.25K 1.10MB/s
11039 20:16:37.367138 kselftest.tar.xz 98%[==================> ] 1.65M 1.49MB/s
11040 20:16:37.373335 kselftest.tar.xz 100%[===================>] 1.67M 1.51MB/s in 1.1s
11041 20:16:37.373444
11042 20:16:37.521402 2024-03-03 20:16:37 (1.51 MB/s) - 'kselftest.tar.xz' saved [1746752/1746752]
11043 20:16:37.521543
11044 20:16:42.338356 skiplist:
11045 20:16:42.342048 ========================================
11046 20:16:42.345342 ========================================
11047 20:16:42.393975 rtc:rtctest
11048 20:16:42.413974 ============== Tests to run ===============
11049 20:16:42.414066 rtc:rtctest
11050 20:16:42.420742 ===========End Tests to run ===============
11051 20:16:42.423787 shardfile-rtc pass
11052 20:16:42.529622 <12>[ 34.420835] kselftest: Running tests in rtc
11053 20:16:42.535922 TAP version 13
11054 20:16:42.549108 1..1
11055 20:16:42.581925 # selftests: rtc: rtctest
11056 20:16:43.025778 # TAP version 13
11057 20:16:43.025914 # 1..8
11058 20:16:43.029018 # # Starting 8 tests from 2 test cases.
11059 20:16:43.032327 # # RUN rtc.date_read ...
11060 20:16:43.039021 # # rtctest.c:49:date_read:Current RTC date/time is 03/03/2024 20:16:42.
11061 20:16:43.042101 # # OK rtc.date_read
11062 20:16:43.045322 # ok 1 rtc.date_read
11063 20:16:43.048811 # # RUN rtc.date_read_loop ...
11064 20:16:43.058407 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11065 20:16:52.141179 <6>[ 44.033528] vpu: disabling
11066 20:16:52.144380 <6>[ 44.033651] vproc2: disabling
11067 20:16:52.147888 <6>[ 44.033706] vproc1: disabling
11068 20:16:52.151068 <6>[ 44.033761] vaud18: disabling
11069 20:16:52.154447 <6>[ 44.034013] vsram_others: disabling
11070 20:16:52.157898 <6>[ 44.034193] va09: disabling
11071 20:16:52.160979 <6>[ 44.034271] vsram_md: disabling
11072 20:16:52.164316 <6>[ 44.034407] Vgpu: disabling
11073 20:17:13.021465 # # rtctest.c:115:date_read_loop:Performed 2649 RTC time reads.
11074 20:17:13.024725 # # OK rtc.date_read_loop
11075 20:17:13.028096 # ok 2 rtc.date_read_loop
11076 20:17:13.030955 # # RUN rtc.uie_read ...
11077 20:17:15.999139 # # OK rtc.uie_read
11078 20:17:16.002378 # ok 3 rtc.uie_read
11079 20:17:16.005330 # # RUN rtc.uie_select ...
11080 20:17:18.998203 # # OK rtc.uie_select
11081 20:17:19.001586 # ok 4 rtc.uie_select
11082 20:17:19.004847 # # RUN rtc.alarm_alm_set ...
11083 20:17:19.011975 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 20:17:22.
11084 20:17:19.014962 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11085 20:17:19.021915 # # alarm_alm_set: Test terminated by assertion
11086 20:17:19.024792 # # FAIL rtc.alarm_alm_set
11087 20:17:19.025207 # not ok 5 rtc.alarm_alm_set
11088 20:17:19.031914 # # RUN rtc.alarm_wkalm_set ...
11089 20:17:19.038137 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 03/03/2024 20:17:22.
11090 20:17:22.001601 # # OK rtc.alarm_wkalm_set
11091 20:17:22.002135 # ok 6 rtc.alarm_wkalm_set
11092 20:17:22.007755 # # RUN rtc.alarm_alm_set_minute ...
11093 20:17:22.010910 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 20:18:00.
11094 20:17:22.017362 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11095 20:17:22.024408 # # alarm_alm_set_minute: Test terminated by assertion
11096 20:17:22.027535 # # FAIL rtc.alarm_alm_set_minute
11097 20:17:22.031224 # not ok 7 rtc.alarm_alm_set_minute
11098 20:17:22.034022 # # RUN rtc.alarm_wkalm_set_minute ...
11099 20:17:22.041155 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 03/03/2024 20:18:00.
11100 20:17:59.997339 # # OK rtc.alarm_wkalm_set_minute
11101 20:18:00.000491 # ok 8 rtc.alarm_wkalm_set_minute
11102 20:18:00.003712 # # FAILED: 6 / 8 tests passed.
11103 20:18:00.006977 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11104 20:18:00.013529 not ok 1 selftests: rtc: rtctest # exit=1
11105 20:18:00.684748 Traceback (most recent call last):
11106 20:18:00.694592 File "/lava-12928144/0/tests/1_kselftest-rtc/automated/linux/kselftest/./parse-output.py", line 4, in <module>
11107 20:18:00.697727 from tap import parser
11108 20:18:00.700948 ModuleNotFoundError: No module named 'tap'
11109 20:18:00.722166 + ../../utils/send-to-lava.sh ./output/result.txt
11110 20:18:00.835134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11111 20:18:00.835649 + set +x
11112 20:18:00.836283 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11114 20:18:00.841515 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12928144_1.6.2.3.5>
11115 20:18:00.842296 Received signal: <ENDRUN> 1_kselftest-rtc 12928144_1.6.2.3.5
11116 20:18:00.842671 Ending use of test pattern.
11117 20:18:00.843090 Ending test lava.1_kselftest-rtc (12928144_1.6.2.3.5), duration 85.06
11119 20:18:00.844625 <LAVA_TEST_RUNNER EXIT>
11120 20:18:00.845284 ok: lava_test_shell seems to have completed
11121 20:18:00.845821 shardfile-rtc: pass
11122 20:18:00.846232 end: 3.1 lava-test-shell (duration 00:01:26) [common]
11123 20:18:00.846641 end: 3 lava-test-retry (duration 00:01:26) [common]
11124 20:18:00.847068 start: 4 finalize (timeout 00:06:10) [common]
11125 20:18:00.847505 start: 4.1 power-off (timeout 00:00:30) [common]
11126 20:18:00.848247 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11127 20:18:00.974817 >> Command sent successfully.
11128 20:18:00.985620 Returned 0 in 0 seconds
11129 20:18:01.086889 end: 4.1 power-off (duration 00:00:00) [common]
11131 20:18:01.088288 start: 4.2 read-feedback (timeout 00:06:09) [common]
11132 20:18:01.089554 Listened to connection for namespace 'common' for up to 1s
11133 20:18:02.089699 Finalising connection for namespace 'common'
11134 20:18:02.090337 Disconnecting from shell: Finalise
11135 20:18:02.090725 / #
11136 20:18:02.191809 end: 4.2 read-feedback (duration 00:00:01) [common]
11137 20:18:02.192485 end: 4 finalize (duration 00:00:01) [common]
11138 20:18:02.193062 Cleaning after the job
11139 20:18:02.193568 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/ramdisk
11140 20:18:02.205944 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/kernel
11141 20:18:02.243614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/dtb
11142 20:18:02.243901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/nfsrootfs
11143 20:18:02.338567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928144/tftp-deploy-p_3bgsc4/modules
11144 20:18:02.345653 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928144
11145 20:18:02.989940 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928144
11146 20:18:02.990101 Job finished correctly