Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 13
1 20:14:26.469971 lava-dispatcher, installed at version: 2024.01
2 20:14:26.470204 start: 0 validate
3 20:14:26.470344 Start time: 2024-03-03 20:14:26.470337+00:00 (UTC)
4 20:14:26.470477 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:14:26.470613 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 20:14:26.739885 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:14:26.740053 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:14:27.006778 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:14:27.006941 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:14:27.272681 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:14:27.272897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:14:27.531281 Using caching service: 'http://localhost/cache/?uri=%s'
13 20:14:27.531477 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 20:14:27.801139 validate duration: 1.33
16 20:14:27.801400 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:14:27.801497 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:14:27.801587 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:14:27.801707 Not decompressing ramdisk as can be used compressed.
20 20:14:27.801793 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20240129.0/arm64/initrd.cpio.gz
21 20:14:27.801858 saving as /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/ramdisk/initrd.cpio.gz
22 20:14:27.801922 total size: 4663085 (4 MB)
23 20:14:27.803013 progress 0 % (0 MB)
24 20:14:27.804552 progress 5 % (0 MB)
25 20:14:27.806058 progress 10 % (0 MB)
26 20:14:27.807562 progress 15 % (0 MB)
27 20:14:27.808958 progress 20 % (0 MB)
28 20:14:27.810271 progress 25 % (1 MB)
29 20:14:27.811796 progress 30 % (1 MB)
30 20:14:27.813175 progress 35 % (1 MB)
31 20:14:27.814582 progress 40 % (1 MB)
32 20:14:27.816355 progress 45 % (2 MB)
33 20:14:27.817673 progress 50 % (2 MB)
34 20:14:27.819120 progress 55 % (2 MB)
35 20:14:27.820711 progress 60 % (2 MB)
36 20:14:27.822320 progress 65 % (2 MB)
37 20:14:27.823634 progress 70 % (3 MB)
38 20:14:27.825981 progress 75 % (3 MB)
39 20:14:27.828461 progress 80 % (3 MB)
40 20:14:27.830901 progress 85 % (3 MB)
41 20:14:27.833698 progress 90 % (4 MB)
42 20:14:27.836167 progress 95 % (4 MB)
43 20:14:27.838611 progress 100 % (4 MB)
44 20:14:27.838895 4 MB downloaded in 0.04 s (120.30 MB/s)
45 20:14:27.839196 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:14:27.839849 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:14:27.840035 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:14:27.840218 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:14:27.840467 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 20:14:27.840621 saving as /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/kernel/Image
52 20:14:27.840764 total size: 51601920 (49 MB)
53 20:14:27.840908 No compression specified
54 20:14:27.843278 progress 0 % (0 MB)
55 20:14:27.869495 progress 5 % (2 MB)
56 20:14:27.884712 progress 10 % (4 MB)
57 20:14:27.898551 progress 15 % (7 MB)
58 20:14:27.912082 progress 20 % (9 MB)
59 20:14:27.926044 progress 25 % (12 MB)
60 20:14:27.939598 progress 30 % (14 MB)
61 20:14:27.953277 progress 35 % (17 MB)
62 20:14:27.966563 progress 40 % (19 MB)
63 20:14:27.979942 progress 45 % (22 MB)
64 20:14:27.993584 progress 50 % (24 MB)
65 20:14:28.007063 progress 55 % (27 MB)
66 20:14:28.020379 progress 60 % (29 MB)
67 20:14:28.033992 progress 65 % (32 MB)
68 20:14:28.047608 progress 70 % (34 MB)
69 20:14:28.061231 progress 75 % (36 MB)
70 20:14:28.074497 progress 80 % (39 MB)
71 20:14:28.087812 progress 85 % (41 MB)
72 20:14:28.101026 progress 90 % (44 MB)
73 20:14:28.114100 progress 95 % (46 MB)
74 20:14:28.127149 progress 100 % (49 MB)
75 20:14:28.127391 49 MB downloaded in 0.29 s (171.69 MB/s)
76 20:14:28.127547 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:14:28.127796 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:14:28.127885 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:14:28.127971 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:14:28.128108 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 20:14:28.128186 saving as /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/dtb/mt8192-asurada-spherion-r0.dtb
83 20:14:28.128248 total size: 47278 (0 MB)
84 20:14:28.128310 No compression specified
85 20:14:28.129423 progress 69 % (0 MB)
86 20:14:28.129696 progress 100 % (0 MB)
87 20:14:28.129853 0 MB downloaded in 0.00 s (28.14 MB/s)
88 20:14:28.129977 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:14:28.130196 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:14:28.130285 start: 1.4 download-retry (timeout 00:10:00) [common]
92 20:14:28.130369 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 20:14:28.130481 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20240129.0/arm64/full.rootfs.tar.xz
94 20:14:28.130552 saving as /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/nfsrootfs/full.rootfs.tar
95 20:14:28.130612 total size: 89509512 (85 MB)
96 20:14:28.130673 Using unxz to decompress xz
97 20:14:28.134973 progress 0 % (0 MB)
98 20:14:28.344119 progress 5 % (4 MB)
99 20:14:28.557422 progress 10 % (8 MB)
100 20:14:28.805325 progress 15 % (12 MB)
101 20:14:29.000951 progress 20 % (17 MB)
102 20:14:29.110215 progress 25 % (21 MB)
103 20:14:29.351189 progress 30 % (25 MB)
104 20:14:29.634864 progress 35 % (29 MB)
105 20:14:29.898943 progress 40 % (34 MB)
106 20:14:30.160499 progress 45 % (38 MB)
107 20:14:30.404370 progress 50 % (42 MB)
108 20:14:30.661170 progress 55 % (46 MB)
109 20:14:30.908950 progress 60 % (51 MB)
110 20:14:31.170494 progress 65 % (55 MB)
111 20:14:31.466507 progress 70 % (59 MB)
112 20:14:31.759153 progress 75 % (64 MB)
113 20:14:32.048619 progress 80 % (68 MB)
114 20:14:32.301175 progress 85 % (72 MB)
115 20:14:32.523307 progress 90 % (76 MB)
116 20:14:32.776269 progress 95 % (81 MB)
117 20:14:33.033924 progress 100 % (85 MB)
118 20:14:33.039772 85 MB downloaded in 4.91 s (17.39 MB/s)
119 20:14:33.040031 end: 1.4.1 http-download (duration 00:00:05) [common]
121 20:14:33.040305 end: 1.4 download-retry (duration 00:00:05) [common]
122 20:14:33.040397 start: 1.5 download-retry (timeout 00:09:55) [common]
123 20:14:33.040486 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 20:14:33.040639 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:14:33.040710 saving as /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/modules/modules.tar
126 20:14:33.040771 total size: 8632284 (8 MB)
127 20:14:33.040835 Using unxz to decompress xz
128 20:14:33.045189 progress 0 % (0 MB)
129 20:14:33.065224 progress 5 % (0 MB)
130 20:14:33.088836 progress 10 % (0 MB)
131 20:14:33.112599 progress 15 % (1 MB)
132 20:14:33.134983 progress 20 % (1 MB)
133 20:14:33.159193 progress 25 % (2 MB)
134 20:14:33.185586 progress 30 % (2 MB)
135 20:14:33.213135 progress 35 % (2 MB)
136 20:14:33.238571 progress 40 % (3 MB)
137 20:14:33.263052 progress 45 % (3 MB)
138 20:14:33.287339 progress 50 % (4 MB)
139 20:14:33.311531 progress 55 % (4 MB)
140 20:14:33.336396 progress 60 % (4 MB)
141 20:14:33.360726 progress 65 % (5 MB)
142 20:14:33.385478 progress 70 % (5 MB)
143 20:14:33.410084 progress 75 % (6 MB)
144 20:14:33.436133 progress 80 % (6 MB)
145 20:14:33.460614 progress 85 % (7 MB)
146 20:14:33.486819 progress 90 % (7 MB)
147 20:14:33.515143 progress 95 % (7 MB)
148 20:14:33.543106 progress 100 % (8 MB)
149 20:14:33.548448 8 MB downloaded in 0.51 s (16.22 MB/s)
150 20:14:33.548701 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:14:33.548976 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:14:33.549071 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 20:14:33.549169 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 20:14:35.270697 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92
156 20:14:35.270919 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 20:14:35.271025 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 20:14:35.271192 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh
159 20:14:35.271329 makedir: /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin
160 20:14:35.271436 makedir: /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/tests
161 20:14:35.271536 makedir: /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/results
162 20:14:35.271638 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-add-keys
163 20:14:35.271945 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-add-sources
164 20:14:35.272079 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-background-process-start
165 20:14:35.272210 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-background-process-stop
166 20:14:35.272340 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-common-functions
167 20:14:35.272466 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-echo-ipv4
168 20:14:35.272594 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-install-packages
169 20:14:35.272723 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-installed-packages
170 20:14:35.272851 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-os-build
171 20:14:35.272978 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-probe-channel
172 20:14:35.273105 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-probe-ip
173 20:14:35.273233 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-target-ip
174 20:14:35.273360 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-target-mac
175 20:14:35.273487 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-target-storage
176 20:14:35.273616 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-case
177 20:14:35.273747 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-event
178 20:14:35.273874 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-feedback
179 20:14:35.274001 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-raise
180 20:14:35.274126 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-reference
181 20:14:35.274254 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-runner
182 20:14:35.274380 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-set
183 20:14:35.274506 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-test-shell
184 20:14:35.274633 Updating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-install-packages (oe)
185 20:14:35.274787 Updating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/bin/lava-installed-packages (oe)
186 20:14:35.274913 Creating /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/environment
187 20:14:35.275010 LAVA metadata
188 20:14:35.275081 - LAVA_JOB_ID=12928152
189 20:14:35.275145 - LAVA_DISPATCHER_IP=192.168.201.1
190 20:14:35.275248 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 20:14:35.275314 skipped lava-vland-overlay
192 20:14:35.275388 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 20:14:35.275467 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 20:14:35.275528 skipped lava-multinode-overlay
195 20:14:35.275600 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 20:14:35.275699 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 20:14:35.275788 Loading test definitions
198 20:14:35.275876 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 20:14:35.275945 Using /lava-12928152 at stage 0
200 20:14:35.276257 uuid=12928152_1.6.2.3.1 testdef=None
201 20:14:35.276347 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 20:14:35.276433 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 20:14:35.276926 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 20:14:35.277149 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 20:14:35.277763 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 20:14:35.277993 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 20:14:35.278594 runner path: /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/0/tests/0_lc-compliance test_uuid 12928152_1.6.2.3.1
210 20:14:35.278753 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 20:14:35.278961 Creating lava-test-runner.conf files
213 20:14:35.279024 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928152/lava-overlay-s8b5mdwh/lava-12928152/0 for stage 0
214 20:14:35.279114 - 0_lc-compliance
215 20:14:35.279212 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 20:14:35.279300 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 20:14:35.285374 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 20:14:35.285474 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 20:14:35.285560 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 20:14:35.285644 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 20:14:35.285730 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 20:14:35.412894 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 20:14:35.413276 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 20:14:35.413397 extracting modules file /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92
225 20:14:35.658601 extracting modules file /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928152/extract-overlay-ramdisk-g0uu6tm0/ramdisk
226 20:14:35.882966 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 20:14:35.883143 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 20:14:35.883239 [common] Applying overlay to NFS
229 20:14:35.883312 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928152/compress-overlay-1px2f75b/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92
230 20:14:35.889849 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 20:14:35.889959 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 20:14:35.890051 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 20:14:35.890140 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 20:14:35.890214 Building ramdisk /var/lib/lava/dispatcher/tmp/12928152/extract-overlay-ramdisk-g0uu6tm0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928152/extract-overlay-ramdisk-g0uu6tm0/ramdisk
235 20:14:36.223426 >> 119447 blocks
236 20:14:38.125934 rename /var/lib/lava/dispatcher/tmp/12928152/extract-overlay-ramdisk-g0uu6tm0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/ramdisk/ramdisk.cpio.gz
237 20:14:38.126381 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 20:14:38.126500 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 20:14:38.126604 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 20:14:38.126710 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/kernel/Image'
241 20:14:50.834342 Returned 0 in 12 seconds
242 20:14:50.934957 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/kernel/image.itb
243 20:14:51.294013 output: FIT description: Kernel Image image with one or more FDT blobs
244 20:14:51.294394 output: Created: Sun Mar 3 20:14:51 2024
245 20:14:51.294474 output: Image 0 (kernel-1)
246 20:14:51.294546 output: Description:
247 20:14:51.294614 output: Created: Sun Mar 3 20:14:51 2024
248 20:14:51.294676 output: Type: Kernel Image
249 20:14:51.294736 output: Compression: lzma compressed
250 20:14:51.294796 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
251 20:14:51.294854 output: Architecture: AArch64
252 20:14:51.294910 output: OS: Linux
253 20:14:51.294968 output: Load Address: 0x00000000
254 20:14:51.295041 output: Entry Point: 0x00000000
255 20:14:51.295114 output: Hash algo: crc32
256 20:14:51.295170 output: Hash value: 91cb1a17
257 20:14:51.295227 output: Image 1 (fdt-1)
258 20:14:51.295281 output: Description: mt8192-asurada-spherion-r0
259 20:14:51.295338 output: Created: Sun Mar 3 20:14:51 2024
260 20:14:51.295392 output: Type: Flat Device Tree
261 20:14:51.295446 output: Compression: uncompressed
262 20:14:51.295499 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 20:14:51.295554 output: Architecture: AArch64
264 20:14:51.295608 output: Hash algo: crc32
265 20:14:51.295660 output: Hash value: cc4352de
266 20:14:51.295750 output: Image 2 (ramdisk-1)
267 20:14:51.295803 output: Description: unavailable
268 20:14:51.295856 output: Created: Sun Mar 3 20:14:51 2024
269 20:14:51.295910 output: Type: RAMDisk Image
270 20:14:51.295963 output: Compression: Unknown Compression
271 20:14:51.296017 output: Data Size: 17808582 Bytes = 17391.19 KiB = 16.98 MiB
272 20:14:51.296070 output: Architecture: AArch64
273 20:14:51.296123 output: OS: Linux
274 20:14:51.296176 output: Load Address: unavailable
275 20:14:51.296229 output: Entry Point: unavailable
276 20:14:51.296281 output: Hash algo: crc32
277 20:14:51.296334 output: Hash value: ba3a8f8e
278 20:14:51.296387 output: Default Configuration: 'conf-1'
279 20:14:51.296441 output: Configuration 0 (conf-1)
280 20:14:51.296494 output: Description: mt8192-asurada-spherion-r0
281 20:14:51.296568 output: Kernel: kernel-1
282 20:14:51.296636 output: Init Ramdisk: ramdisk-1
283 20:14:51.296689 output: FDT: fdt-1
284 20:14:51.296742 output: Loadables: kernel-1
285 20:14:51.296795 output:
286 20:14:51.296999 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 20:14:51.297103 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 20:14:51.297207 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 20:14:51.297307 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 20:14:51.297392 No LXC device requested
291 20:14:51.297475 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 20:14:51.297560 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 20:14:51.297640 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 20:14:51.297716 Checking files for TFTP limit of 4294967296 bytes.
295 20:14:51.298219 end: 1 tftp-deploy (duration 00:00:23) [common]
296 20:14:51.298323 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 20:14:51.298416 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 20:14:51.298565 substitutions:
299 20:14:51.298666 - {DTB}: 12928152/tftp-deploy-w1fw5qu9/dtb/mt8192-asurada-spherion-r0.dtb
300 20:14:51.298781 - {INITRD}: 12928152/tftp-deploy-w1fw5qu9/ramdisk/ramdisk.cpio.gz
301 20:14:51.298841 - {KERNEL}: 12928152/tftp-deploy-w1fw5qu9/kernel/Image
302 20:14:51.298899 - {LAVA_MAC}: None
303 20:14:51.298956 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92
304 20:14:51.299015 - {NFS_SERVER_IP}: 192.168.201.1
305 20:14:51.299071 - {PRESEED_CONFIG}: None
306 20:14:51.299127 - {PRESEED_LOCAL}: None
307 20:14:51.299183 - {RAMDISK}: 12928152/tftp-deploy-w1fw5qu9/ramdisk/ramdisk.cpio.gz
308 20:14:51.299238 - {ROOT_PART}: None
309 20:14:51.299293 - {ROOT}: None
310 20:14:51.299348 - {SERVER_IP}: 192.168.201.1
311 20:14:51.299402 - {TEE}: None
312 20:14:51.299456 Parsed boot commands:
313 20:14:51.299511 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 20:14:51.299770 Parsed boot commands: tftpboot 192.168.201.1 12928152/tftp-deploy-w1fw5qu9/kernel/image.itb 12928152/tftp-deploy-w1fw5qu9/kernel/cmdline
315 20:14:51.299904 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 20:14:51.299994 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 20:14:51.300087 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 20:14:51.300173 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 20:14:51.300249 Not connected, no need to disconnect.
320 20:14:51.300325 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 20:14:51.300411 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 20:14:51.300487 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 20:14:51.304555 Setting prompt string to ['lava-test: # ']
324 20:14:51.304937 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 20:14:51.305049 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 20:14:51.305142 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 20:14:51.305255 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 20:14:51.305481 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
329 20:14:56.440151 >> Command sent successfully.
330 20:14:56.442586 Returned 0 in 5 seconds
331 20:14:56.542956 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 20:14:56.543291 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 20:14:56.543398 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 20:14:56.543486 Setting prompt string to 'Starting depthcharge on Spherion...'
336 20:14:56.543556 Changing prompt to 'Starting depthcharge on Spherion...'
337 20:14:56.543625 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 20:14:56.543939 [Enter `^Ec?' for help]
339 20:14:56.717876
340 20:14:56.718020
341 20:14:56.718091 F0: 102B 0000
342 20:14:56.718158
343 20:14:56.718222 F3: 1001 0000 [0200]
344 20:14:56.721068
345 20:14:56.721152 F3: 1001 0000
346 20:14:56.721220
347 20:14:56.721283 F7: 102D 0000
348 20:14:56.721343
349 20:14:56.724627 F1: 0000 0000
350 20:14:56.724712
351 20:14:56.724778 V0: 0000 0000 [0001]
352 20:14:56.724843
353 20:14:56.727414 00: 0007 8000
354 20:14:56.727502
355 20:14:56.727570 01: 0000 0000
356 20:14:56.727634
357 20:14:56.730907 BP: 0C00 0209 [0000]
358 20:14:56.730991
359 20:14:56.731057 G0: 1182 0000
360 20:14:56.731118
361 20:14:56.734508 EC: 0000 0021 [4000]
362 20:14:56.734592
363 20:14:56.734658 S7: 0000 0000 [0000]
364 20:14:56.734721
365 20:14:56.737851 CC: 0000 0000 [0001]
366 20:14:56.737935
367 20:14:56.738001 T0: 0000 0040 [010F]
368 20:14:56.738064
369 20:14:56.738123 Jump to BL
370 20:14:56.741490
371 20:14:56.764616
372 20:14:56.764702
373 20:14:56.764769
374 20:14:56.771759 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 20:14:56.775427 ARM64: Exception handlers installed.
376 20:14:56.779028 ARM64: Testing exception
377 20:14:56.782145 ARM64: Done test exception
378 20:14:56.788985 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 20:14:56.799442 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 20:14:56.806533 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 20:14:56.815633 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 20:14:56.822020 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 20:14:56.832316 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 20:14:56.842881 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 20:14:56.849321 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 20:14:56.867539 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 20:14:56.870868 WDT: Last reset was cold boot
388 20:14:56.874453 SPI1(PAD0) initialized at 2873684 Hz
389 20:14:56.878137 SPI5(PAD0) initialized at 992727 Hz
390 20:14:56.881002 VBOOT: Loading verstage.
391 20:14:56.887213 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 20:14:56.890746 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 20:14:56.894521 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 20:14:56.897403 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 20:14:56.904764 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 20:14:56.911778 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 20:14:56.922551 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 20:14:56.922636
399 20:14:56.922702
400 20:14:56.932541 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 20:14:56.936492 ARM64: Exception handlers installed.
402 20:14:56.939676 ARM64: Testing exception
403 20:14:56.939778 ARM64: Done test exception
404 20:14:56.946762 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 20:14:56.949394 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 20:14:56.963318 Probing TPM: . done!
407 20:14:56.963401 TPM ready after 0 ms
408 20:14:56.970575 Connected to device vid:did:rid of 1ae0:0028:00
409 20:14:56.978570 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 20:14:57.036734 Initialized TPM device CR50 revision 0
411 20:14:57.048995 tlcl_send_startup: Startup return code is 0
412 20:14:57.049085 TPM: setup succeeded
413 20:14:57.060290 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 20:14:57.069407 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 20:14:57.081323 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 20:14:57.090916 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 20:14:57.094463 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 20:14:57.098311 in-header: 03 07 00 00 08 00 00 00
419 20:14:57.101881 in-data: aa e4 47 04 13 02 00 00
420 20:14:57.105580 Chrome EC: UHEPI supported
421 20:14:57.109221 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 20:14:57.114194 in-header: 03 95 00 00 08 00 00 00
423 20:14:57.117755 in-data: 18 20 20 08 00 00 00 00
424 20:14:57.117839 Phase 1
425 20:14:57.121724 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 20:14:57.127969 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 20:14:57.135339 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 20:14:57.135469 Recovery requested (1009000e)
429 20:14:57.145990 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 20:14:57.153145 tlcl_extend: response is 0
431 20:14:57.162464 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 20:14:57.168553 tlcl_extend: response is 0
433 20:14:57.175710 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 20:14:57.194953 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 20:14:57.202093 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 20:14:57.202179
437 20:14:57.202247
438 20:14:57.211736 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 20:14:57.215023 ARM64: Exception handlers installed.
440 20:14:57.218869 ARM64: Testing exception
441 20:14:57.218954 ARM64: Done test exception
442 20:14:57.240657 pmic_efuse_setting: Set efuses in 11 msecs
443 20:14:57.243816 pmwrap_interface_init: Select PMIF_VLD_RDY
444 20:14:57.250442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 20:14:57.254056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 20:14:57.261315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 20:14:57.264727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 20:14:57.269183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 20:14:57.276102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 20:14:57.279234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 20:14:57.283880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 20:14:57.286793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 20:14:57.294631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 20:14:57.297853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 20:14:57.301500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 20:14:57.305196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 20:14:57.312476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 20:14:57.319912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 20:14:57.323936 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 20:14:57.331465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 20:14:57.335020 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 20:14:57.342174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 20:14:57.346448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 20:14:57.353125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 20:14:57.357131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 20:14:57.364823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 20:14:57.368211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 20:14:57.375595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 20:14:57.379306 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 20:14:57.386579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 20:14:57.390100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 20:14:57.393747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 20:14:57.400953 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 20:14:57.404817 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 20:14:57.408438 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 20:14:57.416013 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 20:14:57.419326 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 20:14:57.423385 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 20:14:57.430109 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 20:14:57.434531 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 20:14:57.440336 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 20:14:57.444305 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 20:14:57.447991 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 20:14:57.452231 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 20:14:57.459652 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 20:14:57.462362 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 20:14:57.466364 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 20:14:57.469685 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 20:14:57.473220 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 20:14:57.480491 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 20:14:57.484409 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 20:14:57.487627 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 20:14:57.491620 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 20:14:57.495193 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 20:14:57.502955 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 20:14:57.513388 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 20:14:57.517185 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 20:14:57.524164 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 20:14:57.535180 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 20:14:57.538422 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 20:14:57.541855 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 20:14:57.546117 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 20:14:57.553668 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1
504 20:14:57.561081 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 20:14:57.564266 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 20:14:57.568354 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 20:14:57.578131 [RTC]rtc_get_frequency_meter,154: input=15, output=834
508 20:14:57.588139 [RTC]rtc_get_frequency_meter,154: input=7, output=708
509 20:14:57.597437 [RTC]rtc_get_frequency_meter,154: input=11, output=771
510 20:14:57.606567 [RTC]rtc_get_frequency_meter,154: input=13, output=804
511 20:14:57.616458 [RTC]rtc_get_frequency_meter,154: input=12, output=788
512 20:14:57.625925 [RTC]rtc_get_frequency_meter,154: input=12, output=787
513 20:14:57.635605 [RTC]rtc_get_frequency_meter,154: input=13, output=803
514 20:14:57.638594 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 20:14:57.646030 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 20:14:57.649808 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 20:14:57.652992 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
518 20:14:57.657045 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 20:14:57.660745 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
520 20:14:57.664591 ADC[4]: Raw value=903400 ID=7
521 20:14:57.668391 ADC[3]: Raw value=213652 ID=1
522 20:14:57.668501 RAM Code: 0x71
523 20:14:57.671635 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 20:14:57.678861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 20:14:57.686471 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 20:14:57.693965 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 20:14:57.697370 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 20:14:57.701004 in-header: 03 07 00 00 08 00 00 00
529 20:14:57.704641 in-data: aa e4 47 04 13 02 00 00
530 20:14:57.704715 Chrome EC: UHEPI supported
531 20:14:57.711338 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 20:14:57.715641 in-header: 03 95 00 00 08 00 00 00
533 20:14:57.719283 in-data: 18 20 20 08 00 00 00 00
534 20:14:57.723236 MRC: failed to locate region type 0.
535 20:14:57.730013 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 20:14:57.730122 DRAM-K: Running full calibration
537 20:14:57.737330 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 20:14:57.741260 header.status = 0x0
539 20:14:57.741366 header.version = 0x6 (expected: 0x6)
540 20:14:57.744566 header.size = 0xd00 (expected: 0xd00)
541 20:14:57.748601 header.flags = 0x0
542 20:14:57.755558 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 20:14:57.771538 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 20:14:57.779541 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 20:14:57.782922 dram_init: ddr_geometry: 2
546 20:14:57.783027 [EMI] MDL number = 2
547 20:14:57.786468 [EMI] Get MDL freq = 0
548 20:14:57.786574 dram_init: ddr_type: 0
549 20:14:57.790602 is_discrete_lpddr4: 1
550 20:14:57.794559 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 20:14:57.794664
552 20:14:57.794756
553 20:14:57.794846 [Bian_co] ETT version 0.0.0.1
554 20:14:57.801072 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 20:14:57.801177
556 20:14:57.804328 dramc_set_vcore_voltage set vcore to 650000
557 20:14:57.808562 Read voltage for 800, 4
558 20:14:57.808640 Vio18 = 0
559 20:14:57.808704 Vcore = 650000
560 20:14:57.808800 Vdram = 0
561 20:14:57.812109 Vddq = 0
562 20:14:57.812182 Vmddr = 0
563 20:14:57.816318 dram_init: config_dvfs: 1
564 20:14:57.819416 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 20:14:57.823533 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 20:14:57.826778 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 20:14:57.830598 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 20:14:57.834369 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 20:14:57.840970 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 20:14:57.841047 MEM_TYPE=3, freq_sel=18
571 20:14:57.844226 sv_algorithm_assistance_LP4_1600
572 20:14:57.847408 ============ PULL DRAM RESETB DOWN ============
573 20:14:57.853958 ========== PULL DRAM RESETB DOWN end =========
574 20:14:57.857979 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 20:14:57.861444 ===================================
576 20:14:57.865021 LPDDR4 DRAM CONFIGURATION
577 20:14:57.865099 ===================================
578 20:14:57.868343 EX_ROW_EN[0] = 0x0
579 20:14:57.871845 EX_ROW_EN[1] = 0x0
580 20:14:57.871960 LP4Y_EN = 0x0
581 20:14:57.875658 WORK_FSP = 0x0
582 20:14:57.875787 WL = 0x2
583 20:14:57.879155 RL = 0x2
584 20:14:57.879256 BL = 0x2
585 20:14:57.879351 RPST = 0x0
586 20:14:57.882355 RD_PRE = 0x0
587 20:14:57.886640 WR_PRE = 0x1
588 20:14:57.886741 WR_PST = 0x0
589 20:14:57.888997 DBI_WR = 0x0
590 20:14:57.889096 DBI_RD = 0x0
591 20:14:57.893200 OTF = 0x1
592 20:14:57.893300 ===================================
593 20:14:57.896632 ===================================
594 20:14:57.900924 ANA top config
595 20:14:57.903551 ===================================
596 20:14:57.903651 DLL_ASYNC_EN = 0
597 20:14:57.907206 ALL_SLAVE_EN = 1
598 20:14:57.910497 NEW_RANK_MODE = 1
599 20:14:57.913718 DLL_IDLE_MODE = 1
600 20:14:57.913827 LP45_APHY_COMB_EN = 1
601 20:14:57.916999 TX_ODT_DIS = 1
602 20:14:57.920418 NEW_8X_MODE = 1
603 20:14:57.923683 ===================================
604 20:14:57.927239 ===================================
605 20:14:57.930196 data_rate = 1600
606 20:14:57.933440 CKR = 1
607 20:14:57.936866 DQ_P2S_RATIO = 8
608 20:14:57.940530 ===================================
609 20:14:57.940636 CA_P2S_RATIO = 8
610 20:14:57.943908 DQ_CA_OPEN = 0
611 20:14:57.947110 DQ_SEMI_OPEN = 0
612 20:14:57.950048 CA_SEMI_OPEN = 0
613 20:14:57.953774 CA_FULL_RATE = 0
614 20:14:57.956622 DQ_CKDIV4_EN = 1
615 20:14:57.956708 CA_CKDIV4_EN = 1
616 20:14:57.960156 CA_PREDIV_EN = 0
617 20:14:57.963363 PH8_DLY = 0
618 20:14:57.966833 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 20:14:57.969807 DQ_AAMCK_DIV = 4
620 20:14:57.973293 CA_AAMCK_DIV = 4
621 20:14:57.973378 CA_ADMCK_DIV = 4
622 20:14:57.976508 DQ_TRACK_CA_EN = 0
623 20:14:57.979951 CA_PICK = 800
624 20:14:57.984000 CA_MCKIO = 800
625 20:14:57.986680 MCKIO_SEMI = 0
626 20:14:57.990700 PLL_FREQ = 3068
627 20:14:57.990787 DQ_UI_PI_RATIO = 32
628 20:14:57.993639 CA_UI_PI_RATIO = 0
629 20:14:57.997327 ===================================
630 20:14:58.001721 ===================================
631 20:14:58.005064 memory_type:LPDDR4
632 20:14:58.005147 GP_NUM : 10
633 20:14:58.008255 SRAM_EN : 1
634 20:14:58.008370 MD32_EN : 0
635 20:14:58.012531 ===================================
636 20:14:58.015896 [ANA_INIT] >>>>>>>>>>>>>>
637 20:14:58.019503 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 20:14:58.023501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 20:14:58.026811 ===================================
640 20:14:58.026933 data_rate = 1600,PCW = 0X7600
641 20:14:58.030575 ===================================
642 20:14:58.033888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 20:14:58.041572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 20:14:58.046614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 20:14:58.049967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 20:14:58.053841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 20:14:58.057214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 20:14:58.060007 [ANA_INIT] flow start
649 20:14:58.060088 [ANA_INIT] PLL >>>>>>>>
650 20:14:58.063931 [ANA_INIT] PLL <<<<<<<<
651 20:14:58.066601 [ANA_INIT] MIDPI >>>>>>>>
652 20:14:58.066699 [ANA_INIT] MIDPI <<<<<<<<
653 20:14:58.069792 [ANA_INIT] DLL >>>>>>>>
654 20:14:58.073432 [ANA_INIT] flow end
655 20:14:58.077084 ============ LP4 DIFF to SE enter ============
656 20:14:58.080153 ============ LP4 DIFF to SE exit ============
657 20:14:58.083434 [ANA_INIT] <<<<<<<<<<<<<
658 20:14:58.087597 [Flow] Enable top DCM control >>>>>
659 20:14:58.090062 [Flow] Enable top DCM control <<<<<
660 20:14:58.093361 Enable DLL master slave shuffle
661 20:14:58.096539 ==============================================================
662 20:14:58.100281 Gating Mode config
663 20:14:58.106454 ==============================================================
664 20:14:58.106537 Config description:
665 20:14:58.116498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 20:14:58.123214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 20:14:58.129581 SELPH_MODE 0: By rank 1: By Phase
668 20:14:58.132736 ==============================================================
669 20:14:58.136146 GAT_TRACK_EN = 1
670 20:14:58.139875 RX_GATING_MODE = 2
671 20:14:58.142628 RX_GATING_TRACK_MODE = 2
672 20:14:58.146216 SELPH_MODE = 1
673 20:14:58.149433 PICG_EARLY_EN = 1
674 20:14:58.153057 VALID_LAT_VALUE = 1
675 20:14:58.156829 ==============================================================
676 20:14:58.159830 Enter into Gating configuration >>>>
677 20:14:58.163276 Exit from Gating configuration <<<<
678 20:14:58.165896 Enter into DVFS_PRE_config >>>>>
679 20:14:58.179426 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 20:14:58.182703 Exit from DVFS_PRE_config <<<<<
681 20:14:58.186186 Enter into PICG configuration >>>>
682 20:14:58.188926 Exit from PICG configuration <<<<
683 20:14:58.189009 [RX_INPUT] configuration >>>>>
684 20:14:58.192404 [RX_INPUT] configuration <<<<<
685 20:14:58.199216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 20:14:58.202259 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 20:14:58.208898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 20:14:58.215827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 20:14:58.222707 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 20:14:58.228796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 20:14:58.232181 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 20:14:58.235301 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 20:14:58.241810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 20:14:58.244986 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 20:14:58.248777 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 20:14:58.254833 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 20:14:58.258574 ===================================
698 20:14:58.258679 LPDDR4 DRAM CONFIGURATION
699 20:14:58.261911 ===================================
700 20:14:58.265476 EX_ROW_EN[0] = 0x0
701 20:14:58.265584 EX_ROW_EN[1] = 0x0
702 20:14:58.269286 LP4Y_EN = 0x0
703 20:14:58.269389 WORK_FSP = 0x0
704 20:14:58.271524 WL = 0x2
705 20:14:58.271626 RL = 0x2
706 20:14:58.275394 BL = 0x2
707 20:14:58.275503 RPST = 0x0
708 20:14:58.278220 RD_PRE = 0x0
709 20:14:58.281492 WR_PRE = 0x1
710 20:14:58.281595 WR_PST = 0x0
711 20:14:58.285220 DBI_WR = 0x0
712 20:14:58.285321 DBI_RD = 0x0
713 20:14:58.288281 OTF = 0x1
714 20:14:58.291365 ===================================
715 20:14:58.294996 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 20:14:58.297913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 20:14:58.301451 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 20:14:58.304789 ===================================
719 20:14:58.308089 LPDDR4 DRAM CONFIGURATION
720 20:14:58.312030 ===================================
721 20:14:58.314907 EX_ROW_EN[0] = 0x10
722 20:14:58.315019 EX_ROW_EN[1] = 0x0
723 20:14:58.318109 LP4Y_EN = 0x0
724 20:14:58.318206 WORK_FSP = 0x0
725 20:14:58.321415 WL = 0x2
726 20:14:58.321492 RL = 0x2
727 20:14:58.324478 BL = 0x2
728 20:14:58.324553 RPST = 0x0
729 20:14:58.328496 RD_PRE = 0x0
730 20:14:58.330984 WR_PRE = 0x1
731 20:14:58.331085 WR_PST = 0x0
732 20:14:58.334258 DBI_WR = 0x0
733 20:14:58.334361 DBI_RD = 0x0
734 20:14:58.337969 OTF = 0x1
735 20:14:58.341275 ===================================
736 20:14:58.344691 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 20:14:58.350309 nWR fixed to 40
738 20:14:58.353456 [ModeRegInit_LP4] CH0 RK0
739 20:14:58.353548 [ModeRegInit_LP4] CH0 RK1
740 20:14:58.356354 [ModeRegInit_LP4] CH1 RK0
741 20:14:58.359919 [ModeRegInit_LP4] CH1 RK1
742 20:14:58.360002 match AC timing 13
743 20:14:58.366944 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 20:14:58.369596 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 20:14:58.373841 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 20:14:58.380270 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 20:14:58.383387 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 20:14:58.383492 [EMI DOE] emi_dcm 0
749 20:14:58.390091 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 20:14:58.390197 ==
751 20:14:58.393339 Dram Type= 6, Freq= 0, CH_0, rank 0
752 20:14:58.396790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 20:14:58.396897 ==
754 20:14:58.403594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 20:14:58.409389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 20:14:58.417677 [CA 0] Center 37 (7~68) winsize 62
757 20:14:58.420889 [CA 1] Center 36 (6~67) winsize 62
758 20:14:58.424702 [CA 2] Center 34 (4~65) winsize 62
759 20:14:58.427999 [CA 3] Center 34 (4~65) winsize 62
760 20:14:58.431239 [CA 4] Center 34 (4~64) winsize 61
761 20:14:58.433853 [CA 5] Center 33 (3~64) winsize 62
762 20:14:58.433953
763 20:14:58.437087 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 20:14:58.437161
765 20:14:58.440910 [CATrainingPosCal] consider 1 rank data
766 20:14:58.443613 u2DelayCellTimex100 = 270/100 ps
767 20:14:58.446780 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 20:14:58.453795 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
769 20:14:58.456746 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 20:14:58.460493 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 20:14:58.463465 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
772 20:14:58.466699 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 20:14:58.466801
774 20:14:58.469802 CA PerBit enable=1, Macro0, CA PI delay=33
775 20:14:58.469906
776 20:14:58.473175 [CBTSetCACLKResult] CA Dly = 33
777 20:14:58.476711 CS Dly: 7 (0~38)
778 20:14:58.476816 ==
779 20:14:58.479707 Dram Type= 6, Freq= 0, CH_0, rank 1
780 20:14:58.483538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 20:14:58.483645 ==
782 20:14:58.490058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 20:14:58.493056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 20:14:58.503496 [CA 0] Center 37 (6~68) winsize 63
785 20:14:58.506662 [CA 1] Center 37 (7~68) winsize 62
786 20:14:58.510038 [CA 2] Center 34 (4~65) winsize 62
787 20:14:58.513315 [CA 3] Center 34 (4~65) winsize 62
788 20:14:58.516847 [CA 4] Center 33 (3~64) winsize 62
789 20:14:58.520045 [CA 5] Center 33 (3~64) winsize 62
790 20:14:58.520137
791 20:14:58.523249 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 20:14:58.523348
793 20:14:58.526503 [CATrainingPosCal] consider 2 rank data
794 20:14:58.529648 u2DelayCellTimex100 = 270/100 ps
795 20:14:58.533030 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 20:14:58.539658 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
797 20:14:58.542731 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 20:14:58.546144 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 20:14:58.550220 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
800 20:14:58.552882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 20:14:58.552989
802 20:14:58.556216 CA PerBit enable=1, Macro0, CA PI delay=33
803 20:14:58.556325
804 20:14:58.559551 [CBTSetCACLKResult] CA Dly = 33
805 20:14:58.563141 CS Dly: 7 (0~38)
806 20:14:58.563271
807 20:14:58.566065 ----->DramcWriteLeveling(PI) begin...
808 20:14:58.566174 ==
809 20:14:58.569607 Dram Type= 6, Freq= 0, CH_0, rank 0
810 20:14:58.573622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 20:14:58.573724 ==
812 20:14:58.576947 Write leveling (Byte 0): 32 => 32
813 20:14:58.580709 Write leveling (Byte 1): 31 => 31
814 20:14:58.580796 DramcWriteLeveling(PI) end<-----
815 20:14:58.580870
816 20:14:58.584685 ==
817 20:14:58.584797 Dram Type= 6, Freq= 0, CH_0, rank 0
818 20:14:58.588422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 20:14:58.591455 ==
820 20:14:58.591535 [Gating] SW mode calibration
821 20:14:58.601706 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 20:14:58.605038 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 20:14:58.608662 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 20:14:58.614996 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 20:14:58.618445 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
826 20:14:58.621611 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 20:14:58.628711 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 20:14:58.631387 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 20:14:58.635388 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 20:14:58.641293 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 20:14:58.645154 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 20:14:58.648730 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 20:14:58.655269 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 20:14:58.658577 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 20:14:58.661590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 20:14:58.668395 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 20:14:58.671765 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 20:14:58.675137 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 20:14:58.678530 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 20:14:58.685177 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 20:14:58.688246 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 20:14:58.691786 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 20:14:58.698441 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 20:14:58.701771 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 20:14:58.705176 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 20:14:58.711702 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 20:14:58.715170 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 20:14:58.718469 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 20:14:58.724865 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
850 20:14:58.727953 0 9 12 | B1->B0 | 2928 3434 | 1 1 | (1 1) (1 1)
851 20:14:58.731214 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 20:14:58.737876 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 20:14:58.741468 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 20:14:58.744349 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 20:14:58.751004 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 20:14:58.755147 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
857 20:14:58.758245 0 10 8 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
858 20:14:58.764416 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
859 20:14:58.767972 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:14:58.771462 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:14:58.777704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:14:58.781883 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:14:58.784301 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 20:14:58.790853 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 20:14:58.794554 0 11 8 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
866 20:14:58.797771 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
867 20:14:58.804888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 20:14:58.807599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 20:14:58.811108 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 20:14:58.817118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 20:14:58.820513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 20:14:58.824659 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 20:14:58.830655 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 20:14:58.833949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 20:14:58.837251 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 20:14:58.843941 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 20:14:58.847050 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 20:14:58.850502 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 20:14:58.857522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 20:14:58.860376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 20:14:58.863631 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 20:14:58.870366 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 20:14:58.874038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 20:14:58.876888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 20:14:58.884178 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 20:14:58.886823 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 20:14:58.890599 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 20:14:58.896760 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 20:14:58.900434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
890 20:14:58.903826 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 20:14:58.906882 Total UI for P1: 0, mck2ui 16
892 20:14:58.909857 best dqsien dly found for B0: ( 0, 14, 8)
893 20:14:58.913694 Total UI for P1: 0, mck2ui 16
894 20:14:58.917045 best dqsien dly found for B1: ( 0, 14, 10)
895 20:14:58.920392 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 20:14:58.923392 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 20:14:58.923868
898 20:14:58.926641 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 20:14:58.933391 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 20:14:58.933984 [Gating] SW calibration Done
901 20:14:58.934343 ==
902 20:14:58.936594 Dram Type= 6, Freq= 0, CH_0, rank 0
903 20:14:58.943860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 20:14:58.944322 ==
905 20:14:58.944675 RX Vref Scan: 0
906 20:14:58.944996
907 20:14:58.946859 RX Vref 0 -> 0, step: 1
908 20:14:58.947290
909 20:14:58.950361 RX Delay -130 -> 252, step: 16
910 20:14:58.953478 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 20:14:58.956182 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 20:14:58.959827 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 20:14:58.966185 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 20:14:58.970074 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 20:14:58.972873 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 20:14:58.976197 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
917 20:14:58.979618 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
918 20:14:58.985894 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 20:14:58.990321 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 20:14:58.992734 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 20:14:58.996371 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
922 20:14:58.999712 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
923 20:14:59.003821 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 20:14:59.010139 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 20:14:59.013794 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 20:14:59.014254 ==
927 20:14:59.017009 Dram Type= 6, Freq= 0, CH_0, rank 0
928 20:14:59.020558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 20:14:59.021045 ==
930 20:14:59.023595 DQS Delay:
931 20:14:59.024096 DQS0 = 0, DQS1 = 0
932 20:14:59.024447 DQM Delay:
933 20:14:59.027086 DQM0 = 85, DQM1 = 73
934 20:14:59.027518 DQ Delay:
935 20:14:59.030759 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 20:14:59.033243 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
937 20:14:59.036870 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
938 20:14:59.040845 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
939 20:14:59.041373
940 20:14:59.041771
941 20:14:59.042098 ==
942 20:14:59.043954 Dram Type= 6, Freq= 0, CH_0, rank 0
943 20:14:59.049890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 20:14:59.050347 ==
945 20:14:59.050700
946 20:14:59.051016
947 20:14:59.051332 TX Vref Scan disable
948 20:14:59.053498 == TX Byte 0 ==
949 20:14:59.057465 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
950 20:14:59.063568 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
951 20:14:59.064073 == TX Byte 1 ==
952 20:14:59.066897 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
953 20:14:59.073961 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
954 20:14:59.074393 ==
955 20:14:59.077196 Dram Type= 6, Freq= 0, CH_0, rank 0
956 20:14:59.079781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 20:14:59.080220 ==
958 20:14:59.092432 TX Vref=22, minBit 4, minWin=27, winSum=443
959 20:14:59.096021 TX Vref=24, minBit 4, minWin=27, winSum=443
960 20:14:59.098877 TX Vref=26, minBit 8, minWin=27, winSum=446
961 20:14:59.102429 TX Vref=28, minBit 10, minWin=27, winSum=448
962 20:14:59.105892 TX Vref=30, minBit 10, minWin=27, winSum=448
963 20:14:59.112802 TX Vref=32, minBit 4, minWin=27, winSum=448
964 20:14:59.115783 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 28
965 20:14:59.116231
966 20:14:59.119602 Final TX Range 1 Vref 28
967 20:14:59.120094
968 20:14:59.120557 ==
969 20:14:59.122247 Dram Type= 6, Freq= 0, CH_0, rank 0
970 20:14:59.125602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 20:14:59.129669 ==
972 20:14:59.130122
973 20:14:59.130476
974 20:14:59.130795 TX Vref Scan disable
975 20:14:59.132567 == TX Byte 0 ==
976 20:14:59.135728 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 20:14:59.140174 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 20:14:59.143513 == TX Byte 1 ==
979 20:14:59.146300 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 20:14:59.149419 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 20:14:59.152444
982 20:14:59.152873 [DATLAT]
983 20:14:59.153234 Freq=800, CH0 RK0
984 20:14:59.153567
985 20:14:59.156142 DATLAT Default: 0xa
986 20:14:59.156616 0, 0xFFFF, sum = 0
987 20:14:59.159172 1, 0xFFFF, sum = 0
988 20:14:59.159667 2, 0xFFFF, sum = 0
989 20:14:59.163002 3, 0xFFFF, sum = 0
990 20:14:59.163466 4, 0xFFFF, sum = 0
991 20:14:59.165867 5, 0xFFFF, sum = 0
992 20:14:59.169826 6, 0xFFFF, sum = 0
993 20:14:59.170312 7, 0xFFFF, sum = 0
994 20:14:59.172902 8, 0xFFFF, sum = 0
995 20:14:59.173344 9, 0x0, sum = 1
996 20:14:59.173745 10, 0x0, sum = 2
997 20:14:59.176029 11, 0x0, sum = 3
998 20:14:59.176677 12, 0x0, sum = 4
999 20:14:59.179480 best_step = 10
1000 20:14:59.180044
1001 20:14:59.180395 ==
1002 20:14:59.182394 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 20:14:59.185873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 20:14:59.186316 ==
1005 20:14:59.188896 RX Vref Scan: 1
1006 20:14:59.189351
1007 20:14:59.189713 Set Vref Range= 32 -> 127
1008 20:14:59.192828
1009 20:14:59.193274 RX Vref 32 -> 127, step: 1
1010 20:14:59.193617
1011 20:14:59.196346 RX Delay -111 -> 252, step: 8
1012 20:14:59.196790
1013 20:14:59.199276 Set Vref, RX VrefLevel [Byte0]: 32
1014 20:14:59.202365 [Byte1]: 32
1015 20:14:59.202947
1016 20:14:59.205927 Set Vref, RX VrefLevel [Byte0]: 33
1017 20:14:59.208981 [Byte1]: 33
1018 20:14:59.213103
1019 20:14:59.213530 Set Vref, RX VrefLevel [Byte0]: 34
1020 20:14:59.216573 [Byte1]: 34
1021 20:14:59.220631
1022 20:14:59.221063 Set Vref, RX VrefLevel [Byte0]: 35
1023 20:14:59.224184 [Byte1]: 35
1024 20:14:59.229016
1025 20:14:59.229483 Set Vref, RX VrefLevel [Byte0]: 36
1026 20:14:59.231413 [Byte1]: 36
1027 20:14:59.236238
1028 20:14:59.236664 Set Vref, RX VrefLevel [Byte0]: 37
1029 20:14:59.239507 [Byte1]: 37
1030 20:14:59.244723
1031 20:14:59.245171 Set Vref, RX VrefLevel [Byte0]: 38
1032 20:14:59.247497 [Byte1]: 38
1033 20:14:59.251774
1034 20:14:59.252218 Set Vref, RX VrefLevel [Byte0]: 39
1035 20:14:59.255065 [Byte1]: 39
1036 20:14:59.259207
1037 20:14:59.259822 Set Vref, RX VrefLevel [Byte0]: 40
1038 20:14:59.262597 [Byte1]: 40
1039 20:14:59.267006
1040 20:14:59.267429 Set Vref, RX VrefLevel [Byte0]: 41
1041 20:14:59.270135 [Byte1]: 41
1042 20:14:59.274671
1043 20:14:59.275229 Set Vref, RX VrefLevel [Byte0]: 42
1044 20:14:59.277629 [Byte1]: 42
1045 20:14:59.281715
1046 20:14:59.282126 Set Vref, RX VrefLevel [Byte0]: 43
1047 20:14:59.285195 [Byte1]: 43
1048 20:14:59.289445
1049 20:14:59.289845 Set Vref, RX VrefLevel [Byte0]: 44
1050 20:14:59.293403 [Byte1]: 44
1051 20:14:59.297492
1052 20:14:59.297913 Set Vref, RX VrefLevel [Byte0]: 45
1053 20:14:59.300698 [Byte1]: 45
1054 20:14:59.304968
1055 20:14:59.305537 Set Vref, RX VrefLevel [Byte0]: 46
1056 20:14:59.308498 [Byte1]: 46
1057 20:14:59.313017
1058 20:14:59.313440 Set Vref, RX VrefLevel [Byte0]: 47
1059 20:14:59.315555 [Byte1]: 47
1060 20:14:59.320123
1061 20:14:59.320547 Set Vref, RX VrefLevel [Byte0]: 48
1062 20:14:59.323744 [Byte1]: 48
1063 20:14:59.327610
1064 20:14:59.328083 Set Vref, RX VrefLevel [Byte0]: 49
1065 20:14:59.331451 [Byte1]: 49
1066 20:14:59.335517
1067 20:14:59.336069 Set Vref, RX VrefLevel [Byte0]: 50
1068 20:14:59.338789 [Byte1]: 50
1069 20:14:59.343386
1070 20:14:59.343956 Set Vref, RX VrefLevel [Byte0]: 51
1071 20:14:59.346639 [Byte1]: 51
1072 20:14:59.350756
1073 20:14:59.351273 Set Vref, RX VrefLevel [Byte0]: 52
1074 20:14:59.354489 [Byte1]: 52
1075 20:14:59.358490
1076 20:14:59.358934 Set Vref, RX VrefLevel [Byte0]: 53
1077 20:14:59.361906 [Byte1]: 53
1078 20:14:59.366036
1079 20:14:59.366613 Set Vref, RX VrefLevel [Byte0]: 54
1080 20:14:59.369411 [Byte1]: 54
1081 20:14:59.373887
1082 20:14:59.374314 Set Vref, RX VrefLevel [Byte0]: 55
1083 20:14:59.377622 [Byte1]: 55
1084 20:14:59.381525
1085 20:14:59.381940 Set Vref, RX VrefLevel [Byte0]: 56
1086 20:14:59.385100 [Byte1]: 56
1087 20:14:59.388732
1088 20:14:59.389148 Set Vref, RX VrefLevel [Byte0]: 57
1089 20:14:59.392566 [Byte1]: 57
1090 20:14:59.396665
1091 20:14:59.397121 Set Vref, RX VrefLevel [Byte0]: 58
1092 20:14:59.400149 [Byte1]: 58
1093 20:14:59.404544
1094 20:14:59.404957 Set Vref, RX VrefLevel [Byte0]: 59
1095 20:14:59.407830 [Byte1]: 59
1096 20:14:59.412445
1097 20:14:59.412858 Set Vref, RX VrefLevel [Byte0]: 60
1098 20:14:59.415649 [Byte1]: 60
1099 20:14:59.419273
1100 20:14:59.419920 Set Vref, RX VrefLevel [Byte0]: 61
1101 20:14:59.423141 [Byte1]: 61
1102 20:14:59.427166
1103 20:14:59.427771 Set Vref, RX VrefLevel [Byte0]: 62
1104 20:14:59.430647 [Byte1]: 62
1105 20:14:59.434733
1106 20:14:59.435273 Set Vref, RX VrefLevel [Byte0]: 63
1107 20:14:59.438111 [Byte1]: 63
1108 20:14:59.442469
1109 20:14:59.442935 Set Vref, RX VrefLevel [Byte0]: 64
1110 20:14:59.445670 [Byte1]: 64
1111 20:14:59.450891
1112 20:14:59.451312 Set Vref, RX VrefLevel [Byte0]: 65
1113 20:14:59.453302 [Byte1]: 65
1114 20:14:59.457849
1115 20:14:59.458280 Set Vref, RX VrefLevel [Byte0]: 66
1116 20:14:59.461220 [Byte1]: 66
1117 20:14:59.465536
1118 20:14:59.466027 Set Vref, RX VrefLevel [Byte0]: 67
1119 20:14:59.468700 [Byte1]: 67
1120 20:14:59.473012
1121 20:14:59.473453 Set Vref, RX VrefLevel [Byte0]: 68
1122 20:14:59.476569 [Byte1]: 68
1123 20:14:59.481121
1124 20:14:59.481564 Set Vref, RX VrefLevel [Byte0]: 69
1125 20:14:59.484270 [Byte1]: 69
1126 20:14:59.488641
1127 20:14:59.489058 Set Vref, RX VrefLevel [Byte0]: 70
1128 20:14:59.494779 [Byte1]: 70
1129 20:14:59.495196
1130 20:14:59.498510 Set Vref, RX VrefLevel [Byte0]: 71
1131 20:14:59.501864 [Byte1]: 71
1132 20:14:59.502287
1133 20:14:59.505133 Set Vref, RX VrefLevel [Byte0]: 72
1134 20:14:59.508366 [Byte1]: 72
1135 20:14:59.511180
1136 20:14:59.511604 Set Vref, RX VrefLevel [Byte0]: 73
1137 20:14:59.514876 [Byte1]: 73
1138 20:14:59.519031
1139 20:14:59.519455 Set Vref, RX VrefLevel [Byte0]: 74
1140 20:14:59.522184 [Byte1]: 74
1141 20:14:59.526829
1142 20:14:59.527306 Set Vref, RX VrefLevel [Byte0]: 75
1143 20:14:59.530274 [Byte1]: 75
1144 20:14:59.534978
1145 20:14:59.535458 Set Vref, RX VrefLevel [Byte0]: 76
1146 20:14:59.537748 [Byte1]: 76
1147 20:14:59.542085
1148 20:14:59.542589 Set Vref, RX VrefLevel [Byte0]: 77
1149 20:14:59.545342 [Byte1]: 77
1150 20:14:59.549557
1151 20:14:59.550219 Set Vref, RX VrefLevel [Byte0]: 78
1152 20:14:59.553057 [Byte1]: 78
1153 20:14:59.557443
1154 20:14:59.558000 Set Vref, RX VrefLevel [Byte0]: 79
1155 20:14:59.560602 [Byte1]: 79
1156 20:14:59.564951
1157 20:14:59.565377 Set Vref, RX VrefLevel [Byte0]: 80
1158 20:14:59.568137 [Byte1]: 80
1159 20:14:59.572960
1160 20:14:59.573549 Set Vref, RX VrefLevel [Byte0]: 81
1161 20:14:59.575651 [Byte1]: 81
1162 20:14:59.580220
1163 20:14:59.580643 Final RX Vref Byte 0 = 64 to rank0
1164 20:14:59.583739 Final RX Vref Byte 1 = 51 to rank0
1165 20:14:59.587021 Final RX Vref Byte 0 = 64 to rank1
1166 20:14:59.590131 Final RX Vref Byte 1 = 51 to rank1==
1167 20:14:59.593587 Dram Type= 6, Freq= 0, CH_0, rank 0
1168 20:14:59.600666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1169 20:14:59.601094 ==
1170 20:14:59.601433 DQS Delay:
1171 20:14:59.603536 DQS0 = 0, DQS1 = 0
1172 20:14:59.604008 DQM Delay:
1173 20:14:59.604349 DQM0 = 87, DQM1 = 76
1174 20:14:59.606784 DQ Delay:
1175 20:14:59.610017 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1176 20:14:59.613417 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1177 20:14:59.616443 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1178 20:14:59.620202 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1179 20:14:59.620726
1180 20:14:59.621066
1181 20:14:59.626382 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e20, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
1182 20:14:59.629975 CH0 RK0: MR19=606, MR18=3E20
1183 20:14:59.677313 CH0_RK0: MR19=0x606, MR18=0x3E20, DQSOSC=394, MR23=63, INC=95, DEC=63
1184 20:14:59.678197
1185 20:14:59.678882 ----->DramcWriteLeveling(PI) begin...
1186 20:14:59.679402 ==
1187 20:14:59.680206 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 20:14:59.680543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 20:14:59.680849 ==
1190 20:14:59.681144 Write leveling (Byte 0): 36 => 36
1191 20:14:59.681432 Write leveling (Byte 1): 31 => 31
1192 20:14:59.681716 DramcWriteLeveling(PI) end<-----
1193 20:14:59.681995
1194 20:14:59.682273 ==
1195 20:14:59.682548 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 20:14:59.682826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 20:14:59.683103 ==
1198 20:14:59.683381 [Gating] SW mode calibration
1199 20:14:59.683658 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1200 20:14:59.694894 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1201 20:14:59.695396 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 20:14:59.696106 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1203 20:14:59.696447 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1204 20:14:59.698335 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1205 20:14:59.701959 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 20:14:59.705362 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 20:14:59.708370 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 20:14:59.715252 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 20:14:59.718401 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 20:14:59.721607 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 20:14:59.728442 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 20:14:59.731864 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 20:14:59.734700 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 20:14:59.741704 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 20:14:59.744950 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 20:14:59.748327 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 20:14:59.754895 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 20:14:59.758298 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1219 20:14:59.762149 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1220 20:14:59.768431 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 20:14:59.771624 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 20:14:59.774500 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 20:14:59.781550 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 20:14:59.784337 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 20:14:59.788132 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 20:14:59.794486 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 20:14:59.798710 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1228 20:14:59.801172 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1229 20:14:59.807426 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 20:14:59.811256 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 20:14:59.814724 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 20:14:59.821693 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 20:14:59.824991 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 20:14:59.828739 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1235 20:14:59.832340 0 10 8 | B1->B0 | 3333 2b2b | 1 0 | (1 0) (1 0)
1236 20:14:59.836255 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1237 20:14:59.843540 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 20:14:59.845899 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 20:14:59.853342 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 20:14:59.854165 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 20:14:59.860566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 20:14:59.863134 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1243 20:14:59.867263 0 11 8 | B1->B0 | 2e2d 3d3d | 1 0 | (0 0) (0 0)
1244 20:14:59.873349 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1245 20:14:59.876703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 20:14:59.879660 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 20:14:59.887413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 20:14:59.889876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 20:14:59.892921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 20:14:59.899984 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 20:14:59.903085 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1252 20:14:59.906965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 20:14:59.913114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 20:14:59.916181 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 20:14:59.919763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 20:14:59.926280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 20:14:59.929292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 20:14:59.932965 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 20:14:59.939473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 20:14:59.942410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 20:14:59.946568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 20:14:59.952688 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 20:14:59.955792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 20:14:59.959798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 20:14:59.965811 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 20:14:59.969037 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1267 20:14:59.972749 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1268 20:14:59.975728 Total UI for P1: 0, mck2ui 16
1269 20:14:59.979187 best dqsien dly found for B0: ( 0, 14, 4)
1270 20:14:59.985826 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1271 20:14:59.988778 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 20:14:59.992179 Total UI for P1: 0, mck2ui 16
1273 20:14:59.996233 best dqsien dly found for B1: ( 0, 14, 8)
1274 20:14:59.999751 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1275 20:15:00.002389 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1276 20:15:00.002976
1277 20:15:00.005630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1278 20:15:00.008812 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1279 20:15:00.012377 [Gating] SW calibration Done
1280 20:15:00.012803 ==
1281 20:15:00.015491 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 20:15:00.018843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 20:15:00.019380 ==
1284 20:15:00.022785 RX Vref Scan: 0
1285 20:15:00.023214
1286 20:15:00.025424 RX Vref 0 -> 0, step: 1
1287 20:15:00.026026
1288 20:15:00.028444 RX Delay -130 -> 252, step: 16
1289 20:15:00.032116 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1290 20:15:00.035610 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1291 20:15:00.038337 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1292 20:15:00.041747 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1293 20:15:00.048579 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1294 20:15:00.052085 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1295 20:15:00.054996 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1296 20:15:00.058957 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1297 20:15:00.062014 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1298 20:15:00.068611 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1299 20:15:00.071498 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1300 20:15:00.075055 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1301 20:15:00.077885 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1302 20:15:00.081443 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1303 20:15:00.088251 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1304 20:15:00.091537 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1305 20:15:00.092089 ==
1306 20:15:00.094621 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 20:15:00.097968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 20:15:00.098386 ==
1309 20:15:00.101758 DQS Delay:
1310 20:15:00.102174 DQS0 = 0, DQS1 = 0
1311 20:15:00.106033 DQM Delay:
1312 20:15:00.106448 DQM0 = 82, DQM1 = 75
1313 20:15:00.106777 DQ Delay:
1314 20:15:00.107792 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1315 20:15:00.111218 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1316 20:15:00.114603 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1317 20:15:00.118578 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
1318 20:15:00.119005
1319 20:15:00.119465
1320 20:15:00.121496 ==
1321 20:15:00.121947 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 20:15:00.128257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 20:15:00.128784 ==
1324 20:15:00.129182
1325 20:15:00.129505
1326 20:15:00.130852 TX Vref Scan disable
1327 20:15:00.131310 == TX Byte 0 ==
1328 20:15:00.134550 Update DQ dly =588 (2 ,2, 12) DQ OEN =(1 ,7)
1329 20:15:00.140987 Update DQM dly =588 (2 ,2, 12) DQM OEN =(1 ,7)
1330 20:15:00.141588 == TX Byte 1 ==
1331 20:15:00.143935 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1332 20:15:00.150883 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1333 20:15:00.151457 ==
1334 20:15:00.154648 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 20:15:00.157260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 20:15:00.157789 ==
1337 20:15:00.171278 TX Vref=22, minBit 2, minWin=27, winSum=441
1338 20:15:00.174476 TX Vref=24, minBit 0, minWin=27, winSum=440
1339 20:15:00.178170 TX Vref=26, minBit 3, minWin=27, winSum=446
1340 20:15:00.181250 TX Vref=28, minBit 3, minWin=27, winSum=442
1341 20:15:00.184347 TX Vref=30, minBit 0, minWin=27, winSum=441
1342 20:15:00.191345 TX Vref=32, minBit 0, minWin=27, winSum=441
1343 20:15:00.194820 [TxChooseVref] Worse bit 3, Min win 27, Win sum 446, Final Vref 26
1344 20:15:00.195372
1345 20:15:00.197891 Final TX Range 1 Vref 26
1346 20:15:00.198414
1347 20:15:00.198919 ==
1348 20:15:00.201507 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 20:15:00.204876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 20:15:00.205454 ==
1351 20:15:00.208562
1352 20:15:00.208977
1353 20:15:00.209305 TX Vref Scan disable
1354 20:15:00.211598 == TX Byte 0 ==
1355 20:15:00.214953 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1356 20:15:00.221124 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1357 20:15:00.221543 == TX Byte 1 ==
1358 20:15:00.225369 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 20:15:00.228180 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 20:15:00.231778
1361 20:15:00.232195 [DATLAT]
1362 20:15:00.232545 Freq=800, CH0 RK1
1363 20:15:00.232861
1364 20:15:00.234656 DATLAT Default: 0xa
1365 20:15:00.235072 0, 0xFFFF, sum = 0
1366 20:15:00.238372 1, 0xFFFF, sum = 0
1367 20:15:00.238919 2, 0xFFFF, sum = 0
1368 20:15:00.242070 3, 0xFFFF, sum = 0
1369 20:15:00.242617 4, 0xFFFF, sum = 0
1370 20:15:00.244390 5, 0xFFFF, sum = 0
1371 20:15:00.248131 6, 0xFFFF, sum = 0
1372 20:15:00.248581 7, 0xFFFF, sum = 0
1373 20:15:00.251203 8, 0xFFFF, sum = 0
1374 20:15:00.251805 9, 0x0, sum = 1
1375 20:15:00.252179 10, 0x0, sum = 2
1376 20:15:00.254646 11, 0x0, sum = 3
1377 20:15:00.255069 12, 0x0, sum = 4
1378 20:15:00.258049 best_step = 10
1379 20:15:00.258485
1380 20:15:00.258966 ==
1381 20:15:00.261583 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 20:15:00.264432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 20:15:00.265033 ==
1384 20:15:00.268080 RX Vref Scan: 0
1385 20:15:00.268639
1386 20:15:00.268981 RX Vref 0 -> 0, step: 1
1387 20:15:00.269424
1388 20:15:00.270880 RX Delay -111 -> 252, step: 8
1389 20:15:00.277945 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1390 20:15:00.281722 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1391 20:15:00.284792 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1392 20:15:00.288129 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1393 20:15:00.291988 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1394 20:15:00.297762 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1395 20:15:00.301120 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1396 20:15:00.304676 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1397 20:15:00.307792 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1398 20:15:00.311646 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1399 20:15:00.318466 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1400 20:15:00.322156 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1401 20:15:00.324492 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1402 20:15:00.328147 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1403 20:15:00.334749 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1404 20:15:00.337693 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1405 20:15:00.338337 ==
1406 20:15:00.341278 Dram Type= 6, Freq= 0, CH_0, rank 1
1407 20:15:00.344329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 20:15:00.344937 ==
1409 20:15:00.347819 DQS Delay:
1410 20:15:00.348402 DQS0 = 0, DQS1 = 0
1411 20:15:00.348758 DQM Delay:
1412 20:15:00.351009 DQM0 = 86, DQM1 = 76
1413 20:15:00.351640 DQ Delay:
1414 20:15:00.354694 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1415 20:15:00.357953 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1416 20:15:00.361245 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1417 20:15:00.364334 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1418 20:15:00.364757
1419 20:15:00.365233
1420 20:15:00.374344 [DQSOSCAuto] RK1, (LSB)MR18= 0x38ff, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
1421 20:15:00.375025 CH0 RK1: MR19=605, MR18=38FF
1422 20:15:00.381171 CH0_RK1: MR19=0x605, MR18=0x38FF, DQSOSC=395, MR23=63, INC=94, DEC=63
1423 20:15:00.384090 [RxdqsGatingPostProcess] freq 800
1424 20:15:00.390741 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1425 20:15:00.394011 Pre-setting of DQS Precalculation
1426 20:15:00.397608 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1427 20:15:00.398192 ==
1428 20:15:00.401499 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 20:15:00.407457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 20:15:00.408013 ==
1431 20:15:00.410566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1432 20:15:00.417366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1433 20:15:00.426938 [CA 0] Center 36 (6~67) winsize 62
1434 20:15:00.429785 [CA 1] Center 36 (6~67) winsize 62
1435 20:15:00.433431 [CA 2] Center 34 (4~65) winsize 62
1436 20:15:00.436787 [CA 3] Center 34 (4~65) winsize 62
1437 20:15:00.439569 [CA 4] Center 34 (4~65) winsize 62
1438 20:15:00.443099 [CA 5] Center 34 (3~65) winsize 63
1439 20:15:00.443523
1440 20:15:00.446385 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1441 20:15:00.446832
1442 20:15:00.449828 [CATrainingPosCal] consider 1 rank data
1443 20:15:00.452714 u2DelayCellTimex100 = 270/100 ps
1444 20:15:00.456704 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1445 20:15:00.463116 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1446 20:15:00.466276 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 20:15:00.469304 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 20:15:00.473163 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 20:15:00.475628 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1450 20:15:00.476123
1451 20:15:00.478908 CA PerBit enable=1, Macro0, CA PI delay=34
1452 20:15:00.479334
1453 20:15:00.483150 [CBTSetCACLKResult] CA Dly = 34
1454 20:15:00.486205 CS Dly: 5 (0~36)
1455 20:15:00.486833 ==
1456 20:15:00.489688 Dram Type= 6, Freq= 0, CH_1, rank 1
1457 20:15:00.493276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 20:15:00.493976 ==
1459 20:15:00.497467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1460 20:15:00.504308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1461 20:15:00.512814 [CA 0] Center 36 (6~67) winsize 62
1462 20:15:00.516494 [CA 1] Center 37 (6~68) winsize 63
1463 20:15:00.520627 [CA 2] Center 34 (4~65) winsize 62
1464 20:15:00.524547 [CA 3] Center 34 (3~65) winsize 63
1465 20:15:00.527546 [CA 4] Center 34 (4~65) winsize 62
1466 20:15:00.531046 [CA 5] Center 34 (4~64) winsize 61
1467 20:15:00.531460
1468 20:15:00.534371 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1469 20:15:00.534786
1470 20:15:00.537400 [CATrainingPosCal] consider 2 rank data
1471 20:15:00.540508 u2DelayCellTimex100 = 270/100 ps
1472 20:15:00.543772 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 20:15:00.546977 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 20:15:00.550472 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 20:15:00.553629 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 20:15:00.557150 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 20:15:00.560617 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1478 20:15:00.563551
1479 20:15:00.567352 CA PerBit enable=1, Macro0, CA PI delay=34
1480 20:15:00.567803
1481 20:15:00.570056 [CBTSetCACLKResult] CA Dly = 34
1482 20:15:00.570477 CS Dly: 6 (0~38)
1483 20:15:00.570810
1484 20:15:00.573512 ----->DramcWriteLeveling(PI) begin...
1485 20:15:00.573937 ==
1486 20:15:00.577038 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 20:15:00.580031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1488 20:15:00.583585 ==
1489 20:15:00.584172 Write leveling (Byte 0): 25 => 25
1490 20:15:00.586522 Write leveling (Byte 1): 26 => 26
1491 20:15:00.590177 DramcWriteLeveling(PI) end<-----
1492 20:15:00.590596
1493 20:15:00.590928 ==
1494 20:15:00.593957 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 20:15:00.600356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 20:15:00.600779 ==
1497 20:15:00.603331 [Gating] SW mode calibration
1498 20:15:00.610144 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1499 20:15:00.613289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1500 20:15:00.619825 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1501 20:15:00.623315 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1502 20:15:00.626495 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 20:15:00.633046 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 20:15:00.636019 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 20:15:00.639461 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 20:15:00.646230 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 20:15:00.649914 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 20:15:00.653125 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 20:15:00.660725 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 20:15:00.662827 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 20:15:00.666284 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 20:15:00.673143 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 20:15:00.675766 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 20:15:00.679980 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 20:15:00.686054 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 20:15:00.689246 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 20:15:00.693209 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1518 20:15:00.699163 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1519 20:15:00.702759 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 20:15:00.705637 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 20:15:00.712210 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 20:15:00.715446 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 20:15:00.718720 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 20:15:00.725882 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 20:15:00.728610 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1526 20:15:00.731978 0 9 8 | B1->B0 | 2e2e 3232 | 1 0 | (1 1) (0 0)
1527 20:15:00.738314 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 20:15:00.742349 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 20:15:00.745010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 20:15:00.751921 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 20:15:00.755606 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 20:15:00.758325 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 20:15:00.764910 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1534 20:15:00.769043 0 10 8 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (0 0)
1535 20:15:00.771759 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 20:15:00.775243 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 20:15:00.781394 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 20:15:00.784983 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 20:15:00.788618 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 20:15:00.794735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 20:15:00.798121 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 20:15:00.801490 0 11 8 | B1->B0 | 3d3d 3b3b | 1 0 | (0 0) (0 0)
1543 20:15:00.808134 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 20:15:00.811352 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 20:15:00.814587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 20:15:00.821792 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 20:15:00.824471 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 20:15:00.827832 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 20:15:00.835364 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1550 20:15:00.837961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 20:15:00.841470 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 20:15:00.847768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 20:15:00.851814 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 20:15:00.854210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 20:15:00.860484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 20:15:00.864022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 20:15:00.867481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 20:15:00.873953 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 20:15:00.877207 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 20:15:00.881155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 20:15:00.887851 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 20:15:00.890508 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 20:15:00.894140 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 20:15:00.900478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 20:15:00.904181 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1566 20:15:00.907293 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 20:15:00.910406 Total UI for P1: 0, mck2ui 16
1568 20:15:00.913983 best dqsien dly found for B0: ( 0, 14, 4)
1569 20:15:00.916919 Total UI for P1: 0, mck2ui 16
1570 20:15:00.920499 best dqsien dly found for B1: ( 0, 14, 6)
1571 20:15:00.923608 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1572 20:15:00.927119 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1573 20:15:00.927196
1574 20:15:00.930340 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1575 20:15:00.936941 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1576 20:15:00.937039 [Gating] SW calibration Done
1577 20:15:00.937107 ==
1578 20:15:00.940139 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 20:15:00.946845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 20:15:00.946944 ==
1581 20:15:00.947012 RX Vref Scan: 0
1582 20:15:00.947106
1583 20:15:00.950020 RX Vref 0 -> 0, step: 1
1584 20:15:00.950104
1585 20:15:00.953366 RX Delay -130 -> 252, step: 16
1586 20:15:00.956608 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1587 20:15:00.959807 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1588 20:15:00.963474 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1589 20:15:00.969960 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1590 20:15:00.973198 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1591 20:15:00.976592 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1592 20:15:00.979908 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1593 20:15:00.983152 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1594 20:15:00.989908 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1595 20:15:00.993083 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1596 20:15:00.996323 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1597 20:15:00.999694 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1598 20:15:01.006673 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1599 20:15:01.010424 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1600 20:15:01.012695 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1601 20:15:01.016273 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1602 20:15:01.016373 ==
1603 20:15:01.019751 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 20:15:01.026942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 20:15:01.027056 ==
1606 20:15:01.027183 DQS Delay:
1607 20:15:01.027290 DQS0 = 0, DQS1 = 0
1608 20:15:01.030375 DQM Delay:
1609 20:15:01.030539 DQM0 = 89, DQM1 = 78
1610 20:15:01.032679 DQ Delay:
1611 20:15:01.036899 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1612 20:15:01.039857 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1613 20:15:01.042882 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1614 20:15:01.046119 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1615 20:15:01.046280
1616 20:15:01.046429
1617 20:15:01.046570 ==
1618 20:15:01.049333 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 20:15:01.052710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 20:15:01.052842 ==
1621 20:15:01.052952
1622 20:15:01.053097
1623 20:15:01.056399 TX Vref Scan disable
1624 20:15:01.056567 == TX Byte 0 ==
1625 20:15:01.062746 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1626 20:15:01.066334 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1627 20:15:01.066415 == TX Byte 1 ==
1628 20:15:01.073294 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1629 20:15:01.076269 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1630 20:15:01.076346 ==
1631 20:15:01.080291 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 20:15:01.082831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 20:15:01.082906 ==
1634 20:15:01.096621 TX Vref=22, minBit 0, minWin=27, winSum=441
1635 20:15:01.099805 TX Vref=24, minBit 8, minWin=27, winSum=448
1636 20:15:01.103448 TX Vref=26, minBit 0, minWin=27, winSum=445
1637 20:15:01.106399 TX Vref=28, minBit 10, minWin=27, winSum=448
1638 20:15:01.109751 TX Vref=30, minBit 10, minWin=27, winSum=447
1639 20:15:01.116815 TX Vref=32, minBit 0, minWin=27, winSum=446
1640 20:15:01.119553 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 24
1641 20:15:01.119661
1642 20:15:01.122899 Final TX Range 1 Vref 24
1643 20:15:01.122981
1644 20:15:01.123045 ==
1645 20:15:01.126750 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 20:15:01.129689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 20:15:01.133715 ==
1648 20:15:01.133815
1649 20:15:01.133881
1650 20:15:01.133942 TX Vref Scan disable
1651 20:15:01.137257 == TX Byte 0 ==
1652 20:15:01.140292 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1653 20:15:01.146994 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1654 20:15:01.147077 == TX Byte 1 ==
1655 20:15:01.149945 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1656 20:15:01.153411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1657 20:15:01.156743
1658 20:15:01.156855 [DATLAT]
1659 20:15:01.156953 Freq=800, CH1 RK0
1660 20:15:01.157053
1661 20:15:01.160200 DATLAT Default: 0xa
1662 20:15:01.160311 0, 0xFFFF, sum = 0
1663 20:15:01.163350 1, 0xFFFF, sum = 0
1664 20:15:01.163453 2, 0xFFFF, sum = 0
1665 20:15:01.166985 3, 0xFFFF, sum = 0
1666 20:15:01.167130 4, 0xFFFF, sum = 0
1667 20:15:01.170071 5, 0xFFFF, sum = 0
1668 20:15:01.173479 6, 0xFFFF, sum = 0
1669 20:15:01.173603 7, 0xFFFF, sum = 0
1670 20:15:01.177118 8, 0xFFFF, sum = 0
1671 20:15:01.177201 9, 0x0, sum = 1
1672 20:15:01.177268 10, 0x0, sum = 2
1673 20:15:01.180109 11, 0x0, sum = 3
1674 20:15:01.180192 12, 0x0, sum = 4
1675 20:15:01.183102 best_step = 10
1676 20:15:01.183183
1677 20:15:01.183247 ==
1678 20:15:01.186344 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 20:15:01.190029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 20:15:01.190137 ==
1681 20:15:01.193141 RX Vref Scan: 1
1682 20:15:01.193251
1683 20:15:01.196187 Set Vref Range= 32 -> 127
1684 20:15:01.196267
1685 20:15:01.196332 RX Vref 32 -> 127, step: 1
1686 20:15:01.196404
1687 20:15:01.199592 RX Delay -95 -> 252, step: 8
1688 20:15:01.199734
1689 20:15:01.202751 Set Vref, RX VrefLevel [Byte0]: 32
1690 20:15:01.206364 [Byte1]: 32
1691 20:15:01.209380
1692 20:15:01.209481 Set Vref, RX VrefLevel [Byte0]: 33
1693 20:15:01.212774 [Byte1]: 33
1694 20:15:01.216830
1695 20:15:01.216909 Set Vref, RX VrefLevel [Byte0]: 34
1696 20:15:01.220400 [Byte1]: 34
1697 20:15:01.224581
1698 20:15:01.224656 Set Vref, RX VrefLevel [Byte0]: 35
1699 20:15:01.227827 [Byte1]: 35
1700 20:15:01.232540
1701 20:15:01.232618 Set Vref, RX VrefLevel [Byte0]: 36
1702 20:15:01.235505 [Byte1]: 36
1703 20:15:01.240962
1704 20:15:01.241042 Set Vref, RX VrefLevel [Byte0]: 37
1705 20:15:01.243431 [Byte1]: 37
1706 20:15:01.247485
1707 20:15:01.247584 Set Vref, RX VrefLevel [Byte0]: 38
1708 20:15:01.251139 [Byte1]: 38
1709 20:15:01.255221
1710 20:15:01.255320 Set Vref, RX VrefLevel [Byte0]: 39
1711 20:15:01.258811 [Byte1]: 39
1712 20:15:01.262431
1713 20:15:01.262505 Set Vref, RX VrefLevel [Byte0]: 40
1714 20:15:01.266771 [Byte1]: 40
1715 20:15:01.270724
1716 20:15:01.270797 Set Vref, RX VrefLevel [Byte0]: 41
1717 20:15:01.273953 [Byte1]: 41
1718 20:15:01.278329
1719 20:15:01.278437 Set Vref, RX VrefLevel [Byte0]: 42
1720 20:15:01.284714 [Byte1]: 42
1721 20:15:01.284793
1722 20:15:01.287899 Set Vref, RX VrefLevel [Byte0]: 43
1723 20:15:01.290836 [Byte1]: 43
1724 20:15:01.290910
1725 20:15:01.294377 Set Vref, RX VrefLevel [Byte0]: 44
1726 20:15:01.298392 [Byte1]: 44
1727 20:15:01.298491
1728 20:15:01.301243 Set Vref, RX VrefLevel [Byte0]: 45
1729 20:15:01.304464 [Byte1]: 45
1730 20:15:01.308057
1731 20:15:01.308148 Set Vref, RX VrefLevel [Byte0]: 46
1732 20:15:01.311471 [Byte1]: 46
1733 20:15:01.315910
1734 20:15:01.316001 Set Vref, RX VrefLevel [Byte0]: 47
1735 20:15:01.319531 [Byte1]: 47
1736 20:15:01.323400
1737 20:15:01.323507 Set Vref, RX VrefLevel [Byte0]: 48
1738 20:15:01.326788 [Byte1]: 48
1739 20:15:01.331129
1740 20:15:01.331207 Set Vref, RX VrefLevel [Byte0]: 49
1741 20:15:01.334523 [Byte1]: 49
1742 20:15:01.338989
1743 20:15:01.339060 Set Vref, RX VrefLevel [Byte0]: 50
1744 20:15:01.342145 [Byte1]: 50
1745 20:15:01.346101
1746 20:15:01.346175 Set Vref, RX VrefLevel [Byte0]: 51
1747 20:15:01.349623 [Byte1]: 51
1748 20:15:01.354093
1749 20:15:01.354191 Set Vref, RX VrefLevel [Byte0]: 52
1750 20:15:01.357541 [Byte1]: 52
1751 20:15:01.361274
1752 20:15:01.361381 Set Vref, RX VrefLevel [Byte0]: 53
1753 20:15:01.364761 [Byte1]: 53
1754 20:15:01.369105
1755 20:15:01.369175 Set Vref, RX VrefLevel [Byte0]: 54
1756 20:15:01.372555 [Byte1]: 54
1757 20:15:01.376518
1758 20:15:01.376591 Set Vref, RX VrefLevel [Byte0]: 55
1759 20:15:01.383088 [Byte1]: 55
1760 20:15:01.383186
1761 20:15:01.386744 Set Vref, RX VrefLevel [Byte0]: 56
1762 20:15:01.390114 [Byte1]: 56
1763 20:15:01.390220
1764 20:15:01.392995 Set Vref, RX VrefLevel [Byte0]: 57
1765 20:15:01.396134 [Byte1]: 57
1766 20:15:01.399330
1767 20:15:01.399432 Set Vref, RX VrefLevel [Byte0]: 58
1768 20:15:01.402972 [Byte1]: 58
1769 20:15:01.406964
1770 20:15:01.407058 Set Vref, RX VrefLevel [Byte0]: 59
1771 20:15:01.410248 [Byte1]: 59
1772 20:15:01.414744
1773 20:15:01.414842 Set Vref, RX VrefLevel [Byte0]: 60
1774 20:15:01.418678 [Byte1]: 60
1775 20:15:01.422183
1776 20:15:01.422301 Set Vref, RX VrefLevel [Byte0]: 61
1777 20:15:01.425511 [Byte1]: 61
1778 20:15:01.429545
1779 20:15:01.429647 Set Vref, RX VrefLevel [Byte0]: 62
1780 20:15:01.433330 [Byte1]: 62
1781 20:15:01.437144
1782 20:15:01.437250 Set Vref, RX VrefLevel [Byte0]: 63
1783 20:15:01.440824 [Byte1]: 63
1784 20:15:01.444817
1785 20:15:01.445030 Set Vref, RX VrefLevel [Byte0]: 64
1786 20:15:01.448191 [Byte1]: 64
1787 20:15:01.452648
1788 20:15:01.452760 Set Vref, RX VrefLevel [Byte0]: 65
1789 20:15:01.456227 [Byte1]: 65
1790 20:15:01.460213
1791 20:15:01.460342 Set Vref, RX VrefLevel [Byte0]: 66
1792 20:15:01.463780 [Byte1]: 66
1793 20:15:01.467634
1794 20:15:01.467742 Set Vref, RX VrefLevel [Byte0]: 67
1795 20:15:01.470753 [Byte1]: 67
1796 20:15:01.475387
1797 20:15:01.475496 Set Vref, RX VrefLevel [Byte0]: 68
1798 20:15:01.478712 [Byte1]: 68
1799 20:15:01.482981
1800 20:15:01.483063 Set Vref, RX VrefLevel [Byte0]: 69
1801 20:15:01.486458 [Byte1]: 69
1802 20:15:01.490298
1803 20:15:01.490407 Set Vref, RX VrefLevel [Byte0]: 70
1804 20:15:01.493883 [Byte1]: 70
1805 20:15:01.498105
1806 20:15:01.498214 Set Vref, RX VrefLevel [Byte0]: 71
1807 20:15:01.502161 [Byte1]: 71
1808 20:15:01.505645
1809 20:15:01.505762 Set Vref, RX VrefLevel [Byte0]: 72
1810 20:15:01.509774 [Byte1]: 72
1811 20:15:01.513499
1812 20:15:01.513569 Set Vref, RX VrefLevel [Byte0]: 73
1813 20:15:01.516676 [Byte1]: 73
1814 20:15:01.520887
1815 20:15:01.520972 Set Vref, RX VrefLevel [Byte0]: 74
1816 20:15:01.524009 [Byte1]: 74
1817 20:15:01.528724
1818 20:15:01.528860 Set Vref, RX VrefLevel [Byte0]: 75
1819 20:15:01.531834 [Byte1]: 75
1820 20:15:01.536171
1821 20:15:01.536280 Final RX Vref Byte 0 = 57 to rank0
1822 20:15:01.539833 Final RX Vref Byte 1 = 64 to rank0
1823 20:15:01.542946 Final RX Vref Byte 0 = 57 to rank1
1824 20:15:01.546277 Final RX Vref Byte 1 = 64 to rank1==
1825 20:15:01.549289 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 20:15:01.556327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 20:15:01.556455 ==
1828 20:15:01.556550 DQS Delay:
1829 20:15:01.559561 DQS0 = 0, DQS1 = 0
1830 20:15:01.559661 DQM Delay:
1831 20:15:01.559778 DQM0 = 86, DQM1 = 80
1832 20:15:01.562359 DQ Delay:
1833 20:15:01.565776 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1834 20:15:01.568890 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1835 20:15:01.572606 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1836 20:15:01.575849 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1837 20:15:01.575924
1838 20:15:01.575988
1839 20:15:01.582831 [DQSOSCAuto] RK0, (LSB)MR18= 0x2815, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1840 20:15:01.585892 CH1 RK0: MR19=606, MR18=2815
1841 20:15:01.593526 CH1_RK0: MR19=0x606, MR18=0x2815, DQSOSC=399, MR23=63, INC=92, DEC=61
1842 20:15:01.593613
1843 20:15:01.595569 ----->DramcWriteLeveling(PI) begin...
1844 20:15:01.595702 ==
1845 20:15:01.599442 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 20:15:01.602535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 20:15:01.602642 ==
1848 20:15:01.605504 Write leveling (Byte 0): 26 => 26
1849 20:15:01.608643 Write leveling (Byte 1): 30 => 30
1850 20:15:01.611764 DramcWriteLeveling(PI) end<-----
1851 20:15:01.611859
1852 20:15:01.611923 ==
1853 20:15:01.615481 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 20:15:01.618701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 20:15:01.621843 ==
1856 20:15:01.621924 [Gating] SW mode calibration
1857 20:15:01.628856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 20:15:01.635586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 20:15:01.638483 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1860 20:15:01.645549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1861 20:15:01.648251 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 20:15:01.651926 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 20:15:01.658352 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 20:15:01.661780 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 20:15:01.665213 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 20:15:01.671452 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 20:15:01.675317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 20:15:01.678651 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 20:15:01.685009 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 20:15:01.688336 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 20:15:01.691373 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 20:15:01.698833 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 20:15:01.702561 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 20:15:01.705345 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 20:15:01.711617 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1876 20:15:01.714976 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1877 20:15:01.718326 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1878 20:15:01.724907 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 20:15:01.728298 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 20:15:01.731976 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 20:15:01.734369 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 20:15:01.741145 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 20:15:01.744509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 20:15:01.747957 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 20:15:01.754564 0 9 8 | B1->B0 | 2e2e 2828 | 1 0 | (1 1) (0 0)
1886 20:15:01.757842 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 20:15:01.760893 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 20:15:01.768250 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 20:15:01.771124 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 20:15:01.774568 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 20:15:01.781508 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 20:15:01.784402 0 10 4 | B1->B0 | 3131 3434 | 0 0 | (0 1) (0 0)
1893 20:15:01.787602 0 10 8 | B1->B0 | 2828 2f2f | 0 0 | (1 1) (1 1)
1894 20:15:01.794728 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 20:15:01.797367 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 20:15:01.801361 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 20:15:01.808049 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 20:15:01.811912 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 20:15:01.814423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 20:15:01.820889 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1901 20:15:01.823937 0 11 8 | B1->B0 | 4444 3333 | 0 1 | (0 0) (0 0)
1902 20:15:01.827389 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 20:15:01.834081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 20:15:01.837588 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 20:15:01.841041 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 20:15:01.847949 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 20:15:01.850837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 20:15:01.854565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 20:15:01.860979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1910 20:15:01.864705 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 20:15:01.867597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 20:15:01.874905 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 20:15:01.877880 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 20:15:01.881219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 20:15:01.887823 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 20:15:01.890998 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 20:15:01.894193 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 20:15:01.900841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 20:15:01.904320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 20:15:01.907846 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 20:15:01.914216 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 20:15:01.917280 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 20:15:01.920852 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 20:15:01.927580 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1925 20:15:01.930510 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 20:15:01.934044 Total UI for P1: 0, mck2ui 16
1927 20:15:01.937184 best dqsien dly found for B0: ( 0, 14, 4)
1928 20:15:01.940672 Total UI for P1: 0, mck2ui 16
1929 20:15:01.944391 best dqsien dly found for B1: ( 0, 14, 4)
1930 20:15:01.947104 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1931 20:15:01.950723 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1932 20:15:01.951144
1933 20:15:01.953884 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1934 20:15:01.957432 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 20:15:01.960197 [Gating] SW calibration Done
1936 20:15:01.960670 ==
1937 20:15:01.963995 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 20:15:01.967039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 20:15:01.967461 ==
1940 20:15:01.970874 RX Vref Scan: 0
1941 20:15:01.971289
1942 20:15:01.971620 RX Vref 0 -> 0, step: 1
1943 20:15:01.974023
1944 20:15:01.974439 RX Delay -130 -> 252, step: 16
1945 20:15:01.981085 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1946 20:15:01.983609 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1947 20:15:01.986969 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1948 20:15:01.990287 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1949 20:15:01.993427 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1950 20:15:02.000605 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1951 20:15:02.003328 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1952 20:15:02.006679 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1953 20:15:02.010487 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1954 20:15:02.013693 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1955 20:15:02.019946 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1956 20:15:02.022943 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1957 20:15:02.026618 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1958 20:15:02.029864 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1959 20:15:02.036657 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1960 20:15:02.039516 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1961 20:15:02.039994 ==
1962 20:15:02.043071 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 20:15:02.046481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 20:15:02.046926 ==
1965 20:15:02.049778 DQS Delay:
1966 20:15:02.050194 DQS0 = 0, DQS1 = 0
1967 20:15:02.050562 DQM Delay:
1968 20:15:02.053088 DQM0 = 86, DQM1 = 78
1969 20:15:02.053530 DQ Delay:
1970 20:15:02.056465 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1971 20:15:02.059296 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1972 20:15:02.062635 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1973 20:15:02.066606 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1974 20:15:02.067025
1975 20:15:02.067356
1976 20:15:02.067667 ==
1977 20:15:02.069604 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 20:15:02.075920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 20:15:02.076396 ==
1980 20:15:02.076887
1981 20:15:02.077214
1982 20:15:02.077518 TX Vref Scan disable
1983 20:15:02.080025 == TX Byte 0 ==
1984 20:15:02.082944 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1985 20:15:02.089984 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1986 20:15:02.090509 == TX Byte 1 ==
1987 20:15:02.093122 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1988 20:15:02.100096 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1989 20:15:02.100533 ==
1990 20:15:02.102923 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 20:15:02.106577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 20:15:02.107000 ==
1993 20:15:02.119490 TX Vref=22, minBit 1, minWin=27, winSum=440
1994 20:15:02.122693 TX Vref=24, minBit 9, minWin=26, winSum=445
1995 20:15:02.126307 TX Vref=26, minBit 9, minWin=26, winSum=444
1996 20:15:02.128957 TX Vref=28, minBit 0, minWin=28, winSum=452
1997 20:15:02.132713 TX Vref=30, minBit 8, minWin=27, winSum=452
1998 20:15:02.135871 TX Vref=32, minBit 0, minWin=28, winSum=451
1999 20:15:02.142291 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
2000 20:15:02.142724
2001 20:15:02.145298 Final TX Range 1 Vref 28
2002 20:15:02.145721
2003 20:15:02.146089 ==
2004 20:15:02.149348 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 20:15:02.152752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 20:15:02.153176 ==
2007 20:15:02.153509
2008 20:15:02.155451
2009 20:15:02.155910 TX Vref Scan disable
2010 20:15:02.159232 == TX Byte 0 ==
2011 20:15:02.163046 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2012 20:15:02.165883 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2013 20:15:02.169518 == TX Byte 1 ==
2014 20:15:02.172208 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2015 20:15:02.178777 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2016 20:15:02.179203
2017 20:15:02.179554 [DATLAT]
2018 20:15:02.179915 Freq=800, CH1 RK1
2019 20:15:02.180236
2020 20:15:02.182312 DATLAT Default: 0xa
2021 20:15:02.182725 0, 0xFFFF, sum = 0
2022 20:15:02.185918 1, 0xFFFF, sum = 0
2023 20:15:02.186339 2, 0xFFFF, sum = 0
2024 20:15:02.188998 3, 0xFFFF, sum = 0
2025 20:15:02.191968 4, 0xFFFF, sum = 0
2026 20:15:02.192390 5, 0xFFFF, sum = 0
2027 20:15:02.195723 6, 0xFFFF, sum = 0
2028 20:15:02.196153 7, 0xFFFF, sum = 0
2029 20:15:02.198773 8, 0xFFFF, sum = 0
2030 20:15:02.199226 9, 0x0, sum = 1
2031 20:15:02.199631 10, 0x0, sum = 2
2032 20:15:02.202738 11, 0x0, sum = 3
2033 20:15:02.203175 12, 0x0, sum = 4
2034 20:15:02.205218 best_step = 10
2035 20:15:02.205697
2036 20:15:02.206043 ==
2037 20:15:02.208614 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 20:15:02.211844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 20:15:02.212273 ==
2040 20:15:02.215025 RX Vref Scan: 0
2041 20:15:02.215654
2042 20:15:02.216272 RX Vref 0 -> 0, step: 1
2043 20:15:02.218735
2044 20:15:02.219173 RX Delay -95 -> 252, step: 8
2045 20:15:02.225711 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2046 20:15:02.230099 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2047 20:15:02.232612 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2048 20:15:02.235844 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2049 20:15:02.239217 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2050 20:15:02.245545 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2051 20:15:02.248849 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2052 20:15:02.251707 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2053 20:15:02.255593 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2054 20:15:02.259378 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2055 20:15:02.265449 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2056 20:15:02.268799 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2057 20:15:02.271645 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2058 20:15:02.274872 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2059 20:15:02.281730 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2060 20:15:02.285518 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2061 20:15:02.285601 ==
2062 20:15:02.288113 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 20:15:02.291479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 20:15:02.291590 ==
2065 20:15:02.294799 DQS Delay:
2066 20:15:02.294876 DQS0 = 0, DQS1 = 0
2067 20:15:02.294979 DQM Delay:
2068 20:15:02.298262 DQM0 = 87, DQM1 = 79
2069 20:15:02.298356 DQ Delay:
2070 20:15:02.301719 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2071 20:15:02.305095 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2072 20:15:02.308407 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2073 20:15:02.311149 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2074 20:15:02.311231
2075 20:15:02.311296
2076 20:15:02.321272 [DQSOSCAuto] RK1, (LSB)MR18= 0x1109, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2077 20:15:02.321356 CH1 RK1: MR19=606, MR18=1109
2078 20:15:02.327906 CH1_RK1: MR19=0x606, MR18=0x1109, DQSOSC=405, MR23=63, INC=90, DEC=60
2079 20:15:02.331070 [RxdqsGatingPostProcess] freq 800
2080 20:15:02.338227 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 20:15:02.341809 Pre-setting of DQS Precalculation
2082 20:15:02.344696 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 20:15:02.351392 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 20:15:02.361474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 20:15:02.361628
2086 20:15:02.361731
2087 20:15:02.364473 [Calibration Summary] 1600 Mbps
2088 20:15:02.364613 CH 0, Rank 0
2089 20:15:02.368231 SW Impedance : PASS
2090 20:15:02.368402 DUTY Scan : NO K
2091 20:15:02.371718 ZQ Calibration : PASS
2092 20:15:02.374862 Jitter Meter : NO K
2093 20:15:02.375092 CBT Training : PASS
2094 20:15:02.377940 Write leveling : PASS
2095 20:15:02.381138 RX DQS gating : PASS
2096 20:15:02.381394 RX DQ/DQS(RDDQC) : PASS
2097 20:15:02.384677 TX DQ/DQS : PASS
2098 20:15:02.384921 RX DATLAT : PASS
2099 20:15:02.388791 RX DQ/DQS(Engine): PASS
2100 20:15:02.391654 TX OE : NO K
2101 20:15:02.391997 All Pass.
2102 20:15:02.392367
2103 20:15:02.394933 CH 0, Rank 1
2104 20:15:02.395350 SW Impedance : PASS
2105 20:15:02.398385 DUTY Scan : NO K
2106 20:15:02.398855 ZQ Calibration : PASS
2107 20:15:02.401074 Jitter Meter : NO K
2108 20:15:02.404667 CBT Training : PASS
2109 20:15:02.405176 Write leveling : PASS
2110 20:15:02.407798 RX DQS gating : PASS
2111 20:15:02.411481 RX DQ/DQS(RDDQC) : PASS
2112 20:15:02.412009 TX DQ/DQS : PASS
2113 20:15:02.414096 RX DATLAT : PASS
2114 20:15:02.418145 RX DQ/DQS(Engine): PASS
2115 20:15:02.418596 TX OE : NO K
2116 20:15:02.421208 All Pass.
2117 20:15:02.421631
2118 20:15:02.422009 CH 1, Rank 0
2119 20:15:02.424379 SW Impedance : PASS
2120 20:15:02.424807 DUTY Scan : NO K
2121 20:15:02.427503 ZQ Calibration : PASS
2122 20:15:02.431175 Jitter Meter : NO K
2123 20:15:02.431596 CBT Training : PASS
2124 20:15:02.434784 Write leveling : PASS
2125 20:15:02.437748 RX DQS gating : PASS
2126 20:15:02.438053 RX DQ/DQS(RDDQC) : PASS
2127 20:15:02.440618 TX DQ/DQS : PASS
2128 20:15:02.444472 RX DATLAT : PASS
2129 20:15:02.444711 RX DQ/DQS(Engine): PASS
2130 20:15:02.447728 TX OE : NO K
2131 20:15:02.447932 All Pass.
2132 20:15:02.448096
2133 20:15:02.450422 CH 1, Rank 1
2134 20:15:02.450610 SW Impedance : PASS
2135 20:15:02.453519 DUTY Scan : NO K
2136 20:15:02.457107 ZQ Calibration : PASS
2137 20:15:02.457243 Jitter Meter : NO K
2138 20:15:02.460712 CBT Training : PASS
2139 20:15:02.460842 Write leveling : PASS
2140 20:15:02.464117 RX DQS gating : PASS
2141 20:15:02.466884 RX DQ/DQS(RDDQC) : PASS
2142 20:15:02.466988 TX DQ/DQS : PASS
2143 20:15:02.470287 RX DATLAT : PASS
2144 20:15:02.473661 RX DQ/DQS(Engine): PASS
2145 20:15:02.473768 TX OE : NO K
2146 20:15:02.476763 All Pass.
2147 20:15:02.476877
2148 20:15:02.476980 DramC Write-DBI off
2149 20:15:02.480530 PER_BANK_REFRESH: Hybrid Mode
2150 20:15:02.483590 TX_TRACKING: ON
2151 20:15:02.486733 [GetDramInforAfterCalByMRR] Vendor 6.
2152 20:15:02.489993 [GetDramInforAfterCalByMRR] Revision 606.
2153 20:15:02.494124 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 20:15:02.494200 MR0 0x3b3b
2155 20:15:02.494264 MR8 0x5151
2156 20:15:02.500813 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 20:15:02.500891
2158 20:15:02.500954 MR0 0x3b3b
2159 20:15:02.501014 MR8 0x5151
2160 20:15:02.503239 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 20:15:02.503322
2162 20:15:02.513749 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 20:15:02.516723 [FAST_K] Save calibration result to emmc
2164 20:15:02.520178 [FAST_K] Save calibration result to emmc
2165 20:15:02.523690 dram_init: config_dvfs: 1
2166 20:15:02.526349 dramc_set_vcore_voltage set vcore to 662500
2167 20:15:02.529694 Read voltage for 1200, 2
2168 20:15:02.529778 Vio18 = 0
2169 20:15:02.529845 Vcore = 662500
2170 20:15:02.533254 Vdram = 0
2171 20:15:02.533339 Vddq = 0
2172 20:15:02.533406 Vmddr = 0
2173 20:15:02.539913 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 20:15:02.542939 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 20:15:02.546791 MEM_TYPE=3, freq_sel=15
2176 20:15:02.549547 sv_algorithm_assistance_LP4_1600
2177 20:15:02.553052 ============ PULL DRAM RESETB DOWN ============
2178 20:15:02.559540 ========== PULL DRAM RESETB DOWN end =========
2179 20:15:02.563273 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 20:15:02.566318 ===================================
2181 20:15:02.569625 LPDDR4 DRAM CONFIGURATION
2182 20:15:02.573190 ===================================
2183 20:15:02.573295 EX_ROW_EN[0] = 0x0
2184 20:15:02.576014 EX_ROW_EN[1] = 0x0
2185 20:15:02.576123 LP4Y_EN = 0x0
2186 20:15:02.579335 WORK_FSP = 0x0
2187 20:15:02.579500 WL = 0x4
2188 20:15:02.583139 RL = 0x4
2189 20:15:02.583312 BL = 0x2
2190 20:15:02.586274 RPST = 0x0
2191 20:15:02.589928 RD_PRE = 0x0
2192 20:15:02.590091 WR_PRE = 0x1
2193 20:15:02.592764 WR_PST = 0x0
2194 20:15:02.592924 DBI_WR = 0x0
2195 20:15:02.595944 DBI_RD = 0x0
2196 20:15:02.596104 OTF = 0x1
2197 20:15:02.599099 ===================================
2198 20:15:02.603208 ===================================
2199 20:15:02.606613 ANA top config
2200 20:15:02.606829 ===================================
2201 20:15:02.609139 DLL_ASYNC_EN = 0
2202 20:15:02.612716 ALL_SLAVE_EN = 0
2203 20:15:02.615635 NEW_RANK_MODE = 1
2204 20:15:02.619374 DLL_IDLE_MODE = 1
2205 20:15:02.619635 LP45_APHY_COMB_EN = 1
2206 20:15:02.622379 TX_ODT_DIS = 1
2207 20:15:02.626107 NEW_8X_MODE = 1
2208 20:15:02.629749 ===================================
2209 20:15:02.633129 ===================================
2210 20:15:02.636166 data_rate = 2400
2211 20:15:02.639650 CKR = 1
2212 20:15:02.640142 DQ_P2S_RATIO = 8
2213 20:15:02.643199 ===================================
2214 20:15:02.646187 CA_P2S_RATIO = 8
2215 20:15:02.649479 DQ_CA_OPEN = 0
2216 20:15:02.653183 DQ_SEMI_OPEN = 0
2217 20:15:02.656642 CA_SEMI_OPEN = 0
2218 20:15:02.659386 CA_FULL_RATE = 0
2219 20:15:02.659906 DQ_CKDIV4_EN = 0
2220 20:15:02.662563 CA_CKDIV4_EN = 0
2221 20:15:02.665680 CA_PREDIV_EN = 0
2222 20:15:02.669273 PH8_DLY = 17
2223 20:15:02.672351 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 20:15:02.675959 DQ_AAMCK_DIV = 4
2225 20:15:02.679124 CA_AAMCK_DIV = 4
2226 20:15:02.679575 CA_ADMCK_DIV = 4
2227 20:15:02.682573 DQ_TRACK_CA_EN = 0
2228 20:15:02.685495 CA_PICK = 1200
2229 20:15:02.689324 CA_MCKIO = 1200
2230 20:15:02.692169 MCKIO_SEMI = 0
2231 20:15:02.696545 PLL_FREQ = 2366
2232 20:15:02.699222 DQ_UI_PI_RATIO = 32
2233 20:15:02.699774 CA_UI_PI_RATIO = 0
2234 20:15:02.702401 ===================================
2235 20:15:02.705937 ===================================
2236 20:15:02.709183 memory_type:LPDDR4
2237 20:15:02.712296 GP_NUM : 10
2238 20:15:02.712781 SRAM_EN : 1
2239 20:15:02.715504 MD32_EN : 0
2240 20:15:02.718979 ===================================
2241 20:15:02.722584 [ANA_INIT] >>>>>>>>>>>>>>
2242 20:15:02.725982 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 20:15:02.728635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 20:15:02.732130 ===================================
2245 20:15:02.732722 data_rate = 2400,PCW = 0X5b00
2246 20:15:02.737003 ===================================
2247 20:15:02.739303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 20:15:02.745612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 20:15:02.752027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 20:15:02.755287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 20:15:02.758913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 20:15:02.762829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 20:15:02.764954 [ANA_INIT] flow start
2254 20:15:02.768579 [ANA_INIT] PLL >>>>>>>>
2255 20:15:02.769003 [ANA_INIT] PLL <<<<<<<<
2256 20:15:02.771924 [ANA_INIT] MIDPI >>>>>>>>
2257 20:15:02.775157 [ANA_INIT] MIDPI <<<<<<<<
2258 20:15:02.775578 [ANA_INIT] DLL >>>>>>>>
2259 20:15:02.778361 [ANA_INIT] DLL <<<<<<<<
2260 20:15:02.782525 [ANA_INIT] flow end
2261 20:15:02.785088 ============ LP4 DIFF to SE enter ============
2262 20:15:02.788469 ============ LP4 DIFF to SE exit ============
2263 20:15:02.791326 [ANA_INIT] <<<<<<<<<<<<<
2264 20:15:02.795890 [Flow] Enable top DCM control >>>>>
2265 20:15:02.798366 [Flow] Enable top DCM control <<<<<
2266 20:15:02.801853 Enable DLL master slave shuffle
2267 20:15:02.804778 ==============================================================
2268 20:15:02.808218 Gating Mode config
2269 20:15:02.815058 ==============================================================
2270 20:15:02.815552 Config description:
2271 20:15:02.824511 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 20:15:02.831355 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 20:15:02.837838 SELPH_MODE 0: By rank 1: By Phase
2274 20:15:02.841346 ==============================================================
2275 20:15:02.844988 GAT_TRACK_EN = 1
2276 20:15:02.848206 RX_GATING_MODE = 2
2277 20:15:02.851122 RX_GATING_TRACK_MODE = 2
2278 20:15:02.854953 SELPH_MODE = 1
2279 20:15:02.858590 PICG_EARLY_EN = 1
2280 20:15:02.861454 VALID_LAT_VALUE = 1
2281 20:15:02.864632 ==============================================================
2282 20:15:02.867722 Enter into Gating configuration >>>>
2283 20:15:02.871203 Exit from Gating configuration <<<<
2284 20:15:02.874355 Enter into DVFS_PRE_config >>>>>
2285 20:15:02.888388 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 20:15:02.891107 Exit from DVFS_PRE_config <<<<<
2287 20:15:02.891731 Enter into PICG configuration >>>>
2288 20:15:02.894334 Exit from PICG configuration <<<<
2289 20:15:02.898357 [RX_INPUT] configuration >>>>>
2290 20:15:02.901056 [RX_INPUT] configuration <<<<<
2291 20:15:02.907718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 20:15:02.910822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 20:15:02.917582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 20:15:02.924533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 20:15:02.930787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 20:15:02.937580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 20:15:02.940720 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 20:15:02.943759 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 20:15:02.947123 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 20:15:02.953867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 20:15:02.957022 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 20:15:02.960959 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 20:15:02.963636 ===================================
2304 20:15:02.967844 LPDDR4 DRAM CONFIGURATION
2305 20:15:02.970879 ===================================
2306 20:15:02.974031 EX_ROW_EN[0] = 0x0
2307 20:15:02.974450 EX_ROW_EN[1] = 0x0
2308 20:15:02.976630 LP4Y_EN = 0x0
2309 20:15:02.977048 WORK_FSP = 0x0
2310 20:15:02.980334 WL = 0x4
2311 20:15:02.980750 RL = 0x4
2312 20:15:02.983426 BL = 0x2
2313 20:15:02.983889 RPST = 0x0
2314 20:15:02.987115 RD_PRE = 0x0
2315 20:15:02.987534 WR_PRE = 0x1
2316 20:15:02.990244 WR_PST = 0x0
2317 20:15:02.990663 DBI_WR = 0x0
2318 20:15:02.993567 DBI_RD = 0x0
2319 20:15:02.993987 OTF = 0x1
2320 20:15:02.997445 ===================================
2321 20:15:03.003383 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 20:15:03.006679 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 20:15:03.010217 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 20:15:03.013612 ===================================
2325 20:15:03.017113 LPDDR4 DRAM CONFIGURATION
2326 20:15:03.020562 ===================================
2327 20:15:03.023745 EX_ROW_EN[0] = 0x10
2328 20:15:03.024169 EX_ROW_EN[1] = 0x0
2329 20:15:03.026533 LP4Y_EN = 0x0
2330 20:15:03.026950 WORK_FSP = 0x0
2331 20:15:03.029638 WL = 0x4
2332 20:15:03.030056 RL = 0x4
2333 20:15:03.033075 BL = 0x2
2334 20:15:03.033490 RPST = 0x0
2335 20:15:03.036556 RD_PRE = 0x0
2336 20:15:03.036975 WR_PRE = 0x1
2337 20:15:03.040216 WR_PST = 0x0
2338 20:15:03.040649 DBI_WR = 0x0
2339 20:15:03.043908 DBI_RD = 0x0
2340 20:15:03.044321 OTF = 0x1
2341 20:15:03.046320 ===================================
2342 20:15:03.053298 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 20:15:03.053798 ==
2344 20:15:03.056383 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 20:15:03.063025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 20:15:03.063445 ==
2347 20:15:03.063843 [Duty_Offset_Calibration]
2348 20:15:03.066351 B0:1 B1:-1 CA:0
2349 20:15:03.066760
2350 20:15:03.069360 [DutyScan_Calibration_Flow] k_type=0
2351 20:15:03.078807
2352 20:15:03.079288 ==CLK 0==
2353 20:15:03.081906 Final CLK duty delay cell = 0
2354 20:15:03.084953 [0] MAX Duty = 5125%(X100), DQS PI = 24
2355 20:15:03.088297 [0] MIN Duty = 4907%(X100), DQS PI = 8
2356 20:15:03.088857 [0] AVG Duty = 5016%(X100)
2357 20:15:03.091638
2358 20:15:03.095075 CH0 CLK Duty spec in!! Max-Min= 218%
2359 20:15:03.098391 [DutyScan_Calibration_Flow] ====Done====
2360 20:15:03.098980
2361 20:15:03.101723 [DutyScan_Calibration_Flow] k_type=1
2362 20:15:03.116096
2363 20:15:03.116533 ==DQS 0 ==
2364 20:15:03.119320 Final DQS duty delay cell = -4
2365 20:15:03.122688 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2366 20:15:03.126399 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2367 20:15:03.128956 [-4] AVG Duty = 4968%(X100)
2368 20:15:03.129197
2369 20:15:03.129493 ==DQS 1 ==
2370 20:15:03.132610 Final DQS duty delay cell = -4
2371 20:15:03.135861 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2372 20:15:03.139187 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2373 20:15:03.142224 [-4] AVG Duty = 4938%(X100)
2374 20:15:03.142319
2375 20:15:03.146151 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2376 20:15:03.146257
2377 20:15:03.149369 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2378 20:15:03.152108 [DutyScan_Calibration_Flow] ====Done====
2379 20:15:03.152188
2380 20:15:03.155284 [DutyScan_Calibration_Flow] k_type=3
2381 20:15:03.173730
2382 20:15:03.173813 ==DQM 0 ==
2383 20:15:03.177526 Final DQM duty delay cell = 0
2384 20:15:03.180690 [0] MAX Duty = 5062%(X100), DQS PI = 18
2385 20:15:03.183653 [0] MIN Duty = 4875%(X100), DQS PI = 8
2386 20:15:03.186967 [0] AVG Duty = 4968%(X100)
2387 20:15:03.187041
2388 20:15:03.187105 ==DQM 1 ==
2389 20:15:03.190391 Final DQM duty delay cell = 4
2390 20:15:03.193336 [4] MAX Duty = 5187%(X100), DQS PI = 14
2391 20:15:03.196965 [4] MIN Duty = 5000%(X100), DQS PI = 24
2392 20:15:03.199971 [4] AVG Duty = 5093%(X100)
2393 20:15:03.200045
2394 20:15:03.203683 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2395 20:15:03.203782
2396 20:15:03.206602 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2397 20:15:03.210085 [DutyScan_Calibration_Flow] ====Done====
2398 20:15:03.210183
2399 20:15:03.213589 [DutyScan_Calibration_Flow] k_type=2
2400 20:15:03.228593
2401 20:15:03.228668 ==DQ 0 ==
2402 20:15:03.232271 Final DQ duty delay cell = -4
2403 20:15:03.235540 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2404 20:15:03.238513 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2405 20:15:03.242061 [-4] AVG Duty = 4969%(X100)
2406 20:15:03.242133
2407 20:15:03.242193 ==DQ 1 ==
2408 20:15:03.246255 Final DQ duty delay cell = -4
2409 20:15:03.248677 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2410 20:15:03.251938 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2411 20:15:03.255623 [-4] AVG Duty = 4922%(X100)
2412 20:15:03.255744
2413 20:15:03.258999 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2414 20:15:03.259070
2415 20:15:03.262293 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2416 20:15:03.265654 [DutyScan_Calibration_Flow] ====Done====
2417 20:15:03.265726 ==
2418 20:15:03.268469 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 20:15:03.272233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 20:15:03.272312 ==
2421 20:15:03.275242 [Duty_Offset_Calibration]
2422 20:15:03.275339 B0:-1 B1:1 CA:1
2423 20:15:03.275427
2424 20:15:03.278325 [DutyScan_Calibration_Flow] k_type=0
2425 20:15:03.289216
2426 20:15:03.289310 ==CLK 0==
2427 20:15:03.293560 Final CLK duty delay cell = 0
2428 20:15:03.296214 [0] MAX Duty = 5156%(X100), DQS PI = 22
2429 20:15:03.299963 [0] MIN Duty = 4969%(X100), DQS PI = 60
2430 20:15:03.300038 [0] AVG Duty = 5062%(X100)
2431 20:15:03.303034
2432 20:15:03.305950 CH1 CLK Duty spec in!! Max-Min= 187%
2433 20:15:03.309308 [DutyScan_Calibration_Flow] ====Done====
2434 20:15:03.309392
2435 20:15:03.312516 [DutyScan_Calibration_Flow] k_type=1
2436 20:15:03.328815
2437 20:15:03.328921 ==DQS 0 ==
2438 20:15:03.331897 Final DQS duty delay cell = 0
2439 20:15:03.335079 [0] MAX Duty = 5125%(X100), DQS PI = 18
2440 20:15:03.338524 [0] MIN Duty = 4875%(X100), DQS PI = 6
2441 20:15:03.341659 [0] AVG Duty = 5000%(X100)
2442 20:15:03.341734
2443 20:15:03.341795 ==DQS 1 ==
2444 20:15:03.345457 Final DQS duty delay cell = 0
2445 20:15:03.348769 [0] MAX Duty = 5094%(X100), DQS PI = 12
2446 20:15:03.351395 [0] MIN Duty = 4969%(X100), DQS PI = 58
2447 20:15:03.355184 [0] AVG Duty = 5031%(X100)
2448 20:15:03.355271
2449 20:15:03.358039 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2450 20:15:03.358112
2451 20:15:03.361753 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2452 20:15:03.364891 [DutyScan_Calibration_Flow] ====Done====
2453 20:15:03.364972
2454 20:15:03.368777 [DutyScan_Calibration_Flow] k_type=3
2455 20:15:03.384508
2456 20:15:03.384589 ==DQM 0 ==
2457 20:15:03.388177 Final DQM duty delay cell = -4
2458 20:15:03.390830 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2459 20:15:03.394903 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2460 20:15:03.397542 [-4] AVG Duty = 4953%(X100)
2461 20:15:03.397668
2462 20:15:03.397733 ==DQM 1 ==
2463 20:15:03.400594 Final DQM duty delay cell = 0
2464 20:15:03.403991 [0] MAX Duty = 5156%(X100), DQS PI = 10
2465 20:15:03.407105 [0] MIN Duty = 4969%(X100), DQS PI = 28
2466 20:15:03.410652 [0] AVG Duty = 5062%(X100)
2467 20:15:03.410733
2468 20:15:03.414300 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2469 20:15:03.414382
2470 20:15:03.417211 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2471 20:15:03.420559 [DutyScan_Calibration_Flow] ====Done====
2472 20:15:03.420639
2473 20:15:03.424227 [DutyScan_Calibration_Flow] k_type=2
2474 20:15:03.441498
2475 20:15:03.441578 ==DQ 0 ==
2476 20:15:03.444421 Final DQ duty delay cell = 0
2477 20:15:03.447558 [0] MAX Duty = 5156%(X100), DQS PI = 28
2478 20:15:03.451108 [0] MIN Duty = 4907%(X100), DQS PI = 8
2479 20:15:03.451184 [0] AVG Duty = 5031%(X100)
2480 20:15:03.451248
2481 20:15:03.454325 ==DQ 1 ==
2482 20:15:03.457482 Final DQ duty delay cell = 0
2483 20:15:03.460845 [0] MAX Duty = 5124%(X100), DQS PI = 10
2484 20:15:03.464230 [0] MIN Duty = 4969%(X100), DQS PI = 60
2485 20:15:03.464304 [0] AVG Duty = 5046%(X100)
2486 20:15:03.464367
2487 20:15:03.467667 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2488 20:15:03.470925
2489 20:15:03.474541 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2490 20:15:03.477410 [DutyScan_Calibration_Flow] ====Done====
2491 20:15:03.480814 nWR fixed to 30
2492 20:15:03.480893 [ModeRegInit_LP4] CH0 RK0
2493 20:15:03.483988 [ModeRegInit_LP4] CH0 RK1
2494 20:15:03.487056 [ModeRegInit_LP4] CH1 RK0
2495 20:15:03.491222 [ModeRegInit_LP4] CH1 RK1
2496 20:15:03.491301 match AC timing 7
2497 20:15:03.497053 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 20:15:03.500490 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 20:15:03.504426 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 20:15:03.510272 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 20:15:03.514248 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 20:15:03.514326 ==
2503 20:15:03.517391 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 20:15:03.520219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 20:15:03.520300 ==
2506 20:15:03.527369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 20:15:03.533959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2508 20:15:03.541596 [CA 0] Center 39 (9~70) winsize 62
2509 20:15:03.545613 [CA 1] Center 39 (9~70) winsize 62
2510 20:15:03.548106 [CA 2] Center 35 (5~66) winsize 62
2511 20:15:03.550949 [CA 3] Center 35 (5~66) winsize 62
2512 20:15:03.554997 [CA 4] Center 34 (4~64) winsize 61
2513 20:15:03.558137 [CA 5] Center 33 (4~63) winsize 60
2514 20:15:03.558235
2515 20:15:03.561415 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 20:15:03.561513
2517 20:15:03.564246 [CATrainingPosCal] consider 1 rank data
2518 20:15:03.568405 u2DelayCellTimex100 = 270/100 ps
2519 20:15:03.571589 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2520 20:15:03.574167 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2521 20:15:03.581495 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 20:15:03.584847 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2523 20:15:03.587726 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2524 20:15:03.590799 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2525 20:15:03.591230
2526 20:15:03.594443 CA PerBit enable=1, Macro0, CA PI delay=33
2527 20:15:03.594886
2528 20:15:03.597528 [CBTSetCACLKResult] CA Dly = 33
2529 20:15:03.601734 CS Dly: 8 (0~39)
2530 20:15:03.602220 ==
2531 20:15:03.605202 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 20:15:03.607772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 20:15:03.608218 ==
2534 20:15:03.613797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 20:15:03.617087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2536 20:15:03.627068 [CA 0] Center 39 (9~70) winsize 62
2537 20:15:03.631422 [CA 1] Center 39 (9~70) winsize 62
2538 20:15:03.633963 [CA 2] Center 35 (5~66) winsize 62
2539 20:15:03.637170 [CA 3] Center 34 (4~65) winsize 62
2540 20:15:03.640675 [CA 4] Center 33 (3~64) winsize 62
2541 20:15:03.643721 [CA 5] Center 33 (3~63) winsize 61
2542 20:15:03.644077
2543 20:15:03.646834 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 20:15:03.647135
2545 20:15:03.650378 [CATrainingPosCal] consider 2 rank data
2546 20:15:03.653833 u2DelayCellTimex100 = 270/100 ps
2547 20:15:03.657117 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2548 20:15:03.663445 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2549 20:15:03.666801 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 20:15:03.669785 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2551 20:15:03.673497 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2552 20:15:03.676811 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2553 20:15:03.677111
2554 20:15:03.679656 CA PerBit enable=1, Macro0, CA PI delay=33
2555 20:15:03.679979
2556 20:15:03.683345 [CBTSetCACLKResult] CA Dly = 33
2557 20:15:03.686937 CS Dly: 9 (0~41)
2558 20:15:03.687291
2559 20:15:03.689899 ----->DramcWriteLeveling(PI) begin...
2560 20:15:03.690288 ==
2561 20:15:03.693359 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 20:15:03.696819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 20:15:03.697255 ==
2564 20:15:03.700226 Write leveling (Byte 0): 31 => 31
2565 20:15:03.703740 Write leveling (Byte 1): 28 => 28
2566 20:15:03.706478 DramcWriteLeveling(PI) end<-----
2567 20:15:03.706903
2568 20:15:03.707357 ==
2569 20:15:03.710008 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 20:15:03.712951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 20:15:03.713498 ==
2572 20:15:03.716304 [Gating] SW mode calibration
2573 20:15:03.722462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 20:15:03.729616 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 20:15:03.733391 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2576 20:15:03.736249 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2577 20:15:03.742225 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2578 20:15:03.745707 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 20:15:03.749685 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 20:15:03.756252 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 20:15:03.759043 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 20:15:03.762432 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
2583 20:15:03.768729 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2584 20:15:03.772699 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2585 20:15:03.775703 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 20:15:03.782339 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 20:15:03.785680 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 20:15:03.789031 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 20:15:03.795228 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 20:15:03.798836 1 0 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2591 20:15:03.802153 1 1 0 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2592 20:15:03.809085 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2593 20:15:03.812382 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 20:15:03.815646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 20:15:03.821656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 20:15:03.824743 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 20:15:03.828083 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 20:15:03.834402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 20:15:03.837783 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2600 20:15:03.841240 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 20:15:03.847718 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 20:15:03.851325 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 20:15:03.854344 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 20:15:03.860676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 20:15:03.864107 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 20:15:03.867896 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 20:15:03.874375 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 20:15:03.877720 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 20:15:03.880627 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 20:15:03.887087 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 20:15:03.890273 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 20:15:03.897417 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 20:15:03.900278 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2614 20:15:03.903484 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 20:15:03.907757 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2616 20:15:03.910584 Total UI for P1: 0, mck2ui 16
2617 20:15:03.914323 best dqsien dly found for B0: ( 1, 3, 26)
2618 20:15:03.920577 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 20:15:03.923872 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 20:15:03.926842 Total UI for P1: 0, mck2ui 16
2621 20:15:03.930309 best dqsien dly found for B1: ( 1, 4, 2)
2622 20:15:03.934062 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2623 20:15:03.937159 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2624 20:15:03.937581
2625 20:15:03.940012 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2626 20:15:03.947119 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2627 20:15:03.947539 [Gating] SW calibration Done
2628 20:15:03.947928 ==
2629 20:15:03.950395 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 20:15:03.957093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 20:15:03.957528 ==
2632 20:15:03.957926 RX Vref Scan: 0
2633 20:15:03.958249
2634 20:15:03.959988 RX Vref 0 -> 0, step: 1
2635 20:15:03.960410
2636 20:15:03.963364 RX Delay -40 -> 252, step: 8
2637 20:15:03.967077 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2638 20:15:03.970094 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2639 20:15:03.973635 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2640 20:15:03.976769 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2641 20:15:03.983430 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2642 20:15:03.986912 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2643 20:15:03.989584 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2644 20:15:03.993246 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2645 20:15:04.000208 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2646 20:15:04.003081 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2647 20:15:04.006428 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2648 20:15:04.009752 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2649 20:15:04.012938 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2650 20:15:04.019695 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2651 20:15:04.022718 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2652 20:15:04.026565 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2653 20:15:04.026986 ==
2654 20:15:04.029599 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 20:15:04.032653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 20:15:04.033078 ==
2657 20:15:04.036743 DQS Delay:
2658 20:15:04.037184 DQS0 = 0, DQS1 = 0
2659 20:15:04.039411 DQM Delay:
2660 20:15:04.039971 DQM0 = 119, DQM1 = 107
2661 20:15:04.040313 DQ Delay:
2662 20:15:04.046229 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2663 20:15:04.049158 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2664 20:15:04.053245 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2665 20:15:04.055891 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2666 20:15:04.056313
2667 20:15:04.056647
2668 20:15:04.056958 ==
2669 20:15:04.059447 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 20:15:04.063435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 20:15:04.063914 ==
2672 20:15:04.064272
2673 20:15:04.064599
2674 20:15:04.065643 TX Vref Scan disable
2675 20:15:04.069240 == TX Byte 0 ==
2676 20:15:04.072673 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2677 20:15:04.075783 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2678 20:15:04.079334 == TX Byte 1 ==
2679 20:15:04.082329 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2680 20:15:04.086116 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2681 20:15:04.086534 ==
2682 20:15:04.088863 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 20:15:04.095408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 20:15:04.095879 ==
2685 20:15:04.106211 TX Vref=22, minBit 1, minWin=25, winSum=417
2686 20:15:04.109565 TX Vref=24, minBit 4, minWin=25, winSum=421
2687 20:15:04.113527 TX Vref=26, minBit 4, minWin=26, winSum=428
2688 20:15:04.116146 TX Vref=28, minBit 5, minWin=26, winSum=430
2689 20:15:04.119173 TX Vref=30, minBit 5, minWin=26, winSum=427
2690 20:15:04.125705 TX Vref=32, minBit 5, minWin=26, winSum=429
2691 20:15:04.129608 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2692 20:15:04.130031
2693 20:15:04.132322 Final TX Range 1 Vref 28
2694 20:15:04.132743
2695 20:15:04.133074 ==
2696 20:15:04.136720 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 20:15:04.139473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 20:15:04.142224 ==
2699 20:15:04.142642
2700 20:15:04.142973
2701 20:15:04.143280 TX Vref Scan disable
2702 20:15:04.145832 == TX Byte 0 ==
2703 20:15:04.149451 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2704 20:15:04.155571 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2705 20:15:04.156026 == TX Byte 1 ==
2706 20:15:04.158756 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2707 20:15:04.165354 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2708 20:15:04.165779
2709 20:15:04.166114 [DATLAT]
2710 20:15:04.166478 Freq=1200, CH0 RK0
2711 20:15:04.166780
2712 20:15:04.169143 DATLAT Default: 0xd
2713 20:15:04.169561 0, 0xFFFF, sum = 0
2714 20:15:04.172703 1, 0xFFFF, sum = 0
2715 20:15:04.175432 2, 0xFFFF, sum = 0
2716 20:15:04.175906 3, 0xFFFF, sum = 0
2717 20:15:04.178777 4, 0xFFFF, sum = 0
2718 20:15:04.179204 5, 0xFFFF, sum = 0
2719 20:15:04.182235 6, 0xFFFF, sum = 0
2720 20:15:04.182663 7, 0xFFFF, sum = 0
2721 20:15:04.185672 8, 0xFFFF, sum = 0
2722 20:15:04.186102 9, 0xFFFF, sum = 0
2723 20:15:04.189229 10, 0xFFFF, sum = 0
2724 20:15:04.189820 11, 0xFFFF, sum = 0
2725 20:15:04.192741 12, 0x0, sum = 1
2726 20:15:04.193166 13, 0x0, sum = 2
2727 20:15:04.195624 14, 0x0, sum = 3
2728 20:15:04.196216 15, 0x0, sum = 4
2729 20:15:04.199319 best_step = 13
2730 20:15:04.199866
2731 20:15:04.200212 ==
2732 20:15:04.202690 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 20:15:04.205959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 20:15:04.206493 ==
2735 20:15:04.206837 RX Vref Scan: 1
2736 20:15:04.209237
2737 20:15:04.209714 Set Vref Range= 32 -> 127
2738 20:15:04.210062
2739 20:15:04.211902 RX Vref 32 -> 127, step: 1
2740 20:15:04.212386
2741 20:15:04.215235 RX Delay -21 -> 252, step: 4
2742 20:15:04.215663
2743 20:15:04.218514 Set Vref, RX VrefLevel [Byte0]: 32
2744 20:15:04.222479 [Byte1]: 32
2745 20:15:04.222985
2746 20:15:04.225462 Set Vref, RX VrefLevel [Byte0]: 33
2747 20:15:04.229421 [Byte1]: 33
2748 20:15:04.232791
2749 20:15:04.233213 Set Vref, RX VrefLevel [Byte0]: 34
2750 20:15:04.235986 [Byte1]: 34
2751 20:15:04.240569
2752 20:15:04.241072 Set Vref, RX VrefLevel [Byte0]: 35
2753 20:15:04.243520 [Byte1]: 35
2754 20:15:04.248361
2755 20:15:04.248836 Set Vref, RX VrefLevel [Byte0]: 36
2756 20:15:04.254567 [Byte1]: 36
2757 20:15:04.255046
2758 20:15:04.258069 Set Vref, RX VrefLevel [Byte0]: 37
2759 20:15:04.260846 [Byte1]: 37
2760 20:15:04.261331
2761 20:15:04.264640 Set Vref, RX VrefLevel [Byte0]: 38
2762 20:15:04.267864 [Byte1]: 38
2763 20:15:04.271619
2764 20:15:04.272117 Set Vref, RX VrefLevel [Byte0]: 39
2765 20:15:04.275082 [Byte1]: 39
2766 20:15:04.279996
2767 20:15:04.280523 Set Vref, RX VrefLevel [Byte0]: 40
2768 20:15:04.283327 [Byte1]: 40
2769 20:15:04.288129
2770 20:15:04.288603 Set Vref, RX VrefLevel [Byte0]: 41
2771 20:15:04.291167 [Byte1]: 41
2772 20:15:04.296107
2773 20:15:04.296723 Set Vref, RX VrefLevel [Byte0]: 42
2774 20:15:04.298791 [Byte1]: 42
2775 20:15:04.303983
2776 20:15:04.304411 Set Vref, RX VrefLevel [Byte0]: 43
2777 20:15:04.306989 [Byte1]: 43
2778 20:15:04.311804
2779 20:15:04.312230 Set Vref, RX VrefLevel [Byte0]: 44
2780 20:15:04.314782 [Byte1]: 44
2781 20:15:04.319485
2782 20:15:04.320035 Set Vref, RX VrefLevel [Byte0]: 45
2783 20:15:04.322838 [Byte1]: 45
2784 20:15:04.327347
2785 20:15:04.327815 Set Vref, RX VrefLevel [Byte0]: 46
2786 20:15:04.331056 [Byte1]: 46
2787 20:15:04.335896
2788 20:15:04.336373 Set Vref, RX VrefLevel [Byte0]: 47
2789 20:15:04.338585 [Byte1]: 47
2790 20:15:04.343588
2791 20:15:04.344115 Set Vref, RX VrefLevel [Byte0]: 48
2792 20:15:04.347072 [Byte1]: 48
2793 20:15:04.350787
2794 20:15:04.351212 Set Vref, RX VrefLevel [Byte0]: 49
2795 20:15:04.354573 [Byte1]: 49
2796 20:15:04.359025
2797 20:15:04.359498 Set Vref, RX VrefLevel [Byte0]: 50
2798 20:15:04.362000 [Byte1]: 50
2799 20:15:04.367275
2800 20:15:04.367758 Set Vref, RX VrefLevel [Byte0]: 51
2801 20:15:04.370819 [Byte1]: 51
2802 20:15:04.375132
2803 20:15:04.375611 Set Vref, RX VrefLevel [Byte0]: 52
2804 20:15:04.378612 [Byte1]: 52
2805 20:15:04.382842
2806 20:15:04.386023 Set Vref, RX VrefLevel [Byte0]: 53
2807 20:15:04.389346 [Byte1]: 53
2808 20:15:04.389867
2809 20:15:04.392475 Set Vref, RX VrefLevel [Byte0]: 54
2810 20:15:04.396327 [Byte1]: 54
2811 20:15:04.396957
2812 20:15:04.399612 Set Vref, RX VrefLevel [Byte0]: 55
2813 20:15:04.402454 [Byte1]: 55
2814 20:15:04.406482
2815 20:15:04.406950 Set Vref, RX VrefLevel [Byte0]: 56
2816 20:15:04.410084 [Byte1]: 56
2817 20:15:04.414143
2818 20:15:04.414632 Set Vref, RX VrefLevel [Byte0]: 57
2819 20:15:04.417366 [Byte1]: 57
2820 20:15:04.422264
2821 20:15:04.422847 Set Vref, RX VrefLevel [Byte0]: 58
2822 20:15:04.425830 [Byte1]: 58
2823 20:15:04.430352
2824 20:15:04.430933 Set Vref, RX VrefLevel [Byte0]: 59
2825 20:15:04.434377 [Byte1]: 59
2826 20:15:04.438273
2827 20:15:04.438723 Set Vref, RX VrefLevel [Byte0]: 60
2828 20:15:04.441854 [Byte1]: 60
2829 20:15:04.446235
2830 20:15:04.446653 Set Vref, RX VrefLevel [Byte0]: 61
2831 20:15:04.449549 [Byte1]: 61
2832 20:15:04.454738
2833 20:15:04.455383 Set Vref, RX VrefLevel [Byte0]: 62
2834 20:15:04.457448 [Byte1]: 62
2835 20:15:04.462311
2836 20:15:04.462732 Set Vref, RX VrefLevel [Byte0]: 63
2837 20:15:04.465703 [Byte1]: 63
2838 20:15:04.469724
2839 20:15:04.470185 Set Vref, RX VrefLevel [Byte0]: 64
2840 20:15:04.473417 [Byte1]: 64
2841 20:15:04.478098
2842 20:15:04.478623 Set Vref, RX VrefLevel [Byte0]: 65
2843 20:15:04.481749 [Byte1]: 65
2844 20:15:04.486296
2845 20:15:04.486712 Set Vref, RX VrefLevel [Byte0]: 66
2846 20:15:04.489326 [Byte1]: 66
2847 20:15:04.493690
2848 20:15:04.494111 Set Vref, RX VrefLevel [Byte0]: 67
2849 20:15:04.497615 [Byte1]: 67
2850 20:15:04.501716
2851 20:15:04.502270 Set Vref, RX VrefLevel [Byte0]: 68
2852 20:15:04.505043 [Byte1]: 68
2853 20:15:04.509521
2854 20:15:04.509935 Set Vref, RX VrefLevel [Byte0]: 69
2855 20:15:04.513170 [Byte1]: 69
2856 20:15:04.517235
2857 20:15:04.517653 Set Vref, RX VrefLevel [Byte0]: 70
2858 20:15:04.520900 [Byte1]: 70
2859 20:15:04.525470
2860 20:15:04.525888 Set Vref, RX VrefLevel [Byte0]: 71
2861 20:15:04.529521 [Byte1]: 71
2862 20:15:04.533615
2863 20:15:04.534033 Set Vref, RX VrefLevel [Byte0]: 72
2864 20:15:04.537317 [Byte1]: 72
2865 20:15:04.541425
2866 20:15:04.541847 Set Vref, RX VrefLevel [Byte0]: 73
2867 20:15:04.544417 [Byte1]: 73
2868 20:15:04.548954
2869 20:15:04.549423 Set Vref, RX VrefLevel [Byte0]: 74
2870 20:15:04.552452 [Byte1]: 74
2871 20:15:04.557193
2872 20:15:04.557615 Set Vref, RX VrefLevel [Byte0]: 75
2873 20:15:04.560577 [Byte1]: 75
2874 20:15:04.564991
2875 20:15:04.565408 Set Vref, RX VrefLevel [Byte0]: 76
2876 20:15:04.568324 [Byte1]: 76
2877 20:15:04.572718
2878 20:15:04.572812 Final RX Vref Byte 0 = 60 to rank0
2879 20:15:04.576269 Final RX Vref Byte 1 = 59 to rank0
2880 20:15:04.579051 Final RX Vref Byte 0 = 60 to rank1
2881 20:15:04.582696 Final RX Vref Byte 1 = 59 to rank1==
2882 20:15:04.586109 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 20:15:04.592816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 20:15:04.592922 ==
2885 20:15:04.593004 DQS Delay:
2886 20:15:04.595645 DQS0 = 0, DQS1 = 0
2887 20:15:04.595794 DQM Delay:
2888 20:15:04.595924 DQM0 = 119, DQM1 = 107
2889 20:15:04.598894 DQ Delay:
2890 20:15:04.602697 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2891 20:15:04.605588 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2892 20:15:04.609007 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
2893 20:15:04.612420 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =114
2894 20:15:04.612578
2895 20:15:04.612737
2896 20:15:04.622052 [DQSOSCAuto] RK0, (LSB)MR18= 0xaf6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 406 ps
2897 20:15:04.622273 CH0 RK0: MR19=403, MR18=AF6
2898 20:15:04.628850 CH0_RK0: MR19=0x403, MR18=0xAF6, DQSOSC=406, MR23=63, INC=39, DEC=26
2899 20:15:04.629186
2900 20:15:04.632754 ----->DramcWriteLeveling(PI) begin...
2901 20:15:04.633179 ==
2902 20:15:04.635643 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 20:15:04.638956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 20:15:04.642544 ==
2905 20:15:04.642969 Write leveling (Byte 0): 31 => 31
2906 20:15:04.646195 Write leveling (Byte 1): 31 => 31
2907 20:15:04.649452 DramcWriteLeveling(PI) end<-----
2908 20:15:04.649968
2909 20:15:04.650320 ==
2910 20:15:04.652741 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 20:15:04.659083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 20:15:04.659551 ==
2913 20:15:04.662793 [Gating] SW mode calibration
2914 20:15:04.669245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 20:15:04.673473 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 20:15:04.679517 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2917 20:15:04.682656 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2918 20:15:04.685863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 20:15:04.692384 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 20:15:04.695808 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 20:15:04.699305 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 20:15:04.705968 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2923 20:15:04.708837 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2924 20:15:04.712063 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2925 20:15:04.718790 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 20:15:04.722076 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 20:15:04.725506 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 20:15:04.729568 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 20:15:04.735376 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 20:15:04.738837 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 20:15:04.742491 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2932 20:15:04.749061 1 1 0 | B1->B0 | 3232 4444 | 0 0 | (1 1) (0 0)
2933 20:15:04.752120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 20:15:04.755276 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 20:15:04.762081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 20:15:04.766188 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 20:15:04.768753 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 20:15:04.775302 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 20:15:04.778706 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2940 20:15:04.782022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2941 20:15:04.788417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 20:15:04.791753 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 20:15:04.794882 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 20:15:04.801937 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 20:15:04.804908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 20:15:04.808216 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 20:15:04.814999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 20:15:04.818173 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 20:15:04.821815 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 20:15:04.828203 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 20:15:04.831699 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 20:15:04.834671 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 20:15:04.841297 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 20:15:04.844351 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2955 20:15:04.849002 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2956 20:15:04.854900 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 20:15:04.855317 Total UI for P1: 0, mck2ui 16
2958 20:15:04.861020 best dqsien dly found for B0: ( 1, 3, 26)
2959 20:15:04.861437 Total UI for P1: 0, mck2ui 16
2960 20:15:04.867636 best dqsien dly found for B1: ( 1, 3, 30)
2961 20:15:04.871269 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2962 20:15:04.874117 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2963 20:15:04.874534
2964 20:15:04.877703 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2965 20:15:04.881204 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2966 20:15:04.884338 [Gating] SW calibration Done
2967 20:15:04.884756 ==
2968 20:15:04.887456 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 20:15:04.890985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 20:15:04.891421 ==
2971 20:15:04.893993 RX Vref Scan: 0
2972 20:15:04.894412
2973 20:15:04.894744 RX Vref 0 -> 0, step: 1
2974 20:15:04.895056
2975 20:15:04.897779 RX Delay -40 -> 252, step: 8
2976 20:15:04.901267 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2977 20:15:04.908028 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2978 20:15:04.910562 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2979 20:15:04.914365 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2980 20:15:04.917538 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2981 20:15:04.920897 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2982 20:15:04.926995 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2983 20:15:04.930382 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2984 20:15:04.933887 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2985 20:15:04.937645 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2986 20:15:04.940556 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2987 20:15:04.947138 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2988 20:15:04.950657 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2989 20:15:04.953579 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2990 20:15:04.956965 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2991 20:15:04.963559 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2992 20:15:04.964019 ==
2993 20:15:04.966623 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 20:15:04.970369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 20:15:04.970784 ==
2996 20:15:04.971158 DQS Delay:
2997 20:15:04.973106 DQS0 = 0, DQS1 = 0
2998 20:15:04.973548 DQM Delay:
2999 20:15:04.977078 DQM0 = 117, DQM1 = 109
3000 20:15:04.977497 DQ Delay:
3001 20:15:04.979888 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3002 20:15:04.983042 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3003 20:15:04.986955 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3004 20:15:04.989765 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
3005 20:15:04.990180
3006 20:15:04.990512
3007 20:15:04.993240 ==
3008 20:15:04.996723 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 20:15:04.999884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 20:15:05.000315 ==
3011 20:15:05.000645
3012 20:15:05.000968
3013 20:15:05.003068 TX Vref Scan disable
3014 20:15:05.003479 == TX Byte 0 ==
3015 20:15:05.009749 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3016 20:15:05.013108 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3017 20:15:05.013524 == TX Byte 1 ==
3018 20:15:05.019618 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3019 20:15:05.022925 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3020 20:15:05.023340 ==
3021 20:15:05.025880 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 20:15:05.029362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 20:15:05.029780 ==
3024 20:15:05.041904 TX Vref=22, minBit 5, minWin=25, winSum=416
3025 20:15:05.045515 TX Vref=24, minBit 13, minWin=25, winSum=421
3026 20:15:05.048385 TX Vref=26, minBit 2, minWin=26, winSum=430
3027 20:15:05.051765 TX Vref=28, minBit 1, minWin=27, winSum=434
3028 20:15:05.055114 TX Vref=30, minBit 8, minWin=26, winSum=432
3029 20:15:05.061879 TX Vref=32, minBit 12, minWin=26, winSum=429
3030 20:15:05.065458 [TxChooseVref] Worse bit 1, Min win 27, Win sum 434, Final Vref 28
3031 20:15:05.065876
3032 20:15:05.068733 Final TX Range 1 Vref 28
3033 20:15:05.069149
3034 20:15:05.069475 ==
3035 20:15:05.071668 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 20:15:05.075365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 20:15:05.075828 ==
3038 20:15:05.078404
3039 20:15:05.078816
3040 20:15:05.079146 TX Vref Scan disable
3041 20:15:05.081743 == TX Byte 0 ==
3042 20:15:05.084863 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3043 20:15:05.091286 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3044 20:15:05.091733 == TX Byte 1 ==
3045 20:15:05.095181 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3046 20:15:05.101414 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3047 20:15:05.101833
3048 20:15:05.102164 [DATLAT]
3049 20:15:05.102467 Freq=1200, CH0 RK1
3050 20:15:05.102768
3051 20:15:05.104669 DATLAT Default: 0xd
3052 20:15:05.107770 0, 0xFFFF, sum = 0
3053 20:15:05.108203 1, 0xFFFF, sum = 0
3054 20:15:05.111756 2, 0xFFFF, sum = 0
3055 20:15:05.112186 3, 0xFFFF, sum = 0
3056 20:15:05.115152 4, 0xFFFF, sum = 0
3057 20:15:05.115868 5, 0xFFFF, sum = 0
3058 20:15:05.118096 6, 0xFFFF, sum = 0
3059 20:15:05.118619 7, 0xFFFF, sum = 0
3060 20:15:05.121748 8, 0xFFFF, sum = 0
3061 20:15:05.122166 9, 0xFFFF, sum = 0
3062 20:15:05.124624 10, 0xFFFF, sum = 0
3063 20:15:05.125050 11, 0xFFFF, sum = 0
3064 20:15:05.127773 12, 0x0, sum = 1
3065 20:15:05.128204 13, 0x0, sum = 2
3066 20:15:05.131374 14, 0x0, sum = 3
3067 20:15:05.131835 15, 0x0, sum = 4
3068 20:15:05.134859 best_step = 13
3069 20:15:05.135276
3070 20:15:05.135607 ==
3071 20:15:05.137930 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 20:15:05.141551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 20:15:05.141976 ==
3074 20:15:05.144241 RX Vref Scan: 0
3075 20:15:05.144685
3076 20:15:05.145022 RX Vref 0 -> 0, step: 1
3077 20:15:05.145369
3078 20:15:05.147562 RX Delay -21 -> 252, step: 4
3079 20:15:05.154632 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3080 20:15:05.157738 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3081 20:15:05.161065 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3082 20:15:05.164062 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3083 20:15:05.167560 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3084 20:15:05.174378 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3085 20:15:05.178093 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3086 20:15:05.180884 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3087 20:15:05.184017 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3088 20:15:05.187368 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3089 20:15:05.194724 iDelay=195, Bit 10, Center 114 (47 ~ 182) 136
3090 20:15:05.197270 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3091 20:15:05.200444 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3092 20:15:05.203757 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3093 20:15:05.207720 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3094 20:15:05.214339 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3095 20:15:05.214855 ==
3096 20:15:05.217839 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 20:15:05.220934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 20:15:05.221399 ==
3099 20:15:05.221766 DQS Delay:
3100 20:15:05.225049 DQS0 = 0, DQS1 = 0
3101 20:15:05.225637 DQM Delay:
3102 20:15:05.227220 DQM0 = 116, DQM1 = 110
3103 20:15:05.227766 DQ Delay:
3104 20:15:05.230814 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3105 20:15:05.233677 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3106 20:15:05.237918 DQ8 =98, DQ9 =94, DQ10 =114, DQ11 =104
3107 20:15:05.240243 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =118
3108 20:15:05.240660
3109 20:15:05.240989
3110 20:15:05.250351 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3111 20:15:05.253827 CH0 RK1: MR19=403, MR18=9E3
3112 20:15:05.257043 CH0_RK1: MR19=0x403, MR18=0x9E3, DQSOSC=406, MR23=63, INC=39, DEC=26
3113 20:15:05.260237 [RxdqsGatingPostProcess] freq 1200
3114 20:15:05.266959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 20:15:05.270513 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 20:15:05.273866 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 20:15:05.277356 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 20:15:05.280004 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 20:15:05.283442 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 20:15:05.286791 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 20:15:05.289990 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 20:15:05.293435 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 20:15:05.297003 Pre-setting of DQS Precalculation
3124 20:15:05.299962 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 20:15:05.300398 ==
3126 20:15:05.303353 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 20:15:05.306469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 20:15:05.307012 ==
3129 20:15:05.313379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 20:15:05.319802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3131 20:15:05.327746 [CA 0] Center 37 (7~68) winsize 62
3132 20:15:05.331630 [CA 1] Center 37 (7~68) winsize 62
3133 20:15:05.334508 [CA 2] Center 34 (4~64) winsize 61
3134 20:15:05.337639 [CA 3] Center 33 (3~64) winsize 62
3135 20:15:05.341160 [CA 4] Center 34 (4~64) winsize 61
3136 20:15:05.344403 [CA 5] Center 33 (3~64) winsize 62
3137 20:15:05.344863
3138 20:15:05.347378 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3139 20:15:05.347870
3140 20:15:05.351331 [CATrainingPosCal] consider 1 rank data
3141 20:15:05.354539 u2DelayCellTimex100 = 270/100 ps
3142 20:15:05.357680 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 20:15:05.364027 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 20:15:05.367741 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3145 20:15:05.370271 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 20:15:05.374802 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 20:15:05.377145 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3148 20:15:05.377611
3149 20:15:05.381289 CA PerBit enable=1, Macro0, CA PI delay=33
3150 20:15:05.381860
3151 20:15:05.384383 [CBTSetCACLKResult] CA Dly = 33
3152 20:15:05.387713 CS Dly: 6 (0~37)
3153 20:15:05.388254 ==
3154 20:15:05.390509 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 20:15:05.394190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 20:15:05.394968 ==
3157 20:15:05.401038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 20:15:05.403719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3159 20:15:05.414030 [CA 0] Center 37 (7~68) winsize 62
3160 20:15:05.416421 [CA 1] Center 38 (8~68) winsize 61
3161 20:15:05.420968 [CA 2] Center 34 (4~65) winsize 62
3162 20:15:05.424347 [CA 3] Center 33 (3~64) winsize 62
3163 20:15:05.427098 [CA 4] Center 34 (4~65) winsize 62
3164 20:15:05.430374 [CA 5] Center 33 (3~64) winsize 62
3165 20:15:05.430936
3166 20:15:05.433778 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3167 20:15:05.434344
3168 20:15:05.437244 [CATrainingPosCal] consider 2 rank data
3169 20:15:05.440383 u2DelayCellTimex100 = 270/100 ps
3170 20:15:05.443883 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 20:15:05.447576 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3172 20:15:05.453744 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 20:15:05.456732 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 20:15:05.460360 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 20:15:05.463642 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 20:15:05.464264
3177 20:15:05.466488 CA PerBit enable=1, Macro0, CA PI delay=33
3178 20:15:05.466945
3179 20:15:05.469949 [CBTSetCACLKResult] CA Dly = 33
3180 20:15:05.470414 CS Dly: 7 (0~40)
3181 20:15:05.470780
3182 20:15:05.473592 ----->DramcWriteLeveling(PI) begin...
3183 20:15:05.476545 ==
3184 20:15:05.479952 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 20:15:05.483703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 20:15:05.484293 ==
3187 20:15:05.486617 Write leveling (Byte 0): 24 => 24
3188 20:15:05.489995 Write leveling (Byte 1): 28 => 28
3189 20:15:05.493612 DramcWriteLeveling(PI) end<-----
3190 20:15:05.494171
3191 20:15:05.494533 ==
3192 20:15:05.497137 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 20:15:05.500218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 20:15:05.500847 ==
3195 20:15:05.504015 [Gating] SW mode calibration
3196 20:15:05.509802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 20:15:05.516404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 20:15:05.520025 0 15 0 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
3199 20:15:05.523740 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 20:15:05.526903 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 20:15:05.532984 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 20:15:05.536625 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 20:15:05.540099 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 20:15:05.547192 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
3205 20:15:05.550299 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3206 20:15:05.553306 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 20:15:05.559954 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 20:15:05.563269 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 20:15:05.566241 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 20:15:05.572823 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 20:15:05.576013 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 20:15:05.579617 1 0 24 | B1->B0 | 2626 3333 | 0 1 | (0 0) (0 0)
3213 20:15:05.585741 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3214 20:15:05.589393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 20:15:05.592924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 20:15:05.599347 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 20:15:05.602941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 20:15:05.605786 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 20:15:05.612590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 20:15:05.616213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3221 20:15:05.619562 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3222 20:15:05.626029 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 20:15:05.629027 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 20:15:05.633061 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 20:15:05.639103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 20:15:05.642563 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 20:15:05.645664 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 20:15:05.652966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 20:15:05.655664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 20:15:05.659214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 20:15:05.666045 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 20:15:05.669244 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 20:15:05.672108 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 20:15:05.679271 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 20:15:05.682015 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 20:15:05.685641 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 20:15:05.692350 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3238 20:15:05.695590 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 20:15:05.698579 Total UI for P1: 0, mck2ui 16
3240 20:15:05.701697 best dqsien dly found for B0: ( 1, 3, 26)
3241 20:15:05.705284 Total UI for P1: 0, mck2ui 16
3242 20:15:05.708246 best dqsien dly found for B1: ( 1, 3, 26)
3243 20:15:05.711532 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3244 20:15:05.715271 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3245 20:15:05.716013
3246 20:15:05.718596 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3247 20:15:05.721962 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3248 20:15:05.725238 [Gating] SW calibration Done
3249 20:15:05.725700 ==
3250 20:15:05.728715 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 20:15:05.731835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 20:15:05.734854 ==
3253 20:15:05.735423 RX Vref Scan: 0
3254 20:15:05.735862
3255 20:15:05.738883 RX Vref 0 -> 0, step: 1
3256 20:15:05.739456
3257 20:15:05.741686 RX Delay -40 -> 252, step: 8
3258 20:15:05.745167 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3259 20:15:05.748458 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3260 20:15:05.751507 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3261 20:15:05.754603 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3262 20:15:05.761384 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3263 20:15:05.764993 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3264 20:15:05.768086 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3265 20:15:05.771454 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3266 20:15:05.774975 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3267 20:15:05.781881 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3268 20:15:05.785212 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3269 20:15:05.787797 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3270 20:15:05.791379 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3271 20:15:05.794628 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3272 20:15:05.800843 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3273 20:15:05.804395 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3274 20:15:05.804889 ==
3275 20:15:05.808322 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 20:15:05.811128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 20:15:05.811586 ==
3278 20:15:05.814650 DQS Delay:
3279 20:15:05.815062 DQS0 = 0, DQS1 = 0
3280 20:15:05.815391 DQM Delay:
3281 20:15:05.817608 DQM0 = 118, DQM1 = 108
3282 20:15:05.818025 DQ Delay:
3283 20:15:05.820910 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3284 20:15:05.825052 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3285 20:15:05.828076 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3286 20:15:05.834145 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3287 20:15:05.834559
3288 20:15:05.834889
3289 20:15:05.835193 ==
3290 20:15:05.837770 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 20:15:05.841332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 20:15:05.841860 ==
3293 20:15:05.842357
3294 20:15:05.843006
3295 20:15:05.844318 TX Vref Scan disable
3296 20:15:05.845002 == TX Byte 0 ==
3297 20:15:05.850515 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3298 20:15:05.854367 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3299 20:15:05.854918 == TX Byte 1 ==
3300 20:15:05.860921 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3301 20:15:05.864993 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3302 20:15:05.865542 ==
3303 20:15:05.867993 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 20:15:05.871167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 20:15:05.871723 ==
3306 20:15:05.884078 TX Vref=22, minBit 8, minWin=24, winSum=412
3307 20:15:05.887226 TX Vref=24, minBit 8, minWin=25, winSum=420
3308 20:15:05.890020 TX Vref=26, minBit 9, minWin=25, winSum=424
3309 20:15:05.893726 TX Vref=28, minBit 9, minWin=25, winSum=427
3310 20:15:05.896917 TX Vref=30, minBit 9, minWin=25, winSum=429
3311 20:15:05.903350 TX Vref=32, minBit 8, minWin=25, winSum=422
3312 20:15:05.907774 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30
3313 20:15:05.908354
3314 20:15:05.909879 Final TX Range 1 Vref 30
3315 20:15:05.910348
3316 20:15:05.910721 ==
3317 20:15:05.913321 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 20:15:05.916698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 20:15:05.917169 ==
3320 20:15:05.919633
3321 20:15:05.920128
3322 20:15:05.920500 TX Vref Scan disable
3323 20:15:05.923039 == TX Byte 0 ==
3324 20:15:05.926710 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3325 20:15:05.933586 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3326 20:15:05.934161 == TX Byte 1 ==
3327 20:15:05.937077 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3328 20:15:05.943088 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3329 20:15:05.943646
3330 20:15:05.944045 [DATLAT]
3331 20:15:05.944391 Freq=1200, CH1 RK0
3332 20:15:05.944725
3333 20:15:05.946617 DATLAT Default: 0xd
3334 20:15:05.947079 0, 0xFFFF, sum = 0
3335 20:15:05.949807 1, 0xFFFF, sum = 0
3336 20:15:05.952943 2, 0xFFFF, sum = 0
3337 20:15:05.953425 3, 0xFFFF, sum = 0
3338 20:15:05.956131 4, 0xFFFF, sum = 0
3339 20:15:05.956601 5, 0xFFFF, sum = 0
3340 20:15:05.960353 6, 0xFFFF, sum = 0
3341 20:15:05.960821 7, 0xFFFF, sum = 0
3342 20:15:05.962775 8, 0xFFFF, sum = 0
3343 20:15:05.963386 9, 0xFFFF, sum = 0
3344 20:15:05.966705 10, 0xFFFF, sum = 0
3345 20:15:05.967175 11, 0xFFFF, sum = 0
3346 20:15:05.969809 12, 0x0, sum = 1
3347 20:15:05.970276 13, 0x0, sum = 2
3348 20:15:05.973055 14, 0x0, sum = 3
3349 20:15:05.973481 15, 0x0, sum = 4
3350 20:15:05.976512 best_step = 13
3351 20:15:05.976928
3352 20:15:05.977261 ==
3353 20:15:05.980197 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 20:15:05.983236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 20:15:05.983809 ==
3356 20:15:05.984154 RX Vref Scan: 1
3357 20:15:05.984466
3358 20:15:05.986567 Set Vref Range= 32 -> 127
3359 20:15:05.987099
3360 20:15:05.989509 RX Vref 32 -> 127, step: 1
3361 20:15:05.990032
3362 20:15:05.993268 RX Delay -21 -> 252, step: 4
3363 20:15:05.993796
3364 20:15:05.996143 Set Vref, RX VrefLevel [Byte0]: 32
3365 20:15:06.000290 [Byte1]: 32
3366 20:15:06.000823
3367 20:15:06.002562 Set Vref, RX VrefLevel [Byte0]: 33
3368 20:15:06.005875 [Byte1]: 33
3369 20:15:06.009572
3370 20:15:06.010051 Set Vref, RX VrefLevel [Byte0]: 34
3371 20:15:06.013257 [Byte1]: 34
3372 20:15:06.017650
3373 20:15:06.018213 Set Vref, RX VrefLevel [Byte0]: 35
3374 20:15:06.020585 [Byte1]: 35
3375 20:15:06.026034
3376 20:15:06.026592 Set Vref, RX VrefLevel [Byte0]: 36
3377 20:15:06.028901 [Byte1]: 36
3378 20:15:06.033314
3379 20:15:06.033869 Set Vref, RX VrefLevel [Byte0]: 37
3380 20:15:06.036438 [Byte1]: 37
3381 20:15:06.041301
3382 20:15:06.041855 Set Vref, RX VrefLevel [Byte0]: 38
3383 20:15:06.044327 [Byte1]: 38
3384 20:15:06.049619
3385 20:15:06.050174 Set Vref, RX VrefLevel [Byte0]: 39
3386 20:15:06.052334 [Byte1]: 39
3387 20:15:06.057054
3388 20:15:06.057607 Set Vref, RX VrefLevel [Byte0]: 40
3389 20:15:06.060786 [Byte1]: 40
3390 20:15:06.065101
3391 20:15:06.065568 Set Vref, RX VrefLevel [Byte0]: 41
3392 20:15:06.068261 [Byte1]: 41
3393 20:15:06.072920
3394 20:15:06.073373 Set Vref, RX VrefLevel [Byte0]: 42
3395 20:15:06.076207 [Byte1]: 42
3396 20:15:06.080941
3397 20:15:06.081518 Set Vref, RX VrefLevel [Byte0]: 43
3398 20:15:06.084082 [Byte1]: 43
3399 20:15:06.088513
3400 20:15:06.088972 Set Vref, RX VrefLevel [Byte0]: 44
3401 20:15:06.092319 [Byte1]: 44
3402 20:15:06.096771
3403 20:15:06.097326 Set Vref, RX VrefLevel [Byte0]: 45
3404 20:15:06.099952 [Byte1]: 45
3405 20:15:06.105172
3406 20:15:06.105764 Set Vref, RX VrefLevel [Byte0]: 46
3407 20:15:06.107849 [Byte1]: 46
3408 20:15:06.113303
3409 20:15:06.113763 Set Vref, RX VrefLevel [Byte0]: 47
3410 20:15:06.115589 [Byte1]: 47
3411 20:15:06.120951
3412 20:15:06.121508 Set Vref, RX VrefLevel [Byte0]: 48
3413 20:15:06.124149 [Byte1]: 48
3414 20:15:06.128616
3415 20:15:06.129171 Set Vref, RX VrefLevel [Byte0]: 49
3416 20:15:06.134547 [Byte1]: 49
3417 20:15:06.135037
3418 20:15:06.138528 Set Vref, RX VrefLevel [Byte0]: 50
3419 20:15:06.141549 [Byte1]: 50
3420 20:15:06.142107
3421 20:15:06.145091 Set Vref, RX VrefLevel [Byte0]: 51
3422 20:15:06.148655 [Byte1]: 51
3423 20:15:06.152265
3424 20:15:06.152823 Set Vref, RX VrefLevel [Byte0]: 52
3425 20:15:06.155894 [Byte1]: 52
3426 20:15:06.160669
3427 20:15:06.161224 Set Vref, RX VrefLevel [Byte0]: 53
3428 20:15:06.163441 [Byte1]: 53
3429 20:15:06.168550
3430 20:15:06.169136 Set Vref, RX VrefLevel [Byte0]: 54
3431 20:15:06.171468 [Byte1]: 54
3432 20:15:06.176000
3433 20:15:06.176467 Set Vref, RX VrefLevel [Byte0]: 55
3434 20:15:06.179843 [Byte1]: 55
3435 20:15:06.184927
3436 20:15:06.185478 Set Vref, RX VrefLevel [Byte0]: 56
3437 20:15:06.186878 [Byte1]: 56
3438 20:15:06.192048
3439 20:15:06.192601 Set Vref, RX VrefLevel [Byte0]: 57
3440 20:15:06.195134 [Byte1]: 57
3441 20:15:06.199864
3442 20:15:06.200416 Set Vref, RX VrefLevel [Byte0]: 58
3443 20:15:06.202645 [Byte1]: 58
3444 20:15:06.208016
3445 20:15:06.208476 Set Vref, RX VrefLevel [Byte0]: 59
3446 20:15:06.210887 [Byte1]: 59
3447 20:15:06.215975
3448 20:15:06.216531 Set Vref, RX VrefLevel [Byte0]: 60
3449 20:15:06.219008 [Byte1]: 60
3450 20:15:06.223732
3451 20:15:06.224290 Set Vref, RX VrefLevel [Byte0]: 61
3452 20:15:06.227250 [Byte1]: 61
3453 20:15:06.231739
3454 20:15:06.232299 Set Vref, RX VrefLevel [Byte0]: 62
3455 20:15:06.234645 [Byte1]: 62
3456 20:15:06.239940
3457 20:15:06.240492 Set Vref, RX VrefLevel [Byte0]: 63
3458 20:15:06.242694 [Byte1]: 63
3459 20:15:06.247483
3460 20:15:06.248099 Set Vref, RX VrefLevel [Byte0]: 64
3461 20:15:06.251067 [Byte1]: 64
3462 20:15:06.254719
3463 20:15:06.255175 Set Vref, RX VrefLevel [Byte0]: 65
3464 20:15:06.258360 [Byte1]: 65
3465 20:15:06.263132
3466 20:15:06.263624 Set Vref, RX VrefLevel [Byte0]: 66
3467 20:15:06.266619 [Byte1]: 66
3468 20:15:06.270742
3469 20:15:06.271195 Set Vref, RX VrefLevel [Byte0]: 67
3470 20:15:06.273946 [Byte1]: 67
3471 20:15:06.278701
3472 20:15:06.279066 Final RX Vref Byte 0 = 48 to rank0
3473 20:15:06.282275 Final RX Vref Byte 1 = 59 to rank0
3474 20:15:06.285123 Final RX Vref Byte 0 = 48 to rank1
3475 20:15:06.288464 Final RX Vref Byte 1 = 59 to rank1==
3476 20:15:06.291602 Dram Type= 6, Freq= 0, CH_1, rank 0
3477 20:15:06.297990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 20:15:06.298179 ==
3479 20:15:06.298351 DQS Delay:
3480 20:15:06.301452 DQS0 = 0, DQS1 = 0
3481 20:15:06.301596 DQM Delay:
3482 20:15:06.301805 DQM0 = 116, DQM1 = 112
3483 20:15:06.304596 DQ Delay:
3484 20:15:06.308553 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3485 20:15:06.310992 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =114
3486 20:15:06.314217 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =102
3487 20:15:06.317844 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =120
3488 20:15:06.317941
3489 20:15:06.318010
3490 20:15:06.327467 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3491 20:15:06.327587 CH1 RK0: MR19=403, MR18=2F5
3492 20:15:06.334214 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3493 20:15:06.334298
3494 20:15:06.337297 ----->DramcWriteLeveling(PI) begin...
3495 20:15:06.337383 ==
3496 20:15:06.341503 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 20:15:06.347284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 20:15:06.347414 ==
3499 20:15:06.350296 Write leveling (Byte 0): 25 => 25
3500 20:15:06.354164 Write leveling (Byte 1): 27 => 27
3501 20:15:06.354269 DramcWriteLeveling(PI) end<-----
3502 20:15:06.357400
3503 20:15:06.357482 ==
3504 20:15:06.360615 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 20:15:06.364165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 20:15:06.364502 ==
3507 20:15:06.367315 [Gating] SW mode calibration
3508 20:15:06.374026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3509 20:15:06.377095 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3510 20:15:06.384657 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
3511 20:15:06.387219 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 20:15:06.390328 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 20:15:06.397368 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 20:15:06.400333 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 20:15:06.404056 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 20:15:06.410808 0 15 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3517 20:15:06.413623 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3518 20:15:06.416858 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 20:15:06.423076 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 20:15:06.427135 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 20:15:06.429656 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 20:15:06.436870 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 20:15:06.439701 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 20:15:06.442788 1 0 24 | B1->B0 | 3232 2323 | 1 1 | (0 0) (0 0)
3525 20:15:06.449542 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3526 20:15:06.452982 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 20:15:06.456071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 20:15:06.462604 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 20:15:06.466120 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 20:15:06.469666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 20:15:06.475901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 20:15:06.478906 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 20:15:06.485865 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 20:15:06.489486 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 20:15:06.492689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 20:15:06.498748 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 20:15:06.502005 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 20:15:06.505569 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 20:15:06.512233 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 20:15:06.515435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 20:15:06.518861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 20:15:06.522477 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 20:15:06.528858 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 20:15:06.532311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 20:15:06.538568 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 20:15:06.542062 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 20:15:06.545522 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 20:15:06.551769 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3549 20:15:06.555524 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3550 20:15:06.558742 Total UI for P1: 0, mck2ui 16
3551 20:15:06.561948 best dqsien dly found for B1: ( 1, 3, 24)
3552 20:15:06.565339 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 20:15:06.568232 Total UI for P1: 0, mck2ui 16
3554 20:15:06.571643 best dqsien dly found for B0: ( 1, 3, 26)
3555 20:15:06.575014 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3556 20:15:06.577768 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3557 20:15:06.577952
3558 20:15:06.581402 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3559 20:15:06.588305 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 20:15:06.588614 [Gating] SW calibration Done
3561 20:15:06.588888 ==
3562 20:15:06.591178 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 20:15:06.597561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 20:15:06.597859 ==
3565 20:15:06.598131 RX Vref Scan: 0
3566 20:15:06.598405
3567 20:15:06.601001 RX Vref 0 -> 0, step: 1
3568 20:15:06.601297
3569 20:15:06.604310 RX Delay -40 -> 252, step: 8
3570 20:15:06.607462 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3571 20:15:06.611157 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3572 20:15:06.617453 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3573 20:15:06.620365 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3574 20:15:06.623646 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3575 20:15:06.627354 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3576 20:15:06.630692 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3577 20:15:06.636937 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3578 20:15:06.640187 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3579 20:15:06.644047 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3580 20:15:06.647541 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3581 20:15:06.650558 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3582 20:15:06.657106 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3583 20:15:06.660818 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3584 20:15:06.663945 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3585 20:15:06.666758 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3586 20:15:06.666889 ==
3587 20:15:06.670812 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 20:15:06.676786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 20:15:06.676969 ==
3590 20:15:06.677061 DQS Delay:
3591 20:15:06.680476 DQS0 = 0, DQS1 = 0
3592 20:15:06.680674 DQM Delay:
3593 20:15:06.680781 DQM0 = 116, DQM1 = 110
3594 20:15:06.683617 DQ Delay:
3595 20:15:06.686483 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3596 20:15:06.690110 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3597 20:15:06.693849 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3598 20:15:06.696897 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3599 20:15:06.697163
3600 20:15:06.697339
3601 20:15:06.697501 ==
3602 20:15:06.699884 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 20:15:06.704031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 20:15:06.706686 ==
3605 20:15:06.706919
3606 20:15:06.707090
3607 20:15:06.707290 TX Vref Scan disable
3608 20:15:06.709542 == TX Byte 0 ==
3609 20:15:06.713448 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 20:15:06.716602 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 20:15:06.719838 == TX Byte 1 ==
3612 20:15:06.723712 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3613 20:15:06.729989 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3614 20:15:06.730549 ==
3615 20:15:06.733364 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 20:15:06.736384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 20:15:06.736945 ==
3618 20:15:06.747600 TX Vref=22, minBit 9, minWin=25, winSum=425
3619 20:15:06.751352 TX Vref=24, minBit 11, minWin=26, winSum=432
3620 20:15:06.754113 TX Vref=26, minBit 9, minWin=26, winSum=434
3621 20:15:06.757667 TX Vref=28, minBit 9, minWin=26, winSum=435
3622 20:15:06.760675 TX Vref=30, minBit 9, minWin=26, winSum=438
3623 20:15:06.767331 TX Vref=32, minBit 9, minWin=26, winSum=435
3624 20:15:06.771228 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 30
3625 20:15:06.771747
3626 20:15:06.773756 Final TX Range 1 Vref 30
3627 20:15:06.774222
3628 20:15:06.774589 ==
3629 20:15:06.777713 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 20:15:06.780386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 20:15:06.784105 ==
3632 20:15:06.784599
3633 20:15:06.784972
3634 20:15:06.785318 TX Vref Scan disable
3635 20:15:06.787959 == TX Byte 0 ==
3636 20:15:06.790751 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3637 20:15:06.797733 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3638 20:15:06.798284 == TX Byte 1 ==
3639 20:15:06.800932 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3640 20:15:06.807350 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3641 20:15:06.807858
3642 20:15:06.808237 [DATLAT]
3643 20:15:06.808585 Freq=1200, CH1 RK1
3644 20:15:06.808923
3645 20:15:06.810432 DATLAT Default: 0xd
3646 20:15:06.814389 0, 0xFFFF, sum = 0
3647 20:15:06.814954 1, 0xFFFF, sum = 0
3648 20:15:06.817170 2, 0xFFFF, sum = 0
3649 20:15:06.817716 3, 0xFFFF, sum = 0
3650 20:15:06.820231 4, 0xFFFF, sum = 0
3651 20:15:06.820704 5, 0xFFFF, sum = 0
3652 20:15:06.823423 6, 0xFFFF, sum = 0
3653 20:15:06.823926 7, 0xFFFF, sum = 0
3654 20:15:06.827316 8, 0xFFFF, sum = 0
3655 20:15:06.827827 9, 0xFFFF, sum = 0
3656 20:15:06.831272 10, 0xFFFF, sum = 0
3657 20:15:06.831895 11, 0xFFFF, sum = 0
3658 20:15:06.833829 12, 0x0, sum = 1
3659 20:15:06.834305 13, 0x0, sum = 2
3660 20:15:06.837708 14, 0x0, sum = 3
3661 20:15:06.838259 15, 0x0, sum = 4
3662 20:15:06.840388 best_step = 13
3663 20:15:06.840855
3664 20:15:06.841224 ==
3665 20:15:06.843919 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 20:15:06.846806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 20:15:06.847372 ==
3668 20:15:06.850479 RX Vref Scan: 0
3669 20:15:06.851039
3670 20:15:06.851415 RX Vref 0 -> 0, step: 1
3671 20:15:06.851800
3672 20:15:06.853463 RX Delay -13 -> 252, step: 4
3673 20:15:06.860005 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3674 20:15:06.864271 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3675 20:15:06.866992 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3676 20:15:06.869675 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3677 20:15:06.873479 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3678 20:15:06.879912 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3679 20:15:06.883562 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3680 20:15:06.886259 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3681 20:15:06.889937 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3682 20:15:06.892940 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3683 20:15:06.899468 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3684 20:15:06.903432 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3685 20:15:06.906358 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3686 20:15:06.909727 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3687 20:15:06.916201 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3688 20:15:06.919618 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3689 20:15:06.920181 ==
3690 20:15:06.922265 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 20:15:06.926129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 20:15:06.926558 ==
3693 20:15:06.929622 DQS Delay:
3694 20:15:06.930427 DQS0 = 0, DQS1 = 0
3695 20:15:06.930992 DQM Delay:
3696 20:15:06.932683 DQM0 = 117, DQM1 = 112
3697 20:15:06.933110 DQ Delay:
3698 20:15:06.935738 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3699 20:15:06.939746 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3700 20:15:06.942631 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =102
3701 20:15:06.949790 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3702 20:15:06.950314
3703 20:15:06.950652
3704 20:15:06.956090 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0eb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3705 20:15:06.958942 CH1 RK1: MR19=303, MR18=F0EB
3706 20:15:06.965540 CH1_RK1: MR19=0x303, MR18=0xF0EB, DQSOSC=416, MR23=63, INC=37, DEC=25
3707 20:15:06.968760 [RxdqsGatingPostProcess] freq 1200
3708 20:15:06.972371 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 20:15:06.975714 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 20:15:06.979228 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 20:15:06.982163 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 20:15:06.985435 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 20:15:06.989009 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 20:15:06.992280 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 20:15:06.995590 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 20:15:06.998982 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 20:15:07.002301 Pre-setting of DQS Precalculation
3718 20:15:07.005312 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 20:15:07.015553 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 20:15:07.022072 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 20:15:07.022630
3722 20:15:07.023008
3723 20:15:07.025176 [Calibration Summary] 2400 Mbps
3724 20:15:07.025645 CH 0, Rank 0
3725 20:15:07.029041 SW Impedance : PASS
3726 20:15:07.029611 DUTY Scan : NO K
3727 20:15:07.032705 ZQ Calibration : PASS
3728 20:15:07.034955 Jitter Meter : NO K
3729 20:15:07.035483 CBT Training : PASS
3730 20:15:07.038183 Write leveling : PASS
3731 20:15:07.043040 RX DQS gating : PASS
3732 20:15:07.043606 RX DQ/DQS(RDDQC) : PASS
3733 20:15:07.045771 TX DQ/DQS : PASS
3734 20:15:07.048205 RX DATLAT : PASS
3735 20:15:07.048675 RX DQ/DQS(Engine): PASS
3736 20:15:07.052029 TX OE : NO K
3737 20:15:07.052599 All Pass.
3738 20:15:07.052977
3739 20:15:07.055027 CH 0, Rank 1
3740 20:15:07.055582 SW Impedance : PASS
3741 20:15:07.058411 DUTY Scan : NO K
3742 20:15:07.061995 ZQ Calibration : PASS
3743 20:15:07.062564 Jitter Meter : NO K
3744 20:15:07.064942 CBT Training : PASS
3745 20:15:07.067945 Write leveling : PASS
3746 20:15:07.068444 RX DQS gating : PASS
3747 20:15:07.071567 RX DQ/DQS(RDDQC) : PASS
3748 20:15:07.074974 TX DQ/DQS : PASS
3749 20:15:07.075446 RX DATLAT : PASS
3750 20:15:07.078211 RX DQ/DQS(Engine): PASS
3751 20:15:07.080848 TX OE : NO K
3752 20:15:07.081322 All Pass.
3753 20:15:07.081695
3754 20:15:07.082040 CH 1, Rank 0
3755 20:15:07.084693 SW Impedance : PASS
3756 20:15:07.088123 DUTY Scan : NO K
3757 20:15:07.088684 ZQ Calibration : PASS
3758 20:15:07.091061 Jitter Meter : NO K
3759 20:15:07.094897 CBT Training : PASS
3760 20:15:07.095457 Write leveling : PASS
3761 20:15:07.097720 RX DQS gating : PASS
3762 20:15:07.101524 RX DQ/DQS(RDDQC) : PASS
3763 20:15:07.102036 TX DQ/DQS : PASS
3764 20:15:07.104012 RX DATLAT : PASS
3765 20:15:07.104481 RX DQ/DQS(Engine): PASS
3766 20:15:07.107710 TX OE : NO K
3767 20:15:07.108183 All Pass.
3768 20:15:07.108555
3769 20:15:07.110292 CH 1, Rank 1
3770 20:15:07.110759 SW Impedance : PASS
3771 20:15:07.114113 DUTY Scan : NO K
3772 20:15:07.117574 ZQ Calibration : PASS
3773 20:15:07.118041 Jitter Meter : NO K
3774 20:15:07.120636 CBT Training : PASS
3775 20:15:07.123776 Write leveling : PASS
3776 20:15:07.124344 RX DQS gating : PASS
3777 20:15:07.127093 RX DQ/DQS(RDDQC) : PASS
3778 20:15:07.130050 TX DQ/DQS : PASS
3779 20:15:07.130497 RX DATLAT : PASS
3780 20:15:07.134260 RX DQ/DQS(Engine): PASS
3781 20:15:07.137435 TX OE : NO K
3782 20:15:07.137963 All Pass.
3783 20:15:07.138307
3784 20:15:07.140375 DramC Write-DBI off
3785 20:15:07.140801 PER_BANK_REFRESH: Hybrid Mode
3786 20:15:07.143764 TX_TRACKING: ON
3787 20:15:07.150787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 20:15:07.156678 [FAST_K] Save calibration result to emmc
3789 20:15:07.160133 dramc_set_vcore_voltage set vcore to 650000
3790 20:15:07.160562 Read voltage for 600, 5
3791 20:15:07.163632 Vio18 = 0
3792 20:15:07.164208 Vcore = 650000
3793 20:15:07.164551 Vdram = 0
3794 20:15:07.166982 Vddq = 0
3795 20:15:07.167492 Vmddr = 0
3796 20:15:07.169737 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 20:15:07.176606 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 20:15:07.179824 MEM_TYPE=3, freq_sel=19
3799 20:15:07.183606 sv_algorithm_assistance_LP4_1600
3800 20:15:07.186499 ============ PULL DRAM RESETB DOWN ============
3801 20:15:07.189833 ========== PULL DRAM RESETB DOWN end =========
3802 20:15:07.196769 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 20:15:07.199866 ===================================
3804 20:15:07.200378 LPDDR4 DRAM CONFIGURATION
3805 20:15:07.203066 ===================================
3806 20:15:07.206151 EX_ROW_EN[0] = 0x0
3807 20:15:07.209631 EX_ROW_EN[1] = 0x0
3808 20:15:07.210057 LP4Y_EN = 0x0
3809 20:15:07.212911 WORK_FSP = 0x0
3810 20:15:07.213338 WL = 0x2
3811 20:15:07.216251 RL = 0x2
3812 20:15:07.216769 BL = 0x2
3813 20:15:07.219883 RPST = 0x0
3814 20:15:07.220400 RD_PRE = 0x0
3815 20:15:07.222429 WR_PRE = 0x1
3816 20:15:07.222854 WR_PST = 0x0
3817 20:15:07.226353 DBI_WR = 0x0
3818 20:15:07.226873 DBI_RD = 0x0
3819 20:15:07.229224 OTF = 0x1
3820 20:15:07.232554 ===================================
3821 20:15:07.235739 ===================================
3822 20:15:07.236172 ANA top config
3823 20:15:07.239285 ===================================
3824 20:15:07.242410 DLL_ASYNC_EN = 0
3825 20:15:07.245637 ALL_SLAVE_EN = 1
3826 20:15:07.249276 NEW_RANK_MODE = 1
3827 20:15:07.249801 DLL_IDLE_MODE = 1
3828 20:15:07.252985 LP45_APHY_COMB_EN = 1
3829 20:15:07.255571 TX_ODT_DIS = 1
3830 20:15:07.259535 NEW_8X_MODE = 1
3831 20:15:07.262516 ===================================
3832 20:15:07.265651 ===================================
3833 20:15:07.269334 data_rate = 1200
3834 20:15:07.269759 CKR = 1
3835 20:15:07.272152 DQ_P2S_RATIO = 8
3836 20:15:07.275555 ===================================
3837 20:15:07.278834 CA_P2S_RATIO = 8
3838 20:15:07.281678 DQ_CA_OPEN = 0
3839 20:15:07.285613 DQ_SEMI_OPEN = 0
3840 20:15:07.288744 CA_SEMI_OPEN = 0
3841 20:15:07.289168 CA_FULL_RATE = 0
3842 20:15:07.292027 DQ_CKDIV4_EN = 1
3843 20:15:07.295075 CA_CKDIV4_EN = 1
3844 20:15:07.299050 CA_PREDIV_EN = 0
3845 20:15:07.301811 PH8_DLY = 0
3846 20:15:07.305274 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 20:15:07.309111 DQ_AAMCK_DIV = 4
3848 20:15:07.309655 CA_AAMCK_DIV = 4
3849 20:15:07.311736 CA_ADMCK_DIV = 4
3850 20:15:07.315424 DQ_TRACK_CA_EN = 0
3851 20:15:07.318323 CA_PICK = 600
3852 20:15:07.321133 CA_MCKIO = 600
3853 20:15:07.325067 MCKIO_SEMI = 0
3854 20:15:07.327857 PLL_FREQ = 2288
3855 20:15:07.328285 DQ_UI_PI_RATIO = 32
3856 20:15:07.331759 CA_UI_PI_RATIO = 0
3857 20:15:07.334556 ===================================
3858 20:15:07.338840 ===================================
3859 20:15:07.341725 memory_type:LPDDR4
3860 20:15:07.344475 GP_NUM : 10
3861 20:15:07.344999 SRAM_EN : 1
3862 20:15:07.347867 MD32_EN : 0
3863 20:15:07.351333 ===================================
3864 20:15:07.354533 [ANA_INIT] >>>>>>>>>>>>>>
3865 20:15:07.355051 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 20:15:07.358134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 20:15:07.361855 ===================================
3868 20:15:07.364582 data_rate = 1200,PCW = 0X5800
3869 20:15:07.367894 ===================================
3870 20:15:07.370781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 20:15:07.377818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 20:15:07.384351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 20:15:07.387632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 20:15:07.390969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 20:15:07.394307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 20:15:07.397730 [ANA_INIT] flow start
3877 20:15:07.398291 [ANA_INIT] PLL >>>>>>>>
3878 20:15:07.400435 [ANA_INIT] PLL <<<<<<<<
3879 20:15:07.403900 [ANA_INIT] MIDPI >>>>>>>>
3880 20:15:07.407851 [ANA_INIT] MIDPI <<<<<<<<
3881 20:15:07.408414 [ANA_INIT] DLL >>>>>>>>
3882 20:15:07.410855 [ANA_INIT] flow end
3883 20:15:07.413908 ============ LP4 DIFF to SE enter ============
3884 20:15:07.417257 ============ LP4 DIFF to SE exit ============
3885 20:15:07.421016 [ANA_INIT] <<<<<<<<<<<<<
3886 20:15:07.423743 [Flow] Enable top DCM control >>>>>
3887 20:15:07.427793 [Flow] Enable top DCM control <<<<<
3888 20:15:07.430603 Enable DLL master slave shuffle
3889 20:15:07.437457 ==============================================================
3890 20:15:07.438021 Gating Mode config
3891 20:15:07.444075 ==============================================================
3892 20:15:07.444644 Config description:
3893 20:15:07.453668 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 20:15:07.460513 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 20:15:07.466814 SELPH_MODE 0: By rank 1: By Phase
3896 20:15:07.470029 ==============================================================
3897 20:15:07.473373 GAT_TRACK_EN = 1
3898 20:15:07.477059 RX_GATING_MODE = 2
3899 20:15:07.480311 RX_GATING_TRACK_MODE = 2
3900 20:15:07.483484 SELPH_MODE = 1
3901 20:15:07.486668 PICG_EARLY_EN = 1
3902 20:15:07.489987 VALID_LAT_VALUE = 1
3903 20:15:07.496372 ==============================================================
3904 20:15:07.499659 Enter into Gating configuration >>>>
3905 20:15:07.502696 Exit from Gating configuration <<<<
3906 20:15:07.506153 Enter into DVFS_PRE_config >>>>>
3907 20:15:07.515811 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 20:15:07.519221 Exit from DVFS_PRE_config <<<<<
3909 20:15:07.522528 Enter into PICG configuration >>>>
3910 20:15:07.525931 Exit from PICG configuration <<<<
3911 20:15:07.529014 [RX_INPUT] configuration >>>>>
3912 20:15:07.532673 [RX_INPUT] configuration <<<<<
3913 20:15:07.536092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 20:15:07.543221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 20:15:07.549188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 20:15:07.553028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 20:15:07.558806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 20:15:07.565257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 20:15:07.569014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 20:15:07.575266 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 20:15:07.579962 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 20:15:07.582777 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 20:15:07.585451 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 20:15:07.592224 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 20:15:07.595711 ===================================
3926 20:15:07.596278 LPDDR4 DRAM CONFIGURATION
3927 20:15:07.599127 ===================================
3928 20:15:07.602763 EX_ROW_EN[0] = 0x0
3929 20:15:07.605201 EX_ROW_EN[1] = 0x0
3930 20:15:07.605762 LP4Y_EN = 0x0
3931 20:15:07.608624 WORK_FSP = 0x0
3932 20:15:07.609088 WL = 0x2
3933 20:15:07.612626 RL = 0x2
3934 20:15:07.613091 BL = 0x2
3935 20:15:07.614992 RPST = 0x0
3936 20:15:07.615471 RD_PRE = 0x0
3937 20:15:07.618333 WR_PRE = 0x1
3938 20:15:07.618914 WR_PST = 0x0
3939 20:15:07.622439 DBI_WR = 0x0
3940 20:15:07.623001 DBI_RD = 0x0
3941 20:15:07.624920 OTF = 0x1
3942 20:15:07.628403 ===================================
3943 20:15:07.631730 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 20:15:07.634604 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 20:15:07.641535 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 20:15:07.645287 ===================================
3947 20:15:07.645848 LPDDR4 DRAM CONFIGURATION
3948 20:15:07.648126 ===================================
3949 20:15:07.652599 EX_ROW_EN[0] = 0x10
3950 20:15:07.654951 EX_ROW_EN[1] = 0x0
3951 20:15:07.655505 LP4Y_EN = 0x0
3952 20:15:07.658357 WORK_FSP = 0x0
3953 20:15:07.658917 WL = 0x2
3954 20:15:07.661127 RL = 0x2
3955 20:15:07.661592 BL = 0x2
3956 20:15:07.665106 RPST = 0x0
3957 20:15:07.665670 RD_PRE = 0x0
3958 20:15:07.668965 WR_PRE = 0x1
3959 20:15:07.669427 WR_PST = 0x0
3960 20:15:07.671018 DBI_WR = 0x0
3961 20:15:07.671484 DBI_RD = 0x0
3962 20:15:07.674675 OTF = 0x1
3963 20:15:07.677850 ===================================
3964 20:15:07.684628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 20:15:07.687921 nWR fixed to 30
3966 20:15:07.691728 [ModeRegInit_LP4] CH0 RK0
3967 20:15:07.692316 [ModeRegInit_LP4] CH0 RK1
3968 20:15:07.694801 [ModeRegInit_LP4] CH1 RK0
3969 20:15:07.697513 [ModeRegInit_LP4] CH1 RK1
3970 20:15:07.698078 match AC timing 17
3971 20:15:07.703814 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 20:15:07.707499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 20:15:07.710369 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 20:15:07.717602 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 20:15:07.720571 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 20:15:07.721037 ==
3977 20:15:07.723726 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 20:15:07.727310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 20:15:07.728010 ==
3980 20:15:07.734241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 20:15:07.740147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3982 20:15:07.743341 [CA 0] Center 36 (6~66) winsize 61
3983 20:15:07.747075 [CA 1] Center 36 (6~66) winsize 61
3984 20:15:07.750369 [CA 2] Center 33 (3~64) winsize 62
3985 20:15:07.753032 [CA 3] Center 34 (4~64) winsize 61
3986 20:15:07.756613 [CA 4] Center 33 (3~64) winsize 62
3987 20:15:07.760343 [CA 5] Center 33 (3~64) winsize 62
3988 20:15:07.760914
3989 20:15:07.763454 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3990 20:15:07.763959
3991 20:15:07.767067 [CATrainingPosCal] consider 1 rank data
3992 20:15:07.770329 u2DelayCellTimex100 = 270/100 ps
3993 20:15:07.773183 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 20:15:07.776771 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3995 20:15:07.779701 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 20:15:07.786557 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3997 20:15:07.789645 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 20:15:07.792810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 20:15:07.793277
4000 20:15:07.796312 CA PerBit enable=1, Macro0, CA PI delay=33
4001 20:15:07.796880
4002 20:15:07.799489 [CBTSetCACLKResult] CA Dly = 33
4003 20:15:07.800090 CS Dly: 5 (0~36)
4004 20:15:07.800468 ==
4005 20:15:07.802703 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 20:15:07.810099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 20:15:07.810668 ==
4008 20:15:07.812266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 20:15:07.819552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4010 20:15:07.822936 [CA 0] Center 36 (6~66) winsize 61
4011 20:15:07.825982 [CA 1] Center 36 (6~66) winsize 61
4012 20:15:07.829393 [CA 2] Center 34 (3~65) winsize 63
4013 20:15:07.833080 [CA 3] Center 33 (3~64) winsize 62
4014 20:15:07.837032 [CA 4] Center 33 (2~64) winsize 63
4015 20:15:07.839260 [CA 5] Center 33 (2~64) winsize 63
4016 20:15:07.839866
4017 20:15:07.842984 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4018 20:15:07.843543
4019 20:15:07.845820 [CATrainingPosCal] consider 2 rank data
4020 20:15:07.849007 u2DelayCellTimex100 = 270/100 ps
4021 20:15:07.853148 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 20:15:07.859547 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 20:15:07.862139 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 20:15:07.865801 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4025 20:15:07.869142 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 20:15:07.871834 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 20:15:07.872381
4028 20:15:07.875314 CA PerBit enable=1, Macro0, CA PI delay=33
4029 20:15:07.875828
4030 20:15:07.879087 [CBTSetCACLKResult] CA Dly = 33
4031 20:15:07.882201 CS Dly: 5 (0~37)
4032 20:15:07.882667
4033 20:15:07.885462 ----->DramcWriteLeveling(PI) begin...
4034 20:15:07.885931 ==
4035 20:15:07.888464 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 20:15:07.891719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 20:15:07.892288 ==
4038 20:15:07.895423 Write leveling (Byte 0): 33 => 33
4039 20:15:07.898109 Write leveling (Byte 1): 28 => 28
4040 20:15:07.902121 DramcWriteLeveling(PI) end<-----
4041 20:15:07.902686
4042 20:15:07.903062 ==
4043 20:15:07.905006 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 20:15:07.908819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 20:15:07.909395 ==
4046 20:15:07.911477 [Gating] SW mode calibration
4047 20:15:07.918563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 20:15:07.925280 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 20:15:07.928007 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 20:15:07.931716 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 20:15:07.938172 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 20:15:07.941209 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
4053 20:15:07.945373 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
4054 20:15:07.951367 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 20:15:07.954772 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 20:15:07.957902 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 20:15:07.964417 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 20:15:07.967513 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 20:15:07.971032 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 20:15:07.978149 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4061 20:15:07.980731 0 10 16 | B1->B0 | 3434 3f3f | 1 0 | (0 0) (0 0)
4062 20:15:07.984180 0 10 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4063 20:15:07.990936 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 20:15:07.994463 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 20:15:07.997435 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 20:15:08.003829 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 20:15:08.007914 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 20:15:08.010804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 20:15:08.017392 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 20:15:08.020976 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 20:15:08.024015 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 20:15:08.030532 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 20:15:08.033664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 20:15:08.037129 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 20:15:08.043613 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 20:15:08.046667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 20:15:08.050113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 20:15:08.056707 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 20:15:08.060489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 20:15:08.063532 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 20:15:08.070683 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 20:15:08.072859 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 20:15:08.077121 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 20:15:08.082984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4085 20:15:08.086274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4086 20:15:08.089896 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 20:15:08.092826 Total UI for P1: 0, mck2ui 16
4088 20:15:08.096557 best dqsien dly found for B0: ( 0, 13, 14)
4089 20:15:08.100075 Total UI for P1: 0, mck2ui 16
4090 20:15:08.102572 best dqsien dly found for B1: ( 0, 13, 14)
4091 20:15:08.106742 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4092 20:15:08.112758 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4093 20:15:08.113253
4094 20:15:08.116134 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4095 20:15:08.119507 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4096 20:15:08.122936 [Gating] SW calibration Done
4097 20:15:08.123453 ==
4098 20:15:08.126620 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 20:15:08.129205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 20:15:08.129725 ==
4101 20:15:08.132606 RX Vref Scan: 0
4102 20:15:08.133074
4103 20:15:08.133445 RX Vref 0 -> 0, step: 1
4104 20:15:08.133790
4105 20:15:08.136164 RX Delay -230 -> 252, step: 16
4106 20:15:08.139612 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4107 20:15:08.146090 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4108 20:15:08.149139 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4109 20:15:08.152431 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4110 20:15:08.155668 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4111 20:15:08.162104 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4112 20:15:08.165950 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4113 20:15:08.168418 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4114 20:15:08.171758 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4115 20:15:08.178852 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4116 20:15:08.182250 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4117 20:15:08.185466 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4118 20:15:08.188654 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4119 20:15:08.195150 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4120 20:15:08.199295 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4121 20:15:08.202014 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4122 20:15:08.202482 ==
4123 20:15:08.204611 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 20:15:08.208036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 20:15:08.211601 ==
4126 20:15:08.212124 DQS Delay:
4127 20:15:08.212494 DQS0 = 0, DQS1 = 0
4128 20:15:08.215127 DQM Delay:
4129 20:15:08.215590 DQM0 = 45, DQM1 = 33
4130 20:15:08.218216 DQ Delay:
4131 20:15:08.218770 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4132 20:15:08.221426 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4133 20:15:08.224877 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4134 20:15:08.227861 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4135 20:15:08.228326
4136 20:15:08.231847
4137 20:15:08.232394 ==
4138 20:15:08.234869 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 20:15:08.238822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 20:15:08.239388 ==
4141 20:15:08.239830
4142 20:15:08.240192
4143 20:15:08.241702 TX Vref Scan disable
4144 20:15:08.242163 == TX Byte 0 ==
4145 20:15:08.248072 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4146 20:15:08.251897 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4147 20:15:08.252453 == TX Byte 1 ==
4148 20:15:08.258203 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4149 20:15:08.260914 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4150 20:15:08.261399 ==
4151 20:15:08.264152 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 20:15:08.267735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 20:15:08.268301 ==
4154 20:15:08.268672
4155 20:15:08.269014
4156 20:15:08.271333 TX Vref Scan disable
4157 20:15:08.274898 == TX Byte 0 ==
4158 20:15:08.277927 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4159 20:15:08.281494 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4160 20:15:08.284295 == TX Byte 1 ==
4161 20:15:08.287635 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4162 20:15:08.294315 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4163 20:15:08.294877
4164 20:15:08.295244 [DATLAT]
4165 20:15:08.295583 Freq=600, CH0 RK0
4166 20:15:08.295985
4167 20:15:08.297637 DATLAT Default: 0x9
4168 20:15:08.298101 0, 0xFFFF, sum = 0
4169 20:15:08.301065 1, 0xFFFF, sum = 0
4170 20:15:08.304119 2, 0xFFFF, sum = 0
4171 20:15:08.304680 3, 0xFFFF, sum = 0
4172 20:15:08.308019 4, 0xFFFF, sum = 0
4173 20:15:08.308561 5, 0xFFFF, sum = 0
4174 20:15:08.310309 6, 0xFFFF, sum = 0
4175 20:15:08.310782 7, 0xFFFF, sum = 0
4176 20:15:08.313886 8, 0x0, sum = 1
4177 20:15:08.314539 9, 0x0, sum = 2
4178 20:15:08.317027 10, 0x0, sum = 3
4179 20:15:08.317506 11, 0x0, sum = 4
4180 20:15:08.317886 best_step = 9
4181 20:15:08.318227
4182 20:15:08.320676 ==
4183 20:15:08.321143 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 20:15:08.327011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 20:15:08.327495 ==
4186 20:15:08.328030 RX Vref Scan: 1
4187 20:15:08.328398
4188 20:15:08.330326 RX Vref 0 -> 0, step: 1
4189 20:15:08.330793
4190 20:15:08.334504 RX Delay -179 -> 252, step: 8
4191 20:15:08.334927
4192 20:15:08.337525 Set Vref, RX VrefLevel [Byte0]: 60
4193 20:15:08.340247 [Byte1]: 59
4194 20:15:08.340673
4195 20:15:08.343586 Final RX Vref Byte 0 = 60 to rank0
4196 20:15:08.346804 Final RX Vref Byte 1 = 59 to rank0
4197 20:15:08.350054 Final RX Vref Byte 0 = 60 to rank1
4198 20:15:08.353344 Final RX Vref Byte 1 = 59 to rank1==
4199 20:15:08.356473 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 20:15:08.360197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 20:15:08.363134 ==
4202 20:15:08.363561 DQS Delay:
4203 20:15:08.363950 DQS0 = 0, DQS1 = 0
4204 20:15:08.366388 DQM Delay:
4205 20:15:08.366810 DQM0 = 44, DQM1 = 32
4206 20:15:08.369917 DQ Delay:
4207 20:15:08.372822 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4208 20:15:08.373249 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4209 20:15:08.376302 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4210 20:15:08.379953 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4211 20:15:08.382936
4212 20:15:08.383451
4213 20:15:08.389511 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4214 20:15:08.392966 CH0 RK0: MR19=808, MR18=5F36
4215 20:15:08.399429 CH0_RK0: MR19=0x808, MR18=0x5F36, DQSOSC=391, MR23=63, INC=171, DEC=114
4216 20:15:08.399997
4217 20:15:08.403428 ----->DramcWriteLeveling(PI) begin...
4218 20:15:08.404020 ==
4219 20:15:08.407134 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 20:15:08.409599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 20:15:08.410042 ==
4222 20:15:08.412860 Write leveling (Byte 0): 32 => 32
4223 20:15:08.416130 Write leveling (Byte 1): 31 => 31
4224 20:15:08.419280 DramcWriteLeveling(PI) end<-----
4225 20:15:08.419722
4226 20:15:08.420080 ==
4227 20:15:08.422336 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 20:15:08.426755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 20:15:08.427281 ==
4230 20:15:08.429463 [Gating] SW mode calibration
4231 20:15:08.436140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 20:15:08.442107 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 20:15:08.445999 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 20:15:08.452486 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 20:15:08.455553 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 20:15:08.459403 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4237 20:15:08.465643 0 9 16 | B1->B0 | 2525 2a2a | 0 0 | (1 0) (1 1)
4238 20:15:08.468591 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 20:15:08.472376 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 20:15:08.478367 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 20:15:08.481926 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 20:15:08.485627 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 20:15:08.492170 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 20:15:08.495284 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 20:15:08.499106 0 10 16 | B1->B0 | 3c3c 3d3d | 0 0 | (0 0) (0 0)
4246 20:15:08.504775 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 20:15:08.508352 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 20:15:08.511295 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 20:15:08.517830 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 20:15:08.521874 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 20:15:08.525407 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 20:15:08.531579 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 20:15:08.535078 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 20:15:08.538133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 20:15:08.544151 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 20:15:08.547761 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 20:15:08.551603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 20:15:08.557783 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 20:15:08.561042 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 20:15:08.564947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 20:15:08.571860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 20:15:08.573883 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 20:15:08.577791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 20:15:08.584038 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 20:15:08.587790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 20:15:08.591340 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 20:15:08.597811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 20:15:08.600353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 20:15:08.604247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 20:15:08.606825 Total UI for P1: 0, mck2ui 16
4271 20:15:08.610806 best dqsien dly found for B0: ( 0, 13, 14)
4272 20:15:08.613872 Total UI for P1: 0, mck2ui 16
4273 20:15:08.616695 best dqsien dly found for B1: ( 0, 13, 14)
4274 20:15:08.620181 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4275 20:15:08.623368 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4276 20:15:08.627198
4277 20:15:08.629925 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4278 20:15:08.633686 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 20:15:08.636398 [Gating] SW calibration Done
4280 20:15:08.636866 ==
4281 20:15:08.639850 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 20:15:08.643857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 20:15:08.644418 ==
4284 20:15:08.644789 RX Vref Scan: 0
4285 20:15:08.646880
4286 20:15:08.647447 RX Vref 0 -> 0, step: 1
4287 20:15:08.647866
4288 20:15:08.650171 RX Delay -230 -> 252, step: 16
4289 20:15:08.653518 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4290 20:15:08.659616 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4291 20:15:08.662967 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4292 20:15:08.666906 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4293 20:15:08.670457 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4294 20:15:08.673127 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4295 20:15:08.679702 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4296 20:15:08.683071 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4297 20:15:08.685707 iDelay=218, Bit 8, Center 33 (-134 ~ 201) 336
4298 20:15:08.688798 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4299 20:15:08.696632 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4300 20:15:08.699001 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4301 20:15:08.702602 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4302 20:15:08.706150 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4303 20:15:08.712288 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4304 20:15:08.715406 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4305 20:15:08.715911 ==
4306 20:15:08.719280 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 20:15:08.722435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 20:15:08.723007 ==
4309 20:15:08.725597 DQS Delay:
4310 20:15:08.726062 DQS0 = 0, DQS1 = 0
4311 20:15:08.729866 DQM Delay:
4312 20:15:08.730424 DQM0 = 41, DQM1 = 37
4313 20:15:08.730800 DQ Delay:
4314 20:15:08.732116 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4315 20:15:08.735781 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4316 20:15:08.738629 DQ8 =33, DQ9 =25, DQ10 =33, DQ11 =33
4317 20:15:08.742300 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4318 20:15:08.742863
4319 20:15:08.743231
4320 20:15:08.743571 ==
4321 20:15:08.745364 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 20:15:08.752497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 20:15:08.753073 ==
4324 20:15:08.753449
4325 20:15:08.753792
4326 20:15:08.755127 TX Vref Scan disable
4327 20:15:08.755588 == TX Byte 0 ==
4328 20:15:08.758873 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4329 20:15:08.765083 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4330 20:15:08.765546 == TX Byte 1 ==
4331 20:15:08.771536 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4332 20:15:08.775010 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4333 20:15:08.775450 ==
4334 20:15:08.778580 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 20:15:08.782200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 20:15:08.782622 ==
4337 20:15:08.783028
4338 20:15:08.783339
4339 20:15:08.785101 TX Vref Scan disable
4340 20:15:08.788256 == TX Byte 0 ==
4341 20:15:08.792626 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4342 20:15:08.795027 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4343 20:15:08.798212 == TX Byte 1 ==
4344 20:15:08.801660 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4345 20:15:08.804522 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4346 20:15:08.805080
4347 20:15:08.807454 [DATLAT]
4348 20:15:08.807966 Freq=600, CH0 RK1
4349 20:15:08.808304
4350 20:15:08.810790 DATLAT Default: 0x9
4351 20:15:08.811202 0, 0xFFFF, sum = 0
4352 20:15:08.814643 1, 0xFFFF, sum = 0
4353 20:15:08.815068 2, 0xFFFF, sum = 0
4354 20:15:08.817603 3, 0xFFFF, sum = 0
4355 20:15:08.818038 4, 0xFFFF, sum = 0
4356 20:15:08.820622 5, 0xFFFF, sum = 0
4357 20:15:08.823988 6, 0xFFFF, sum = 0
4358 20:15:08.824412 7, 0xFFFF, sum = 0
4359 20:15:08.824747 8, 0x0, sum = 1
4360 20:15:08.827735 9, 0x0, sum = 2
4361 20:15:08.828176 10, 0x0, sum = 3
4362 20:15:08.830676 11, 0x0, sum = 4
4363 20:15:08.831378 best_step = 9
4364 20:15:08.832020
4365 20:15:08.832607 ==
4366 20:15:08.833894 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 20:15:08.840663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 20:15:08.841045 ==
4369 20:15:08.841382 RX Vref Scan: 0
4370 20:15:08.841703
4371 20:15:08.843718 RX Vref 0 -> 0, step: 1
4372 20:15:08.843912
4373 20:15:08.847197 RX Delay -179 -> 252, step: 8
4374 20:15:08.850315 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4375 20:15:08.857367 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4376 20:15:08.860973 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4377 20:15:08.863982 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4378 20:15:08.867053 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4379 20:15:08.873504 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4380 20:15:08.877008 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4381 20:15:08.880559 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4382 20:15:08.883716 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4383 20:15:08.887431 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4384 20:15:08.893303 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4385 20:15:08.897035 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4386 20:15:08.900294 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4387 20:15:08.903800 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4388 20:15:08.910016 iDelay=205, Bit 14, Center 52 (-99 ~ 204) 304
4389 20:15:08.913825 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4390 20:15:08.914381 ==
4391 20:15:08.916814 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 20:15:08.919560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 20:15:08.920051 ==
4394 20:15:08.923805 DQS Delay:
4395 20:15:08.924356 DQS0 = 0, DQS1 = 0
4396 20:15:08.926429 DQM Delay:
4397 20:15:08.926885 DQM0 = 42, DQM1 = 37
4398 20:15:08.927249 DQ Delay:
4399 20:15:08.929538 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4400 20:15:08.933065 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4401 20:15:08.936144 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4402 20:15:08.939834 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =44
4403 20:15:08.940383
4404 20:15:08.940747
4405 20:15:08.949696 [DQSOSCAuto] RK1, (LSB)MR18= 0x550a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
4406 20:15:08.952583 CH0 RK1: MR19=808, MR18=550A
4407 20:15:08.959346 CH0_RK1: MR19=0x808, MR18=0x550A, DQSOSC=393, MR23=63, INC=169, DEC=113
4408 20:15:08.962876 [RxdqsGatingPostProcess] freq 600
4409 20:15:08.966080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4410 20:15:08.969617 Pre-setting of DQS Precalculation
4411 20:15:08.975972 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4412 20:15:08.976448 ==
4413 20:15:08.979185 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 20:15:08.982645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 20:15:08.983211 ==
4416 20:15:08.989268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 20:15:08.992295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4418 20:15:08.996484 [CA 0] Center 35 (5~66) winsize 62
4419 20:15:09.000326 [CA 1] Center 35 (5~66) winsize 62
4420 20:15:09.003037 [CA 2] Center 34 (4~65) winsize 62
4421 20:15:09.006370 [CA 3] Center 33 (3~64) winsize 62
4422 20:15:09.009420 [CA 4] Center 34 (4~64) winsize 61
4423 20:15:09.013318 [CA 5] Center 33 (3~64) winsize 62
4424 20:15:09.013878
4425 20:15:09.016333 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4426 20:15:09.016903
4427 20:15:09.019435 [CATrainingPosCal] consider 1 rank data
4428 20:15:09.022651 u2DelayCellTimex100 = 270/100 ps
4429 20:15:09.029511 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 20:15:09.032409 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 20:15:09.035745 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 20:15:09.039285 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 20:15:09.042973 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4434 20:15:09.045747 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 20:15:09.046309
4436 20:15:09.049010 CA PerBit enable=1, Macro0, CA PI delay=33
4437 20:15:09.049475
4438 20:15:09.052866 [CBTSetCACLKResult] CA Dly = 33
4439 20:15:09.055835 CS Dly: 5 (0~36)
4440 20:15:09.056396 ==
4441 20:15:09.058866 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 20:15:09.062013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 20:15:09.062498 ==
4444 20:15:09.068686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 20:15:09.075406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4446 20:15:09.078287 [CA 0] Center 35 (5~66) winsize 62
4447 20:15:09.081908 [CA 1] Center 36 (6~66) winsize 61
4448 20:15:09.085535 [CA 2] Center 34 (4~65) winsize 62
4449 20:15:09.088401 [CA 3] Center 34 (4~65) winsize 62
4450 20:15:09.092289 [CA 4] Center 34 (3~65) winsize 63
4451 20:15:09.094962 [CA 5] Center 34 (3~65) winsize 63
4452 20:15:09.095427
4453 20:15:09.098151 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4454 20:15:09.098710
4455 20:15:09.102151 [CATrainingPosCal] consider 2 rank data
4456 20:15:09.104506 u2DelayCellTimex100 = 270/100 ps
4457 20:15:09.108134 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 20:15:09.110987 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 20:15:09.114431 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 20:15:09.117924 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4461 20:15:09.121251 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4462 20:15:09.124790 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 20:15:09.125254
4464 20:15:09.130730 CA PerBit enable=1, Macro0, CA PI delay=33
4465 20:15:09.131541
4466 20:15:09.134765 [CBTSetCACLKResult] CA Dly = 33
4467 20:15:09.135516 CS Dly: 6 (0~38)
4468 20:15:09.136252
4469 20:15:09.137687 ----->DramcWriteLeveling(PI) begin...
4470 20:15:09.138429 ==
4471 20:15:09.141194 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 20:15:09.143975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 20:15:09.148227 ==
4474 20:15:09.148645 Write leveling (Byte 0): 29 => 29
4475 20:15:09.151139 Write leveling (Byte 1): 29 => 29
4476 20:15:09.154617 DramcWriteLeveling(PI) end<-----
4477 20:15:09.155157
4478 20:15:09.155503 ==
4479 20:15:09.157607 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 20:15:09.164261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 20:15:09.164694 ==
4482 20:15:09.165031 [Gating] SW mode calibration
4483 20:15:09.174584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4484 20:15:09.177576 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4485 20:15:09.180479 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 20:15:09.187626 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 20:15:09.190984 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4488 20:15:09.193832 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 0)
4489 20:15:09.200575 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 20:15:09.204055 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 20:15:09.207174 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 20:15:09.214289 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 20:15:09.217114 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 20:15:09.220108 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 20:15:09.227052 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4496 20:15:09.231153 0 10 12 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (0 0)
4497 20:15:09.236890 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 20:15:09.240266 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 20:15:09.243592 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 20:15:09.250552 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 20:15:09.253378 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 20:15:09.256301 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 20:15:09.263450 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 20:15:09.266303 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 20:15:09.270206 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 20:15:09.276139 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 20:15:09.279354 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 20:15:09.283168 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 20:15:09.289799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 20:15:09.292728 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 20:15:09.296111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 20:15:09.303358 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 20:15:09.306361 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 20:15:09.309321 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 20:15:09.315452 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 20:15:09.318806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 20:15:09.322105 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 20:15:09.329485 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 20:15:09.332069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 20:15:09.336415 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 20:15:09.339103 Total UI for P1: 0, mck2ui 16
4522 20:15:09.342408 best dqsien dly found for B0: ( 0, 13, 10)
4523 20:15:09.345638 Total UI for P1: 0, mck2ui 16
4524 20:15:09.348377 best dqsien dly found for B1: ( 0, 13, 10)
4525 20:15:09.352327 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4526 20:15:09.355223 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4527 20:15:09.355835
4528 20:15:09.361662 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4529 20:15:09.364927 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4530 20:15:09.368980 [Gating] SW calibration Done
4531 20:15:09.369548 ==
4532 20:15:09.371660 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 20:15:09.375027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 20:15:09.375491 ==
4535 20:15:09.376000 RX Vref Scan: 0
4536 20:15:09.376386
4537 20:15:09.378039 RX Vref 0 -> 0, step: 1
4538 20:15:09.378499
4539 20:15:09.381456 RX Delay -230 -> 252, step: 16
4540 20:15:09.385340 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4541 20:15:09.391919 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4542 20:15:09.394381 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4543 20:15:09.398225 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4544 20:15:09.401358 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4545 20:15:09.404271 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4546 20:15:09.411345 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4547 20:15:09.414651 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4548 20:15:09.418299 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4549 20:15:09.420974 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4550 20:15:09.427337 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4551 20:15:09.430607 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4552 20:15:09.434085 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4553 20:15:09.437748 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4554 20:15:09.443981 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4555 20:15:09.447888 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4556 20:15:09.448454 ==
4557 20:15:09.450477 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 20:15:09.453865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 20:15:09.454436 ==
4560 20:15:09.457170 DQS Delay:
4561 20:15:09.457738 DQS0 = 0, DQS1 = 0
4562 20:15:09.458115 DQM Delay:
4563 20:15:09.460248 DQM0 = 47, DQM1 = 39
4564 20:15:09.460710 DQ Delay:
4565 20:15:09.463824 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4566 20:15:09.467046 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4567 20:15:09.471153 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4568 20:15:09.473427 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4569 20:15:09.473890
4570 20:15:09.474257
4571 20:15:09.474596 ==
4572 20:15:09.477049 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 20:15:09.483353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 20:15:09.483867 ==
4575 20:15:09.484243
4576 20:15:09.484587
4577 20:15:09.486946 TX Vref Scan disable
4578 20:15:09.487511 == TX Byte 0 ==
4579 20:15:09.493451 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4580 20:15:09.496966 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4581 20:15:09.497430 == TX Byte 1 ==
4582 20:15:09.503656 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 20:15:09.506628 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 20:15:09.507200 ==
4585 20:15:09.510090 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 20:15:09.512995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 20:15:09.513655 ==
4588 20:15:09.514050
4589 20:15:09.514388
4590 20:15:09.516058 TX Vref Scan disable
4591 20:15:09.519644 == TX Byte 0 ==
4592 20:15:09.522983 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4593 20:15:09.526285 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4594 20:15:09.529297 == TX Byte 1 ==
4595 20:15:09.533174 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4596 20:15:09.536004 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4597 20:15:09.536588
4598 20:15:09.540386 [DATLAT]
4599 20:15:09.540943 Freq=600, CH1 RK0
4600 20:15:09.541310
4601 20:15:09.542849 DATLAT Default: 0x9
4602 20:15:09.543310 0, 0xFFFF, sum = 0
4603 20:15:09.546770 1, 0xFFFF, sum = 0
4604 20:15:09.547335 2, 0xFFFF, sum = 0
4605 20:15:09.548849 3, 0xFFFF, sum = 0
4606 20:15:09.549317 4, 0xFFFF, sum = 0
4607 20:15:09.553288 5, 0xFFFF, sum = 0
4608 20:15:09.554001 6, 0xFFFF, sum = 0
4609 20:15:09.556124 7, 0xFFFF, sum = 0
4610 20:15:09.556693 8, 0x0, sum = 1
4611 20:15:09.559234 9, 0x0, sum = 2
4612 20:15:09.559722 10, 0x0, sum = 3
4613 20:15:09.562728 11, 0x0, sum = 4
4614 20:15:09.563190 best_step = 9
4615 20:15:09.563554
4616 20:15:09.563934 ==
4617 20:15:09.565531 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 20:15:09.572770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 20:15:09.573365 ==
4620 20:15:09.573734 RX Vref Scan: 1
4621 20:15:09.574071
4622 20:15:09.575489 RX Vref 0 -> 0, step: 1
4623 20:15:09.576001
4624 20:15:09.578795 RX Delay -195 -> 252, step: 8
4625 20:15:09.579256
4626 20:15:09.581997 Set Vref, RX VrefLevel [Byte0]: 48
4627 20:15:09.585621 [Byte1]: 59
4628 20:15:09.586193
4629 20:15:09.588709 Final RX Vref Byte 0 = 48 to rank0
4630 20:15:09.592062 Final RX Vref Byte 1 = 59 to rank0
4631 20:15:09.595334 Final RX Vref Byte 0 = 48 to rank1
4632 20:15:09.599097 Final RX Vref Byte 1 = 59 to rank1==
4633 20:15:09.602022 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 20:15:09.606121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 20:15:09.606713 ==
4636 20:15:09.608600 DQS Delay:
4637 20:15:09.609062 DQS0 = 0, DQS1 = 0
4638 20:15:09.611985 DQM Delay:
4639 20:15:09.612445 DQM0 = 48, DQM1 = 38
4640 20:15:09.612814 DQ Delay:
4641 20:15:09.615069 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4642 20:15:09.618626 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4643 20:15:09.621551 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4644 20:15:09.624914 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4645 20:15:09.625377
4646 20:15:09.625746
4647 20:15:09.634909 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4648 20:15:09.638503 CH1 RK0: MR19=808, MR18=4B30
4649 20:15:09.644669 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4650 20:15:09.645238
4651 20:15:09.647804 ----->DramcWriteLeveling(PI) begin...
4652 20:15:09.648326 ==
4653 20:15:09.651516 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 20:15:09.654784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 20:15:09.655355 ==
4656 20:15:09.658523 Write leveling (Byte 0): 30 => 30
4657 20:15:09.661276 Write leveling (Byte 1): 27 => 27
4658 20:15:09.664594 DramcWriteLeveling(PI) end<-----
4659 20:15:09.665159
4660 20:15:09.665529 ==
4661 20:15:09.667528 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 20:15:09.671315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 20:15:09.671964 ==
4664 20:15:09.674160 [Gating] SW mode calibration
4665 20:15:09.680701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4666 20:15:09.688247 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4667 20:15:09.691027 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 20:15:09.697275 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 20:15:09.701269 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 20:15:09.704778 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (0 1) (0 1)
4671 20:15:09.711887 0 9 16 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4672 20:15:09.714007 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 20:15:09.716990 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 20:15:09.723252 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 20:15:09.727261 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 20:15:09.730698 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 20:15:09.736757 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 20:15:09.740175 0 10 12 | B1->B0 | 3636 2a29 | 0 1 | (0 0) (1 1)
4679 20:15:09.743840 0 10 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
4680 20:15:09.749812 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 20:15:09.752943 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 20:15:09.756950 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 20:15:09.763237 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 20:15:09.766344 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 20:15:09.769922 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 20:15:09.776392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4687 20:15:09.779609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 20:15:09.782987 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 20:15:09.789823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 20:15:09.793088 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 20:15:09.795989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 20:15:09.803385 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 20:15:09.806282 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 20:15:09.808861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 20:15:09.816250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 20:15:09.818718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 20:15:09.822698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 20:15:09.828850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 20:15:09.832654 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 20:15:09.835720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 20:15:09.842532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 20:15:09.845786 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4703 20:15:09.849101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 20:15:09.853985 Total UI for P1: 0, mck2ui 16
4705 20:15:09.855205 best dqsien dly found for B0: ( 0, 13, 14)
4706 20:15:09.858571 Total UI for P1: 0, mck2ui 16
4707 20:15:09.861924 best dqsien dly found for B1: ( 0, 13, 12)
4708 20:15:09.865216 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4709 20:15:09.868470 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4710 20:15:09.868894
4711 20:15:09.875555 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4712 20:15:09.878445 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4713 20:15:09.878866 [Gating] SW calibration Done
4714 20:15:09.881920 ==
4715 20:15:09.885470 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 20:15:09.888738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 20:15:09.889276 ==
4718 20:15:09.889619 RX Vref Scan: 0
4719 20:15:09.889929
4720 20:15:09.891791 RX Vref 0 -> 0, step: 1
4721 20:15:09.892339
4722 20:15:09.895188 RX Delay -230 -> 252, step: 16
4723 20:15:09.898344 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4724 20:15:09.901353 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4725 20:15:09.908661 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4726 20:15:09.911321 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4727 20:15:09.914690 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4728 20:15:09.917991 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4729 20:15:09.924253 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4730 20:15:09.927852 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4731 20:15:09.931226 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4732 20:15:09.934267 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4733 20:15:09.941268 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4734 20:15:09.944509 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4735 20:15:09.947227 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4736 20:15:09.950955 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4737 20:15:09.957022 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4738 20:15:09.960604 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4739 20:15:09.961180 ==
4740 20:15:09.964166 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 20:15:09.967424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 20:15:09.967924 ==
4743 20:15:09.970536 DQS Delay:
4744 20:15:09.971103 DQS0 = 0, DQS1 = 0
4745 20:15:09.971479 DQM Delay:
4746 20:15:09.973771 DQM0 = 43, DQM1 = 37
4747 20:15:09.974236 DQ Delay:
4748 20:15:09.977098 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4749 20:15:09.980465 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4750 20:15:09.984230 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4751 20:15:09.986880 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4752 20:15:09.987348
4753 20:15:09.987769
4754 20:15:09.988132 ==
4755 20:15:09.990802 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 20:15:09.997248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 20:15:09.997719 ==
4758 20:15:09.998093
4759 20:15:09.998436
4760 20:15:09.999981 TX Vref Scan disable
4761 20:15:10.000506 == TX Byte 0 ==
4762 20:15:10.003280 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4763 20:15:10.010114 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4764 20:15:10.010700 == TX Byte 1 ==
4765 20:15:10.013462 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4766 20:15:10.020530 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4767 20:15:10.021184 ==
4768 20:15:10.023269 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 20:15:10.026507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 20:15:10.026978 ==
4771 20:15:10.027348
4772 20:15:10.027746
4773 20:15:10.029611 TX Vref Scan disable
4774 20:15:10.033015 == TX Byte 0 ==
4775 20:15:10.036904 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4776 20:15:10.040038 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4777 20:15:10.042984 == TX Byte 1 ==
4778 20:15:10.045875 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4779 20:15:10.050371 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4780 20:15:10.053083
4781 20:15:10.053606 [DATLAT]
4782 20:15:10.053949 Freq=600, CH1 RK1
4783 20:15:10.054265
4784 20:15:10.056462 DATLAT Default: 0x9
4785 20:15:10.056989 0, 0xFFFF, sum = 0
4786 20:15:10.059829 1, 0xFFFF, sum = 0
4787 20:15:10.060362 2, 0xFFFF, sum = 0
4788 20:15:10.063006 3, 0xFFFF, sum = 0
4789 20:15:10.063534 4, 0xFFFF, sum = 0
4790 20:15:10.065851 5, 0xFFFF, sum = 0
4791 20:15:10.069331 6, 0xFFFF, sum = 0
4792 20:15:10.069864 7, 0xFFFF, sum = 0
4793 20:15:10.072806 8, 0x0, sum = 1
4794 20:15:10.073231 9, 0x0, sum = 2
4795 20:15:10.073585 10, 0x0, sum = 3
4796 20:15:10.076117 11, 0x0, sum = 4
4797 20:15:10.076540 best_step = 9
4798 20:15:10.076872
4799 20:15:10.077184 ==
4800 20:15:10.079248 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 20:15:10.085497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 20:15:10.085987 ==
4803 20:15:10.086358 RX Vref Scan: 0
4804 20:15:10.086723
4805 20:15:10.088656 RX Vref 0 -> 0, step: 1
4806 20:15:10.089124
4807 20:15:10.092099 RX Delay -195 -> 252, step: 8
4808 20:15:10.096190 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4809 20:15:10.101940 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4810 20:15:10.105460 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4811 20:15:10.108673 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4812 20:15:10.112172 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4813 20:15:10.119008 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4814 20:15:10.122514 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4815 20:15:10.124813 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4816 20:15:10.128475 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4817 20:15:10.135570 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4818 20:15:10.138516 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4819 20:15:10.141796 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4820 20:15:10.144629 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4821 20:15:10.151952 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4822 20:15:10.154843 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4823 20:15:10.158153 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4824 20:15:10.158719 ==
4825 20:15:10.161802 Dram Type= 6, Freq= 0, CH_1, rank 1
4826 20:15:10.164607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4827 20:15:10.165182 ==
4828 20:15:10.168447 DQS Delay:
4829 20:15:10.169014 DQS0 = 0, DQS1 = 0
4830 20:15:10.171278 DQM Delay:
4831 20:15:10.171774 DQM0 = 45, DQM1 = 37
4832 20:15:10.172152 DQ Delay:
4833 20:15:10.174585 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4834 20:15:10.177580 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4835 20:15:10.181189 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4836 20:15:10.184690 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4837 20:15:10.185266
4838 20:15:10.187431
4839 20:15:10.194320 [DQSOSCAuto] RK1, (LSB)MR18= 0x2418, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
4840 20:15:10.197031 CH1 RK1: MR19=808, MR18=2418
4841 20:15:10.203845 CH1_RK1: MR19=0x808, MR18=0x2418, DQSOSC=403, MR23=63, INC=161, DEC=107
4842 20:15:10.207139 [RxdqsGatingPostProcess] freq 600
4843 20:15:10.210557 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4844 20:15:10.213627 Pre-setting of DQS Precalculation
4845 20:15:10.220494 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4846 20:15:10.227233 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4847 20:15:10.234575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4848 20:15:10.234998
4849 20:15:10.235329
4850 20:15:10.237108 [Calibration Summary] 1200 Mbps
4851 20:15:10.237637 CH 0, Rank 0
4852 20:15:10.240169 SW Impedance : PASS
4853 20:15:10.243837 DUTY Scan : NO K
4854 20:15:10.244264 ZQ Calibration : PASS
4855 20:15:10.247292 Jitter Meter : NO K
4856 20:15:10.250937 CBT Training : PASS
4857 20:15:10.251477 Write leveling : PASS
4858 20:15:10.254149 RX DQS gating : PASS
4859 20:15:10.257104 RX DQ/DQS(RDDQC) : PASS
4860 20:15:10.257731 TX DQ/DQS : PASS
4861 20:15:10.260660 RX DATLAT : PASS
4862 20:15:10.261092 RX DQ/DQS(Engine): PASS
4863 20:15:10.263432 TX OE : NO K
4864 20:15:10.263923 All Pass.
4865 20:15:10.264267
4866 20:15:10.267023 CH 0, Rank 1
4867 20:15:10.267444 SW Impedance : PASS
4868 20:15:10.270202 DUTY Scan : NO K
4869 20:15:10.273467 ZQ Calibration : PASS
4870 20:15:10.273891 Jitter Meter : NO K
4871 20:15:10.277177 CBT Training : PASS
4872 20:15:10.280250 Write leveling : PASS
4873 20:15:10.280799 RX DQS gating : PASS
4874 20:15:10.283402 RX DQ/DQS(RDDQC) : PASS
4875 20:15:10.286711 TX DQ/DQS : PASS
4876 20:15:10.287238 RX DATLAT : PASS
4877 20:15:10.290153 RX DQ/DQS(Engine): PASS
4878 20:15:10.293298 TX OE : NO K
4879 20:15:10.293720 All Pass.
4880 20:15:10.294057
4881 20:15:10.294368 CH 1, Rank 0
4882 20:15:10.296508 SW Impedance : PASS
4883 20:15:10.299766 DUTY Scan : NO K
4884 20:15:10.300292 ZQ Calibration : PASS
4885 20:15:10.302975 Jitter Meter : NO K
4886 20:15:10.306663 CBT Training : PASS
4887 20:15:10.307229 Write leveling : PASS
4888 20:15:10.310336 RX DQS gating : PASS
4889 20:15:10.313038 RX DQ/DQS(RDDQC) : PASS
4890 20:15:10.313505 TX DQ/DQS : PASS
4891 20:15:10.316373 RX DATLAT : PASS
4892 20:15:10.319430 RX DQ/DQS(Engine): PASS
4893 20:15:10.320167 TX OE : NO K
4894 20:15:10.322684 All Pass.
4895 20:15:10.323139
4896 20:15:10.323508 CH 1, Rank 1
4897 20:15:10.326190 SW Impedance : PASS
4898 20:15:10.326674 DUTY Scan : NO K
4899 20:15:10.329875 ZQ Calibration : PASS
4900 20:15:10.333038 Jitter Meter : NO K
4901 20:15:10.333502 CBT Training : PASS
4902 20:15:10.336017 Write leveling : PASS
4903 20:15:10.338984 RX DQS gating : PASS
4904 20:15:10.339448 RX DQ/DQS(RDDQC) : PASS
4905 20:15:10.342080 TX DQ/DQS : PASS
4906 20:15:10.345569 RX DATLAT : PASS
4907 20:15:10.346005 RX DQ/DQS(Engine): PASS
4908 20:15:10.348795 TX OE : NO K
4909 20:15:10.349215 All Pass.
4910 20:15:10.349551
4911 20:15:10.352199 DramC Write-DBI off
4912 20:15:10.355566 PER_BANK_REFRESH: Hybrid Mode
4913 20:15:10.356186 TX_TRACKING: ON
4914 20:15:10.365802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4915 20:15:10.369223 [FAST_K] Save calibration result to emmc
4916 20:15:10.371994 dramc_set_vcore_voltage set vcore to 662500
4917 20:15:10.375485 Read voltage for 933, 3
4918 20:15:10.376037 Vio18 = 0
4919 20:15:10.376414 Vcore = 662500
4920 20:15:10.379123 Vdram = 0
4921 20:15:10.379743 Vddq = 0
4922 20:15:10.380136 Vmddr = 0
4923 20:15:10.385033 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4924 20:15:10.388948 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4925 20:15:10.392044 MEM_TYPE=3, freq_sel=17
4926 20:15:10.395295 sv_algorithm_assistance_LP4_1600
4927 20:15:10.398190 ============ PULL DRAM RESETB DOWN ============
4928 20:15:10.401612 ========== PULL DRAM RESETB DOWN end =========
4929 20:15:10.408528 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4930 20:15:10.411282 ===================================
4931 20:15:10.414385 LPDDR4 DRAM CONFIGURATION
4932 20:15:10.417860 ===================================
4933 20:15:10.418335 EX_ROW_EN[0] = 0x0
4934 20:15:10.421222 EX_ROW_EN[1] = 0x0
4935 20:15:10.421686 LP4Y_EN = 0x0
4936 20:15:10.424104 WORK_FSP = 0x0
4937 20:15:10.424571 WL = 0x3
4938 20:15:10.427637 RL = 0x3
4939 20:15:10.428366 BL = 0x2
4940 20:15:10.431186 RPST = 0x0
4941 20:15:10.431649 RD_PRE = 0x0
4942 20:15:10.434534 WR_PRE = 0x1
4943 20:15:10.435100 WR_PST = 0x0
4944 20:15:10.438010 DBI_WR = 0x0
4945 20:15:10.441121 DBI_RD = 0x0
4946 20:15:10.441593 OTF = 0x1
4947 20:15:10.444048 ===================================
4948 20:15:10.447428 ===================================
4949 20:15:10.447940 ANA top config
4950 20:15:10.453954 ===================================
4951 20:15:10.454508 DLL_ASYNC_EN = 0
4952 20:15:10.457740 ALL_SLAVE_EN = 1
4953 20:15:10.460848 NEW_RANK_MODE = 1
4954 20:15:10.463565 DLL_IDLE_MODE = 1
4955 20:15:10.464087 LP45_APHY_COMB_EN = 1
4956 20:15:10.467159 TX_ODT_DIS = 1
4957 20:15:10.470539 NEW_8X_MODE = 1
4958 20:15:10.474366 ===================================
4959 20:15:10.477198 ===================================
4960 20:15:10.480203 data_rate = 1866
4961 20:15:10.483640 CKR = 1
4962 20:15:10.487153 DQ_P2S_RATIO = 8
4963 20:15:10.490210 ===================================
4964 20:15:10.490742 CA_P2S_RATIO = 8
4965 20:15:10.493262 DQ_CA_OPEN = 0
4966 20:15:10.496776 DQ_SEMI_OPEN = 0
4967 20:15:10.500801 CA_SEMI_OPEN = 0
4968 20:15:10.503733 CA_FULL_RATE = 0
4969 20:15:10.506386 DQ_CKDIV4_EN = 1
4970 20:15:10.506812 CA_CKDIV4_EN = 1
4971 20:15:10.510313 CA_PREDIV_EN = 0
4972 20:15:10.513586 PH8_DLY = 0
4973 20:15:10.517010 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4974 20:15:10.520814 DQ_AAMCK_DIV = 4
4975 20:15:10.523792 CA_AAMCK_DIV = 4
4976 20:15:10.524320 CA_ADMCK_DIV = 4
4977 20:15:10.526217 DQ_TRACK_CA_EN = 0
4978 20:15:10.530280 CA_PICK = 933
4979 20:15:10.533303 CA_MCKIO = 933
4980 20:15:10.536379 MCKIO_SEMI = 0
4981 20:15:10.539914 PLL_FREQ = 3732
4982 20:15:10.543056 DQ_UI_PI_RATIO = 32
4983 20:15:10.546498 CA_UI_PI_RATIO = 0
4984 20:15:10.549291 ===================================
4985 20:15:10.553282 ===================================
4986 20:15:10.553824 memory_type:LPDDR4
4987 20:15:10.556141 GP_NUM : 10
4988 20:15:10.559031 SRAM_EN : 1
4989 20:15:10.559561 MD32_EN : 0
4990 20:15:10.562534 ===================================
4991 20:15:10.565844 [ANA_INIT] >>>>>>>>>>>>>>
4992 20:15:10.569200 <<<<<< [CONFIGURE PHASE]: ANA_TX
4993 20:15:10.572963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4994 20:15:10.575474 ===================================
4995 20:15:10.578379 data_rate = 1866,PCW = 0X8f00
4996 20:15:10.582628 ===================================
4997 20:15:10.585747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4998 20:15:10.589559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 20:15:10.595530 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 20:15:10.598706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5001 20:15:10.602213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5002 20:15:10.608384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5003 20:15:10.608923 [ANA_INIT] flow start
5004 20:15:10.611513 [ANA_INIT] PLL >>>>>>>>
5005 20:15:10.615550 [ANA_INIT] PLL <<<<<<<<
5006 20:15:10.616065 [ANA_INIT] MIDPI >>>>>>>>
5007 20:15:10.618753 [ANA_INIT] MIDPI <<<<<<<<
5008 20:15:10.622043 [ANA_INIT] DLL >>>>>>>>
5009 20:15:10.622600 [ANA_INIT] flow end
5010 20:15:10.625406 ============ LP4 DIFF to SE enter ============
5011 20:15:10.631734 ============ LP4 DIFF to SE exit ============
5012 20:15:10.632213 [ANA_INIT] <<<<<<<<<<<<<
5013 20:15:10.635405 [Flow] Enable top DCM control >>>>>
5014 20:15:10.638859 [Flow] Enable top DCM control <<<<<
5015 20:15:10.642023 Enable DLL master slave shuffle
5016 20:15:10.648210 ==============================================================
5017 20:15:10.651486 Gating Mode config
5018 20:15:10.655542 ==============================================================
5019 20:15:10.658409 Config description:
5020 20:15:10.668042 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5021 20:15:10.674832 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5022 20:15:10.678022 SELPH_MODE 0: By rank 1: By Phase
5023 20:15:10.684708 ==============================================================
5024 20:15:10.688165 GAT_TRACK_EN = 1
5025 20:15:10.691377 RX_GATING_MODE = 2
5026 20:15:10.695790 RX_GATING_TRACK_MODE = 2
5027 20:15:10.696366 SELPH_MODE = 1
5028 20:15:10.697839 PICG_EARLY_EN = 1
5029 20:15:10.701160 VALID_LAT_VALUE = 1
5030 20:15:10.708156 ==============================================================
5031 20:15:10.711239 Enter into Gating configuration >>>>
5032 20:15:10.714575 Exit from Gating configuration <<<<
5033 20:15:10.717393 Enter into DVFS_PRE_config >>>>>
5034 20:15:10.727607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5035 20:15:10.730353 Exit from DVFS_PRE_config <<<<<
5036 20:15:10.734147 Enter into PICG configuration >>>>
5037 20:15:10.737416 Exit from PICG configuration <<<<
5038 20:15:10.741047 [RX_INPUT] configuration >>>>>
5039 20:15:10.744456 [RX_INPUT] configuration <<<<<
5040 20:15:10.750285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5041 20:15:10.753408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5042 20:15:10.760297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 20:15:10.767068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 20:15:10.773614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 20:15:10.780647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 20:15:10.783571 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5047 20:15:10.786809 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5048 20:15:10.790138 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5049 20:15:10.796645 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5050 20:15:10.800309 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5051 20:15:10.803057 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5052 20:15:10.807275 ===================================
5053 20:15:10.810477 LPDDR4 DRAM CONFIGURATION
5054 20:15:10.813119 ===================================
5055 20:15:10.813593 EX_ROW_EN[0] = 0x0
5056 20:15:10.816180 EX_ROW_EN[1] = 0x0
5057 20:15:10.819230 LP4Y_EN = 0x0
5058 20:15:10.819740 WORK_FSP = 0x0
5059 20:15:10.822882 WL = 0x3
5060 20:15:10.823392 RL = 0x3
5061 20:15:10.825857 BL = 0x2
5062 20:15:10.826324 RPST = 0x0
5063 20:15:10.829561 RD_PRE = 0x0
5064 20:15:10.830046 WR_PRE = 0x1
5065 20:15:10.833132 WR_PST = 0x0
5066 20:15:10.833729 DBI_WR = 0x0
5067 20:15:10.835745 DBI_RD = 0x0
5068 20:15:10.836220 OTF = 0x1
5069 20:15:10.838937 ===================================
5070 20:15:10.842944 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5071 20:15:10.849239 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5072 20:15:10.852209 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5073 20:15:10.855359 ===================================
5074 20:15:10.859268 LPDDR4 DRAM CONFIGURATION
5075 20:15:10.862204 ===================================
5076 20:15:10.865633 EX_ROW_EN[0] = 0x10
5077 20:15:10.866161 EX_ROW_EN[1] = 0x0
5078 20:15:10.868904 LP4Y_EN = 0x0
5079 20:15:10.869431 WORK_FSP = 0x0
5080 20:15:10.872092 WL = 0x3
5081 20:15:10.872620 RL = 0x3
5082 20:15:10.875056 BL = 0x2
5083 20:15:10.875517 RPST = 0x0
5084 20:15:10.878951 RD_PRE = 0x0
5085 20:15:10.879371 WR_PRE = 0x1
5086 20:15:10.881906 WR_PST = 0x0
5087 20:15:10.882327 DBI_WR = 0x0
5088 20:15:10.886120 DBI_RD = 0x0
5089 20:15:10.886641 OTF = 0x1
5090 20:15:10.889155 ===================================
5091 20:15:10.895322 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5092 20:15:10.900635 nWR fixed to 30
5093 20:15:10.903560 [ModeRegInit_LP4] CH0 RK0
5094 20:15:10.904216 [ModeRegInit_LP4] CH0 RK1
5095 20:15:10.907109 [ModeRegInit_LP4] CH1 RK0
5096 20:15:10.909995 [ModeRegInit_LP4] CH1 RK1
5097 20:15:10.910569 match AC timing 9
5098 20:15:10.916442 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5099 20:15:10.919754 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5100 20:15:10.922841 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5101 20:15:10.929283 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5102 20:15:10.933130 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5103 20:15:10.933708 ==
5104 20:15:10.936374 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 20:15:10.939270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 20:15:10.939889 ==
5107 20:15:10.946198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 20:15:10.952721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 20:15:10.956610 [CA 0] Center 37 (7~68) winsize 62
5110 20:15:10.959654 [CA 1] Center 37 (7~68) winsize 62
5111 20:15:10.962584 [CA 2] Center 34 (4~65) winsize 62
5112 20:15:10.966556 [CA 3] Center 35 (5~65) winsize 61
5113 20:15:10.969333 [CA 4] Center 33 (3~64) winsize 62
5114 20:15:10.972882 [CA 5] Center 33 (3~63) winsize 61
5115 20:15:10.973461
5116 20:15:10.975784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 20:15:10.976258
5118 20:15:10.979017 [CATrainingPosCal] consider 1 rank data
5119 20:15:10.982426 u2DelayCellTimex100 = 270/100 ps
5120 20:15:10.986082 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 20:15:10.988782 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 20:15:10.992158 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 20:15:10.995520 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5124 20:15:11.002233 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5125 20:15:11.005463 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5126 20:15:11.006037
5127 20:15:11.008986 CA PerBit enable=1, Macro0, CA PI delay=33
5128 20:15:11.009556
5129 20:15:11.012401 [CBTSetCACLKResult] CA Dly = 33
5130 20:15:11.013034 CS Dly: 7 (0~38)
5131 20:15:11.013418 ==
5132 20:15:11.015174 Dram Type= 6, Freq= 0, CH_0, rank 1
5133 20:15:11.022140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 20:15:11.022723 ==
5135 20:15:11.025314 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5136 20:15:11.032206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5137 20:15:11.035188 [CA 0] Center 37 (7~68) winsize 62
5138 20:15:11.038977 [CA 1] Center 37 (7~68) winsize 62
5139 20:15:11.042240 [CA 2] Center 34 (4~65) winsize 62
5140 20:15:11.045038 [CA 3] Center 34 (4~65) winsize 62
5141 20:15:11.048499 [CA 4] Center 33 (3~64) winsize 62
5142 20:15:11.051720 [CA 5] Center 33 (2~64) winsize 63
5143 20:15:11.052309
5144 20:15:11.055533 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5145 20:15:11.056156
5146 20:15:11.058306 [CATrainingPosCal] consider 2 rank data
5147 20:15:11.061721 u2DelayCellTimex100 = 270/100 ps
5148 20:15:11.064875 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5149 20:15:11.071728 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 20:15:11.074348 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5151 20:15:11.077639 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5152 20:15:11.082358 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5153 20:15:11.084420 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5154 20:15:11.084920
5155 20:15:11.088176 CA PerBit enable=1, Macro0, CA PI delay=33
5156 20:15:11.088661
5157 20:15:11.091773 [CBTSetCACLKResult] CA Dly = 33
5158 20:15:11.094302 CS Dly: 8 (0~40)
5159 20:15:11.094876
5160 20:15:11.097612 ----->DramcWriteLeveling(PI) begin...
5161 20:15:11.098082 ==
5162 20:15:11.101091 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 20:15:11.104999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 20:15:11.105574 ==
5165 20:15:11.107723 Write leveling (Byte 0): 34 => 34
5166 20:15:11.111062 Write leveling (Byte 1): 31 => 31
5167 20:15:11.114447 DramcWriteLeveling(PI) end<-----
5168 20:15:11.115028
5169 20:15:11.115403 ==
5170 20:15:11.117614 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 20:15:11.120876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 20:15:11.121350 ==
5173 20:15:11.124431 [Gating] SW mode calibration
5174 20:15:11.130820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5175 20:15:11.137751 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5176 20:15:11.140428 0 14 0 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
5177 20:15:11.145245 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5178 20:15:11.150681 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 20:15:11.153541 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 20:15:11.157816 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 20:15:11.163958 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 20:15:11.166967 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 20:15:11.170727 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
5184 20:15:11.177298 0 15 0 | B1->B0 | 3131 2525 | 1 0 | (1 0) (0 0)
5185 20:15:11.180743 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5186 20:15:11.183446 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 20:15:11.190876 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 20:15:11.193791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 20:15:11.196495 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 20:15:11.203166 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 20:15:11.207036 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5192 20:15:11.210226 1 0 0 | B1->B0 | 2f2f 4242 | 0 0 | (0 0) (0 0)
5193 20:15:11.216564 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 20:15:11.220395 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 20:15:11.223196 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 20:15:11.229575 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 20:15:11.233186 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 20:15:11.236619 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 20:15:11.242974 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5200 20:15:11.246625 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5201 20:15:11.249914 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5202 20:15:11.255744 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 20:15:11.260227 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 20:15:11.262779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 20:15:11.269391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 20:15:11.272825 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 20:15:11.276338 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 20:15:11.282304 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 20:15:11.285791 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 20:15:11.288923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 20:15:11.295793 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 20:15:11.298748 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 20:15:11.302596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 20:15:11.309600 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 20:15:11.312494 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5216 20:15:11.315650 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5217 20:15:11.318698 Total UI for P1: 0, mck2ui 16
5218 20:15:11.322568 best dqsien dly found for B0: ( 1, 2, 28)
5219 20:15:11.328475 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 20:15:11.328903 Total UI for P1: 0, mck2ui 16
5221 20:15:11.335117 best dqsien dly found for B1: ( 1, 3, 0)
5222 20:15:11.339188 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5223 20:15:11.342246 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5224 20:15:11.342773
5225 20:15:11.345059 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5226 20:15:11.348453 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5227 20:15:11.352021 [Gating] SW calibration Done
5228 20:15:11.352445 ==
5229 20:15:11.355157 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 20:15:11.358619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 20:15:11.359153 ==
5232 20:15:11.361757 RX Vref Scan: 0
5233 20:15:11.362286
5234 20:15:11.362626 RX Vref 0 -> 0, step: 1
5235 20:15:11.362943
5236 20:15:11.365634 RX Delay -80 -> 252, step: 8
5237 20:15:11.368462 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5238 20:15:11.374984 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5239 20:15:11.378732 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5240 20:15:11.381779 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5241 20:15:11.385115 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5242 20:15:11.388873 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5243 20:15:11.391235 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5244 20:15:11.398049 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5245 20:15:11.401544 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5246 20:15:11.405361 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5247 20:15:11.408578 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5248 20:15:11.412012 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5249 20:15:11.418043 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5250 20:15:11.421532 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5251 20:15:11.424823 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5252 20:15:11.428681 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5253 20:15:11.429151 ==
5254 20:15:11.431184 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 20:15:11.435185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 20:15:11.438208 ==
5257 20:15:11.438673 DQS Delay:
5258 20:15:11.439047 DQS0 = 0, DQS1 = 0
5259 20:15:11.441578 DQM Delay:
5260 20:15:11.442151 DQM0 = 97, DQM1 = 86
5261 20:15:11.444438 DQ Delay:
5262 20:15:11.447453 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5263 20:15:11.451049 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5264 20:15:11.454706 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5265 20:15:11.458147 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5266 20:15:11.458720
5267 20:15:11.459093
5268 20:15:11.459440 ==
5269 20:15:11.460852 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 20:15:11.464352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 20:15:11.464821 ==
5272 20:15:11.465197
5273 20:15:11.465507
5274 20:15:11.467800 TX Vref Scan disable
5275 20:15:11.468331 == TX Byte 0 ==
5276 20:15:11.474379 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5277 20:15:11.477780 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5278 20:15:11.478206 == TX Byte 1 ==
5279 20:15:11.484649 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5280 20:15:11.487848 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5281 20:15:11.488375 ==
5282 20:15:11.490627 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 20:15:11.493981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 20:15:11.494511 ==
5285 20:15:11.496736
5286 20:15:11.497217
5287 20:15:11.497556 TX Vref Scan disable
5288 20:15:11.500679 == TX Byte 0 ==
5289 20:15:11.503932 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5290 20:15:11.510844 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5291 20:15:11.511376 == TX Byte 1 ==
5292 20:15:11.514171 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5293 20:15:11.520170 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5294 20:15:11.520594
5295 20:15:11.520929 [DATLAT]
5296 20:15:11.521245 Freq=933, CH0 RK0
5297 20:15:11.521551
5298 20:15:11.523396 DATLAT Default: 0xd
5299 20:15:11.523846 0, 0xFFFF, sum = 0
5300 20:15:11.527522 1, 0xFFFF, sum = 0
5301 20:15:11.528112 2, 0xFFFF, sum = 0
5302 20:15:11.530175 3, 0xFFFF, sum = 0
5303 20:15:11.533234 4, 0xFFFF, sum = 0
5304 20:15:11.533852 5, 0xFFFF, sum = 0
5305 20:15:11.537031 6, 0xFFFF, sum = 0
5306 20:15:11.537564 7, 0xFFFF, sum = 0
5307 20:15:11.540310 8, 0xFFFF, sum = 0
5308 20:15:11.540741 9, 0xFFFF, sum = 0
5309 20:15:11.543518 10, 0x0, sum = 1
5310 20:15:11.544115 11, 0x0, sum = 2
5311 20:15:11.546961 12, 0x0, sum = 3
5312 20:15:11.547500 13, 0x0, sum = 4
5313 20:15:11.547915 best_step = 11
5314 20:15:11.548237
5315 20:15:11.549952 ==
5316 20:15:11.553609 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 20:15:11.557090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 20:15:11.557634 ==
5319 20:15:11.557974 RX Vref Scan: 1
5320 20:15:11.558292
5321 20:15:11.559908 RX Vref 0 -> 0, step: 1
5322 20:15:11.560333
5323 20:15:11.563715 RX Delay -61 -> 252, step: 4
5324 20:15:11.564246
5325 20:15:11.566874 Set Vref, RX VrefLevel [Byte0]: 60
5326 20:15:11.570225 [Byte1]: 59
5327 20:15:11.570649
5328 20:15:11.572694 Final RX Vref Byte 0 = 60 to rank0
5329 20:15:11.576234 Final RX Vref Byte 1 = 59 to rank0
5330 20:15:11.579630 Final RX Vref Byte 0 = 60 to rank1
5331 20:15:11.582745 Final RX Vref Byte 1 = 59 to rank1==
5332 20:15:11.586257 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 20:15:11.593024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 20:15:11.593446 ==
5335 20:15:11.593782 DQS Delay:
5336 20:15:11.594097 DQS0 = 0, DQS1 = 0
5337 20:15:11.596146 DQM Delay:
5338 20:15:11.596563 DQM0 = 97, DQM1 = 87
5339 20:15:11.599492 DQ Delay:
5340 20:15:11.603353 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5341 20:15:11.605917 DQ4 =98, DQ5 =90, DQ6 =108, DQ7 =106
5342 20:15:11.609918 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5343 20:15:11.612506 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =94
5344 20:15:11.613030
5345 20:15:11.613362
5346 20:15:11.620488 [DQSOSCAuto] RK0, (LSB)MR18= 0x280e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5347 20:15:11.623128 CH0 RK0: MR19=505, MR18=280E
5348 20:15:11.628783 CH0_RK0: MR19=0x505, MR18=0x280E, DQSOSC=409, MR23=63, INC=64, DEC=43
5349 20:15:11.629295
5350 20:15:11.632468 ----->DramcWriteLeveling(PI) begin...
5351 20:15:11.632943 ==
5352 20:15:11.635844 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 20:15:11.639135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 20:15:11.639732 ==
5355 20:15:11.642092 Write leveling (Byte 0): 33 => 33
5356 20:15:11.645206 Write leveling (Byte 1): 29 => 29
5357 20:15:11.649170 DramcWriteLeveling(PI) end<-----
5358 20:15:11.649628
5359 20:15:11.649989 ==
5360 20:15:11.652341 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 20:15:11.655780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 20:15:11.658751 ==
5363 20:15:11.659278 [Gating] SW mode calibration
5364 20:15:11.665771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 20:15:11.672571 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5366 20:15:11.675372 0 14 0 | B1->B0 | 2323 3030 | 1 0 | (0 0) (0 0)
5367 20:15:11.682076 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5368 20:15:11.685446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 20:15:11.688608 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 20:15:11.696063 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 20:15:11.698818 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 20:15:11.702487 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 20:15:11.708442 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0)
5374 20:15:11.712410 0 15 0 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
5375 20:15:11.714993 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5376 20:15:11.721590 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 20:15:11.724859 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 20:15:11.728341 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 20:15:11.735283 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 20:15:11.739354 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 20:15:11.741502 0 15 28 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
5382 20:15:11.748151 1 0 0 | B1->B0 | 3b3b 4242 | 0 0 | (1 1) (0 0)
5383 20:15:11.751660 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 20:15:11.755110 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 20:15:11.761451 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 20:15:11.764479 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 20:15:11.768134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 20:15:11.774651 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 20:15:11.777743 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5390 20:15:11.781004 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5391 20:15:11.787581 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 20:15:11.791421 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 20:15:11.794987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 20:15:11.801108 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 20:15:11.804053 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 20:15:11.808243 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 20:15:11.813960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 20:15:11.816901 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 20:15:11.820499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 20:15:11.826993 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 20:15:11.830473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 20:15:11.833335 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 20:15:11.840639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 20:15:11.844067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 20:15:11.847007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5406 20:15:11.853384 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5407 20:15:11.853939 Total UI for P1: 0, mck2ui 16
5408 20:15:11.860391 best dqsien dly found for B0: ( 1, 2, 28)
5409 20:15:11.863356 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 20:15:11.866646 Total UI for P1: 0, mck2ui 16
5411 20:15:11.870218 best dqsien dly found for B1: ( 1, 2, 30)
5412 20:15:11.873738 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5413 20:15:11.876391 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5414 20:15:11.876856
5415 20:15:11.879563 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5416 20:15:11.882925 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5417 20:15:11.886921 [Gating] SW calibration Done
5418 20:15:11.887379 ==
5419 20:15:11.889685 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 20:15:11.896586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 20:15:11.897148 ==
5422 20:15:11.897522 RX Vref Scan: 0
5423 20:15:11.897863
5424 20:15:11.899210 RX Vref 0 -> 0, step: 1
5425 20:15:11.899703
5426 20:15:11.902899 RX Delay -80 -> 252, step: 8
5427 20:15:11.906077 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5428 20:15:11.909498 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5429 20:15:11.912957 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5430 20:15:11.916510 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5431 20:15:11.922918 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5432 20:15:11.926196 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5433 20:15:11.929439 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5434 20:15:11.932492 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5435 20:15:11.935594 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5436 20:15:11.939452 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5437 20:15:11.945707 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5438 20:15:11.949133 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5439 20:15:11.952475 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5440 20:15:11.955437 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5441 20:15:11.958971 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5442 20:15:11.965886 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5443 20:15:11.966513 ==
5444 20:15:11.968438 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 20:15:11.972125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 20:15:11.972784 ==
5447 20:15:11.973165 DQS Delay:
5448 20:15:11.975033 DQS0 = 0, DQS1 = 0
5449 20:15:11.975469 DQM Delay:
5450 20:15:11.978696 DQM0 = 97, DQM1 = 90
5451 20:15:11.979171 DQ Delay:
5452 20:15:11.982281 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5453 20:15:11.985418 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5454 20:15:11.988763 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5455 20:15:11.992875 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5456 20:15:11.993664
5457 20:15:11.994064
5458 20:15:11.994409 ==
5459 20:15:11.995264 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 20:15:11.998455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 20:15:11.998915 ==
5462 20:15:11.999284
5463 20:15:12.003522
5464 20:15:12.004124 TX Vref Scan disable
5465 20:15:12.007961 == TX Byte 0 ==
5466 20:15:12.008868 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5467 20:15:12.011864 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5468 20:15:12.014880 == TX Byte 1 ==
5469 20:15:12.018258 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5470 20:15:12.021612 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5471 20:15:12.022172 ==
5472 20:15:12.024946 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 20:15:12.032000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 20:15:12.032565 ==
5475 20:15:12.032931
5476 20:15:12.033269
5477 20:15:12.035018 TX Vref Scan disable
5478 20:15:12.035477 == TX Byte 0 ==
5479 20:15:12.041465 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5480 20:15:12.045650 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5481 20:15:12.046210 == TX Byte 1 ==
5482 20:15:12.051562 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5483 20:15:12.054647 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5484 20:15:12.055207
5485 20:15:12.055570 [DATLAT]
5486 20:15:12.058146 Freq=933, CH0 RK1
5487 20:15:12.058706
5488 20:15:12.059070 DATLAT Default: 0xb
5489 20:15:12.061416 0, 0xFFFF, sum = 0
5490 20:15:12.061988 1, 0xFFFF, sum = 0
5491 20:15:12.064610 2, 0xFFFF, sum = 0
5492 20:15:12.065177 3, 0xFFFF, sum = 0
5493 20:15:12.068691 4, 0xFFFF, sum = 0
5494 20:15:12.069255 5, 0xFFFF, sum = 0
5495 20:15:12.070889 6, 0xFFFF, sum = 0
5496 20:15:12.074453 7, 0xFFFF, sum = 0
5497 20:15:12.075071 8, 0xFFFF, sum = 0
5498 20:15:12.077376 9, 0xFFFF, sum = 0
5499 20:15:12.077894 10, 0x0, sum = 1
5500 20:15:12.078282 11, 0x0, sum = 2
5501 20:15:12.080878 12, 0x0, sum = 3
5502 20:15:12.081347 13, 0x0, sum = 4
5503 20:15:12.084328 best_step = 11
5504 20:15:12.084804
5505 20:15:12.085207 ==
5506 20:15:12.087337 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 20:15:12.091074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 20:15:12.091543 ==
5509 20:15:12.094426 RX Vref Scan: 0
5510 20:15:12.094886
5511 20:15:12.095376 RX Vref 0 -> 0, step: 1
5512 20:15:12.097469
5513 20:15:12.097942 RX Delay -61 -> 252, step: 4
5514 20:15:12.105068 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5515 20:15:12.109314 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5516 20:15:12.112301 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5517 20:15:12.114732 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5518 20:15:12.118211 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5519 20:15:12.121357 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5520 20:15:12.128005 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5521 20:15:12.132214 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5522 20:15:12.135336 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5523 20:15:12.137722 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5524 20:15:12.141617 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5525 20:15:12.148135 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5526 20:15:12.151774 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5527 20:15:12.154523 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5528 20:15:12.158387 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5529 20:15:12.160766 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5530 20:15:12.161232 ==
5531 20:15:12.164614 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 20:15:12.171484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 20:15:12.172108 ==
5534 20:15:12.172485 DQS Delay:
5535 20:15:12.174445 DQS0 = 0, DQS1 = 0
5536 20:15:12.175008 DQM Delay:
5537 20:15:12.177719 DQM0 = 95, DQM1 = 88
5538 20:15:12.178183 DQ Delay:
5539 20:15:12.180812 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5540 20:15:12.184607 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5541 20:15:12.187312 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =82
5542 20:15:12.190619 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =94
5543 20:15:12.191189
5544 20:15:12.191716
5545 20:15:12.197436 [DQSOSCAuto] RK1, (LSB)MR18= 0x22f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 411 ps
5546 20:15:12.200247 CH0 RK1: MR19=504, MR18=22F3
5547 20:15:12.208115 CH0_RK1: MR19=0x504, MR18=0x22F3, DQSOSC=411, MR23=63, INC=64, DEC=42
5548 20:15:12.211203 [RxdqsGatingPostProcess] freq 933
5549 20:15:12.216938 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5550 20:15:12.220638 best DQS0 dly(2T, 0.5T) = (0, 10)
5551 20:15:12.221099 best DQS1 dly(2T, 0.5T) = (0, 11)
5552 20:15:12.223781 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5553 20:15:12.226678 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5554 20:15:12.230702 best DQS0 dly(2T, 0.5T) = (0, 10)
5555 20:15:12.233832 best DQS1 dly(2T, 0.5T) = (0, 10)
5556 20:15:12.236726 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5557 20:15:12.240561 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5558 20:15:12.243571 Pre-setting of DQS Precalculation
5559 20:15:12.250119 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5560 20:15:12.250677 ==
5561 20:15:12.253520 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 20:15:12.256497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 20:15:12.256974 ==
5564 20:15:12.263063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5565 20:15:12.269731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5566 20:15:12.273034 [CA 0] Center 37 (7~67) winsize 61
5567 20:15:12.276612 [CA 1] Center 37 (7~68) winsize 62
5568 20:15:12.279304 [CA 2] Center 34 (4~65) winsize 62
5569 20:15:12.283148 [CA 3] Center 34 (4~64) winsize 61
5570 20:15:12.285762 [CA 4] Center 34 (5~64) winsize 60
5571 20:15:12.289443 [CA 5] Center 33 (3~64) winsize 62
5572 20:15:12.290007
5573 20:15:12.292607 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5574 20:15:12.293168
5575 20:15:12.296390 [CATrainingPosCal] consider 1 rank data
5576 20:15:12.299448 u2DelayCellTimex100 = 270/100 ps
5577 20:15:12.302223 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5578 20:15:12.306226 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5579 20:15:12.308916 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 20:15:12.312419 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 20:15:12.316139 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5582 20:15:12.318882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5583 20:15:12.319409
5584 20:15:12.325550 CA PerBit enable=1, Macro0, CA PI delay=33
5585 20:15:12.326009
5586 20:15:12.329030 [CBTSetCACLKResult] CA Dly = 33
5587 20:15:12.329587 CS Dly: 6 (0~37)
5588 20:15:12.329957 ==
5589 20:15:12.331920 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 20:15:12.335299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 20:15:12.335818 ==
5592 20:15:12.341681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5593 20:15:12.348759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5594 20:15:12.352131 [CA 0] Center 37 (7~67) winsize 61
5595 20:15:12.355440 [CA 1] Center 37 (7~68) winsize 62
5596 20:15:12.358277 [CA 2] Center 34 (4~65) winsize 62
5597 20:15:12.362381 [CA 3] Center 34 (4~65) winsize 62
5598 20:15:12.365884 [CA 4] Center 34 (4~65) winsize 62
5599 20:15:12.368278 [CA 5] Center 33 (3~64) winsize 62
5600 20:15:12.368781
5601 20:15:12.371924 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5602 20:15:12.372392
5603 20:15:12.374597 [CATrainingPosCal] consider 2 rank data
5604 20:15:12.377745 u2DelayCellTimex100 = 270/100 ps
5605 20:15:12.381772 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5606 20:15:12.384564 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5607 20:15:12.387665 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5608 20:15:12.394191 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 20:15:12.398549 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5610 20:15:12.401083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 20:15:12.401606
5612 20:15:12.404702 CA PerBit enable=1, Macro0, CA PI delay=33
5613 20:15:12.405129
5614 20:15:12.407746 [CBTSetCACLKResult] CA Dly = 33
5615 20:15:12.408167 CS Dly: 7 (0~39)
5616 20:15:12.408503
5617 20:15:12.410689 ----->DramcWriteLeveling(PI) begin...
5618 20:15:12.411154 ==
5619 20:15:12.414289 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 20:15:12.421096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 20:15:12.421531 ==
5622 20:15:12.423943 Write leveling (Byte 0): 26 => 26
5623 20:15:12.427760 Write leveling (Byte 1): 27 => 27
5624 20:15:12.431075 DramcWriteLeveling(PI) end<-----
5625 20:15:12.431602
5626 20:15:12.431994 ==
5627 20:15:12.433706 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 20:15:12.437101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 20:15:12.437571 ==
5630 20:15:12.440314 [Gating] SW mode calibration
5631 20:15:12.447854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5632 20:15:12.453721 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5633 20:15:12.457445 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 20:15:12.460957 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 20:15:12.467072 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 20:15:12.470781 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 20:15:12.473810 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 20:15:12.480502 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 20:15:12.484106 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5640 20:15:12.487168 0 14 28 | B1->B0 | 2e2e 2d2d | 0 1 | (1 0) (0 0)
5641 20:15:12.490504 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 20:15:12.497352 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 20:15:12.500582 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 20:15:12.503750 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 20:15:12.510044 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 20:15:12.513658 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 20:15:12.516946 0 15 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
5648 20:15:12.523264 0 15 28 | B1->B0 | 3434 3737 | 1 1 | (0 0) (0 0)
5649 20:15:12.526455 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 20:15:12.530090 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 20:15:12.536630 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 20:15:12.540355 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 20:15:12.543030 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 20:15:12.549646 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 20:15:12.554031 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 20:15:12.555914 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 20:15:12.563127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 20:15:12.566619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 20:15:12.569412 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 20:15:12.576001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 20:15:12.579795 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 20:15:12.582860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 20:15:12.590177 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 20:15:12.592616 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 20:15:12.596031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 20:15:12.602651 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 20:15:12.605857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 20:15:12.608916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 20:15:12.615719 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 20:15:12.618568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 20:15:12.622095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5672 20:15:12.629014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5673 20:15:12.631857 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 20:15:12.635593 Total UI for P1: 0, mck2ui 16
5675 20:15:12.638263 best dqsien dly found for B0: ( 1, 2, 26)
5676 20:15:12.642412 Total UI for P1: 0, mck2ui 16
5677 20:15:12.646118 best dqsien dly found for B1: ( 1, 2, 28)
5678 20:15:12.648869 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5679 20:15:12.652088 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5680 20:15:12.652652
5681 20:15:12.655430 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5682 20:15:12.661944 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5683 20:15:12.662515 [Gating] SW calibration Done
5684 20:15:12.662912 ==
5685 20:15:12.664896 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 20:15:12.671829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 20:15:12.672401 ==
5688 20:15:12.672845 RX Vref Scan: 0
5689 20:15:12.673247
5690 20:15:12.674939 RX Vref 0 -> 0, step: 1
5691 20:15:12.675499
5692 20:15:12.677793 RX Delay -80 -> 252, step: 8
5693 20:15:12.681292 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5694 20:15:12.685737 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5695 20:15:12.687995 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5696 20:15:12.695033 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5697 20:15:12.697777 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5698 20:15:12.701043 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5699 20:15:12.704364 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5700 20:15:12.708087 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5701 20:15:12.711466 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5702 20:15:12.717441 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5703 20:15:12.720929 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5704 20:15:12.724165 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5705 20:15:12.727743 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5706 20:15:12.731043 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5707 20:15:12.737197 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5708 20:15:12.740445 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5709 20:15:12.740910 ==
5710 20:15:12.743895 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 20:15:12.747441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 20:15:12.748071 ==
5713 20:15:12.750414 DQS Delay:
5714 20:15:12.750989 DQS0 = 0, DQS1 = 0
5715 20:15:12.751359 DQM Delay:
5716 20:15:12.753987 DQM0 = 103, DQM1 = 90
5717 20:15:12.754543 DQ Delay:
5718 20:15:12.756960 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5719 20:15:12.760343 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5720 20:15:12.764191 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5721 20:15:12.766916 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5722 20:15:12.767405
5723 20:15:12.767832
5724 20:15:12.770474 ==
5725 20:15:12.773328 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 20:15:12.777679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 20:15:12.778258 ==
5728 20:15:12.778630
5729 20:15:12.778963
5730 20:15:12.780129 TX Vref Scan disable
5731 20:15:12.780587 == TX Byte 0 ==
5732 20:15:12.786588 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5733 20:15:12.789823 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5734 20:15:12.790250 == TX Byte 1 ==
5735 20:15:12.797400 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5736 20:15:12.799550 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5737 20:15:12.800069 ==
5738 20:15:12.803633 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 20:15:12.806331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 20:15:12.806797 ==
5741 20:15:12.807162
5742 20:15:12.807504
5743 20:15:12.810008 TX Vref Scan disable
5744 20:15:12.813514 == TX Byte 0 ==
5745 20:15:12.816542 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5746 20:15:12.819612 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5747 20:15:12.822750 == TX Byte 1 ==
5748 20:15:12.826252 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5749 20:15:12.829741 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5750 20:15:12.830313
5751 20:15:12.832559 [DATLAT]
5752 20:15:12.833025 Freq=933, CH1 RK0
5753 20:15:12.833390
5754 20:15:12.835937 DATLAT Default: 0xd
5755 20:15:12.836500 0, 0xFFFF, sum = 0
5756 20:15:12.839513 1, 0xFFFF, sum = 0
5757 20:15:12.840015 2, 0xFFFF, sum = 0
5758 20:15:12.842925 3, 0xFFFF, sum = 0
5759 20:15:12.843392 4, 0xFFFF, sum = 0
5760 20:15:12.845752 5, 0xFFFF, sum = 0
5761 20:15:12.846220 6, 0xFFFF, sum = 0
5762 20:15:12.849947 7, 0xFFFF, sum = 0
5763 20:15:12.850522 8, 0xFFFF, sum = 0
5764 20:15:12.852403 9, 0xFFFF, sum = 0
5765 20:15:12.852871 10, 0x0, sum = 1
5766 20:15:12.855893 11, 0x0, sum = 2
5767 20:15:12.856359 12, 0x0, sum = 3
5768 20:15:12.859382 13, 0x0, sum = 4
5769 20:15:12.860016 best_step = 11
5770 20:15:12.860393
5771 20:15:12.860734 ==
5772 20:15:12.862626 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 20:15:12.869409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 20:15:12.869991 ==
5775 20:15:12.870370 RX Vref Scan: 1
5776 20:15:12.870716
5777 20:15:12.872463 RX Vref 0 -> 0, step: 1
5778 20:15:12.872927
5779 20:15:12.875755 RX Delay -69 -> 252, step: 4
5780 20:15:12.876233
5781 20:15:12.878678 Set Vref, RX VrefLevel [Byte0]: 48
5782 20:15:12.882093 [Byte1]: 59
5783 20:15:12.882557
5784 20:15:12.885208 Final RX Vref Byte 0 = 48 to rank0
5785 20:15:12.888698 Final RX Vref Byte 1 = 59 to rank0
5786 20:15:12.892910 Final RX Vref Byte 0 = 48 to rank1
5787 20:15:12.895861 Final RX Vref Byte 1 = 59 to rank1==
5788 20:15:12.899391 Dram Type= 6, Freq= 0, CH_1, rank 0
5789 20:15:12.902170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 20:15:12.902741 ==
5791 20:15:12.905375 DQS Delay:
5792 20:15:12.905946 DQS0 = 0, DQS1 = 0
5793 20:15:12.908674 DQM Delay:
5794 20:15:12.909246 DQM0 = 101, DQM1 = 95
5795 20:15:12.911655 DQ Delay:
5796 20:15:12.914840 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5797 20:15:12.918643 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5798 20:15:12.922056 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5799 20:15:12.925454 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5800 20:15:12.925925
5801 20:15:12.926293
5802 20:15:12.931755 [DQSOSCAuto] RK0, (LSB)MR18= 0x1707, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5803 20:15:12.934971 CH1 RK0: MR19=505, MR18=1707
5804 20:15:12.941869 CH1_RK0: MR19=0x505, MR18=0x1707, DQSOSC=414, MR23=63, INC=63, DEC=42
5805 20:15:12.942335
5806 20:15:12.945043 ----->DramcWriteLeveling(PI) begin...
5807 20:15:12.945614 ==
5808 20:15:12.948166 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 20:15:12.951583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 20:15:12.952192 ==
5811 20:15:12.955010 Write leveling (Byte 0): 27 => 27
5812 20:15:12.958441 Write leveling (Byte 1): 27 => 27
5813 20:15:12.961154 DramcWriteLeveling(PI) end<-----
5814 20:15:12.961718
5815 20:15:12.962086 ==
5816 20:15:12.964228 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 20:15:12.967991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 20:15:12.971629 ==
5819 20:15:12.972232 [Gating] SW mode calibration
5820 20:15:12.980695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5821 20:15:12.984154 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5822 20:15:12.987336 0 14 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5823 20:15:12.994073 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 20:15:12.997479 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 20:15:13.000787 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 20:15:13.007749 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 20:15:13.010680 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 20:15:13.014323 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5829 20:15:13.020414 0 14 28 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
5830 20:15:13.023800 0 15 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5831 20:15:13.027617 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 20:15:13.034007 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 20:15:13.037463 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 20:15:13.041239 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 20:15:13.047114 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 20:15:13.050827 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5837 20:15:13.054073 0 15 28 | B1->B0 | 4040 3131 | 1 1 | (0 0) (0 0)
5838 20:15:13.059808 1 0 0 | B1->B0 | 4646 3e3e | 0 1 | (0 0) (0 0)
5839 20:15:13.063236 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 20:15:13.070235 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 20:15:13.073428 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 20:15:13.076639 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 20:15:13.082684 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 20:15:13.086198 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5845 20:15:13.089629 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5846 20:15:13.096095 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 20:15:13.099775 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 20:15:13.102671 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 20:15:13.109580 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 20:15:13.112627 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 20:15:13.116197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 20:15:13.119122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 20:15:13.126154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 20:15:13.129418 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 20:15:13.136558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 20:15:13.139496 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 20:15:13.142361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 20:15:13.149825 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 20:15:13.152095 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 20:15:13.155434 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 20:15:13.162140 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5862 20:15:13.165416 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 20:15:13.168944 Total UI for P1: 0, mck2ui 16
5864 20:15:13.171459 best dqsien dly found for B0: ( 1, 2, 28)
5865 20:15:13.174938 Total UI for P1: 0, mck2ui 16
5866 20:15:13.178635 best dqsien dly found for B1: ( 1, 2, 28)
5867 20:15:13.181423 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5868 20:15:13.184863 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5869 20:15:13.185423
5870 20:15:13.187993 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5871 20:15:13.191533 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5872 20:15:13.195141 [Gating] SW calibration Done
5873 20:15:13.195756 ==
5874 20:15:13.198972 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 20:15:13.201342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 20:15:13.205006 ==
5877 20:15:13.205672 RX Vref Scan: 0
5878 20:15:13.206051
5879 20:15:13.208270 RX Vref 0 -> 0, step: 1
5880 20:15:13.208830
5881 20:15:13.211112 RX Delay -80 -> 252, step: 8
5882 20:15:13.214347 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5883 20:15:13.217894 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5884 20:15:13.221224 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5885 20:15:13.224382 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5886 20:15:13.228283 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5887 20:15:13.234371 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5888 20:15:13.237855 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5889 20:15:13.241050 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5890 20:15:13.243802 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5891 20:15:13.247599 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5892 20:15:13.254278 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5893 20:15:13.258000 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5894 20:15:13.260708 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5895 20:15:13.263842 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5896 20:15:13.267752 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5897 20:15:13.273845 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5898 20:15:13.274407 ==
5899 20:15:13.276922 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 20:15:13.280161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 20:15:13.280638 ==
5902 20:15:13.281007 DQS Delay:
5903 20:15:13.283356 DQS0 = 0, DQS1 = 0
5904 20:15:13.283860 DQM Delay:
5905 20:15:13.286694 DQM0 = 100, DQM1 = 92
5906 20:15:13.287152 DQ Delay:
5907 20:15:13.290229 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5908 20:15:13.293594 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5909 20:15:13.296816 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5910 20:15:13.300178 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5911 20:15:13.300741
5912 20:15:13.301107
5913 20:15:13.301448 ==
5914 20:15:13.304083 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 20:15:13.310195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 20:15:13.310760 ==
5917 20:15:13.311125
5918 20:15:13.311459
5919 20:15:13.311865 TX Vref Scan disable
5920 20:15:13.313168 == TX Byte 0 ==
5921 20:15:13.317270 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5922 20:15:13.323163 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5923 20:15:13.323622 == TX Byte 1 ==
5924 20:15:13.327049 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5925 20:15:13.333328 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5926 20:15:13.333882 ==
5927 20:15:13.336780 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 20:15:13.340285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 20:15:13.340904 ==
5930 20:15:13.341282
5931 20:15:13.341638
5932 20:15:13.343063 TX Vref Scan disable
5933 20:15:13.343523 == TX Byte 0 ==
5934 20:15:13.349623 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5935 20:15:13.352937 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5936 20:15:13.356401 == TX Byte 1 ==
5937 20:15:13.359795 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5938 20:15:13.363106 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5939 20:15:13.363707
5940 20:15:13.364087 [DATLAT]
5941 20:15:13.366771 Freq=933, CH1 RK1
5942 20:15:13.367339
5943 20:15:13.369470 DATLAT Default: 0xb
5944 20:15:13.370075 0, 0xFFFF, sum = 0
5945 20:15:13.372800 1, 0xFFFF, sum = 0
5946 20:15:13.373272 2, 0xFFFF, sum = 0
5947 20:15:13.376152 3, 0xFFFF, sum = 0
5948 20:15:13.376620 4, 0xFFFF, sum = 0
5949 20:15:13.379450 5, 0xFFFF, sum = 0
5950 20:15:13.380042 6, 0xFFFF, sum = 0
5951 20:15:13.382387 7, 0xFFFF, sum = 0
5952 20:15:13.382855 8, 0xFFFF, sum = 0
5953 20:15:13.386260 9, 0xFFFF, sum = 0
5954 20:15:13.386727 10, 0x0, sum = 1
5955 20:15:13.389386 11, 0x0, sum = 2
5956 20:15:13.389858 12, 0x0, sum = 3
5957 20:15:13.393341 13, 0x0, sum = 4
5958 20:15:13.393875 best_step = 11
5959 20:15:13.394212
5960 20:15:13.394523 ==
5961 20:15:13.395983 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 20:15:13.399394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 20:15:13.399992 ==
5964 20:15:13.402933 RX Vref Scan: 0
5965 20:15:13.403454
5966 20:15:13.406093 RX Vref 0 -> 0, step: 1
5967 20:15:13.406620
5968 20:15:13.406959 RX Delay -61 -> 252, step: 4
5969 20:15:13.414446 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5970 20:15:13.417276 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5971 20:15:13.420478 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5972 20:15:13.424145 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5973 20:15:13.427398 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5974 20:15:13.433916 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5975 20:15:13.436784 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5976 20:15:13.440525 iDelay=207, Bit 7, Center 96 (7 ~ 186) 180
5977 20:15:13.444168 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5978 20:15:13.446795 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5979 20:15:13.450295 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5980 20:15:13.456774 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5981 20:15:13.460281 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5982 20:15:13.464117 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
5983 20:15:13.467194 iDelay=207, Bit 14, Center 104 (15 ~ 194) 180
5984 20:15:13.473363 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5985 20:15:13.473785 ==
5986 20:15:13.476599 Dram Type= 6, Freq= 0, CH_1, rank 1
5987 20:15:13.480286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5988 20:15:13.480710 ==
5989 20:15:13.481039 DQS Delay:
5990 20:15:13.482916 DQS0 = 0, DQS1 = 0
5991 20:15:13.483332 DQM Delay:
5992 20:15:13.486251 DQM0 = 101, DQM1 = 95
5993 20:15:13.486671 DQ Delay:
5994 20:15:13.489964 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5995 20:15:13.493113 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
5996 20:15:13.496526 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5997 20:15:13.499965 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
5998 20:15:13.500492
5999 20:15:13.500828
6000 20:15:13.509432 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 421 ps
6001 20:15:13.509956 CH1 RK1: MR19=504, MR18=1FB
6002 20:15:13.515654 CH1_RK1: MR19=0x504, MR18=0x1FB, DQSOSC=421, MR23=63, INC=61, DEC=40
6003 20:15:13.519154 [RxdqsGatingPostProcess] freq 933
6004 20:15:13.526060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6005 20:15:13.529732 best DQS0 dly(2T, 0.5T) = (0, 10)
6006 20:15:13.532562 best DQS1 dly(2T, 0.5T) = (0, 10)
6007 20:15:13.535805 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6008 20:15:13.539326 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6009 20:15:13.542120 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 20:15:13.546088 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 20:15:13.548850 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 20:15:13.552158 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 20:15:13.552577 Pre-setting of DQS Precalculation
6014 20:15:13.558820 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6015 20:15:13.565350 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6016 20:15:13.572156 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6017 20:15:13.572589
6018 20:15:13.572923
6019 20:15:13.575369 [Calibration Summary] 1866 Mbps
6020 20:15:13.578592 CH 0, Rank 0
6021 20:15:13.579010 SW Impedance : PASS
6022 20:15:13.581827 DUTY Scan : NO K
6023 20:15:13.585498 ZQ Calibration : PASS
6024 20:15:13.586021 Jitter Meter : NO K
6025 20:15:13.589125 CBT Training : PASS
6026 20:15:13.591829 Write leveling : PASS
6027 20:15:13.592349 RX DQS gating : PASS
6028 20:15:13.595729 RX DQ/DQS(RDDQC) : PASS
6029 20:15:13.599529 TX DQ/DQS : PASS
6030 20:15:13.600099 RX DATLAT : PASS
6031 20:15:13.603365 RX DQ/DQS(Engine): PASS
6032 20:15:13.603949 TX OE : NO K
6033 20:15:13.605838 All Pass.
6034 20:15:13.606259
6035 20:15:13.606590 CH 0, Rank 1
6036 20:15:13.608313 SW Impedance : PASS
6037 20:15:13.612524 DUTY Scan : NO K
6038 20:15:13.613056 ZQ Calibration : PASS
6039 20:15:13.614913 Jitter Meter : NO K
6040 20:15:13.615332 CBT Training : PASS
6041 20:15:13.618439 Write leveling : PASS
6042 20:15:13.621437 RX DQS gating : PASS
6043 20:15:13.621856 RX DQ/DQS(RDDQC) : PASS
6044 20:15:13.625471 TX DQ/DQS : PASS
6045 20:15:13.628077 RX DATLAT : PASS
6046 20:15:13.628597 RX DQ/DQS(Engine): PASS
6047 20:15:13.631437 TX OE : NO K
6048 20:15:13.632001 All Pass.
6049 20:15:13.632342
6050 20:15:13.635562 CH 1, Rank 0
6051 20:15:13.636123 SW Impedance : PASS
6052 20:15:13.638429 DUTY Scan : NO K
6053 20:15:13.641710 ZQ Calibration : PASS
6054 20:15:13.642242 Jitter Meter : NO K
6055 20:15:13.644637 CBT Training : PASS
6056 20:15:13.648198 Write leveling : PASS
6057 20:15:13.648617 RX DQS gating : PASS
6058 20:15:13.651108 RX DQ/DQS(RDDQC) : PASS
6059 20:15:13.654658 TX DQ/DQS : PASS
6060 20:15:13.655176 RX DATLAT : PASS
6061 20:15:13.657959 RX DQ/DQS(Engine): PASS
6062 20:15:13.661187 TX OE : NO K
6063 20:15:13.661717 All Pass.
6064 20:15:13.662056
6065 20:15:13.662370 CH 1, Rank 1
6066 20:15:13.664292 SW Impedance : PASS
6067 20:15:13.667963 DUTY Scan : NO K
6068 20:15:13.668490 ZQ Calibration : PASS
6069 20:15:13.670976 Jitter Meter : NO K
6070 20:15:13.674744 CBT Training : PASS
6071 20:15:13.675268 Write leveling : PASS
6072 20:15:13.677718 RX DQS gating : PASS
6073 20:15:13.681173 RX DQ/DQS(RDDQC) : PASS
6074 20:15:13.681590 TX DQ/DQS : PASS
6075 20:15:13.684301 RX DATLAT : PASS
6076 20:15:13.684720 RX DQ/DQS(Engine): PASS
6077 20:15:13.687349 TX OE : NO K
6078 20:15:13.687806 All Pass.
6079 20:15:13.688144
6080 20:15:13.690981 DramC Write-DBI off
6081 20:15:13.694180 PER_BANK_REFRESH: Hybrid Mode
6082 20:15:13.694602 TX_TRACKING: ON
6083 20:15:13.704365 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6084 20:15:13.707274 [FAST_K] Save calibration result to emmc
6085 20:15:13.711159 dramc_set_vcore_voltage set vcore to 650000
6086 20:15:13.714740 Read voltage for 400, 6
6087 20:15:13.715261 Vio18 = 0
6088 20:15:13.717464 Vcore = 650000
6089 20:15:13.717882 Vdram = 0
6090 20:15:13.718214 Vddq = 0
6091 20:15:13.718523 Vmddr = 0
6092 20:15:13.724212 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6093 20:15:13.730863 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6094 20:15:13.731388 MEM_TYPE=3, freq_sel=20
6095 20:15:13.733811 sv_algorithm_assistance_LP4_800
6096 20:15:13.737210 ============ PULL DRAM RESETB DOWN ============
6097 20:15:13.743601 ========== PULL DRAM RESETB DOWN end =========
6098 20:15:13.746684 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6099 20:15:13.750942 ===================================
6100 20:15:13.753325 LPDDR4 DRAM CONFIGURATION
6101 20:15:13.756595 ===================================
6102 20:15:13.757071 EX_ROW_EN[0] = 0x0
6103 20:15:13.760125 EX_ROW_EN[1] = 0x0
6104 20:15:13.763484 LP4Y_EN = 0x0
6105 20:15:13.764054 WORK_FSP = 0x0
6106 20:15:13.766376 WL = 0x2
6107 20:15:13.766896 RL = 0x2
6108 20:15:13.770772 BL = 0x2
6109 20:15:13.771293 RPST = 0x0
6110 20:15:13.773215 RD_PRE = 0x0
6111 20:15:13.773742 WR_PRE = 0x1
6112 20:15:13.776451 WR_PST = 0x0
6113 20:15:13.776973 DBI_WR = 0x0
6114 20:15:13.779904 DBI_RD = 0x0
6115 20:15:13.780322 OTF = 0x1
6116 20:15:13.782791 ===================================
6117 20:15:13.786452 ===================================
6118 20:15:13.789406 ANA top config
6119 20:15:13.793027 ===================================
6120 20:15:13.793578 DLL_ASYNC_EN = 0
6121 20:15:13.796166 ALL_SLAVE_EN = 1
6122 20:15:13.799524 NEW_RANK_MODE = 1
6123 20:15:13.802975 DLL_IDLE_MODE = 1
6124 20:15:13.806459 LP45_APHY_COMB_EN = 1
6125 20:15:13.806999 TX_ODT_DIS = 1
6126 20:15:13.809575 NEW_8X_MODE = 1
6127 20:15:13.812679 ===================================
6128 20:15:13.816363 ===================================
6129 20:15:13.819502 data_rate = 800
6130 20:15:13.822383 CKR = 1
6131 20:15:13.826305 DQ_P2S_RATIO = 4
6132 20:15:13.829259 ===================================
6133 20:15:13.832517 CA_P2S_RATIO = 4
6134 20:15:13.833042 DQ_CA_OPEN = 0
6135 20:15:13.836326 DQ_SEMI_OPEN = 1
6136 20:15:13.839383 CA_SEMI_OPEN = 1
6137 20:15:13.842741 CA_FULL_RATE = 0
6138 20:15:13.846520 DQ_CKDIV4_EN = 0
6139 20:15:13.849520 CA_CKDIV4_EN = 1
6140 20:15:13.850087 CA_PREDIV_EN = 0
6141 20:15:13.852574 PH8_DLY = 0
6142 20:15:13.856035 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6143 20:15:13.858912 DQ_AAMCK_DIV = 0
6144 20:15:13.862886 CA_AAMCK_DIV = 0
6145 20:15:13.865400 CA_ADMCK_DIV = 4
6146 20:15:13.865868 DQ_TRACK_CA_EN = 0
6147 20:15:13.869273 CA_PICK = 800
6148 20:15:13.871984 CA_MCKIO = 400
6149 20:15:13.875523 MCKIO_SEMI = 400
6150 20:15:13.878743 PLL_FREQ = 3016
6151 20:15:13.881985 DQ_UI_PI_RATIO = 32
6152 20:15:13.885601 CA_UI_PI_RATIO = 32
6153 20:15:13.888395 ===================================
6154 20:15:13.892301 ===================================
6155 20:15:13.895242 memory_type:LPDDR4
6156 20:15:13.895865 GP_NUM : 10
6157 20:15:13.898523 SRAM_EN : 1
6158 20:15:13.899091 MD32_EN : 0
6159 20:15:13.902061 ===================================
6160 20:15:13.905144 [ANA_INIT] >>>>>>>>>>>>>>
6161 20:15:13.908215 <<<<<< [CONFIGURE PHASE]: ANA_TX
6162 20:15:13.912130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6163 20:15:13.914777 ===================================
6164 20:15:13.918303 data_rate = 800,PCW = 0X7400
6165 20:15:13.921046 ===================================
6166 20:15:13.924150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6167 20:15:13.930954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 20:15:13.941017 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6169 20:15:13.944409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6170 20:15:13.947516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6171 20:15:13.954206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6172 20:15:13.954778 [ANA_INIT] flow start
6173 20:15:13.957441 [ANA_INIT] PLL >>>>>>>>
6174 20:15:13.958009 [ANA_INIT] PLL <<<<<<<<
6175 20:15:13.961245 [ANA_INIT] MIDPI >>>>>>>>
6176 20:15:13.964388 [ANA_INIT] MIDPI <<<<<<<<
6177 20:15:13.967393 [ANA_INIT] DLL >>>>>>>>
6178 20:15:13.968005 [ANA_INIT] flow end
6179 20:15:13.971519 ============ LP4 DIFF to SE enter ============
6180 20:15:13.977537 ============ LP4 DIFF to SE exit ============
6181 20:15:13.978091 [ANA_INIT] <<<<<<<<<<<<<
6182 20:15:13.980720 [Flow] Enable top DCM control >>>>>
6183 20:15:13.984011 [Flow] Enable top DCM control <<<<<
6184 20:15:13.987330 Enable DLL master slave shuffle
6185 20:15:13.994268 ==============================================================
6186 20:15:13.997302 Gating Mode config
6187 20:15:14.000251 ==============================================================
6188 20:15:14.003453 Config description:
6189 20:15:14.013621 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6190 20:15:14.020106 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6191 20:15:14.022969 SELPH_MODE 0: By rank 1: By Phase
6192 20:15:14.030072 ==============================================================
6193 20:15:14.032889 GAT_TRACK_EN = 0
6194 20:15:14.036770 RX_GATING_MODE = 2
6195 20:15:14.039584 RX_GATING_TRACK_MODE = 2
6196 20:15:14.043347 SELPH_MODE = 1
6197 20:15:14.043954 PICG_EARLY_EN = 1
6198 20:15:14.046449 VALID_LAT_VALUE = 1
6199 20:15:14.053142 ==============================================================
6200 20:15:14.056539 Enter into Gating configuration >>>>
6201 20:15:14.059801 Exit from Gating configuration <<<<
6202 20:15:14.062823 Enter into DVFS_PRE_config >>>>>
6203 20:15:14.072777 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6204 20:15:14.075938 Exit from DVFS_PRE_config <<<<<
6205 20:15:14.079994 Enter into PICG configuration >>>>
6206 20:15:14.082628 Exit from PICG configuration <<<<
6207 20:15:14.086204 [RX_INPUT] configuration >>>>>
6208 20:15:14.089055 [RX_INPUT] configuration <<<<<
6209 20:15:14.096315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6210 20:15:14.099029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6211 20:15:14.105582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 20:15:14.112372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 20:15:14.118956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 20:15:14.125416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 20:15:14.128430 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6216 20:15:14.132306 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6217 20:15:14.135851 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6218 20:15:14.141830 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6219 20:15:14.145241 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6220 20:15:14.148343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 20:15:14.151963 ===================================
6222 20:15:14.155538 LPDDR4 DRAM CONFIGURATION
6223 20:15:14.158617 ===================================
6224 20:15:14.161454 EX_ROW_EN[0] = 0x0
6225 20:15:14.162023 EX_ROW_EN[1] = 0x0
6226 20:15:14.164988 LP4Y_EN = 0x0
6227 20:15:14.165598 WORK_FSP = 0x0
6228 20:15:14.168459 WL = 0x2
6229 20:15:14.168918 RL = 0x2
6230 20:15:14.172346 BL = 0x2
6231 20:15:14.172901 RPST = 0x0
6232 20:15:14.174719 RD_PRE = 0x0
6233 20:15:14.175179 WR_PRE = 0x1
6234 20:15:14.178161 WR_PST = 0x0
6235 20:15:14.178725 DBI_WR = 0x0
6236 20:15:14.181048 DBI_RD = 0x0
6237 20:15:14.181508 OTF = 0x1
6238 20:15:14.184599 ===================================
6239 20:15:14.190793 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6240 20:15:14.194580 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6241 20:15:14.197797 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6242 20:15:14.201180 ===================================
6243 20:15:14.204261 LPDDR4 DRAM CONFIGURATION
6244 20:15:14.207637 ===================================
6245 20:15:14.211250 EX_ROW_EN[0] = 0x10
6246 20:15:14.211938 EX_ROW_EN[1] = 0x0
6247 20:15:14.214473 LP4Y_EN = 0x0
6248 20:15:14.215032 WORK_FSP = 0x0
6249 20:15:14.217701 WL = 0x2
6250 20:15:14.218177 RL = 0x2
6251 20:15:14.220827 BL = 0x2
6252 20:15:14.221292 RPST = 0x0
6253 20:15:14.223977 RD_PRE = 0x0
6254 20:15:14.224436 WR_PRE = 0x1
6255 20:15:14.228110 WR_PST = 0x0
6256 20:15:14.228573 DBI_WR = 0x0
6257 20:15:14.231197 DBI_RD = 0x0
6258 20:15:14.231867 OTF = 0x1
6259 20:15:14.233973 ===================================
6260 20:15:14.240544 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6261 20:15:14.246271 nWR fixed to 30
6262 20:15:14.248812 [ModeRegInit_LP4] CH0 RK0
6263 20:15:14.249373 [ModeRegInit_LP4] CH0 RK1
6264 20:15:14.251969 [ModeRegInit_LP4] CH1 RK0
6265 20:15:14.255601 [ModeRegInit_LP4] CH1 RK1
6266 20:15:14.256216 match AC timing 19
6267 20:15:14.263006 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6268 20:15:14.265644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6269 20:15:14.269026 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6270 20:15:14.275402 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6271 20:15:14.278529 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6272 20:15:14.279101 ==
6273 20:15:14.282086 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 20:15:14.284637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 20:15:14.285099 ==
6276 20:15:14.291295 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6277 20:15:14.298747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6278 20:15:14.301393 [CA 0] Center 36 (8~64) winsize 57
6279 20:15:14.304922 [CA 1] Center 36 (8~64) winsize 57
6280 20:15:14.308861 [CA 2] Center 36 (8~64) winsize 57
6281 20:15:14.311407 [CA 3] Center 36 (8~64) winsize 57
6282 20:15:14.315216 [CA 4] Center 36 (8~64) winsize 57
6283 20:15:14.318252 [CA 5] Center 36 (8~64) winsize 57
6284 20:15:14.318808
6285 20:15:14.321074 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6286 20:15:14.321537
6287 20:15:14.324222 [CATrainingPosCal] consider 1 rank data
6288 20:15:14.328040 u2DelayCellTimex100 = 270/100 ps
6289 20:15:14.331044 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 20:15:14.334943 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 20:15:14.338256 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 20:15:14.341198 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 20:15:14.344872 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 20:15:14.347959 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 20:15:14.348421
6296 20:15:14.351155 CA PerBit enable=1, Macro0, CA PI delay=36
6297 20:15:14.351755
6298 20:15:14.354563 [CBTSetCACLKResult] CA Dly = 36
6299 20:15:14.357851 CS Dly: 1 (0~32)
6300 20:15:14.358312 ==
6301 20:15:14.361114 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 20:15:14.364699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 20:15:14.365269 ==
6304 20:15:14.371057 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 20:15:14.377895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6306 20:15:14.380971 [CA 0] Center 36 (8~64) winsize 57
6307 20:15:14.384278 [CA 1] Center 36 (8~64) winsize 57
6308 20:15:14.387510 [CA 2] Center 36 (8~64) winsize 57
6309 20:15:14.388143 [CA 3] Center 36 (8~64) winsize 57
6310 20:15:14.391552 [CA 4] Center 36 (8~64) winsize 57
6311 20:15:14.393903 [CA 5] Center 36 (8~64) winsize 57
6312 20:15:14.394366
6313 20:15:14.400487 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6314 20:15:14.401090
6315 20:15:14.403611 [CATrainingPosCal] consider 2 rank data
6316 20:15:14.407499 u2DelayCellTimex100 = 270/100 ps
6317 20:15:14.411012 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 20:15:14.414388 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 20:15:14.417242 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 20:15:14.420597 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 20:15:14.423614 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 20:15:14.427425 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 20:15:14.427966
6324 20:15:14.429995 CA PerBit enable=1, Macro0, CA PI delay=36
6325 20:15:14.430459
6326 20:15:14.433502 [CBTSetCACLKResult] CA Dly = 36
6327 20:15:14.436640 CS Dly: 1 (0~32)
6328 20:15:14.437105
6329 20:15:14.440089 ----->DramcWriteLeveling(PI) begin...
6330 20:15:14.440560 ==
6331 20:15:14.443367 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 20:15:14.447562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 20:15:14.448294 ==
6334 20:15:14.449914 Write leveling (Byte 0): 40 => 8
6335 20:15:14.453161 Write leveling (Byte 1): 32 => 0
6336 20:15:14.456694 DramcWriteLeveling(PI) end<-----
6337 20:15:14.457113
6338 20:15:14.457442 ==
6339 20:15:14.459748 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 20:15:14.463074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 20:15:14.463500 ==
6342 20:15:14.466687 [Gating] SW mode calibration
6343 20:15:14.473386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6344 20:15:14.479470 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6345 20:15:14.482499 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 20:15:14.489389 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6347 20:15:14.492999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 20:15:14.496208 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 20:15:14.503207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 20:15:14.506586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 20:15:14.510185 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 20:15:14.516458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 20:15:14.519895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 20:15:14.522798 Total UI for P1: 0, mck2ui 16
6355 20:15:14.526215 best dqsien dly found for B0: ( 0, 14, 24)
6356 20:15:14.528872 Total UI for P1: 0, mck2ui 16
6357 20:15:14.532539 best dqsien dly found for B1: ( 0, 14, 24)
6358 20:15:14.536162 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6359 20:15:14.539164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6360 20:15:14.540055
6361 20:15:14.542398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 20:15:14.545869 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6363 20:15:14.549095 [Gating] SW calibration Done
6364 20:15:14.549545 ==
6365 20:15:14.552142 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 20:15:14.555596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 20:15:14.559061 ==
6368 20:15:14.559487 RX Vref Scan: 0
6369 20:15:14.559873
6370 20:15:14.562226 RX Vref 0 -> 0, step: 1
6371 20:15:14.562642
6372 20:15:14.565118 RX Delay -410 -> 252, step: 16
6373 20:15:14.569086 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6374 20:15:14.571624 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6375 20:15:14.575393 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6376 20:15:14.582181 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6377 20:15:14.585164 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6378 20:15:14.588431 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6379 20:15:14.591764 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6380 20:15:14.598335 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6381 20:15:14.601949 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6382 20:15:14.604845 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6383 20:15:14.611576 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6384 20:15:14.615519 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6385 20:15:14.618517 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6386 20:15:14.621663 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6387 20:15:14.628214 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6388 20:15:14.631456 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6389 20:15:14.632076 ==
6390 20:15:14.634729 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 20:15:14.637679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 20:15:14.638164 ==
6393 20:15:14.640968 DQS Delay:
6394 20:15:14.641443 DQS0 = 43, DQS1 = 59
6395 20:15:14.645023 DQM Delay:
6396 20:15:14.645612 DQM0 = 10, DQM1 = 12
6397 20:15:14.646104 DQ Delay:
6398 20:15:14.648232 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6399 20:15:14.651124 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6400 20:15:14.654557 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6401 20:15:14.657787 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6402 20:15:14.658293
6403 20:15:14.658767
6404 20:15:14.659217 ==
6405 20:15:14.661164 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 20:15:14.667714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 20:15:14.668299 ==
6408 20:15:14.668781
6409 20:15:14.669228
6410 20:15:14.669671 TX Vref Scan disable
6411 20:15:14.670507 == TX Byte 0 ==
6412 20:15:14.674462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 20:15:14.677183 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 20:15:14.680914 == TX Byte 1 ==
6415 20:15:14.683779 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6416 20:15:14.688231 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6417 20:15:14.690729 ==
6418 20:15:14.694826 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 20:15:14.698035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 20:15:14.698614 ==
6421 20:15:14.699100
6422 20:15:14.699657
6423 20:15:14.700600 TX Vref Scan disable
6424 20:15:14.701007 == TX Byte 0 ==
6425 20:15:14.704054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 20:15:14.710141 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 20:15:14.710757 == TX Byte 1 ==
6428 20:15:14.713713 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6429 20:15:14.720630 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6430 20:15:14.721200
6431 20:15:14.721573 [DATLAT]
6432 20:15:14.721923 Freq=400, CH0 RK0
6433 20:15:14.722263
6434 20:15:14.723241 DATLAT Default: 0xf
6435 20:15:14.727040 0, 0xFFFF, sum = 0
6436 20:15:14.727624 1, 0xFFFF, sum = 0
6437 20:15:14.730549 2, 0xFFFF, sum = 0
6438 20:15:14.731127 3, 0xFFFF, sum = 0
6439 20:15:14.733179 4, 0xFFFF, sum = 0
6440 20:15:14.733662 5, 0xFFFF, sum = 0
6441 20:15:14.737040 6, 0xFFFF, sum = 0
6442 20:15:14.737655 7, 0xFFFF, sum = 0
6443 20:15:14.739987 8, 0xFFFF, sum = 0
6444 20:15:14.740565 9, 0xFFFF, sum = 0
6445 20:15:14.743414 10, 0xFFFF, sum = 0
6446 20:15:14.744056 11, 0xFFFF, sum = 0
6447 20:15:14.746325 12, 0xFFFF, sum = 0
6448 20:15:14.746805 13, 0x0, sum = 1
6449 20:15:14.749657 14, 0x0, sum = 2
6450 20:15:14.750288 15, 0x0, sum = 3
6451 20:15:14.753305 16, 0x0, sum = 4
6452 20:15:14.753840 best_step = 14
6453 20:15:14.754315
6454 20:15:14.754762 ==
6455 20:15:14.756972 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 20:15:14.762983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 20:15:14.763514 ==
6458 20:15:14.764121 RX Vref Scan: 1
6459 20:15:14.764488
6460 20:15:14.766145 RX Vref 0 -> 0, step: 1
6461 20:15:14.766700
6462 20:15:14.769667 RX Delay -359 -> 252, step: 8
6463 20:15:14.770248
6464 20:15:14.772663 Set Vref, RX VrefLevel [Byte0]: 60
6465 20:15:14.776721 [Byte1]: 59
6466 20:15:14.780187
6467 20:15:14.780762 Final RX Vref Byte 0 = 60 to rank0
6468 20:15:14.782762 Final RX Vref Byte 1 = 59 to rank0
6469 20:15:14.786208 Final RX Vref Byte 0 = 60 to rank1
6470 20:15:14.789369 Final RX Vref Byte 1 = 59 to rank1==
6471 20:15:14.792727 Dram Type= 6, Freq= 0, CH_0, rank 0
6472 20:15:14.799812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 20:15:14.800370 ==
6474 20:15:14.800738 DQS Delay:
6475 20:15:14.802846 DQS0 = 48, DQS1 = 64
6476 20:15:14.803403 DQM Delay:
6477 20:15:14.803833 DQM0 = 12, DQM1 = 14
6478 20:15:14.806023 DQ Delay:
6479 20:15:14.808824 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6480 20:15:14.812421 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6481 20:15:14.816108 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6482 20:15:14.818808 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6483 20:15:14.819376
6484 20:15:14.819948
6485 20:15:14.825857 [DQSOSCAuto] RK0, (LSB)MR18= 0xaf70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 388 ps
6486 20:15:14.829146 CH0 RK0: MR19=C0C, MR18=AF70
6487 20:15:14.835374 CH0_RK0: MR19=0xC0C, MR18=0xAF70, DQSOSC=388, MR23=63, INC=392, DEC=261
6488 20:15:14.836013 ==
6489 20:15:14.838929 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 20:15:14.842478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 20:15:14.843052 ==
6492 20:15:14.845460 [Gating] SW mode calibration
6493 20:15:14.851799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6494 20:15:14.859140 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6495 20:15:14.861910 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 20:15:14.865481 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6497 20:15:14.872614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 20:15:14.875842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 20:15:14.878539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 20:15:14.884706 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 20:15:14.888385 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 20:15:14.891437 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 20:15:14.898444 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 20:15:14.901452 Total UI for P1: 0, mck2ui 16
6505 20:15:14.904606 best dqsien dly found for B0: ( 0, 14, 24)
6506 20:15:14.908349 Total UI for P1: 0, mck2ui 16
6507 20:15:14.911263 best dqsien dly found for B1: ( 0, 14, 24)
6508 20:15:14.914833 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6509 20:15:14.918149 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6510 20:15:14.918721
6511 20:15:14.921262 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 20:15:14.924342 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6513 20:15:14.927821 [Gating] SW calibration Done
6514 20:15:14.928291 ==
6515 20:15:14.931268 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 20:15:14.934938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 20:15:14.935524 ==
6518 20:15:14.938577 RX Vref Scan: 0
6519 20:15:14.939145
6520 20:15:14.941315 RX Vref 0 -> 0, step: 1
6521 20:15:14.941781
6522 20:15:14.943845 RX Delay -410 -> 252, step: 16
6523 20:15:14.947607 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6524 20:15:14.950801 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6525 20:15:14.954046 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6526 20:15:14.960304 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6527 20:15:14.964019 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6528 20:15:14.967632 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6529 20:15:14.970783 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6530 20:15:14.976625 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6531 20:15:14.980306 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6532 20:15:14.983498 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6533 20:15:14.990192 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6534 20:15:14.993451 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6535 20:15:14.996658 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6536 20:15:14.999873 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6537 20:15:15.006693 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6538 20:15:15.009540 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6539 20:15:15.010118 ==
6540 20:15:15.013190 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 20:15:15.016106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 20:15:15.016678 ==
6543 20:15:15.019732 DQS Delay:
6544 20:15:15.020301 DQS0 = 43, DQS1 = 59
6545 20:15:15.023225 DQM Delay:
6546 20:15:15.023853 DQM0 = 11, DQM1 = 17
6547 20:15:15.024242 DQ Delay:
6548 20:15:15.026507 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6549 20:15:15.029329 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6550 20:15:15.032460 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6551 20:15:15.035825 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6552 20:15:15.036390
6553 20:15:15.036762
6554 20:15:15.037105 ==
6555 20:15:15.039192 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 20:15:15.045783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 20:15:15.046375 ==
6558 20:15:15.046752
6559 20:15:15.047097
6560 20:15:15.047427 TX Vref Scan disable
6561 20:15:15.048733 == TX Byte 0 ==
6562 20:15:15.052388 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6563 20:15:15.055630 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6564 20:15:15.059602 == TX Byte 1 ==
6565 20:15:15.062318 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6566 20:15:15.068890 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6567 20:15:15.069355 ==
6568 20:15:15.072323 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 20:15:15.075314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 20:15:15.075759 ==
6571 20:15:15.076098
6572 20:15:15.076410
6573 20:15:15.078317 TX Vref Scan disable
6574 20:15:15.078738 == TX Byte 0 ==
6575 20:15:15.081674 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6576 20:15:15.088381 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6577 20:15:15.088802 == TX Byte 1 ==
6578 20:15:15.091336 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6579 20:15:15.098329 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6580 20:15:15.098854
6581 20:15:15.099222 [DATLAT]
6582 20:15:15.099567 Freq=400, CH0 RK1
6583 20:15:15.099944
6584 20:15:15.101547 DATLAT Default: 0xe
6585 20:15:15.105030 0, 0xFFFF, sum = 0
6586 20:15:15.105461 1, 0xFFFF, sum = 0
6587 20:15:15.108361 2, 0xFFFF, sum = 0
6588 20:15:15.108786 3, 0xFFFF, sum = 0
6589 20:15:15.111787 4, 0xFFFF, sum = 0
6590 20:15:15.112213 5, 0xFFFF, sum = 0
6591 20:15:15.114624 6, 0xFFFF, sum = 0
6592 20:15:15.115176 7, 0xFFFF, sum = 0
6593 20:15:15.118305 8, 0xFFFF, sum = 0
6594 20:15:15.118867 9, 0xFFFF, sum = 0
6595 20:15:15.121590 10, 0xFFFF, sum = 0
6596 20:15:15.122154 11, 0xFFFF, sum = 0
6597 20:15:15.124705 12, 0xFFFF, sum = 0
6598 20:15:15.125174 13, 0x0, sum = 1
6599 20:15:15.127818 14, 0x0, sum = 2
6600 20:15:15.128430 15, 0x0, sum = 3
6601 20:15:15.130845 16, 0x0, sum = 4
6602 20:15:15.131321 best_step = 14
6603 20:15:15.131936
6604 20:15:15.132299 ==
6605 20:15:15.134354 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 20:15:15.140742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 20:15:15.141240 ==
6608 20:15:15.141615 RX Vref Scan: 0
6609 20:15:15.141962
6610 20:15:15.144642 RX Vref 0 -> 0, step: 1
6611 20:15:15.145256
6612 20:15:15.147586 RX Delay -359 -> 252, step: 8
6613 20:15:15.154521 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6614 20:15:15.157435 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6615 20:15:15.161597 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6616 20:15:15.164369 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6617 20:15:15.170895 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6618 20:15:15.174097 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6619 20:15:15.177297 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6620 20:15:15.180439 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6621 20:15:15.187603 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6622 20:15:15.190567 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6623 20:15:15.194052 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6624 20:15:15.200491 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6625 20:15:15.203394 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6626 20:15:15.206869 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6627 20:15:15.210560 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6628 20:15:15.216784 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6629 20:15:15.217359 ==
6630 20:15:15.220168 Dram Type= 6, Freq= 0, CH_0, rank 1
6631 20:15:15.223768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 20:15:15.224344 ==
6633 20:15:15.224717 DQS Delay:
6634 20:15:15.226838 DQS0 = 44, DQS1 = 60
6635 20:15:15.227305 DQM Delay:
6636 20:15:15.229820 DQM0 = 8, DQM1 = 14
6637 20:15:15.230284 DQ Delay:
6638 20:15:15.233805 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6639 20:15:15.236910 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6640 20:15:15.240039 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6641 20:15:15.243371 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6642 20:15:15.244006
6643 20:15:15.244386
6644 20:15:15.249866 [DQSOSCAuto] RK1, (LSB)MR18= 0xab38, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6645 20:15:15.253036 CH0 RK1: MR19=C0C, MR18=AB38
6646 20:15:15.259515 CH0_RK1: MR19=0xC0C, MR18=0xAB38, DQSOSC=388, MR23=63, INC=392, DEC=261
6647 20:15:15.263198 [RxdqsGatingPostProcess] freq 400
6648 20:15:15.270080 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6649 20:15:15.272762 best DQS0 dly(2T, 0.5T) = (0, 10)
6650 20:15:15.276379 best DQS1 dly(2T, 0.5T) = (0, 10)
6651 20:15:15.279475 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6652 20:15:15.280129 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6653 20:15:15.282611 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 20:15:15.286198 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 20:15:15.289671 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 20:15:15.293256 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 20:15:15.296365 Pre-setting of DQS Precalculation
6658 20:15:15.302614 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6659 20:15:15.303202 ==
6660 20:15:15.306473 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 20:15:15.309268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 20:15:15.309742 ==
6663 20:15:15.315912 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6664 20:15:15.322859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6665 20:15:15.325501 [CA 0] Center 36 (8~64) winsize 57
6666 20:15:15.325967 [CA 1] Center 36 (8~64) winsize 57
6667 20:15:15.329415 [CA 2] Center 36 (8~64) winsize 57
6668 20:15:15.332367 [CA 3] Center 36 (8~64) winsize 57
6669 20:15:15.335839 [CA 4] Center 36 (8~64) winsize 57
6670 20:15:15.339012 [CA 5] Center 36 (8~64) winsize 57
6671 20:15:15.339578
6672 20:15:15.342500 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6673 20:15:15.343074
6674 20:15:15.348997 [CATrainingPosCal] consider 1 rank data
6675 20:15:15.349571 u2DelayCellTimex100 = 270/100 ps
6676 20:15:15.355240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 20:15:15.358938 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 20:15:15.361854 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 20:15:15.365361 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 20:15:15.368367 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 20:15:15.372020 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 20:15:15.372594
6683 20:15:15.375489 CA PerBit enable=1, Macro0, CA PI delay=36
6684 20:15:15.376127
6685 20:15:15.378644 [CBTSetCACLKResult] CA Dly = 36
6686 20:15:15.381553 CS Dly: 1 (0~32)
6687 20:15:15.382027 ==
6688 20:15:15.385235 Dram Type= 6, Freq= 0, CH_1, rank 1
6689 20:15:15.388536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 20:15:15.389006 ==
6691 20:15:15.394775 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 20:15:15.399120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6693 20:15:15.402559 [CA 0] Center 36 (8~64) winsize 57
6694 20:15:15.404650 [CA 1] Center 36 (8~64) winsize 57
6695 20:15:15.408297 [CA 2] Center 36 (8~64) winsize 57
6696 20:15:15.411124 [CA 3] Center 36 (8~64) winsize 57
6697 20:15:15.415085 [CA 4] Center 36 (8~64) winsize 57
6698 20:15:15.418149 [CA 5] Center 36 (8~64) winsize 57
6699 20:15:15.418707
6700 20:15:15.421848 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6701 20:15:15.422406
6702 20:15:15.424517 [CATrainingPosCal] consider 2 rank data
6703 20:15:15.428323 u2DelayCellTimex100 = 270/100 ps
6704 20:15:15.431156 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 20:15:15.437609 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 20:15:15.441349 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 20:15:15.444491 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 20:15:15.447639 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 20:15:15.450990 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 20:15:15.451548
6711 20:15:15.454570 CA PerBit enable=1, Macro0, CA PI delay=36
6712 20:15:15.455037
6713 20:15:15.457501 [CBTSetCACLKResult] CA Dly = 36
6714 20:15:15.457967 CS Dly: 1 (0~32)
6715 20:15:15.461074
6716 20:15:15.464653 ----->DramcWriteLeveling(PI) begin...
6717 20:15:15.465206 ==
6718 20:15:15.467021 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 20:15:15.471450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 20:15:15.472094 ==
6721 20:15:15.474309 Write leveling (Byte 0): 40 => 8
6722 20:15:15.477657 Write leveling (Byte 1): 32 => 0
6723 20:15:15.480696 DramcWriteLeveling(PI) end<-----
6724 20:15:15.481177
6725 20:15:15.481541 ==
6726 20:15:15.484058 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 20:15:15.487069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 20:15:15.487537 ==
6729 20:15:15.490399 [Gating] SW mode calibration
6730 20:15:15.498105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6731 20:15:15.504021 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6732 20:15:15.507608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 20:15:15.510341 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6734 20:15:15.516645 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 20:15:15.520315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 20:15:15.523461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 20:15:15.529614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 20:15:15.533362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 20:15:15.536267 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 20:15:15.543170 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 20:15:15.543759 Total UI for P1: 0, mck2ui 16
6742 20:15:15.549664 best dqsien dly found for B0: ( 0, 14, 24)
6743 20:15:15.550226 Total UI for P1: 0, mck2ui 16
6744 20:15:15.556269 best dqsien dly found for B1: ( 0, 14, 24)
6745 20:15:15.559537 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6746 20:15:15.563783 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6747 20:15:15.564343
6748 20:15:15.566862 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 20:15:15.569858 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6750 20:15:15.573117 [Gating] SW calibration Done
6751 20:15:15.573677 ==
6752 20:15:15.576302 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 20:15:15.580215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 20:15:15.580798 ==
6755 20:15:15.582838 RX Vref Scan: 0
6756 20:15:15.583303
6757 20:15:15.583694 RX Vref 0 -> 0, step: 1
6758 20:15:15.586663
6759 20:15:15.587125 RX Delay -410 -> 252, step: 16
6760 20:15:15.593005 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6761 20:15:15.596295 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6762 20:15:15.599340 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6763 20:15:15.603113 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6764 20:15:15.609069 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6765 20:15:15.612717 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6766 20:15:15.615735 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6767 20:15:15.619181 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6768 20:15:15.626307 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6769 20:15:15.629171 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6770 20:15:15.632317 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6771 20:15:15.639286 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6772 20:15:15.642533 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6773 20:15:15.645426 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6774 20:15:15.648703 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6775 20:15:15.655319 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6776 20:15:15.655842 ==
6777 20:15:15.658453 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 20:15:15.661868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 20:15:15.662298 ==
6780 20:15:15.662634 DQS Delay:
6781 20:15:15.665372 DQS0 = 43, DQS1 = 51
6782 20:15:15.665888 DQM Delay:
6783 20:15:15.668379 DQM0 = 12, DQM1 = 14
6784 20:15:15.668800 DQ Delay:
6785 20:15:15.672156 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6786 20:15:15.674867 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6787 20:15:15.678885 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6788 20:15:15.682097 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6789 20:15:15.682673
6790 20:15:15.683020
6791 20:15:15.683350 ==
6792 20:15:15.685278 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 20:15:15.688806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 20:15:15.689229 ==
6795 20:15:15.689563
6796 20:15:15.689874
6797 20:15:15.691662 TX Vref Scan disable
6798 20:15:15.694750 == TX Byte 0 ==
6799 20:15:15.698665 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 20:15:15.701258 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 20:15:15.704999 == TX Byte 1 ==
6802 20:15:15.707667 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6803 20:15:15.711846 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6804 20:15:15.712363 ==
6805 20:15:15.715424 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 20:15:15.717867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 20:15:15.721571 ==
6808 20:15:15.722088
6809 20:15:15.722426
6810 20:15:15.722739 TX Vref Scan disable
6811 20:15:15.724671 == TX Byte 0 ==
6812 20:15:15.727957 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 20:15:15.731031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 20:15:15.734902 == TX Byte 1 ==
6815 20:15:15.738151 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6816 20:15:15.741428 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6817 20:15:15.741852
6818 20:15:15.745025 [DATLAT]
6819 20:15:15.745542 Freq=400, CH1 RK0
6820 20:15:15.745882
6821 20:15:15.747280 DATLAT Default: 0xf
6822 20:15:15.747729 0, 0xFFFF, sum = 0
6823 20:15:15.750842 1, 0xFFFF, sum = 0
6824 20:15:15.751271 2, 0xFFFF, sum = 0
6825 20:15:15.753958 3, 0xFFFF, sum = 0
6826 20:15:15.754439 4, 0xFFFF, sum = 0
6827 20:15:15.757590 5, 0xFFFF, sum = 0
6828 20:15:15.758017 6, 0xFFFF, sum = 0
6829 20:15:15.760615 7, 0xFFFF, sum = 0
6830 20:15:15.761040 8, 0xFFFF, sum = 0
6831 20:15:15.765237 9, 0xFFFF, sum = 0
6832 20:15:15.767421 10, 0xFFFF, sum = 0
6833 20:15:15.767894 11, 0xFFFF, sum = 0
6834 20:15:15.771016 12, 0xFFFF, sum = 0
6835 20:15:15.771534 13, 0x0, sum = 1
6836 20:15:15.774544 14, 0x0, sum = 2
6837 20:15:15.775064 15, 0x0, sum = 3
6838 20:15:15.775403 16, 0x0, sum = 4
6839 20:15:15.777374 best_step = 14
6840 20:15:15.777795
6841 20:15:15.778125 ==
6842 20:15:15.780217 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 20:15:15.784165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 20:15:15.784589 ==
6845 20:15:15.787479 RX Vref Scan: 1
6846 20:15:15.787985
6847 20:15:15.790803 RX Vref 0 -> 0, step: 1
6848 20:15:15.791323
6849 20:15:15.791658 RX Delay -343 -> 252, step: 8
6850 20:15:15.792018
6851 20:15:15.794127 Set Vref, RX VrefLevel [Byte0]: 48
6852 20:15:15.797370 [Byte1]: 59
6853 20:15:15.802822
6854 20:15:15.803350 Final RX Vref Byte 0 = 48 to rank0
6855 20:15:15.805888 Final RX Vref Byte 1 = 59 to rank0
6856 20:15:15.808943 Final RX Vref Byte 0 = 48 to rank1
6857 20:15:15.812467 Final RX Vref Byte 1 = 59 to rank1==
6858 20:15:15.816462 Dram Type= 6, Freq= 0, CH_1, rank 0
6859 20:15:15.822128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 20:15:15.822648 ==
6861 20:15:15.822981 DQS Delay:
6862 20:15:15.825392 DQS0 = 44, DQS1 = 56
6863 20:15:15.825812 DQM Delay:
6864 20:15:15.826145 DQM0 = 9, DQM1 = 12
6865 20:15:15.828504 DQ Delay:
6866 20:15:15.832315 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6867 20:15:15.832857 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6868 20:15:15.835494 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6869 20:15:15.838674 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6870 20:15:15.839095
6871 20:15:15.841754
6872 20:15:15.848871 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e65, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6873 20:15:15.851730 CH1 RK0: MR19=C0C, MR18=8E65
6874 20:15:15.858721 CH1_RK0: MR19=0xC0C, MR18=0x8E65, DQSOSC=392, MR23=63, INC=384, DEC=256
6875 20:15:15.859245 ==
6876 20:15:15.861901 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 20:15:15.865127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 20:15:15.865552 ==
6879 20:15:15.869083 [Gating] SW mode calibration
6880 20:15:15.874999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6881 20:15:15.881389 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6882 20:15:15.885148 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 20:15:15.888670 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6884 20:15:15.895835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 20:15:15.898378 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 20:15:15.901524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 20:15:15.908772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 20:15:15.911721 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 20:15:15.914884 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 20:15:15.921291 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 20:15:15.921814 Total UI for P1: 0, mck2ui 16
6892 20:15:15.928054 best dqsien dly found for B0: ( 0, 14, 24)
6893 20:15:15.928478 Total UI for P1: 0, mck2ui 16
6894 20:15:15.931619 best dqsien dly found for B1: ( 0, 14, 24)
6895 20:15:15.937963 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6896 20:15:15.941576 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6897 20:15:15.942095
6898 20:15:15.944352 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 20:15:15.947713 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6900 20:15:15.950962 [Gating] SW calibration Done
6901 20:15:15.951381 ==
6902 20:15:15.954591 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 20:15:15.957147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 20:15:15.957573 ==
6905 20:15:15.960728 RX Vref Scan: 0
6906 20:15:15.961149
6907 20:15:15.961484 RX Vref 0 -> 0, step: 1
6908 20:15:15.963773
6909 20:15:15.964193 RX Delay -410 -> 252, step: 16
6910 20:15:15.970431 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6911 20:15:15.974024 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6912 20:15:15.977161 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6913 20:15:15.980519 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6914 20:15:15.987181 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6915 20:15:15.990496 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6916 20:15:15.993385 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6917 20:15:16.000530 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6918 20:15:16.004015 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6919 20:15:16.006917 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6920 20:15:16.010146 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6921 20:15:16.016645 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6922 20:15:16.019778 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6923 20:15:16.023042 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6924 20:15:16.027076 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6925 20:15:16.033211 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6926 20:15:16.033695 ==
6927 20:15:16.036274 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 20:15:16.040104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 20:15:16.040625 ==
6930 20:15:16.040968 DQS Delay:
6931 20:15:16.043268 DQS0 = 51, DQS1 = 51
6932 20:15:16.043717 DQM Delay:
6933 20:15:16.046531 DQM0 = 20, DQM1 = 14
6934 20:15:16.047084 DQ Delay:
6935 20:15:16.049633 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6936 20:15:16.053011 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6937 20:15:16.056152 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6938 20:15:16.059998 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6939 20:15:16.060423
6940 20:15:16.060759
6941 20:15:16.061071 ==
6942 20:15:16.062992 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 20:15:16.066611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 20:15:16.069135 ==
6945 20:15:16.069556
6946 20:15:16.069886
6947 20:15:16.070265 TX Vref Scan disable
6948 20:15:16.072915 == TX Byte 0 ==
6949 20:15:16.076055 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6950 20:15:16.079480 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6951 20:15:16.082962 == TX Byte 1 ==
6952 20:15:16.087896 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6953 20:15:16.089083 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6954 20:15:16.089504 ==
6955 20:15:16.092693 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 20:15:16.096058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 20:15:16.098831 ==
6958 20:15:16.099385
6959 20:15:16.099825
6960 20:15:16.100151 TX Vref Scan disable
6961 20:15:16.102587 == TX Byte 0 ==
6962 20:15:16.106524 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6963 20:15:16.109847 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6964 20:15:16.112592 == TX Byte 1 ==
6965 20:15:16.115838 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6966 20:15:16.118972 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6967 20:15:16.119393
6968 20:15:16.122898 [DATLAT]
6969 20:15:16.123409 Freq=400, CH1 RK1
6970 20:15:16.123783
6971 20:15:16.125296 DATLAT Default: 0xe
6972 20:15:16.125764 0, 0xFFFF, sum = 0
6973 20:15:16.129626 1, 0xFFFF, sum = 0
6974 20:15:16.130051 2, 0xFFFF, sum = 0
6975 20:15:16.132414 3, 0xFFFF, sum = 0
6976 20:15:16.132842 4, 0xFFFF, sum = 0
6977 20:15:16.135458 5, 0xFFFF, sum = 0
6978 20:15:16.135918 6, 0xFFFF, sum = 0
6979 20:15:16.139101 7, 0xFFFF, sum = 0
6980 20:15:16.139650 8, 0xFFFF, sum = 0
6981 20:15:16.142830 9, 0xFFFF, sum = 0
6982 20:15:16.143354 10, 0xFFFF, sum = 0
6983 20:15:16.145737 11, 0xFFFF, sum = 0
6984 20:15:16.148666 12, 0xFFFF, sum = 0
6985 20:15:16.149187 13, 0x0, sum = 1
6986 20:15:16.149535 14, 0x0, sum = 2
6987 20:15:16.152086 15, 0x0, sum = 3
6988 20:15:16.152609 16, 0x0, sum = 4
6989 20:15:16.156948 best_step = 14
6990 20:15:16.157524
6991 20:15:16.158089 ==
6992 20:15:16.158774 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 20:15:16.161613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 20:15:16.162047 ==
6995 20:15:16.165465 RX Vref Scan: 0
6996 20:15:16.166010
6997 20:15:16.166351 RX Vref 0 -> 0, step: 1
6998 20:15:16.168570
6999 20:15:16.169084 RX Delay -343 -> 252, step: 8
7000 20:15:16.176597 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7001 20:15:16.180619 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7002 20:15:16.183544 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7003 20:15:16.189931 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7004 20:15:16.193424 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7005 20:15:16.197172 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7006 20:15:16.199791 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7007 20:15:16.206610 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7008 20:15:16.210060 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7009 20:15:16.213125 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7010 20:15:16.216605 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
7011 20:15:16.222611 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7012 20:15:16.226243 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7013 20:15:16.229433 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7014 20:15:16.232630 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7015 20:15:16.240183 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7016 20:15:16.240745 ==
7017 20:15:16.242601 Dram Type= 6, Freq= 0, CH_1, rank 1
7018 20:15:16.245954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7019 20:15:16.246518 ==
7020 20:15:16.249201 DQS Delay:
7021 20:15:16.249664 DQS0 = 44, DQS1 = 56
7022 20:15:16.250035 DQM Delay:
7023 20:15:16.252237 DQM0 = 10, DQM1 = 12
7024 20:15:16.252699 DQ Delay:
7025 20:15:16.255788 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7026 20:15:16.258941 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7027 20:15:16.262622 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7028 20:15:16.266058 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7029 20:15:16.266616
7030 20:15:16.266986
7031 20:15:16.275418 [DQSOSCAuto] RK1, (LSB)MR18= 0x6554, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7032 20:15:16.276021 CH1 RK1: MR19=C0C, MR18=6554
7033 20:15:16.282520 CH1_RK1: MR19=0xC0C, MR18=0x6554, DQSOSC=397, MR23=63, INC=374, DEC=249
7034 20:15:16.286182 [RxdqsGatingPostProcess] freq 400
7035 20:15:16.292019 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7036 20:15:16.295273 best DQS0 dly(2T, 0.5T) = (0, 10)
7037 20:15:16.298872 best DQS1 dly(2T, 0.5T) = (0, 10)
7038 20:15:16.302633 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7039 20:15:16.305205 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7040 20:15:16.308257 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 20:15:16.311600 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 20:15:16.315532 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 20:15:16.318598 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 20:15:16.319160 Pre-setting of DQS Precalculation
7045 20:15:16.325028 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7046 20:15:16.331266 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7047 20:15:16.338201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7048 20:15:16.338778
7049 20:15:16.339151
7050 20:15:16.341479 [Calibration Summary] 800 Mbps
7051 20:15:16.344862 CH 0, Rank 0
7052 20:15:16.345425 SW Impedance : PASS
7053 20:15:16.348323 DUTY Scan : NO K
7054 20:15:16.351556 ZQ Calibration : PASS
7055 20:15:16.352162 Jitter Meter : NO K
7056 20:15:16.354143 CBT Training : PASS
7057 20:15:16.357485 Write leveling : PASS
7058 20:15:16.358054 RX DQS gating : PASS
7059 20:15:16.360522 RX DQ/DQS(RDDQC) : PASS
7060 20:15:16.364253 TX DQ/DQS : PASS
7061 20:15:16.364719 RX DATLAT : PASS
7062 20:15:16.367276 RX DQ/DQS(Engine): PASS
7063 20:15:16.370788 TX OE : NO K
7064 20:15:16.371360 All Pass.
7065 20:15:16.371789
7066 20:15:16.372149 CH 0, Rank 1
7067 20:15:16.374026 SW Impedance : PASS
7068 20:15:16.377794 DUTY Scan : NO K
7069 20:15:16.378368 ZQ Calibration : PASS
7070 20:15:16.380374 Jitter Meter : NO K
7071 20:15:16.383970 CBT Training : PASS
7072 20:15:16.384438 Write leveling : NO K
7073 20:15:16.387021 RX DQS gating : PASS
7074 20:15:16.387486 RX DQ/DQS(RDDQC) : PASS
7075 20:15:16.390460 TX DQ/DQS : PASS
7076 20:15:16.393614 RX DATLAT : PASS
7077 20:15:16.394081 RX DQ/DQS(Engine): PASS
7078 20:15:16.397573 TX OE : NO K
7079 20:15:16.398143 All Pass.
7080 20:15:16.398519
7081 20:15:16.400851 CH 1, Rank 0
7082 20:15:16.401423 SW Impedance : PASS
7083 20:15:16.404115 DUTY Scan : NO K
7084 20:15:16.407357 ZQ Calibration : PASS
7085 20:15:16.407971 Jitter Meter : NO K
7086 20:15:16.410372 CBT Training : PASS
7087 20:15:16.413314 Write leveling : PASS
7088 20:15:16.413787 RX DQS gating : PASS
7089 20:15:16.417186 RX DQ/DQS(RDDQC) : PASS
7090 20:15:16.420493 TX DQ/DQS : PASS
7091 20:15:16.420966 RX DATLAT : PASS
7092 20:15:16.423941 RX DQ/DQS(Engine): PASS
7093 20:15:16.427184 TX OE : NO K
7094 20:15:16.427843 All Pass.
7095 20:15:16.428244
7096 20:15:16.428600 CH 1, Rank 1
7097 20:15:16.430170 SW Impedance : PASS
7098 20:15:16.433112 DUTY Scan : NO K
7099 20:15:16.433595 ZQ Calibration : PASS
7100 20:15:16.436628 Jitter Meter : NO K
7101 20:15:16.439863 CBT Training : PASS
7102 20:15:16.440332 Write leveling : NO K
7103 20:15:16.443794 RX DQS gating : PASS
7104 20:15:16.446624 RX DQ/DQS(RDDQC) : PASS
7105 20:15:16.447186 TX DQ/DQS : PASS
7106 20:15:16.450252 RX DATLAT : PASS
7107 20:15:16.453901 RX DQ/DQS(Engine): PASS
7108 20:15:16.454496 TX OE : NO K
7109 20:15:16.454877 All Pass.
7110 20:15:16.455222
7111 20:15:16.456841 DramC Write-DBI off
7112 20:15:16.459743 PER_BANK_REFRESH: Hybrid Mode
7113 20:15:16.460210 TX_TRACKING: ON
7114 20:15:16.470380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7115 20:15:16.474689 [FAST_K] Save calibration result to emmc
7116 20:15:16.476439 dramc_set_vcore_voltage set vcore to 725000
7117 20:15:16.480016 Read voltage for 1600, 0
7118 20:15:16.480583 Vio18 = 0
7119 20:15:16.483335 Vcore = 725000
7120 20:15:16.483938 Vdram = 0
7121 20:15:16.484318 Vddq = 0
7122 20:15:16.484667 Vmddr = 0
7123 20:15:16.489924 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7124 20:15:16.496123 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7125 20:15:16.496690 MEM_TYPE=3, freq_sel=13
7126 20:15:16.500027 sv_algorithm_assistance_LP4_3733
7127 20:15:16.502901 ============ PULL DRAM RESETB DOWN ============
7128 20:15:16.510939 ========== PULL DRAM RESETB DOWN end =========
7129 20:15:16.512390 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7130 20:15:16.516322 ===================================
7131 20:15:16.519547 LPDDR4 DRAM CONFIGURATION
7132 20:15:16.522945 ===================================
7133 20:15:16.523512 EX_ROW_EN[0] = 0x0
7134 20:15:16.525813 EX_ROW_EN[1] = 0x0
7135 20:15:16.529029 LP4Y_EN = 0x0
7136 20:15:16.529575 WORK_FSP = 0x1
7137 20:15:16.532355 WL = 0x5
7138 20:15:16.532825 RL = 0x5
7139 20:15:16.536449 BL = 0x2
7140 20:15:16.537013 RPST = 0x0
7141 20:15:16.538954 RD_PRE = 0x0
7142 20:15:16.539423 WR_PRE = 0x1
7143 20:15:16.542326 WR_PST = 0x1
7144 20:15:16.542885 DBI_WR = 0x0
7145 20:15:16.546427 DBI_RD = 0x0
7146 20:15:16.546992 OTF = 0x1
7147 20:15:16.549387 ===================================
7148 20:15:16.552324 ===================================
7149 20:15:16.555660 ANA top config
7150 20:15:16.559194 ===================================
7151 20:15:16.559911 DLL_ASYNC_EN = 0
7152 20:15:16.562231 ALL_SLAVE_EN = 0
7153 20:15:16.565354 NEW_RANK_MODE = 1
7154 20:15:16.568465 DLL_IDLE_MODE = 1
7155 20:15:16.571909 LP45_APHY_COMB_EN = 1
7156 20:15:16.572377 TX_ODT_DIS = 0
7157 20:15:16.575640 NEW_8X_MODE = 1
7158 20:15:16.578831 ===================================
7159 20:15:16.581855 ===================================
7160 20:15:16.585411 data_rate = 3200
7161 20:15:16.588654 CKR = 1
7162 20:15:16.592448 DQ_P2S_RATIO = 8
7163 20:15:16.595856 ===================================
7164 20:15:16.598701 CA_P2S_RATIO = 8
7165 20:15:16.599272 DQ_CA_OPEN = 0
7166 20:15:16.602299 DQ_SEMI_OPEN = 0
7167 20:15:16.605363 CA_SEMI_OPEN = 0
7168 20:15:16.608394 CA_FULL_RATE = 0
7169 20:15:16.611942 DQ_CKDIV4_EN = 0
7170 20:15:16.614933 CA_CKDIV4_EN = 0
7171 20:15:16.615502 CA_PREDIV_EN = 0
7172 20:15:16.618464 PH8_DLY = 12
7173 20:15:16.621529 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7174 20:15:16.625622 DQ_AAMCK_DIV = 4
7175 20:15:16.628318 CA_AAMCK_DIV = 4
7176 20:15:16.631816 CA_ADMCK_DIV = 4
7177 20:15:16.632381 DQ_TRACK_CA_EN = 0
7178 20:15:16.635377 CA_PICK = 1600
7179 20:15:16.639217 CA_MCKIO = 1600
7180 20:15:16.641409 MCKIO_SEMI = 0
7181 20:15:16.644842 PLL_FREQ = 3068
7182 20:15:16.647791 DQ_UI_PI_RATIO = 32
7183 20:15:16.650922 CA_UI_PI_RATIO = 0
7184 20:15:16.655018 ===================================
7185 20:15:16.658003 ===================================
7186 20:15:16.658478 memory_type:LPDDR4
7187 20:15:16.660906 GP_NUM : 10
7188 20:15:16.664179 SRAM_EN : 1
7189 20:15:16.664642 MD32_EN : 0
7190 20:15:16.668346 ===================================
7191 20:15:16.671065 [ANA_INIT] >>>>>>>>>>>>>>
7192 20:15:16.674610 <<<<<< [CONFIGURE PHASE]: ANA_TX
7193 20:15:16.677885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7194 20:15:16.681142 ===================================
7195 20:15:16.684389 data_rate = 3200,PCW = 0X7600
7196 20:15:16.687457 ===================================
7197 20:15:16.690823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7198 20:15:16.694151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 20:15:16.700848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7200 20:15:16.704165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7201 20:15:16.710754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7202 20:15:16.713758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7203 20:15:16.714347 [ANA_INIT] flow start
7204 20:15:16.717062 [ANA_INIT] PLL >>>>>>>>
7205 20:15:16.720830 [ANA_INIT] PLL <<<<<<<<
7206 20:15:16.721313 [ANA_INIT] MIDPI >>>>>>>>
7207 20:15:16.723816 [ANA_INIT] MIDPI <<<<<<<<
7208 20:15:16.727250 [ANA_INIT] DLL >>>>>>>>
7209 20:15:16.727829 [ANA_INIT] DLL <<<<<<<<
7210 20:15:16.730442 [ANA_INIT] flow end
7211 20:15:16.733563 ============ LP4 DIFF to SE enter ============
7212 20:15:16.740103 ============ LP4 DIFF to SE exit ============
7213 20:15:16.740531 [ANA_INIT] <<<<<<<<<<<<<
7214 20:15:16.743345 [Flow] Enable top DCM control >>>>>
7215 20:15:16.747023 [Flow] Enable top DCM control <<<<<
7216 20:15:16.749842 Enable DLL master slave shuffle
7217 20:15:16.756498 ==============================================================
7218 20:15:16.757052 Gating Mode config
7219 20:15:16.763398 ==============================================================
7220 20:15:16.766133 Config description:
7221 20:15:16.776269 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7222 20:15:16.783627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7223 20:15:16.786513 SELPH_MODE 0: By rank 1: By Phase
7224 20:15:16.792780 ==============================================================
7225 20:15:16.795868 GAT_TRACK_EN = 1
7226 20:15:16.799564 RX_GATING_MODE = 2
7227 20:15:16.800170 RX_GATING_TRACK_MODE = 2
7228 20:15:16.803046 SELPH_MODE = 1
7229 20:15:16.806144 PICG_EARLY_EN = 1
7230 20:15:16.809330 VALID_LAT_VALUE = 1
7231 20:15:16.816162 ==============================================================
7232 20:15:16.819451 Enter into Gating configuration >>>>
7233 20:15:16.822964 Exit from Gating configuration <<<<
7234 20:15:16.826011 Enter into DVFS_PRE_config >>>>>
7235 20:15:16.835367 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7236 20:15:16.839519 Exit from DVFS_PRE_config <<<<<
7237 20:15:16.843164 Enter into PICG configuration >>>>
7238 20:15:16.846019 Exit from PICG configuration <<<<
7239 20:15:16.848803 [RX_INPUT] configuration >>>>>
7240 20:15:16.851788 [RX_INPUT] configuration <<<<<
7241 20:15:16.855422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7242 20:15:16.862511 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7243 20:15:16.869085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 20:15:16.875223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 20:15:16.882167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 20:15:16.885364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 20:15:16.892169 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7248 20:15:16.895637 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7249 20:15:16.898036 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7250 20:15:16.901462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7251 20:15:16.908288 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7252 20:15:16.912076 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 20:15:16.915850 ===================================
7254 20:15:16.917762 LPDDR4 DRAM CONFIGURATION
7255 20:15:16.921316 ===================================
7256 20:15:16.921893 EX_ROW_EN[0] = 0x0
7257 20:15:16.924594 EX_ROW_EN[1] = 0x0
7258 20:15:16.925175 LP4Y_EN = 0x0
7259 20:15:16.928107 WORK_FSP = 0x1
7260 20:15:16.930977 WL = 0x5
7261 20:15:16.931443 RL = 0x5
7262 20:15:16.934845 BL = 0x2
7263 20:15:16.935311 RPST = 0x0
7264 20:15:16.938471 RD_PRE = 0x0
7265 20:15:16.939134 WR_PRE = 0x1
7266 20:15:16.941538 WR_PST = 0x1
7267 20:15:16.942003 DBI_WR = 0x0
7268 20:15:16.945136 DBI_RD = 0x0
7269 20:15:16.945600 OTF = 0x1
7270 20:15:16.947641 ===================================
7271 20:15:16.951306 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7272 20:15:16.957512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7273 20:15:16.961326 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7274 20:15:16.963892 ===================================
7275 20:15:16.967556 LPDDR4 DRAM CONFIGURATION
7276 20:15:16.971370 ===================================
7277 20:15:16.972005 EX_ROW_EN[0] = 0x10
7278 20:15:16.974279 EX_ROW_EN[1] = 0x0
7279 20:15:16.977333 LP4Y_EN = 0x0
7280 20:15:16.977905 WORK_FSP = 0x1
7281 20:15:16.980554 WL = 0x5
7282 20:15:16.981021 RL = 0x5
7283 20:15:16.983613 BL = 0x2
7284 20:15:16.984182 RPST = 0x0
7285 20:15:16.986867 RD_PRE = 0x0
7286 20:15:16.987334 WR_PRE = 0x1
7287 20:15:16.990895 WR_PST = 0x1
7288 20:15:16.991423 DBI_WR = 0x0
7289 20:15:16.993779 DBI_RD = 0x0
7290 20:15:16.994245 OTF = 0x1
7291 20:15:16.997866 ===================================
7292 20:15:17.004293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7293 20:15:17.004883 ==
7294 20:15:17.007235 Dram Type= 6, Freq= 0, CH_0, rank 0
7295 20:15:17.009825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 20:15:17.013582 ==
7297 20:15:17.014155 [Duty_Offset_Calibration]
7298 20:15:17.016903 B0:1 B1:-1 CA:0
7299 20:15:17.017474
7300 20:15:17.020074 [DutyScan_Calibration_Flow] k_type=0
7301 20:15:17.029087
7302 20:15:17.029707 ==CLK 0==
7303 20:15:17.032573 Final CLK duty delay cell = 0
7304 20:15:17.035912 [0] MAX Duty = 5125%(X100), DQS PI = 20
7305 20:15:17.038972 [0] MIN Duty = 4907%(X100), DQS PI = 6
7306 20:15:17.039597 [0] AVG Duty = 5016%(X100)
7307 20:15:17.042114
7308 20:15:17.045479 CH0 CLK Duty spec in!! Max-Min= 218%
7309 20:15:17.049255 [DutyScan_Calibration_Flow] ====Done====
7310 20:15:17.049726
7311 20:15:17.052087 [DutyScan_Calibration_Flow] k_type=1
7312 20:15:17.068134
7313 20:15:17.068702 ==DQS 0 ==
7314 20:15:17.071208 Final DQS duty delay cell = -4
7315 20:15:17.074592 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7316 20:15:17.078183 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7317 20:15:17.081238 [-4] AVG Duty = 4906%(X100)
7318 20:15:17.081658
7319 20:15:17.081991 ==DQS 1 ==
7320 20:15:17.084138 Final DQS duty delay cell = 0
7321 20:15:17.087504 [0] MAX Duty = 5156%(X100), DQS PI = 0
7322 20:15:17.091374 [0] MIN Duty = 5031%(X100), DQS PI = 18
7323 20:15:17.094076 [0] AVG Duty = 5093%(X100)
7324 20:15:17.094378
7325 20:15:17.097755 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7326 20:15:17.097979
7327 20:15:17.100936 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7328 20:15:17.104131 [DutyScan_Calibration_Flow] ====Done====
7329 20:15:17.104353
7330 20:15:17.107493 [DutyScan_Calibration_Flow] k_type=3
7331 20:15:17.125860
7332 20:15:17.126164 ==DQM 0 ==
7333 20:15:17.128584 Final DQM duty delay cell = 0
7334 20:15:17.132447 [0] MAX Duty = 5124%(X100), DQS PI = 20
7335 20:15:17.135212 [0] MIN Duty = 4875%(X100), DQS PI = 10
7336 20:15:17.138580 [0] AVG Duty = 4999%(X100)
7337 20:15:17.138801
7338 20:15:17.138977 ==DQM 1 ==
7339 20:15:17.142176 Final DQM duty delay cell = 0
7340 20:15:17.144989 [0] MAX Duty = 5000%(X100), DQS PI = 4
7341 20:15:17.148568 [0] MIN Duty = 4813%(X100), DQS PI = 20
7342 20:15:17.151512 [0] AVG Duty = 4906%(X100)
7343 20:15:17.151759
7344 20:15:17.154703 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7345 20:15:17.154925
7346 20:15:17.157726 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7347 20:15:17.161173 [DutyScan_Calibration_Flow] ====Done====
7348 20:15:17.161394
7349 20:15:17.164659 [DutyScan_Calibration_Flow] k_type=2
7350 20:15:17.181994
7351 20:15:17.182308 ==DQ 0 ==
7352 20:15:17.185447 Final DQ duty delay cell = -4
7353 20:15:17.188208 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7354 20:15:17.191238 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7355 20:15:17.195098 [-4] AVG Duty = 4953%(X100)
7356 20:15:17.195322
7357 20:15:17.195497 ==DQ 1 ==
7358 20:15:17.197743 Final DQ duty delay cell = 0
7359 20:15:17.201518 [0] MAX Duty = 5125%(X100), DQS PI = 2
7360 20:15:17.204908 [0] MIN Duty = 5000%(X100), DQS PI = 36
7361 20:15:17.207697 [0] AVG Duty = 5062%(X100)
7362 20:15:17.207920
7363 20:15:17.211580 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7364 20:15:17.211820
7365 20:15:17.214901 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7366 20:15:17.218039 [DutyScan_Calibration_Flow] ====Done====
7367 20:15:17.218260 ==
7368 20:15:17.221093 Dram Type= 6, Freq= 0, CH_1, rank 0
7369 20:15:17.224678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7370 20:15:17.224907 ==
7371 20:15:17.227972 [Duty_Offset_Calibration]
7372 20:15:17.228194 B0:-1 B1:1 CA:1
7373 20:15:17.231224
7374 20:15:17.233790 [DutyScan_Calibration_Flow] k_type=0
7375 20:15:17.242976
7376 20:15:17.243197 ==CLK 0==
7377 20:15:17.245224 Final CLK duty delay cell = 0
7378 20:15:17.248593 [0] MAX Duty = 5187%(X100), DQS PI = 22
7379 20:15:17.252148 [0] MIN Duty = 5000%(X100), DQS PI = 0
7380 20:15:17.255372 [0] AVG Duty = 5093%(X100)
7381 20:15:17.255593
7382 20:15:17.258709 CH1 CLK Duty spec in!! Max-Min= 187%
7383 20:15:17.261559 [DutyScan_Calibration_Flow] ====Done====
7384 20:15:17.261779
7385 20:15:17.265219 [DutyScan_Calibration_Flow] k_type=1
7386 20:15:17.282045
7387 20:15:17.282373 ==DQS 0 ==
7388 20:15:17.285512 Final DQS duty delay cell = 0
7389 20:15:17.288175 [0] MAX Duty = 5124%(X100), DQS PI = 18
7390 20:15:17.291586 [0] MIN Duty = 4907%(X100), DQS PI = 8
7391 20:15:17.294791 [0] AVG Duty = 5015%(X100)
7392 20:15:17.295096
7393 20:15:17.295332 ==DQS 1 ==
7394 20:15:17.298256 Final DQS duty delay cell = 0
7395 20:15:17.301432 [0] MAX Duty = 5093%(X100), DQS PI = 24
7396 20:15:17.305041 [0] MIN Duty = 4969%(X100), DQS PI = 56
7397 20:15:17.308051 [0] AVG Duty = 5031%(X100)
7398 20:15:17.308229
7399 20:15:17.311631 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7400 20:15:17.311798
7401 20:15:17.314562 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7402 20:15:17.317970 [DutyScan_Calibration_Flow] ====Done====
7403 20:15:17.318098
7404 20:15:17.322060 [DutyScan_Calibration_Flow] k_type=3
7405 20:15:17.338471
7406 20:15:17.338554 ==DQM 0 ==
7407 20:15:17.341932 Final DQM duty delay cell = 0
7408 20:15:17.345045 [0] MAX Duty = 5218%(X100), DQS PI = 18
7409 20:15:17.348973 [0] MIN Duty = 5031%(X100), DQS PI = 8
7410 20:15:17.351343 [0] AVG Duty = 5124%(X100)
7411 20:15:17.351425
7412 20:15:17.351491 ==DQM 1 ==
7413 20:15:17.355365 Final DQM duty delay cell = 0
7414 20:15:17.358177 [0] MAX Duty = 5156%(X100), DQS PI = 6
7415 20:15:17.361791 [0] MIN Duty = 5000%(X100), DQS PI = 28
7416 20:15:17.364890 [0] AVG Duty = 5078%(X100)
7417 20:15:17.364973
7418 20:15:17.367796 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7419 20:15:17.367879
7420 20:15:17.371146 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7421 20:15:17.375168 [DutyScan_Calibration_Flow] ====Done====
7422 20:15:17.375251
7423 20:15:17.377865 [DutyScan_Calibration_Flow] k_type=2
7424 20:15:17.395307
7425 20:15:17.395391 ==DQ 0 ==
7426 20:15:17.398607 Final DQ duty delay cell = 0
7427 20:15:17.402878 [0] MAX Duty = 5156%(X100), DQS PI = 28
7428 20:15:17.405127 [0] MIN Duty = 4906%(X100), DQS PI = 10
7429 20:15:17.405214 [0] AVG Duty = 5031%(X100)
7430 20:15:17.408339
7431 20:15:17.408443 ==DQ 1 ==
7432 20:15:17.411778 Final DQ duty delay cell = 0
7433 20:15:17.414887 [0] MAX Duty = 5156%(X100), DQS PI = 10
7434 20:15:17.418263 [0] MIN Duty = 4969%(X100), DQS PI = 56
7435 20:15:17.418347 [0] AVG Duty = 5062%(X100)
7436 20:15:17.421741
7437 20:15:17.424715 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7438 20:15:17.424799
7439 20:15:17.428063 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7440 20:15:17.431462 [DutyScan_Calibration_Flow] ====Done====
7441 20:15:17.435215 nWR fixed to 30
7442 20:15:17.435299 [ModeRegInit_LP4] CH0 RK0
7443 20:15:17.437983 [ModeRegInit_LP4] CH0 RK1
7444 20:15:17.441936 [ModeRegInit_LP4] CH1 RK0
7445 20:15:17.444743 [ModeRegInit_LP4] CH1 RK1
7446 20:15:17.444827 match AC timing 5
7447 20:15:17.451840 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7448 20:15:17.454852 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7449 20:15:17.457812 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7450 20:15:17.464540 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7451 20:15:17.467630 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7452 20:15:17.467757 [MiockJmeterHQA]
7453 20:15:17.467849
7454 20:15:17.471310 [DramcMiockJmeter] u1RxGatingPI = 0
7455 20:15:17.474779 0 : 4253, 4026
7456 20:15:17.474886 4 : 4363, 4137
7457 20:15:17.477654 8 : 4254, 4029
7458 20:15:17.477783 12 : 4253, 4027
7459 20:15:17.481096 16 : 4253, 4026
7460 20:15:17.481206 20 : 4252, 4027
7461 20:15:17.481293 24 : 4252, 4026
7462 20:15:17.484295 28 : 4258, 4029
7463 20:15:17.484437 32 : 4252, 4027
7464 20:15:17.487417 36 : 4365, 4140
7465 20:15:17.487557 40 : 4366, 4140
7466 20:15:17.490690 44 : 4253, 4029
7467 20:15:17.490839 48 : 4255, 4029
7468 20:15:17.494221 52 : 4360, 4138
7469 20:15:17.494341 56 : 4252, 4027
7470 20:15:17.494434 60 : 4360, 4138
7471 20:15:17.497371 64 : 4254, 4030
7472 20:15:17.497486 68 : 4255, 4029
7473 20:15:17.500974 72 : 4250, 4027
7474 20:15:17.501101 76 : 4250, 4026
7475 20:15:17.505157 80 : 4255, 4029
7476 20:15:17.505383 84 : 4250, 4027
7477 20:15:17.507205 88 : 4363, 4139
7478 20:15:17.507386 92 : 4360, 468
7479 20:15:17.507518 96 : 4252, 0
7480 20:15:17.510954 100 : 4249, 0
7481 20:15:17.511200 104 : 4252, 0
7482 20:15:17.514440 108 : 4250, 0
7483 20:15:17.514713 112 : 4255, 0
7484 20:15:17.514875 116 : 4254, 0
7485 20:15:17.517385 120 : 4252, 0
7486 20:15:17.517655 124 : 4250, 0
7487 20:15:17.517813 128 : 4361, 0
7488 20:15:17.521035 132 : 4365, 0
7489 20:15:17.521421 136 : 4363, 0
7490 20:15:17.524293 140 : 4252, 0
7491 20:15:17.524564 144 : 4250, 0
7492 20:15:17.524775 148 : 4363, 0
7493 20:15:17.527184 152 : 4253, 0
7494 20:15:17.527440 156 : 4249, 0
7495 20:15:17.530261 160 : 4255, 0
7496 20:15:17.530589 164 : 4255, 0
7497 20:15:17.530853 168 : 4360, 0
7498 20:15:17.533870 172 : 4250, 0
7499 20:15:17.534195 176 : 4250, 0
7500 20:15:17.537235 180 : 4361, 0
7501 20:15:17.537709 184 : 4361, 0
7502 20:15:17.538222 188 : 4365, 0
7503 20:15:17.540264 192 : 4255, 0
7504 20:15:17.540687 196 : 4363, 0
7505 20:15:17.543976 200 : 4361, 0
7506 20:15:17.544401 204 : 4250, 0
7507 20:15:17.544740 208 : 4249, 0
7508 20:15:17.547267 212 : 4250, 0
7509 20:15:17.547840 216 : 4252, 0
7510 20:15:17.550247 220 : 4250, 0
7511 20:15:17.550962 224 : 4250, 353
7512 20:15:17.551326 228 : 4252, 3772
7513 20:15:17.553745 232 : 4255, 4032
7514 20:15:17.554273 236 : 4250, 4026
7515 20:15:17.557566 240 : 4363, 4140
7516 20:15:17.558096 244 : 4360, 4138
7517 20:15:17.560381 248 : 4250, 4027
7518 20:15:17.560804 252 : 4250, 4026
7519 20:15:17.563382 256 : 4253, 4029
7520 20:15:17.564010 260 : 4250, 4027
7521 20:15:17.567065 264 : 4360, 4138
7522 20:15:17.567493 268 : 4250, 4027
7523 20:15:17.570492 272 : 4252, 4029
7524 20:15:17.571023 276 : 4363, 4140
7525 20:15:17.574107 280 : 4254, 4030
7526 20:15:17.574640 284 : 4250, 4026
7527 20:15:17.577303 288 : 4250, 4027
7528 20:15:17.577836 292 : 4250, 4026
7529 20:15:17.578182 296 : 4250, 4027
7530 20:15:17.580388 300 : 4249, 4027
7531 20:15:17.580815 304 : 4360, 4137
7532 20:15:17.583584 308 : 4253, 4029
7533 20:15:17.584048 312 : 4250, 4027
7534 20:15:17.587112 316 : 4254, 4030
7535 20:15:17.587542 320 : 4252, 4029
7536 20:15:17.590484 324 : 4255, 4029
7537 20:15:17.591107 328 : 4360, 4138
7538 20:15:17.593984 332 : 4254, 4030
7539 20:15:17.594411 336 : 4250, 3759
7540 20:15:17.597221 340 : 4250, 1828
7541 20:15:17.597759
7542 20:15:17.598102 MIOCK jitter meter ch=0
7543 20:15:17.598421
7544 20:15:17.599846 1T = (340-92) = 248 dly cells
7545 20:15:17.606745 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7546 20:15:17.607291 ==
7547 20:15:17.610347 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 20:15:17.613255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 20:15:17.613791 ==
7550 20:15:17.619921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 20:15:17.623344 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 20:15:17.627286 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 20:15:17.633561 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 20:15:17.642997 [CA 0] Center 43 (13~74) winsize 62
7555 20:15:17.646264 [CA 1] Center 43 (13~74) winsize 62
7556 20:15:17.649794 [CA 2] Center 39 (10~69) winsize 60
7557 20:15:17.652585 [CA 3] Center 39 (9~69) winsize 61
7558 20:15:17.656101 [CA 4] Center 37 (8~67) winsize 60
7559 20:15:17.659572 [CA 5] Center 36 (7~66) winsize 60
7560 20:15:17.660220
7561 20:15:17.662911 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 20:15:17.663531
7563 20:15:17.669259 [CATrainingPosCal] consider 1 rank data
7564 20:15:17.669848 u2DelayCellTimex100 = 262/100 ps
7565 20:15:17.675824 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7566 20:15:17.679310 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7567 20:15:17.682665 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7568 20:15:17.685561 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7569 20:15:17.688843 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7570 20:15:17.691893 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7571 20:15:17.692393
7572 20:15:17.696207 CA PerBit enable=1, Macro0, CA PI delay=36
7573 20:15:17.696795
7574 20:15:17.698443 [CBTSetCACLKResult] CA Dly = 36
7575 20:15:17.702203 CS Dly: 11 (0~42)
7576 20:15:17.706132 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 20:15:17.708528 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 20:15:17.712258 ==
7579 20:15:17.715138 Dram Type= 6, Freq= 0, CH_0, rank 1
7580 20:15:17.718597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 20:15:17.719185 ==
7582 20:15:17.722112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7583 20:15:17.728534 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7584 20:15:17.731711 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7585 20:15:17.738075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7586 20:15:17.746883 [CA 0] Center 42 (12~73) winsize 62
7587 20:15:17.750126 [CA 1] Center 43 (13~73) winsize 61
7588 20:15:17.753444 [CA 2] Center 37 (8~67) winsize 60
7589 20:15:17.756569 [CA 3] Center 37 (8~67) winsize 60
7590 20:15:17.760864 [CA 4] Center 36 (6~66) winsize 61
7591 20:15:17.762717 [CA 5] Center 35 (5~65) winsize 61
7592 20:15:17.763198
7593 20:15:17.766297 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7594 20:15:17.766885
7595 20:15:17.772625 [CATrainingPosCal] consider 2 rank data
7596 20:15:17.773197 u2DelayCellTimex100 = 262/100 ps
7597 20:15:17.779317 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7598 20:15:17.783096 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7599 20:15:17.786072 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7600 20:15:17.789244 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7601 20:15:17.792870 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7602 20:15:17.796378 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7603 20:15:17.796863
7604 20:15:17.798829 CA PerBit enable=1, Macro0, CA PI delay=36
7605 20:15:17.799328
7606 20:15:17.803082 [CBTSetCACLKResult] CA Dly = 36
7607 20:15:17.805639 CS Dly: 12 (0~44)
7608 20:15:17.808704 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7609 20:15:17.812296 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7610 20:15:17.812740
7611 20:15:17.815522 ----->DramcWriteLeveling(PI) begin...
7612 20:15:17.818819 ==
7613 20:15:17.819260 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 20:15:17.825302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 20:15:17.825757 ==
7616 20:15:17.829249 Write leveling (Byte 0): 35 => 35
7617 20:15:17.831884 Write leveling (Byte 1): 28 => 28
7618 20:15:17.835637 DramcWriteLeveling(PI) end<-----
7619 20:15:17.836116
7620 20:15:17.836557 ==
7621 20:15:17.838366 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 20:15:17.841609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 20:15:17.842050 ==
7624 20:15:17.846050 [Gating] SW mode calibration
7625 20:15:17.852116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7626 20:15:17.858763 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7627 20:15:17.861673 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 20:15:17.865169 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 20:15:17.872364 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 20:15:17.874742 1 4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7631 20:15:17.878318 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7632 20:15:17.884537 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7633 20:15:17.888245 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7634 20:15:17.891266 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 20:15:17.897667 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 20:15:17.901594 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 20:15:17.904722 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 20:15:17.911061 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7639 20:15:17.915348 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7640 20:15:17.917968 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7641 20:15:17.924601 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7642 20:15:17.928218 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 20:15:17.931367 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 20:15:17.937623 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 20:15:17.941121 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 20:15:17.944876 1 6 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7647 20:15:17.952036 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7648 20:15:17.953956 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7649 20:15:17.958120 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7650 20:15:17.964576 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 20:15:17.967576 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 20:15:17.970803 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 20:15:17.977257 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7654 20:15:17.981102 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7655 20:15:17.984326 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7656 20:15:17.990164 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7657 20:15:17.993549 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7658 20:15:17.996839 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 20:15:18.003471 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 20:15:18.006733 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 20:15:18.010491 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 20:15:18.016646 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 20:15:18.019735 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 20:15:18.023339 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 20:15:18.030164 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 20:15:18.033707 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 20:15:18.036477 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 20:15:18.040048 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 20:15:18.046690 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7670 20:15:18.049817 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7671 20:15:18.056580 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7672 20:15:18.057106 Total UI for P1: 0, mck2ui 16
7673 20:15:18.059737 best dqsien dly found for B0: ( 1, 9, 10)
7674 20:15:18.065815 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7675 20:15:18.070096 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 20:15:18.072812 Total UI for P1: 0, mck2ui 16
7677 20:15:18.076056 best dqsien dly found for B1: ( 1, 9, 18)
7678 20:15:18.079269 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7679 20:15:18.082602 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7680 20:15:18.083033
7681 20:15:18.086070 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7682 20:15:18.092438 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7683 20:15:18.092867 [Gating] SW calibration Done
7684 20:15:18.095994 ==
7685 20:15:18.099380 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 20:15:18.102748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 20:15:18.103281 ==
7688 20:15:18.103624 RX Vref Scan: 0
7689 20:15:18.103986
7690 20:15:18.105679 RX Vref 0 -> 0, step: 1
7691 20:15:18.106100
7692 20:15:18.109486 RX Delay 0 -> 252, step: 8
7693 20:15:18.112854 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7694 20:15:18.115309 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7695 20:15:18.119119 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7696 20:15:18.125614 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7697 20:15:18.128606 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7698 20:15:18.131597 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7699 20:15:18.135028 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7700 20:15:18.138486 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7701 20:15:18.145843 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7702 20:15:18.149035 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7703 20:15:18.151573 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7704 20:15:18.155330 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7705 20:15:18.161741 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7706 20:15:18.165683 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7707 20:15:18.168273 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7708 20:15:18.171088 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7709 20:15:18.171560 ==
7710 20:15:18.174993 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 20:15:18.182061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 20:15:18.182630 ==
7713 20:15:18.183031 DQS Delay:
7714 20:15:18.184361 DQS0 = 0, DQS1 = 0
7715 20:15:18.184828 DQM Delay:
7716 20:15:18.188084 DQM0 = 134, DQM1 = 127
7717 20:15:18.188551 DQ Delay:
7718 20:15:18.191153 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7719 20:15:18.194606 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
7720 20:15:18.197613 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7721 20:15:18.201274 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
7722 20:15:18.201746
7723 20:15:18.202122
7724 20:15:18.202468 ==
7725 20:15:18.204345 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 20:15:18.211003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 20:15:18.211647 ==
7728 20:15:18.212061
7729 20:15:18.212412
7730 20:15:18.212743 TX Vref Scan disable
7731 20:15:18.214731 == TX Byte 0 ==
7732 20:15:18.217591 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7733 20:15:18.224192 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7734 20:15:18.224755 == TX Byte 1 ==
7735 20:15:18.227613 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7736 20:15:18.234262 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7737 20:15:18.234747 ==
7738 20:15:18.237477 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 20:15:18.241078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 20:15:18.241652 ==
7741 20:15:18.253536
7742 20:15:18.256928 TX Vref early break, caculate TX vref
7743 20:15:18.260327 TX Vref=16, minBit 4, minWin=22, winSum=373
7744 20:15:18.263835 TX Vref=18, minBit 0, minWin=23, winSum=385
7745 20:15:18.267748 TX Vref=20, minBit 1, minWin=24, winSum=394
7746 20:15:18.270025 TX Vref=22, minBit 1, minWin=24, winSum=399
7747 20:15:18.276404 TX Vref=24, minBit 1, minWin=25, winSum=413
7748 20:15:18.280120 TX Vref=26, minBit 0, minWin=25, winSum=420
7749 20:15:18.283951 TX Vref=28, minBit 0, minWin=24, winSum=416
7750 20:15:18.286926 TX Vref=30, minBit 0, minWin=25, winSum=412
7751 20:15:18.290038 TX Vref=32, minBit 5, minWin=23, winSum=402
7752 20:15:18.293014 TX Vref=34, minBit 7, minWin=23, winSum=393
7753 20:15:18.299722 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
7754 20:15:18.300294
7755 20:15:18.303100 Final TX Range 0 Vref 26
7756 20:15:18.303568
7757 20:15:18.303978 ==
7758 20:15:18.306107 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 20:15:18.309332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 20:15:18.309808 ==
7761 20:15:18.310182
7762 20:15:18.312449
7763 20:15:18.312911 TX Vref Scan disable
7764 20:15:18.320218 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7765 20:15:18.320778 == TX Byte 0 ==
7766 20:15:18.322804 u2DelayCellOfst[0]=14 cells (4 PI)
7767 20:15:18.326007 u2DelayCellOfst[1]=18 cells (5 PI)
7768 20:15:18.329629 u2DelayCellOfst[2]=14 cells (4 PI)
7769 20:15:18.332353 u2DelayCellOfst[3]=14 cells (4 PI)
7770 20:15:18.336457 u2DelayCellOfst[4]=11 cells (3 PI)
7771 20:15:18.338795 u2DelayCellOfst[5]=0 cells (0 PI)
7772 20:15:18.342272 u2DelayCellOfst[6]=22 cells (6 PI)
7773 20:15:18.346230 u2DelayCellOfst[7]=22 cells (6 PI)
7774 20:15:18.349162 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7775 20:15:18.352082 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7776 20:15:18.355810 == TX Byte 1 ==
7777 20:15:18.359096 u2DelayCellOfst[8]=0 cells (0 PI)
7778 20:15:18.362008 u2DelayCellOfst[9]=0 cells (0 PI)
7779 20:15:18.366291 u2DelayCellOfst[10]=7 cells (2 PI)
7780 20:15:18.368625 u2DelayCellOfst[11]=3 cells (1 PI)
7781 20:15:18.371859 u2DelayCellOfst[12]=11 cells (3 PI)
7782 20:15:18.375357 u2DelayCellOfst[13]=11 cells (3 PI)
7783 20:15:18.379080 u2DelayCellOfst[14]=14 cells (4 PI)
7784 20:15:18.379638 u2DelayCellOfst[15]=11 cells (3 PI)
7785 20:15:18.385724 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7786 20:15:18.388748 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7787 20:15:18.391628 DramC Write-DBI on
7788 20:15:18.392128 ==
7789 20:15:18.395144 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 20:15:18.398727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 20:15:18.399292 ==
7792 20:15:18.399713
7793 20:15:18.400085
7794 20:15:18.401717 TX Vref Scan disable
7795 20:15:18.402181 == TX Byte 0 ==
7796 20:15:18.408181 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7797 20:15:18.408744 == TX Byte 1 ==
7798 20:15:18.414684 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7799 20:15:18.415247 DramC Write-DBI off
7800 20:15:18.415623
7801 20:15:18.416013 [DATLAT]
7802 20:15:18.418085 Freq=1600, CH0 RK0
7803 20:15:18.418551
7804 20:15:18.421231 DATLAT Default: 0xf
7805 20:15:18.421796 0, 0xFFFF, sum = 0
7806 20:15:18.424380 1, 0xFFFF, sum = 0
7807 20:15:18.424851 2, 0xFFFF, sum = 0
7808 20:15:18.427916 3, 0xFFFF, sum = 0
7809 20:15:18.428386 4, 0xFFFF, sum = 0
7810 20:15:18.431103 5, 0xFFFF, sum = 0
7811 20:15:18.431571 6, 0xFFFF, sum = 0
7812 20:15:18.435026 7, 0xFFFF, sum = 0
7813 20:15:18.435494 8, 0xFFFF, sum = 0
7814 20:15:18.437800 9, 0xFFFF, sum = 0
7815 20:15:18.438268 10, 0xFFFF, sum = 0
7816 20:15:18.442079 11, 0xFFFF, sum = 0
7817 20:15:18.442668 12, 0xFFFF, sum = 0
7818 20:15:18.444543 13, 0xFFFF, sum = 0
7819 20:15:18.445016 14, 0x0, sum = 1
7820 20:15:18.447365 15, 0x0, sum = 2
7821 20:15:18.447868 16, 0x0, sum = 3
7822 20:15:18.450772 17, 0x0, sum = 4
7823 20:15:18.451245 best_step = 15
7824 20:15:18.451608
7825 20:15:18.451957 ==
7826 20:15:18.453924 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 20:15:18.461186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 20:15:18.461727 ==
7829 20:15:18.462069 RX Vref Scan: 1
7830 20:15:18.462384
7831 20:15:18.464232 Set Vref Range= 24 -> 127
7832 20:15:18.464656
7833 20:15:18.467091 RX Vref 24 -> 127, step: 1
7834 20:15:18.467511
7835 20:15:18.471566 RX Delay 19 -> 252, step: 4
7836 20:15:18.472037
7837 20:15:18.473897 Set Vref, RX VrefLevel [Byte0]: 24
7838 20:15:18.477467 [Byte1]: 24
7839 20:15:18.477981
7840 20:15:18.480321 Set Vref, RX VrefLevel [Byte0]: 25
7841 20:15:18.483776 [Byte1]: 25
7842 20:15:18.484200
7843 20:15:18.486908 Set Vref, RX VrefLevel [Byte0]: 26
7844 20:15:18.490007 [Byte1]: 26
7845 20:15:18.493312
7846 20:15:18.493731 Set Vref, RX VrefLevel [Byte0]: 27
7847 20:15:18.496939 [Byte1]: 27
7848 20:15:18.500924
7849 20:15:18.501450 Set Vref, RX VrefLevel [Byte0]: 28
7850 20:15:18.504057 [Byte1]: 28
7851 20:15:18.508701
7852 20:15:18.509267 Set Vref, RX VrefLevel [Byte0]: 29
7853 20:15:18.512651 [Byte1]: 29
7854 20:15:18.516618
7855 20:15:18.517191 Set Vref, RX VrefLevel [Byte0]: 30
7856 20:15:18.519537 [Byte1]: 30
7857 20:15:18.524024
7858 20:15:18.524583 Set Vref, RX VrefLevel [Byte0]: 31
7859 20:15:18.530830 [Byte1]: 31
7860 20:15:18.531493
7861 20:15:18.533457 Set Vref, RX VrefLevel [Byte0]: 32
7862 20:15:18.537039 [Byte1]: 32
7863 20:15:18.537507
7864 20:15:18.540156 Set Vref, RX VrefLevel [Byte0]: 33
7865 20:15:18.543861 [Byte1]: 33
7866 20:15:18.544435
7867 20:15:18.546786 Set Vref, RX VrefLevel [Byte0]: 34
7868 20:15:18.549692 [Byte1]: 34
7869 20:15:18.554567
7870 20:15:18.555156 Set Vref, RX VrefLevel [Byte0]: 35
7871 20:15:18.557619 [Byte1]: 35
7872 20:15:18.561633
7873 20:15:18.562121 Set Vref, RX VrefLevel [Byte0]: 36
7874 20:15:18.564750 [Byte1]: 36
7875 20:15:18.568899
7876 20:15:18.569566 Set Vref, RX VrefLevel [Byte0]: 37
7877 20:15:18.572659 [Byte1]: 37
7878 20:15:18.576918
7879 20:15:18.577475 Set Vref, RX VrefLevel [Byte0]: 38
7880 20:15:18.580227 [Byte1]: 38
7881 20:15:18.584949
7882 20:15:18.585507 Set Vref, RX VrefLevel [Byte0]: 39
7883 20:15:18.587728 [Byte1]: 39
7884 20:15:18.591592
7885 20:15:18.592101 Set Vref, RX VrefLevel [Byte0]: 40
7886 20:15:18.595662 [Byte1]: 40
7887 20:15:18.599663
7888 20:15:18.600284 Set Vref, RX VrefLevel [Byte0]: 41
7889 20:15:18.603096 [Byte1]: 41
7890 20:15:18.607105
7891 20:15:18.607667 Set Vref, RX VrefLevel [Byte0]: 42
7892 20:15:18.610182 [Byte1]: 42
7893 20:15:18.614850
7894 20:15:18.615408 Set Vref, RX VrefLevel [Byte0]: 43
7895 20:15:18.618090 [Byte1]: 43
7896 20:15:18.622727
7897 20:15:18.623288 Set Vref, RX VrefLevel [Byte0]: 44
7898 20:15:18.625773 [Byte1]: 44
7899 20:15:18.630047
7900 20:15:18.630609 Set Vref, RX VrefLevel [Byte0]: 45
7901 20:15:18.633257 [Byte1]: 45
7902 20:15:18.637542
7903 20:15:18.638008 Set Vref, RX VrefLevel [Byte0]: 46
7904 20:15:18.641158 [Byte1]: 46
7905 20:15:18.646239
7906 20:15:18.646800 Set Vref, RX VrefLevel [Byte0]: 47
7907 20:15:18.648071 [Byte1]: 47
7908 20:15:18.652676
7909 20:15:18.653242 Set Vref, RX VrefLevel [Byte0]: 48
7910 20:15:18.655764 [Byte1]: 48
7911 20:15:18.659976
7912 20:15:18.660442 Set Vref, RX VrefLevel [Byte0]: 49
7913 20:15:18.663785 [Byte1]: 49
7914 20:15:18.667452
7915 20:15:18.667963 Set Vref, RX VrefLevel [Byte0]: 50
7916 20:15:18.670876 [Byte1]: 50
7917 20:15:18.675402
7918 20:15:18.676030 Set Vref, RX VrefLevel [Byte0]: 51
7919 20:15:18.678202 [Byte1]: 51
7920 20:15:18.683233
7921 20:15:18.683790 Set Vref, RX VrefLevel [Byte0]: 52
7922 20:15:18.686717 [Byte1]: 52
7923 20:15:18.690383
7924 20:15:18.690940 Set Vref, RX VrefLevel [Byte0]: 53
7925 20:15:18.694351 [Byte1]: 53
7926 20:15:18.697726
7927 20:15:18.698146 Set Vref, RX VrefLevel [Byte0]: 54
7928 20:15:18.701377 [Byte1]: 54
7929 20:15:18.705794
7930 20:15:18.706330 Set Vref, RX VrefLevel [Byte0]: 55
7931 20:15:18.709264 [Byte1]: 55
7932 20:15:18.713223
7933 20:15:18.713644 Set Vref, RX VrefLevel [Byte0]: 56
7934 20:15:18.716618 [Byte1]: 56
7935 20:15:18.720662
7936 20:15:18.721180 Set Vref, RX VrefLevel [Byte0]: 57
7937 20:15:18.724262 [Byte1]: 57
7938 20:15:18.728410
7939 20:15:18.728929 Set Vref, RX VrefLevel [Byte0]: 58
7940 20:15:18.731288 [Byte1]: 58
7941 20:15:18.735778
7942 20:15:18.736205 Set Vref, RX VrefLevel [Byte0]: 59
7943 20:15:18.739180 [Byte1]: 59
7944 20:15:18.743222
7945 20:15:18.743716 Set Vref, RX VrefLevel [Byte0]: 60
7946 20:15:18.746976 [Byte1]: 60
7947 20:15:18.751432
7948 20:15:18.752037 Set Vref, RX VrefLevel [Byte0]: 61
7949 20:15:18.754180 [Byte1]: 61
7950 20:15:18.758853
7951 20:15:18.759407 Set Vref, RX VrefLevel [Byte0]: 62
7952 20:15:18.761825 [Byte1]: 62
7953 20:15:18.766396
7954 20:15:18.766953 Set Vref, RX VrefLevel [Byte0]: 63
7955 20:15:18.769391 [Byte1]: 63
7956 20:15:18.773662
7957 20:15:18.774223 Set Vref, RX VrefLevel [Byte0]: 64
7958 20:15:18.777453 [Byte1]: 64
7959 20:15:18.781857
7960 20:15:18.782431 Set Vref, RX VrefLevel [Byte0]: 65
7961 20:15:18.784850 [Byte1]: 65
7962 20:15:18.788939
7963 20:15:18.789420 Set Vref, RX VrefLevel [Byte0]: 66
7964 20:15:18.792482 [Byte1]: 66
7965 20:15:18.796412
7966 20:15:18.796976 Set Vref, RX VrefLevel [Byte0]: 67
7967 20:15:18.800163 [Byte1]: 67
7968 20:15:18.804367
7969 20:15:18.804814 Set Vref, RX VrefLevel [Byte0]: 68
7970 20:15:18.807409 [Byte1]: 68
7971 20:15:18.811847
7972 20:15:18.812362 Set Vref, RX VrefLevel [Byte0]: 69
7973 20:15:18.814988 [Byte1]: 69
7974 20:15:18.819728
7975 20:15:18.820249 Set Vref, RX VrefLevel [Byte0]: 70
7976 20:15:18.822683 [Byte1]: 70
7977 20:15:18.827415
7978 20:15:18.828018 Set Vref, RX VrefLevel [Byte0]: 71
7979 20:15:18.830477 [Byte1]: 71
7980 20:15:18.834368
7981 20:15:18.834831 Set Vref, RX VrefLevel [Byte0]: 72
7982 20:15:18.837615 [Byte1]: 72
7983 20:15:18.842041
7984 20:15:18.842596 Set Vref, RX VrefLevel [Byte0]: 73
7985 20:15:18.845108 [Byte1]: 73
7986 20:15:18.849225
7987 20:15:18.849786 Set Vref, RX VrefLevel [Byte0]: 74
7988 20:15:18.853352 [Byte1]: 74
7989 20:15:18.857192
7990 20:15:18.859871 Set Vref, RX VrefLevel [Byte0]: 75
7991 20:15:18.860338 [Byte1]: 75
7992 20:15:18.864535
7993 20:15:18.865094 Set Vref, RX VrefLevel [Byte0]: 76
7994 20:15:18.867598 [Byte1]: 76
7995 20:15:18.872143
7996 20:15:18.872740 Set Vref, RX VrefLevel [Byte0]: 77
7997 20:15:18.875478 [Byte1]: 77
7998 20:15:18.879828
7999 20:15:18.880333 Set Vref, RX VrefLevel [Byte0]: 78
8000 20:15:18.883166 [Byte1]: 78
8001 20:15:18.887024
8002 20:15:18.887445 Set Vref, RX VrefLevel [Byte0]: 79
8003 20:15:18.890321 [Byte1]: 79
8004 20:15:18.894611
8005 20:15:18.895098 Set Vref, RX VrefLevel [Byte0]: 80
8006 20:15:18.898181 [Byte1]: 80
8007 20:15:18.902909
8008 20:15:18.903483 Final RX Vref Byte 0 = 66 to rank0
8009 20:15:18.905724 Final RX Vref Byte 1 = 59 to rank0
8010 20:15:18.908917 Final RX Vref Byte 0 = 66 to rank1
8011 20:15:18.912426 Final RX Vref Byte 1 = 59 to rank1==
8012 20:15:18.916588 Dram Type= 6, Freq= 0, CH_0, rank 0
8013 20:15:18.921872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 20:15:18.922521 ==
8015 20:15:18.923170 DQS Delay:
8016 20:15:18.925216 DQS0 = 0, DQS1 = 0
8017 20:15:18.925652 DQM Delay:
8018 20:15:18.925996 DQM0 = 132, DQM1 = 124
8019 20:15:18.928711 DQ Delay:
8020 20:15:18.931923 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8021 20:15:18.935094 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
8022 20:15:18.938399 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8023 20:15:18.942532 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
8024 20:15:18.943054
8025 20:15:18.943391
8026 20:15:18.943856
8027 20:15:18.944910 [DramC_TX_OE_Calibration] TA2
8028 20:15:18.948165 Original DQ_B0 (3 6) =30, OEN = 27
8029 20:15:18.952701 Original DQ_B1 (3 6) =30, OEN = 27
8030 20:15:18.955232 24, 0x0, End_B0=24 End_B1=24
8031 20:15:18.958880 25, 0x0, End_B0=25 End_B1=25
8032 20:15:18.959410 26, 0x0, End_B0=26 End_B1=26
8033 20:15:18.961769 27, 0x0, End_B0=27 End_B1=27
8034 20:15:18.964819 28, 0x0, End_B0=28 End_B1=28
8035 20:15:18.968588 29, 0x0, End_B0=29 End_B1=29
8036 20:15:18.969120 30, 0x0, End_B0=30 End_B1=30
8037 20:15:18.971291 31, 0x4141, End_B0=30 End_B1=30
8038 20:15:18.975189 Byte0 end_step=30 best_step=27
8039 20:15:18.978084 Byte1 end_step=30 best_step=27
8040 20:15:18.981871 Byte0 TX OE(2T, 0.5T) = (3, 3)
8041 20:15:18.984808 Byte1 TX OE(2T, 0.5T) = (3, 3)
8042 20:15:18.985332
8043 20:15:18.985674
8044 20:15:18.991374 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8045 20:15:18.995757 CH0 RK0: MR19=303, MR18=1F10
8046 20:15:19.001086 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8047 20:15:19.001514
8048 20:15:19.005252 ----->DramcWriteLeveling(PI) begin...
8049 20:15:19.005782 ==
8050 20:15:19.008084 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 20:15:19.011286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 20:15:19.011867 ==
8053 20:15:19.014538 Write leveling (Byte 0): 35 => 35
8054 20:15:19.017710 Write leveling (Byte 1): 28 => 28
8055 20:15:19.021298 DramcWriteLeveling(PI) end<-----
8056 20:15:19.021823
8057 20:15:19.022162 ==
8058 20:15:19.024060 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 20:15:19.030872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 20:15:19.031392 ==
8061 20:15:19.031778 [Gating] SW mode calibration
8062 20:15:19.040447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 20:15:19.043532 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8064 20:15:19.050689 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 20:15:19.053501 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 20:15:19.057214 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 20:15:19.064081 1 4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8068 20:15:19.066553 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8069 20:15:19.070033 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8070 20:15:19.077013 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 20:15:19.080516 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 20:15:19.083161 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 20:15:19.089599 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 20:15:19.093250 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 20:15:19.096155 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8076 20:15:19.103011 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8077 20:15:19.106503 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8078 20:15:19.109462 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 20:15:19.116370 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 20:15:19.120251 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 20:15:19.122866 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 20:15:19.129700 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 20:15:19.132611 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8084 20:15:19.135665 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8085 20:15:19.142390 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8086 20:15:19.145880 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 20:15:19.149279 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 20:15:19.156331 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 20:15:19.159216 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 20:15:19.162308 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 20:15:19.169029 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 20:15:19.171970 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 20:15:19.176108 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 20:15:19.182482 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 20:15:19.185137 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 20:15:19.188366 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 20:15:19.194977 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 20:15:19.198691 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 20:15:19.201918 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 20:15:19.208385 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 20:15:19.212085 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 20:15:19.215151 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 20:15:19.222003 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 20:15:19.225021 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 20:15:19.228332 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 20:15:19.234807 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 20:15:19.238099 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 20:15:19.241895 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 20:15:19.245234 Total UI for P1: 0, mck2ui 16
8110 20:15:19.248422 best dqsien dly found for B0: ( 1, 9, 12)
8111 20:15:19.254664 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 20:15:19.258146 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 20:15:19.261278 Total UI for P1: 0, mck2ui 16
8114 20:15:19.264795 best dqsien dly found for B1: ( 1, 9, 18)
8115 20:15:19.267642 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8116 20:15:19.271306 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8117 20:15:19.271767
8118 20:15:19.274371 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8119 20:15:19.278336 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8120 20:15:19.280969 [Gating] SW calibration Done
8121 20:15:19.281486 ==
8122 20:15:19.284898 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 20:15:19.287659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 20:15:19.290899 ==
8125 20:15:19.291321 RX Vref Scan: 0
8126 20:15:19.291661
8127 20:15:19.294115 RX Vref 0 -> 0, step: 1
8128 20:15:19.294538
8129 20:15:19.294876 RX Delay 0 -> 252, step: 8
8130 20:15:19.301325 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8131 20:15:19.304306 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8132 20:15:19.307516 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8133 20:15:19.310638 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8134 20:15:19.317476 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8135 20:15:19.320885 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8136 20:15:19.324222 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8137 20:15:19.327427 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8138 20:15:19.330571 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8139 20:15:19.336977 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8140 20:15:19.340290 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8141 20:15:19.343912 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8142 20:15:19.348022 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8143 20:15:19.353244 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8144 20:15:19.357228 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8145 20:15:19.360055 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8146 20:15:19.360526 ==
8147 20:15:19.363500 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 20:15:19.366972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 20:15:19.367538 ==
8150 20:15:19.369844 DQS Delay:
8151 20:15:19.370307 DQS0 = 0, DQS1 = 0
8152 20:15:19.373090 DQM Delay:
8153 20:15:19.373558 DQM0 = 134, DQM1 = 128
8154 20:15:19.374087 DQ Delay:
8155 20:15:19.379748 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
8156 20:15:19.382764 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8157 20:15:19.386311 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8158 20:15:19.389639 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8159 20:15:19.390056
8160 20:15:19.390402
8161 20:15:19.390713 ==
8162 20:15:19.392690 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 20:15:19.396420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 20:15:19.396945 ==
8165 20:15:19.397284
8166 20:15:19.397596
8167 20:15:19.399213 TX Vref Scan disable
8168 20:15:19.403165 == TX Byte 0 ==
8169 20:15:19.405996 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8170 20:15:19.409638 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8171 20:15:19.412302 == TX Byte 1 ==
8172 20:15:19.415927 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8173 20:15:19.419325 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8174 20:15:19.419896 ==
8175 20:15:19.422891 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 20:15:19.429525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 20:15:19.430060 ==
8178 20:15:19.441753
8179 20:15:19.445144 TX Vref early break, caculate TX vref
8180 20:15:19.448370 TX Vref=16, minBit 1, minWin=22, winSum=377
8181 20:15:19.451899 TX Vref=18, minBit 0, minWin=23, winSum=387
8182 20:15:19.455052 TX Vref=20, minBit 1, minWin=22, winSum=389
8183 20:15:19.458211 TX Vref=22, minBit 7, minWin=23, winSum=403
8184 20:15:19.461840 TX Vref=24, minBit 1, minWin=24, winSum=413
8185 20:15:19.467822 TX Vref=26, minBit 4, minWin=24, winSum=409
8186 20:15:19.471948 TX Vref=28, minBit 1, minWin=24, winSum=411
8187 20:15:19.474696 TX Vref=30, minBit 0, minWin=24, winSum=401
8188 20:15:19.477819 TX Vref=32, minBit 2, minWin=23, winSum=394
8189 20:15:19.481304 TX Vref=34, minBit 1, minWin=23, winSum=390
8190 20:15:19.488039 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 24
8191 20:15:19.488508
8192 20:15:19.491590 Final TX Range 0 Vref 24
8193 20:15:19.492116
8194 20:15:19.492487 ==
8195 20:15:19.494038 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 20:15:19.498327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 20:15:19.498912 ==
8198 20:15:19.499311
8199 20:15:19.499658
8200 20:15:19.500819 TX Vref Scan disable
8201 20:15:19.507724 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8202 20:15:19.508298 == TX Byte 0 ==
8203 20:15:19.511536 u2DelayCellOfst[0]=11 cells (3 PI)
8204 20:15:19.514493 u2DelayCellOfst[1]=14 cells (4 PI)
8205 20:15:19.518110 u2DelayCellOfst[2]=11 cells (3 PI)
8206 20:15:19.521513 u2DelayCellOfst[3]=11 cells (3 PI)
8207 20:15:19.524141 u2DelayCellOfst[4]=7 cells (2 PI)
8208 20:15:19.527838 u2DelayCellOfst[5]=0 cells (0 PI)
8209 20:15:19.530864 u2DelayCellOfst[6]=14 cells (4 PI)
8210 20:15:19.533563 u2DelayCellOfst[7]=18 cells (5 PI)
8211 20:15:19.537164 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8212 20:15:19.540363 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8213 20:15:19.544054 == TX Byte 1 ==
8214 20:15:19.547441 u2DelayCellOfst[8]=0 cells (0 PI)
8215 20:15:19.550616 u2DelayCellOfst[9]=0 cells (0 PI)
8216 20:15:19.554488 u2DelayCellOfst[10]=7 cells (2 PI)
8217 20:15:19.555065 u2DelayCellOfst[11]=3 cells (1 PI)
8218 20:15:19.556889 u2DelayCellOfst[12]=14 cells (4 PI)
8219 20:15:19.560288 u2DelayCellOfst[13]=11 cells (3 PI)
8220 20:15:19.563757 u2DelayCellOfst[14]=18 cells (5 PI)
8221 20:15:19.566966 u2DelayCellOfst[15]=11 cells (3 PI)
8222 20:15:19.573474 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8223 20:15:19.576422 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8224 20:15:19.576908 DramC Write-DBI on
8225 20:15:19.579854 ==
8226 20:15:19.583059 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 20:15:19.586971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 20:15:19.587538 ==
8229 20:15:19.587972
8230 20:15:19.588326
8231 20:15:19.589406 TX Vref Scan disable
8232 20:15:19.589876 == TX Byte 0 ==
8233 20:15:19.596168 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8234 20:15:19.596646 == TX Byte 1 ==
8235 20:15:19.599890 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8236 20:15:19.603592 DramC Write-DBI off
8237 20:15:19.604210
8238 20:15:19.604635 [DATLAT]
8239 20:15:19.606055 Freq=1600, CH0 RK1
8240 20:15:19.606526
8241 20:15:19.606898 DATLAT Default: 0xf
8242 20:15:19.610155 0, 0xFFFF, sum = 0
8243 20:15:19.610818 1, 0xFFFF, sum = 0
8244 20:15:19.612419 2, 0xFFFF, sum = 0
8245 20:15:19.612895 3, 0xFFFF, sum = 0
8246 20:15:19.616047 4, 0xFFFF, sum = 0
8247 20:15:19.619377 5, 0xFFFF, sum = 0
8248 20:15:19.620021 6, 0xFFFF, sum = 0
8249 20:15:19.622565 7, 0xFFFF, sum = 0
8250 20:15:19.623086 8, 0xFFFF, sum = 0
8251 20:15:19.626113 9, 0xFFFF, sum = 0
8252 20:15:19.626687 10, 0xFFFF, sum = 0
8253 20:15:19.630335 11, 0xFFFF, sum = 0
8254 20:15:19.630902 12, 0xFFFF, sum = 0
8255 20:15:19.632155 13, 0xFFFF, sum = 0
8256 20:15:19.632637 14, 0x0, sum = 1
8257 20:15:19.635943 15, 0x0, sum = 2
8258 20:15:19.636514 16, 0x0, sum = 3
8259 20:15:19.638918 17, 0x0, sum = 4
8260 20:15:19.639494 best_step = 15
8261 20:15:19.639918
8262 20:15:19.640279 ==
8263 20:15:19.642234 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 20:15:19.649156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 20:15:19.649676 ==
8266 20:15:19.650020 RX Vref Scan: 0
8267 20:15:19.650339
8268 20:15:19.652240 RX Vref 0 -> 0, step: 1
8269 20:15:19.652665
8270 20:15:19.655579 RX Delay 11 -> 252, step: 4
8271 20:15:19.658838 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8272 20:15:19.661920 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8273 20:15:19.665517 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8274 20:15:19.671689 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8275 20:15:19.675623 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8276 20:15:19.678565 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8277 20:15:19.681806 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8278 20:15:19.685167 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8279 20:15:19.691643 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8280 20:15:19.694823 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8281 20:15:19.698820 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8282 20:15:19.701602 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8283 20:15:19.708111 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8284 20:15:19.711451 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8285 20:15:19.714427 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8286 20:15:19.717671 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8287 20:15:19.718093 ==
8288 20:15:19.721279 Dram Type= 6, Freq= 0, CH_0, rank 1
8289 20:15:19.728166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 20:15:19.728691 ==
8291 20:15:19.729034 DQS Delay:
8292 20:15:19.731386 DQS0 = 0, DQS1 = 0
8293 20:15:19.731944 DQM Delay:
8294 20:15:19.732294 DQM0 = 130, DQM1 = 125
8295 20:15:19.734195 DQ Delay:
8296 20:15:19.737739 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8297 20:15:19.740851 DQ4 =130, DQ5 =120, DQ6 =140, DQ7 =140
8298 20:15:19.743882 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8299 20:15:19.747274 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8300 20:15:19.747748
8301 20:15:19.748093
8302 20:15:19.748407
8303 20:15:19.751106 [DramC_TX_OE_Calibration] TA2
8304 20:15:19.754132 Original DQ_B0 (3 6) =30, OEN = 27
8305 20:15:19.757251 Original DQ_B1 (3 6) =30, OEN = 27
8306 20:15:19.760817 24, 0x0, End_B0=24 End_B1=24
8307 20:15:19.764249 25, 0x0, End_B0=25 End_B1=25
8308 20:15:19.764688 26, 0x0, End_B0=26 End_B1=26
8309 20:15:19.767354 27, 0x0, End_B0=27 End_B1=27
8310 20:15:19.770499 28, 0x0, End_B0=28 End_B1=28
8311 20:15:19.774020 29, 0x0, End_B0=29 End_B1=29
8312 20:15:19.774452 30, 0x0, End_B0=30 End_B1=30
8313 20:15:19.777172 31, 0x4141, End_B0=30 End_B1=30
8314 20:15:19.780139 Byte0 end_step=30 best_step=27
8315 20:15:19.783936 Byte1 end_step=30 best_step=27
8316 20:15:19.786914 Byte0 TX OE(2T, 0.5T) = (3, 3)
8317 20:15:19.790003 Byte1 TX OE(2T, 0.5T) = (3, 3)
8318 20:15:19.790300
8319 20:15:19.790536
8320 20:15:19.797493 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8321 20:15:19.800173 CH0 RK1: MR19=303, MR18=1F02
8322 20:15:19.806669 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8323 20:15:19.809824 [RxdqsGatingPostProcess] freq 1600
8324 20:15:19.816269 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8325 20:15:19.816420 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 20:15:19.819913 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 20:15:19.823589 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 20:15:19.826445 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 20:15:19.829514 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 20:15:19.833319 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 20:15:19.836086 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 20:15:19.839556 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 20:15:19.843196 Pre-setting of DQS Precalculation
8334 20:15:19.845969 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8335 20:15:19.846050 ==
8336 20:15:19.849536 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 20:15:19.856523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 20:15:19.856630 ==
8339 20:15:19.859133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 20:15:19.865692 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 20:15:19.869060 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 20:15:19.875803 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 20:15:19.883246 [CA 0] Center 41 (12~71) winsize 60
8344 20:15:19.886996 [CA 1] Center 42 (12~72) winsize 61
8345 20:15:19.890739 [CA 2] Center 37 (8~66) winsize 59
8346 20:15:19.893595 [CA 3] Center 36 (7~65) winsize 59
8347 20:15:19.897927 [CA 4] Center 36 (7~66) winsize 60
8348 20:15:19.900526 [CA 5] Center 36 (7~66) winsize 60
8349 20:15:19.900607
8350 20:15:19.903405 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 20:15:19.903486
8352 20:15:19.906662 [CATrainingPosCal] consider 1 rank data
8353 20:15:19.910221 u2DelayCellTimex100 = 262/100 ps
8354 20:15:19.916840 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8355 20:15:19.919985 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8356 20:15:19.923397 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8357 20:15:19.926547 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8358 20:15:19.930275 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8359 20:15:19.933098 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 20:15:19.933251
8361 20:15:19.936567 CA PerBit enable=1, Macro0, CA PI delay=36
8362 20:15:19.936733
8363 20:15:19.939422 [CBTSetCACLKResult] CA Dly = 36
8364 20:15:19.943282 CS Dly: 9 (0~40)
8365 20:15:19.946277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 20:15:19.950185 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 20:15:19.950568 ==
8368 20:15:19.952887 Dram Type= 6, Freq= 0, CH_1, rank 1
8369 20:15:19.959566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 20:15:19.959931 ==
8371 20:15:19.963251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 20:15:19.969489 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 20:15:19.972892 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 20:15:19.979224 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 20:15:19.987073 [CA 0] Center 42 (13~72) winsize 60
8376 20:15:19.990544 [CA 1] Center 43 (13~73) winsize 61
8377 20:15:19.993646 [CA 2] Center 37 (8~67) winsize 60
8378 20:15:19.997931 [CA 3] Center 37 (8~67) winsize 60
8379 20:15:20.000178 [CA 4] Center 38 (9~67) winsize 59
8380 20:15:20.004005 [CA 5] Center 37 (8~67) winsize 60
8381 20:15:20.004524
8382 20:15:20.006806 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8383 20:15:20.007224
8384 20:15:20.013991 [CATrainingPosCal] consider 2 rank data
8385 20:15:20.014458 u2DelayCellTimex100 = 262/100 ps
8386 20:15:20.020420 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8387 20:15:20.023351 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8388 20:15:20.026698 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8389 20:15:20.029814 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8390 20:15:20.033375 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8391 20:15:20.036376 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8392 20:15:20.036800
8393 20:15:20.040385 CA PerBit enable=1, Macro0, CA PI delay=36
8394 20:15:20.040863
8395 20:15:20.042973 [CBTSetCACLKResult] CA Dly = 36
8396 20:15:20.046359 CS Dly: 10 (0~43)
8397 20:15:20.049651 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 20:15:20.053573 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 20:15:20.054388
8400 20:15:20.056150 ----->DramcWriteLeveling(PI) begin...
8401 20:15:20.056575 ==
8402 20:15:20.059738 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 20:15:20.066341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 20:15:20.066783 ==
8405 20:15:20.069721 Write leveling (Byte 0): 24 => 24
8406 20:15:20.072837 Write leveling (Byte 1): 27 => 27
8407 20:15:20.073259 DramcWriteLeveling(PI) end<-----
8408 20:15:20.076455
8409 20:15:20.076868 ==
8410 20:15:20.079822 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 20:15:20.082726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 20:15:20.083149 ==
8413 20:15:20.085971 [Gating] SW mode calibration
8414 20:15:20.092364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8415 20:15:20.096604 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8416 20:15:20.103197 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 20:15:20.105784 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 20:15:20.108852 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8419 20:15:20.115756 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8420 20:15:20.119010 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 20:15:20.122506 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 20:15:20.128583 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 20:15:20.132195 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 20:15:20.135610 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 20:15:20.142014 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 20:15:20.144875 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8427 20:15:20.151797 1 5 12 | B1->B0 | 3232 2424 | 1 0 | (1 0) (1 0)
8428 20:15:20.154885 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 20:15:20.158424 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 20:15:20.164887 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 20:15:20.168184 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 20:15:20.171316 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 20:15:20.178264 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 20:15:20.181694 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8435 20:15:20.184957 1 6 12 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
8436 20:15:20.191520 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 20:15:20.195065 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 20:15:20.198218 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 20:15:20.204467 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 20:15:20.207434 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 20:15:20.211407 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 20:15:20.217378 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 20:15:20.221561 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8444 20:15:20.223842 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8445 20:15:20.230409 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 20:15:20.233666 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 20:15:20.236820 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 20:15:20.243858 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 20:15:20.246469 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 20:15:20.250206 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 20:15:20.257221 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 20:15:20.260025 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 20:15:20.263318 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 20:15:20.270027 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 20:15:20.273333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 20:15:20.277412 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 20:15:20.283406 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 20:15:20.286701 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 20:15:20.289965 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8460 20:15:20.296997 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 20:15:20.297082 Total UI for P1: 0, mck2ui 16
8462 20:15:20.303004 best dqsien dly found for B0: ( 1, 9, 10)
8463 20:15:20.303086 Total UI for P1: 0, mck2ui 16
8464 20:15:20.306416 best dqsien dly found for B1: ( 1, 9, 10)
8465 20:15:20.312855 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8466 20:15:20.316157 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8467 20:15:20.316238
8468 20:15:20.319782 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8469 20:15:20.323469 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8470 20:15:20.326261 [Gating] SW calibration Done
8471 20:15:20.326342 ==
8472 20:15:20.329307 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 20:15:20.332882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 20:15:20.332964 ==
8475 20:15:20.336252 RX Vref Scan: 0
8476 20:15:20.336334
8477 20:15:20.336399 RX Vref 0 -> 0, step: 1
8478 20:15:20.336459
8479 20:15:20.339316 RX Delay 0 -> 252, step: 8
8480 20:15:20.342249 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8481 20:15:20.349110 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8482 20:15:20.352280 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8483 20:15:20.355772 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8484 20:15:20.358749 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8485 20:15:20.362304 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8486 20:15:20.369573 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8487 20:15:20.372319 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8488 20:15:20.375927 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8489 20:15:20.379521 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8490 20:15:20.382102 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8491 20:15:20.388752 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8492 20:15:20.392394 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8493 20:15:20.395530 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8494 20:15:20.398603 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8495 20:15:20.404965 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8496 20:15:20.405046 ==
8497 20:15:20.408324 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 20:15:20.412019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 20:15:20.412100 ==
8500 20:15:20.412165 DQS Delay:
8501 20:15:20.415312 DQS0 = 0, DQS1 = 0
8502 20:15:20.415394 DQM Delay:
8503 20:15:20.418485 DQM0 = 137, DQM1 = 128
8504 20:15:20.418566 DQ Delay:
8505 20:15:20.421798 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8506 20:15:20.425194 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8507 20:15:20.428594 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8508 20:15:20.431711 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8509 20:15:20.431792
8510 20:15:20.431860
8511 20:15:20.435468 ==
8512 20:15:20.438181 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 20:15:20.441526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 20:15:20.441612 ==
8515 20:15:20.441677
8516 20:15:20.441737
8517 20:15:20.444635 TX Vref Scan disable
8518 20:15:20.444716 == TX Byte 0 ==
8519 20:15:20.451494 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8520 20:15:20.454404 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8521 20:15:20.454485 == TX Byte 1 ==
8522 20:15:20.461191 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8523 20:15:20.464401 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8524 20:15:20.464483 ==
8525 20:15:20.467901 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 20:15:20.471298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 20:15:20.471379 ==
8528 20:15:20.484345
8529 20:15:20.488003 TX Vref early break, caculate TX vref
8530 20:15:20.490923 TX Vref=16, minBit 0, minWin=22, winSum=376
8531 20:15:20.494853 TX Vref=18, minBit 0, minWin=22, winSum=388
8532 20:15:20.497767 TX Vref=20, minBit 5, minWin=23, winSum=396
8533 20:15:20.500863 TX Vref=22, minBit 0, minWin=24, winSum=405
8534 20:15:20.504464 TX Vref=24, minBit 0, minWin=25, winSum=414
8535 20:15:20.511095 TX Vref=26, minBit 0, minWin=24, winSum=417
8536 20:15:20.514155 TX Vref=28, minBit 1, minWin=24, winSum=418
8537 20:15:20.517885 TX Vref=30, minBit 0, minWin=25, winSum=416
8538 20:15:20.520812 TX Vref=32, minBit 0, minWin=24, winSum=408
8539 20:15:20.523852 TX Vref=34, minBit 0, minWin=24, winSum=395
8540 20:15:20.530852 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
8541 20:15:20.530933
8542 20:15:20.533764 Final TX Range 0 Vref 30
8543 20:15:20.533845
8544 20:15:20.533909 ==
8545 20:15:20.537321 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 20:15:20.540845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 20:15:20.540926 ==
8548 20:15:20.540991
8549 20:15:20.541051
8550 20:15:20.543528 TX Vref Scan disable
8551 20:15:20.550302 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8552 20:15:20.550384 == TX Byte 0 ==
8553 20:15:20.553275 u2DelayCellOfst[0]=18 cells (5 PI)
8554 20:15:20.556893 u2DelayCellOfst[1]=14 cells (4 PI)
8555 20:15:20.560422 u2DelayCellOfst[2]=0 cells (0 PI)
8556 20:15:20.563486 u2DelayCellOfst[3]=3 cells (1 PI)
8557 20:15:20.566552 u2DelayCellOfst[4]=11 cells (3 PI)
8558 20:15:20.570362 u2DelayCellOfst[5]=22 cells (6 PI)
8559 20:15:20.573803 u2DelayCellOfst[6]=22 cells (6 PI)
8560 20:15:20.576763 u2DelayCellOfst[7]=7 cells (2 PI)
8561 20:15:20.579914 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8562 20:15:20.583022 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8563 20:15:20.586559 == TX Byte 1 ==
8564 20:15:20.590194 u2DelayCellOfst[8]=0 cells (0 PI)
8565 20:15:20.592904 u2DelayCellOfst[9]=3 cells (1 PI)
8566 20:15:20.596657 u2DelayCellOfst[10]=14 cells (4 PI)
8567 20:15:20.599730 u2DelayCellOfst[11]=3 cells (1 PI)
8568 20:15:20.599812 u2DelayCellOfst[12]=18 cells (5 PI)
8569 20:15:20.603015 u2DelayCellOfst[13]=18 cells (5 PI)
8570 20:15:20.606356 u2DelayCellOfst[14]=18 cells (5 PI)
8571 20:15:20.609733 u2DelayCellOfst[15]=22 cells (6 PI)
8572 20:15:20.616088 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8573 20:15:20.619960 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8574 20:15:20.620042 DramC Write-DBI on
8575 20:15:20.623084 ==
8576 20:15:20.626086 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 20:15:20.629743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 20:15:20.629913 ==
8579 20:15:20.629998
8580 20:15:20.630071
8581 20:15:20.633683 TX Vref Scan disable
8582 20:15:20.633781 == TX Byte 0 ==
8583 20:15:20.639105 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8584 20:15:20.639208 == TX Byte 1 ==
8585 20:15:20.642984 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8586 20:15:20.645820 DramC Write-DBI off
8587 20:15:20.645930
8588 20:15:20.646019 [DATLAT]
8589 20:15:20.648806 Freq=1600, CH1 RK0
8590 20:15:20.648929
8591 20:15:20.649027 DATLAT Default: 0xf
8592 20:15:20.652578 0, 0xFFFF, sum = 0
8593 20:15:20.652661 1, 0xFFFF, sum = 0
8594 20:15:20.656001 2, 0xFFFF, sum = 0
8595 20:15:20.656084 3, 0xFFFF, sum = 0
8596 20:15:20.659082 4, 0xFFFF, sum = 0
8597 20:15:20.659165 5, 0xFFFF, sum = 0
8598 20:15:20.663164 6, 0xFFFF, sum = 0
8599 20:15:20.665768 7, 0xFFFF, sum = 0
8600 20:15:20.665851 8, 0xFFFF, sum = 0
8601 20:15:20.668645 9, 0xFFFF, sum = 0
8602 20:15:20.668728 10, 0xFFFF, sum = 0
8603 20:15:20.672084 11, 0xFFFF, sum = 0
8604 20:15:20.672168 12, 0xFFFF, sum = 0
8605 20:15:20.675225 13, 0xFFFF, sum = 0
8606 20:15:20.675308 14, 0x0, sum = 1
8607 20:15:20.679233 15, 0x0, sum = 2
8608 20:15:20.679317 16, 0x0, sum = 3
8609 20:15:20.681887 17, 0x0, sum = 4
8610 20:15:20.681970 best_step = 15
8611 20:15:20.682035
8612 20:15:20.682098 ==
8613 20:15:20.685072 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 20:15:20.688688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 20:15:20.692774 ==
8616 20:15:20.692856 RX Vref Scan: 1
8617 20:15:20.692921
8618 20:15:20.695503 Set Vref Range= 24 -> 127
8619 20:15:20.695613
8620 20:15:20.698880 RX Vref 24 -> 127, step: 1
8621 20:15:20.698961
8622 20:15:20.699026 RX Delay 11 -> 252, step: 4
8623 20:15:20.699086
8624 20:15:20.702354 Set Vref, RX VrefLevel [Byte0]: 24
8625 20:15:20.705433 [Byte1]: 24
8626 20:15:20.709369
8627 20:15:20.709450 Set Vref, RX VrefLevel [Byte0]: 25
8628 20:15:20.712048 [Byte1]: 25
8629 20:15:20.717081
8630 20:15:20.717161 Set Vref, RX VrefLevel [Byte0]: 26
8631 20:15:20.719787 [Byte1]: 26
8632 20:15:20.724442
8633 20:15:20.724522 Set Vref, RX VrefLevel [Byte0]: 27
8634 20:15:20.727918 [Byte1]: 27
8635 20:15:20.732034
8636 20:15:20.732115 Set Vref, RX VrefLevel [Byte0]: 28
8637 20:15:20.736065 [Byte1]: 28
8638 20:15:20.739750
8639 20:15:20.740169 Set Vref, RX VrefLevel [Byte0]: 29
8640 20:15:20.743186 [Byte1]: 29
8641 20:15:20.747715
8642 20:15:20.748235 Set Vref, RX VrefLevel [Byte0]: 30
8643 20:15:20.750774 [Byte1]: 30
8644 20:15:20.755104
8645 20:15:20.755517 Set Vref, RX VrefLevel [Byte0]: 31
8646 20:15:20.758262 [Byte1]: 31
8647 20:15:20.762273
8648 20:15:20.762353 Set Vref, RX VrefLevel [Byte0]: 32
8649 20:15:20.766086 [Byte1]: 32
8650 20:15:20.770187
8651 20:15:20.770267 Set Vref, RX VrefLevel [Byte0]: 33
8652 20:15:20.772901 [Byte1]: 33
8653 20:15:20.777477
8654 20:15:20.777562 Set Vref, RX VrefLevel [Byte0]: 34
8655 20:15:20.780482 [Byte1]: 34
8656 20:15:20.785209
8657 20:15:20.785288 Set Vref, RX VrefLevel [Byte0]: 35
8658 20:15:20.788225 [Byte1]: 35
8659 20:15:20.793014
8660 20:15:20.793094 Set Vref, RX VrefLevel [Byte0]: 36
8661 20:15:20.795952 [Byte1]: 36
8662 20:15:20.800409
8663 20:15:20.800490 Set Vref, RX VrefLevel [Byte0]: 37
8664 20:15:20.803596 [Byte1]: 37
8665 20:15:20.808278
8666 20:15:20.808359 Set Vref, RX VrefLevel [Byte0]: 38
8667 20:15:20.811222 [Byte1]: 38
8668 20:15:20.815419
8669 20:15:20.815500 Set Vref, RX VrefLevel [Byte0]: 39
8670 20:15:20.819386 [Byte1]: 39
8671 20:15:20.823111
8672 20:15:20.823191 Set Vref, RX VrefLevel [Byte0]: 40
8673 20:15:20.826967 [Byte1]: 40
8674 20:15:20.830561
8675 20:15:20.830641 Set Vref, RX VrefLevel [Byte0]: 41
8676 20:15:20.834069 [Byte1]: 41
8677 20:15:20.838186
8678 20:15:20.838268 Set Vref, RX VrefLevel [Byte0]: 42
8679 20:15:20.841782 [Byte1]: 42
8680 20:15:20.845996
8681 20:15:20.846077 Set Vref, RX VrefLevel [Byte0]: 43
8682 20:15:20.849530 [Byte1]: 43
8683 20:15:20.853500
8684 20:15:20.853581 Set Vref, RX VrefLevel [Byte0]: 44
8685 20:15:20.856833 [Byte1]: 44
8686 20:15:20.862292
8687 20:15:20.862373 Set Vref, RX VrefLevel [Byte0]: 45
8688 20:15:20.864333 [Byte1]: 45
8689 20:15:20.868592
8690 20:15:20.868674 Set Vref, RX VrefLevel [Byte0]: 46
8691 20:15:20.871826 [Byte1]: 46
8692 20:15:20.877013
8693 20:15:20.877095 Set Vref, RX VrefLevel [Byte0]: 47
8694 20:15:20.879609 [Byte1]: 47
8695 20:15:20.883737
8696 20:15:20.883819 Set Vref, RX VrefLevel [Byte0]: 48
8697 20:15:20.887372 [Byte1]: 48
8698 20:15:20.892015
8699 20:15:20.892095 Set Vref, RX VrefLevel [Byte0]: 49
8700 20:15:20.894770 [Byte1]: 49
8701 20:15:20.900007
8702 20:15:20.900088 Set Vref, RX VrefLevel [Byte0]: 50
8703 20:15:20.902397 [Byte1]: 50
8704 20:15:20.906948
8705 20:15:20.907029 Set Vref, RX VrefLevel [Byte0]: 51
8706 20:15:20.909935 [Byte1]: 51
8707 20:15:20.914511
8708 20:15:20.914592 Set Vref, RX VrefLevel [Byte0]: 52
8709 20:15:20.918428 [Byte1]: 52
8710 20:15:20.921979
8711 20:15:20.922059 Set Vref, RX VrefLevel [Byte0]: 53
8712 20:15:20.925166 [Byte1]: 53
8713 20:15:20.929925
8714 20:15:20.930007 Set Vref, RX VrefLevel [Byte0]: 54
8715 20:15:20.933492 [Byte1]: 54
8716 20:15:20.937766
8717 20:15:20.937847 Set Vref, RX VrefLevel [Byte0]: 55
8718 20:15:20.941347 [Byte1]: 55
8719 20:15:20.944861
8720 20:15:20.944942 Set Vref, RX VrefLevel [Byte0]: 56
8721 20:15:20.948249 [Byte1]: 56
8722 20:15:20.952765
8723 20:15:20.952848 Set Vref, RX VrefLevel [Byte0]: 57
8724 20:15:20.956058 [Byte1]: 57
8725 20:15:20.960686
8726 20:15:20.960768 Set Vref, RX VrefLevel [Byte0]: 58
8727 20:15:20.963600 [Byte1]: 58
8728 20:15:20.967532
8729 20:15:20.967613 Set Vref, RX VrefLevel [Byte0]: 59
8730 20:15:20.971377 [Byte1]: 59
8731 20:15:20.975876
8732 20:15:20.975957 Set Vref, RX VrefLevel [Byte0]: 60
8733 20:15:20.978425 [Byte1]: 60
8734 20:15:20.982930
8735 20:15:20.983012 Set Vref, RX VrefLevel [Byte0]: 61
8736 20:15:20.986151 [Byte1]: 61
8737 20:15:20.990826
8738 20:15:20.990908 Set Vref, RX VrefLevel [Byte0]: 62
8739 20:15:20.993933 [Byte1]: 62
8740 20:15:20.997946
8741 20:15:20.998027 Set Vref, RX VrefLevel [Byte0]: 63
8742 20:15:21.002002 [Byte1]: 63
8743 20:15:21.005589
8744 20:15:21.005670 Set Vref, RX VrefLevel [Byte0]: 64
8745 20:15:21.009091 [Byte1]: 64
8746 20:15:21.013737
8747 20:15:21.013819 Set Vref, RX VrefLevel [Byte0]: 65
8748 20:15:21.016797 [Byte1]: 65
8749 20:15:21.021565
8750 20:15:21.021646 Set Vref, RX VrefLevel [Byte0]: 66
8751 20:15:21.024536 [Byte1]: 66
8752 20:15:21.028373
8753 20:15:21.028454 Set Vref, RX VrefLevel [Byte0]: 67
8754 20:15:21.032337 [Byte1]: 67
8755 20:15:21.035963
8756 20:15:21.036044 Set Vref, RX VrefLevel [Byte0]: 68
8757 20:15:21.039882 [Byte1]: 68
8758 20:15:21.043787
8759 20:15:21.043869 Set Vref, RX VrefLevel [Byte0]: 69
8760 20:15:21.047342 [Byte1]: 69
8761 20:15:21.051841
8762 20:15:21.051922 Set Vref, RX VrefLevel [Byte0]: 70
8763 20:15:21.054965 [Byte1]: 70
8764 20:15:21.059237
8765 20:15:21.059330 Set Vref, RX VrefLevel [Byte0]: 71
8766 20:15:21.062157 [Byte1]: 71
8767 20:15:21.066559
8768 20:15:21.066660 Set Vref, RX VrefLevel [Byte0]: 72
8769 20:15:21.069817 [Byte1]: 72
8770 20:15:21.074502
8771 20:15:21.074623 Set Vref, RX VrefLevel [Byte0]: 73
8772 20:15:21.077704 [Byte1]: 73
8773 20:15:21.082426
8774 20:15:21.082560 Set Vref, RX VrefLevel [Byte0]: 74
8775 20:15:21.085552 [Byte1]: 74
8776 20:15:21.089458
8777 20:15:21.089630 Final RX Vref Byte 0 = 53 to rank0
8778 20:15:21.093346 Final RX Vref Byte 1 = 59 to rank0
8779 20:15:21.096834 Final RX Vref Byte 0 = 53 to rank1
8780 20:15:21.100220 Final RX Vref Byte 1 = 59 to rank1==
8781 20:15:21.102819 Dram Type= 6, Freq= 0, CH_1, rank 0
8782 20:15:21.109590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 20:15:21.109986 ==
8784 20:15:21.110296 DQS Delay:
8785 20:15:21.112680 DQS0 = 0, DQS1 = 0
8786 20:15:21.113064 DQM Delay:
8787 20:15:21.113395 DQM0 = 133, DQM1 = 127
8788 20:15:21.116311 DQ Delay:
8789 20:15:21.119378 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8790 20:15:21.123018 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8791 20:15:21.126352 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8792 20:15:21.129875 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8793 20:15:21.130295
8794 20:15:21.130628
8795 20:15:21.130937
8796 20:15:21.132594 [DramC_TX_OE_Calibration] TA2
8797 20:15:21.135629 Original DQ_B0 (3 6) =30, OEN = 27
8798 20:15:21.139588 Original DQ_B1 (3 6) =30, OEN = 27
8799 20:15:21.142498 24, 0x0, End_B0=24 End_B1=24
8800 20:15:21.145980 25, 0x0, End_B0=25 End_B1=25
8801 20:15:21.146063 26, 0x0, End_B0=26 End_B1=26
8802 20:15:21.148653 27, 0x0, End_B0=27 End_B1=27
8803 20:15:21.152501 28, 0x0, End_B0=28 End_B1=28
8804 20:15:21.155779 29, 0x0, End_B0=29 End_B1=29
8805 20:15:21.156207 30, 0x0, End_B0=30 End_B1=30
8806 20:15:21.159944 31, 0x4141, End_B0=30 End_B1=30
8807 20:15:21.162848 Byte0 end_step=30 best_step=27
8808 20:15:21.166247 Byte1 end_step=30 best_step=27
8809 20:15:21.169344 Byte0 TX OE(2T, 0.5T) = (3, 3)
8810 20:15:21.172373 Byte1 TX OE(2T, 0.5T) = (3, 3)
8811 20:15:21.172811
8812 20:15:21.173150
8813 20:15:21.179167 [DQSOSCAuto] RK0, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8814 20:15:21.182664 CH1 RK0: MR19=303, MR18=160C
8815 20:15:21.189698 CH1_RK0: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8816 20:15:21.190121
8817 20:15:21.192425 ----->DramcWriteLeveling(PI) begin...
8818 20:15:21.192852 ==
8819 20:15:21.195290 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 20:15:21.198846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 20:15:21.199281 ==
8822 20:15:21.202103 Write leveling (Byte 0): 23 => 23
8823 20:15:21.205647 Write leveling (Byte 1): 25 => 25
8824 20:15:21.208712 DramcWriteLeveling(PI) end<-----
8825 20:15:21.209132
8826 20:15:21.209472 ==
8827 20:15:21.212066 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 20:15:21.215312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 20:15:21.218893 ==
8830 20:15:21.219317 [Gating] SW mode calibration
8831 20:15:21.228614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8832 20:15:21.231824 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8833 20:15:21.235181 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 20:15:21.241803 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 20:15:21.246174 1 4 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
8836 20:15:21.248286 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8837 20:15:21.255124 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 20:15:21.258447 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 20:15:21.262093 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 20:15:21.268238 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 20:15:21.271494 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 20:15:21.274944 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 20:15:21.281544 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8844 20:15:21.284754 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8845 20:15:21.288641 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8846 20:15:21.294433 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 20:15:21.297899 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 20:15:21.300766 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 20:15:21.307811 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 20:15:21.310878 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 20:15:21.314073 1 6 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8852 20:15:21.320822 1 6 12 | B1->B0 | 4646 2828 | 0 1 | (0 0) (0 0)
8853 20:15:21.324150 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 20:15:21.326929 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 20:15:21.333763 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 20:15:21.337334 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 20:15:21.340788 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 20:15:21.347391 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 20:15:21.350486 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 20:15:21.353940 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8861 20:15:21.360312 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 20:15:21.363745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 20:15:21.367811 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 20:15:21.373876 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 20:15:21.378687 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 20:15:21.379757 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 20:15:21.386690 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 20:15:21.389627 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 20:15:21.393312 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 20:15:21.399861 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 20:15:21.403352 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 20:15:21.406140 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 20:15:21.413346 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 20:15:21.416477 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 20:15:21.419370 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8876 20:15:21.427056 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8877 20:15:21.429731 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8878 20:15:21.432937 Total UI for P1: 0, mck2ui 16
8879 20:15:21.436575 best dqsien dly found for B1: ( 1, 9, 10)
8880 20:15:21.439500 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 20:15:21.442773 Total UI for P1: 0, mck2ui 16
8882 20:15:21.446089 best dqsien dly found for B0: ( 1, 9, 12)
8883 20:15:21.449841 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8884 20:15:21.452426 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8885 20:15:21.456070
8886 20:15:21.459372 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8887 20:15:21.462690 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8888 20:15:21.465685 [Gating] SW calibration Done
8889 20:15:21.466257 ==
8890 20:15:21.469113 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 20:15:21.472474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 20:15:21.472561 ==
8893 20:15:21.475286 RX Vref Scan: 0
8894 20:15:21.475368
8895 20:15:21.475434 RX Vref 0 -> 0, step: 1
8896 20:15:21.475496
8897 20:15:21.479186 RX Delay 0 -> 252, step: 8
8898 20:15:21.481651 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8899 20:15:21.488196 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8900 20:15:21.491591 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8901 20:15:21.494991 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8902 20:15:21.498751 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8903 20:15:21.502132 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8904 20:15:21.507902 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8905 20:15:21.511107 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8906 20:15:21.514418 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8907 20:15:21.518093 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8908 20:15:21.520955 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8909 20:15:21.527574 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8910 20:15:21.531869 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8911 20:15:21.534540 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8912 20:15:21.538228 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8913 20:15:21.544651 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8914 20:15:21.544734 ==
8915 20:15:21.547614 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 20:15:21.550643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 20:15:21.550726 ==
8918 20:15:21.550792 DQS Delay:
8919 20:15:21.554015 DQS0 = 0, DQS1 = 0
8920 20:15:21.554097 DQM Delay:
8921 20:15:21.557593 DQM0 = 136, DQM1 = 129
8922 20:15:21.557674 DQ Delay:
8923 20:15:21.560474 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8924 20:15:21.564237 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8925 20:15:21.567227 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8926 20:15:21.571224 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8927 20:15:21.571310
8928 20:15:21.574051
8929 20:15:21.574134 ==
8930 20:15:21.576970 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 20:15:21.580479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 20:15:21.580562 ==
8933 20:15:21.580633
8934 20:15:21.580694
8935 20:15:21.583559 TX Vref Scan disable
8936 20:15:21.583641 == TX Byte 0 ==
8937 20:15:21.590419 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8938 20:15:21.594082 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 20:15:21.594164 == TX Byte 1 ==
8940 20:15:21.600569 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8941 20:15:21.603295 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8942 20:15:21.603377 ==
8943 20:15:21.606799 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 20:15:21.610483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 20:15:21.610650 ==
8946 20:15:21.624061
8947 20:15:21.626873 TX Vref early break, caculate TX vref
8948 20:15:21.630033 TX Vref=16, minBit 0, minWin=22, winSum=382
8949 20:15:21.633377 TX Vref=18, minBit 0, minWin=23, winSum=392
8950 20:15:21.636625 TX Vref=20, minBit 0, minWin=23, winSum=395
8951 20:15:21.639947 TX Vref=22, minBit 0, minWin=24, winSum=406
8952 20:15:21.643245 TX Vref=24, minBit 5, minWin=24, winSum=417
8953 20:15:21.649844 TX Vref=26, minBit 0, minWin=24, winSum=419
8954 20:15:21.653691 TX Vref=28, minBit 0, minWin=24, winSum=418
8955 20:15:21.656424 TX Vref=30, minBit 0, minWin=24, winSum=416
8956 20:15:21.660009 TX Vref=32, minBit 0, minWin=23, winSum=406
8957 20:15:21.663000 TX Vref=34, minBit 0, minWin=22, winSum=397
8958 20:15:21.669643 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 26
8959 20:15:21.669771
8960 20:15:21.673105 Final TX Range 0 Vref 26
8961 20:15:21.673188
8962 20:15:21.673254 ==
8963 20:15:21.676373 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 20:15:21.680104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 20:15:21.680186 ==
8966 20:15:21.680252
8967 20:15:21.680313
8968 20:15:21.682953 TX Vref Scan disable
8969 20:15:21.689249 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8970 20:15:21.689331 == TX Byte 0 ==
8971 20:15:21.692628 u2DelayCellOfst[0]=18 cells (5 PI)
8972 20:15:21.696647 u2DelayCellOfst[1]=11 cells (3 PI)
8973 20:15:21.699537 u2DelayCellOfst[2]=0 cells (0 PI)
8974 20:15:21.702406 u2DelayCellOfst[3]=7 cells (2 PI)
8975 20:15:21.705901 u2DelayCellOfst[4]=7 cells (2 PI)
8976 20:15:21.709369 u2DelayCellOfst[5]=18 cells (5 PI)
8977 20:15:21.712409 u2DelayCellOfst[6]=18 cells (5 PI)
8978 20:15:21.715633 u2DelayCellOfst[7]=3 cells (1 PI)
8979 20:15:21.719698 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8980 20:15:21.722189 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8981 20:15:21.725292 == TX Byte 1 ==
8982 20:15:21.729154 u2DelayCellOfst[8]=0 cells (0 PI)
8983 20:15:21.732573 u2DelayCellOfst[9]=7 cells (2 PI)
8984 20:15:21.735344 u2DelayCellOfst[10]=14 cells (4 PI)
8985 20:15:21.735426 u2DelayCellOfst[11]=7 cells (2 PI)
8986 20:15:21.739014 u2DelayCellOfst[12]=18 cells (5 PI)
8987 20:15:21.741905 u2DelayCellOfst[13]=18 cells (5 PI)
8988 20:15:21.745299 u2DelayCellOfst[14]=18 cells (5 PI)
8989 20:15:21.748658 u2DelayCellOfst[15]=18 cells (5 PI)
8990 20:15:21.755323 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8991 20:15:21.758685 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8992 20:15:21.758909 DramC Write-DBI on
8993 20:15:21.759034 ==
8994 20:15:21.761942 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 20:15:21.769313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 20:15:21.769401 ==
8997 20:15:21.769468
8998 20:15:21.769529
8999 20:15:21.772029 TX Vref Scan disable
9000 20:15:21.772113 == TX Byte 0 ==
9001 20:15:21.778781 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9002 20:15:21.778959 == TX Byte 1 ==
9003 20:15:21.781762 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9004 20:15:21.785706 DramC Write-DBI off
9005 20:15:21.785885
9006 20:15:21.785977 [DATLAT]
9007 20:15:21.788884 Freq=1600, CH1 RK1
9008 20:15:21.789078
9009 20:15:21.789177 DATLAT Default: 0xf
9010 20:15:21.792214 0, 0xFFFF, sum = 0
9011 20:15:21.792415 1, 0xFFFF, sum = 0
9012 20:15:21.794913 2, 0xFFFF, sum = 0
9013 20:15:21.795097 3, 0xFFFF, sum = 0
9014 20:15:21.798482 4, 0xFFFF, sum = 0
9015 20:15:21.798681 5, 0xFFFF, sum = 0
9016 20:15:21.801636 6, 0xFFFF, sum = 0
9017 20:15:21.801839 7, 0xFFFF, sum = 0
9018 20:15:21.804742 8, 0xFFFF, sum = 0
9019 20:15:21.808129 9, 0xFFFF, sum = 0
9020 20:15:21.808283 10, 0xFFFF, sum = 0
9021 20:15:21.811473 11, 0xFFFF, sum = 0
9022 20:15:21.811557 12, 0xFFFF, sum = 0
9023 20:15:21.814450 13, 0xFFFF, sum = 0
9024 20:15:21.814539 14, 0x0, sum = 1
9025 20:15:21.817986 15, 0x0, sum = 2
9026 20:15:21.818075 16, 0x0, sum = 3
9027 20:15:21.821160 17, 0x0, sum = 4
9028 20:15:21.821256 best_step = 15
9029 20:15:21.821331
9030 20:15:21.821403 ==
9031 20:15:21.824318 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 20:15:21.828009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 20:15:21.831121 ==
9034 20:15:21.831232 RX Vref Scan: 0
9035 20:15:21.831320
9036 20:15:21.834577 RX Vref 0 -> 0, step: 1
9037 20:15:21.834699
9038 20:15:21.837501 RX Delay 11 -> 252, step: 4
9039 20:15:21.840724 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9040 20:15:21.844421 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9041 20:15:21.847133 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9042 20:15:21.854514 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9043 20:15:21.857614 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9044 20:15:21.860969 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9045 20:15:21.864629 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9046 20:15:21.867584 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9047 20:15:21.874358 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9048 20:15:21.877736 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9049 20:15:21.881452 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9050 20:15:21.883977 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9051 20:15:21.887247 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9052 20:15:21.894571 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9053 20:15:21.897452 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9054 20:15:21.900575 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9055 20:15:21.901035 ==
9056 20:15:21.904442 Dram Type= 6, Freq= 0, CH_1, rank 1
9057 20:15:21.907527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9058 20:15:21.910295 ==
9059 20:15:21.910724 DQS Delay:
9060 20:15:21.911065 DQS0 = 0, DQS1 = 0
9061 20:15:21.914027 DQM Delay:
9062 20:15:21.914453 DQM0 = 133, DQM1 = 126
9063 20:15:21.917289 DQ Delay:
9064 20:15:21.920939 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9065 20:15:21.924149 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9066 20:15:21.927314 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9067 20:15:21.930427 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9068 20:15:21.930853
9069 20:15:21.931189
9070 20:15:21.931504
9071 20:15:21.933889 [DramC_TX_OE_Calibration] TA2
9072 20:15:21.936927 Original DQ_B0 (3 6) =30, OEN = 27
9073 20:15:21.940741 Original DQ_B1 (3 6) =30, OEN = 27
9074 20:15:21.943392 24, 0x0, End_B0=24 End_B1=24
9075 20:15:21.943856 25, 0x0, End_B0=25 End_B1=25
9076 20:15:21.946576 26, 0x0, End_B0=26 End_B1=26
9077 20:15:21.950574 27, 0x0, End_B0=27 End_B1=27
9078 20:15:21.953146 28, 0x0, End_B0=28 End_B1=28
9079 20:15:21.956903 29, 0x0, End_B0=29 End_B1=29
9080 20:15:21.957330 30, 0x0, End_B0=30 End_B1=30
9081 20:15:21.960974 31, 0x4141, End_B0=30 End_B1=30
9082 20:15:21.963795 Byte0 end_step=30 best_step=27
9083 20:15:21.966888 Byte1 end_step=30 best_step=27
9084 20:15:21.970162 Byte0 TX OE(2T, 0.5T) = (3, 3)
9085 20:15:21.973241 Byte1 TX OE(2T, 0.5T) = (3, 3)
9086 20:15:21.973753
9087 20:15:21.974185
9088 20:15:21.980137 [DQSOSCAuto] RK1, (LSB)MR18= 0xa06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9089 20:15:21.983263 CH1 RK1: MR19=303, MR18=A06
9090 20:15:21.989529 CH1_RK1: MR19=0x303, MR18=0xA06, DQSOSC=404, MR23=63, INC=22, DEC=15
9091 20:15:21.992747 [RxdqsGatingPostProcess] freq 1600
9092 20:15:21.995962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9093 20:15:21.999928 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 20:15:22.002698 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 20:15:22.007025 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 20:15:22.009711 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 20:15:22.013064 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 20:15:22.015716 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 20:15:22.018896 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 20:15:22.022491 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 20:15:22.025558 Pre-setting of DQS Precalculation
9102 20:15:22.028932 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9103 20:15:22.035996 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9104 20:15:22.045831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 20:15:22.046363
9106 20:15:22.046710
9107 20:15:22.048774 [Calibration Summary] 3200 Mbps
9108 20:15:22.049197 CH 0, Rank 0
9109 20:15:22.052235 SW Impedance : PASS
9110 20:15:22.052660 DUTY Scan : NO K
9111 20:15:22.055542 ZQ Calibration : PASS
9112 20:15:22.058930 Jitter Meter : NO K
9113 20:15:22.059472 CBT Training : PASS
9114 20:15:22.062192 Write leveling : PASS
9115 20:15:22.065391 RX DQS gating : PASS
9116 20:15:22.066004 RX DQ/DQS(RDDQC) : PASS
9117 20:15:22.068355 TX DQ/DQS : PASS
9118 20:15:22.072069 RX DATLAT : PASS
9119 20:15:22.072599 RX DQ/DQS(Engine): PASS
9120 20:15:22.075447 TX OE : PASS
9121 20:15:22.076120 All Pass.
9122 20:15:22.076614
9123 20:15:22.078144 CH 0, Rank 1
9124 20:15:22.078729 SW Impedance : PASS
9125 20:15:22.081360 DUTY Scan : NO K
9126 20:15:22.084623 ZQ Calibration : PASS
9127 20:15:22.085091 Jitter Meter : NO K
9128 20:15:22.087974 CBT Training : PASS
9129 20:15:22.088395 Write leveling : PASS
9130 20:15:22.091976 RX DQS gating : PASS
9131 20:15:22.094591 RX DQ/DQS(RDDQC) : PASS
9132 20:15:22.095063 TX DQ/DQS : PASS
9133 20:15:22.098211 RX DATLAT : PASS
9134 20:15:22.101454 RX DQ/DQS(Engine): PASS
9135 20:15:22.101974 TX OE : PASS
9136 20:15:22.104410 All Pass.
9137 20:15:22.104886
9138 20:15:22.105231 CH 1, Rank 0
9139 20:15:22.108046 SW Impedance : PASS
9140 20:15:22.108618 DUTY Scan : NO K
9141 20:15:22.111124 ZQ Calibration : PASS
9142 20:15:22.114615 Jitter Meter : NO K
9143 20:15:22.115110 CBT Training : PASS
9144 20:15:22.118152 Write leveling : PASS
9145 20:15:22.121164 RX DQS gating : PASS
9146 20:15:22.121643 RX DQ/DQS(RDDQC) : PASS
9147 20:15:22.124623 TX DQ/DQS : PASS
9148 20:15:22.127643 RX DATLAT : PASS
9149 20:15:22.128113 RX DQ/DQS(Engine): PASS
9150 20:15:22.130690 TX OE : PASS
9151 20:15:22.131113 All Pass.
9152 20:15:22.131452
9153 20:15:22.134225 CH 1, Rank 1
9154 20:15:22.134791 SW Impedance : PASS
9155 20:15:22.137667 DUTY Scan : NO K
9156 20:15:22.140599 ZQ Calibration : PASS
9157 20:15:22.141042 Jitter Meter : NO K
9158 20:15:22.143877 CBT Training : PASS
9159 20:15:22.147526 Write leveling : PASS
9160 20:15:22.147996 RX DQS gating : PASS
9161 20:15:22.150719 RX DQ/DQS(RDDQC) : PASS
9162 20:15:22.154623 TX DQ/DQS : PASS
9163 20:15:22.155050 RX DATLAT : PASS
9164 20:15:22.157191 RX DQ/DQS(Engine): PASS
9165 20:15:22.160749 TX OE : PASS
9166 20:15:22.161172 All Pass.
9167 20:15:22.161507
9168 20:15:22.161819 DramC Write-DBI on
9169 20:15:22.164033 PER_BANK_REFRESH: Hybrid Mode
9170 20:15:22.167049 TX_TRACKING: ON
9171 20:15:22.173903 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9172 20:15:22.183359 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9173 20:15:22.189887 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9174 20:15:22.193124 [FAST_K] Save calibration result to emmc
9175 20:15:22.197111 sync common calibartion params.
9176 20:15:22.199540 sync cbt_mode0:1, 1:1
9177 20:15:22.199622 dram_init: ddr_geometry: 2
9178 20:15:22.203339 dram_init: ddr_geometry: 2
9179 20:15:22.206179 dram_init: ddr_geometry: 2
9180 20:15:22.209535 0:dram_rank_size:100000000
9181 20:15:22.209624 1:dram_rank_size:100000000
9182 20:15:22.216432 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9183 20:15:22.219313 DFS_SHUFFLE_HW_MODE: ON
9184 20:15:22.222656 dramc_set_vcore_voltage set vcore to 725000
9185 20:15:22.222758 Read voltage for 1600, 0
9186 20:15:22.225671 Vio18 = 0
9187 20:15:22.225782 Vcore = 725000
9188 20:15:22.225871 Vdram = 0
9189 20:15:22.228836 Vddq = 0
9190 20:15:22.228957 Vmddr = 0
9191 20:15:22.232982 switch to 3200 Mbps bootup
9192 20:15:22.233104 [DramcRunTimeConfig]
9193 20:15:22.236133 PHYPLL
9194 20:15:22.236267 DPM_CONTROL_AFTERK: ON
9195 20:15:22.239483 PER_BANK_REFRESH: ON
9196 20:15:22.242690 REFRESH_OVERHEAD_REDUCTION: ON
9197 20:15:22.243113 CMD_PICG_NEW_MODE: OFF
9198 20:15:22.245874 XRTWTW_NEW_MODE: ON
9199 20:15:22.246293 XRTRTR_NEW_MODE: ON
9200 20:15:22.249667 TX_TRACKING: ON
9201 20:15:22.250087 RDSEL_TRACKING: OFF
9202 20:15:22.252225 DQS Precalculation for DVFS: ON
9203 20:15:22.255603 RX_TRACKING: OFF
9204 20:15:22.256082 HW_GATING DBG: ON
9205 20:15:22.258759 ZQCS_ENABLE_LP4: ON
9206 20:15:22.259180 RX_PICG_NEW_MODE: ON
9207 20:15:22.262220 TX_PICG_NEW_MODE: ON
9208 20:15:22.265544 ENABLE_RX_DCM_DPHY: ON
9209 20:15:22.265965 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9210 20:15:22.268611 DUMMY_READ_FOR_TRACKING: OFF
9211 20:15:22.272262 !!! SPM_CONTROL_AFTERK: OFF
9212 20:15:22.275784 !!! SPM could not control APHY
9213 20:15:22.278905 IMPEDANCE_TRACKING: ON
9214 20:15:22.279322 TEMP_SENSOR: ON
9215 20:15:22.282180 HW_SAVE_FOR_SR: OFF
9216 20:15:22.282601 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9217 20:15:22.288476 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9218 20:15:22.288899 Read ODT Tracking: ON
9219 20:15:22.291898 Refresh Rate DeBounce: ON
9220 20:15:22.295560 DFS_NO_QUEUE_FLUSH: ON
9221 20:15:22.296020 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9222 20:15:22.298230 ENABLE_DFS_RUNTIME_MRW: OFF
9223 20:15:22.301881 DDR_RESERVE_NEW_MODE: ON
9224 20:15:22.305125 MR_CBT_SWITCH_FREQ: ON
9225 20:15:22.305544 =========================
9226 20:15:22.324556 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9227 20:15:22.327337 dram_init: ddr_geometry: 2
9228 20:15:22.346009 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9229 20:15:22.350049 dram_init: dram init end (result: 0)
9230 20:15:22.355505 DRAM-K: Full calibration passed in 24612 msecs
9231 20:15:22.358973 MRC: failed to locate region type 0.
9232 20:15:22.359397 DRAM rank0 size:0x100000000,
9233 20:15:22.362447 DRAM rank1 size=0x100000000
9234 20:15:22.372970 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9235 20:15:22.379192 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9236 20:15:22.385874 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9237 20:15:22.395802 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9238 20:15:22.396361 DRAM rank0 size:0x100000000,
9239 20:15:22.398601 DRAM rank1 size=0x100000000
9240 20:15:22.399021 CBMEM:
9241 20:15:22.402433 IMD: root @ 0xfffff000 254 entries.
9242 20:15:22.405452 IMD: root @ 0xffffec00 62 entries.
9243 20:15:22.409401 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9244 20:15:22.415399 WARNING: RO_VPD is uninitialized or empty.
9245 20:15:22.418579 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9246 20:15:22.426716 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9247 20:15:22.438676 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9248 20:15:22.450103 BS: romstage times (exec / console): total (unknown) / 24107 ms
9249 20:15:22.450532
9250 20:15:22.450872
9251 20:15:22.459866 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9252 20:15:22.463393 ARM64: Exception handlers installed.
9253 20:15:22.466641 ARM64: Testing exception
9254 20:15:22.469736 ARM64: Done test exception
9255 20:15:22.470175 Enumerating buses...
9256 20:15:22.473183 Show all devs... Before device enumeration.
9257 20:15:22.476838 Root Device: enabled 1
9258 20:15:22.479934 CPU_CLUSTER: 0: enabled 1
9259 20:15:22.480455 CPU: 00: enabled 1
9260 20:15:22.483235 Compare with tree...
9261 20:15:22.483743 Root Device: enabled 1
9262 20:15:22.486312 CPU_CLUSTER: 0: enabled 1
9263 20:15:22.489559 CPU: 00: enabled 1
9264 20:15:22.490156 Root Device scanning...
9265 20:15:22.493784 scan_static_bus for Root Device
9266 20:15:22.496109 CPU_CLUSTER: 0 enabled
9267 20:15:22.499729 scan_static_bus for Root Device done
9268 20:15:22.502748 scan_bus: bus Root Device finished in 8 msecs
9269 20:15:22.503350 done
9270 20:15:22.510337 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9271 20:15:22.512512 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9272 20:15:22.519776 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9273 20:15:22.526185 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9274 20:15:22.526608 Allocating resources...
9275 20:15:22.529218 Reading resources...
9276 20:15:22.532696 Root Device read_resources bus 0 link: 0
9277 20:15:22.535286 DRAM rank0 size:0x100000000,
9278 20:15:22.535748 DRAM rank1 size=0x100000000
9279 20:15:22.542254 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9280 20:15:22.542926 CPU: 00 missing read_resources
9281 20:15:22.548583 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9282 20:15:22.552310 Root Device read_resources bus 0 link: 0 done
9283 20:15:22.555133 Done reading resources.
9284 20:15:22.558346 Show resources in subtree (Root Device)...After reading.
9285 20:15:22.562092 Root Device child on link 0 CPU_CLUSTER: 0
9286 20:15:22.564962 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 20:15:22.575173 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 20:15:22.575426 CPU: 00
9289 20:15:22.581171 Root Device assign_resources, bus 0 link: 0
9290 20:15:22.584864 CPU_CLUSTER: 0 missing set_resources
9291 20:15:22.587863 Root Device assign_resources, bus 0 link: 0 done
9292 20:15:22.591651 Done setting resources.
9293 20:15:22.594802 Show resources in subtree (Root Device)...After assigning values.
9294 20:15:22.598061 Root Device child on link 0 CPU_CLUSTER: 0
9295 20:15:22.604438 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 20:15:22.611174 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 20:15:22.614288 CPU: 00
9298 20:15:22.614467 Done allocating resources.
9299 20:15:22.621129 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9300 20:15:22.621329 Enabling resources...
9301 20:15:22.624984 done.
9302 20:15:22.627717 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9303 20:15:22.631054 Initializing devices...
9304 20:15:22.631231 Root Device init
9305 20:15:22.634421 init hardware done!
9306 20:15:22.634602 0x00000018: ctrlr->caps
9307 20:15:22.637835 52.000 MHz: ctrlr->f_max
9308 20:15:22.640608 0.400 MHz: ctrlr->f_min
9309 20:15:22.644244 0x40ff8080: ctrlr->voltages
9310 20:15:22.644429 sclk: 390625
9311 20:15:22.644574 Bus Width = 1
9312 20:15:22.648044 sclk: 390625
9313 20:15:22.648282 Bus Width = 1
9314 20:15:22.650723 Early init status = 3
9315 20:15:22.653939 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9316 20:15:22.657719 in-header: 03 fc 00 00 01 00 00 00
9317 20:15:22.661345 in-data: 00
9318 20:15:22.664843 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9319 20:15:22.668919 in-header: 03 fd 00 00 00 00 00 00
9320 20:15:22.672129 in-data:
9321 20:15:22.675336 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9322 20:15:22.678481 in-header: 03 fc 00 00 01 00 00 00
9323 20:15:22.682172 in-data: 00
9324 20:15:22.685519 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9325 20:15:22.690943 in-header: 03 fd 00 00 00 00 00 00
9326 20:15:22.693632 in-data:
9327 20:15:22.696738 [SSUSB] Setting up USB HOST controller...
9328 20:15:22.700067 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9329 20:15:22.703735 [SSUSB] phy power-on done.
9330 20:15:22.706360 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9331 20:15:22.712979 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9332 20:15:22.716246 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9333 20:15:22.722916 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9334 20:15:22.729727 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9335 20:15:22.735970 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9336 20:15:22.742834 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9337 20:15:22.750076 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9338 20:15:22.752648 SPM: binary array size = 0x9dc
9339 20:15:22.756163 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9340 20:15:22.762532 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9341 20:15:22.769244 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9342 20:15:22.776257 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9343 20:15:22.779098 configure_display: Starting display init
9344 20:15:22.813545 anx7625_power_on_init: Init interface.
9345 20:15:22.816764 anx7625_disable_pd_protocol: Disabled PD feature.
9346 20:15:22.820453 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9347 20:15:22.848077 anx7625_start_dp_work: Secure OCM version=00
9348 20:15:22.850956 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9349 20:15:22.865725 sp_tx_get_edid_block: EDID Block = 1
9350 20:15:22.968295 Extracted contents:
9351 20:15:22.971848 header: 00 ff ff ff ff ff ff 00
9352 20:15:22.975696 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9353 20:15:22.978111 version: 01 04
9354 20:15:22.982031 basic params: 95 1f 11 78 0a
9355 20:15:22.984920 chroma info: 76 90 94 55 54 90 27 21 50 54
9356 20:15:22.988496 established: 00 00 00
9357 20:15:22.994856 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9358 20:15:22.998359 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9359 20:15:23.004658 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 20:15:23.011433 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9361 20:15:23.017746 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9362 20:15:23.020875 extensions: 00
9363 20:15:23.021324 checksum: fb
9364 20:15:23.021667
9365 20:15:23.028443 Manufacturer: IVO Model 57d Serial Number 0
9366 20:15:23.028866 Made week 0 of 2020
9367 20:15:23.030804 EDID version: 1.4
9368 20:15:23.031222 Digital display
9369 20:15:23.034616 6 bits per primary color channel
9370 20:15:23.037272 DisplayPort interface
9371 20:15:23.037691 Maximum image size: 31 cm x 17 cm
9372 20:15:23.041062 Gamma: 220%
9373 20:15:23.041479 Check DPMS levels
9374 20:15:23.047592 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9375 20:15:23.050989 First detailed timing is preferred timing
9376 20:15:23.051510 Established timings supported:
9377 20:15:23.054101 Standard timings supported:
9378 20:15:23.057332 Detailed timings
9379 20:15:23.060962 Hex of detail: 383680a07038204018303c0035ae10000019
9380 20:15:23.067741 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9381 20:15:23.070830 0780 0798 07c8 0820 hborder 0
9382 20:15:23.073818 0438 043b 0447 0458 vborder 0
9383 20:15:23.077034 -hsync -vsync
9384 20:15:23.077598 Did detailed timing
9385 20:15:23.083487 Hex of detail: 000000000000000000000000000000000000
9386 20:15:23.086840 Manufacturer-specified data, tag 0
9387 20:15:23.090150 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9388 20:15:23.093306 ASCII string: InfoVision
9389 20:15:23.096846 Hex of detail: 000000fe00523134304e574635205248200a
9390 20:15:23.099926 ASCII string: R140NWF5 RH
9391 20:15:23.100343 Checksum
9392 20:15:23.104029 Checksum: 0xfb (valid)
9393 20:15:23.106800 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9394 20:15:23.109729 DSI data_rate: 832800000 bps
9395 20:15:23.116503 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9396 20:15:23.119816 anx7625_parse_edid: pixelclock(138800).
9397 20:15:23.122786 hactive(1920), hsync(48), hfp(24), hbp(88)
9398 20:15:23.126289 vactive(1080), vsync(12), vfp(3), vbp(17)
9399 20:15:23.129422 anx7625_dsi_config: config dsi.
9400 20:15:23.136528 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9401 20:15:23.151552 anx7625_dsi_config: success to config DSI
9402 20:15:23.153584 anx7625_dp_start: MIPI phy setup OK.
9403 20:15:23.157262 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9404 20:15:23.160498 mtk_ddp_mode_set invalid vrefresh 60
9405 20:15:23.164154 main_disp_path_setup
9406 20:15:23.164574 ovl_layer_smi_id_en
9407 20:15:23.167111 ovl_layer_smi_id_en
9408 20:15:23.167535 ccorr_config
9409 20:15:23.167930 aal_config
9410 20:15:23.170750 gamma_config
9411 20:15:23.171168 postmask_config
9412 20:15:23.173940 dither_config
9413 20:15:23.176895 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9414 20:15:23.183457 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9415 20:15:23.186480 Root Device init finished in 551 msecs
9416 20:15:23.190268 CPU_CLUSTER: 0 init
9417 20:15:23.197694 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9418 20:15:23.203401 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9419 20:15:23.203960 APU_MBOX 0x190000b0 = 0x10001
9420 20:15:23.206661 APU_MBOX 0x190001b0 = 0x10001
9421 20:15:23.209673 APU_MBOX 0x190005b0 = 0x10001
9422 20:15:23.212789 APU_MBOX 0x190006b0 = 0x10001
9423 20:15:23.219742 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9424 20:15:23.229383 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9425 20:15:23.242523 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9426 20:15:23.248384 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9427 20:15:23.260135 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9428 20:15:23.269120 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9429 20:15:23.272700 CPU_CLUSTER: 0 init finished in 81 msecs
9430 20:15:23.276077 Devices initialized
9431 20:15:23.278853 Show all devs... After init.
9432 20:15:23.279514 Root Device: enabled 1
9433 20:15:23.282604 CPU_CLUSTER: 0: enabled 1
9434 20:15:23.286094 CPU: 00: enabled 1
9435 20:15:23.288930 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9436 20:15:23.292239 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9437 20:15:23.295725 ELOG: NV offset 0x57f000 size 0x1000
9438 20:15:23.302591 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9439 20:15:23.309002 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9440 20:15:23.312780 ELOG: Event(17) added with size 13 at 2024-03-03 20:15:23 UTC
9441 20:15:23.319402 out: cmd=0x121: 03 db 21 01 00 00 00 00
9442 20:15:23.321949 in-header: 03 af 00 00 2c 00 00 00
9443 20:15:23.331850 in-data: b0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9444 20:15:23.338621 ELOG: Event(A1) added with size 10 at 2024-03-03 20:15:23 UTC
9445 20:15:23.344876 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9446 20:15:23.351609 ELOG: Event(A0) added with size 9 at 2024-03-03 20:15:23 UTC
9447 20:15:23.355167 elog_add_boot_reason: Logged dev mode boot
9448 20:15:23.361479 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9449 20:15:23.361908 Finalize devices...
9450 20:15:23.365418 Devices finalized
9451 20:15:23.367786 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9452 20:15:23.371167 Writing coreboot table at 0xffe64000
9453 20:15:23.377849 0. 000000000010a000-0000000000113fff: RAMSTAGE
9454 20:15:23.381181 1. 0000000040000000-00000000400fffff: RAM
9455 20:15:23.385017 2. 0000000040100000-000000004032afff: RAMSTAGE
9456 20:15:23.387746 3. 000000004032b000-00000000545fffff: RAM
9457 20:15:23.391335 4. 0000000054600000-000000005465ffff: BL31
9458 20:15:23.394510 5. 0000000054660000-00000000ffe63fff: RAM
9459 20:15:23.401057 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9460 20:15:23.404102 7. 0000000100000000-000000023fffffff: RAM
9461 20:15:23.407634 Passing 5 GPIOs to payload:
9462 20:15:23.411798 NAME | PORT | POLARITY | VALUE
9463 20:15:23.417607 EC in RW | 0x000000aa | low | undefined
9464 20:15:23.420630 EC interrupt | 0x00000005 | low | undefined
9465 20:15:23.427302 TPM interrupt | 0x000000ab | high | undefined
9466 20:15:23.430526 SD card detect | 0x00000011 | high | undefined
9467 20:15:23.434080 speaker enable | 0x00000093 | high | undefined
9468 20:15:23.437386 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9469 20:15:23.440809 in-header: 03 f9 00 00 02 00 00 00
9470 20:15:23.444482 in-data: 02 00
9471 20:15:23.447486 ADC[4]: Raw value=900073 ID=7
9472 20:15:23.450785 ADC[3]: Raw value=213652 ID=1
9473 20:15:23.451209 RAM Code: 0x71
9474 20:15:23.454263 ADC[6]: Raw value=74667 ID=0
9475 20:15:23.457575 ADC[5]: Raw value=212912 ID=1
9476 20:15:23.458007 SKU Code: 0x1
9477 20:15:23.464202 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5d53
9478 20:15:23.464667 coreboot table: 964 bytes.
9479 20:15:23.467307 IMD ROOT 0. 0xfffff000 0x00001000
9480 20:15:23.470581 IMD SMALL 1. 0xffffe000 0x00001000
9481 20:15:23.474390 RO MCACHE 2. 0xffffc000 0x00001104
9482 20:15:23.477042 CONSOLE 3. 0xfff7c000 0x00080000
9483 20:15:23.480856 FMAP 4. 0xfff7b000 0x00000452
9484 20:15:23.483903 TIME STAMP 5. 0xfff7a000 0x00000910
9485 20:15:23.486936 VBOOT WORK 6. 0xfff66000 0x00014000
9486 20:15:23.490745 RAMOOPS 7. 0xffe66000 0x00100000
9487 20:15:23.493681 COREBOOT 8. 0xffe64000 0x00002000
9488 20:15:23.496742 IMD small region:
9489 20:15:23.499969 IMD ROOT 0. 0xffffec00 0x00000400
9490 20:15:23.503631 VPD 1. 0xffffeb80 0x0000006c
9491 20:15:23.507266 MMC STATUS 2. 0xffffeb60 0x00000004
9492 20:15:23.513225 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9493 20:15:23.513822 Probing TPM: done!
9494 20:15:23.520540 Connected to device vid:did:rid of 1ae0:0028:00
9495 20:15:23.527359 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9496 20:15:23.530204 Initialized TPM device CR50 revision 0
9497 20:15:23.534248 Checking cr50 for pending updates
9498 20:15:23.538960 Reading cr50 TPM mode
9499 20:15:23.547507 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9500 20:15:23.554047 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9501 20:15:23.594089 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9502 20:15:23.597488 Checking segment from ROM address 0x40100000
9503 20:15:23.604264 Checking segment from ROM address 0x4010001c
9504 20:15:23.607306 Loading segment from ROM address 0x40100000
9505 20:15:23.607768 code (compression=0)
9506 20:15:23.617127 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9507 20:15:23.623950 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9508 20:15:23.624462 it's not compressed!
9509 20:15:23.630972 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9510 20:15:23.637150 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9511 20:15:23.654421 Loading segment from ROM address 0x4010001c
9512 20:15:23.655022 Entry Point 0x80000000
9513 20:15:23.658051 Loaded segments
9514 20:15:23.661935 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9515 20:15:23.668387 Jumping to boot code at 0x80000000(0xffe64000)
9516 20:15:23.674486 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9517 20:15:23.681635 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9518 20:15:23.689386 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9519 20:15:23.692497 Checking segment from ROM address 0x40100000
9520 20:15:23.695739 Checking segment from ROM address 0x4010001c
9521 20:15:23.702600 Loading segment from ROM address 0x40100000
9522 20:15:23.703241 code (compression=1)
9523 20:15:23.709089 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9524 20:15:23.718982 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9525 20:15:23.719414 using LZMA
9526 20:15:23.727842 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9527 20:15:23.733643 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9528 20:15:23.737446 Loading segment from ROM address 0x4010001c
9529 20:15:23.740355 Entry Point 0x54601000
9530 20:15:23.740784 Loaded segments
9531 20:15:23.743500 NOTICE: MT8192 bl31_setup
9532 20:15:23.751256 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9533 20:15:23.754245 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9534 20:15:23.757891 WARNING: region 0:
9535 20:15:23.761280 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 20:15:23.761712 WARNING: region 1:
9537 20:15:23.767471 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9538 20:15:23.771388 WARNING: region 2:
9539 20:15:23.774161 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9540 20:15:23.777548 WARNING: region 3:
9541 20:15:23.780479 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 20:15:23.784127 WARNING: region 4:
9543 20:15:23.790611 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 20:15:23.791175 WARNING: region 5:
9545 20:15:23.794370 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 20:15:23.797312 WARNING: region 6:
9547 20:15:23.800760 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 20:15:23.803922 WARNING: region 7:
9549 20:15:23.807509 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 20:15:23.814716 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9551 20:15:23.817214 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9552 20:15:23.824212 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9553 20:15:23.827128 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9554 20:15:23.830510 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9555 20:15:23.836868 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9556 20:15:23.840601 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9557 20:15:23.843584 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9558 20:15:23.850703 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9559 20:15:23.853380 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9560 20:15:23.860211 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9561 20:15:23.863417 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9562 20:15:23.866806 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9563 20:15:23.873924 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9564 20:15:23.877316 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9565 20:15:23.879662 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9566 20:15:23.886720 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9567 20:15:23.890257 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9568 20:15:23.896195 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9569 20:15:23.899763 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9570 20:15:23.903121 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9571 20:15:23.909347 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9572 20:15:23.913005 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9573 20:15:23.919316 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9574 20:15:23.922739 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9575 20:15:23.925880 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9576 20:15:23.932180 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9577 20:15:23.935931 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9578 20:15:23.942521 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9579 20:15:23.945627 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9580 20:15:23.949293 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9581 20:15:23.955987 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9582 20:15:23.959053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9583 20:15:23.962170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9584 20:15:23.968917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9585 20:15:23.972111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9586 20:15:23.977297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9587 20:15:23.978717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9588 20:15:23.985780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9589 20:15:23.989234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9590 20:15:23.992220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9591 20:15:23.995479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9592 20:15:24.001747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9593 20:15:24.005123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9594 20:15:24.008706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9595 20:15:24.012165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9596 20:15:24.018891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9597 20:15:24.022077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9598 20:15:24.024785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9599 20:15:24.031506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9600 20:15:24.034857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9601 20:15:24.041289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9602 20:15:24.044846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9603 20:15:24.051311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9604 20:15:24.054740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9605 20:15:24.061256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9606 20:15:24.064338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9607 20:15:24.068109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9608 20:15:24.074285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9609 20:15:24.077453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9610 20:15:24.084385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9611 20:15:24.087453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9612 20:15:24.094489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9613 20:15:24.097119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9614 20:15:24.103981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9615 20:15:24.107578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9616 20:15:24.110830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9617 20:15:24.117323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9618 20:15:24.120665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9619 20:15:24.127157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9620 20:15:24.130889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9621 20:15:24.136662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9622 20:15:24.140345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9623 20:15:24.147094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9624 20:15:24.151151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9625 20:15:24.153732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9626 20:15:24.159784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9627 20:15:24.163850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9628 20:15:24.169659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9629 20:15:24.172946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9630 20:15:24.179429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9631 20:15:24.182683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9632 20:15:24.189445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9633 20:15:24.192698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9634 20:15:24.199597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9635 20:15:24.202607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9636 20:15:24.206158 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9637 20:15:24.212486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9638 20:15:24.216298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9639 20:15:24.223028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9640 20:15:24.226258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9641 20:15:24.232888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9642 20:15:24.235657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9643 20:15:24.242321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9644 20:15:24.245769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9645 20:15:24.249358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9646 20:15:24.256032 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9647 20:15:24.259413 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9648 20:15:24.262267 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9649 20:15:24.265907 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9650 20:15:24.272203 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9651 20:15:24.276123 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9652 20:15:24.282150 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9653 20:15:24.285526 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9654 20:15:24.289182 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9655 20:15:24.295355 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9656 20:15:24.298719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9657 20:15:24.305477 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9658 20:15:24.308652 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9659 20:15:24.312500 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9660 20:15:24.318392 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9661 20:15:24.321695 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9662 20:15:24.328345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9663 20:15:24.332072 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9664 20:15:24.335479 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9665 20:15:24.341808 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9666 20:15:24.345434 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9667 20:15:24.348163 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9668 20:15:24.355015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9669 20:15:24.358728 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9670 20:15:24.362046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9671 20:15:24.364793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9672 20:15:24.371622 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9673 20:15:24.374738 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9674 20:15:24.377998 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9675 20:15:24.385069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9676 20:15:24.388411 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9677 20:15:24.394967 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9678 20:15:24.398016 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9679 20:15:24.401418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9680 20:15:24.408223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9681 20:15:24.411555 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9682 20:15:24.418074 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9683 20:15:24.421622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9684 20:15:24.424491 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9685 20:15:24.431840 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9686 20:15:24.434421 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9687 20:15:24.437938 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9688 20:15:24.444813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9689 20:15:24.447526 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9690 20:15:24.454440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9691 20:15:24.458197 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9692 20:15:24.464466 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9693 20:15:24.467435 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9694 20:15:24.470986 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9695 20:15:24.477536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9696 20:15:24.481055 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9697 20:15:24.483955 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9698 20:15:24.491097 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9699 20:15:24.494314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9700 20:15:24.500512 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9701 20:15:24.503827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9702 20:15:24.507609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9703 20:15:24.513798 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9704 20:15:24.516710 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9705 20:15:24.524061 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9706 20:15:24.527413 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9707 20:15:24.533767 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9708 20:15:24.536787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9709 20:15:24.539944 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9710 20:15:24.546769 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9711 20:15:24.550287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9712 20:15:24.556293 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9713 20:15:24.559644 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9714 20:15:24.563445 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9715 20:15:24.570177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9716 20:15:24.572803 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9717 20:15:24.579582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9718 20:15:24.583078 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9719 20:15:24.585984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9720 20:15:24.592489 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9721 20:15:24.596141 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9722 20:15:24.602473 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9723 20:15:24.605740 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9724 20:15:24.609082 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9725 20:15:24.615690 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9726 20:15:24.618998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9727 20:15:24.625619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9728 20:15:24.629505 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9729 20:15:24.632259 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9730 20:15:24.639261 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9731 20:15:24.642188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9732 20:15:24.648950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9733 20:15:24.651728 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9734 20:15:24.655280 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9735 20:15:24.662137 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9736 20:15:24.665110 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9737 20:15:24.671440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9738 20:15:24.675066 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9739 20:15:24.678286 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9740 20:15:24.685479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9741 20:15:24.688124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9742 20:15:24.695035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9743 20:15:24.698150 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9744 20:15:24.704348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9745 20:15:24.707665 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9746 20:15:24.711366 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9747 20:15:24.718400 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9748 20:15:24.720841 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9749 20:15:24.728059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9750 20:15:24.730894 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9751 20:15:24.738095 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9752 20:15:24.740722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9753 20:15:24.747621 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9754 20:15:24.750726 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9755 20:15:24.753904 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9756 20:15:24.760126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9757 20:15:24.763966 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9758 20:15:24.770142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9759 20:15:24.773395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9760 20:15:24.780569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9761 20:15:24.783987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9762 20:15:24.786568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9763 20:15:24.793162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9764 20:15:24.796595 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9765 20:15:24.803908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9766 20:15:24.806412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9767 20:15:24.812937 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9768 20:15:24.816721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9769 20:15:24.819564 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9770 20:15:24.826713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9771 20:15:24.830079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9772 20:15:24.836196 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9773 20:15:24.839524 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9774 20:15:24.846344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9775 20:15:24.849139 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9776 20:15:24.852654 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9777 20:15:24.859778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9778 20:15:24.862744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9779 20:15:24.865926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9780 20:15:24.872385 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9781 20:15:24.875788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9782 20:15:24.879503 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9783 20:15:24.882382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9784 20:15:24.888812 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9785 20:15:24.892249 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9786 20:15:24.899296 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9787 20:15:24.902193 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9788 20:15:24.905805 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9789 20:15:24.912241 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9790 20:15:24.915399 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9791 20:15:24.919285 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9792 20:15:24.925653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9793 20:15:24.928981 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9794 20:15:24.935262 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9795 20:15:24.938425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9796 20:15:24.941969 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9797 20:15:24.948650 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9798 20:15:24.951544 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9799 20:15:24.954912 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9800 20:15:24.961248 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9801 20:15:24.965148 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9802 20:15:24.972284 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9803 20:15:24.974976 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9804 20:15:24.978046 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9805 20:15:24.985092 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9806 20:15:24.987880 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9807 20:15:24.994393 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9808 20:15:24.997895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9809 20:15:25.000804 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9810 20:15:25.007485 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9811 20:15:25.011584 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9812 20:15:25.014494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9813 20:15:25.021274 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9814 20:15:25.024132 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9815 20:15:25.027349 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9816 20:15:25.034291 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9817 20:15:25.037807 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9818 20:15:25.045172 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9819 20:15:25.047346 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9820 20:15:25.050552 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9821 20:15:25.053899 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9822 20:15:25.057177 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9823 20:15:25.063733 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9824 20:15:25.067578 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9825 20:15:25.070200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9826 20:15:25.073622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9827 20:15:25.080136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9828 20:15:25.083899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9829 20:15:25.086698 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9830 20:15:25.093415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9831 20:15:25.096796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9832 20:15:25.099734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9833 20:15:25.106671 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9834 20:15:25.110298 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9835 20:15:25.116955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9836 20:15:25.120129 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9837 20:15:25.123276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9838 20:15:25.129457 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9839 20:15:25.132776 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9840 20:15:25.139028 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9841 20:15:25.142754 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9842 20:15:25.149025 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9843 20:15:25.152828 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9844 20:15:25.156021 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9845 20:15:25.161819 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9846 20:15:25.165248 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9847 20:15:25.172381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9848 20:15:25.175657 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9849 20:15:25.179071 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9850 20:15:25.185498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9851 20:15:25.189440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9852 20:15:25.195728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9853 20:15:25.199030 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9854 20:15:25.206038 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9855 20:15:25.208802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9856 20:15:25.212274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9857 20:15:25.218544 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9858 20:15:25.222162 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9859 20:15:25.228592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9860 20:15:25.232307 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9861 20:15:25.238822 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9862 20:15:25.241635 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9863 20:15:25.244976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9864 20:15:25.251777 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9865 20:15:25.254945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9866 20:15:25.261538 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9867 20:15:25.264917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9868 20:15:25.268264 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9869 20:15:25.274599 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9870 20:15:25.277876 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9871 20:15:25.284346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9872 20:15:25.287786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9873 20:15:25.294214 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9874 20:15:25.297374 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9875 20:15:25.300799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9876 20:15:25.307554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9877 20:15:25.311035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9878 20:15:25.317674 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9879 20:15:25.320214 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9880 20:15:25.324016 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9881 20:15:25.330402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9882 20:15:25.333544 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9883 20:15:25.339817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9884 20:15:25.343394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9885 20:15:25.349732 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9886 20:15:25.353041 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9887 20:15:25.356199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9888 20:15:25.363252 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9889 20:15:25.366786 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9890 20:15:25.372690 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9891 20:15:25.376023 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9892 20:15:25.382782 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9893 20:15:25.386150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9894 20:15:25.389432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9895 20:15:25.396145 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9896 20:15:25.400285 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9897 20:15:25.406095 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9898 20:15:25.409421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9899 20:15:25.412677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9900 20:15:25.419944 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9901 20:15:25.422838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9902 20:15:25.429956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9903 20:15:25.433083 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9904 20:15:25.438780 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9905 20:15:25.442281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9906 20:15:25.445944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9907 20:15:25.452326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9908 20:15:25.455899 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9909 20:15:25.462241 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9910 20:15:25.466016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9911 20:15:25.472510 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9912 20:15:25.475355 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9913 20:15:25.482036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9914 20:15:25.485286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9915 20:15:25.489076 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9916 20:15:25.494834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9917 20:15:25.498525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9918 20:15:25.505177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9919 20:15:25.508746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9920 20:15:25.515607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9921 20:15:25.518400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9922 20:15:25.525068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9923 20:15:25.528147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9924 20:15:25.534724 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9925 20:15:25.537977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9926 20:15:25.541326 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9927 20:15:25.547917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9928 20:15:25.550898 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9929 20:15:25.557806 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9930 20:15:25.560950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9931 20:15:25.567581 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9932 20:15:25.571134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9933 20:15:25.577266 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9934 20:15:25.580581 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9935 20:15:25.584242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9936 20:15:25.590973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9937 20:15:25.593475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9938 20:15:25.600348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9939 20:15:25.603648 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9940 20:15:25.610239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9941 20:15:25.613470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9942 20:15:25.620020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9943 20:15:25.623122 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9944 20:15:25.626982 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9945 20:15:25.633297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9946 20:15:25.636254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9947 20:15:25.643178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9948 20:15:25.646610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9949 20:15:25.652897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9950 20:15:25.656492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9951 20:15:25.662831 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9952 20:15:25.665722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9953 20:15:25.669375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9954 20:15:25.675606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9955 20:15:25.679634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9956 20:15:25.685522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9957 20:15:25.689400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9958 20:15:25.695302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9959 20:15:25.698692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9960 20:15:25.705474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9961 20:15:25.709309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9962 20:15:25.714767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9963 20:15:25.718336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9964 20:15:25.724611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9965 20:15:25.728208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9966 20:15:25.735471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9967 20:15:25.737888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9968 20:15:25.744991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9969 20:15:25.748274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9970 20:15:25.754382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9971 20:15:25.757903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9972 20:15:25.764651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9973 20:15:25.768030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9974 20:15:25.775007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9975 20:15:25.778421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9976 20:15:25.784651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9977 20:15:25.787528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9978 20:15:25.794441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9979 20:15:25.797526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9980 20:15:25.804006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9981 20:15:25.807397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9982 20:15:25.813597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9983 20:15:25.820711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9984 20:15:25.823639 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9985 20:15:25.824210 INFO: [APUAPC] vio 0
9986 20:15:25.830930 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9987 20:15:25.834897 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9988 20:15:25.837252 INFO: [APUAPC] D0_APC_0: 0x400510
9989 20:15:25.841264 INFO: [APUAPC] D0_APC_1: 0x0
9990 20:15:25.844263 INFO: [APUAPC] D0_APC_2: 0x1540
9991 20:15:25.847156 INFO: [APUAPC] D0_APC_3: 0x0
9992 20:15:25.851230 INFO: [APUAPC] D1_APC_0: 0xffffffff
9993 20:15:25.854233 INFO: [APUAPC] D1_APC_1: 0xffffffff
9994 20:15:25.857854 INFO: [APUAPC] D1_APC_2: 0x3fffff
9995 20:15:25.860390 INFO: [APUAPC] D1_APC_3: 0x0
9996 20:15:25.863965 INFO: [APUAPC] D2_APC_0: 0xffffffff
9997 20:15:25.867921 INFO: [APUAPC] D2_APC_1: 0xffffffff
9998 20:15:25.870670 INFO: [APUAPC] D2_APC_2: 0x3fffff
9999 20:15:25.873739 INFO: [APUAPC] D2_APC_3: 0x0
10000 20:15:25.876873 INFO: [APUAPC] D3_APC_0: 0xffffffff
10001 20:15:25.880371 INFO: [APUAPC] D3_APC_1: 0xffffffff
10002 20:15:25.883533 INFO: [APUAPC] D3_APC_2: 0x3fffff
10003 20:15:25.886661 INFO: [APUAPC] D3_APC_3: 0x0
10004 20:15:25.889872 INFO: [APUAPC] D4_APC_0: 0xffffffff
10005 20:15:25.893396 INFO: [APUAPC] D4_APC_1: 0xffffffff
10006 20:15:25.896754 INFO: [APUAPC] D4_APC_2: 0x3fffff
10007 20:15:25.900017 INFO: [APUAPC] D4_APC_3: 0x0
10008 20:15:25.903503 INFO: [APUAPC] D5_APC_0: 0xffffffff
10009 20:15:25.907235 INFO: [APUAPC] D5_APC_1: 0xffffffff
10010 20:15:25.910079 INFO: [APUAPC] D5_APC_2: 0x3fffff
10011 20:15:25.913227 INFO: [APUAPC] D5_APC_3: 0x0
10012 20:15:25.916263 INFO: [APUAPC] D6_APC_0: 0xffffffff
10013 20:15:25.920472 INFO: [APUAPC] D6_APC_1: 0xffffffff
10014 20:15:25.923283 INFO: [APUAPC] D6_APC_2: 0x3fffff
10015 20:15:25.926310 INFO: [APUAPC] D6_APC_3: 0x0
10016 20:15:25.930022 INFO: [APUAPC] D7_APC_0: 0xffffffff
10017 20:15:25.933202 INFO: [APUAPC] D7_APC_1: 0xffffffff
10018 20:15:25.936252 INFO: [APUAPC] D7_APC_2: 0x3fffff
10019 20:15:25.936760 INFO: [APUAPC] D7_APC_3: 0x0
10020 20:15:25.942921 INFO: [APUAPC] D8_APC_0: 0xffffffff
10021 20:15:25.946331 INFO: [APUAPC] D8_APC_1: 0xffffffff
10022 20:15:25.949637 INFO: [APUAPC] D8_APC_2: 0x3fffff
10023 20:15:25.950110 INFO: [APUAPC] D8_APC_3: 0x0
10024 20:15:25.953081 INFO: [APUAPC] D9_APC_0: 0xffffffff
10025 20:15:25.959495 INFO: [APUAPC] D9_APC_1: 0xffffffff
10026 20:15:25.962587 INFO: [APUAPC] D9_APC_2: 0x3fffff
10027 20:15:25.963060 INFO: [APUAPC] D9_APC_3: 0x0
10028 20:15:25.966025 INFO: [APUAPC] D10_APC_0: 0xffffffff
10029 20:15:25.969419 INFO: [APUAPC] D10_APC_1: 0xffffffff
10030 20:15:25.976313 INFO: [APUAPC] D10_APC_2: 0x3fffff
10031 20:15:25.976977 INFO: [APUAPC] D10_APC_3: 0x0
10032 20:15:25.982566 INFO: [APUAPC] D11_APC_0: 0xffffffff
10033 20:15:25.985652 INFO: [APUAPC] D11_APC_1: 0xffffffff
10034 20:15:25.988676 INFO: [APUAPC] D11_APC_2: 0x3fffff
10035 20:15:25.989276 INFO: [APUAPC] D11_APC_3: 0x0
10036 20:15:25.995612 INFO: [APUAPC] D12_APC_0: 0xffffffff
10037 20:15:25.998797 INFO: [APUAPC] D12_APC_1: 0xffffffff
10038 20:15:26.002466 INFO: [APUAPC] D12_APC_2: 0x3fffff
10039 20:15:26.005376 INFO: [APUAPC] D12_APC_3: 0x0
10040 20:15:26.008733 INFO: [APUAPC] D13_APC_0: 0xffffffff
10041 20:15:26.012332 INFO: [APUAPC] D13_APC_1: 0xffffffff
10042 20:15:26.015236 INFO: [APUAPC] D13_APC_2: 0x3fffff
10043 20:15:26.018783 INFO: [APUAPC] D13_APC_3: 0x0
10044 20:15:26.021972 INFO: [APUAPC] D14_APC_0: 0xffffffff
10045 20:15:26.025291 INFO: [APUAPC] D14_APC_1: 0xffffffff
10046 20:15:26.028633 INFO: [APUAPC] D14_APC_2: 0x3fffff
10047 20:15:26.031749 INFO: [APUAPC] D14_APC_3: 0x0
10048 20:15:26.034845 INFO: [APUAPC] D15_APC_0: 0xffffffff
10049 20:15:26.038028 INFO: [APUAPC] D15_APC_1: 0xffffffff
10050 20:15:26.041259 INFO: [APUAPC] D15_APC_2: 0x3fffff
10051 20:15:26.044748 INFO: [APUAPC] D15_APC_3: 0x0
10052 20:15:26.048311 INFO: [APUAPC] APC_CON: 0x4
10053 20:15:26.048731 INFO: [NOCDAPC] D0_APC_0: 0x0
10054 20:15:26.051847 INFO: [NOCDAPC] D0_APC_1: 0x0
10055 20:15:26.054493 INFO: [NOCDAPC] D1_APC_0: 0x0
10056 20:15:26.058101 INFO: [NOCDAPC] D1_APC_1: 0xfff
10057 20:15:26.060962 INFO: [NOCDAPC] D2_APC_0: 0x0
10058 20:15:26.065042 INFO: [NOCDAPC] D2_APC_1: 0xfff
10059 20:15:26.068403 INFO: [NOCDAPC] D3_APC_0: 0x0
10060 20:15:26.070965 INFO: [NOCDAPC] D3_APC_1: 0xfff
10061 20:15:26.074805 INFO: [NOCDAPC] D4_APC_0: 0x0
10062 20:15:26.077322 INFO: [NOCDAPC] D4_APC_1: 0xfff
10063 20:15:26.081373 INFO: [NOCDAPC] D5_APC_0: 0x0
10064 20:15:26.084983 INFO: [NOCDAPC] D5_APC_1: 0xfff
10065 20:15:26.085402 INFO: [NOCDAPC] D6_APC_0: 0x0
10066 20:15:26.087604 INFO: [NOCDAPC] D6_APC_1: 0xfff
10067 20:15:26.091620 INFO: [NOCDAPC] D7_APC_0: 0x0
10068 20:15:26.094146 INFO: [NOCDAPC] D7_APC_1: 0xfff
10069 20:15:26.097262 INFO: [NOCDAPC] D8_APC_0: 0x0
10070 20:15:26.100918 INFO: [NOCDAPC] D8_APC_1: 0xfff
10071 20:15:26.104187 INFO: [NOCDAPC] D9_APC_0: 0x0
10072 20:15:26.107048 INFO: [NOCDAPC] D9_APC_1: 0xfff
10073 20:15:26.111373 INFO: [NOCDAPC] D10_APC_0: 0x0
10074 20:15:26.114196 INFO: [NOCDAPC] D10_APC_1: 0xfff
10075 20:15:26.117187 INFO: [NOCDAPC] D11_APC_0: 0x0
10076 20:15:26.120853 INFO: [NOCDAPC] D11_APC_1: 0xfff
10077 20:15:26.123636 INFO: [NOCDAPC] D12_APC_0: 0x0
10078 20:15:26.128081 INFO: [NOCDAPC] D12_APC_1: 0xfff
10079 20:15:26.128662 INFO: [NOCDAPC] D13_APC_0: 0x0
10080 20:15:26.130377 INFO: [NOCDAPC] D13_APC_1: 0xfff
10081 20:15:26.133394 INFO: [NOCDAPC] D14_APC_0: 0x0
10082 20:15:26.136988 INFO: [NOCDAPC] D14_APC_1: 0xfff
10083 20:15:26.140786 INFO: [NOCDAPC] D15_APC_0: 0x0
10084 20:15:26.143486 INFO: [NOCDAPC] D15_APC_1: 0xfff
10085 20:15:26.146852 INFO: [NOCDAPC] APC_CON: 0x4
10086 20:15:26.150055 INFO: [APUAPC] set_apusys_apc done
10087 20:15:26.153627 INFO: [DEVAPC] devapc_init done
10088 20:15:26.156732 INFO: GICv3 without legacy support detected.
10089 20:15:26.160396 INFO: ARM GICv3 driver initialized in EL3
10090 20:15:26.166866 INFO: Maximum SPI INTID supported: 639
10091 20:15:26.169844 INFO: BL31: Initializing runtime services
10092 20:15:26.176044 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10093 20:15:26.176464 INFO: SPM: enable CPC mode
10094 20:15:26.183180 INFO: mcdi ready for mcusys-off-idle and system suspend
10095 20:15:26.186127 INFO: BL31: Preparing for EL3 exit to normal world
10096 20:15:26.192965 INFO: Entry point address = 0x80000000
10097 20:15:26.193383 INFO: SPSR = 0x8
10098 20:15:26.198984
10099 20:15:26.199399
10100 20:15:26.199812
10101 20:15:26.201906 Starting depthcharge on Spherion...
10102 20:15:26.202779
10103 20:15:26.203288 Wipe memory regions:
10104 20:15:26.203946
10105 20:15:26.206935 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10106 20:15:26.207603 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10107 20:15:26.208172 Setting prompt string to ['asurada:']
10108 20:15:26.208675 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10109 20:15:26.209517 [0x00000040000000, 0x00000054600000)
10110 20:15:26.327638
10111 20:15:26.327819 [0x00000054660000, 0x00000080000000)
10112 20:15:26.587733
10113 20:15:26.587935 [0x000000821a7280, 0x000000ffe64000)
10114 20:15:27.333151
10115 20:15:27.333759 [0x00000100000000, 0x00000240000000)
10116 20:15:29.222271
10117 20:15:29.226055 Initializing XHCI USB controller at 0x11200000.
10118 20:15:30.264441
10119 20:15:30.267660 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10120 20:15:30.268152
10121 20:15:30.268652
10122 20:15:30.269111
10123 20:15:30.270054 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 20:15:30.371721 asurada: tftpboot 192.168.201.1 12928152/tftp-deploy-w1fw5qu9/kernel/image.itb 12928152/tftp-deploy-w1fw5qu9/kernel/cmdline
10126 20:15:30.372314 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 20:15:30.372749 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10128 20:15:30.377257 tftpboot 192.168.201.1 12928152/tftp-deploy-w1fw5qu9/kernel/image.itp-deploy-w1fw5qu9/kernel/cmdline
10129 20:15:30.377497
10130 20:15:30.377735 Waiting for link
10131 20:15:30.537989
10132 20:15:30.538118 R8152: Initializing
10133 20:15:30.538213
10134 20:15:30.541178 Version 6 (ocp_data = 5c30)
10135 20:15:30.541258
10136 20:15:30.544386 R8152: Done initializing
10137 20:15:30.544462
10138 20:15:30.544545 Adding net device
10139 20:15:32.391368
10140 20:15:32.391778 done.
10141 20:15:32.392105
10142 20:15:32.392447 MAC: 00:e0:4c:68:02:81
10143 20:15:32.392805
10144 20:15:32.393909 Sending DHCP discover... done.
10145 20:15:32.394145
10146 20:15:32.397488 Waiting for reply... done.
10147 20:15:32.397870
10148 20:15:32.400679 Sending DHCP request... done.
10149 20:15:32.401055
10150 20:15:32.405939 Waiting for reply... done.
10151 20:15:32.406311
10152 20:15:32.406661 My ip is 192.168.201.14
10153 20:15:32.406971
10154 20:15:32.409452 The DHCP server ip is 192.168.201.1
10155 20:15:32.409812
10156 20:15:32.415656 TFTP server IP predefined by user: 192.168.201.1
10157 20:15:32.416047
10158 20:15:32.422683 Bootfile predefined by user: 12928152/tftp-deploy-w1fw5qu9/kernel/image.itb
10159 20:15:32.422984
10160 20:15:32.425860 Sending tftp read request... done.
10161 20:15:32.426161
10162 20:15:32.431804 Waiting for the transfer...
10163 20:15:32.432210
10164 20:15:33.116904 00000000 ################################################################
10165 20:15:33.117420
10166 20:15:33.840151 00080000 ################################################################
10167 20:15:33.840711
10168 20:15:34.536259 00100000 ################################################################
10169 20:15:34.536905
10170 20:15:35.251752 00180000 ################################################################
10171 20:15:35.252291
10172 20:15:35.969761 00200000 ################################################################
10173 20:15:35.970377
10174 20:15:36.701350 00280000 ################################################################
10175 20:15:36.701936
10176 20:15:37.431748 00300000 ################################################################
10177 20:15:37.432292
10178 20:15:38.163559 00380000 ################################################################
10179 20:15:38.164208
10180 20:15:38.894668 00400000 ################################################################
10181 20:15:38.895242
10182 20:15:39.602728 00480000 ################################################################
10183 20:15:39.602868
10184 20:15:40.290829 00500000 ################################################################
10185 20:15:40.291376
10186 20:15:40.973141 00580000 ################################################################
10187 20:15:40.973294
10188 20:15:41.563987 00600000 ################################################################
10189 20:15:41.564163
10190 20:15:42.244479 00680000 ################################################################
10191 20:15:42.245004
10192 20:15:42.966977 00700000 ################################################################
10193 20:15:42.967553
10194 20:15:43.691914 00780000 ################################################################
10195 20:15:43.692502
10196 20:15:44.409903 00800000 ################################################################
10197 20:15:44.410526
10198 20:15:45.133716 00880000 ################################################################
10199 20:15:45.134255
10200 20:15:45.843035 00900000 ################################################################
10201 20:15:45.843582
10202 20:15:46.551427 00980000 ################################################################
10203 20:15:46.552037
10204 20:15:47.284917 00a00000 ################################################################
10205 20:15:47.285454
10206 20:15:48.011608 00a80000 ################################################################
10207 20:15:48.012198
10208 20:15:48.736670 00b00000 ################################################################
10209 20:15:48.737200
10210 20:15:49.464337 00b80000 ################################################################
10211 20:15:49.464900
10212 20:15:50.187661 00c00000 ################################################################
10213 20:15:50.188275
10214 20:15:50.927718 00c80000 ################################################################
10215 20:15:50.928238
10216 20:15:51.656896 00d00000 ################################################################
10217 20:15:51.657455
10218 20:15:52.385042 00d80000 ################################################################
10219 20:15:52.385604
10220 20:15:53.113567 00e00000 ################################################################
10221 20:15:53.114106
10222 20:15:53.842989 00e80000 ################################################################
10223 20:15:53.843506
10224 20:15:54.560506 00f00000 ################################################################
10225 20:15:54.561021
10226 20:15:55.290439 00f80000 ################################################################
10227 20:15:55.290948
10228 20:15:56.007305 01000000 ################################################################
10229 20:15:56.007874
10230 20:15:56.734181 01080000 ################################################################
10231 20:15:56.734709
10232 20:15:57.456669 01100000 ################################################################
10233 20:15:57.457189
10234 20:15:58.188834 01180000 ################################################################
10235 20:15:58.189403
10236 20:15:58.902542 01200000 ################################################################
10237 20:15:58.903068
10238 20:15:59.614744 01280000 ################################################################
10239 20:15:59.615286
10240 20:16:00.331361 01300000 ################################################################
10241 20:16:00.331912
10242 20:16:01.036973 01380000 ################################################################
10243 20:16:01.037549
10244 20:16:01.743779 01400000 ################################################################
10245 20:16:01.744331
10246 20:16:02.454904 01480000 ################################################################
10247 20:16:02.455532
10248 20:16:03.172770 01500000 ################################################################
10249 20:16:03.173291
10250 20:16:03.866680 01580000 ################################################################
10251 20:16:03.867422
10252 20:16:04.590732 01600000 ################################################################
10253 20:16:04.591299
10254 20:16:05.295869 01680000 ################################################################
10255 20:16:05.296409
10256 20:16:06.013587 01700000 ################################################################
10257 20:16:06.014147
10258 20:16:06.677822 01780000 ################################################################
10259 20:16:06.678038
10260 20:16:07.393819 01800000 ################################################################
10261 20:16:07.394390
10262 20:16:08.040304 01880000 ################################################################
10263 20:16:08.040443
10264 20:16:08.607571 01900000 ################################################################
10265 20:16:08.607763
10266 20:16:09.196026 01980000 ################################################################
10267 20:16:09.196557
10268 20:16:09.874171 01a00000 ################################################################
10269 20:16:09.874308
10270 20:16:10.449753 01a80000 ################################################################
10271 20:16:10.449904
10272 20:16:11.025462 01b00000 ################################################################
10273 20:16:11.025612
10274 20:16:11.610889 01b80000 ################################################################
10275 20:16:11.611042
10276 20:16:12.199875 01c00000 ################################################################
10277 20:16:12.200026
10278 20:16:12.235833 01c80000 ##### done.
10279 20:16:12.235973
10280 20:16:12.238422 The bootfile was 29917934 bytes long.
10281 20:16:12.238558
10282 20:16:12.242271 Sending tftp read request... done.
10283 20:16:12.242354
10284 20:16:12.245107 Waiting for the transfer...
10285 20:16:12.245188
10286 20:16:12.245253 00000000 # done.
10287 20:16:12.245315
10288 20:16:12.255143 Command line loaded dynamically from TFTP file: 12928152/tftp-deploy-w1fw5qu9/kernel/cmdline
10289 20:16:12.255227
10290 20:16:12.274809 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10291 20:16:12.274910
10292 20:16:12.279059 Loading FIT.
10293 20:16:12.279141
10294 20:16:12.281418 Image ramdisk-1 has 17808582 bytes.
10295 20:16:12.281500
10296 20:16:12.281566 Image fdt-1 has 47278 bytes.
10297 20:16:12.281626
10298 20:16:12.284524 Image kernel-1 has 12060038 bytes.
10299 20:16:12.284606
10300 20:16:12.294393 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10301 20:16:12.294478
10302 20:16:12.311157 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10303 20:16:12.311259
10304 20:16:12.317747 Choosing best match conf-1 for compat google,spherion-rev2.
10305 20:16:12.321609
10306 20:16:12.355880 Connected to device vid:did:rid of 1ae0:0028:00
10307 20:16:12.371572
10308 20:16:12.375038 tpm_get_response: command 0x17b, return code 0x0
10309 20:16:12.375122
10310 20:16:12.377695 ec_init: CrosEC protocol v3 supported (256, 248)
10311 20:16:12.382439
10312 20:16:12.385413 tpm_cleanup: add release locality here.
10313 20:16:12.385495
10314 20:16:12.385561 Shutting down all USB controllers.
10315 20:16:12.388641
10316 20:16:12.388723 Removing current net device
10317 20:16:12.388788
10318 20:16:12.395128 Exiting depthcharge with code 4 at timestamp: 75626670
10319 20:16:12.395212
10320 20:16:12.399088 LZMA decompressing kernel-1 to 0x821a6718
10321 20:16:12.399171
10322 20:16:12.402484 LZMA decompressing kernel-1 to 0x40000000
10323 20:16:13.901195
10324 20:16:13.901354 jumping to kernel
10325 20:16:13.901808 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10326 20:16:13.901906 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10327 20:16:13.901985 Setting prompt string to ['Linux version [0-9]']
10328 20:16:13.902057 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10329 20:16:13.902126 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10330 20:16:13.983841
10331 20:16:13.987406 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10332 20:16:13.990822 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10333 20:16:13.990919 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10334 20:16:13.990992 Setting prompt string to []
10335 20:16:13.991070 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10336 20:16:13.991146 Using line separator: #'\n'#
10337 20:16:13.991207 No login prompt set.
10338 20:16:13.991268 Parsing kernel messages
10339 20:16:13.991324 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10340 20:16:13.991426 [login-action] Waiting for messages, (timeout 00:03:37)
10341 20:16:13.991490 Waiting using forced prompt support (timeout 00:01:49)
10342 20:16:14.010333 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10343 20:16:14.013800 [ 0.000000] random: crng init done
10344 20:16:14.020233 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10345 20:16:14.023584 [ 0.000000] efi: UEFI not found.
10346 20:16:14.030081 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10347 20:16:14.040813 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10348 20:16:14.049886 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10349 20:16:14.056854 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10350 20:16:14.063220 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10351 20:16:14.069659 [ 0.000000] printk: bootconsole [mtk8250] enabled
10352 20:16:14.076326 [ 0.000000] NUMA: No NUMA configuration found
10353 20:16:14.082647 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10354 20:16:14.090090 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10355 20:16:14.090174 [ 0.000000] Zone ranges:
10356 20:16:14.095896 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10357 20:16:14.099373 [ 0.000000] DMA32 empty
10358 20:16:14.105863 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10359 20:16:14.109492 [ 0.000000] Movable zone start for each node
10360 20:16:14.112400 [ 0.000000] Early memory node ranges
10361 20:16:14.119496 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10362 20:16:14.125810 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10363 20:16:14.133093 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10364 20:16:14.139341 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10365 20:16:14.145433 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10366 20:16:14.152818 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10367 20:16:14.209046 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10368 20:16:14.214999 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10369 20:16:14.222068 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10370 20:16:14.225156 [ 0.000000] psci: probing for conduit method from DT.
10371 20:16:14.232164 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10372 20:16:14.235188 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10373 20:16:14.241582 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10374 20:16:14.245117 [ 0.000000] psci: SMC Calling Convention v1.2
10375 20:16:14.252509 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10376 20:16:14.254952 [ 0.000000] Detected VIPT I-cache on CPU0
10377 20:16:14.261647 [ 0.000000] CPU features: detected: GIC system register CPU interface
10378 20:16:14.268075 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10379 20:16:14.274340 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10380 20:16:14.281813 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10381 20:16:14.291331 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10382 20:16:14.297757 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10383 20:16:14.301051 [ 0.000000] alternatives: applying boot alternatives
10384 20:16:14.307887 [ 0.000000] Fallback order for Node 0: 0
10385 20:16:14.314191 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10386 20:16:14.317229 [ 0.000000] Policy zone: Normal
10387 20:16:14.340522 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10388 20:16:14.350295 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10389 20:16:14.362025 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10390 20:16:14.371589 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10391 20:16:14.377451 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10392 20:16:14.381205 <6>[ 0.000000] software IO TLB: area num 8.
10393 20:16:14.438069 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10394 20:16:14.587535 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10395 20:16:14.593352 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10396 20:16:14.600357 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10397 20:16:14.603079 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10398 20:16:14.610380 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10399 20:16:14.616136 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10400 20:16:14.619830 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10401 20:16:14.630215 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10402 20:16:14.636765 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10403 20:16:14.642558 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10404 20:16:14.649491 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10405 20:16:14.652480 <6>[ 0.000000] GICv3: 608 SPIs implemented
10406 20:16:14.656011 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10407 20:16:14.662543 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10408 20:16:14.666078 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10409 20:16:14.672537 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10410 20:16:14.685547 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10411 20:16:14.698793 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10412 20:16:14.705608 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10413 20:16:14.713601 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10414 20:16:14.727188 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10415 20:16:14.733535 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10416 20:16:14.739858 <6>[ 0.009185] Console: colour dummy device 80x25
10417 20:16:14.750352 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10418 20:16:14.756557 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10419 20:16:14.759718 <6>[ 0.029225] LSM: Security Framework initializing
10420 20:16:14.767398 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 20:16:14.776384 <6>[ 0.041977] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 20:16:14.786012 <6>[ 0.051384] cblist_init_generic: Setting adjustable number of callback queues.
10423 20:16:14.789555 <6>[ 0.058874] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 20:16:14.799317 <6>[ 0.065213] cblist_init_generic: Setting adjustable number of callback queues.
10425 20:16:14.806389 <6>[ 0.072641] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 20:16:14.809193 <6>[ 0.079082] rcu: Hierarchical SRCU implementation.
10427 20:16:14.816357 <6>[ 0.079084] rcu: Max phase no-delay instances is 1000.
10428 20:16:14.823194 <6>[ 0.079108] printk: bootconsole [mtk8250] printing thread started
10429 20:16:14.829586 <6>[ 0.097431] EFI services will not be available.
10430 20:16:14.832521 <6>[ 0.097632] smp: Bringing up secondary CPUs ...
10431 20:16:14.838744 <6>[ 0.097945] Detected VIPT I-cache on CPU1
10432 20:16:14.845564 <6>[ 0.098011] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 20:16:14.852254 <6>[ 0.098044] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 20:16:14.861745 <6>[ 0.125874] Detected VIPT I-cache on CPU2
10435 20:16:14.868042 <6>[ 0.125922] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 20:16:14.878145 <6>[ 0.125938] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 20:16:14.881241 <6>[ 0.126197] Detected VIPT I-cache on CPU3
10438 20:16:14.888139 <6>[ 0.126243] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 20:16:14.895230 <6>[ 0.126256] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 20:16:14.897729 <6>[ 0.126571] CPU features: detected: Spectre-v4
10441 20:16:14.904727 <6>[ 0.126577] CPU features: detected: Spectre-BHB
10442 20:16:14.907701 <6>[ 0.126582] Detected PIPT I-cache on CPU4
10443 20:16:14.914172 <6>[ 0.126640] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 20:16:14.921029 <6>[ 0.126657] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 20:16:14.927977 <6>[ 0.126952] Detected PIPT I-cache on CPU5
10446 20:16:14.934900 <6>[ 0.127014] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 20:16:14.940998 <6>[ 0.127030] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 20:16:14.944162 <6>[ 0.127305] Detected PIPT I-cache on CPU6
10449 20:16:14.954173 <6>[ 0.127371] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 20:16:14.960762 <6>[ 0.127386] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 20:16:14.963827 <6>[ 0.127677] Detected PIPT I-cache on CPU7
10452 20:16:14.970360 <6>[ 0.127744] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 20:16:14.977446 <6>[ 0.127760] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 20:16:14.980975 <6>[ 0.127807] smp: Brought up 1 node, 8 CPUs
10455 20:16:14.987292 <6>[ 0.127812] SMP: Total of 8 processors activated.
10456 20:16:14.993365 <6>[ 0.127815] CPU features: detected: 32-bit EL0 Support
10457 20:16:14.999764 <6>[ 0.127817] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 20:16:15.006674 <6>[ 0.127819] CPU features: detected: Common not Private translations
10459 20:16:15.013438 <6>[ 0.127821] CPU features: detected: CRC32 instructions
10460 20:16:15.019572 <6>[ 0.127824] CPU features: detected: RCpc load-acquire (LDAPR)
10461 20:16:15.023485 <6>[ 0.127825] CPU features: detected: LSE atomic instructions
10462 20:16:15.030894 <6>[ 0.127827] CPU features: detected: Privileged Access Never
10463 20:16:15.036298 <6>[ 0.127829] CPU features: detected: RAS Extension Support
10464 20:16:15.043205 <6>[ 0.127832] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 20:16:15.046178 <6>[ 0.127900] CPU: All CPU(s) started at EL2
10466 20:16:15.052748 <6>[ 0.127902] alternatives: applying system-wide alternatives
10467 20:16:15.056167 <6>[ 0.141058] devtmpfs: initialized
10468 20:16:15.065774 <6>[ 0.147217] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 20:16:15.088450 ��egistered PF_INET protocol family
10470 20:16:15.095311 <6>[ 0.364251<] printk: console [ttyS0] printing thread started
10471 20:16:15.101844 6<6>[ 0.364280] printk: console [ttyS0] enabled
10472 20:16:15.108414 >[ 0.228829] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 20:16:15.116625 <6>[ 0.364284] printk: bootconsole [mtk8250] disabled
10474 20:16:15.122716 <6>[ 0.382368] printk: bootconsole [mtk8250] printing thread stopped
10475 20:16:15.126585 <6>[ 0.383678] SuperH (H)SCI(F) driver initialized
10476 20:16:15.132766 <6>[ 0.384179] msm_serial: driver initialized
10477 20:16:15.139827 <6>[ 0.388873] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10478 20:16:15.149163 <6>[ 0.388903] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10479 20:16:15.155962 <6>[ 0.388933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10480 20:16:15.166683 <6>[ 0.388965] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10481 20:16:15.177325 <6>[ 0.388988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10482 20:16:15.186526 <6>[ 0.389016] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10483 20:16:15.190382 <6>[ 0.389043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10484 20:16:15.206556 <6>[ 0.389151] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10485 20:16:15.215857 <6>[ 0.389181] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10486 20:16:15.215939 <6>[ 0.400569] loop: module loaded
10487 20:16:15.222801 <6>[ 0.403166] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10488 20:16:15.225594 <4>[ 0.420001] mtk-pmic-keys: Failed to locate of_node [id: -1]
10489 20:16:15.230989 <6>[ 0.420980] megasas: 07.719.03.00-rc1
10490 20:16:15.233284 <6>[ 0.432986] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10491 20:16:15.239699 <6>[ 0.432999] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10492 20:16:15.247241 <6>[ 0.445558] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10493 20:16:15.256115 <6>[ 0.505729] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10494 20:16:15.732064 <6>[ 1.000816] Freeing initrd memory: 17384K
10495 20:16:15.740296 <6>[ 1.006779] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10496 20:16:15.747096 <6>[ 1.011390] tun: Universal TUN/TAP device driver, 1.6
10497 20:16:15.750526 <6>[ 1.012154] thunder_xcv, ver 1.0
10498 20:16:15.753493 <6>[ 1.012174] thunder_bgx, ver 1.0
10499 20:16:15.756609 <6>[ 1.012188] nicpf, ver 1.0
10500 20:16:15.763516 <6>[ 1.013252] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10501 20:16:15.769786 <6>[ 1.013255] hns3: Copyright (c) 2017 Huawei Corporation.
10502 20:16:15.773116 <6>[ 1.013280] hclge is initializing
10503 20:16:15.779680 <6>[ 1.013296] e1000: Intel(R) PRO/1000 Network Driver
10504 20:16:15.783153 <6>[ 1.013298] e1000: Copyright (c) 1999-2006 Intel Corporation.
10505 20:16:15.790646 <6>[ 1.013315] e1000e: Intel(R) PRO/1000 Network Driver
10506 20:16:15.797470 <6>[ 1.013317] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10507 20:16:15.800848 <6>[ 1.013333] igb: Intel(R) Gigabit Ethernet Network Driver
10508 20:16:15.807476 <6>[ 1.013335] igb: Copyright (c) 2007-2014 Intel Corporation.
10509 20:16:15.814688 <6>[ 1.013351] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10510 20:16:15.820945 <6>[ 1.013353] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10511 20:16:15.824739 <6>[ 1.013655] sky2: driver version 1.30
10512 20:16:15.828191 <6>[ 1.014753] VFIO - User Level meta-driver version: 0.3
10513 20:16:15.834528 <6>[ 1.017607] usbcore: registered new interface driver usb-storage
10514 20:16:15.840693 <6>[ 1.017794] usbcore: registered new device driver onboard-usb-hub
10515 20:16:15.847317 <6>[ 1.020585] mt6397-rtc mt6359-rtc: registered as rtc0
10516 20:16:15.857068 <6>[ 1.020736] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:16:16 UTC (1709496976)
10517 20:16:15.860905 <6>[ 1.021357] i2c_dev: i2c /dev entries driver
10518 20:16:15.867209 <6>[ 1.028599] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10519 20:16:15.873519 <6>[ 1.043580] cpu cpu0: EM: created perf domain
10520 20:16:15.877111 <6>[ 1.043910] cpu cpu4: EM: created perf domain
10521 20:16:15.883654 <6>[ 1.047756] sdhci: Secure Digital Host Controller Interface driver
10522 20:16:15.890102 <6>[ 1.047757] sdhci: Copyright(c) Pierre Ossman
10523 20:16:15.894041 <6>[ 1.048121] Synopsys Designware Multimedia Card Interface Driver
10524 20:16:15.900279 <6>[ 1.048489] sdhci-pltfm: SDHCI platform and OF driver helper
10525 20:16:15.903652 <6>[ 1.053069] mmc0: CQHCI version 5.10
10526 20:16:15.910291 <6>[ 1.058949] ledtrig-cpu: registered to indicate activity on CPUs
10527 20:16:15.916549 <6>[ 1.059696] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10528 20:16:15.923169 <6>[ 1.059976] usbcore: registered new interface driver usbhid
10529 20:16:15.926708 <6>[ 1.059978] usbhid: USB HID core driver
10530 20:16:15.933321 <6>[ 1.060106] spi_master spi0: will run message pump with realtime priority
10531 20:16:15.946426 <6>[ 1.090469] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10532 20:16:15.959634 <6>[ 1.092654] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10533 20:16:15.966338 <6>[ 1.093566] cros-ec-spi spi0.0: Chrome EC device registered
10534 20:16:15.975911 <6>[ 1.110644] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10535 20:16:15.983107 <6>[ 1.113436] NET: Registered PF_PACKET protocol family
10536 20:16:15.986080 <6>[ 1.113559] 9pnet: Installing 9P2000 support
10537 20:16:15.989388 <5>[ 1.113632] Key type dns_resolver registered
10538 20:16:15.995942 <6>[ 1.114046] registered taskstats version 1
10539 20:16:15.999428 <5>[ 1.114065] Loading compiled-in X.509 certificates
10540 20:16:16.008752 <4>[ 1.130873] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 20:16:16.018929 <4>[ 1.131029] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10542 20:16:16.029131 <3>[ 1.131057] debugfs: File 'uA_load' in directory '/' already present!
10543 20:16:16.036512 <3>[ 1.131064] debugfs: File 'min_uV' in directory '/' already present!
10544 20:16:16.042454 <3>[ 1.131067] debugfs: File 'max_uV' in directory '/' already present!
10545 20:16:16.048627 <3>[ 1.131070] debugfs: File 'constraint_flags' in directory '/' already present!
10546 20:16:16.055131 <3>[ 1.133144] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10547 20:16:16.061557 <6>[ 1.139927] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10548 20:16:16.068726 <6>[ 1.140597] xhci-mtk 11200000.usb: xHCI Host Controller
10549 20:16:16.074917 <6>[ 1.140618] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10550 20:16:16.084671 <6>[ 1.140877] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10551 20:16:16.091568 <6>[ 1.140950] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10552 20:16:16.098394 <6>[ 1.141105] xhci-mtk 11200000.usb: xHCI Host Controller
10553 20:16:16.104843 <6>[ 1.141119] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10554 20:16:16.111325 <6>[ 1.141140] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10555 20:16:16.114597 <6>[ 1.141943] hub 1-0:1.0: USB hub found
10556 20:16:16.121281 <6>[ 1.141966] hub 1-0:1.0: 1 port detected
10557 20:16:16.127946 <6>[ 1.142218] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10558 20:16:16.131460 <6>[ 1.142555] hub 2-0:1.0: USB hub found
10559 20:16:16.138187 <6>[ 1.142573] hub 2-0:1.0: 1 port detected
10560 20:16:16.141221 <6>[ 1.146609] mtk-msdc 11f70000.mmc: Got CD GPIO
10561 20:16:16.144355 <6>[ 1.147580] mmc0: Command Queue Engine enabled
10562 20:16:16.151399 <6>[ 1.147595] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10563 20:16:16.157782 <6>[ 1.147983] mmcblk0: mmc0:0001 DA4128 116 GiB
10564 20:16:16.164205 <6>[ 1.151260] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10565 20:16:16.167569 <6>[ 1.152336] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10566 20:16:16.174655 <6>[ 1.152939] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10567 20:16:16.180671 <6>[ 1.153781] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10568 20:16:16.187158 <6>[ 1.167379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10569 20:16:16.197812 <6>[ 1.167386] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10570 20:16:16.203711 <4>[ 1.167535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10571 20:16:16.213457 <6>[ 1.168167] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10572 20:16:16.220870 <6>[ 1.168170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10573 20:16:16.226860 <6>[ 1.168295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10574 20:16:16.236872 <6>[ 1.168309] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10575 20:16:16.244064 <6>[ 1.168314] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10576 20:16:16.253059 <6>[ 1.168319] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10577 20:16:16.263131 <6>[ 1.169892] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10578 20:16:16.270016 <6>[ 1.169913] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10579 20:16:16.279798 <6>[ 1.169918] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10580 20:16:16.286492 <6>[ 1.169924] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10581 20:16:16.296578 <6>[ 1.169948] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10582 20:16:16.302773 <6>[ 1.169954] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10583 20:16:16.312972 <6>[ 1.169960] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10584 20:16:16.318768 <6>[ 1.169966] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10585 20:16:16.329688 <6>[ 1.169971] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10586 20:16:16.335667 <6>[ 1.169976] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10587 20:16:16.345210 <6>[ 1.169981] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10588 20:16:16.352101 <6>[ 1.169987] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10589 20:16:16.361709 <6>[ 1.169992] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10590 20:16:16.368629 <6>[ 1.169997] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10591 20:16:16.378681 <6>[ 1.170002] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10592 20:16:16.384902 <6>[ 1.170587] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10593 20:16:16.391336 <6>[ 1.171594] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10594 20:16:16.398485 <6>[ 1.172211] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10595 20:16:16.405077 <6>[ 1.172830] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10596 20:16:16.411773 <6>[ 1.173465] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10597 20:16:16.421070 <6>[ 1.173718] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10598 20:16:16.431230 <6>[ 1.173733] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10599 20:16:16.438007 <6>[ 1.173738] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10600 20:16:16.447662 <6>[ 1.173744] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10601 20:16:16.458053 <6>[ 1.173750] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10602 20:16:16.467255 <6>[ 1.173756] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10603 20:16:16.477438 <6>[ 1.173762] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10604 20:16:16.483620 <6>[ 1.173768] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10605 20:16:16.493859 <6>[ 1.173773] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10606 20:16:16.503413 <6>[ 1.173780] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10607 20:16:16.513396 <6>[ 1.173785] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10608 20:16:16.525003 <6>[ 1.175038] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10609 20:16:16.530304 <6>[ 1.184911] Trying to probe devices needed for running init ...
10610 20:16:16.536798 <6>[ 1.525878] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10611 20:16:16.539950 <6>[ 1.556467] hub 2-1:1.0: USB hub found
10612 20:16:16.543476 <6>[ 1.556777] hub 2-1:1.0: 3 ports detected
10613 20:16:16.549691 <6>[ 1.559175] hub 2-1:1.0: USB hub found
10614 20:16:16.552873 <6>[ 1.559479] hub 2-1:1.0: 3 ports detected
10615 20:16:16.559660 <6>[ 1.681644] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10616 20:16:16.572514 <6>[ 1.838348] hub 1-1:1.0: USB hub found
10617 20:16:16.575406 <6>[ 1.838736] hub 1-1:1.0: 4 ports detected
10618 20:16:16.578773 <6>[ 1.842224] hub 1-1:1.0: USB hub found
10619 20:16:16.581916 <6>[ 1.842585] hub 1-1:1.0: 4 ports detected
10620 20:16:16.655740 <6>[ 1.917843] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10621 20:16:16.891466 <6>[ 2.153810] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10622 20:16:17.012079 <6>[ 2.280904] hub 1-1.4:1.0: USB hub found
10623 20:16:17.015563 <6>[ 2.281219] hub 1-1.4:1.0: 2 ports detected
10624 20:16:17.019346 <6>[ 2.284256] hub 1-1.4:1.0: USB hub found
10625 20:16:17.025324 <6>[ 2.284570] hub 1-1.4:1.0: 2 ports detected
10626 20:16:17.311541 <6>[ 2.573776] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10627 20:16:17.496875 <6>[ 2.757779] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10628 20:16:28.203517 <6>[ 13.475386] ALSA device list:
10629 20:16:28.210559 <6>[ 13.475408] No soundcards found.
10630 20:16:28.213825 <6>[ 13.479511] Freeing unused kernel memory: 8448K
10631 20:16:28.216757 <6>[ 13.479623] Run /init as init process
10632 20:16:28.220458 Loading, please wait...
10633 20:16:28.237271 Starting version 247.3-7+deb11u4
10634 20:16:28.418086 <6>[ 13.683310] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10635 20:16:28.443157 <6>[ 13.698411] remoteproc remoteproc0: scp is available
10636 20:16:28.450011 <6>[ 13.698658] remoteproc remoteproc0: powering up scp
10637 20:16:28.456427 <6>[ 13.698668] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10638 20:16:28.465368 <6>[ 13.698737] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10639 20:16:28.473649 <3>[ 13.740061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 20:16:28.480453 <3>[ 13.740074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10641 20:16:28.490598 <3>[ 13.740078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10642 20:16:28.502507 <3>[ 13.765801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10643 20:16:28.508656 <3>[ 13.765888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10644 20:16:28.519569 <3>[ 13.765897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10645 20:16:28.525291 <3>[ 13.765911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 20:16:28.535259 <3>[ 13.765921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 20:16:28.541685 <3>[ 13.768518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10648 20:16:28.551637 <3>[ 13.771807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10649 20:16:28.558497 <3>[ 13.771828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10650 20:16:28.568231 <3>[ 13.771839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10651 20:16:28.575030 <3>[ 13.771993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 20:16:28.581649 <3>[ 13.772001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10653 20:16:28.591635 <3>[ 13.772009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 20:16:28.598766 <3>[ 13.772712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10655 20:16:28.608687 <3>[ 13.772724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 20:16:28.615198 <3>[ 13.776176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10657 20:16:28.621679 <6>[ 13.777298] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10658 20:16:28.631902 <6>[ 13.779602] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10659 20:16:28.638078 <6>[ 13.779660] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10660 20:16:28.647972 <6>[ 13.779678] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10661 20:16:28.651900 <6>[ 13.803430] mc: Linux media interface: v0.10
10662 20:16:28.661824 <4>[ 13.818611] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10663 20:16:28.667552 <4>[ 13.818611] Fallback method does not support PEC.
10664 20:16:28.670936 <6>[ 13.819423] videodev: Linux video capture interface: v2.00
10665 20:16:28.680902 <3>[ 13.844027] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 20:16:28.687590 <6>[ 13.844459] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10667 20:16:28.697764 <6>[ 13.850651] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10668 20:16:28.704388 <6>[ 13.850662] remoteproc remoteproc0: remote processor scp is now up
10669 20:16:28.711357 <4>[ 13.852555] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10670 20:16:28.717843 <4>[ 13.859498] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10671 20:16:28.727090 <3>[ 13.871486] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 20:16:28.733816 <6>[ 13.915994] usbcore: registered new device driver r8152-cfgselector
10673 20:16:28.740891 <6>[ 13.918150] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10674 20:16:28.744160 <6>[ 13.918167] pci_bus 0000:00: root bus resource [bus 00-ff]
10675 20:16:28.753486 <6>[ 13.918177] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10676 20:16:28.763328 <6>[ 13.918182] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10677 20:16:28.770116 <6>[ 13.918255] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10678 20:16:28.778091 <6>[ 13.918275] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10679 20:16:28.779710 <6>[ 13.918364] pci 0000:00:00.0: supports D1 D2
10680 20:16:28.786694 <6>[ 13.918368] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10681 20:16:28.796333 <6>[ 13.920492] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10682 20:16:28.803283 <6>[ 13.920866] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10683 20:16:28.809621 <6>[ 13.920906] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10684 20:16:28.816076 <6>[ 13.920929] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10685 20:16:28.825839 <6>[ 13.920948] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10686 20:16:28.829059 <6>[ 13.921085] pci 0000:01:00.0: supports D1 D2
10687 20:16:28.836201 <6>[ 13.921089] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10688 20:16:28.842209 <6>[ 13.929501] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10689 20:16:28.852227 <6>[ 13.931966] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10690 20:16:28.859139 <6>[ 13.933624] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10691 20:16:28.868875 <6>[ 13.933662] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10692 20:16:28.875695 <6>[ 13.933668] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10693 20:16:28.882336 <6>[ 13.933681] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10694 20:16:28.892015 <6>[ 13.933697] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10695 20:16:28.898804 <6>[ 13.933713] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10696 20:16:28.905088 <6>[ 13.933729] pci 0000:00:00.0: PCI bridge to [bus 01]
10697 20:16:28.911652 <6>[ 13.933737] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10698 20:16:28.918900 <6>[ 13.933880] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10699 20:16:28.925213 <6>[ 13.934773] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10700 20:16:28.932144 <6>[ 13.935197] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10701 20:16:28.941282 <6>[ 13.938510] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10702 20:16:28.951260 <6>[ 13.938831] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10703 20:16:28.958028 <6>[ 13.968704] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10704 20:16:28.967566 <5>[ 13.988827] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10705 20:16:28.971605 <6>[ 13.993697] Bluetooth: Core ver 2.22
10706 20:16:28.977670 <6>[ 13.993765] NET: Registered PF_BLUETOOTH protocol family
10707 20:16:28.984074 <6>[ 13.993767] Bluetooth: HCI device and connection manager initialized
10708 20:16:28.987695 <6>[ 13.993792] Bluetooth: HCI socket layer initialized
10709 20:16:28.994100 <6>[ 13.993798] Bluetooth: L2CAP socket layer initialized
10710 20:16:28.997700 <6>[ 13.993809] Bluetooth: SCO socket layer initialized
10711 20:16:29.004161 <5>[ 14.000430] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10712 20:16:29.014138 <5>[ 14.000873] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10713 20:16:29.023845 <4>[ 14.000978] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10714 20:16:29.027625 <6>[ 14.001000] cfg80211: failed to load regulatory.db
10715 20:16:29.037413 <6>[ 14.001909] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10716 20:16:29.043486 <6>[ 14.017014] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10717 20:16:29.056980 <6>[ 14.018159] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10718 20:16:29.060633 <6>[ 14.018251] usbcore: registered new interface driver uvcvideo
10719 20:16:29.070248 <4>[ 14.024964] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10720 20:16:29.079969 <4>[ 14.024973] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10721 20:16:29.083109 <6>[ 14.056980] usbcore: registered new interface driver btusb
10722 20:16:29.090263 <6>[ 14.057147] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10723 20:16:29.100733 <4>[ 14.057731] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10724 20:16:29.106286 <3>[ 14.057748] Bluetooth: hci0: Failed to load firmware file (-2)
10725 20:16:29.113026 <3>[ 14.057754] Bluetooth: hci0: Failed to set up firmware (-2)
10726 20:16:29.123004 <4>[ 14.057762] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10727 20:16:29.126597 <6>[ 14.077765] r8152 2-1.3:1.0 eth0: v1.12.13
10728 20:16:29.132726 <6>[ 14.077866] usbcore: registered new interface driver r8152
10729 20:16:29.139629 <6>[ 14.098729] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10730 20:16:29.145775 <6>[ 14.098825] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10731 20:16:29.152576 <6>[ 14.104880] usbcore: registered new interface driver cdc_ether
10732 20:16:29.159393 <6>[ 14.111718] usbcore: registered new interface driver r8153_ecm
10733 20:16:29.165782 <6>[ 14.117638] mt7921e 0000:01:00.0: ASIC revision: 79610010
10734 20:16:29.172150 <6>[ 14.127014] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10735 20:16:29.179551 <6>[ 14.212947] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10736 20:16:29.183238 <6>[ 14.212947]
10737 20:16:29.185643 Begin: Loading essential drivers ... done.
10738 20:16:29.188768 Begin: Running /scripts/init-premount ... done.
10739 20:16:29.205373 Begin: Mounting root file system ... Begin: Running /scripts/nfs-to<6>[ 14.469225] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10740 20:16:29.205518 p ... done.
10741 20:16:29.215199 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10742 20:16:29.218643 Device /sys/class/net/enx00e04c680281 found
10743 20:16:29.218742 done.
10744 20:16:29.270931 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10745 20:16:30.039876 <6>[ 15.306738] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10746 20:16:30.386583 <6>[ 15.656542] r8152 2-1.3:1.0 enx00e04c680281: carrier on
10747 20:16:31.250263 IP-Config: no response after 2 secs - giving up
10748 20:16:31.294042 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10749 20:16:31.314607 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10750 20:16:32.036636 IP-Config: enx00e04c680281 complete (dhcp from 192.168.201.1):
10751 20:16:32.042885 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10752 20:16:32.052411 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10753 20:16:32.060638 host : mt8192-asurada-spherion-r0-cbg-9
10754 20:16:32.066046 domain : lava-rack
10755 20:16:32.069197 rootserver: 192.168.201.1 rootpath:
10756 20:16:32.069279 filename :
10757 20:16:32.161607 done.
10758 20:16:32.169522 Begin: Running /scripts/nfs-bottom ... done.
10759 20:16:32.193165 Begin: Running /scripts/init-bottom ... done.
10760 20:16:33.419403 <6>[ 18.686942] NET: Registered PF_INET6 protocol family
10761 20:16:33.422653 <6>[ 18.690536] Segment Routing with IPv6
10762 20:16:33.428667 <6>[ 18.690553] In-situ OAM (IOAM) with IPv6
10763 20:16:33.565903 <30>[ 18.816218] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10764 20:16:33.569979 <30>[ 18.817217] systemd[1]: Detected architecture arm64.
10765 20:16:33.570074
10766 20:16:33.576035 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10767 20:16:33.576128
10768 20:16:33.598755 <30>[ 18.868426] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10769 20:16:34.461506 <30>[ 19.728014] systemd[1]: Queued start job for default target Graphical Interface.
10770 20:16:34.488532 [[0;32m OK [<30>[ 19.756184] systemd[1]: Created slice system-getty.slice.
10771 20:16:34.491595 0m] Created slice [0;1;39msystem-getty.slice[0m.
10772 20:16:34.510947 [[0;32m OK [0m] Created slic<30>[ 19.779094] systemd[1]: Created slice system-modprobe.slice.
10773 20:16:34.514406 e [0;1;39msystem-modprobe.slice[0m.
10774 20:16:34.535642 [[0;32m OK [0m] Created slic<30>[ 19.803009] systemd[1]: Created slice system-serial\x2dgetty.slice.
10775 20:16:34.541295 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10776 20:16:34.560345 [[0;32m OK [0m] Created slic<30>[ 19.827626] systemd[1]: Created slice User and Session Slice.
10777 20:16:34.562798 e [0;1;39mUser and Session Slice[0m.
10778 20:16:34.586446 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 19.850532] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10779 20:16:34.589067 ssword …ts to Console Directory Watch[0m.
10780 20:16:34.613444 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.877990] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10781 20:16:34.616417 sword R…uests to Wall Directory Watch[0m.
10782 20:16:34.640924 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.901912] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10783 20:16:34.647224 <30>[ 19.902110] systemd[1]: Reached target Local Encrypted Volumes.
10784 20:16:34.650523 l Encrypted Volumes[0m.
10785 20:16:34.669855 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.937901] systemd[1]: Reached target Paths.
10786 20:16:34.669985 s[0m.
10787 20:16:34.693665 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.957774] systemd[1]: Reached target Remote File Systems.
10788 20:16:34.693817 te File Systems[0m.
10789 20:16:34.714085 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.982171] systemd[1]: Reached target Slices.
10790 20:16:34.714203 es[0m.
10791 20:16:34.733855 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 20.001822] systemd[1]: Reached target Swap.
10792 20:16:34.733971 [0m.
10793 20:16:34.757335 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 20.022281] systemd[1]: Listening on initctl Compatibility Named Pipe.
10794 20:16:34.761461 l Compatibility Named Pipe[0m.
10795 20:16:34.770847 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 20.038520] systemd[1]: Listening on Journal Audit Socket.
10796 20:16:34.773846 l Audit Socket[0m.
10797 20:16:34.796472 [[0;32m OK [<30>[ 20.064111] systemd[1]: Listening on Journal Socket (/dev/log).
10798 20:16:34.799479 0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10799 20:16:34.819225 [[0;32m OK [0m] Listening on<30>[ 20.087041] systemd[1]: Listening on Journal Socket.
10800 20:16:34.822497 [0;1;39mJournal Socket[0m.
10801 20:16:34.839525 [[0;32m OK [0m] Listening on<30>[ 20.107669] systemd[1]: Listening on Network Service Netlink Socket.
10802 20:16:34.846457 [0;1;39mNetwork Service Netlink Socket[0m.
10803 20:16:34.869062 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 20.133796] systemd[1]: Listening on udev Control Socket.
10804 20:16:34.869179 ontrol Socket[0m.
10805 20:16:34.886017 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.154278] systemd[1]: Listening on udev Kernel Socket.
10806 20:16:34.889916 ernel Socket[0m.
10807 20:16:34.937448 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.202200] systemd[1]: Mounting Huge Pages File System...
10808 20:16:34.937593 m[0m...
10809 20:16:34.961957 Mounting [0;1;39mPOSIX Message Queue F<30>[ 20.226272] systemd[1]: Mounting POSIX Message Queue File System...
10810 20:16:34.962099 ile System[0m...
10811 20:16:34.985024 Mountin<30>[ 20.252983] systemd[1]: Mounting Kernel Debug File System...
10812 20:16:34.988411 g [0;1;39mKernel Debug File System[0m...
10813 20:16:35.009152 <30>[ 20.274276] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10814 20:16:35.019854 <30>[ 20.280547] systemd[1]: Starting Create list of static device nodes for the current kernel...
10815 20:16:35.026007 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10816 20:16:35.070162 Starting [0;1;39mLoad Kernel Module co<30>[ 20.334461] systemd[1]: Starting Load Kernel Module configfs...
10817 20:16:35.070306 nfigfs[0m...
10818 20:16:35.095080 Starting [0;1;39mLoad <30>[ 20.362708] systemd[1]: Starting Load Kernel Module drm...
10819 20:16:35.098375 Kernel Module drm[0m...
10820 20:16:35.122256 Starting [0;1;39mLoad Kernel Module fu<30>[ 20.386438] systemd[1]: Starting Load Kernel Module fuse...
10821 20:16:35.122391 se[0m...
10822 20:16:35.145170 <30>[ 20.412379] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10823 20:16:35.157088 Startin<30>[ 20.428332] systemd[1]: Starting Journal Service...
10824 20:16:35.160129 g [0;1;39mJournal Service[0m...
10825 20:16:35.173848 <6>[ 20.441645] fuse: init (API version 7.37)
10826 20:16:35.192726 Startin<30>[ 20.460755] systemd[1]: Starting Load Kernel Modules...
10827 20:16:35.196066 g [0;1;39mLoad Kernel Modules[0m...
10828 20:16:35.219618 Starting [0;1;39mRemou<30>[ 20.487292] systemd[1]: Starting Remount Root and Kernel File Systems...
10829 20:16:35.225636 nt Root and Kernel File Systems[0m...
10830 20:16:35.249991 Starting [0;1;39mColdplug All udev Dev<30>[ 20.514526] systemd[1]: Starting Coldplug All udev Devices...
10831 20:16:35.250109 ices[0m...
10832 20:16:35.276305 [[0;32m OK [0m] Mounted [0;<30>[ 20.543901] systemd[1]: Mounted Huge Pages File System.
10833 20:16:35.279464 1;39mHuge Pages File System[0m.
10834 20:16:35.297732 <3>[ 20.563024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 20:16:35.304585 <30>[ 20.566821] systemd[1]: Mounted POSIX Message Queue File System.
10836 20:16:35.317365 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File Sy<3>[ 20.583817] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 20:16:35.321064 stem[0m.
10838 20:16:35.342462 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.610299] systemd[1]: Mounted Kernel Debug File System.
10839 20:16:35.345664 g File System[0m.
10840 20:16:35.361359 <3>[ 20.627629] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 20:16:35.372574 [[0;32m OK [<30>[ 20.640445] systemd[1]: Finished Create list of static device nodes for the current kernel.
10842 20:16:35.386664 0m] Finished [0;1;39mCreate list of st… nodes<3>[ 20.653290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 20:16:35.389149 for the current kernel[0m.
10844 20:16:35.409143 <3>[ 20.676843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 20:16:35.419913 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<30>[ 20.679021] systemd[1]: modprobe@configfs.service: Succeeded.
10846 20:16:35.426605 l Module configf<30>[ 20.679838] systemd[1]: Finished Load Kernel Module configfs.
10847 20:16:35.429484 s[0m.
10848 20:16:35.436168 <3>[ 20.698781] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 20:16:35.447786 [[0;32m OK [0m] Finished [0<30>[ 20.714956] systemd[1]: modprobe@drm.service: Succeeded.
10850 20:16:35.454780 ;1;39mLoad Kerne<30>[ 20.715735] systemd[1]: Finished Load Kernel Module drm.
10851 20:16:35.457662 l Module drm[0m.
10852 20:16:35.469330 <3>[ 20.735575] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 20:16:35.481795 [[0;32m OK [<30>[ 20.747645] systemd[1]: modprobe@fuse.service: Succeeded.
10854 20:16:35.488361 0m] Finished [0<30>[ 20.748302] systemd[1]: Finished Load Kernel Module fuse.
10855 20:16:35.491314 ;1;39mLoad Kernel Module fuse[0m.
10856 20:16:35.501472 <3>[ 20.766303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 20:16:35.512304 [[0;32m OK [0m] Finished [0<30>[ 20.779811] systemd[1]: Finished Load Kernel Modules.
10858 20:16:35.515257 ;1;39mLoad Kernel Modules[0m.
10859 20:16:35.526209 <3>[ 20.793099] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 20:16:35.535347 [[0;32m OK [0m] Finished [0<30>[ 20.803531] systemd[1]: Finished Remount Root and Kernel File Systems.
10861 20:16:35.541893 ;1;39mRemount Root and Kernel File Systems[0m.
10862 20:16:35.557917 <3>[ 20.822366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 20:16:35.591619 Mounting [0;1;39mFUSE <30>[ 20.859458] systemd[1]: Mounting FUSE Control File System...
10864 20:16:35.595585 Control File System[0m...
10865 20:16:35.621598 <30>[ 20.889230] systemd[1]: Mounting Kernel Configuration File System...
10866 20:16:35.624536 Mounting [0;1;39mKernel Configuration File System[0m...
10867 20:16:35.657349 <30>[ 20.924264] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10868 20:16:35.667279 <30>[ 20.924598] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10869 20:16:35.673652 Startin<30>[ 20.930792] systemd[1]: Starting Load/Save Random Seed...
10870 20:16:35.677270 g [0;1;39mLoad/Save Random Seed[0m...
10871 20:16:35.706116 Startin<30>[ 20.972988] systemd[1]: Starting Apply Kernel Variables...
10872 20:16:35.708823 g [0;1;39mApply Kernel Variables[0m...
10873 20:16:35.735945 Starting [0;1;39mCreat<30>[ 21.003677] systemd[1]: Starting Create System Users...
10874 20:16:35.738969 e System Users[0m...
10875 20:16:35.774820 [[0;32m OK [<4>[ 21.031463] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10876 20:16:35.781573 0m] Started [0;<3>[ 21.031479] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10877 20:16:35.787970 1;39mJournal Ser<30>[ 21.032605] systemd[1]: Started Journal Service.
10878 20:16:35.788078 vice[0m.
10879 20:16:35.814945 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10880 20:16:35.826799 See 'systemctl status systemd-udev-trigger.service' for details.
10881 20:16:35.848140 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10882 20:16:35.862991 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10883 20:16:35.879714 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10884 20:16:35.897626 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10885 20:16:35.916693 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10886 20:16:35.972306 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10887 20:16:35.993537 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10888 20:16:36.046377 <46>[ 21.310345] systemd-journald[312]: Received client request to flush runtime journal.
10889 20:16:37.146127 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10890 20:16:37.158783 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10891 20:16:37.174075 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10892 20:16:37.222114 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10893 20:16:37.450132 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10894 20:16:37.503427 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10895 20:16:37.603902 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10896 20:16:37.663189 Starting [0;1;39mNetwork Service[0m...
10897 20:16:37.934433 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10898 20:16:37.955724 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10899 20:16:37.993920 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10900 20:16:38.364656 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10901 20:16:38.378160 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10902 20:16:38.402918 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10903 20:16:38.421834 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10904 20:16:38.439234 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10905 20:16:38.487450 Starting [0;1;39mNetwork Name Resolution[0m...
10906 20:16:38.507830 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10907 20:16:38.536264 Starting [0;1;39mNetwork Time Synchronization[0m...
10908 20:16:38.553858 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10909 20:16:38.590584 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10910 20:16:38.644446 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10911 20:16:39.020219 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10912 20:16:39.034640 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10913 20:16:39.053185 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10914 20:16:39.066796 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10915 20:16:39.081650 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10916 20:16:39.106940 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10917 20:16:39.152819 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10918 20:16:39.173629 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10919 20:16:39.709625 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10920 20:16:39.721885 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10921 20:16:39.888480 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10922 20:16:39.901791 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10923 20:16:39.917656 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10924 20:16:39.966924 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10925 20:16:40.254096 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10926 20:16:40.326612 Starting [0;1;39mUser Login Management[0m...
10927 20:16:40.347135 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10928 20:16:40.365453 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10929 20:16:40.385479 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10930 20:16:40.426578 Starting [0;1;39mPermit User Sessions[0m...
10931 20:16:40.533936 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10932 20:16:40.587285 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10933 20:16:40.608066 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10934 20:16:40.634746 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10935 20:16:40.657949 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10936 20:16:40.677936 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10937 20:16:40.697005 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10938 20:16:40.714964 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10939 20:16:40.775454 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10940 20:16:40.825098 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10941 20:16:40.905630
10942 20:16:40.906265
10943 20:16:40.908930 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10944 20:16:40.909400
10945 20:16:40.912345 debian-bullseye-arm64 login: root (automatic login)
10946 20:16:40.912767
10947 20:16:40.913101
10948 20:16:41.295050 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10949 20:16:41.295783
10950 20:16:41.302230 The programs included with the Debian GNU/Linux system are free software;
10951 20:16:41.308030 the exact distribution terms for each program are described in the
10952 20:16:41.311129 individual files in /usr/share/doc/*/copyright.
10953 20:16:41.311662
10954 20:16:41.318200 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10955 20:16:41.321028 permitted by applicable law.
10956 20:16:41.449637 Matched prompt #10: / #
10958 20:16:41.450813 Setting prompt string to ['/ #']
10959 20:16:41.451309 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10961 20:16:41.452370 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10962 20:16:41.452819 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
10963 20:16:41.453290 Setting prompt string to ['/ #']
10964 20:16:41.453780 Forcing a shell prompt, looking for ['/ #']
10966 20:16:41.504630 / #
10967 20:16:41.505289 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10968 20:16:41.505997 Waiting using forced prompt support (timeout 00:02:30)
10969 20:16:41.511705
10970 20:16:41.512653 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10971 20:16:41.513195 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
10973 20:16:41.614432 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92'
10974 20:16:41.622052 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12928152/extract-nfsrootfs-y17hxb92'
10976 20:16:41.723780 / # export NFS_SERVER_IP='192.168.201.1'
10977 20:16:41.730571 export NFS_SERVER_IP='192.168.201.1'
10978 20:16:41.731560 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10979 20:16:41.732148 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
10980 20:16:41.732645 end: 2 depthcharge-action (duration 00:01:50) [common]
10981 20:16:41.733250 start: 3 lava-test-retry (timeout 00:30:00) [common]
10982 20:16:41.733882 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10983 20:16:41.734360 Using namespace: common
10985 20:16:41.835832 / # #
10986 20:16:41.836044 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10987 20:16:41.841775 #
10988 20:16:41.842173 Using /lava-12928152
10990 20:16:41.942893 / # export SHELL=/bin/sh
10991 20:16:41.950519 export SHELL=/bin/sh
10993 20:16:42.052379 / # . /lava-12928152/environment
10994 20:16:42.059837 . /lava-12928152/environment
10996 20:16:42.168834 / # /lava-12928152/bin/lava-test-runner /lava-12928152/0
10997 20:16:42.169496 Test shell timeout: 10s (minimum of the action and connection timeout)
10998 20:16:42.174960 /lava-12928152/bin/lava-test-runner /lava-12928152/0
10999 20:16:42.489492 + export TESTRUN_ID=0_lc-compliance
11000 20:16:42.495266 + cd /lava-12928152/0/tests/0_lc-compliance
11001 20:16:42.495874 + cat uuid
11002 20:16:42.509906 + UUID=12928152_1.6.2.3.1
11003 20:16:42.510359 + set +x
11004 20:16:42.516147 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12928152_1.6.2.3.1>
11005 20:16:42.516948 Received signal: <STARTRUN> 0_lc-compliance 12928152_1.6.2.3.1
11006 20:16:42.517353 Starting test lava.0_lc-compliance (12928152_1.6.2.3.1)
11007 20:16:42.517765 Skipping test definition patterns.
11008 20:16:42.519556 + /usr/bin/lc-compliance-parser.sh
11009 20:16:43.800052 [0:00:29.027753847] [418] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-6f1bd9cf
11010 20:16:43.802901 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11011 20:16:43.822986 [0:00:29.051123001] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11012 20:16:43.883550 [0:00:29.112156462] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11013 20:16:43.909351 [==========] Running 120 tests from 1 test suite.
11014 20:16:43.941633 [0:00:29.169727693] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11015 20:16:43.993376 [0:00:29.221481231] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11016 20:16:43.999863 [----------] Global test environment set-up.
11017 20:16:44.088991 [----------] 120 tests from CaptureTests/SingleStream
11018 20:16:44.196328 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11019 20:16:44.282726 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11020 20:16:44.283510 Received signal: <TESTSET> START CaptureTests/SingleStream
11021 20:16:44.283998 Starting test_set CaptureTests/SingleStream
11022 20:16:44.286254 Camera needs 4 requests, can't test only 1
11023 20:16:44.386779 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11024 20:16:44.486562
11025 20:16:44.590590 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (64 ms)
11026 20:16:44.687753 [0:00:29.915757693] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11027 20:16:44.731128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11028 20:16:44.731800 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11030 20:16:44.752960 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11031 20:16:44.824883 Camera needs 4 requests, can't test only 2
11032 20:16:44.932756 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11033 20:16:45.025863
11034 20:16:45.121932 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
11035 20:16:45.238215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11036 20:16:45.239104 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11038 20:16:45.257433 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11039 20:16:45.328181 Camera needs 4 requests, can't test only 3
11040 20:16:45.443774 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11041 20:16:45.554450
11042 20:16:45.595235 [0:00:30.822397308] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11043 20:16:45.669175 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11044 20:16:45.780026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11045 20:16:45.780351 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11047 20:16:45.798202 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11048 20:16:45.863905 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (693 ms)
11049 20:16:45.967040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11050 20:16:45.967347 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11052 20:16:45.986055 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11053 20:16:46.056960 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (906 ms)
11054 20:16:46.172995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11055 20:16:46.173323 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11057 20:16:46.192543 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11058 20:16:46.841878 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1257 ms)
11059 20:16:46.851841 [0:00:32.079007308] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11060 20:16:46.981973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11061 20:16:46.982875 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11063 20:16:47.006077 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11064 20:16:48.656251 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1815 ms)
11065 20:16:48.665668 [0:00:33.895239385] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11066 20:16:48.766474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11067 20:16:48.766771 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11069 20:16:48.786800 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11070 20:16:51.386039 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2730 ms)
11071 20:16:51.395616 [0:00:36.625126924] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11072 20:16:51.498556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11073 20:16:51.498859 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11075 20:16:51.516190 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11076 20:16:55.584557 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4199 ms)
11077 20:16:55.594353 [0:00:40.823969001] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 20:16:55.704106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11079 20:16:55.704404 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11081 20:16:55.724709 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11082 20:16:58.761139 <6>[ 44.033736] vpu: disabling
11083 20:16:58.763622 <6>[ 44.033934] vproc2: disabling
11084 20:16:58.766498 <6>[ 44.033989] vproc1: disabling
11085 20:16:58.770077 <6>[ 44.034044] vaud18: disabling
11086 20:16:58.773328 <6>[ 44.034297] vsram_others: disabling
11087 20:16:58.776623 <6>[ 44.034476] va09: disabling
11088 20:16:58.780523 <6>[ 44.034555] vsram_md: disabling
11089 20:16:58.782914 <6>[ 44.034807] Vgpu: disabling
11090 20:17:02.162489 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6579 ms)
11091 20:17:02.172764 [0:00:47.402532386] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11092 20:17:02.228874 [0:00:47.459127079] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11093 20:17:02.285500 [0:00:47.515971232] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11094 20:17:02.288663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11095 20:17:02.288970 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11097 20:17:02.299877 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11098 20:17:02.340419 [0:00:47.571152079] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11099 20:17:02.363781 Camera needs 4 requests, can't test only 1
11100 20:17:02.445569 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11101 20:17:02.527473
11102 20:17:02.622515 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (57 ms)
11103 20:17:02.730611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11104 20:17:02.730930 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11106 20:17:02.750776 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11107 20:17:02.811819 Camera needs 4 requests, can't test only 2
11108 20:17:02.902451 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11109 20:17:02.991138
11110 20:17:03.036329 [0:00:48.266809386] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11111 20:17:03.080529 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (57 ms)
11112 20:17:03.186193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11113 20:17:03.186509 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11115 20:17:03.205319 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11116 20:17:03.263601 Camera needs 4 requests, can't test only 3
11117 20:17:03.350821 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11118 20:17:03.440261
11119 20:17:03.534630 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
11120 20:17:03.635957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11121 20:17:03.636259 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11123 20:17:03.653549 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11124 20:17:03.715637 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (697 ms)
11125 20:17:03.812417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11126 20:17:03.812729 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11128 20:17:03.831908 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11129 20:17:03.934785 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (906 ms)
11130 20:17:03.948311 [0:00:49.174661540] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11131 20:17:04.047508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11132 20:17:04.047798 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11134 20:17:04.065411 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11135 20:17:05.192438 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1258 ms)
11136 20:17:05.205215 [0:00:50.432055925] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 20:17:05.301357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11138 20:17:05.301647 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11140 20:17:05.319533 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11141 20:17:07.010736 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1818 ms)
11142 20:17:07.023750 [0:00:52.252721848] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11143 20:17:07.117303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11144 20:17:07.117607 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11146 20:17:07.135319 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11147 20:17:09.740948 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2731 ms)
11148 20:17:09.754159 [0:00:54.983739079] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 20:17:09.845059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11150 20:17:09.845374 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11152 20:17:09.862172 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11153 20:17:13.940134 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4199 ms)
11154 20:17:13.952695 [0:00:59.182159465] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11155 20:17:14.060502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11156 20:17:14.060796 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11158 20:17:14.078816 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11159 20:17:20.517848 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6578 ms)
11160 20:17:20.531615 [0:01:05.760350716] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 20:17:20.584443 [0:01:05.815652286] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 20:17:20.634588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11163 20:17:20.634889 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11165 20:17:20.648795 [0:01:05.875024842] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 20:17:20.657804 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11167 20:17:20.699949 [0:01:05.930794426] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11168 20:17:20.723129 Camera needs 4 requests, can't test only 1
11169 20:17:20.815054 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11170 20:17:20.904249
11171 20:17:21.001550 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (58 ms)
11172 20:17:21.105002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11173 20:17:21.105306 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11175 20:17:21.121827 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11176 20:17:21.179881 Camera needs 4 requests, can't test only 2
11177 20:17:21.270786 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11178 20:17:21.359932
11179 20:17:21.398020 [0:01:06.629089520] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11180 20:17:21.453934 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (57 ms)
11181 20:17:21.553485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11182 20:17:21.553816 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11184 20:17:21.571614 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11185 20:17:21.630245 Camera needs 4 requests, can't test only 3
11186 20:17:21.725631 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11187 20:17:21.821037
11188 20:17:21.912726 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (58 ms)
11189 20:17:22.024422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11190 20:17:22.024718 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11192 20:17:22.043313 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11193 20:17:22.100417 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (698 ms)
11194 20:17:22.205669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11195 20:17:22.205954 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11197 20:17:22.223402 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11198 20:17:22.294844 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (906 ms)
11199 20:17:22.307489 [0:01:07.534620057] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11200 20:17:22.403315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11201 20:17:22.403604 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11203 20:17:22.422010 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11204 20:17:23.550683 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11205 20:17:23.563814 [0:01:08.792840578] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 20:17:23.670704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11207 20:17:23.671000 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11209 20:17:23.689255 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11210 20:17:25.369338 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1819 ms)
11211 20:17:25.382840 [0:01:10.611304152] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 20:17:25.483559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11213 20:17:25.483928 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11215 20:17:25.504646 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11216 20:17:28.097708 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11217 20:17:28.111372 [0:01:13.339923382] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 20:17:28.219646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11219 20:17:28.219966 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11221 20:17:28.238985 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11222 20:17:32.296049 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4198 ms)
11223 20:17:32.309233 [0:01:17.538723855] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 20:17:32.408882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11225 20:17:32.409174 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11227 20:17:32.428224 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11228 20:17:38.874141 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6579 ms)
11229 20:17:38.888103 [0:01:24.118003148] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11230 20:17:38.943357 [0:01:24.175034802] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 20:17:38.983414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11232 20:17:38.983728 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11234 20:17:38.996911 [0:01:24.228324385] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 20:17:39.003021 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11236 20:17:39.050386 [0:01:24.281848442] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 20:17:39.062892 Camera needs 4 requests, can't test only 1
11238 20:17:39.146535 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11239 20:17:39.230792
11240 20:17:39.322530 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11241 20:17:39.419875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11242 20:17:39.420170 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11244 20:17:39.440803 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11245 20:17:39.502285 Camera needs 4 requests, can't test only 2
11246 20:17:39.592772 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11247 20:17:39.688068
11248 20:17:39.743180 [0:01:24.975003762] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 20:17:39.786686 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (57 ms)
11250 20:17:39.895755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11251 20:17:39.896047 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11253 20:17:39.915137 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11254 20:17:39.974234 Camera needs 4 requests, can't test only 3
11255 20:17:40.063284 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11256 20:17:40.149377
11257 20:17:40.242277 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (51 ms)
11258 20:17:40.345462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11259 20:17:40.345760 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11261 20:17:40.365812 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11262 20:17:40.427240 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (695 ms)
11263 20:17:40.540046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11264 20:17:40.540344 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11266 20:17:40.559572 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11267 20:17:40.638857 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (904 ms)
11268 20:17:40.651822 [0:01:25.879913001] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 20:17:40.745839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11270 20:17:40.746158 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11272 20:17:40.766343 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11273 20:17:41.896361 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1257 ms)
11274 20:17:41.909791 [0:01:27.137271528] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 20:17:42.006337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11276 20:17:42.006664 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11278 20:17:42.024941 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11279 20:17:43.713341 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1817 ms)
11280 20:17:43.726723 [0:01:28.954245901] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 20:17:43.835660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11282 20:17:43.835994 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11284 20:17:43.856267 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11285 20:17:46.441124 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11286 20:17:46.454066 [0:01:31.683827895] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 20:17:46.580295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11288 20:17:46.581136 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11290 20:17:46.604811 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11291 20:17:50.639532 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4199 ms)
11292 20:17:50.652875 [0:01:35.883132871] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11293 20:17:50.780614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11294 20:17:50.781383 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11296 20:17:50.798739 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11297 20:17:57.218784 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6579 ms)
11298 20:17:57.232096 [0:01:42.462179719] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11299 20:17:57.284992 [0:01:42.517609489] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 20:17:57.339588 [0:01:42.572578343] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 20:17:57.362452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11302 20:17:57.363139 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11304 20:17:57.386335 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11305 20:17:57.396195 [0:01:42.629568402] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 20:17:57.465185 Camera needs 4 requests, can't test only 1
11307 20:17:57.582302 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11308 20:17:57.681480
11309 20:17:57.802099 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (58 ms)
11310 20:17:57.936159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11311 20:17:57.937010 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11313 20:17:57.957877 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11314 20:17:58.031410 Camera needs 4 requests, can't test only 2
11315 20:17:58.146283 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11316 20:17:58.251412
11317 20:17:58.370859 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11318 20:17:58.502749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11319 20:17:58.503722 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11321 20:17:58.526014 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11322 20:17:58.601301 Camera needs 4 requests, can't test only 3
11323 20:17:58.707477 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11324 20:17:58.824860
11325 20:17:58.944204 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11326 20:17:59.080535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11327 20:17:59.081340 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11329 20:17:59.105648 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11330 20:17:59.465683 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2079 ms)
11331 20:17:59.479314 [0:01:44.707604445] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 20:17:59.608057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11333 20:17:59.608890 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11335 20:17:59.631072 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11336 20:18:02.175219 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2710 ms)
11337 20:18:02.188147 [0:01:47.419678776] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 20:18:02.310379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11339 20:18:02.311146 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11341 20:18:02.331355 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11342 20:18:05.936361 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3762 ms)
11343 20:18:05.949658 [0:01:51.181492889] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11344 20:18:06.072224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11345 20:18:06.073054 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11347 20:18:06.097380 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11348 20:18:11.376907 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5441 ms)
11349 20:18:11.390316 [0:01:56.622281817] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11350 20:18:11.518384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11351 20:18:11.519156 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11353 20:18:11.541632 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11354 20:18:19.550204 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8174 ms)
11355 20:18:19.563771 [0:02:04.795702963] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11356 20:18:19.703362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11357 20:18:19.704274 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11359 20:18:19.725052 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11360 20:18:32.131735 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12579 ms)
11361 20:18:32.144662 [0:02:17.375457364] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11362 20:18:32.276288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11363 20:18:32.277068 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11365 20:18:32.299497 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11366 20:18:51.851003 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19720 ms)
11367 20:18:51.864995 [0:02:37.095314847] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11368 20:18:51.916568 [0:02:37.149568225] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 20:18:51.969895 [0:02:37.203015762] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 20:18:51.994392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11371 20:18:51.995228 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11373 20:18:52.015966 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11374 20:18:52.029302 [0:02:37.257562987] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 20:18:52.092912 Camera needs 4 requests, can't test only 1
11376 20:18:52.213286 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11377 20:18:52.328219
11378 20:18:52.443125 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11379 20:18:52.583975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11380 20:18:52.584743 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11382 20:18:52.604236 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11383 20:18:52.678512 Camera needs 4 requests, can't test only 2
11384 20:18:52.802354 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11385 20:18:52.919861
11386 20:18:53.040495 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (53 ms)
11387 20:18:53.166292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11388 20:18:53.167085 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11390 20:18:53.185788 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11391 20:18:53.257305 Camera needs 4 requests, can't test only 3
11392 20:18:53.379493 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11393 20:18:53.504209
11394 20:18:53.629153 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11395 20:18:53.752070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11396 20:18:53.753038 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11398 20:18:53.772260 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11399 20:18:54.097132 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2078 ms)
11400 20:18:54.106645 [0:02:39.335374526] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 20:18:54.236336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11402 20:18:54.237132 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11404 20:18:54.256352 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11405 20:18:56.806443 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2709 ms)
11406 20:18:56.815779 [0:02:42.046814374] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 20:18:56.942917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11408 20:18:56.943714 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11410 20:18:56.962225 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11411 20:19:00.566121 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3760 ms)
11412 20:19:00.575947 [0:02:45.807646346] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 20:19:00.690958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11414 20:19:00.691712 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11416 20:19:00.707171 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11417 20:19:06.007372 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5441 ms)
11418 20:19:06.017092 [0:02:51.248196587] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 20:19:06.147321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11420 20:19:06.148254 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11422 20:19:06.167750 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11423 20:19:14.180159 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8174 ms)
11424 20:19:14.189947 [0:02:59.421847488] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 20:19:14.326755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11426 20:19:14.327538 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11428 20:19:14.347306 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11429 20:19:26.761451 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12581 ms)
11430 20:19:26.770789 [0:03:12.003465991] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11431 20:19:26.910315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11432 20:19:26.911112 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11434 20:19:26.932169 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11435 20:19:46.482854 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19723 ms)
11436 20:19:46.493051 [0:03:31.726700891] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11437 20:19:46.546724 [0:03:31.782178460] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 20:19:46.600953 [0:03:31.836828909] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 20:19:46.617536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11440 20:19:46.618281 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11442 20:19:46.635761 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11443 20:19:46.654501 [0:03:31.890486322] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 20:19:46.707791 Camera needs 4 requests, can't test only 1
11445 20:19:46.814049 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11446 20:19:46.930898
11447 20:19:47.058565 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11448 20:19:47.196244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11449 20:19:47.197255 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11451 20:19:47.216703 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11452 20:19:47.294075 Camera needs 4 requests, can't test only 2
11453 20:19:47.409125 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11454 20:19:47.513953
11455 20:19:47.644517 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11456 20:19:47.773346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11457 20:19:47.774118 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11459 20:19:47.793345 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11460 20:19:47.866856 Camera needs 4 requests, can't test only 3
11461 20:19:47.985299 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11462 20:19:48.096455
11463 20:19:48.218963 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11464 20:19:48.346659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11465 20:19:48.347467 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11467 20:19:48.365237 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11468 20:19:48.728193 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11469 20:19:48.738248 [0:03:33.969649258] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11470 20:19:48.875271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11471 20:19:48.876135 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11473 20:19:48.893619 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11474 20:19:51.437930 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2710 ms)
11475 20:19:51.447746 [0:03:36.681911372] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11476 20:19:51.578970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11477 20:19:51.579831 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11479 20:19:51.601564 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11480 20:19:55.198689 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3760 ms)
11481 20:19:55.208213 [0:03:40.442564102] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11482 20:19:55.337991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11483 20:19:55.339032 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11485 20:19:55.359977 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11486 20:20:00.638926 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5441 ms)
11487 20:20:00.648464 [0:03:45.883494607] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 20:20:00.773458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11489 20:20:00.774276 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11491 20:20:00.792108 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11492 20:20:08.814721 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8176 ms)
11493 20:20:08.823803 [0:03:54.059704281] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11494 20:20:08.933335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11495 20:20:08.933697 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11497 20:20:08.950498 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11498 20:20:21.394778 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12582 ms)
11499 20:20:21.404691 [0:04:06.641984506] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11500 20:20:21.513471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11501 20:20:21.513805 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11503 20:20:21.527883 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11504 20:20:41.117862 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19719 ms)
11505 20:20:41.127209 [0:04:26.362435723] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11506 20:20:41.180893 [0:04:26.417890875] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 20:20:41.235871 [0:04:26.472896801] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 20:20:41.241802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11509 20:20:41.242068 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11511 20:20:41.259028 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11512 20:20:41.291404 [0:04:26.528851246] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 20:20:41.321034 Camera needs 4 requests, can't test only 1
11514 20:20:41.408514 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11515 20:20:41.496285
11516 20:20:41.589634 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11517 20:20:41.686677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11518 20:20:41.687051 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11520 20:20:41.699611 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11521 20:20:41.756727 Camera needs 4 requests, can't test only 2
11522 20:20:41.844258 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11523 20:20:41.931679
11524 20:20:42.029462 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11525 20:20:42.130961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11526 20:20:42.131256 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11528 20:20:42.144357 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11529 20:20:42.203037 Camera needs 4 requests, can't test only 3
11530 20:20:42.289993 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11531 20:20:42.373068
11532 20:20:42.469349 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (56 ms)
11533 20:20:42.575389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11534 20:20:42.575749 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11536 20:20:42.589675 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11537 20:20:43.363767 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2077 ms)
11538 20:20:43.373689 [0:04:28.606606225] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11539 20:20:43.472761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11540 20:20:43.473050 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11542 20:20:43.488846 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11543 20:20:46.075177 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11544 20:20:46.085844 [0:04:31.319866074] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 20:20:46.179830 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11547 20:20:46.182672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11548 20:20:46.200544 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11549 20:20:49.836180 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3760 ms)
11550 20:20:49.846507 [0:04:35.080716224] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11551 20:20:49.954509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11552 20:20:49.954809 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11554 20:20:49.969092 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11555 20:20:55.276828 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5441 ms)
11556 20:20:55.286892 [0:04:40.521671929] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11557 20:20:55.395503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11558 20:20:55.395798 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11560 20:20:55.409886 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11561 20:21:03.450310 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8173 ms)
11562 20:21:03.460211 [0:04:48.694485820] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11563 20:21:03.558200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11564 20:21:03.558496 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11566 20:21:03.572629 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11567 20:21:16.032336 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12581 ms)
11568 20:21:16.041990 [0:05:01.275911871] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11569 20:21:16.170478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11570 20:21:16.171287 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11572 20:21:16.188190 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11573 20:21:35.752775 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19720 ms)
11574 20:21:35.762375 [0:05:20.994892208] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 20:21:35.896220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11576 20:21:35.897136 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11578 20:21:35.916935 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11579 20:21:36.166824 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11580 20:21:36.179587 [0:05:21.410691326] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 20:21:36.308969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11582 20:21:36.309803 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11584 20:21:36.332361 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11585 20:21:36.655407 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11586 20:21:36.668637 [0:05:21.899766058] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11587 20:21:36.781565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11588 20:21:36.782060 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11590 20:21:36.799811 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11591 20:21:37.212987 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11592 20:21:37.226048 [0:05:22.457204965] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 20:21:37.345677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11594 20:21:37.346412 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11596 20:21:37.365900 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11597 20:21:37.910450 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (697 ms)
11598 20:21:37.923290 [0:05:23.154455024] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 20:21:38.051120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11600 20:21:38.051913 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11602 20:21:38.071660 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11603 20:21:38.818151 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (908 ms)
11604 20:21:38.831489 [0:05:24.061102098] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 20:21:38.934671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11606 20:21:38.935049 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11608 20:21:38.954154 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11609 20:21:40.073056 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1255 ms)
11610 20:21:40.085767 [0:05:25.317850052] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 20:21:40.209899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11612 20:21:40.210639 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11614 20:21:40.231018 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11615 20:21:41.889328 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1817 ms)
11616 20:21:41.901988 [0:05:27.135152804] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 20:21:42.035735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11618 20:21:42.036465 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11620 20:21:42.057427 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11621 20:21:44.617218 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2728 ms)
11622 20:21:44.629948 [0:05:29.862330227] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 20:21:44.749028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11624 20:21:44.749789 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11626 20:21:44.771085 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11627 20:21:48.814147 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4197 ms)
11628 20:21:48.826974 [0:05:34.059289603] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 20:21:48.946826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11630 20:21:48.947661 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11632 20:21:48.969668 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11633 20:21:55.390645 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6576 ms)
11634 20:21:55.403189 [0:05:40.635758458] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 20:21:55.526693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11636 20:21:55.527488 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11638 20:21:55.551570 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11639 20:21:55.811429 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (418 ms)
11640 20:21:55.820823 [0:05:41.053444804] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 20:21:55.943582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11642 20:21:55.944406 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11644 20:21:55.964350 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11645 20:21:56.300805 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (489 ms)
11646 20:21:56.311015 [0:05:41.542138851] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 20:21:56.443876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11648 20:21:56.444635 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11650 20:21:56.462448 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11651 20:21:56.858014 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (557 ms)
11652 20:21:56.867749 [0:05:42.099406181] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 20:21:56.993124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11654 20:21:56.993884 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11656 20:21:57.011916 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11657 20:21:57.555783 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (698 ms)
11658 20:21:57.565200 [0:05:42.797261328] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 20:21:57.691440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11660 20:21:57.692232 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11662 20:21:57.713189 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11663 20:21:58.463541 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (908 ms)
11664 20:21:58.473584 [0:05:43.705044397] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11665 20:21:58.598751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11666 20:21:58.599543 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11668 20:21:58.619089 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11669 20:21:59.721112 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1257 ms)
11670 20:21:59.731066 [0:05:44.962647260] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11671 20:21:59.859659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11672 20:21:59.860444 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11674 20:21:59.880066 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11675 20:22:01.538169 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1818 ms)
11676 20:22:01.548098 [0:05:46.779870114] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11677 20:22:01.685115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11678 20:22:01.685911 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11680 20:22:01.706887 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11681 20:22:04.268599 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2729 ms)
11682 20:22:04.277208 [0:05:49.511536870] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11683 20:22:04.403921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11684 20:22:04.404712 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11686 20:22:04.422447 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11687 20:22:08.466366 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4200 ms)
11688 20:22:08.476162 [0:05:53.711118060] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11689 20:22:08.576894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11690 20:22:08.577216 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11692 20:22:08.593279 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11693 20:22:15.045831 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6579 ms)
11694 20:22:15.055996 [0:06:00.290262059] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11695 20:22:15.155243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11696 20:22:15.155562 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11698 20:22:15.170511 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11699 20:22:15.464090 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (418 ms)
11700 20:22:15.473660 [0:06:00.706662273] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11701 20:22:15.579184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11702 20:22:15.579506 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11704 20:22:15.594610 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11705 20:22:15.952137 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (488 ms)
11706 20:22:15.962526 [0:06:01.194507680] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 20:22:16.057412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11708 20:22:16.057734 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11710 20:22:16.074393 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11711 20:22:16.509234 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (558 ms)
11712 20:22:16.519448 [0:06:01.751868906] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11713 20:22:16.630184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11714 20:22:16.630489 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11716 20:22:16.645390 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11717 20:22:17.206927 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (697 ms)
11718 20:22:17.217122 [0:06:02.449417918] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11719 20:22:17.323444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11720 20:22:17.323770 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11722 20:22:17.338246 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11723 20:22:18.116067 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (909 ms)
11724 20:22:18.126165 [0:06:03.358650739] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11725 20:22:18.233919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11726 20:22:18.234255 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11728 20:22:18.249512 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11729 20:22:19.373414 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1258 ms)
11730 20:22:19.382940 [0:06:04.615994734] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11731 20:22:19.504215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11732 20:22:19.504661 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11734 20:22:19.522359 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11735 20:22:21.191081 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1818 ms)
11736 20:22:21.200749 [0:06:06.433684986] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11737 20:22:21.301693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11738 20:22:21.302108 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11740 20:22:21.315026 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11741 20:22:23.920278 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2729 ms)
11742 20:22:23.929864 [0:06:09.166004814] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11743 20:22:24.029191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11744 20:22:24.029467 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11746 20:22:24.044625 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11747 20:22:28.120323 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4200 ms)
11748 20:22:28.129821 [0:06:13.365427010] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11749 20:22:28.226468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11750 20:22:28.226756 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11752 20:22:28.241988 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11753 20:22:34.699440 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6579 ms)
11754 20:22:34.709222 [0:06:19.945123088] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 20:22:34.816940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11756 20:22:34.817274 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11758 20:22:34.831972 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11759 20:22:35.119164 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (420 ms)
11760 20:22:35.129326 [0:06:20.361785282] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11761 20:22:35.232472 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11763 20:22:35.235143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11764 20:22:35.251273 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11765 20:22:35.606704 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (487 ms)
11766 20:22:35.616778 [0:06:20.849649761] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11767 20:22:35.717710 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11769 20:22:35.721136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11770 20:22:35.735463 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11771 20:22:36.164650 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (558 ms)
11772 20:22:36.173855 [0:06:21.407282194] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11773 20:22:36.278206 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11775 20:22:36.281373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11776 20:22:36.296663 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11777 20:22:36.861194 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (697 ms)
11778 20:22:36.870870 [0:06:22.104333848] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11779 20:22:36.975016 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11781 20:22:36.977410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11782 20:22:36.993495 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11783 20:22:37.770573 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (909 ms)
11784 20:22:37.780031 [0:06:23.013620167] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 20:22:37.886752 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11787 20:22:37.889210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11788 20:22:37.906181 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11789 20:22:39.027440 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1257 ms)
11790 20:22:39.037728 [0:06:24.270673149] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11791 20:22:39.142196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11792 20:22:39.142568 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11794 20:22:39.158263 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11795 20:22:40.845237 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1818 ms)
11796 20:22:40.854382 [0:06:26.087989070] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11797 20:22:40.949426 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11799 20:22:40.952254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11800 20:22:40.966331 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11801 20:22:43.572844 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11802 20:22:43.582277 [0:06:28.818197892] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11803 20:22:43.702949 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11805 20:22:43.706395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11806 20:22:43.724636 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11807 20:22:47.771283 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4199 ms)
11808 20:22:47.781277 [0:06:33.017339656] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11809 20:22:47.905434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11810 20:22:47.906203 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11812 20:22:47.926127 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11813 20:22:54.351101 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6580 ms)
11814 20:22:54.485553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11815 20:22:54.486368 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11817 20:22:54.504795 [----------] 120 tests from CaptureTests/SingleStream (370545 ms total)
11818 20:22:54.615442
11819 20:22:54.732305 [----------] Global test environment tear-down
11820 20:22:54.836172 [==========] 120 tests from 1 test suite ran. (370545 ms total)
11821 20:22:54.950672 <LAVA_SIGNAL_TESTSET STOP>
11822 20:22:54.951769 Received signal: <TESTSET> STOP
11823 20:22:54.952307 Closing test_set CaptureTests/SingleStream
11824 20:22:54.968299 + set +x
11825 20:22:54.971085 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12928152_1.6.2.3.1>
11826 20:22:54.971781 Received signal: <ENDRUN> 0_lc-compliance 12928152_1.6.2.3.1
11827 20:22:54.972176 Ending use of test pattern.
11828 20:22:54.972496 Ending test lava.0_lc-compliance (12928152_1.6.2.3.1), duration 372.46
11830 20:22:54.974470 <LAVA_TEST_RUNNER EXIT>
11831 20:22:54.975101 ok: lava_test_shell seems to have completed
11832 20:22:54.983939 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11833 20:22:54.984785 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11834 20:22:54.985220 end: 3 lava-test-retry (duration 00:06:13) [common]
11835 20:22:54.985641 start: 4 finalize (timeout 00:10:00) [common]
11836 20:22:54.986072 start: 4.1 power-off (timeout 00:00:30) [common]
11837 20:22:54.986785 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11838 20:22:55.109340 >> Command sent successfully.
11839 20:22:55.113225 Returned 0 in 0 seconds
11840 20:22:55.214215 end: 4.1 power-off (duration 00:00:00) [common]
11842 20:22:55.216089 start: 4.2 read-feedback (timeout 00:10:00) [common]
11843 20:22:55.217682 Listened to connection for namespace 'common' for up to 1s
11844 20:22:56.218208 Finalising connection for namespace 'common'
11845 20:22:56.218974 Disconnecting from shell: Finalise
11846 20:22:56.219493 / #
11847 20:22:56.320383 end: 4.2 read-feedback (duration 00:00:01) [common]
11848 20:22:56.320559 end: 4 finalize (duration 00:00:01) [common]
11849 20:22:56.320716 Cleaning after the job
11850 20:22:56.320840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/ramdisk
11851 20:22:56.323357 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/kernel
11852 20:22:56.336494 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/dtb
11853 20:22:56.336687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/nfsrootfs
11854 20:22:56.393637 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928152/tftp-deploy-w1fw5qu9/modules
11855 20:22:56.400761 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928152
11856 20:22:56.720845 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928152
11857 20:22:56.721023 Job finished correctly