Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 32
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 33
1 20:16:35.320853 lava-dispatcher, installed at version: 2024.01
2 20:16:35.321086 start: 0 validate
3 20:16:35.321232 Start time: 2024-03-03 20:16:35.321224+00:00 (UTC)
4 20:16:35.321373 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:16:35.321506 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20240129.0%2Farm64%2Frootfs.cpio.gz exists
6 20:16:35.589499 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:16:35.589811 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:16:35.856074 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:16:35.856316 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:16:36.122110 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:16:36.122355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:16:36.466570 validate duration: 1.15
14 20:16:36.467089 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:16:36.467282 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:16:36.467451 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:16:36.467666 Not decompressing ramdisk as can be used compressed.
18 20:16:36.467816 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20240129.0/arm64/rootfs.cpio.gz
19 20:16:36.467946 saving as /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/ramdisk/rootfs.cpio.gz
20 20:16:36.468067 total size: 84944419 (81 MB)
21 20:16:36.469955 progress 0 % (0 MB)
22 20:16:36.505807 progress 5 % (4 MB)
23 20:16:36.540201 progress 10 % (8 MB)
24 20:16:36.564121 progress 15 % (12 MB)
25 20:16:36.587732 progress 20 % (16 MB)
26 20:16:36.611320 progress 25 % (20 MB)
27 20:16:36.634774 progress 30 % (24 MB)
28 20:16:36.658307 progress 35 % (28 MB)
29 20:16:36.681705 progress 40 % (32 MB)
30 20:16:36.705190 progress 45 % (36 MB)
31 20:16:36.728846 progress 50 % (40 MB)
32 20:16:36.752216 progress 55 % (44 MB)
33 20:16:36.775771 progress 60 % (48 MB)
34 20:16:36.799048 progress 65 % (52 MB)
35 20:16:36.822634 progress 70 % (56 MB)
36 20:16:36.846123 progress 75 % (60 MB)
37 20:16:36.869934 progress 80 % (64 MB)
38 20:16:36.893458 progress 85 % (68 MB)
39 20:16:36.917128 progress 90 % (72 MB)
40 20:16:36.940528 progress 95 % (76 MB)
41 20:16:36.963769 progress 100 % (81 MB)
42 20:16:36.963999 81 MB downloaded in 0.50 s (163.35 MB/s)
43 20:16:36.964186 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:16:36.964482 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:16:36.964573 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:16:36.964673 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:16:36.964816 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:16:36.964900 saving as /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/kernel/Image
50 20:16:36.964968 total size: 51601920 (49 MB)
51 20:16:36.965032 No compression specified
52 20:16:36.966171 progress 0 % (0 MB)
53 20:16:36.981107 progress 5 % (2 MB)
54 20:16:36.995600 progress 10 % (4 MB)
55 20:16:37.010124 progress 15 % (7 MB)
56 20:16:37.024519 progress 20 % (9 MB)
57 20:16:37.039092 progress 25 % (12 MB)
58 20:16:37.053580 progress 30 % (14 MB)
59 20:16:37.068043 progress 35 % (17 MB)
60 20:16:37.082459 progress 40 % (19 MB)
61 20:16:37.096955 progress 45 % (22 MB)
62 20:16:37.111381 progress 50 % (24 MB)
63 20:16:37.125816 progress 55 % (27 MB)
64 20:16:37.144302 progress 60 % (29 MB)
65 20:16:37.159513 progress 65 % (32 MB)
66 20:16:37.175839 progress 70 % (34 MB)
67 20:16:37.196140 progress 75 % (36 MB)
68 20:16:37.210324 progress 80 % (39 MB)
69 20:16:37.224412 progress 85 % (41 MB)
70 20:16:37.238271 progress 90 % (44 MB)
71 20:16:37.251852 progress 95 % (46 MB)
72 20:16:37.265567 progress 100 % (49 MB)
73 20:16:37.265847 49 MB downloaded in 0.30 s (163.56 MB/s)
74 20:16:37.266005 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:16:37.266240 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:16:37.266375 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:16:37.266497 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:16:37.266691 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:16:37.266802 saving as /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/dtb/mt8192-asurada-spherion-r0.dtb
81 20:16:37.266887 total size: 47278 (0 MB)
82 20:16:37.266953 No compression specified
83 20:16:37.268075 progress 69 % (0 MB)
84 20:16:37.268371 progress 100 % (0 MB)
85 20:16:37.268535 0 MB downloaded in 0.00 s (27.40 MB/s)
86 20:16:37.268662 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:16:37.268889 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:16:37.268975 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:16:37.269058 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:16:37.269174 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:16:37.269243 saving as /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/modules/modules.tar
93 20:16:37.269305 total size: 8632284 (8 MB)
94 20:16:37.269367 Using unxz to decompress xz
95 20:16:37.273987 progress 0 % (0 MB)
96 20:16:37.294747 progress 5 % (0 MB)
97 20:16:37.319968 progress 10 % (0 MB)
98 20:16:37.345001 progress 15 % (1 MB)
99 20:16:37.369198 progress 20 % (1 MB)
100 20:16:37.396169 progress 25 % (2 MB)
101 20:16:37.424822 progress 30 % (2 MB)
102 20:16:37.453805 progress 35 % (2 MB)
103 20:16:37.480626 progress 40 % (3 MB)
104 20:16:37.507247 progress 45 % (3 MB)
105 20:16:37.534503 progress 50 % (4 MB)
106 20:16:37.560885 progress 55 % (4 MB)
107 20:16:37.586948 progress 60 % (4 MB)
108 20:16:37.612754 progress 65 % (5 MB)
109 20:16:37.639092 progress 70 % (5 MB)
110 20:16:37.665327 progress 75 % (6 MB)
111 20:16:37.692507 progress 80 % (6 MB)
112 20:16:37.717940 progress 85 % (7 MB)
113 20:16:37.745175 progress 90 % (7 MB)
114 20:16:37.775337 progress 95 % (7 MB)
115 20:16:37.804787 progress 100 % (8 MB)
116 20:16:37.810291 8 MB downloaded in 0.54 s (15.22 MB/s)
117 20:16:37.810640 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:16:37.811094 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:16:37.811197 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:16:37.811323 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:16:37.811411 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:16:37.811524 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:16:37.811823 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h
125 20:16:37.812020 makedir: /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin
126 20:16:37.812142 makedir: /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/tests
127 20:16:37.812259 makedir: /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/results
128 20:16:37.812410 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-add-keys
129 20:16:37.812595 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-add-sources
130 20:16:37.812785 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-background-process-start
131 20:16:37.812968 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-background-process-stop
132 20:16:37.813155 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-common-functions
133 20:16:37.813343 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-echo-ipv4
134 20:16:37.813529 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-install-packages
135 20:16:37.813699 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-installed-packages
136 20:16:37.813886 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-os-build
137 20:16:37.814072 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-probe-channel
138 20:16:37.814244 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-probe-ip
139 20:16:37.814428 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-target-ip
140 20:16:37.814616 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-target-mac
141 20:16:37.814804 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-target-storage
142 20:16:37.814981 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-case
143 20:16:37.815165 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-event
144 20:16:37.815360 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-feedback
145 20:16:37.815509 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-raise
146 20:16:37.815655 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-reference
147 20:16:37.815811 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-runner
148 20:16:37.815943 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-set
149 20:16:37.816104 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-test-shell
150 20:16:37.816258 Updating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-install-packages (oe)
151 20:16:37.816448 Updating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/bin/lava-installed-packages (oe)
152 20:16:37.816606 Creating /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/environment
153 20:16:37.816719 LAVA metadata
154 20:16:37.816821 - LAVA_JOB_ID=12928123
155 20:16:37.816893 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:16:37.817026 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:16:37.817131 skipped lava-vland-overlay
158 20:16:37.817246 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:16:37.817382 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:16:37.817478 skipped lava-multinode-overlay
161 20:16:37.817583 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:16:37.817674 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:16:37.817770 Loading test definitions
164 20:16:37.817885 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 20:16:37.817968 Using /lava-12928123 at stage 0
166 20:16:37.818096 Fetching tests from https://github.com/kernelci/kernelci-core
167 20:16:37.818197 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/0/tests/0_sleep'
168 20:16:38.416425 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/0/tests/0_sleep
169 20:16:38.418379 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 20:16:38.419015 uuid=12928123_1.5.2.3.1 testdef=None
171 20:16:38.419235 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 20:16:38.419654 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 20:16:38.420544 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 20:16:38.420931 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 20:16:38.422024 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 20:16:38.422396 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 20:16:38.423461 runner path: /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/0/tests/0_sleep test_uuid 12928123_1.5.2.3.1
181 20:16:38.423593 sleep_params='mem'
182 20:16:38.423809 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 20:16:38.424167 Creating lava-test-runner.conf files
185 20:16:38.424276 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928123/lava-overlay-euijye5h/lava-12928123/0 for stage 0
186 20:16:38.424426 - 0_sleep
187 20:16:38.424591 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 20:16:38.424717 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 20:16:38.578387 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 20:16:38.578555 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 20:16:38.578666 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 20:16:38.578768 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 20:16:38.578871 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 20:16:41.212952 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 20:16:41.213407 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 20:16:41.213541 extracting modules file /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928123/extract-overlay-ramdisk-moacdzhz/ramdisk
197 20:16:41.464729 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 20:16:41.464894 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 20:16:41.464983 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928123/compress-overlay-c1auna50/overlay-1.5.2.4.tar.gz to ramdisk
200 20:16:41.465053 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928123/compress-overlay-c1auna50/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928123/extract-overlay-ramdisk-moacdzhz/ramdisk
201 20:16:41.576130 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 20:16:41.576297 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 20:16:41.576397 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 20:16:41.576486 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 20:16:41.576570 Building ramdisk /var/lib/lava/dispatcher/tmp/12928123/extract-overlay-ramdisk-moacdzhz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928123/extract-overlay-ramdisk-moacdzhz/ramdisk
206 20:16:43.258988 >> 563791 blocks
207 20:16:53.593201 rename /var/lib/lava/dispatcher/tmp/12928123/extract-overlay-ramdisk-moacdzhz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/ramdisk/ramdisk.cpio.gz
208 20:16:53.593683 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 20:16:53.593865 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 20:16:53.594003 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 20:16:53.594169 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/kernel/Image'
212 20:17:07.156058 Returned 0 in 13 seconds
213 20:17:07.256683 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/kernel/image.itb
214 20:17:08.641668 output: FIT description: Kernel Image image with one or more FDT blobs
215 20:17:08.642057 output: Created: Sun Mar 3 20:17:08 2024
216 20:17:08.642133 output: Image 0 (kernel-1)
217 20:17:08.642198 output: Description:
218 20:17:08.642260 output: Created: Sun Mar 3 20:17:08 2024
219 20:17:08.642320 output: Type: Kernel Image
220 20:17:08.642380 output: Compression: lzma compressed
221 20:17:08.642439 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
222 20:17:08.642498 output: Architecture: AArch64
223 20:17:08.642555 output: OS: Linux
224 20:17:08.642615 output: Load Address: 0x00000000
225 20:17:08.642675 output: Entry Point: 0x00000000
226 20:17:08.642733 output: Hash algo: crc32
227 20:17:08.642796 output: Hash value: 91cb1a17
228 20:17:08.642854 output: Image 1 (fdt-1)
229 20:17:08.642912 output: Description: mt8192-asurada-spherion-r0
230 20:17:08.642965 output: Created: Sun Mar 3 20:17:08 2024
231 20:17:08.643019 output: Type: Flat Device Tree
232 20:17:08.643071 output: Compression: uncompressed
233 20:17:08.643124 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 20:17:08.643177 output: Architecture: AArch64
235 20:17:08.643229 output: Hash algo: crc32
236 20:17:08.643282 output: Hash value: cc4352de
237 20:17:08.643352 output: Image 2 (ramdisk-1)
238 20:17:08.643407 output: Description: unavailable
239 20:17:08.643460 output: Created: Sun Mar 3 20:17:08 2024
240 20:17:08.643514 output: Type: RAMDisk Image
241 20:17:08.643567 output: Compression: Unknown Compression
242 20:17:08.643620 output: Data Size: 98363737 Bytes = 96058.34 KiB = 93.81 MiB
243 20:17:08.643673 output: Architecture: AArch64
244 20:17:08.643726 output: OS: Linux
245 20:17:08.643779 output: Load Address: unavailable
246 20:17:08.643832 output: Entry Point: unavailable
247 20:17:08.643885 output: Hash algo: crc32
248 20:17:08.643938 output: Hash value: 05f7b382
249 20:17:08.643991 output: Default Configuration: 'conf-1'
250 20:17:08.644044 output: Configuration 0 (conf-1)
251 20:17:08.644097 output: Description: mt8192-asurada-spherion-r0
252 20:17:08.644150 output: Kernel: kernel-1
253 20:17:08.644203 output: Init Ramdisk: ramdisk-1
254 20:17:08.644255 output: FDT: fdt-1
255 20:17:08.644320 output: Loadables: kernel-1
256 20:17:08.644375 output:
257 20:17:08.644581 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 20:17:08.644680 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 20:17:08.644783 end: 1.5 prepare-tftp-overlay (duration 00:00:31) [common]
260 20:17:08.644877 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 20:17:08.644961 No LXC device requested
262 20:17:08.645041 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 20:17:08.645125 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 20:17:08.645202 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 20:17:08.645270 Checking files for TFTP limit of 4294967296 bytes.
266 20:17:08.645779 end: 1 tftp-deploy (duration 00:00:32) [common]
267 20:17:08.645885 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 20:17:08.645982 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 20:17:08.646109 substitutions:
270 20:17:08.646182 - {DTB}: 12928123/tftp-deploy-6815w_fp/dtb/mt8192-asurada-spherion-r0.dtb
271 20:17:08.646249 - {INITRD}: 12928123/tftp-deploy-6815w_fp/ramdisk/ramdisk.cpio.gz
272 20:17:08.646309 - {KERNEL}: 12928123/tftp-deploy-6815w_fp/kernel/Image
273 20:17:08.646367 - {LAVA_MAC}: None
274 20:17:08.646424 - {PRESEED_CONFIG}: None
275 20:17:08.646480 - {PRESEED_LOCAL}: None
276 20:17:08.646536 - {RAMDISK}: 12928123/tftp-deploy-6815w_fp/ramdisk/ramdisk.cpio.gz
277 20:17:08.646593 - {ROOT_PART}: None
278 20:17:08.646648 - {ROOT}: None
279 20:17:08.646704 - {SERVER_IP}: 192.168.201.1
280 20:17:08.646759 - {TEE}: None
281 20:17:08.646814 Parsed boot commands:
282 20:17:08.646870 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 20:17:08.647052 Parsed boot commands: tftpboot 192.168.201.1 12928123/tftp-deploy-6815w_fp/kernel/image.itb 12928123/tftp-deploy-6815w_fp/kernel/cmdline
284 20:17:08.647146 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 20:17:08.647231 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 20:17:08.647322 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 20:17:08.647411 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 20:17:08.647484 Not connected, no need to disconnect.
289 20:17:08.647558 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 20:17:08.647637 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 20:17:08.647705 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 20:17:08.651990 Setting prompt string to ['lava-test: # ']
293 20:17:08.652395 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 20:17:08.652530 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 20:17:08.652661 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 20:17:08.652784 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 20:17:08.653131 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 20:17:13.786780 >> Command sent successfully.
299 20:17:13.790237 Returned 0 in 5 seconds
300 20:17:13.890637 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 20:17:13.891083 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 20:17:13.891209 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 20:17:13.891314 Setting prompt string to 'Starting depthcharge on Spherion...'
305 20:17:13.891383 Changing prompt to 'Starting depthcharge on Spherion...'
306 20:17:13.891449 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 20:17:13.891731 [Enter `^Ec?' for help]
308 20:17:14.060818
309 20:17:14.060969
310 20:17:14.061039 F0: 102B 0000
311 20:17:14.061107
312 20:17:14.064336 F3: 1001 0000 [0200]
313 20:17:14.064423
314 20:17:14.064490 F3: 1001 0000
315 20:17:14.064552
316 20:17:14.064611 F7: 102D 0000
317 20:17:14.064669
318 20:17:14.067543 F1: 0000 0000
319 20:17:14.067627
320 20:17:14.067693 V0: 0000 0000 [0001]
321 20:17:14.067759
322 20:17:14.070637 00: 0007 8000
323 20:17:14.070724
324 20:17:14.070791 01: 0000 0000
325 20:17:14.070854
326 20:17:14.074365 BP: 0C00 0209 [0000]
327 20:17:14.074448
328 20:17:14.074514 G0: 1182 0000
329 20:17:14.074576
330 20:17:14.077526 EC: 0000 0021 [4000]
331 20:17:14.077609
332 20:17:14.077675 S7: 0000 0000 [0000]
333 20:17:14.077736
334 20:17:14.081388 CC: 0000 0000 [0001]
335 20:17:14.081470
336 20:17:14.081536 T0: 0000 0040 [010F]
337 20:17:14.081597
338 20:17:14.084389 Jump to BL
339 20:17:14.084472
340 20:17:14.108154
341 20:17:14.108239
342 20:17:14.108344
343 20:17:14.116218 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 20:17:14.119703 ARM64: Exception handlers installed.
345 20:17:14.123732 ARM64: Testing exception
346 20:17:14.123861 ARM64: Done test exception
347 20:17:14.133211 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 20:17:14.143240 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 20:17:14.150444 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 20:17:14.160161 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 20:17:14.167014 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 20:17:14.173571 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 20:17:14.184795 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 20:17:14.191682 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 20:17:14.210910 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 20:17:14.214413 WDT: Last reset was cold boot
357 20:17:14.217599 SPI1(PAD0) initialized at 2873684 Hz
358 20:17:14.220788 SPI5(PAD0) initialized at 992727 Hz
359 20:17:14.224463 VBOOT: Loading verstage.
360 20:17:14.230671 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 20:17:14.235068 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 20:17:14.238293 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 20:17:14.241399 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 20:17:14.248241 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 20:17:14.255153 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 20:17:14.265965 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 20:17:14.266049
368 20:17:14.266114
369 20:17:14.276537 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 20:17:14.279650 ARM64: Exception handlers installed.
371 20:17:14.283041 ARM64: Testing exception
372 20:17:14.283124 ARM64: Done test exception
373 20:17:14.289730 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 20:17:14.293040 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 20:17:14.306940 Probing TPM: . done!
376 20:17:14.307023 TPM ready after 0 ms
377 20:17:14.314944 Connected to device vid:did:rid of 1ae0:0028:00
378 20:17:14.321635 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 20:17:14.381550 Initialized TPM device CR50 revision 0
380 20:17:14.391156 tlcl_send_startup: Startup return code is 0
381 20:17:14.391243 TPM: setup succeeded
382 20:17:14.403264 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 20:17:14.412023 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 20:17:14.425170 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 20:17:14.432884 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 20:17:14.435708 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 20:17:14.440282 in-header: 03 07 00 00 08 00 00 00
388 20:17:14.444177 in-data: aa e4 47 04 13 02 00 00
389 20:17:14.447932 Chrome EC: UHEPI supported
390 20:17:14.455398 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 20:17:14.458587 in-header: 03 95 00 00 08 00 00 00
392 20:17:14.462765 in-data: 18 20 20 08 00 00 00 00
393 20:17:14.462848 Phase 1
394 20:17:14.466590 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 20:17:14.470424 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 20:17:14.477190 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 20:17:14.481115 Recovery requested (1009000e)
398 20:17:14.491780 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 20:17:14.495272 tlcl_extend: response is 0
400 20:17:14.504380 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 20:17:14.509181 tlcl_extend: response is 0
402 20:17:14.516582 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 20:17:14.536443 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 20:17:14.543030 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 20:17:14.543115
406 20:17:14.543180
407 20:17:14.553018 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 20:17:14.556619 ARM64: Exception handlers installed.
409 20:17:14.559988 ARM64: Testing exception
410 20:17:14.560071 ARM64: Done test exception
411 20:17:14.581954 pmic_efuse_setting: Set efuses in 11 msecs
412 20:17:14.585154 pmwrap_interface_init: Select PMIF_VLD_RDY
413 20:17:14.591717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 20:17:14.595398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 20:17:14.603140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 20:17:14.606518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 20:17:14.610075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 20:17:14.613843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 20:17:14.621860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 20:17:14.625348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 20:17:14.629597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 20:17:14.633329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 20:17:14.640559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 20:17:14.644326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 20:17:14.648749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 20:17:14.656174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 20:17:14.660014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 20:17:14.667055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 20:17:14.670481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 20:17:14.678210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 20:17:14.681543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 20:17:14.689117 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 20:17:14.692480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 20:17:14.700135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 20:17:14.704130 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 20:17:14.711056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 20:17:14.714662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 20:17:14.721774 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 20:17:14.725207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 20:17:14.732893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 20:17:14.736553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 20:17:14.739966 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 20:17:14.747600 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 20:17:14.750810 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 20:17:14.754652 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 20:17:14.762297 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 20:17:14.766054 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 20:17:14.769361 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 20:17:14.777241 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 20:17:14.781061 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 20:17:14.784850 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 20:17:14.788741 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 20:17:14.795606 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 20:17:14.799493 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 20:17:14.802844 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 20:17:14.806611 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 20:17:14.810278 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 20:17:14.817771 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 20:17:14.821452 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 20:17:14.825458 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 20:17:14.828679 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 20:17:14.832028 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 20:17:14.835903 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 20:17:14.846864 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 20:17:14.854120 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 20:17:14.858024 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 20:17:14.864929 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 20:17:14.876233 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 20:17:14.879543 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 20:17:14.883481 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 20:17:14.886603 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 20:17:14.895398 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
473 20:17:14.898565 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 20:17:14.906945 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 20:17:14.910431 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 20:17:14.919617 [RTC]rtc_get_frequency_meter,154: input=15, output=758
477 20:17:14.929068 [RTC]rtc_get_frequency_meter,154: input=23, output=941
478 20:17:14.938357 [RTC]rtc_get_frequency_meter,154: input=19, output=851
479 20:17:14.948694 [RTC]rtc_get_frequency_meter,154: input=17, output=803
480 20:17:14.957764 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 20:17:14.967224 [RTC]rtc_get_frequency_meter,154: input=16, output=781
482 20:17:14.976842 [RTC]rtc_get_frequency_meter,154: input=17, output=804
483 20:17:14.980565 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 20:17:14.984217 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 20:17:14.988107 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 20:17:14.995328 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
487 20:17:14.999042 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 20:17:15.002835 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
489 20:17:15.006552 ADC[4]: Raw value=905834 ID=7
490 20:17:15.006638 ADC[3]: Raw value=213441 ID=1
491 20:17:15.010764 RAM Code: 0x71
492 20:17:15.014975 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 20:17:15.018691 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 20:17:15.026250 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 20:17:15.033349 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 20:17:15.037113 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 20:17:15.040886 in-header: 03 07 00 00 08 00 00 00
498 20:17:15.044636 in-data: aa e4 47 04 13 02 00 00
499 20:17:15.048220 Chrome EC: UHEPI supported
500 20:17:15.054861 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 20:17:15.058621 in-header: 03 95 00 00 08 00 00 00
502 20:17:15.062859 in-data: 18 20 20 08 00 00 00 00
503 20:17:15.062943 MRC: failed to locate region type 0.
504 20:17:15.070181 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 20:17:15.073726 DRAM-K: Running full calibration
506 20:17:15.081038 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 20:17:15.081167 header.status = 0x0
508 20:17:15.084798 header.version = 0x6 (expected: 0x6)
509 20:17:15.088331 header.size = 0xd00 (expected: 0xd00)
510 20:17:15.088440 header.flags = 0x0
511 20:17:15.095804 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 20:17:15.114876 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
513 20:17:15.122691 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 20:17:15.122783 dram_init: ddr_geometry: 2
515 20:17:15.126924 [EMI] MDL number = 2
516 20:17:15.127013 [EMI] Get MDL freq = 0
517 20:17:15.130868 dram_init: ddr_type: 0
518 20:17:15.130958 is_discrete_lpddr4: 1
519 20:17:15.134814 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 20:17:15.134902
521 20:17:15.134991
522 20:17:15.137938 [Bian_co] ETT version 0.0.0.1
523 20:17:15.141780 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 20:17:15.141869
525 20:17:15.145689 dramc_set_vcore_voltage set vcore to 650000
526 20:17:15.148974 Read voltage for 800, 4
527 20:17:15.149063 Vio18 = 0
528 20:17:15.153349 Vcore = 650000
529 20:17:15.153437 Vdram = 0
530 20:17:15.153526 Vddq = 0
531 20:17:15.153611 Vmddr = 0
532 20:17:15.156997 dram_init: config_dvfs: 1
533 20:17:15.160578 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 20:17:15.168312 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 20:17:15.172062 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 20:17:15.175872 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 20:17:15.179053 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 20:17:15.182889 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 20:17:15.182977 MEM_TYPE=3, freq_sel=18
540 20:17:15.186958 sv_algorithm_assistance_LP4_1600
541 20:17:15.190399 ============ PULL DRAM RESETB DOWN ============
542 20:17:15.196912 ========== PULL DRAM RESETB DOWN end =========
543 20:17:15.200785 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 20:17:15.204443 ===================================
545 20:17:15.204532 LPDDR4 DRAM CONFIGURATION
546 20:17:15.208421 ===================================
547 20:17:15.211614 EX_ROW_EN[0] = 0x0
548 20:17:15.211702 EX_ROW_EN[1] = 0x0
549 20:17:15.215605 LP4Y_EN = 0x0
550 20:17:15.215693 WORK_FSP = 0x0
551 20:17:15.218819 WL = 0x2
552 20:17:15.218897 RL = 0x2
553 20:17:15.222632 BL = 0x2
554 20:17:15.222746 RPST = 0x0
555 20:17:15.225986 RD_PRE = 0x0
556 20:17:15.226072 WR_PRE = 0x1
557 20:17:15.229436 WR_PST = 0x0
558 20:17:15.229524 DBI_WR = 0x0
559 20:17:15.232585 DBI_RD = 0x0
560 20:17:15.232671 OTF = 0x1
561 20:17:15.236179 ===================================
562 20:17:15.239229 ===================================
563 20:17:15.242594 ANA top config
564 20:17:15.245887 ===================================
565 20:17:15.245974 DLL_ASYNC_EN = 0
566 20:17:15.249660 ALL_SLAVE_EN = 1
567 20:17:15.252771 NEW_RANK_MODE = 1
568 20:17:15.255847 DLL_IDLE_MODE = 1
569 20:17:15.259659 LP45_APHY_COMB_EN = 1
570 20:17:15.259746 TX_ODT_DIS = 1
571 20:17:15.262878 NEW_8X_MODE = 1
572 20:17:15.266464 ===================================
573 20:17:15.269748 ===================================
574 20:17:15.273481 data_rate = 1600
575 20:17:15.276996 CKR = 1
576 20:17:15.277084 DQ_P2S_RATIO = 8
577 20:17:15.280247 ===================================
578 20:17:15.283213 CA_P2S_RATIO = 8
579 20:17:15.286749 DQ_CA_OPEN = 0
580 20:17:15.290363 DQ_SEMI_OPEN = 0
581 20:17:15.293592 CA_SEMI_OPEN = 0
582 20:17:15.293678 CA_FULL_RATE = 0
583 20:17:15.297256 DQ_CKDIV4_EN = 1
584 20:17:15.300661 CA_CKDIV4_EN = 1
585 20:17:15.303558 CA_PREDIV_EN = 0
586 20:17:15.306759 PH8_DLY = 0
587 20:17:15.310450 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 20:17:15.310536 DQ_AAMCK_DIV = 4
589 20:17:15.313882 CA_AAMCK_DIV = 4
590 20:17:15.316892 CA_ADMCK_DIV = 4
591 20:17:15.320463 DQ_TRACK_CA_EN = 0
592 20:17:15.323496 CA_PICK = 800
593 20:17:15.326827 CA_MCKIO = 800
594 20:17:15.326938 MCKIO_SEMI = 0
595 20:17:15.330191 PLL_FREQ = 3068
596 20:17:15.334284 DQ_UI_PI_RATIO = 32
597 20:17:15.338282 CA_UI_PI_RATIO = 0
598 20:17:15.341493 ===================================
599 20:17:15.345599 ===================================
600 20:17:15.345727 memory_type:LPDDR4
601 20:17:15.348818 GP_NUM : 10
602 20:17:15.348941 SRAM_EN : 1
603 20:17:15.352632 MD32_EN : 0
604 20:17:15.356167 ===================================
605 20:17:15.356321 [ANA_INIT] >>>>>>>>>>>>>>
606 20:17:15.360267 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 20:17:15.363641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 20:17:15.368190 ===================================
609 20:17:15.371066 data_rate = 1600,PCW = 0X7600
610 20:17:15.374198 ===================================
611 20:17:15.377866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 20:17:15.381035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 20:17:15.387894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 20:17:15.391123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 20:17:15.394294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 20:17:15.401245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 20:17:15.401332 [ANA_INIT] flow start
618 20:17:15.404184 [ANA_INIT] PLL >>>>>>>>
619 20:17:15.404270 [ANA_INIT] PLL <<<<<<<<
620 20:17:15.407767 [ANA_INIT] MIDPI >>>>>>>>
621 20:17:15.410736 [ANA_INIT] MIDPI <<<<<<<<
622 20:17:15.414321 [ANA_INIT] DLL >>>>>>>>
623 20:17:15.414407 [ANA_INIT] flow end
624 20:17:15.417472 ============ LP4 DIFF to SE enter ============
625 20:17:15.424278 ============ LP4 DIFF to SE exit ============
626 20:17:15.424399 [ANA_INIT] <<<<<<<<<<<<<
627 20:17:15.427948 [Flow] Enable top DCM control >>>>>
628 20:17:15.430965 [Flow] Enable top DCM control <<<<<
629 20:17:15.433970 Enable DLL master slave shuffle
630 20:17:15.441035 ==============================================================
631 20:17:15.441122 Gating Mode config
632 20:17:15.447775 ==============================================================
633 20:17:15.451226 Config description:
634 20:17:15.457556 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 20:17:15.464836 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 20:17:15.471420 SELPH_MODE 0: By rank 1: By Phase
637 20:17:15.478087 ==============================================================
638 20:17:15.478174 GAT_TRACK_EN = 1
639 20:17:15.481310 RX_GATING_MODE = 2
640 20:17:15.484311 RX_GATING_TRACK_MODE = 2
641 20:17:15.488124 SELPH_MODE = 1
642 20:17:15.491493 PICG_EARLY_EN = 1
643 20:17:15.494392 VALID_LAT_VALUE = 1
644 20:17:15.501164 ==============================================================
645 20:17:15.504937 Enter into Gating configuration >>>>
646 20:17:15.508054 Exit from Gating configuration <<<<
647 20:17:15.511607 Enter into DVFS_PRE_config >>>>>
648 20:17:15.521336 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 20:17:15.525086 Exit from DVFS_PRE_config <<<<<
650 20:17:15.528164 Enter into PICG configuration >>>>
651 20:17:15.531319 Exit from PICG configuration <<<<
652 20:17:15.531402 [RX_INPUT] configuration >>>>>
653 20:17:15.534816 [RX_INPUT] configuration <<<<<
654 20:17:15.541643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 20:17:15.544750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 20:17:15.552014 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 20:17:15.558189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 20:17:15.564956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 20:17:15.571832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 20:17:15.574884 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 20:17:15.578363 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 20:17:15.581351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 20:17:15.588137 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 20:17:15.591442 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 20:17:15.594905 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 20:17:15.598299 ===================================
667 20:17:15.601890 LPDDR4 DRAM CONFIGURATION
668 20:17:15.605172 ===================================
669 20:17:15.608133 EX_ROW_EN[0] = 0x0
670 20:17:15.608218 EX_ROW_EN[1] = 0x0
671 20:17:15.611633 LP4Y_EN = 0x0
672 20:17:15.611759 WORK_FSP = 0x0
673 20:17:15.615216 WL = 0x2
674 20:17:15.615300 RL = 0x2
675 20:17:15.618508 BL = 0x2
676 20:17:15.618592 RPST = 0x0
677 20:17:15.621767 RD_PRE = 0x0
678 20:17:15.621871 WR_PRE = 0x1
679 20:17:15.625327 WR_PST = 0x0
680 20:17:15.625411 DBI_WR = 0x0
681 20:17:15.628144 DBI_RD = 0x0
682 20:17:15.628230 OTF = 0x1
683 20:17:15.631438 ===================================
684 20:17:15.635283 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 20:17:15.641575 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 20:17:15.645209 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 20:17:15.648185 ===================================
688 20:17:15.652038 LPDDR4 DRAM CONFIGURATION
689 20:17:15.655105 ===================================
690 20:17:15.655190 EX_ROW_EN[0] = 0x10
691 20:17:15.658785 EX_ROW_EN[1] = 0x0
692 20:17:15.662055 LP4Y_EN = 0x0
693 20:17:15.662139 WORK_FSP = 0x0
694 20:17:15.665223 WL = 0x2
695 20:17:15.665306 RL = 0x2
696 20:17:15.668253 BL = 0x2
697 20:17:15.668389 RPST = 0x0
698 20:17:15.671498 RD_PRE = 0x0
699 20:17:15.671581 WR_PRE = 0x1
700 20:17:15.675179 WR_PST = 0x0
701 20:17:15.675295 DBI_WR = 0x0
702 20:17:15.678168 DBI_RD = 0x0
703 20:17:15.678251 OTF = 0x1
704 20:17:15.681928 ===================================
705 20:17:15.688123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 20:17:15.692253 nWR fixed to 40
707 20:17:15.695809 [ModeRegInit_LP4] CH0 RK0
708 20:17:15.695920 [ModeRegInit_LP4] CH0 RK1
709 20:17:15.698965 [ModeRegInit_LP4] CH1 RK0
710 20:17:15.702502 [ModeRegInit_LP4] CH1 RK1
711 20:17:15.702615 match AC timing 13
712 20:17:15.708931 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 20:17:15.712581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 20:17:15.715819 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 20:17:15.722409 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 20:17:15.726230 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 20:17:15.726314 [EMI DOE] emi_dcm 0
718 20:17:15.732469 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 20:17:15.732553 ==
720 20:17:15.735966 Dram Type= 6, Freq= 0, CH_0, rank 0
721 20:17:15.739486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 20:17:15.739607 ==
723 20:17:15.745775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 20:17:15.749277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 20:17:15.759496 [CA 0] Center 36 (6~67) winsize 62
726 20:17:15.762844 [CA 1] Center 36 (6~67) winsize 62
727 20:17:15.766608 [CA 2] Center 34 (4~65) winsize 62
728 20:17:15.769787 [CA 3] Center 33 (3~64) winsize 62
729 20:17:15.772891 [CA 4] Center 33 (3~64) winsize 62
730 20:17:15.776687 [CA 5] Center 32 (2~62) winsize 61
731 20:17:15.776772
732 20:17:15.780000 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 20:17:15.780085
734 20:17:15.783160 [CATrainingPosCal] consider 1 rank data
735 20:17:15.786399 u2DelayCellTimex100 = 270/100 ps
736 20:17:15.789538 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 20:17:15.793054 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 20:17:15.799694 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 20:17:15.803298 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 20:17:15.806222 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
741 20:17:15.809844 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
742 20:17:15.809969
743 20:17:15.812973 CA PerBit enable=1, Macro0, CA PI delay=32
744 20:17:15.813097
745 20:17:15.816542 [CBTSetCACLKResult] CA Dly = 32
746 20:17:15.816666 CS Dly: 5 (0~36)
747 20:17:15.816781 ==
748 20:17:15.819554 Dram Type= 6, Freq= 0, CH_0, rank 1
749 20:17:15.826461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 20:17:15.826587 ==
751 20:17:15.829615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 20:17:15.836418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 20:17:15.846277 [CA 0] Center 36 (6~67) winsize 62
754 20:17:15.849181 [CA 1] Center 36 (6~67) winsize 62
755 20:17:15.852809 [CA 2] Center 34 (4~65) winsize 62
756 20:17:15.856169 [CA 3] Center 33 (3~64) winsize 62
757 20:17:15.859482 [CA 4] Center 32 (2~63) winsize 62
758 20:17:15.862496 [CA 5] Center 32 (2~63) winsize 62
759 20:17:15.862578
760 20:17:15.866014 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 20:17:15.866097
762 20:17:15.869161 [CATrainingPosCal] consider 2 rank data
763 20:17:15.872580 u2DelayCellTimex100 = 270/100 ps
764 20:17:15.875914 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 20:17:15.879301 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 20:17:15.886115 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 20:17:15.889317 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 20:17:15.892408 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 20:17:15.896158 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
770 20:17:15.896297
771 20:17:15.899230 CA PerBit enable=1, Macro0, CA PI delay=32
772 20:17:15.899312
773 20:17:15.902923 [CBTSetCACLKResult] CA Dly = 32
774 20:17:15.903006 CS Dly: 5 (0~37)
775 20:17:15.903072
776 20:17:15.905765 ----->DramcWriteLeveling(PI) begin...
777 20:17:15.909533 ==
778 20:17:15.909616 Dram Type= 6, Freq= 0, CH_0, rank 0
779 20:17:15.916710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 20:17:15.916794 ==
781 20:17:15.920197 Write leveling (Byte 0): 33 => 33
782 20:17:15.920328 Write leveling (Byte 1): 30 => 30
783 20:17:15.924383 DramcWriteLeveling(PI) end<-----
784 20:17:15.924493
785 20:17:15.924586 ==
786 20:17:15.927573 Dram Type= 6, Freq= 0, CH_0, rank 0
787 20:17:15.931287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 20:17:15.931385 ==
789 20:17:15.934595 [Gating] SW mode calibration
790 20:17:15.941617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 20:17:15.948613 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 20:17:15.951474 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 20:17:15.955121 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 20:17:15.961701 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 20:17:15.965335 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 20:17:15.968419 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 20:17:15.975182 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 20:17:15.978387 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 20:17:15.981928 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 20:17:15.988155 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 20:17:15.991787 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 20:17:15.995123 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 20:17:15.998475 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 20:17:16.005245 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 20:17:16.008275 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 20:17:16.012036 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 20:17:16.018976 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 20:17:16.021666 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 20:17:16.025198 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 20:17:16.031730 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 20:17:16.035209 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 20:17:16.038793 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 20:17:16.045781 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 20:17:16.048748 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 20:17:16.051917 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 20:17:16.058595 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 20:17:16.062325 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 20:17:16.065243 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
819 20:17:16.072223 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
820 20:17:16.075376 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 20:17:16.078619 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 20:17:16.082289 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 20:17:16.088857 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 20:17:16.092583 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 20:17:16.095603 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
826 20:17:16.102483 0 10 8 | B1->B0 | 2f2f 2525 | 1 1 | (1 0) (1 0)
827 20:17:16.105516 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 20:17:16.109083 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 20:17:16.115775 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 20:17:16.118830 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 20:17:16.122245 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 20:17:16.128753 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 20:17:16.132585 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
834 20:17:16.135528 0 11 8 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (0 0)
835 20:17:16.142245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 20:17:16.145621 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 20:17:16.149212 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 20:17:16.152045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 20:17:16.159012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 20:17:16.162074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 20:17:16.165714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 20:17:16.172141 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
843 20:17:16.175845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 20:17:16.178784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 20:17:16.185740 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 20:17:16.188734 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 20:17:16.192491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 20:17:16.199316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 20:17:16.202460 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 20:17:16.205525 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 20:17:16.212468 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 20:17:16.215461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 20:17:16.219146 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 20:17:16.225458 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 20:17:16.228988 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 20:17:16.232296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 20:17:16.235536 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 20:17:16.242499 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 20:17:16.245588 Total UI for P1: 0, mck2ui 16
860 20:17:16.249191 best dqsien dly found for B0: ( 0, 14, 4)
861 20:17:16.252057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 20:17:16.255633 Total UI for P1: 0, mck2ui 16
863 20:17:16.259270 best dqsien dly found for B1: ( 0, 14, 8)
864 20:17:16.262770 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
865 20:17:16.266055 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 20:17:16.266138
867 20:17:16.269659 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
868 20:17:16.273209 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 20:17:16.276249 [Gating] SW calibration Done
870 20:17:16.276350 ==
871 20:17:16.279775 Dram Type= 6, Freq= 0, CH_0, rank 0
872 20:17:16.283244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 20:17:16.283329 ==
874 20:17:16.286377 RX Vref Scan: 0
875 20:17:16.286460
876 20:17:16.289533 RX Vref 0 -> 0, step: 1
877 20:17:16.289617
878 20:17:16.289683 RX Delay -130 -> 252, step: 16
879 20:17:16.296093 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 20:17:16.299345 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 20:17:16.303017 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 20:17:16.306155 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 20:17:16.309278 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 20:17:16.316413 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 20:17:16.319597 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
886 20:17:16.323403 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 20:17:16.326375 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 20:17:16.330078 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
889 20:17:16.336228 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 20:17:16.339995 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 20:17:16.342987 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 20:17:16.346372 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 20:17:16.349981 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 20:17:16.356213 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
895 20:17:16.356339 ==
896 20:17:16.359804 Dram Type= 6, Freq= 0, CH_0, rank 0
897 20:17:16.362960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 20:17:16.363073 ==
899 20:17:16.363171 DQS Delay:
900 20:17:16.366331 DQS0 = 0, DQS1 = 0
901 20:17:16.366421 DQM Delay:
902 20:17:16.369717 DQM0 = 90, DQM1 = 85
903 20:17:16.369843 DQ Delay:
904 20:17:16.373096 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
905 20:17:16.376456 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
906 20:17:16.379832 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
907 20:17:16.383263 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
908 20:17:16.383371
909 20:17:16.383466
910 20:17:16.383556 ==
911 20:17:16.386413 Dram Type= 6, Freq= 0, CH_0, rank 0
912 20:17:16.389973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 20:17:16.390058 ==
914 20:17:16.390144
915 20:17:16.390237
916 20:17:16.393030 TX Vref Scan disable
917 20:17:16.396822 == TX Byte 0 ==
918 20:17:16.399871 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
919 20:17:16.403104 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
920 20:17:16.406348 == TX Byte 1 ==
921 20:17:16.409642 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
922 20:17:16.413383 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
923 20:17:16.413461 ==
924 20:17:16.416534 Dram Type= 6, Freq= 0, CH_0, rank 0
925 20:17:16.423392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 20:17:16.423479 ==
927 20:17:16.434842 TX Vref=22, minBit 3, minWin=27, winSum=443
928 20:17:16.438458 TX Vref=24, minBit 8, minWin=27, winSum=451
929 20:17:16.441612 TX Vref=26, minBit 10, minWin=27, winSum=454
930 20:17:16.444819 TX Vref=28, minBit 8, minWin=28, winSum=458
931 20:17:16.448048 TX Vref=30, minBit 0, minWin=28, winSum=456
932 20:17:16.455068 TX Vref=32, minBit 10, minWin=27, winSum=452
933 20:17:16.458058 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
934 20:17:16.458164
935 20:17:16.461631 Final TX Range 1 Vref 28
936 20:17:16.461735
937 20:17:16.461838 ==
938 20:17:16.465136 Dram Type= 6, Freq= 0, CH_0, rank 0
939 20:17:16.468349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 20:17:16.468428 ==
941 20:17:16.471709
942 20:17:16.471785
943 20:17:16.471886 TX Vref Scan disable
944 20:17:16.475224 == TX Byte 0 ==
945 20:17:16.478361 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
946 20:17:16.485160 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
947 20:17:16.485249 == TX Byte 1 ==
948 20:17:16.488332 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 20:17:16.491756 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 20:17:16.495081
951 20:17:16.495196 [DATLAT]
952 20:17:16.495295 Freq=800, CH0 RK0
953 20:17:16.495389
954 20:17:16.498403 DATLAT Default: 0xa
955 20:17:16.498503 0, 0xFFFF, sum = 0
956 20:17:16.502041 1, 0xFFFF, sum = 0
957 20:17:16.502129 2, 0xFFFF, sum = 0
958 20:17:16.505421 3, 0xFFFF, sum = 0
959 20:17:16.505508 4, 0xFFFF, sum = 0
960 20:17:16.508886 5, 0xFFFF, sum = 0
961 20:17:16.508972 6, 0xFFFF, sum = 0
962 20:17:16.511791 7, 0xFFFF, sum = 0
963 20:17:16.511878 8, 0xFFFF, sum = 0
964 20:17:16.515568 9, 0x0, sum = 1
965 20:17:16.515680 10, 0x0, sum = 2
966 20:17:16.518731 11, 0x0, sum = 3
967 20:17:16.518837 12, 0x0, sum = 4
968 20:17:16.521967 best_step = 10
969 20:17:16.522066
970 20:17:16.522157 ==
971 20:17:16.525116 Dram Type= 6, Freq= 0, CH_0, rank 0
972 20:17:16.528902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 20:17:16.529007 ==
974 20:17:16.532136 RX Vref Scan: 1
975 20:17:16.532239
976 20:17:16.532331 Set Vref Range= 32 -> 127
977 20:17:16.532394
978 20:17:16.535200 RX Vref 32 -> 127, step: 1
979 20:17:16.535297
980 20:17:16.538435 RX Delay -79 -> 252, step: 8
981 20:17:16.538546
982 20:17:16.542123 Set Vref, RX VrefLevel [Byte0]: 32
983 20:17:16.545372 [Byte1]: 32
984 20:17:16.545461
985 20:17:16.548582 Set Vref, RX VrefLevel [Byte0]: 33
986 20:17:16.552281 [Byte1]: 33
987 20:17:16.552374
988 20:17:16.555933 Set Vref, RX VrefLevel [Byte0]: 34
989 20:17:16.559029 [Byte1]: 34
990 20:17:16.562925
991 20:17:16.563010 Set Vref, RX VrefLevel [Byte0]: 35
992 20:17:16.566679 [Byte1]: 35
993 20:17:16.570540
994 20:17:16.570668 Set Vref, RX VrefLevel [Byte0]: 36
995 20:17:16.573760 [Byte1]: 36
996 20:17:16.578313
997 20:17:16.578426 Set Vref, RX VrefLevel [Byte0]: 37
998 20:17:16.581994 [Byte1]: 37
999 20:17:16.586193
1000 20:17:16.586278 Set Vref, RX VrefLevel [Byte0]: 38
1001 20:17:16.589738 [Byte1]: 38
1002 20:17:16.593594
1003 20:17:16.593709 Set Vref, RX VrefLevel [Byte0]: 39
1004 20:17:16.596636 [Byte1]: 39
1005 20:17:16.601249
1006 20:17:16.601343 Set Vref, RX VrefLevel [Byte0]: 40
1007 20:17:16.604266 [Byte1]: 40
1008 20:17:16.608569
1009 20:17:16.608695 Set Vref, RX VrefLevel [Byte0]: 41
1010 20:17:16.612080 [Byte1]: 41
1011 20:17:16.615893
1012 20:17:16.615971 Set Vref, RX VrefLevel [Byte0]: 42
1013 20:17:16.618958 [Byte1]: 42
1014 20:17:16.623381
1015 20:17:16.623487 Set Vref, RX VrefLevel [Byte0]: 43
1016 20:17:16.626503 [Byte1]: 43
1017 20:17:16.631059
1018 20:17:16.631175 Set Vref, RX VrefLevel [Byte0]: 44
1019 20:17:16.633901 [Byte1]: 44
1020 20:17:16.638405
1021 20:17:16.638513 Set Vref, RX VrefLevel [Byte0]: 45
1022 20:17:16.641529 [Byte1]: 45
1023 20:17:16.645697
1024 20:17:16.645781 Set Vref, RX VrefLevel [Byte0]: 46
1025 20:17:16.649337 [Byte1]: 46
1026 20:17:16.653742
1027 20:17:16.653825 Set Vref, RX VrefLevel [Byte0]: 47
1028 20:17:16.656762 [Byte1]: 47
1029 20:17:16.660963
1030 20:17:16.661072 Set Vref, RX VrefLevel [Byte0]: 48
1031 20:17:16.664250 [Byte1]: 48
1032 20:17:16.668665
1033 20:17:16.668747 Set Vref, RX VrefLevel [Byte0]: 49
1034 20:17:16.671835 [Byte1]: 49
1035 20:17:16.676185
1036 20:17:16.676303 Set Vref, RX VrefLevel [Byte0]: 50
1037 20:17:16.679366 [Byte1]: 50
1038 20:17:16.683913
1039 20:17:16.684023 Set Vref, RX VrefLevel [Byte0]: 51
1040 20:17:16.686915 [Byte1]: 51
1041 20:17:16.691060
1042 20:17:16.691172 Set Vref, RX VrefLevel [Byte0]: 52
1043 20:17:16.694562 [Byte1]: 52
1044 20:17:16.698584
1045 20:17:16.698691 Set Vref, RX VrefLevel [Byte0]: 53
1046 20:17:16.701913 [Byte1]: 53
1047 20:17:16.706438
1048 20:17:16.706552 Set Vref, RX VrefLevel [Byte0]: 54
1049 20:17:16.709582 [Byte1]: 54
1050 20:17:16.714041
1051 20:17:16.714154 Set Vref, RX VrefLevel [Byte0]: 55
1052 20:17:16.717234 [Byte1]: 55
1053 20:17:16.721532
1054 20:17:16.721646 Set Vref, RX VrefLevel [Byte0]: 56
1055 20:17:16.724556 [Byte1]: 56
1056 20:17:16.728725
1057 20:17:16.728834 Set Vref, RX VrefLevel [Byte0]: 57
1058 20:17:16.732189 [Byte1]: 57
1059 20:17:16.736268
1060 20:17:16.736382 Set Vref, RX VrefLevel [Byte0]: 58
1061 20:17:16.740035 [Byte1]: 58
1062 20:17:16.743940
1063 20:17:16.744049 Set Vref, RX VrefLevel [Byte0]: 59
1064 20:17:16.747208 [Byte1]: 59
1065 20:17:16.751409
1066 20:17:16.751519 Set Vref, RX VrefLevel [Byte0]: 60
1067 20:17:16.754810 [Byte1]: 60
1068 20:17:16.759135
1069 20:17:16.759220 Set Vref, RX VrefLevel [Byte0]: 61
1070 20:17:16.762825 [Byte1]: 61
1071 20:17:16.766523
1072 20:17:16.766607 Set Vref, RX VrefLevel [Byte0]: 62
1073 20:17:16.769850 [Byte1]: 62
1074 20:17:16.774469
1075 20:17:16.774553 Set Vref, RX VrefLevel [Byte0]: 63
1076 20:17:16.777558 [Byte1]: 63
1077 20:17:16.781896
1078 20:17:16.782005 Set Vref, RX VrefLevel [Byte0]: 64
1079 20:17:16.785037 [Byte1]: 64
1080 20:17:16.789511
1081 20:17:16.789621 Set Vref, RX VrefLevel [Byte0]: 65
1082 20:17:16.792448 [Byte1]: 65
1083 20:17:16.796646
1084 20:17:16.796759 Set Vref, RX VrefLevel [Byte0]: 66
1085 20:17:16.800178 [Byte1]: 66
1086 20:17:16.804234
1087 20:17:16.804326 Set Vref, RX VrefLevel [Byte0]: 67
1088 20:17:16.807818 [Byte1]: 67
1089 20:17:16.812191
1090 20:17:16.812275 Set Vref, RX VrefLevel [Byte0]: 68
1091 20:17:16.815499 [Byte1]: 68
1092 20:17:16.819565
1093 20:17:16.819649 Set Vref, RX VrefLevel [Byte0]: 69
1094 20:17:16.822661 [Byte1]: 69
1095 20:17:16.826999
1096 20:17:16.827083 Set Vref, RX VrefLevel [Byte0]: 70
1097 20:17:16.830183 [Byte1]: 70
1098 20:17:16.834626
1099 20:17:16.834710 Set Vref, RX VrefLevel [Byte0]: 71
1100 20:17:16.837738 [Byte1]: 71
1101 20:17:16.841897
1102 20:17:16.841980 Set Vref, RX VrefLevel [Byte0]: 72
1103 20:17:16.845597 [Byte1]: 72
1104 20:17:16.849729
1105 20:17:16.849813 Set Vref, RX VrefLevel [Byte0]: 73
1106 20:17:16.853000 [Byte1]: 73
1107 20:17:16.857169
1108 20:17:16.857253 Set Vref, RX VrefLevel [Byte0]: 74
1109 20:17:16.860712 [Byte1]: 74
1110 20:17:16.864691
1111 20:17:16.864775 Set Vref, RX VrefLevel [Byte0]: 75
1112 20:17:16.868453 [Byte1]: 75
1113 20:17:16.872814
1114 20:17:16.872898 Set Vref, RX VrefLevel [Byte0]: 76
1115 20:17:16.875931 [Byte1]: 76
1116 20:17:16.879781
1117 20:17:16.879865 Set Vref, RX VrefLevel [Byte0]: 77
1118 20:17:16.883517 [Byte1]: 77
1119 20:17:16.887714
1120 20:17:16.887797 Set Vref, RX VrefLevel [Byte0]: 78
1121 20:17:16.890761 [Byte1]: 78
1122 20:17:16.895204
1123 20:17:16.895288 Final RX Vref Byte 0 = 57 to rank0
1124 20:17:16.898238 Final RX Vref Byte 1 = 59 to rank0
1125 20:17:16.901877 Final RX Vref Byte 0 = 57 to rank1
1126 20:17:16.905449 Final RX Vref Byte 1 = 59 to rank1==
1127 20:17:16.908490 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 20:17:16.911818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 20:17:16.915158 ==
1130 20:17:16.915239 DQS Delay:
1131 20:17:16.915304 DQS0 = 0, DQS1 = 0
1132 20:17:16.918480 DQM Delay:
1133 20:17:16.918552 DQM0 = 91, DQM1 = 85
1134 20:17:16.921851 DQ Delay:
1135 20:17:16.925371 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1136 20:17:16.925442 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1137 20:17:16.928566 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1138 20:17:16.931614 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1139 20:17:16.934969
1140 20:17:16.935041
1141 20:17:16.941708 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1142 20:17:16.945423 CH0 RK0: MR19=606, MR18=4D44
1143 20:17:16.952011 CH0_RK0: MR19=0x606, MR18=0x4D44, DQSOSC=390, MR23=63, INC=97, DEC=64
1144 20:17:16.952090
1145 20:17:16.955077 ----->DramcWriteLeveling(PI) begin...
1146 20:17:16.955147 ==
1147 20:17:16.958700 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 20:17:16.961739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 20:17:16.961864 ==
1150 20:17:16.964863 Write leveling (Byte 0): 35 => 35
1151 20:17:16.968807 Write leveling (Byte 1): 31 => 31
1152 20:17:16.971655 DramcWriteLeveling(PI) end<-----
1153 20:17:16.971770
1154 20:17:16.971878 ==
1155 20:17:16.975550 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 20:17:16.978321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 20:17:16.978404 ==
1158 20:17:16.981863 [Gating] SW mode calibration
1159 20:17:17.026439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 20:17:17.026787 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 20:17:17.026888 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 20:17:17.026959 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 20:17:17.027070 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 20:17:17.027179 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 20:17:17.027306 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 20:17:17.027382 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 20:17:17.027522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 20:17:17.069884 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 20:17:17.070075 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 20:17:17.070203 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 20:17:17.070560 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 20:17:17.070702 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 20:17:17.070828 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 20:17:17.070939 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 20:17:17.071044 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 20:17:17.071165 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 20:17:17.071269 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 20:17:17.097971 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1179 20:17:17.098336 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1180 20:17:17.098457 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 20:17:17.098568 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 20:17:17.098692 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 20:17:17.098804 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 20:17:17.101768 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 20:17:17.105339 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 20:17:17.108646 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1187 20:17:17.111783 0 9 8 | B1->B0 | 2d2d 2525 | 1 1 | (0 0) (0 0)
1188 20:17:17.118377 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 20:17:17.121788 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 20:17:17.125378 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 20:17:17.128329 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 20:17:17.135682 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 20:17:17.138513 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 20:17:17.142122 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1195 20:17:17.148881 0 10 8 | B1->B0 | 2929 2727 | 1 1 | (1 1) (0 0)
1196 20:17:17.151938 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1197 20:17:17.155479 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 20:17:17.162937 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 20:17:17.166537 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 20:17:17.170319 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 20:17:17.173558 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 20:17:17.177225 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1203 20:17:17.184016 0 11 8 | B1->B0 | 4242 3434 | 0 0 | (1 1) (0 0)
1204 20:17:17.187741 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 20:17:17.191199 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 20:17:17.198034 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 20:17:17.201052 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 20:17:17.204595 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 20:17:17.207956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 20:17:17.214806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 20:17:17.217891 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 20:17:17.220898 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1213 20:17:17.227607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 20:17:17.231122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 20:17:17.234523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 20:17:17.241180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 20:17:17.244089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 20:17:17.247551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 20:17:17.254453 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 20:17:17.257583 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 20:17:17.261167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 20:17:17.267499 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 20:17:17.271127 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 20:17:17.274326 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 20:17:17.278237 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 20:17:17.284725 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 20:17:17.287910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 20:17:17.291631 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 20:17:17.294564 Total UI for P1: 0, mck2ui 16
1230 20:17:17.298373 best dqsien dly found for B0: ( 0, 14, 10)
1231 20:17:17.301612 Total UI for P1: 0, mck2ui 16
1232 20:17:17.304674 best dqsien dly found for B1: ( 0, 14, 10)
1233 20:17:17.307888 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1234 20:17:17.314552 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1235 20:17:17.314656
1236 20:17:17.318228 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1237 20:17:17.321360 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1238 20:17:17.324492 [Gating] SW calibration Done
1239 20:17:17.324568 ==
1240 20:17:17.327564 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 20:17:17.331267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1242 20:17:17.331368 ==
1243 20:17:17.331462 RX Vref Scan: 0
1244 20:17:17.334410
1245 20:17:17.334483 RX Vref 0 -> 0, step: 1
1246 20:17:17.334546
1247 20:17:17.338110 RX Delay -130 -> 252, step: 16
1248 20:17:17.341571 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1249 20:17:17.344725 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1250 20:17:17.350983 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1251 20:17:17.354541 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1252 20:17:17.357579 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1253 20:17:17.360978 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1254 20:17:17.364295 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1255 20:17:17.371244 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1256 20:17:17.374185 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1257 20:17:17.377947 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1258 20:17:17.381163 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1259 20:17:17.384353 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1260 20:17:17.391236 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1261 20:17:17.394521 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1262 20:17:17.397665 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1263 20:17:17.400800 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1264 20:17:17.400877 ==
1265 20:17:17.404314 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 20:17:17.411390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 20:17:17.411521 ==
1268 20:17:17.411639 DQS Delay:
1269 20:17:17.414621 DQS0 = 0, DQS1 = 0
1270 20:17:17.414733 DQM Delay:
1271 20:17:17.414827 DQM0 = 93, DQM1 = 84
1272 20:17:17.417760 DQ Delay:
1273 20:17:17.420772 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1274 20:17:17.424166 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1275 20:17:17.427931 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1276 20:17:17.431063 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1277 20:17:17.431169
1278 20:17:17.431260
1279 20:17:17.431350 ==
1280 20:17:17.434886 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 20:17:17.438140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 20:17:17.438215 ==
1283 20:17:17.438277
1284 20:17:17.438336
1285 20:17:17.441327 TX Vref Scan disable
1286 20:17:17.441423 == TX Byte 0 ==
1287 20:17:17.447680 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1288 20:17:17.451385 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1289 20:17:17.451462 == TX Byte 1 ==
1290 20:17:17.457835 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1291 20:17:17.461495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1292 20:17:17.461615 ==
1293 20:17:17.464694 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 20:17:17.467820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 20:17:17.467924 ==
1296 20:17:17.482129 TX Vref=22, minBit 9, minWin=27, winSum=449
1297 20:17:17.485738 TX Vref=24, minBit 1, minWin=28, winSum=451
1298 20:17:17.489063 TX Vref=26, minBit 1, minWin=28, winSum=457
1299 20:17:17.492141 TX Vref=28, minBit 1, minWin=28, winSum=457
1300 20:17:17.495262 TX Vref=30, minBit 7, minWin=28, winSum=455
1301 20:17:17.502241 TX Vref=32, minBit 10, minWin=27, winSum=452
1302 20:17:17.505329 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
1303 20:17:17.505434
1304 20:17:17.509036 Final TX Range 1 Vref 26
1305 20:17:17.509134
1306 20:17:17.509225 ==
1307 20:17:17.512489 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 20:17:17.515623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 20:17:17.515708 ==
1310 20:17:17.515775
1311 20:17:17.518718
1312 20:17:17.518801 TX Vref Scan disable
1313 20:17:17.522526 == TX Byte 0 ==
1314 20:17:17.525819 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1315 20:17:17.529217 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1316 20:17:17.532409 == TX Byte 1 ==
1317 20:17:17.536008 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1318 20:17:17.539078 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1319 20:17:17.539190
1320 20:17:17.542854 [DATLAT]
1321 20:17:17.542928 Freq=800, CH0 RK1
1322 20:17:17.542997
1323 20:17:17.545589 DATLAT Default: 0xa
1324 20:17:17.545665 0, 0xFFFF, sum = 0
1325 20:17:17.549393 1, 0xFFFF, sum = 0
1326 20:17:17.549499 2, 0xFFFF, sum = 0
1327 20:17:17.552454 3, 0xFFFF, sum = 0
1328 20:17:17.552571 4, 0xFFFF, sum = 0
1329 20:17:17.555582 5, 0xFFFF, sum = 0
1330 20:17:17.555690 6, 0xFFFF, sum = 0
1331 20:17:17.558945 7, 0xFFFF, sum = 0
1332 20:17:17.562376 8, 0xFFFF, sum = 0
1333 20:17:17.562488 9, 0x0, sum = 1
1334 20:17:17.562585 10, 0x0, sum = 2
1335 20:17:17.565963 11, 0x0, sum = 3
1336 20:17:17.566048 12, 0x0, sum = 4
1337 20:17:17.569445 best_step = 10
1338 20:17:17.569528
1339 20:17:17.569595 ==
1340 20:17:17.572594 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 20:17:17.575705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 20:17:17.575790 ==
1343 20:17:17.579383 RX Vref Scan: 0
1344 20:17:17.579466
1345 20:17:17.579531 RX Vref 0 -> 0, step: 1
1346 20:17:17.579592
1347 20:17:17.582442 RX Delay -95 -> 252, step: 8
1348 20:17:17.589353 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1349 20:17:17.592650 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1350 20:17:17.595993 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1351 20:17:17.599590 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1352 20:17:17.602413 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1353 20:17:17.606054 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1354 20:17:17.612349 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1355 20:17:17.616196 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1356 20:17:17.619190 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1357 20:17:17.622978 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1358 20:17:17.626196 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1359 20:17:17.632621 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1360 20:17:17.635585 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1361 20:17:17.639212 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1362 20:17:17.642493 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1363 20:17:17.649486 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1364 20:17:17.649565 ==
1365 20:17:17.652722 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 20:17:17.656260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 20:17:17.656377 ==
1368 20:17:17.656472 DQS Delay:
1369 20:17:17.659279 DQS0 = 0, DQS1 = 0
1370 20:17:17.659379 DQM Delay:
1371 20:17:17.662564 DQM0 = 93, DQM1 = 85
1372 20:17:17.662667 DQ Delay:
1373 20:17:17.665676 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1374 20:17:17.669620 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1375 20:17:17.672594 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76
1376 20:17:17.675670 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1377 20:17:17.675772
1378 20:17:17.675867
1379 20:17:17.682879 [DQSOSCAuto] RK1, (LSB)MR18= 0x4414, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1380 20:17:17.685741 CH0 RK1: MR19=606, MR18=4414
1381 20:17:17.692547 CH0_RK1: MR19=0x606, MR18=0x4414, DQSOSC=392, MR23=63, INC=96, DEC=64
1382 20:17:17.695641 [RxdqsGatingPostProcess] freq 800
1383 20:17:17.702567 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1384 20:17:17.705749 Pre-setting of DQS Precalculation
1385 20:17:17.708992 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1386 20:17:17.709103 ==
1387 20:17:17.712594 Dram Type= 6, Freq= 0, CH_1, rank 0
1388 20:17:17.716139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 20:17:17.716250 ==
1390 20:17:17.722639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1391 20:17:17.729309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1392 20:17:17.737704 [CA 0] Center 36 (6~67) winsize 62
1393 20:17:17.740814 [CA 1] Center 36 (6~67) winsize 62
1394 20:17:17.743966 [CA 2] Center 35 (5~66) winsize 62
1395 20:17:17.747555 [CA 3] Center 34 (4~65) winsize 62
1396 20:17:17.751056 [CA 4] Center 34 (4~65) winsize 62
1397 20:17:17.754141 [CA 5] Center 34 (4~65) winsize 62
1398 20:17:17.754225
1399 20:17:17.757803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1400 20:17:17.757888
1401 20:17:17.760760 [CATrainingPosCal] consider 1 rank data
1402 20:17:17.763832 u2DelayCellTimex100 = 270/100 ps
1403 20:17:17.767581 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 20:17:17.770710 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 20:17:17.777706 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1406 20:17:17.780714 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 20:17:17.783965 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 20:17:17.787337 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 20:17:17.787422
1410 20:17:17.790852 CA PerBit enable=1, Macro0, CA PI delay=34
1411 20:17:17.790937
1412 20:17:17.794013 [CBTSetCACLKResult] CA Dly = 34
1413 20:17:17.794135 CS Dly: 6 (0~37)
1414 20:17:17.794211 ==
1415 20:17:17.797289 Dram Type= 6, Freq= 0, CH_1, rank 1
1416 20:17:17.804044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 20:17:17.804130 ==
1418 20:17:17.807594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 20:17:17.814125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 20:17:17.823674 [CA 0] Center 36 (6~67) winsize 62
1421 20:17:17.827241 [CA 1] Center 37 (6~68) winsize 63
1422 20:17:17.831319 [CA 2] Center 35 (5~66) winsize 62
1423 20:17:17.834904 [CA 3] Center 34 (4~65) winsize 62
1424 20:17:17.838865 [CA 4] Center 34 (4~65) winsize 62
1425 20:17:17.842126 [CA 5] Center 34 (4~65) winsize 62
1426 20:17:17.842216
1427 20:17:17.846000 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 20:17:17.846097
1429 20:17:17.849742 [CATrainingPosCal] consider 2 rank data
1430 20:17:17.849832 u2DelayCellTimex100 = 270/100 ps
1431 20:17:17.853443 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 20:17:17.859825 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 20:17:17.862991 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1434 20:17:17.866674 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 20:17:17.869673 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 20:17:17.873162 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 20:17:17.873247
1438 20:17:17.876763 CA PerBit enable=1, Macro0, CA PI delay=34
1439 20:17:17.876848
1440 20:17:17.879963 [CBTSetCACLKResult] CA Dly = 34
1441 20:17:17.880047 CS Dly: 6 (0~38)
1442 20:17:17.883091
1443 20:17:17.886825 ----->DramcWriteLeveling(PI) begin...
1444 20:17:17.886911 ==
1445 20:17:17.889988 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 20:17:17.893172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 20:17:17.893260 ==
1448 20:17:17.896231 Write leveling (Byte 0): 27 => 27
1449 20:17:17.899825 Write leveling (Byte 1): 27 => 27
1450 20:17:17.903223 DramcWriteLeveling(PI) end<-----
1451 20:17:17.903332
1452 20:17:17.903410 ==
1453 20:17:17.906708 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 20:17:17.910046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 20:17:17.910156 ==
1456 20:17:17.913237 [Gating] SW mode calibration
1457 20:17:17.919592 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1458 20:17:17.923376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1459 20:17:17.929933 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1460 20:17:17.933166 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1461 20:17:17.936548 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 20:17:17.943186 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 20:17:17.946961 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 20:17:17.950099 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 20:17:17.956570 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 20:17:17.960296 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 20:17:17.963366 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 20:17:17.970007 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 20:17:17.973405 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 20:17:17.976408 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 20:17:17.983207 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 20:17:17.986531 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 20:17:17.989943 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 20:17:17.996883 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 20:17:18.000071 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1476 20:17:18.003375 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1477 20:17:18.009561 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 20:17:18.013357 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 20:17:18.016804 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 20:17:18.023243 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 20:17:18.026601 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 20:17:18.029733 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 20:17:18.033162 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 20:17:18.039775 0 9 4 | B1->B0 | 2322 2b2b | 1 0 | (0 0) (0 0)
1485 20:17:18.043160 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1486 20:17:18.046574 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 20:17:18.053332 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 20:17:18.056314 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 20:17:18.060151 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 20:17:18.066330 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 20:17:18.070086 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1492 20:17:18.073183 0 10 4 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 0)
1493 20:17:18.079603 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1494 20:17:18.083386 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 20:17:18.086621 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 20:17:18.093304 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 20:17:18.096415 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 20:17:18.099610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 20:17:18.106500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 20:17:18.109822 0 11 4 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (1 1)
1501 20:17:18.112842 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1502 20:17:18.120038 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 20:17:18.123806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 20:17:18.126881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 20:17:18.129930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 20:17:18.136511 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 20:17:18.140187 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1508 20:17:18.143154 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1509 20:17:18.149866 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 20:17:18.153307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 20:17:18.156377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 20:17:18.163335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 20:17:18.166324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 20:17:18.169959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 20:17:18.176705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 20:17:18.179765 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 20:17:18.183297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 20:17:18.189474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 20:17:18.192795 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 20:17:18.196142 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 20:17:18.202693 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 20:17:18.206458 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 20:17:18.209747 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1524 20:17:18.216479 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1525 20:17:18.219516 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 20:17:18.222734 Total UI for P1: 0, mck2ui 16
1527 20:17:18.225947 best dqsien dly found for B0: ( 0, 14, 2)
1528 20:17:18.229466 Total UI for P1: 0, mck2ui 16
1529 20:17:18.232855 best dqsien dly found for B1: ( 0, 14, 4)
1530 20:17:18.236247 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1531 20:17:18.239767 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1532 20:17:18.239890
1533 20:17:18.242846 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1534 20:17:18.246462 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1535 20:17:18.249778 [Gating] SW calibration Done
1536 20:17:18.249867 ==
1537 20:17:18.252957 Dram Type= 6, Freq= 0, CH_1, rank 0
1538 20:17:18.256530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1539 20:17:18.256624 ==
1540 20:17:18.259895 RX Vref Scan: 0
1541 20:17:18.259970
1542 20:17:18.260032 RX Vref 0 -> 0, step: 1
1543 20:17:18.262797
1544 20:17:18.262876 RX Delay -130 -> 252, step: 16
1545 20:17:18.270034 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1546 20:17:18.273258 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1547 20:17:18.276584 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1548 20:17:18.279556 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1549 20:17:18.283317 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1550 20:17:18.286359 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1551 20:17:18.293414 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1552 20:17:18.296611 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1553 20:17:18.299777 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1554 20:17:18.303364 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1555 20:17:18.306843 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1556 20:17:18.313257 iDelay=206, Bit 11, Center 85 (-18 ~ 189) 208
1557 20:17:18.316386 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1558 20:17:18.319991 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1559 20:17:18.323140 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1560 20:17:18.326866 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1561 20:17:18.329968 ==
1562 20:17:18.333198 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 20:17:18.336779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 20:17:18.336867 ==
1565 20:17:18.336935 DQS Delay:
1566 20:17:18.339809 DQS0 = 0, DQS1 = 0
1567 20:17:18.339918 DQM Delay:
1568 20:17:18.343200 DQM0 = 91, DQM1 = 87
1569 20:17:18.343283 DQ Delay:
1570 20:17:18.346551 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1571 20:17:18.349721 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =93
1572 20:17:18.353150 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1573 20:17:18.356714 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1574 20:17:18.356797
1575 20:17:18.356862
1576 20:17:18.356924 ==
1577 20:17:18.359914 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 20:17:18.363496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 20:17:18.363581 ==
1580 20:17:18.363647
1581 20:17:18.363711
1582 20:17:18.366435 TX Vref Scan disable
1583 20:17:18.369748 == TX Byte 0 ==
1584 20:17:18.373182 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1585 20:17:18.376780 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1586 20:17:18.379738 == TX Byte 1 ==
1587 20:17:18.383325 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1588 20:17:18.386468 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1589 20:17:18.386552 ==
1590 20:17:18.390340 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 20:17:18.393345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 20:17:18.393429 ==
1593 20:17:18.408249 TX Vref=22, minBit 2, minWin=26, winSum=438
1594 20:17:18.411421 TX Vref=24, minBit 3, minWin=26, winSum=439
1595 20:17:18.414804 TX Vref=26, minBit 3, minWin=26, winSum=442
1596 20:17:18.418139 TX Vref=28, minBit 7, minWin=26, winSum=444
1597 20:17:18.421431 TX Vref=30, minBit 3, minWin=26, winSum=446
1598 20:17:18.424665 TX Vref=32, minBit 0, minWin=27, winSum=444
1599 20:17:18.431392 [TxChooseVref] Worse bit 0, Min win 27, Win sum 444, Final Vref 32
1600 20:17:18.431476
1601 20:17:18.434641 Final TX Range 1 Vref 32
1602 20:17:18.434724
1603 20:17:18.434789 ==
1604 20:17:18.438280 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 20:17:18.441379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 20:17:18.441462 ==
1607 20:17:18.441526
1608 20:17:18.441586
1609 20:17:18.445064 TX Vref Scan disable
1610 20:17:18.448014 == TX Byte 0 ==
1611 20:17:18.451726 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 20:17:18.454829 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 20:17:18.458414 == TX Byte 1 ==
1614 20:17:18.461373 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 20:17:18.464763 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 20:17:18.464886
1617 20:17:18.468526 [DATLAT]
1618 20:17:18.468646 Freq=800, CH1 RK0
1619 20:17:18.468761
1620 20:17:18.471591 DATLAT Default: 0xa
1621 20:17:18.471709 0, 0xFFFF, sum = 0
1622 20:17:18.474794 1, 0xFFFF, sum = 0
1623 20:17:18.474915 2, 0xFFFF, sum = 0
1624 20:17:18.478111 3, 0xFFFF, sum = 0
1625 20:17:18.478235 4, 0xFFFF, sum = 0
1626 20:17:18.481405 5, 0xFFFF, sum = 0
1627 20:17:18.481530 6, 0xFFFF, sum = 0
1628 20:17:18.484766 7, 0xFFFF, sum = 0
1629 20:17:18.484892 8, 0xFFFF, sum = 0
1630 20:17:18.488430 9, 0x0, sum = 1
1631 20:17:18.488556 10, 0x0, sum = 2
1632 20:17:18.491249 11, 0x0, sum = 3
1633 20:17:18.491372 12, 0x0, sum = 4
1634 20:17:18.494728 best_step = 10
1635 20:17:18.494848
1636 20:17:18.494962 ==
1637 20:17:18.497900 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 20:17:18.501144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 20:17:18.501244 ==
1640 20:17:18.504923 RX Vref Scan: 1
1641 20:17:18.505019
1642 20:17:18.505108 Set Vref Range= 32 -> 127
1643 20:17:18.505193
1644 20:17:18.508054 RX Vref 32 -> 127, step: 1
1645 20:17:18.508148
1646 20:17:18.511201 RX Delay -79 -> 252, step: 8
1647 20:17:18.511283
1648 20:17:18.514933 Set Vref, RX VrefLevel [Byte0]: 32
1649 20:17:18.517995 [Byte1]: 32
1650 20:17:18.518077
1651 20:17:18.521727 Set Vref, RX VrefLevel [Byte0]: 33
1652 20:17:18.524874 [Byte1]: 33
1653 20:17:18.524956
1654 20:17:18.528490 Set Vref, RX VrefLevel [Byte0]: 34
1655 20:17:18.531443 [Byte1]: 34
1656 20:17:18.535243
1657 20:17:18.535325 Set Vref, RX VrefLevel [Byte0]: 35
1658 20:17:18.538624 [Byte1]: 35
1659 20:17:18.543125
1660 20:17:18.543210 Set Vref, RX VrefLevel [Byte0]: 36
1661 20:17:18.546689 [Byte1]: 36
1662 20:17:18.550913
1663 20:17:18.551039 Set Vref, RX VrefLevel [Byte0]: 37
1664 20:17:18.553966 [Byte1]: 37
1665 20:17:18.558262
1666 20:17:18.558383 Set Vref, RX VrefLevel [Byte0]: 38
1667 20:17:18.561442 [Byte1]: 38
1668 20:17:18.565758
1669 20:17:18.565877 Set Vref, RX VrefLevel [Byte0]: 39
1670 20:17:18.568686 [Byte1]: 39
1671 20:17:18.573362
1672 20:17:18.573444 Set Vref, RX VrefLevel [Byte0]: 40
1673 20:17:18.576862 [Byte1]: 40
1674 20:17:18.580473
1675 20:17:18.580553 Set Vref, RX VrefLevel [Byte0]: 41
1676 20:17:18.584338 [Byte1]: 41
1677 20:17:18.587996
1678 20:17:18.588115 Set Vref, RX VrefLevel [Byte0]: 42
1679 20:17:18.591416 [Byte1]: 42
1680 20:17:18.595796
1681 20:17:18.595920 Set Vref, RX VrefLevel [Byte0]: 43
1682 20:17:18.599362 [Byte1]: 43
1683 20:17:18.603334
1684 20:17:18.603457 Set Vref, RX VrefLevel [Byte0]: 44
1685 20:17:18.606633 [Byte1]: 44
1686 20:17:18.610950
1687 20:17:18.611055 Set Vref, RX VrefLevel [Byte0]: 45
1688 20:17:18.614055 [Byte1]: 45
1689 20:17:18.618394
1690 20:17:18.618475 Set Vref, RX VrefLevel [Byte0]: 46
1691 20:17:18.621587 [Byte1]: 46
1692 20:17:18.625901
1693 20:17:18.625982 Set Vref, RX VrefLevel [Byte0]: 47
1694 20:17:18.629719 [Byte1]: 47
1695 20:17:18.633353
1696 20:17:18.633460 Set Vref, RX VrefLevel [Byte0]: 48
1697 20:17:18.636542 [Byte1]: 48
1698 20:17:18.641056
1699 20:17:18.641137 Set Vref, RX VrefLevel [Byte0]: 49
1700 20:17:18.644298 [Byte1]: 49
1701 20:17:18.648703
1702 20:17:18.648784 Set Vref, RX VrefLevel [Byte0]: 50
1703 20:17:18.652083 [Byte1]: 50
1704 20:17:18.655949
1705 20:17:18.656031 Set Vref, RX VrefLevel [Byte0]: 51
1706 20:17:18.659259 [Byte1]: 51
1707 20:17:18.663544
1708 20:17:18.663627 Set Vref, RX VrefLevel [Byte0]: 52
1709 20:17:18.667182 [Byte1]: 52
1710 20:17:18.671075
1711 20:17:18.671158 Set Vref, RX VrefLevel [Byte0]: 53
1712 20:17:18.674310 [Byte1]: 53
1713 20:17:18.678594
1714 20:17:18.678677 Set Vref, RX VrefLevel [Byte0]: 54
1715 20:17:18.681957 [Byte1]: 54
1716 20:17:18.686532
1717 20:17:18.686615 Set Vref, RX VrefLevel [Byte0]: 55
1718 20:17:18.689713 [Byte1]: 55
1719 20:17:18.694086
1720 20:17:18.694169 Set Vref, RX VrefLevel [Byte0]: 56
1721 20:17:18.697133 [Byte1]: 56
1722 20:17:18.701294
1723 20:17:18.701378 Set Vref, RX VrefLevel [Byte0]: 57
1724 20:17:18.704617 [Byte1]: 57
1725 20:17:18.709162
1726 20:17:18.709252 Set Vref, RX VrefLevel [Byte0]: 58
1727 20:17:18.712202 [Byte1]: 58
1728 20:17:18.716395
1729 20:17:18.716475 Set Vref, RX VrefLevel [Byte0]: 59
1730 20:17:18.719558 [Byte1]: 59
1731 20:17:18.724066
1732 20:17:18.724147 Set Vref, RX VrefLevel [Byte0]: 60
1733 20:17:18.727524 [Byte1]: 60
1734 20:17:18.731788
1735 20:17:18.731869 Set Vref, RX VrefLevel [Byte0]: 61
1736 20:17:18.734853 [Byte1]: 61
1737 20:17:18.739262
1738 20:17:18.739390 Set Vref, RX VrefLevel [Byte0]: 62
1739 20:17:18.742354 [Byte1]: 62
1740 20:17:18.746667
1741 20:17:18.746787 Set Vref, RX VrefLevel [Byte0]: 63
1742 20:17:18.750325 [Byte1]: 63
1743 20:17:18.754452
1744 20:17:18.754574 Set Vref, RX VrefLevel [Byte0]: 64
1745 20:17:18.757701 [Byte1]: 64
1746 20:17:18.761902
1747 20:17:18.762025 Set Vref, RX VrefLevel [Byte0]: 65
1748 20:17:18.765591 [Byte1]: 65
1749 20:17:18.769175
1750 20:17:18.769296 Set Vref, RX VrefLevel [Byte0]: 66
1751 20:17:18.772762 [Byte1]: 66
1752 20:17:18.777217
1753 20:17:18.777336 Set Vref, RX VrefLevel [Byte0]: 67
1754 20:17:18.779872 [Byte1]: 67
1755 20:17:18.784294
1756 20:17:18.784418 Set Vref, RX VrefLevel [Byte0]: 68
1757 20:17:18.787546 [Byte1]: 68
1758 20:17:18.792116
1759 20:17:18.792215 Set Vref, RX VrefLevel [Byte0]: 69
1760 20:17:18.794988 [Byte1]: 69
1761 20:17:18.799722
1762 20:17:18.799804 Set Vref, RX VrefLevel [Byte0]: 70
1763 20:17:18.802809 [Byte1]: 70
1764 20:17:18.807309
1765 20:17:18.807391 Set Vref, RX VrefLevel [Byte0]: 71
1766 20:17:18.810254 [Byte1]: 71
1767 20:17:18.814815
1768 20:17:18.814942 Set Vref, RX VrefLevel [Byte0]: 72
1769 20:17:18.818186 [Byte1]: 72
1770 20:17:18.822025
1771 20:17:18.822144 Set Vref, RX VrefLevel [Byte0]: 73
1772 20:17:18.825568 [Byte1]: 73
1773 20:17:18.829822
1774 20:17:18.829945 Set Vref, RX VrefLevel [Byte0]: 74
1775 20:17:18.833023 [Byte1]: 74
1776 20:17:18.837425
1777 20:17:18.837592 Set Vref, RX VrefLevel [Byte0]: 75
1778 20:17:18.840512 [Byte1]: 75
1779 20:17:18.844766
1780 20:17:18.844888 Final RX Vref Byte 0 = 60 to rank0
1781 20:17:18.848640 Final RX Vref Byte 1 = 55 to rank0
1782 20:17:18.851655 Final RX Vref Byte 0 = 60 to rank1
1783 20:17:18.854775 Final RX Vref Byte 1 = 55 to rank1==
1784 20:17:18.858379 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 20:17:18.862056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 20:17:18.865005 ==
1787 20:17:18.865125 DQS Delay:
1788 20:17:18.865239 DQS0 = 0, DQS1 = 0
1789 20:17:18.868229 DQM Delay:
1790 20:17:18.868385 DQM0 = 96, DQM1 = 90
1791 20:17:18.871386 DQ Delay:
1792 20:17:18.874928 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1793 20:17:18.877815 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1794 20:17:18.881326 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84
1795 20:17:18.885031 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1796 20:17:18.885153
1797 20:17:18.885268
1798 20:17:18.891868 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1799 20:17:18.894989 CH1 RK0: MR19=606, MR18=2C49
1800 20:17:18.901954 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1801 20:17:18.902080
1802 20:17:18.905231 ----->DramcWriteLeveling(PI) begin...
1803 20:17:18.905355 ==
1804 20:17:18.908271 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 20:17:18.911510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 20:17:18.911634 ==
1807 20:17:18.914577 Write leveling (Byte 0): 27 => 27
1808 20:17:18.918455 Write leveling (Byte 1): 28 => 28
1809 20:17:18.921642 DramcWriteLeveling(PI) end<-----
1810 20:17:18.921764
1811 20:17:18.921876 ==
1812 20:17:18.925039 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 20:17:18.928193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 20:17:18.928351 ==
1815 20:17:18.931661 [Gating] SW mode calibration
1816 20:17:18.938297 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 20:17:18.944586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 20:17:18.947994 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 20:17:18.951742 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1820 20:17:18.958354 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 20:17:18.961484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 20:17:18.965179 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 20:17:18.971486 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 20:17:18.975100 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 20:17:18.978559 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 20:17:18.985134 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 20:17:18.988419 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 20:17:18.991638 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 20:17:18.998388 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 20:17:19.001532 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 20:17:19.004977 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 20:17:19.011518 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 20:17:19.014931 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 20:17:19.018393 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1835 20:17:19.022163 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1836 20:17:19.028321 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 20:17:19.031930 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 20:17:19.034868 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 20:17:19.041848 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 20:17:19.045496 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 20:17:19.048634 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 20:17:19.055120 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 20:17:19.058401 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
1844 20:17:19.061910 0 9 8 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
1845 20:17:19.068791 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 20:17:19.071900 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 20:17:19.075002 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 20:17:19.081802 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 20:17:19.084871 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 20:17:19.088577 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1851 20:17:19.091715 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
1852 20:17:19.098608 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1853 20:17:19.101893 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 20:17:19.105600 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 20:17:19.112184 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 20:17:19.115450 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 20:17:19.119168 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 20:17:19.125530 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1859 20:17:19.128874 0 11 4 | B1->B0 | 3333 2727 | 1 1 | (0 0) (0 0)
1860 20:17:19.132669 0 11 8 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
1861 20:17:19.138963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 20:17:19.142168 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 20:17:19.145861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 20:17:19.152361 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 20:17:19.155627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 20:17:19.158648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 20:17:19.162428 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1868 20:17:19.168974 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 20:17:19.172629 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 20:17:19.175653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 20:17:19.182669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 20:17:19.185734 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 20:17:19.189335 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 20:17:19.195660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 20:17:19.199271 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 20:17:19.202193 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 20:17:19.209118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 20:17:19.212171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 20:17:19.215595 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 20:17:19.222557 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 20:17:19.225787 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 20:17:19.228913 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 20:17:19.235719 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1884 20:17:19.235802 Total UI for P1: 0, mck2ui 16
1885 20:17:19.239254 best dqsien dly found for B1: ( 0, 14, 2)
1886 20:17:19.246035 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 20:17:19.249037 Total UI for P1: 0, mck2ui 16
1888 20:17:19.252022 best dqsien dly found for B0: ( 0, 14, 4)
1889 20:17:19.255851 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1890 20:17:19.259377 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1891 20:17:19.259487
1892 20:17:19.262376 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 20:17:19.265489 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 20:17:19.269177 [Gating] SW calibration Done
1895 20:17:19.269261 ==
1896 20:17:19.272178 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 20:17:19.276044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 20:17:19.276129 ==
1899 20:17:19.279219 RX Vref Scan: 0
1900 20:17:19.279302
1901 20:17:19.279369 RX Vref 0 -> 0, step: 1
1902 20:17:19.279432
1903 20:17:19.282224 RX Delay -130 -> 252, step: 16
1904 20:17:19.288929 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1905 20:17:19.292620 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1906 20:17:19.295612 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1907 20:17:19.298955 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1908 20:17:19.302872 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1909 20:17:19.306020 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1910 20:17:19.312523 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1911 20:17:19.315711 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1912 20:17:19.318775 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1913 20:17:19.322441 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1914 20:17:19.326017 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1915 20:17:19.332208 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1916 20:17:19.335741 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1917 20:17:19.339385 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1918 20:17:19.342397 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1919 20:17:19.345909 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1920 20:17:19.349332 ==
1921 20:17:19.349446 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 20:17:19.355756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 20:17:19.355867 ==
1924 20:17:19.355964 DQS Delay:
1925 20:17:19.359030 DQS0 = 0, DQS1 = 0
1926 20:17:19.359142 DQM Delay:
1927 20:17:19.362343 DQM0 = 93, DQM1 = 90
1928 20:17:19.362452 DQ Delay:
1929 20:17:19.365838 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1930 20:17:19.369389 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1931 20:17:19.372669 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1932 20:17:19.375868 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1933 20:17:19.375980
1934 20:17:19.376078
1935 20:17:19.376144 ==
1936 20:17:19.379141 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 20:17:19.382509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 20:17:19.382613 ==
1939 20:17:19.382712
1940 20:17:19.385848
1941 20:17:19.385931 TX Vref Scan disable
1942 20:17:19.388747 == TX Byte 0 ==
1943 20:17:19.392321 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1944 20:17:19.395761 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1945 20:17:19.398838 == TX Byte 1 ==
1946 20:17:19.402491 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1947 20:17:19.405620 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1948 20:17:19.405750 ==
1949 20:17:19.408967 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 20:17:19.415656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 20:17:19.415787 ==
1952 20:17:19.427753 TX Vref=22, minBit 1, minWin=27, winSum=445
1953 20:17:19.430864 TX Vref=24, minBit 1, minWin=27, winSum=447
1954 20:17:19.434015 TX Vref=26, minBit 1, minWin=27, winSum=445
1955 20:17:19.437548 TX Vref=28, minBit 1, minWin=27, winSum=453
1956 20:17:19.440682 TX Vref=30, minBit 1, minWin=27, winSum=452
1957 20:17:19.443870 TX Vref=32, minBit 1, minWin=27, winSum=449
1958 20:17:19.450897 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1959 20:17:19.450981
1960 20:17:19.453949 Final TX Range 1 Vref 28
1961 20:17:19.454035
1962 20:17:19.454102 ==
1963 20:17:19.457561 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 20:17:19.460935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 20:17:19.461021 ==
1966 20:17:19.461107
1967 20:17:19.461188
1968 20:17:19.464132 TX Vref Scan disable
1969 20:17:19.467775 == TX Byte 0 ==
1970 20:17:19.470880 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 20:17:19.474647 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 20:17:19.477381 == TX Byte 1 ==
1973 20:17:19.481368 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 20:17:19.484129 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 20:17:19.484215
1976 20:17:19.487857 [DATLAT]
1977 20:17:19.487937 Freq=800, CH1 RK1
1978 20:17:19.488002
1979 20:17:19.491111 DATLAT Default: 0xa
1980 20:17:19.491191 0, 0xFFFF, sum = 0
1981 20:17:19.494800 1, 0xFFFF, sum = 0
1982 20:17:19.494886 2, 0xFFFF, sum = 0
1983 20:17:19.497866 3, 0xFFFF, sum = 0
1984 20:17:19.497945 4, 0xFFFF, sum = 0
1985 20:17:19.500966 5, 0xFFFF, sum = 0
1986 20:17:19.501039 6, 0xFFFF, sum = 0
1987 20:17:19.504171 7, 0xFFFF, sum = 0
1988 20:17:19.504282 8, 0xFFFF, sum = 0
1989 20:17:19.508090 9, 0x0, sum = 1
1990 20:17:19.508175 10, 0x0, sum = 2
1991 20:17:19.511195 11, 0x0, sum = 3
1992 20:17:19.511281 12, 0x0, sum = 4
1993 20:17:19.514575 best_step = 10
1994 20:17:19.514680
1995 20:17:19.514780 ==
1996 20:17:19.517581 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 20:17:19.520920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 20:17:19.521034 ==
1999 20:17:19.524612 RX Vref Scan: 0
2000 20:17:19.524721
2001 20:17:19.524806 RX Vref 0 -> 0, step: 1
2002 20:17:19.524870
2003 20:17:19.527941 RX Delay -79 -> 252, step: 8
2004 20:17:19.534407 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2005 20:17:19.537600 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2006 20:17:19.541135 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2007 20:17:19.544537 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2008 20:17:19.547665 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2009 20:17:19.551289 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2010 20:17:19.557695 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2011 20:17:19.561074 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2012 20:17:19.564438 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2013 20:17:19.567584 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2014 20:17:19.571140 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2015 20:17:19.574086 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2016 20:17:19.580916 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2017 20:17:19.584545 iDelay=209, Bit 13, Center 104 (9 ~ 200) 192
2018 20:17:19.587777 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2019 20:17:19.591290 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2020 20:17:19.591371 ==
2021 20:17:19.594514 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 20:17:19.601442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 20:17:19.601534 ==
2024 20:17:19.601602 DQS Delay:
2025 20:17:19.604010 DQS0 = 0, DQS1 = 0
2026 20:17:19.604114 DQM Delay:
2027 20:17:19.604208 DQM0 = 97, DQM1 = 92
2028 20:17:19.607838 DQ Delay:
2029 20:17:19.611065 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2030 20:17:19.614384 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2031 20:17:19.617557 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2032 20:17:19.620735 DQ12 =100, DQ13 =104, DQ14 =96, DQ15 =96
2033 20:17:19.620858
2034 20:17:19.620954
2035 20:17:19.627615 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2036 20:17:19.631410 CH1 RK1: MR19=606, MR18=4913
2037 20:17:19.637972 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2038 20:17:19.641052 [RxdqsGatingPostProcess] freq 800
2039 20:17:19.644060 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 20:17:19.647818 Pre-setting of DQS Precalculation
2041 20:17:19.654644 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 20:17:19.661273 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 20:17:19.667732 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 20:17:19.667829
2045 20:17:19.667896
2046 20:17:19.671153 [Calibration Summary] 1600 Mbps
2047 20:17:19.671264 CH 0, Rank 0
2048 20:17:19.674473 SW Impedance : PASS
2049 20:17:19.677599 DUTY Scan : NO K
2050 20:17:19.677683 ZQ Calibration : PASS
2051 20:17:19.681335 Jitter Meter : NO K
2052 20:17:19.684629 CBT Training : PASS
2053 20:17:19.684731 Write leveling : PASS
2054 20:17:19.687595 RX DQS gating : PASS
2055 20:17:19.691235 RX DQ/DQS(RDDQC) : PASS
2056 20:17:19.691319 TX DQ/DQS : PASS
2057 20:17:19.694270 RX DATLAT : PASS
2058 20:17:19.694371 RX DQ/DQS(Engine): PASS
2059 20:17:19.698122 TX OE : NO K
2060 20:17:19.698206 All Pass.
2061 20:17:19.698273
2062 20:17:19.701078 CH 0, Rank 1
2063 20:17:19.701192 SW Impedance : PASS
2064 20:17:19.704813 DUTY Scan : NO K
2065 20:17:19.708030 ZQ Calibration : PASS
2066 20:17:19.708104 Jitter Meter : NO K
2067 20:17:19.711292 CBT Training : PASS
2068 20:17:19.714603 Write leveling : PASS
2069 20:17:19.714687 RX DQS gating : PASS
2070 20:17:19.717965 RX DQ/DQS(RDDQC) : PASS
2071 20:17:19.721185 TX DQ/DQS : PASS
2072 20:17:19.721270 RX DATLAT : PASS
2073 20:17:19.724305 RX DQ/DQS(Engine): PASS
2074 20:17:19.727808 TX OE : NO K
2075 20:17:19.727893 All Pass.
2076 20:17:19.727960
2077 20:17:19.728024 CH 1, Rank 0
2078 20:17:19.731470 SW Impedance : PASS
2079 20:17:19.734578 DUTY Scan : NO K
2080 20:17:19.734692 ZQ Calibration : PASS
2081 20:17:19.737712 Jitter Meter : NO K
2082 20:17:19.737798 CBT Training : PASS
2083 20:17:19.741514 Write leveling : PASS
2084 20:17:19.744533 RX DQS gating : PASS
2085 20:17:19.744622 RX DQ/DQS(RDDQC) : PASS
2086 20:17:19.748297 TX DQ/DQS : PASS
2087 20:17:19.751527 RX DATLAT : PASS
2088 20:17:19.751621 RX DQ/DQS(Engine): PASS
2089 20:17:19.754601 TX OE : NO K
2090 20:17:19.754686 All Pass.
2091 20:17:19.754752
2092 20:17:19.758361 CH 1, Rank 1
2093 20:17:19.758449 SW Impedance : PASS
2094 20:17:19.761416 DUTY Scan : NO K
2095 20:17:19.765111 ZQ Calibration : PASS
2096 20:17:19.765199 Jitter Meter : NO K
2097 20:17:19.768236 CBT Training : PASS
2098 20:17:19.771303 Write leveling : PASS
2099 20:17:19.771392 RX DQS gating : PASS
2100 20:17:19.774889 RX DQ/DQS(RDDQC) : PASS
2101 20:17:19.774973 TX DQ/DQS : PASS
2102 20:17:19.778083 RX DATLAT : PASS
2103 20:17:19.781263 RX DQ/DQS(Engine): PASS
2104 20:17:19.781349 TX OE : NO K
2105 20:17:19.784688 All Pass.
2106 20:17:19.784794
2107 20:17:19.784865 DramC Write-DBI off
2108 20:17:19.788201 PER_BANK_REFRESH: Hybrid Mode
2109 20:17:19.791630 TX_TRACKING: ON
2110 20:17:19.795140 [GetDramInforAfterCalByMRR] Vendor 6.
2111 20:17:19.798334 [GetDramInforAfterCalByMRR] Revision 606.
2112 20:17:19.801675 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 20:17:19.801763 MR0 0x3b3b
2114 20:17:19.801862 MR8 0x5151
2115 20:17:19.808168 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 20:17:19.808277
2117 20:17:19.808380 MR0 0x3b3b
2118 20:17:19.808470 MR8 0x5151
2119 20:17:19.811777 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 20:17:19.811859
2121 20:17:19.821285 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 20:17:19.824574 [FAST_K] Save calibration result to emmc
2123 20:17:19.828085 [FAST_K] Save calibration result to emmc
2124 20:17:19.831295 dram_init: config_dvfs: 1
2125 20:17:19.835091 dramc_set_vcore_voltage set vcore to 662500
2126 20:17:19.838163 Read voltage for 1200, 2
2127 20:17:19.838282 Vio18 = 0
2128 20:17:19.838380 Vcore = 662500
2129 20:17:19.841859 Vdram = 0
2130 20:17:19.841947 Vddq = 0
2131 20:17:19.842013 Vmddr = 0
2132 20:17:19.848169 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 20:17:19.851227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 20:17:19.854854 MEM_TYPE=3, freq_sel=15
2135 20:17:19.858058 sv_algorithm_assistance_LP4_1600
2136 20:17:19.861689 ============ PULL DRAM RESETB DOWN ============
2137 20:17:19.864973 ========== PULL DRAM RESETB DOWN end =========
2138 20:17:19.871797 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 20:17:19.875010 ===================================
2140 20:17:19.875112 LPDDR4 DRAM CONFIGURATION
2141 20:17:19.878225 ===================================
2142 20:17:19.881515 EX_ROW_EN[0] = 0x0
2143 20:17:19.884883 EX_ROW_EN[1] = 0x0
2144 20:17:19.884967 LP4Y_EN = 0x0
2145 20:17:19.888027 WORK_FSP = 0x0
2146 20:17:19.888110 WL = 0x4
2147 20:17:19.891816 RL = 0x4
2148 20:17:19.891926 BL = 0x2
2149 20:17:19.894795 RPST = 0x0
2150 20:17:19.894879 RD_PRE = 0x0
2151 20:17:19.898523 WR_PRE = 0x1
2152 20:17:19.898607 WR_PST = 0x0
2153 20:17:19.901632 DBI_WR = 0x0
2154 20:17:19.901717 DBI_RD = 0x0
2155 20:17:19.905232 OTF = 0x1
2156 20:17:19.908657 ===================================
2157 20:17:19.911577 ===================================
2158 20:17:19.911661 ANA top config
2159 20:17:19.914935 ===================================
2160 20:17:19.918152 DLL_ASYNC_EN = 0
2161 20:17:19.921893 ALL_SLAVE_EN = 0
2162 20:17:19.921980 NEW_RANK_MODE = 1
2163 20:17:19.925139 DLL_IDLE_MODE = 1
2164 20:17:19.928550 LP45_APHY_COMB_EN = 1
2165 20:17:19.931402 TX_ODT_DIS = 1
2166 20:17:19.934900 NEW_8X_MODE = 1
2167 20:17:19.938329 ===================================
2168 20:17:19.941463 ===================================
2169 20:17:19.941578 data_rate = 2400
2170 20:17:19.945008 CKR = 1
2171 20:17:19.948100 DQ_P2S_RATIO = 8
2172 20:17:19.951730 ===================================
2173 20:17:19.955365 CA_P2S_RATIO = 8
2174 20:17:19.958409 DQ_CA_OPEN = 0
2175 20:17:19.962076 DQ_SEMI_OPEN = 0
2176 20:17:19.962160 CA_SEMI_OPEN = 0
2177 20:17:19.965268 CA_FULL_RATE = 0
2178 20:17:19.968439 DQ_CKDIV4_EN = 0
2179 20:17:19.971430 CA_CKDIV4_EN = 0
2180 20:17:19.974699 CA_PREDIV_EN = 0
2181 20:17:19.978488 PH8_DLY = 17
2182 20:17:19.978572 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 20:17:19.981628 DQ_AAMCK_DIV = 4
2184 20:17:19.984765 CA_AAMCK_DIV = 4
2185 20:17:19.988399 CA_ADMCK_DIV = 4
2186 20:17:19.991377 DQ_TRACK_CA_EN = 0
2187 20:17:19.995137 CA_PICK = 1200
2188 20:17:19.998283 CA_MCKIO = 1200
2189 20:17:19.998366 MCKIO_SEMI = 0
2190 20:17:20.001427 PLL_FREQ = 2366
2191 20:17:20.004615 DQ_UI_PI_RATIO = 32
2192 20:17:20.008524 CA_UI_PI_RATIO = 0
2193 20:17:20.011594 ===================================
2194 20:17:20.014764 ===================================
2195 20:17:20.018503 memory_type:LPDDR4
2196 20:17:20.018593 GP_NUM : 10
2197 20:17:20.021302 SRAM_EN : 1
2198 20:17:20.021386 MD32_EN : 0
2199 20:17:20.025343 ===================================
2200 20:17:20.028119 [ANA_INIT] >>>>>>>>>>>>>>
2201 20:17:20.031928 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 20:17:20.035088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 20:17:20.038550 ===================================
2204 20:17:20.041660 data_rate = 2400,PCW = 0X5b00
2205 20:17:20.045189 ===================================
2206 20:17:20.048135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 20:17:20.054947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 20:17:20.058451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 20:17:20.064893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 20:17:20.068327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 20:17:20.071971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 20:17:20.072056 [ANA_INIT] flow start
2213 20:17:20.074952 [ANA_INIT] PLL >>>>>>>>
2214 20:17:20.078782 [ANA_INIT] PLL <<<<<<<<
2215 20:17:20.078866 [ANA_INIT] MIDPI >>>>>>>>
2216 20:17:20.081906 [ANA_INIT] MIDPI <<<<<<<<
2217 20:17:20.085157 [ANA_INIT] DLL >>>>>>>>
2218 20:17:20.085248 [ANA_INIT] DLL <<<<<<<<
2219 20:17:20.088424 [ANA_INIT] flow end
2220 20:17:20.091605 ============ LP4 DIFF to SE enter ============
2221 20:17:20.095156 ============ LP4 DIFF to SE exit ============
2222 20:17:20.098317 [ANA_INIT] <<<<<<<<<<<<<
2223 20:17:20.102232 [Flow] Enable top DCM control >>>>>
2224 20:17:20.105221 [Flow] Enable top DCM control <<<<<
2225 20:17:20.108408 Enable DLL master slave shuffle
2226 20:17:20.115385 ==============================================================
2227 20:17:20.115468 Gating Mode config
2228 20:17:20.122273 ==============================================================
2229 20:17:20.122417 Config description:
2230 20:17:20.131711 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 20:17:20.138392 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 20:17:20.145313 SELPH_MODE 0: By rank 1: By Phase
2233 20:17:20.148794 ==============================================================
2234 20:17:20.151666 GAT_TRACK_EN = 1
2235 20:17:20.155227 RX_GATING_MODE = 2
2236 20:17:20.158840 RX_GATING_TRACK_MODE = 2
2237 20:17:20.161705 SELPH_MODE = 1
2238 20:17:20.165188 PICG_EARLY_EN = 1
2239 20:17:20.168453 VALID_LAT_VALUE = 1
2240 20:17:20.171909 ==============================================================
2241 20:17:20.175224 Enter into Gating configuration >>>>
2242 20:17:20.178331 Exit from Gating configuration <<<<
2243 20:17:20.181828 Enter into DVFS_PRE_config >>>>>
2244 20:17:20.195361 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 20:17:20.195448 Exit from DVFS_PRE_config <<<<<
2246 20:17:20.198966 Enter into PICG configuration >>>>
2247 20:17:20.201941 Exit from PICG configuration <<<<
2248 20:17:20.205650 [RX_INPUT] configuration >>>>>
2249 20:17:20.208795 [RX_INPUT] configuration <<<<<
2250 20:17:20.215598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 20:17:20.218774 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 20:17:20.225599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 20:17:20.232498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 20:17:20.239022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 20:17:20.245557 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 20:17:20.248708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 20:17:20.251821 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 20:17:20.255232 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 20:17:20.261831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 20:17:20.265268 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 20:17:20.268504 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 20:17:20.272101 ===================================
2263 20:17:20.275091 LPDDR4 DRAM CONFIGURATION
2264 20:17:20.278903 ===================================
2265 20:17:20.279013 EX_ROW_EN[0] = 0x0
2266 20:17:20.281914 EX_ROW_EN[1] = 0x0
2267 20:17:20.285644 LP4Y_EN = 0x0
2268 20:17:20.285730 WORK_FSP = 0x0
2269 20:17:20.288652 WL = 0x4
2270 20:17:20.288735 RL = 0x4
2271 20:17:20.291962 BL = 0x2
2272 20:17:20.292044 RPST = 0x0
2273 20:17:20.295808 RD_PRE = 0x0
2274 20:17:20.295891 WR_PRE = 0x1
2275 20:17:20.298919 WR_PST = 0x0
2276 20:17:20.299001 DBI_WR = 0x0
2277 20:17:20.302053 DBI_RD = 0x0
2278 20:17:20.302135 OTF = 0x1
2279 20:17:20.305662 ===================================
2280 20:17:20.308859 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 20:17:20.312298 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 20:17:20.319122 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 20:17:20.322260 ===================================
2284 20:17:20.325451 LPDDR4 DRAM CONFIGURATION
2285 20:17:20.329054 ===================================
2286 20:17:20.329137 EX_ROW_EN[0] = 0x10
2287 20:17:20.332811 EX_ROW_EN[1] = 0x0
2288 20:17:20.332893 LP4Y_EN = 0x0
2289 20:17:20.335738 WORK_FSP = 0x0
2290 20:17:20.335863 WL = 0x4
2291 20:17:20.338861 RL = 0x4
2292 20:17:20.338943 BL = 0x2
2293 20:17:20.342427 RPST = 0x0
2294 20:17:20.342509 RD_PRE = 0x0
2295 20:17:20.345629 WR_PRE = 0x1
2296 20:17:20.345748 WR_PST = 0x0
2297 20:17:20.349129 DBI_WR = 0x0
2298 20:17:20.349254 DBI_RD = 0x0
2299 20:17:20.352626 OTF = 0x1
2300 20:17:20.355757 ===================================
2301 20:17:20.362404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 20:17:20.362514 ==
2303 20:17:20.365808 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 20:17:20.369399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 20:17:20.369482 ==
2306 20:17:20.372863 [Duty_Offset_Calibration]
2307 20:17:20.372945 B0:2 B1:1 CA:1
2308 20:17:20.373010
2309 20:17:20.376103 [DutyScan_Calibration_Flow] k_type=0
2310 20:17:20.386650
2311 20:17:20.386776 ==CLK 0==
2312 20:17:20.389610 Final CLK duty delay cell = 0
2313 20:17:20.392709 [0] MAX Duty = 5187%(X100), DQS PI = 24
2314 20:17:20.396619 [0] MIN Duty = 4875%(X100), DQS PI = 0
2315 20:17:20.396742 [0] AVG Duty = 5031%(X100)
2316 20:17:20.396854
2317 20:17:20.399551 CH0 CLK Duty spec in!! Max-Min= 312%
2318 20:17:20.406251 [DutyScan_Calibration_Flow] ====Done====
2319 20:17:20.406369
2320 20:17:20.409210 [DutyScan_Calibration_Flow] k_type=1
2321 20:17:20.424517
2322 20:17:20.424646 ==DQS 0 ==
2323 20:17:20.428041 Final DQS duty delay cell = -4
2324 20:17:20.431057 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2325 20:17:20.434690 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2326 20:17:20.437853 [-4] AVG Duty = 4937%(X100)
2327 20:17:20.437979
2328 20:17:20.438092 ==DQS 1 ==
2329 20:17:20.441636 Final DQS duty delay cell = 0
2330 20:17:20.445100 [0] MAX Duty = 5156%(X100), DQS PI = 60
2331 20:17:20.447927 [0] MIN Duty = 5000%(X100), DQS PI = 32
2332 20:17:20.451094 [0] AVG Duty = 5078%(X100)
2333 20:17:20.451212
2334 20:17:20.454751 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2335 20:17:20.454874
2336 20:17:20.457721 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2337 20:17:20.461158 [DutyScan_Calibration_Flow] ====Done====
2338 20:17:20.461277
2339 20:17:20.464744 [DutyScan_Calibration_Flow] k_type=3
2340 20:17:20.481961
2341 20:17:20.482085 ==DQM 0 ==
2342 20:17:20.484954 Final DQM duty delay cell = 0
2343 20:17:20.488487 [0] MAX Duty = 5156%(X100), DQS PI = 30
2344 20:17:20.491576 [0] MIN Duty = 4875%(X100), DQS PI = 58
2345 20:17:20.491657 [0] AVG Duty = 5015%(X100)
2346 20:17:20.495180
2347 20:17:20.495260 ==DQM 1 ==
2348 20:17:20.498227 Final DQM duty delay cell = 0
2349 20:17:20.501423 [0] MAX Duty = 5093%(X100), DQS PI = 0
2350 20:17:20.505053 [0] MIN Duty = 5031%(X100), DQS PI = 16
2351 20:17:20.505205 [0] AVG Duty = 5062%(X100)
2352 20:17:20.508010
2353 20:17:20.511790 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2354 20:17:20.511871
2355 20:17:20.514912 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2356 20:17:20.518569 [DutyScan_Calibration_Flow] ====Done====
2357 20:17:20.518650
2358 20:17:20.521565 [DutyScan_Calibration_Flow] k_type=2
2359 20:17:20.538184
2360 20:17:20.538267 ==DQ 0 ==
2361 20:17:20.541342 Final DQ duty delay cell = 0
2362 20:17:20.545164 [0] MAX Duty = 5031%(X100), DQS PI = 26
2363 20:17:20.548224 [0] MIN Duty = 4875%(X100), DQS PI = 0
2364 20:17:20.548346 [0] AVG Duty = 4953%(X100)
2365 20:17:20.548413
2366 20:17:20.551901 ==DQ 1 ==
2367 20:17:20.554851 Final DQ duty delay cell = 0
2368 20:17:20.557963 [0] MAX Duty = 5093%(X100), DQS PI = 24
2369 20:17:20.561644 [0] MIN Duty = 4907%(X100), DQS PI = 36
2370 20:17:20.561726 [0] AVG Duty = 5000%(X100)
2371 20:17:20.561790
2372 20:17:20.565027 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2373 20:17:20.565109
2374 20:17:20.567988 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2375 20:17:20.574796 [DutyScan_Calibration_Flow] ====Done====
2376 20:17:20.574878 ==
2377 20:17:20.578008 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 20:17:20.581666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 20:17:20.581749 ==
2380 20:17:20.584633 [Duty_Offset_Calibration]
2381 20:17:20.584714 B0:1 B1:0 CA:0
2382 20:17:20.584779
2383 20:17:20.587954 [DutyScan_Calibration_Flow] k_type=0
2384 20:17:20.597005
2385 20:17:20.597086 ==CLK 0==
2386 20:17:20.600486 Final CLK duty delay cell = -4
2387 20:17:20.604044 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2388 20:17:20.607117 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2389 20:17:20.610705 [-4] AVG Duty = 4969%(X100)
2390 20:17:20.610787
2391 20:17:20.613841 CH1 CLK Duty spec in!! Max-Min= 124%
2392 20:17:20.617029 [DutyScan_Calibration_Flow] ====Done====
2393 20:17:20.617111
2394 20:17:20.620727 [DutyScan_Calibration_Flow] k_type=1
2395 20:17:20.636869
2396 20:17:20.636955 ==DQS 0 ==
2397 20:17:20.640212 Final DQS duty delay cell = 0
2398 20:17:20.643882 [0] MAX Duty = 5094%(X100), DQS PI = 26
2399 20:17:20.646709 [0] MIN Duty = 4875%(X100), DQS PI = 0
2400 20:17:20.646813 [0] AVG Duty = 4984%(X100)
2401 20:17:20.650268
2402 20:17:20.650390 ==DQS 1 ==
2403 20:17:20.653528 Final DQS duty delay cell = 0
2404 20:17:20.656646 [0] MAX Duty = 5187%(X100), DQS PI = 20
2405 20:17:20.660436 [0] MIN Duty = 4969%(X100), DQS PI = 8
2406 20:17:20.660559 [0] AVG Duty = 5078%(X100)
2407 20:17:20.663875
2408 20:17:20.666949 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2409 20:17:20.667054
2410 20:17:20.670621 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2411 20:17:20.673589 [DutyScan_Calibration_Flow] ====Done====
2412 20:17:20.673671
2413 20:17:20.677324 [DutyScan_Calibration_Flow] k_type=3
2414 20:17:20.693567
2415 20:17:20.693649 ==DQM 0 ==
2416 20:17:20.696868 Final DQM duty delay cell = 0
2417 20:17:20.700376 [0] MAX Duty = 5156%(X100), DQS PI = 6
2418 20:17:20.703306 [0] MIN Duty = 5031%(X100), DQS PI = 0
2419 20:17:20.703432 [0] AVG Duty = 5093%(X100)
2420 20:17:20.703546
2421 20:17:20.706791 ==DQM 1 ==
2422 20:17:20.710382 Final DQM duty delay cell = 0
2423 20:17:20.713548 [0] MAX Duty = 5031%(X100), DQS PI = 26
2424 20:17:20.716860 [0] MIN Duty = 4875%(X100), DQS PI = 36
2425 20:17:20.716984 [0] AVG Duty = 4953%(X100)
2426 20:17:20.720111
2427 20:17:20.723723 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2428 20:17:20.723823
2429 20:17:20.726720 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2430 20:17:20.729849 [DutyScan_Calibration_Flow] ====Done====
2431 20:17:20.729945
2432 20:17:20.733575 [DutyScan_Calibration_Flow] k_type=2
2433 20:17:20.749044
2434 20:17:20.749157 ==DQ 0 ==
2435 20:17:20.752238 Final DQ duty delay cell = -4
2436 20:17:20.755910 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2437 20:17:20.759118 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2438 20:17:20.762406 [-4] AVG Duty = 4984%(X100)
2439 20:17:20.762491
2440 20:17:20.762558 ==DQ 1 ==
2441 20:17:20.765780 Final DQ duty delay cell = 0
2442 20:17:20.769568 [0] MAX Duty = 5125%(X100), DQS PI = 20
2443 20:17:20.772804 [0] MIN Duty = 4969%(X100), DQS PI = 10
2444 20:17:20.772901 [0] AVG Duty = 5047%(X100)
2445 20:17:20.775967
2446 20:17:20.778993 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2447 20:17:20.779076
2448 20:17:20.782662 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2449 20:17:20.786080 [DutyScan_Calibration_Flow] ====Done====
2450 20:17:20.789247 nWR fixed to 30
2451 20:17:20.789330 [ModeRegInit_LP4] CH0 RK0
2452 20:17:20.792452 [ModeRegInit_LP4] CH0 RK1
2453 20:17:20.795606 [ModeRegInit_LP4] CH1 RK0
2454 20:17:20.799327 [ModeRegInit_LP4] CH1 RK1
2455 20:17:20.799409 match AC timing 7
2456 20:17:20.802509 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 20:17:20.809521 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 20:17:20.812460 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 20:17:20.816241 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 20:17:20.822952 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 20:17:20.823034 ==
2462 20:17:20.825829 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 20:17:20.829634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 20:17:20.829719 ==
2465 20:17:20.835974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 20:17:20.839631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 20:17:20.849267 [CA 0] Center 39 (8~70) winsize 63
2468 20:17:20.852878 [CA 1] Center 39 (8~70) winsize 63
2469 20:17:20.856205 [CA 2] Center 35 (5~66) winsize 62
2470 20:17:20.859222 [CA 3] Center 34 (4~65) winsize 62
2471 20:17:20.862924 [CA 4] Center 33 (3~64) winsize 62
2472 20:17:20.866082 [CA 5] Center 32 (3~62) winsize 60
2473 20:17:20.866167
2474 20:17:20.869237 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2475 20:17:20.869356
2476 20:17:20.877561 [CATrainingPosCal] consider 1 rank data
2477 20:17:20.877648 u2DelayCellTimex100 = 270/100 ps
2478 20:17:20.879430 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2479 20:17:20.883036 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2480 20:17:20.889880 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2481 20:17:20.892507 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2482 20:17:20.896106 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2483 20:17:20.899148 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2484 20:17:20.899248
2485 20:17:20.902535 CA PerBit enable=1, Macro0, CA PI delay=32
2486 20:17:20.902620
2487 20:17:20.906093 [CBTSetCACLKResult] CA Dly = 32
2488 20:17:20.906204 CS Dly: 6 (0~37)
2489 20:17:20.909303 ==
2490 20:17:20.909401 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 20:17:20.916178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 20:17:20.916264 ==
2493 20:17:20.919483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 20:17:20.926192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2495 20:17:20.935257 [CA 0] Center 38 (8~69) winsize 62
2496 20:17:20.938392 [CA 1] Center 38 (8~69) winsize 62
2497 20:17:20.941762 [CA 2] Center 35 (4~66) winsize 63
2498 20:17:20.945321 [CA 3] Center 34 (4~65) winsize 62
2499 20:17:20.948867 [CA 4] Center 33 (3~64) winsize 62
2500 20:17:20.952188 [CA 5] Center 32 (3~62) winsize 60
2501 20:17:20.952313
2502 20:17:20.955328 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 20:17:20.955423
2504 20:17:20.958256 [CATrainingPosCal] consider 2 rank data
2505 20:17:20.961767 u2DelayCellTimex100 = 270/100 ps
2506 20:17:20.965415 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2507 20:17:20.968564 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2508 20:17:20.975506 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2509 20:17:20.978381 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2510 20:17:20.982094 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2511 20:17:20.985128 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2512 20:17:20.985252
2513 20:17:20.988192 CA PerBit enable=1, Macro0, CA PI delay=32
2514 20:17:20.988352
2515 20:17:20.992409 [CBTSetCACLKResult] CA Dly = 32
2516 20:17:20.992537 CS Dly: 6 (0~38)
2517 20:17:20.992649
2518 20:17:20.995118 ----->DramcWriteLeveling(PI) begin...
2519 20:17:20.998343 ==
2520 20:17:21.001681 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 20:17:21.004969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 20:17:21.005098 ==
2523 20:17:21.008823 Write leveling (Byte 0): 32 => 32
2524 20:17:21.012010 Write leveling (Byte 1): 31 => 31
2525 20:17:21.015128 DramcWriteLeveling(PI) end<-----
2526 20:17:21.015261
2527 20:17:21.015372 ==
2528 20:17:21.018679 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 20:17:21.021796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 20:17:21.021919 ==
2531 20:17:21.025451 [Gating] SW mode calibration
2532 20:17:21.032302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 20:17:21.035305 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 20:17:21.041981 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2535 20:17:21.045709 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2536 20:17:21.048572 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 20:17:21.055372 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 20:17:21.058434 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 20:17:21.062075 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 20:17:21.068793 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2541 20:17:21.071966 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2542 20:17:21.075501 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
2543 20:17:21.082053 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 20:17:21.085799 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 20:17:21.089232 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 20:17:21.095561 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 20:17:21.098692 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 20:17:21.102391 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2549 20:17:21.105483 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2550 20:17:21.112111 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2551 20:17:21.115724 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 20:17:21.118886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 20:17:21.125668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 20:17:21.129188 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 20:17:21.132179 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 20:17:21.139005 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 20:17:21.142473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 20:17:21.145477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 20:17:21.152186 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 20:17:21.155789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 20:17:21.158830 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 20:17:21.165588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 20:17:21.169354 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 20:17:21.172442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 20:17:21.179157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 20:17:21.182231 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 20:17:21.185561 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 20:17:21.189097 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 20:17:21.196130 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 20:17:21.199113 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 20:17:21.202397 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 20:17:21.209371 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 20:17:21.212521 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 20:17:21.215592 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 20:17:21.219332 Total UI for P1: 0, mck2ui 16
2576 20:17:21.222432 best dqsien dly found for B0: ( 1, 3, 28)
2577 20:17:21.229108 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 20:17:21.229192 Total UI for P1: 0, mck2ui 16
2579 20:17:21.236058 best dqsien dly found for B1: ( 1, 4, 0)
2580 20:17:21.239345 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2581 20:17:21.242355 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2582 20:17:21.242438
2583 20:17:21.245984 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2584 20:17:21.248997 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 20:17:21.252680 [Gating] SW calibration Done
2586 20:17:21.252763 ==
2587 20:17:21.255602 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 20:17:21.259171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 20:17:21.259259 ==
2590 20:17:21.262386 RX Vref Scan: 0
2591 20:17:21.262474
2592 20:17:21.262541 RX Vref 0 -> 0, step: 1
2593 20:17:21.262604
2594 20:17:21.265594 RX Delay -40 -> 252, step: 8
2595 20:17:21.269266 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2596 20:17:21.272349 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2597 20:17:21.279183 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2598 20:17:21.282904 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2599 20:17:21.285888 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2600 20:17:21.289301 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2601 20:17:21.292539 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2602 20:17:21.299066 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2603 20:17:21.302678 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2604 20:17:21.306181 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2605 20:17:21.309211 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2606 20:17:21.312805 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2607 20:17:21.319331 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2608 20:17:21.322657 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2609 20:17:21.325827 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2610 20:17:21.329176 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2611 20:17:21.329259 ==
2612 20:17:21.332664 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 20:17:21.336088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 20:17:21.339214 ==
2615 20:17:21.339298 DQS Delay:
2616 20:17:21.339364 DQS0 = 0, DQS1 = 0
2617 20:17:21.342717 DQM Delay:
2618 20:17:21.342800 DQM0 = 121, DQM1 = 112
2619 20:17:21.345956 DQ Delay:
2620 20:17:21.349743 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2621 20:17:21.352529 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2622 20:17:21.356159 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2623 20:17:21.359100 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2624 20:17:21.359183
2625 20:17:21.359247
2626 20:17:21.359308 ==
2627 20:17:21.362614 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 20:17:21.366447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 20:17:21.366530 ==
2630 20:17:21.366594
2631 20:17:21.369496
2632 20:17:21.369577 TX Vref Scan disable
2633 20:17:21.372711 == TX Byte 0 ==
2634 20:17:21.376418 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2635 20:17:21.379436 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2636 20:17:21.383051 == TX Byte 1 ==
2637 20:17:21.386141 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2638 20:17:21.389754 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2639 20:17:21.389835 ==
2640 20:17:21.392898 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 20:17:21.396552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 20:17:21.399404 ==
2643 20:17:21.409598 TX Vref=22, minBit 0, minWin=25, winSum=407
2644 20:17:21.413199 TX Vref=24, minBit 0, minWin=25, winSum=406
2645 20:17:21.416616 TX Vref=26, minBit 10, minWin=25, winSum=415
2646 20:17:21.419584 TX Vref=28, minBit 15, minWin=25, winSum=424
2647 20:17:21.423185 TX Vref=30, minBit 12, minWin=25, winSum=421
2648 20:17:21.430088 TX Vref=32, minBit 0, minWin=26, winSum=422
2649 20:17:21.433167 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 32
2650 20:17:21.433250
2651 20:17:21.436849 Final TX Range 1 Vref 32
2652 20:17:21.436956
2653 20:17:21.437052 ==
2654 20:17:21.439968 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 20:17:21.442897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 20:17:21.442998 ==
2657 20:17:21.446130
2658 20:17:21.446232
2659 20:17:21.446351 TX Vref Scan disable
2660 20:17:21.449942 == TX Byte 0 ==
2661 20:17:21.453016 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2662 20:17:21.456467 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2663 20:17:21.459566 == TX Byte 1 ==
2664 20:17:21.463140 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2665 20:17:21.466292 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2666 20:17:21.470064
2667 20:17:21.470186 [DATLAT]
2668 20:17:21.470250 Freq=1200, CH0 RK0
2669 20:17:21.470310
2670 20:17:21.473313 DATLAT Default: 0xd
2671 20:17:21.473440 0, 0xFFFF, sum = 0
2672 20:17:21.476551 1, 0xFFFF, sum = 0
2673 20:17:21.476635 2, 0xFFFF, sum = 0
2674 20:17:21.479677 3, 0xFFFF, sum = 0
2675 20:17:21.479761 4, 0xFFFF, sum = 0
2676 20:17:21.482828 5, 0xFFFF, sum = 0
2677 20:17:21.485920 6, 0xFFFF, sum = 0
2678 20:17:21.486003 7, 0xFFFF, sum = 0
2679 20:17:21.489581 8, 0xFFFF, sum = 0
2680 20:17:21.489665 9, 0xFFFF, sum = 0
2681 20:17:21.492645 10, 0xFFFF, sum = 0
2682 20:17:21.492729 11, 0xFFFF, sum = 0
2683 20:17:21.496395 12, 0x0, sum = 1
2684 20:17:21.496479 13, 0x0, sum = 2
2685 20:17:21.499476 14, 0x0, sum = 3
2686 20:17:21.499559 15, 0x0, sum = 4
2687 20:17:21.499627 best_step = 13
2688 20:17:21.499687
2689 20:17:21.503113 ==
2690 20:17:21.506615 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 20:17:21.509535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 20:17:21.509650 ==
2693 20:17:21.509741 RX Vref Scan: 1
2694 20:17:21.509828
2695 20:17:21.513177 Set Vref Range= 32 -> 127
2696 20:17:21.513260
2697 20:17:21.516495 RX Vref 32 -> 127, step: 1
2698 20:17:21.516577
2699 20:17:21.519875 RX Delay -13 -> 252, step: 4
2700 20:17:21.519957
2701 20:17:21.523088 Set Vref, RX VrefLevel [Byte0]: 32
2702 20:17:21.526214 [Byte1]: 32
2703 20:17:21.526296
2704 20:17:21.529763 Set Vref, RX VrefLevel [Byte0]: 33
2705 20:17:21.532827 [Byte1]: 33
2706 20:17:21.532938
2707 20:17:21.536440 Set Vref, RX VrefLevel [Byte0]: 34
2708 20:17:21.539680 [Byte1]: 34
2709 20:17:21.543908
2710 20:17:21.544029 Set Vref, RX VrefLevel [Byte0]: 35
2711 20:17:21.546988 [Byte1]: 35
2712 20:17:21.551984
2713 20:17:21.552093 Set Vref, RX VrefLevel [Byte0]: 36
2714 20:17:21.555046 [Byte1]: 36
2715 20:17:21.559978
2716 20:17:21.560086 Set Vref, RX VrefLevel [Byte0]: 37
2717 20:17:21.563024 [Byte1]: 37
2718 20:17:21.567571
2719 20:17:21.567652 Set Vref, RX VrefLevel [Byte0]: 38
2720 20:17:21.571141 [Byte1]: 38
2721 20:17:21.575515
2722 20:17:21.575597 Set Vref, RX VrefLevel [Byte0]: 39
2723 20:17:21.579012 [Byte1]: 39
2724 20:17:21.583371
2725 20:17:21.583453 Set Vref, RX VrefLevel [Byte0]: 40
2726 20:17:21.586851 [Byte1]: 40
2727 20:17:21.591209
2728 20:17:21.591307 Set Vref, RX VrefLevel [Byte0]: 41
2729 20:17:21.594284 [Byte1]: 41
2730 20:17:21.599364
2731 20:17:21.599459 Set Vref, RX VrefLevel [Byte0]: 42
2732 20:17:21.602152 [Byte1]: 42
2733 20:17:21.607116
2734 20:17:21.607198 Set Vref, RX VrefLevel [Byte0]: 43
2735 20:17:21.610094 [Byte1]: 43
2736 20:17:21.614960
2737 20:17:21.617936 Set Vref, RX VrefLevel [Byte0]: 44
2738 20:17:21.618019 [Byte1]: 44
2739 20:17:21.622755
2740 20:17:21.622852 Set Vref, RX VrefLevel [Byte0]: 45
2741 20:17:21.626349 [Byte1]: 45
2742 20:17:21.630753
2743 20:17:21.630850 Set Vref, RX VrefLevel [Byte0]: 46
2744 20:17:21.633763 [Byte1]: 46
2745 20:17:21.638727
2746 20:17:21.638814 Set Vref, RX VrefLevel [Byte0]: 47
2747 20:17:21.641564 [Byte1]: 47
2748 20:17:21.646439
2749 20:17:21.646521 Set Vref, RX VrefLevel [Byte0]: 48
2750 20:17:21.649613 [Byte1]: 48
2751 20:17:21.654483
2752 20:17:21.654565 Set Vref, RX VrefLevel [Byte0]: 49
2753 20:17:21.657606 [Byte1]: 49
2754 20:17:21.662225
2755 20:17:21.662307 Set Vref, RX VrefLevel [Byte0]: 50
2756 20:17:21.665252 [Byte1]: 50
2757 20:17:21.670635
2758 20:17:21.670717 Set Vref, RX VrefLevel [Byte0]: 51
2759 20:17:21.673309 [Byte1]: 51
2760 20:17:21.678264
2761 20:17:21.678359 Set Vref, RX VrefLevel [Byte0]: 52
2762 20:17:21.681560 [Byte1]: 52
2763 20:17:21.685763
2764 20:17:21.685844 Set Vref, RX VrefLevel [Byte0]: 53
2765 20:17:21.689095 [Byte1]: 53
2766 20:17:21.693598
2767 20:17:21.693679 Set Vref, RX VrefLevel [Byte0]: 54
2768 20:17:21.697364 [Byte1]: 54
2769 20:17:21.701478
2770 20:17:21.701560 Set Vref, RX VrefLevel [Byte0]: 55
2771 20:17:21.705041 [Byte1]: 55
2772 20:17:21.709225
2773 20:17:21.709329 Set Vref, RX VrefLevel [Byte0]: 56
2774 20:17:21.713089 [Byte1]: 56
2775 20:17:21.717196
2776 20:17:21.717279 Set Vref, RX VrefLevel [Byte0]: 57
2777 20:17:21.720890 [Byte1]: 57
2778 20:17:21.725672
2779 20:17:21.725754 Set Vref, RX VrefLevel [Byte0]: 58
2780 20:17:21.728829 [Byte1]: 58
2781 20:17:21.733032
2782 20:17:21.733114 Set Vref, RX VrefLevel [Byte0]: 59
2783 20:17:21.736516 [Byte1]: 59
2784 20:17:21.741218
2785 20:17:21.741300 Set Vref, RX VrefLevel [Byte0]: 60
2786 20:17:21.744199 [Byte1]: 60
2787 20:17:21.748872
2788 20:17:21.748954 Set Vref, RX VrefLevel [Byte0]: 61
2789 20:17:21.752524 [Byte1]: 61
2790 20:17:21.756835
2791 20:17:21.756917 Set Vref, RX VrefLevel [Byte0]: 62
2792 20:17:21.760541 [Byte1]: 62
2793 20:17:21.764974
2794 20:17:21.765056 Set Vref, RX VrefLevel [Byte0]: 63
2795 20:17:21.768390 [Byte1]: 63
2796 20:17:21.772696
2797 20:17:21.772778 Set Vref, RX VrefLevel [Byte0]: 64
2798 20:17:21.776322 [Byte1]: 64
2799 20:17:21.780609
2800 20:17:21.780690 Set Vref, RX VrefLevel [Byte0]: 65
2801 20:17:21.784159 [Byte1]: 65
2802 20:17:21.788658
2803 20:17:21.788740 Set Vref, RX VrefLevel [Byte0]: 66
2804 20:17:21.791831 [Byte1]: 66
2805 20:17:21.796241
2806 20:17:21.796350 Set Vref, RX VrefLevel [Byte0]: 67
2807 20:17:21.799768 [Byte1]: 67
2808 20:17:21.803989
2809 20:17:21.804071 Set Vref, RX VrefLevel [Byte0]: 68
2810 20:17:21.807580 [Byte1]: 68
2811 20:17:21.811853
2812 20:17:21.815158 Set Vref, RX VrefLevel [Byte0]: 69
2813 20:17:21.818714 [Byte1]: 69
2814 20:17:21.818796
2815 20:17:21.821800 Set Vref, RX VrefLevel [Byte0]: 70
2816 20:17:21.825382 [Byte1]: 70
2817 20:17:21.825465
2818 20:17:21.828953 Set Vref, RX VrefLevel [Byte0]: 71
2819 20:17:21.831956 [Byte1]: 71
2820 20:17:21.835734
2821 20:17:21.835855 Final RX Vref Byte 0 = 56 to rank0
2822 20:17:21.839386 Final RX Vref Byte 1 = 57 to rank0
2823 20:17:21.842277 Final RX Vref Byte 0 = 56 to rank1
2824 20:17:21.845695 Final RX Vref Byte 1 = 57 to rank1==
2825 20:17:21.849264 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 20:17:21.855702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 20:17:21.855786 ==
2828 20:17:21.855866 DQS Delay:
2829 20:17:21.855956 DQS0 = 0, DQS1 = 0
2830 20:17:21.859141 DQM Delay:
2831 20:17:21.859224 DQM0 = 120, DQM1 = 113
2832 20:17:21.862825 DQ Delay:
2833 20:17:21.865952 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2834 20:17:21.869038 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2835 20:17:21.872673 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2836 20:17:21.876229 DQ12 =120, DQ13 =118, DQ14 =126, DQ15 =122
2837 20:17:21.876370
2838 20:17:21.876437
2839 20:17:21.882315 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2840 20:17:21.886099 CH0 RK0: MR19=404, MR18=140D
2841 20:17:21.892797 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2842 20:17:21.892881
2843 20:17:21.896103 ----->DramcWriteLeveling(PI) begin...
2844 20:17:21.896213 ==
2845 20:17:21.899011 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 20:17:21.902775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 20:17:21.906125 ==
2848 20:17:21.906208 Write leveling (Byte 0): 33 => 33
2849 20:17:21.909281 Write leveling (Byte 1): 28 => 28
2850 20:17:21.912793 DramcWriteLeveling(PI) end<-----
2851 20:17:21.912875
2852 20:17:21.912941 ==
2853 20:17:21.916183 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 20:17:21.922685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 20:17:21.922768 ==
2856 20:17:21.922833 [Gating] SW mode calibration
2857 20:17:21.932709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 20:17:21.936233 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 20:17:21.939422 0 15 0 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (0 0)
2860 20:17:21.946136 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 20:17:21.949534 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 20:17:21.952610 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 20:17:21.959254 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 20:17:21.962737 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 20:17:21.966071 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2866 20:17:21.973031 0 15 28 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 1)
2867 20:17:21.976067 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2868 20:17:21.979465 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 20:17:21.986049 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 20:17:21.989812 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 20:17:21.992864 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 20:17:21.999620 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 20:17:22.002644 1 0 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
2874 20:17:22.006316 1 0 28 | B1->B0 | 3636 3636 | 0 1 | (0 0) (0 0)
2875 20:17:22.009707 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2876 20:17:22.016551 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 20:17:22.019586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 20:17:22.023291 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 20:17:22.029794 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 20:17:22.033258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 20:17:22.036621 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 20:17:22.042987 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2883 20:17:22.046392 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 20:17:22.049519 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 20:17:22.056116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 20:17:22.059411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 20:17:22.062721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 20:17:22.069423 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 20:17:22.073264 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 20:17:22.076317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 20:17:22.082927 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 20:17:22.086308 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 20:17:22.089441 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 20:17:22.093110 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 20:17:22.099805 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 20:17:22.103009 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 20:17:22.106052 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 20:17:22.112993 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2899 20:17:22.116591 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2900 20:17:22.119513 Total UI for P1: 0, mck2ui 16
2901 20:17:22.123043 best dqsien dly found for B1: ( 1, 3, 28)
2902 20:17:22.126360 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 20:17:22.129991 Total UI for P1: 0, mck2ui 16
2904 20:17:22.133245 best dqsien dly found for B0: ( 1, 3, 30)
2905 20:17:22.136586 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2906 20:17:22.139921 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2907 20:17:22.140020
2908 20:17:22.146574 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2909 20:17:22.149565 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2910 20:17:22.149647 [Gating] SW calibration Done
2911 20:17:22.153028 ==
2912 20:17:22.156211 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 20:17:22.159807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 20:17:22.159889 ==
2915 20:17:22.159953 RX Vref Scan: 0
2916 20:17:22.160014
2917 20:17:22.163107 RX Vref 0 -> 0, step: 1
2918 20:17:22.163189
2919 20:17:22.166252 RX Delay -40 -> 252, step: 8
2920 20:17:22.169859 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2921 20:17:22.173240 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2922 20:17:22.176217 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2923 20:17:22.183276 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2924 20:17:22.186470 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2925 20:17:22.189829 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2926 20:17:22.193220 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2927 20:17:22.196417 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2928 20:17:22.203204 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2929 20:17:22.206796 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2930 20:17:22.210052 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2931 20:17:22.213003 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2932 20:17:22.216706 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2933 20:17:22.223605 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2934 20:17:22.226699 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2935 20:17:22.230454 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2936 20:17:22.230538 ==
2937 20:17:22.233405 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 20:17:22.236852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 20:17:22.236963 ==
2940 20:17:22.240199 DQS Delay:
2941 20:17:22.240315 DQS0 = 0, DQS1 = 0
2942 20:17:22.240385 DQM Delay:
2943 20:17:22.243370 DQM0 = 122, DQM1 = 113
2944 20:17:22.243453 DQ Delay:
2945 20:17:22.247042 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2946 20:17:22.250217 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2947 20:17:22.253457 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
2948 20:17:22.260184 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2949 20:17:22.260301
2950 20:17:22.260376
2951 20:17:22.260440 ==
2952 20:17:22.263868 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 20:17:22.266812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 20:17:22.266896 ==
2955 20:17:22.266965
2956 20:17:22.267027
2957 20:17:22.270238 TX Vref Scan disable
2958 20:17:22.270322 == TX Byte 0 ==
2959 20:17:22.277181 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 20:17:22.280571 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 20:17:22.280655 == TX Byte 1 ==
2962 20:17:22.287349 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2963 20:17:22.290491 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2964 20:17:22.290575 ==
2965 20:17:22.294044 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 20:17:22.297018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 20:17:22.297120 ==
2968 20:17:22.309838 TX Vref=22, minBit 1, minWin=25, winSum=413
2969 20:17:22.313558 TX Vref=24, minBit 12, minWin=25, winSum=416
2970 20:17:22.316780 TX Vref=26, minBit 10, minWin=25, winSum=422
2971 20:17:22.320428 TX Vref=28, minBit 1, minWin=26, winSum=423
2972 20:17:22.323393 TX Vref=30, minBit 1, minWin=26, winSum=422
2973 20:17:22.330127 TX Vref=32, minBit 0, minWin=26, winSum=424
2974 20:17:22.333763 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
2975 20:17:22.333846
2976 20:17:22.336923 Final TX Range 1 Vref 32
2977 20:17:22.337064
2978 20:17:22.337159 ==
2979 20:17:22.339958 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 20:17:22.343664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 20:17:22.343779 ==
2982 20:17:22.346717
2983 20:17:22.346823
2984 20:17:22.346952 TX Vref Scan disable
2985 20:17:22.350089 == TX Byte 0 ==
2986 20:17:22.353502 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2987 20:17:22.356631 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2988 20:17:22.359831 == TX Byte 1 ==
2989 20:17:22.362998 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2990 20:17:22.366502 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2991 20:17:22.370146
2992 20:17:22.370227 [DATLAT]
2993 20:17:22.370292 Freq=1200, CH0 RK1
2994 20:17:22.370353
2995 20:17:22.373611 DATLAT Default: 0xd
2996 20:17:22.373693 0, 0xFFFF, sum = 0
2997 20:17:22.377049 1, 0xFFFF, sum = 0
2998 20:17:22.377132 2, 0xFFFF, sum = 0
2999 20:17:22.379875 3, 0xFFFF, sum = 0
3000 20:17:22.379959 4, 0xFFFF, sum = 0
3001 20:17:22.383427 5, 0xFFFF, sum = 0
3002 20:17:22.386936 6, 0xFFFF, sum = 0
3003 20:17:22.387020 7, 0xFFFF, sum = 0
3004 20:17:22.390221 8, 0xFFFF, sum = 0
3005 20:17:22.390304 9, 0xFFFF, sum = 0
3006 20:17:22.393956 10, 0xFFFF, sum = 0
3007 20:17:22.394039 11, 0xFFFF, sum = 0
3008 20:17:22.396979 12, 0x0, sum = 1
3009 20:17:22.397062 13, 0x0, sum = 2
3010 20:17:22.399963 14, 0x0, sum = 3
3011 20:17:22.400046 15, 0x0, sum = 4
3012 20:17:22.400112 best_step = 13
3013 20:17:22.400172
3014 20:17:22.403792 ==
3015 20:17:22.406689 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 20:17:22.409923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 20:17:22.410079 ==
3018 20:17:22.410223 RX Vref Scan: 0
3019 20:17:22.410377
3020 20:17:22.413729 RX Vref 0 -> 0, step: 1
3021 20:17:22.413847
3022 20:17:22.416613 RX Delay -13 -> 252, step: 4
3023 20:17:22.420003 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3024 20:17:22.426989 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3025 20:17:22.429996 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3026 20:17:22.433505 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3027 20:17:22.437363 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3028 20:17:22.440485 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3029 20:17:22.443515 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3030 20:17:22.450189 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3031 20:17:22.453864 iDelay=195, Bit 8, Center 104 (39 ~ 170) 132
3032 20:17:22.456873 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3033 20:17:22.460613 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3034 20:17:22.463517 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3035 20:17:22.470494 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3036 20:17:22.473588 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3037 20:17:22.477242 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3038 20:17:22.480753 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3039 20:17:22.480838 ==
3040 20:17:22.483838 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 20:17:22.487172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 20:17:22.490723 ==
3043 20:17:22.490808 DQS Delay:
3044 20:17:22.490895 DQS0 = 0, DQS1 = 0
3045 20:17:22.493546 DQM Delay:
3046 20:17:22.493631 DQM0 = 121, DQM1 = 112
3047 20:17:22.497716 DQ Delay:
3048 20:17:22.500744 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3049 20:17:22.503807 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3050 20:17:22.507487 DQ8 =104, DQ9 =100, DQ10 =112, DQ11 =104
3051 20:17:22.510529 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3052 20:17:22.510615
3053 20:17:22.510701
3054 20:17:22.517318 [DQSOSCAuto] RK1, (LSB)MR18= 0xeee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3055 20:17:22.520546 CH0 RK1: MR19=403, MR18=EEE
3056 20:17:22.527429 CH0_RK1: MR19=0x403, MR18=0xEEE, DQSOSC=404, MR23=63, INC=40, DEC=26
3057 20:17:22.530642 [RxdqsGatingPostProcess] freq 1200
3058 20:17:22.537035 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 20:17:22.540251 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 20:17:22.540373 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 20:17:22.543639 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 20:17:22.547106 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 20:17:22.550557 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 20:17:22.553899 best DQS1 dly(2T, 0.5T) = (0, 11)
3065 20:17:22.557038 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 20:17:22.560790 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3067 20:17:22.563757 Pre-setting of DQS Precalculation
3068 20:17:22.570550 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 20:17:22.570633 ==
3070 20:17:22.573634 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 20:17:22.577146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 20:17:22.577229 ==
3073 20:17:22.580622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 20:17:22.587253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 20:17:22.596379 [CA 0] Center 37 (7~68) winsize 62
3076 20:17:22.599650 [CA 1] Center 37 (7~68) winsize 62
3077 20:17:22.602873 [CA 2] Center 35 (5~65) winsize 61
3078 20:17:22.606358 [CA 3] Center 34 (4~64) winsize 61
3079 20:17:22.609985 [CA 4] Center 34 (4~64) winsize 61
3080 20:17:22.613081 [CA 5] Center 33 (3~63) winsize 61
3081 20:17:22.613167
3082 20:17:22.616809 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 20:17:22.616894
3084 20:17:22.619796 [CATrainingPosCal] consider 1 rank data
3085 20:17:22.623475 u2DelayCellTimex100 = 270/100 ps
3086 20:17:22.626629 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 20:17:22.629765 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 20:17:22.636494 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 20:17:22.639527 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 20:17:22.643013 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 20:17:22.646428 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3092 20:17:22.646513
3093 20:17:22.649621 CA PerBit enable=1, Macro0, CA PI delay=33
3094 20:17:22.649699
3095 20:17:22.653128 [CBTSetCACLKResult] CA Dly = 33
3096 20:17:22.653210 CS Dly: 7 (0~38)
3097 20:17:22.653275 ==
3098 20:17:22.656812 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 20:17:22.663185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 20:17:22.663268 ==
3101 20:17:22.666402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 20:17:22.673256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 20:17:22.682182 [CA 0] Center 37 (7~68) winsize 62
3104 20:17:22.685625 [CA 1] Center 38 (8~68) winsize 61
3105 20:17:22.688793 [CA 2] Center 35 (5~65) winsize 61
3106 20:17:22.692594 [CA 3] Center 34 (4~65) winsize 62
3107 20:17:22.695425 [CA 4] Center 34 (4~65) winsize 62
3108 20:17:22.698957 [CA 5] Center 34 (4~64) winsize 61
3109 20:17:22.699040
3110 20:17:22.701786 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 20:17:22.701868
3112 20:17:22.705286 [CATrainingPosCal] consider 2 rank data
3113 20:17:22.708523 u2DelayCellTimex100 = 270/100 ps
3114 20:17:22.711832 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 20:17:22.715676 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 20:17:22.722026 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 20:17:22.725162 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 20:17:22.729071 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 20:17:22.732201 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3120 20:17:22.732347
3121 20:17:22.735367 CA PerBit enable=1, Macro0, CA PI delay=33
3122 20:17:22.735450
3123 20:17:22.738549 [CBTSetCACLKResult] CA Dly = 33
3124 20:17:22.738631 CS Dly: 8 (0~40)
3125 20:17:22.738726
3126 20:17:22.741865 ----->DramcWriteLeveling(PI) begin...
3127 20:17:22.745521 ==
3128 20:17:22.748347 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 20:17:22.751713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 20:17:22.751822 ==
3131 20:17:22.755317 Write leveling (Byte 0): 25 => 25
3132 20:17:22.758422 Write leveling (Byte 1): 30 => 30
3133 20:17:22.762152 DramcWriteLeveling(PI) end<-----
3134 20:17:22.762235
3135 20:17:22.762300 ==
3136 20:17:22.765168 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 20:17:22.768850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 20:17:22.768935 ==
3139 20:17:22.772220 [Gating] SW mode calibration
3140 20:17:22.778364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 20:17:22.782012 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 20:17:22.788774 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3143 20:17:22.791705 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 20:17:22.795342 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 20:17:22.801651 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 20:17:22.805294 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 20:17:22.808640 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 20:17:22.815578 0 15 24 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 1)
3149 20:17:22.818796 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3150 20:17:22.821717 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 20:17:22.828441 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 20:17:22.832176 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 20:17:22.835364 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 20:17:22.842030 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 20:17:22.845133 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 20:17:22.848884 1 0 24 | B1->B0 | 3131 3f3e | 0 1 | (1 1) (0 0)
3157 20:17:22.855368 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 20:17:22.858801 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 20:17:22.861804 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 20:17:22.868561 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 20:17:22.872050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 20:17:22.875083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 20:17:22.878800 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 20:17:22.885109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 20:17:22.888434 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3166 20:17:22.891985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 20:17:22.898694 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 20:17:22.902472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 20:17:22.905672 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 20:17:22.912310 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 20:17:22.915852 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 20:17:22.919265 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 20:17:22.925525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 20:17:22.929084 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 20:17:22.932389 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 20:17:22.935810 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 20:17:22.942850 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 20:17:22.945897 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 20:17:22.949473 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 20:17:22.955734 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3181 20:17:22.959354 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3182 20:17:22.962834 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 20:17:22.965627 Total UI for P1: 0, mck2ui 16
3184 20:17:22.969216 best dqsien dly found for B0: ( 1, 3, 26)
3185 20:17:22.972328 Total UI for P1: 0, mck2ui 16
3186 20:17:22.975911 best dqsien dly found for B1: ( 1, 3, 28)
3187 20:17:22.979562 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3188 20:17:22.982570 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3189 20:17:22.982653
3190 20:17:22.989096 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3191 20:17:22.992439 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3192 20:17:22.992522 [Gating] SW calibration Done
3193 20:17:22.996014 ==
3194 20:17:22.996096 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 20:17:23.002780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 20:17:23.002863 ==
3197 20:17:23.002928 RX Vref Scan: 0
3198 20:17:23.002989
3199 20:17:23.006052 RX Vref 0 -> 0, step: 1
3200 20:17:23.006135
3201 20:17:23.009198 RX Delay -40 -> 252, step: 8
3202 20:17:23.012846 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3203 20:17:23.016040 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3204 20:17:23.019411 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3205 20:17:23.026094 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3206 20:17:23.029253 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3207 20:17:23.032904 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3208 20:17:23.035923 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3209 20:17:23.039575 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3210 20:17:23.043014 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3211 20:17:23.049367 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3212 20:17:23.052680 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3213 20:17:23.056380 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3214 20:17:23.059454 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3215 20:17:23.065974 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3216 20:17:23.069587 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3217 20:17:23.072951 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3218 20:17:23.073034 ==
3219 20:17:23.076009 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 20:17:23.079655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 20:17:23.079738 ==
3222 20:17:23.082731 DQS Delay:
3223 20:17:23.082814 DQS0 = 0, DQS1 = 0
3224 20:17:23.082879 DQM Delay:
3225 20:17:23.086368 DQM0 = 119, DQM1 = 116
3226 20:17:23.086492 DQ Delay:
3227 20:17:23.089370 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3228 20:17:23.093279 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3229 20:17:23.099461 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3230 20:17:23.103125 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3231 20:17:23.103207
3232 20:17:23.103272
3233 20:17:23.103332 ==
3234 20:17:23.106315 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 20:17:23.109924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 20:17:23.110036 ==
3237 20:17:23.110130
3238 20:17:23.110219
3239 20:17:23.112963 TX Vref Scan disable
3240 20:17:23.113046 == TX Byte 0 ==
3241 20:17:23.119966 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3242 20:17:23.123180 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3243 20:17:23.123264 == TX Byte 1 ==
3244 20:17:23.129549 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3245 20:17:23.133451 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3246 20:17:23.133534 ==
3247 20:17:23.136603 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 20:17:23.139807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 20:17:23.139892 ==
3250 20:17:23.152807 TX Vref=22, minBit 9, minWin=24, winSum=409
3251 20:17:23.156060 TX Vref=24, minBit 9, minWin=25, winSum=416
3252 20:17:23.159418 TX Vref=26, minBit 9, minWin=24, winSum=422
3253 20:17:23.162761 TX Vref=28, minBit 1, minWin=26, winSum=427
3254 20:17:23.166217 TX Vref=30, minBit 9, minWin=26, winSum=431
3255 20:17:23.169302 TX Vref=32, minBit 9, minWin=26, winSum=432
3256 20:17:23.176121 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3257 20:17:23.176226
3258 20:17:23.179503 Final TX Range 1 Vref 32
3259 20:17:23.179587
3260 20:17:23.179651 ==
3261 20:17:23.183068 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 20:17:23.186493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 20:17:23.186576 ==
3264 20:17:23.186641
3265 20:17:23.186701
3266 20:17:23.189753 TX Vref Scan disable
3267 20:17:23.192869 == TX Byte 0 ==
3268 20:17:23.196616 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3269 20:17:23.199705 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3270 20:17:23.202765 == TX Byte 1 ==
3271 20:17:23.206538 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3272 20:17:23.209620 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3273 20:17:23.209728
3274 20:17:23.212694 [DATLAT]
3275 20:17:23.212778 Freq=1200, CH1 RK0
3276 20:17:23.212889
3277 20:17:23.216276 DATLAT Default: 0xd
3278 20:17:23.216400 0, 0xFFFF, sum = 0
3279 20:17:23.219406 1, 0xFFFF, sum = 0
3280 20:17:23.219492 2, 0xFFFF, sum = 0
3281 20:17:23.223146 3, 0xFFFF, sum = 0
3282 20:17:23.223232 4, 0xFFFF, sum = 0
3283 20:17:23.226262 5, 0xFFFF, sum = 0
3284 20:17:23.226349 6, 0xFFFF, sum = 0
3285 20:17:23.229857 7, 0xFFFF, sum = 0
3286 20:17:23.229943 8, 0xFFFF, sum = 0
3287 20:17:23.233228 9, 0xFFFF, sum = 0
3288 20:17:23.233315 10, 0xFFFF, sum = 0
3289 20:17:23.236431 11, 0xFFFF, sum = 0
3290 20:17:23.236516 12, 0x0, sum = 1
3291 20:17:23.240067 13, 0x0, sum = 2
3292 20:17:23.240189 14, 0x0, sum = 3
3293 20:17:23.242932 15, 0x0, sum = 4
3294 20:17:23.243017 best_step = 13
3295 20:17:23.243103
3296 20:17:23.243183 ==
3297 20:17:23.246240 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 20:17:23.253063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 20:17:23.253151 ==
3300 20:17:23.253217 RX Vref Scan: 1
3301 20:17:23.253278
3302 20:17:23.256600 Set Vref Range= 32 -> 127
3303 20:17:23.256682
3304 20:17:23.259862 RX Vref 32 -> 127, step: 1
3305 20:17:23.259943
3306 20:17:23.260007 RX Delay -5 -> 252, step: 4
3307 20:17:23.260067
3308 20:17:23.263166 Set Vref, RX VrefLevel [Byte0]: 32
3309 20:17:23.266310 [Byte1]: 32
3310 20:17:23.271000
3311 20:17:23.271083 Set Vref, RX VrefLevel [Byte0]: 33
3312 20:17:23.273933 [Byte1]: 33
3313 20:17:23.278852
3314 20:17:23.278933 Set Vref, RX VrefLevel [Byte0]: 34
3315 20:17:23.282058 [Byte1]: 34
3316 20:17:23.286642
3317 20:17:23.286747 Set Vref, RX VrefLevel [Byte0]: 35
3318 20:17:23.289891 [Byte1]: 35
3319 20:17:23.294284
3320 20:17:23.294366 Set Vref, RX VrefLevel [Byte0]: 36
3321 20:17:23.297851 [Byte1]: 36
3322 20:17:23.302209
3323 20:17:23.302319 Set Vref, RX VrefLevel [Byte0]: 37
3324 20:17:23.305317 [Byte1]: 37
3325 20:17:23.310145
3326 20:17:23.310254 Set Vref, RX VrefLevel [Byte0]: 38
3327 20:17:23.313365 [Byte1]: 38
3328 20:17:23.317737
3329 20:17:23.317819 Set Vref, RX VrefLevel [Byte0]: 39
3330 20:17:23.321388 [Byte1]: 39
3331 20:17:23.325644
3332 20:17:23.325726 Set Vref, RX VrefLevel [Byte0]: 40
3333 20:17:23.329295 [Byte1]: 40
3334 20:17:23.333544
3335 20:17:23.333626 Set Vref, RX VrefLevel [Byte0]: 41
3336 20:17:23.337072 [Byte1]: 41
3337 20:17:23.341453
3338 20:17:23.341534 Set Vref, RX VrefLevel [Byte0]: 42
3339 20:17:23.345183 [Byte1]: 42
3340 20:17:23.349184
3341 20:17:23.349265 Set Vref, RX VrefLevel [Byte0]: 43
3342 20:17:23.352888 [Byte1]: 43
3343 20:17:23.356964
3344 20:17:23.357066 Set Vref, RX VrefLevel [Byte0]: 44
3345 20:17:23.360548 [Byte1]: 44
3346 20:17:23.364828
3347 20:17:23.364910 Set Vref, RX VrefLevel [Byte0]: 45
3348 20:17:23.368242 [Byte1]: 45
3349 20:17:23.372799
3350 20:17:23.372881 Set Vref, RX VrefLevel [Byte0]: 46
3351 20:17:23.376572 [Byte1]: 46
3352 20:17:23.380625
3353 20:17:23.380710 Set Vref, RX VrefLevel [Byte0]: 47
3354 20:17:23.384113 [Byte1]: 47
3355 20:17:23.388741
3356 20:17:23.388822 Set Vref, RX VrefLevel [Byte0]: 48
3357 20:17:23.391711 [Byte1]: 48
3358 20:17:23.396519
3359 20:17:23.396600 Set Vref, RX VrefLevel [Byte0]: 49
3360 20:17:23.399611 [Byte1]: 49
3361 20:17:23.404419
3362 20:17:23.404534 Set Vref, RX VrefLevel [Byte0]: 50
3363 20:17:23.407649 [Byte1]: 50
3364 20:17:23.412006
3365 20:17:23.412090 Set Vref, RX VrefLevel [Byte0]: 51
3366 20:17:23.415126 [Byte1]: 51
3367 20:17:23.420266
3368 20:17:23.420374 Set Vref, RX VrefLevel [Byte0]: 52
3369 20:17:23.423386 [Byte1]: 52
3370 20:17:23.427679
3371 20:17:23.427761 Set Vref, RX VrefLevel [Byte0]: 53
3372 20:17:23.430900 [Byte1]: 53
3373 20:17:23.435617
3374 20:17:23.435698 Set Vref, RX VrefLevel [Byte0]: 54
3375 20:17:23.438857 [Byte1]: 54
3376 20:17:23.443635
3377 20:17:23.443716 Set Vref, RX VrefLevel [Byte0]: 55
3378 20:17:23.446703 [Byte1]: 55
3379 20:17:23.451636
3380 20:17:23.451718 Set Vref, RX VrefLevel [Byte0]: 56
3381 20:17:23.455111 [Byte1]: 56
3382 20:17:23.459357
3383 20:17:23.459438 Set Vref, RX VrefLevel [Byte0]: 57
3384 20:17:23.462259 [Byte1]: 57
3385 20:17:23.466964
3386 20:17:23.467045 Set Vref, RX VrefLevel [Byte0]: 58
3387 20:17:23.470693 [Byte1]: 58
3388 20:17:23.474934
3389 20:17:23.475016 Set Vref, RX VrefLevel [Byte0]: 59
3390 20:17:23.478209 [Byte1]: 59
3391 20:17:23.482920
3392 20:17:23.483004 Set Vref, RX VrefLevel [Byte0]: 60
3393 20:17:23.485941 [Byte1]: 60
3394 20:17:23.490801
3395 20:17:23.490882 Set Vref, RX VrefLevel [Byte0]: 61
3396 20:17:23.493838 [Byte1]: 61
3397 20:17:23.498880
3398 20:17:23.498961 Set Vref, RX VrefLevel [Byte0]: 62
3399 20:17:23.502197 [Byte1]: 62
3400 20:17:23.506703
3401 20:17:23.506784 Set Vref, RX VrefLevel [Byte0]: 63
3402 20:17:23.509702 [Byte1]: 63
3403 20:17:23.514154
3404 20:17:23.514262 Set Vref, RX VrefLevel [Byte0]: 64
3405 20:17:23.517553 [Byte1]: 64
3406 20:17:23.522198
3407 20:17:23.522279 Set Vref, RX VrefLevel [Byte0]: 65
3408 20:17:23.525468 [Byte1]: 65
3409 20:17:23.530091
3410 20:17:23.530177 Set Vref, RX VrefLevel [Byte0]: 66
3411 20:17:23.533213 [Byte1]: 66
3412 20:17:23.538289
3413 20:17:23.538371 Final RX Vref Byte 0 = 55 to rank0
3414 20:17:23.541286 Final RX Vref Byte 1 = 53 to rank0
3415 20:17:23.544209 Final RX Vref Byte 0 = 55 to rank1
3416 20:17:23.547854 Final RX Vref Byte 1 = 53 to rank1==
3417 20:17:23.551514 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 20:17:23.557657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 20:17:23.557765 ==
3420 20:17:23.557859 DQS Delay:
3421 20:17:23.557948 DQS0 = 0, DQS1 = 0
3422 20:17:23.561136 DQM Delay:
3423 20:17:23.561218 DQM0 = 120, DQM1 = 117
3424 20:17:23.564774 DQ Delay:
3425 20:17:23.568307 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3426 20:17:23.571179 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3427 20:17:23.574870 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3428 20:17:23.578067 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3429 20:17:23.578149
3430 20:17:23.578214
3431 20:17:23.584853 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3432 20:17:23.587598 CH1 RK0: MR19=304, MR18=FE11
3433 20:17:23.594622 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3434 20:17:23.594705
3435 20:17:23.597600 ----->DramcWriteLeveling(PI) begin...
3436 20:17:23.597711 ==
3437 20:17:23.601133 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 20:17:23.604781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 20:17:23.607778 ==
3440 20:17:23.607862 Write leveling (Byte 0): 24 => 24
3441 20:17:23.611087 Write leveling (Byte 1): 30 => 30
3442 20:17:23.614350 DramcWriteLeveling(PI) end<-----
3443 20:17:23.614435
3444 20:17:23.614538 ==
3445 20:17:23.618076 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 20:17:23.624719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 20:17:23.624805 ==
3448 20:17:23.624892 [Gating] SW mode calibration
3449 20:17:23.634576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 20:17:23.637709 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 20:17:23.641429 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 20:17:23.648052 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 20:17:23.651470 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 20:17:23.654683 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 20:17:23.660998 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 20:17:23.664696 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3457 20:17:23.667998 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (1 0) (0 1)
3458 20:17:23.674680 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 1)
3459 20:17:23.678165 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 20:17:23.681197 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 20:17:23.687959 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 20:17:23.691028 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 20:17:23.693852 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 20:17:23.701053 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3465 20:17:23.704134 1 0 24 | B1->B0 | 4343 2626 | 0 0 | (0 0) (0 0)
3466 20:17:23.707140 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3467 20:17:23.713700 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 20:17:23.717374 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 20:17:23.720743 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 20:17:23.727043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 20:17:23.730731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 20:17:23.733864 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3473 20:17:23.740273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3474 20:17:23.743899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3475 20:17:23.747446 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 20:17:23.753799 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 20:17:23.756904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 20:17:23.760228 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 20:17:23.766892 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 20:17:23.770637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 20:17:23.774003 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 20:17:23.780707 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 20:17:23.783994 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 20:17:23.787040 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 20:17:23.793725 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 20:17:23.796858 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 20:17:23.800557 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 20:17:23.803701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3489 20:17:23.810399 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3490 20:17:23.813864 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3491 20:17:23.816890 Total UI for P1: 0, mck2ui 16
3492 20:17:23.819959 best dqsien dly found for B1: ( 1, 3, 22)
3493 20:17:23.823624 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 20:17:23.827135 Total UI for P1: 0, mck2ui 16
3495 20:17:23.829958 best dqsien dly found for B0: ( 1, 3, 28)
3496 20:17:23.833391 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3497 20:17:23.840174 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3498 20:17:23.840259
3499 20:17:23.843175 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3500 20:17:23.846892 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3501 20:17:23.850079 [Gating] SW calibration Done
3502 20:17:23.850166 ==
3503 20:17:23.853162 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 20:17:23.856825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 20:17:23.856910 ==
3506 20:17:23.856997 RX Vref Scan: 0
3507 20:17:23.860399
3508 20:17:23.860483 RX Vref 0 -> 0, step: 1
3509 20:17:23.860569
3510 20:17:23.863455 RX Delay -40 -> 252, step: 8
3511 20:17:23.866880 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3512 20:17:23.869810 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3513 20:17:23.876501 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3514 20:17:23.880078 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3515 20:17:23.882947 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3516 20:17:23.886364 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 20:17:23.890049 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3518 20:17:23.896446 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3519 20:17:23.899928 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3520 20:17:23.903064 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3521 20:17:23.906628 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 20:17:23.909518 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3523 20:17:23.916088 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3524 20:17:23.919480 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3525 20:17:23.922975 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3526 20:17:23.926616 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3527 20:17:23.926724 ==
3528 20:17:23.929622 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 20:17:23.936242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 20:17:23.936373 ==
3531 20:17:23.936440 DQS Delay:
3532 20:17:23.939690 DQS0 = 0, DQS1 = 0
3533 20:17:23.939772 DQM Delay:
3534 20:17:23.942688 DQM0 = 120, DQM1 = 117
3535 20:17:23.942770 DQ Delay:
3536 20:17:23.946218 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3537 20:17:23.949809 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3538 20:17:23.952995 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3539 20:17:23.955902 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3540 20:17:23.956007
3541 20:17:23.956099
3542 20:17:23.956217 ==
3543 20:17:23.959510 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 20:17:23.966187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 20:17:23.966293 ==
3546 20:17:23.966384
3547 20:17:23.966480
3548 20:17:23.966571 TX Vref Scan disable
3549 20:17:23.969205 == TX Byte 0 ==
3550 20:17:23.972886 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3551 20:17:23.976000 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3552 20:17:23.979710 == TX Byte 1 ==
3553 20:17:23.982687 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3554 20:17:23.986198 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3555 20:17:23.989654 ==
3556 20:17:23.992799 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 20:17:23.996321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 20:17:23.996418 ==
3559 20:17:24.007651 TX Vref=22, minBit 2, minWin=25, winSum=423
3560 20:17:24.010793 TX Vref=24, minBit 9, minWin=25, winSum=423
3561 20:17:24.013888 TX Vref=26, minBit 1, minWin=26, winSum=426
3562 20:17:24.017254 TX Vref=28, minBit 9, minWin=26, winSum=433
3563 20:17:24.020925 TX Vref=30, minBit 4, minWin=26, winSum=434
3564 20:17:24.027463 TX Vref=32, minBit 9, minWin=26, winSum=436
3565 20:17:24.030370 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3566 20:17:24.030471
3567 20:17:24.033961 Final TX Range 1 Vref 32
3568 20:17:24.034043
3569 20:17:24.034113 ==
3570 20:17:24.037503 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 20:17:24.040513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 20:17:24.043878 ==
3573 20:17:24.043959
3574 20:17:24.044025
3575 20:17:24.044113 TX Vref Scan disable
3576 20:17:24.047526 == TX Byte 0 ==
3577 20:17:24.050426 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3578 20:17:24.057245 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3579 20:17:24.057332 == TX Byte 1 ==
3580 20:17:24.060795 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3581 20:17:24.066876 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3582 20:17:24.066959
3583 20:17:24.067023 [DATLAT]
3584 20:17:24.067083 Freq=1200, CH1 RK1
3585 20:17:24.067142
3586 20:17:24.070539 DATLAT Default: 0xd
3587 20:17:24.073649 0, 0xFFFF, sum = 0
3588 20:17:24.073732 1, 0xFFFF, sum = 0
3589 20:17:24.077286 2, 0xFFFF, sum = 0
3590 20:17:24.077368 3, 0xFFFF, sum = 0
3591 20:17:24.080414 4, 0xFFFF, sum = 0
3592 20:17:24.080497 5, 0xFFFF, sum = 0
3593 20:17:24.083428 6, 0xFFFF, sum = 0
3594 20:17:24.083541 7, 0xFFFF, sum = 0
3595 20:17:24.086964 8, 0xFFFF, sum = 0
3596 20:17:24.087048 9, 0xFFFF, sum = 0
3597 20:17:24.089991 10, 0xFFFF, sum = 0
3598 20:17:24.090075 11, 0xFFFF, sum = 0
3599 20:17:24.093568 12, 0x0, sum = 1
3600 20:17:24.093652 13, 0x0, sum = 2
3601 20:17:24.097077 14, 0x0, sum = 3
3602 20:17:24.097178 15, 0x0, sum = 4
3603 20:17:24.099889 best_step = 13
3604 20:17:24.099971
3605 20:17:24.100036 ==
3606 20:17:24.103736 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 20:17:24.106732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 20:17:24.106815 ==
3609 20:17:24.106880 RX Vref Scan: 0
3610 20:17:24.110027
3611 20:17:24.110108 RX Vref 0 -> 0, step: 1
3612 20:17:24.110174
3613 20:17:24.113396 RX Delay -5 -> 252, step: 4
3614 20:17:24.119946 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3615 20:17:24.123204 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3616 20:17:24.127002 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3617 20:17:24.129892 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3618 20:17:24.133519 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3619 20:17:24.136421 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 20:17:24.143175 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3621 20:17:24.146493 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3622 20:17:24.149962 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3623 20:17:24.153177 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3624 20:17:24.156786 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3625 20:17:24.163438 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3626 20:17:24.166650 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3627 20:17:24.169638 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3628 20:17:24.173466 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3629 20:17:24.179538 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3630 20:17:24.179622 ==
3631 20:17:24.183097 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 20:17:24.186172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 20:17:24.186283 ==
3634 20:17:24.186365 DQS Delay:
3635 20:17:24.189849 DQS0 = 0, DQS1 = 0
3636 20:17:24.189932 DQM Delay:
3637 20:17:24.192759 DQM0 = 120, DQM1 = 118
3638 20:17:24.192867 DQ Delay:
3639 20:17:24.196557 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3640 20:17:24.199693 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3641 20:17:24.203460 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3642 20:17:24.206298 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3643 20:17:24.206380
3644 20:17:24.206445
3645 20:17:24.215999 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3646 20:17:24.219438 CH1 RK1: MR19=403, MR18=14F0
3647 20:17:24.226204 CH1_RK1: MR19=0x403, MR18=0x14F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3648 20:17:24.226314 [RxdqsGatingPostProcess] freq 1200
3649 20:17:24.232887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 20:17:24.236170 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 20:17:24.239742 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 20:17:24.242984 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 20:17:24.245977 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 20:17:24.249565 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 20:17:24.252759 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 20:17:24.256096 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 20:17:24.259340 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 20:17:24.263036 Pre-setting of DQS Precalculation
3659 20:17:24.266245 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 20:17:24.272780 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 20:17:24.279534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 20:17:24.279617
3663 20:17:24.279682
3664 20:17:24.283119 [Calibration Summary] 2400 Mbps
3665 20:17:24.286620 CH 0, Rank 0
3666 20:17:24.286702 SW Impedance : PASS
3667 20:17:24.289390 DUTY Scan : NO K
3668 20:17:24.293078 ZQ Calibration : PASS
3669 20:17:24.293160 Jitter Meter : NO K
3670 20:17:24.295935 CBT Training : PASS
3671 20:17:24.299426 Write leveling : PASS
3672 20:17:24.299508 RX DQS gating : PASS
3673 20:17:24.303078 RX DQ/DQS(RDDQC) : PASS
3674 20:17:24.305995 TX DQ/DQS : PASS
3675 20:17:24.306077 RX DATLAT : PASS
3676 20:17:24.309491 RX DQ/DQS(Engine): PASS
3677 20:17:24.312561 TX OE : NO K
3678 20:17:24.312688 All Pass.
3679 20:17:24.312803
3680 20:17:24.312911 CH 0, Rank 1
3681 20:17:24.316430 SW Impedance : PASS
3682 20:17:24.319312 DUTY Scan : NO K
3683 20:17:24.319432 ZQ Calibration : PASS
3684 20:17:24.322973 Jitter Meter : NO K
3685 20:17:24.323095 CBT Training : PASS
3686 20:17:24.325868 Write leveling : PASS
3687 20:17:24.329232 RX DQS gating : PASS
3688 20:17:24.329353 RX DQ/DQS(RDDQC) : PASS
3689 20:17:24.332993 TX DQ/DQS : PASS
3690 20:17:24.335946 RX DATLAT : PASS
3691 20:17:24.336064 RX DQ/DQS(Engine): PASS
3692 20:17:24.339692 TX OE : NO K
3693 20:17:24.339813 All Pass.
3694 20:17:24.339925
3695 20:17:24.342643 CH 1, Rank 0
3696 20:17:24.342822 SW Impedance : PASS
3697 20:17:24.345921 DUTY Scan : NO K
3698 20:17:24.349530 ZQ Calibration : PASS
3699 20:17:24.349652 Jitter Meter : NO K
3700 20:17:24.353076 CBT Training : PASS
3701 20:17:24.356242 Write leveling : PASS
3702 20:17:24.356401 RX DQS gating : PASS
3703 20:17:24.359191 RX DQ/DQS(RDDQC) : PASS
3704 20:17:24.359309 TX DQ/DQS : PASS
3705 20:17:24.362533 RX DATLAT : PASS
3706 20:17:24.366455 RX DQ/DQS(Engine): PASS
3707 20:17:24.366577 TX OE : NO K
3708 20:17:24.369362 All Pass.
3709 20:17:24.369483
3710 20:17:24.369595 CH 1, Rank 1
3711 20:17:24.373126 SW Impedance : PASS
3712 20:17:24.373248 DUTY Scan : NO K
3713 20:17:24.376134 ZQ Calibration : PASS
3714 20:17:24.379424 Jitter Meter : NO K
3715 20:17:24.379546 CBT Training : PASS
3716 20:17:24.382622 Write leveling : PASS
3717 20:17:24.386175 RX DQS gating : PASS
3718 20:17:24.386297 RX DQ/DQS(RDDQC) : PASS
3719 20:17:24.389229 TX DQ/DQS : PASS
3720 20:17:24.393025 RX DATLAT : PASS
3721 20:17:24.393149 RX DQ/DQS(Engine): PASS
3722 20:17:24.396233 TX OE : NO K
3723 20:17:24.396391 All Pass.
3724 20:17:24.396504
3725 20:17:24.399233 DramC Write-DBI off
3726 20:17:24.402947 PER_BANK_REFRESH: Hybrid Mode
3727 20:17:24.403097 TX_TRACKING: ON
3728 20:17:24.412875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 20:17:24.415833 [FAST_K] Save calibration result to emmc
3730 20:17:24.419567 dramc_set_vcore_voltage set vcore to 650000
3731 20:17:24.422629 Read voltage for 600, 5
3732 20:17:24.422743 Vio18 = 0
3733 20:17:24.422823 Vcore = 650000
3734 20:17:24.426457 Vdram = 0
3735 20:17:24.426557 Vddq = 0
3736 20:17:24.426655 Vmddr = 0
3737 20:17:24.432737 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 20:17:24.435837 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 20:17:24.439589 MEM_TYPE=3, freq_sel=19
3740 20:17:24.442490 sv_algorithm_assistance_LP4_1600
3741 20:17:24.446225 ============ PULL DRAM RESETB DOWN ============
3742 20:17:24.449176 ========== PULL DRAM RESETB DOWN end =========
3743 20:17:24.456044 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 20:17:24.459141 ===================================
3745 20:17:24.459222 LPDDR4 DRAM CONFIGURATION
3746 20:17:24.462452 ===================================
3747 20:17:24.466160 EX_ROW_EN[0] = 0x0
3748 20:17:24.469361 EX_ROW_EN[1] = 0x0
3749 20:17:24.469444 LP4Y_EN = 0x0
3750 20:17:24.472232 WORK_FSP = 0x0
3751 20:17:24.472369 WL = 0x2
3752 20:17:24.475719 RL = 0x2
3753 20:17:24.475800 BL = 0x2
3754 20:17:24.479408 RPST = 0x0
3755 20:17:24.479489 RD_PRE = 0x0
3756 20:17:24.482544 WR_PRE = 0x1
3757 20:17:24.482626 WR_PST = 0x0
3758 20:17:24.485644 DBI_WR = 0x0
3759 20:17:24.485725 DBI_RD = 0x0
3760 20:17:24.489089 OTF = 0x1
3761 20:17:24.492595 ===================================
3762 20:17:24.496007 ===================================
3763 20:17:24.496089 ANA top config
3764 20:17:24.499247 ===================================
3765 20:17:24.502384 DLL_ASYNC_EN = 0
3766 20:17:24.505929 ALL_SLAVE_EN = 1
3767 20:17:24.508827 NEW_RANK_MODE = 1
3768 20:17:24.509001 DLL_IDLE_MODE = 1
3769 20:17:24.512264 LP45_APHY_COMB_EN = 1
3770 20:17:24.515791 TX_ODT_DIS = 1
3771 20:17:24.519309 NEW_8X_MODE = 1
3772 20:17:24.522354 ===================================
3773 20:17:24.525419 ===================================
3774 20:17:24.529088 data_rate = 1200
3775 20:17:24.529173 CKR = 1
3776 20:17:24.532237 DQ_P2S_RATIO = 8
3777 20:17:24.535879 ===================================
3778 20:17:24.538799 CA_P2S_RATIO = 8
3779 20:17:24.542243 DQ_CA_OPEN = 0
3780 20:17:24.545799 DQ_SEMI_OPEN = 0
3781 20:17:24.545880 CA_SEMI_OPEN = 0
3782 20:17:24.548868 CA_FULL_RATE = 0
3783 20:17:24.552048 DQ_CKDIV4_EN = 1
3784 20:17:24.555707 CA_CKDIV4_EN = 1
3785 20:17:24.558812 CA_PREDIV_EN = 0
3786 20:17:24.561854 PH8_DLY = 0
3787 20:17:24.561935 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 20:17:24.565471 DQ_AAMCK_DIV = 4
3789 20:17:24.568979 CA_AAMCK_DIV = 4
3790 20:17:24.571971 CA_ADMCK_DIV = 4
3791 20:17:24.575660 DQ_TRACK_CA_EN = 0
3792 20:17:24.578638 CA_PICK = 600
3793 20:17:24.582388 CA_MCKIO = 600
3794 20:17:24.582470 MCKIO_SEMI = 0
3795 20:17:24.585291 PLL_FREQ = 2288
3796 20:17:24.588539 DQ_UI_PI_RATIO = 32
3797 20:17:24.592016 CA_UI_PI_RATIO = 0
3798 20:17:24.595518 ===================================
3799 20:17:24.598559 ===================================
3800 20:17:24.602212 memory_type:LPDDR4
3801 20:17:24.602293 GP_NUM : 10
3802 20:17:24.605196 SRAM_EN : 1
3803 20:17:24.605282 MD32_EN : 0
3804 20:17:24.608878 ===================================
3805 20:17:24.612026 [ANA_INIT] >>>>>>>>>>>>>>
3806 20:17:24.615486 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 20:17:24.618622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 20:17:24.622335 ===================================
3809 20:17:24.625429 data_rate = 1200,PCW = 0X5800
3810 20:17:24.628799 ===================================
3811 20:17:24.631938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 20:17:24.638763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 20:17:24.641599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 20:17:24.648677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 20:17:24.651758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 20:17:24.655356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 20:17:24.655439 [ANA_INIT] flow start
3818 20:17:24.658380 [ANA_INIT] PLL >>>>>>>>
3819 20:17:24.662145 [ANA_INIT] PLL <<<<<<<<
3820 20:17:24.662225 [ANA_INIT] MIDPI >>>>>>>>
3821 20:17:24.665200 [ANA_INIT] MIDPI <<<<<<<<
3822 20:17:24.668181 [ANA_INIT] DLL >>>>>>>>
3823 20:17:24.668297 [ANA_INIT] flow end
3824 20:17:24.675396 ============ LP4 DIFF to SE enter ============
3825 20:17:24.678494 ============ LP4 DIFF to SE exit ============
3826 20:17:24.682160 [ANA_INIT] <<<<<<<<<<<<<
3827 20:17:24.685069 [Flow] Enable top DCM control >>>>>
3828 20:17:24.688125 [Flow] Enable top DCM control <<<<<
3829 20:17:24.688234 Enable DLL master slave shuffle
3830 20:17:24.694782 ==============================================================
3831 20:17:24.698264 Gating Mode config
3832 20:17:24.701762 ==============================================================
3833 20:17:24.704746 Config description:
3834 20:17:24.714641 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 20:17:24.721232 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 20:17:24.724747 SELPH_MODE 0: By rank 1: By Phase
3837 20:17:24.731190 ==============================================================
3838 20:17:24.734677 GAT_TRACK_EN = 1
3839 20:17:24.737840 RX_GATING_MODE = 2
3840 20:17:24.741411 RX_GATING_TRACK_MODE = 2
3841 20:17:24.744622 SELPH_MODE = 1
3842 20:17:24.744704 PICG_EARLY_EN = 1
3843 20:17:24.748189 VALID_LAT_VALUE = 1
3844 20:17:24.755013 ==============================================================
3845 20:17:24.757755 Enter into Gating configuration >>>>
3846 20:17:24.761172 Exit from Gating configuration <<<<
3847 20:17:24.764586 Enter into DVFS_PRE_config >>>>>
3848 20:17:24.774423 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 20:17:24.777851 Exit from DVFS_PRE_config <<<<<
3850 20:17:24.781299 Enter into PICG configuration >>>>
3851 20:17:24.784595 Exit from PICG configuration <<<<
3852 20:17:24.787870 [RX_INPUT] configuration >>>>>
3853 20:17:24.791119 [RX_INPUT] configuration <<<<<
3854 20:17:24.794703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 20:17:24.801349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 20:17:24.807783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 20:17:24.814338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 20:17:24.821170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 20:17:24.824659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 20:17:24.830922 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 20:17:24.834481 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 20:17:24.837956 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 20:17:24.841353 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 20:17:24.844920 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 20:17:24.851064 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 20:17:24.854831 ===================================
3867 20:17:24.857679 LPDDR4 DRAM CONFIGURATION
3868 20:17:24.861524 ===================================
3869 20:17:24.861606 EX_ROW_EN[0] = 0x0
3870 20:17:24.864596 EX_ROW_EN[1] = 0x0
3871 20:17:24.864678 LP4Y_EN = 0x0
3872 20:17:24.867925 WORK_FSP = 0x0
3873 20:17:24.868007 WL = 0x2
3874 20:17:24.871475 RL = 0x2
3875 20:17:24.871556 BL = 0x2
3876 20:17:24.874634 RPST = 0x0
3877 20:17:24.874715 RD_PRE = 0x0
3878 20:17:24.878239 WR_PRE = 0x1
3879 20:17:24.878321 WR_PST = 0x0
3880 20:17:24.881246 DBI_WR = 0x0
3881 20:17:24.881328 DBI_RD = 0x0
3882 20:17:24.884472 OTF = 0x1
3883 20:17:24.887794 ===================================
3884 20:17:24.891139 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 20:17:24.894741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 20:17:24.901438 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 20:17:24.904631 ===================================
3888 20:17:24.904714 LPDDR4 DRAM CONFIGURATION
3889 20:17:24.907597 ===================================
3890 20:17:24.911237 EX_ROW_EN[0] = 0x10
3891 20:17:24.914219 EX_ROW_EN[1] = 0x0
3892 20:17:24.914301 LP4Y_EN = 0x0
3893 20:17:24.917729 WORK_FSP = 0x0
3894 20:17:24.917811 WL = 0x2
3895 20:17:24.921385 RL = 0x2
3896 20:17:24.921467 BL = 0x2
3897 20:17:24.924440 RPST = 0x0
3898 20:17:24.924521 RD_PRE = 0x0
3899 20:17:24.927847 WR_PRE = 0x1
3900 20:17:24.927929 WR_PST = 0x0
3901 20:17:24.931116 DBI_WR = 0x0
3902 20:17:24.931198 DBI_RD = 0x0
3903 20:17:24.934238 OTF = 0x1
3904 20:17:24.937885 ===================================
3905 20:17:24.944277 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 20:17:24.947917 nWR fixed to 30
3907 20:17:24.948005 [ModeRegInit_LP4] CH0 RK0
3908 20:17:24.950802 [ModeRegInit_LP4] CH0 RK1
3909 20:17:24.954418 [ModeRegInit_LP4] CH1 RK0
3910 20:17:24.957968 [ModeRegInit_LP4] CH1 RK1
3911 20:17:24.958050 match AC timing 17
3912 20:17:24.964413 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 20:17:24.967782 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 20:17:24.971076 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 20:17:24.978082 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 20:17:24.980901 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 20:17:24.980983 ==
3918 20:17:24.984589 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 20:17:24.987614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 20:17:24.987697 ==
3921 20:17:24.994176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 20:17:25.001068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3923 20:17:25.004240 [CA 0] Center 35 (5~66) winsize 62
3924 20:17:25.007841 [CA 1] Center 35 (5~66) winsize 62
3925 20:17:25.010798 [CA 2] Center 33 (3~64) winsize 62
3926 20:17:25.013937 [CA 3] Center 33 (2~64) winsize 63
3927 20:17:25.017502 [CA 4] Center 33 (2~64) winsize 63
3928 20:17:25.021127 [CA 5] Center 32 (2~63) winsize 62
3929 20:17:25.021209
3930 20:17:25.024026 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3931 20:17:25.024108
3932 20:17:25.027677 [CATrainingPosCal] consider 1 rank data
3933 20:17:25.031247 u2DelayCellTimex100 = 270/100 ps
3934 20:17:25.034273 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3935 20:17:25.037894 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3936 20:17:25.040988 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3937 20:17:25.044689 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3938 20:17:25.047832 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3939 20:17:25.050814 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3940 20:17:25.050897
3941 20:17:25.054458 CA PerBit enable=1, Macro0, CA PI delay=32
3942 20:17:25.054543
3943 20:17:25.057627 [CBTSetCACLKResult] CA Dly = 32
3944 20:17:25.061254 CS Dly: 5 (0~36)
3945 20:17:25.061388 ==
3946 20:17:25.064323 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 20:17:25.067586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 20:17:25.067670 ==
3949 20:17:25.074091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 20:17:25.080744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 20:17:25.084067 [CA 0] Center 35 (5~66) winsize 62
3952 20:17:25.087608 [CA 1] Center 35 (5~66) winsize 62
3953 20:17:25.090766 [CA 2] Center 34 (3~65) winsize 63
3954 20:17:25.093915 [CA 3] Center 33 (3~64) winsize 62
3955 20:17:25.097664 [CA 4] Center 33 (2~64) winsize 63
3956 20:17:25.100863 [CA 5] Center 32 (2~63) winsize 62
3957 20:17:25.100984
3958 20:17:25.103998 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 20:17:25.104123
3960 20:17:25.107486 [CATrainingPosCal] consider 2 rank data
3961 20:17:25.110743 u2DelayCellTimex100 = 270/100 ps
3962 20:17:25.114063 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3963 20:17:25.117392 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 20:17:25.120579 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3965 20:17:25.124033 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3966 20:17:25.127473 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3967 20:17:25.130993 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3968 20:17:25.131114
3969 20:17:25.137495 CA PerBit enable=1, Macro0, CA PI delay=32
3970 20:17:25.137616
3971 20:17:25.137729 [CBTSetCACLKResult] CA Dly = 32
3972 20:17:25.140504 CS Dly: 5 (0~36)
3973 20:17:25.140622
3974 20:17:25.144104 ----->DramcWriteLeveling(PI) begin...
3975 20:17:25.144213 ==
3976 20:17:25.147254 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 20:17:25.151032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 20:17:25.151114 ==
3979 20:17:25.154002 Write leveling (Byte 0): 33 => 33
3980 20:17:25.157617 Write leveling (Byte 1): 33 => 33
3981 20:17:25.160788 DramcWriteLeveling(PI) end<-----
3982 20:17:25.160886
3983 20:17:25.160965 ==
3984 20:17:25.164346 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 20:17:25.167244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 20:17:25.167366 ==
3987 20:17:25.171031 [Gating] SW mode calibration
3988 20:17:25.177747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 20:17:25.183937 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 20:17:25.187212 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 20:17:25.194294 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 20:17:25.197402 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 20:17:25.200433 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
3994 20:17:25.207339 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
3995 20:17:25.210369 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 20:17:25.214094 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 20:17:25.220714 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 20:17:25.224076 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 20:17:25.227389 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 20:17:25.233745 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 20:17:25.237127 0 10 12 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
4002 20:17:25.240320 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4003 20:17:25.243578 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 20:17:25.250789 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 20:17:25.253799 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 20:17:25.256893 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 20:17:25.263580 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 20:17:25.267263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 20:17:25.270349 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 20:17:25.277119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4011 20:17:25.280428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 20:17:25.283587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 20:17:25.290224 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 20:17:25.293356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 20:17:25.296958 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 20:17:25.303396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 20:17:25.306792 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 20:17:25.310195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 20:17:25.316923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 20:17:25.319976 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 20:17:25.323606 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 20:17:25.330338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 20:17:25.333365 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 20:17:25.336857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 20:17:25.343149 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 20:17:25.346998 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 20:17:25.349743 Total UI for P1: 0, mck2ui 16
4028 20:17:25.353025 best dqsien dly found for B0: ( 0, 13, 14)
4029 20:17:25.356806 Total UI for P1: 0, mck2ui 16
4030 20:17:25.359917 best dqsien dly found for B1: ( 0, 13, 14)
4031 20:17:25.363379 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4032 20:17:25.366388 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4033 20:17:25.366512
4034 20:17:25.370087 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4035 20:17:25.373391 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 20:17:25.376440 [Gating] SW calibration Done
4037 20:17:25.376562 ==
4038 20:17:25.380114 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 20:17:25.382989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 20:17:25.386652 ==
4041 20:17:25.386775 RX Vref Scan: 0
4042 20:17:25.386890
4043 20:17:25.389589 RX Vref 0 -> 0, step: 1
4044 20:17:25.389712
4045 20:17:25.393056 RX Delay -230 -> 252, step: 16
4046 20:17:25.396636 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4047 20:17:25.399729 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4048 20:17:25.403366 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4049 20:17:25.406380 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4050 20:17:25.413172 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4051 20:17:25.416589 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4052 20:17:25.419635 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4053 20:17:25.423283 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4054 20:17:25.429514 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4055 20:17:25.433127 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4056 20:17:25.436741 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4057 20:17:25.439628 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4058 20:17:25.446446 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4059 20:17:25.449336 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4060 20:17:25.452737 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4061 20:17:25.456053 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4062 20:17:25.456179 ==
4063 20:17:25.459575 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 20:17:25.466151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 20:17:25.466279 ==
4066 20:17:25.466395 DQS Delay:
4067 20:17:25.469565 DQS0 = 0, DQS1 = 0
4068 20:17:25.469688 DQM Delay:
4069 20:17:25.469800 DQM0 = 51, DQM1 = 46
4070 20:17:25.472530 DQ Delay:
4071 20:17:25.476167 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4072 20:17:25.479316 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4073 20:17:25.482371 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4074 20:17:25.486071 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4075 20:17:25.486196
4076 20:17:25.486310
4077 20:17:25.486419 ==
4078 20:17:25.489057 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 20:17:25.492769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 20:17:25.492893 ==
4081 20:17:25.493008
4082 20:17:25.493117
4083 20:17:25.495663 TX Vref Scan disable
4084 20:17:25.499289 == TX Byte 0 ==
4085 20:17:25.502662 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 20:17:25.506005 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 20:17:25.509102 == TX Byte 1 ==
4088 20:17:25.512657 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4089 20:17:25.515692 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4090 20:17:25.515815 ==
4091 20:17:25.518864 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 20:17:25.522429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 20:17:25.522554 ==
4094 20:17:25.525465
4095 20:17:25.525590
4096 20:17:25.525705 TX Vref Scan disable
4097 20:17:25.529365 == TX Byte 0 ==
4098 20:17:25.532879 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 20:17:25.539429 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 20:17:25.539553 == TX Byte 1 ==
4101 20:17:25.542413 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4102 20:17:25.549077 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4103 20:17:25.549202
4104 20:17:25.549315 [DATLAT]
4105 20:17:25.549424 Freq=600, CH0 RK0
4106 20:17:25.549537
4107 20:17:25.552633 DATLAT Default: 0x9
4108 20:17:25.552754 0, 0xFFFF, sum = 0
4109 20:17:25.555713 1, 0xFFFF, sum = 0
4110 20:17:25.555836 2, 0xFFFF, sum = 0
4111 20:17:25.559434 3, 0xFFFF, sum = 0
4112 20:17:25.562275 4, 0xFFFF, sum = 0
4113 20:17:25.562401 5, 0xFFFF, sum = 0
4114 20:17:25.565822 6, 0xFFFF, sum = 0
4115 20:17:25.565948 7, 0xFFFF, sum = 0
4116 20:17:25.568837 8, 0x0, sum = 1
4117 20:17:25.568959 9, 0x0, sum = 2
4118 20:17:25.569075 10, 0x0, sum = 3
4119 20:17:25.572195 11, 0x0, sum = 4
4120 20:17:25.572356 best_step = 9
4121 20:17:25.572469
4122 20:17:25.572578 ==
4123 20:17:25.575660 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 20:17:25.582545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 20:17:25.582669 ==
4126 20:17:25.582785 RX Vref Scan: 1
4127 20:17:25.582929
4128 20:17:25.585844 RX Vref 0 -> 0, step: 1
4129 20:17:25.585967
4130 20:17:25.588911 RX Delay -163 -> 252, step: 8
4131 20:17:25.589033
4132 20:17:25.592489 Set Vref, RX VrefLevel [Byte0]: 56
4133 20:17:25.595563 [Byte1]: 57
4134 20:17:25.595686
4135 20:17:25.599241 Final RX Vref Byte 0 = 56 to rank0
4136 20:17:25.602280 Final RX Vref Byte 1 = 57 to rank0
4137 20:17:25.606093 Final RX Vref Byte 0 = 56 to rank1
4138 20:17:25.609033 Final RX Vref Byte 1 = 57 to rank1==
4139 20:17:25.612266 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 20:17:25.615602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 20:17:25.615722 ==
4142 20:17:25.619008 DQS Delay:
4143 20:17:25.619130 DQS0 = 0, DQS1 = 0
4144 20:17:25.619243 DQM Delay:
4145 20:17:25.622213 DQM0 = 53, DQM1 = 47
4146 20:17:25.622335 DQ Delay:
4147 20:17:25.625804 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4148 20:17:25.628996 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4149 20:17:25.632533 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =44
4150 20:17:25.635073 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =52
4151 20:17:25.635195
4152 20:17:25.635308
4153 20:17:25.645450 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4154 20:17:25.648951 CH0 RK0: MR19=808, MR18=6C5F
4155 20:17:25.651774 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4156 20:17:25.655172
4157 20:17:25.658864 ----->DramcWriteLeveling(PI) begin...
4158 20:17:25.658990 ==
4159 20:17:25.662066 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 20:17:25.665561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 20:17:25.665684 ==
4162 20:17:25.668432 Write leveling (Byte 0): 34 => 34
4163 20:17:25.671453 Write leveling (Byte 1): 31 => 31
4164 20:17:25.675050 DramcWriteLeveling(PI) end<-----
4165 20:17:25.675174
4166 20:17:25.675286 ==
4167 20:17:25.678548 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 20:17:25.681601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 20:17:25.681721 ==
4170 20:17:25.684933 [Gating] SW mode calibration
4171 20:17:25.691710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 20:17:25.698285 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 20:17:25.701418 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 20:17:25.704591 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 20:17:25.711598 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 20:17:25.714692 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4177 20:17:25.718315 0 9 16 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (0 0)
4178 20:17:25.724556 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 20:17:25.727794 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 20:17:25.731436 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 20:17:25.738188 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 20:17:25.741503 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 20:17:25.744934 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 20:17:25.751158 0 10 12 | B1->B0 | 2525 2c2b | 0 1 | (0 0) (0 0)
4185 20:17:25.754487 0 10 16 | B1->B0 | 3f3f 4242 | 0 0 | (0 0) (1 1)
4186 20:17:25.757728 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 20:17:25.764607 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 20:17:25.768000 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 20:17:25.771116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 20:17:25.777979 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 20:17:25.781397 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 20:17:25.784268 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4193 20:17:25.791133 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4194 20:17:25.794100 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 20:17:25.797751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 20:17:25.801307 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 20:17:25.807513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 20:17:25.810833 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 20:17:25.814079 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 20:17:25.820769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 20:17:25.823956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 20:17:25.827502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 20:17:25.834539 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 20:17:25.837345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 20:17:25.841022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 20:17:25.847585 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 20:17:25.850661 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 20:17:25.853976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 20:17:25.860689 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4210 20:17:25.863656 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 20:17:25.867206 Total UI for P1: 0, mck2ui 16
4212 20:17:25.870600 best dqsien dly found for B0: ( 0, 13, 16)
4213 20:17:25.873799 Total UI for P1: 0, mck2ui 16
4214 20:17:25.876966 best dqsien dly found for B1: ( 0, 13, 16)
4215 20:17:25.880745 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4216 20:17:25.883811 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4217 20:17:25.883933
4218 20:17:25.887092 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4219 20:17:25.890701 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4220 20:17:25.893586 [Gating] SW calibration Done
4221 20:17:25.893710 ==
4222 20:17:25.897049 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 20:17:25.903820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 20:17:25.903949 ==
4225 20:17:25.904064 RX Vref Scan: 0
4226 20:17:25.904176
4227 20:17:25.907079 RX Vref 0 -> 0, step: 1
4228 20:17:25.907203
4229 20:17:25.910265 RX Delay -230 -> 252, step: 16
4230 20:17:25.913863 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4231 20:17:25.917013 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4232 20:17:25.920704 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4233 20:17:25.926828 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4234 20:17:25.930383 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4235 20:17:25.933463 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4236 20:17:25.937045 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4237 20:17:25.940638 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4238 20:17:25.946873 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4239 20:17:25.950431 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4240 20:17:25.953483 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4241 20:17:25.957055 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4242 20:17:25.963611 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4243 20:17:25.966630 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4244 20:17:25.970400 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4245 20:17:25.973490 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4246 20:17:25.973613 ==
4247 20:17:25.977107 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 20:17:25.983282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 20:17:25.983407 ==
4250 20:17:25.983521 DQS Delay:
4251 20:17:25.986837 DQS0 = 0, DQS1 = 0
4252 20:17:25.986964 DQM Delay:
4253 20:17:25.987079 DQM0 = 54, DQM1 = 42
4254 20:17:25.990433 DQ Delay:
4255 20:17:25.993308 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4256 20:17:25.996550 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4257 20:17:26.000031 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4258 20:17:26.003110 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4259 20:17:26.003234
4260 20:17:26.003372
4261 20:17:26.003499 ==
4262 20:17:26.006574 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 20:17:26.009902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 20:17:26.009987 ==
4265 20:17:26.010051
4266 20:17:26.010111
4267 20:17:26.013414 TX Vref Scan disable
4268 20:17:26.016591 == TX Byte 0 ==
4269 20:17:26.019817 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4270 20:17:26.023597 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4271 20:17:26.026591 == TX Byte 1 ==
4272 20:17:26.030283 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4273 20:17:26.033382 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4274 20:17:26.033505 ==
4275 20:17:26.036343 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 20:17:26.039933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 20:17:26.042956 ==
4278 20:17:26.043081
4279 20:17:26.043244
4280 20:17:26.043368 TX Vref Scan disable
4281 20:17:26.047080 == TX Byte 0 ==
4282 20:17:26.050111 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4283 20:17:26.056701 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4284 20:17:26.056846 == TX Byte 1 ==
4285 20:17:26.059963 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4286 20:17:26.066972 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4287 20:17:26.067099
4288 20:17:26.067246 [DATLAT]
4289 20:17:26.067368 Freq=600, CH0 RK1
4290 20:17:26.067494
4291 20:17:26.069928 DATLAT Default: 0x9
4292 20:17:26.070051 0, 0xFFFF, sum = 0
4293 20:17:26.073613 1, 0xFFFF, sum = 0
4294 20:17:26.073740 2, 0xFFFF, sum = 0
4295 20:17:26.076552 3, 0xFFFF, sum = 0
4296 20:17:26.080422 4, 0xFFFF, sum = 0
4297 20:17:26.080548 5, 0xFFFF, sum = 0
4298 20:17:26.083493 6, 0xFFFF, sum = 0
4299 20:17:26.083622 7, 0xFFFF, sum = 0
4300 20:17:26.086985 8, 0x0, sum = 1
4301 20:17:26.087115 9, 0x0, sum = 2
4302 20:17:26.087234 10, 0x0, sum = 3
4303 20:17:26.090046 11, 0x0, sum = 4
4304 20:17:26.090197 best_step = 9
4305 20:17:26.090320
4306 20:17:26.090426 ==
4307 20:17:26.093553 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 20:17:26.100193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 20:17:26.100320 ==
4310 20:17:26.100432 RX Vref Scan: 0
4311 20:17:26.100496
4312 20:17:26.103216 RX Vref 0 -> 0, step: 1
4313 20:17:26.103298
4314 20:17:26.106672 RX Delay -179 -> 252, step: 8
4315 20:17:26.109727 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4316 20:17:26.116319 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4317 20:17:26.120182 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4318 20:17:26.123093 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4319 20:17:26.126868 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4320 20:17:26.130220 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4321 20:17:26.133744 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4322 20:17:26.140559 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4323 20:17:26.143515 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4324 20:17:26.146505 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4325 20:17:26.150200 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4326 20:17:26.156792 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4327 20:17:26.160271 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4328 20:17:26.163407 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4329 20:17:26.167101 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4330 20:17:26.170016 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4331 20:17:26.173621 ==
4332 20:17:26.173724 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 20:17:26.180379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 20:17:26.180462 ==
4335 20:17:26.180527 DQS Delay:
4336 20:17:26.183389 DQS0 = 0, DQS1 = 0
4337 20:17:26.183517 DQM Delay:
4338 20:17:26.186855 DQM0 = 54, DQM1 = 46
4339 20:17:26.186934 DQ Delay:
4340 20:17:26.189920 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4341 20:17:26.193534 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4342 20:17:26.196927 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4343 20:17:26.199688 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4344 20:17:26.199761
4345 20:17:26.199822
4346 20:17:26.206619 [DQSOSCAuto] RK1, (LSB)MR18= 0x6525, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4347 20:17:26.210058 CH0 RK1: MR19=808, MR18=6525
4348 20:17:26.216954 CH0_RK1: MR19=0x808, MR18=0x6525, DQSOSC=390, MR23=63, INC=172, DEC=114
4349 20:17:26.219869 [RxdqsGatingPostProcess] freq 600
4350 20:17:26.223228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 20:17:26.226395 Pre-setting of DQS Precalculation
4352 20:17:26.233005 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 20:17:26.233082 ==
4354 20:17:26.236730 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 20:17:26.239999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 20:17:26.240086 ==
4357 20:17:26.246552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 20:17:26.253266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4359 20:17:26.256456 [CA 0] Center 36 (5~67) winsize 63
4360 20:17:26.259573 [CA 1] Center 36 (5~67) winsize 63
4361 20:17:26.262976 [CA 2] Center 34 (4~65) winsize 62
4362 20:17:26.266671 [CA 3] Center 34 (4~65) winsize 62
4363 20:17:26.269681 [CA 4] Center 34 (4~65) winsize 62
4364 20:17:26.273281 [CA 5] Center 33 (3~64) winsize 62
4365 20:17:26.273411
4366 20:17:26.276433 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4367 20:17:26.276560
4368 20:17:26.279869 [CATrainingPosCal] consider 1 rank data
4369 20:17:26.283011 u2DelayCellTimex100 = 270/100 ps
4370 20:17:26.286556 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4371 20:17:26.289680 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4372 20:17:26.293372 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 20:17:26.296619 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 20:17:26.299778 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 20:17:26.303322 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 20:17:26.303403
4377 20:17:26.309823 CA PerBit enable=1, Macro0, CA PI delay=33
4378 20:17:26.309905
4379 20:17:26.309969 [CBTSetCACLKResult] CA Dly = 33
4380 20:17:26.313276 CS Dly: 5 (0~36)
4381 20:17:26.313357 ==
4382 20:17:26.316126 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 20:17:26.319537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 20:17:26.319620 ==
4385 20:17:26.325942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 20:17:26.332582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 20:17:26.336334 [CA 0] Center 36 (5~67) winsize 63
4388 20:17:26.339518 [CA 1] Center 36 (5~67) winsize 63
4389 20:17:26.343037 [CA 2] Center 34 (4~65) winsize 62
4390 20:17:26.345906 [CA 3] Center 34 (4~65) winsize 62
4391 20:17:26.349363 [CA 4] Center 34 (4~65) winsize 62
4392 20:17:26.352763 [CA 5] Center 34 (3~65) winsize 63
4393 20:17:26.352845
4394 20:17:26.356421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 20:17:26.356503
4396 20:17:26.359345 [CATrainingPosCal] consider 2 rank data
4397 20:17:26.362983 u2DelayCellTimex100 = 270/100 ps
4398 20:17:26.365979 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4399 20:17:26.369565 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4400 20:17:26.372573 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 20:17:26.376221 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 20:17:26.379405 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 20:17:26.383022 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 20:17:26.385915
4405 20:17:26.389612 CA PerBit enable=1, Macro0, CA PI delay=33
4406 20:17:26.389694
4407 20:17:26.392617 [CBTSetCACLKResult] CA Dly = 33
4408 20:17:26.392699 CS Dly: 5 (0~37)
4409 20:17:26.392793
4410 20:17:26.396039 ----->DramcWriteLeveling(PI) begin...
4411 20:17:26.396137 ==
4412 20:17:26.399184 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 20:17:26.402884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 20:17:26.405811 ==
4415 20:17:26.405907 Write leveling (Byte 0): 28 => 28
4416 20:17:26.408974 Write leveling (Byte 1): 31 => 31
4417 20:17:26.412689 DramcWriteLeveling(PI) end<-----
4418 20:17:26.412786
4419 20:17:26.412882 ==
4420 20:17:26.415711 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 20:17:26.422737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 20:17:26.422834 ==
4423 20:17:26.422930 [Gating] SW mode calibration
4424 20:17:26.432432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 20:17:26.435531 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 20:17:26.438852 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 20:17:26.446049 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 20:17:26.449195 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4429 20:17:26.452594 0 9 12 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
4430 20:17:26.459118 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 20:17:26.462526 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 20:17:26.465675 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 20:17:26.472585 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 20:17:26.475596 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 20:17:26.479026 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 20:17:26.485719 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4437 20:17:26.488662 0 10 12 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
4438 20:17:26.492209 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 20:17:26.498606 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 20:17:26.502274 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 20:17:26.505369 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 20:17:26.512054 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 20:17:26.515269 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 20:17:26.519050 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4445 20:17:26.525205 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 20:17:26.528661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 20:17:26.532023 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 20:17:26.538595 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 20:17:26.542260 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 20:17:26.545111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 20:17:26.551728 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 20:17:26.555202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 20:17:26.558452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 20:17:26.565004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 20:17:26.568430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 20:17:26.571353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 20:17:26.578197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 20:17:26.581745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 20:17:26.584678 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 20:17:26.591571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 20:17:26.594764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4462 20:17:26.598067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4463 20:17:26.601597 Total UI for P1: 0, mck2ui 16
4464 20:17:26.604496 best dqsien dly found for B0: ( 0, 13, 14)
4465 20:17:26.611143 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 20:17:26.611226 Total UI for P1: 0, mck2ui 16
4467 20:17:26.614890 best dqsien dly found for B1: ( 0, 13, 14)
4468 20:17:26.621618 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4469 20:17:26.624664 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4470 20:17:26.624738
4471 20:17:26.628239 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4472 20:17:26.631355 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4473 20:17:26.635016 [Gating] SW calibration Done
4474 20:17:26.635086 ==
4475 20:17:26.637885 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 20:17:26.641321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 20:17:26.641418 ==
4478 20:17:26.644824 RX Vref Scan: 0
4479 20:17:26.644896
4480 20:17:26.644957 RX Vref 0 -> 0, step: 1
4481 20:17:26.645023
4482 20:17:26.647933 RX Delay -230 -> 252, step: 16
4483 20:17:26.651030 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4484 20:17:26.657663 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4485 20:17:26.661030 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4486 20:17:26.664234 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4487 20:17:26.667882 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4488 20:17:26.674575 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4489 20:17:26.677974 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 20:17:26.681148 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4491 20:17:26.684520 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4492 20:17:26.688011 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4493 20:17:26.694098 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4494 20:17:26.697760 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4495 20:17:26.701414 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4496 20:17:26.704173 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4497 20:17:26.711262 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4498 20:17:26.714203 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4499 20:17:26.714309 ==
4500 20:17:26.717383 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 20:17:26.720955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 20:17:26.721070 ==
4503 20:17:26.724043 DQS Delay:
4504 20:17:26.724113 DQS0 = 0, DQS1 = 0
4505 20:17:26.724188 DQM Delay:
4506 20:17:26.727639 DQM0 = 49, DQM1 = 46
4507 20:17:26.727749 DQ Delay:
4508 20:17:26.730846 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4509 20:17:26.734419 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4510 20:17:26.737539 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4511 20:17:26.741176 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4512 20:17:26.741259
4513 20:17:26.741335
4514 20:17:26.741421 ==
4515 20:17:26.744081 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 20:17:26.751036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 20:17:26.751114 ==
4518 20:17:26.751177
4519 20:17:26.751235
4520 20:17:26.751300 TX Vref Scan disable
4521 20:17:26.754677 == TX Byte 0 ==
4522 20:17:26.757859 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4523 20:17:26.764714 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4524 20:17:26.764795 == TX Byte 1 ==
4525 20:17:26.767880 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 20:17:26.774691 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 20:17:26.774790 ==
4528 20:17:26.778174 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 20:17:26.781145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 20:17:26.781216 ==
4531 20:17:26.781284
4532 20:17:26.781371
4533 20:17:26.784632 TX Vref Scan disable
4534 20:17:26.788132 == TX Byte 0 ==
4535 20:17:26.791216 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4536 20:17:26.794422 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4537 20:17:26.797678 == TX Byte 1 ==
4538 20:17:26.801314 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 20:17:26.804473 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 20:17:26.804578
4541 20:17:26.804640 [DATLAT]
4542 20:17:26.807797 Freq=600, CH1 RK0
4543 20:17:26.807865
4544 20:17:26.807925 DATLAT Default: 0x9
4545 20:17:26.811322 0, 0xFFFF, sum = 0
4546 20:17:26.811392 1, 0xFFFF, sum = 0
4547 20:17:26.814543 2, 0xFFFF, sum = 0
4548 20:17:26.814621 3, 0xFFFF, sum = 0
4549 20:17:26.817978 4, 0xFFFF, sum = 0
4550 20:17:26.818084 5, 0xFFFF, sum = 0
4551 20:17:26.820941 6, 0xFFFF, sum = 0
4552 20:17:26.824498 7, 0xFFFF, sum = 0
4553 20:17:26.824573 8, 0x0, sum = 1
4554 20:17:26.824638 9, 0x0, sum = 2
4555 20:17:26.827611 10, 0x0, sum = 3
4556 20:17:26.827712 11, 0x0, sum = 4
4557 20:17:26.831209 best_step = 9
4558 20:17:26.831287
4559 20:17:26.831348 ==
4560 20:17:26.834311 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 20:17:26.838008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 20:17:26.838109 ==
4563 20:17:26.841098 RX Vref Scan: 1
4564 20:17:26.841170
4565 20:17:26.841236 RX Vref 0 -> 0, step: 1
4566 20:17:26.841297
4567 20:17:26.844232 RX Delay -163 -> 252, step: 8
4568 20:17:26.844338
4569 20:17:26.847994 Set Vref, RX VrefLevel [Byte0]: 55
4570 20:17:26.851006 [Byte1]: 53
4571 20:17:26.855020
4572 20:17:26.858131 Final RX Vref Byte 0 = 55 to rank0
4573 20:17:26.858205 Final RX Vref Byte 1 = 53 to rank0
4574 20:17:26.861231 Final RX Vref Byte 0 = 55 to rank1
4575 20:17:26.864602 Final RX Vref Byte 1 = 53 to rank1==
4576 20:17:26.868235 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 20:17:26.874374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 20:17:26.874448 ==
4579 20:17:26.874516 DQS Delay:
4580 20:17:26.877995 DQS0 = 0, DQS1 = 0
4581 20:17:26.878065 DQM Delay:
4582 20:17:26.878126 DQM0 = 49, DQM1 = 44
4583 20:17:26.881468 DQ Delay:
4584 20:17:26.884668 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4585 20:17:26.888320 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4586 20:17:26.891431 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4587 20:17:26.894968 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4588 20:17:26.895051
4589 20:17:26.895116
4590 20:17:26.901071 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4591 20:17:26.904458 CH1 RK0: MR19=808, MR18=4A70
4592 20:17:26.911045 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4593 20:17:26.911129
4594 20:17:26.914430 ----->DramcWriteLeveling(PI) begin...
4595 20:17:26.914512 ==
4596 20:17:26.917926 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 20:17:26.921254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 20:17:26.921336 ==
4599 20:17:26.924197 Write leveling (Byte 0): 30 => 30
4600 20:17:26.927495 Write leveling (Byte 1): 30 => 30
4601 20:17:26.931008 DramcWriteLeveling(PI) end<-----
4602 20:17:26.931083
4603 20:17:26.931147 ==
4604 20:17:26.934503 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 20:17:26.937904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 20:17:26.937976 ==
4607 20:17:26.941355 [Gating] SW mode calibration
4608 20:17:26.948202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 20:17:26.954281 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 20:17:26.958076 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 20:17:26.964150 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 20:17:26.967658 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4613 20:17:26.970954 0 9 12 | B1->B0 | 2e2e 2d2d | 1 1 | (1 0) (1 1)
4614 20:17:26.977944 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 20:17:26.981094 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 20:17:26.984079 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 20:17:26.988040 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 20:17:26.994634 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 20:17:26.997785 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 20:17:27.001202 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 20:17:27.007723 0 10 12 | B1->B0 | 3a3a 3737 | 0 0 | (1 1) (0 0)
4622 20:17:27.010693 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 20:17:27.014435 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 20:17:27.020864 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 20:17:27.024488 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 20:17:27.027485 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 20:17:27.033942 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 20:17:27.037638 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4629 20:17:27.040723 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 20:17:27.047614 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 20:17:27.050802 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 20:17:27.054074 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 20:17:27.060587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 20:17:27.064178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 20:17:27.067199 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 20:17:27.074235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 20:17:27.077694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 20:17:27.080498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 20:17:27.087394 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 20:17:27.090881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 20:17:27.093996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 20:17:27.100968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 20:17:27.103924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 20:17:27.107111 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 20:17:27.110622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4646 20:17:27.117456 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 20:17:27.120531 Total UI for P1: 0, mck2ui 16
4648 20:17:27.123880 best dqsien dly found for B0: ( 0, 13, 12)
4649 20:17:27.127513 Total UI for P1: 0, mck2ui 16
4650 20:17:27.130515 best dqsien dly found for B1: ( 0, 13, 12)
4651 20:17:27.133949 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4652 20:17:27.137288 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4653 20:17:27.137370
4654 20:17:27.140322 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4655 20:17:27.144203 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4656 20:17:27.147153 [Gating] SW calibration Done
4657 20:17:27.147234 ==
4658 20:17:27.150724 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 20:17:27.153756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 20:17:27.153839 ==
4661 20:17:27.157321 RX Vref Scan: 0
4662 20:17:27.157418
4663 20:17:27.160597 RX Vref 0 -> 0, step: 1
4664 20:17:27.160680
4665 20:17:27.160746 RX Delay -230 -> 252, step: 16
4666 20:17:27.166922 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4667 20:17:27.170311 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4668 20:17:27.173451 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4669 20:17:27.176694 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4670 20:17:27.183776 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4671 20:17:27.186854 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4672 20:17:27.190229 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4673 20:17:27.193520 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4674 20:17:27.196691 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4675 20:17:27.203204 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4676 20:17:27.206693 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4677 20:17:27.210202 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4678 20:17:27.213594 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4679 20:17:27.220226 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4680 20:17:27.223994 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4681 20:17:27.227026 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4682 20:17:27.227150 ==
4683 20:17:27.230672 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 20:17:27.233531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 20:17:27.233666 ==
4686 20:17:27.237150 DQS Delay:
4687 20:17:27.237281 DQS0 = 0, DQS1 = 0
4688 20:17:27.240712 DQM Delay:
4689 20:17:27.240846 DQM0 = 52, DQM1 = 49
4690 20:17:27.240967 DQ Delay:
4691 20:17:27.243694 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4692 20:17:27.247149 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4693 20:17:27.250301 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4694 20:17:27.254073 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4695 20:17:27.254213
4696 20:17:27.254327
4697 20:17:27.257021 ==
4698 20:17:27.257145 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 20:17:27.263718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 20:17:27.263845 ==
4701 20:17:27.263969
4702 20:17:27.264083
4703 20:17:27.267197 TX Vref Scan disable
4704 20:17:27.267329 == TX Byte 0 ==
4705 20:17:27.270317 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4706 20:17:27.276913 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4707 20:17:27.277019 == TX Byte 1 ==
4708 20:17:27.280426 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 20:17:27.286988 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 20:17:27.287088 ==
4711 20:17:27.290198 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 20:17:27.293237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 20:17:27.293322 ==
4714 20:17:27.293393
4715 20:17:27.293457
4716 20:17:27.296921 TX Vref Scan disable
4717 20:17:27.300430 == TX Byte 0 ==
4718 20:17:27.303189 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 20:17:27.306926 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 20:17:27.309981 == TX Byte 1 ==
4721 20:17:27.313471 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 20:17:27.316554 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 20:17:27.316638
4724 20:17:27.320104 [DATLAT]
4725 20:17:27.320186 Freq=600, CH1 RK1
4726 20:17:27.320252
4727 20:17:27.323395 DATLAT Default: 0x9
4728 20:17:27.323504 0, 0xFFFF, sum = 0
4729 20:17:27.326549 1, 0xFFFF, sum = 0
4730 20:17:27.326633 2, 0xFFFF, sum = 0
4731 20:17:27.329745 3, 0xFFFF, sum = 0
4732 20:17:27.329829 4, 0xFFFF, sum = 0
4733 20:17:27.333527 5, 0xFFFF, sum = 0
4734 20:17:27.333612 6, 0xFFFF, sum = 0
4735 20:17:27.336497 7, 0xFFFF, sum = 0
4736 20:17:27.336607 8, 0x0, sum = 1
4737 20:17:27.340012 9, 0x0, sum = 2
4738 20:17:27.340122 10, 0x0, sum = 3
4739 20:17:27.343496 11, 0x0, sum = 4
4740 20:17:27.343587 best_step = 9
4741 20:17:27.343652
4742 20:17:27.343713 ==
4743 20:17:27.346578 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 20:17:27.350035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 20:17:27.353445 ==
4746 20:17:27.353580 RX Vref Scan: 0
4747 20:17:27.353696
4748 20:17:27.356554 RX Vref 0 -> 0, step: 1
4749 20:17:27.356658
4750 20:17:27.359668 RX Delay -163 -> 252, step: 8
4751 20:17:27.363349 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4752 20:17:27.366376 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4753 20:17:27.373196 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4754 20:17:27.376377 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4755 20:17:27.379996 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4756 20:17:27.383363 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4757 20:17:27.386484 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4758 20:17:27.389573 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4759 20:17:27.396834 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4760 20:17:27.399928 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4761 20:17:27.403024 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4762 20:17:27.406634 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4763 20:17:27.413390 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4764 20:17:27.416133 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4765 20:17:27.419564 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4766 20:17:27.423015 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4767 20:17:27.423100 ==
4768 20:17:27.426431 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 20:17:27.432866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 20:17:27.432994 ==
4771 20:17:27.433110 DQS Delay:
4772 20:17:27.436167 DQS0 = 0, DQS1 = 0
4773 20:17:27.436296 DQM Delay:
4774 20:17:27.436410 DQM0 = 49, DQM1 = 45
4775 20:17:27.439405 DQ Delay:
4776 20:17:27.442971 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4777 20:17:27.445974 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4778 20:17:27.449448 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4779 20:17:27.452745 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4780 20:17:27.452872
4781 20:17:27.452988
4782 20:17:27.459361 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4783 20:17:27.463071 CH1 RK1: MR19=808, MR18=6C23
4784 20:17:27.469360 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4785 20:17:27.473039 [RxdqsGatingPostProcess] freq 600
4786 20:17:27.476092 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 20:17:27.479145 Pre-setting of DQS Precalculation
4788 20:17:27.486073 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 20:17:27.492661 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 20:17:27.499308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 20:17:27.499495
4792 20:17:27.499610
4793 20:17:27.502820 [Calibration Summary] 1200 Mbps
4794 20:17:27.502942 CH 0, Rank 0
4795 20:17:27.505972 SW Impedance : PASS
4796 20:17:27.509047 DUTY Scan : NO K
4797 20:17:27.509170 ZQ Calibration : PASS
4798 20:17:27.512731 Jitter Meter : NO K
4799 20:17:27.515708 CBT Training : PASS
4800 20:17:27.515833 Write leveling : PASS
4801 20:17:27.518936 RX DQS gating : PASS
4802 20:17:27.522347 RX DQ/DQS(RDDQC) : PASS
4803 20:17:27.522500 TX DQ/DQS : PASS
4804 20:17:27.525996 RX DATLAT : PASS
4805 20:17:27.528918 RX DQ/DQS(Engine): PASS
4806 20:17:27.529042 TX OE : NO K
4807 20:17:27.529157 All Pass.
4808 20:17:27.529267
4809 20:17:27.532275 CH 0, Rank 1
4810 20:17:27.535712 SW Impedance : PASS
4811 20:17:27.535835 DUTY Scan : NO K
4812 20:17:27.539336 ZQ Calibration : PASS
4813 20:17:27.539456 Jitter Meter : NO K
4814 20:17:27.542361 CBT Training : PASS
4815 20:17:27.546025 Write leveling : PASS
4816 20:17:27.546147 RX DQS gating : PASS
4817 20:17:27.549244 RX DQ/DQS(RDDQC) : PASS
4818 20:17:27.552231 TX DQ/DQS : PASS
4819 20:17:27.552389 RX DATLAT : PASS
4820 20:17:27.555962 RX DQ/DQS(Engine): PASS
4821 20:17:27.559266 TX OE : NO K
4822 20:17:27.559388 All Pass.
4823 20:17:27.559500
4824 20:17:27.559608 CH 1, Rank 0
4825 20:17:27.562386 SW Impedance : PASS
4826 20:17:27.566232 DUTY Scan : NO K
4827 20:17:27.566356 ZQ Calibration : PASS
4828 20:17:27.569112 Jitter Meter : NO K
4829 20:17:27.572503 CBT Training : PASS
4830 20:17:27.572644 Write leveling : PASS
4831 20:17:27.575377 RX DQS gating : PASS
4832 20:17:27.579123 RX DQ/DQS(RDDQC) : PASS
4833 20:17:27.579239 TX DQ/DQS : PASS
4834 20:17:27.582365 RX DATLAT : PASS
4835 20:17:27.582482 RX DQ/DQS(Engine): PASS
4836 20:17:27.585680 TX OE : NO K
4837 20:17:27.585801 All Pass.
4838 20:17:27.585894
4839 20:17:27.589298 CH 1, Rank 1
4840 20:17:27.589380 SW Impedance : PASS
4841 20:17:27.592435 DUTY Scan : NO K
4842 20:17:27.595913 ZQ Calibration : PASS
4843 20:17:27.596043 Jitter Meter : NO K
4844 20:17:27.598979 CBT Training : PASS
4845 20:17:27.602532 Write leveling : PASS
4846 20:17:27.602653 RX DQS gating : PASS
4847 20:17:27.605810 RX DQ/DQS(RDDQC) : PASS
4848 20:17:27.609200 TX DQ/DQS : PASS
4849 20:17:27.609321 RX DATLAT : PASS
4850 20:17:27.612523 RX DQ/DQS(Engine): PASS
4851 20:17:27.612647 TX OE : NO K
4852 20:17:27.616211 All Pass.
4853 20:17:27.616325
4854 20:17:27.616422 DramC Write-DBI off
4855 20:17:27.619289 PER_BANK_REFRESH: Hybrid Mode
4856 20:17:27.622387 TX_TRACKING: ON
4857 20:17:27.628897 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 20:17:27.632673 [FAST_K] Save calibration result to emmc
4859 20:17:27.639163 dramc_set_vcore_voltage set vcore to 662500
4860 20:17:27.639247 Read voltage for 933, 3
4861 20:17:27.639314 Vio18 = 0
4862 20:17:27.642424 Vcore = 662500
4863 20:17:27.642507 Vdram = 0
4864 20:17:27.642574 Vddq = 0
4865 20:17:27.646013 Vmddr = 0
4866 20:17:27.649029 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 20:17:27.655733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 20:17:27.658857 MEM_TYPE=3, freq_sel=17
4869 20:17:27.658986 sv_algorithm_assistance_LP4_1600
4870 20:17:27.665609 ============ PULL DRAM RESETB DOWN ============
4871 20:17:27.668678 ========== PULL DRAM RESETB DOWN end =========
4872 20:17:27.672225 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 20:17:27.675625 ===================================
4874 20:17:27.678456 LPDDR4 DRAM CONFIGURATION
4875 20:17:27.681843 ===================================
4876 20:17:27.685575 EX_ROW_EN[0] = 0x0
4877 20:17:27.685661 EX_ROW_EN[1] = 0x0
4878 20:17:27.688461 LP4Y_EN = 0x0
4879 20:17:27.688550 WORK_FSP = 0x0
4880 20:17:27.691718 WL = 0x3
4881 20:17:27.691804 RL = 0x3
4882 20:17:27.695484 BL = 0x2
4883 20:17:27.695571 RPST = 0x0
4884 20:17:27.698648 RD_PRE = 0x0
4885 20:17:27.698734 WR_PRE = 0x1
4886 20:17:27.701799 WR_PST = 0x0
4887 20:17:27.701886 DBI_WR = 0x0
4888 20:17:27.705196 DBI_RD = 0x0
4889 20:17:27.708927 OTF = 0x1
4890 20:17:27.711974 ===================================
4891 20:17:27.715209 ===================================
4892 20:17:27.715294 ANA top config
4893 20:17:27.718269 ===================================
4894 20:17:27.721578 DLL_ASYNC_EN = 0
4895 20:17:27.721662 ALL_SLAVE_EN = 1
4896 20:17:27.725021 NEW_RANK_MODE = 1
4897 20:17:27.728597 DLL_IDLE_MODE = 1
4898 20:17:27.732083 LP45_APHY_COMB_EN = 1
4899 20:17:27.735177 TX_ODT_DIS = 1
4900 20:17:27.735262 NEW_8X_MODE = 1
4901 20:17:27.738398 ===================================
4902 20:17:27.741938 ===================================
4903 20:17:27.744877 data_rate = 1866
4904 20:17:27.748299 CKR = 1
4905 20:17:27.751586 DQ_P2S_RATIO = 8
4906 20:17:27.755041 ===================================
4907 20:17:27.758143 CA_P2S_RATIO = 8
4908 20:17:27.761861 DQ_CA_OPEN = 0
4909 20:17:27.761946 DQ_SEMI_OPEN = 0
4910 20:17:27.764895 CA_SEMI_OPEN = 0
4911 20:17:27.768087 CA_FULL_RATE = 0
4912 20:17:27.771853 DQ_CKDIV4_EN = 1
4913 20:17:27.774885 CA_CKDIV4_EN = 1
4914 20:17:27.778045 CA_PREDIV_EN = 0
4915 20:17:27.778123 PH8_DLY = 0
4916 20:17:27.781528 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 20:17:27.784720 DQ_AAMCK_DIV = 4
4918 20:17:27.788282 CA_AAMCK_DIV = 4
4919 20:17:27.791261 CA_ADMCK_DIV = 4
4920 20:17:27.794569 DQ_TRACK_CA_EN = 0
4921 20:17:27.794657 CA_PICK = 933
4922 20:17:27.798183 CA_MCKIO = 933
4923 20:17:27.801245 MCKIO_SEMI = 0
4924 20:17:27.804817 PLL_FREQ = 3732
4925 20:17:27.807970 DQ_UI_PI_RATIO = 32
4926 20:17:27.811645 CA_UI_PI_RATIO = 0
4927 20:17:27.814779 ===================================
4928 20:17:27.818234 ===================================
4929 20:17:27.818319 memory_type:LPDDR4
4930 20:17:27.820983 GP_NUM : 10
4931 20:17:27.824435 SRAM_EN : 1
4932 20:17:27.824521 MD32_EN : 0
4933 20:17:27.827939 ===================================
4934 20:17:27.831328 [ANA_INIT] >>>>>>>>>>>>>>
4935 20:17:27.834694 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 20:17:27.837692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 20:17:27.841131 ===================================
4938 20:17:27.844353 data_rate = 1866,PCW = 0X8f00
4939 20:17:27.847897 ===================================
4940 20:17:27.851045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 20:17:27.854692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 20:17:27.861237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 20:17:27.864456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 20:17:27.867600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 20:17:27.871210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 20:17:27.874259 [ANA_INIT] flow start
4947 20:17:27.877384 [ANA_INIT] PLL >>>>>>>>
4948 20:17:27.877494 [ANA_INIT] PLL <<<<<<<<
4949 20:17:27.881143 [ANA_INIT] MIDPI >>>>>>>>
4950 20:17:27.884130 [ANA_INIT] MIDPI <<<<<<<<
4951 20:17:27.887881 [ANA_INIT] DLL >>>>>>>>
4952 20:17:27.887978 [ANA_INIT] flow end
4953 20:17:27.891398 ============ LP4 DIFF to SE enter ============
4954 20:17:27.897351 ============ LP4 DIFF to SE exit ============
4955 20:17:27.897433 [ANA_INIT] <<<<<<<<<<<<<
4956 20:17:27.900737 [Flow] Enable top DCM control >>>>>
4957 20:17:27.904369 [Flow] Enable top DCM control <<<<<
4958 20:17:27.907632 Enable DLL master slave shuffle
4959 20:17:27.914449 ==============================================================
4960 20:17:27.914532 Gating Mode config
4961 20:17:27.920568 ==============================================================
4962 20:17:27.924123 Config description:
4963 20:17:27.934071 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 20:17:27.940616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 20:17:27.943870 SELPH_MODE 0: By rank 1: By Phase
4966 20:17:27.950422 ==============================================================
4967 20:17:27.953858 GAT_TRACK_EN = 1
4968 20:17:27.953941 RX_GATING_MODE = 2
4969 20:17:27.957356 RX_GATING_TRACK_MODE = 2
4970 20:17:27.960756 SELPH_MODE = 1
4971 20:17:27.963921 PICG_EARLY_EN = 1
4972 20:17:27.967305 VALID_LAT_VALUE = 1
4973 20:17:27.974080 ==============================================================
4974 20:17:27.977271 Enter into Gating configuration >>>>
4975 20:17:27.980928 Exit from Gating configuration <<<<
4976 20:17:27.984003 Enter into DVFS_PRE_config >>>>>
4977 20:17:27.993903 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 20:17:27.997045 Exit from DVFS_PRE_config <<<<<
4979 20:17:28.000728 Enter into PICG configuration >>>>
4980 20:17:28.003971 Exit from PICG configuration <<<<
4981 20:17:28.007081 [RX_INPUT] configuration >>>>>
4982 20:17:28.010896 [RX_INPUT] configuration <<<<<
4983 20:17:28.013922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 20:17:28.020617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 20:17:28.026840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 20:17:28.030655 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 20:17:28.037235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 20:17:28.043724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 20:17:28.046770 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 20:17:28.053567 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 20:17:28.056812 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 20:17:28.060548 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 20:17:28.063419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 20:17:28.070334 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 20:17:28.073775 ===================================
4996 20:17:28.073858 LPDDR4 DRAM CONFIGURATION
4997 20:17:28.076959 ===================================
4998 20:17:28.080117 EX_ROW_EN[0] = 0x0
4999 20:17:28.083696 EX_ROW_EN[1] = 0x0
5000 20:17:28.083778 LP4Y_EN = 0x0
5001 20:17:28.086974 WORK_FSP = 0x0
5002 20:17:28.087075 WL = 0x3
5003 20:17:28.090109 RL = 0x3
5004 20:17:28.090192 BL = 0x2
5005 20:17:28.093793 RPST = 0x0
5006 20:17:28.093875 RD_PRE = 0x0
5007 20:17:28.097104 WR_PRE = 0x1
5008 20:17:28.097187 WR_PST = 0x0
5009 20:17:28.100175 DBI_WR = 0x0
5010 20:17:28.100290 DBI_RD = 0x0
5011 20:17:28.103258 OTF = 0x1
5012 20:17:28.106986 ===================================
5013 20:17:28.110257 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 20:17:28.113812 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 20:17:28.120615 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 20:17:28.123679 ===================================
5017 20:17:28.123761 LPDDR4 DRAM CONFIGURATION
5018 20:17:28.126768 ===================================
5019 20:17:28.130412 EX_ROW_EN[0] = 0x10
5020 20:17:28.130494 EX_ROW_EN[1] = 0x0
5021 20:17:28.133567 LP4Y_EN = 0x0
5022 20:17:28.133649 WORK_FSP = 0x0
5023 20:17:28.137210 WL = 0x3
5024 20:17:28.137291 RL = 0x3
5025 20:17:28.140205 BL = 0x2
5026 20:17:28.143175 RPST = 0x0
5027 20:17:28.143290 RD_PRE = 0x0
5028 20:17:28.146825 WR_PRE = 0x1
5029 20:17:28.146907 WR_PST = 0x0
5030 20:17:28.149896 DBI_WR = 0x0
5031 20:17:28.149978 DBI_RD = 0x0
5032 20:17:28.153623 OTF = 0x1
5033 20:17:28.156590 ===================================
5034 20:17:28.160194 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 20:17:28.165683 nWR fixed to 30
5036 20:17:28.168919 [ModeRegInit_LP4] CH0 RK0
5037 20:17:28.169050 [ModeRegInit_LP4] CH0 RK1
5038 20:17:28.172182 [ModeRegInit_LP4] CH1 RK0
5039 20:17:28.175571 [ModeRegInit_LP4] CH1 RK1
5040 20:17:28.175695 match AC timing 9
5041 20:17:28.182586 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 20:17:28.185559 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 20:17:28.188736 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 20:17:28.195379 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 20:17:28.199026 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 20:17:28.199109 ==
5047 20:17:28.202023 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 20:17:28.205262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 20:17:28.205344 ==
5050 20:17:28.212007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 20:17:28.218737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 20:17:28.222417 [CA 0] Center 37 (6~68) winsize 63
5053 20:17:28.225084 [CA 1] Center 37 (7~68) winsize 62
5054 20:17:28.228764 [CA 2] Center 34 (4~65) winsize 62
5055 20:17:28.231963 [CA 3] Center 34 (3~65) winsize 63
5056 20:17:28.235137 [CA 4] Center 33 (3~64) winsize 62
5057 20:17:28.238921 [CA 5] Center 32 (2~62) winsize 61
5058 20:17:28.239003
5059 20:17:28.242104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 20:17:28.242186
5061 20:17:28.245118 [CATrainingPosCal] consider 1 rank data
5062 20:17:28.248723 u2DelayCellTimex100 = 270/100 ps
5063 20:17:28.252201 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5064 20:17:28.255225 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 20:17:28.258399 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5066 20:17:28.262112 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5067 20:17:28.265250 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5068 20:17:28.268900 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5069 20:17:28.272036
5070 20:17:28.275088 CA PerBit enable=1, Macro0, CA PI delay=32
5071 20:17:28.275202
5072 20:17:28.278699 [CBTSetCACLKResult] CA Dly = 32
5073 20:17:28.278781 CS Dly: 5 (0~36)
5074 20:17:28.278846 ==
5075 20:17:28.281962 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 20:17:28.285252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 20:17:28.288617 ==
5078 20:17:28.291685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 20:17:28.298725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 20:17:28.301735 [CA 0] Center 37 (7~68) winsize 62
5081 20:17:28.305400 [CA 1] Center 37 (7~68) winsize 62
5082 20:17:28.308479 [CA 2] Center 34 (4~65) winsize 62
5083 20:17:28.311986 [CA 3] Center 34 (4~65) winsize 62
5084 20:17:28.315213 [CA 4] Center 33 (3~63) winsize 61
5085 20:17:28.318541 [CA 5] Center 32 (2~62) winsize 61
5086 20:17:28.318624
5087 20:17:28.321618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 20:17:28.321701
5089 20:17:28.324934 [CATrainingPosCal] consider 2 rank data
5090 20:17:28.328544 u2DelayCellTimex100 = 270/100 ps
5091 20:17:28.331529 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5092 20:17:28.335099 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 20:17:28.338556 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5094 20:17:28.341846 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5095 20:17:28.344997 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5096 20:17:28.351754 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5097 20:17:28.351836
5098 20:17:28.355299 CA PerBit enable=1, Macro0, CA PI delay=32
5099 20:17:28.355381
5100 20:17:28.358789 [CBTSetCACLKResult] CA Dly = 32
5101 20:17:28.358872 CS Dly: 5 (0~37)
5102 20:17:28.358941
5103 20:17:28.361892 ----->DramcWriteLeveling(PI) begin...
5104 20:17:28.361976 ==
5105 20:17:28.364912 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 20:17:28.371619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 20:17:28.371717 ==
5108 20:17:28.375344 Write leveling (Byte 0): 30 => 30
5109 20:17:28.375427 Write leveling (Byte 1): 29 => 29
5110 20:17:28.378397 DramcWriteLeveling(PI) end<-----
5111 20:17:28.378513
5112 20:17:28.378610 ==
5113 20:17:28.381717 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 20:17:28.388234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 20:17:28.388341 ==
5116 20:17:28.391641 [Gating] SW mode calibration
5117 20:17:28.398328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 20:17:28.401668 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 20:17:28.408499 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
5120 20:17:28.411613 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 20:17:28.414684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 20:17:28.421990 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 20:17:28.425107 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 20:17:28.428194 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 20:17:28.434689 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5126 20:17:28.438289 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
5127 20:17:28.441272 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5128 20:17:28.445070 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 20:17:28.451139 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 20:17:28.454804 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 20:17:28.458053 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 20:17:28.464741 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 20:17:28.467970 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 20:17:28.471562 0 15 28 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5135 20:17:28.477654 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5136 20:17:28.481439 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 20:17:28.485095 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 20:17:28.491173 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 20:17:28.494564 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 20:17:28.498210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 20:17:28.504979 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 20:17:28.507952 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 20:17:28.511649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 20:17:28.518004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 20:17:28.521121 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 20:17:28.524807 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 20:17:28.531000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 20:17:28.534707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 20:17:28.537788 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 20:17:28.544714 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 20:17:28.547789 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 20:17:28.550958 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 20:17:28.557960 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 20:17:28.561154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 20:17:28.564248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 20:17:28.570888 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 20:17:28.574251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 20:17:28.577475 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5159 20:17:28.581072 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 20:17:28.584603 Total UI for P1: 0, mck2ui 16
5161 20:17:28.587770 best dqsien dly found for B0: ( 1, 2, 26)
5162 20:17:28.590847 Total UI for P1: 0, mck2ui 16
5163 20:17:28.594474 best dqsien dly found for B1: ( 1, 2, 30)
5164 20:17:28.597732 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5165 20:17:28.601086 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5166 20:17:28.601169
5167 20:17:28.607868 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5168 20:17:28.610895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5169 20:17:28.614643 [Gating] SW calibration Done
5170 20:17:28.614729 ==
5171 20:17:28.617681 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 20:17:28.620790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 20:17:28.620898 ==
5174 20:17:28.620992 RX Vref Scan: 0
5175 20:17:28.621081
5176 20:17:28.624259 RX Vref 0 -> 0, step: 1
5177 20:17:28.624363
5178 20:17:28.627509 RX Delay -80 -> 252, step: 8
5179 20:17:28.631356 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5180 20:17:28.634430 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5181 20:17:28.640967 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5182 20:17:28.644494 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5183 20:17:28.647577 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5184 20:17:28.650645 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5185 20:17:28.654310 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5186 20:17:28.657317 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5187 20:17:28.664378 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5188 20:17:28.667384 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5189 20:17:28.671127 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5190 20:17:28.674138 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5191 20:17:28.677188 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5192 20:17:28.680885 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5193 20:17:28.687609 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5194 20:17:28.690747 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5195 20:17:28.690831 ==
5196 20:17:28.693628 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 20:17:28.697010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 20:17:28.697093 ==
5199 20:17:28.700613 DQS Delay:
5200 20:17:28.700701 DQS0 = 0, DQS1 = 0
5201 20:17:28.700767 DQM Delay:
5202 20:17:28.703743 DQM0 = 104, DQM1 = 95
5203 20:17:28.703825 DQ Delay:
5204 20:17:28.707106 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5205 20:17:28.710687 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5206 20:17:28.713573 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5207 20:17:28.717563 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5208 20:17:28.717722
5209 20:17:28.717838
5210 20:17:28.720632 ==
5211 20:17:28.723859 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 20:17:28.727191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 20:17:28.727335 ==
5214 20:17:28.727466
5215 20:17:28.727576
5216 20:17:28.730787 TX Vref Scan disable
5217 20:17:28.730895 == TX Byte 0 ==
5218 20:17:28.736935 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5219 20:17:28.740424 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5220 20:17:28.740507 == TX Byte 1 ==
5221 20:17:28.743360 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5222 20:17:28.750629 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5223 20:17:28.750712 ==
5224 20:17:28.753555 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 20:17:28.756619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 20:17:28.756751 ==
5227 20:17:28.756859
5228 20:17:28.756920
5229 20:17:28.760504 TX Vref Scan disable
5230 20:17:28.763452 == TX Byte 0 ==
5231 20:17:28.766649 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5232 20:17:28.770308 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5233 20:17:28.773439 == TX Byte 1 ==
5234 20:17:28.777049 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5235 20:17:28.780103 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5236 20:17:28.780220
5237 20:17:28.783459 [DATLAT]
5238 20:17:28.783582 Freq=933, CH0 RK0
5239 20:17:28.783698
5240 20:17:28.786868 DATLAT Default: 0xd
5241 20:17:28.786993 0, 0xFFFF, sum = 0
5242 20:17:28.790493 1, 0xFFFF, sum = 0
5243 20:17:28.790625 2, 0xFFFF, sum = 0
5244 20:17:28.793752 3, 0xFFFF, sum = 0
5245 20:17:28.793878 4, 0xFFFF, sum = 0
5246 20:17:28.796866 5, 0xFFFF, sum = 0
5247 20:17:28.796991 6, 0xFFFF, sum = 0
5248 20:17:28.799852 7, 0xFFFF, sum = 0
5249 20:17:28.799977 8, 0xFFFF, sum = 0
5250 20:17:28.803565 9, 0xFFFF, sum = 0
5251 20:17:28.803692 10, 0x0, sum = 1
5252 20:17:28.806746 11, 0x0, sum = 2
5253 20:17:28.806875 12, 0x0, sum = 3
5254 20:17:28.809741 13, 0x0, sum = 4
5255 20:17:28.809868 best_step = 11
5256 20:17:28.809980
5257 20:17:28.810091 ==
5258 20:17:28.813499 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 20:17:28.816495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 20:17:28.819836 ==
5261 20:17:28.819996 RX Vref Scan: 1
5262 20:17:28.820114
5263 20:17:28.822826 RX Vref 0 -> 0, step: 1
5264 20:17:28.822947
5265 20:17:28.826257 RX Delay -45 -> 252, step: 4
5266 20:17:28.826381
5267 20:17:28.829782 Set Vref, RX VrefLevel [Byte0]: 56
5268 20:17:28.832980 [Byte1]: 57
5269 20:17:28.833101
5270 20:17:28.836482 Final RX Vref Byte 0 = 56 to rank0
5271 20:17:28.840038 Final RX Vref Byte 1 = 57 to rank0
5272 20:17:28.843235 Final RX Vref Byte 0 = 56 to rank1
5273 20:17:28.846311 Final RX Vref Byte 1 = 57 to rank1==
5274 20:17:28.849923 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 20:17:28.852853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 20:17:28.852938 ==
5277 20:17:28.856106 DQS Delay:
5278 20:17:28.856229 DQS0 = 0, DQS1 = 0
5279 20:17:28.856350 DQM Delay:
5280 20:17:28.859452 DQM0 = 104, DQM1 = 97
5281 20:17:28.859579 DQ Delay:
5282 20:17:28.862761 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5283 20:17:28.866211 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5284 20:17:28.869648 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5285 20:17:28.872665 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5286 20:17:28.872747
5287 20:17:28.876445
5288 20:17:28.882561 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5289 20:17:28.886133 CH0 RK0: MR19=505, MR18=332B
5290 20:17:28.892539 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5291 20:17:28.892664
5292 20:17:28.896055 ----->DramcWriteLeveling(PI) begin...
5293 20:17:28.896174 ==
5294 20:17:28.899332 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 20:17:28.903076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 20:17:28.903200 ==
5297 20:17:28.906234 Write leveling (Byte 0): 33 => 33
5298 20:17:28.909276 Write leveling (Byte 1): 30 => 30
5299 20:17:28.913018 DramcWriteLeveling(PI) end<-----
5300 20:17:28.913136
5301 20:17:28.913247 ==
5302 20:17:28.916045 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 20:17:28.919697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 20:17:28.919819 ==
5305 20:17:28.922745 [Gating] SW mode calibration
5306 20:17:28.929234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 20:17:28.935973 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 20:17:28.939662 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5309 20:17:28.942730 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 20:17:28.949301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 20:17:28.952634 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 20:17:28.956089 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 20:17:28.962442 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 20:17:28.965580 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
5315 20:17:28.969462 0 14 28 | B1->B0 | 2b2b 2b2b | 0 0 | (1 0) (0 1)
5316 20:17:28.975688 0 15 0 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5317 20:17:28.979236 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 20:17:28.982272 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 20:17:28.989206 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 20:17:28.992085 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 20:17:28.995607 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 20:17:29.002226 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5323 20:17:29.006022 0 15 28 | B1->B0 | 3d3d 3938 | 0 1 | (0 0) (0 0)
5324 20:17:29.009097 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5325 20:17:29.015774 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 20:17:29.018721 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 20:17:29.021847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 20:17:29.029016 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 20:17:29.032517 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 20:17:29.035542 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 20:17:29.041763 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5332 20:17:29.045408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5333 20:17:29.048890 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 20:17:29.051914 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 20:17:29.058719 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 20:17:29.062079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 20:17:29.065375 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 20:17:29.072085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 20:17:29.075443 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 20:17:29.079017 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 20:17:29.085500 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 20:17:29.088530 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 20:17:29.092115 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 20:17:29.098314 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 20:17:29.101782 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 20:17:29.104937 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 20:17:29.111732 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5348 20:17:29.115368 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 20:17:29.118688 Total UI for P1: 0, mck2ui 16
5350 20:17:29.121689 best dqsien dly found for B0: ( 1, 2, 28)
5351 20:17:29.125473 Total UI for P1: 0, mck2ui 16
5352 20:17:29.128707 best dqsien dly found for B1: ( 1, 2, 30)
5353 20:17:29.131603 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5354 20:17:29.135070 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5355 20:17:29.135193
5356 20:17:29.138845 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5357 20:17:29.142015 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5358 20:17:29.145036 [Gating] SW calibration Done
5359 20:17:29.145156 ==
5360 20:17:29.148651 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 20:17:29.151743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 20:17:29.151866 ==
5363 20:17:29.155434 RX Vref Scan: 0
5364 20:17:29.155555
5365 20:17:29.158665 RX Vref 0 -> 0, step: 1
5366 20:17:29.158789
5367 20:17:29.158903 RX Delay -80 -> 252, step: 8
5368 20:17:29.165235 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5369 20:17:29.168408 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5370 20:17:29.171603 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5371 20:17:29.175289 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5372 20:17:29.178221 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5373 20:17:29.184958 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5374 20:17:29.188508 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5375 20:17:29.191531 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5376 20:17:29.195365 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5377 20:17:29.198455 iDelay=208, Bit 9, Center 91 (8 ~ 175) 168
5378 20:17:29.202095 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5379 20:17:29.208892 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5380 20:17:29.211936 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5381 20:17:29.215402 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5382 20:17:29.218543 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5383 20:17:29.221658 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5384 20:17:29.221781 ==
5385 20:17:29.224987 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 20:17:29.231997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 20:17:29.232119 ==
5388 20:17:29.232248 DQS Delay:
5389 20:17:29.232376 DQS0 = 0, DQS1 = 0
5390 20:17:29.234886 DQM Delay:
5391 20:17:29.235003 DQM0 = 105, DQM1 = 95
5392 20:17:29.238427 DQ Delay:
5393 20:17:29.241531 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5394 20:17:29.245060 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5395 20:17:29.248628 DQ8 =87, DQ9 =91, DQ10 =95, DQ11 =91
5396 20:17:29.251592 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5397 20:17:29.251713
5398 20:17:29.251823
5399 20:17:29.251931 ==
5400 20:17:29.255295 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 20:17:29.258816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 20:17:29.258940 ==
5403 20:17:29.259050
5404 20:17:29.259160
5405 20:17:29.261903 TX Vref Scan disable
5406 20:17:29.264889 == TX Byte 0 ==
5407 20:17:29.268449 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5408 20:17:29.271558 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5409 20:17:29.275267 == TX Byte 1 ==
5410 20:17:29.278451 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5411 20:17:29.281551 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5412 20:17:29.281675 ==
5413 20:17:29.285238 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 20:17:29.288224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 20:17:29.288367 ==
5416 20:17:29.291657
5417 20:17:29.291754
5418 20:17:29.291842 TX Vref Scan disable
5419 20:17:29.294933 == TX Byte 0 ==
5420 20:17:29.298633 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5421 20:17:29.305190 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5422 20:17:29.305310 == TX Byte 1 ==
5423 20:17:29.308380 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5424 20:17:29.315012 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5425 20:17:29.315134
5426 20:17:29.315249 [DATLAT]
5427 20:17:29.315359 Freq=933, CH0 RK1
5428 20:17:29.315465
5429 20:17:29.318128 DATLAT Default: 0xb
5430 20:17:29.318250 0, 0xFFFF, sum = 0
5431 20:17:29.321294 1, 0xFFFF, sum = 0
5432 20:17:29.324936 2, 0xFFFF, sum = 0
5433 20:17:29.325060 3, 0xFFFF, sum = 0
5434 20:17:29.327997 4, 0xFFFF, sum = 0
5435 20:17:29.328119 5, 0xFFFF, sum = 0
5436 20:17:29.331658 6, 0xFFFF, sum = 0
5437 20:17:29.331781 7, 0xFFFF, sum = 0
5438 20:17:29.334742 8, 0xFFFF, sum = 0
5439 20:17:29.334865 9, 0xFFFF, sum = 0
5440 20:17:29.338437 10, 0x0, sum = 1
5441 20:17:29.338559 11, 0x0, sum = 2
5442 20:17:29.341634 12, 0x0, sum = 3
5443 20:17:29.341758 13, 0x0, sum = 4
5444 20:17:29.341873 best_step = 11
5445 20:17:29.341981
5446 20:17:29.344967 ==
5447 20:17:29.347958 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 20:17:29.351626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 20:17:29.351745 ==
5450 20:17:29.351859 RX Vref Scan: 0
5451 20:17:29.351960
5452 20:17:29.355194 RX Vref 0 -> 0, step: 1
5453 20:17:29.355314
5454 20:17:29.357843 RX Delay -45 -> 252, step: 4
5455 20:17:29.361415 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5456 20:17:29.368083 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5457 20:17:29.371377 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5458 20:17:29.374643 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5459 20:17:29.378259 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5460 20:17:29.381137 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5461 20:17:29.388060 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5462 20:17:29.391122 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5463 20:17:29.394843 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5464 20:17:29.398294 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5465 20:17:29.401642 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5466 20:17:29.404631 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5467 20:17:29.411686 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5468 20:17:29.414705 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5469 20:17:29.417697 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5470 20:17:29.421514 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5471 20:17:29.421637 ==
5472 20:17:29.424576 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 20:17:29.431244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 20:17:29.431368 ==
5475 20:17:29.431475 DQS Delay:
5476 20:17:29.434248 DQS0 = 0, DQS1 = 0
5477 20:17:29.434368 DQM Delay:
5478 20:17:29.434480 DQM0 = 104, DQM1 = 95
5479 20:17:29.437900 DQ Delay:
5480 20:17:29.440976 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5481 20:17:29.444640 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5482 20:17:29.447782 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5483 20:17:29.451353 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5484 20:17:29.451437
5485 20:17:29.451503
5486 20:17:29.461036 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5487 20:17:29.461120 CH0 RK1: MR19=505, MR18=2902
5488 20:17:29.467592 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5489 20:17:29.471140 [RxdqsGatingPostProcess] freq 933
5490 20:17:29.477623 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 20:17:29.480822 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 20:17:29.484076 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 20:17:29.487595 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 20:17:29.490923 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 20:17:29.491062 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 20:17:29.494042 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 20:17:29.497617 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 20:17:29.500683 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 20:17:29.504038 Pre-setting of DQS Precalculation
5500 20:17:29.510735 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 20:17:29.510824 ==
5502 20:17:29.513796 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 20:17:29.517451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 20:17:29.517535 ==
5505 20:17:29.524070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 20:17:29.530543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5507 20:17:29.533653 [CA 0] Center 36 (6~67) winsize 62
5508 20:17:29.537178 [CA 1] Center 37 (6~68) winsize 63
5509 20:17:29.540269 [CA 2] Center 34 (4~65) winsize 62
5510 20:17:29.543961 [CA 3] Center 34 (4~65) winsize 62
5511 20:17:29.547027 [CA 4] Center 34 (4~64) winsize 61
5512 20:17:29.547111 [CA 5] Center 33 (3~64) winsize 62
5513 20:17:29.550923
5514 20:17:29.553798 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5515 20:17:29.553881
5516 20:17:29.556799 [CATrainingPosCal] consider 1 rank data
5517 20:17:29.560446 u2DelayCellTimex100 = 270/100 ps
5518 20:17:29.563472 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 20:17:29.567294 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5520 20:17:29.570312 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5521 20:17:29.574024 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5522 20:17:29.576960 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 20:17:29.580658 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 20:17:29.580736
5525 20:17:29.583828 CA PerBit enable=1, Macro0, CA PI delay=33
5526 20:17:29.583912
5527 20:17:29.586971 [CBTSetCACLKResult] CA Dly = 33
5528 20:17:29.590709 CS Dly: 6 (0~37)
5529 20:17:29.590791 ==
5530 20:17:29.593824 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 20:17:29.596788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 20:17:29.596894 ==
5533 20:17:29.603444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 20:17:29.610270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 20:17:29.613593 [CA 0] Center 37 (6~68) winsize 63
5536 20:17:29.616813 [CA 1] Center 37 (7~68) winsize 62
5537 20:17:29.620532 [CA 2] Center 35 (5~66) winsize 62
5538 20:17:29.623592 [CA 3] Center 34 (4~65) winsize 62
5539 20:17:29.626758 [CA 4] Center 34 (4~65) winsize 62
5540 20:17:29.629763 [CA 5] Center 34 (4~64) winsize 61
5541 20:17:29.629866
5542 20:17:29.633723 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 20:17:29.633814
5544 20:17:29.636575 [CATrainingPosCal] consider 2 rank data
5545 20:17:29.639803 u2DelayCellTimex100 = 270/100 ps
5546 20:17:29.642923 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5547 20:17:29.646752 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5548 20:17:29.649796 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5549 20:17:29.653203 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5550 20:17:29.656229 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5551 20:17:29.659758 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5552 20:17:29.659862
5553 20:17:29.666220 CA PerBit enable=1, Macro0, CA PI delay=34
5554 20:17:29.666329
5555 20:17:29.666424 [CBTSetCACLKResult] CA Dly = 34
5556 20:17:29.669333 CS Dly: 7 (0~40)
5557 20:17:29.669407
5558 20:17:29.673061 ----->DramcWriteLeveling(PI) begin...
5559 20:17:29.673139 ==
5560 20:17:29.676166 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 20:17:29.679615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 20:17:29.679718 ==
5563 20:17:29.682705 Write leveling (Byte 0): 26 => 26
5564 20:17:29.686363 Write leveling (Byte 1): 29 => 29
5565 20:17:29.689362 DramcWriteLeveling(PI) end<-----
5566 20:17:29.689445
5567 20:17:29.689512 ==
5568 20:17:29.692534 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 20:17:29.699445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 20:17:29.699558 ==
5571 20:17:29.699662 [Gating] SW mode calibration
5572 20:17:29.709285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 20:17:29.712971 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 20:17:29.715802 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 20:17:29.722468 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 20:17:29.725847 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 20:17:29.729489 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 20:17:29.736195 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 20:17:29.739197 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5580 20:17:29.742287 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5581 20:17:29.749329 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5582 20:17:29.752748 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 20:17:29.755717 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 20:17:29.762681 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 20:17:29.765569 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 20:17:29.769156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 20:17:29.775879 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 20:17:29.778791 0 15 24 | B1->B0 | 2525 3130 | 1 1 | (0 0) (0 0)
5589 20:17:29.782477 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5590 20:17:29.789038 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 20:17:29.792707 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 20:17:29.795634 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 20:17:29.802562 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 20:17:29.805656 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 20:17:29.809185 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 20:17:29.815889 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5597 20:17:29.818978 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 20:17:29.822068 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 20:17:29.828705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 20:17:29.832255 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 20:17:29.835934 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 20:17:29.839015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 20:17:29.845854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 20:17:29.849006 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 20:17:29.851981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 20:17:29.858921 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 20:17:29.861971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 20:17:29.865443 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 20:17:29.872446 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 20:17:29.875674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 20:17:29.878749 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 20:17:29.885530 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5613 20:17:29.889076 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5614 20:17:29.892026 Total UI for P1: 0, mck2ui 16
5615 20:17:29.895332 best dqsien dly found for B1: ( 1, 2, 24)
5616 20:17:29.898712 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 20:17:29.902264 Total UI for P1: 0, mck2ui 16
5618 20:17:29.905223 best dqsien dly found for B0: ( 1, 2, 26)
5619 20:17:29.908539 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5620 20:17:29.912018 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5621 20:17:29.912126
5622 20:17:29.918400 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5623 20:17:29.922081 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5624 20:17:29.925095 [Gating] SW calibration Done
5625 20:17:29.925177 ==
5626 20:17:29.928651 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 20:17:29.931643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 20:17:29.931727 ==
5629 20:17:29.931793 RX Vref Scan: 0
5630 20:17:29.931855
5631 20:17:29.935359 RX Vref 0 -> 0, step: 1
5632 20:17:29.935440
5633 20:17:29.938327 RX Delay -80 -> 252, step: 8
5634 20:17:29.941668 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5635 20:17:29.945396 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5636 20:17:29.948524 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5637 20:17:29.955362 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5638 20:17:29.958331 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5639 20:17:29.961793 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5640 20:17:29.964607 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5641 20:17:29.968040 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5642 20:17:29.971623 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5643 20:17:29.978060 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5644 20:17:29.981903 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5645 20:17:29.984973 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5646 20:17:29.987950 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5647 20:17:29.991486 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5648 20:17:29.998156 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5649 20:17:30.001200 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5650 20:17:30.001307 ==
5651 20:17:30.004456 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 20:17:30.008122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 20:17:30.008229 ==
5654 20:17:30.008366 DQS Delay:
5655 20:17:30.011256 DQS0 = 0, DQS1 = 0
5656 20:17:30.011353 DQM Delay:
5657 20:17:30.014701 DQM0 = 102, DQM1 = 97
5658 20:17:30.014803 DQ Delay:
5659 20:17:30.018228 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5660 20:17:30.021441 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5661 20:17:30.024492 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5662 20:17:30.028022 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5663 20:17:30.028102
5664 20:17:30.028200
5665 20:17:30.028298 ==
5666 20:17:30.031346 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 20:17:30.037736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 20:17:30.037837 ==
5669 20:17:30.037939
5670 20:17:30.038027
5671 20:17:30.038126 TX Vref Scan disable
5672 20:17:30.041501 == TX Byte 0 ==
5673 20:17:30.044922 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5674 20:17:30.048672 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5675 20:17:30.051571 == TX Byte 1 ==
5676 20:17:30.055324 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5677 20:17:30.058380 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5678 20:17:30.061480 ==
5679 20:17:30.065295 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 20:17:30.068520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 20:17:30.068598 ==
5682 20:17:30.068662
5683 20:17:30.068721
5684 20:17:30.071529 TX Vref Scan disable
5685 20:17:30.071596 == TX Byte 0 ==
5686 20:17:30.078360 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5687 20:17:30.081268 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5688 20:17:30.081351 == TX Byte 1 ==
5689 20:17:30.088262 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5690 20:17:30.091316 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5691 20:17:30.091399
5692 20:17:30.091464 [DATLAT]
5693 20:17:30.094938 Freq=933, CH1 RK0
5694 20:17:30.095020
5695 20:17:30.095084 DATLAT Default: 0xd
5696 20:17:30.098055 0, 0xFFFF, sum = 0
5697 20:17:30.098138 1, 0xFFFF, sum = 0
5698 20:17:30.101815 2, 0xFFFF, sum = 0
5699 20:17:30.101898 3, 0xFFFF, sum = 0
5700 20:17:30.104991 4, 0xFFFF, sum = 0
5701 20:17:30.108070 5, 0xFFFF, sum = 0
5702 20:17:30.108153 6, 0xFFFF, sum = 0
5703 20:17:30.111717 7, 0xFFFF, sum = 0
5704 20:17:30.111800 8, 0xFFFF, sum = 0
5705 20:17:30.114846 9, 0xFFFF, sum = 0
5706 20:17:30.114929 10, 0x0, sum = 1
5707 20:17:30.114995 11, 0x0, sum = 2
5708 20:17:30.118326 12, 0x0, sum = 3
5709 20:17:30.118409 13, 0x0, sum = 4
5710 20:17:30.121485 best_step = 11
5711 20:17:30.121566
5712 20:17:30.121630 ==
5713 20:17:30.125171 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 20:17:30.128061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 20:17:30.128164 ==
5716 20:17:30.131226 RX Vref Scan: 1
5717 20:17:30.131316
5718 20:17:30.131396 RX Vref 0 -> 0, step: 1
5719 20:17:30.134706
5720 20:17:30.134825 RX Delay -45 -> 252, step: 4
5721 20:17:30.134919
5722 20:17:30.138226 Set Vref, RX VrefLevel [Byte0]: 55
5723 20:17:30.141522 [Byte1]: 53
5724 20:17:30.145555
5725 20:17:30.145662 Final RX Vref Byte 0 = 55 to rank0
5726 20:17:30.148910 Final RX Vref Byte 1 = 53 to rank0
5727 20:17:30.151974 Final RX Vref Byte 0 = 55 to rank1
5728 20:17:30.155525 Final RX Vref Byte 1 = 53 to rank1==
5729 20:17:30.159012 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 20:17:30.165793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 20:17:30.165906 ==
5732 20:17:30.166000 DQS Delay:
5733 20:17:30.166097 DQS0 = 0, DQS1 = 0
5734 20:17:30.168811 DQM Delay:
5735 20:17:30.168912 DQM0 = 104, DQM1 = 100
5736 20:17:30.172481 DQ Delay:
5737 20:17:30.175398 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5738 20:17:30.178908 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =104
5739 20:17:30.181867 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5740 20:17:30.185483 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108
5741 20:17:30.185573
5742 20:17:30.185648
5743 20:17:30.191943 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5744 20:17:30.195483 CH1 RK0: MR19=505, MR18=172E
5745 20:17:30.201982 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5746 20:17:30.202058
5747 20:17:30.205627 ----->DramcWriteLeveling(PI) begin...
5748 20:17:30.205729 ==
5749 20:17:30.208686 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 20:17:30.212469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 20:17:30.212564 ==
5752 20:17:30.215506 Write leveling (Byte 0): 29 => 29
5753 20:17:30.219206 Write leveling (Byte 1): 28 => 28
5754 20:17:30.222745 DramcWriteLeveling(PI) end<-----
5755 20:17:30.222851
5756 20:17:30.222958 ==
5757 20:17:30.225833 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 20:17:30.229317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 20:17:30.232446 ==
5760 20:17:30.232558 [Gating] SW mode calibration
5761 20:17:30.239151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 20:17:30.245824 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 20:17:30.248816 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 20:17:30.255693 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 20:17:30.258606 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 20:17:30.262326 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 20:17:30.268663 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 20:17:30.272089 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5769 20:17:30.275849 0 14 24 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 1)
5770 20:17:30.282125 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 0)
5771 20:17:30.285525 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 20:17:30.288625 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 20:17:30.295214 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 20:17:30.298587 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 20:17:30.301816 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 20:17:30.308877 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 20:17:30.312414 0 15 24 | B1->B0 | 3838 2727 | 0 0 | (0 0) (0 0)
5778 20:17:30.315611 0 15 28 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
5779 20:17:30.318616 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 20:17:30.325290 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 20:17:30.328394 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 20:17:30.331990 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 20:17:30.338905 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 20:17:30.341989 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 20:17:30.345056 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5786 20:17:30.352149 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5787 20:17:30.355112 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 20:17:30.358121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 20:17:30.364862 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 20:17:30.368517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 20:17:30.371542 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 20:17:30.378161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 20:17:30.381785 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 20:17:30.384903 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 20:17:30.391590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 20:17:30.394960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 20:17:30.398048 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 20:17:30.404614 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 20:17:30.408051 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 20:17:30.411542 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 20:17:30.418261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5802 20:17:30.421279 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 20:17:30.424704 Total UI for P1: 0, mck2ui 16
5804 20:17:30.428133 best dqsien dly found for B0: ( 1, 2, 24)
5805 20:17:30.431276 Total UI for P1: 0, mck2ui 16
5806 20:17:30.434990 best dqsien dly found for B1: ( 1, 2, 24)
5807 20:17:30.438121 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5808 20:17:30.441165 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5809 20:17:30.441272
5810 20:17:30.444812 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5811 20:17:30.447931 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 20:17:30.451125 [Gating] SW calibration Done
5813 20:17:30.451230 ==
5814 20:17:30.454815 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 20:17:30.457690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 20:17:30.461326 ==
5817 20:17:30.461416 RX Vref Scan: 0
5818 20:17:30.461479
5819 20:17:30.464433 RX Vref 0 -> 0, step: 1
5820 20:17:30.464536
5821 20:17:30.467528 RX Delay -80 -> 252, step: 8
5822 20:17:30.471088 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5823 20:17:30.474214 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5824 20:17:30.477914 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5825 20:17:30.481009 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5826 20:17:30.484649 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5827 20:17:30.491320 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5828 20:17:30.494436 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5829 20:17:30.497552 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5830 20:17:30.501188 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5831 20:17:30.504199 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5832 20:17:30.510815 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5833 20:17:30.514280 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5834 20:17:30.517892 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5835 20:17:30.520808 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5836 20:17:30.524517 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5837 20:17:30.531146 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5838 20:17:30.531248 ==
5839 20:17:30.534043 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 20:17:30.537288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 20:17:30.537386 ==
5842 20:17:30.537480 DQS Delay:
5843 20:17:30.540960 DQS0 = 0, DQS1 = 0
5844 20:17:30.541061 DQM Delay:
5845 20:17:30.544365 DQM0 = 104, DQM1 = 98
5846 20:17:30.544451 DQ Delay:
5847 20:17:30.547313 DQ0 =111, DQ1 =103, DQ2 =91, DQ3 =99
5848 20:17:30.550784 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =103
5849 20:17:30.554174 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5850 20:17:30.557219 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5851 20:17:30.557297
5852 20:17:30.557360
5853 20:17:30.557419 ==
5854 20:17:30.560742 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 20:17:30.567101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 20:17:30.567209 ==
5857 20:17:30.567307
5858 20:17:30.567397
5859 20:17:30.567465 TX Vref Scan disable
5860 20:17:30.570807 == TX Byte 0 ==
5861 20:17:30.574339 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5862 20:17:30.577398 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5863 20:17:30.580700 == TX Byte 1 ==
5864 20:17:30.584313 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 20:17:30.590959 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 20:17:30.591043 ==
5867 20:17:30.593945 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 20:17:30.597204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 20:17:30.597278 ==
5870 20:17:30.597341
5871 20:17:30.597407
5872 20:17:30.600780 TX Vref Scan disable
5873 20:17:30.600865 == TX Byte 0 ==
5874 20:17:30.607094 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5875 20:17:30.610278 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5876 20:17:30.610354 == TX Byte 1 ==
5877 20:17:30.617462 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5878 20:17:30.620632 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5879 20:17:30.620709
5880 20:17:30.620776 [DATLAT]
5881 20:17:30.623644 Freq=933, CH1 RK1
5882 20:17:30.623735
5883 20:17:30.623809 DATLAT Default: 0xb
5884 20:17:30.627532 0, 0xFFFF, sum = 0
5885 20:17:30.627653 1, 0xFFFF, sum = 0
5886 20:17:30.630503 2, 0xFFFF, sum = 0
5887 20:17:30.630606 3, 0xFFFF, sum = 0
5888 20:17:30.633852 4, 0xFFFF, sum = 0
5889 20:17:30.633947 5, 0xFFFF, sum = 0
5890 20:17:30.637088 6, 0xFFFF, sum = 0
5891 20:17:30.637160 7, 0xFFFF, sum = 0
5892 20:17:30.640966 8, 0xFFFF, sum = 0
5893 20:17:30.643845 9, 0xFFFF, sum = 0
5894 20:17:30.643936 10, 0x0, sum = 1
5895 20:17:30.644000 11, 0x0, sum = 2
5896 20:17:30.647312 12, 0x0, sum = 3
5897 20:17:30.647415 13, 0x0, sum = 4
5898 20:17:30.650739 best_step = 11
5899 20:17:30.650843
5900 20:17:30.650935 ==
5901 20:17:30.653815 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 20:17:30.657292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 20:17:30.657399 ==
5904 20:17:30.660254 RX Vref Scan: 0
5905 20:17:30.660385
5906 20:17:30.660479 RX Vref 0 -> 0, step: 1
5907 20:17:30.660568
5908 20:17:30.663438 RX Delay -53 -> 252, step: 4
5909 20:17:30.671213 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5910 20:17:30.674133 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5911 20:17:30.677726 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5912 20:17:30.681362 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5913 20:17:30.684223 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5914 20:17:30.691218 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5915 20:17:30.694288 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5916 20:17:30.697864 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5917 20:17:30.700906 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5918 20:17:30.704563 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5919 20:17:30.707605 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5920 20:17:30.714281 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5921 20:17:30.717935 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5922 20:17:30.720983 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5923 20:17:30.724650 iDelay=203, Bit 14, Center 108 (27 ~ 190) 164
5924 20:17:30.727694 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5925 20:17:30.731135 ==
5926 20:17:30.734495 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 20:17:30.737509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 20:17:30.737589 ==
5929 20:17:30.737664 DQS Delay:
5930 20:17:30.740992 DQS0 = 0, DQS1 = 0
5931 20:17:30.741095 DQM Delay:
5932 20:17:30.744642 DQM0 = 105, DQM1 = 100
5933 20:17:30.744717 DQ Delay:
5934 20:17:30.748054 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5935 20:17:30.751125 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5936 20:17:30.754570 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5937 20:17:30.757963 DQ12 =110, DQ13 =106, DQ14 =108, DQ15 =108
5938 20:17:30.758065
5939 20:17:30.758164
5940 20:17:30.767771 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5941 20:17:30.767877 CH1 RK1: MR19=504, MR18=29FD
5942 20:17:30.774356 CH1_RK1: MR19=0x504, MR18=0x29FD, DQSOSC=408, MR23=63, INC=65, DEC=43
5943 20:17:30.777487 [RxdqsGatingPostProcess] freq 933
5944 20:17:30.784338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5945 20:17:30.787499 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 20:17:30.790719 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 20:17:30.794154 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 20:17:30.797877 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 20:17:30.801066 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 20:17:30.801138 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 20:17:30.804484 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 20:17:30.807327 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 20:17:30.810641 Pre-setting of DQS Precalculation
5954 20:17:30.817514 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5955 20:17:30.824197 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5956 20:17:30.830891 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5957 20:17:30.831007
5958 20:17:30.831103
5959 20:17:30.833978 [Calibration Summary] 1866 Mbps
5960 20:17:30.837559 CH 0, Rank 0
5961 20:17:30.837660 SW Impedance : PASS
5962 20:17:30.840866 DUTY Scan : NO K
5963 20:17:30.840948 ZQ Calibration : PASS
5964 20:17:30.844312 Jitter Meter : NO K
5965 20:17:30.847202 CBT Training : PASS
5966 20:17:30.847308 Write leveling : PASS
5967 20:17:30.850840 RX DQS gating : PASS
5968 20:17:30.854356 RX DQ/DQS(RDDQC) : PASS
5969 20:17:30.854462 TX DQ/DQS : PASS
5970 20:17:30.857108 RX DATLAT : PASS
5971 20:17:30.860678 RX DQ/DQS(Engine): PASS
5972 20:17:30.860753 TX OE : NO K
5973 20:17:30.864181 All Pass.
5974 20:17:30.864290
5975 20:17:30.864389 CH 0, Rank 1
5976 20:17:30.867262 SW Impedance : PASS
5977 20:17:30.867412 DUTY Scan : NO K
5978 20:17:30.870331 ZQ Calibration : PASS
5979 20:17:30.874056 Jitter Meter : NO K
5980 20:17:30.874157 CBT Training : PASS
5981 20:17:30.876997 Write leveling : PASS
5982 20:17:30.880585 RX DQS gating : PASS
5983 20:17:30.880663 RX DQ/DQS(RDDQC) : PASS
5984 20:17:30.883631 TX DQ/DQS : PASS
5985 20:17:30.887409 RX DATLAT : PASS
5986 20:17:30.887484 RX DQ/DQS(Engine): PASS
5987 20:17:30.890947 TX OE : NO K
5988 20:17:30.891050 All Pass.
5989 20:17:30.891144
5990 20:17:30.893830 CH 1, Rank 0
5991 20:17:30.893902 SW Impedance : PASS
5992 20:17:30.897328 DUTY Scan : NO K
5993 20:17:30.897406 ZQ Calibration : PASS
5994 20:17:30.900391 Jitter Meter : NO K
5995 20:17:30.903492 CBT Training : PASS
5996 20:17:30.903592 Write leveling : PASS
5997 20:17:30.906959 RX DQS gating : PASS
5998 20:17:30.910620 RX DQ/DQS(RDDQC) : PASS
5999 20:17:30.910697 TX DQ/DQS : PASS
6000 20:17:30.913569 RX DATLAT : PASS
6001 20:17:30.916791 RX DQ/DQS(Engine): PASS
6002 20:17:30.916867 TX OE : NO K
6003 20:17:30.920519 All Pass.
6004 20:17:30.920594
6005 20:17:30.920656 CH 1, Rank 1
6006 20:17:30.923623 SW Impedance : PASS
6007 20:17:30.923700 DUTY Scan : NO K
6008 20:17:30.927198 ZQ Calibration : PASS
6009 20:17:30.930358 Jitter Meter : NO K
6010 20:17:30.930457 CBT Training : PASS
6011 20:17:30.933368 Write leveling : PASS
6012 20:17:30.937115 RX DQS gating : PASS
6013 20:17:30.937191 RX DQ/DQS(RDDQC) : PASS
6014 20:17:30.940212 TX DQ/DQS : PASS
6015 20:17:30.943297 RX DATLAT : PASS
6016 20:17:30.943368 RX DQ/DQS(Engine): PASS
6017 20:17:30.947027 TX OE : NO K
6018 20:17:30.947099 All Pass.
6019 20:17:30.947192
6020 20:17:30.949973 DramC Write-DBI off
6021 20:17:30.953573 PER_BANK_REFRESH: Hybrid Mode
6022 20:17:30.953657 TX_TRACKING: ON
6023 20:17:30.963602 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6024 20:17:30.966668 [FAST_K] Save calibration result to emmc
6025 20:17:30.970451 dramc_set_vcore_voltage set vcore to 650000
6026 20:17:30.973499 Read voltage for 400, 6
6027 20:17:30.973603 Vio18 = 0
6028 20:17:30.973695 Vcore = 650000
6029 20:17:30.976574 Vdram = 0
6030 20:17:30.976675 Vddq = 0
6031 20:17:30.976764 Vmddr = 0
6032 20:17:30.983069 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6033 20:17:30.986862 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6034 20:17:30.989847 MEM_TYPE=3, freq_sel=20
6035 20:17:30.993603 sv_algorithm_assistance_LP4_800
6036 20:17:30.996550 ============ PULL DRAM RESETB DOWN ============
6037 20:17:31.000035 ========== PULL DRAM RESETB DOWN end =========
6038 20:17:31.006925 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6039 20:17:31.010051 ===================================
6040 20:17:31.010134 LPDDR4 DRAM CONFIGURATION
6041 20:17:31.013538 ===================================
6042 20:17:31.016689 EX_ROW_EN[0] = 0x0
6043 20:17:31.016772 EX_ROW_EN[1] = 0x0
6044 20:17:31.020411 LP4Y_EN = 0x0
6045 20:17:31.020495 WORK_FSP = 0x0
6046 20:17:31.023437 WL = 0x2
6047 20:17:31.027001 RL = 0x2
6048 20:17:31.027115 BL = 0x2
6049 20:17:31.030204 RPST = 0x0
6050 20:17:31.030309 RD_PRE = 0x0
6051 20:17:31.033474 WR_PRE = 0x1
6052 20:17:31.033578 WR_PST = 0x0
6053 20:17:31.036949 DBI_WR = 0x0
6054 20:17:31.037022 DBI_RD = 0x0
6055 20:17:31.040045 OTF = 0x1
6056 20:17:31.043548 ===================================
6057 20:17:31.046516 ===================================
6058 20:17:31.046599 ANA top config
6059 20:17:31.049710 ===================================
6060 20:17:31.053334 DLL_ASYNC_EN = 0
6061 20:17:31.056392 ALL_SLAVE_EN = 1
6062 20:17:31.056480 NEW_RANK_MODE = 1
6063 20:17:31.059768 DLL_IDLE_MODE = 1
6064 20:17:31.063230 LP45_APHY_COMB_EN = 1
6065 20:17:31.066731 TX_ODT_DIS = 1
6066 20:17:31.070027 NEW_8X_MODE = 1
6067 20:17:31.073159 ===================================
6068 20:17:31.076013 ===================================
6069 20:17:31.079378 data_rate = 800
6070 20:17:31.079486 CKR = 1
6071 20:17:31.083066 DQ_P2S_RATIO = 4
6072 20:17:31.086496 ===================================
6073 20:17:31.089519 CA_P2S_RATIO = 4
6074 20:17:31.092535 DQ_CA_OPEN = 0
6075 20:17:31.096189 DQ_SEMI_OPEN = 1
6076 20:17:31.096271 CA_SEMI_OPEN = 1
6077 20:17:31.099411 CA_FULL_RATE = 0
6078 20:17:31.102462 DQ_CKDIV4_EN = 0
6079 20:17:31.106149 CA_CKDIV4_EN = 1
6080 20:17:31.109508 CA_PREDIV_EN = 0
6081 20:17:31.112236 PH8_DLY = 0
6082 20:17:31.115681 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6083 20:17:31.115764 DQ_AAMCK_DIV = 0
6084 20:17:31.119353 CA_AAMCK_DIV = 0
6085 20:17:31.122474 CA_ADMCK_DIV = 4
6086 20:17:31.126229 DQ_TRACK_CA_EN = 0
6087 20:17:31.129277 CA_PICK = 800
6088 20:17:31.132849 CA_MCKIO = 400
6089 20:17:31.132959 MCKIO_SEMI = 400
6090 20:17:31.135893 PLL_FREQ = 3016
6091 20:17:31.139361 DQ_UI_PI_RATIO = 32
6092 20:17:31.142295 CA_UI_PI_RATIO = 32
6093 20:17:31.145726 ===================================
6094 20:17:31.149266 ===================================
6095 20:17:31.152562 memory_type:LPDDR4
6096 20:17:31.152644 GP_NUM : 10
6097 20:17:31.155622 SRAM_EN : 1
6098 20:17:31.159211 MD32_EN : 0
6099 20:17:31.162463 ===================================
6100 20:17:31.162588 [ANA_INIT] >>>>>>>>>>>>>>
6101 20:17:31.165574 <<<<<< [CONFIGURE PHASE]: ANA_TX
6102 20:17:31.169107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6103 20:17:31.172152 ===================================
6104 20:17:31.175907 data_rate = 800,PCW = 0X7400
6105 20:17:31.178777 ===================================
6106 20:17:31.182420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6107 20:17:31.188798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 20:17:31.199397 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 20:17:31.205740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6110 20:17:31.208809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6111 20:17:31.212446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6112 20:17:31.212529 [ANA_INIT] flow start
6113 20:17:31.215400 [ANA_INIT] PLL >>>>>>>>
6114 20:17:31.218786 [ANA_INIT] PLL <<<<<<<<
6115 20:17:31.218869 [ANA_INIT] MIDPI >>>>>>>>
6116 20:17:31.222102 [ANA_INIT] MIDPI <<<<<<<<
6117 20:17:31.225595 [ANA_INIT] DLL >>>>>>>>
6118 20:17:31.225678 [ANA_INIT] flow end
6119 20:17:31.232313 ============ LP4 DIFF to SE enter ============
6120 20:17:31.235420 ============ LP4 DIFF to SE exit ============
6121 20:17:31.235503 [ANA_INIT] <<<<<<<<<<<<<
6122 20:17:31.238698 [Flow] Enable top DCM control >>>>>
6123 20:17:31.242063 [Flow] Enable top DCM control <<<<<
6124 20:17:31.245588 Enable DLL master slave shuffle
6125 20:17:31.252300 ==============================================================
6126 20:17:31.255416 Gating Mode config
6127 20:17:31.259002 ==============================================================
6128 20:17:31.261784 Config description:
6129 20:17:31.271931 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6130 20:17:31.278650 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6131 20:17:31.281931 SELPH_MODE 0: By rank 1: By Phase
6132 20:17:31.288965 ==============================================================
6133 20:17:31.291996 GAT_TRACK_EN = 0
6134 20:17:31.295396 RX_GATING_MODE = 2
6135 20:17:31.295507 RX_GATING_TRACK_MODE = 2
6136 20:17:31.298473 SELPH_MODE = 1
6137 20:17:31.301987 PICG_EARLY_EN = 1
6138 20:17:31.305375 VALID_LAT_VALUE = 1
6139 20:17:31.311590 ==============================================================
6140 20:17:31.315147 Enter into Gating configuration >>>>
6141 20:17:31.318228 Exit from Gating configuration <<<<
6142 20:17:31.321824 Enter into DVFS_PRE_config >>>>>
6143 20:17:31.331665 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6144 20:17:31.335284 Exit from DVFS_PRE_config <<<<<
6145 20:17:31.338402 Enter into PICG configuration >>>>
6146 20:17:31.341999 Exit from PICG configuration <<<<
6147 20:17:31.345191 [RX_INPUT] configuration >>>>>
6148 20:17:31.348604 [RX_INPUT] configuration <<<<<
6149 20:17:31.351635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6150 20:17:31.358380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6151 20:17:31.365220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 20:17:31.371820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 20:17:31.375120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 20:17:31.381825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 20:17:31.385018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6156 20:17:31.391497 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6157 20:17:31.395027 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6158 20:17:31.398252 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6159 20:17:31.401665 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6160 20:17:31.408112 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 20:17:31.411609 ===================================
6162 20:17:31.411734 LPDDR4 DRAM CONFIGURATION
6163 20:17:31.414843 ===================================
6164 20:17:31.418168 EX_ROW_EN[0] = 0x0
6165 20:17:31.421551 EX_ROW_EN[1] = 0x0
6166 20:17:31.421655 LP4Y_EN = 0x0
6167 20:17:31.425108 WORK_FSP = 0x0
6168 20:17:31.425189 WL = 0x2
6169 20:17:31.428248 RL = 0x2
6170 20:17:31.428348 BL = 0x2
6171 20:17:31.431327 RPST = 0x0
6172 20:17:31.431420 RD_PRE = 0x0
6173 20:17:31.434921 WR_PRE = 0x1
6174 20:17:31.435036 WR_PST = 0x0
6175 20:17:31.438334 DBI_WR = 0x0
6176 20:17:31.438439 DBI_RD = 0x0
6177 20:17:31.441687 OTF = 0x1
6178 20:17:31.444581 ===================================
6179 20:17:31.448142 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6180 20:17:31.451695 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6181 20:17:31.457771 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 20:17:31.461466 ===================================
6183 20:17:31.461551 LPDDR4 DRAM CONFIGURATION
6184 20:17:31.464627 ===================================
6185 20:17:31.467659 EX_ROW_EN[0] = 0x10
6186 20:17:31.471469 EX_ROW_EN[1] = 0x0
6187 20:17:31.471551 LP4Y_EN = 0x0
6188 20:17:31.474292 WORK_FSP = 0x0
6189 20:17:31.474404 WL = 0x2
6190 20:17:31.478254 RL = 0x2
6191 20:17:31.478358 BL = 0x2
6192 20:17:31.481004 RPST = 0x0
6193 20:17:31.481126 RD_PRE = 0x0
6194 20:17:31.484624 WR_PRE = 0x1
6195 20:17:31.484753 WR_PST = 0x0
6196 20:17:31.487483 DBI_WR = 0x0
6197 20:17:31.487609 DBI_RD = 0x0
6198 20:17:31.491168 OTF = 0x1
6199 20:17:31.494392 ===================================
6200 20:17:31.501256 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6201 20:17:31.504614 nWR fixed to 30
6202 20:17:31.504748 [ModeRegInit_LP4] CH0 RK0
6203 20:17:31.507515 [ModeRegInit_LP4] CH0 RK1
6204 20:17:31.511155 [ModeRegInit_LP4] CH1 RK0
6205 20:17:31.514236 [ModeRegInit_LP4] CH1 RK1
6206 20:17:31.514364 match AC timing 19
6207 20:17:31.517689 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6208 20:17:31.524614 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6209 20:17:31.527428 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6210 20:17:31.530864 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6211 20:17:31.537768 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6212 20:17:31.537854 ==
6213 20:17:31.541352 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 20:17:31.544237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 20:17:31.544344 ==
6216 20:17:31.551254 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 20:17:31.558031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6218 20:17:31.558115 [CA 0] Center 36 (8~64) winsize 57
6219 20:17:31.561016 [CA 1] Center 36 (8~64) winsize 57
6220 20:17:31.564158 [CA 2] Center 36 (8~64) winsize 57
6221 20:17:31.568010 [CA 3] Center 36 (8~64) winsize 57
6222 20:17:31.570986 [CA 4] Center 36 (8~64) winsize 57
6223 20:17:31.574631 [CA 5] Center 36 (8~64) winsize 57
6224 20:17:31.574715
6225 20:17:31.577745 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6226 20:17:31.577828
6227 20:17:31.580931 [CATrainingPosCal] consider 1 rank data
6228 20:17:31.584428 u2DelayCellTimex100 = 270/100 ps
6229 20:17:31.587633 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 20:17:31.591187 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 20:17:31.597303 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 20:17:31.600701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 20:17:31.604203 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 20:17:31.607268 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 20:17:31.607352
6236 20:17:31.611061 CA PerBit enable=1, Macro0, CA PI delay=36
6237 20:17:31.611145
6238 20:17:31.614005 [CBTSetCACLKResult] CA Dly = 36
6239 20:17:31.614087 CS Dly: 1 (0~32)
6240 20:17:31.617667 ==
6241 20:17:31.617748 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 20:17:31.624271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 20:17:31.624389 ==
6244 20:17:31.627430 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 20:17:31.634156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6246 20:17:31.637585 [CA 0] Center 36 (8~64) winsize 57
6247 20:17:31.640626 [CA 1] Center 36 (8~64) winsize 57
6248 20:17:31.644220 [CA 2] Center 36 (8~64) winsize 57
6249 20:17:31.647191 [CA 3] Center 36 (8~64) winsize 57
6250 20:17:31.650781 [CA 4] Center 36 (8~64) winsize 57
6251 20:17:31.653857 [CA 5] Center 36 (8~64) winsize 57
6252 20:17:31.653938
6253 20:17:31.657434 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6254 20:17:31.657516
6255 20:17:31.660776 [CATrainingPosCal] consider 2 rank data
6256 20:17:31.664187 u2DelayCellTimex100 = 270/100 ps
6257 20:17:31.667495 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 20:17:31.670604 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 20:17:31.674276 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 20:17:31.677340 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 20:17:31.680450 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 20:17:31.687059 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 20:17:31.687140
6264 20:17:31.690819 CA PerBit enable=1, Macro0, CA PI delay=36
6265 20:17:31.690902
6266 20:17:31.693956 [CBTSetCACLKResult] CA Dly = 36
6267 20:17:31.694038 CS Dly: 1 (0~32)
6268 20:17:31.694103
6269 20:17:31.696986 ----->DramcWriteLeveling(PI) begin...
6270 20:17:31.697069 ==
6271 20:17:31.700627 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 20:17:31.703763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 20:17:31.707412 ==
6274 20:17:31.707495 Write leveling (Byte 0): 40 => 8
6275 20:17:31.710329 Write leveling (Byte 1): 40 => 8
6276 20:17:31.713796 DramcWriteLeveling(PI) end<-----
6277 20:17:31.713877
6278 20:17:31.713941 ==
6279 20:17:31.716884 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 20:17:31.723769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 20:17:31.723895 ==
6282 20:17:31.723999 [Gating] SW mode calibration
6283 20:17:31.733591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6284 20:17:31.737152 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6285 20:17:31.743474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 20:17:31.746698 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 20:17:31.750070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 20:17:31.757224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 20:17:31.760415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 20:17:31.763462 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 20:17:31.766967 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 20:17:31.773608 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 20:17:31.777236 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 20:17:31.780074 Total UI for P1: 0, mck2ui 16
6295 20:17:31.783904 best dqsien dly found for B0: ( 0, 14, 24)
6296 20:17:31.786809 Total UI for P1: 0, mck2ui 16
6297 20:17:31.789931 best dqsien dly found for B1: ( 0, 14, 24)
6298 20:17:31.793179 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6299 20:17:31.796734 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6300 20:17:31.796816
6301 20:17:31.800328 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 20:17:31.806473 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 20:17:31.806554 [Gating] SW calibration Done
6304 20:17:31.806619 ==
6305 20:17:31.810105 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 20:17:31.816868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 20:17:31.816954 ==
6308 20:17:31.817019 RX Vref Scan: 0
6309 20:17:31.817079
6310 20:17:31.819974 RX Vref 0 -> 0, step: 1
6311 20:17:31.820055
6312 20:17:31.823601 RX Delay -410 -> 252, step: 16
6313 20:17:31.826604 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6314 20:17:31.829894 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6315 20:17:31.836388 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6316 20:17:31.840005 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6317 20:17:31.843304 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6318 20:17:31.846269 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6319 20:17:31.853031 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6320 20:17:31.856606 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6321 20:17:31.859780 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6322 20:17:31.863054 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6323 20:17:31.869538 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6324 20:17:31.873138 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6325 20:17:31.876404 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6326 20:17:31.879568 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6327 20:17:31.886580 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6328 20:17:31.889817 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6329 20:17:31.889939 ==
6330 20:17:31.892741 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 20:17:31.896269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 20:17:31.896426 ==
6333 20:17:31.899316 DQS Delay:
6334 20:17:31.899437 DQS0 = 27, DQS1 = 35
6335 20:17:31.903108 DQM Delay:
6336 20:17:31.903231 DQM0 = 10, DQM1 = 12
6337 20:17:31.903340 DQ Delay:
6338 20:17:31.906236 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6339 20:17:31.909310 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6340 20:17:31.913106 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6341 20:17:31.916130 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6342 20:17:31.916251
6343 20:17:31.916370
6344 20:17:31.916475 ==
6345 20:17:31.919630 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 20:17:31.925865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 20:17:31.925988 ==
6348 20:17:31.926100
6349 20:17:31.926208
6350 20:17:31.926318 TX Vref Scan disable
6351 20:17:31.928995 == TX Byte 0 ==
6352 20:17:31.932734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 20:17:31.935758 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 20:17:31.939336 == TX Byte 1 ==
6355 20:17:31.942832 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 20:17:31.945921 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 20:17:31.946004 ==
6358 20:17:31.949415 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 20:17:31.956250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 20:17:31.956392 ==
6361 20:17:31.956483
6362 20:17:31.956570
6363 20:17:31.956655 TX Vref Scan disable
6364 20:17:31.959309 == TX Byte 0 ==
6365 20:17:31.962747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 20:17:31.966354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 20:17:31.969330 == TX Byte 1 ==
6368 20:17:31.972850 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 20:17:31.976634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 20:17:31.976714
6371 20:17:31.979347 [DATLAT]
6372 20:17:31.979471 Freq=400, CH0 RK0
6373 20:17:31.979585
6374 20:17:31.982877 DATLAT Default: 0xf
6375 20:17:31.983001 0, 0xFFFF, sum = 0
6376 20:17:31.985998 1, 0xFFFF, sum = 0
6377 20:17:31.986119 2, 0xFFFF, sum = 0
6378 20:17:31.989440 3, 0xFFFF, sum = 0
6379 20:17:31.989566 4, 0xFFFF, sum = 0
6380 20:17:31.992974 5, 0xFFFF, sum = 0
6381 20:17:31.993096 6, 0xFFFF, sum = 0
6382 20:17:31.996199 7, 0xFFFF, sum = 0
6383 20:17:31.996358 8, 0xFFFF, sum = 0
6384 20:17:31.999371 9, 0xFFFF, sum = 0
6385 20:17:31.999496 10, 0xFFFF, sum = 0
6386 20:17:32.002808 11, 0xFFFF, sum = 0
6387 20:17:32.002893 12, 0xFFFF, sum = 0
6388 20:17:32.005781 13, 0x0, sum = 1
6389 20:17:32.005957 14, 0x0, sum = 2
6390 20:17:32.009339 15, 0x0, sum = 3
6391 20:17:32.009422 16, 0x0, sum = 4
6392 20:17:32.012442 best_step = 14
6393 20:17:32.012524
6394 20:17:32.012589 ==
6395 20:17:32.016113 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 20:17:32.019272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 20:17:32.019355 ==
6398 20:17:32.022915 RX Vref Scan: 1
6399 20:17:32.022997
6400 20:17:32.023062 RX Vref 0 -> 0, step: 1
6401 20:17:32.023123
6402 20:17:32.025891 RX Delay -311 -> 252, step: 8
6403 20:17:32.025973
6404 20:17:32.028886 Set Vref, RX VrefLevel [Byte0]: 56
6405 20:17:32.032643 [Byte1]: 57
6406 20:17:32.036906
6407 20:17:32.037001 Final RX Vref Byte 0 = 56 to rank0
6408 20:17:32.040612 Final RX Vref Byte 1 = 57 to rank0
6409 20:17:32.043685 Final RX Vref Byte 0 = 56 to rank1
6410 20:17:32.047231 Final RX Vref Byte 1 = 57 to rank1==
6411 20:17:32.050325 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 20:17:32.057119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 20:17:32.057201 ==
6414 20:17:32.057266 DQS Delay:
6415 20:17:32.060155 DQS0 = 28, DQS1 = 36
6416 20:17:32.060236 DQM Delay:
6417 20:17:32.060328 DQM0 = 11, DQM1 = 13
6418 20:17:32.064016 DQ Delay:
6419 20:17:32.067096 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6420 20:17:32.067178 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6421 20:17:32.070051 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6422 20:17:32.074001 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6423 20:17:32.074083
6424 20:17:32.074168
6425 20:17:32.083696 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6426 20:17:32.087040 CH0 RK0: MR19=C0C, MR18=D1BE
6427 20:17:32.093577 CH0_RK0: MR19=0xC0C, MR18=0xD1BE, DQSOSC=384, MR23=63, INC=400, DEC=267
6428 20:17:32.093676 ==
6429 20:17:32.096957 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 20:17:32.100124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 20:17:32.100232 ==
6432 20:17:32.104037 [Gating] SW mode calibration
6433 20:17:32.110287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6434 20:17:32.113812 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6435 20:17:32.120231 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 20:17:32.123775 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 20:17:32.126708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 20:17:32.133424 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 20:17:32.136971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 20:17:32.140057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 20:17:32.147341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 20:17:32.150411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 20:17:32.153494 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 20:17:32.157225 Total UI for P1: 0, mck2ui 16
6445 20:17:32.160315 best dqsien dly found for B0: ( 0, 14, 24)
6446 20:17:32.164078 Total UI for P1: 0, mck2ui 16
6447 20:17:32.167061 best dqsien dly found for B1: ( 0, 14, 24)
6448 20:17:32.170592 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6449 20:17:32.173868 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6450 20:17:32.173951
6451 20:17:32.180706 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 20:17:32.183770 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 20:17:32.183935 [Gating] SW calibration Done
6454 20:17:32.187205 ==
6455 20:17:32.190416 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 20:17:32.193602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 20:17:32.193712 ==
6458 20:17:32.193779 RX Vref Scan: 0
6459 20:17:32.193845
6460 20:17:32.196518 RX Vref 0 -> 0, step: 1
6461 20:17:32.196624
6462 20:17:32.199862 RX Delay -410 -> 252, step: 16
6463 20:17:32.203306 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6464 20:17:32.209880 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6465 20:17:32.213089 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6466 20:17:32.217149 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6467 20:17:32.219803 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6468 20:17:32.226826 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6469 20:17:32.230111 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6470 20:17:32.233312 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6471 20:17:32.236892 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6472 20:17:32.239632 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6473 20:17:32.246196 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6474 20:17:32.249860 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6475 20:17:32.253327 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6476 20:17:32.260160 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6477 20:17:32.263290 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6478 20:17:32.266323 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6479 20:17:32.266408 ==
6480 20:17:32.270030 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 20:17:32.273241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 20:17:32.276368 ==
6483 20:17:32.276497 DQS Delay:
6484 20:17:32.276614 DQS0 = 27, DQS1 = 35
6485 20:17:32.279396 DQM Delay:
6486 20:17:32.279520 DQM0 = 11, DQM1 = 10
6487 20:17:32.283158 DQ Delay:
6488 20:17:32.283264 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6489 20:17:32.286333 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6490 20:17:32.289445 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6491 20:17:32.293035 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6492 20:17:32.293120
6493 20:17:32.293186
6494 20:17:32.295995 ==
6495 20:17:32.296078 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 20:17:32.303191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 20:17:32.303276 ==
6498 20:17:32.303343
6499 20:17:32.303404
6500 20:17:32.305986 TX Vref Scan disable
6501 20:17:32.306070 == TX Byte 0 ==
6502 20:17:32.309354 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6503 20:17:32.313074 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6504 20:17:32.315881 == TX Byte 1 ==
6505 20:17:32.319329 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 20:17:32.322647 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 20:17:32.325912 ==
6508 20:17:32.329368 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 20:17:32.332929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 20:17:32.333012 ==
6511 20:17:32.333077
6512 20:17:32.333138
6513 20:17:32.335999 TX Vref Scan disable
6514 20:17:32.336081 == TX Byte 0 ==
6515 20:17:32.339088 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6516 20:17:32.346114 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6517 20:17:32.346197 == TX Byte 1 ==
6518 20:17:32.349182 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 20:17:32.352939 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 20:17:32.355937
6521 20:17:32.356059 [DATLAT]
6522 20:17:32.356175 Freq=400, CH0 RK1
6523 20:17:32.356274
6524 20:17:32.359433 DATLAT Default: 0xe
6525 20:17:32.359516 0, 0xFFFF, sum = 0
6526 20:17:32.362338 1, 0xFFFF, sum = 0
6527 20:17:32.362424 2, 0xFFFF, sum = 0
6528 20:17:32.365724 3, 0xFFFF, sum = 0
6529 20:17:32.369402 4, 0xFFFF, sum = 0
6530 20:17:32.369487 5, 0xFFFF, sum = 0
6531 20:17:32.372806 6, 0xFFFF, sum = 0
6532 20:17:32.372916 7, 0xFFFF, sum = 0
6533 20:17:32.375802 8, 0xFFFF, sum = 0
6534 20:17:32.375912 9, 0xFFFF, sum = 0
6535 20:17:32.378953 10, 0xFFFF, sum = 0
6536 20:17:32.379038 11, 0xFFFF, sum = 0
6537 20:17:32.382608 12, 0xFFFF, sum = 0
6538 20:17:32.382698 13, 0x0, sum = 1
6539 20:17:32.385546 14, 0x0, sum = 2
6540 20:17:32.385626 15, 0x0, sum = 3
6541 20:17:32.389256 16, 0x0, sum = 4
6542 20:17:32.389344 best_step = 14
6543 20:17:32.389428
6544 20:17:32.389507 ==
6545 20:17:32.392487 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 20:17:32.395601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 20:17:32.395685 ==
6548 20:17:32.399057 RX Vref Scan: 0
6549 20:17:32.399143
6550 20:17:32.402073 RX Vref 0 -> 0, step: 1
6551 20:17:32.402148
6552 20:17:32.405899 RX Delay -311 -> 252, step: 8
6553 20:17:32.408903 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6554 20:17:32.415670 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6555 20:17:32.418939 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6556 20:17:32.422201 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6557 20:17:32.425586 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6558 20:17:32.432221 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6559 20:17:32.435409 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6560 20:17:32.438926 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6561 20:17:32.442049 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6562 20:17:32.448869 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6563 20:17:32.452066 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6564 20:17:32.455880 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6565 20:17:32.458813 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6566 20:17:32.465132 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6567 20:17:32.468597 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6568 20:17:32.471794 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6569 20:17:32.471878 ==
6570 20:17:32.475129 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 20:17:32.481786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 20:17:32.481871 ==
6573 20:17:32.481957 DQS Delay:
6574 20:17:32.485085 DQS0 = 24, DQS1 = 32
6575 20:17:32.485168 DQM Delay:
6576 20:17:32.485254 DQM0 = 8, DQM1 = 10
6577 20:17:32.489103 DQ Delay:
6578 20:17:32.492016 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6579 20:17:32.492100 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6580 20:17:32.494982 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6581 20:17:32.498745 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6582 20:17:32.498829
6583 20:17:32.498913
6584 20:17:32.508579 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6585 20:17:32.511806 CH0 RK1: MR19=C0C, MR18=BC5C
6586 20:17:32.518439 CH0_RK1: MR19=0xC0C, MR18=0xBC5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6587 20:17:32.521641 [RxdqsGatingPostProcess] freq 400
6588 20:17:32.525164 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6589 20:17:32.528087 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 20:17:32.531376 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 20:17:32.535054 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 20:17:32.538442 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 20:17:32.541398 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 20:17:32.544836 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 20:17:32.548098 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 20:17:32.551519 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 20:17:32.555125 Pre-setting of DQS Precalculation
6598 20:17:32.558381 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6599 20:17:32.558466 ==
6600 20:17:32.561392 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 20:17:32.568245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 20:17:32.568385 ==
6603 20:17:32.571067 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 20:17:32.578165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6605 20:17:32.581113 [CA 0] Center 36 (8~64) winsize 57
6606 20:17:32.584914 [CA 1] Center 36 (8~64) winsize 57
6607 20:17:32.587985 [CA 2] Center 36 (8~64) winsize 57
6608 20:17:32.591390 [CA 3] Center 36 (8~64) winsize 57
6609 20:17:32.594644 [CA 4] Center 36 (8~64) winsize 57
6610 20:17:32.597914 [CA 5] Center 36 (8~64) winsize 57
6611 20:17:32.598050
6612 20:17:32.601041 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6613 20:17:32.601167
6614 20:17:32.604841 [CATrainingPosCal] consider 1 rank data
6615 20:17:32.607765 u2DelayCellTimex100 = 270/100 ps
6616 20:17:32.611095 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 20:17:32.614694 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 20:17:32.617693 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 20:17:32.621321 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 20:17:32.624362 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 20:17:32.627862 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 20:17:32.627945
6623 20:17:32.634466 CA PerBit enable=1, Macro0, CA PI delay=36
6624 20:17:32.634572
6625 20:17:32.634665 [CBTSetCACLKResult] CA Dly = 36
6626 20:17:32.638071 CS Dly: 1 (0~32)
6627 20:17:32.638151 ==
6628 20:17:32.640968 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 20:17:32.644263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 20:17:32.644402 ==
6631 20:17:32.651361 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 20:17:32.658007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6633 20:17:32.660876 [CA 0] Center 36 (8~64) winsize 57
6634 20:17:32.664597 [CA 1] Center 36 (8~64) winsize 57
6635 20:17:32.667774 [CA 2] Center 36 (8~64) winsize 57
6636 20:17:32.667855 [CA 3] Center 36 (8~64) winsize 57
6637 20:17:32.670815 [CA 4] Center 36 (8~64) winsize 57
6638 20:17:32.674442 [CA 5] Center 36 (8~64) winsize 57
6639 20:17:32.674523
6640 20:17:32.681151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6641 20:17:32.681252
6642 20:17:32.684043 [CATrainingPosCal] consider 2 rank data
6643 20:17:32.687695 u2DelayCellTimex100 = 270/100 ps
6644 20:17:32.690683 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 20:17:32.694371 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 20:17:32.697464 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 20:17:32.700759 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 20:17:32.704264 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 20:17:32.707206 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 20:17:32.707287
6651 20:17:32.710514 CA PerBit enable=1, Macro0, CA PI delay=36
6652 20:17:32.710698
6653 20:17:32.714290 [CBTSetCACLKResult] CA Dly = 36
6654 20:17:32.717180 CS Dly: 1 (0~32)
6655 20:17:32.717275
6656 20:17:32.720534 ----->DramcWriteLeveling(PI) begin...
6657 20:17:32.720644 ==
6658 20:17:32.724162 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 20:17:32.727297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 20:17:32.727378 ==
6661 20:17:32.730723 Write leveling (Byte 0): 40 => 8
6662 20:17:32.733822 Write leveling (Byte 1): 40 => 8
6663 20:17:32.737524 DramcWriteLeveling(PI) end<-----
6664 20:17:32.737604
6665 20:17:32.737668 ==
6666 20:17:32.740538 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 20:17:32.744048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 20:17:32.744130 ==
6669 20:17:32.747140 [Gating] SW mode calibration
6670 20:17:32.753844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6671 20:17:32.760521 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6672 20:17:32.763413 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 20:17:32.766720 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 20:17:32.773481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 20:17:32.776645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 20:17:32.780377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 20:17:32.787060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 20:17:32.790248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 20:17:32.793573 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 20:17:32.799748 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 20:17:32.803476 Total UI for P1: 0, mck2ui 16
6682 20:17:32.806487 best dqsien dly found for B0: ( 0, 14, 24)
6683 20:17:32.810235 Total UI for P1: 0, mck2ui 16
6684 20:17:32.813283 best dqsien dly found for B1: ( 0, 14, 24)
6685 20:17:32.816835 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6686 20:17:32.819589 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6687 20:17:32.819670
6688 20:17:32.823217 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 20:17:32.826755 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 20:17:32.829628 [Gating] SW calibration Done
6691 20:17:32.829709 ==
6692 20:17:32.832863 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 20:17:32.836172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 20:17:32.836279 ==
6695 20:17:32.839685 RX Vref Scan: 0
6696 20:17:32.839766
6697 20:17:32.842771 RX Vref 0 -> 0, step: 1
6698 20:17:32.842852
6699 20:17:32.842916 RX Delay -410 -> 252, step: 16
6700 20:17:32.849928 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6701 20:17:32.853092 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6702 20:17:32.856550 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6703 20:17:32.859401 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6704 20:17:32.866401 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6705 20:17:32.869604 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6706 20:17:32.872684 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6707 20:17:32.876165 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6708 20:17:32.882651 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6709 20:17:32.886338 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6710 20:17:32.889368 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6711 20:17:32.893158 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6712 20:17:32.899297 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6713 20:17:32.902583 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6714 20:17:32.906376 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6715 20:17:32.909445 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6716 20:17:32.913153 ==
6717 20:17:32.916190 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 20:17:32.919287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 20:17:32.919368 ==
6720 20:17:32.919433 DQS Delay:
6721 20:17:32.922898 DQS0 = 35, DQS1 = 35
6722 20:17:32.922979 DQM Delay:
6723 20:17:32.926269 DQM0 = 20, DQM1 = 17
6724 20:17:32.926351 DQ Delay:
6725 20:17:32.929332 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6726 20:17:32.932993 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6727 20:17:32.936062 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6728 20:17:32.939063 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6729 20:17:32.939143
6730 20:17:32.939207
6731 20:17:32.939265 ==
6732 20:17:32.942981 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 20:17:32.945839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 20:17:32.945923 ==
6735 20:17:32.945987
6736 20:17:32.946046
6737 20:17:32.949137 TX Vref Scan disable
6738 20:17:32.949218 == TX Byte 0 ==
6739 20:17:32.956079 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 20:17:32.959217 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 20:17:32.959324 == TX Byte 1 ==
6742 20:17:32.965875 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 20:17:32.969228 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 20:17:32.969310 ==
6745 20:17:32.972748 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 20:17:32.975924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 20:17:32.976064 ==
6748 20:17:32.976199
6749 20:17:32.976312
6750 20:17:32.979071 TX Vref Scan disable
6751 20:17:32.979167 == TX Byte 0 ==
6752 20:17:32.985770 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 20:17:32.989058 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 20:17:32.989133 == TX Byte 1 ==
6755 20:17:32.995608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 20:17:32.998847 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 20:17:32.998925
6758 20:17:32.998989 [DATLAT]
6759 20:17:33.002484 Freq=400, CH1 RK0
6760 20:17:33.002553
6761 20:17:33.002613 DATLAT Default: 0xf
6762 20:17:33.005949 0, 0xFFFF, sum = 0
6763 20:17:33.006019 1, 0xFFFF, sum = 0
6764 20:17:33.008687 2, 0xFFFF, sum = 0
6765 20:17:33.008783 3, 0xFFFF, sum = 0
6766 20:17:33.012275 4, 0xFFFF, sum = 0
6767 20:17:33.012356 5, 0xFFFF, sum = 0
6768 20:17:33.015949 6, 0xFFFF, sum = 0
6769 20:17:33.016017 7, 0xFFFF, sum = 0
6770 20:17:33.018903 8, 0xFFFF, sum = 0
6771 20:17:33.019036 9, 0xFFFF, sum = 0
6772 20:17:33.022730 10, 0xFFFF, sum = 0
6773 20:17:33.025809 11, 0xFFFF, sum = 0
6774 20:17:33.025919 12, 0xFFFF, sum = 0
6775 20:17:33.028884 13, 0x0, sum = 1
6776 20:17:33.028967 14, 0x0, sum = 2
6777 20:17:33.032198 15, 0x0, sum = 3
6778 20:17:33.032328 16, 0x0, sum = 4
6779 20:17:33.032410 best_step = 14
6780 20:17:33.032475
6781 20:17:33.035460 ==
6782 20:17:33.035567 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 20:17:33.042134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 20:17:33.042215 ==
6785 20:17:33.042279 RX Vref Scan: 1
6786 20:17:33.042339
6787 20:17:33.045791 RX Vref 0 -> 0, step: 1
6788 20:17:33.045875
6789 20:17:33.048965 RX Delay -311 -> 252, step: 8
6790 20:17:33.049047
6791 20:17:33.052641 Set Vref, RX VrefLevel [Byte0]: 55
6792 20:17:33.055570 [Byte1]: 53
6793 20:17:33.059302
6794 20:17:33.059384 Final RX Vref Byte 0 = 55 to rank0
6795 20:17:33.062384 Final RX Vref Byte 1 = 53 to rank0
6796 20:17:33.065891 Final RX Vref Byte 0 = 55 to rank1
6797 20:17:33.069178 Final RX Vref Byte 1 = 53 to rank1==
6798 20:17:33.072278 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 20:17:33.079054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 20:17:33.079138 ==
6801 20:17:33.079204 DQS Delay:
6802 20:17:33.082190 DQS0 = 28, DQS1 = 32
6803 20:17:33.082272 DQM Delay:
6804 20:17:33.082341 DQM0 = 10, DQM1 = 10
6805 20:17:33.085651 DQ Delay:
6806 20:17:33.088623 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6807 20:17:33.088706 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6808 20:17:33.092342 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6809 20:17:33.095358 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6810 20:17:33.095441
6811 20:17:33.095516
6812 20:17:33.105286 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6813 20:17:33.108657 CH1 RK0: MR19=C0C, MR18=93CC
6814 20:17:33.115264 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6815 20:17:33.115348 ==
6816 20:17:33.118578 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 20:17:33.122029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 20:17:33.122112 ==
6819 20:17:33.125709 [Gating] SW mode calibration
6820 20:17:33.131983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6821 20:17:33.138565 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6822 20:17:33.141813 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 20:17:33.145206 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 20:17:33.148639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 20:17:33.155508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 20:17:33.158620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 20:17:33.161757 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 20:17:33.168957 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 20:17:33.172036 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 20:17:33.175040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 20:17:33.178549 Total UI for P1: 0, mck2ui 16
6832 20:17:33.181959 best dqsien dly found for B0: ( 0, 14, 24)
6833 20:17:33.185511 Total UI for P1: 0, mck2ui 16
6834 20:17:33.188943 best dqsien dly found for B1: ( 0, 14, 24)
6835 20:17:33.191825 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6836 20:17:33.195580 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6837 20:17:33.195702
6838 20:17:33.201735 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 20:17:33.205150 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 20:17:33.208708 [Gating] SW calibration Done
6841 20:17:33.208842 ==
6842 20:17:33.211852 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 20:17:33.215204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 20:17:33.215336 ==
6845 20:17:33.215450 RX Vref Scan: 0
6846 20:17:33.215573
6847 20:17:33.218524 RX Vref 0 -> 0, step: 1
6848 20:17:33.218646
6849 20:17:33.221956 RX Delay -410 -> 252, step: 16
6850 20:17:33.225468 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6851 20:17:33.231957 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6852 20:17:33.235177 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6853 20:17:33.238440 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6854 20:17:33.242131 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6855 20:17:33.245175 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6856 20:17:33.251504 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6857 20:17:33.255492 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6858 20:17:33.258444 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6859 20:17:33.262151 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6860 20:17:33.268776 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6861 20:17:33.271937 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6862 20:17:33.274954 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6863 20:17:33.281864 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6864 20:17:33.284949 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6865 20:17:33.288480 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6866 20:17:33.288580 ==
6867 20:17:33.291751 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 20:17:33.295286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 20:17:33.295376 ==
6870 20:17:33.298307 DQS Delay:
6871 20:17:33.298381 DQS0 = 35, DQS1 = 35
6872 20:17:33.301827 DQM Delay:
6873 20:17:33.301919 DQM0 = 18, DQM1 = 14
6874 20:17:33.305097 DQ Delay:
6875 20:17:33.305169 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6876 20:17:33.308224 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6877 20:17:33.311378 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6878 20:17:33.314678 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6879 20:17:33.314751
6880 20:17:33.314821
6881 20:17:33.318492 ==
6882 20:17:33.318579 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 20:17:33.325220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 20:17:33.325306 ==
6885 20:17:33.325394
6886 20:17:33.325476
6887 20:17:33.328141 TX Vref Scan disable
6888 20:17:33.328228 == TX Byte 0 ==
6889 20:17:33.331613 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6890 20:17:33.334996 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6891 20:17:33.338206 == TX Byte 1 ==
6892 20:17:33.341612 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 20:17:33.344809 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 20:17:33.348442 ==
6895 20:17:33.348526 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 20:17:33.354986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 20:17:33.355072 ==
6898 20:17:33.355159
6899 20:17:33.355239
6900 20:17:33.358480 TX Vref Scan disable
6901 20:17:33.358576 == TX Byte 0 ==
6902 20:17:33.361276 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 20:17:33.368408 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 20:17:33.368485 == TX Byte 1 ==
6905 20:17:33.371347 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 20:17:33.374977 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 20:17:33.377925
6908 20:17:33.377997 [DATLAT]
6909 20:17:33.378058 Freq=400, CH1 RK1
6910 20:17:33.378118
6911 20:17:33.381703 DATLAT Default: 0xe
6912 20:17:33.381774 0, 0xFFFF, sum = 0
6913 20:17:33.384894 1, 0xFFFF, sum = 0
6914 20:17:33.384973 2, 0xFFFF, sum = 0
6915 20:17:33.387881 3, 0xFFFF, sum = 0
6916 20:17:33.387961 4, 0xFFFF, sum = 0
6917 20:17:33.391521 5, 0xFFFF, sum = 0
6918 20:17:33.391594 6, 0xFFFF, sum = 0
6919 20:17:33.394602 7, 0xFFFF, sum = 0
6920 20:17:33.398118 8, 0xFFFF, sum = 0
6921 20:17:33.398192 9, 0xFFFF, sum = 0
6922 20:17:33.401412 10, 0xFFFF, sum = 0
6923 20:17:33.401499 11, 0xFFFF, sum = 0
6924 20:17:33.404933 12, 0xFFFF, sum = 0
6925 20:17:33.405007 13, 0x0, sum = 1
6926 20:17:33.407999 14, 0x0, sum = 2
6927 20:17:33.408079 15, 0x0, sum = 3
6928 20:17:33.411588 16, 0x0, sum = 4
6929 20:17:33.411662 best_step = 14
6930 20:17:33.411723
6931 20:17:33.411791 ==
6932 20:17:33.414689 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 20:17:33.417896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 20:17:33.417969 ==
6935 20:17:33.421515 RX Vref Scan: 0
6936 20:17:33.421598
6937 20:17:33.424245 RX Vref 0 -> 0, step: 1
6938 20:17:33.424368
6939 20:17:33.424430 RX Delay -311 -> 252, step: 8
6940 20:17:33.433278 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6941 20:17:33.436844 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6942 20:17:33.439805 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6943 20:17:33.443453 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6944 20:17:33.449572 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6945 20:17:33.453011 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6946 20:17:33.456416 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6947 20:17:33.459779 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6948 20:17:33.466776 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6949 20:17:33.469557 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6950 20:17:33.472951 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6951 20:17:33.476492 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6952 20:17:33.483222 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6953 20:17:33.486430 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6954 20:17:33.490187 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6955 20:17:33.493271 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6956 20:17:33.496980 ==
6957 20:17:33.500021 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 20:17:33.503054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 20:17:33.503156 ==
6960 20:17:33.503247 DQS Delay:
6961 20:17:33.506478 DQS0 = 28, DQS1 = 32
6962 20:17:33.506551 DQM Delay:
6963 20:17:33.509731 DQM0 = 11, DQM1 = 11
6964 20:17:33.509829 DQ Delay:
6965 20:17:33.513436 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6966 20:17:33.516903 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6967 20:17:33.519938 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6968 20:17:33.523007 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6969 20:17:33.523079
6970 20:17:33.523140
6971 20:17:33.529836 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6972 20:17:33.533658 CH1 RK1: MR19=C0C, MR18=C052
6973 20:17:33.539453 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
6974 20:17:33.542767 [RxdqsGatingPostProcess] freq 400
6975 20:17:33.546264 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6976 20:17:33.549824 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 20:17:33.553181 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 20:17:33.556456 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 20:17:33.559564 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 20:17:33.563521 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 20:17:33.566278 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 20:17:33.569680 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 20:17:33.573059 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 20:17:33.576485 Pre-setting of DQS Precalculation
6985 20:17:33.579679 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6986 20:17:33.589441 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6987 20:17:33.596165 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6988 20:17:33.596270
6989 20:17:33.596399
6990 20:17:33.599893 [Calibration Summary] 800 Mbps
6991 20:17:33.600001 CH 0, Rank 0
6992 20:17:33.603089 SW Impedance : PASS
6993 20:17:33.603172 DUTY Scan : NO K
6994 20:17:33.606709 ZQ Calibration : PASS
6995 20:17:33.609662 Jitter Meter : NO K
6996 20:17:33.609744 CBT Training : PASS
6997 20:17:33.612796 Write leveling : PASS
6998 20:17:33.616314 RX DQS gating : PASS
6999 20:17:33.616397 RX DQ/DQS(RDDQC) : PASS
7000 20:17:33.619650 TX DQ/DQS : PASS
7001 20:17:33.622945 RX DATLAT : PASS
7002 20:17:33.623028 RX DQ/DQS(Engine): PASS
7003 20:17:33.626191 TX OE : NO K
7004 20:17:33.626275 All Pass.
7005 20:17:33.626339
7006 20:17:33.626399 CH 0, Rank 1
7007 20:17:33.629969 SW Impedance : PASS
7008 20:17:33.633039 DUTY Scan : NO K
7009 20:17:33.633122 ZQ Calibration : PASS
7010 20:17:33.636181 Jitter Meter : NO K
7011 20:17:33.639978 CBT Training : PASS
7012 20:17:33.640060 Write leveling : NO K
7013 20:17:33.642958 RX DQS gating : PASS
7014 20:17:33.646132 RX DQ/DQS(RDDQC) : PASS
7015 20:17:33.646214 TX DQ/DQS : PASS
7016 20:17:33.649714 RX DATLAT : PASS
7017 20:17:33.652790 RX DQ/DQS(Engine): PASS
7018 20:17:33.652873 TX OE : NO K
7019 20:17:33.656212 All Pass.
7020 20:17:33.656323
7021 20:17:33.656390 CH 1, Rank 0
7022 20:17:33.659481 SW Impedance : PASS
7023 20:17:33.659563 DUTY Scan : NO K
7024 20:17:33.662627 ZQ Calibration : PASS
7025 20:17:33.666253 Jitter Meter : NO K
7026 20:17:33.666335 CBT Training : PASS
7027 20:17:33.669405 Write leveling : PASS
7028 20:17:33.672834 RX DQS gating : PASS
7029 20:17:33.672916 RX DQ/DQS(RDDQC) : PASS
7030 20:17:33.675868 TX DQ/DQS : PASS
7031 20:17:33.675951 RX DATLAT : PASS
7032 20:17:33.679580 RX DQ/DQS(Engine): PASS
7033 20:17:33.683025 TX OE : NO K
7034 20:17:33.683108 All Pass.
7035 20:17:33.683173
7036 20:17:33.683233 CH 1, Rank 1
7037 20:17:33.685934 SW Impedance : PASS
7038 20:17:33.689559 DUTY Scan : NO K
7039 20:17:33.689642 ZQ Calibration : PASS
7040 20:17:33.692791 Jitter Meter : NO K
7041 20:17:33.695829 CBT Training : PASS
7042 20:17:33.695932 Write leveling : NO K
7043 20:17:33.699459 RX DQS gating : PASS
7044 20:17:33.702307 RX DQ/DQS(RDDQC) : PASS
7045 20:17:33.702389 TX DQ/DQS : PASS
7046 20:17:33.705744 RX DATLAT : PASS
7047 20:17:33.709346 RX DQ/DQS(Engine): PASS
7048 20:17:33.709429 TX OE : NO K
7049 20:17:33.709495 All Pass.
7050 20:17:33.712562
7051 20:17:33.712644 DramC Write-DBI off
7052 20:17:33.716186 PER_BANK_REFRESH: Hybrid Mode
7053 20:17:33.716321 TX_TRACKING: ON
7054 20:17:33.725871 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7055 20:17:33.729118 [FAST_K] Save calibration result to emmc
7056 20:17:33.732511 dramc_set_vcore_voltage set vcore to 725000
7057 20:17:33.735746 Read voltage for 1600, 0
7058 20:17:33.735843 Vio18 = 0
7059 20:17:33.738789 Vcore = 725000
7060 20:17:33.738872 Vdram = 0
7061 20:17:33.738937 Vddq = 0
7062 20:17:33.742433 Vmddr = 0
7063 20:17:33.745544 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7064 20:17:33.752495 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7065 20:17:33.752577 MEM_TYPE=3, freq_sel=13
7066 20:17:33.755502 sv_algorithm_assistance_LP4_3733
7067 20:17:33.759086 ============ PULL DRAM RESETB DOWN ============
7068 20:17:33.765935 ========== PULL DRAM RESETB DOWN end =========
7069 20:17:33.769117 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7070 20:17:33.772021 ===================================
7071 20:17:33.775492 LPDDR4 DRAM CONFIGURATION
7072 20:17:33.778803 ===================================
7073 20:17:33.778886 EX_ROW_EN[0] = 0x0
7074 20:17:33.781965 EX_ROW_EN[1] = 0x0
7075 20:17:33.785470 LP4Y_EN = 0x0
7076 20:17:33.785552 WORK_FSP = 0x1
7077 20:17:33.788829 WL = 0x5
7078 20:17:33.788912 RL = 0x5
7079 20:17:33.792202 BL = 0x2
7080 20:17:33.792304 RPST = 0x0
7081 20:17:33.795569 RD_PRE = 0x0
7082 20:17:33.795651 WR_PRE = 0x1
7083 20:17:33.799014 WR_PST = 0x1
7084 20:17:33.799096 DBI_WR = 0x0
7085 20:17:33.801859 DBI_RD = 0x0
7086 20:17:33.801942 OTF = 0x1
7087 20:17:33.805315 ===================================
7088 20:17:33.808625 ===================================
7089 20:17:33.811875 ANA top config
7090 20:17:33.815426 ===================================
7091 20:17:33.815508 DLL_ASYNC_EN = 0
7092 20:17:33.818413 ALL_SLAVE_EN = 0
7093 20:17:33.822082 NEW_RANK_MODE = 1
7094 20:17:33.824978 DLL_IDLE_MODE = 1
7095 20:17:33.828600 LP45_APHY_COMB_EN = 1
7096 20:17:33.828729 TX_ODT_DIS = 0
7097 20:17:33.831758 NEW_8X_MODE = 1
7098 20:17:33.835227 ===================================
7099 20:17:33.838645 ===================================
7100 20:17:33.842195 data_rate = 3200
7101 20:17:33.845423 CKR = 1
7102 20:17:33.848467 DQ_P2S_RATIO = 8
7103 20:17:33.851563 ===================================
7104 20:17:33.851671 CA_P2S_RATIO = 8
7105 20:17:33.855269 DQ_CA_OPEN = 0
7106 20:17:33.858410 DQ_SEMI_OPEN = 0
7107 20:17:33.861583 CA_SEMI_OPEN = 0
7108 20:17:33.865212 CA_FULL_RATE = 0
7109 20:17:33.868199 DQ_CKDIV4_EN = 0
7110 20:17:33.868281 CA_CKDIV4_EN = 0
7111 20:17:33.871897 CA_PREDIV_EN = 0
7112 20:17:33.875073 PH8_DLY = 12
7113 20:17:33.878730 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7114 20:17:33.881698 DQ_AAMCK_DIV = 4
7115 20:17:33.884751 CA_AAMCK_DIV = 4
7116 20:17:33.884834 CA_ADMCK_DIV = 4
7117 20:17:33.888571 DQ_TRACK_CA_EN = 0
7118 20:17:33.891570 CA_PICK = 1600
7119 20:17:33.895044 CA_MCKIO = 1600
7120 20:17:33.898519 MCKIO_SEMI = 0
7121 20:17:33.901377 PLL_FREQ = 3068
7122 20:17:33.905046 DQ_UI_PI_RATIO = 32
7123 20:17:33.908048 CA_UI_PI_RATIO = 0
7124 20:17:33.908175 ===================================
7125 20:17:33.911603 ===================================
7126 20:17:33.914742 memory_type:LPDDR4
7127 20:17:33.918053 GP_NUM : 10
7128 20:17:33.918136 SRAM_EN : 1
7129 20:17:33.921437 MD32_EN : 0
7130 20:17:33.925067 ===================================
7131 20:17:33.928182 [ANA_INIT] >>>>>>>>>>>>>>
7132 20:17:33.931429 <<<<<< [CONFIGURE PHASE]: ANA_TX
7133 20:17:33.934569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7134 20:17:33.938152 ===================================
7135 20:17:33.938281 data_rate = 3200,PCW = 0X7600
7136 20:17:33.941620 ===================================
7137 20:17:33.945068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7138 20:17:33.951388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 20:17:33.958491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 20:17:33.961538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7141 20:17:33.965250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7142 20:17:33.968363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7143 20:17:33.971470 [ANA_INIT] flow start
7144 20:17:33.974632 [ANA_INIT] PLL >>>>>>>>
7145 20:17:33.974757 [ANA_INIT] PLL <<<<<<<<
7146 20:17:33.978415 [ANA_INIT] MIDPI >>>>>>>>
7147 20:17:33.981538 [ANA_INIT] MIDPI <<<<<<<<
7148 20:17:33.981662 [ANA_INIT] DLL >>>>>>>>
7149 20:17:33.984596 [ANA_INIT] DLL <<<<<<<<
7150 20:17:33.988020 [ANA_INIT] flow end
7151 20:17:33.991791 ============ LP4 DIFF to SE enter ============
7152 20:17:33.994783 ============ LP4 DIFF to SE exit ============
7153 20:17:33.998474 [ANA_INIT] <<<<<<<<<<<<<
7154 20:17:34.001444 [Flow] Enable top DCM control >>>>>
7155 20:17:34.004576 [Flow] Enable top DCM control <<<<<
7156 20:17:34.008245 Enable DLL master slave shuffle
7157 20:17:34.011304 ==============================================================
7158 20:17:34.014780 Gating Mode config
7159 20:17:34.018268 ==============================================================
7160 20:17:34.021288 Config description:
7161 20:17:34.031068 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7162 20:17:34.038224 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7163 20:17:34.041256 SELPH_MODE 0: By rank 1: By Phase
7164 20:17:34.048018 ==============================================================
7165 20:17:34.051319 GAT_TRACK_EN = 1
7166 20:17:34.054439 RX_GATING_MODE = 2
7167 20:17:34.057552 RX_GATING_TRACK_MODE = 2
7168 20:17:34.061009 SELPH_MODE = 1
7169 20:17:34.064457 PICG_EARLY_EN = 1
7170 20:17:34.064539 VALID_LAT_VALUE = 1
7171 20:17:34.071558 ==============================================================
7172 20:17:34.074568 Enter into Gating configuration >>>>
7173 20:17:34.077773 Exit from Gating configuration <<<<
7174 20:17:34.081231 Enter into DVFS_PRE_config >>>>>
7175 20:17:34.090950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7176 20:17:34.094585 Exit from DVFS_PRE_config <<<<<
7177 20:17:34.097586 Enter into PICG configuration >>>>
7178 20:17:34.101349 Exit from PICG configuration <<<<
7179 20:17:34.104398 [RX_INPUT] configuration >>>>>
7180 20:17:34.108005 [RX_INPUT] configuration <<<<<
7181 20:17:34.111236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7182 20:17:34.117998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7183 20:17:34.124372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 20:17:34.130968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 20:17:34.137518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 20:17:34.144443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 20:17:34.147537 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7188 20:17:34.151116 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7189 20:17:34.154448 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7190 20:17:34.157372 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7191 20:17:34.164784 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7192 20:17:34.167654 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 20:17:34.170984 ===================================
7194 20:17:34.174274 LPDDR4 DRAM CONFIGURATION
7195 20:17:34.177271 ===================================
7196 20:17:34.177374 EX_ROW_EN[0] = 0x0
7197 20:17:34.181257 EX_ROW_EN[1] = 0x0
7198 20:17:34.181360 LP4Y_EN = 0x0
7199 20:17:34.184094 WORK_FSP = 0x1
7200 20:17:34.184197 WL = 0x5
7201 20:17:34.187393 RL = 0x5
7202 20:17:34.191086 BL = 0x2
7203 20:17:34.191203 RPST = 0x0
7204 20:17:34.194295 RD_PRE = 0x0
7205 20:17:34.194409 WR_PRE = 0x1
7206 20:17:34.198077 WR_PST = 0x1
7207 20:17:34.198183 DBI_WR = 0x0
7208 20:17:34.200908 DBI_RD = 0x0
7209 20:17:34.201007 OTF = 0x1
7210 20:17:34.203922 ===================================
7211 20:17:34.207058 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7212 20:17:34.214246 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7213 20:17:34.217225 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 20:17:34.220308 ===================================
7215 20:17:34.224000 LPDDR4 DRAM CONFIGURATION
7216 20:17:34.227152 ===================================
7217 20:17:34.227236 EX_ROW_EN[0] = 0x10
7218 20:17:34.230529 EX_ROW_EN[1] = 0x0
7219 20:17:34.230611 LP4Y_EN = 0x0
7220 20:17:34.234116 WORK_FSP = 0x1
7221 20:17:34.234199 WL = 0x5
7222 20:17:34.237261 RL = 0x5
7223 20:17:34.237343 BL = 0x2
7224 20:17:34.240222 RPST = 0x0
7225 20:17:34.243844 RD_PRE = 0x0
7226 20:17:34.243927 WR_PRE = 0x1
7227 20:17:34.247388 WR_PST = 0x1
7228 20:17:34.247471 DBI_WR = 0x0
7229 20:17:34.250595 DBI_RD = 0x0
7230 20:17:34.250677 OTF = 0x1
7231 20:17:34.254185 ===================================
7232 20:17:34.260602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7233 20:17:34.260685 ==
7234 20:17:34.263585 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 20:17:34.267170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7236 20:17:34.267254 ==
7237 20:17:34.270233 [Duty_Offset_Calibration]
7238 20:17:34.273847 B0:2 B1:1 CA:1
7239 20:17:34.273959
7240 20:17:34.276906 [DutyScan_Calibration_Flow] k_type=0
7241 20:17:34.285241
7242 20:17:34.285323 ==CLK 0==
7243 20:17:34.288877 Final CLK duty delay cell = 0
7244 20:17:34.292008 [0] MAX Duty = 5187%(X100), DQS PI = 24
7245 20:17:34.295439 [0] MIN Duty = 4907%(X100), DQS PI = 0
7246 20:17:34.295522 [0] AVG Duty = 5047%(X100)
7247 20:17:34.298788
7248 20:17:34.298870 CH0 CLK Duty spec in!! Max-Min= 280%
7249 20:17:34.305606 [DutyScan_Calibration_Flow] ====Done====
7250 20:17:34.305689
7251 20:17:34.308608 [DutyScan_Calibration_Flow] k_type=1
7252 20:17:34.324205
7253 20:17:34.324296 ==DQS 0 ==
7254 20:17:34.328061 Final DQS duty delay cell = -4
7255 20:17:34.330912 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7256 20:17:34.334154 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7257 20:17:34.337808 [-4] AVG Duty = 4906%(X100)
7258 20:17:34.337931
7259 20:17:34.338035 ==DQS 1 ==
7260 20:17:34.340733 Final DQS duty delay cell = 0
7261 20:17:34.343897 [0] MAX Duty = 5187%(X100), DQS PI = 6
7262 20:17:34.347575 [0] MIN Duty = 5031%(X100), DQS PI = 52
7263 20:17:34.350564 [0] AVG Duty = 5109%(X100)
7264 20:17:34.350686
7265 20:17:34.354246 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7266 20:17:34.354369
7267 20:17:34.357229 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7268 20:17:34.360993 [DutyScan_Calibration_Flow] ====Done====
7269 20:17:34.361115
7270 20:17:34.363936 [DutyScan_Calibration_Flow] k_type=3
7271 20:17:34.381435
7272 20:17:34.381560 ==DQM 0 ==
7273 20:17:34.385163 Final DQM duty delay cell = 0
7274 20:17:34.388700 [0] MAX Duty = 5187%(X100), DQS PI = 26
7275 20:17:34.391980 [0] MIN Duty = 4875%(X100), DQS PI = 58
7276 20:17:34.392102 [0] AVG Duty = 5031%(X100)
7277 20:17:34.394964
7278 20:17:34.395083 ==DQM 1 ==
7279 20:17:34.398671 Final DQM duty delay cell = 0
7280 20:17:34.401760 [0] MAX Duty = 5187%(X100), DQS PI = 8
7281 20:17:34.404895 [0] MIN Duty = 5031%(X100), DQS PI = 50
7282 20:17:34.405018 [0] AVG Duty = 5109%(X100)
7283 20:17:34.408366
7284 20:17:34.411961 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7285 20:17:34.412078
7286 20:17:34.415059 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7287 20:17:34.417978 [DutyScan_Calibration_Flow] ====Done====
7288 20:17:34.418101
7289 20:17:34.421620 [DutyScan_Calibration_Flow] k_type=2
7290 20:17:34.438964
7291 20:17:34.439095 ==DQ 0 ==
7292 20:17:34.442179 Final DQ duty delay cell = 0
7293 20:17:34.445751 [0] MAX Duty = 5062%(X100), DQS PI = 24
7294 20:17:34.448854 [0] MIN Duty = 4907%(X100), DQS PI = 0
7295 20:17:34.448973 [0] AVG Duty = 4984%(X100)
7296 20:17:34.449088
7297 20:17:34.451869 ==DQ 1 ==
7298 20:17:34.455291 Final DQ duty delay cell = 0
7299 20:17:34.458707 [0] MAX Duty = 5125%(X100), DQS PI = 6
7300 20:17:34.462327 [0] MIN Duty = 4907%(X100), DQS PI = 34
7301 20:17:34.462448 [0] AVG Duty = 5016%(X100)
7302 20:17:34.462560
7303 20:17:34.465389 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7304 20:17:34.465510
7305 20:17:34.469099 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7306 20:17:34.475254 [DutyScan_Calibration_Flow] ====Done====
7307 20:17:34.475380 ==
7308 20:17:34.479086 Dram Type= 6, Freq= 0, CH_1, rank 0
7309 20:17:34.482203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 20:17:34.482323 ==
7311 20:17:34.485278 [Duty_Offset_Calibration]
7312 20:17:34.485402 B0:1 B1:0 CA:0
7313 20:17:34.485511
7314 20:17:34.488987 [DutyScan_Calibration_Flow] k_type=0
7315 20:17:34.497928
7316 20:17:34.498049 ==CLK 0==
7317 20:17:34.501561 Final CLK duty delay cell = -4
7318 20:17:34.504574 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7319 20:17:34.508165 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7320 20:17:34.511177 [-4] AVG Duty = 4922%(X100)
7321 20:17:34.511296
7322 20:17:34.514798 CH1 CLK Duty spec in!! Max-Min= 156%
7323 20:17:34.517949 [DutyScan_Calibration_Flow] ====Done====
7324 20:17:34.518069
7325 20:17:34.520962 [DutyScan_Calibration_Flow] k_type=1
7326 20:17:34.538235
7327 20:17:34.538359 ==DQS 0 ==
7328 20:17:34.541602 Final DQS duty delay cell = 0
7329 20:17:34.545020 [0] MAX Duty = 5094%(X100), DQS PI = 24
7330 20:17:34.548001 [0] MIN Duty = 4844%(X100), DQS PI = 48
7331 20:17:34.551615 [0] AVG Duty = 4969%(X100)
7332 20:17:34.551695
7333 20:17:34.551759 ==DQS 1 ==
7334 20:17:34.554684 Final DQS duty delay cell = 0
7335 20:17:34.558659 [0] MAX Duty = 5249%(X100), DQS PI = 16
7336 20:17:34.561261 [0] MIN Duty = 4938%(X100), DQS PI = 8
7337 20:17:34.564661 [0] AVG Duty = 5093%(X100)
7338 20:17:34.564783
7339 20:17:34.567974 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7340 20:17:34.568095
7341 20:17:34.571383 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7342 20:17:34.574900 [DutyScan_Calibration_Flow] ====Done====
7343 20:17:34.575022
7344 20:17:34.577837 [DutyScan_Calibration_Flow] k_type=3
7345 20:17:34.595313
7346 20:17:34.595435 ==DQM 0 ==
7347 20:17:34.598390 Final DQM duty delay cell = 0
7348 20:17:34.601809 [0] MAX Duty = 5218%(X100), DQS PI = 18
7349 20:17:34.604722 [0] MIN Duty = 4969%(X100), DQS PI = 48
7350 20:17:34.608421 [0] AVG Duty = 5093%(X100)
7351 20:17:34.608543
7352 20:17:34.608653 ==DQM 1 ==
7353 20:17:34.611497 Final DQM duty delay cell = 0
7354 20:17:34.614979 [0] MAX Duty = 5062%(X100), DQS PI = 16
7355 20:17:34.618135 [0] MIN Duty = 4876%(X100), DQS PI = 52
7356 20:17:34.621904 [0] AVG Duty = 4969%(X100)
7357 20:17:34.622023
7358 20:17:34.624927 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7359 20:17:34.625047
7360 20:17:34.628663 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7361 20:17:34.631440 [DutyScan_Calibration_Flow] ====Done====
7362 20:17:34.631562
7363 20:17:34.635380 [DutyScan_Calibration_Flow] k_type=2
7364 20:17:34.651182
7365 20:17:34.651303 ==DQ 0 ==
7366 20:17:34.654902 Final DQ duty delay cell = -4
7367 20:17:34.657959 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7368 20:17:34.661095 [-4] MIN Duty = 4875%(X100), DQS PI = 48
7369 20:17:34.664624 [-4] AVG Duty = 4953%(X100)
7370 20:17:34.664738
7371 20:17:34.664851 ==DQ 1 ==
7372 20:17:34.667662 Final DQ duty delay cell = 0
7373 20:17:34.671085 [0] MAX Duty = 5156%(X100), DQS PI = 18
7374 20:17:34.674640 [0] MIN Duty = 4938%(X100), DQS PI = 8
7375 20:17:34.674763 [0] AVG Duty = 5047%(X100)
7376 20:17:34.677734
7377 20:17:34.681185 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7378 20:17:34.681306
7379 20:17:34.684718 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7380 20:17:34.687864 [DutyScan_Calibration_Flow] ====Done====
7381 20:17:34.691091 nWR fixed to 30
7382 20:17:34.691212 [ModeRegInit_LP4] CH0 RK0
7383 20:17:34.694164 [ModeRegInit_LP4] CH0 RK1
7384 20:17:34.697390 [ModeRegInit_LP4] CH1 RK0
7385 20:17:34.700804 [ModeRegInit_LP4] CH1 RK1
7386 20:17:34.700924 match AC timing 5
7387 20:17:34.707552 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7388 20:17:34.710994 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7389 20:17:34.714018 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7390 20:17:34.720709 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7391 20:17:34.724376 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7392 20:17:34.724498 [MiockJmeterHQA]
7393 20:17:34.724610
7394 20:17:34.727464 [DramcMiockJmeter] u1RxGatingPI = 0
7395 20:17:34.730612 0 : 4255, 4030
7396 20:17:34.730735 4 : 4252, 4027
7397 20:17:34.734311 8 : 4257, 4029
7398 20:17:34.734435 12 : 4366, 4140
7399 20:17:34.734551 16 : 4252, 4027
7400 20:17:34.737296 20 : 4252, 4027
7401 20:17:34.737419 24 : 4252, 4027
7402 20:17:34.740899 28 : 4363, 4137
7403 20:17:34.741020 32 : 4252, 4026
7404 20:17:34.744164 36 : 4363, 4137
7405 20:17:34.744293 40 : 4252, 4027
7406 20:17:34.747577 44 : 4252, 4027
7407 20:17:34.747699 48 : 4253, 4027
7408 20:17:34.747814 52 : 4254, 4029
7409 20:17:34.750894 56 : 4361, 4137
7410 20:17:34.751015 60 : 4250, 4027
7411 20:17:34.753915 64 : 4360, 4137
7412 20:17:34.754039 68 : 4250, 4027
7413 20:17:34.757163 72 : 4250, 4027
7414 20:17:34.757287 76 : 4250, 4026
7415 20:17:34.760694 80 : 4361, 4137
7416 20:17:34.760819 84 : 4250, 4027
7417 20:17:34.760931 88 : 4361, 105
7418 20:17:34.763822 92 : 4250, 0
7419 20:17:34.763943 96 : 4252, 0
7420 20:17:34.764057 100 : 4361, 0
7421 20:17:34.767413 104 : 4250, 0
7422 20:17:34.767536 108 : 4250, 0
7423 20:17:34.770536 112 : 4250, 0
7424 20:17:34.770660 116 : 4360, 0
7425 20:17:34.770775 120 : 4361, 0
7426 20:17:34.774218 124 : 4250, 0
7427 20:17:34.774342 128 : 4250, 0
7428 20:17:34.777355 132 : 4250, 0
7429 20:17:34.777475 136 : 4363, 0
7430 20:17:34.777589 140 : 4253, 0
7431 20:17:34.780944 144 : 4250, 0
7432 20:17:34.781067 148 : 4252, 0
7433 20:17:34.783846 152 : 4361, 0
7434 20:17:34.783954 156 : 4250, 0
7435 20:17:34.784048 160 : 4250, 0
7436 20:17:34.787392 164 : 4250, 0
7437 20:17:34.787493 168 : 4361, 0
7438 20:17:34.787585 172 : 4250, 0
7439 20:17:34.790980 176 : 4252, 0
7440 20:17:34.791063 180 : 4253, 0
7441 20:17:34.793779 184 : 4250, 0
7442 20:17:34.793862 188 : 4252, 0
7443 20:17:34.793927 192 : 4253, 0
7444 20:17:34.797605 196 : 4249, 0
7445 20:17:34.797688 200 : 4252, 0
7446 20:17:34.800624 204 : 4361, 1753
7447 20:17:34.800706 208 : 4250, 3998
7448 20:17:34.804133 212 : 4361, 4138
7449 20:17:34.804216 216 : 4250, 4027
7450 20:17:34.806962 220 : 4250, 4026
7451 20:17:34.807045 224 : 4250, 4026
7452 20:17:34.807111 228 : 4252, 4029
7453 20:17:34.810191 232 : 4250, 4027
7454 20:17:34.810274 236 : 4250, 4027
7455 20:17:34.814010 240 : 4250, 4027
7456 20:17:34.814093 244 : 4253, 4029
7457 20:17:34.817251 248 : 4250, 4027
7458 20:17:34.817375 252 : 4361, 4137
7459 20:17:34.820568 256 : 4361, 4137
7460 20:17:34.820691 260 : 4250, 4027
7461 20:17:34.823706 264 : 4363, 4139
7462 20:17:34.823828 268 : 4361, 4137
7463 20:17:34.826905 272 : 4253, 4027
7464 20:17:34.827030 276 : 4250, 4027
7465 20:17:34.830327 280 : 4252, 4029
7466 20:17:34.830452 284 : 4250, 4027
7467 20:17:34.830567 288 : 4252, 4030
7468 20:17:34.833729 292 : 4250, 4027
7469 20:17:34.833854 296 : 4252, 4029
7470 20:17:34.837207 300 : 4250, 4027
7471 20:17:34.837440 304 : 4360, 4138
7472 20:17:34.840757 308 : 4361, 4051
7473 20:17:34.840863 312 : 4250, 1913
7474 20:17:34.840958
7475 20:17:34.843768 MIOCK jitter meter ch=0
7476 20:17:34.843863
7477 20:17:34.847566 1T = (312-88) = 224 dly cells
7478 20:17:34.853493 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7479 20:17:34.853575 ==
7480 20:17:34.857036 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 20:17:34.860319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7482 20:17:34.860415 ==
7483 20:17:34.863629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7484 20:17:34.870653 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7485 20:17:34.873735 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7486 20:17:34.880070 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7487 20:17:34.888886 [CA 0] Center 43 (13~74) winsize 62
7488 20:17:34.892022 [CA 1] Center 43 (13~74) winsize 62
7489 20:17:34.895568 [CA 2] Center 38 (9~68) winsize 60
7490 20:17:34.898852 [CA 3] Center 38 (8~68) winsize 61
7491 20:17:34.901856 [CA 4] Center 37 (7~67) winsize 61
7492 20:17:34.905712 [CA 5] Center 36 (7~65) winsize 59
7493 20:17:34.905794
7494 20:17:34.908941 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7495 20:17:34.909022
7496 20:17:34.911977 [CATrainingPosCal] consider 1 rank data
7497 20:17:34.915657 u2DelayCellTimex100 = 290/100 ps
7498 20:17:34.918633 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7499 20:17:34.925376 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7500 20:17:34.928480 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7501 20:17:34.931894 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7502 20:17:34.935464 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7503 20:17:34.938589 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7504 20:17:34.938714
7505 20:17:34.942077 CA PerBit enable=1, Macro0, CA PI delay=36
7506 20:17:34.942181
7507 20:17:34.945217 [CBTSetCACLKResult] CA Dly = 36
7508 20:17:34.945323 CS Dly: 9 (0~40)
7509 20:17:34.952204 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7510 20:17:34.955164 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7511 20:17:34.955246 ==
7512 20:17:34.958644 Dram Type= 6, Freq= 0, CH_0, rank 1
7513 20:17:34.962311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 20:17:34.962399 ==
7515 20:17:34.968849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 20:17:34.972093 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 20:17:34.978394 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 20:17:34.982009 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 20:17:34.991975 [CA 0] Center 42 (12~73) winsize 62
7520 20:17:34.995447 [CA 1] Center 42 (12~73) winsize 62
7521 20:17:34.998851 [CA 2] Center 38 (9~68) winsize 60
7522 20:17:35.001808 [CA 3] Center 38 (8~68) winsize 61
7523 20:17:35.005290 [CA 4] Center 36 (7~66) winsize 60
7524 20:17:35.008878 [CA 5] Center 35 (6~65) winsize 60
7525 20:17:35.008985
7526 20:17:35.012007 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 20:17:35.012088
7528 20:17:35.015647 [CATrainingPosCal] consider 2 rank data
7529 20:17:35.018780 u2DelayCellTimex100 = 290/100 ps
7530 20:17:35.021811 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7531 20:17:35.028957 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7532 20:17:35.032007 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7533 20:17:35.035003 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7534 20:17:35.038568 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7535 20:17:35.041680 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7536 20:17:35.041762
7537 20:17:35.045299 CA PerBit enable=1, Macro0, CA PI delay=36
7538 20:17:35.045406
7539 20:17:35.048323 [CBTSetCACLKResult] CA Dly = 36
7540 20:17:35.051640 CS Dly: 10 (0~42)
7541 20:17:35.055155 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 20:17:35.058686 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 20:17:35.058793
7544 20:17:35.062190 ----->DramcWriteLeveling(PI) begin...
7545 20:17:35.062272 ==
7546 20:17:35.065214 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 20:17:35.068719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 20:17:35.071435 ==
7549 20:17:35.071529 Write leveling (Byte 0): 35 => 35
7550 20:17:35.075203 Write leveling (Byte 1): 28 => 28
7551 20:17:35.078189 DramcWriteLeveling(PI) end<-----
7552 20:17:35.078270
7553 20:17:35.078335 ==
7554 20:17:35.081553 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 20:17:35.088138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 20:17:35.088266 ==
7557 20:17:35.091616 [Gating] SW mode calibration
7558 20:17:35.098404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7559 20:17:35.101353 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7560 20:17:35.108252 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7561 20:17:35.111540 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7562 20:17:35.114606 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7563 20:17:35.121660 1 4 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)
7564 20:17:35.124698 1 4 16 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)
7565 20:17:35.128458 1 4 20 | B1->B0 | 3333 3535 | 1 1 | (1 1) (1 1)
7566 20:17:35.131335 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7567 20:17:35.137898 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 20:17:35.141465 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7569 20:17:35.145082 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7570 20:17:35.151232 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7571 20:17:35.154935 1 5 12 | B1->B0 | 3434 2d2c | 1 1 | (1 1) (1 0)
7572 20:17:35.158012 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7573 20:17:35.164765 1 5 20 | B1->B0 | 2929 2f2e | 0 1 | (0 0) (0 0)
7574 20:17:35.167834 1 5 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7575 20:17:35.171667 1 5 28 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7576 20:17:35.177880 1 6 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7577 20:17:35.181712 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7578 20:17:35.184577 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
7579 20:17:35.191128 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7580 20:17:35.194563 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7581 20:17:35.197840 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7582 20:17:35.204684 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7583 20:17:35.207865 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 20:17:35.211072 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 20:17:35.217615 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 20:17:35.221080 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 20:17:35.224468 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 20:17:35.231139 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 20:17:35.234300 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 20:17:35.237680 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 20:17:35.244373 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 20:17:35.248075 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 20:17:35.251276 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 20:17:35.254336 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 20:17:35.261029 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 20:17:35.264732 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 20:17:35.268244 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 20:17:35.274976 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 20:17:35.278121 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 20:17:35.281176 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 20:17:35.288024 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 20:17:35.291759 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 20:17:35.295019 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 20:17:35.301236 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7605 20:17:35.301362 Total UI for P1: 0, mck2ui 16
7606 20:17:35.307888 best dqsien dly found for B0: ( 1, 9, 10)
7607 20:17:35.311293 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 20:17:35.314345 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7609 20:17:35.321150 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 20:17:35.321276 Total UI for P1: 0, mck2ui 16
7611 20:17:35.327730 best dqsien dly found for B1: ( 1, 9, 20)
7612 20:17:35.331135 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7613 20:17:35.334124 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7614 20:17:35.334247
7615 20:17:35.337696 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7616 20:17:35.340771 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7617 20:17:35.344438 [Gating] SW calibration Done
7618 20:17:35.344557 ==
7619 20:17:35.347192 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 20:17:35.351005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 20:17:35.351131 ==
7622 20:17:35.354000 RX Vref Scan: 0
7623 20:17:35.354123
7624 20:17:35.354286 RX Vref 0 -> 0, step: 1
7625 20:17:35.354426
7626 20:17:35.357469 RX Delay 0 -> 252, step: 8
7627 20:17:35.360503 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7628 20:17:35.367080 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7629 20:17:35.370766 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7630 20:17:35.373754 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7631 20:17:35.377388 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7632 20:17:35.380553 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7633 20:17:35.387466 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7634 20:17:35.390510 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7635 20:17:35.394099 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7636 20:17:35.397058 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7637 20:17:35.400818 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7638 20:17:35.407345 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7639 20:17:35.410432 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7640 20:17:35.413750 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7641 20:17:35.417160 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7642 20:17:35.420246 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7643 20:17:35.424018 ==
7644 20:17:35.426862 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 20:17:35.430088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 20:17:35.430209 ==
7647 20:17:35.430324 DQS Delay:
7648 20:17:35.433860 DQS0 = 0, DQS1 = 0
7649 20:17:35.433984 DQM Delay:
7650 20:17:35.437351 DQM0 = 137, DQM1 = 129
7651 20:17:35.437472 DQ Delay:
7652 20:17:35.440439 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7653 20:17:35.443751 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7654 20:17:35.446851 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
7655 20:17:35.450437 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7656 20:17:35.450557
7657 20:17:35.450670
7658 20:17:35.450780 ==
7659 20:17:35.453648 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 20:17:35.460377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 20:17:35.460499 ==
7662 20:17:35.460608
7663 20:17:35.460713
7664 20:17:35.460823 TX Vref Scan disable
7665 20:17:35.463681 == TX Byte 0 ==
7666 20:17:35.467595 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7667 20:17:35.473765 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7668 20:17:35.473889 == TX Byte 1 ==
7669 20:17:35.477167 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7670 20:17:35.483624 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7671 20:17:35.483747 ==
7672 20:17:35.487349 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 20:17:35.490622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 20:17:35.490747 ==
7675 20:17:35.502522
7676 20:17:35.505559 TX Vref early break, caculate TX vref
7677 20:17:35.509266 TX Vref=16, minBit 0, minWin=22, winSum=372
7678 20:17:35.512196 TX Vref=18, minBit 4, minWin=23, winSum=386
7679 20:17:35.515606 TX Vref=20, minBit 0, minWin=24, winSum=395
7680 20:17:35.518711 TX Vref=22, minBit 0, minWin=24, winSum=406
7681 20:17:35.522099 TX Vref=24, minBit 7, minWin=25, winSum=416
7682 20:17:35.528728 TX Vref=26, minBit 1, minWin=25, winSum=427
7683 20:17:35.532278 TX Vref=28, minBit 6, minWin=25, winSum=426
7684 20:17:35.535787 TX Vref=30, minBit 2, minWin=24, winSum=413
7685 20:17:35.539013 TX Vref=32, minBit 0, minWin=24, winSum=402
7686 20:17:35.545460 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 26
7687 20:17:35.545584
7688 20:17:35.549047 Final TX Range 0 Vref 26
7689 20:17:35.549167
7690 20:17:35.549281 ==
7691 20:17:35.552161 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 20:17:35.555671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 20:17:35.555791 ==
7694 20:17:35.555904
7695 20:17:35.556014
7696 20:17:35.558979 TX Vref Scan disable
7697 20:17:35.562450 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7698 20:17:35.565591 == TX Byte 0 ==
7699 20:17:35.568673 u2DelayCellOfst[0]=10 cells (3 PI)
7700 20:17:35.572023 u2DelayCellOfst[1]=16 cells (5 PI)
7701 20:17:35.575693 u2DelayCellOfst[2]=10 cells (3 PI)
7702 20:17:35.578828 u2DelayCellOfst[3]=6 cells (2 PI)
7703 20:17:35.581990 u2DelayCellOfst[4]=6 cells (2 PI)
7704 20:17:35.582112 u2DelayCellOfst[5]=0 cells (0 PI)
7705 20:17:35.585520 u2DelayCellOfst[6]=16 cells (5 PI)
7706 20:17:35.589020 u2DelayCellOfst[7]=16 cells (5 PI)
7707 20:17:35.595171 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7708 20:17:35.598554 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7709 20:17:35.598678 == TX Byte 1 ==
7710 20:17:35.602124 u2DelayCellOfst[8]=0 cells (0 PI)
7711 20:17:35.605628 u2DelayCellOfst[9]=0 cells (0 PI)
7712 20:17:35.608746 u2DelayCellOfst[10]=6 cells (2 PI)
7713 20:17:35.612191 u2DelayCellOfst[11]=6 cells (2 PI)
7714 20:17:35.615225 u2DelayCellOfst[12]=10 cells (3 PI)
7715 20:17:35.618578 u2DelayCellOfst[13]=13 cells (4 PI)
7716 20:17:35.621908 u2DelayCellOfst[14]=16 cells (5 PI)
7717 20:17:35.625312 u2DelayCellOfst[15]=10 cells (3 PI)
7718 20:17:35.628820 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7719 20:17:35.631691 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7720 20:17:35.635416 DramC Write-DBI on
7721 20:17:35.635537 ==
7722 20:17:35.638462 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 20:17:35.642184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 20:17:35.642306 ==
7725 20:17:35.642419
7726 20:17:35.642527
7727 20:17:35.644949 TX Vref Scan disable
7728 20:17:35.648481 == TX Byte 0 ==
7729 20:17:35.651772 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7730 20:17:35.654889 == TX Byte 1 ==
7731 20:17:35.658635 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7732 20:17:35.658758 DramC Write-DBI off
7733 20:17:35.658869
7734 20:17:35.661732 [DATLAT]
7735 20:17:35.661850 Freq=1600, CH0 RK0
7736 20:17:35.661964
7737 20:17:35.665377 DATLAT Default: 0xf
7738 20:17:35.665460 0, 0xFFFF, sum = 0
7739 20:17:35.668467 1, 0xFFFF, sum = 0
7740 20:17:35.668550 2, 0xFFFF, sum = 0
7741 20:17:35.672006 3, 0xFFFF, sum = 0
7742 20:17:35.672091 4, 0xFFFF, sum = 0
7743 20:17:35.674968 5, 0xFFFF, sum = 0
7744 20:17:35.675053 6, 0xFFFF, sum = 0
7745 20:17:35.678504 7, 0xFFFF, sum = 0
7746 20:17:35.678580 8, 0xFFFF, sum = 0
7747 20:17:35.681692 9, 0xFFFF, sum = 0
7748 20:17:35.681764 10, 0xFFFF, sum = 0
7749 20:17:35.685299 11, 0xFFFF, sum = 0
7750 20:17:35.688221 12, 0xFFFF, sum = 0
7751 20:17:35.688345 13, 0xFFFF, sum = 0
7752 20:17:35.691662 14, 0x0, sum = 1
7753 20:17:35.691744 15, 0x0, sum = 2
7754 20:17:35.695311 16, 0x0, sum = 3
7755 20:17:35.695393 17, 0x0, sum = 4
7756 20:17:35.695459 best_step = 15
7757 20:17:35.695519
7758 20:17:35.698336 ==
7759 20:17:35.698417 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 20:17:35.705198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 20:17:35.705280 ==
7762 20:17:35.705344 RX Vref Scan: 1
7763 20:17:35.705403
7764 20:17:35.708258 Set Vref Range= 24 -> 127
7765 20:17:35.708367
7766 20:17:35.711912 RX Vref 24 -> 127, step: 1
7767 20:17:35.712019
7768 20:17:35.715326 RX Delay 19 -> 252, step: 4
7769 20:17:35.715399
7770 20:17:35.718225 Set Vref, RX VrefLevel [Byte0]: 24
7771 20:17:35.721913 [Byte1]: 24
7772 20:17:35.721994
7773 20:17:35.724678 Set Vref, RX VrefLevel [Byte0]: 25
7774 20:17:35.728167 [Byte1]: 25
7775 20:17:35.728251
7776 20:17:35.731757 Set Vref, RX VrefLevel [Byte0]: 26
7777 20:17:35.734663 [Byte1]: 26
7778 20:17:35.738096
7779 20:17:35.738185 Set Vref, RX VrefLevel [Byte0]: 27
7780 20:17:35.741691 [Byte1]: 27
7781 20:17:35.745561
7782 20:17:35.745671 Set Vref, RX VrefLevel [Byte0]: 28
7783 20:17:35.749226 [Byte1]: 28
7784 20:17:35.753606
7785 20:17:35.753687 Set Vref, RX VrefLevel [Byte0]: 29
7786 20:17:35.756717 [Byte1]: 29
7787 20:17:35.760970
7788 20:17:35.761050 Set Vref, RX VrefLevel [Byte0]: 30
7789 20:17:35.764126 [Byte1]: 30
7790 20:17:35.768779
7791 20:17:35.768859 Set Vref, RX VrefLevel [Byte0]: 31
7792 20:17:35.771731 [Byte1]: 31
7793 20:17:35.776115
7794 20:17:35.776241 Set Vref, RX VrefLevel [Byte0]: 32
7795 20:17:35.779485 [Byte1]: 32
7796 20:17:35.783633
7797 20:17:35.783753 Set Vref, RX VrefLevel [Byte0]: 33
7798 20:17:35.786672 [Byte1]: 33
7799 20:17:35.790900
7800 20:17:35.791021 Set Vref, RX VrefLevel [Byte0]: 34
7801 20:17:35.794321 [Byte1]: 34
7802 20:17:35.798495
7803 20:17:35.798619 Set Vref, RX VrefLevel [Byte0]: 35
7804 20:17:35.802283 [Byte1]: 35
7805 20:17:35.806067
7806 20:17:35.806190 Set Vref, RX VrefLevel [Byte0]: 36
7807 20:17:35.809706 [Byte1]: 36
7808 20:17:35.813997
7809 20:17:35.814116 Set Vref, RX VrefLevel [Byte0]: 37
7810 20:17:35.816989 [Byte1]: 37
7811 20:17:35.821409
7812 20:17:35.821528 Set Vref, RX VrefLevel [Byte0]: 38
7813 20:17:35.824866 [Byte1]: 38
7814 20:17:35.829065
7815 20:17:35.829187 Set Vref, RX VrefLevel [Byte0]: 39
7816 20:17:35.832087 [Byte1]: 39
7817 20:17:35.836277
7818 20:17:35.836397 Set Vref, RX VrefLevel [Byte0]: 40
7819 20:17:35.839772 [Byte1]: 40
7820 20:17:35.844099
7821 20:17:35.844206 Set Vref, RX VrefLevel [Byte0]: 41
7822 20:17:35.847255 [Byte1]: 41
7823 20:17:35.851439
7824 20:17:35.851549 Set Vref, RX VrefLevel [Byte0]: 42
7825 20:17:35.855161 [Byte1]: 42
7826 20:17:35.859224
7827 20:17:35.859305 Set Vref, RX VrefLevel [Byte0]: 43
7828 20:17:35.862682 [Byte1]: 43
7829 20:17:35.866944
7830 20:17:35.867030 Set Vref, RX VrefLevel [Byte0]: 44
7831 20:17:35.869846 [Byte1]: 44
7832 20:17:35.874515
7833 20:17:35.874600 Set Vref, RX VrefLevel [Byte0]: 45
7834 20:17:35.877434 [Byte1]: 45
7835 20:17:35.881867
7836 20:17:35.881976 Set Vref, RX VrefLevel [Byte0]: 46
7837 20:17:35.885348 [Byte1]: 46
7838 20:17:35.889359
7839 20:17:35.889440 Set Vref, RX VrefLevel [Byte0]: 47
7840 20:17:35.893080 [Byte1]: 47
7841 20:17:35.896863
7842 20:17:35.896945 Set Vref, RX VrefLevel [Byte0]: 48
7843 20:17:35.900252 [Byte1]: 48
7844 20:17:35.904898
7845 20:17:35.905019 Set Vref, RX VrefLevel [Byte0]: 49
7846 20:17:35.907961 [Byte1]: 49
7847 20:17:35.912414
7848 20:17:35.912535 Set Vref, RX VrefLevel [Byte0]: 50
7849 20:17:35.915597 [Byte1]: 50
7850 20:17:35.919781
7851 20:17:35.919899 Set Vref, RX VrefLevel [Byte0]: 51
7852 20:17:35.922924 [Byte1]: 51
7853 20:17:35.927317
7854 20:17:35.927441 Set Vref, RX VrefLevel [Byte0]: 52
7855 20:17:35.930840 [Byte1]: 52
7856 20:17:35.934897
7857 20:17:35.935023 Set Vref, RX VrefLevel [Byte0]: 53
7858 20:17:35.938396 [Byte1]: 53
7859 20:17:35.942621
7860 20:17:35.942740 Set Vref, RX VrefLevel [Byte0]: 54
7861 20:17:35.945632 [Byte1]: 54
7862 20:17:35.950046
7863 20:17:35.953145 Set Vref, RX VrefLevel [Byte0]: 55
7864 20:17:35.956924 [Byte1]: 55
7865 20:17:35.957045
7866 20:17:35.959933 Set Vref, RX VrefLevel [Byte0]: 56
7867 20:17:35.962927 [Byte1]: 56
7868 20:17:35.963049
7869 20:17:35.966775 Set Vref, RX VrefLevel [Byte0]: 57
7870 20:17:35.969956 [Byte1]: 57
7871 20:17:35.970077
7872 20:17:35.973003 Set Vref, RX VrefLevel [Byte0]: 58
7873 20:17:35.976618 [Byte1]: 58
7874 20:17:35.980571
7875 20:17:35.980691 Set Vref, RX VrefLevel [Byte0]: 59
7876 20:17:35.983937 [Byte1]: 59
7877 20:17:35.987757
7878 20:17:35.987892 Set Vref, RX VrefLevel [Byte0]: 60
7879 20:17:35.991142 [Byte1]: 60
7880 20:17:35.995505
7881 20:17:35.995627 Set Vref, RX VrefLevel [Byte0]: 61
7882 20:17:35.998554 [Byte1]: 61
7883 20:17:36.003103
7884 20:17:36.003224 Set Vref, RX VrefLevel [Byte0]: 62
7885 20:17:36.006633 [Byte1]: 62
7886 20:17:36.010753
7887 20:17:36.010875 Set Vref, RX VrefLevel [Byte0]: 63
7888 20:17:36.013991 [Byte1]: 63
7889 20:17:36.018431
7890 20:17:36.018623 Set Vref, RX VrefLevel [Byte0]: 64
7891 20:17:36.021332 [Byte1]: 64
7892 20:17:36.025700
7893 20:17:36.025780 Set Vref, RX VrefLevel [Byte0]: 65
7894 20:17:36.029325 [Byte1]: 65
7895 20:17:36.033714
7896 20:17:36.033795 Set Vref, RX VrefLevel [Byte0]: 66
7897 20:17:36.036853 [Byte1]: 66
7898 20:17:36.040798
7899 20:17:36.040878 Set Vref, RX VrefLevel [Byte0]: 67
7900 20:17:36.044476 [Byte1]: 67
7901 20:17:36.048661
7902 20:17:36.048741 Set Vref, RX VrefLevel [Byte0]: 68
7903 20:17:36.051701 [Byte1]: 68
7904 20:17:36.056186
7905 20:17:36.056266 Set Vref, RX VrefLevel [Byte0]: 69
7906 20:17:36.059264 [Byte1]: 69
7907 20:17:36.063642
7908 20:17:36.063722 Set Vref, RX VrefLevel [Byte0]: 70
7909 20:17:36.067210 [Byte1]: 70
7910 20:17:36.071526
7911 20:17:36.071607 Set Vref, RX VrefLevel [Byte0]: 71
7912 20:17:36.074607 [Byte1]: 71
7913 20:17:36.078968
7914 20:17:36.079048 Set Vref, RX VrefLevel [Byte0]: 72
7915 20:17:36.082029 [Byte1]: 72
7916 20:17:36.086293
7917 20:17:36.086374 Set Vref, RX VrefLevel [Byte0]: 73
7918 20:17:36.089784 [Byte1]: 73
7919 20:17:36.093783
7920 20:17:36.093863 Set Vref, RX VrefLevel [Byte0]: 74
7921 20:17:36.097570 [Byte1]: 74
7922 20:17:36.101870
7923 20:17:36.101951 Set Vref, RX VrefLevel [Byte0]: 75
7924 20:17:36.104969 [Byte1]: 75
7925 20:17:36.109062
7926 20:17:36.109143 Final RX Vref Byte 0 = 59 to rank0
7927 20:17:36.112686 Final RX Vref Byte 1 = 58 to rank0
7928 20:17:36.115677 Final RX Vref Byte 0 = 59 to rank1
7929 20:17:36.119155 Final RX Vref Byte 1 = 58 to rank1==
7930 20:17:36.122540 Dram Type= 6, Freq= 0, CH_0, rank 0
7931 20:17:36.129199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7932 20:17:36.129281 ==
7933 20:17:36.129345 DQS Delay:
7934 20:17:36.129405 DQS0 = 0, DQS1 = 0
7935 20:17:36.132699 DQM Delay:
7936 20:17:36.132819 DQM0 = 134, DQM1 = 127
7937 20:17:36.135763 DQ Delay:
7938 20:17:36.138941 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7939 20:17:36.142344 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7940 20:17:36.145518 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7941 20:17:36.149254 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7942 20:17:36.149378
7943 20:17:36.149488
7944 20:17:36.149599
7945 20:17:36.152187 [DramC_TX_OE_Calibration] TA2
7946 20:17:36.155695 Original DQ_B0 (3 6) =30, OEN = 27
7947 20:17:36.159159 Original DQ_B1 (3 6) =30, OEN = 27
7948 20:17:36.162548 24, 0x0, End_B0=24 End_B1=24
7949 20:17:36.162631 25, 0x0, End_B0=25 End_B1=25
7950 20:17:36.165465 26, 0x0, End_B0=26 End_B1=26
7951 20:17:36.169158 27, 0x0, End_B0=27 End_B1=27
7952 20:17:36.172190 28, 0x0, End_B0=28 End_B1=28
7953 20:17:36.172297 29, 0x0, End_B0=29 End_B1=29
7954 20:17:36.175903 30, 0x0, End_B0=30 End_B1=30
7955 20:17:36.179005 31, 0x4141, End_B0=30 End_B1=30
7956 20:17:36.182160 Byte0 end_step=30 best_step=27
7957 20:17:36.185906 Byte1 end_step=30 best_step=27
7958 20:17:36.189130 Byte0 TX OE(2T, 0.5T) = (3, 3)
7959 20:17:36.189211 Byte1 TX OE(2T, 0.5T) = (3, 3)
7960 20:17:36.192158
7961 20:17:36.192241
7962 20:17:36.199129 [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7963 20:17:36.202399 CH0 RK0: MR19=303, MR18=2520
7964 20:17:36.209171 CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16
7965 20:17:36.209253
7966 20:17:36.212181 ----->DramcWriteLeveling(PI) begin...
7967 20:17:36.212276 ==
7968 20:17:36.215628 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 20:17:36.219177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 20:17:36.219280 ==
7971 20:17:36.222308 Write leveling (Byte 0): 37 => 37
7972 20:17:36.226095 Write leveling (Byte 1): 27 => 27
7973 20:17:36.229249 DramcWriteLeveling(PI) end<-----
7974 20:17:36.229331
7975 20:17:36.229395 ==
7976 20:17:36.232142 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 20:17:36.235621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 20:17:36.235702 ==
7979 20:17:36.239131 [Gating] SW mode calibration
7980 20:17:36.245566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7981 20:17:36.252207 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7982 20:17:36.255829 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 20:17:36.258922 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 20:17:36.265656 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7985 20:17:36.268988 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7986 20:17:36.272467 1 4 16 | B1->B0 | 3232 3535 | 0 1 | (0 0) (1 1)
7987 20:17:36.278999 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7988 20:17:36.282237 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7989 20:17:36.285291 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 20:17:36.292267 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7991 20:17:36.295525 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7992 20:17:36.299038 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7993 20:17:36.305622 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
7994 20:17:36.308591 1 5 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (1 0)
7995 20:17:36.312138 1 5 20 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7996 20:17:36.315914 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7997 20:17:36.322160 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7998 20:17:36.325751 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 20:17:36.328877 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8000 20:17:36.335637 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8001 20:17:36.338667 1 6 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8002 20:17:36.342377 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8003 20:17:36.348701 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 20:17:36.351779 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 20:17:36.355238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 20:17:36.362014 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 20:17:36.365351 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 20:17:36.368228 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 20:17:36.375247 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8010 20:17:36.378667 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8011 20:17:36.381557 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 20:17:36.388162 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 20:17:36.391701 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 20:17:36.395035 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 20:17:36.401806 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 20:17:36.405033 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 20:17:36.408150 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 20:17:36.414783 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 20:17:36.417893 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 20:17:36.421353 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 20:17:36.428000 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 20:17:36.431027 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 20:17:36.434636 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 20:17:36.441226 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8025 20:17:36.444236 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8026 20:17:36.448026 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 20:17:36.451072 Total UI for P1: 0, mck2ui 16
8028 20:17:36.454574 best dqsien dly found for B0: ( 1, 9, 10)
8029 20:17:36.457930 Total UI for P1: 0, mck2ui 16
8030 20:17:36.461276 best dqsien dly found for B1: ( 1, 9, 12)
8031 20:17:36.464171 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8032 20:17:36.467623 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8033 20:17:36.467705
8034 20:17:36.474462 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8035 20:17:36.477581 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8036 20:17:36.480718 [Gating] SW calibration Done
8037 20:17:36.480800 ==
8038 20:17:36.484225 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 20:17:36.487656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 20:17:36.487738 ==
8041 20:17:36.487803 RX Vref Scan: 0
8042 20:17:36.490804
8043 20:17:36.490885 RX Vref 0 -> 0, step: 1
8044 20:17:36.490950
8045 20:17:36.493910 RX Delay 0 -> 252, step: 8
8046 20:17:36.497600 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8047 20:17:36.500594 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8048 20:17:36.507648 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8049 20:17:36.510701 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8050 20:17:36.514114 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8051 20:17:36.517167 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8052 20:17:36.520459 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8053 20:17:36.527350 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8054 20:17:36.530664 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8055 20:17:36.533697 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8056 20:17:36.537108 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8057 20:17:36.540581 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8058 20:17:36.546753 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8059 20:17:36.550384 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8060 20:17:36.553498 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8061 20:17:36.556620 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8062 20:17:36.556702 ==
8063 20:17:36.560242 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 20:17:36.567032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 20:17:36.567113 ==
8066 20:17:36.567178 DQS Delay:
8067 20:17:36.569934 DQS0 = 0, DQS1 = 0
8068 20:17:36.570016 DQM Delay:
8069 20:17:36.570080 DQM0 = 137, DQM1 = 128
8070 20:17:36.573848 DQ Delay:
8071 20:17:36.577034 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8072 20:17:36.580190 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8073 20:17:36.583301 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8074 20:17:36.587058 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8075 20:17:36.587140
8076 20:17:36.587228
8077 20:17:36.587367 ==
8078 20:17:36.590014 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 20:17:36.593432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 20:17:36.596993 ==
8081 20:17:36.597075
8082 20:17:36.597140
8083 20:17:36.597199 TX Vref Scan disable
8084 20:17:36.600132 == TX Byte 0 ==
8085 20:17:36.603244 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8086 20:17:36.606842 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8087 20:17:36.610183 == TX Byte 1 ==
8088 20:17:36.613591 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8089 20:17:36.616760 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8090 20:17:36.619771 ==
8091 20:17:36.623193 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 20:17:36.626753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 20:17:36.626835 ==
8094 20:17:36.641300
8095 20:17:36.644294 TX Vref early break, caculate TX vref
8096 20:17:36.647831 TX Vref=16, minBit 0, minWin=23, winSum=383
8097 20:17:36.651136 TX Vref=18, minBit 1, minWin=23, winSum=394
8098 20:17:36.654347 TX Vref=20, minBit 1, minWin=23, winSum=402
8099 20:17:36.657999 TX Vref=22, minBit 0, minWin=24, winSum=413
8100 20:17:36.660977 TX Vref=24, minBit 0, minWin=25, winSum=415
8101 20:17:36.667629 TX Vref=26, minBit 1, minWin=25, winSum=428
8102 20:17:36.671228 TX Vref=28, minBit 0, minWin=25, winSum=423
8103 20:17:36.674189 TX Vref=30, minBit 2, minWin=25, winSum=415
8104 20:17:36.677900 TX Vref=32, minBit 4, minWin=24, winSum=409
8105 20:17:36.681183 TX Vref=34, minBit 0, minWin=24, winSum=406
8106 20:17:36.684195 TX Vref=36, minBit 0, minWin=24, winSum=391
8107 20:17:36.690930 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8108 20:17:36.691013
8109 20:17:36.694740 Final TX Range 0 Vref 26
8110 20:17:36.694823
8111 20:17:36.694887 ==
8112 20:17:36.697608 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 20:17:36.700642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 20:17:36.700725 ==
8115 20:17:36.700789
8116 20:17:36.704391
8117 20:17:36.704472 TX Vref Scan disable
8118 20:17:36.710625 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8119 20:17:36.710708 == TX Byte 0 ==
8120 20:17:36.714312 u2DelayCellOfst[0]=10 cells (3 PI)
8121 20:17:36.717594 u2DelayCellOfst[1]=13 cells (4 PI)
8122 20:17:36.720465 u2DelayCellOfst[2]=6 cells (2 PI)
8123 20:17:36.723945 u2DelayCellOfst[3]=6 cells (2 PI)
8124 20:17:36.727637 u2DelayCellOfst[4]=6 cells (2 PI)
8125 20:17:36.730537 u2DelayCellOfst[5]=0 cells (0 PI)
8126 20:17:36.733755 u2DelayCellOfst[6]=13 cells (4 PI)
8127 20:17:36.737571 u2DelayCellOfst[7]=13 cells (4 PI)
8128 20:17:36.740704 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8129 20:17:36.744418 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8130 20:17:36.747411 == TX Byte 1 ==
8131 20:17:36.750473 u2DelayCellOfst[8]=0 cells (0 PI)
8132 20:17:36.754416 u2DelayCellOfst[9]=3 cells (1 PI)
8133 20:17:36.754498 u2DelayCellOfst[10]=6 cells (2 PI)
8134 20:17:36.757309 u2DelayCellOfst[11]=3 cells (1 PI)
8135 20:17:36.760695 u2DelayCellOfst[12]=10 cells (3 PI)
8136 20:17:36.763952 u2DelayCellOfst[13]=13 cells (4 PI)
8137 20:17:36.767374 u2DelayCellOfst[14]=13 cells (4 PI)
8138 20:17:36.770518 u2DelayCellOfst[15]=10 cells (3 PI)
8139 20:17:36.773647 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8140 20:17:36.780604 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8141 20:17:36.780682 DramC Write-DBI on
8142 20:17:36.780748 ==
8143 20:17:36.784074 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 20:17:36.790411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 20:17:36.790499 ==
8146 20:17:36.790571
8147 20:17:36.790630
8148 20:17:36.790687 TX Vref Scan disable
8149 20:17:36.794719 == TX Byte 0 ==
8150 20:17:36.797906 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8151 20:17:36.801535 == TX Byte 1 ==
8152 20:17:36.804379 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8153 20:17:36.807878 DramC Write-DBI off
8154 20:17:36.807961
8155 20:17:36.808025 [DATLAT]
8156 20:17:36.808084 Freq=1600, CH0 RK1
8157 20:17:36.808142
8158 20:17:36.811005 DATLAT Default: 0xf
8159 20:17:36.811086 0, 0xFFFF, sum = 0
8160 20:17:36.814658 1, 0xFFFF, sum = 0
8161 20:17:36.817717 2, 0xFFFF, sum = 0
8162 20:17:36.817792 3, 0xFFFF, sum = 0
8163 20:17:36.820757 4, 0xFFFF, sum = 0
8164 20:17:36.820831 5, 0xFFFF, sum = 0
8165 20:17:36.824241 6, 0xFFFF, sum = 0
8166 20:17:36.824380 7, 0xFFFF, sum = 0
8167 20:17:36.827537 8, 0xFFFF, sum = 0
8168 20:17:36.827645 9, 0xFFFF, sum = 0
8169 20:17:36.831155 10, 0xFFFF, sum = 0
8170 20:17:36.831237 11, 0xFFFF, sum = 0
8171 20:17:36.834714 12, 0xFFFF, sum = 0
8172 20:17:36.834802 13, 0xFFFF, sum = 0
8173 20:17:36.837743 14, 0x0, sum = 1
8174 20:17:36.837825 15, 0x0, sum = 2
8175 20:17:36.841268 16, 0x0, sum = 3
8176 20:17:36.841347 17, 0x0, sum = 4
8177 20:17:36.844361 best_step = 15
8178 20:17:36.844435
8179 20:17:36.844496 ==
8180 20:17:36.847329 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 20:17:36.851010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 20:17:36.851092 ==
8183 20:17:36.851156 RX Vref Scan: 0
8184 20:17:36.854134
8185 20:17:36.854215 RX Vref 0 -> 0, step: 1
8186 20:17:36.854280
8187 20:17:36.857790 RX Delay 19 -> 252, step: 4
8188 20:17:36.861048 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8189 20:17:36.867739 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8190 20:17:36.870750 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8191 20:17:36.874745 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8192 20:17:36.877714 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8193 20:17:36.880894 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8194 20:17:36.887323 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8195 20:17:36.890747 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8196 20:17:36.894071 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8197 20:17:36.897327 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8198 20:17:36.900748 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8199 20:17:36.907289 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8200 20:17:36.910676 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8201 20:17:36.914200 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8202 20:17:36.917026 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8203 20:17:36.920764 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8204 20:17:36.923764 ==
8205 20:17:36.927520 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 20:17:36.930552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 20:17:36.930624 ==
8208 20:17:36.930684 DQS Delay:
8209 20:17:36.934100 DQS0 = 0, DQS1 = 0
8210 20:17:36.934176 DQM Delay:
8211 20:17:36.937379 DQM0 = 134, DQM1 = 127
8212 20:17:36.937462 DQ Delay:
8213 20:17:36.940432 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8214 20:17:36.943643 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8215 20:17:36.947343 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =120
8216 20:17:36.950311 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8217 20:17:36.950457
8218 20:17:36.950520
8219 20:17:36.950580
8220 20:17:36.953993 [DramC_TX_OE_Calibration] TA2
8221 20:17:36.957125 Original DQ_B0 (3 6) =30, OEN = 27
8222 20:17:36.960827 Original DQ_B1 (3 6) =30, OEN = 27
8223 20:17:36.963961 24, 0x0, End_B0=24 End_B1=24
8224 20:17:36.966981 25, 0x0, End_B0=25 End_B1=25
8225 20:17:36.967079 26, 0x0, End_B0=26 End_B1=26
8226 20:17:36.970747 27, 0x0, End_B0=27 End_B1=27
8227 20:17:36.973711 28, 0x0, End_B0=28 End_B1=28
8228 20:17:36.977090 29, 0x0, End_B0=29 End_B1=29
8229 20:17:36.980132 30, 0x0, End_B0=30 End_B1=30
8230 20:17:36.980218 31, 0x4141, End_B0=30 End_B1=30
8231 20:17:36.983978 Byte0 end_step=30 best_step=27
8232 20:17:36.986956 Byte1 end_step=30 best_step=27
8233 20:17:36.990257 Byte0 TX OE(2T, 0.5T) = (3, 3)
8234 20:17:36.993847 Byte1 TX OE(2T, 0.5T) = (3, 3)
8235 20:17:36.993931
8236 20:17:36.993997
8237 20:17:37.000694 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8238 20:17:37.003692 CH0 RK1: MR19=303, MR18=1E06
8239 20:17:37.010781 CH0_RK1: MR19=0x303, MR18=0x1E06, DQSOSC=394, MR23=63, INC=23, DEC=15
8240 20:17:37.013887 [RxdqsGatingPostProcess] freq 1600
8241 20:17:37.020379 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8242 20:17:37.020463 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 20:17:37.023470 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 20:17:37.026787 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 20:17:37.030135 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 20:17:37.033453 best DQS0 dly(2T, 0.5T) = (1, 1)
8247 20:17:37.036922 best DQS1 dly(2T, 0.5T) = (1, 1)
8248 20:17:37.040746 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8249 20:17:37.044084 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8250 20:17:37.047178 Pre-setting of DQS Precalculation
8251 20:17:37.050293 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8252 20:17:37.050377 ==
8253 20:17:37.053501 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 20:17:37.060215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 20:17:37.060310 ==
8256 20:17:37.063871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8257 20:17:37.070130 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8258 20:17:37.073263 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8259 20:17:37.080059 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8260 20:17:37.087389 [CA 0] Center 42 (13~72) winsize 60
8261 20:17:37.090944 [CA 1] Center 42 (13~72) winsize 60
8262 20:17:37.093958 [CA 2] Center 38 (9~68) winsize 60
8263 20:17:37.097431 [CA 3] Center 38 (10~67) winsize 58
8264 20:17:37.101215 [CA 4] Center 38 (9~68) winsize 60
8265 20:17:37.104141 [CA 5] Center 37 (8~67) winsize 60
8266 20:17:37.104250
8267 20:17:37.107368 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8268 20:17:37.107452
8269 20:17:37.110677 [CATrainingPosCal] consider 1 rank data
8270 20:17:37.113823 u2DelayCellTimex100 = 290/100 ps
8271 20:17:37.117657 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8272 20:17:37.124259 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8273 20:17:37.127357 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8274 20:17:37.130385 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8275 20:17:37.134146 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8276 20:17:37.137063 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8277 20:17:37.137145
8278 20:17:37.140782 CA PerBit enable=1, Macro0, CA PI delay=37
8279 20:17:37.140863
8280 20:17:37.144269 [CBTSetCACLKResult] CA Dly = 37
8281 20:17:37.147004 CS Dly: 11 (0~42)
8282 20:17:37.150651 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8283 20:17:37.153818 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8284 20:17:37.153900 ==
8285 20:17:37.156866 Dram Type= 6, Freq= 0, CH_1, rank 1
8286 20:17:37.163575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 20:17:37.163657 ==
8288 20:17:37.166923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 20:17:37.170611 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 20:17:37.177305 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 20:17:37.183373 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 20:17:37.190810 [CA 0] Center 42 (12~72) winsize 61
8293 20:17:37.194476 [CA 1] Center 42 (12~72) winsize 61
8294 20:17:37.197567 [CA 2] Center 38 (9~68) winsize 60
8295 20:17:37.200723 [CA 3] Center 38 (8~68) winsize 61
8296 20:17:37.204362 [CA 4] Center 38 (8~68) winsize 61
8297 20:17:37.207610 [CA 5] Center 37 (8~67) winsize 60
8298 20:17:37.207692
8299 20:17:37.211190 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8300 20:17:37.211273
8301 20:17:37.214197 [CATrainingPosCal] consider 2 rank data
8302 20:17:37.217398 u2DelayCellTimex100 = 290/100 ps
8303 20:17:37.220942 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8304 20:17:37.227603 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8305 20:17:37.230559 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8306 20:17:37.234183 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8307 20:17:37.237598 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8308 20:17:37.240515 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8309 20:17:37.240596
8310 20:17:37.243919 CA PerBit enable=1, Macro0, CA PI delay=37
8311 20:17:37.244000
8312 20:17:37.247718 [CBTSetCACLKResult] CA Dly = 37
8313 20:17:37.250911 CS Dly: 12 (0~45)
8314 20:17:37.253988 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 20:17:37.257116 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 20:17:37.257198
8317 20:17:37.260585 ----->DramcWriteLeveling(PI) begin...
8318 20:17:37.260668 ==
8319 20:17:37.263795 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 20:17:37.267200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 20:17:37.270639 ==
8322 20:17:37.274160 Write leveling (Byte 0): 28 => 28
8323 20:17:37.274241 Write leveling (Byte 1): 28 => 28
8324 20:17:37.277258 DramcWriteLeveling(PI) end<-----
8325 20:17:37.277338
8326 20:17:37.277402 ==
8327 20:17:37.280874 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 20:17:37.287152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 20:17:37.287233 ==
8330 20:17:37.290585 [Gating] SW mode calibration
8331 20:17:37.297126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8332 20:17:37.300723 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8333 20:17:37.307183 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 20:17:37.310352 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 20:17:37.314013 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8336 20:17:37.320848 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8337 20:17:37.323911 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 20:17:37.327527 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 20:17:37.330677 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 20:17:37.337100 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 20:17:37.340576 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 20:17:37.343903 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 20:17:37.350442 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8344 20:17:37.354071 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8345 20:17:37.357013 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 20:17:37.364125 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 20:17:37.367048 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 20:17:37.369996 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 20:17:37.377164 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 20:17:37.380509 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 20:17:37.383772 1 6 8 | B1->B0 | 2727 3636 | 0 1 | (1 1) (0 0)
8352 20:17:37.390554 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8353 20:17:37.393615 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 20:17:37.397189 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 20:17:37.403377 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 20:17:37.406859 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 20:17:37.410230 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 20:17:37.416984 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 20:17:37.420213 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 20:17:37.423322 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8361 20:17:37.429925 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8362 20:17:37.433688 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 20:17:37.436773 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 20:17:37.443577 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 20:17:37.447053 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 20:17:37.450172 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 20:17:37.453539 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 20:17:37.460542 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 20:17:37.463681 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 20:17:37.466762 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 20:17:37.473509 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 20:17:37.477029 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 20:17:37.479943 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 20:17:37.486723 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 20:17:37.489934 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 20:17:37.493092 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8377 20:17:37.499889 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 20:17:37.503701 Total UI for P1: 0, mck2ui 16
8379 20:17:37.506686 best dqsien dly found for B0: ( 1, 9, 10)
8380 20:17:37.506768 Total UI for P1: 0, mck2ui 16
8381 20:17:37.513423 best dqsien dly found for B1: ( 1, 9, 10)
8382 20:17:37.516561 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8383 20:17:37.519661 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8384 20:17:37.519759
8385 20:17:37.523226 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8386 20:17:37.526710 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8387 20:17:37.529975 [Gating] SW calibration Done
8388 20:17:37.530101 ==
8389 20:17:37.533068 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 20:17:37.536602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 20:17:37.536685 ==
8392 20:17:37.539663 RX Vref Scan: 0
8393 20:17:37.539744
8394 20:17:37.539809 RX Vref 0 -> 0, step: 1
8395 20:17:37.542880
8396 20:17:37.542961 RX Delay 0 -> 252, step: 8
8397 20:17:37.546204 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8398 20:17:37.552967 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8399 20:17:37.556441 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8400 20:17:37.560026 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8401 20:17:37.563137 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8402 20:17:37.566240 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8403 20:17:37.572861 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8404 20:17:37.576736 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8405 20:17:37.580104 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8406 20:17:37.582774 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8407 20:17:37.585968 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8408 20:17:37.592690 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8409 20:17:37.596185 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8410 20:17:37.599788 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8411 20:17:37.603035 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8412 20:17:37.606248 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8413 20:17:37.609839 ==
8414 20:17:37.612929 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 20:17:37.616038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 20:17:37.616120 ==
8417 20:17:37.616185 DQS Delay:
8418 20:17:37.619765 DQS0 = 0, DQS1 = 0
8419 20:17:37.619846 DQM Delay:
8420 20:17:37.622894 DQM0 = 137, DQM1 = 133
8421 20:17:37.622975 DQ Delay:
8422 20:17:37.625983 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8423 20:17:37.629761 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8424 20:17:37.632836 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8425 20:17:37.635830 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =147
8426 20:17:37.635912
8427 20:17:37.635975
8428 20:17:37.636034 ==
8429 20:17:37.639438 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 20:17:37.645785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 20:17:37.645867 ==
8432 20:17:37.645932
8433 20:17:37.645991
8434 20:17:37.646048 TX Vref Scan disable
8435 20:17:37.649610 == TX Byte 0 ==
8436 20:17:37.652857 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8437 20:17:37.659667 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8438 20:17:37.659749 == TX Byte 1 ==
8439 20:17:37.662756 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8440 20:17:37.669580 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8441 20:17:37.669662 ==
8442 20:17:37.672660 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 20:17:37.676279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 20:17:37.676384 ==
8445 20:17:37.689399
8446 20:17:37.692709 TX Vref early break, caculate TX vref
8447 20:17:37.696133 TX Vref=16, minBit 0, minWin=23, winSum=376
8448 20:17:37.699314 TX Vref=18, minBit 1, minWin=23, winSum=384
8449 20:17:37.702660 TX Vref=20, minBit 1, minWin=23, winSum=394
8450 20:17:37.705804 TX Vref=22, minBit 0, minWin=24, winSum=406
8451 20:17:37.709368 TX Vref=24, minBit 0, minWin=25, winSum=413
8452 20:17:37.715665 TX Vref=26, minBit 0, minWin=25, winSum=422
8453 20:17:37.719211 TX Vref=28, minBit 2, minWin=25, winSum=422
8454 20:17:37.722884 TX Vref=30, minBit 2, minWin=24, winSum=416
8455 20:17:37.725837 TX Vref=32, minBit 2, minWin=24, winSum=409
8456 20:17:37.729031 TX Vref=34, minBit 0, minWin=23, winSum=400
8457 20:17:37.732768 TX Vref=36, minBit 2, minWin=22, winSum=391
8458 20:17:37.738989 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8459 20:17:37.739072
8460 20:17:37.742737 Final TX Range 0 Vref 26
8461 20:17:37.742818
8462 20:17:37.742884 ==
8463 20:17:37.745761 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 20:17:37.749357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 20:17:37.749459 ==
8466 20:17:37.749527
8467 20:17:37.749617
8468 20:17:37.752412 TX Vref Scan disable
8469 20:17:37.759100 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8470 20:17:37.759181 == TX Byte 0 ==
8471 20:17:37.762627 u2DelayCellOfst[0]=16 cells (5 PI)
8472 20:17:37.765600 u2DelayCellOfst[1]=10 cells (3 PI)
8473 20:17:37.768823 u2DelayCellOfst[2]=0 cells (0 PI)
8474 20:17:37.772141 u2DelayCellOfst[3]=6 cells (2 PI)
8475 20:17:37.775905 u2DelayCellOfst[4]=6 cells (2 PI)
8476 20:17:37.779171 u2DelayCellOfst[5]=16 cells (5 PI)
8477 20:17:37.782450 u2DelayCellOfst[6]=16 cells (5 PI)
8478 20:17:37.785766 u2DelayCellOfst[7]=6 cells (2 PI)
8479 20:17:37.788970 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8480 20:17:37.792060 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8481 20:17:37.795699 == TX Byte 1 ==
8482 20:17:37.795782 u2DelayCellOfst[8]=0 cells (0 PI)
8483 20:17:37.798883 u2DelayCellOfst[9]=3 cells (1 PI)
8484 20:17:37.802032 u2DelayCellOfst[10]=13 cells (4 PI)
8485 20:17:37.805537 u2DelayCellOfst[11]=6 cells (2 PI)
8486 20:17:37.808816 u2DelayCellOfst[12]=13 cells (4 PI)
8487 20:17:37.812153 u2DelayCellOfst[13]=16 cells (5 PI)
8488 20:17:37.815305 u2DelayCellOfst[14]=16 cells (5 PI)
8489 20:17:37.818691 u2DelayCellOfst[15]=16 cells (5 PI)
8490 20:17:37.822285 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8491 20:17:37.828756 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8492 20:17:37.828846 DramC Write-DBI on
8493 20:17:37.828918 ==
8494 20:17:37.832252 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 20:17:37.835381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 20:17:37.839045 ==
8497 20:17:37.839126
8498 20:17:37.839191
8499 20:17:37.839250 TX Vref Scan disable
8500 20:17:37.842194 == TX Byte 0 ==
8501 20:17:37.846013 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8502 20:17:37.849008 == TX Byte 1 ==
8503 20:17:37.852122 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8504 20:17:37.855697 DramC Write-DBI off
8505 20:17:37.855779
8506 20:17:37.855843 [DATLAT]
8507 20:17:37.855902 Freq=1600, CH1 RK0
8508 20:17:37.855960
8509 20:17:37.858802 DATLAT Default: 0xf
8510 20:17:37.858947 0, 0xFFFF, sum = 0
8511 20:17:37.862273 1, 0xFFFF, sum = 0
8512 20:17:37.862356 2, 0xFFFF, sum = 0
8513 20:17:37.865424 3, 0xFFFF, sum = 0
8514 20:17:37.869036 4, 0xFFFF, sum = 0
8515 20:17:37.869118 5, 0xFFFF, sum = 0
8516 20:17:37.872065 6, 0xFFFF, sum = 0
8517 20:17:37.872148 7, 0xFFFF, sum = 0
8518 20:17:37.875683 8, 0xFFFF, sum = 0
8519 20:17:37.875766 9, 0xFFFF, sum = 0
8520 20:17:37.878641 10, 0xFFFF, sum = 0
8521 20:17:37.878724 11, 0xFFFF, sum = 0
8522 20:17:37.881970 12, 0xFFFF, sum = 0
8523 20:17:37.882053 13, 0xFFFF, sum = 0
8524 20:17:37.885917 14, 0x0, sum = 1
8525 20:17:37.885999 15, 0x0, sum = 2
8526 20:17:37.888866 16, 0x0, sum = 3
8527 20:17:37.888967 17, 0x0, sum = 4
8528 20:17:37.892324 best_step = 15
8529 20:17:37.892437
8530 20:17:37.892546 ==
8531 20:17:37.895730 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 20:17:37.899062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 20:17:37.899144 ==
8534 20:17:37.899209 RX Vref Scan: 1
8535 20:17:37.899281
8536 20:17:37.902084 Set Vref Range= 24 -> 127
8537 20:17:37.902166
8538 20:17:37.905661 RX Vref 24 -> 127, step: 1
8539 20:17:37.905753
8540 20:17:37.909287 RX Delay 27 -> 252, step: 4
8541 20:17:37.909382
8542 20:17:37.912415 Set Vref, RX VrefLevel [Byte0]: 24
8543 20:17:37.915447 [Byte1]: 24
8544 20:17:37.915529
8545 20:17:37.919059 Set Vref, RX VrefLevel [Byte0]: 25
8546 20:17:37.922159 [Byte1]: 25
8547 20:17:37.922242
8548 20:17:37.925727 Set Vref, RX VrefLevel [Byte0]: 26
8549 20:17:37.928721 [Byte1]: 26
8550 20:17:37.932196
8551 20:17:37.932299 Set Vref, RX VrefLevel [Byte0]: 27
8552 20:17:37.935703 [Byte1]: 27
8553 20:17:37.940099
8554 20:17:37.940213 Set Vref, RX VrefLevel [Byte0]: 28
8555 20:17:37.943239 [Byte1]: 28
8556 20:17:37.947577
8557 20:17:37.947658 Set Vref, RX VrefLevel [Byte0]: 29
8558 20:17:37.950547 [Byte1]: 29
8559 20:17:37.954813
8560 20:17:37.954894 Set Vref, RX VrefLevel [Byte0]: 30
8561 20:17:37.958473 [Byte1]: 30
8562 20:17:37.962700
8563 20:17:37.962780 Set Vref, RX VrefLevel [Byte0]: 31
8564 20:17:37.965723 [Byte1]: 31
8565 20:17:37.970000
8566 20:17:37.970081 Set Vref, RX VrefLevel [Byte0]: 32
8567 20:17:37.973133 [Byte1]: 32
8568 20:17:37.977374
8569 20:17:37.977455 Set Vref, RX VrefLevel [Byte0]: 33
8570 20:17:37.981127 [Byte1]: 33
8571 20:17:37.985198
8572 20:17:37.985282 Set Vref, RX VrefLevel [Byte0]: 34
8573 20:17:37.988241 [Byte1]: 34
8574 20:17:37.992907
8575 20:17:37.993004 Set Vref, RX VrefLevel [Byte0]: 35
8576 20:17:37.996068 [Byte1]: 35
8577 20:17:38.000135
8578 20:17:38.000243 Set Vref, RX VrefLevel [Byte0]: 36
8579 20:17:38.003639 [Byte1]: 36
8580 20:17:38.007560
8581 20:17:38.007641 Set Vref, RX VrefLevel [Byte0]: 37
8582 20:17:38.010918 [Byte1]: 37
8583 20:17:38.015203
8584 20:17:38.015285 Set Vref, RX VrefLevel [Byte0]: 38
8585 20:17:38.018873 [Byte1]: 38
8586 20:17:38.022528
8587 20:17:38.022609 Set Vref, RX VrefLevel [Byte0]: 39
8588 20:17:38.029592 [Byte1]: 39
8589 20:17:38.029674
8590 20:17:38.032733 Set Vref, RX VrefLevel [Byte0]: 40
8591 20:17:38.036079 [Byte1]: 40
8592 20:17:38.036160
8593 20:17:38.039118 Set Vref, RX VrefLevel [Byte0]: 41
8594 20:17:38.042798 [Byte1]: 41
8595 20:17:38.042879
8596 20:17:38.045903 Set Vref, RX VrefLevel [Byte0]: 42
8597 20:17:38.049348 [Byte1]: 42
8598 20:17:38.052801
8599 20:17:38.052882 Set Vref, RX VrefLevel [Byte0]: 43
8600 20:17:38.055900 [Byte1]: 43
8601 20:17:38.060614
8602 20:17:38.060696 Set Vref, RX VrefLevel [Byte0]: 44
8603 20:17:38.063559 [Byte1]: 44
8604 20:17:38.067887
8605 20:17:38.067970 Set Vref, RX VrefLevel [Byte0]: 45
8606 20:17:38.071456 [Byte1]: 45
8607 20:17:38.075711
8608 20:17:38.075808 Set Vref, RX VrefLevel [Byte0]: 46
8609 20:17:38.078823 [Byte1]: 46
8610 20:17:38.082896
8611 20:17:38.082978 Set Vref, RX VrefLevel [Byte0]: 47
8612 20:17:38.086116 [Byte1]: 47
8613 20:17:38.090402
8614 20:17:38.090484 Set Vref, RX VrefLevel [Byte0]: 48
8615 20:17:38.094163 [Byte1]: 48
8616 20:17:38.098306
8617 20:17:38.098387 Set Vref, RX VrefLevel [Byte0]: 49
8618 20:17:38.101276 [Byte1]: 49
8619 20:17:38.105736
8620 20:17:38.105855 Set Vref, RX VrefLevel [Byte0]: 50
8621 20:17:38.109004 [Byte1]: 50
8622 20:17:38.113095
8623 20:17:38.113177 Set Vref, RX VrefLevel [Byte0]: 51
8624 20:17:38.116673 [Byte1]: 51
8625 20:17:38.120514
8626 20:17:38.120595 Set Vref, RX VrefLevel [Byte0]: 52
8627 20:17:38.124243 [Byte1]: 52
8628 20:17:38.128579
8629 20:17:38.128660 Set Vref, RX VrefLevel [Byte0]: 53
8630 20:17:38.131631 [Byte1]: 53
8631 20:17:38.135913
8632 20:17:38.135995 Set Vref, RX VrefLevel [Byte0]: 54
8633 20:17:38.139284 [Byte1]: 54
8634 20:17:38.143706
8635 20:17:38.143787 Set Vref, RX VrefLevel [Byte0]: 55
8636 20:17:38.146443 [Byte1]: 55
8637 20:17:38.150667
8638 20:17:38.150756 Set Vref, RX VrefLevel [Byte0]: 56
8639 20:17:38.154353 [Byte1]: 56
8640 20:17:38.158111
8641 20:17:38.158192 Set Vref, RX VrefLevel [Byte0]: 57
8642 20:17:38.161425 [Byte1]: 57
8643 20:17:38.166142
8644 20:17:38.166223 Set Vref, RX VrefLevel [Byte0]: 58
8645 20:17:38.169309 [Byte1]: 58
8646 20:17:38.173364
8647 20:17:38.173445 Set Vref, RX VrefLevel [Byte0]: 59
8648 20:17:38.176901 [Byte1]: 59
8649 20:17:38.181095
8650 20:17:38.181205 Set Vref, RX VrefLevel [Byte0]: 60
8651 20:17:38.184070 [Byte1]: 60
8652 20:17:38.188393
8653 20:17:38.188504 Set Vref, RX VrefLevel [Byte0]: 61
8654 20:17:38.192000 [Byte1]: 61
8655 20:17:38.195770
8656 20:17:38.195851 Set Vref, RX VrefLevel [Byte0]: 62
8657 20:17:38.199586 [Byte1]: 62
8658 20:17:38.203657
8659 20:17:38.203737 Set Vref, RX VrefLevel [Byte0]: 63
8660 20:17:38.206668 [Byte1]: 63
8661 20:17:38.211223
8662 20:17:38.211305 Set Vref, RX VrefLevel [Byte0]: 64
8663 20:17:38.214621 [Byte1]: 64
8664 20:17:38.218416
8665 20:17:38.218497 Set Vref, RX VrefLevel [Byte0]: 65
8666 20:17:38.221809 [Byte1]: 65
8667 20:17:38.226440
8668 20:17:38.226521 Set Vref, RX VrefLevel [Byte0]: 66
8669 20:17:38.229199 [Byte1]: 66
8670 20:17:38.233433
8671 20:17:38.233514 Set Vref, RX VrefLevel [Byte0]: 67
8672 20:17:38.237219 [Byte1]: 67
8673 20:17:38.241436
8674 20:17:38.241516 Set Vref, RX VrefLevel [Byte0]: 68
8675 20:17:38.244559 [Byte1]: 68
8676 20:17:38.248668
8677 20:17:38.248749 Set Vref, RX VrefLevel [Byte0]: 69
8678 20:17:38.252049 [Byte1]: 69
8679 20:17:38.256162
8680 20:17:38.256269 Set Vref, RX VrefLevel [Byte0]: 70
8681 20:17:38.259560 [Byte1]: 70
8682 20:17:38.263810
8683 20:17:38.263891 Set Vref, RX VrefLevel [Byte0]: 71
8684 20:17:38.267510 [Byte1]: 71
8685 20:17:38.271255
8686 20:17:38.271337 Set Vref, RX VrefLevel [Byte0]: 72
8687 20:17:38.274923 [Byte1]: 72
8688 20:17:38.278871
8689 20:17:38.278952 Set Vref, RX VrefLevel [Byte0]: 73
8690 20:17:38.282077 [Byte1]: 73
8691 20:17:38.286441
8692 20:17:38.286522 Set Vref, RX VrefLevel [Byte0]: 74
8693 20:17:38.292685 [Byte1]: 74
8694 20:17:38.292766
8695 20:17:38.295869 Set Vref, RX VrefLevel [Byte0]: 75
8696 20:17:38.299277 [Byte1]: 75
8697 20:17:38.299358
8698 20:17:38.303020 Set Vref, RX VrefLevel [Byte0]: 76
8699 20:17:38.305996 [Byte1]: 76
8700 20:17:38.306117
8701 20:17:38.309595 Set Vref, RX VrefLevel [Byte0]: 77
8702 20:17:38.312707 [Byte1]: 77
8703 20:17:38.316329
8704 20:17:38.316410 Set Vref, RX VrefLevel [Byte0]: 78
8705 20:17:38.319755 [Byte1]: 78
8706 20:17:38.324241
8707 20:17:38.324346 Final RX Vref Byte 0 = 57 to rank0
8708 20:17:38.327567 Final RX Vref Byte 1 = 59 to rank0
8709 20:17:38.330776 Final RX Vref Byte 0 = 57 to rank1
8710 20:17:38.334253 Final RX Vref Byte 1 = 59 to rank1==
8711 20:17:38.337191 Dram Type= 6, Freq= 0, CH_1, rank 0
8712 20:17:38.344087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 20:17:38.344169 ==
8714 20:17:38.344234 DQS Delay:
8715 20:17:38.344320 DQS0 = 0, DQS1 = 0
8716 20:17:38.347653 DQM Delay:
8717 20:17:38.347734 DQM0 = 134, DQM1 = 131
8718 20:17:38.350657 DQ Delay:
8719 20:17:38.353879 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8720 20:17:38.357613 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8721 20:17:38.361056 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =122
8722 20:17:38.364054 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8723 20:17:38.364136
8724 20:17:38.364199
8725 20:17:38.364259
8726 20:17:38.367569 [DramC_TX_OE_Calibration] TA2
8727 20:17:38.370949 Original DQ_B0 (3 6) =30, OEN = 27
8728 20:17:38.373901 Original DQ_B1 (3 6) =30, OEN = 27
8729 20:17:38.377603 24, 0x0, End_B0=24 End_B1=24
8730 20:17:38.377686 25, 0x0, End_B0=25 End_B1=25
8731 20:17:38.380691 26, 0x0, End_B0=26 End_B1=26
8732 20:17:38.384308 27, 0x0, End_B0=27 End_B1=27
8733 20:17:38.387489 28, 0x0, End_B0=28 End_B1=28
8734 20:17:38.387572 29, 0x0, End_B0=29 End_B1=29
8735 20:17:38.390545 30, 0x0, End_B0=30 End_B1=30
8736 20:17:38.393647 31, 0x4141, End_B0=30 End_B1=30
8737 20:17:38.397267 Byte0 end_step=30 best_step=27
8738 20:17:38.400391 Byte1 end_step=30 best_step=27
8739 20:17:38.404122 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 20:17:38.404223 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 20:17:38.407013
8742 20:17:38.407110
8743 20:17:38.413625 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8744 20:17:38.417514 CH1 RK0: MR19=303, MR18=1624
8745 20:17:38.423594 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8746 20:17:38.423677
8747 20:17:38.426967 ----->DramcWriteLeveling(PI) begin...
8748 20:17:38.427050 ==
8749 20:17:38.430706 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 20:17:38.433884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 20:17:38.434000 ==
8752 20:17:38.437286 Write leveling (Byte 0): 25 => 25
8753 20:17:38.440437 Write leveling (Byte 1): 28 => 28
8754 20:17:38.443653 DramcWriteLeveling(PI) end<-----
8755 20:17:38.443734
8756 20:17:38.443798 ==
8757 20:17:38.447038 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 20:17:38.450485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 20:17:38.450567 ==
8760 20:17:38.454119 [Gating] SW mode calibration
8761 20:17:38.460454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8762 20:17:38.467336 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8763 20:17:38.470307 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 20:17:38.473595 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 20:17:38.480257 1 4 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8766 20:17:38.483684 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8767 20:17:38.486870 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 20:17:38.493429 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 20:17:38.497201 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 20:17:38.500178 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 20:17:38.507004 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 20:17:38.510225 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8773 20:17:38.513374 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8774 20:17:38.519970 1 5 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 1)
8775 20:17:38.523692 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 20:17:38.527146 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 20:17:38.533687 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 20:17:38.536782 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 20:17:38.540054 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 20:17:38.546742 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 20:17:38.550234 1 6 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8782 20:17:38.553497 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8783 20:17:38.559722 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 20:17:38.562999 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 20:17:38.566623 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 20:17:38.569992 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 20:17:38.576587 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 20:17:38.580175 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 20:17:38.583741 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8790 20:17:38.590305 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8791 20:17:38.593163 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8792 20:17:38.597024 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 20:17:38.603684 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 20:17:38.606676 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 20:17:38.609844 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 20:17:38.616721 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 20:17:38.619812 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 20:17:38.623475 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 20:17:38.630301 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 20:17:38.633227 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 20:17:38.637043 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 20:17:38.643318 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 20:17:38.646301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 20:17:38.649866 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8805 20:17:38.656512 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8806 20:17:38.659991 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8807 20:17:38.663371 Total UI for P1: 0, mck2ui 16
8808 20:17:38.666501 best dqsien dly found for B1: ( 1, 9, 6)
8809 20:17:38.669922 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 20:17:38.673161 Total UI for P1: 0, mck2ui 16
8811 20:17:38.676191 best dqsien dly found for B0: ( 1, 9, 12)
8812 20:17:38.679295 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8813 20:17:38.682817 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8814 20:17:38.682900
8815 20:17:38.686195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8816 20:17:38.692954 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8817 20:17:38.693036 [Gating] SW calibration Done
8818 20:17:38.696226 ==
8819 20:17:38.696346 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 20:17:38.702995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 20:17:38.703077 ==
8822 20:17:38.703142 RX Vref Scan: 0
8823 20:17:38.703203
8824 20:17:38.706156 RX Vref 0 -> 0, step: 1
8825 20:17:38.706238
8826 20:17:38.709793 RX Delay 0 -> 252, step: 8
8827 20:17:38.712987 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8828 20:17:38.715983 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8829 20:17:38.719730 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8830 20:17:38.726321 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8831 20:17:38.729505 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8832 20:17:38.732585 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8833 20:17:38.736175 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8834 20:17:38.739340 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8835 20:17:38.746053 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8836 20:17:38.749417 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8837 20:17:38.752470 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8838 20:17:38.756098 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8839 20:17:38.759092 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8840 20:17:38.765814 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8841 20:17:38.769363 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8842 20:17:38.772230 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8843 20:17:38.772350 ==
8844 20:17:38.776040 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 20:17:38.778970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 20:17:38.779053 ==
8847 20:17:38.782413 DQS Delay:
8848 20:17:38.782554 DQS0 = 0, DQS1 = 0
8849 20:17:38.785595 DQM Delay:
8850 20:17:38.785677 DQM0 = 136, DQM1 = 133
8851 20:17:38.789388 DQ Delay:
8852 20:17:38.792305 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8853 20:17:38.795823 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8854 20:17:38.799173 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8855 20:17:38.802454 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8856 20:17:38.802582
8857 20:17:38.802706
8858 20:17:38.802823 ==
8859 20:17:38.805737 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 20:17:38.809046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 20:17:38.809128 ==
8862 20:17:38.809193
8863 20:17:38.809253
8864 20:17:38.812576 TX Vref Scan disable
8865 20:17:38.815839 == TX Byte 0 ==
8866 20:17:38.819072 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8867 20:17:38.822284 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8868 20:17:38.825563 == TX Byte 1 ==
8869 20:17:38.829379 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8870 20:17:38.832525 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8871 20:17:38.832607 ==
8872 20:17:38.835564 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 20:17:38.842281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 20:17:38.842370 ==
8875 20:17:38.853360
8876 20:17:38.856789 TX Vref early break, caculate TX vref
8877 20:17:38.860084 TX Vref=16, minBit 0, minWin=23, winSum=382
8878 20:17:38.863103 TX Vref=18, minBit 2, minWin=23, winSum=395
8879 20:17:38.866768 TX Vref=20, minBit 0, minWin=24, winSum=401
8880 20:17:38.869811 TX Vref=22, minBit 0, minWin=24, winSum=410
8881 20:17:38.873429 TX Vref=24, minBit 1, minWin=24, winSum=417
8882 20:17:38.880059 TX Vref=26, minBit 0, minWin=25, winSum=426
8883 20:17:38.882976 TX Vref=28, minBit 0, minWin=26, winSum=426
8884 20:17:38.886700 TX Vref=30, minBit 0, minWin=25, winSum=421
8885 20:17:38.890058 TX Vref=32, minBit 0, minWin=25, winSum=414
8886 20:17:38.893467 TX Vref=34, minBit 0, minWin=24, winSum=402
8887 20:17:38.899571 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8888 20:17:38.899654
8889 20:17:38.903196 Final TX Range 0 Vref 28
8890 20:17:38.903278
8891 20:17:38.903343 ==
8892 20:17:38.906573 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 20:17:38.909931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 20:17:38.910013 ==
8895 20:17:38.910077
8896 20:17:38.910138
8897 20:17:38.913376 TX Vref Scan disable
8898 20:17:38.919724 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8899 20:17:38.919805 == TX Byte 0 ==
8900 20:17:38.923195 u2DelayCellOfst[0]=16 cells (5 PI)
8901 20:17:38.926185 u2DelayCellOfst[1]=10 cells (3 PI)
8902 20:17:38.929936 u2DelayCellOfst[2]=0 cells (0 PI)
8903 20:17:38.932984 u2DelayCellOfst[3]=6 cells (2 PI)
8904 20:17:38.936220 u2DelayCellOfst[4]=10 cells (3 PI)
8905 20:17:38.939353 u2DelayCellOfst[5]=16 cells (5 PI)
8906 20:17:38.942979 u2DelayCellOfst[6]=16 cells (5 PI)
8907 20:17:38.945908 u2DelayCellOfst[7]=6 cells (2 PI)
8908 20:17:38.949640 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8909 20:17:38.952687 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8910 20:17:38.956422 == TX Byte 1 ==
8911 20:17:38.956503 u2DelayCellOfst[8]=0 cells (0 PI)
8912 20:17:38.959848 u2DelayCellOfst[9]=3 cells (1 PI)
8913 20:17:38.962917 u2DelayCellOfst[10]=10 cells (3 PI)
8914 20:17:38.966220 u2DelayCellOfst[11]=3 cells (1 PI)
8915 20:17:38.969575 u2DelayCellOfst[12]=13 cells (4 PI)
8916 20:17:38.972588 u2DelayCellOfst[13]=13 cells (4 PI)
8917 20:17:38.976326 u2DelayCellOfst[14]=16 cells (5 PI)
8918 20:17:38.979679 u2DelayCellOfst[15]=16 cells (5 PI)
8919 20:17:38.982669 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8920 20:17:38.989463 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8921 20:17:38.989545 DramC Write-DBI on
8922 20:17:38.989611 ==
8923 20:17:38.992453 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 20:17:38.995741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 20:17:38.999603 ==
8926 20:17:38.999685
8927 20:17:38.999750
8928 20:17:38.999809 TX Vref Scan disable
8929 20:17:39.002693 == TX Byte 0 ==
8930 20:17:39.006540 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8931 20:17:39.009581 == TX Byte 1 ==
8932 20:17:39.012727 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8933 20:17:39.016089 DramC Write-DBI off
8934 20:17:39.016170
8935 20:17:39.016234 [DATLAT]
8936 20:17:39.016322 Freq=1600, CH1 RK1
8937 20:17:39.016429
8938 20:17:39.019146 DATLAT Default: 0xf
8939 20:17:39.019227 0, 0xFFFF, sum = 0
8940 20:17:39.022700 1, 0xFFFF, sum = 0
8941 20:17:39.026230 2, 0xFFFF, sum = 0
8942 20:17:39.026325 3, 0xFFFF, sum = 0
8943 20:17:39.029368 4, 0xFFFF, sum = 0
8944 20:17:39.029451 5, 0xFFFF, sum = 0
8945 20:17:39.032854 6, 0xFFFF, sum = 0
8946 20:17:39.032937 7, 0xFFFF, sum = 0
8947 20:17:39.035900 8, 0xFFFF, sum = 0
8948 20:17:39.035983 9, 0xFFFF, sum = 0
8949 20:17:39.039576 10, 0xFFFF, sum = 0
8950 20:17:39.039659 11, 0xFFFF, sum = 0
8951 20:17:39.042430 12, 0xFFFF, sum = 0
8952 20:17:39.042513 13, 0xFFFF, sum = 0
8953 20:17:39.045735 14, 0x0, sum = 1
8954 20:17:39.045818 15, 0x0, sum = 2
8955 20:17:39.049137 16, 0x0, sum = 3
8956 20:17:39.049220 17, 0x0, sum = 4
8957 20:17:39.052685 best_step = 15
8958 20:17:39.052783
8959 20:17:39.052877 ==
8960 20:17:39.056060 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 20:17:39.059070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 20:17:39.059153 ==
8963 20:17:39.062773 RX Vref Scan: 0
8964 20:17:39.062855
8965 20:17:39.062919 RX Vref 0 -> 0, step: 1
8966 20:17:39.062979
8967 20:17:39.065782 RX Delay 19 -> 252, step: 4
8968 20:17:39.069514 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8969 20:17:39.075664 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8970 20:17:39.078984 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8971 20:17:39.082356 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8972 20:17:39.086118 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8973 20:17:39.089247 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8974 20:17:39.092258 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8975 20:17:39.099055 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8976 20:17:39.102130 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8977 20:17:39.105574 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8978 20:17:39.108940 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8979 20:17:39.112780 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8980 20:17:39.118799 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8981 20:17:39.122226 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8982 20:17:39.125675 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8983 20:17:39.129221 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8984 20:17:39.129304 ==
8985 20:17:39.132261 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 20:17:39.139262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 20:17:39.139345 ==
8988 20:17:39.139410 DQS Delay:
8989 20:17:39.142349 DQS0 = 0, DQS1 = 0
8990 20:17:39.142430 DQM Delay:
8991 20:17:39.142495 DQM0 = 134, DQM1 = 130
8992 20:17:39.145961 DQ Delay:
8993 20:17:39.149507 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8994 20:17:39.152622 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8995 20:17:39.155553 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8996 20:17:39.158801 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8997 20:17:39.158883
8998 20:17:39.158947
8999 20:17:39.159006
9000 20:17:39.162437 [DramC_TX_OE_Calibration] TA2
9001 20:17:39.165968 Original DQ_B0 (3 6) =30, OEN = 27
9002 20:17:39.169366 Original DQ_B1 (3 6) =30, OEN = 27
9003 20:17:39.172502 24, 0x0, End_B0=24 End_B1=24
9004 20:17:39.172584 25, 0x0, End_B0=25 End_B1=25
9005 20:17:39.175614 26, 0x0, End_B0=26 End_B1=26
9006 20:17:39.179203 27, 0x0, End_B0=27 End_B1=27
9007 20:17:39.182578 28, 0x0, End_B0=28 End_B1=28
9008 20:17:39.185790 29, 0x0, End_B0=29 End_B1=29
9009 20:17:39.185873 30, 0x0, End_B0=30 End_B1=30
9010 20:17:39.189052 31, 0x4141, End_B0=30 End_B1=30
9011 20:17:39.191994 Byte0 end_step=30 best_step=27
9012 20:17:39.195535 Byte1 end_step=30 best_step=27
9013 20:17:39.198680 Byte0 TX OE(2T, 0.5T) = (3, 3)
9014 20:17:39.202289 Byte1 TX OE(2T, 0.5T) = (3, 3)
9015 20:17:39.202371
9016 20:17:39.202436
9017 20:17:39.208566 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9018 20:17:39.212257 CH1 RK1: MR19=303, MR18=2207
9019 20:17:39.218436 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9020 20:17:39.221933 [RxdqsGatingPostProcess] freq 1600
9021 20:17:39.225333 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9022 20:17:39.228869 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 20:17:39.231899 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 20:17:39.235489 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 20:17:39.238599 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 20:17:39.241758 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 20:17:39.245330 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 20:17:39.248248 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 20:17:39.251668 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 20:17:39.255290 Pre-setting of DQS Precalculation
9031 20:17:39.258415 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9032 20:17:39.265399 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9033 20:17:39.275342 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9034 20:17:39.275424
9035 20:17:39.275488
9036 20:17:39.278289 [Calibration Summary] 3200 Mbps
9037 20:17:39.278371 CH 0, Rank 0
9038 20:17:39.281438 SW Impedance : PASS
9039 20:17:39.281520 DUTY Scan : NO K
9040 20:17:39.285392 ZQ Calibration : PASS
9041 20:17:39.285474 Jitter Meter : NO K
9042 20:17:39.288482 CBT Training : PASS
9043 20:17:39.291945 Write leveling : PASS
9044 20:17:39.292027 RX DQS gating : PASS
9045 20:17:39.294756 RX DQ/DQS(RDDQC) : PASS
9046 20:17:39.298137 TX DQ/DQS : PASS
9047 20:17:39.298220 RX DATLAT : PASS
9048 20:17:39.301567 RX DQ/DQS(Engine): PASS
9049 20:17:39.305073 TX OE : PASS
9050 20:17:39.305155 All Pass.
9051 20:17:39.305220
9052 20:17:39.305280 CH 0, Rank 1
9053 20:17:39.308139 SW Impedance : PASS
9054 20:17:39.311278 DUTY Scan : NO K
9055 20:17:39.311359 ZQ Calibration : PASS
9056 20:17:39.315034 Jitter Meter : NO K
9057 20:17:39.318033 CBT Training : PASS
9058 20:17:39.318115 Write leveling : PASS
9059 20:17:39.321441 RX DQS gating : PASS
9060 20:17:39.324952 RX DQ/DQS(RDDQC) : PASS
9061 20:17:39.325034 TX DQ/DQS : PASS
9062 20:17:39.327799 RX DATLAT : PASS
9063 20:17:39.331274 RX DQ/DQS(Engine): PASS
9064 20:17:39.331355 TX OE : PASS
9065 20:17:39.331420 All Pass.
9066 20:17:39.334882
9067 20:17:39.334962 CH 1, Rank 0
9068 20:17:39.338203 SW Impedance : PASS
9069 20:17:39.338285 DUTY Scan : NO K
9070 20:17:39.341261 ZQ Calibration : PASS
9071 20:17:39.344956 Jitter Meter : NO K
9072 20:17:39.345037 CBT Training : PASS
9073 20:17:39.347911 Write leveling : PASS
9074 20:17:39.347993 RX DQS gating : PASS
9075 20:17:39.351541 RX DQ/DQS(RDDQC) : PASS
9076 20:17:39.354574 TX DQ/DQS : PASS
9077 20:17:39.354656 RX DATLAT : PASS
9078 20:17:39.357626 RX DQ/DQS(Engine): PASS
9079 20:17:39.361184 TX OE : PASS
9080 20:17:39.361266 All Pass.
9081 20:17:39.361331
9082 20:17:39.361391 CH 1, Rank 1
9083 20:17:39.364509 SW Impedance : PASS
9084 20:17:39.367471 DUTY Scan : NO K
9085 20:17:39.367551 ZQ Calibration : PASS
9086 20:17:39.371123 Jitter Meter : NO K
9087 20:17:39.374305 CBT Training : PASS
9088 20:17:39.374387 Write leveling : PASS
9089 20:17:39.377385 RX DQS gating : PASS
9090 20:17:39.380966 RX DQ/DQS(RDDQC) : PASS
9091 20:17:39.381047 TX DQ/DQS : PASS
9092 20:17:39.384085 RX DATLAT : PASS
9093 20:17:39.387557 RX DQ/DQS(Engine): PASS
9094 20:17:39.387638 TX OE : PASS
9095 20:17:39.390928 All Pass.
9096 20:17:39.391039
9097 20:17:39.391107 DramC Write-DBI on
9098 20:17:39.394322 PER_BANK_REFRESH: Hybrid Mode
9099 20:17:39.394429 TX_TRACKING: ON
9100 20:17:39.404125 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9101 20:17:39.410647 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9102 20:17:39.420725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 20:17:39.424399 [FAST_K] Save calibration result to emmc
9104 20:17:39.427188 sync common calibartion params.
9105 20:17:39.427269 sync cbt_mode0:1, 1:1
9106 20:17:39.430759 dram_init: ddr_geometry: 2
9107 20:17:39.434173 dram_init: ddr_geometry: 2
9108 20:17:39.434254 dram_init: ddr_geometry: 2
9109 20:17:39.437614 0:dram_rank_size:100000000
9110 20:17:39.440718 1:dram_rank_size:100000000
9111 20:17:39.444001 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9112 20:17:39.447281 DFS_SHUFFLE_HW_MODE: ON
9113 20:17:39.450943 dramc_set_vcore_voltage set vcore to 725000
9114 20:17:39.453958 Read voltage for 1600, 0
9115 20:17:39.454039 Vio18 = 0
9116 20:17:39.457672 Vcore = 725000
9117 20:17:39.457754 Vdram = 0
9118 20:17:39.457819 Vddq = 0
9119 20:17:39.460668 Vmddr = 0
9120 20:17:39.460749 switch to 3200 Mbps bootup
9121 20:17:39.463773 [DramcRunTimeConfig]
9122 20:17:39.463854 PHYPLL
9123 20:17:39.467489 DPM_CONTROL_AFTERK: ON
9124 20:17:39.467570 PER_BANK_REFRESH: ON
9125 20:17:39.470447 REFRESH_OVERHEAD_REDUCTION: ON
9126 20:17:39.473868 CMD_PICG_NEW_MODE: OFF
9127 20:17:39.473949 XRTWTW_NEW_MODE: ON
9128 20:17:39.477118 XRTRTR_NEW_MODE: ON
9129 20:17:39.477199 TX_TRACKING: ON
9130 20:17:39.480831 RDSEL_TRACKING: OFF
9131 20:17:39.483905 DQS Precalculation for DVFS: ON
9132 20:17:39.483986 RX_TRACKING: OFF
9133 20:17:39.487593 HW_GATING DBG: ON
9134 20:17:39.487674 ZQCS_ENABLE_LP4: ON
9135 20:17:39.490637 RX_PICG_NEW_MODE: ON
9136 20:17:39.490718 TX_PICG_NEW_MODE: ON
9137 20:17:39.493793 ENABLE_RX_DCM_DPHY: ON
9138 20:17:39.497588 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9139 20:17:39.501075 DUMMY_READ_FOR_TRACKING: OFF
9140 20:17:39.501159 !!! SPM_CONTROL_AFTERK: OFF
9141 20:17:39.504025 !!! SPM could not control APHY
9142 20:17:39.507515 IMPEDANCE_TRACKING: ON
9143 20:17:39.507596 TEMP_SENSOR: ON
9144 20:17:39.510647 HW_SAVE_FOR_SR: OFF
9145 20:17:39.513823 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9146 20:17:39.517039 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9147 20:17:39.517144 Read ODT Tracking: ON
9148 20:17:39.520422 Refresh Rate DeBounce: ON
9149 20:17:39.523786 DFS_NO_QUEUE_FLUSH: ON
9150 20:17:39.527228 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9151 20:17:39.527309 ENABLE_DFS_RUNTIME_MRW: OFF
9152 20:17:39.530689 DDR_RESERVE_NEW_MODE: ON
9153 20:17:39.533800 MR_CBT_SWITCH_FREQ: ON
9154 20:17:39.533881 =========================
9155 20:17:39.553970 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9156 20:17:39.557430 dram_init: ddr_geometry: 2
9157 20:17:39.575714 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9158 20:17:39.578833 dram_init: dram init end (result: 0)
9159 20:17:39.585379 DRAM-K: Full calibration passed in 24499 msecs
9160 20:17:39.588591 MRC: failed to locate region type 0.
9161 20:17:39.588673 DRAM rank0 size:0x100000000,
9162 20:17:39.592195 DRAM rank1 size=0x100000000
9163 20:17:39.601863 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9164 20:17:39.608702 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9165 20:17:39.615057 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9166 20:17:39.622021 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9167 20:17:39.625086 DRAM rank0 size:0x100000000,
9168 20:17:39.628641 DRAM rank1 size=0x100000000
9169 20:17:39.628723 CBMEM:
9170 20:17:39.631783 IMD: root @ 0xfffff000 254 entries.
9171 20:17:39.635380 IMD: root @ 0xffffec00 62 entries.
9172 20:17:39.638394 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9173 20:17:39.641728 WARNING: RO_VPD is uninitialized or empty.
9174 20:17:39.648247 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9175 20:17:39.655526 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9176 20:17:39.668428 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9177 20:17:39.680081 BS: romstage times (exec / console): total (unknown) / 24023 ms
9178 20:17:39.680164
9179 20:17:39.680228
9180 20:17:39.689338 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9181 20:17:39.692919 ARM64: Exception handlers installed.
9182 20:17:39.695916 ARM64: Testing exception
9183 20:17:39.699388 ARM64: Done test exception
9184 20:17:39.699489 Enumerating buses...
9185 20:17:39.702813 Show all devs... Before device enumeration.
9186 20:17:39.706122 Root Device: enabled 1
9187 20:17:39.709383 CPU_CLUSTER: 0: enabled 1
9188 20:17:39.709465 CPU: 00: enabled 1
9189 20:17:39.713048 Compare with tree...
9190 20:17:39.713129 Root Device: enabled 1
9191 20:17:39.716214 CPU_CLUSTER: 0: enabled 1
9192 20:17:39.719306 CPU: 00: enabled 1
9193 20:17:39.719387 Root Device scanning...
9194 20:17:39.722899 scan_static_bus for Root Device
9195 20:17:39.726443 CPU_CLUSTER: 0 enabled
9196 20:17:39.729198 scan_static_bus for Root Device done
9197 20:17:39.732596 scan_bus: bus Root Device finished in 8 msecs
9198 20:17:39.732677 done
9199 20:17:39.739390 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9200 20:17:39.742837 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9201 20:17:39.749247 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9202 20:17:39.752860 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9203 20:17:39.755928 Allocating resources...
9204 20:17:39.758972 Reading resources...
9205 20:17:39.762757 Root Device read_resources bus 0 link: 0
9206 20:17:39.762864 DRAM rank0 size:0x100000000,
9207 20:17:39.765706 DRAM rank1 size=0x100000000
9208 20:17:39.769145 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9209 20:17:39.772424 CPU: 00 missing read_resources
9210 20:17:39.775742 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9211 20:17:39.782685 Root Device read_resources bus 0 link: 0 done
9212 20:17:39.782767 Done reading resources.
9213 20:17:39.789426 Show resources in subtree (Root Device)...After reading.
9214 20:17:39.792616 Root Device child on link 0 CPU_CLUSTER: 0
9215 20:17:39.796226 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 20:17:39.806051 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 20:17:39.806134 CPU: 00
9218 20:17:39.809092 Root Device assign_resources, bus 0 link: 0
9219 20:17:39.812630 CPU_CLUSTER: 0 missing set_resources
9220 20:17:39.819106 Root Device assign_resources, bus 0 link: 0 done
9221 20:17:39.819188 Done setting resources.
9222 20:17:39.825564 Show resources in subtree (Root Device)...After assigning values.
9223 20:17:39.829089 Root Device child on link 0 CPU_CLUSTER: 0
9224 20:17:39.832144 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 20:17:39.842927 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 20:17:39.843009 CPU: 00
9227 20:17:39.845789 Done allocating resources.
9228 20:17:39.849202 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9229 20:17:39.852172 Enabling resources...
9230 20:17:39.852278 done.
9231 20:17:39.859139 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9232 20:17:39.859221 Initializing devices...
9233 20:17:39.862681 Root Device init
9234 20:17:39.862763 init hardware done!
9235 20:17:39.865521 0x00000018: ctrlr->caps
9236 20:17:39.869284 52.000 MHz: ctrlr->f_max
9237 20:17:39.869368 0.400 MHz: ctrlr->f_min
9238 20:17:39.872280 0x40ff8080: ctrlr->voltages
9239 20:17:39.872403 sclk: 390625
9240 20:17:39.875409 Bus Width = 1
9241 20:17:39.875490 sclk: 390625
9242 20:17:39.879098 Bus Width = 1
9243 20:17:39.879179 Early init status = 3
9244 20:17:39.885520 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9245 20:17:39.888814 in-header: 03 fc 00 00 01 00 00 00
9246 20:17:39.888896 in-data: 00
9247 20:17:39.895450 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9248 20:17:39.898511 in-header: 03 fd 00 00 00 00 00 00
9249 20:17:39.902210 in-data:
9250 20:17:39.905224 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9251 20:17:39.908948 in-header: 03 fc 00 00 01 00 00 00
9252 20:17:39.911966 in-data: 00
9253 20:17:39.915553 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9254 20:17:39.919806 in-header: 03 fd 00 00 00 00 00 00
9255 20:17:39.922853 in-data:
9256 20:17:39.926398 [SSUSB] Setting up USB HOST controller...
9257 20:17:39.929894 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9258 20:17:39.933235 [SSUSB] phy power-on done.
9259 20:17:39.936380 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9260 20:17:39.943051 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9261 20:17:39.946171 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9262 20:17:39.953034 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9263 20:17:39.959355 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9264 20:17:39.966390 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9265 20:17:39.973080 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9266 20:17:39.979436 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9267 20:17:39.982631 SPM: binary array size = 0x9dc
9268 20:17:39.986226 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9269 20:17:39.992789 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9270 20:17:39.999333 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9271 20:17:40.002713 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9272 20:17:40.009306 configure_display: Starting display init
9273 20:17:40.042803 anx7625_power_on_init: Init interface.
9274 20:17:40.046091 anx7625_disable_pd_protocol: Disabled PD feature.
9275 20:17:40.049371 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9276 20:17:40.077501 anx7625_start_dp_work: Secure OCM version=00
9277 20:17:40.080440 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9278 20:17:40.095376 sp_tx_get_edid_block: EDID Block = 1
9279 20:17:40.198038 Extracted contents:
9280 20:17:40.201246 header: 00 ff ff ff ff ff ff 00
9281 20:17:40.204423 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9282 20:17:40.207867 version: 01 04
9283 20:17:40.211089 basic params: 95 1f 11 78 0a
9284 20:17:40.214600 chroma info: 76 90 94 55 54 90 27 21 50 54
9285 20:17:40.218144 established: 00 00 00
9286 20:17:40.224435 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9287 20:17:40.227632 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9288 20:17:40.234531 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9289 20:17:40.241157 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9290 20:17:40.248022 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9291 20:17:40.251186 extensions: 00
9292 20:17:40.251268 checksum: fb
9293 20:17:40.251333
9294 20:17:40.254253 Manufacturer: IVO Model 57d Serial Number 0
9295 20:17:40.258075 Made week 0 of 2020
9296 20:17:40.258158 EDID version: 1.4
9297 20:17:40.261064 Digital display
9298 20:17:40.264185 6 bits per primary color channel
9299 20:17:40.264318 DisplayPort interface
9300 20:17:40.267702 Maximum image size: 31 cm x 17 cm
9301 20:17:40.270981 Gamma: 220%
9302 20:17:40.271062 Check DPMS levels
9303 20:17:40.274404 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9304 20:17:40.277471 First detailed timing is preferred timing
9305 20:17:40.281163 Established timings supported:
9306 20:17:40.284080 Standard timings supported:
9307 20:17:40.287480 Detailed timings
9308 20:17:40.290502 Hex of detail: 383680a07038204018303c0035ae10000019
9309 20:17:40.294012 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9310 20:17:40.300704 0780 0798 07c8 0820 hborder 0
9311 20:17:40.303972 0438 043b 0447 0458 vborder 0
9312 20:17:40.307579 -hsync -vsync
9313 20:17:40.307660 Did detailed timing
9314 20:17:40.314400 Hex of detail: 000000000000000000000000000000000000
9315 20:17:40.314480 Manufacturer-specified data, tag 0
9316 20:17:40.320673 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9317 20:17:40.323769 ASCII string: InfoVision
9318 20:17:40.327670 Hex of detail: 000000fe00523134304e574635205248200a
9319 20:17:40.331123 ASCII string: R140NWF5 RH
9320 20:17:40.331196 Checksum
9321 20:17:40.333993 Checksum: 0xfb (valid)
9322 20:17:40.337079 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9323 20:17:40.340607 DSI data_rate: 832800000 bps
9324 20:17:40.347581 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9325 20:17:40.350561 anx7625_parse_edid: pixelclock(138800).
9326 20:17:40.354227 hactive(1920), hsync(48), hfp(24), hbp(88)
9327 20:17:40.357375 vactive(1080), vsync(12), vfp(3), vbp(17)
9328 20:17:40.360555 anx7625_dsi_config: config dsi.
9329 20:17:40.367189 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9330 20:17:40.380009 anx7625_dsi_config: success to config DSI
9331 20:17:40.383310 anx7625_dp_start: MIPI phy setup OK.
9332 20:17:40.386510 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9333 20:17:40.390164 mtk_ddp_mode_set invalid vrefresh 60
9334 20:17:40.393578 main_disp_path_setup
9335 20:17:40.393697 ovl_layer_smi_id_en
9336 20:17:40.396992 ovl_layer_smi_id_en
9337 20:17:40.397115 ccorr_config
9338 20:17:40.397224 aal_config
9339 20:17:40.399813 gamma_config
9340 20:17:40.399930 postmask_config
9341 20:17:40.403569 dither_config
9342 20:17:40.406661 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9343 20:17:40.413618 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9344 20:17:40.416508 Root Device init finished in 551 msecs
9345 20:17:40.419597 CPU_CLUSTER: 0 init
9346 20:17:40.426678 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9347 20:17:40.430015 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9348 20:17:40.433225 APU_MBOX 0x190000b0 = 0x10001
9349 20:17:40.436270 APU_MBOX 0x190001b0 = 0x10001
9350 20:17:40.439673 APU_MBOX 0x190005b0 = 0x10001
9351 20:17:40.443217 APU_MBOX 0x190006b0 = 0x10001
9352 20:17:40.446331 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9353 20:17:40.458891 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9354 20:17:40.471650 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9355 20:17:40.477894 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9356 20:17:40.489378 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9357 20:17:40.499090 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9358 20:17:40.501971 CPU_CLUSTER: 0 init finished in 81 msecs
9359 20:17:40.505350 Devices initialized
9360 20:17:40.508838 Show all devs... After init.
9361 20:17:40.508918 Root Device: enabled 1
9362 20:17:40.511916 CPU_CLUSTER: 0: enabled 1
9363 20:17:40.515524 CPU: 00: enabled 1
9364 20:17:40.518343 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9365 20:17:40.521771 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9366 20:17:40.525577 ELOG: NV offset 0x57f000 size 0x1000
9367 20:17:40.531627 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9368 20:17:40.538407 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9369 20:17:40.541700 ELOG: Event(17) added with size 13 at 2024-03-03 20:14:51 UTC
9370 20:17:40.548118 out: cmd=0x121: 03 db 21 01 00 00 00 00
9371 20:17:40.551702 in-header: 03 b2 00 00 2c 00 00 00
9372 20:17:40.561319 in-data: ad 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 20:17:40.568246 ELOG: Event(A1) added with size 10 at 2024-03-03 20:14:51 UTC
9374 20:17:40.575118 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9375 20:17:40.581844 ELOG: Event(A0) added with size 9 at 2024-03-03 20:14:51 UTC
9376 20:17:40.585043 elog_add_boot_reason: Logged dev mode boot
9377 20:17:40.591254 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9378 20:17:40.591378 Finalize devices...
9379 20:17:40.595001 Devices finalized
9380 20:17:40.598050 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9381 20:17:40.601822 Writing coreboot table at 0xffe64000
9382 20:17:40.604945 0. 000000000010a000-0000000000113fff: RAMSTAGE
9383 20:17:40.607791 1. 0000000040000000-00000000400fffff: RAM
9384 20:17:40.614503 2. 0000000040100000-000000004032afff: RAMSTAGE
9385 20:17:40.618170 3. 000000004032b000-00000000545fffff: RAM
9386 20:17:40.621155 4. 0000000054600000-000000005465ffff: BL31
9387 20:17:40.624932 5. 0000000054660000-00000000ffe63fff: RAM
9388 20:17:40.631592 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9389 20:17:40.634791 7. 0000000100000000-000000023fffffff: RAM
9390 20:17:40.638228 Passing 5 GPIOs to payload:
9391 20:17:40.641320 NAME | PORT | POLARITY | VALUE
9392 20:17:40.645072 EC in RW | 0x000000aa | low | undefined
9393 20:17:40.651251 EC interrupt | 0x00000005 | low | undefined
9394 20:17:40.654795 TPM interrupt | 0x000000ab | high | undefined
9395 20:17:40.660826 SD card detect | 0x00000011 | high | undefined
9396 20:17:40.664576 speaker enable | 0x00000093 | high | undefined
9397 20:17:40.667875 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9398 20:17:40.670972 in-header: 03 f9 00 00 02 00 00 00
9399 20:17:40.674265 in-data: 02 00
9400 20:17:40.674347 ADC[4]: Raw value=905465 ID=7
9401 20:17:40.677721 ADC[3]: Raw value=213441 ID=1
9402 20:17:40.680705 RAM Code: 0x71
9403 20:17:40.680787 ADC[6]: Raw value=75701 ID=0
9404 20:17:40.684398 ADC[5]: Raw value=213072 ID=1
9405 20:17:40.687452 SKU Code: 0x1
9406 20:17:40.690664 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5b3f
9407 20:17:40.694335 coreboot table: 964 bytes.
9408 20:17:40.697358 IMD ROOT 0. 0xfffff000 0x00001000
9409 20:17:40.700578 IMD SMALL 1. 0xffffe000 0x00001000
9410 20:17:40.704251 RO MCACHE 2. 0xffffc000 0x00001104
9411 20:17:40.707353 CONSOLE 3. 0xfff7c000 0x00080000
9412 20:17:40.710543 FMAP 4. 0xfff7b000 0x00000452
9413 20:17:40.714207 TIME STAMP 5. 0xfff7a000 0x00000910
9414 20:17:40.717219 VBOOT WORK 6. 0xfff66000 0x00014000
9415 20:17:40.720353 RAMOOPS 7. 0xffe66000 0x00100000
9416 20:17:40.724067 COREBOOT 8. 0xffe64000 0x00002000
9417 20:17:40.726907 IMD small region:
9418 20:17:40.730190 IMD ROOT 0. 0xffffec00 0x00000400
9419 20:17:40.733664 VPD 1. 0xffffeb80 0x0000006c
9420 20:17:40.737078 MMC STATUS 2. 0xffffeb60 0x00000004
9421 20:17:40.740648 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9422 20:17:40.743629 Probing TPM: done!
9423 20:17:40.747310 Connected to device vid:did:rid of 1ae0:0028:00
9424 20:17:40.757585 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9425 20:17:40.761271 Initialized TPM device CR50 revision 0
9426 20:17:40.765023 Checking cr50 for pending updates
9427 20:17:40.768569 Reading cr50 TPM mode
9428 20:17:40.777471 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9429 20:17:40.784010 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9430 20:17:40.824262 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9431 20:17:40.827394 Checking segment from ROM address 0x40100000
9432 20:17:40.830516 Checking segment from ROM address 0x4010001c
9433 20:17:40.837365 Loading segment from ROM address 0x40100000
9434 20:17:40.837448 code (compression=0)
9435 20:17:40.847312 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9436 20:17:40.853801 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9437 20:17:40.853884 it's not compressed!
9438 20:17:40.860876 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9439 20:17:40.864050 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9440 20:17:40.884210 Loading segment from ROM address 0x4010001c
9441 20:17:40.884316 Entry Point 0x80000000
9442 20:17:40.887726 Loaded segments
9443 20:17:40.890897 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9444 20:17:40.897689 Jumping to boot code at 0x80000000(0xffe64000)
9445 20:17:40.904182 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9446 20:17:40.910869 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9447 20:17:40.918899 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9448 20:17:40.921987 Checking segment from ROM address 0x40100000
9449 20:17:40.925651 Checking segment from ROM address 0x4010001c
9450 20:17:40.931876 Loading segment from ROM address 0x40100000
9451 20:17:40.931999 code (compression=1)
9452 20:17:40.938664 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9453 20:17:40.948842 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9454 20:17:40.948964 using LZMA
9455 20:17:40.957307 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9456 20:17:40.964118 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9457 20:17:40.967073 Loading segment from ROM address 0x4010001c
9458 20:17:40.967194 Entry Point 0x54601000
9459 20:17:40.970313 Loaded segments
9460 20:17:40.973564 NOTICE: MT8192 bl31_setup
9461 20:17:40.980625 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9462 20:17:40.983954 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9463 20:17:40.987382 WARNING: region 0:
9464 20:17:40.990682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 20:17:40.990764 WARNING: region 1:
9466 20:17:40.997193 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9467 20:17:41.000835 WARNING: region 2:
9468 20:17:41.003782 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9469 20:17:41.007396 WARNING: region 3:
9470 20:17:41.010557 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 20:17:41.013818 WARNING: region 4:
9472 20:17:41.020600 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 20:17:41.020683 WARNING: region 5:
9474 20:17:41.024196 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 20:17:41.027241 WARNING: region 6:
9476 20:17:41.030455 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 20:17:41.034173 WARNING: region 7:
9478 20:17:41.037097 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 20:17:41.043683 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9480 20:17:41.047559 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9481 20:17:41.050604 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9482 20:17:41.057117 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9483 20:17:41.060197 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9484 20:17:41.063960 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9485 20:17:41.070790 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9486 20:17:41.073863 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9487 20:17:41.080790 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9488 20:17:41.083920 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9489 20:17:41.086921 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9490 20:17:41.093742 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9491 20:17:41.096882 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9492 20:17:41.100747 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9493 20:17:41.107195 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9494 20:17:41.110465 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9495 20:17:41.116886 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9496 20:17:41.120176 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9497 20:17:41.123763 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9498 20:17:41.130118 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9499 20:17:41.133575 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9500 20:17:41.136779 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9501 20:17:41.143695 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9502 20:17:41.147376 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9503 20:17:41.153973 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9504 20:17:41.157036 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9505 20:17:41.160956 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9506 20:17:41.167312 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9507 20:17:41.170435 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9508 20:17:41.177313 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9509 20:17:41.180304 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9510 20:17:41.183971 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9511 20:17:41.190414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9512 20:17:41.193971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9513 20:17:41.197287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9514 20:17:41.200543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9515 20:17:41.207241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9516 20:17:41.210897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9517 20:17:41.213850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9518 20:17:41.217451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9519 20:17:41.220580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9520 20:17:41.227180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9521 20:17:41.230930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9522 20:17:41.234275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9523 20:17:41.240712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9524 20:17:41.244421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9525 20:17:41.247339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9526 20:17:41.250667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9527 20:17:41.257271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9528 20:17:41.260462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9529 20:17:41.267539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9530 20:17:41.270748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9531 20:17:41.273954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9532 20:17:41.281001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9533 20:17:41.284102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9534 20:17:41.290868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9535 20:17:41.294550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9536 20:17:41.297671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9537 20:17:41.304201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9538 20:17:41.307522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9539 20:17:41.314735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9540 20:17:41.317809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9541 20:17:41.323932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9542 20:17:41.327521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9543 20:17:41.334045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9544 20:17:41.337369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9545 20:17:41.341118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9546 20:17:41.347335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9547 20:17:41.350872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9548 20:17:41.357537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9549 20:17:41.360624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9550 20:17:41.367555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9551 20:17:41.371657 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9552 20:17:41.374574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9553 20:17:41.381049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9554 20:17:41.384522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9555 20:17:41.391362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9556 20:17:41.394675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9557 20:17:41.400995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9558 20:17:41.404165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9559 20:17:41.407793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9560 20:17:41.414225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9561 20:17:41.417739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9562 20:17:41.424415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9563 20:17:41.427596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9564 20:17:41.434274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9565 20:17:41.437871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9566 20:17:41.441227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9567 20:17:41.447594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9568 20:17:41.451332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9569 20:17:41.457951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9570 20:17:41.461362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9571 20:17:41.467713 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9572 20:17:41.471515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9573 20:17:41.474537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9574 20:17:41.481360 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9575 20:17:41.484647 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9576 20:17:41.488087 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9577 20:17:41.494428 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9578 20:17:41.497954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9579 20:17:41.501486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9580 20:17:41.504309 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9581 20:17:41.511439 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9582 20:17:41.514581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9583 20:17:41.521300 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9584 20:17:41.524764 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9585 20:17:41.528114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9586 20:17:41.534862 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9587 20:17:41.537957 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9588 20:17:41.544743 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9589 20:17:41.548203 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9590 20:17:41.551611 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9591 20:17:41.558075 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9592 20:17:41.561744 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9593 20:17:41.568469 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9594 20:17:41.571516 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9595 20:17:41.574640 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9596 20:17:41.578323 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9597 20:17:41.584465 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9598 20:17:41.588134 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9599 20:17:41.591409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9600 20:17:41.598324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9601 20:17:41.601346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9602 20:17:41.604598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9603 20:17:41.608228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9604 20:17:41.614913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9605 20:17:41.617935 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9606 20:17:41.624415 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9607 20:17:41.627716 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9608 20:17:41.631042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9609 20:17:41.637884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9610 20:17:41.641149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9611 20:17:41.648063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9612 20:17:41.651185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9613 20:17:41.654773 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9614 20:17:41.661312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9615 20:17:41.664877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9616 20:17:41.668010 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9617 20:17:41.674790 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9618 20:17:41.678433 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9619 20:17:41.684598 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9620 20:17:41.688246 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9621 20:17:41.691925 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9622 20:17:41.698071 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9623 20:17:41.701450 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9624 20:17:41.704899 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9625 20:17:41.711653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9626 20:17:41.715334 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9627 20:17:41.721615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9628 20:17:41.725372 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9629 20:17:41.728393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9630 20:17:41.735314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9631 20:17:41.738271 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9632 20:17:41.742101 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9633 20:17:41.748711 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9634 20:17:41.751633 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9635 20:17:41.758457 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9636 20:17:41.761844 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9637 20:17:41.764787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9638 20:17:41.771850 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9639 20:17:41.774768 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9640 20:17:41.781697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9641 20:17:41.784800 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9642 20:17:41.788332 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9643 20:17:41.795053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9644 20:17:41.798061 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9645 20:17:41.805163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9646 20:17:41.808412 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9647 20:17:41.811855 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9648 20:17:41.818060 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9649 20:17:41.821665 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9650 20:17:41.828512 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9651 20:17:41.831526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9652 20:17:41.834630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9653 20:17:41.841471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9654 20:17:41.845137 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9655 20:17:41.848195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9656 20:17:41.855149 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9657 20:17:41.858270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9658 20:17:41.864645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9659 20:17:41.868052 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9660 20:17:41.871301 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9661 20:17:41.877913 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9662 20:17:41.881205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9663 20:17:41.888252 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9664 20:17:41.891596 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9665 20:17:41.894456 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9666 20:17:41.901165 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9667 20:17:41.904402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9668 20:17:41.911330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9669 20:17:41.914407 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9670 20:17:41.917814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9671 20:17:41.924678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9672 20:17:41.927701 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9673 20:17:41.934781 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9674 20:17:41.937896 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9675 20:17:41.944096 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9676 20:17:41.947736 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9677 20:17:41.950828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9678 20:17:41.957900 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9679 20:17:41.960880 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9680 20:17:41.967597 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9681 20:17:41.971113 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9682 20:17:41.974353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9683 20:17:41.980874 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9684 20:17:41.984579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9685 20:17:41.991380 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9686 20:17:41.994414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9687 20:17:41.998128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9688 20:17:42.004370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9689 20:17:42.008034 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9690 20:17:42.014157 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9691 20:17:42.018025 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9692 20:17:42.024302 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9693 20:17:42.027725 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9694 20:17:42.030885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9695 20:17:42.037755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9696 20:17:42.041120 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9697 20:17:42.047470 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9698 20:17:42.051170 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9699 20:17:42.054590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9700 20:17:42.060973 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9701 20:17:42.064056 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9702 20:17:42.070742 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9703 20:17:42.073704 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9704 20:17:42.080645 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9705 20:17:42.083993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9706 20:17:42.087667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9707 20:17:42.093820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9708 20:17:42.097357 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9709 20:17:42.100530 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9710 20:17:42.103637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9711 20:17:42.110423 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9712 20:17:42.113764 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9713 20:17:42.117352 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9714 20:17:42.123894 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9715 20:17:42.127273 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9716 20:17:42.133976 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9717 20:17:42.136955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9718 20:17:42.140587 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9719 20:17:42.147294 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9720 20:17:42.150414 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9721 20:17:42.153735 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9722 20:17:42.160067 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9723 20:17:42.163576 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9724 20:17:42.167109 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9725 20:17:42.173865 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9726 20:17:42.177053 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9727 20:17:42.180444 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9728 20:17:42.187184 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9729 20:17:42.190086 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9730 20:17:42.193574 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9731 20:17:42.200340 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9732 20:17:42.203893 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9733 20:17:42.207046 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9734 20:17:42.213882 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9735 20:17:42.216923 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9736 20:17:42.224188 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9737 20:17:42.227210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9738 20:17:42.230775 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9739 20:17:42.237441 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9740 20:17:42.240487 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9741 20:17:42.244208 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9742 20:17:42.250214 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9743 20:17:42.253813 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9744 20:17:42.256930 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9745 20:17:42.263648 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9746 20:17:42.267249 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9747 20:17:42.270178 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9748 20:17:42.277176 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9749 20:17:42.280645 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9750 20:17:42.283793 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9751 20:17:42.286924 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9752 20:17:42.290183 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9753 20:17:42.297308 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9754 20:17:42.300157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9755 20:17:42.303581 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9756 20:17:42.310036 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9757 20:17:42.313845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9758 20:17:42.316843 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9759 20:17:42.320535 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9760 20:17:42.327149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9761 20:17:42.330245 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9762 20:17:42.333763 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9763 20:17:42.340236 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9764 20:17:42.343613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9765 20:17:42.350221 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9766 20:17:42.353362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9767 20:17:42.359979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9768 20:17:42.363683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9769 20:17:42.366740 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9770 20:17:42.373346 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9771 20:17:42.377009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9772 20:17:42.383098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9773 20:17:42.386791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9774 20:17:42.389904 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9775 20:17:42.397106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9776 20:17:42.399776 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9777 20:17:42.406337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9778 20:17:42.409624 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9779 20:17:42.413044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9780 20:17:42.420449 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9781 20:17:42.423334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9782 20:17:42.430052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9783 20:17:42.433167 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9784 20:17:42.436273 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9785 20:17:42.443016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9786 20:17:42.446378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9787 20:17:42.453142 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9788 20:17:42.456253 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9789 20:17:42.462904 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9790 20:17:42.466118 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9791 20:17:42.469715 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9792 20:17:42.476112 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9793 20:17:42.479762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9794 20:17:42.486282 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9795 20:17:42.489379 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9796 20:17:42.492639 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9797 20:17:42.499664 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9798 20:17:42.502730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9799 20:17:42.509550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9800 20:17:42.512588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9801 20:17:42.516009 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9802 20:17:42.522556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9803 20:17:42.526302 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9804 20:17:42.532564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9805 20:17:42.536109 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9806 20:17:42.542538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9807 20:17:42.545963 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9808 20:17:42.549497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9809 20:17:42.556029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9810 20:17:42.559296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9811 20:17:42.566023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9812 20:17:42.569089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9813 20:17:42.572373 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9814 20:17:42.579011 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9815 20:17:42.582511 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9816 20:17:42.589218 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9817 20:17:42.592264 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9818 20:17:42.596051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9819 20:17:42.602245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9820 20:17:42.605702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9821 20:17:42.612509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9822 20:17:42.615570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9823 20:17:42.619244 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9824 20:17:42.625798 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9825 20:17:42.629128 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9826 20:17:42.635960 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9827 20:17:42.638956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9828 20:17:42.642440 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9829 20:17:42.649024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9830 20:17:42.651935 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9831 20:17:42.658907 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9832 20:17:42.662165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9833 20:17:42.668561 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9834 20:17:42.671609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9835 20:17:42.674978 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9836 20:17:42.681674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9837 20:17:42.685212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9838 20:17:42.691777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9839 20:17:42.695413 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9840 20:17:42.701644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9841 20:17:42.705309 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9842 20:17:42.708222 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9843 20:17:42.715275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9844 20:17:42.718297 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9845 20:17:42.725038 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9846 20:17:42.728128 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9847 20:17:42.734817 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9848 20:17:42.738344 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9849 20:17:42.744865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9850 20:17:42.748409 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9851 20:17:42.751347 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9852 20:17:42.758058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9853 20:17:42.761815 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9854 20:17:42.768149 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9855 20:17:42.771803 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9856 20:17:42.778175 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9857 20:17:42.781439 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9858 20:17:42.785343 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9859 20:17:42.791601 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9860 20:17:42.794666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9861 20:17:42.801319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9862 20:17:42.804452 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9863 20:17:42.811373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9864 20:17:42.815048 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9865 20:17:42.818208 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9866 20:17:42.824262 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9867 20:17:42.828116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9868 20:17:42.834201 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9869 20:17:42.838009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9870 20:17:42.844206 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9871 20:17:42.848028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9872 20:17:42.850941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9873 20:17:42.857720 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9874 20:17:42.861261 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9875 20:17:42.867666 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9876 20:17:42.870873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9877 20:17:42.877454 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9878 20:17:42.880745 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9879 20:17:42.887581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9880 20:17:42.891184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9881 20:17:42.894483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9882 20:17:42.901146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9883 20:17:42.904247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9884 20:17:42.911180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9885 20:17:42.914174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9886 20:17:42.921086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9887 20:17:42.923953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9888 20:17:42.931045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9889 20:17:42.934158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9890 20:17:42.937923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9891 20:17:42.944174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9892 20:17:42.947936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9893 20:17:42.954001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9894 20:17:42.957195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9895 20:17:42.963906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9896 20:17:42.967366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9897 20:17:42.974272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9898 20:17:42.977403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9899 20:17:42.984157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9900 20:17:42.987414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9901 20:17:42.994343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9902 20:17:42.997198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9903 20:17:43.004002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9904 20:17:43.007022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9905 20:17:43.013865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9906 20:17:43.017091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9907 20:17:43.023528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9908 20:17:43.027149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9909 20:17:43.033695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9910 20:17:43.037145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9911 20:17:43.043801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9912 20:17:43.046962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9913 20:17:43.053663 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9914 20:17:43.053745 INFO: [APUAPC] vio 0
9915 20:17:43.060590 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9916 20:17:43.063614 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9917 20:17:43.067166 INFO: [APUAPC] D0_APC_0: 0x400510
9918 20:17:43.070755 INFO: [APUAPC] D0_APC_1: 0x0
9919 20:17:43.073898 INFO: [APUAPC] D0_APC_2: 0x1540
9920 20:17:43.077050 INFO: [APUAPC] D0_APC_3: 0x0
9921 20:17:43.080768 INFO: [APUAPC] D1_APC_0: 0xffffffff
9922 20:17:43.083804 INFO: [APUAPC] D1_APC_1: 0xffffffff
9923 20:17:43.087332 INFO: [APUAPC] D1_APC_2: 0x3fffff
9924 20:17:43.090896 INFO: [APUAPC] D1_APC_3: 0x0
9925 20:17:43.093831 INFO: [APUAPC] D2_APC_0: 0xffffffff
9926 20:17:43.097048 INFO: [APUAPC] D2_APC_1: 0xffffffff
9927 20:17:43.100628 INFO: [APUAPC] D2_APC_2: 0x3fffff
9928 20:17:43.100710 INFO: [APUAPC] D2_APC_3: 0x0
9929 20:17:43.107492 INFO: [APUAPC] D3_APC_0: 0xffffffff
9930 20:17:43.110775 INFO: [APUAPC] D3_APC_1: 0xffffffff
9931 20:17:43.113848 INFO: [APUAPC] D3_APC_2: 0x3fffff
9932 20:17:43.113931 INFO: [APUAPC] D3_APC_3: 0x0
9933 20:17:43.117508 INFO: [APUAPC] D4_APC_0: 0xffffffff
9934 20:17:43.120385 INFO: [APUAPC] D4_APC_1: 0xffffffff
9935 20:17:43.123981 INFO: [APUAPC] D4_APC_2: 0x3fffff
9936 20:17:43.127159 INFO: [APUAPC] D4_APC_3: 0x0
9937 20:17:43.130604 INFO: [APUAPC] D5_APC_0: 0xffffffff
9938 20:17:43.134161 INFO: [APUAPC] D5_APC_1: 0xffffffff
9939 20:17:43.137242 INFO: [APUAPC] D5_APC_2: 0x3fffff
9940 20:17:43.140735 INFO: [APUAPC] D5_APC_3: 0x0
9941 20:17:43.143968 INFO: [APUAPC] D6_APC_0: 0xffffffff
9942 20:17:43.147275 INFO: [APUAPC] D6_APC_1: 0xffffffff
9943 20:17:43.150298 INFO: [APUAPC] D6_APC_2: 0x3fffff
9944 20:17:43.153981 INFO: [APUAPC] D6_APC_3: 0x0
9945 20:17:43.157027 INFO: [APUAPC] D7_APC_0: 0xffffffff
9946 20:17:43.160569 INFO: [APUAPC] D7_APC_1: 0xffffffff
9947 20:17:43.163736 INFO: [APUAPC] D7_APC_2: 0x3fffff
9948 20:17:43.167477 INFO: [APUAPC] D7_APC_3: 0x0
9949 20:17:43.170567 INFO: [APUAPC] D8_APC_0: 0xffffffff
9950 20:17:43.174294 INFO: [APUAPC] D8_APC_1: 0xffffffff
9951 20:17:43.177284 INFO: [APUAPC] D8_APC_2: 0x3fffff
9952 20:17:43.180458 INFO: [APUAPC] D8_APC_3: 0x0
9953 20:17:43.184174 INFO: [APUAPC] D9_APC_0: 0xffffffff
9954 20:17:43.187190 INFO: [APUAPC] D9_APC_1: 0xffffffff
9955 20:17:43.190272 INFO: [APUAPC] D9_APC_2: 0x3fffff
9956 20:17:43.193656 INFO: [APUAPC] D9_APC_3: 0x0
9957 20:17:43.197451 INFO: [APUAPC] D10_APC_0: 0xffffffff
9958 20:17:43.200516 INFO: [APUAPC] D10_APC_1: 0xffffffff
9959 20:17:43.203470 INFO: [APUAPC] D10_APC_2: 0x3fffff
9960 20:17:43.207226 INFO: [APUAPC] D10_APC_3: 0x0
9961 20:17:43.210357 INFO: [APUAPC] D11_APC_0: 0xffffffff
9962 20:17:43.213984 INFO: [APUAPC] D11_APC_1: 0xffffffff
9963 20:17:43.216895 INFO: [APUAPC] D11_APC_2: 0x3fffff
9964 20:17:43.220519 INFO: [APUAPC] D11_APC_3: 0x0
9965 20:17:43.223720 INFO: [APUAPC] D12_APC_0: 0xffffffff
9966 20:17:43.226847 INFO: [APUAPC] D12_APC_1: 0xffffffff
9967 20:17:43.230153 INFO: [APUAPC] D12_APC_2: 0x3fffff
9968 20:17:43.233588 INFO: [APUAPC] D12_APC_3: 0x0
9969 20:17:43.236619 INFO: [APUAPC] D13_APC_0: 0xffffffff
9970 20:17:43.240318 INFO: [APUAPC] D13_APC_1: 0xffffffff
9971 20:17:43.243324 INFO: [APUAPC] D13_APC_2: 0x3fffff
9972 20:17:43.247064 INFO: [APUAPC] D13_APC_3: 0x0
9973 20:17:43.250217 INFO: [APUAPC] D14_APC_0: 0xffffffff
9974 20:17:43.253333 INFO: [APUAPC] D14_APC_1: 0xffffffff
9975 20:17:43.256646 INFO: [APUAPC] D14_APC_2: 0x3fffff
9976 20:17:43.260033 INFO: [APUAPC] D14_APC_3: 0x0
9977 20:17:43.263258 INFO: [APUAPC] D15_APC_0: 0xffffffff
9978 20:17:43.266883 INFO: [APUAPC] D15_APC_1: 0xffffffff
9979 20:17:43.269967 INFO: [APUAPC] D15_APC_2: 0x3fffff
9980 20:17:43.273746 INFO: [APUAPC] D15_APC_3: 0x0
9981 20:17:43.276700 INFO: [APUAPC] APC_CON: 0x4
9982 20:17:43.280236 INFO: [NOCDAPC] D0_APC_0: 0x0
9983 20:17:43.283344 INFO: [NOCDAPC] D0_APC_1: 0x0
9984 20:17:43.286985 INFO: [NOCDAPC] D1_APC_0: 0x0
9985 20:17:43.287067 INFO: [NOCDAPC] D1_APC_1: 0xfff
9986 20:17:43.290029 INFO: [NOCDAPC] D2_APC_0: 0x0
9987 20:17:43.293657 INFO: [NOCDAPC] D2_APC_1: 0xfff
9988 20:17:43.297199 INFO: [NOCDAPC] D3_APC_0: 0x0
9989 20:17:43.300103 INFO: [NOCDAPC] D3_APC_1: 0xfff
9990 20:17:43.303339 INFO: [NOCDAPC] D4_APC_0: 0x0
9991 20:17:43.306867 INFO: [NOCDAPC] D4_APC_1: 0xfff
9992 20:17:43.310498 INFO: [NOCDAPC] D5_APC_0: 0x0
9993 20:17:43.313705 INFO: [NOCDAPC] D5_APC_1: 0xfff
9994 20:17:43.316772 INFO: [NOCDAPC] D6_APC_0: 0x0
9995 20:17:43.316854 INFO: [NOCDAPC] D6_APC_1: 0xfff
9996 20:17:43.320388 INFO: [NOCDAPC] D7_APC_0: 0x0
9997 20:17:43.323378 INFO: [NOCDAPC] D7_APC_1: 0xfff
9998 20:17:43.327053 INFO: [NOCDAPC] D8_APC_0: 0x0
9999 20:17:43.329928 INFO: [NOCDAPC] D8_APC_1: 0xfff
10000 20:17:43.333367 INFO: [NOCDAPC] D9_APC_0: 0x0
10001 20:17:43.336609 INFO: [NOCDAPC] D9_APC_1: 0xfff
10002 20:17:43.340188 INFO: [NOCDAPC] D10_APC_0: 0x0
10003 20:17:43.343297 INFO: [NOCDAPC] D10_APC_1: 0xfff
10004 20:17:43.346524 INFO: [NOCDAPC] D11_APC_0: 0x0
10005 20:17:43.350040 INFO: [NOCDAPC] D11_APC_1: 0xfff
10006 20:17:43.353454 INFO: [NOCDAPC] D12_APC_0: 0x0
10007 20:17:43.356880 INFO: [NOCDAPC] D12_APC_1: 0xfff
10008 20:17:43.356961 INFO: [NOCDAPC] D13_APC_0: 0x0
10009 20:17:43.359720 INFO: [NOCDAPC] D13_APC_1: 0xfff
10010 20:17:43.363104 INFO: [NOCDAPC] D14_APC_0: 0x0
10011 20:17:43.366438 INFO: [NOCDAPC] D14_APC_1: 0xfff
10012 20:17:43.369659 INFO: [NOCDAPC] D15_APC_0: 0x0
10013 20:17:43.373072 INFO: [NOCDAPC] D15_APC_1: 0xfff
10014 20:17:43.376305 INFO: [NOCDAPC] APC_CON: 0x4
10015 20:17:43.379899 INFO: [APUAPC] set_apusys_apc done
10016 20:17:43.383044 INFO: [DEVAPC] devapc_init done
10017 20:17:43.386596 INFO: GICv3 without legacy support detected.
10018 20:17:43.389597 INFO: ARM GICv3 driver initialized in EL3
10019 20:17:43.396420 INFO: Maximum SPI INTID supported: 639
10020 20:17:43.399496 INFO: BL31: Initializing runtime services
10021 20:17:43.403126 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10022 20:17:43.406623 INFO: SPM: enable CPC mode
10023 20:17:43.413204 INFO: mcdi ready for mcusys-off-idle and system suspend
10024 20:17:43.416142 INFO: BL31: Preparing for EL3 exit to normal world
10025 20:17:43.419320 INFO: Entry point address = 0x80000000
10026 20:17:43.422938 INFO: SPSR = 0x8
10027 20:17:43.428468
10028 20:17:43.428548
10029 20:17:43.428611
10030 20:17:43.432052 Starting depthcharge on Spherion...
10031 20:17:43.432158
10032 20:17:43.432250 Wipe memory regions:
10033 20:17:43.432368
10034 20:17:43.433018 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10035 20:17:43.433115 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10036 20:17:43.433196 Setting prompt string to ['asurada:']
10037 20:17:43.433278 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10038 20:17:43.435148 [0x00000040000000, 0x00000054600000)
10039 20:17:43.557173
10040 20:17:43.557291 [0x00000054660000, 0x00000080000000)
10041 20:17:43.817969
10042 20:17:43.818105 [0x000000821a7280, 0x000000ffe64000)
10043 20:17:44.562964
10044 20:17:44.563120 [0x00000100000000, 0x00000240000000)
10045 20:17:46.453262
10046 20:17:46.456671 Initializing XHCI USB controller at 0x11200000.
10047 20:17:47.495109
10048 20:17:47.498272 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10049 20:17:47.498361
10050 20:17:47.498450
10051 20:17:47.498525
10052 20:17:47.498807 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 20:17:47.599168 asurada: tftpboot 192.168.201.1 12928123/tftp-deploy-6815w_fp/kernel/image.itb 12928123/tftp-deploy-6815w_fp/kernel/cmdline
10055 20:17:47.599295 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 20:17:47.599413 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10057 20:17:47.603398 tftpboot 192.168.201.1 12928123/tftp-deploy-6815w_fp/kernel/image.ittp-deploy-6815w_fp/kernel/cmdline
10058 20:17:47.603509
10059 20:17:47.603576 Waiting for link
10060 20:17:47.764177
10061 20:17:47.764354 R8152: Initializing
10062 20:17:47.764423
10063 20:17:47.767224 Version 9 (ocp_data = 6010)
10064 20:17:47.767305
10065 20:17:47.770839 R8152: Done initializing
10066 20:17:47.770947
10067 20:17:47.771040 Adding net device
10068 20:17:49.716730
10069 20:17:49.716880 done.
10070 20:17:49.716947
10071 20:17:49.717008 MAC: 00:e0:4c:78:7a:aa
10072 20:17:49.717066
10073 20:17:49.719659 Sending DHCP discover... done.
10074 20:17:49.719768
10075 20:17:49.722875 Waiting for reply... done.
10076 20:17:49.722957
10077 20:17:49.726105 Sending DHCP request... done.
10078 20:17:49.726199
10079 20:17:49.731337 Waiting for reply... done.
10080 20:17:49.731419
10081 20:17:49.731483 My ip is 192.168.201.12
10082 20:17:49.731544
10083 20:17:49.735016 The DHCP server ip is 192.168.201.1
10084 20:17:49.735098
10085 20:17:49.741825 TFTP server IP predefined by user: 192.168.201.1
10086 20:17:49.741907
10087 20:17:49.748608 Bootfile predefined by user: 12928123/tftp-deploy-6815w_fp/kernel/image.itb
10088 20:17:49.748689
10089 20:17:49.748753 Sending tftp read request... done.
10090 20:17:49.751597
10091 20:17:49.755229 Waiting for the transfer...
10092 20:17:49.755310
10093 20:17:50.017964 00000000 ################################################################
10094 20:17:50.018100
10095 20:17:50.276938 00080000 ################################################################
10096 20:17:50.277082
10097 20:17:50.564159 00100000 ################################################################
10098 20:17:50.564346
10099 20:17:50.845696 00180000 ################################################################
10100 20:17:50.845840
10101 20:17:51.120527 00200000 ################################################################
10102 20:17:51.120733
10103 20:17:51.392228 00280000 ################################################################
10104 20:17:51.392426
10105 20:17:51.663864 00300000 ################################################################
10106 20:17:51.664011
10107 20:17:51.928898 00380000 ################################################################
10108 20:17:51.929058
10109 20:17:52.183569 00400000 ################################################################
10110 20:17:52.183768
10111 20:17:52.455022 00480000 ################################################################
10112 20:17:52.455221
10113 20:17:52.729166 00500000 ################################################################
10114 20:17:52.729375
10115 20:17:53.015022 00580000 ################################################################
10116 20:17:53.015193
10117 20:17:53.307446 00600000 ################################################################
10118 20:17:53.307587
10119 20:17:53.599734 00680000 ################################################################
10120 20:17:53.599883
10121 20:17:53.887409 00700000 ################################################################
10122 20:17:53.887574
10123 20:17:54.184869 00780000 ################################################################
10124 20:17:54.185023
10125 20:17:54.453442 00800000 ################################################################
10126 20:17:54.453589
10127 20:17:54.724819 00880000 ################################################################
10128 20:17:54.724962
10129 20:17:54.998216 00900000 ################################################################
10130 20:17:54.998359
10131 20:17:55.279345 00980000 ################################################################
10132 20:17:55.279490
10133 20:17:55.558847 00a00000 ################################################################
10134 20:17:55.559056
10135 20:17:55.822719 00a80000 ################################################################
10136 20:17:55.822906
10137 20:17:56.095497 00b00000 ################################################################
10138 20:17:56.095653
10139 20:17:56.367945 00b80000 ################################################################
10140 20:17:56.368103
10141 20:17:56.637172 00c00000 ################################################################
10142 20:17:56.637377
10143 20:17:56.910709 00c80000 ################################################################
10144 20:17:56.910910
10145 20:17:57.173332 00d00000 ################################################################
10146 20:17:57.173467
10147 20:17:57.431001 00d80000 ################################################################
10148 20:17:57.431141
10149 20:17:57.683489 00e00000 ################################################################
10150 20:17:57.683626
10151 20:17:57.941739 00e80000 ################################################################
10152 20:17:57.941892
10153 20:17:58.192260 00f00000 ################################################################
10154 20:17:58.192428
10155 20:17:58.445725 00f80000 ################################################################
10156 20:17:58.445908
10157 20:17:58.708849 01000000 ################################################################
10158 20:17:58.708989
10159 20:17:58.978705 01080000 ################################################################
10160 20:17:58.978918
10161 20:17:59.252810 01100000 ################################################################
10162 20:17:59.252976
10163 20:17:59.524709 01180000 ################################################################
10164 20:17:59.524847
10165 20:17:59.796204 01200000 ################################################################
10166 20:17:59.796361
10167 20:18:00.067015 01280000 ################################################################
10168 20:18:00.067161
10169 20:18:00.348662 01300000 ################################################################
10170 20:18:00.348820
10171 20:18:00.609500 01380000 ################################################################
10172 20:18:00.609648
10173 20:18:00.891370 01400000 ################################################################
10174 20:18:00.891544
10175 20:18:01.157829 01480000 ################################################################
10176 20:18:01.157978
10177 20:18:01.441963 01500000 ################################################################
10178 20:18:01.442100
10179 20:18:01.696447 01580000 ################################################################
10180 20:18:01.696657
10181 20:18:01.977073 01600000 ################################################################
10182 20:18:01.977286
10183 20:18:02.263683 01680000 ################################################################
10184 20:18:02.263877
10185 20:18:02.522344 01700000 ################################################################
10186 20:18:02.522555
10187 20:18:02.801930 01780000 ################################################################
10188 20:18:02.802151
10189 20:18:03.073727 01800000 ################################################################
10190 20:18:03.073941
10191 20:18:03.368109 01880000 ################################################################
10192 20:18:03.368334
10193 20:18:03.626094 01900000 ################################################################
10194 20:18:03.626258
10195 20:18:03.893540 01980000 ################################################################
10196 20:18:03.893757
10197 20:18:04.166962 01a00000 ################################################################
10198 20:18:04.167117
10199 20:18:04.430671 01a80000 ################################################################
10200 20:18:04.430825
10201 20:18:04.724533 01b00000 ################################################################
10202 20:18:04.724691
10203 20:18:04.988282 01b80000 ################################################################
10204 20:18:04.988511
10205 20:18:05.257443 01c00000 ################################################################
10206 20:18:05.257602
10207 20:18:05.526418 01c80000 ################################################################
10208 20:18:05.526575
10209 20:18:05.786178 01d00000 ################################################################
10210 20:18:05.786395
10211 20:18:06.051992 01d80000 ################################################################
10212 20:18:06.052212
10213 20:18:06.331191 01e00000 ################################################################
10214 20:18:06.331353
10215 20:18:06.599669 01e80000 ################################################################
10216 20:18:06.599906
10217 20:18:06.894138 01f00000 ################################################################
10218 20:18:06.894291
10219 20:18:07.189782 01f80000 ################################################################
10220 20:18:07.190013
10221 20:18:07.482265 02000000 ################################################################
10222 20:18:07.482427
10223 20:18:07.784127 02080000 ################################################################
10224 20:18:07.784349
10225 20:18:08.066722 02100000 ################################################################
10226 20:18:08.066928
10227 20:18:08.347772 02180000 ################################################################
10228 20:18:08.347925
10229 20:18:08.628053 02200000 ################################################################
10230 20:18:08.628241
10231 20:18:08.910746 02280000 ################################################################
10232 20:18:08.910966
10233 20:18:09.196592 02300000 ################################################################
10234 20:18:09.196816
10235 20:18:09.477898 02380000 ################################################################
10236 20:18:09.478055
10237 20:18:09.736313 02400000 ################################################################
10238 20:18:09.736471
10239 20:18:10.001616 02480000 ################################################################
10240 20:18:10.001791
10241 20:18:10.261181 02500000 ################################################################
10242 20:18:10.261327
10243 20:18:10.512888 02580000 ################################################################
10244 20:18:10.513079
10245 20:18:10.808980 02600000 ################################################################
10246 20:18:10.809155
10247 20:18:11.087881 02680000 ################################################################
10248 20:18:11.088092
10249 20:18:11.371159 02700000 ################################################################
10250 20:18:11.371342
10251 20:18:11.664884 02780000 ################################################################
10252 20:18:11.665034
10253 20:18:11.940145 02800000 ################################################################
10254 20:18:11.940356
10255 20:18:12.220647 02880000 ################################################################
10256 20:18:12.220825
10257 20:18:12.498055 02900000 ################################################################
10258 20:18:12.498206
10259 20:18:12.794966 02980000 ################################################################
10260 20:18:12.795121
10261 20:18:13.074688 02a00000 ################################################################
10262 20:18:13.074846
10263 20:18:13.345084 02a80000 ################################################################
10264 20:18:13.345237
10265 20:18:13.624407 02b00000 ################################################################
10266 20:18:13.624593
10267 20:18:13.893204 02b80000 ################################################################
10268 20:18:13.893359
10269 20:18:14.168400 02c00000 ################################################################
10270 20:18:14.168552
10271 20:18:14.451883 02c80000 ################################################################
10272 20:18:14.452098
10273 20:18:14.741210 02d00000 ################################################################
10274 20:18:14.741358
10275 20:18:15.009249 02d80000 ################################################################
10276 20:18:15.009407
10277 20:18:15.274095 02e00000 ################################################################
10278 20:18:15.274297
10279 20:18:15.532462 02e80000 ################################################################
10280 20:18:15.532680
10281 20:18:15.800182 02f00000 ################################################################
10282 20:18:15.800347
10283 20:18:16.068571 02f80000 ################################################################
10284 20:18:16.068761
10285 20:18:16.350227 03000000 ################################################################
10286 20:18:16.350447
10287 20:18:16.623246 03080000 ################################################################
10288 20:18:16.623398
10289 20:18:16.888899 03100000 ################################################################
10290 20:18:16.889065
10291 20:18:17.153950 03180000 ################################################################
10292 20:18:17.154135
10293 20:18:17.432565 03200000 ################################################################
10294 20:18:17.432744
10295 20:18:17.726196 03280000 ################################################################
10296 20:18:17.726348
10297 20:18:18.024408 03300000 ################################################################
10298 20:18:18.024556
10299 20:18:18.323375 03380000 ################################################################
10300 20:18:18.323588
10301 20:18:18.608338 03400000 ################################################################
10302 20:18:18.608490
10303 20:18:18.895596 03480000 ################################################################
10304 20:18:18.895803
10305 20:18:19.178241 03500000 ################################################################
10306 20:18:19.178445
10307 20:18:19.476532 03580000 ################################################################
10308 20:18:19.476734
10309 20:18:19.774035 03600000 ################################################################
10310 20:18:19.774181
10311 20:18:20.072848 03680000 ################################################################
10312 20:18:20.072988
10313 20:18:20.343228 03700000 ################################################################
10314 20:18:20.343384
10315 20:18:20.608059 03780000 ################################################################
10316 20:18:20.608203
10317 20:18:20.878155 03800000 ################################################################
10318 20:18:20.878294
10319 20:18:21.144028 03880000 ################################################################
10320 20:18:21.144170
10321 20:18:21.417216 03900000 ################################################################
10322 20:18:21.417360
10323 20:18:21.694347 03980000 ################################################################
10324 20:18:21.694551
10325 20:18:21.981208 03a00000 ################################################################
10326 20:18:21.981348
10327 20:18:22.243354 03a80000 ################################################################
10328 20:18:22.243503
10329 20:18:22.519829 03b00000 ################################################################
10330 20:18:22.519967
10331 20:18:22.797729 03b80000 ################################################################
10332 20:18:22.797869
10333 20:18:23.057988 03c00000 ################################################################
10334 20:18:23.058141
10335 20:18:23.326562 03c80000 ################################################################
10336 20:18:23.326692
10337 20:18:23.590865 03d00000 ################################################################
10338 20:18:23.591004
10339 20:18:23.864383 03d80000 ################################################################
10340 20:18:23.864522
10341 20:18:24.120045 03e00000 ################################################################
10342 20:18:24.120177
10343 20:18:24.375967 03e80000 ################################################################
10344 20:18:24.376142
10345 20:18:24.629095 03f00000 ################################################################
10346 20:18:24.629228
10347 20:18:24.898495 03f80000 ################################################################
10348 20:18:24.898691
10349 20:18:25.157759 04000000 ################################################################
10350 20:18:25.157910
10351 20:18:25.424428 04080000 ################################################################
10352 20:18:25.424596
10353 20:18:25.687444 04100000 ################################################################
10354 20:18:25.687621
10355 20:18:25.942130 04180000 ################################################################
10356 20:18:25.942267
10357 20:18:26.208845 04200000 ################################################################
10358 20:18:26.209023
10359 20:18:26.467991 04280000 ################################################################
10360 20:18:26.468156
10361 20:18:26.737518 04300000 ################################################################
10362 20:18:26.737676
10363 20:18:27.020610 04380000 ################################################################
10364 20:18:27.020745
10365 20:18:27.273434 04400000 ################################################################
10366 20:18:27.273569
10367 20:18:27.536752 04480000 ################################################################
10368 20:18:27.536887
10369 20:18:27.796400 04500000 ################################################################
10370 20:18:27.796564
10371 20:18:28.055307 04580000 ################################################################
10372 20:18:28.055445
10373 20:18:28.316422 04600000 ################################################################
10374 20:18:28.316560
10375 20:18:28.584084 04680000 ################################################################
10376 20:18:28.584247
10377 20:18:28.844089 04700000 ################################################################
10378 20:18:28.844225
10379 20:18:29.111463 04780000 ################################################################
10380 20:18:29.111628
10381 20:18:29.370496 04800000 ################################################################
10382 20:18:29.370674
10383 20:18:29.631563 04880000 ################################################################
10384 20:18:29.631756
10385 20:18:29.888093 04900000 ################################################################
10386 20:18:29.888272
10387 20:18:30.144710 04980000 ################################################################
10388 20:18:30.144872
10389 20:18:30.400587 04a00000 ################################################################
10390 20:18:30.400739
10391 20:18:30.658031 04a80000 ################################################################
10392 20:18:30.658165
10393 20:18:30.915309 04b00000 ################################################################
10394 20:18:30.915453
10395 20:18:31.174005 04b80000 ################################################################
10396 20:18:31.174140
10397 20:18:31.433914 04c00000 ################################################################
10398 20:18:31.434052
10399 20:18:31.691912 04c80000 ################################################################
10400 20:18:31.692048
10401 20:18:31.953314 04d00000 ################################################################
10402 20:18:31.953456
10403 20:18:32.215027 04d80000 ################################################################
10404 20:18:32.215164
10405 20:18:32.476574 04e00000 ################################################################
10406 20:18:32.476766
10407 20:18:32.745662 04e80000 ################################################################
10408 20:18:32.745797
10409 20:18:33.001173 04f00000 ################################################################
10410 20:18:33.001315
10411 20:18:33.257332 04f80000 ################################################################
10412 20:18:33.257492
10413 20:18:33.513427 05000000 ################################################################
10414 20:18:33.513566
10415 20:18:33.769611 05080000 ################################################################
10416 20:18:33.769756
10417 20:18:34.031946 05100000 ################################################################
10418 20:18:34.032123
10419 20:18:34.301865 05180000 ################################################################
10420 20:18:34.302010
10421 20:18:34.573820 05200000 ################################################################
10422 20:18:34.573993
10423 20:18:34.843805 05280000 ################################################################
10424 20:18:34.843973
10425 20:18:35.110065 05300000 ################################################################
10426 20:18:35.110239
10427 20:18:35.370587 05380000 ################################################################
10428 20:18:35.370797
10429 20:18:35.627764 05400000 ################################################################
10430 20:18:35.627908
10431 20:18:35.887885 05480000 ################################################################
10432 20:18:35.888088
10433 20:18:36.150590 05500000 ################################################################
10434 20:18:36.150734
10435 20:18:36.410851 05580000 ################################################################
10436 20:18:36.410999
10437 20:18:36.671578 05600000 ################################################################
10438 20:18:36.671781
10439 20:18:36.931663 05680000 ################################################################
10440 20:18:36.931840
10441 20:18:37.200245 05700000 ################################################################
10442 20:18:37.200473
10443 20:18:37.466615 05780000 ################################################################
10444 20:18:37.466762
10445 20:18:37.726893 05800000 ################################################################
10446 20:18:37.727044
10447 20:18:37.988434 05880000 ################################################################
10448 20:18:37.988584
10449 20:18:38.245374 05900000 ################################################################
10450 20:18:38.245582
10451 20:18:38.507224 05980000 ################################################################
10452 20:18:38.507367
10453 20:18:38.768923 05a00000 ################################################################
10454 20:18:38.769078
10455 20:18:39.032568 05a80000 ################################################################
10456 20:18:39.032710
10457 20:18:39.298880 05b00000 ################################################################
10458 20:18:39.299090
10459 20:18:39.561514 05b80000 ################################################################
10460 20:18:39.561644
10461 20:18:39.821184 05c00000 ################################################################
10462 20:18:39.821320
10463 20:18:40.080793 05c80000 ################################################################
10464 20:18:40.080951
10465 20:18:40.341686 05d00000 ################################################################
10466 20:18:40.341847
10467 20:18:40.602909 05d80000 ################################################################
10468 20:18:40.603039
10469 20:18:40.864387 05e00000 ################################################################
10470 20:18:40.864552
10471 20:18:41.130932 05e80000 ################################################################
10472 20:18:41.131075
10473 20:18:41.395243 05f00000 ################################################################
10474 20:18:41.395383
10475 20:18:41.657877 05f80000 ################################################################
10476 20:18:41.658020
10477 20:18:41.921477 06000000 ################################################################
10478 20:18:41.921616
10479 20:18:42.191082 06080000 ################################################################
10480 20:18:42.191225
10481 20:18:42.453907 06100000 ################################################################
10482 20:18:42.454037
10483 20:18:42.714601 06180000 ################################################################
10484 20:18:42.714767
10485 20:18:42.985745 06200000 ################################################################
10486 20:18:42.985886
10487 20:18:43.246012 06280000 ################################################################
10488 20:18:43.246157
10489 20:18:43.505855 06300000 ################################################################
10490 20:18:43.505998
10491 20:18:43.762697 06380000 ################################################################
10492 20:18:43.762854
10493 20:18:44.024639 06400000 ################################################################
10494 20:18:44.024791
10495 20:18:44.285826 06480000 ################################################################
10496 20:18:44.285973
10497 20:18:44.546833 06500000 ################################################################
10498 20:18:44.546974
10499 20:18:44.811387 06580000 ################################################################
10500 20:18:44.811588
10501 20:18:45.075642 06600000 ################################################################
10502 20:18:45.075847
10503 20:18:45.338420 06680000 ################################################################
10504 20:18:45.338624
10505 20:18:45.601973 06700000 ################################################################
10506 20:18:45.602182
10507 20:18:45.864217 06780000 ################################################################
10508 20:18:45.864392
10509 20:18:46.123939 06800000 ################################################################
10510 20:18:46.124079
10511 20:18:46.383749 06880000 ################################################################
10512 20:18:46.383894
10513 20:18:46.564880 06900000 ############################################## done.
10514 20:18:46.565010
10515 20:18:46.568212 The bootfile was 110473090 bytes long.
10516 20:18:46.568339
10517 20:18:46.571564 Sending tftp read request... done.
10518 20:18:46.571649
10519 20:18:46.574708 Waiting for the transfer...
10520 20:18:46.574817
10521 20:18:46.574927 00000000 # done.
10522 20:18:46.578469
10523 20:18:46.584985 Command line loaded dynamically from TFTP file: 12928123/tftp-deploy-6815w_fp/kernel/cmdline
10524 20:18:46.585095
10525 20:18:46.598034 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10526 20:18:46.598122
10527 20:18:46.598189 Loading FIT.
10528 20:18:46.598252
10529 20:18:46.601650 Image ramdisk-1 has 98363737 bytes.
10530 20:18:46.601732
10531 20:18:46.605320 Image fdt-1 has 47278 bytes.
10532 20:18:46.605452
10533 20:18:46.608593 Image kernel-1 has 12060038 bytes.
10534 20:18:46.608665
10535 20:18:46.617991 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10536 20:18:46.618072
10537 20:18:46.635010 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10538 20:18:46.635096
10539 20:18:46.641700 Choosing best match conf-1 for compat google,spherion-rev2.
10540 20:18:46.641777
10541 20:18:46.649015 Connected to device vid:did:rid of 1ae0:0028:00
10542 20:18:46.657056
10543 20:18:46.660233 tpm_get_response: command 0x17b, return code 0x0
10544 20:18:46.660358
10545 20:18:46.663583 ec_init: CrosEC protocol v3 supported (256, 248)
10546 20:18:46.668505
10547 20:18:46.671612 tpm_cleanup: add release locality here.
10548 20:18:46.671690
10549 20:18:46.671753 Shutting down all USB controllers.
10550 20:18:46.675409
10551 20:18:46.675496 Removing current net device
10552 20:18:46.675558
10553 20:18:46.681765 Exiting depthcharge with code 4 at timestamp: 92569925
10554 20:18:46.681840
10555 20:18:46.684999 LZMA decompressing kernel-1 to 0x821a6718
10556 20:18:46.685074
10557 20:18:46.688763 LZMA decompressing kernel-1 to 0x40000000
10558 20:18:48.188006
10559 20:18:48.188157 jumping to kernel
10560 20:18:48.188722 end: 2.2.4 bootloader-commands (duration 00:01:05) [common]
10561 20:18:48.188822 start: 2.2.5 auto-login-action (timeout 00:03:20) [common]
10562 20:18:48.188905 Setting prompt string to ['Linux version [0-9]']
10563 20:18:48.188974 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10564 20:18:48.189041 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10565 20:18:48.270462
10566 20:18:48.274148 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10567 20:18:48.278036 start: 2.2.5.1 login-action (timeout 00:03:20) [common]
10568 20:18:48.278135 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10569 20:18:48.278205 Setting prompt string to []
10570 20:18:48.278286 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10571 20:18:48.278362 Using line separator: #'\n'#
10572 20:18:48.278420 No login prompt set.
10573 20:18:48.278492 Parsing kernel messages
10574 20:18:48.278557 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10575 20:18:48.278655 [login-action] Waiting for messages, (timeout 00:03:20)
10576 20:18:48.278723 Waiting using forced prompt support (timeout 00:01:40)
10577 20:18:48.296934 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10578 20:18:48.300466 [ 0.000000] random: crng init done
10579 20:18:48.307118 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10580 20:18:48.310189 [ 0.000000] efi: UEFI not found.
10581 20:18:48.317041 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10582 20:18:48.326705 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10583 20:18:48.333551 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10584 20:18:48.343598 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10585 20:18:48.350164 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10586 20:18:48.356742 [ 0.000000] printk: bootconsole [mtk8250] enabled
10587 20:18:48.363247 [ 0.000000] NUMA: No NUMA configuration found
10588 20:18:48.369940 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10589 20:18:48.373038 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10590 20:18:48.376584 [ 0.000000] Zone ranges:
10591 20:18:48.383389 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10592 20:18:48.386978 [ 0.000000] DMA32 empty
10593 20:18:48.393267 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10594 20:18:48.396213 [ 0.000000] Movable zone start for each node
10595 20:18:48.399957 [ 0.000000] Early memory node ranges
10596 20:18:48.406093 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10597 20:18:48.413023 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10598 20:18:48.419917 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10599 20:18:48.426469 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10600 20:18:48.432935 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10601 20:18:48.439194 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10602 20:18:48.495430 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10603 20:18:48.502018 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10604 20:18:48.508828 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10605 20:18:48.511868 [ 0.000000] psci: probing for conduit method from DT.
10606 20:18:48.518358 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10607 20:18:48.522085 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10608 20:18:48.528869 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10609 20:18:48.532196 [ 0.000000] psci: SMC Calling Convention v1.2
10610 20:18:48.538829 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10611 20:18:48.542115 [ 0.000000] Detected VIPT I-cache on CPU0
10612 20:18:48.548531 [ 0.000000] CPU features: detected: GIC system register CPU interface
10613 20:18:48.555439 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10614 20:18:48.561496 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10615 20:18:48.568662 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10616 20:18:48.574986 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10617 20:18:48.581862 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10618 20:18:48.588196 [ 0.000000] alternatives: applying boot alternatives
10619 20:18:48.595401 [ 0.000000] Fallback order for Node 0: 0
10620 20:18:48.601684 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10621 20:18:48.601794 [ 0.000000] Policy zone: Normal
10622 20:18:48.618726 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10623 20:18:48.628498 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10624 20:18:48.639833 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10625 20:18:48.649695 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10626 20:18:48.656203 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10627 20:18:48.659584 <6>[ 0.000000] software IO TLB: area num 8.
10628 20:18:48.716791 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10629 20:18:48.866280 <6>[ 0.000000] Memory: 7871140K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 481628K reserved, 32768K cma-reserved)
10630 20:18:48.872485 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10631 20:18:48.879294 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10632 20:18:48.882452 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10633 20:18:48.889262 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10634 20:18:48.896093 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10635 20:18:48.899093 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10636 20:18:48.909057 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10637 20:18:48.915928 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10638 20:18:48.919159 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10639 20:18:48.926962 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10640 20:18:48.930239 <6>[ 0.000000] GICv3: 608 SPIs implemented
10641 20:18:48.937010 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10642 20:18:48.940090 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10643 20:18:48.943516 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10644 20:18:48.953407 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10645 20:18:48.963088 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10646 20:18:48.976483 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10647 20:18:48.983431 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10648 20:18:48.992724 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10649 20:18:49.005839 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10650 20:18:49.011960 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10651 20:18:49.018742 <6>[ 0.009182] Console: colour dummy device 80x25
10652 20:18:49.029084 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10653 20:18:49.032711 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10654 20:18:49.038810 <6>[ 0.029221] LSM: Security Framework initializing
10655 20:18:49.045809 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10656 20:18:49.055466 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10657 20:18:49.062478 <6>[ 0.051486] cblist_init_generic: Setting adjustable number of callback queues.
10658 20:18:49.068887 <6>[ 0.058975] cblist_init_generic: Setting shift to 3 and lim to 1.
10659 20:18:49.078984 <6>[ 0.065352] cblist_init_generic: Setting adjustable number of callback queues.
10660 20:18:49.085288 <6>[ 0.072780] cblist_init_generic: Setting shift to 3 and lim to 1.
10661 20:18:49.088877 <6>[ 0.079259] rcu: Hierarchical SRCU implementation.
10662 20:18:49.095088 <6>[ 0.079261] rcu: Max phase no-delay instances is 1000.
10663 20:18:49.102014 <6>[ 0.079286] printk: bootconsole [mtk8250] printing thread started
10664 20:18:49.109096 <6>[ 0.097582] EFI services will not be available.
10665 20:18:49.112054 <6>[ 0.097785] smp: Bringing up secondary CPUs ...
10666 20:18:49.115189 <6>[ 0.098101] Detected VIPT I-cache on CPU1
10667 20:18:49.125648 <6>[ 0.098167] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10668 20:18:49.131856 <6>[ 0.098199] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10669 20:18:49.140802 <6>[ 0.126099] Detected VIPT I-cache on CPU2
10670 20:18:49.147854 <6>[ 0.126147] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10671 20:18:49.157670 <6>[ 0.126163] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10672 20:18:49.160639 <6>[ 0.126423] Detected VIPT I-cache on CPU3
10673 20:18:49.167414 <6>[ 0.126469] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10674 20:18:49.173881 <6>[ 0.126483] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10675 20:18:49.177589 <6>[ 0.126796] CPU features: detected: Spectre-v4
10676 20:18:49.183616 <6>[ 0.126802] CPU features: detected: Spectre-BHB
10677 20:18:49.187016 <6>[ 0.126806] Detected PIPT I-cache on CPU4
10678 20:18:49.193937 <6>[ 0.126864] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10679 20:18:49.200494 <6>[ 0.126882] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10680 20:18:49.206877 <6>[ 0.127178] Detected PIPT I-cache on CPU5
10681 20:18:49.213745 <6>[ 0.127236] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10682 20:18:49.220487 <6>[ 0.127251] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10683 20:18:49.223317 <6>[ 0.127527] Detected PIPT I-cache on CPU6
10684 20:18:49.230221 <6>[ 0.127595] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10685 20:18:49.240135 <6>[ 0.127610] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10686 20:18:49.243166 <6>[ 0.127902] Detected PIPT I-cache on CPU7
10687 20:18:49.249715 <6>[ 0.127966] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10688 20:18:49.257073 <6>[ 0.127982] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10689 20:18:49.259504 <6>[ 0.128028] smp: Brought up 1 node, 8 CPUs
10690 20:18:49.266912 <6>[ 0.128033] SMP: Total of 8 processors activated.
10691 20:18:49.269711 <6>[ 0.128036] CPU features: detected: 32-bit EL0 Support
10692 20:18:49.279752 <6>[ 0.128038] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10693 20:18:49.286572 <6>[ 0.128040] CPU features: detected: Common not Private translations
10694 20:18:49.293393 <6>[ 0.128042] CPU features: detected: CRC32 instructions
10695 20:18:49.296475 <6>[ 0.128045] CPU features: detected: RCpc load-acquire (LDAPR)
10696 20:18:49.303030 <6>[ 0.128047] CPU features: detected: LSE atomic instructions
10697 20:18:49.309962 <6>[ 0.128048] CPU features: detected: Privileged Access Never
10698 20:18:49.316557 <6>[ 0.128050] CPU features: detected: RAS Extension Support
10699 20:18:49.322912 <6>[ 0.128053] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10700 20:18:49.326360 <6>[ 0.128117] CPU: All CPU(s) started at EL2
10701 20:18:49.333034 <6>[ 0.128119] alternatives: applying system-wide alternatives
10702 20:18:49.336143 <6>[ 0.141223] devtmpfs: initialized
10703 20:18:49.357734 ��
10704 20:18:49.368275 ͡�������*��ɥ������Bzɑ�Ɂ�b��ʲ�ѕͥjR�<6>[ 0.355643] print<k: console [ttyS0] printing thread started
10705 20:18:49.371364 6<6>[ 0.355673] printk: console [ttyS0] enabled
10706 20:18:49.374866 >[ 0.225751] pnp: PnP ACPI: disabled
10707 20:18:49.383255 <6>[ 0.355676] printk: bootconsole [mtk8250] disabled
10708 20:18:49.390309 <6>[ 0.369656] printk: bootconsole [mtk8250] printing thread stopped
10709 20:18:49.393313 <6>[ 0.370869] SuperH (H)SCI(F) driver initialized
10710 20:18:49.399751 <6>[ 0.371336] msm_serial: driver initialized
10711 20:18:49.406395 <6>[ 0.375925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10712 20:18:49.416337 <6>[ 0.375955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10713 20:18:49.423273 <6>[ 0.375984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10714 20:18:49.438019 <6>[ 0.376014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10715 20:18:49.446386 <6>[ 0.376035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10716 20:18:49.452243 <6>[ 0.376062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10717 20:18:49.468996 <6>[ 0.376090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10718 20:18:49.469390 <6>[ 0.376214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10719 20:18:49.482776 <6>[ 0.376244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10720 20:18:49.482860 <6>[ 0.388657] loop: module loaded
10721 20:18:49.490700 <6>[ 0.391199] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10722 20:18:49.493929 <4>[ 0.407771] mtk-pmic-keys: Failed to locate of_node [id: -1]
10723 20:18:49.497714 <6>[ 0.408658] megasas: 07.719.03.00-rc1
10724 20:18:49.500829 <6>[ 0.420931] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10725 20:18:49.507717 <6>[ 0.421062] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10726 20:18:49.514284 <6>[ 0.433103] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10727 20:18:49.523920 <6>[ 0.487411] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10728 20:18:53.271177 <6>[ 4.259006] Freeing initrd memory: 96052K
10729 20:18:53.277401 <6>[ 4.265174] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10730 20:18:53.280953 <6>[ 4.270097] tun: Universal TUN/TAP device driver, 1.6
10731 20:18:53.284407 <6>[ 4.270852] thunder_xcv, ver 1.0
10732 20:18:53.287686 <6>[ 4.270871] thunder_bgx, ver 1.0
10733 20:18:53.290719 <6>[ 4.270887] nicpf, ver 1.0
10734 20:18:53.300571 <6>[ 4.271950] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10735 20:18:53.303642 <6>[ 4.271954] hns3: Copyright (c) 2017 Huawei Corporation.
10736 20:18:53.307213 <6>[ 4.271980] hclge is initializing
10737 20:18:53.313543 <6>[ 4.271994] e1000: Intel(R) PRO/1000 Network Driver
10738 20:18:53.320509 <6>[ 4.271996] e1000: Copyright (c) 1999-2006 Intel Corporation.
10739 20:18:53.324723 <6>[ 4.272016] e1000e: Intel(R) PRO/1000 Network Driver
10740 20:18:53.332429 <6>[ 4.272017] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10741 20:18:53.336213 <6>[ 4.272034] igb: Intel(R) Gigabit Ethernet Network Driver
10742 20:18:53.342901 <6>[ 4.272037] igb: Copyright (c) 2007-2014 Intel Corporation.
10743 20:18:53.349595 <6>[ 4.272051] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10744 20:18:53.356856 <6>[ 4.272053] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10745 20:18:53.360402 <6>[ 4.272344] sky2: driver version 1.30
10746 20:18:53.363520 <6>[ 4.273413] VFIO - User Level meta-driver version: 0.3
10747 20:18:53.370397 <6>[ 4.276225] usbcore: registered new interface driver usb-storage
10748 20:18:53.376875 <6>[ 4.276404] usbcore: registered new device driver onboard-usb-hub
10749 20:18:53.383224 <6>[ 4.279188] mt6397-rtc mt6359-rtc: registered as rtc0
10750 20:18:53.390003 <6>[ 4.279346] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:16:04 UTC (1709496964)
10751 20:18:53.396770 <6>[ 4.279959] i2c_dev: i2c /dev entries driver
10752 20:18:53.403384 <6>[ 4.287264] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10753 20:18:53.409582 <6>[ 4.303250] cpu cpu0: EM: created perf domain
10754 20:18:53.412841 <6>[ 4.303604] cpu cpu4: EM: created perf domain
10755 20:18:53.419863 <6>[ 4.309194] sdhci: Secure Digital Host Controller Interface driver
10756 20:18:53.422838 <6>[ 4.309196] sdhci: Copyright(c) Pierre Ossman
10757 20:18:53.429580 <6>[ 4.309546] Synopsys Designware Multimedia Card Interface Driver
10758 20:18:53.436407 <6>[ 4.309932] sdhci-pltfm: SDHCI platform and OF driver helper
10759 20:18:53.442613 <6>[ 4.315129] ledtrig-cpu: registered to indicate activity on CPUs
10760 20:18:53.446408 <6>[ 4.315622] mmc0: CQHCI version 5.10
10761 20:18:53.452985 <6>[ 4.316107] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10762 20:18:53.459184 <6>[ 4.316383] usbcore: registered new interface driver usbhid
10763 20:18:53.462673 <6>[ 4.316385] usbhid: USB HID core driver
10764 20:18:53.469477 <6>[ 4.316496] spi_master spi0: will run message pump with realtime priority
10765 20:18:53.482523 <6>[ 4.347536] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10766 20:18:53.495949 <6>[ 4.349396] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10767 20:18:53.502559 <6>[ 4.351620] cros-ec-spi spi0.0: Chrome EC device registered
10768 20:18:53.512599 <6>[ 4.363501] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10769 20:18:53.515546 <6>[ 4.364505] NET: Registered PF_PACKET protocol family
10770 20:18:53.519012 <6>[ 4.364583] 9pnet: Installing 9P2000 support
10771 20:18:53.525872 <5>[ 4.364614] Key type dns_resolver registered
10772 20:18:53.529184 <6>[ 4.364945] registered taskstats version 1
10773 20:18:53.535636 <5>[ 4.364958] Loading compiled-in X.509 certificates
10774 20:18:53.545508 <4>[ 4.380552] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10775 20:18:53.555252 <4>[ 4.380807] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10776 20:18:53.562094 <3>[ 4.380827] debugfs: File 'uA_load' in directory '/' already present!
10777 20:18:53.568768 <3>[ 4.380837] debugfs: File 'min_uV' in directory '/' already present!
10778 20:18:53.575560 <3>[ 4.380844] debugfs: File 'max_uV' in directory '/' already present!
10779 20:18:53.582260 <3>[ 4.380851] debugfs: File 'constraint_flags' in directory '/' already present!
10780 20:18:53.592148 <3>[ 4.384442] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10781 20:18:53.598849 <6>[ 4.394060] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10782 20:18:53.601850 <6>[ 4.394647] xhci-mtk 11200000.usb: xHCI Host Controller
10783 20:18:53.611812 <6>[ 4.394667] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10784 20:18:53.621915 <6>[ 4.394883] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10785 20:18:53.625094 <6>[ 4.394927] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10786 20:18:53.631615 <6>[ 4.395018] xhci-mtk 11200000.usb: xHCI Host Controller
10787 20:18:53.638339 <6>[ 4.395025] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10788 20:18:53.647980 <6>[ 4.395031] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10789 20:18:53.651635 <6>[ 4.395796] hub 1-0:1.0: USB hub found
10790 20:18:53.654677 <6>[ 4.395901] hub 1-0:1.0: 1 port detected
10791 20:18:53.665031 <6>[ 4.396243] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10792 20:18:53.668102 <6>[ 4.396474] hub 2-0:1.0: USB hub found
10793 20:18:53.671193 <6>[ 4.396493] hub 2-0:1.0: 1 port detected
10794 20:18:53.674668 <6>[ 4.399292] mtk-msdc 11f70000.mmc: Got CD GPIO
10795 20:18:53.684689 <6>[ 4.406696] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10796 20:18:53.691230 <6>[ 4.406704] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10797 20:18:53.701235 <4>[ 4.406777] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10798 20:18:53.707629 <6>[ 4.407268] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10799 20:18:53.717544 <6>[ 4.407269] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10800 20:18:53.724249 <6>[ 4.407558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10801 20:18:53.731100 <6>[ 4.407570] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10802 20:18:53.740729 <6>[ 4.407574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10803 20:18:53.750984 <6>[ 4.407579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10804 20:18:53.757277 <6>[ 4.408822] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10805 20:18:53.767653 <6>[ 4.408833] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10806 20:18:53.774285 <6>[ 4.408835] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10807 20:18:53.783917 <6>[ 4.408837] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10808 20:18:53.790738 <6>[ 4.408840] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10809 20:18:53.800762 <6>[ 4.408843] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10810 20:18:53.807103 <6>[ 4.408845] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10811 20:18:53.817504 <6>[ 4.408848] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10812 20:18:53.824111 <6>[ 4.408851] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10813 20:18:53.833950 <6>[ 4.408854] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10814 20:18:53.840678 <6>[ 4.408857] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10815 20:18:53.850158 <6>[ 4.408859] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10816 20:18:53.856930 <6>[ 4.408862] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10817 20:18:53.867117 <6>[ 4.408864] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10818 20:18:53.873205 <6>[ 4.408866] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10819 20:18:53.880100 <6>[ 4.409182] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10820 20:18:53.886464 <6>[ 4.409897] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10821 20:18:53.893501 <6>[ 4.410142] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10822 20:18:53.900184 <6>[ 4.410388] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10823 20:18:53.906956 <6>[ 4.410637] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10824 20:18:53.916800 <6>[ 4.410791] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10825 20:18:53.926654 <6>[ 4.410803] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10826 20:18:53.936691 <6>[ 4.410806] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10827 20:18:53.942904 <6>[ 4.410810] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10828 20:18:53.953266 <6>[ 4.410814] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10829 20:18:53.962891 <6>[ 4.410817] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10830 20:18:53.972563 <6>[ 4.410820] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10831 20:18:53.982649 <6>[ 4.410825] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10832 20:18:53.989620 <6>[ 4.410829] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10833 20:18:53.999596 <6>[ 4.410834] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10834 20:18:54.012594 <6>[ 4.410837] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10835 20:18:54.018988 <6>[ 4.411567] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10836 20:18:54.025597 <6>[ 4.414953] mmc0: Command Queue Engine enabled
10837 20:18:54.029231 <6>[ 4.414966] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10838 20:18:54.035953 <6>[ 4.415407] mmcblk0: mmc0:0001 DA4128 116 GiB
10839 20:18:54.042393 <6>[ 4.418414] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10840 20:18:54.045509 <6>[ 4.419444] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10841 20:18:54.052244 <6>[ 4.419996] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10842 20:18:54.058963 <6>[ 4.420516] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10843 20:18:54.065533 <6>[ 4.745888] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10844 20:18:54.068939 <6>[ 4.776648] hub 2-1:1.0: USB hub found
10845 20:18:54.071969 <6>[ 4.777058] hub 2-1:1.0: 3 ports detected
10846 20:18:54.078900 <6>[ 4.779004] hub 2-1:1.0: USB hub found
10847 20:18:54.082095 <6>[ 4.779301] hub 2-1:1.0: 3 ports detected
10848 20:18:54.088835 <6>[ 4.905631] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10849 20:18:54.091747 <6>[ 5.058593] hub 1-1:1.0: USB hub found
10850 20:18:54.094915 <6>[ 5.058993] hub 1-1:1.0: 4 ports detected
10851 20:18:54.101602 <6>[ 5.062054] hub 1-1:1.0: USB hub found
10852 20:18:54.104999 <6>[ 5.062461] hub 1-1:1.0: 4 ports detected
10853 20:18:54.150647 <6>[ 5.133791] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10854 20:18:54.390056 <6>[ 5.373804] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10855 20:18:54.514555 <6>[ 5.501825] hub 1-1.4:1.0: USB hub found
10856 20:18:54.518255 <6>[ 5.502283] hub 1-1.4:1.0: 2 ports detected
10857 20:18:54.521264 <6>[ 5.505889] hub 1-1.4:1.0: USB hub found
10858 20:18:54.527851 <6>[ 5.506244] hub 1-1.4:1.0: 2 ports detected
10859 20:18:54.810168 <6>[ 5.793792] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10860 20:18:54.994013 <6>[ 5.977794] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10861 20:19:05.714359 <6>[ 16.707174] ALSA device list:
10862 20:19:05.721055 <6>[ 16.707197] No soundcards found.
10863 20:19:05.724649 <6>[ 16.711599] Freeing unused kernel memory: 8448K
10864 20:19:05.727915 <6>[ 16.711750] Run /init as init process
10865 20:19:05.769883 <6>[ 16.758142] NET: Registered PF_INET6 protocol family
10866 20:19:05.773020 <6>[ 16.759599] Segment Routing with IPv6
10867 20:19:05.779781 <6>[ 16.759623] In-situ OAM (IOAM) with IPv6
10868 20:19:05.802898 <30>[ 16.776987] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10869 20:19:05.809498 <30>[ 16.777587] systemd[1]: Detected architecture arm64.
10870 20:19:05.809580
10871 20:19:05.812702 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10872 20:19:05.812788
10873 20:19:05.833689 <30>[ 16.821963] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10874 20:19:05.981106 <30>[ 16.965569] systemd[1]: Queued start job for default target Graphical Interface.
10875 20:19:06.013099 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.998402] systemd[1]: Created slice system-getty.slice.
10876 20:19:06.013199 m-getty.slice[0m.
10877 20:19:06.037151 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 17.022389] systemd[1]: Created slice system-modprobe.slice.
10878 20:19:06.037234 m-modprobe.slice[0m.
10879 20:19:06.061262 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 17.046542] systemd[1]: Created slice system-serial\x2dgetty.slice.
10880 20:19:06.065067 m-serial\x2dgetty.slice[0m.
10881 20:19:06.082719 [[0;32m OK [0m] Created slic<30>[ 17.070987] systemd[1]: Created slice User and Session Slice.
10882 20:19:06.085530 e [0;1;39mUser and Session Slice[0m.
10883 20:19:06.109822 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 17.094565] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10884 20:19:06.112553 ssword …ts to Console Directory Watch[0m.
10885 20:19:06.137515 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 17.122530] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10886 20:19:06.140600 sword R…uests to Wall Directory Watch[0m.
10887 20:19:06.168513 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 17.150342] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10888 20:19:06.175387 <30>[ 17.150587] systemd[1]: Reached target Local Encrypted Volumes.
10889 20:19:06.178314 l Encrypted Volumes[0m.
10890 20:19:06.198234 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 17.186322] systemd[1]: Reached target Paths.
10891 20:19:06.198315 s[0m.
10892 20:19:06.220347 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 17.205794] systemd[1]: Reached target Remote File Systems.
10893 20:19:06.220431 te File Systems[0m.
10894 20:19:06.237137 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 17.225776] systemd[1]: Reached target Slices.
10895 20:19:06.237219 es[0m.
10896 20:19:06.256929 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 17.245796] systemd[1]: Reached target Swap.
10897 20:19:06.257012 [0m.
10898 20:19:06.280838 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 17.266298] systemd[1]: Listening on initctl Compatibility Named Pipe.
10899 20:19:06.284502 l Compatibility Named Pipe[0m.
10900 20:19:06.305237 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 17.290635] systemd[1]: Listening on Journal Audit Socket.
10901 20:19:06.305319 l Audit Socket[0m.
10902 20:19:06.326387 [[0;32m OK [0m] Listening on<30>[ 17.314958] systemd[1]: Listening on Journal Socket (/dev/log).
10903 20:19:06.330057 [0;1;39mJournal Socket (/dev/log)[0m.
10904 20:19:06.350557 [[0;32m OK [0m] Listening on<30>[ 17.338986] systemd[1]: Listening on Journal Socket.
10905 20:19:06.353808 [0;1;39mJournal Socket[0m.
10906 20:19:06.369880 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 17.358352] systemd[1]: Listening on udev Control Socket.
10907 20:19:06.372910 ontrol Socket[0m.
10908 20:19:06.394383 [[0;32m OK [0m] Listening on<30>[ 17.382848] systemd[1]: Listening on udev Kernel Socket.
10909 20:19:06.397415 [0;1;39mudev Kernel Socket[0m.
10910 20:19:06.453786 Mounting [0;1;39mHuge Pages File Syste<30>[ 17.442023] systemd[1]: Mounting Huge Pages File System...
10911 20:19:06.456658 m[0m...
10912 20:19:06.480616 Mounting [0;1;39mPOSIX Message Queue F<30>[ 17.465748] systemd[1]: Mounting POSIX Message Queue File System...
10913 20:19:06.480701 ile System[0m...
10914 20:19:06.508634 Mounting [0;1;39mKernel Debug File Sys<30>[ 17.493790] systemd[1]: Mounting Kernel Debug File System...
10915 20:19:06.508765 tem[0m...
10916 20:19:06.530963 Startin<30>[ 17.513972] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10917 20:19:06.537642 <30>[ 17.516381] systemd[1]: Starting Create list of static device nodes for the current kernel...
10918 20:19:06.544057 g [0;1;39mCreate list of st…odes for the current kernel[0m...
10919 20:19:06.568934 Starting [0;1;39mLoad Kernel Module co<30>[ 17.553977] systemd[1]: Starting Load Kernel Module configfs...
10920 20:19:06.569042 nfigfs[0m...
10921 20:19:06.592053 Starting [0;1;39mLoad Kernel Module dr<30>[ 17.577607] systemd[1]: Starting Load Kernel Module drm...
10922 20:19:06.592138 m[0m...
10923 20:19:06.612547 <30>[ 17.597955] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10924 20:19:06.662161 Starting [0;1;39mJournal Service[0m..<30>[ 17.650491] systemd[1]: Starting Journal Service...
10925 20:19:06.662298 .
10926 20:19:06.683504 Starting [0;1;39mLoad <30>[ 17.672024] systemd[1]: Starting Load Kernel Modules...
10927 20:19:06.686673 Kernel Modules[0m...
10928 20:19:06.712200 Starting [0;1;39mRemount Root and Kern<30>[ 17.697732] systemd[1]: Starting Remount Root and Kernel File Systems...
10929 20:19:06.715417 el File Systems[0m...
10930 20:19:06.740554 Starting [0;1;39mColdplug All udev Dev<30>[ 17.725492] systemd[1]: Starting Coldplug All udev Devices...
10931 20:19:06.740637 ices[0m...
10932 20:19:06.762683 [[0;32m OK [0m] Started [0;<30>[ 17.751581] systemd[1]: Started Journal Service.
10933 20:19:06.765959 1;39mJournal Service[0m.
10934 20:19:06.780716 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10935 20:19:06.798495 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10936 20:19:06.814495 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10937 20:19:06.834584 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10938 20:19:06.851190 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10939 20:19:06.867561 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10940 20:19:06.882301 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10941 20:19:06.902166 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10942 20:19:06.917541 See 'systemctl status systemd-remount-fs.service' for details.
10943 20:19:06.965056 Mounting [0;1;39mKernel Configuration File System[0m...
10944 20:19:06.986351 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10945 20:19:07.001090 <46>[ 17.988650] systemd-journald[190]: Received client request to flush runtime journal.
10946 20:19:07.011628 Starting [0;1;39mLoad/Save Random Seed[0m...
10947 20:19:07.030789 Starting [0;1;39mApply Kernel Variables[0m...
10948 20:19:07.050486 Starting [0;1;39mCreate System Users[0m...
10949 20:19:07.071504 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10950 20:19:07.086393 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10951 20:19:07.106743 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10952 20:19:07.119556 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10953 20:19:07.135643 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10954 20:19:07.151661 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10955 20:19:07.210613 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10956 20:19:07.230341 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10957 20:19:07.242071 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10958 20:19:07.257600 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10959 20:19:07.306467 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10960 20:19:07.330667 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10961 20:19:07.352418 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10962 20:19:07.371341 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10963 20:19:07.392822 Starting [0;1;39mNetwork Time Synchronization[0m...
10964 20:19:07.414522 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10965 20:19:07.454774 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10966 20:19:07.473214 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10967 20:19:07.492206 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10968 20:19:07.517786 [[0;32m OK [0m] Started [0;<6>[ 18.501906] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10969 20:19:07.524592 1;39mDaily Clean<6>[ 18.506291] remoteproc remoteproc0: scp is available
10970 20:19:07.530964 up of Temporary <6>[ 18.506446] remoteproc remoteproc0: powering up scp
10971 20:19:07.538010 Directories[0m.<6>[ 18.506452] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10972 20:19:07.540996
10973 20:19:07.544167 <6>[ 18.506475] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10974 20:19:07.554164 <6>[ 18.522540] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10975 20:19:07.561011 <6>[ 18.522583] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10976 20:19:07.570953 <6>[ 18.522591] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10977 20:19:07.577526 <6>[ 18.542534] usbcore: registered new device driver r8152-cfgselector
10978 20:19:07.580912 <6>[ 18.556819] mc: Linux media interface: v0.10
10979 20:19:07.587512 <6>[ 18.578218] videodev: Linux video capture interface: v2.00
10980 20:19:07.593796 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10981 20:19:07.606086 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10982 20:19:07.616626 <4>[ 18.604010] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10983 20:19:07.623604 <4>[ 18.608595] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10984 20:19:07.629853 <3>[ 18.609931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10985 20:19:07.639745 <3>[ 18.609949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 20:19:07.646610 <3>[ 18.609959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10987 20:19:07.656078 <3>[ 18.616956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10988 20:19:07.662974 <3>[ 18.616976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10989 20:19:07.673040 <3>[ 18.616984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10990 20:19:07.679859 <3>[ 18.616994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10991 20:19:07.686124 <3>[ 18.617002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 20:19:07.696147 <3>[ 18.633156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 20:19:07.706339 [[0;32m OK [<6>[ 18.633845] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10994 20:19:07.712627 <6>[ 18.633849] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10995 20:19:07.719618 <6>[ 18.633855] remoteproc remoteproc0: remote processor scp is now up
10996 20:19:07.726531 <3>[ 18.642302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10997 20:19:07.736638 <3>[ 18.642323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10998 20:19:07.746243 0m] Started [0;<3>[ 18.642331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10999 20:19:07.756147 1;39mDiscard unu<3>[ 18.658315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11000 20:19:07.762550 sed blocks once <3>[ 18.658358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11001 20:19:07.766151 a week[0m.
11002 20:19:07.773028 <3>[ 18.658361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11003 20:19:07.779863 <3>[ 18.658370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11004 20:19:07.789759 <3>[ 18.658373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11005 20:19:07.797015 <3>[ 18.659092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 20:19:07.803986 <6>[ 18.664334] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11007 20:19:07.810545 <6>[ 18.664347] pci_bus 0000:00: root bus resource [bus 00-ff]
11008 20:19:07.817433 <6>[ 18.664355] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11009 20:19:07.827360 <6>[ 18.664360] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11010 20:19:07.834776 [[0;32m OK [<6>[ 18.664400] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11011 20:19:07.844902 0m] Reached targ<6>[ 18.664420] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11012 20:19:07.848071 et [0;1;39mTime<6>[ 18.664497] pci 0000:00:00.0: supports D1 D2
11013 20:19:07.854875 <6>[ 18.664500] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11014 20:19:07.864668 <6>[ 18.682105] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11015 20:19:07.864750 rs[0m.
11016 20:19:07.871612 <6>[ 18.684837] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11017 20:19:07.878774 <6>[ 18.684880] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11018 20:19:07.885154 <6>[ 18.684899] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11019 20:19:07.895236 <6>[ 18.684915] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11020 20:19:07.901477 [[0;32m OK [0m] Listening on<6>[ 18.685029] pci 0000:01:00.0: supports D1 D2
11021 20:19:07.908602 [0;1;39mD-Bus <6>[ 18.685031] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11022 20:19:07.918805 System Message B<6>[ 18.703412] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11023 20:19:07.921328 us Socket[0m.
11024 20:19:07.928076 <6>[ 18.705761] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11025 20:19:07.935065 <6>[ 18.705802] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11026 20:19:07.944865 <6>[ 18.705805] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11027 20:19:07.951986 <6>[ 18.705815] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11028 20:19:07.958153 <6>[ 18.705827] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11029 20:19:07.968120 <6>[ 18.705841] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11030 20:19:07.975034 [[0;32m OK [<6>[ 18.705854] pci 0000:00:00.0: PCI bridge to [bus 01]
11031 20:19:07.985474 0m] Reached targ<6>[ 18.705859] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11032 20:19:07.992686 et [0;1;39mSock<6>[ 18.708597] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11033 20:19:07.992781 ets[0m.
11034 20:19:07.999761 <6>[ 18.709990] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11035 20:19:08.003066 <6>[ 18.710279] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11036 20:19:08.014182 <6>[ 18.710299] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11037 20:19:08.024322 <6>[ 18.714061] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11038 20:19:08.030915 <6>[ 18.724639] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11039 20:19:08.041992 [[0;32m OK [<6>[ 18.726975] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11040 20:19:08.052423 0m] Reached targ<4>[ 18.728826] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11041 20:19:08.062567 et [0;1;39mBasi<4>[ 18.728851] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11042 20:19:08.068805 <4>[ 18.757371] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11043 20:19:08.076418 <4>[ 18.757371] Fallback method does not support PEC.
11044 20:19:08.076500 c System[0m.
11045 20:19:08.086422 <3>[ 18.775624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11046 20:19:08.089831 <6>[ 18.791598] r8152 2-1.3:1.0 eth0: v1.12.13
11047 20:19:08.096975 <6>[ 18.795614] usbcore: registered new interface driver r8152
11048 20:19:08.099984 <6>[ 18.796886] Bluetooth: Core ver 2.22
11049 20:19:08.103820 <6>[ 18.798182] NET: Registered PF_BLUETOOTH protocol family
11050 20:19:08.110010 <6>[ 18.798192] Bluetooth: HCI device and connection manager initialized
11051 20:19:08.117415 <6>[ 18.798231] Bluetooth: HCI socket layer initialized
11052 20:19:08.120831 <6>[ 18.798241] Bluetooth: L2CAP socket layer initialized
11053 20:19:08.127231 <6>[ 18.798285] Bluetooth: SCO socket layer initialized
11054 20:19:08.137399 <3>[ 18.798747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11055 20:19:08.140222 <6>[ 18.825749] usbcore: registered new interface driver cdc_ether
11056 20:19:08.150238 <3>[ 18.831969] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 20:19:08.160530 <3>[ 18.873052] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 20:19:08.166908 <6>[ 18.879704] usbcore: registered new interface driver r8153_ecm
11059 20:19:08.170244 <6>[ 18.898911] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11060 20:19:08.180511 <6>[ 18.902017] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11061 20:19:08.186865 <3>[ 18.921717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11062 20:19:08.200178 <6>[ 18.945978] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11063 20:19:08.206765 <6>[ 18.949624] usbcore: registered new interface driver uvcvideo
11064 20:19:08.213587 <6>[ 18.958876] usbcore: registered new interface driver btusb
11065 20:19:08.223740 <4>[ 18.960622] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11066 20:19:08.229891 <3>[ 18.960636] Bluetooth: hci0: Failed to load firmware file (-2)
11067 20:19:08.233015 <3>[ 18.960639] Bluetooth: hci0: Failed to set up firmware (-2)
11068 20:19:08.243185 <4>[ 18.960641] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11069 20:19:08.253030 <6>[ 18.960729] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11070 20:19:08.260626 <6>[ 18.963388] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11071 20:19:08.266168 <6>[ 18.965092] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11072 20:19:08.276156 <3>[ 18.986894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11073 20:19:08.286404 <3>[ 18.987722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11074 20:19:08.292569 <3>[ 18.990216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11075 20:19:08.302592 <3>[ 19.011166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11076 20:19:08.313116 <3>[ 19.032736] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11077 20:19:08.319363 <5>[ 19.045239] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11078 20:19:08.326154 <5>[ 19.057213] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11079 20:19:08.332432 <5>[ 19.057451] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11080 20:19:08.342857 <4>[ 19.057551] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11081 20:19:08.349196 <6>[ 19.057562] cfg80211: failed to load regulatory.db
11082 20:19:08.356042 <6>[ 19.151115] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11083 20:19:08.362756 <6>[ 19.151224] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11084 20:19:08.366191 <6>[ 19.169729] mt7921e 0000:01:00.0: ASIC revision: 79610010
11085 20:19:08.375943 <6>[ 19.264451] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11086 20:19:08.378985 <6>[ 19.264451]
11087 20:19:08.390367 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11088 20:19:08.419906 Starting [0;1;39mUser Login Management[0m...
11089 20:19:08.436973 Starting [0;1;39mPermit User Sessions[0m...
11090 20:19:08.464538 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11091 20:19:08.509905 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11092 20:19:08.536961 <6>[ 19.523954] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11093 20:19:08.554100 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11094 20:19:08.708567 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11095 20:19:08.722073 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11096 20:19:08.745756 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11097 20:19:08.786774 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11098 20:19:08.807292 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11099 20:19:08.823027 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11100 20:19:08.838161 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11101 20:19:08.854353 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11102 20:19:08.906520 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11103 20:19:08.927151 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11104 20:19:08.952079 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11105 20:19:09.007288 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11106 20:19:09.027534 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11107 20:19:09.055221 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11108 20:19:09.094470
11109 20:19:09.094607
11110 20:19:09.097652 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11111 20:19:09.097777
11112 20:19:09.100640 debian-bullseye-arm64 login: root (automatic login)
11113 20:19:09.100761
11114 20:19:09.100877
11115 20:19:09.117071 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
11116 20:19:09.117202
11117 20:19:09.123804 The programs included with the Debian GNU/Linux system are free software;
11118 20:19:09.129890 the exact distribution terms for each program are described in the
11119 20:19:09.133208 individual files in /usr/share/doc/*/copyright.
11120 20:19:09.133336
11121 20:19:09.140143 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11122 20:19:09.143344 permitted by applicable law.
11123 20:19:09.144009 Matched prompt #10: / #
11125 20:19:09.144360 Setting prompt string to ['/ #']
11126 20:19:09.144493 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11128 20:19:09.144789 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11129 20:19:09.144917 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11130 20:19:09.145014 Setting prompt string to ['/ #']
11131 20:19:09.145102 Forcing a shell prompt, looking for ['/ #']
11133 20:19:09.195405 / #
11134 20:19:09.195507 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11135 20:19:09.195607 Waiting using forced prompt support (timeout 00:02:30)
11136 20:19:09.200140
11137 20:19:09.200435 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11138 20:19:09.200528 start: 2.2.7 export-device-env (timeout 00:02:59) [common]
11139 20:19:09.200620 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11140 20:19:09.200706 end: 2.2 depthcharge-retry (duration 00:02:01) [common]
11141 20:19:09.200797 end: 2 depthcharge-action (duration 00:02:01) [common]
11142 20:19:09.200884 start: 3 lava-test-retry (timeout 00:05:00) [common]
11143 20:19:09.200964 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11144 20:19:09.201039 Using namespace: common
11146 20:19:09.301370 / # #
11147 20:19:09.301489 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11148 20:19:09.307028 #
11149 20:19:09.307294 Using /lava-12928123
11151 20:19:09.407630 / # export SHELL=/bin/sh
11152 20:19:09.407781 export SHELL=/bin/sh<6>[ 20.369853] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11153 20:19:09.412618
11155 20:19:09.513132 / # . /lava-12928123/environment
11156 20:19:09.518024 . /lava-12928123/environment
11158 20:19:09.618524 / # /lava-12928123/bin/lava-test-runner /lava-12928123/0
11159 20:19:09.618634 Test shell timeout: 10s (minimum of the action and connection timeout)
11160 20:19:09.624196 /lava-12928123/bin/lava-test-runner /lava-12928123/0
11161 20:19:09.644027 + export TESTRUN_ID=0_sleep
11162 20:19:09.647154 + cd /lava-12928123/0/tests/0_sleep
11163 20:19:09.650302 + cat uuid
11164 20:19:09.650385 + UUID=12928123_1.5.2.3.1
11165 20:19:09.654125 + set +x
11166 20:19:09.657204 <LAVA_SIGNAL_STARTRUN 0_sleep 12928123_1.5.2.3.1>
11167 20:19:09.657463 Received signal: <STARTRUN> 0_sleep 12928123_1.5.2.3.1
11168 20:19:09.657537 Starting test lava.0_sleep (12928123_1.5.2.3.1)
11169 20:19:09.657618 Skipping test definition patterns.
11170 20:19:09.660214 + ./config/lava/sleep/sleep.sh mem
11171 20:19:09.663428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11172 20:19:09.663680 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11174 20:19:09.670672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11175 20:19:09.670923 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11177 20:19:09.673793 rtcwake: assuming RTC uses UTC ...
11178 20:19:09.680149 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:16:26 2024
11179 20:19:09.683999 <6>[ 20.675926] PM: suspend entry (deep)
11180 20:19:09.686925 <6>[ 20.675972] Filesystems sync: 0.000 seconds
11181 20:19:09.693520 <6>[ 20.678786] Freezing user space processes
11182 20:19:09.712895 <6>[ 20.697836] Freezing user space processes completed (elapsed 0.019 seconds)
11183 20:19:09.715811 <6>[ 20.697851] OOM killer disabled.
11184 20:19:09.719420 <6>[ 20.697854] Freezing remaining freezable tasks
11185 20:19:09.726108 <6>[ 20.699261] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11186 20:19:09.735751 <6>[ 20.699273] printk: Suspending console(s) (use no_console_suspend to debug)
11187 20:19:15.284378 <6>[ 20.921531] Disabling non-boot CPUs ...
11188 20:19:15.287557 <4>[ 20.922473] IRQ282: set affinity failed(-22).
11189 20:19:15.291150 <4>[ 20.922488] IRQ284: set affinity failed(-22).
11190 20:19:15.297359 <6>[ 20.922574] psci: CPU1 killed (polled 0 ms)
11191 20:19:15.300634 <4>[ 20.923760] IRQ282: set affinity failed(-22).
11192 20:19:15.307573 <4>[ 20.923770] IRQ284: set affinity failed(-22).
11193 20:19:15.310642 <6>[ 20.923828] psci: CPU2 killed (polled 0 ms)
11194 20:19:15.314362 <4>[ 20.925033] IRQ282: set affinity failed(-22).
11195 20:19:15.321155 <4>[ 20.925044] IRQ284: set affinity failed(-22).
11196 20:19:15.324026 <6>[ 20.925101] psci: CPU3 killed (polled 0 ms)
11197 20:19:15.327253 <4>[ 20.925959] IRQ282: set affinity failed(-22).
11198 20:19:15.334180 <4>[ 20.925964] IRQ284: set affinity failed(-22).
11199 20:19:15.337503 <6>[ 20.926011] psci: CPU4 killed (polled 0 ms)
11200 20:19:15.344120 <4>[ 20.927006] IRQ282: set affinity failed(-22).
11201 20:19:15.347299 <4>[ 20.927014] IRQ284: set affinity failed(-22).
11202 20:19:15.350613 <6>[ 20.927081] psci: CPU5 killed (polled 0 ms)
11203 20:19:15.357512 <6>[ 20.927965] psci: CPU6 killed (polled 0 ms)
11204 20:19:15.360955 <6>[ 20.928714] psci: CPU7 killed (polled 0 ms)
11205 20:19:15.364544 <6>[ 20.930116] Enabling non-boot CPUs ...
11206 20:19:15.367294 <6>[ 20.930354] Detected VIPT I-cache on CPU1
11207 20:19:15.377807 <6>[ 20.930441] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11208 20:19:15.384065 <6>[ 20.930502] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11209 20:19:15.384178 <6>[ 20.931067] CPU1 is up
11210 20:19:15.391271 <6>[ 20.931211] Detected VIPT I-cache on CPU2
11211 20:19:15.397204 <6>[ 20.931267] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11212 20:19:15.403989 <6>[ 20.931307] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11213 20:19:15.407055 <6>[ 20.931776] CPU2 is up
11214 20:19:15.410493 <6>[ 20.931915] Detected VIPT I-cache on CPU3
11215 20:19:15.417353 <6>[ 20.931972] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11216 20:19:15.424187 <6>[ 20.932011] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11217 20:19:15.427125 <6>[ 20.932478] CPU3 is up
11218 20:19:15.434115 <6>[ 20.932599] CPU features: detected: Hardware dirty bit management
11219 20:19:15.437185 <6>[ 20.932621] Detected PIPT I-cache on CPU4
11220 20:19:15.443900 <6>[ 20.932652] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11221 20:19:15.450569 <6>[ 20.932675] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11222 20:19:15.454289 <6>[ 20.933033] CPU4 is up
11223 20:19:15.460676 <6>[ 20.933169] Detected PIPT I-cache on CPU5
11224 20:19:15.467325 <6>[ 20.933203] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11225 20:19:15.473832 <6>[ 20.933226] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11226 20:19:15.477005 <6>[ 20.933583] CPU5 is up
11227 20:19:15.480365 <6>[ 20.933732] Detected PIPT I-cache on CPU6
11228 20:19:15.487016 <6>[ 20.933767] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11229 20:19:15.493942 <6>[ 20.933789] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11230 20:19:15.497488 <6>[ 20.934130] CPU6 is up
11231 20:19:15.500656 <6>[ 20.934268] Detected PIPT I-cache on CPU7
11232 20:19:15.511434 <6>[ 20.934303] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11233 20:19:15.518121 <6>[ 20.934326] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11234 20:19:15.518208 <6>[ 20.934684] CPU7 is up
11235 20:19:15.528152 <4>[ 21.076511] typec port0-partner: PM: parent port0 should not be sleeping
11236 20:19:15.616422 <6>[ 21.609767] OOM killer enabled.
11237 20:19:15.619206 <6>[ 21.609776] Restarting tasks ... done.
11238 20:19:15.622548 <5>[ 21.611736] random: crng reseeded on system resumption
11239 20:19:15.625940 <6>[ 21.613246] PM: suspend exit
11240 20:19:15.633083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11241 20:19:15.633348 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11243 20:19:15.635980 rtcwake: assuming RTC uses UTC ...
11244 20:19:15.642751 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:16:32 2024
11245 20:19:15.656202 <6>[ 21.650994] PM: suspend entry (deep)
11246 20:19:15.659378 <6>[ 21.651044] Filesystems sync: 0.000 seconds
11247 20:19:15.663202 <6>[ 21.651711] Freezing user space processes
11248 20:19:15.669379 <6>[ 21.653562] Freezing user space processes completed (elapsed 0.001 seconds)
11249 20:19:15.672421 <6>[ 21.653572] OOM killer disabled.
11250 20:19:15.679250 <6>[ 21.653574] Freezing remaining freezable tasks
11251 20:19:15.686254 <6>[ 21.654853] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11252 20:19:15.692746 <6>[ 21.654861] printk: Suspending console(s) (use no_console_suspend to debug)
11253 20:19:21.290239 <6>[ 21.838270] Disabling non-boot CPUs ...
11254 20:19:21.293500 <6>[ 21.840019] psci: CPU1 killed (polled 0 ms)
11255 20:19:21.296640 <6>[ 21.841483] psci: CPU2 killed (polled 4 ms)
11256 20:19:21.303236 <6>[ 21.843133] psci: CPU3 killed (polled 0 ms)
11257 20:19:21.306849 <6>[ 21.843627] psci: CPU4 killed (polled 0 ms)
11258 20:19:21.310068 <6>[ 21.845111] psci: CPU5 killed (polled 0 ms)
11259 20:19:21.316821 <6>[ 21.845647] psci: CPU6 killed (polled 0 ms)
11260 20:19:21.319766 <6>[ 21.846207] psci: CPU7 killed (polled 0 ms)
11261 20:19:21.323473 <6>[ 21.846555] Enabling non-boot CPUs ...
11262 20:19:21.330283 <6>[ 21.846741] Detected VIPT I-cache on CPU1
11263 20:19:21.336583 <6>[ 21.846809] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11264 20:19:21.343518 <6>[ 21.846855] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11265 20:19:21.346744 <6>[ 21.847312] CPU1 is up
11266 20:19:21.350286 <6>[ 21.847414] Detected VIPT I-cache on CPU2
11267 20:19:21.356589 <6>[ 21.847449] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11268 20:19:21.363437 <6>[ 21.847473] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11269 20:19:21.366520 <6>[ 21.847803] CPU2 is up
11270 20:19:21.370060 <6>[ 21.847898] Detected VIPT I-cache on CPU3
11271 20:19:21.376567 <6>[ 21.847934] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11272 20:19:21.383260 <6>[ 21.847959] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11273 20:19:21.386699 <6>[ 21.848283] CPU3 is up
11274 20:19:21.389671 <6>[ 21.848394] Detected PIPT I-cache on CPU4
11275 20:19:21.399397 <6>[ 21.848420] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11276 20:19:21.406573 <6>[ 21.848438] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11277 20:19:21.406718 <6>[ 21.848735] CPU4 is up
11278 20:19:21.413549 <6>[ 21.848842] Detected PIPT I-cache on CPU5
11279 20:19:21.419843 <6>[ 21.848870] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11280 20:19:21.426665 <6>[ 21.848888] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11281 20:19:21.429787 <6>[ 21.849168] CPU5 is up
11282 20:19:21.433317 <6>[ 21.849276] Detected PIPT I-cache on CPU6
11283 20:19:21.443029 <6>[ 21.849304] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11284 20:19:21.449624 <6>[ 21.849322] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11285 20:19:21.449711 <6>[ 21.849635] CPU6 is up
11286 20:19:21.456636 <6>[ 21.849744] Detected PIPT I-cache on CPU7
11287 20:19:21.463400 <6>[ 21.849772] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11288 20:19:21.470212 <6>[ 21.849790] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11289 20:19:21.473442 <6>[ 21.850100] CPU7 is up
11290 20:19:21.534219 <6>[ 22.445730] OOM killer enabled.
11291 20:19:21.537425 <6>[ 22.445739] Restarting tasks ... done.
11292 20:19:21.540612 <5>[ 22.449839] random: crng reseeded on system resumption
11293 20:19:21.543773 <6>[ 22.452981] PM: suspend exit
11294 20:19:21.550439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11295 20:19:21.550721 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11297 20:19:21.554329 rtcwake: assuming RTC uses UTC ...
11298 20:19:21.560815 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:16:38 2024
11299 20:19:21.577858 <6>[ 22.490019] PM: suspend entry (deep)
11300 20:19:21.581112 <6>[ 22.490074] Filesystems sync: 0.000 seconds
11301 20:19:21.584964 <6>[ 22.490775] Freezing user space processes
11302 20:19:21.591146 <6>[ 22.492534] Freezing user space processes completed (elapsed 0.001 seconds)
11303 20:19:21.594614 <6>[ 22.492544] OOM killer disabled.
11304 20:19:21.601523 <6>[ 22.492546] Freezing remaining freezable tasks
11305 20:19:21.608176 <6>[ 22.493512] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11306 20:19:21.614256 <6>[ 22.493521] printk: Suspending console(s) (use no_console_suspend to debug)
11307 20:19:27.278360 <6>[ 22.670816] Disabling non-boot CPUs ...
11308 20:19:27.281380 <6>[ 22.671650] psci: CPU1 killed (polled 0 ms)
11309 20:19:27.284783 <6>[ 22.673551] psci: CPU2 killed (polled 4 ms)
11310 20:19:27.291300 <6>[ 22.675361] psci: CPU3 killed (polled 0 ms)
11311 20:19:27.294570 <6>[ 22.675831] psci: CPU4 killed (polled 0 ms)
11312 20:19:27.297658 <6>[ 22.676357] psci: CPU5 killed (polled 0 ms)
11313 20:19:27.304680 <6>[ 22.676935] psci: CPU6 killed (polled 0 ms)
11314 20:19:27.307893 <6>[ 22.677570] psci: CPU7 killed (polled 0 ms)
11315 20:19:27.311103 <6>[ 22.677949] Enabling non-boot CPUs ...
11316 20:19:27.317880 <6>[ 22.678161] Detected VIPT I-cache on CPU1
11317 20:19:27.324683 <6>[ 22.678238] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11318 20:19:27.331261 <6>[ 22.678291] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11319 20:19:27.334427 <6>[ 22.678832] CPU1 is up
11320 20:19:27.337581 <6>[ 22.678950] Detected VIPT I-cache on CPU2
11321 20:19:27.344377 <6>[ 22.678995] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11322 20:19:27.350936 <6>[ 22.679027] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11323 20:19:27.354141 <6>[ 22.679436] CPU2 is up
11324 20:19:27.357612 <6>[ 22.679553] Detected VIPT I-cache on CPU3
11325 20:19:27.364552 <6>[ 22.679599] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11326 20:19:27.371316 <6>[ 22.679630] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11327 20:19:27.374404 <6>[ 22.680045] CPU3 is up
11328 20:19:27.378057 <6>[ 22.680158] Detected PIPT I-cache on CPU4
11329 20:19:27.387835 <6>[ 22.680181] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11330 20:19:27.395035 <6>[ 22.680197] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11331 20:19:27.395119 <6>[ 22.680465] CPU4 is up
11332 20:19:27.401032 <6>[ 22.680577] Detected PIPT I-cache on CPU5
11333 20:19:27.407813 <6>[ 22.680600] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11334 20:19:27.414755 <6>[ 22.680615] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11335 20:19:27.417866 <6>[ 22.680863] CPU5 is up
11336 20:19:27.420864 <6>[ 22.680974] Detected PIPT I-cache on CPU6
11337 20:19:27.428190 <6>[ 22.680997] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11338 20:19:27.434622 <6>[ 22.681012] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11339 20:19:27.437939 <6>[ 22.681271] CPU6 is up
11340 20:19:27.441538 <6>[ 22.681382] Detected PIPT I-cache on CPU7
11341 20:19:27.447653 <6>[ 22.681405] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11342 20:19:27.455025 <6>[ 22.681420] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11343 20:19:27.458116 <6>[ 22.681696] CPU7 is up
11344 20:19:27.501597 <6>[ 23.245693] OOM killer enabled.
11345 20:19:27.505274 <6>[ 23.245702] Restarting tasks ... done.
11346 20:19:27.508318 <5>[ 23.247448] random: crng reseeded on system resumption
11347 20:19:27.511565 <6>[ 23.248234] PM: suspend exit
11348 20:19:27.518319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11349 20:19:27.518581 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11351 20:19:27.522082 rtcwake: assuming RTC uses UTC ...
11352 20:19:27.528272 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:16:44 2024
11353 20:19:27.541518 <6>[ 23.286469] PM: suspend entry (deep)
11354 20:19:27.545147 <6>[ 23.286497] Filesystems sync: 0.000 seconds
11355 20:19:27.548639 <6>[ 23.286798] Freezing user space processes
11356 20:19:27.555293 <6>[ 23.288153] Freezing user space processes completed (elapsed 0.001 seconds)
11357 20:19:27.558336 <6>[ 23.288157] OOM killer disabled.
11358 20:19:27.564912 <6>[ 23.288159] Freezing remaining freezable tasks
11359 20:19:27.571877 <6>[ 23.289474] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11360 20:19:27.578115 <6>[ 23.289481] printk: Suspending console(s) (use no_console_suspend to debug)
11361 20:19:33.288276 <6>[ 23.467963] Disabling non-boot CPUs ...
11362 20:19:33.291553 <6>[ 23.468958] psci: CPU1 killed (polled 0 ms)
11363 20:19:33.295200 <6>[ 23.470996] psci: CPU2 killed (polled 0 ms)
11364 20:19:33.301679 <6>[ 23.472022] psci: CPU3 killed (polled 0 ms)
11365 20:19:33.304794 <6>[ 23.472598] psci: CPU4 killed (polled 0 ms)
11366 20:19:33.308608 <6>[ 23.473086] psci: CPU5 killed (polled 0 ms)
11367 20:19:33.314739 <6>[ 23.473787] psci: CPU6 killed (polled 0 ms)
11368 20:19:33.318486 <6>[ 23.474406] psci: CPU7 killed (polled 0 ms)
11369 20:19:33.321644 <6>[ 23.474720] Enabling non-boot CPUs ...
11370 20:19:33.325233 <6>[ 23.474950] Detected VIPT I-cache on CPU1
11371 20:19:33.335066 <6>[ 23.475033] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11372 20:19:33.341750 <6>[ 23.475091] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11373 20:19:33.345319 <6>[ 23.475709] CPU1 is up
11374 20:19:33.348720 <6>[ 23.475847] Detected VIPT I-cache on CPU2
11375 20:19:33.355055 <6>[ 23.475901] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11376 20:19:33.361546 <6>[ 23.475938] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11377 20:19:33.365081 <6>[ 23.476434] CPU2 is up
11378 20:19:33.368137 <6>[ 23.476567] Detected VIPT I-cache on CPU3
11379 20:19:33.375005 <6>[ 23.476622] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11380 20:19:33.381694 <6>[ 23.476658] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11381 20:19:33.385368 <6>[ 23.477160] CPU3 is up
11382 20:19:33.388169 <6>[ 23.477282] Detected PIPT I-cache on CPU4
11383 20:19:33.398461 <6>[ 23.477305] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11384 20:19:33.405406 <6>[ 23.477319] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11385 20:19:33.405490 <6>[ 23.477623] CPU4 is up
11386 20:19:33.412279 <6>[ 23.477745] Detected PIPT I-cache on CPU5
11387 20:19:33.419108 <6>[ 23.477767] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11388 20:19:33.425874 <6>[ 23.477782] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11389 20:19:33.429042 <6>[ 23.478021] CPU5 is up
11390 20:19:33.432186 <6>[ 23.478148] Detected PIPT I-cache on CPU6
11391 20:19:33.438802 <6>[ 23.478171] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11392 20:19:33.445560 <6>[ 23.478185] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11393 20:19:33.448767 <6>[ 23.478431] CPU6 is up
11394 20:19:33.451858 <6>[ 23.478550] Detected PIPT I-cache on CPU7
11395 20:19:33.462328 <6>[ 23.478573] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11396 20:19:33.468723 <6>[ 23.478587] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11397 20:19:33.468805 <6>[ 23.478847] CPU7 is up
11398 20:19:33.520177 <6>[ 24.061640] OOM killer enabled.
11399 20:19:33.523666 <6>[ 24.061650] Restarting tasks ... done.
11400 20:19:33.526993 <5>[ 24.063928] random: crng reseeded on system resumption
11401 20:19:33.530006 <6>[ 24.065018] PM: suspend exit
11402 20:19:33.536876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11403 20:19:33.537140 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11405 20:19:33.539989 rtcwake: assuming RTC uses UTC ...
11406 20:19:33.546538 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:16:50 2024
11407 20:19:33.560055 <6>[ 24.103236] PM: suspend entry (deep)
11408 20:19:33.563634 <6>[ 24.103263] Filesystems sync: 0.000 seconds
11409 20:19:33.566858 <6>[ 24.103562] Freezing user space processes
11410 20:19:33.573574 <6>[ 24.105018] Freezing user space processes completed (elapsed 0.001 seconds)
11411 20:19:33.579856 <6>[ 24.105026] OOM killer disabled.
11412 20:19:33.583593 <6>[ 24.105027] Freezing remaining freezable tasks
11413 20:19:33.590223 <6>[ 24.106209] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11414 20:19:33.596482 <6>[ 24.106213] printk: Suspending console(s) (use no_console_suspend to debug)
11415 20:19:39.293970 <6>[ 24.283905] Disabling non-boot CPUs ...
11416 20:19:39.297260 <6>[ 24.285371] psci: CPU1 killed (polled 4 ms)
11417 20:19:39.300440 <6>[ 24.287471] psci: CPU2 killed (polled 0 ms)
11418 20:19:39.307169 <6>[ 24.289368] psci: CPU3 killed (polled 4 ms)
11419 20:19:39.310493 <6>[ 24.289935] psci: CPU4 killed (polled 0 ms)
11420 20:19:39.313615 <6>[ 24.290563] psci: CPU5 killed (polled 0 ms)
11421 20:19:39.320505 <6>[ 24.291280] psci: CPU6 killed (polled 0 ms)
11422 20:19:39.323975 <6>[ 24.291946] psci: CPU7 killed (polled 0 ms)
11423 20:19:39.326998 <6>[ 24.292264] Enabling non-boot CPUs ...
11424 20:19:39.333761 <6>[ 24.292502] Detected VIPT I-cache on CPU1
11425 20:19:39.340523 <6>[ 24.292588] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11426 20:19:39.347223 <6>[ 24.292649] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11427 20:19:39.350280 <6>[ 24.293277] CPU1 is up
11428 20:19:39.354006 <6>[ 24.293513] Detected VIPT I-cache on CPU2
11429 20:19:39.360580 <6>[ 24.293570] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11430 20:19:39.366993 <6>[ 24.293609] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11431 20:19:39.370622 <6>[ 24.294114] CPU2 is up
11432 20:19:39.373649 <6>[ 24.294260] Detected VIPT I-cache on CPU3
11433 20:19:39.380477 <6>[ 24.294318] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11434 20:19:39.387021 <6>[ 24.294357] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11435 20:19:39.390230 <6>[ 24.294874] CPU3 is up
11436 20:19:39.393690 <6>[ 24.295005] Detected PIPT I-cache on CPU4
11437 20:19:39.403470 <6>[ 24.295031] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11438 20:19:39.410206 <6>[ 24.295050] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11439 20:19:39.414525 <6>[ 24.295346] CPU4 is up
11440 20:19:39.421413 <6>[ 24.295473] Detected PIPT I-cache on CPU5
11441 20:19:39.427683 <6>[ 24.295501] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11442 20:19:39.434514 <6>[ 24.295519] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11443 20:19:39.438107 <6>[ 24.295801] CPU5 is up
11444 20:19:39.441207 <6>[ 24.295928] Detected PIPT I-cache on CPU6
11445 20:19:39.448024 <6>[ 24.295956] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11446 20:19:39.454116 <6>[ 24.295974] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11447 20:19:39.457821 <6>[ 24.296261] CPU6 is up
11448 20:19:39.460858 <6>[ 24.296388] Detected PIPT I-cache on CPU7
11449 20:19:39.467513 <6>[ 24.296422] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11450 20:19:39.474310 <6>[ 24.296440] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11451 20:19:39.477479 <6>[ 24.296750] CPU7 is up
11452 20:19:39.522418 <6>[ 24.885686] OOM killer enabled.
11453 20:19:39.529300 <6>[ 24.885696] Restarting tasks ... done.
11454 20:19:39.532363 <5>[ 24.888186] random: crng reseeded on system resumption
11455 20:19:39.535655 <6>[ 24.889130] PM: suspend exit
11456 20:19:39.542667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11457 20:19:39.542933 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11459 20:19:39.545891 rtcwake: assuming RTC uses UTC ...
11460 20:19:39.552188 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:16:56 2024
11461 20:19:39.565541 <6>[ 24.926839] PM: suspend entry (deep)
11462 20:19:39.569181 <6>[ 24.926889] Filesystems sync: 0.000 seconds
11463 20:19:39.572227 <6>[ 24.927552] Freezing user space processes
11464 20:19:39.578950 <6>[ 24.929430] Freezing user space processes completed (elapsed 0.001 seconds)
11465 20:19:39.582142 <6>[ 24.929440] OOM killer disabled.
11466 20:19:39.588988 <6>[ 24.929442] Freezing remaining freezable tasks
11467 20:19:39.595738 <6>[ 24.930833] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11468 20:19:39.602482 <6>[ 24.930840] printk: Suspending console(s) (use no_console_suspend to debug)
11469 20:19:45.285032 <6>[ 25.137013] Disabling non-boot CPUs ...
11470 20:19:45.288576 <6>[ 25.137640] psci: CPU1 killed (polled 0 ms)
11471 20:19:45.291918 <6>[ 25.138270] psci: CPU2 killed (polled 0 ms)
11472 20:19:45.298481 <6>[ 25.139833] psci: CPU3 killed (polled 0 ms)
11473 20:19:45.301889 <6>[ 25.141246] psci: CPU4 killed (polled 0 ms)
11474 20:19:45.304991 <6>[ 25.142671] psci: CPU5 killed (polled 0 ms)
11475 20:19:45.311571 <6>[ 25.143155] psci: CPU6 killed (polled 0 ms)
11476 20:19:45.315112 <6>[ 25.143641] psci: CPU7 killed (polled 0 ms)
11477 20:19:45.318469 <6>[ 25.143929] Enabling non-boot CPUs ...
11478 20:19:45.325066 <6>[ 25.144100] Detected VIPT I-cache on CPU1
11479 20:19:45.331678 <6>[ 25.144158] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11480 20:19:45.338531 <6>[ 25.144199] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11481 20:19:45.341564 <6>[ 25.144581] CPU1 is up
11482 20:19:45.345068 <6>[ 25.144664] Detected VIPT I-cache on CPU2
11483 20:19:45.351877 <6>[ 25.144691] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11484 20:19:45.358258 <6>[ 25.144710] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11485 20:19:45.361343 <6>[ 25.144953] CPU2 is up
11486 20:19:45.364892 <6>[ 25.145035] Detected VIPT I-cache on CPU3
11487 20:19:45.371568 <6>[ 25.145063] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11488 20:19:45.378076 <6>[ 25.145081] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11489 20:19:45.381495 <6>[ 25.145359] CPU3 is up
11490 20:19:45.384520 <6>[ 25.145454] Detected PIPT I-cache on CPU4
11491 20:19:45.395002 <6>[ 25.145476] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11492 20:19:45.401646 <6>[ 25.145490] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11493 20:19:45.404581 <6>[ 25.145737] CPU4 is up
11494 20:19:45.411491 <6>[ 25.145830] Detected PIPT I-cache on CPU5
11495 20:19:45.418138 <6>[ 25.145853] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11496 20:19:45.424609 <6>[ 25.145867] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11497 20:19:45.428076 <6>[ 25.146092] CPU5 is up
11498 20:19:45.431223 <6>[ 25.146188] Detected PIPT I-cache on CPU6
11499 20:19:45.437771 <6>[ 25.146210] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11500 20:19:45.444593 <6>[ 25.146225] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11501 20:19:45.448207 <6>[ 25.146451] CPU6 is up
11502 20:19:45.451238 <6>[ 25.146542] Detected PIPT I-cache on CPU7
11503 20:19:45.458247 <6>[ 25.146571] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11504 20:19:45.464539 <6>[ 25.146585] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11505 20:19:45.468157 <6>[ 25.146827] CPU7 is up
11506 20:19:45.509492 <6>[ 25.721557] OOM killer enabled.
11507 20:19:45.512462 <6>[ 25.721566] Restarting tasks ... done.
11508 20:19:45.516159 <5>[ 25.724195] random: crng reseeded on system resumption
11509 20:19:45.519211 <6>[ 25.724906] PM: suspend exit
11510 20:19:45.525437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11511 20:19:45.525700 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11513 20:19:45.529157 rtcwake: assuming RTC uses UTC ...
11514 20:19:45.535401 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:17:02 2024
11515 20:19:45.548908 <6>[ 25.763300] PM: suspend entry (deep)
11516 20:19:45.552259 <6>[ 25.763333] Filesystems sync: 0.000 seconds
11517 20:19:45.555676 <6>[ 25.763660] Freezing user space processes
11518 20:19:45.562027 <6>[ 25.765198] Freezing user space processes completed (elapsed 0.001 seconds)
11519 20:19:45.565561 <6>[ 25.765207] OOM killer disabled.
11520 20:19:45.572259 <6>[ 25.765209] Freezing remaining freezable tasks
11521 20:19:45.578982 <6>[ 25.766520] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11522 20:19:45.585726 <6>[ 25.766528] printk: Suspending console(s) (use no_console_suspend to debug)
11523 20:19:51.292802 <6>[ 25.951080] Disabling non-boot CPUs ...
11524 20:19:51.295855 <4>[ 25.951977] migrate_one_irq: 74 callbacks suppressed
11525 20:19:51.302715 <4>[ 25.951988] IRQ282: set affinity failed(-22).
11526 20:19:51.305744 <4>[ 25.951997] IRQ284: set affinity failed(-22).
11527 20:19:51.309253 <6>[ 25.953090] psci: CPU1 killed (polled 0 ms)
11528 20:19:51.315554 <4>[ 25.954176] IRQ282: set affinity failed(-22).
11529 20:19:51.319321 <4>[ 25.954186] IRQ284: set affinity failed(-22).
11530 20:19:51.322462 <6>[ 25.955259] psci: CPU2 killed (polled 0 ms)
11531 20:19:51.329036 <4>[ 25.956093] IRQ282: set affinity failed(-22).
11532 20:19:51.332250 <4>[ 25.956103] IRQ284: set affinity failed(-22).
11533 20:19:51.338947 <6>[ 25.957171] psci: CPU3 killed (polled 0 ms)
11534 20:19:51.342521 <4>[ 25.957757] IRQ282: set affinity failed(-22).
11535 20:19:51.345914 <4>[ 25.957761] IRQ284: set affinity failed(-22).
11536 20:19:51.352440 <6>[ 25.957799] psci: CPU4 killed (polled 0 ms)
11537 20:19:51.356060 <4>[ 25.958273] IRQ282: set affinity failed(-22).
11538 20:19:51.359235 <4>[ 25.958279] IRQ284: set affinity failed(-22).
11539 20:19:51.365863 <6>[ 25.958320] psci: CPU5 killed (polled 0 ms)
11540 20:19:51.369341 <6>[ 25.958868] psci: CPU6 killed (polled 0 ms)
11541 20:19:51.372224 <6>[ 25.959507] psci: CPU7 killed (polled 0 ms)
11542 20:19:51.378905 <6>[ 25.959907] Enabling non-boot CPUs ...
11543 20:19:51.382732 <6>[ 25.960136] Detected VIPT I-cache on CPU1
11544 20:19:51.389276 <6>[ 25.960222] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11545 20:19:51.395667 <6>[ 25.960281] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11546 20:19:51.399194 <6>[ 25.960910] CPU1 is up
11547 20:19:51.403202 <6>[ 25.961046] Detected VIPT I-cache on CPU2
11548 20:19:51.409468 <6>[ 25.961100] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11549 20:19:51.415963 <6>[ 25.961136] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11550 20:19:51.419159 <6>[ 25.961659] CPU2 is up
11551 20:19:51.422810 <6>[ 25.961796] Detected VIPT I-cache on CPU3
11552 20:19:51.432686 <6>[ 25.961851] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11553 20:19:51.439404 <6>[ 25.961887] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11554 20:19:51.439486 <6>[ 25.962386] CPU3 is up
11555 20:19:51.445864 <6>[ 25.962509] Detected PIPT I-cache on CPU4
11556 20:19:51.452225 <6>[ 25.962530] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11557 20:19:51.458929 <6>[ 25.962544] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11558 20:19:51.462698 <6>[ 25.962794] CPU4 is up
11559 20:19:51.465895 <6>[ 25.962911] Detected PIPT I-cache on CPU5
11560 20:19:51.472532 <6>[ 25.962932] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11561 20:19:51.479181 <6>[ 25.962946] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11562 20:19:51.482390 <6>[ 25.963176] CPU5 is up
11563 20:19:51.486097 <6>[ 25.963292] Detected PIPT I-cache on CPU6
11564 20:19:51.495607 <6>[ 25.963313] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11565 20:19:51.502060 <6>[ 25.963326] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11566 20:19:51.502143 <6>[ 25.963556] CPU6 is up
11567 20:19:51.508709 <6>[ 25.963673] Detected PIPT I-cache on CPU7
11568 20:19:51.515498 <6>[ 25.963694] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11569 20:19:51.522203 <6>[ 25.963707] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11570 20:19:51.525313 <6>[ 25.963954] CPU7 is up
11571 20:19:51.532362 <6>[ 26.562588] OOM killer enabled.
11572 20:19:51.535495 <6>[ 26.562597] Restarting tasks ... done.
11573 20:19:51.542635 <5>[ 26.565620] random: crng reseeded on system resumption
11574 20:19:51.542720 <6>[ 26.568724] PM: suspend exit
11575 20:19:51.548661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11576 20:19:51.548925 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11578 20:19:51.552273 rtcwake: assuming RTC uses UTC ...
11579 20:19:51.558742 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:17:08 2024
11580 20:19:51.572361 <6>[ 26.603743] PM: suspend entry (deep)
11581 20:19:51.575522 <6>[ 26.603769] Filesystems sync: 0.000 seconds
11582 20:19:51.579100 <6>[ 26.604046] Freezing user space processes
11583 20:19:51.585944 <6>[ 26.605405] Freezing user space processes completed (elapsed 0.001 seconds)
11584 20:19:51.589142 <6>[ 26.605412] OOM killer disabled.
11585 20:19:51.595939 <6>[ 26.605414] Freezing remaining freezable tasks
11586 20:19:51.602520 <6>[ 26.606677] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11587 20:19:51.608958 <6>[ 26.606683] printk: Suspending console(s) (use no_console_suspend to debug)
11588 20:19:57.288111 <6>[ 26.784089] Disabling non-boot CPUs ...
11589 20:19:57.291188 <6>[ 26.784978] psci: CPU1 killed (polled 0 ms)
11590 20:19:57.294829 <6>[ 26.787113] psci: CPU2 killed (polled 0 ms)
11591 20:19:57.300975 <6>[ 26.788988] psci: CPU3 killed (polled 0 ms)
11592 20:19:57.304422 <6>[ 26.789560] psci: CPU4 killed (polled 0 ms)
11593 20:19:57.307900 <6>[ 26.790064] psci: CPU5 killed (polled 0 ms)
11594 20:19:57.314901 <6>[ 26.790657] psci: CPU6 killed (polled 0 ms)
11595 20:19:57.318321 <6>[ 26.791218] psci: CPU7 killed (polled 0 ms)
11596 20:19:57.321145 <6>[ 26.791520] Enabling non-boot CPUs ...
11597 20:19:57.324480 <6>[ 26.791742] Detected VIPT I-cache on CPU1
11598 20:19:57.334501 <6>[ 26.791826] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11599 20:19:57.341485 <6>[ 26.791883] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11600 20:19:57.341566 <6>[ 26.792494] CPU1 is up
11601 20:19:57.347769 <6>[ 26.792623] Detected VIPT I-cache on CPU2
11602 20:19:57.354656 <6>[ 26.792676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11603 20:19:57.361507 <6>[ 26.792710] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11604 20:19:57.364673 <6>[ 26.793235] CPU2 is up
11605 20:19:57.367677 <6>[ 26.793364] Detected VIPT I-cache on CPU3
11606 20:19:57.374473 <6>[ 26.793417] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11607 20:19:57.380837 <6>[ 26.793451] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11608 20:19:57.384485 <6>[ 26.793940] CPU3 is up
11609 20:19:57.387904 <6>[ 26.794053] Detected PIPT I-cache on CPU4
11610 20:19:57.397770 <6>[ 26.794070] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11611 20:19:57.404106 <6>[ 26.794081] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11612 20:19:57.404189 <6>[ 26.794291] CPU4 is up
11613 20:19:57.410774 <6>[ 26.794405] Detected PIPT I-cache on CPU5
11614 20:19:57.417431 <6>[ 26.794421] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11615 20:19:57.424022 <6>[ 26.794432] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11616 20:19:57.427258 <6>[ 26.794614] CPU5 is up
11617 20:19:57.430749 <6>[ 26.794731] Detected PIPT I-cache on CPU6
11618 20:19:57.437954 <6>[ 26.794747] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11619 20:19:57.443922 <6>[ 26.794758] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11620 20:19:57.447746 <6>[ 26.794939] CPU6 is up
11621 20:19:57.450778 <6>[ 26.795049] Detected PIPT I-cache on CPU7
11622 20:19:57.457509 <6>[ 26.795071] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11623 20:19:57.467786 <6>[ 26.795080] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11624 20:19:57.467868 <6>[ 26.795283] CPU7 is up
11625 20:19:57.475937 <6>[ 27.338975] OOM killer enabled.
11626 20:19:57.478951 <LAVA_SIGNAL_TES<6>[ 27.338983] Restarting tasks ... done.
11627 20:19:57.479214 Received signal: <TES<6>[> 27.338983] Restarting tasks ... done.
<5
11628 20:19:57.486029 <5>[ 27.340275] random: crng reseeded on system resumption
11629 20:19:57.489088 <6>[ 27.340941] PM: suspend exit
11630 20:19:57.492765 TCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11631 20:19:57.495756 rtcwake: assuming RTC uses UTC ...
11632 20:19:57.502250 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:17:14 2024
11633 20:19:57.515899 <6>[ 27.380113] PM: suspend entry (deep)
11634 20:19:57.518882 <6>[ 27.380154] Filesystems sync: 0.000 seconds
11635 20:19:57.522539 <6>[ 27.380755] Freezing user space processes
11636 20:19:57.529562 <6>[ 27.382511] Freezing user space processes completed (elapsed 0.001 seconds)
11637 20:19:57.532567 <6>[ 27.382519] OOM killer disabled.
11638 20:19:57.539240 <6>[ 27.382521] Freezing remaining freezable tasks
11639 20:19:57.545840 <6>[ 27.383803] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11640 20:19:57.552316 <6>[ 27.383810] printk: Suspending console(s) (use no_console_suspend to debug)
11641 20:20:03.285910 <6>[ 27.558094] Disabling non-boot CPUs ...
11642 20:20:03.289076 <6>[ 27.559807] psci: CPU1 killed (polled 0 ms)
11643 20:20:03.292166 <6>[ 27.561182] psci: CPU2 killed (polled 4 ms)
11644 20:20:03.298755 <6>[ 27.562813] psci: CPU3 killed (polled 0 ms)
11645 20:20:03.302723 <6>[ 27.563255] psci: CPU4 killed (polled 0 ms)
11646 20:20:03.305699 <6>[ 27.563688] psci: CPU5 killed (polled 0 ms)
11647 20:20:03.312187 <6>[ 27.564109] psci: CPU6 killed (polled 0 ms)
11648 20:20:03.315456 <6>[ 27.564615] psci: CPU7 killed (polled 0 ms)
11649 20:20:03.319136 <6>[ 27.564969] Enabling non-boot CPUs ...
11650 20:20:03.322212 <6>[ 27.565159] Detected VIPT I-cache on CPU1
11651 20:20:03.332562 <6>[ 27.565225] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11652 20:20:03.339238 <6>[ 27.565270] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11653 20:20:03.339321 <6>[ 27.565731] CPU1 is up
11654 20:20:03.346038 <6>[ 27.565831] Detected VIPT I-cache on CPU2
11655 20:20:03.352581 <6>[ 27.565868] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11656 20:20:03.359330 <6>[ 27.565892] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11657 20:20:03.362669 <6>[ 27.566229] CPU2 is up
11658 20:20:03.365781 <6>[ 27.566327] Detected VIPT I-cache on CPU3
11659 20:20:03.372264 <6>[ 27.566364] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11660 20:20:03.379058 <6>[ 27.566389] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11661 20:20:03.382793 <6>[ 27.566731] CPU3 is up
11662 20:20:03.385670 <6>[ 27.566830] Detected PIPT I-cache on CPU4
11663 20:20:03.392532 <6>[ 27.566847] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11664 20:20:03.402051 <6>[ 27.566857] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11665 20:20:03.402134 <6>[ 27.567065] CPU4 is up
11666 20:20:03.409057 <6>[ 27.567159] Detected PIPT I-cache on CPU5
11667 20:20:03.415517 <6>[ 27.567176] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11668 20:20:03.422141 <6>[ 27.567187] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11669 20:20:03.425328 <6>[ 27.567362] CPU5 is up
11670 20:20:03.429040 <6>[ 27.567456] Detected PIPT I-cache on CPU6
11671 20:20:03.438975 <6>[ 27.567473] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11672 20:20:03.445825 <6>[ 27.567483] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11673 20:20:03.445909 <6>[ 27.567662] CPU6 is up
11674 20:20:03.452469 <6>[ 27.567757] Detected PIPT I-cache on CPU7
11675 20:20:03.459245 <6>[ 27.567779] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11676 20:20:03.465672 <6>[ 27.567790] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11677 20:20:03.468901 <6>[ 27.567987] CPU7 is up
11678 20:20:03.529242 <6>[ 28.165445] OOM killer enabled.
11679 20:20:03.532904 <6>[ 28.165455] Restarting tasks ... done.
11680 20:20:03.539606 <LAVA_SIGNAL_TES<5>[ 28.168012] random: crng reseeded on system resumption
11681 20:20:03.539872 Received signal: <TES<5>[> 28.168012] random: crng reseeded on system resumption
<6
11682 20:20:03.542887 <6>[ 28.168755] PM: suspend exit
11683 20:20:03.546060 TCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11684 20:20:03.549156 rtcwake: assuming RTC uses UTC ...
11685 20:20:03.555861 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 20:17:20 2024
11686 20:20:03.569418 <6>[ 28.206829] PM: suspend entry (deep)
11687 20:20:03.572468 <6>[ 28.206859] Filesystems sync: 0.000 seconds
11688 20:20:03.576060 <6>[ 28.207166] Freezing user space processes
11689 20:20:03.582757 <6>[ 28.208677] Freezing user space processes completed (elapsed 0.001 seconds)
11690 20:20:03.585906 <6>[ 28.208685] OOM killer disabled.
11691 20:20:03.592536 <6>[ 28.208686] Freezing remaining freezable tasks
11692 20:20:03.599434 <6>[ 28.209862] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11693 20:20:03.605690 <6>[ 28.209866] printk: Suspending console(s) (use no_console_suspend to debug)
11694 20:20:09.285061 <6>[ 28.387945] Disabling non-boot CPUs ...
11695 20:20:09.288031 <6>[ 28.389945] psci: CPU1 killed (polled 4 ms)
11696 20:20:09.291556 <6>[ 28.392104] psci: CPU2 killed (polled 0 ms)
11697 20:20:09.298193 <6>[ 28.394044] psci: CPU3 killed (polled 4 ms)
11698 20:20:09.301675 <6>[ 28.394571] psci: CPU4 killed (polled 0 ms)
11699 20:20:09.305002 <6>[ 28.395088] psci: CPU5 killed (polled 0 ms)
11700 20:20:09.311643 <6>[ 28.395780] psci: CPU6 killed (polled 0 ms)
11701 20:20:09.314699 <6>[ 28.396410] psci: CPU7 killed (polled 0 ms)
11702 20:20:09.318278 <6>[ 28.396736] Enabling non-boot CPUs ...
11703 20:20:09.324721 <6>[ 28.396968] Detected VIPT I-cache on CPU1
11704 20:20:09.331826 <6>[ 28.397054] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11705 20:20:09.338337 <6>[ 28.397112] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11706 20:20:09.341926 <6>[ 28.397756] CPU1 is up
11707 20:20:09.345057 <6>[ 28.397897] Detected VIPT I-cache on CPU2
11708 20:20:09.351629 <6>[ 28.397952] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11709 20:20:09.358384 <6>[ 28.397988] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11710 20:20:09.361525 <6>[ 28.398499] CPU2 is up
11711 20:20:09.365016 <6>[ 28.398635] Detected VIPT I-cache on CPU3
11712 20:20:09.371656 <6>[ 28.398691] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11713 20:20:09.378283 <6>[ 28.398727] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11714 20:20:09.381833 <6>[ 28.399234] CPU3 is up
11715 20:20:09.384886 <6>[ 28.399358] Detected PIPT I-cache on CPU4
11716 20:20:09.394890 <6>[ 28.399381] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11717 20:20:09.401281 <6>[ 28.399397] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11718 20:20:09.401362 <6>[ 28.399671] CPU4 is up
11719 20:20:09.408763 <6>[ 28.399794] Detected PIPT I-cache on CPU5
11720 20:20:09.415791 <6>[ 28.399818] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11721 20:20:09.422166 <6>[ 28.399833] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11722 20:20:09.425732 <6>[ 28.400083] CPU5 is up
11723 20:20:09.428824 <6>[ 28.400204] Detected PIPT I-cache on CPU6
11724 20:20:09.435784 <6>[ 28.400228] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11725 20:20:09.442463 <6>[ 28.400243] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11726 20:20:09.445667 <6>[ 28.400490] CPU6 is up
11727 20:20:09.448891 <6>[ 28.400611] Detected PIPT I-cache on CPU7
11728 20:20:09.459136 <6>[ 28.400641] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11729 20:20:09.465910 <6>[ 28.400656] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11730 20:20:09.465992 <6>[ 28.400935] CPU7 is up
11731 20:20:09.517092 <6>[ 28.985420] OOM killer enabled.
11732 20:20:09.520104 <6>[ 28.985429] Restarting tasks ... done.
11733 20:20:09.526981 <5>[ 28.987486] random: crng reseeded on system resumption
11734 20:20:09.527063 <6>[ 28.996664] PM: suspend exit
11735 20:20:09.533236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11736 20:20:09.533317 + set +x
11737 20:20:09.533565 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11739 20:20:09.539976 <LAVA_SIGNAL_ENDRUN 0_sleep 12928123_1.5.2.3.1>
11740 20:20:09.540057 <LAVA_TEST_RUNNER EXIT>
11741 20:20:09.540318 Received signal: <ENDRUN> 0_sleep 12928123_1.5.2.3.1
11742 20:20:09.540414 Ending use of test pattern.
11743 20:20:09.540475 Ending test lava.0_sleep (12928123_1.5.2.3.1), duration 59.88
11745 20:20:09.540690 ok: lava_test_shell seems to have completed
11746 20:20:09.540815 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
11747 20:20:09.540904 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11748 20:20:09.540984 end: 3 lava-test-retry (duration 00:01:00) [common]
11749 20:20:09.541070 start: 4 finalize (timeout 00:06:27) [common]
11750 20:20:09.541154 start: 4.1 power-off (timeout 00:00:30) [common]
11751 20:20:09.541302 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11752 20:20:09.620096 >> Command sent successfully.
11753 20:20:09.623518 Returned 0 in 0 seconds
11754 20:20:09.723902 end: 4.1 power-off (duration 00:00:00) [common]
11756 20:20:09.724209 start: 4.2 read-feedback (timeout 00:06:27) [common]
11757 20:20:09.724503 Listened to connection for namespace 'common' for up to 1s
11758 20:20:10.725457 Finalising connection for namespace 'common'
11759 20:20:10.725639 Disconnecting from shell: Finalise
11760 20:20:10.725716 / #
11761 20:20:10.826040 end: 4.2 read-feedback (duration 00:00:01) [common]
11762 20:20:10.826192 end: 4 finalize (duration 00:00:01) [common]
11763 20:20:10.826306 Cleaning after the job
11764 20:20:10.826404 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/ramdisk
11765 20:20:10.840180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/kernel
11766 20:20:10.864901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/dtb
11767 20:20:10.865119 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928123/tftp-deploy-6815w_fp/modules
11768 20:20:10.872682 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928123
11769 20:20:11.047072 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928123
11770 20:20:11.047248 Job finished correctly